aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-omap2/clock34xx_data.c
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-omap2/clock34xx_data.c')
-rw-r--r--arch/arm/mach-omap2/clock34xx_data.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock34xx_data.c
index 8bdcc9cc7f9..c6031d74d6f 100644
--- a/arch/arm/mach-omap2/clock34xx_data.c
+++ b/arch/arm/mach-omap2/clock34xx_data.c
@@ -776,6 +776,8 @@ static struct clk dpll4_m5_ck = {
776 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, 776 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
777 .clksel = div16_dpll4_clksel, 777 .clksel = div16_dpll4_clksel,
778 .clkdm_name = "dpll4_clkdm", 778 .clkdm_name = "dpll4_clkdm",
779 .set_rate = &omap2_clksel_set_rate,
780 .round_rate = &omap2_clksel_round_rate,
779 .recalc = &omap2_clksel_recalc, 781 .recalc = &omap2_clksel_recalc,
780}; 782};
781 783
@@ -1500,6 +1502,7 @@ static struct clk uart2_fck = {
1500 .parent = &core_48m_fck, 1502 .parent = &core_48m_fck,
1501 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1503 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1502 .enable_bit = OMAP3430_EN_UART2_SHIFT, 1504 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1505 .clkdm_name = "core_l4_clkdm",
1503 .recalc = &followparent_recalc, 1506 .recalc = &followparent_recalc,
1504}; 1507};
1505 1508
@@ -1509,6 +1512,7 @@ static struct clk uart1_fck = {
1509 .parent = &core_48m_fck, 1512 .parent = &core_48m_fck,
1510 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1513 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1511 .enable_bit = OMAP3430_EN_UART1_SHIFT, 1514 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1515 .clkdm_name = "core_l4_clkdm",
1512 .recalc = &followparent_recalc, 1516 .recalc = &followparent_recalc,
1513}; 1517};
1514 1518
@@ -2745,7 +2749,7 @@ static struct clk mcbsp4_ick = {
2745}; 2749};
2746 2750
2747static const struct clksel mcbsp_234_clksel[] = { 2751static const struct clksel mcbsp_234_clksel[] = {
2748 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates }, 2752 { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2749 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, 2753 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2750 { .parent = NULL } 2754 { .parent = NULL }
2751}; 2755};