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-rw-r--r--arch/arm/mach-omap2/clock34xx.c582
1 files changed, 526 insertions, 56 deletions
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 31bb7010bd4..0a14dca31e3 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -30,15 +30,251 @@
30#include <mach/clock.h> 30#include <mach/clock.h>
31#include <mach/sram.h> 31#include <mach/sram.h>
32#include <asm/div64.h> 32#include <asm/div64.h>
33#include <asm/clkdev.h>
33 34
34#include "memory.h" 35#include <mach/sdrc.h>
35#include "clock.h" 36#include "clock.h"
36#include "clock34xx.h"
37#include "prm.h" 37#include "prm.h"
38#include "prm-regbits-34xx.h" 38#include "prm-regbits-34xx.h"
39#include "cm.h" 39#include "cm.h"
40#include "cm-regbits-34xx.h" 40#include "cm-regbits-34xx.h"
41 41
42static const struct clkops clkops_noncore_dpll_ops;
43
44#include "clock34xx.h"
45
46struct omap_clk {
47 u32 cpu;
48 struct clk_lookup lk;
49};
50
51#define CLK(dev, con, ck, cp) \
52 { \
53 .cpu = cp, \
54 .lk = { \
55 .dev_id = dev, \
56 .con_id = con, \
57 .clk = ck, \
58 }, \
59 }
60
61#define CK_343X (1 << 0)
62#define CK_3430ES1 (1 << 1)
63#define CK_3430ES2 (1 << 2)
64
65static struct omap_clk omap34xx_clks[] = {
66 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X),
67 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X),
68 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X),
69 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2),
70 CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X),
71 CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X),
72 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_343X),
73 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_343X),
74 CLK(NULL, "sys_ck", &sys_ck, CK_343X),
75 CLK(NULL, "sys_altclk", &sys_altclk, CK_343X),
76 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_343X),
77 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_343X),
78 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_343X),
79 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_343X),
80 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X),
81 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X),
82 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X),
83 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_343X),
84 CLK(NULL, "core_ck", &core_ck, CK_343X),
85 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_343X),
86 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_343X),
87 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X),
88 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_343X),
89 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X),
90 CLK(NULL, "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X),
91 CLK(NULL, "dpll4_ck", &dpll4_ck, CK_343X),
92 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_343X),
93 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X),
94 CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_343X),
95 CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_343X),
96 CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_343X),
97 CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_343X),
98 CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_343X),
99 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_343X),
100 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X),
101 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_343X),
102 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X),
103 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_343X),
104 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X),
105 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_343X),
106 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X),
107 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_343X),
108 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X),
109 CLK(NULL, "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X),
110 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2),
111 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2),
112 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_343X),
113 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_343X),
114 CLK(NULL, "corex2_fck", &corex2_fck, CK_343X),
115 CLK(NULL, "dpll1_fck", &dpll1_fck, CK_343X),
116 CLK(NULL, "mpu_ck", &mpu_ck, CK_343X),
117 CLK(NULL, "arm_fck", &arm_fck, CK_343X),
118 CLK(NULL, "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X),
119 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X),
120 CLK(NULL, "iva2_ck", &iva2_ck, CK_343X),
121 CLK(NULL, "l3_ick", &l3_ick, CK_343X),
122 CLK(NULL, "l4_ick", &l4_ick, CK_343X),
123 CLK(NULL, "rm_ick", &rm_ick, CK_343X),
124 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1),
125 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1),
126 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
127 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
128 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
129 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2),
130 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2),
131 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
132 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_343X),
133 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_343X),
134 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2),
135 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2),
136 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2),
137 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_343X),
138 CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2),
139 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_343X),
140 CLK(NULL, "mspro_fck", &mspro_fck, CK_343X),
141 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_343X),
142 CLK("i2c_omap.3", "fck", &i2c3_fck, CK_343X),
143 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_343X),
144 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_343X),
145 CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_343X),
146 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_343X),
147 CLK(NULL, "core_48m_fck", &core_48m_fck, CK_343X),
148 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_343X),
149 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_343X),
150 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_343X),
151 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_343X),
152 CLK(NULL, "uart2_fck", &uart2_fck, CK_343X),
153 CLK(NULL, "uart1_fck", &uart1_fck, CK_343X),
154 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
155 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X),
156 CLK("omap_hdq.0", "fck", &hdq_fck, CK_343X),
157 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck, CK_343X),
158 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck, CK_343X),
159 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X),
160 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick, CK_343X),
161 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X),
162 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X),
163 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X),
164 CLK(NULL, "pka_ick", &pka_ick, CK_343X),
165 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_343X),
166 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2),
167 CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2),
168 CLK(NULL, "icr_ick", &icr_ick, CK_343X),
169 CLK(NULL, "aes2_ick", &aes2_ick, CK_343X),
170 CLK(NULL, "sha12_ick", &sha12_ick, CK_343X),
171 CLK(NULL, "des2_ick", &des2_ick, CK_343X),
172 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_343X),
173 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_343X),
174 CLK(NULL, "mspro_ick", &mspro_ick, CK_343X),
175 CLK("omap_hdq.0", "ick", &hdq_ick, CK_343X),
176 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_343X),
177 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_343X),
178 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_343X),
179 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_343X),
180 CLK("i2c_omap.3", "ick", &i2c3_ick, CK_343X),
181 CLK("i2c_omap.2", "ick", &i2c2_ick, CK_343X),
182 CLK("i2c_omap.1", "ick", &i2c1_ick, CK_343X),
183 CLK(NULL, "uart2_ick", &uart2_ick, CK_343X),
184 CLK(NULL, "uart1_ick", &uart1_ick, CK_343X),
185 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_343X),
186 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_343X),
187 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_343X),
188 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_343X),
189 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
190 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X),
191 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X),
192 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X),
193 CLK(NULL, "ssi_ick", &ssi_ick, CK_343X),
194 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
195 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X),
196 CLK(NULL, "aes1_ick", &aes1_ick, CK_343X),
197 CLK("omap_rng", "ick", &rng_ick, CK_343X),
198 CLK(NULL, "sha11_ick", &sha11_ick, CK_343X),
199 CLK(NULL, "des1_ick", &des1_ick, CK_343X),
200 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck, CK_343X),
201 CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_343X),
202 CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_343X),
203 CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_343X),
204 CLK(NULL, "dss_ick", &dss_ick, CK_343X),
205 CLK(NULL, "cam_mclk", &cam_mclk, CK_343X),
206 CLK(NULL, "cam_ick", &cam_ick, CK_343X),
207 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X),
208 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2),
209 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2),
210 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2),
211 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2),
212 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_343X),
213 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_343X),
214 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_343X),
215 CLK("omap_wdt", "fck", &wdt2_fck, CK_343X),
216 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X),
217 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2),
218 CLK("omap_wdt", "ick", &wdt2_ick, CK_343X),
219 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_343X),
220 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_343X),
221 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_343X),
222 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_343X),
223 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_343X),
224 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_343X),
225 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_343X),
226 CLK(NULL, "uart3_fck", &uart3_fck, CK_343X),
227 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_343X),
228 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_343X),
229 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_343X),
230 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_343X),
231 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_343X),
232 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_343X),
233 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_343X),
234 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_343X),
235 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X),
236 CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_343X),
237 CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_343X),
238 CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_343X),
239 CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_343X),
240 CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_343X),
241 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_343X),
242 CLK(NULL, "per_l4_ick", &per_l4_ick, CK_343X),
243 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_343X),
244 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_343X),
245 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_343X),
246 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_343X),
247 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_343X),
248 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_343X),
249 CLK(NULL, "uart3_ick", &uart3_ick, CK_343X),
250 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_343X),
251 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_343X),
252 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_343X),
253 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_343X),
254 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_343X),
255 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_343X),
256 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_343X),
257 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_343X),
258 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_343X),
259 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_343X),
260 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_343X),
261 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_343X),
262 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_343X),
263 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_343X),
264 CLK(NULL, "emu_src_ck", &emu_src_ck, CK_343X),
265 CLK(NULL, "pclk_fck", &pclk_fck, CK_343X),
266 CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_343X),
267 CLK(NULL, "atclk_fck", &atclk_fck, CK_343X),
268 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_343X),
269 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_343X),
270 CLK(NULL, "sr1_fck", &sr1_fck, CK_343X),
271 CLK(NULL, "sr2_fck", &sr2_fck, CK_343X),
272 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X),
273 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_343X),
274 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_343X),
275 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_343X),
276};
277
42/* CM_AUTOIDLE_PLL*.AUTO_* bit values */ 278/* CM_AUTOIDLE_PLL*.AUTO_* bit values */
43#define DPLL_AUTOIDLE_DISABLE 0x0 279#define DPLL_AUTOIDLE_DISABLE 0x0
44#define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1 280#define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
@@ -51,11 +287,9 @@
51 * 287 *
52 * Recalculate and propagate the DPLL rate. 288 * Recalculate and propagate the DPLL rate.
53 */ 289 */
54static void omap3_dpll_recalc(struct clk *clk) 290static unsigned long omap3_dpll_recalc(struct clk *clk)
55{ 291{
56 clk->rate = omap2_get_dpll_rate(clk); 292 return omap2_get_dpll_rate(clk);
57
58 propagate_rate(clk);
59} 293}
60 294
61/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ 295/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
@@ -78,14 +312,12 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
78 const struct dpll_data *dd; 312 const struct dpll_data *dd;
79 int i = 0; 313 int i = 0;
80 int ret = -EINVAL; 314 int ret = -EINVAL;
81 u32 idlest_mask;
82 315
83 dd = clk->dpll_data; 316 dd = clk->dpll_data;
84 317
85 state <<= dd->idlest_bit; 318 state <<= __ffs(dd->idlest_mask);
86 idlest_mask = 1 << dd->idlest_bit;
87 319
88 while (((__raw_readl(dd->idlest_reg) & idlest_mask) != state) && 320 while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
89 i < MAX_DPLL_WAIT_TRIES) { 321 i < MAX_DPLL_WAIT_TRIES) {
90 i++; 322 i++;
91 udelay(1); 323 udelay(1);
@@ -104,6 +336,42 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
104 return ret; 336 return ret;
105} 337}
106 338
339/* From 3430 TRM ES2 4.7.6.2 */
340static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
341{
342 unsigned long fint;
343 u16 f = 0;
344
345 fint = clk->dpll_data->clk_ref->rate / (n + 1);
346
347 pr_debug("clock: fint is %lu\n", fint);
348
349 if (fint >= 750000 && fint <= 1000000)
350 f = 0x3;
351 else if (fint > 1000000 && fint <= 1250000)
352 f = 0x4;
353 else if (fint > 1250000 && fint <= 1500000)
354 f = 0x5;
355 else if (fint > 1500000 && fint <= 1750000)
356 f = 0x6;
357 else if (fint > 1750000 && fint <= 2100000)
358 f = 0x7;
359 else if (fint > 7500000 && fint <= 10000000)
360 f = 0xB;
361 else if (fint > 10000000 && fint <= 12500000)
362 f = 0xC;
363 else if (fint > 12500000 && fint <= 15000000)
364 f = 0xD;
365 else if (fint > 15000000 && fint <= 17500000)
366 f = 0xE;
367 else if (fint > 17500000 && fint <= 21000000)
368 f = 0xF;
369 else
370 pr_debug("clock: unknown freqsel setting for %d\n", n);
371
372 return f;
373}
374
107/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */ 375/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
108 376
109/* 377/*
@@ -128,25 +396,20 @@ static int _omap3_noncore_dpll_lock(struct clk *clk)
128 396
129 ai = omap3_dpll_autoidle_read(clk); 397 ai = omap3_dpll_autoidle_read(clk);
130 398
399 omap3_dpll_deny_idle(clk);
400
131 _omap3_dpll_write_clken(clk, DPLL_LOCKED); 401 _omap3_dpll_write_clken(clk, DPLL_LOCKED);
132 402
133 if (ai) { 403 r = _omap3_wait_dpll_status(clk, 1);
134 /* 404
135 * If no downstream clocks are enabled, CM_IDLEST bit 405 if (ai)
136 * may never become active, so don't wait for DPLL to lock.
137 */
138 r = 0;
139 omap3_dpll_allow_idle(clk); 406 omap3_dpll_allow_idle(clk);
140 } else {
141 r = _omap3_wait_dpll_status(clk, 1);
142 omap3_dpll_deny_idle(clk);
143 };
144 407
145 return r; 408 return r;
146} 409}
147 410
148/* 411/*
149 * omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness 412 * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
150 * @clk: pointer to a DPLL struct clk 413 * @clk: pointer to a DPLL struct clk
151 * 414 *
152 * Instructs a non-CORE DPLL to enter low-power bypass mode. In 415 * Instructs a non-CORE DPLL to enter low-power bypass mode. In
@@ -236,14 +499,25 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
236static int omap3_noncore_dpll_enable(struct clk *clk) 499static int omap3_noncore_dpll_enable(struct clk *clk)
237{ 500{
238 int r; 501 int r;
502 struct dpll_data *dd;
239 503
240 if (clk == &dpll3_ck) 504 if (clk == &dpll3_ck)
241 return -EINVAL; 505 return -EINVAL;
242 506
243 if (clk->parent->rate == clk_get_rate(clk)) 507 dd = clk->dpll_data;
508 if (!dd)
509 return -EINVAL;
510
511 if (clk->rate == dd->clk_bypass->rate) {
512 WARN_ON(clk->parent != dd->clk_bypass);
244 r = _omap3_noncore_dpll_bypass(clk); 513 r = _omap3_noncore_dpll_bypass(clk);
245 else 514 } else {
515 WARN_ON(clk->parent != dd->clk_ref);
246 r = _omap3_noncore_dpll_lock(clk); 516 r = _omap3_noncore_dpll_lock(clk);
517 }
518 /* FIXME: this is dubious - if clk->rate has changed, what about propagating? */
519 if (!r)
520 clk->rate = omap2_get_dpll_rate(clk);
247 521
248 return r; 522 return r;
249} 523}
@@ -270,6 +544,215 @@ static void omap3_noncore_dpll_disable(struct clk *clk)
270 _omap3_noncore_dpll_stop(clk); 544 _omap3_noncore_dpll_stop(clk);
271} 545}
272 546
547
548/* Non-CORE DPLL rate set code */
549
550/*
551 * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
552 * @clk: struct clk * of DPLL to set
553 * @m: DPLL multiplier to set
554 * @n: DPLL divider to set
555 * @freqsel: FREQSEL value to set
556 *
557 * Program the DPLL with the supplied M, N values, and wait for the DPLL to
558 * lock.. Returns -EINVAL upon error, or 0 upon success.
559 */
560static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
561{
562 struct dpll_data *dd = clk->dpll_data;
563 u32 v;
564
565 /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
566 _omap3_noncore_dpll_bypass(clk);
567
568 /* Set jitter correction */
569 v = __raw_readl(dd->control_reg);
570 v &= ~dd->freqsel_mask;
571 v |= freqsel << __ffs(dd->freqsel_mask);
572 __raw_writel(v, dd->control_reg);
573
574 /* Set DPLL multiplier, divider */
575 v = __raw_readl(dd->mult_div1_reg);
576 v &= ~(dd->mult_mask | dd->div1_mask);
577 v |= m << __ffs(dd->mult_mask);
578 v |= (n - 1) << __ffs(dd->div1_mask);
579 __raw_writel(v, dd->mult_div1_reg);
580
581 /* We let the clock framework set the other output dividers later */
582
583 /* REVISIT: Set ramp-up delay? */
584
585 _omap3_noncore_dpll_lock(clk);
586
587 return 0;
588}
589
590/**
591 * omap3_noncore_dpll_set_rate - set non-core DPLL rate
592 * @clk: struct clk * of DPLL to set
593 * @rate: rounded target rate
594 *
595 * Set the DPLL CLKOUT to the target rate. If the DPLL can enter
596 * low-power bypass, and the target rate is the bypass source clock
597 * rate, then configure the DPLL for bypass. Otherwise, round the
598 * target rate if it hasn't been done already, then program and lock
599 * the DPLL. Returns -EINVAL upon error, or 0 upon success.
600 */
601static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
602{
603 struct clk *new_parent = NULL;
604 u16 freqsel;
605 struct dpll_data *dd;
606 int ret;
607
608 if (!clk || !rate)
609 return -EINVAL;
610
611 dd = clk->dpll_data;
612 if (!dd)
613 return -EINVAL;
614
615 if (rate == omap2_get_dpll_rate(clk))
616 return 0;
617
618 /*
619 * Ensure both the bypass and ref clocks are enabled prior to
620 * doing anything; we need the bypass clock running to reprogram
621 * the DPLL.
622 */
623 omap2_clk_enable(dd->clk_bypass);
624 omap2_clk_enable(dd->clk_ref);
625
626 if (dd->clk_bypass->rate == rate &&
627 (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
628 pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
629
630 ret = _omap3_noncore_dpll_bypass(clk);
631 if (!ret)
632 new_parent = dd->clk_bypass;
633 } else {
634 if (dd->last_rounded_rate != rate)
635 omap2_dpll_round_rate(clk, rate);
636
637 if (dd->last_rounded_rate == 0)
638 return -EINVAL;
639
640 freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
641 if (!freqsel)
642 WARN_ON(1);
643
644 pr_debug("clock: %s: set rate: locking rate to %lu.\n",
645 clk->name, rate);
646
647 ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
648 dd->last_rounded_n, freqsel);
649 if (!ret)
650 new_parent = dd->clk_ref;
651 }
652 if (!ret) {
653 /*
654 * Switch the parent clock in the heirarchy, and make sure
655 * that the new parent's usecount is correct. Note: we
656 * enable the new parent before disabling the old to avoid
657 * any unnecessary hardware disable->enable transitions.
658 */
659 if (clk->usecount) {
660 omap2_clk_enable(new_parent);
661 omap2_clk_disable(clk->parent);
662 }
663 clk_reparent(clk, new_parent);
664 clk->rate = rate;
665 }
666 omap2_clk_disable(dd->clk_ref);
667 omap2_clk_disable(dd->clk_bypass);
668
669 return 0;
670}
671
672static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
673{
674 /*
675 * According to the 12-5 CDP code from TI, "Limitation 2.5"
676 * on 3430ES1 prevents us from changing DPLL multipliers or dividers
677 * on DPLL4.
678 */
679 if (omap_rev() == OMAP3430_REV_ES1_0) {
680 printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
681 "silicon 'Limitation 2.5' on 3430ES1.\n");
682 return -EINVAL;
683 }
684 return omap3_noncore_dpll_set_rate(clk, rate);
685}
686
687
688/*
689 * CORE DPLL (DPLL3) rate programming functions
690 *
691 * These call into SRAM code to do the actual CM writes, since the SDRAM
692 * is clocked from DPLL3.
693 */
694
695/**
696 * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
697 * @clk: struct clk * of DPLL to set
698 * @rate: rounded target rate
699 *
700 * Program the DPLL M2 divider with the rounded target rate. Returns
701 * -EINVAL upon error, or 0 upon success.
702 */
703static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
704{
705 u32 new_div = 0;
706 unsigned long validrate, sdrcrate;
707 struct omap_sdrc_params *sp;
708
709 if (!clk || !rate)
710 return -EINVAL;
711
712 if (clk != &dpll3_m2_ck)
713 return -EINVAL;
714
715 if (rate == clk->rate)
716 return 0;
717
718 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
719 if (validrate != rate)
720 return -EINVAL;
721
722 sdrcrate = sdrc_ick.rate;
723 if (rate > clk->rate)
724 sdrcrate <<= ((rate / clk->rate) - 1);
725 else
726 sdrcrate >>= ((clk->rate / rate) - 1);
727
728 sp = omap2_sdrc_get_params(sdrcrate);
729 if (!sp)
730 return -EINVAL;
731
732 pr_info("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
733 validrate);
734 pr_info("clock: SDRC timing params used: %08x %08x %08x\n",
735 sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
736
737 /* REVISIT: SRAM code doesn't support other M2 divisors yet */
738 WARN_ON(new_div != 1 && new_div != 2);
739
740 /* REVISIT: Add SDRC_MR changing to this code also */
741 omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
742 sp->actim_ctrlb, new_div);
743
744 return 0;
745}
746
747
748static const struct clkops clkops_noncore_dpll_ops = {
749 .enable = &omap3_noncore_dpll_enable,
750 .disable = &omap3_noncore_dpll_disable,
751};
752
753/* DPLL autoidle read/set code */
754
755
273/** 756/**
274 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits 757 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
275 * @clk: struct clk * of the DPLL to read 758 * @clk: struct clk * of the DPLL to read
@@ -356,9 +839,10 @@ static void omap3_dpll_deny_idle(struct clk *clk)
356 * Using parent clock DPLL data, look up DPLL state. If locked, set our 839 * Using parent clock DPLL data, look up DPLL state. If locked, set our
357 * rate to the dpll_clk * 2; otherwise, just use dpll_clk. 840 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
358 */ 841 */
359static void omap3_clkoutx2_recalc(struct clk *clk) 842static unsigned long omap3_clkoutx2_recalc(struct clk *clk)
360{ 843{
361 const struct dpll_data *dd; 844 const struct dpll_data *dd;
845 unsigned long rate;
362 u32 v; 846 u32 v;
363 struct clk *pclk; 847 struct clk *pclk;
364 848
@@ -372,17 +856,15 @@ static void omap3_clkoutx2_recalc(struct clk *clk)
372 856
373 dd = pclk->dpll_data; 857 dd = pclk->dpll_data;
374 858
375 WARN_ON(!dd->control_reg || !dd->enable_mask); 859 WARN_ON(!dd->enable_mask);
376 860
377 v = __raw_readl(dd->control_reg) & dd->enable_mask; 861 v = __raw_readl(dd->control_reg) & dd->enable_mask;
378 v >>= __ffs(dd->enable_mask); 862 v >>= __ffs(dd->enable_mask);
379 if (v != DPLL_LOCKED) 863 if (v != OMAP3XXX_EN_DPLL_LOCKED)
380 clk->rate = clk->parent->rate; 864 rate = clk->parent->rate;
381 else 865 else
382 clk->rate = clk->parent->rate * 2; 866 rate = clk->parent->rate * 2;
383 867 return rate;
384 if (clk->flags & RATE_PROPAGATES)
385 propagate_rate(clk);
386} 868}
387 869
388/* Common clock code */ 870/* Common clock code */
@@ -432,7 +914,7 @@ static int __init omap2_clk_arch_init(void)
432 914
433 /* REVISIT: not yet ready for 343x */ 915 /* REVISIT: not yet ready for 343x */
434#if 0 916#if 0
435 if (omap2_select_table_rate(&virt_prcm_set, mpurate)) 917 if (clk_set_rate(&virt_prcm_set, mpurate))
436 printk(KERN_ERR "Could not find matching MPU rate\n"); 918 printk(KERN_ERR "Could not find matching MPU rate\n");
437#endif 919#endif
438 920
@@ -450,26 +932,13 @@ arch_initcall(omap2_clk_arch_init);
450int __init omap2_clk_init(void) 932int __init omap2_clk_init(void)
451{ 933{
452 /* struct prcm_config *prcm; */ 934 /* struct prcm_config *prcm; */
453 struct clk **clkp; 935 struct omap_clk *c;
454 /* u32 clkrate; */ 936 /* u32 clkrate; */
455 u32 cpu_clkflg; 937 u32 cpu_clkflg;
456 938
457 /* REVISIT: Ultimately this will be used for multiboot */
458#if 0
459 if (cpu_is_omap242x()) {
460 cpu_mask = RATE_IN_242X;
461 cpu_clkflg = CLOCK_IN_OMAP242X;
462 clkp = onchip_24xx_clks;
463 } else if (cpu_is_omap2430()) {
464 cpu_mask = RATE_IN_243X;
465 cpu_clkflg = CLOCK_IN_OMAP243X;
466 clkp = onchip_24xx_clks;
467 }
468#endif
469 if (cpu_is_omap34xx()) { 939 if (cpu_is_omap34xx()) {
470 cpu_mask = RATE_IN_343X; 940 cpu_mask = RATE_IN_343X;
471 cpu_clkflg = CLOCK_IN_OMAP343X; 941 cpu_clkflg = CK_343X;
472 clkp = onchip_34xx_clks;
473 942
474 /* 943 /*
475 * Update this if there are further clock changes between ES2 944 * Update this if there are further clock changes between ES2
@@ -477,23 +946,24 @@ int __init omap2_clk_init(void)
477 */ 946 */
478 if (omap_rev() == OMAP3430_REV_ES1_0) { 947 if (omap_rev() == OMAP3430_REV_ES1_0) {
479 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */ 948 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
480 cpu_clkflg |= CLOCK_IN_OMAP3430ES1; 949 cpu_clkflg |= CK_3430ES1;
481 } else { 950 } else {
482 cpu_mask |= RATE_IN_3430ES2; 951 cpu_mask |= RATE_IN_3430ES2;
483 cpu_clkflg |= CLOCK_IN_OMAP3430ES2; 952 cpu_clkflg |= CK_3430ES2;
484 } 953 }
485 } 954 }
486 955
487 clk_init(&omap2_clk_functions); 956 clk_init(&omap2_clk_functions);
488 957
489 for (clkp = onchip_34xx_clks; 958 for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
490 clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks); 959 clk_init_one(c->lk.clk);
491 clkp++) { 960
492 if ((*clkp)->flags & cpu_clkflg) { 961 for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
493 clk_register(*clkp); 962 if (c->cpu & cpu_clkflg) {
494 omap2_init_clk_clkdm(*clkp); 963 clkdev_add(&c->lk);
964 clk_register(c->lk.clk);
965 omap2_init_clk_clkdm(c->lk.clk);
495 } 966 }
496 }
497 967
498 /* REVISIT: Not yet ready for OMAP3 */ 968 /* REVISIT: Not yet ready for OMAP3 */
499#if 0 969#if 0
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 01:02:07 -0500