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-rw-r--r--arch/arm/mach-l7200/include/mach/aux_reg.h28
-rw-r--r--arch/arm/mach-l7200/include/mach/debug-macro.S40
-rw-r--r--arch/arm/mach-l7200/include/mach/dma.h23
-rw-r--r--arch/arm/mach-l7200/include/mach/entry-macro.S35
-rw-r--r--arch/arm/mach-l7200/include/mach/gp_timers.h42
-rw-r--r--arch/arm/mach-l7200/include/mach/gpio.h105
-rw-r--r--arch/arm/mach-l7200/include/mach/hardware.h57
-rw-r--r--arch/arm/mach-l7200/include/mach/io.h27
-rw-r--r--arch/arm/mach-l7200/include/mach/irqs.h56
-rw-r--r--arch/arm/mach-l7200/include/mach/memory.h29
-rw-r--r--arch/arm/mach-l7200/include/mach/pmpcon.h46
-rw-r--r--arch/arm/mach-l7200/include/mach/pmu.h125
-rw-r--r--arch/arm/mach-l7200/include/mach/serial.h37
-rw-r--r--arch/arm/mach-l7200/include/mach/serial_l7200.h101
-rw-r--r--arch/arm/mach-l7200/include/mach/sib.h119
-rw-r--r--arch/arm/mach-l7200/include/mach/sys-clock.h67
-rw-r--r--arch/arm/mach-l7200/include/mach/system.h29
-rw-r--r--arch/arm/mach-l7200/include/mach/time.h73
-rw-r--r--arch/arm/mach-l7200/include/mach/timex.h20
-rw-r--r--arch/arm/mach-l7200/include/mach/uncompress.h39
-rw-r--r--arch/arm/mach-l7200/include/mach/vmalloc.h4
21 files changed, 1102 insertions, 0 deletions
diff --git a/arch/arm/mach-l7200/include/mach/aux_reg.h b/arch/arm/mach-l7200/include/mach/aux_reg.h
new file mode 100644
index 00000000000..4671558cdd5
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/aux_reg.h
@@ -0,0 +1,28 @@
1/*
2 * arch/arm/mach-l7200/include/mach/aux_reg.h
3 *
4 * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
5 *
6 * Changelog:
7 * 08-02-2000 SJH Created file
8 */
9#ifndef _ASM_ARCH_AUXREG_H
10#define _ASM_ARCH_AUXREG_H
11
12#include <mach/hardware.h>
13
14#define l7200aux_reg *((volatile unsigned int *) (AUX_BASE))
15
16/*
17 * Auxillary register values
18 */
19#define AUX_CLEAR 0x00000000
20#define AUX_DIAG_LED_ON 0x00000002
21#define AUX_RTS_UART1 0x00000004
22#define AUX_DTR_UART1 0x00000008
23#define AUX_KBD_COLUMN_12_HIGH 0x00000010
24#define AUX_KBD_COLUMN_12_OFF 0x00000020
25#define AUX_KBD_COLUMN_13_HIGH 0x00000040
26#define AUX_KBD_COLUMN_13_OFF 0x00000080
27
28#endif
diff --git a/arch/arm/mach-l7200/include/mach/debug-macro.S b/arch/arm/mach-l7200/include/mach/debug-macro.S
new file mode 100644
index 00000000000..34eed2a63e6
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/debug-macro.S
@@ -0,0 +1,40 @@
1/* arch/arm/mach-l7200/include/mach/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14 .equ io_virt, IO_BASE
15 .equ io_phys, IO_START
16
17 .macro addruart,rx
18 mrc p15, 0, \rx, c1, c0
19 tst \rx, #1 @ MMU enabled?
20 moveq \rx, #io_phys @ physical base address
21 movne \rx, #io_virt @ virtual address
22 add \rx, \rx, #0x00044000 @ UART1
23@ add \rx, \rx, #0x00045000 @ UART2
24 .endm
25
26 .macro senduart,rd,rx
27 str \rd, [\rx, #0x0] @ UARTDR
28 .endm
29
30 .macro waituart,rd,rx
311001: ldr \rd, [\rx, #0x18] @ UARTFLG
32 tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full
33 bne 1001b
34 .endm
35
36 .macro busyuart,rd,rx
371001: ldr \rd, [\rx, #0x18] @ UARTFLG
38 tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy
39 bne 1001b
40 .endm
diff --git a/arch/arm/mach-l7200/include/mach/dma.h b/arch/arm/mach-l7200/include/mach/dma.h
new file mode 100644
index 00000000000..c7e48bd4590
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/dma.h
@@ -0,0 +1,23 @@
1/*
2 * arch/arm/mach-l7200/include/mach/dma.h
3 *
4 * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
5 *
6 * Changelog:
7 * 08-29-2000 SJH Created
8 */
9#ifndef __ASM_ARCH_DMA_H
10#define __ASM_ARCH_DMA_H
11
12/* DMA is not yet implemented! It should be the same as acorn, copy over.. */
13
14/*
15 * This is the maximum DMA address that can be DMAd to.
16 * There should not be more than (0xd0000000 - 0xc0000000)
17 * bytes of RAM.
18 */
19#define MAX_DMA_ADDRESS 0xd0000000
20
21#define DMA_S0 0
22
23#endif /* _ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-l7200/include/mach/entry-macro.S b/arch/arm/mach-l7200/include/mach/entry-macro.S
new file mode 100644
index 00000000000..1726d91fc1d
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/entry-macro.S
@@ -0,0 +1,35 @@
1/*
2 * arch/arm/mach-l7200/include/mach/entry-macro.S
3 *
4 * Low-level IRQ helper macros for L7200-based platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10#include <mach/hardware.h>
11
12 .equ irq_base_addr, IO_BASE_2
13
14 .macro disable_fiq
15 .endm
16
17 .macro get_irqnr_preamble, base, tmp
18 .endm
19
20 .macro arch_ret_to_user, tmp1, tmp2
21 .endm
22
23 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
24 mov \irqstat, #irq_base_addr @ Virt addr IRQ regs
25 add \irqstat, \irqstat, #0x00001000 @ Status reg
26 ldr \irqstat, [\irqstat, #0] @ get interrupts
27 mov \irqnr, #0
281001: tst \irqstat, #1
29 addeq \irqnr, \irqnr, #1
30 moveq \irqstat, \irqstat, lsr #1
31 tsteq \irqnr, #32
32 beq 1001b
33 teq \irqnr, #32
34 .endm
35
diff --git a/arch/arm/mach-l7200/include/mach/gp_timers.h b/arch/arm/mach-l7200/include/mach/gp_timers.h
new file mode 100644
index 00000000000..2b7086a26b8
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/gp_timers.h
@@ -0,0 +1,42 @@
1/*
2 * arch/arm/mach-l7200/include/mach/gp_timers.h
3 *
4 * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
5 *
6 * Changelog:
7 * 07-28-2000 SJH Created file
8 * 08-02-2000 SJH Used structure for registers
9 */
10#ifndef _ASM_ARCH_GPTIMERS_H
11#define _ASM_ARCH_GPTIMERS_H
12
13#include <mach/hardware.h>
14
15/*
16 * Layout of L7200 general purpose timer registers
17 */
18struct GPT_Regs {
19 unsigned int TIMERLOAD;
20 unsigned int TIMERVALUE;
21 unsigned int TIMERCONTROL;
22 unsigned int TIMERCLEAR;
23};
24
25#define GPT_BASE (IO_BASE_2 + 0x3000)
26#define l7200_timer1_regs ((volatile struct GPT_Regs *) (GPT_BASE))
27#define l7200_timer2_regs ((volatile struct GPT_Regs *) (GPT_BASE + 0x20))
28
29/*
30 * General register values
31 */
32#define GPT_PRESCALE_1 0x00000000
33#define GPT_PRESCALE_16 0x00000004
34#define GPT_PRESCALE_256 0x00000008
35#define GPT_MODE_FREERUN 0x00000000
36#define GPT_MODE_PERIODIC 0x00000040
37#define GPT_ENABLE 0x00000080
38#define GPT_BZTOG 0x00000100
39#define GPT_BZMOD 0x00000200
40#define GPT_LOAD_MASK 0x0000ffff
41
42#endif
diff --git a/arch/arm/mach-l7200/include/mach/gpio.h b/arch/arm/mach-l7200/include/mach/gpio.h
new file mode 100644
index 00000000000..c7b0a5d7b8b
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/gpio.h
@@ -0,0 +1,105 @@
1/****************************************************************************/
2/*
3 * arch/arm/mach-l7200/include/mach/gpio.h
4 *
5 * Registers and helper functions for the L7200 Link-Up Systems
6 * GPIO.
7 *
8 * (C) Copyright 2000, S A McConnell (samcconn@cotw.com)
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive for
12 * more details.
13 */
14
15/****************************************************************************/
16
17#define GPIO_OFF 0x00005000 /* Offset from IO_START to the GPIO reg's. */
18
19/* IO_START and IO_BASE are defined in hardware.h */
20
21#define GPIO_START (IO_START_2 + GPIO_OFF) /* Physical addr of the GPIO reg. */
22#define GPIO_BASE (IO_BASE_2 + GPIO_OFF) /* Virtual addr of the GPIO reg. */
23
24/* Offsets from the start of the GPIO for all the registers. */
25#define PADR_OFF 0x000
26#define PADDR_OFF 0x004
27#define PASBSR_OFF 0x008
28#define PAEENR_OFF 0x00c
29#define PAESNR_OFF 0x010
30#define PAESTR_OFF 0x014
31#define PAIMR_OFF 0x018
32#define PAINT_OFF 0x01c
33
34#define PBDR_OFF 0x020
35#define PBDDR_OFF 0x024
36#define PBSBSR_OFF 0x028
37#define PBIMR_OFF 0x038
38#define PBINT_OFF 0x03c
39
40#define PCDR_OFF 0x040
41#define PCDDR_OFF 0x044
42#define PCSBSR_OFF 0x048
43#define PCIMR_OFF 0x058
44#define PCINT_OFF 0x05c
45
46#define PDDR_OFF 0x060
47#define PDDDR_OFF 0x064
48#define PDSBSR_OFF 0x068
49#define PDEENR_OFF 0x06c
50#define PDESNR_OFF 0x070
51#define PDESTR_OFF 0x074
52#define PDIMR_OFF 0x078
53#define PDINT_OFF 0x07c
54
55#define PEDR_OFF 0x080
56#define PEDDR_OFF 0x084
57#define PESBSR_OFF 0x088
58#define PEEENR_OFF 0x08c
59#define PEESNR_OFF 0x090
60#define PEESTR_OFF 0x094
61#define PEIMR_OFF 0x098
62#define PEINT_OFF 0x09c
63
64/* Define the GPIO registers for use by device drivers and the kernel. */
65#define PADR (*(volatile unsigned long *)(GPIO_BASE+PADR_OFF))
66#define PADDR (*(volatile unsigned long *)(GPIO_BASE+PADDR_OFF))
67#define PASBSR (*(volatile unsigned long *)(GPIO_BASE+PASBSR_OFF))
68#define PAEENR (*(volatile unsigned long *)(GPIO_BASE+PAEENR_OFF))
69#define PAESNR (*(volatile unsigned long *)(GPIO_BASE+PAESNR_OFF))
70#define PAESTR (*(volatile unsigned long *)(GPIO_BASE+PAESTR_OFF))
71#define PAIMR (*(volatile unsigned long *)(GPIO_BASE+PAIMR_OFF))
72#define PAINT (*(volatile unsigned long *)(GPIO_BASE+PAINT_OFF))
73
74#define PBDR (*(volatile unsigned long *)(GPIO_BASE+PBDR_OFF))
75#define PBDDR (*(volatile unsigned long *)(GPIO_BASE+PBDDR_OFF))
76#define PBSBSR (*(volatile unsigned long *)(GPIO_BASE+PBSBSR_OFF))
77#define PBIMR (*(volatile unsigned long *)(GPIO_BASE+PBIMR_OFF))
78#define PBINT (*(volatile unsigned long *)(GPIO_BASE+PBINT_OFF))
79
80#define PCDR (*(volatile unsigned long *)(GPIO_BASE+PCDR_OFF))
81#define PCDDR (*(volatile unsigned long *)(GPIO_BASE+PCDDR_OFF))
82#define PCSBSR (*(volatile unsigned long *)(GPIO_BASE+PCSBSR_OFF))
83#define PCIMR (*(volatile unsigned long *)(GPIO_BASE+PCIMR_OFF))
84#define PCINT (*(volatile unsigned long *)(GPIO_BASE+PCINT_OFF))
85
86#define PDDR (*(volatile unsigned long *)(GPIO_BASE+PDDR_OFF))
87#define PDDDR (*(volatile unsigned long *)(GPIO_BASE+PDDDR_OFF))
88#define PDSBSR (*(volatile unsigned long *)(GPIO_BASE+PDSBSR_OFF))
89#define PDEENR (*(volatile unsigned long *)(GPIO_BASE+PDEENR_OFF))
90#define PDESNR (*(volatile unsigned long *)(GPIO_BASE+PDESNR_OFF))
91#define PDESTR (*(volatile unsigned long *)(GPIO_BASE+PDESTR_OFF))
92#define PDIMR (*(volatile unsigned long *)(GPIO_BASE+PDIMR_OFF))
93#define PDINT (*(volatile unsigned long *)(GPIO_BASE+PDINT_OFF))
94
95#define PEDR (*(volatile unsigned long *)(GPIO_BASE+PEDR_OFF))
96#define PEDDR (*(volatile unsigned long *)(GPIO_BASE+PEDDR_OFF))
97#define PESBSR (*(volatile unsigned long *)(GPIO_BASE+PESBSR_OFF))
98#define PEEENR (*(volatile unsigned long *)(GPIO_BASE+PEEENR_OFF))
99#define PEESNR (*(volatile unsigned long *)(GPIO_BASE+PEESNR_OFF))
100#define PEESTR (*(volatile unsigned long *)(GPIO_BASE+PEESTR_OFF))
101#define PEIMR (*(volatile unsigned long *)(GPIO_BASE+PEIMR_OFF))
102#define PEINT (*(volatile unsigned long *)(GPIO_BASE+PEINT_OFF))
103
104#define VEE_EN 0x02
105#define BACKLIGHT_EN 0x04
diff --git a/arch/arm/mach-l7200/include/mach/hardware.h b/arch/arm/mach-l7200/include/mach/hardware.h
new file mode 100644
index 00000000000..c31909cfc25
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/hardware.h
@@ -0,0 +1,57 @@
1/*
2 * arch/arm/mach-l7200/include/mach/hardware.h
3 *
4 * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
5 * Steve Hill (sjhill@cotw.com)
6 *
7 * This file contains the hardware definitions for the
8 * LinkUp Systems L7200 SOC development board.
9 *
10 * Changelog:
11 * 02-01-2000 RS Created L7200 version, derived from rpc code
12 * 03-21-2000 SJH Cleaned up file
13 * 04-21-2000 RS Changed mapping of I/O in virtual space
14 * 04-25-2000 SJH Removed unused symbols and such
15 * 05-05-2000 SJH Complete rewrite
16 * 07-31-2000 SJH Added undocumented debug auxillary port to
17 * get at last two columns for keyboard driver
18 */
19#ifndef __ASM_ARCH_HARDWARE_H
20#define __ASM_ARCH_HARDWARE_H
21
22/* Hardware addresses of major areas.
23 * *_START is the physical address
24 * *_SIZE is the size of the region
25 * *_BASE is the virtual address
26 */
27#define RAM_START 0xf0000000
28#define RAM_SIZE 0x02000000
29#define RAM_BASE 0xc0000000
30
31#define IO_START 0x80000000 /* I/O */
32#define IO_SIZE 0x01000000
33#define IO_BASE 0xd0000000
34
35#define IO_START_2 0x90000000 /* I/O */
36#define IO_SIZE_2 0x01000000
37#define IO_BASE_2 0xd1000000
38
39#define AUX_START 0x1a000000 /* AUX PORT */
40#define AUX_SIZE 0x01000000
41#define AUX_BASE 0xd2000000
42
43#define FLASH1_START 0x00000000 /* FLASH BANK 1 */
44#define FLASH1_SIZE 0x01000000
45#define FLASH1_BASE 0xd3000000
46
47#define FLASH2_START 0x10000000 /* FLASH BANK 2 */
48#define FLASH2_SIZE 0x01000000
49#define FLASH2_BASE 0xd4000000
50
51#define ISA_START 0x20000000 /* ISA */
52#define ISA_SIZE 0x20000000
53#define ISA_BASE 0xe0000000
54
55#define PCIO_BASE IO_BASE
56
57#endif
diff --git a/arch/arm/mach-l7200/include/mach/io.h b/arch/arm/mach-l7200/include/mach/io.h
new file mode 100644
index 00000000000..d432ba9e5df
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/io.h
@@ -0,0 +1,27 @@
1/*
2 * arch/arm/mach-l7200/include/mach/io.h
3 *
4 * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
5 *
6 * Changelog:
7 * 03-21-2000 SJH Created from arch/arm/mach-nexuspci/include/mach/io.h
8 * 08-31-2000 SJH Added in IO functions necessary for new drivers
9 */
10#ifndef __ASM_ARM_ARCH_IO_H
11#define __ASM_ARM_ARCH_IO_H
12
13#include <mach/hardware.h>
14
15#define IO_SPACE_LIMIT 0xffffffff
16
17/*
18 * There are not real ISA nor PCI buses, so we fake it.
19 */
20static inline void __iomem *__io(unsigned long addr)
21{
22 return (void __iomem *)addr;
23}
24#define __io(a) __io(a)
25#define __mem_pci(a) (a)
26
27#endif
diff --git a/arch/arm/mach-l7200/include/mach/irqs.h b/arch/arm/mach-l7200/include/mach/irqs.h
new file mode 100644
index 00000000000..7edffd713c5
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/irqs.h
@@ -0,0 +1,56 @@
1/*
2 * arch/arm/mach-l7200/include/mach/irqs.h
3 *
4 * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
5 * Steve Hill (sjhill@cotw.com)
6 *
7 * Changelog:
8 * 01-02-2000 RS Create l7200 version
9 * 03-28-2000 SJH Removed unused interrupt
10 * 07-28-2000 SJH Added pseudo-keyboard interrupt
11 */
12
13/*
14 * NOTE: The second timer (Timer 2) is used as the keyboard
15 * interrupt when the keyboard driver is enabled.
16 */
17
18#define NR_IRQS 32
19
20#define IRQ_STWDOG 0 /* Watchdog timer */
21#define IRQ_PROG 1 /* Programmable interrupt */
22#define IRQ_DEBUG_RX 2 /* Comm Rx debug */
23#define IRQ_DEBUG_TX 3 /* Comm Tx debug */
24#define IRQ_GCTC1 4 /* Timer 1 */
25#define IRQ_GCTC2 5 /* Timer 2 / Keyboard */
26#define IRQ_DMA 6 /* DMA controller */
27#define IRQ_CLCD 7 /* Color LCD controller */
28#define IRQ_SM_RX 8 /* Smart card */
29#define IRQ_SM_TX 9 /* Smart cart */
30#define IRQ_SM_RST 10 /* Smart card */
31#define IRQ_SIB 11 /* Serial Interface Bus */
32#define IRQ_MMC 12 /* MultiMediaCard */
33#define IRQ_SSP1 13 /* Synchronous Serial Port 1 */
34#define IRQ_SSP2 14 /* Synchronous Serial Port 1 */
35#define IRQ_SPI 15 /* SPI slave */
36#define IRQ_UART_1 16 /* UART 1 */
37#define IRQ_UART_2 17 /* UART 2 */
38#define IRQ_IRDA 18 /* IRDA */
39#define IRQ_RTC_TICK 19 /* Real Time Clock tick */
40#define IRQ_RTC_ALARM 20 /* Real Time Clock alarm */
41#define IRQ_GPIO 21 /* General Purpose IO */
42#define IRQ_GPIO_DMA 22 /* General Purpose IO, DMA */
43#define IRQ_M2M 23 /* Memory to memory DMA */
44#define IRQ_RESERVED 24 /* RESERVED, don't use */
45#define IRQ_INTF 25 /* External active low interrupt */
46#define IRQ_INT0 26 /* External active low interrupt */
47#define IRQ_INT1 27 /* External active low interrupt */
48#define IRQ_INT2 28 /* External active low interrupt */
49#define IRQ_UCB1200 29 /* Interrupt generated by UCB1200*/
50#define IRQ_BAT_LO 30 /* Low batery or external power */
51#define IRQ_MEDIA_CHG 31 /* Media change interrupt */
52
53/*
54 * This is the offset of the FIQ "IRQ" numbers
55 */
56#define FIQ_START 64
diff --git a/arch/arm/mach-l7200/include/mach/memory.h b/arch/arm/mach-l7200/include/mach/memory.h
new file mode 100644
index 00000000000..f338cf3ffd9
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/memory.h
@@ -0,0 +1,29 @@
1/*
2 * arch/arm/mach-l7200/include/mach/memory.h
3 *
4 * Copyright (c) 2000 Steve Hill (sjhill@cotw.com)
5 * Copyright (c) 2000 Rob Scott (rscott@mtrob.fdns.net)
6 *
7 * Changelog:
8 * 03-13-2000 SJH Created
9 * 04-13-2000 RS Changed bus macros for new addr
10 * 05-03-2000 SJH Removed bus macros and fixed virt_to_phys macro
11 */
12#ifndef __ASM_ARCH_MEMORY_H
13#define __ASM_ARCH_MEMORY_H
14
15/*
16 * Physical DRAM offset on the L7200 SDB.
17 */
18#define PHYS_OFFSET UL(0xf0000000)
19
20#define __virt_to_bus(x) __virt_to_phys(x)
21#define __bus_to_virt(x) __phys_to_virt(x)
22
23/*
24 * Cache flushing area - ROM
25 */
26#define FLUSH_BASE_PHYS 0x40000000
27#define FLUSH_BASE 0xdf000000
28
29#endif
diff --git a/arch/arm/mach-l7200/include/mach/pmpcon.h b/arch/arm/mach-l7200/include/mach/pmpcon.h
new file mode 100644
index 00000000000..3959871e836
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/pmpcon.h
@@ -0,0 +1,46 @@
1/****************************************************************************/
2/*
3 * arch/arm/mach-l7200/include/mach/pmpcon.h
4 *
5 * Registers and helper functions for the L7200 Link-Up Systems
6 * DC/DC converter register.
7 *
8 * (C) Copyright 2000, S A McConnell (samcconn@cotw.com)
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive for
12 * more details.
13 */
14
15/****************************************************************************/
16
17#define PMPCON_OFF 0x00006000 /* Offset from IO_START_2. */
18
19/* IO_START_2 and IO_BASE_2 are defined in hardware.h */
20
21#define PMPCON_START (IO_START_2 + PMPCON_OFF) /* Physical address of reg. */
22#define PMPCON_BASE (IO_BASE_2 + PMPCON_OFF) /* Virtual address of reg. */
23
24
25#define PMPCON (*(volatile unsigned int *)(PMPCON_BASE))
26
27#define PWM2_50CYCLE 0x800
28#define CONTRAST 0x9
29
30#define PWM1H (CONTRAST)
31#define PWM1L (CONTRAST << 4)
32
33#define PMPCON_VALUE (PWM2_50CYCLE | PWM1L | PWM1H)
34
35/* PMPCON = 0x811; // too light and fuzzy
36 * PMPCON = 0x844;
37 * PMPCON = 0x866; // better color poor depth
38 * PMPCON = 0x888; // Darker but better depth
39 * PMPCON = 0x899; // Darker even better depth
40 * PMPCON = 0x8aa; // too dark even better depth
41 * PMPCON = 0X8cc; // Way too dark
42 */
43
44/* As CONTRAST value increases the greater the depth perception and
45 * the darker the colors.
46 */
diff --git a/arch/arm/mach-l7200/include/mach/pmu.h b/arch/arm/mach-l7200/include/mach/pmu.h
new file mode 100644
index 00000000000..a2da7aedf20
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/pmu.h
@@ -0,0 +1,125 @@
1/****************************************************************************/
2/*
3 * arch/arm/mach-l7200/include/mach/pmu.h
4 *
5 * Registers and helper functions for the L7200 Link-Up Systems
6 * Power Management Unit (PMU).
7 *
8 * (C) Copyright 2000, S A McConnell (samcconn@cotw.com)
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive for
12 * more details.
13 */
14
15/****************************************************************************/
16
17#define PMU_OFF 0x00050000 /* Offset from IO_START to the PMU registers. */
18
19/* IO_START and IO_BASE are defined in hardware.h */
20
21#define PMU_START (IO_START + PMU_OFF) /* Physical addr. of the PMU reg. */
22#define PMU_BASE (IO_BASE + PMU_OFF) /* Virtual addr. of the PMU reg. */
23
24
25/* Define the PMU registers for use by device drivers and the kernel. */
26
27typedef struct {
28 unsigned int CURRENT; /* Current configuration register */
29 unsigned int NEXT; /* Next configuration register */
30 unsigned int reserved;
31 unsigned int RUN; /* Run configuration register */
32 unsigned int COMM; /* Configuration command register */
33 unsigned int SDRAM; /* SDRAM configuration bypass register */
34} pmu_interface;
35
36#define PMU ((volatile pmu_interface *)(PMU_BASE))
37
38
39/* Macro's for reading the common register fields. */
40
41#define GET_TRANSOP(reg) ((reg >> 25) & 0x03) /* Bits 26-25 */
42#define GET_OSCEN(reg) ((reg >> 16) & 0x01)
43#define GET_OSCMUX(reg) ((reg >> 15) & 0x01)
44#define GET_PLLMUL(reg) ((reg >> 9) & 0x3f) /* Bits 14-9 */
45#define GET_PLLEN(reg) ((reg >> 8) & 0x01)
46#define GET_PLLMUX(reg) ((reg >> 7) & 0x01)
47#define GET_BCLK_DIV(reg) ((reg >> 3) & 0x03) /* Bits 4-3 */
48#define GET_SDRB_SEL(reg) ((reg >> 2) & 0x01)
49#define GET_SDRF_SEL(reg) ((reg >> 1) & 0x01)
50#define GET_FASTBUS(reg) (reg & 0x1)
51
52/* CFG_NEXT register */
53
54#define CFG_NEXT_CLOCKRECOVERY ((PMU->NEXT >> 18) & 0x7f) /* Bits 24-18 */
55#define CFG_NEXT_INTRET ((PMU->NEXT >> 17) & 0x01)
56#define CFG_NEXT_SDR_STOP ((PMU->NEXT >> 6) & 0x01)
57#define CFG_NEXT_SYSCLKEN ((PMU->NEXT >> 5) & 0x01)
58
59/* Useful field values that can be used to construct the
60 * CFG_NEXT and CFG_RUN registers.
61 */
62
63#define TRANSOP_NOP 0<<25 /* NOCHANGE_NOSTALL */
64#define NOCHANGE_STALL 1<<25
65#define CHANGE_NOSTALL 2<<25
66#define CHANGE_STALL 3<<25
67
68#define INTRET 1<<17
69#define OSCEN 1<<16
70#define OSCMUX 1<<15
71
72/* PLL frequencies */
73
74#define PLLMUL_0 0<<9 /* 3.6864 MHz */
75#define PLLMUL_1 1<<9 /* ?????? MHz */
76#define PLLMUL_5 5<<9 /* 18.432 MHz */
77#define PLLMUL_10 10<<9 /* 36.864 MHz */
78#define PLLMUL_18 18<<9 /* ?????? MHz */
79#define PLLMUL_20 20<<9 /* 73.728 MHz */
80#define PLLMUL_32 32<<9 /* ?????? MHz */
81#define PLLMUL_35 35<<9 /* 129.024 MHz */
82#define PLLMUL_36 36<<9 /* ?????? MHz */
83#define PLLMUL_39 39<<9 /* ?????? MHz */
84#define PLLMUL_40 40<<9 /* 147.456 MHz */
85
86/* Clock recovery times */
87
88#define CRCLOCK_1 1<<18
89#define CRCLOCK_2 2<<18
90#define CRCLOCK_4 4<<18
91#define CRCLOCK_8 8<<18
92#define CRCLOCK_16 16<<18
93#define CRCLOCK_32 32<<18
94#define CRCLOCK_63 63<<18
95#define CRCLOCK_127 127<<18
96
97#define PLLEN 1<<8
98#define PLLMUX 1<<7
99#define SDR_STOP 1<<6
100#define SYSCLKEN 1<<5
101
102#define BCLK_DIV_4 2<<3
103#define BCLK_DIV_2 1<<3
104#define BCLK_DIV_1 0<<3
105
106#define SDRB_SEL 1<<2
107#define SDRF_SEL 1<<1
108#define FASTBUS 1<<0
109
110
111/* CFG_SDRAM */
112
113#define SDRREFFQ 1<<0 /* Only if SDRSTOPRQ is not set. */
114#define SDRREFACK 1<<1 /* Read-only */
115#define SDRSTOPRQ 1<<2 /* Only if SDRREFFQ is not set. */
116#define SDRSTOPACK 1<<3 /* Read-only */
117#define PICEN 1<<4 /* Enable Co-procesor */
118#define PICTEST 1<<5
119
120#define GET_SDRREFFQ ((PMU->SDRAM >> 0) & 0x01)
121#define GET_SDRREFACK ((PMU->SDRAM >> 1) & 0x01) /* Read-only */
122#define GET_SDRSTOPRQ ((PMU->SDRAM >> 2) & 0x01)
123#define GET_SDRSTOPACK ((PMU->SDRAM >> 3) & 0x01) /* Read-only */
124#define GET_PICEN ((PMU->SDRAM >> 4) & 0x01)
125#define GET_PICTEST ((PMU->SDRAM >> 5) & 0x01)
diff --git a/arch/arm/mach-l7200/include/mach/serial.h b/arch/arm/mach-l7200/include/mach/serial.h
new file mode 100644
index 00000000000..adc05e5f837
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/serial.h
@@ -0,0 +1,37 @@
1/*
2 * arch/arm/mach-l7200/include/mach/serial.h
3 *
4 * Copyright (c) 2000 Rob Scott (rscott@mtrob.fdns.net)
5 * Steve Hill (sjhill@cotw.com)
6 *
7 * Changelog:
8 * 03-20-2000 SJH Created
9 * 03-26-2000 SJH Added flags for serial ports
10 * 03-27-2000 SJH Corrected BASE_BAUD value
11 * 04-14-2000 RS Made register addr dependent on IO_BASE
12 * 05-03-2000 SJH Complete rewrite
13 * 05-09-2000 SJH Stripped out architecture specific serial stuff
14 * and placed it in a separate file
15 * 07-28-2000 SJH Moved base baud rate variable
16 */
17#ifndef __ASM_ARCH_SERIAL_H
18#define __ASM_ARCH_SERIAL_H
19
20/*
21 * This assumes you have a 3.6864 MHz clock for your UART.
22 */
23#define BASE_BAUD 3686400
24
25/*
26 * Standard COM flags
27 */
28#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
29
30#define STD_SERIAL_PORT_DEFNS \
31 /* MAGIC UART CLK PORT IRQ FLAGS */ \
32 { 0, BASE_BAUD, UART1_BASE, IRQ_UART_1, STD_COM_FLAGS }, /* ttyLU0 */ \
33 { 0, BASE_BAUD, UART2_BASE, IRQ_UART_2, STD_COM_FLAGS }, /* ttyLU1 */ \
34
35#define EXTRA_SERIAL_PORT_DEFNS
36
37#endif
diff --git a/arch/arm/mach-l7200/include/mach/serial_l7200.h b/arch/arm/mach-l7200/include/mach/serial_l7200.h
new file mode 100644
index 00000000000..645f1c5e568
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/serial_l7200.h
@@ -0,0 +1,101 @@
1/*
2 * arch/arm/mach-l7200/include/mach/serial_l7200.h
3 *
4 * Copyright (c) 2000 Steven Hill (sjhill@cotw.com)
5 *
6 * Changelog:
7 * 05-09-2000 SJH Created
8 */
9#ifndef __ASM_ARCH_SERIAL_L7200_H
10#define __ASM_ARCH_SERIAL_L7200_H
11
12#include <mach/memory.h>
13
14/*
15 * This assumes you have a 3.6864 MHz clock for your UART.
16 */
17#define BASE_BAUD 3686400
18
19/*
20 * UART base register addresses
21 */
22#define UART1_BASE (IO_BASE + 0x00044000)
23#define UART2_BASE (IO_BASE + 0x00045000)
24
25/*
26 * UART register offsets
27 */
28#define UARTDR 0x00 /* Tx/Rx data */
29#define RXSTAT 0x04 /* Rx status */
30#define H_UBRLCR 0x08 /* mode register high */
31#define M_UBRLCR 0x0C /* mode reg mid (MSB of baud)*/
32#define L_UBRLCR 0x10 /* mode reg low (LSB of baud)*/
33#define UARTCON 0x14 /* control register */
34#define UARTFLG 0x18 /* flag register */
35#define UARTINTSTAT 0x1C /* FIFO IRQ status register */
36#define UARTINTMASK 0x20 /* FIFO IRQ mask register */
37
38/*
39 * UART baud rate register values
40 */
41#define BR_110 0x827
42#define BR_1200 0x06e
43#define BR_2400 0x05f
44#define BR_4800 0x02f
45#define BR_9600 0x017
46#define BR_14400 0x00f
47#define BR_19200 0x00b
48#define BR_38400 0x005
49#define BR_57600 0x003
50#define BR_76800 0x002
51#define BR_115200 0x001
52
53/*
54 * Receiver status register (RXSTAT) mask values
55 */
56#define RXSTAT_NO_ERR 0x00 /* No error */
57#define RXSTAT_FRM_ERR 0x01 /* Framing error */
58#define RXSTAT_PAR_ERR 0x02 /* Parity error */
59#define RXSTAT_OVR_ERR 0x04 /* Overrun error */
60
61/*
62 * High byte of UART bit rate and line control register (H_UBRLCR) values
63 */
64#define UBRLCR_BRK 0x01 /* generate break on tx */
65#define UBRLCR_PEN 0x02 /* enable parity */
66#define UBRLCR_PDIS 0x00 /* disable parity */
67#define UBRLCR_EVEN 0x04 /* 1= even parity,0 = odd parity */
68#define UBRLCR_STP2 0x08 /* transmit 2 stop bits */
69#define UBRLCR_FIFO 0x10 /* enable FIFO */
70#define UBRLCR_LEN5 0x60 /* word length5 */
71#define UBRLCR_LEN6 0x40 /* word length6 */
72#define UBRLCR_LEN7 0x20 /* word length7 */
73#define UBRLCR_LEN8 0x00 /* word length8 */
74
75/*
76 * UART control register (UARTCON) values
77 */
78#define UARTCON_UARTEN 0x01 /* Enable UART */
79#define UARTCON_DMAONERR 0x08 /* Mask RxDmaRq when errors occur */
80
81/*
82 * UART flag register (UARTFLG) mask values
83 */
84#define UARTFLG_UTXFF 0x20 /* Transmit FIFO full */
85#define UARTFLG_URXFE 0x10 /* Receiver FIFO empty */
86#define UARTFLG_UBUSY 0x08 /* Transmitter busy */
87#define UARTFLG_DCD 0x04 /* Data carrier detect */
88#define UARTFLG_DSR 0x02 /* Data set ready */
89#define UARTFLG_CTS 0x01 /* Clear to send */
90
91/*
92 * UART interrupt status/clear registers (UARTINTSTAT/CLR) values
93 */
94#define UART_TXINT 0x01 /* TX interrupt */
95#define UART_RXINT 0x02 /* RX interrupt */
96#define UART_RXERRINT 0x04 /* RX error interrupt */
97#define UART_MSINT 0x08 /* Modem Status interrupt */
98#define UART_UDINT 0x10 /* UART Disabled interrupt */
99#define UART_ALLIRQS 0x1f /* All interrupts */
100
101#endif
diff --git a/arch/arm/mach-l7200/include/mach/sib.h b/arch/arm/mach-l7200/include/mach/sib.h
new file mode 100644
index 00000000000..965728712cf
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/sib.h
@@ -0,0 +1,119 @@
1/****************************************************************************/
2/*
3 * arch/arm/mach-l7200/include/mach/sib.h
4 *
5 * Registers and helper functions for the Serial Interface Bus.
6 *
7 * (C) Copyright 2000, S A McConnell (samcconn@cotw.com)
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file COPYING in the main directory of this archive for
11 * more details.
12 */
13
14/****************************************************************************/
15
16#define SIB_OFF 0x00040000 /* Offset from IO_START to the SIB reg's. */
17
18/* IO_START and IO_BASE are defined in hardware.h */
19
20#define SIB_START (IO_START + SIB_OFF) /* Physical addr of the SIB reg. */
21#define SIB_BASE (IO_BASE + SIB_OFF) /* Virtual addr of the SIB reg. */
22
23/* Offsets from the start of the SIB for all the registers. */
24
25/* Define the SIB registers for use by device drivers and the kernel. */
26
27typedef struct
28{
29 unsigned int MCCR; /* SIB Control Register Offset: 0x00 */
30 unsigned int RES1; /* Reserved Offset: 0x04 */
31 unsigned int MCDR0; /* SIB Data Register 0 Offset: 0x08 */
32 unsigned int MCDR1; /* SIB Data Register 1 Offset: 0x0c */
33 unsigned int MCDR2; /* SIB Data Register 2 (UCB1x00) Offset: 0x10 */
34 unsigned int RES2; /* Reserved Offset: 0x14 */
35 unsigned int MCSR; /* SIB Status Register Offset: 0x18 */
36} SIB_Interface;
37
38#define SIB ((volatile SIB_Interface *) (SIB_BASE))
39
40/* MCCR */
41
42#define INTERNAL_FREQ 9216000 /* Hertz */
43#define AUDIO_FREQ 5000 /* Hertz */
44#define TELECOM_FREQ 5000 /* Hertz */
45
46#define AUDIO_DIVIDE (INTERNAL_FREQ / (32 * AUDIO_FREQ))
47#define TELECOM_DIVIDE (INTERNAL_FREQ / (32 * TELECOM_FREQ))
48
49#define MCCR_ASD57 AUDIO_DIVIDE
50#define MCCR_TSD57 (TELECOM_DIVIDE << 8)
51#define MCCR_MCE (1 << 16) /* SIB enable */
52#define MCCR_ECS (1 << 17) /* External Clock Select */
53#define MCCR_ADM (1 << 18) /* A/D Data Sampling */
54#define MCCR_PMC (1 << 26) /* PIN Multiplexer Control */
55
56
57#define GET_ASD ((SIB->MCCR >> 0) & 0x3f) /* Audio Sample Rate Div. */
58#define GET_TSD ((SIB->MCCR >> 8) & 0x3f) /* Telcom Sample Rate Div. */
59#define GET_MCE ((SIB->MCCR >> 16) & 0x01) /* SIB Enable */
60#define GET_ECS ((SIB->MCCR >> 17) & 0x01) /* External Clock Select */
61#define GET_ADM ((SIB->MCCR >> 18) & 0x01) /* A/D Data Sampling Mode */
62#define GET_TTM ((SIB->MCCR >> 19) & 0x01) /* Telco Trans. FIFO I mask */
63#define GET_TRM ((SIB->MCCR >> 20) & 0x01) /* Telco Recv. FIFO I mask */
64#define GET_ATM ((SIB->MCCR >> 21) & 0x01) /* Audio Trans. FIFO I mask */
65#define GET_ARM ((SIB->MCCR >> 22) & 0x01) /* Audio Recv. FIFO I mask */
66#define GET_LBM ((SIB->MCCR >> 23) & 0x01) /* Loop Back Mode */
67#define GET_ECP ((SIB->MCCR >> 24) & 0x03) /* Extern. Clck Prescale sel */
68#define GET_PMC ((SIB->MCCR >> 26) & 0x01) /* PIN Multiplexer Control */
69#define GET_ERI ((SIB->MCCR >> 27) & 0x01) /* External Read Interrupt */
70#define GET_EWI ((SIB->MCCR >> 28) & 0x01) /* External Write Interrupt */
71
72/* MCDR0 */
73
74#define AUDIO_RECV ((SIB->MCDR0 >> 4) & 0xfff)
75#define AUDIO_WRITE(v) ((SIB->MCDR0 = (v & 0xfff) << 4))
76
77/* MCDR1 */
78
79#define TELECOM_RECV ((SIB->MCDR1 >> 2) & 032fff)
80#define TELECOM_WRITE(v) ((SIB->MCDR1 = (v & 0x3fff) << 2))
81
82
83/* MCSR */
84
85#define MCSR_ATU (1 << 4) /* Audio Transmit FIFO Underrun */
86#define MCSR_ARO (1 << 5) /* Audio Receive FIFO Underrun */
87#define MCSR_TTU (1 << 6) /* TELECOM Transmit FIFO Underrun */
88#define MCSR_TRO (1 << 7) /* TELECOM Receive FIFO Underrun */
89
90#define MCSR_CLEAR_UNDERUN_BITS (MCSR_ATU | MCSR_ARO | MCSR_TTU | MCSR_TRO)
91
92
93#define GET_ATS ((SIB->MCSR >> 0) & 0x01) /* Audio Transmit FIFO Service Req*/
94#define GET_ARS ((SIB->MCSR >> 1) & 0x01) /* Audio Recv FIFO Service Request*/
95#define GET_TTS ((SIB->MCSR >> 2) & 0x01) /* TELECOM Transmit FIFO Flag */
96#define GET_TRS ((SIB->MCSR >> 3) & 0x01) /* TELECOM Recv FIFO Service Req. */
97#define GET_ATU ((SIB->MCSR >> 4) & 0x01) /* Audio Transmit FIFO Underrun */
98#define GET_ARO ((SIB->MCSR >> 5) & 0x01) /* Audio Receive FIFO Underrun */
99#define GET_TTU ((SIB->MCSR >> 6) & 0x01) /* TELECOM Transmit FIFO Underrun */
100#define GET_TRO ((SIB->MCSR >> 7) & 0x01) /* TELECOM Receive FIFO Underrun */
101#define GET_ANF ((SIB->MCSR >> 8) & 0x01) /* Audio Transmit FIFO not full */
102#define GET_ANE ((SIB->MCSR >> 9) & 0x01) /* Audio Receive FIFO not empty */
103#define GET_TNF ((SIB->MCSR >> 10) & 0x01) /* Telecom Transmit FIFO not full */
104#define GET_TNE ((SIB->MCSR >> 11) & 0x01) /* Telecom Receive FIFO not empty */
105#define GET_CWC ((SIB->MCSR >> 12) & 0x01) /* Codec Write Complete */
106#define GET_CRC ((SIB->MCSR >> 13) & 0x01) /* Codec Read Complete */
107#define GET_ACE ((SIB->MCSR >> 14) & 0x01) /* Audio Codec Enabled */
108#define GET_TCE ((SIB->MCSR >> 15) & 0x01) /* Telecom Codec Enabled */
109
110/* MCDR2 */
111
112#define MCDR2_rW (1 << 16)
113
114#define WRITE_MCDR2(reg, data) (SIB->MCDR2 =((reg<<17)|MCDR2_rW|(data&0xffff)))
115#define MCDR2_WRITE_COMPLETE GET_CWC
116
117#define INITIATE_MCDR2_READ(reg) (SIB->MCDR2 = (reg << 17))
118#define MCDR2_READ_COMPLETE GET_CRC
119#define MCDR2_READ (SIB->MCDR2 & 0xffff)
diff --git a/arch/arm/mach-l7200/include/mach/sys-clock.h b/arch/arm/mach-l7200/include/mach/sys-clock.h
new file mode 100644
index 00000000000..2d7722be60e
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/sys-clock.h
@@ -0,0 +1,67 @@
1/****************************************************************************/
2/*
3 * arch/arm/mach-l7200/include/mach/sys-clock.h
4 *
5 * Registers and helper functions for the L7200 Link-Up Systems
6 * System clocks.
7 *
8 * (C) Copyright 2000, S A McConnell (samcconn@cotw.com)
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive for
12 * more details.
13 */
14
15/****************************************************************************/
16
17#define SYS_CLOCK_OFF 0x00050030 /* Offset from IO_START. */
18
19/* IO_START and IO_BASE are defined in hardware.h */
20
21#define SYS_CLOCK_START (IO_START + SYS_CLCOK_OFF) /* Physical address */
22#define SYS_CLOCK_BASE (IO_BASE + SYS_CLOCK_OFF) /* Virtual address */
23
24/* Define the interface to the SYS_CLOCK */
25
26typedef struct
27{
28 unsigned int ENABLE;
29 unsigned int ESYNC;
30 unsigned int SELECT;
31} sys_clock_interface;
32
33#define SYS_CLOCK ((volatile sys_clock_interface *)(SYS_CLOCK_BASE))
34
35//#define CLOCK_EN (*(volatile unsigned long *)(PMU_BASE+CLOCK_EN_OFF))
36//#define CLOCK_ESYNC (*(volatile unsigned long *)(PMU_BASE+CLOCK_ESYNC_OFF))
37//#define CLOCK_SEL (*(volatile unsigned long *)(PMU_BASE+CLOCK_SEL_OFF))
38
39/* SYS_CLOCK -> ENABLE */
40
41#define SYN_EN 1<<0
42#define B18M_EN 1<<1
43#define CLK3M6_EN 1<<2
44#define BUART_EN 1<<3
45#define CLK18MU_EN 1<<4
46#define FIR_EN 1<<5
47#define MIRN_EN 1<<6
48#define UARTM_EN 1<<7
49#define SIBADC_EN 1<<8
50#define ALTD_EN 1<<9
51#define CLCLK_EN 1<<10
52
53/* SYS_CLOCK -> SELECT */
54
55#define CLK18M_DIV 1<<0
56#define MIR_SEL 1<<1
57#define SSP_SEL 1<<4
58#define MM_DIV 1<<5
59#define MM_SEL 1<<6
60#define ADC_SEL_2 0<<7
61#define ADC_SEL_4 1<<7
62#define ADC_SEL_8 3<<7
63#define ADC_SEL_16 7<<7
64#define ADC_SEL_32 0x0f<<7
65#define ADC_SEL_64 0x1f<<7
66#define ADC_SEL_128 0x3f<<7
67#define ALTD_SEL 1<<13
diff --git a/arch/arm/mach-l7200/include/mach/system.h b/arch/arm/mach-l7200/include/mach/system.h
new file mode 100644
index 00000000000..5272abee0d0
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/system.h
@@ -0,0 +1,29 @@
1/*
2 * arch/arm/mach-l7200/include/mach/system.h
3 *
4 * Copyright (c) 2000 Steve Hill (sjhill@cotw.com)
5 *
6 * Changelog
7 * 03-21-2000 SJH Created
8 * 04-26-2000 SJH Fixed functions
9 * 05-03-2000 SJH Removed usage of obsolete 'iomd.h'
10 * 05-31-2000 SJH Properly implemented 'arch_idle'
11 */
12#ifndef __ASM_ARCH_SYSTEM_H
13#define __ASM_ARCH_SYSTEM_H
14
15#include <mach/hardware.h>
16
17static inline void arch_idle(void)
18{
19 *(unsigned long *)(IO_BASE + 0x50004) = 1; /* idle mode */
20}
21
22static inline void arch_reset(char mode)
23{
24 if (mode == 's') {
25 cpu_reset(0);
26 }
27}
28
29#endif
diff --git a/arch/arm/mach-l7200/include/mach/time.h b/arch/arm/mach-l7200/include/mach/time.h
new file mode 100644
index 00000000000..061771c2c2b
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/time.h
@@ -0,0 +1,73 @@
1/*
2 * arch/arm/mach-l7200/include/mach/time.h
3 *
4 * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
5 * Steve Hill (sjhill@cotw.com)
6 *
7 * Changelog:
8 * 01-02-2000 RS Created l7200 version, derived from rpc code
9 * 05-03-2000 SJH Complete rewrite
10 */
11#ifndef _ASM_ARCH_TIME_H
12#define _ASM_ARCH_TIME_H
13
14#include <mach/irqs.h>
15
16/*
17 * RTC base register address
18 */
19#define RTC_BASE (IO_BASE_2 + 0x2000)
20
21/*
22 * RTC registers
23 */
24#define RTC_RTCDR (*(volatile unsigned char *) (RTC_BASE + 0x000))
25#define RTC_RTCMR (*(volatile unsigned char *) (RTC_BASE + 0x004))
26#define RTC_RTCS (*(volatile unsigned char *) (RTC_BASE + 0x008))
27#define RTC_RTCC (*(volatile unsigned char *) (RTC_BASE + 0x008))
28#define RTC_RTCDV (*(volatile unsigned char *) (RTC_BASE + 0x00c))
29#define RTC_RTCCR (*(volatile unsigned char *) (RTC_BASE + 0x010))
30
31/*
32 * RTCCR register values
33 */
34#define RTC_RATE_32 0x00 /* 32 Hz tick */
35#define RTC_RATE_64 0x10 /* 64 Hz tick */
36#define RTC_RATE_128 0x20 /* 128 Hz tick */
37#define RTC_RATE_256 0x30 /* 256 Hz tick */
38#define RTC_EN_ALARM 0x01 /* Enable alarm */
39#define RTC_EN_TIC 0x04 /* Enable counter */
40#define RTC_EN_STWDOG 0x08 /* Enable watchdog */
41
42/*
43 * Handler for RTC timer interrupt
44 */
45static irqreturn_t
46timer_interrupt(int irq, void *dev_id)
47{
48 struct pt_regs *regs = get_irq_regs();
49 do_timer(1);
50#ifndef CONFIG_SMP
51 update_process_times(user_mode(regs));
52#endif
53 do_profile(regs);
54 RTC_RTCC = 0; /* Clear interrupt */
55
56 return IRQ_HANDLED;
57}
58
59/*
60 * Set up RTC timer interrupt, and return the current time in seconds.
61 */
62void __init time_init(void)
63{
64 RTC_RTCC = 0; /* Clear interrupt */
65
66 timer_irq.handler = timer_interrupt;
67
68 setup_irq(IRQ_RTC_TICK, &timer_irq);
69
70 RTC_RTCCR = RTC_RATE_128 | RTC_EN_TIC; /* Set rate and enable timer */
71}
72
73#endif
diff --git a/arch/arm/mach-l7200/include/mach/timex.h b/arch/arm/mach-l7200/include/mach/timex.h
new file mode 100644
index 00000000000..ffc96a63b5a
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/timex.h
@@ -0,0 +1,20 @@
1/*
2 * arch/arm/mach-l7200/include/mach/timex.h
3 *
4 * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
5 * Steve Hill (sjhill@cotw.com)
6 *
7 * 04-21-2000 RS Created file
8 * 05-03-2000 SJH Tick rate was wrong
9 *
10 */
11
12/*
13 * On the ARM720T, clock ticks are set to 128 Hz.
14 *
15 * NOTE: The actual RTC value is set in 'time.h' which
16 * must be changed when choosing a different tick
17 * rate. The value of HZ in 'param.h' must also
18 * be changed to match below.
19 */
20#define CLOCK_TICK_RATE 128
diff --git a/arch/arm/mach-l7200/include/mach/uncompress.h b/arch/arm/mach-l7200/include/mach/uncompress.h
new file mode 100644
index 00000000000..591c962bb31
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/uncompress.h
@@ -0,0 +1,39 @@
1/*
2 * arch/arm/mach-l7200/include/mach/uncompress.h
3 *
4 * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
5 *
6 * Changelog:
7 * 05-01-2000 SJH Created
8 * 05-13-2000 SJH Filled in function bodies
9 * 07-26-2000 SJH Removed hard coded baud rate
10 */
11
12#include <mach/hardware.h>
13
14#define IO_UART IO_START + 0x00044000
15
16#define __raw_writeb(v,p) (*(volatile unsigned char *)(p) = (v))
17#define __raw_readb(p) (*(volatile unsigned char *)(p))
18
19static inline void putc(int c)
20{
21 while(__raw_readb(IO_UART + 0x18) & 0x20 ||
22 __raw_readb(IO_UART + 0x18) & 0x08)
23 barrier();
24
25 __raw_writeb(c, IO_UART + 0x00);
26}
27
28static inline void flush(void)
29{
30}
31
32static __inline__ void arch_decomp_setup(void)
33{
34 __raw_writeb(0x00, IO_UART + 0x08); /* Set HSB */
35 __raw_writeb(0x00, IO_UART + 0x20); /* Disable IRQs */
36 __raw_writeb(0x01, IO_UART + 0x14); /* Enable UART */
37}
38
39#define arch_decomp_wdog()
diff --git a/arch/arm/mach-l7200/include/mach/vmalloc.h b/arch/arm/mach-l7200/include/mach/vmalloc.h
new file mode 100644
index 00000000000..85f0abbf15f
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/vmalloc.h
@@ -0,0 +1,4 @@
1/*
2 * arch/arm/mach-l7200/include/mach/vmalloc.h
3 */
4#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 10:20:38 -0500