diff options
Diffstat (limited to 'arch/arm/common/gic.c')
-rw-r--r-- | arch/arm/common/gic.c | 22 |
1 files changed, 10 insertions, 12 deletions
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index 4deece5fbdf..0c89bd35e06 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c | |||
@@ -72,7 +72,7 @@ static inline unsigned int gic_irq(unsigned int irq) | |||
72 | * unmask it, in the same way we need to unmask an interrupt when | 72 | * unmask it, in the same way we need to unmask an interrupt when |
73 | * we first enable it. | 73 | * we first enable it. |
74 | * | 74 | * |
75 | * The GIC has a seperate notion of "end of interrupt" to re-enable | 75 | * The GIC has a separate notion of "end of interrupt" to re-enable |
76 | * an interrupt after handling, in order to support hardware | 76 | * an interrupt after handling, in order to support hardware |
77 | * prioritisation. | 77 | * prioritisation. |
78 | * | 78 | * |
@@ -125,12 +125,11 @@ static void gic_set_cpu(unsigned int irq, cpumask_t mask_val) | |||
125 | } | 125 | } |
126 | #endif | 126 | #endif |
127 | 127 | ||
128 | static void fastcall gic_handle_cascade_irq(unsigned int irq, | 128 | static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) |
129 | struct irq_desc *desc) | ||
130 | { | 129 | { |
131 | struct gic_chip_data *chip_data = get_irq_data(irq); | 130 | struct gic_chip_data *chip_data = get_irq_data(irq); |
132 | struct irq_chip *chip = get_irq_chip(irq); | 131 | struct irq_chip *chip = get_irq_chip(irq); |
133 | unsigned int cascade_irq; | 132 | unsigned int cascade_irq, gic_irq; |
134 | unsigned long status; | 133 | unsigned long status; |
135 | 134 | ||
136 | /* primary controller ack'ing */ | 135 | /* primary controller ack'ing */ |
@@ -140,16 +139,15 @@ static void fastcall gic_handle_cascade_irq(unsigned int irq, | |||
140 | status = readl(chip_data->cpu_base + GIC_CPU_INTACK); | 139 | status = readl(chip_data->cpu_base + GIC_CPU_INTACK); |
141 | spin_unlock(&irq_controller_lock); | 140 | spin_unlock(&irq_controller_lock); |
142 | 141 | ||
143 | cascade_irq = (status & 0x3ff); | 142 | gic_irq = (status & 0x3ff); |
144 | if (cascade_irq > 1020) | 143 | if (gic_irq == 1023) |
145 | goto out; | 144 | goto out; |
146 | if (cascade_irq < 32 || cascade_irq >= NR_IRQS) { | ||
147 | do_bad_IRQ(cascade_irq, desc); | ||
148 | goto out; | ||
149 | } | ||
150 | 145 | ||
151 | cascade_irq += chip_data->irq_offset; | 146 | cascade_irq = gic_irq + chip_data->irq_offset; |
152 | generic_handle_irq(cascade_irq); | 147 | if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS)) |
148 | do_bad_IRQ(cascade_irq, desc); | ||
149 | else | ||
150 | generic_handle_irq(cascade_irq); | ||
153 | 151 | ||
154 | out: | 152 | out: |
155 | /* primary controller unmasking */ | 153 | /* primary controller unmasking */ |