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-rw-r--r--Documentation/powerpc/booting-without-of.txt1025
-rw-r--r--Documentation/powerpc/bootwrapper.txt141
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/board.txt29
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm.txt67
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/brg.txt21
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/i2c.txt41
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/pic.txt18
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/usb.txt15
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/network.txt45
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt58
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/firmware.txt24
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/par_io.txt51
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/pincfg.txt60
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/ucc.txt70
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/usb.txt22
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/serial.txt21
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/diu.txt18
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/dma.txt127
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/gtm.txt31
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/guts.txt25
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/i2c.txt32
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/lbc.txt35
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/msi-pic.txt36
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/sata.txt29
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/sec.txt68
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/spi.txt24
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/ssi.txt38
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/tsec.txt69
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/usb.txt59
29 files changed, 1280 insertions, 1019 deletions
diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt
index 46a9dba11f2..aee243a846a 100644
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -1247,80 +1247,7 @@ descriptions for the SOC devices for which new nodes have been
1247defined; this list will expand as more and more SOC-containing 1247defined; this list will expand as more and more SOC-containing
1248platforms are moved over to use the flattened-device-tree model. 1248platforms are moved over to use the flattened-device-tree model.
1249 1249
1250 a) MDIO IO device 1250 a) PHY nodes
1251
1252 The MDIO is a bus to which the PHY devices are connected. For each
1253 device that exists on this bus, a child node should be created. See
1254 the definition of the PHY node below for an example of how to define
1255 a PHY.
1256
1257 Required properties:
1258 - reg : Offset and length of the register set for the device
1259 - compatible : Should define the compatible device type for the
1260 mdio. Currently, this is most likely to be "fsl,gianfar-mdio"
1261
1262 Example:
1263
1264 mdio@24520 {
1265 reg = <24520 20>;
1266 compatible = "fsl,gianfar-mdio";
1267
1268 ethernet-phy@0 {
1269 ......
1270 };
1271 };
1272
1273
1274 b) Gianfar-compatible ethernet nodes
1275
1276 Required properties:
1277
1278 - device_type : Should be "network"
1279 - model : Model of the device. Can be "TSEC", "eTSEC", or "FEC"
1280 - compatible : Should be "gianfar"
1281 - reg : Offset and length of the register set for the device
1282 - mac-address : List of bytes representing the ethernet address of
1283 this controller
1284 - interrupts : <a b> where a is the interrupt number and b is a
1285 field that represents an encoding of the sense and level
1286 information for the interrupt. This should be encoded based on
1287 the information in section 2) depending on the type of interrupt
1288 controller you have.
1289 - interrupt-parent : the phandle for the interrupt controller that
1290 services interrupts for this device.
1291 - phy-handle : The phandle for the PHY connected to this ethernet
1292 controller.
1293 - fixed-link : <a b c d e> where a is emulated phy id - choose any,
1294 but unique to the all specified fixed-links, b is duplex - 0 half,
1295 1 full, c is link speed - d#10/d#100/d#1000, d is pause - 0 no
1296 pause, 1 pause, e is asym_pause - 0 no asym_pause, 1 asym_pause.
1297
1298 Recommended properties:
1299
1300 - phy-connection-type : a string naming the controller/PHY interface type,
1301 i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id", "sgmii",
1302 "tbi", or "rtbi". This property is only really needed if the connection
1303 is of type "rgmii-id", as all other connection types are detected by
1304 hardware.
1305
1306
1307 Example:
1308
1309 ethernet@24000 {
1310 #size-cells = <0>;
1311 device_type = "network";
1312 model = "TSEC";
1313 compatible = "gianfar";
1314 reg = <24000 1000>;
1315 mac-address = [ 00 E0 0C 00 73 00 ];
1316 interrupts = <d 3 e 3 12 3>;
1317 interrupt-parent = <40000>;
1318 phy-handle = <2452000>
1319 };
1320
1321
1322
1323 c) PHY nodes
1324 1251
1325 Required properties: 1252 Required properties:
1326 1253
@@ -1348,7 +1275,7 @@ platforms are moved over to use the flattened-device-tree model.
1348 }; 1275 };
1349 1276
1350 1277
1351 d) Interrupt controllers 1278 b) Interrupt controllers
1352 1279
1353 Some SOC devices contain interrupt controllers that are different 1280 Some SOC devices contain interrupt controllers that are different
1354 from the standard Open PIC specification. The SOC device nodes for 1281 from the standard Open PIC specification. The SOC device nodes for
@@ -1361,491 +1288,14 @@ platforms are moved over to use the flattened-device-tree model.
1361 1288
1362 pic@40000 { 1289 pic@40000 {
1363 linux,phandle = <40000>; 1290 linux,phandle = <40000>;
1364 clock-frequency = <0>;
1365 interrupt-controller; 1291 interrupt-controller;
1366 #address-cells = <0>; 1292 #address-cells = <0>;
1367 reg = <40000 40000>; 1293 reg = <40000 40000>;
1368 built-in;
1369 compatible = "chrp,open-pic"; 1294 compatible = "chrp,open-pic";
1370 device_type = "open-pic"; 1295 device_type = "open-pic";
1371 big-endian;
1372 };
1373
1374
1375 e) I2C
1376
1377 Required properties :
1378
1379 - device_type : Should be "i2c"
1380 - reg : Offset and length of the register set for the device
1381
1382 Recommended properties :
1383
1384 - compatible : Should be "fsl-i2c" for parts compatible with
1385 Freescale I2C specifications.
1386 - interrupts : <a b> where a is the interrupt number and b is a
1387 field that represents an encoding of the sense and level
1388 information for the interrupt. This should be encoded based on
1389 the information in section 2) depending on the type of interrupt
1390 controller you have.
1391 - interrupt-parent : the phandle for the interrupt controller that
1392 services interrupts for this device.
1393 - dfsrr : boolean; if defined, indicates that this I2C device has
1394 a digital filter sampling rate register
1395 - fsl5200-clocking : boolean; if defined, indicated that this device
1396 uses the FSL 5200 clocking mechanism.
1397
1398 Example :
1399
1400 i2c@3000 {
1401 interrupt-parent = <40000>;
1402 interrupts = <1b 3>;
1403 reg = <3000 18>;
1404 device_type = "i2c";
1405 compatible = "fsl-i2c";
1406 dfsrr;
1407 };
1408
1409
1410 f) Freescale SOC USB controllers
1411
1412 The device node for a USB controller that is part of a Freescale
1413 SOC is as described in the document "Open Firmware Recommended
1414 Practice : Universal Serial Bus" with the following modifications
1415 and additions :
1416
1417 Required properties :
1418 - compatible : Should be "fsl-usb2-mph" for multi port host USB
1419 controllers, or "fsl-usb2-dr" for dual role USB controllers
1420 - phy_type : For multi port host USB controllers, should be one of
1421 "ulpi", or "serial". For dual role USB controllers, should be
1422 one of "ulpi", "utmi", "utmi_wide", or "serial".
1423 - reg : Offset and length of the register set for the device
1424 - port0 : boolean; if defined, indicates port0 is connected for
1425 fsl-usb2-mph compatible controllers. Either this property or
1426 "port1" (or both) must be defined for "fsl-usb2-mph" compatible
1427 controllers.
1428 - port1 : boolean; if defined, indicates port1 is connected for
1429 fsl-usb2-mph compatible controllers. Either this property or
1430 "port0" (or both) must be defined for "fsl-usb2-mph" compatible
1431 controllers.
1432 - dr_mode : indicates the working mode for "fsl-usb2-dr" compatible
1433 controllers. Can be "host", "peripheral", or "otg". Default to
1434 "host" if not defined for backward compatibility.
1435
1436 Recommended properties :
1437 - interrupts : <a b> where a is the interrupt number and b is a
1438 field that represents an encoding of the sense and level
1439 information for the interrupt. This should be encoded based on
1440 the information in section 2) depending on the type of interrupt
1441 controller you have.
1442 - interrupt-parent : the phandle for the interrupt controller that
1443 services interrupts for this device.
1444
1445 Example multi port host USB controller device node :
1446 usb@22000 {
1447 compatible = "fsl-usb2-mph";
1448 reg = <22000 1000>;
1449 #address-cells = <1>;
1450 #size-cells = <0>;
1451 interrupt-parent = <700>;
1452 interrupts = <27 1>;
1453 phy_type = "ulpi";
1454 port0;
1455 port1;
1456 }; 1296 };
1457 1297
1458 Example dual role USB controller device node : 1298 c) CFI or JEDEC memory-mapped NOR flash
1459 usb@23000 {
1460 compatible = "fsl-usb2-dr";
1461 reg = <23000 1000>;
1462 #address-cells = <1>;
1463 #size-cells = <0>;
1464 interrupt-parent = <700>;
1465 interrupts = <26 1>;
1466 dr_mode = "otg";
1467 phy = "ulpi";
1468 };
1469
1470
1471 g) Freescale SOC SEC Security Engines
1472
1473 Required properties:
1474
1475 - device_type : Should be "crypto"
1476 - model : Model of the device. Should be "SEC1" or "SEC2"
1477 - compatible : Should be "talitos"
1478 - reg : Offset and length of the register set for the device
1479 - interrupts : <a b> where a is the interrupt number and b is a
1480 field that represents an encoding of the sense and level
1481 information for the interrupt. This should be encoded based on
1482 the information in section 2) depending on the type of interrupt
1483 controller you have.
1484 - interrupt-parent : the phandle for the interrupt controller that
1485 services interrupts for this device.
1486 - num-channels : An integer representing the number of channels
1487 available.
1488 - channel-fifo-len : An integer representing the number of
1489 descriptor pointers each channel fetch fifo can hold.
1490 - exec-units-mask : The bitmask representing what execution units
1491 (EUs) are available. It's a single 32-bit cell. EU information
1492 should be encoded following the SEC's Descriptor Header Dword
1493 EU_SEL0 field documentation, i.e. as follows:
1494
1495 bit 0 = reserved - should be 0
1496 bit 1 = set if SEC has the ARC4 EU (AFEU)
1497 bit 2 = set if SEC has the DES/3DES EU (DEU)
1498 bit 3 = set if SEC has the message digest EU (MDEU)
1499 bit 4 = set if SEC has the random number generator EU (RNG)
1500 bit 5 = set if SEC has the public key EU (PKEU)
1501 bit 6 = set if SEC has the AES EU (AESU)
1502 bit 7 = set if SEC has the Kasumi EU (KEU)
1503
1504 bits 8 through 31 are reserved for future SEC EUs.
1505
1506 - descriptor-types-mask : The bitmask representing what descriptors
1507 are available. It's a single 32-bit cell. Descriptor type
1508 information should be encoded following the SEC's Descriptor
1509 Header Dword DESC_TYPE field documentation, i.e. as follows:
1510
1511 bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type
1512 bit 1 = set if SEC supports the ipsec_esp descriptor type
1513 bit 2 = set if SEC supports the common_nonsnoop desc. type
1514 bit 3 = set if SEC supports the 802.11i AES ccmp desc. type
1515 bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type
1516 bit 5 = set if SEC supports the srtp descriptor type
1517 bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type
1518 bit 7 = set if SEC supports the pkeu_assemble descriptor type
1519 bit 8 = set if SEC supports the aesu_key_expand_output desc.type
1520 bit 9 = set if SEC supports the pkeu_ptmul descriptor type
1521 bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type
1522 bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type
1523
1524 ..and so on and so forth.
1525
1526 Example:
1527
1528 /* MPC8548E */
1529 crypto@30000 {
1530 device_type = "crypto";
1531 model = "SEC2";
1532 compatible = "talitos";
1533 reg = <30000 10000>;
1534 interrupts = <1d 3>;
1535 interrupt-parent = <40000>;
1536 num-channels = <4>;
1537 channel-fifo-len = <18>;
1538 exec-units-mask = <000000fe>;
1539 descriptor-types-mask = <012b0ebf>;
1540 };
1541
1542 h) Board Control and Status (BCSR)
1543
1544 Required properties:
1545
1546 - device_type : Should be "board-control"
1547 - reg : Offset and length of the register set for the device
1548
1549 Example:
1550
1551 bcsr@f8000000 {
1552 device_type = "board-control";
1553 reg = <f8000000 8000>;
1554 };
1555
1556 i) Freescale QUICC Engine module (QE)
1557 This represents qe module that is installed on PowerQUICC II Pro.
1558
1559 NOTE: This is an interim binding; it should be updated to fit
1560 in with the CPM binding later in this document.
1561
1562 Basically, it is a bus of devices, that could act more or less
1563 as a complete entity (UCC, USB etc ). All of them should be siblings on
1564 the "root" qe node, using the common properties from there.
1565 The description below applies to the qe of MPC8360 and
1566 more nodes and properties would be extended in the future.
1567
1568 i) Root QE device
1569
1570 Required properties:
1571 - compatible : should be "fsl,qe";
1572 - model : precise model of the QE, Can be "QE", "CPM", or "CPM2"
1573 - reg : offset and length of the device registers.
1574 - bus-frequency : the clock frequency for QUICC Engine.
1575
1576 Recommended properties
1577 - brg-frequency : the internal clock source frequency for baud-rate
1578 generators in Hz.
1579
1580 Example:
1581 qe@e0100000 {
1582 #address-cells = <1>;
1583 #size-cells = <1>;
1584 #interrupt-cells = <2>;
1585 compatible = "fsl,qe";
1586 ranges = <0 e0100000 00100000>;
1587 reg = <e0100000 480>;
1588 brg-frequency = <0>;
1589 bus-frequency = <179A7B00>;
1590 }
1591
1592
1593 ii) SPI (Serial Peripheral Interface)
1594
1595 Required properties:
1596 - cell-index : SPI controller index.
1597 - compatible : should be "fsl,spi".
1598 - mode : the SPI operation mode, it can be "cpu" or "cpu-qe".
1599 - reg : Offset and length of the register set for the device
1600 - interrupts : <a b> where a is the interrupt number and b is a
1601 field that represents an encoding of the sense and level
1602 information for the interrupt. This should be encoded based on
1603 the information in section 2) depending on the type of interrupt
1604 controller you have.
1605 - interrupt-parent : the phandle for the interrupt controller that
1606 services interrupts for this device.
1607
1608 Example:
1609 spi@4c0 {
1610 cell-index = <0>;
1611 compatible = "fsl,spi";
1612 reg = <4c0 40>;
1613 interrupts = <82 0>;
1614 interrupt-parent = <700>;
1615 mode = "cpu";
1616 };
1617
1618
1619 iii) USB (Universal Serial Bus Controller)
1620
1621 Required properties:
1622 - compatible : could be "qe_udc" or "fhci-hcd".
1623 - mode : the could be "host" or "slave".
1624 - reg : Offset and length of the register set for the device
1625 - interrupts : <a b> where a is the interrupt number and b is a
1626 field that represents an encoding of the sense and level
1627 information for the interrupt. This should be encoded based on
1628 the information in section 2) depending on the type of interrupt
1629 controller you have.
1630 - interrupt-parent : the phandle for the interrupt controller that
1631 services interrupts for this device.
1632
1633 Example(slave):
1634 usb@6c0 {
1635 compatible = "qe_udc";
1636 reg = <6c0 40>;
1637 interrupts = <8b 0>;
1638 interrupt-parent = <700>;
1639 mode = "slave";
1640 };
1641
1642
1643 iv) UCC (Unified Communications Controllers)
1644
1645 Required properties:
1646 - device_type : should be "network", "hldc", "uart", "transparent"
1647 "bisync", "atm", or "serial".
1648 - compatible : could be "ucc_geth" or "fsl_atm" and so on.
1649 - cell-index : the ucc number(1-8), corresponding to UCCx in UM.
1650 - reg : Offset and length of the register set for the device
1651 - interrupts : <a b> where a is the interrupt number and b is a
1652 field that represents an encoding of the sense and level
1653 information for the interrupt. This should be encoded based on
1654 the information in section 2) depending on the type of interrupt
1655 controller you have.
1656 - interrupt-parent : the phandle for the interrupt controller that
1657 services interrupts for this device.
1658 - pio-handle : The phandle for the Parallel I/O port configuration.
1659 - port-number : for UART drivers, the port number to use, between 0 and 3.
1660 This usually corresponds to the /dev/ttyQE device, e.g. <0> = /dev/ttyQE0.
1661 The port number is added to the minor number of the device. Unlike the
1662 CPM UART driver, the port-number is required for the QE UART driver.
1663 - soft-uart : for UART drivers, if specified this means the QE UART device
1664 driver should use "Soft-UART" mode, which is needed on some SOCs that have
1665 broken UART hardware. Soft-UART is provided via a microcode upload.
1666 - rx-clock-name: the UCC receive clock source
1667 "none": clock source is disabled
1668 "brg1" through "brg16": clock source is BRG1-BRG16, respectively
1669 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
1670 - tx-clock-name: the UCC transmit clock source
1671 "none": clock source is disabled
1672 "brg1" through "brg16": clock source is BRG1-BRG16, respectively
1673 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
1674 The following two properties are deprecated. rx-clock has been replaced
1675 with rx-clock-name, and tx-clock has been replaced with tx-clock-name.
1676 Drivers that currently use the deprecated properties should continue to
1677 do so, in order to support older device trees, but they should be updated
1678 to check for the new properties first.
1679 - rx-clock : represents the UCC receive clock source.
1680 0x00 : clock source is disabled;
1681 0x1~0x10 : clock source is BRG1~BRG16 respectively;
1682 0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
1683 - tx-clock: represents the UCC transmit clock source;
1684 0x00 : clock source is disabled;
1685 0x1~0x10 : clock source is BRG1~BRG16 respectively;
1686 0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
1687
1688 Required properties for network device_type:
1689 - mac-address : list of bytes representing the ethernet address.
1690 - phy-handle : The phandle for the PHY connected to this controller.
1691
1692 Recommended properties:
1693 - phy-connection-type : a string naming the controller/PHY interface type,
1694 i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id" (Internal
1695 Delay), "rgmii-txid" (delay on TX only), "rgmii-rxid" (delay on RX only),
1696 "tbi", or "rtbi".
1697
1698 Example:
1699 ucc@2000 {
1700 device_type = "network";
1701 compatible = "ucc_geth";
1702 cell-index = <1>;
1703 reg = <2000 200>;
1704 interrupts = <a0 0>;
1705 interrupt-parent = <700>;
1706 mac-address = [ 00 04 9f 00 23 23 ];
1707 rx-clock = "none";
1708 tx-clock = "clk9";
1709 phy-handle = <212000>;
1710 phy-connection-type = "gmii";
1711 pio-handle = <140001>;
1712 };
1713
1714
1715 v) Parallel I/O Ports
1716
1717 This node configures Parallel I/O ports for CPUs with QE support.
1718 The node should reside in the "soc" node of the tree. For each
1719 device that using parallel I/O ports, a child node should be created.
1720 See the definition of the Pin configuration nodes below for more
1721 information.
1722
1723 Required properties:
1724 - device_type : should be "par_io".
1725 - reg : offset to the register set and its length.
1726 - num-ports : number of Parallel I/O ports
1727
1728 Example:
1729 par_io@1400 {
1730 reg = <1400 100>;
1731 #address-cells = <1>;
1732 #size-cells = <0>;
1733 device_type = "par_io";
1734 num-ports = <7>;
1735 ucc_pin@01 {
1736 ......
1737 };
1738
1739
1740 vi) Pin configuration nodes
1741
1742 Required properties:
1743 - linux,phandle : phandle of this node; likely referenced by a QE
1744 device.
1745 - pio-map : array of pin configurations. Each pin is defined by 6
1746 integers. The six numbers are respectively: port, pin, dir,
1747 open_drain, assignment, has_irq.
1748 - port : port number of the pin; 0-6 represent port A-G in UM.
1749 - pin : pin number in the port.
1750 - dir : direction of the pin, should encode as follows:
1751
1752 0 = The pin is disabled
1753 1 = The pin is an output
1754 2 = The pin is an input
1755 3 = The pin is I/O
1756
1757 - open_drain : indicates the pin is normal or wired-OR:
1758
1759 0 = The pin is actively driven as an output
1760 1 = The pin is an open-drain driver. As an output, the pin is
1761 driven active-low, otherwise it is three-stated.
1762
1763 - assignment : function number of the pin according to the Pin Assignment
1764 tables in User Manual. Each pin can have up to 4 possible functions in
1765 QE and two options for CPM.
1766 - has_irq : indicates if the pin is used as source of external
1767 interrupts.
1768
1769 Example:
1770 ucc_pin@01 {
1771 linux,phandle = <140001>;
1772 pio-map = <
1773 /* port pin dir open_drain assignment has_irq */
1774 0 3 1 0 1 0 /* TxD0 */
1775 0 4 1 0 1 0 /* TxD1 */
1776 0 5 1 0 1 0 /* TxD2 */
1777 0 6 1 0 1 0 /* TxD3 */
1778 1 6 1 0 3 0 /* TxD4 */
1779 1 7 1 0 1 0 /* TxD5 */
1780 1 9 1 0 2 0 /* TxD6 */
1781 1 a 1 0 2 0 /* TxD7 */
1782 0 9 2 0 1 0 /* RxD0 */
1783 0 a 2 0 1 0 /* RxD1 */
1784 0 b 2 0 1 0 /* RxD2 */
1785 0 c 2 0 1 0 /* RxD3 */
1786 0 d 2 0 1 0 /* RxD4 */
1787 1 1 2 0 2 0 /* RxD5 */
1788 1 0 2 0 2 0 /* RxD6 */
1789 1 4 2 0 2 0 /* RxD7 */
1790 0 7 1 0 1 0 /* TX_EN */
1791 0 8 1 0 1 0 /* TX_ER */
1792 0 f 2 0 1 0 /* RX_DV */
1793 0 10 2 0 1 0 /* RX_ER */
1794 0 0 2 0 1 0 /* RX_CLK */
1795 2 9 1 0 3 0 /* GTX_CLK - CLK10 */
1796 2 8 2 0 1 0>; /* GTX125 - CLK9 */
1797 };
1798
1799 vii) Multi-User RAM (MURAM)
1800
1801 Required properties:
1802 - compatible : should be "fsl,qe-muram", "fsl,cpm-muram".
1803 - mode : the could be "host" or "slave".
1804 - ranges : Should be defined as specified in 1) to describe the
1805 translation of MURAM addresses.
1806 - data-only : sub-node which defines the address area under MURAM
1807 bus that can be allocated as data/parameter
1808
1809 Example:
1810
1811 muram@10000 {
1812 compatible = "fsl,qe-muram", "fsl,cpm-muram";
1813 ranges = <0 00010000 0000c000>;
1814
1815 data-only@0{
1816 compatible = "fsl,qe-muram-data",
1817 "fsl,cpm-muram-data";
1818 reg = <0 c000>;
1819 };
1820 };
1821
1822 viii) Uploaded QE firmware
1823
1824 If a new firwmare has been uploaded to the QE (usually by the
1825 boot loader), then a 'firmware' child node should be added to the QE
1826 node. This node provides information on the uploaded firmware that
1827 device drivers may need.
1828
1829 Required properties:
1830 - id: The string name of the firmware. This is taken from the 'id'
1831 member of the qe_firmware structure of the uploaded firmware.
1832 Device drivers can search this string to determine if the
1833 firmware they want is already present.
1834 - extended-modes: The Extended Modes bitfield, taken from the
1835 firmware binary. It is a 64-bit number represented
1836 as an array of two 32-bit numbers.
1837 - virtual-traps: The virtual traps, taken from the firmware binary.
1838 It is an array of 8 32-bit numbers.
1839
1840 Example:
1841
1842 firmware {
1843 id = "Soft-UART";
1844 extended-modes = <0 0>;
1845 virtual-traps = <0 0 0 0 0 0 0 0>;
1846 }
1847
1848 j) CFI or JEDEC memory-mapped NOR flash
1849 1299
1850 Flash chips (Memory Technology Devices) are often used for solid state 1300 Flash chips (Memory Technology Devices) are often used for solid state
1851 file systems on embedded devices. 1301 file systems on embedded devices.
@@ -1909,268 +1359,7 @@ platforms are moved over to use the flattened-device-tree model.
1909 }; 1359 };
1910 }; 1360 };
1911 1361
1912 k) Global Utilities Block 1362 d) 4xx/Axon EMAC ethernet nodes
1913
1914 The global utilities block controls power management, I/O device
1915 enabling, power-on-reset configuration monitoring, general-purpose
1916 I/O signal configuration, alternate function selection for multiplexed
1917 signals, and clock control.
1918
1919 Required properties:
1920
1921 - compatible : Should define the compatible device type for
1922 global-utilities.
1923 - reg : Offset and length of the register set for the device.
1924
1925 Recommended properties:
1926
1927 - fsl,has-rstcr : Indicates that the global utilities register set
1928 contains a functioning "reset control register" (i.e. the board
1929 is wired to reset upon setting the HRESET_REQ bit in this register).
1930
1931 Example:
1932
1933 global-utilities@e0000 { /* global utilities block */
1934 compatible = "fsl,mpc8548-guts";
1935 reg = <e0000 1000>;
1936 fsl,has-rstcr;
1937 };
1938
1939 l) Freescale Communications Processor Module
1940
1941 NOTE: This is an interim binding, and will likely change slightly,
1942 as more devices are supported. The QE bindings especially are
1943 incomplete.
1944
1945 i) Root CPM node
1946
1947 Properties:
1948 - compatible : "fsl,cpm1", "fsl,cpm2", or "fsl,qe".
1949 - reg : A 48-byte region beginning with CPCR.
1950
1951 Example:
1952 cpm@119c0 {
1953 #address-cells = <1>;
1954 #size-cells = <1>;
1955 #interrupt-cells = <2>;
1956 compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
1957 reg = <119c0 30>;
1958 }
1959
1960 ii) Properties common to mulitple CPM/QE devices
1961
1962 - fsl,cpm-command : This value is ORed with the opcode and command flag
1963 to specify the device on which a CPM command operates.
1964
1965 - fsl,cpm-brg : Indicates which baud rate generator the device
1966 is associated with. If absent, an unused BRG
1967 should be dynamically allocated. If zero, the
1968 device uses an external clock rather than a BRG.
1969
1970 - reg : Unless otherwise specified, the first resource represents the
1971 scc/fcc/ucc registers, and the second represents the device's
1972 parameter RAM region (if it has one).
1973
1974 iii) Serial
1975
1976 Currently defined compatibles:
1977 - fsl,cpm1-smc-uart
1978 - fsl,cpm2-smc-uart
1979 - fsl,cpm1-scc-uart
1980 - fsl,cpm2-scc-uart
1981 - fsl,qe-uart
1982
1983 Example:
1984
1985 serial@11a00 {
1986 device_type = "serial";
1987 compatible = "fsl,mpc8272-scc-uart",
1988 "fsl,cpm2-scc-uart";
1989 reg = <11a00 20 8000 100>;
1990 interrupts = <28 8>;
1991 interrupt-parent = <&PIC>;
1992 fsl,cpm-brg = <1>;
1993 fsl,cpm-command = <00800000>;
1994 };
1995
1996 iii) Network
1997
1998 Currently defined compatibles:
1999 - fsl,cpm1-scc-enet
2000 - fsl,cpm2-scc-enet
2001 - fsl,cpm1-fec-enet
2002 - fsl,cpm2-fcc-enet (third resource is GFEMR)
2003 - fsl,qe-enet
2004
2005 Example:
2006
2007 ethernet@11300 {
2008 device_type = "network";
2009 compatible = "fsl,mpc8272-fcc-enet",
2010 "fsl,cpm2-fcc-enet";
2011 reg = <11300 20 8400 100 11390 1>;
2012 local-mac-address = [ 00 00 00 00 00 00 ];
2013 interrupts = <20 8>;
2014 interrupt-parent = <&PIC>;
2015 phy-handle = <&PHY0>;
2016 fsl,cpm-command = <12000300>;
2017 };
2018
2019 iv) MDIO
2020
2021 Currently defined compatibles:
2022 fsl,pq1-fec-mdio (reg is same as first resource of FEC device)
2023 fsl,cpm2-mdio-bitbang (reg is port C registers)
2024
2025 Properties for fsl,cpm2-mdio-bitbang:
2026 fsl,mdio-pin : pin of port C controlling mdio data
2027 fsl,mdc-pin : pin of port C controlling mdio clock
2028
2029 Example:
2030
2031 mdio@10d40 {
2032 device_type = "mdio";
2033 compatible = "fsl,mpc8272ads-mdio-bitbang",
2034 "fsl,mpc8272-mdio-bitbang",
2035 "fsl,cpm2-mdio-bitbang";
2036 reg = <10d40 14>;
2037 #address-cells = <1>;
2038 #size-cells = <0>;
2039 fsl,mdio-pin = <12>;
2040 fsl,mdc-pin = <13>;
2041 };
2042
2043 v) Baud Rate Generators
2044
2045 Currently defined compatibles:
2046 fsl,cpm-brg
2047 fsl,cpm1-brg
2048 fsl,cpm2-brg
2049
2050 Properties:
2051 - reg : There may be an arbitrary number of reg resources; BRG
2052 numbers are assigned to these in order.
2053 - clock-frequency : Specifies the base frequency driving
2054 the BRG.
2055
2056 Example:
2057
2058 brg@119f0 {
2059 compatible = "fsl,mpc8272-brg",
2060 "fsl,cpm2-brg",
2061 "fsl,cpm-brg";
2062 reg = <119f0 10 115f0 10>;
2063 clock-frequency = <d#25000000>;
2064 };
2065
2066 vi) Interrupt Controllers
2067
2068 Currently defined compatibles:
2069 - fsl,cpm1-pic
2070 - only one interrupt cell
2071 - fsl,pq1-pic
2072 - fsl,cpm2-pic
2073 - second interrupt cell is level/sense:
2074 - 2 is falling edge
2075 - 8 is active low
2076
2077 Example:
2078
2079 interrupt-controller@10c00 {
2080 #interrupt-cells = <2>;
2081 interrupt-controller;
2082 reg = <10c00 80>;
2083 compatible = "mpc8272-pic", "fsl,cpm2-pic";
2084 };
2085
2086 vii) USB (Universal Serial Bus Controller)
2087
2088 Properties:
2089 - compatible : "fsl,cpm1-usb", "fsl,cpm2-usb", "fsl,qe-usb"
2090
2091 Example:
2092 usb@11bc0 {
2093 #address-cells = <1>;
2094 #size-cells = <0>;
2095 compatible = "fsl,cpm2-usb";
2096 reg = <11b60 18 8b00 100>;
2097 interrupts = <b 8>;
2098 interrupt-parent = <&PIC>;
2099 fsl,cpm-command = <2e600000>;
2100 };
2101
2102 viii) Multi-User RAM (MURAM)
2103
2104 The multi-user/dual-ported RAM is expressed as a bus under the CPM node.
2105
2106 Ranges must be set up subject to the following restrictions:
2107
2108 - Children's reg nodes must be offsets from the start of all muram, even
2109 if the user-data area does not begin at zero.
2110 - If multiple range entries are used, the difference between the parent
2111 address and the child address must be the same in all, so that a single
2112 mapping can cover them all while maintaining the ability to determine
2113 CPM-side offsets with pointer subtraction. It is recommended that
2114 multiple range entries not be used.
2115 - A child address of zero must be translatable, even if no reg resources
2116 contain it.
2117
2118 A child "data" node must exist, compatible with "fsl,cpm-muram-data", to
2119 indicate the portion of muram that is usable by the OS for arbitrary
2120 purposes. The data node may have an arbitrary number of reg resources,
2121 all of which contribute to the allocatable muram pool.
2122
2123 Example, based on mpc8272:
2124
2125 muram@0 {
2126 #address-cells = <1>;
2127 #size-cells = <1>;
2128 ranges = <0 0 10000>;
2129
2130 data@0 {
2131 compatible = "fsl,cpm-muram-data";
2132 reg = <0 2000 9800 800>;
2133 };
2134 };
2135
2136 m) Chipselect/Local Bus
2137
2138 Properties:
2139 - name : Should be localbus
2140 - #address-cells : Should be either two or three. The first cell is the
2141 chipselect number, and the remaining cells are the
2142 offset into the chipselect.
2143 - #size-cells : Either one or two, depending on how large each chipselect
2144 can be.
2145 - ranges : Each range corresponds to a single chipselect, and cover
2146 the entire access window as configured.
2147
2148 Example:
2149 localbus@f0010100 {
2150 compatible = "fsl,mpc8272-localbus",
2151 "fsl,pq2-localbus";
2152 #address-cells = <2>;
2153 #size-cells = <1>;
2154 reg = <f0010100 40>;
2155
2156 ranges = <0 0 fe000000 02000000
2157 1 0 f4500000 00008000>;
2158
2159 flash@0,0 {
2160 compatible = "jedec-flash";
2161 reg = <0 0 2000000>;
2162 bank-width = <4>;
2163 device-width = <1>;
2164 };
2165
2166 board-control@1,0 {
2167 reg = <1 0 20>;
2168 compatible = "fsl,mpc8272ads-bcsr";
2169 };
2170 };
2171
2172
2173 n) 4xx/Axon EMAC ethernet nodes
2174 1363
2175 The EMAC ethernet controller in IBM and AMCC 4xx chips, and also 1364 The EMAC ethernet controller in IBM and AMCC 4xx chips, and also
2176 the Axon bridge. To operate this needs to interact with a ths 1365 the Axon bridge. To operate this needs to interact with a ths
@@ -2318,7 +1507,7 @@ platforms are moved over to use the flattened-device-tree model.
2318 available. 1507 available.
2319 For Axon: 0x0000012a 1508 For Axon: 0x0000012a
2320 1509
2321 o) Xilinx IP cores 1510 e) Xilinx IP cores
2322 1511
2323 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use 1512 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
2324 in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range 1513 in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range
@@ -2612,206 +1801,7 @@ platforms are moved over to use the flattened-device-tree model.
2612 - reg-offset : A value of 3 is required 1801 - reg-offset : A value of 3 is required
2613 - reg-shift : A value of 2 is required 1802 - reg-shift : A value of 2 is required
2614 1803
2615 1804 f) USB EHCI controllers
2616 p) Freescale Synchronous Serial Interface
2617
2618 The SSI is a serial device that communicates with audio codecs. It can
2619 be programmed in AC97, I2S, left-justified, or right-justified modes.
2620
2621 Required properties:
2622 - compatible : compatible list, containing "fsl,ssi"
2623 - cell-index : the SSI, <0> = SSI1, <1> = SSI2, and so on
2624 - reg : offset and length of the register set for the device
2625 - interrupts : <a b> where a is the interrupt number and b is a
2626 field that represents an encoding of the sense and
2627 level information for the interrupt. This should be
2628 encoded based on the information in section 2)
2629 depending on the type of interrupt controller you
2630 have.
2631 - interrupt-parent : the phandle for the interrupt controller that
2632 services interrupts for this device.
2633 - fsl,mode : the operating mode for the SSI interface
2634 "i2s-slave" - I2S mode, SSI is clock slave
2635 "i2s-master" - I2S mode, SSI is clock master
2636 "lj-slave" - left-justified mode, SSI is clock slave
2637 "lj-master" - l.j. mode, SSI is clock master
2638 "rj-slave" - right-justified mode, SSI is clock slave
2639 "rj-master" - r.j., SSI is clock master
2640 "ac97-slave" - AC97 mode, SSI is clock slave
2641 "ac97-master" - AC97 mode, SSI is clock master
2642
2643 Optional properties:
2644 - codec-handle : phandle to a 'codec' node that defines an audio
2645 codec connected to this SSI. This node is typically
2646 a child of an I2C or other control node.
2647
2648 Child 'codec' node required properties:
2649 - compatible : compatible list, contains the name of the codec
2650
2651 Child 'codec' node optional properties:
2652 - clock-frequency : The frequency of the input clock, which typically
2653 comes from an on-board dedicated oscillator.
2654
2655 * Freescale 83xx DMA Controller
2656
2657 Freescale PowerPC 83xx have on chip general purpose DMA controllers.
2658
2659 Required properties:
2660
2661 - compatible : compatible list, contains 2 entries, first is
2662 "fsl,CHIP-dma", where CHIP is the processor
2663 (mpc8349, mpc8360, etc.) and the second is
2664 "fsl,elo-dma"
2665 - reg : <registers mapping for DMA general status reg>
2666 - ranges : Should be defined as specified in 1) to describe the
2667 DMA controller channels.
2668 - cell-index : controller index. 0 for controller @ 0x8100
2669 - interrupts : <interrupt mapping for DMA IRQ>
2670 - interrupt-parent : optional, if needed for interrupt mapping
2671
2672
2673 - DMA channel nodes:
2674 - compatible : compatible list, contains 2 entries, first is
2675 "fsl,CHIP-dma-channel", where CHIP is the processor
2676 (mpc8349, mpc8350, etc.) and the second is
2677 "fsl,elo-dma-channel"
2678 - reg : <registers mapping for channel>
2679 - cell-index : dma channel index starts at 0.
2680
2681 Optional properties:
2682 - interrupts : <interrupt mapping for DMA channel IRQ>
2683 (on 83xx this is expected to be identical to
2684 the interrupts property of the parent node)
2685 - interrupt-parent : optional, if needed for interrupt mapping
2686
2687 Example:
2688 dma@82a8 {
2689 #address-cells = <1>;
2690 #size-cells = <1>;
2691 compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
2692 reg = <82a8 4>;
2693 ranges = <0 8100 1a4>;
2694 interrupt-parent = <&ipic>;
2695 interrupts = <47 8>;
2696 cell-index = <0>;
2697 dma-channel@0 {
2698 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
2699 cell-index = <0>;
2700 reg = <0 80>;
2701 };
2702 dma-channel@80 {
2703 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
2704 cell-index = <1>;
2705 reg = <80 80>;
2706 };
2707 dma-channel@100 {
2708 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
2709 cell-index = <2>;
2710 reg = <100 80>;
2711 };
2712 dma-channel@180 {
2713 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
2714 cell-index = <3>;
2715 reg = <180 80>;
2716 };
2717 };
2718
2719 * Freescale 85xx/86xx DMA Controller
2720
2721 Freescale PowerPC 85xx/86xx have on chip general purpose DMA controllers.
2722
2723 Required properties:
2724
2725 - compatible : compatible list, contains 2 entries, first is
2726 "fsl,CHIP-dma", where CHIP is the processor
2727 (mpc8540, mpc8540, etc.) and the second is
2728 "fsl,eloplus-dma"
2729 - reg : <registers mapping for DMA general status reg>
2730 - cell-index : controller index. 0 for controller @ 0x21000,
2731 1 for controller @ 0xc000
2732 - ranges : Should be defined as specified in 1) to describe the
2733 DMA controller channels.
2734
2735 - DMA channel nodes:
2736 - compatible : compatible list, contains 2 entries, first is
2737 "fsl,CHIP-dma-channel", where CHIP is the processor
2738 (mpc8540, mpc8560, etc.) and the second is
2739 "fsl,eloplus-dma-channel"
2740 - cell-index : dma channel index starts at 0.
2741 - reg : <registers mapping for channel>
2742 - interrupts : <interrupt mapping for DMA channel IRQ>
2743 - interrupt-parent : optional, if needed for interrupt mapping
2744
2745 Example:
2746 dma@21300 {
2747 #address-cells = <1>;
2748 #size-cells = <1>;
2749 compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
2750 reg = <21300 4>;
2751 ranges = <0 21100 200>;
2752 cell-index = <0>;
2753 dma-channel@0 {
2754 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
2755 reg = <0 80>;
2756 cell-index = <0>;
2757 interrupt-parent = <&mpic>;
2758 interrupts = <14 2>;
2759 };
2760 dma-channel@80 {
2761 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
2762 reg = <80 80>;
2763 cell-index = <1>;
2764 interrupt-parent = <&mpic>;
2765 interrupts = <15 2>;
2766 };
2767 dma-channel@100 {
2768 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
2769 reg = <100 80>;
2770 cell-index = <2>;
2771 interrupt-parent = <&mpic>;
2772 interrupts = <16 2>;
2773 };
2774 dma-channel@180 {
2775 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
2776 reg = <180 80>;
2777 cell-index = <3>;
2778 interrupt-parent = <&mpic>;
2779 interrupts = <17 2>;
2780 };
2781 };
2782
2783 * Freescale 8xxx/3.0 Gb/s SATA nodes
2784
2785 SATA nodes are defined to describe on-chip Serial ATA controllers.
2786 Each SATA port should have its own node.
2787
2788 Required properties:
2789 - compatible : compatible list, contains 2 entries, first is
2790 "fsl,CHIP-sata", where CHIP is the processor
2791 (mpc8315, mpc8379, etc.) and the second is
2792 "fsl,pq-sata"
2793 - interrupts : <interrupt mapping for SATA IRQ>
2794 - cell-index : controller index.
2795 1 for controller @ 0x18000
2796 2 for controller @ 0x19000
2797 3 for controller @ 0x1a000
2798 4 for controller @ 0x1b000
2799
2800 Optional properties:
2801 - interrupt-parent : optional, if needed for interrupt mapping
2802 - reg : <registers mapping>
2803
2804 Example:
2805
2806 sata@18000 {
2807 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
2808 reg = <0x18000 0x1000>;
2809 cell-index = <1>;
2810 interrupts = <2c 8>;
2811 interrupt-parent = < &ipic >;
2812 };
2813
2814 q) USB EHCI controllers
2815 1805
2816 Required properties: 1806 Required properties:
2817 - compatible : should be "usb-ehci". 1807 - compatible : should be "usb-ehci".
@@ -3643,14 +2633,11 @@ not necessary as they are usually the same as the root node.
3643 2633
3644 pic@40000 { 2634 pic@40000 {
3645 linux,phandle = <40000>; 2635 linux,phandle = <40000>;
3646 clock-frequency = <0>;
3647 interrupt-controller; 2636 interrupt-controller;
3648 #address-cells = <0>; 2637 #address-cells = <0>;
3649 reg = <40000 40000>; 2638 reg = <40000 40000>;
3650 built-in;
3651 compatible = "chrp,open-pic"; 2639 compatible = "chrp,open-pic";
3652 device_type = "open-pic"; 2640 device_type = "open-pic";
3653 big-endian;
3654 }; 2641 };
3655 2642
3656 i2c@3000 { 2643 i2c@3000 {
diff --git a/Documentation/powerpc/bootwrapper.txt b/Documentation/powerpc/bootwrapper.txt
new file mode 100644
index 00000000000..d60fced5e1c
--- /dev/null
+++ b/Documentation/powerpc/bootwrapper.txt
@@ -0,0 +1,141 @@
1The PowerPC boot wrapper
2------------------------
3Copyright (C) Secret Lab Technologies Ltd.
4
5PowerPC image targets compresses and wraps the kernel image (vmlinux) with
6a boot wrapper to make it usable by the system firmware. There is no
7standard PowerPC firmware interface, so the boot wrapper is designed to
8be adaptable for each kind of image that needs to be built.
9
10The boot wrapper can be found in the arch/powerpc/boot/ directory. The
11Makefile in that directory has targets for all the available image types.
12The different image types are used to support all of the various firmware
13interfaces found on PowerPC platforms. OpenFirmware is the most commonly
14used firmware type on general purpose PowerPC systems from Apple, IBM and
15others. U-Boot is typically found on embedded PowerPC hardware, but there
16are a handful of other firmware implementations which are also popular. Each
17firmware interface requires a different image format.
18
19The boot wrapper is built from the makefile in arch/powerpc/boot/Makefile and
20it uses the wrapper script (arch/powerpc/boot/wrapper) to generate target
21image. The details of the build system is discussed in the next section.
22Currently, the following image format targets exist:
23
24 cuImage.%: Backwards compatible uImage for older version of
25 U-Boot (for versions that don't understand the device
26 tree). This image embeds a device tree blob inside
27 the image. The boot wrapper, kernel and device tree
28 are all embedded inside the U-Boot uImage file format
29 with boot wrapper code that extracts data from the old
30 bd_info structure and loads the data into the device
31 tree before jumping into the kernel.
32 Because of the series of #ifdefs found in the
33 bd_info structure used in the old U-Boot interfaces,
34 cuImages are platform specific. Each specific
35 U-Boot platform has a different platform init file
36 which populates the embedded device tree with data
37 from the platform specific bd_info file. The platform
38 specific cuImage platform init code can be found in
39 arch/powerpc/boot/cuboot.*.c. Selection of the correct
40 cuImage init code for a specific board can be found in
41 the wrapper structure.
42 dtbImage.%: Similar to zImage, except device tree blob is embedded
43 inside the image instead of provided by firmware. The
44 output image file can be either an elf file or a flat
45 binary depending on the platform.
46 dtbImages are used on systems which do not have an
47 interface for passing a device tree directly.
48 dtbImages are similar to simpleImages except that
49 dtbImages have platform specific code for extracting
50 data from the board firmware, but simpleImages do not
51 talk to the firmware at all.
52 PlayStation 3 support uses dtbImage. So do Embedded
53 Planet boards using the PlanetCore firmware. Board
54 specific initialization code is typically found in a
55 file named arch/powerpc/boot/<platform>.c; but this
56 can be overridden by the wrapper script.
57 simpleImage.%: Firmware independent compressed image that does not
58 depend on any particular firmware interface and embeds
59 a device tree blob. This image is a flat binary that
60 can be loaded to any location in RAM and jumped to.
61 Firmware cannot pass any configuration data to the
62 kernel with this image type and it depends entirely on
63 the embedded device tree for all information.
64 The simpleImage is useful for booting systems with
65 an unknown firmware interface or for booting from
66 a debugger when no firmware is present (such as on
67 the Xilinx Virtex platform). The only assumption that
68 simpleImage makes is that RAM is correctly initialized
69 and that the MMU is either off or has RAM mapped to
70 base address 0.
71 simpleImage also supports inserting special platform
72 specific initialization code to the start of the bootup
73 sequence. The virtex405 platform uses this feature to
74 ensure that the cache is invalidated before caching
75 is enabled. Platform specific initialization code is
76 added as part of the wrapper script and is keyed on
77 the image target name. For example, all
78 simpleImage.virtex405-* targets will add the
79 virtex405-head.S initialization code (This also means
80 that the dts file for virtex405 targets should be
81 named (virtex405-<board>.dts). Search the wrapper
82 script for 'virtex405' and see the file
83 arch/powerpc/boot/virtex405-head.S for details.
84 treeImage.%; Image format for used with OpenBIOS firmware found
85 on some ppc4xx hardware. This image embeds a device
86 tree blob inside the image.
87 uImage: Native image format used by U-Boot. The uImage target
88 does not add any boot code. It just wraps a compressed
89 vmlinux in the uImage data structure. This image
90 requires a version of U-Boot that is able to pass
91 a device tree to the kernel at boot. If using an older
92 version of U-Boot, then you need to use a cuImage
93 instead.
94 zImage.%: Image format which does not embed a device tree.
95 Used by OpenFirmware and other firmware interfaces
96 which are able to supply a device tree. This image
97 expects firmware to provide the device tree at boot.
98 Typically, if you have general purpose PowerPC
99 hardware then you want this image format.
100
101Image types which embed a device tree blob (simpleImage, dtbImage, treeImage,
102and cuImage) all generate the device tree blob from a file in the
103arch/powerpc/boot/dts/ directory. The Makefile selects the correct device
104tree source based on the name of the target. Therefore, if the kernel is
105built with 'make treeImage.walnut simpleImage.virtex405-ml403', then the
106build system will use arch/powerpc/boot/dts/walnut.dts to build
107treeImage.walnut and arch/powerpc/boot/dts/virtex405-ml403.dts to build
108the simpleImage.virtex405-ml403.
109
110Two special targets called 'zImage' and 'zImage.initrd' also exist. These
111targets build all the default images as selected by the kernel configuration.
112Default images are selected by the boot wrapper Makefile
113(arch/powerpc/boot/Makefile) by adding targets to the $image-y variable. Look
114at the Makefile to see which default image targets are available.
115
116How it is built
117---------------
118arch/powerpc is designed to support multiplatform kernels, which means
119that a single vmlinux image can be booted on many different target boards.
120It also means that the boot wrapper must be able to wrap for many kinds of
121images on a single build. The design decision was made to not use any
122conditional compilation code (#ifdef, etc) in the boot wrapper source code.
123All of the boot wrapper pieces are buildable at any time regardless of the
124kernel configuration. Building all the wrapper bits on every kernel build
125also ensures that obscure parts of the wrapper are at the very least compile
126tested in a large variety of environments.
127
128The wrapper is adapted for different image types at link time by linking in
129just the wrapper bits that are appropriate for the image type. The 'wrapper
130script' (found in arch/powerpc/boot/wrapper) is called by the Makefile and
131is responsible for selecting the correct wrapper bits for the image type.
132The arguments are well documented in the script's comment block, so they
133are not repeated here. However, it is worth mentioning that the script
134uses the -p (platform) argument as the main method of deciding which wrapper
135bits to compile in. Look for the large 'case "$platform" in' block in the
136middle of the script. This is also the place where platform specific fixups
137can be selected by changing the link order.
138
139In particular, care should be taken when working with cuImages. cuImage
140wrapper bits are very board specific and care should be taken to make sure
141the target you are trying to build is supported by the wrapper bits.
diff --git a/Documentation/powerpc/dts-bindings/fsl/board.txt b/Documentation/powerpc/dts-bindings/fsl/board.txt
new file mode 100644
index 00000000000..74ae6f1cd2d
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/board.txt
@@ -0,0 +1,29 @@
1* Board Control and Status (BCSR)
2
3Required properties:
4
5 - device_type : Should be "board-control"
6 - reg : Offset and length of the register set for the device
7
8Example:
9
10 bcsr@f8000000 {
11 device_type = "board-control";
12 reg = <f8000000 8000>;
13 };
14
15* Freescale on board FPGA
16
17This is the memory-mapped registers for on board FPGA.
18
19Required properities:
20- compatible : should be "fsl,fpga-pixis".
21- reg : should contain the address and the lenght of the FPPGA register
22 set.
23
24Example (MPC8610HPCD):
25
26 board-control@e8000000 {
27 compatible = "fsl,fpga-pixis";
28 reg = <0xe8000000 32>;
29 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm.txt
new file mode 100644
index 00000000000..088fc471e03
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm.txt
@@ -0,0 +1,67 @@
1* Freescale Communications Processor Module
2
3NOTE: This is an interim binding, and will likely change slightly,
4as more devices are supported. The QE bindings especially are
5incomplete.
6
7* Root CPM node
8
9Properties:
10- compatible : "fsl,cpm1", "fsl,cpm2", or "fsl,qe".
11- reg : A 48-byte region beginning with CPCR.
12
13Example:
14 cpm@119c0 {
15 #address-cells = <1>;
16 #size-cells = <1>;
17 #interrupt-cells = <2>;
18 compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
19 reg = <119c0 30>;
20 }
21
22* Properties common to mulitple CPM/QE devices
23
24- fsl,cpm-command : This value is ORed with the opcode and command flag
25 to specify the device on which a CPM command operates.
26
27- fsl,cpm-brg : Indicates which baud rate generator the device
28 is associated with. If absent, an unused BRG
29 should be dynamically allocated. If zero, the
30 device uses an external clock rather than a BRG.
31
32- reg : Unless otherwise specified, the first resource represents the
33 scc/fcc/ucc registers, and the second represents the device's
34 parameter RAM region (if it has one).
35
36* Multi-User RAM (MURAM)
37
38The multi-user/dual-ported RAM is expressed as a bus under the CPM node.
39
40Ranges must be set up subject to the following restrictions:
41
42- Children's reg nodes must be offsets from the start of all muram, even
43 if the user-data area does not begin at zero.
44- If multiple range entries are used, the difference between the parent
45 address and the child address must be the same in all, so that a single
46 mapping can cover them all while maintaining the ability to determine
47 CPM-side offsets with pointer subtraction. It is recommended that
48 multiple range entries not be used.
49- A child address of zero must be translatable, even if no reg resources
50 contain it.
51
52A child "data" node must exist, compatible with "fsl,cpm-muram-data", to
53indicate the portion of muram that is usable by the OS for arbitrary
54purposes. The data node may have an arbitrary number of reg resources,
55all of which contribute to the allocatable muram pool.
56
57Example, based on mpc8272:
58 muram@0 {
59 #address-cells = <1>;
60 #size-cells = <1>;
61 ranges = <0 0 10000>;
62
63 data@0 {
64 compatible = "fsl,cpm-muram-data";
65 reg = <0 2000 9800 800>;
66 };
67 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/brg.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/brg.txt
new file mode 100644
index 00000000000..4c7d45eaf02
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/brg.txt
@@ -0,0 +1,21 @@
1* Baud Rate Generators
2
3Currently defined compatibles:
4fsl,cpm-brg
5fsl,cpm1-brg
6fsl,cpm2-brg
7
8Properties:
9- reg : There may be an arbitrary number of reg resources; BRG
10 numbers are assigned to these in order.
11- clock-frequency : Specifies the base frequency driving
12 the BRG.
13
14Example:
15 brg@119f0 {
16 compatible = "fsl,mpc8272-brg",
17 "fsl,cpm2-brg",
18 "fsl,cpm-brg";
19 reg = <119f0 10 115f0 10>;
20 clock-frequency = <d#25000000>;
21 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/i2c.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/i2c.txt
new file mode 100644
index 00000000000..87bc6048667
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/i2c.txt
@@ -0,0 +1,41 @@
1* I2C
2
3The I2C controller is expressed as a bus under the CPM node.
4
5Properties:
6- compatible : "fsl,cpm1-i2c", "fsl,cpm2-i2c"
7- reg : On CPM2 devices, the second resource doesn't specify the I2C
8 Parameter RAM itself, but the I2C_BASE field of the CPM2 Parameter RAM
9 (typically 0x8afc 0x2).
10- #address-cells : Should be one. The cell is the i2c device address with
11 the r/w bit set to zero.
12- #size-cells : Should be zero.
13- clock-frequency : Can be used to set the i2c clock frequency. If
14 unspecified, a default frequency of 60kHz is being used.
15The following two properties are deprecated. They are only used by legacy
16i2c drivers to find the bus to probe:
17- linux,i2c-index : Can be used to hard code an i2c bus number. By default,
18 the bus number is dynamically assigned by the i2c core.
19- linux,i2c-class : Can be used to override the i2c class. The class is used
20 by legacy i2c device drivers to find a bus in a specific context like
21 system management, video or sound. By default, I2C_CLASS_HWMON (1) is
22 being used. The definition of the classes can be found in
23 include/i2c/i2c.h
24
25Example, based on mpc823:
26
27 i2c@860 {
28 compatible = "fsl,mpc823-i2c",
29 "fsl,cpm1-i2c";
30 reg = <0x860 0x20 0x3c80 0x30>;
31 interrupts = <16>;
32 interrupt-parent = <&CPM_PIC>;
33 fsl,cpm-command = <0x10>;
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 rtc@68 {
38 compatible = "dallas,ds1307";
39 reg = <0x68>;
40 };
41 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/pic.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/pic.txt
new file mode 100644
index 00000000000..8e3ee168161
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/pic.txt
@@ -0,0 +1,18 @@
1* Interrupt Controllers
2
3Currently defined compatibles:
4- fsl,cpm1-pic
5 - only one interrupt cell
6- fsl,pq1-pic
7- fsl,cpm2-pic
8 - second interrupt cell is level/sense:
9 - 2 is falling edge
10 - 8 is active low
11
12Example:
13 interrupt-controller@10c00 {
14 #interrupt-cells = <2>;
15 interrupt-controller;
16 reg = <10c00 80>;
17 compatible = "mpc8272-pic", "fsl,cpm2-pic";
18 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/usb.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/usb.txt
new file mode 100644
index 00000000000..74bfda4bb82
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/usb.txt
@@ -0,0 +1,15 @@
1* USB (Universal Serial Bus Controller)
2
3Properties:
4- compatible : "fsl,cpm1-usb", "fsl,cpm2-usb", "fsl,qe-usb"
5
6Example:
7 usb@11bc0 {
8 #address-cells = <1>;
9 #size-cells = <0>;
10 compatible = "fsl,cpm2-usb";
11 reg = <11b60 18 8b00 100>;
12 interrupts = <b 8>;
13 interrupt-parent = <&PIC>;
14 fsl,cpm-command = <2e600000>;
15 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/network.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/network.txt
new file mode 100644
index 00000000000..0e426944658
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/network.txt
@@ -0,0 +1,45 @@
1* Network
2
3Currently defined compatibles:
4- fsl,cpm1-scc-enet
5- fsl,cpm2-scc-enet
6- fsl,cpm1-fec-enet
7- fsl,cpm2-fcc-enet (third resource is GFEMR)
8- fsl,qe-enet
9
10Example:
11
12 ethernet@11300 {
13 device_type = "network";
14 compatible = "fsl,mpc8272-fcc-enet",
15 "fsl,cpm2-fcc-enet";
16 reg = <11300 20 8400 100 11390 1>;
17 local-mac-address = [ 00 00 00 00 00 00 ];
18 interrupts = <20 8>;
19 interrupt-parent = <&PIC>;
20 phy-handle = <&PHY0>;
21 fsl,cpm-command = <12000300>;
22 };
23
24* MDIO
25
26Currently defined compatibles:
27fsl,pq1-fec-mdio (reg is same as first resource of FEC device)
28fsl,cpm2-mdio-bitbang (reg is port C registers)
29
30Properties for fsl,cpm2-mdio-bitbang:
31fsl,mdio-pin : pin of port C controlling mdio data
32fsl,mdc-pin : pin of port C controlling mdio clock
33
34Example:
35 mdio@10d40 {
36 device_type = "mdio";
37 compatible = "fsl,mpc8272ads-mdio-bitbang",
38 "fsl,mpc8272-mdio-bitbang",
39 "fsl,cpm2-mdio-bitbang";
40 reg = <10d40 14>;
41 #address-cells = <1>;
42 #size-cells = <0>;
43 fsl,mdio-pin = <12>;
44 fsl,mdc-pin = <13>;
45 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt
new file mode 100644
index 00000000000..78790d58dc2
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt
@@ -0,0 +1,58 @@
1* Freescale QUICC Engine module (QE)
2This represents qe module that is installed on PowerQUICC II Pro.
3
4NOTE: This is an interim binding; it should be updated to fit
5in with the CPM binding later in this document.
6
7Basically, it is a bus of devices, that could act more or less
8as a complete entity (UCC, USB etc ). All of them should be siblings on
9the "root" qe node, using the common properties from there.
10The description below applies to the qe of MPC8360 and
11more nodes and properties would be extended in the future.
12
13i) Root QE device
14
15Required properties:
16- compatible : should be "fsl,qe";
17- model : precise model of the QE, Can be "QE", "CPM", or "CPM2"
18- reg : offset and length of the device registers.
19- bus-frequency : the clock frequency for QUICC Engine.
20
21Recommended properties
22- brg-frequency : the internal clock source frequency for baud-rate
23 generators in Hz.
24
25Example:
26 qe@e0100000 {
27 #address-cells = <1>;
28 #size-cells = <1>;
29 #interrupt-cells = <2>;
30 compatible = "fsl,qe";
31 ranges = <0 e0100000 00100000>;
32 reg = <e0100000 480>;
33 brg-frequency = <0>;
34 bus-frequency = <179A7B00>;
35 }
36
37* Multi-User RAM (MURAM)
38
39Required properties:
40- compatible : should be "fsl,qe-muram", "fsl,cpm-muram".
41- mode : the could be "host" or "slave".
42- ranges : Should be defined as specified in 1) to describe the
43 translation of MURAM addresses.
44- data-only : sub-node which defines the address area under MURAM
45 bus that can be allocated as data/parameter
46
47Example:
48
49 muram@10000 {
50 compatible = "fsl,qe-muram", "fsl,cpm-muram";
51 ranges = <0 00010000 0000c000>;
52
53 data-only@0{
54 compatible = "fsl,qe-muram-data",
55 "fsl,cpm-muram-data";
56 reg = <0 c000>;
57 };
58 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/firmware.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/firmware.txt
new file mode 100644
index 00000000000..6c238f59b2a
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/firmware.txt
@@ -0,0 +1,24 @@
1* Uploaded QE firmware
2
3 If a new firwmare has been uploaded to the QE (usually by the
4 boot loader), then a 'firmware' child node should be added to the QE
5 node. This node provides information on the uploaded firmware that
6 device drivers may need.
7
8 Required properties:
9 - id: The string name of the firmware. This is taken from the 'id'
10 member of the qe_firmware structure of the uploaded firmware.
11 Device drivers can search this string to determine if the
12 firmware they want is already present.
13 - extended-modes: The Extended Modes bitfield, taken from the
14 firmware binary. It is a 64-bit number represented
15 as an array of two 32-bit numbers.
16 - virtual-traps: The virtual traps, taken from the firmware binary.
17 It is an array of 8 32-bit numbers.
18
19Example:
20 firmware {
21 id = "Soft-UART";
22 extended-modes = <0 0>;
23 virtual-traps = <0 0 0 0 0 0 0 0>;
24 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/par_io.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/par_io.txt
new file mode 100644
index 00000000000..60984260207
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/par_io.txt
@@ -0,0 +1,51 @@
1* Parallel I/O Ports
2
3This node configures Parallel I/O ports for CPUs with QE support.
4The node should reside in the "soc" node of the tree. For each
5device that using parallel I/O ports, a child node should be created.
6See the definition of the Pin configuration nodes below for more
7information.
8
9Required properties:
10- device_type : should be "par_io".
11- reg : offset to the register set and its length.
12- num-ports : number of Parallel I/O ports
13
14Example:
15par_io@1400 {
16 reg = <1400 100>;
17 #address-cells = <1>;
18 #size-cells = <0>;
19 device_type = "par_io";
20 num-ports = <7>;
21 ucc_pin@01 {
22 ......
23 };
24
25Note that "par_io" nodes are obsolete, and should not be used for
26the new device trees. Instead, each Par I/O bank should be represented
27via its own gpio-controller node:
28
29Required properties:
30- #gpio-cells : should be "2".
31- compatible : should be "fsl,<chip>-qe-pario-bank",
32 "fsl,mpc8323-qe-pario-bank".
33- reg : offset to the register set and its length.
34- gpio-controller : node to identify gpio controllers.
35
36Example:
37 qe_pio_a: gpio-controller@1400 {
38 #gpio-cells = <2>;
39 compatible = "fsl,mpc8360-qe-pario-bank",
40 "fsl,mpc8323-qe-pario-bank";
41 reg = <0x1400 0x18>;
42 gpio-controller;
43 };
44
45 qe_pio_e: gpio-controller@1460 {
46 #gpio-cells = <2>;
47 compatible = "fsl,mpc8360-qe-pario-bank",
48 "fsl,mpc8323-qe-pario-bank";
49 reg = <0x1460 0x18>;
50 gpio-controller;
51 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/pincfg.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/pincfg.txt
new file mode 100644
index 00000000000..c5b43061db3
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/pincfg.txt
@@ -0,0 +1,60 @@
1* Pin configuration nodes
2
3Required properties:
4- linux,phandle : phandle of this node; likely referenced by a QE
5 device.
6- pio-map : array of pin configurations. Each pin is defined by 6
7 integers. The six numbers are respectively: port, pin, dir,
8 open_drain, assignment, has_irq.
9 - port : port number of the pin; 0-6 represent port A-G in UM.
10 - pin : pin number in the port.
11 - dir : direction of the pin, should encode as follows:
12
13 0 = The pin is disabled
14 1 = The pin is an output
15 2 = The pin is an input
16 3 = The pin is I/O
17
18 - open_drain : indicates the pin is normal or wired-OR:
19
20 0 = The pin is actively driven as an output
21 1 = The pin is an open-drain driver. As an output, the pin is
22 driven active-low, otherwise it is three-stated.
23
24 - assignment : function number of the pin according to the Pin Assignment
25 tables in User Manual. Each pin can have up to 4 possible functions in
26 QE and two options for CPM.
27 - has_irq : indicates if the pin is used as source of external
28 interrupts.
29
30Example:
31 ucc_pin@01 {
32 linux,phandle = <140001>;
33 pio-map = <
34 /* port pin dir open_drain assignment has_irq */
35 0 3 1 0 1 0 /* TxD0 */
36 0 4 1 0 1 0 /* TxD1 */
37 0 5 1 0 1 0 /* TxD2 */
38 0 6 1 0 1 0 /* TxD3 */
39 1 6 1 0 3 0 /* TxD4 */
40 1 7 1 0 1 0 /* TxD5 */
41 1 9 1 0 2 0 /* TxD6 */
42 1 a 1 0 2 0 /* TxD7 */
43 0 9 2 0 1 0 /* RxD0 */
44 0 a 2 0 1 0 /* RxD1 */
45 0 b 2 0 1 0 /* RxD2 */
46 0 c 2 0 1 0 /* RxD3 */
47 0 d 2 0 1 0 /* RxD4 */
48 1 1 2 0 2 0 /* RxD5 */
49 1 0 2 0 2 0 /* RxD6 */
50 1 4 2 0 2 0 /* RxD7 */
51 0 7 1 0 1 0 /* TX_EN */
52 0 8 1 0 1 0 /* TX_ER */
53 0 f 2 0 1 0 /* RX_DV */
54 0 10 2 0 1 0 /* RX_ER */
55 0 0 2 0 1 0 /* RX_CLK */
56 2 9 1 0 3 0 /* GTX_CLK - CLK10 */
57 2 8 2 0 1 0>; /* GTX125 - CLK9 */
58 };
59
60
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/ucc.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/ucc.txt
new file mode 100644
index 00000000000..e47734bee3f
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/ucc.txt
@@ -0,0 +1,70 @@
1* UCC (Unified Communications Controllers)
2
3Required properties:
4- device_type : should be "network", "hldc", "uart", "transparent"
5 "bisync", "atm", or "serial".
6- compatible : could be "ucc_geth" or "fsl_atm" and so on.
7- cell-index : the ucc number(1-8), corresponding to UCCx in UM.
8- reg : Offset and length of the register set for the device
9- interrupts : <a b> where a is the interrupt number and b is a
10 field that represents an encoding of the sense and level
11 information for the interrupt. This should be encoded based on
12 the information in section 2) depending on the type of interrupt
13 controller you have.
14- interrupt-parent : the phandle for the interrupt controller that
15 services interrupts for this device.
16- pio-handle : The phandle for the Parallel I/O port configuration.
17- port-number : for UART drivers, the port number to use, between 0 and 3.
18 This usually corresponds to the /dev/ttyQE device, e.g. <0> = /dev/ttyQE0.
19 The port number is added to the minor number of the device. Unlike the
20 CPM UART driver, the port-number is required for the QE UART driver.
21- soft-uart : for UART drivers, if specified this means the QE UART device
22 driver should use "Soft-UART" mode, which is needed on some SOCs that have
23 broken UART hardware. Soft-UART is provided via a microcode upload.
24- rx-clock-name: the UCC receive clock source
25 "none": clock source is disabled
26 "brg1" through "brg16": clock source is BRG1-BRG16, respectively
27 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
28- tx-clock-name: the UCC transmit clock source
29 "none": clock source is disabled
30 "brg1" through "brg16": clock source is BRG1-BRG16, respectively
31 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
32The following two properties are deprecated. rx-clock has been replaced
33with rx-clock-name, and tx-clock has been replaced with tx-clock-name.
34Drivers that currently use the deprecated properties should continue to
35do so, in order to support older device trees, but they should be updated
36to check for the new properties first.
37- rx-clock : represents the UCC receive clock source.
38 0x00 : clock source is disabled;
39 0x1~0x10 : clock source is BRG1~BRG16 respectively;
40 0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
41- tx-clock: represents the UCC transmit clock source;
42 0x00 : clock source is disabled;
43 0x1~0x10 : clock source is BRG1~BRG16 respectively;
44 0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
45
46Required properties for network device_type:
47- mac-address : list of bytes representing the ethernet address.
48- phy-handle : The phandle for the PHY connected to this controller.
49
50Recommended properties:
51- phy-connection-type : a string naming the controller/PHY interface type,
52 i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id" (Internal
53 Delay), "rgmii-txid" (delay on TX only), "rgmii-rxid" (delay on RX only),
54 "tbi", or "rtbi".
55
56Example:
57 ucc@2000 {
58 device_type = "network";
59 compatible = "ucc_geth";
60 cell-index = <1>;
61 reg = <2000 200>;
62 interrupts = <a0 0>;
63 interrupt-parent = <700>;
64 mac-address = [ 00 04 9f 00 23 23 ];
65 rx-clock = "none";
66 tx-clock = "clk9";
67 phy-handle = <212000>;
68 phy-connection-type = "gmii";
69 pio-handle = <140001>;
70 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/usb.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/usb.txt
new file mode 100644
index 00000000000..c8f44d6bcbc
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/usb.txt
@@ -0,0 +1,22 @@
1* USB (Universal Serial Bus Controller)
2
3Required properties:
4- compatible : could be "qe_udc" or "fhci-hcd".
5- mode : the could be "host" or "slave".
6- reg : Offset and length of the register set for the device
7- interrupts : <a b> where a is the interrupt number and b is a
8 field that represents an encoding of the sense and level
9 information for the interrupt. This should be encoded based on
10 the information in section 2) depending on the type of interrupt
11 controller you have.
12- interrupt-parent : the phandle for the interrupt controller that
13 services interrupts for this device.
14
15Example(slave):
16 usb@6c0 {
17 compatible = "qe_udc";
18 reg = <6c0 40>;
19 interrupts = <8b 0>;
20 interrupt-parent = <700>;
21 mode = "slave";
22 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/serial.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/serial.txt
new file mode 100644
index 00000000000..b35f3482e3e
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/serial.txt
@@ -0,0 +1,21 @@
1* Serial
2
3Currently defined compatibles:
4- fsl,cpm1-smc-uart
5- fsl,cpm2-smc-uart
6- fsl,cpm1-scc-uart
7- fsl,cpm2-scc-uart
8- fsl,qe-uart
9
10Example:
11
12 serial@11a00 {
13 device_type = "serial";
14 compatible = "fsl,mpc8272-scc-uart",
15 "fsl,cpm2-scc-uart";
16 reg = <11a00 20 8000 100>;
17 interrupts = <28 8>;
18 interrupt-parent = <&PIC>;
19 fsl,cpm-brg = <1>;
20 fsl,cpm-command = <00800000>;
21 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/diu.txt b/Documentation/powerpc/dts-bindings/fsl/diu.txt
new file mode 100644
index 00000000000..deb35de7098
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/diu.txt
@@ -0,0 +1,18 @@
1* Freescale Display Interface Unit
2
3The Freescale DIU is a LCD controller, with proper hardware, it can also
4drive DVI monitors.
5
6Required properties:
7- compatible : should be "fsl-diu".
8- reg : should contain at least address and length of the DIU register
9 set.
10- Interrupts : one DIU interrupt should be describe here.
11
12Example (MPC8610HPCD):
13 display@2c000 {
14 compatible = "fsl,diu";
15 reg = <0x2c000 100>;
16 interrupts = <72 2>;
17 interrupt-parent = <&mpic>;
18 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/dma.txt b/Documentation/powerpc/dts-bindings/fsl/dma.txt
new file mode 100644
index 00000000000..86826df00e6
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/dma.txt
@@ -0,0 +1,127 @@
1* Freescale 83xx DMA Controller
2
3Freescale PowerPC 83xx have on chip general purpose DMA controllers.
4
5Required properties:
6
7- compatible : compatible list, contains 2 entries, first is
8 "fsl,CHIP-dma", where CHIP is the processor
9 (mpc8349, mpc8360, etc.) and the second is
10 "fsl,elo-dma"
11- reg : <registers mapping for DMA general status reg>
12- ranges : Should be defined as specified in 1) to describe the
13 DMA controller channels.
14- cell-index : controller index. 0 for controller @ 0x8100
15- interrupts : <interrupt mapping for DMA IRQ>
16- interrupt-parent : optional, if needed for interrupt mapping
17
18
19- DMA channel nodes:
20 - compatible : compatible list, contains 2 entries, first is
21 "fsl,CHIP-dma-channel", where CHIP is the processor
22 (mpc8349, mpc8350, etc.) and the second is
23 "fsl,elo-dma-channel"
24 - reg : <registers mapping for channel>
25 - cell-index : dma channel index starts at 0.
26
27Optional properties:
28 - interrupts : <interrupt mapping for DMA channel IRQ>
29 (on 83xx this is expected to be identical to
30 the interrupts property of the parent node)
31 - interrupt-parent : optional, if needed for interrupt mapping
32
33Example:
34 dma@82a8 {
35 #address-cells = <1>;
36 #size-cells = <1>;
37 compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
38 reg = <82a8 4>;
39 ranges = <0 8100 1a4>;
40 interrupt-parent = <&ipic>;
41 interrupts = <47 8>;
42 cell-index = <0>;
43 dma-channel@0 {
44 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
45 cell-index = <0>;
46 reg = <0 80>;
47 };
48 dma-channel@80 {
49 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
50 cell-index = <1>;
51 reg = <80 80>;
52 };
53 dma-channel@100 {
54 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
55 cell-index = <2>;
56 reg = <100 80>;
57 };
58 dma-channel@180 {
59 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
60 cell-index = <3>;
61 reg = <180 80>;
62 };
63 };
64
65* Freescale 85xx/86xx DMA Controller
66
67Freescale PowerPC 85xx/86xx have on chip general purpose DMA controllers.
68
69Required properties:
70
71- compatible : compatible list, contains 2 entries, first is
72 "fsl,CHIP-dma", where CHIP is the processor
73 (mpc8540, mpc8540, etc.) and the second is
74 "fsl,eloplus-dma"
75- reg : <registers mapping for DMA general status reg>
76- cell-index : controller index. 0 for controller @ 0x21000,
77 1 for controller @ 0xc000
78- ranges : Should be defined as specified in 1) to describe the
79 DMA controller channels.
80
81- DMA channel nodes:
82 - compatible : compatible list, contains 2 entries, first is
83 "fsl,CHIP-dma-channel", where CHIP is the processor
84 (mpc8540, mpc8560, etc.) and the second is
85 "fsl,eloplus-dma-channel"
86 - cell-index : dma channel index starts at 0.
87 - reg : <registers mapping for channel>
88 - interrupts : <interrupt mapping for DMA channel IRQ>
89 - interrupt-parent : optional, if needed for interrupt mapping
90
91Example:
92 dma@21300 {
93 #address-cells = <1>;
94 #size-cells = <1>;
95 compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
96 reg = <21300 4>;
97 ranges = <0 21100 200>;
98 cell-index = <0>;
99 dma-channel@0 {
100 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
101 reg = <0 80>;
102 cell-index = <0>;
103 interrupt-parent = <&mpic>;
104 interrupts = <14 2>;
105 };
106 dma-channel@80 {
107 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
108 reg = <80 80>;
109 cell-index = <1>;
110 interrupt-parent = <&mpic>;
111 interrupts = <15 2>;
112 };
113 dma-channel@100 {
114 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
115 reg = <100 80>;
116 cell-index = <2>;
117 interrupt-parent = <&mpic>;
118 interrupts = <16 2>;
119 };
120 dma-channel@180 {
121 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
122 reg = <180 80>;
123 cell-index = <3>;
124 interrupt-parent = <&mpic>;
125 interrupts = <17 2>;
126 };
127 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/gtm.txt b/Documentation/powerpc/dts-bindings/fsl/gtm.txt
new file mode 100644
index 00000000000..9a33efded4b
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/gtm.txt
@@ -0,0 +1,31 @@
1* Freescale General-purpose Timers Module
2
3Required properties:
4 - compatible : should be
5 "fsl,<chip>-gtm", "fsl,gtm" for SOC GTMs
6 "fsl,<chip>-qe-gtm", "fsl,qe-gtm", "fsl,gtm" for QE GTMs
7 "fsl,<chip>-cpm2-gtm", "fsl,cpm2-gtm", "fsl,gtm" for CPM2 GTMs
8 - reg : should contain gtm registers location and length (0x40).
9 - interrupts : should contain four interrupts.
10 - interrupt-parent : interrupt source phandle.
11 - clock-frequency : specifies the frequency driving the timer.
12
13Example:
14
15timer@500 {
16 compatible = "fsl,mpc8360-gtm", "fsl,gtm";
17 reg = <0x500 0x40>;
18 interrupts = <90 8 78 8 84 8 72 8>;
19 interrupt-parent = <&ipic>;
20 /* filled by u-boot */
21 clock-frequency = <0>;
22};
23
24timer@440 {
25 compatible = "fsl,mpc8360-qe-gtm", "fsl,qe-gtm", "fsl,gtm";
26 reg = <0x440 0x40>;
27 interrupts = <12 13 14 15>;
28 interrupt-parent = <&qeic>;
29 /* filled by u-boot */
30 clock-frequency = <0>;
31};
diff --git a/Documentation/powerpc/dts-bindings/fsl/guts.txt b/Documentation/powerpc/dts-bindings/fsl/guts.txt
new file mode 100644
index 00000000000..9e7a2417dac
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/guts.txt
@@ -0,0 +1,25 @@
1* Global Utilities Block
2
3The global utilities block controls power management, I/O device
4enabling, power-on-reset configuration monitoring, general-purpose
5I/O signal configuration, alternate function selection for multiplexed
6signals, and clock control.
7
8Required properties:
9
10 - compatible : Should define the compatible device type for
11 global-utilities.
12 - reg : Offset and length of the register set for the device.
13
14Recommended properties:
15
16 - fsl,has-rstcr : Indicates that the global utilities register set
17 contains a functioning "reset control register" (i.e. the board
18 is wired to reset upon setting the HRESET_REQ bit in this register).
19
20Example:
21 global-utilities@e0000 { /* global utilities block */
22 compatible = "fsl,mpc8548-guts";
23 reg = <e0000 1000>;
24 fsl,has-rstcr;
25 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/i2c.txt b/Documentation/powerpc/dts-bindings/fsl/i2c.txt
new file mode 100644
index 00000000000..d0ab33e21fe
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/i2c.txt
@@ -0,0 +1,32 @@
1* I2C
2
3Required properties :
4
5 - device_type : Should be "i2c"
6 - reg : Offset and length of the register set for the device
7
8Recommended properties :
9
10 - compatible : Should be "fsl-i2c" for parts compatible with
11 Freescale I2C specifications.
12 - interrupts : <a b> where a is the interrupt number and b is a
13 field that represents an encoding of the sense and level
14 information for the interrupt. This should be encoded based on
15 the information in section 2) depending on the type of interrupt
16 controller you have.
17 - interrupt-parent : the phandle for the interrupt controller that
18 services interrupts for this device.
19 - dfsrr : boolean; if defined, indicates that this I2C device has
20 a digital filter sampling rate register
21 - fsl5200-clocking : boolean; if defined, indicated that this device
22 uses the FSL 5200 clocking mechanism.
23
24Example :
25 i2c@3000 {
26 interrupt-parent = <40000>;
27 interrupts = <1b 3>;
28 reg = <3000 18>;
29 device_type = "i2c";
30 compatible = "fsl-i2c";
31 dfsrr;
32 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/lbc.txt b/Documentation/powerpc/dts-bindings/fsl/lbc.txt
new file mode 100644
index 00000000000..3300fec501c
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/lbc.txt
@@ -0,0 +1,35 @@
1* Chipselect/Local Bus
2
3Properties:
4- name : Should be localbus
5- #address-cells : Should be either two or three. The first cell is the
6 chipselect number, and the remaining cells are the
7 offset into the chipselect.
8- #size-cells : Either one or two, depending on how large each chipselect
9 can be.
10- ranges : Each range corresponds to a single chipselect, and cover
11 the entire access window as configured.
12
13Example:
14 localbus@f0010100 {
15 compatible = "fsl,mpc8272-localbus",
16 "fsl,pq2-localbus";
17 #address-cells = <2>;
18 #size-cells = <1>;
19 reg = <f0010100 40>;
20
21 ranges = <0 0 fe000000 02000000
22 1 0 f4500000 00008000>;
23
24 flash@0,0 {
25 compatible = "jedec-flash";
26 reg = <0 0 2000000>;
27 bank-width = <4>;
28 device-width = <1>;
29 };
30
31 board-control@1,0 {
32 reg = <1 0 20>;
33 compatible = "fsl,mpc8272ads-bcsr";
34 };
35 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/msi-pic.txt b/Documentation/powerpc/dts-bindings/fsl/msi-pic.txt
new file mode 100644
index 00000000000..b26b91992c5
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/msi-pic.txt
@@ -0,0 +1,36 @@
1* Freescale MSI interrupt controller
2
3Reguired properities:
4- compatible : compatible list, contains 2 entries,
5 first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
6 etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending on
7 the parent type.
8- reg : should contain the address and the length of the shared message
9 interrupt register set.
10- msi-available-ranges: use <start count> style section to define which
11 msi interrupt can be used in the 256 msi interrupts. This property is
12 optional, without this, all the 256 MSI interrupts can be used.
13- interrupts : each one of the interrupts here is one entry per 32 MSIs,
14 and routed to the host interrupt controller. the interrupts should
15 be set as edge sensitive.
16- interrupt-parent: the phandle for the interrupt controller
17 that services interrupts for this device. for 83xx cpu, the interrupts
18 are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed
19 to MPIC.
20
21Example:
22 msi@41600 {
23 compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
24 reg = <0x41600 0x80>;
25 msi-available-ranges = <0 0x100>;
26 interrupts = <
27 0xe0 0
28 0xe1 0
29 0xe2 0
30 0xe3 0
31 0xe4 0
32 0xe5 0
33 0xe6 0
34 0xe7 0>;
35 interrupt-parent = <&mpic>;
36 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/sata.txt b/Documentation/powerpc/dts-bindings/fsl/sata.txt
new file mode 100644
index 00000000000..b46bcf46c3d
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/sata.txt
@@ -0,0 +1,29 @@
1* Freescale 8xxx/3.0 Gb/s SATA nodes
2
3SATA nodes are defined to describe on-chip Serial ATA controllers.
4Each SATA port should have its own node.
5
6Required properties:
7- compatible : compatible list, contains 2 entries, first is
8 "fsl,CHIP-sata", where CHIP is the processor
9 (mpc8315, mpc8379, etc.) and the second is
10 "fsl,pq-sata"
11- interrupts : <interrupt mapping for SATA IRQ>
12- cell-index : controller index.
13 1 for controller @ 0x18000
14 2 for controller @ 0x19000
15 3 for controller @ 0x1a000
16 4 for controller @ 0x1b000
17
18Optional properties:
19- interrupt-parent : optional, if needed for interrupt mapping
20- reg : <registers mapping>
21
22Example:
23 sata@18000 {
24 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
25 reg = <0x18000 0x1000>;
26 cell-index = <1>;
27 interrupts = <2c 8>;
28 interrupt-parent = < &ipic >;
29 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/sec.txt b/Documentation/powerpc/dts-bindings/fsl/sec.txt
new file mode 100644
index 00000000000..2b6f2d45c45
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/sec.txt
@@ -0,0 +1,68 @@
1Freescale SoC SEC Security Engines
2
3Required properties:
4
5- compatible : Should contain entries for this and backward compatible
6 SEC versions, high to low, e.g., "fsl,sec2.1", "fsl,sec2.0"
7- reg : Offset and length of the register set for the device
8- interrupts : the SEC's interrupt number
9- fsl,num-channels : An integer representing the number of channels
10 available.
11- fsl,channel-fifo-len : An integer representing the number of
12 descriptor pointers each channel fetch fifo can hold.
13- fsl,exec-units-mask : The bitmask representing what execution units
14 (EUs) are available. It's a single 32-bit cell. EU information
15 should be encoded following the SEC's Descriptor Header Dword
16 EU_SEL0 field documentation, i.e. as follows:
17
18 bit 0 = reserved - should be 0
19 bit 1 = set if SEC has the ARC4 EU (AFEU)
20 bit 2 = set if SEC has the DES/3DES EU (DEU)
21 bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A)
22 bit 4 = set if SEC has the random number generator EU (RNG)
23 bit 5 = set if SEC has the public key EU (PKEU)
24 bit 6 = set if SEC has the AES EU (AESU)
25 bit 7 = set if SEC has the Kasumi EU (KEU)
26 bit 8 = set if SEC has the CRC EU (CRCU)
27 bit 11 = set if SEC has the message digest EU extended alg set (MDEU-B)
28
29remaining bits are reserved for future SEC EUs.
30
31- fsl,descriptor-types-mask : The bitmask representing what descriptors
32 are available. It's a single 32-bit cell. Descriptor type information
33 should be encoded following the SEC's Descriptor Header Dword DESC_TYPE
34 field documentation, i.e. as follows:
35
36 bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type
37 bit 1 = set if SEC supports the ipsec_esp descriptor type
38 bit 2 = set if SEC supports the common_nonsnoop desc. type
39 bit 3 = set if SEC supports the 802.11i AES ccmp desc. type
40 bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type
41 bit 5 = set if SEC supports the srtp descriptor type
42 bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type
43 bit 7 = set if SEC supports the pkeu_assemble descriptor type
44 bit 8 = set if SEC supports the aesu_key_expand_output desc.type
45 bit 9 = set if SEC supports the pkeu_ptmul descriptor type
46 bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type
47 bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type
48
49 ..and so on and so forth.
50
51Optional properties:
52
53- interrupt-parent : the phandle for the interrupt controller that
54 services interrupts for this device.
55
56Example:
57
58 /* MPC8548E */
59 crypto@30000 {
60 compatible = "fsl,sec2.1", "fsl,sec2.0";
61 reg = <0x30000 0x10000>;
62 interrupts = <29 2>;
63 interrupt-parent = <&mpic>;
64 fsl,num-channels = <4>;
65 fsl,channel-fifo-len = <24>;
66 fsl,exec-units-mask = <0xfe>;
67 fsl,descriptor-types-mask = <0x12b0ebf>;
68 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/spi.txt b/Documentation/powerpc/dts-bindings/fsl/spi.txt
new file mode 100644
index 00000000000..e7d9a344c4f
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/spi.txt
@@ -0,0 +1,24 @@
1* SPI (Serial Peripheral Interface)
2
3Required properties:
4- cell-index : SPI controller index.
5- compatible : should be "fsl,spi".
6- mode : the SPI operation mode, it can be "cpu" or "cpu-qe".
7- reg : Offset and length of the register set for the device
8- interrupts : <a b> where a is the interrupt number and b is a
9 field that represents an encoding of the sense and level
10 information for the interrupt. This should be encoded based on
11 the information in section 2) depending on the type of interrupt
12 controller you have.
13- interrupt-parent : the phandle for the interrupt controller that
14 services interrupts for this device.
15
16Example:
17 spi@4c0 {
18 cell-index = <0>;
19 compatible = "fsl,spi";
20 reg = <4c0 40>;
21 interrupts = <82 0>;
22 interrupt-parent = <700>;
23 mode = "cpu";
24 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/ssi.txt b/Documentation/powerpc/dts-bindings/fsl/ssi.txt
new file mode 100644
index 00000000000..d100555d488
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/ssi.txt
@@ -0,0 +1,38 @@
1Freescale Synchronous Serial Interface
2
3The SSI is a serial device that communicates with audio codecs. It can
4be programmed in AC97, I2S, left-justified, or right-justified modes.
5
6Required properties:
7- compatible : compatible list, containing "fsl,ssi"
8- cell-index : the SSI, <0> = SSI1, <1> = SSI2, and so on
9- reg : offset and length of the register set for the device
10- interrupts : <a b> where a is the interrupt number and b is a
11 field that represents an encoding of the sense and
12 level information for the interrupt. This should be
13 encoded based on the information in section 2)
14 depending on the type of interrupt controller you
15 have.
16- interrupt-parent : the phandle for the interrupt controller that
17 services interrupts for this device.
18- fsl,mode : the operating mode for the SSI interface
19 "i2s-slave" - I2S mode, SSI is clock slave
20 "i2s-master" - I2S mode, SSI is clock master
21 "lj-slave" - left-justified mode, SSI is clock slave
22 "lj-master" - l.j. mode, SSI is clock master
23 "rj-slave" - right-justified mode, SSI is clock slave
24 "rj-master" - r.j., SSI is clock master
25 "ac97-slave" - AC97 mode, SSI is clock slave
26 "ac97-master" - AC97 mode, SSI is clock master
27
28Optional properties:
29- codec-handle : phandle to a 'codec' node that defines an audio
30 codec connected to this SSI. This node is typically
31 a child of an I2C or other control node.
32
33Child 'codec' node required properties:
34- compatible : compatible list, contains the name of the codec
35
36Child 'codec' node optional properties:
37- clock-frequency : The frequency of the input clock, which typically
38 comes from an on-board dedicated oscillator.
diff --git a/Documentation/powerpc/dts-bindings/fsl/tsec.txt b/Documentation/powerpc/dts-bindings/fsl/tsec.txt
new file mode 100644
index 00000000000..583ef6b56c4
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/tsec.txt
@@ -0,0 +1,69 @@
1* MDIO IO device
2
3The MDIO is a bus to which the PHY devices are connected. For each
4device that exists on this bus, a child node should be created. See
5the definition of the PHY node below for an example of how to define
6a PHY.
7
8Required properties:
9 - reg : Offset and length of the register set for the device
10 - compatible : Should define the compatible device type for the
11 mdio. Currently, this is most likely to be "fsl,gianfar-mdio"
12
13Example:
14
15 mdio@24520 {
16 reg = <24520 20>;
17 compatible = "fsl,gianfar-mdio";
18
19 ethernet-phy@0 {
20 ......
21 };
22 };
23
24
25* Gianfar-compatible ethernet nodes
26
27Required properties:
28
29 - device_type : Should be "network"
30 - model : Model of the device. Can be "TSEC", "eTSEC", or "FEC"
31 - compatible : Should be "gianfar"
32 - reg : Offset and length of the register set for the device
33 - mac-address : List of bytes representing the ethernet address of
34 this controller
35 - interrupts : <a b> where a is the interrupt number and b is a
36 field that represents an encoding of the sense and level
37 information for the interrupt. This should be encoded based on
38 the information in section 2) depending on the type of interrupt
39 controller you have.
40 - interrupt-parent : the phandle for the interrupt controller that
41 services interrupts for this device.
42 - phy-handle : The phandle for the PHY connected to this ethernet
43 controller.
44 - fixed-link : <a b c d e> where a is emulated phy id - choose any,
45 but unique to the all specified fixed-links, b is duplex - 0 half,
46 1 full, c is link speed - d#10/d#100/d#1000, d is pause - 0 no
47 pause, 1 pause, e is asym_pause - 0 no asym_pause, 1 asym_pause.
48
49Recommended properties:
50
51 - phy-connection-type : a string naming the controller/PHY interface type,
52 i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id", "sgmii",
53 "tbi", or "rtbi". This property is only really needed if the connection
54 is of type "rgmii-id", as all other connection types are detected by
55 hardware.
56
57
58Example:
59 ethernet@24000 {
60 #size-cells = <0>;
61 device_type = "network";
62 model = "TSEC";
63 compatible = "gianfar";
64 reg = <24000 1000>;
65 mac-address = [ 00 E0 0C 00 73 00 ];
66 interrupts = <d 3 e 3 12 3>;
67 interrupt-parent = <40000>;
68 phy-handle = <2452000>
69 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/usb.txt b/Documentation/powerpc/dts-bindings/fsl/usb.txt
new file mode 100644
index 00000000000..b0015240269
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/usb.txt
@@ -0,0 +1,59 @@
1Freescale SOC USB controllers
2
3The device node for a USB controller that is part of a Freescale
4SOC is as described in the document "Open Firmware Recommended
5Practice : Universal Serial Bus" with the following modifications
6and additions :
7
8Required properties :
9 - compatible : Should be "fsl-usb2-mph" for multi port host USB
10 controllers, or "fsl-usb2-dr" for dual role USB controllers
11 - phy_type : For multi port host USB controllers, should be one of
12 "ulpi", or "serial". For dual role USB controllers, should be
13 one of "ulpi", "utmi", "utmi_wide", or "serial".
14 - reg : Offset and length of the register set for the device
15 - port0 : boolean; if defined, indicates port0 is connected for
16 fsl-usb2-mph compatible controllers. Either this property or
17 "port1" (or both) must be defined for "fsl-usb2-mph" compatible
18 controllers.
19 - port1 : boolean; if defined, indicates port1 is connected for
20 fsl-usb2-mph compatible controllers. Either this property or
21 "port0" (or both) must be defined for "fsl-usb2-mph" compatible
22 controllers.
23 - dr_mode : indicates the working mode for "fsl-usb2-dr" compatible
24 controllers. Can be "host", "peripheral", or "otg". Default to
25 "host" if not defined for backward compatibility.
26
27Recommended properties :
28 - interrupts : <a b> where a is the interrupt number and b is a
29 field that represents an encoding of the sense and level
30 information for the interrupt. This should be encoded based on
31 the information in section 2) depending on the type of interrupt
32 controller you have.
33 - interrupt-parent : the phandle for the interrupt controller that
34 services interrupts for this device.
35
36Example multi port host USB controller device node :
37 usb@22000 {
38 compatible = "fsl-usb2-mph";
39 reg = <22000 1000>;
40 #address-cells = <1>;
41 #size-cells = <0>;
42 interrupt-parent = <700>;
43 interrupts = <27 1>;
44 phy_type = "ulpi";
45 port0;
46 port1;
47 };
48
49Example dual role USB controller device node :
50 usb@23000 {
51 compatible = "fsl-usb2-dr";
52 reg = <23000 1000>;
53 #address-cells = <1>;
54 #size-cells = <0>;
55 interrupt-parent = <700>;
56 interrupts = <26 1>;
57 dr_mode = "otg";
58 phy = "ulpi";
59 };
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-24 15:39:21 -0500