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-rw-r--r--arch/mips/kernel/smtc.c2
-rw-r--r--include/asm-mips/smtc.h10
2 files changed, 10 insertions, 2 deletions
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index 16aa5d37117..43826c16101 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -28,8 +28,6 @@
28 * This file should be built into the kernel only if CONFIG_MIPS_MT_SMTC is set. 28 * This file should be built into the kernel only if CONFIG_MIPS_MT_SMTC is set.
29 */ 29 */
30 30
31#define MIPS_CPU_IPI_IRQ 1
32
33#define LOCK_MT_PRA() \ 31#define LOCK_MT_PRA() \
34 local_irq_save(flags); \ 32 local_irq_save(flags); \
35 mtflags = dmt() 33 mtflags = dmt()
diff --git a/include/asm-mips/smtc.h b/include/asm-mips/smtc.h
index 44dfa4adecf..ff3e8936b49 100644
--- a/include/asm-mips/smtc.h
+++ b/include/asm-mips/smtc.h
@@ -55,4 +55,14 @@ extern void smtc_boot_secondary(int cpu, struct task_struct *t);
55 55
56#define PARKED_INDEX ((unsigned int)0x80000000) 56#define PARKED_INDEX ((unsigned int)0x80000000)
57 57
58/*
59 * Define low-level interrupt mask for IPIs, if necessary.
60 * By default, use SW interrupt 1, which requires no external
61 * hardware support, but which works only for single-core
62 * MIPS MT systems.
63 */
64#ifndef MIPS_CPU_IPI_IRQ
65#define MIPS_CPU_IPI_IRQ 1
66#endif
67
58#endif /* _ASM_SMTC_MT_H */ 68#endif /* _ASM_SMTC_MT_H */