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-rw-r--r--arch/arm/mach-tegra/Kconfig19
-rw-r--r--arch/arm/mach-tegra/Makefile3
-rw-r--r--arch/arm/mach-tegra/board-seaboard-pinmux.c179
-rw-r--r--arch/arm/mach-tegra/board-seaboard.c196
-rw-r--r--arch/arm/mach-tegra/board-seaboard.h38
5 files changed, 435 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index bdf52f0f729..b94e52df0d8 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -27,12 +27,31 @@ config MACH_HARMONY
27 help 27 help
28 Support for nVidia Harmony development platform 28 Support for nVidia Harmony development platform
29 29
30config MACH_KAEN
31 bool "Kaen board"
32 select MACH_SEABOARD
33 help
34 Support for the Kaen version of Seaboard
35
36config MACH_SEABOARD
37 bool "Seaboard board"
38 help
39 Support for nVidia Seaboard development platform. It will
40 also be included for some of the derivative boards that
41 have large similarities with the seaboard design.
42
30config MACH_TRIMSLICE 43config MACH_TRIMSLICE
31 bool "TrimSlice board" 44 bool "TrimSlice board"
32 select TEGRA_PCI 45 select TEGRA_PCI
33 help 46 help
34 Support for CompuLab TrimSlice platform 47 Support for CompuLab TrimSlice platform
35 48
49config MACH_WARIO
50 bool "Wario board"
51 select MACH_SEABOARD
52 help
53 Support for the Wario version of Seaboard
54
36choice 55choice
37 prompt "Low-level debug console UART" 56 prompt "Low-level debug console UART"
38 default TEGRA_DEBUG_UART_NONE 57 default TEGRA_DEBUG_UART_NONE
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index c530dba75d6..9bf39fa34d8 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -22,5 +22,8 @@ obj-${CONFIG_MACH_HARMONY} += board-harmony.o
22obj-${CONFIG_MACH_HARMONY} += board-harmony-pinmux.o 22obj-${CONFIG_MACH_HARMONY} += board-harmony-pinmux.o
23obj-${CONFIG_MACH_HARMONY} += board-harmony-pcie.o 23obj-${CONFIG_MACH_HARMONY} += board-harmony-pcie.o
24 24
25obj-${CONFIG_MACH_SEABOARD} += board-seaboard.o
26obj-${CONFIG_MACH_SEABOARD} += board-seaboard-pinmux.o
27
25obj-${CONFIG_MACH_TRIMSLICE} += board-trimslice.o 28obj-${CONFIG_MACH_TRIMSLICE} += board-trimslice.o
26obj-${CONFIG_MACH_TRIMSLICE} += board-trimslice-pinmux.o 29obj-${CONFIG_MACH_TRIMSLICE} += board-trimslice-pinmux.o
diff --git a/arch/arm/mach-tegra/board-seaboard-pinmux.c b/arch/arm/mach-tegra/board-seaboard-pinmux.c
new file mode 100644
index 00000000000..2d6ad83ed4b
--- /dev/null
+++ b/arch/arm/mach-tegra/board-seaboard-pinmux.c
@@ -0,0 +1,179 @@
1/*
2 * Copyright (C) 2010 NVIDIA Corporation
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 */
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/gpio.h>
18
19#include <mach/pinmux.h>
20#include <mach/pinmux-t2.h>
21
22#include "gpio-names.h"
23#include "board-seaboard.h"
24
25#define DEFAULT_DRIVE(_name) \
26 { \
27 .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \
28 .hsm = TEGRA_HSM_DISABLE, \
29 .schmitt = TEGRA_SCHMITT_ENABLE, \
30 .drive = TEGRA_DRIVE_DIV_1, \
31 .pull_down = TEGRA_PULL_31, \
32 .pull_up = TEGRA_PULL_31, \
33 .slew_rising = TEGRA_SLEW_SLOWEST, \
34 .slew_falling = TEGRA_SLEW_SLOWEST, \
35 }
36
37static __initdata struct tegra_drive_pingroup_config seaboard_drive_pinmux[] = {
38 DEFAULT_DRIVE(SDIO1),
39};
40
41static __initdata struct tegra_pingroup_config seaboard_pinmux[] = {
42 {TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
43 {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
44 {TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
45 {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
46 {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
47 {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
48 {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
49 {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
50 {TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
51 {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
52 {TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
53 {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
54 {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
55 {TEGRA_PINGROUP_DDC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
56 {TEGRA_PINGROUP_DTA, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
57 {TEGRA_PINGROUP_DTB, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
58 {TEGRA_PINGROUP_DTC, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
59 {TEGRA_PINGROUP_DTD, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
60 {TEGRA_PINGROUP_DTE, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
61 {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
62 {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
63 {TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
64 {TEGRA_PINGROUP_GMC, TEGRA_MUX_UARTD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
65 {TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
66 {TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
67 {TEGRA_PINGROUP_GPU, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
68 {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
69 {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
70 {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
71 {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
72 {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTB, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
73 {TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTB, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
74 {TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
75 {TEGRA_PINGROUP_KBCB, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
76 {TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
77 {TEGRA_PINGROUP_KBCD, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
78 {TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
79 {TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
80 {TEGRA_PINGROUP_LCSN, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
81 {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
82 {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
83 {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
84 {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
85 {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
86 {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
87 {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
88 {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
89 {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
90 {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
91 {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
92 {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
93 {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
94 {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
95 {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
96 {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
97 {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
98 {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
99 {TEGRA_PINGROUP_LDC, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
100 {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
101 {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
102 {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
103 {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
104 {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
105 {TEGRA_PINGROUP_LM0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
106 {TEGRA_PINGROUP_LM1, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
107 {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
108 {TEGRA_PINGROUP_LPW0, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
109 {TEGRA_PINGROUP_LPW1, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
110 {TEGRA_PINGROUP_LPW2, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
111 {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
112 {TEGRA_PINGROUP_LSC1, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
113 {TEGRA_PINGROUP_LSCK, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
114 {TEGRA_PINGROUP_LSDA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
115 {TEGRA_PINGROUP_LSDI, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
116 {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
117 {TEGRA_PINGROUP_LVP0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
118 {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
119 {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
120 {TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
121 {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
122 {TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
123 {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
124 {TEGRA_PINGROUP_SDB, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
125 {TEGRA_PINGROUP_SDC, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
126 {TEGRA_PINGROUP_SDD, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
127 {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
128 {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
129 {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
130 {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
131 {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
132 {TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
133 {TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
134 {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
135 {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
136 {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
137 {TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
138 {TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
139 {TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
140 {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
141 {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
142 {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
143 {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
144 {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
145 {TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
146 {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
147 {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
148 {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
149 {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
150 {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
151 {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
152 {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
153 {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
154 {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
155 {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
156 {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
157 {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
158};
159
160
161
162
163static struct tegra_gpio_table gpio_table[] = {
164 { .gpio = TEGRA_GPIO_PI5, .enable = true }, /* mmc2 cd */
165 { .gpio = TEGRA_GPIO_PH1, .enable = true }, /* mmc2 wp */
166 { .gpio = TEGRA_GPIO_PI6, .enable = true }, /* mmc2 pwr */
167 { .gpio = TEGRA_GPIO_LIDSWITCH, .enable = true }, /* lid switch */
168 { .gpio = TEGRA_GPIO_POWERKEY, .enable = true }, /* power key */
169};
170
171void __init seaboard_pinmux_init(void)
172{
173 tegra_pinmux_config_table(seaboard_pinmux, ARRAY_SIZE(seaboard_pinmux));
174
175 tegra_drive_pinmux_config_table(seaboard_drive_pinmux,
176 ARRAY_SIZE(seaboard_drive_pinmux));
177
178 tegra_gpio_config(gpio_table, ARRAY_SIZE(gpio_table));
179}
diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c
new file mode 100644
index 00000000000..6ca9e61f6cd
--- /dev/null
+++ b/arch/arm/mach-tegra/board-seaboard.c
@@ -0,0 +1,196 @@
1/*
2 * Copyright (c) 2010, 2011 NVIDIA Corporation.
3 * Copyright (C) 2010, 2011 Google, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 */
16
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/platform_device.h>
20#include <linux/serial_8250.h>
21#include <linux/delay.h>
22#include <linux/input.h>
23#include <linux/io.h>
24#include <linux/gpio_keys.h>
25
26#include <mach/iomap.h>
27#include <mach/irqs.h>
28#include <mach/sdhci.h>
29
30#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
32
33#include "board.h"
34#include "board-seaboard.h"
35#include "clock.h"
36#include "devices.h"
37#include "gpio-names.h"
38
39static struct plat_serial8250_port debug_uart_platform_data[] = {
40 {
41 /* Memory and IRQ filled in before registration */
42 .flags = UPF_BOOT_AUTOCONF,
43 .iotype = UPIO_MEM,
44 .regshift = 2,
45 .uartclk = 216000000,
46 }, {
47 .flags = 0,
48 }
49};
50
51static struct platform_device debug_uart = {
52 .name = "serial8250",
53 .id = PLAT8250_DEV_PLATFORM,
54 .dev = {
55 .platform_data = debug_uart_platform_data,
56 },
57};
58
59static __initdata struct tegra_clk_init_table seaboard_clk_init_table[] = {
60 /* name parent rate enabled */
61 { "uartb", "pll_p", 216000000, true},
62 { "uartd", "pll_p", 216000000, true},
63 { NULL, NULL, 0, 0},
64};
65
66static struct gpio_keys_button seaboard_gpio_keys_buttons[] = {
67 {
68 .code = SW_LID,
69 .gpio = TEGRA_GPIO_LIDSWITCH,
70 .active_low = 0,
71 .desc = "Lid",
72 .type = EV_SW,
73 .wakeup = 1,
74 .debounce_interval = 1,
75 },
76 {
77 .code = KEY_POWER,
78 .gpio = TEGRA_GPIO_POWERKEY,
79 .active_low = 1,
80 .desc = "Power",
81 .type = EV_KEY,
82 .wakeup = 1,
83 },
84};
85
86static struct gpio_keys_platform_data seaboard_gpio_keys = {
87 .buttons = seaboard_gpio_keys_buttons,
88 .nbuttons = ARRAY_SIZE(seaboard_gpio_keys_buttons),
89};
90
91static struct platform_device seaboard_gpio_keys_device = {
92 .name = "gpio-keys",
93 .id = -1,
94 .dev = {
95 .platform_data = &seaboard_gpio_keys,
96 }
97};
98
99static struct tegra_sdhci_platform_data sdhci_pdata1 = {
100 .cd_gpio = -1,
101 .wp_gpio = -1,
102 .power_gpio = -1,
103};
104
105static struct tegra_sdhci_platform_data sdhci_pdata3 = {
106 .cd_gpio = TEGRA_GPIO_PI5,
107 .wp_gpio = TEGRA_GPIO_PH1,
108 .power_gpio = TEGRA_GPIO_PI6,
109};
110
111static struct tegra_sdhci_platform_data sdhci_pdata4 = {
112 .cd_gpio = -1,
113 .wp_gpio = -1,
114 .power_gpio = -1,
115 .is_8bit = 1,
116};
117
118static struct platform_device *seaboard_devices[] __initdata = {
119 &debug_uart,
120 &tegra_pmu_device,
121 &tegra_sdhci_device1,
122 &tegra_sdhci_device3,
123 &tegra_sdhci_device4,
124 &seaboard_gpio_keys_device,
125};
126
127static void __init __tegra_seaboard_init(void)
128{
129 seaboard_pinmux_init();
130
131 tegra_clk_init_from_table(seaboard_clk_init_table);
132
133 tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1;
134 tegra_sdhci_device3.dev.platform_data = &sdhci_pdata3;
135 tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4;
136
137 platform_add_devices(seaboard_devices, ARRAY_SIZE(seaboard_devices));
138}
139
140static void __init tegra_seaboard_init(void)
141{
142 /* Seaboard uses UARTD for the debug port. */
143 debug_uart_platform_data[0].membase = IO_ADDRESS(TEGRA_UARTD_BASE);
144 debug_uart_platform_data[0].mapbase = TEGRA_UARTD_BASE;
145 debug_uart_platform_data[0].irq = INT_UARTD;
146
147 __tegra_seaboard_init();
148}
149
150static void __init tegra_kaen_init(void)
151{
152 /* Kaen uses UARTB for the debug port. */
153 debug_uart_platform_data[0].membase = IO_ADDRESS(TEGRA_UARTB_BASE);
154 debug_uart_platform_data[0].mapbase = TEGRA_UARTB_BASE;
155 debug_uart_platform_data[0].irq = INT_UARTB;
156
157 __tegra_seaboard_init();
158}
159
160static void __init tegra_wario_init(void)
161{
162 /* Wario uses UARTB for the debug port. */
163 debug_uart_platform_data[0].membase = IO_ADDRESS(TEGRA_UARTB_BASE);
164 debug_uart_platform_data[0].mapbase = TEGRA_UARTB_BASE;
165 debug_uart_platform_data[0].irq = INT_UARTB;
166
167 __tegra_seaboard_init();
168}
169
170
171MACHINE_START(SEABOARD, "seaboard")
172 .boot_params = 0x00000100,
173 .map_io = tegra_map_common_io,
174 .init_early = tegra_init_early,
175 .init_irq = tegra_init_irq,
176 .timer = &tegra_timer,
177 .init_machine = tegra_seaboard_init,
178MACHINE_END
179
180MACHINE_START(KAEN, "kaen")
181 .boot_params = 0x00000100,
182 .map_io = tegra_map_common_io,
183 .init_early = tegra_init_early,
184 .init_irq = tegra_init_irq,
185 .timer = &tegra_timer,
186 .init_machine = tegra_kaen_init,
187MACHINE_END
188
189MACHINE_START(WARIO, "wario")
190 .boot_params = 0x00000100,
191 .map_io = tegra_map_common_io,
192 .init_early = tegra_init_early,
193 .init_irq = tegra_init_irq,
194 .timer = &tegra_timer,
195 .init_machine = tegra_wario_init,
196MACHINE_END
diff --git a/arch/arm/mach-tegra/board-seaboard.h b/arch/arm/mach-tegra/board-seaboard.h
new file mode 100644
index 00000000000..a098e359973
--- /dev/null
+++ b/arch/arm/mach-tegra/board-seaboard.h
@@ -0,0 +1,38 @@
1/*
2 * arch/arm/mach-tegra/board-seaboard.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#ifndef _MACH_TEGRA_BOARD_SEABOARD_H
18#define _MACH_TEGRA_BOARD_SEABOARD_H
19
20#define TEGRA_GPIO_LIDSWITCH TEGRA_GPIO_PC7
21#define TEGRA_GPIO_USB1 TEGRA_GPIO_PD0
22#define TEGRA_GPIO_POWERKEY TEGRA_GPIO_PV2
23#define TEGRA_GPIO_BACKLIGHT TEGRA_GPIO_PD4
24#define TEGRA_GPIO_LVDS_SHUTDOWN TEGRA_GPIO_PB2
25#define TEGRA_GPIO_BACKLIGHT_PWM TEGRA_GPIO_PU5
26#define TEGRA_GPIO_BACKLIGHT_VDD TEGRA_GPIO_PW0
27#define TEGRA_GPIO_EN_VDD_PNL TEGRA_GPIO_PC6
28#define TEGRA_GPIO_MAGNETOMETER TEGRA_GPIO_PN5
29#define TEGRA_GPIO_ISL29018_IRQ TEGRA_GPIO_PZ2
30#define TEGRA_GPIO_AC_ONLINE TEGRA_GPIO_PV3
31
32#define TPS_GPIO_BASE TEGRA_NR_GPIOS
33
34#define TPS_GPIO_WWAN_PWR (TPS_GPIO_BASE + 2)
35
36void seaboard_pinmux_init(void);
37
38#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-15 03:45:54 -0400