1 files changed, 9 insertions, 0 deletions

diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index fa5297d643d..38353386e91 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -201,6 +201,15 @@ void __init omap_map_sram(void)
                 base = OMAP3_SRAM_PA;
                 base = ROUND_DOWN(base, PAGE_SIZE);
                 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
+
+                /*
+                 * SRAM must be marked as non-cached on OMAP3 since the
+                 * CORE DPLL M2 divider change code (in SRAM) runs with the
+                 * SDRAM controller disabled, and if it is marked cached,
+                 * the ARM may attempt to write cache lines back to SDRAM
+                 * which will cause the system to hang.
+                 */
+                omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED;
         }
 
         omap_sram_io_desc[0].length = 1024 * 1024;      /* Use section desc */