diff options
-rw-r--r-- | include/asm-sh/cpu-sh5/cache.h (renamed from include/asm-sh64/cache.h) | 61 |
1 files changed, 8 insertions, 53 deletions
diff --git a/include/asm-sh64/cache.h b/include/asm-sh/cpu-sh5/cache.h index a4f36f0036e..2d1f9c28b92 100644 --- a/include/asm-sh64/cache.h +++ b/include/asm-sh/cpu-sh5/cache.h | |||
@@ -12,22 +12,16 @@ | |||
12 | * Copyright (C) 2003, 2004 Paul Mundt | 12 | * Copyright (C) 2003, 2004 Paul Mundt |
13 | * | 13 | * |
14 | */ | 14 | */ |
15 | #include <asm/cacheflush.h> | ||
16 | 15 | ||
17 | #define L1_CACHE_SHIFT 5 | 16 | #define L1_CACHE_SHIFT 5 |
18 | /* bytes per L1 cache line */ | 17 | |
19 | #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) | 18 | /* Valid and Dirty bits */ |
20 | #define L1_CACHE_ALIGN_MASK (~(L1_CACHE_BYTES - 1)) | 19 | #define SH_CACHE_VALID (1LL<<0) |
21 | #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES - 1)) & L1_CACHE_ALIGN_MASK) | 20 | #define SH_CACHE_UPDATED (1LL<<57) |
22 | #define L1_CACHE_SIZE_BYTES (L1_CACHE_BYTES << 10) | 21 | |
23 | 22 | /* Cache flags */ | |
24 | #ifdef MODULE | 23 | #define SH_CACHE_MODE_WT (1LL<<0) |
25 | #define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES))) | 24 | #define SH_CACHE_MODE_WB (1LL<<1) |
26 | #else | ||
27 | #define __cacheline_aligned \ | ||
28 | __attribute__((__aligned__(L1_CACHE_BYTES), \ | ||
29 | __section__(".data.cacheline_aligned"))) | ||
30 | #endif | ||
31 | 25 | ||
32 | /* | 26 | /* |
33 | * Control Registers. | 27 | * Control Registers. |
@@ -58,7 +52,6 @@ | |||
58 | 52 | ||
59 | #define OCCR1_NOLOCK 0x0 /* Set No Locking */ | 53 | #define OCCR1_NOLOCK 0x0 /* Set No Locking */ |
60 | 54 | ||
61 | |||
62 | /* | 55 | /* |
63 | * SH-5 | 56 | * SH-5 |
64 | * A bit of description here, for neff=32. | 57 | * A bit of description here, for neff=32. |
@@ -77,43 +70,6 @@ | |||
77 | * | 70 | * |
78 | */ | 71 | */ |
79 | 72 | ||
80 | /* Valid and Dirty bits */ | ||
81 | #define SH_CACHE_VALID (1LL<<0) | ||
82 | #define SH_CACHE_UPDATED (1LL<<57) | ||
83 | |||
84 | /* Cache flags */ | ||
85 | #define SH_CACHE_MODE_WT (1LL<<0) | ||
86 | #define SH_CACHE_MODE_WB (1LL<<1) | ||
87 | |||
88 | #ifndef __ASSEMBLY__ | ||
89 | |||
90 | /* | ||
91 | * Cache information structure. | ||
92 | * | ||
93 | * Defined for both I and D cache, per-processor. | ||
94 | */ | ||
95 | struct cache_info { | ||
96 | unsigned int ways; | ||
97 | unsigned int sets; | ||
98 | unsigned int linesz; | ||
99 | |||
100 | unsigned int way_shift; | ||
101 | unsigned int entry_shift; | ||
102 | unsigned int set_shift; | ||
103 | unsigned int way_step_shift; | ||
104 | unsigned int asid_shift; | ||
105 | |||
106 | unsigned int way_ofs; | ||
107 | |||
108 | unsigned int asid_mask; | ||
109 | unsigned int idx_mask; | ||
110 | unsigned int epn_mask; | ||
111 | |||
112 | unsigned long flags; | ||
113 | }; | ||
114 | |||
115 | #endif /* __ASSEMBLY__ */ | ||
116 | |||
117 | /* Instruction cache */ | 73 | /* Instruction cache */ |
118 | #define CACHE_IC_ADDRESS_ARRAY 0x01000000 | 74 | #define CACHE_IC_ADDRESS_ARRAY 0x01000000 |
119 | 75 | ||
@@ -130,7 +86,6 @@ struct cache_info { | |||
130 | /* Mask to select synonym bit(s) */ | 86 | /* Mask to select synonym bit(s) */ |
131 | #define CACHE_OC_SYN_MASK (((1UL<<CACHE_OC_N_SYNBITS)-1)<<CACHE_OC_SYN_SHIFT) | 87 | #define CACHE_OC_SYN_MASK (((1UL<<CACHE_OC_N_SYNBITS)-1)<<CACHE_OC_SYN_SHIFT) |
132 | 88 | ||
133 | |||
134 | /* | 89 | /* |
135 | * Instruction cache can't be invalidated based on physical addresses. | 90 | * Instruction cache can't be invalidated based on physical addresses. |
136 | * No Instruction Cache defines required, then. | 91 | * No Instruction Cache defines required, then. |