2 files changed, 42 insertions, 2 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b4813586d92..cd0ffa015c2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2158,11 +2158,11 @@
 #define  DREF_CPU_SOURCE_OUTPUT_MASK            (3<<13)
 #define  DREF_SSC_SOURCE_DISABLE                (0<<11)
 #define  DREF_SSC_SOURCE_ENABLE                 (2<<11)
-#define  DREF_SSC_SOURCE_MASK                   (2<<11)
+#define  DREF_SSC_SOURCE_MASK                   (3<<11)
 #define  DREF_NONSPREAD_SOURCE_DISABLE          (0<<9)
 #define  DREF_NONSPREAD_CK505_ENABLE            (1<<9)
 #define  DREF_NONSPREAD_SOURCE_ENABLE           (2<<9)
-#define  DREF_NONSPREAD_SOURCE_MASK             (2<<9)
+#define  DREF_NONSPREAD_SOURCE_MASK             (3<<9)
 #define  DREF_SUPERSPREAD_SOURCE_DISABLE        (0<<7)
 #define  DREF_SUPERSPREAD_SOURCE_ENABLE         (2<<7)
 #define  DREF_SSC4_DOWNSPREAD                   (0<<6)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 123cce1ae47..db4c3870095 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2814,6 +2814,46 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                                   link_bw, &m_n);
         }
 
+        /* Ironlake: try to setup display ref clock before DPLL
+         * enabling. This is only under driver's control after
+         * PCH B stepping, previous chipset stepping should be
+         * ignoring this setting.
+         */
+        if (IS_IGDNG(dev)) {
+                temp = I915_READ(PCH_DREF_CONTROL);
+                /* Always enable nonspread source */
+                temp &= ~DREF_NONSPREAD_SOURCE_MASK;
+                temp |= DREF_NONSPREAD_SOURCE_ENABLE;
+                I915_WRITE(PCH_DREF_CONTROL, temp);
+                POSTING_READ(PCH_DREF_CONTROL);
+
+                temp &= ~DREF_SSC_SOURCE_MASK;
+                temp |= DREF_SSC_SOURCE_ENABLE;
+                I915_WRITE(PCH_DREF_CONTROL, temp);
+                POSTING_READ(PCH_DREF_CONTROL);
+
+                udelay(200);
+
+                if (is_edp) {
+                        if (dev_priv->lvds_use_ssc) {
+                                temp |= DREF_SSC1_ENABLE;
+                                I915_WRITE(PCH_DREF_CONTROL, temp);
+                                POSTING_READ(PCH_DREF_CONTROL);
+
+                                udelay(200);
+
+                                temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
+                                temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
+                                I915_WRITE(PCH_DREF_CONTROL, temp);
+                                POSTING_READ(PCH_DREF_CONTROL);
+                        } else {
+                                temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
+                                I915_WRITE(PCH_DREF_CONTROL, temp);
+                                POSTING_READ(PCH_DREF_CONTROL);
+                        }
+                }
+        }
+
         if (IS_IGD(dev)) {
                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
                 if (has_reduced_clock)