diff options
-rw-r--r-- | arch/sh/kernel/cpu/Makefile | 9 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/irq/Makefile | 7 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/irq/imask.c (renamed from arch/sh/kernel/cpu/irq_imask.c) | 16 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/irq/intc2.c | 284 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/irq/ipr.c (renamed from arch/sh/kernel/cpu/irq_ipr.c) | 217 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/irq/pint.c | 169 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4/irq_intc2.c | 222 | ||||
-rw-r--r-- | arch/sh/kernel/irq.c | 64 | ||||
-rw-r--r-- | include/asm-sh/irq-sh7780.h | 349 | ||||
-rw-r--r-- | include/asm-sh/irq.h | 143 |
10 files changed, 963 insertions, 517 deletions
diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile index cd43714df61..5bfc33bec5d 100644 --- a/arch/sh/kernel/cpu/Makefile +++ b/arch/sh/kernel/cpu/Makefile | |||
@@ -2,15 +2,12 @@ | |||
2 | # Makefile for the Linux/SuperH CPU-specifc backends. | 2 | # Makefile for the Linux/SuperH CPU-specifc backends. |
3 | # | 3 | # |
4 | 4 | ||
5 | obj-y := irq_ipr.o irq_imask.o init.o bus.o | 5 | obj-y += irq/ init.o bus.o clock.o |
6 | 6 | ||
7 | obj-$(CONFIG_CPU_SH2) += sh2/ | 7 | obj-$(CONFIG_CPU_SH2) += sh2/ |
8 | obj-$(CONFIG_CPU_SH3) += sh3/ | 8 | obj-$(CONFIG_CPU_SH3) += sh3/ |
9 | obj-$(CONFIG_CPU_SH4) += sh4/ | 9 | obj-$(CONFIG_CPU_SH4) += sh4/ |
10 | 10 | ||
11 | obj-$(CONFIG_SH_RTC) += rtc.o | 11 | obj-$(CONFIG_SH_RTC) += rtc.o |
12 | obj-$(CONFIG_UBC_WAKEUP) += ubc.o | 12 | obj-$(CONFIG_UBC_WAKEUP) += ubc.o |
13 | obj-$(CONFIG_SH_ADC) += adc.o | 13 | obj-$(CONFIG_SH_ADC) += adc.o |
14 | |||
15 | USE_STANDARD_AS_RULE := true | ||
16 | |||
diff --git a/arch/sh/kernel/cpu/irq/Makefile b/arch/sh/kernel/cpu/irq/Makefile new file mode 100644 index 00000000000..e3cccea15e1 --- /dev/null +++ b/arch/sh/kernel/cpu/irq/Makefile | |||
@@ -0,0 +1,7 @@ | |||
1 | # | ||
2 | # Makefile for the Linux/SuperH CPU-specifc IRQ handlers. | ||
3 | # | ||
4 | obj-y += ipr.o imask.o | ||
5 | |||
6 | obj-$(CONFIG_CPU_HAS_PINT_IRQ) += pint.o | ||
7 | obj-$(CONFIG_CPU_HAS_INTC2_IRQ) += intc2.o | ||
diff --git a/arch/sh/kernel/cpu/irq_imask.c b/arch/sh/kernel/cpu/irq/imask.c index a963d00a971..baed9a550d3 100644 --- a/arch/sh/kernel/cpu/irq_imask.c +++ b/arch/sh/kernel/cpu/irq/imask.c | |||
@@ -1,16 +1,12 @@ | |||
1 | /* $Id: irq_imask.c,v 1.1.2.1 2002/11/17 10:53:43 mrbrown Exp $ | 1 | /* |
2 | * | 2 | * arch/sh/kernel/cpu/irq/imask.c |
3 | * linux/arch/sh/kernel/irq_imask.c | ||
4 | * | 3 | * |
5 | * Copyright (C) 1999, 2000 Niibe Yutaka | 4 | * Copyright (C) 1999, 2000 Niibe Yutaka |
6 | * | 5 | * |
7 | * Simple interrupt handling using IMASK of SR register. | 6 | * Simple interrupt handling using IMASK of SR register. |
8 | * | 7 | * |
9 | */ | 8 | */ |
10 | |||
11 | /* NOTE: Will not work on level 15 */ | 9 | /* NOTE: Will not work on level 15 */ |
12 | |||
13 | |||
14 | #include <linux/ptrace.h> | 10 | #include <linux/ptrace.h> |
15 | #include <linux/errno.h> | 11 | #include <linux/errno.h> |
16 | #include <linux/kernel_stat.h> | 12 | #include <linux/kernel_stat.h> |
@@ -19,13 +15,11 @@ | |||
19 | #include <linux/interrupt.h> | 15 | #include <linux/interrupt.h> |
20 | #include <linux/init.h> | 16 | #include <linux/init.h> |
21 | #include <linux/bitops.h> | 17 | #include <linux/bitops.h> |
22 | |||
23 | #include <asm/system.h> | ||
24 | #include <asm/irq.h> | ||
25 | |||
26 | #include <linux/spinlock.h> | 18 | #include <linux/spinlock.h> |
27 | #include <linux/cache.h> | 19 | #include <linux/cache.h> |
28 | #include <linux/irq.h> | 20 | #include <linux/irq.h> |
21 | #include <asm/system.h> | ||
22 | #include <asm/irq.h> | ||
29 | 23 | ||
30 | /* Bitmap of IRQ masked */ | 24 | /* Bitmap of IRQ masked */ |
31 | static unsigned long imask_mask = 0x7fff; | 25 | static unsigned long imask_mask = 0x7fff; |
@@ -40,7 +34,7 @@ static void end_imask_irq(unsigned int irq); | |||
40 | #define IMASK_PRIORITY 15 | 34 | #define IMASK_PRIORITY 15 |
41 | 35 | ||
42 | static unsigned int startup_imask_irq(unsigned int irq) | 36 | static unsigned int startup_imask_irq(unsigned int irq) |
43 | { | 37 | { |
44 | /* Nothing to do */ | 38 | /* Nothing to do */ |
45 | return 0; /* never anything pending */ | 39 | return 0; /* never anything pending */ |
46 | } | 40 | } |
diff --git a/arch/sh/kernel/cpu/irq/intc2.c b/arch/sh/kernel/cpu/irq/intc2.c new file mode 100644 index 00000000000..06e8afab32e --- /dev/null +++ b/arch/sh/kernel/cpu/irq/intc2.c | |||
@@ -0,0 +1,284 @@ | |||
1 | /* | ||
2 | * Interrupt handling for INTC2-based IRQ. | ||
3 | * | ||
4 | * Copyright (C) 2001 David J. Mckay (david.mckay@st.com) | ||
5 | * Copyright (C) 2005, 2006 Paul Mundt (lethal@linux-sh.org) | ||
6 | * | ||
7 | * May be copied or modified under the terms of the GNU General Public | ||
8 | * License. See linux/COPYING for more information. | ||
9 | * | ||
10 | * These are the "new Hitachi style" interrupts, as present on the | ||
11 | * Hitachi 7751, the STM ST40 STB1, SH7760, and SH7780. | ||
12 | */ | ||
13 | |||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/init.h> | ||
16 | #include <linux/irq.h> | ||
17 | #include <asm/system.h> | ||
18 | #include <asm/io.h> | ||
19 | #include <asm/machvec.h> | ||
20 | |||
21 | struct intc2_data { | ||
22 | unsigned char msk_offset; | ||
23 | unsigned char msk_shift; | ||
24 | |||
25 | int (*clear_irq) (int); | ||
26 | }; | ||
27 | |||
28 | static struct intc2_data intc2_data[NR_INTC2_IRQS]; | ||
29 | |||
30 | static void enable_intc2_irq(unsigned int irq); | ||
31 | static void disable_intc2_irq(unsigned int irq); | ||
32 | |||
33 | /* shutdown is same as "disable" */ | ||
34 | #define shutdown_intc2_irq disable_intc2_irq | ||
35 | |||
36 | static void mask_and_ack_intc2(unsigned int); | ||
37 | static void end_intc2_irq(unsigned int irq); | ||
38 | |||
39 | static unsigned int startup_intc2_irq(unsigned int irq) | ||
40 | { | ||
41 | enable_intc2_irq(irq); | ||
42 | return 0; /* never anything pending */ | ||
43 | } | ||
44 | |||
45 | static struct hw_interrupt_type intc2_irq_type = { | ||
46 | .typename = "INTC2-IRQ", | ||
47 | .startup = startup_intc2_irq, | ||
48 | .shutdown = shutdown_intc2_irq, | ||
49 | .enable = enable_intc2_irq, | ||
50 | .disable = disable_intc2_irq, | ||
51 | .ack = mask_and_ack_intc2, | ||
52 | .end = end_intc2_irq | ||
53 | }; | ||
54 | |||
55 | static void disable_intc2_irq(unsigned int irq) | ||
56 | { | ||
57 | int irq_offset = irq - INTC2_FIRST_IRQ; | ||
58 | int msk_shift, msk_offset; | ||
59 | |||
60 | /* Sanity check */ | ||
61 | if (unlikely(irq_offset < 0 || irq_offset >= NR_INTC2_IRQS)) | ||
62 | return; | ||
63 | |||
64 | msk_shift = intc2_data[irq_offset].msk_shift; | ||
65 | msk_offset = intc2_data[irq_offset].msk_offset; | ||
66 | |||
67 | ctrl_outl(1 << msk_shift, | ||
68 | INTC2_BASE + INTC2_INTMSK_OFFSET + msk_offset); | ||
69 | } | ||
70 | |||
71 | static void enable_intc2_irq(unsigned int irq) | ||
72 | { | ||
73 | int irq_offset = irq - INTC2_FIRST_IRQ; | ||
74 | int msk_shift, msk_offset; | ||
75 | |||
76 | /* Sanity check */ | ||
77 | if (unlikely(irq_offset < 0 || irq_offset >= NR_INTC2_IRQS)) | ||
78 | return; | ||
79 | |||
80 | msk_shift = intc2_data[irq_offset].msk_shift; | ||
81 | msk_offset = intc2_data[irq_offset].msk_offset; | ||
82 | |||
83 | ctrl_outl(1 << msk_shift, | ||
84 | INTC2_BASE + INTC2_INTMSKCLR_OFFSET + msk_offset); | ||
85 | } | ||
86 | |||
87 | static void mask_and_ack_intc2(unsigned int irq) | ||
88 | { | ||
89 | disable_intc2_irq(irq); | ||
90 | } | ||
91 | |||
92 | static void end_intc2_irq(unsigned int irq) | ||
93 | { | ||
94 | if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) | ||
95 | enable_intc2_irq(irq); | ||
96 | |||
97 | if (unlikely(intc2_data[irq - INTC2_FIRST_IRQ].clear_irq)) | ||
98 | intc2_data[irq - INTC2_FIRST_IRQ].clear_irq(irq); | ||
99 | } | ||
100 | |||
101 | /* | ||
102 | * Setup an INTC2 style interrupt. | ||
103 | * NOTE: Unlike IPR interrupts, parameters are not shifted by this code, | ||
104 | * allowing the use of the numbers straight out of the datasheet. | ||
105 | * For example: | ||
106 | * PIO1 which is INTPRI00[19,16] and INTMSK00[13] | ||
107 | * would be: ^ ^ ^ ^ | ||
108 | * | | | | | ||
109 | * make_intc2_irq(84, 0, 16, 0, 13); | ||
110 | */ | ||
111 | void make_intc2_irq(unsigned int irq, | ||
112 | unsigned int ipr_offset, unsigned int ipr_shift, | ||
113 | unsigned int msk_offset, unsigned int msk_shift, | ||
114 | unsigned int priority) | ||
115 | { | ||
116 | int irq_offset = irq - INTC2_FIRST_IRQ; | ||
117 | unsigned int flags; | ||
118 | unsigned long ipr; | ||
119 | |||
120 | if (unlikely(irq_offset < 0 || irq_offset >= NR_INTC2_IRQS)) | ||
121 | return; | ||
122 | |||
123 | disable_irq_nosync(irq); | ||
124 | |||
125 | /* Fill the data we need */ | ||
126 | intc2_data[irq_offset].msk_offset = msk_offset; | ||
127 | intc2_data[irq_offset].msk_shift = msk_shift; | ||
128 | intc2_data[irq_offset].clear_irq = NULL; | ||
129 | |||
130 | /* Set the priority level */ | ||
131 | local_irq_save(flags); | ||
132 | |||
133 | ipr = ctrl_inl(INTC2_BASE + INTC2_INTPRI_OFFSET + ipr_offset); | ||
134 | ipr &= ~(0xf << ipr_shift); | ||
135 | ipr |= priority << ipr_shift; | ||
136 | ctrl_outl(ipr, INTC2_BASE + INTC2_INTPRI_OFFSET + ipr_offset); | ||
137 | |||
138 | local_irq_restore(flags); | ||
139 | |||
140 | irq_desc[irq].handler = &intc2_irq_type; | ||
141 | |||
142 | disable_intc2_irq(irq); | ||
143 | } | ||
144 | |||
145 | static struct intc2_init { | ||
146 | unsigned short irq; | ||
147 | unsigned char ipr_offset, ipr_shift; | ||
148 | unsigned char msk_offset, msk_shift; | ||
149 | unsigned char priority; | ||
150 | } intc2_init_data[] __initdata = { | ||
151 | #if defined(CONFIG_CPU_SUBTYPE_ST40) | ||
152 | {64, 0, 0, 0, 0, 13}, /* PCI serr */ | ||
153 | {65, 0, 4, 0, 1, 13}, /* PCI err */ | ||
154 | {66, 0, 4, 0, 2, 13}, /* PCI ad */ | ||
155 | {67, 0, 4, 0, 3, 13}, /* PCI pwd down */ | ||
156 | {72, 0, 8, 0, 5, 13}, /* DMAC INT0 */ | ||
157 | {73, 0, 8, 0, 6, 13}, /* DMAC INT1 */ | ||
158 | {74, 0, 8, 0, 7, 13}, /* DMAC INT2 */ | ||
159 | {75, 0, 8, 0, 8, 13}, /* DMAC INT3 */ | ||
160 | {76, 0, 8, 0, 9, 13}, /* DMAC INT4 */ | ||
161 | {78, 0, 8, 0, 11, 13}, /* DMAC ERR */ | ||
162 | {80, 0, 12, 0, 12, 13}, /* PIO0 */ | ||
163 | {84, 0, 16, 0, 13, 13}, /* PIO1 */ | ||
164 | {88, 0, 20, 0, 14, 13}, /* PIO2 */ | ||
165 | {112, 4, 0, 4, 0, 13}, /* Mailbox */ | ||
166 | #ifdef CONFIG_CPU_SUBTYPE_ST40GX1 | ||
167 | {116, 4, 4, 4, 4, 13}, /* SSC0 */ | ||
168 | {120, 4, 8, 4, 8, 13}, /* IR Blaster */ | ||
169 | {124, 4, 12, 4, 12, 13}, /* USB host */ | ||
170 | {128, 4, 16, 4, 16, 13}, /* Video processor BLITTER */ | ||
171 | {132, 4, 20, 4, 20, 13}, /* UART0 */ | ||
172 | {134, 4, 20, 4, 22, 13}, /* UART2 */ | ||
173 | {136, 4, 24, 4, 24, 13}, /* IO_PIO0 */ | ||
174 | {140, 4, 28, 4, 28, 13}, /* EMPI */ | ||
175 | {144, 8, 0, 8, 0, 13}, /* MAFE */ | ||
176 | {148, 8, 4, 8, 4, 13}, /* PWM */ | ||
177 | {152, 8, 8, 8, 8, 13}, /* SSC1 */ | ||
178 | {156, 8, 12, 8, 12, 13}, /* IO_PIO1 */ | ||
179 | {160, 8, 16, 8, 16, 13}, /* USB target */ | ||
180 | {164, 8, 20, 8, 20, 13}, /* UART1 */ | ||
181 | {168, 8, 24, 8, 24, 13}, /* Teletext */ | ||
182 | {172, 8, 28, 8, 28, 13}, /* VideoSync VTG */ | ||
183 | {173, 8, 28, 8, 29, 13}, /* VideoSync DVP0 */ | ||
184 | {174, 8, 28, 8, 30, 13}, /* VideoSync DVP1 */ | ||
185 | #endif | ||
186 | #elif defined(CONFIG_CPU_SUBTYPE_SH7760) | ||
187 | /* | ||
188 | * SH7760 INTC2-Style interrupts, vectors IRQ48-111 INTEVT 0x800-0xFE0 | ||
189 | */ | ||
190 | /* INTPRIO0 | INTMSK0 */ | ||
191 | {48, 0, 28, 0, 31, 3}, /* IRQ 4 */ | ||
192 | {49, 0, 24, 0, 30, 3}, /* IRQ 3 */ | ||
193 | {50, 0, 20, 0, 29, 3}, /* IRQ 2 */ | ||
194 | {51, 0, 16, 0, 28, 3}, /* IRQ 1 */ | ||
195 | /* 52-55 (INTEVT 0x880-0x8E0) unused/reserved */ | ||
196 | /* INTPRIO4 | INTMSK0 */ | ||
197 | {56, 4, 28, 0, 25, 3}, /* HCAN2_CHAN0 */ | ||
198 | {57, 4, 24, 0, 24, 3}, /* HCAN2_CHAN1 */ | ||
199 | {58, 4, 20, 0, 23, 3}, /* I2S_CHAN0 */ | ||
200 | {59, 4, 16, 0, 22, 3}, /* I2S_CHAN1 */ | ||
201 | {60, 4, 12, 0, 21, 3}, /* AC97_CHAN0 */ | ||
202 | {61, 4, 8, 0, 20, 3}, /* AC97_CHAN1 */ | ||
203 | {62, 4, 4, 0, 19, 3}, /* I2C_CHAN0 */ | ||
204 | {63, 4, 0, 0, 18, 3}, /* I2C_CHAN1 */ | ||
205 | /* INTPRIO8 | INTMSK0 */ | ||
206 | {52, 8, 16, 0, 11, 3}, /* SCIF0_ERI_IRQ */ | ||
207 | {53, 8, 16, 0, 10, 3}, /* SCIF0_RXI_IRQ */ | ||
208 | {54, 8, 16, 0, 9, 3}, /* SCIF0_BRI_IRQ */ | ||
209 | {55, 8, 16, 0, 8, 3}, /* SCIF0_TXI_IRQ */ | ||
210 | {64, 8, 28, 0, 17, 3}, /* USBHI_IRQ */ | ||
211 | {65, 8, 24, 0, 16, 3}, /* LCDC */ | ||
212 | /* 66, 67 unused */ | ||
213 | {68, 8, 20, 0, 14, 13}, /* DMABRGI0_IRQ */ | ||
214 | {69, 8, 20, 0, 13, 13}, /* DMABRGI1_IRQ */ | ||
215 | {70, 8, 20, 0, 12, 13}, /* DMABRGI2_IRQ */ | ||
216 | /* 71 unused */ | ||
217 | {72, 8, 12, 0, 7, 3}, /* SCIF1_ERI_IRQ */ | ||
218 | {73, 8, 12, 0, 6, 3}, /* SCIF1_RXI_IRQ */ | ||
219 | {74, 8, 12, 0, 5, 3}, /* SCIF1_BRI_IRQ */ | ||
220 | {75, 8, 12, 0, 4, 3}, /* SCIF1_TXI_IRQ */ | ||
221 | {76, 8, 8, 0, 3, 3}, /* SCIF2_ERI_IRQ */ | ||
222 | {77, 8, 8, 0, 2, 3}, /* SCIF2_RXI_IRQ */ | ||
223 | {78, 8, 8, 0, 1, 3}, /* SCIF2_BRI_IRQ */ | ||
224 | {79, 8, 8, 0, 0, 3}, /* SCIF2_TXI_IRQ */ | ||
225 | /* | INTMSK4 */ | ||
226 | {80, 8, 4, 4, 23, 3}, /* SIM_ERI */ | ||
227 | {81, 8, 4, 4, 22, 3}, /* SIM_RXI */ | ||
228 | {82, 8, 4, 4, 21, 3}, /* SIM_TXI */ | ||
229 | {83, 8, 4, 4, 20, 3}, /* SIM_TEI */ | ||
230 | {84, 8, 0, 4, 19, 3}, /* HSPII */ | ||
231 | /* INTPRIOC | INTMSK4 */ | ||
232 | /* 85-87 unused/reserved */ | ||
233 | {88, 12, 20, 4, 18, 3}, /* MMCI0 */ | ||
234 | {89, 12, 20, 4, 17, 3}, /* MMCI1 */ | ||
235 | {90, 12, 20, 4, 16, 3}, /* MMCI2 */ | ||
236 | {91, 12, 20, 4, 15, 3}, /* MMCI3 */ | ||
237 | {92, 12, 12, 4, 6, 3}, /* MFI (unsure, bug? in my 7760 manual*/ | ||
238 | /* 93-107 reserved/undocumented */ | ||
239 | {108,12, 4, 4, 1, 3}, /* ADC */ | ||
240 | {109,12, 0, 4, 0, 3}, /* CMTI */ | ||
241 | /* 110-111 reserved/unused */ | ||
242 | #elif defined(CONFIG_CPU_SUBTYPE_SH7780) | ||
243 | { TIMER_IRQ, 0, 24, 0, INTC_TMU0_MSK, 2}, | ||
244 | #ifdef CONFIG_SH_RTC | ||
245 | { RTC_IRQ, 4, 0, 0, INTC_RTC_MSK, TIMER_PRIORITY }, | ||
246 | #endif | ||
247 | { SCIF0_ERI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY }, | ||
248 | { SCIF0_RXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY }, | ||
249 | { SCIF0_BRI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY }, | ||
250 | { SCIF0_TXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY }, | ||
251 | |||
252 | { SCIF1_ERI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY }, | ||
253 | { SCIF1_RXI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY }, | ||
254 | { SCIF1_BRI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY }, | ||
255 | { SCIF1_TXI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY }, | ||
256 | |||
257 | { PCIC0_IRQ, 0x10, 8, 0, INTC_PCIC0_MSK, PCIC0_PRIORITY }, | ||
258 | { PCIC1_IRQ, 0x10, 0, 0, INTC_PCIC1_MSK, PCIC1_PRIORITY }, | ||
259 | { PCIC2_IRQ, 0x14, 24, 0, INTC_PCIC2_MSK, PCIC2_PRIORITY }, | ||
260 | { PCIC3_IRQ, 0x14, 16, 0, INTC_PCIC3_MSK, PCIC3_PRIORITY }, | ||
261 | { PCIC4_IRQ, 0x14, 8, 0, INTC_PCIC4_MSK, PCIC4_PRIORITY }, | ||
262 | #endif | ||
263 | }; | ||
264 | |||
265 | void __init init_IRQ_intc2(void) | ||
266 | { | ||
267 | int i; | ||
268 | |||
269 | for (i = 0; i < ARRAY_SIZE(intc2_init_data); i++) { | ||
270 | struct intc2_init *p = intc2_init_data + i; | ||
271 | make_intc2_irq(p->irq, p->ipr_offset, p->ipr_shift, | ||
272 | p-> msk_offset, p->msk_shift, p->priority); | ||
273 | } | ||
274 | } | ||
275 | |||
276 | /* Adds a termination callback to the interrupt */ | ||
277 | void intc2_add_clear_irq(int irq, int (*fn)(int)) | ||
278 | { | ||
279 | if (unlikely(irq < INTC2_FIRST_IRQ)) | ||
280 | return; | ||
281 | |||
282 | intc2_data[irq - INTC2_FIRST_IRQ].clear_irq = fn; | ||
283 | } | ||
284 | |||
diff --git a/arch/sh/kernel/cpu/irq_ipr.c b/arch/sh/kernel/cpu/irq/ipr.c index 71f92096132..fdbd718ae5c 100644 --- a/arch/sh/kernel/cpu/irq_ipr.c +++ b/arch/sh/kernel/cpu/irq/ipr.c | |||
@@ -1,6 +1,5 @@ | |||
1 | /* $Id: irq_ipr.c,v 1.1.2.1 2002/11/17 10:53:43 mrbrown Exp $ | 1 | /* |
2 | * | 2 | * arch/sh/kernel/cpu/irq/ipr.c |
3 | * linux/arch/sh/kernel/irq_ipr.c | ||
4 | * | 3 | * |
5 | * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi | 4 | * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi |
6 | * Copyright (C) 2000 Kazumoto Kojima | 5 | * Copyright (C) 2000 Kazumoto Kojima |
@@ -109,7 +108,8 @@ static void end_ipr_irq(unsigned int irq) | |||
109 | enable_ipr_irq(irq); | 108 | enable_ipr_irq(irq); |
110 | } | 109 | } |
111 | 110 | ||
112 | void make_ipr_irq(unsigned int irq, unsigned int addr, int pos, int priority) | 111 | void make_ipr_irq(unsigned int irq, unsigned int addr, int pos, |
112 | int priority, int maskpos) | ||
113 | { | 113 | { |
114 | disable_irq_nosync(irq); | 114 | disable_irq_nosync(irq); |
115 | ipr_data[irq].addr = addr; | 115 | ipr_data[irq].addr = addr; |
@@ -120,126 +120,47 @@ void make_ipr_irq(unsigned int irq, unsigned int addr, int pos, int priority) | |||
120 | disable_ipr_irq(irq); | 120 | disable_ipr_irq(irq); |
121 | } | 121 | } |
122 | 122 | ||
123 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ | ||
124 | defined(CONFIG_CPU_SUBTYPE_SH7707) || \ | ||
125 | defined(CONFIG_CPU_SUBTYPE_SH7709) | ||
126 | static unsigned char pint_map[256]; | ||
127 | static unsigned long portcr_mask = 0; | ||
128 | |||
129 | static void enable_pint_irq(unsigned int irq); | ||
130 | static void disable_pint_irq(unsigned int irq); | ||
131 | |||
132 | /* shutdown is same as "disable" */ | ||
133 | #define shutdown_pint_irq disable_pint_irq | ||
134 | |||
135 | static void mask_and_ack_pint(unsigned int); | ||
136 | static void end_pint_irq(unsigned int irq); | ||
137 | |||
138 | static unsigned int startup_pint_irq(unsigned int irq) | ||
139 | { | ||
140 | enable_pint_irq(irq); | ||
141 | return 0; /* never anything pending */ | ||
142 | } | ||
143 | |||
144 | static struct hw_interrupt_type pint_irq_type = { | ||
145 | .typename = "PINT-IRQ", | ||
146 | .startup = startup_pint_irq, | ||
147 | .shutdown = shutdown_pint_irq, | ||
148 | .enable = enable_pint_irq, | ||
149 | .disable = disable_pint_irq, | ||
150 | .ack = mask_and_ack_pint, | ||
151 | .end = end_pint_irq | ||
152 | }; | ||
153 | |||
154 | static void disable_pint_irq(unsigned int irq) | ||
155 | { | ||
156 | unsigned long val, flags; | ||
157 | |||
158 | local_irq_save(flags); | ||
159 | val = ctrl_inw(INTC_INTER); | ||
160 | val &= ~(1 << (irq - PINT_IRQ_BASE)); | ||
161 | ctrl_outw(val, INTC_INTER); /* disable PINTn */ | ||
162 | portcr_mask &= ~(3 << (irq - PINT_IRQ_BASE)*2); | ||
163 | local_irq_restore(flags); | ||
164 | } | ||
165 | |||
166 | static void enable_pint_irq(unsigned int irq) | ||
167 | { | ||
168 | unsigned long val, flags; | ||
169 | |||
170 | local_irq_save(flags); | ||
171 | val = ctrl_inw(INTC_INTER); | ||
172 | val |= 1 << (irq - PINT_IRQ_BASE); | ||
173 | ctrl_outw(val, INTC_INTER); /* enable PINTn */ | ||
174 | portcr_mask |= 3 << (irq - PINT_IRQ_BASE)*2; | ||
175 | local_irq_restore(flags); | ||
176 | } | ||
177 | |||
178 | static void mask_and_ack_pint(unsigned int irq) | ||
179 | { | ||
180 | disable_pint_irq(irq); | ||
181 | } | ||
182 | |||
183 | static void end_pint_irq(unsigned int irq) | ||
184 | { | ||
185 | if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) | ||
186 | enable_pint_irq(irq); | ||
187 | } | ||
188 | |||
189 | void make_pint_irq(unsigned int irq) | ||
190 | { | ||
191 | disable_irq_nosync(irq); | ||
192 | irq_desc[irq].handler = &pint_irq_type; | ||
193 | disable_pint_irq(irq); | ||
194 | } | ||
195 | #endif | ||
196 | |||
197 | void __init init_IRQ(void) | 123 | void __init init_IRQ(void) |
198 | { | 124 | { |
199 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ | 125 | #ifndef CONFIG_CPU_SUBTYPE_SH7780 |
200 | defined(CONFIG_CPU_SUBTYPE_SH7707) || \ | 126 | make_ipr_irq(TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY, 0); |
201 | defined(CONFIG_CPU_SUBTYPE_SH7709) | 127 | make_ipr_irq(TIMER1_IRQ, TIMER1_IPR_ADDR, TIMER1_IPR_POS, TIMER1_PRIORITY, 0); |
202 | int i; | ||
203 | #endif | ||
204 | |||
205 | make_ipr_irq(TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY); | ||
206 | make_ipr_irq(TIMER1_IRQ, TIMER1_IPR_ADDR, TIMER1_IPR_POS, TIMER1_PRIORITY); | ||
207 | #if defined(CONFIG_SH_RTC) | 128 | #if defined(CONFIG_SH_RTC) |
208 | make_ipr_irq(RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY); | 129 | make_ipr_irq(RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY, 0); |
209 | #endif | 130 | #endif |
210 | 131 | ||
211 | #ifdef SCI_ERI_IRQ | 132 | #ifdef SCI_ERI_IRQ |
212 | make_ipr_irq(SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY); | 133 | make_ipr_irq(SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY, 0); |
213 | make_ipr_irq(SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY); | 134 | make_ipr_irq(SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY, 0); |
214 | make_ipr_irq(SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY); | 135 | make_ipr_irq(SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY, 0); |
215 | #endif | 136 | #endif |
216 | 137 | ||
217 | #ifdef SCIF1_ERI_IRQ | 138 | #ifdef SCIF1_ERI_IRQ |
218 | make_ipr_irq(SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY); | 139 | make_ipr_irq(SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY, 0); |
219 | make_ipr_irq(SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY); | 140 | make_ipr_irq(SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY, 0); |
220 | make_ipr_irq(SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY); | 141 | make_ipr_irq(SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY, 0); |
221 | make_ipr_irq(SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY); | 142 | make_ipr_irq(SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY, 0); |
222 | #endif | 143 | #endif |
223 | 144 | ||
224 | #if defined(CONFIG_CPU_SUBTYPE_SH7300) | 145 | #if defined(CONFIG_CPU_SUBTYPE_SH7300) |
225 | make_ipr_irq(SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY); | 146 | make_ipr_irq(SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY, 0); |
226 | make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY); | 147 | make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY, 0); |
227 | make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY); | 148 | make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY, 0); |
228 | make_ipr_irq(VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY); | 149 | make_ipr_irq(VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY, 0); |
229 | #endif | 150 | #endif |
230 | 151 | ||
231 | #ifdef SCIF_ERI_IRQ | 152 | #ifdef SCIF_ERI_IRQ |
232 | make_ipr_irq(SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY); | 153 | make_ipr_irq(SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY, 0); |
233 | make_ipr_irq(SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY); | 154 | make_ipr_irq(SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY, 0); |
234 | make_ipr_irq(SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY); | 155 | make_ipr_irq(SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY, 0); |
235 | make_ipr_irq(SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY); | 156 | make_ipr_irq(SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY, 0); |
236 | #endif | 157 | #endif |
237 | 158 | ||
238 | #ifdef IRDA_ERI_IRQ | 159 | #ifdef IRDA_ERI_IRQ |
239 | make_ipr_irq(IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY); | 160 | make_ipr_irq(IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY, 0); |
240 | make_ipr_irq(IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY); | 161 | make_ipr_irq(IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY, 0); |
241 | make_ipr_irq(IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY); | 162 | make_ipr_irq(IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY, 0); |
242 | make_ipr_irq(IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY); | 163 | make_ipr_irq(IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY, 0); |
243 | #endif | 164 | #endif |
244 | 165 | ||
245 | #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \ | 166 | #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \ |
@@ -254,86 +175,32 @@ void __init init_IRQ(void) | |||
254 | * You should set corresponding bits of PFC to "00" | 175 | * You should set corresponding bits of PFC to "00" |
255 | * to enable these interrupts. | 176 | * to enable these interrupts. |
256 | */ | 177 | */ |
257 | make_ipr_irq(IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY); | 178 | make_ipr_irq(IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY, 0); |
258 | make_ipr_irq(IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY); | 179 | make_ipr_irq(IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY, 0); |
259 | make_ipr_irq(IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY); | 180 | make_ipr_irq(IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY, 0); |
260 | make_ipr_irq(IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY); | 181 | make_ipr_irq(IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY, 0); |
261 | make_ipr_irq(IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY); | 182 | make_ipr_irq(IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY, 0); |
262 | make_ipr_irq(IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY); | 183 | make_ipr_irq(IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY, 0); |
263 | #if !defined(CONFIG_CPU_SUBTYPE_SH7300) | 184 | #endif |
264 | make_ipr_irq(PINT0_IRQ, PINT0_IPR_ADDR, PINT0_IPR_POS, PINT0_PRIORITY); | 185 | #endif |
265 | make_ipr_irq(PINT8_IRQ, PINT8_IPR_ADDR, PINT8_IPR_POS, PINT8_PRIORITY); | ||
266 | enable_ipr_irq(PINT0_IRQ); | ||
267 | enable_ipr_irq(PINT8_IRQ); | ||
268 | 186 | ||
269 | for(i = 0; i < 16; i++) | 187 | #ifdef CONFIG_CPU_HAS_PINT_IRQ |
270 | make_pint_irq(PINT_IRQ_BASE + i); | 188 | init_IRQ_pint(); |
271 | for(i = 0; i < 256; i++) | 189 | #endif |
272 | { | ||
273 | if(i & 1) pint_map[i] = 0; | ||
274 | else if(i & 2) pint_map[i] = 1; | ||
275 | else if(i & 4) pint_map[i] = 2; | ||
276 | else if(i & 8) pint_map[i] = 3; | ||
277 | else if(i & 0x10) pint_map[i] = 4; | ||
278 | else if(i & 0x20) pint_map[i] = 5; | ||
279 | else if(i & 0x40) pint_map[i] = 6; | ||
280 | else if(i & 0x80) pint_map[i] = 7; | ||
281 | } | ||
282 | #endif /* !CONFIG_CPU_SUBTYPE_SH7300 */ | ||
283 | #endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 || CONFIG_CPU_SUBTYPE_SH7300*/ | ||
284 | 190 | ||
285 | #ifdef CONFIG_CPU_SUBTYPE_ST40 | 191 | #ifdef CONFIG_CPU_HAS_INTC2_IRQ |
286 | init_IRQ_intc2(); | 192 | init_IRQ_intc2(); |
287 | #endif | 193 | #endif |
288 | |||
289 | /* Perform the machine specific initialisation */ | 194 | /* Perform the machine specific initialisation */ |
290 | if (sh_mv.mv_init_irq != NULL) { | 195 | if (sh_mv.mv_init_irq != NULL) |
291 | sh_mv.mv_init_irq(); | 196 | sh_mv.mv_init_irq(); |
292 | } | ||
293 | } | 197 | } |
294 | #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \ | 198 | |
295 | defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) | 199 | #if !defined(CONFIG_CPU_HAS_PINT_IRQ) |
296 | int ipr_irq_demux(int irq) | 200 | int ipr_irq_demux(int irq) |
297 | { | 201 | { |
298 | #if !defined(CONFIG_CPU_SUBTYPE_SH7300) | ||
299 | unsigned long creg, dreg, d, sav; | ||
300 | |||
301 | if(irq == PINT0_IRQ) | ||
302 | { | ||
303 | #if defined(CONFIG_CPU_SUBTYPE_SH7707) | ||
304 | creg = PORT_PACR; | ||
305 | dreg = PORT_PADR; | ||
306 | #else | ||
307 | creg = PORT_PCCR; | ||
308 | dreg = PORT_PCDR; | ||
309 | #endif | ||
310 | sav = ctrl_inw(creg); | ||
311 | ctrl_outw(sav | portcr_mask, creg); | ||
312 | d = (~ctrl_inb(dreg) ^ ctrl_inw(INTC_ICR2)) & ctrl_inw(INTC_INTER) & 0xff; | ||
313 | ctrl_outw(sav, creg); | ||
314 | if(d == 0) return irq; | ||
315 | return PINT_IRQ_BASE + pint_map[d]; | ||
316 | } | ||
317 | else if(irq == PINT8_IRQ) | ||
318 | { | ||
319 | #if defined(CONFIG_CPU_SUBTYPE_SH7707) | ||
320 | creg = PORT_PBCR; | ||
321 | dreg = PORT_PBDR; | ||
322 | #else | ||
323 | creg = PORT_PFCR; | ||
324 | dreg = PORT_PFDR; | ||
325 | #endif | ||
326 | sav = ctrl_inw(creg); | ||
327 | ctrl_outw(sav | (portcr_mask >> 16), creg); | ||
328 | d = (~ctrl_inb(dreg) ^ (ctrl_inw(INTC_ICR2) >> 8)) & (ctrl_inw(INTC_INTER) >> 8) & 0xff; | ||
329 | ctrl_outw(sav, creg); | ||
330 | if(d == 0) return irq; | ||
331 | return PINT_IRQ_BASE + 8 + pint_map[d]; | ||
332 | } | ||
333 | #endif | ||
334 | return irq; | 202 | return irq; |
335 | } | 203 | } |
336 | #endif | 204 | #endif |
337 | 205 | ||
338 | EXPORT_SYMBOL(make_ipr_irq); | 206 | EXPORT_SYMBOL(make_ipr_irq); |
339 | |||
diff --git a/arch/sh/kernel/cpu/irq/pint.c b/arch/sh/kernel/cpu/irq/pint.c new file mode 100644 index 00000000000..95d6024fe1a --- /dev/null +++ b/arch/sh/kernel/cpu/irq/pint.c | |||
@@ -0,0 +1,169 @@ | |||
1 | /* | ||
2 | * arch/sh/kernel/cpu/irq/pint.c - Interrupt handling for PINT-based IRQs. | ||
3 | * | ||
4 | * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi | ||
5 | * Copyright (C) 2000 Kazumoto Kojima | ||
6 | * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp> | ||
7 | * | ||
8 | * This file is subject to the terms and conditions of the GNU General Public | ||
9 | * License. See the file "COPYING" in the main directory of this archive | ||
10 | * for more details. | ||
11 | */ | ||
12 | |||
13 | #include <linux/config.h> | ||
14 | #include <linux/init.h> | ||
15 | #include <linux/irq.h> | ||
16 | #include <linux/module.h> | ||
17 | |||
18 | #include <asm/system.h> | ||
19 | #include <asm/io.h> | ||
20 | #include <asm/machvec.h> | ||
21 | |||
22 | static unsigned char pint_map[256]; | ||
23 | static unsigned long portcr_mask; | ||
24 | |||
25 | static void enable_pint_irq(unsigned int irq); | ||
26 | static void disable_pint_irq(unsigned int irq); | ||
27 | |||
28 | /* shutdown is same as "disable" */ | ||
29 | #define shutdown_pint_irq disable_pint_irq | ||
30 | |||
31 | static void mask_and_ack_pint(unsigned int); | ||
32 | static void end_pint_irq(unsigned int irq); | ||
33 | |||
34 | static unsigned int startup_pint_irq(unsigned int irq) | ||
35 | { | ||
36 | enable_pint_irq(irq); | ||
37 | return 0; /* never anything pending */ | ||
38 | } | ||
39 | |||
40 | static struct hw_interrupt_type pint_irq_type = { | ||
41 | .typename = "PINT-IRQ", | ||
42 | .startup = startup_pint_irq, | ||
43 | .shutdown = shutdown_pint_irq, | ||
44 | .enable = enable_pint_irq, | ||
45 | .disable = disable_pint_irq, | ||
46 | .ack = mask_and_ack_pint, | ||
47 | .end = end_pint_irq | ||
48 | }; | ||
49 | |||
50 | static void disable_pint_irq(unsigned int irq) | ||
51 | { | ||
52 | unsigned long val, flags; | ||
53 | |||
54 | local_irq_save(flags); | ||
55 | val = ctrl_inw(INTC_INTER); | ||
56 | val &= ~(1 << (irq - PINT_IRQ_BASE)); | ||
57 | ctrl_outw(val, INTC_INTER); /* disable PINTn */ | ||
58 | portcr_mask &= ~(3 << (irq - PINT_IRQ_BASE)*2); | ||
59 | local_irq_restore(flags); | ||
60 | } | ||
61 | |||
62 | static void enable_pint_irq(unsigned int irq) | ||
63 | { | ||
64 | unsigned long val, flags; | ||
65 | |||
66 | local_irq_save(flags); | ||
67 | val = ctrl_inw(INTC_INTER); | ||
68 | val |= 1 << (irq - PINT_IRQ_BASE); | ||
69 | ctrl_outw(val, INTC_INTER); /* enable PINTn */ | ||
70 | portcr_mask |= 3 << (irq - PINT_IRQ_BASE)*2; | ||
71 | local_irq_restore(flags); | ||
72 | } | ||
73 | |||
74 | static void mask_and_ack_pint(unsigned int irq) | ||
75 | { | ||
76 | disable_pint_irq(irq); | ||
77 | } | ||
78 | |||
79 | static void end_pint_irq(unsigned int irq) | ||
80 | { | ||
81 | if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) | ||
82 | enable_pint_irq(irq); | ||
83 | } | ||
84 | |||
85 | void make_pint_irq(unsigned int irq) | ||
86 | { | ||
87 | disable_irq_nosync(irq); | ||
88 | irq_desc[irq].handler = &pint_irq_type; | ||
89 | disable_pint_irq(irq); | ||
90 | } | ||
91 | |||
92 | void __init init_IRQ_pint(void) | ||
93 | { | ||
94 | int i; | ||
95 | |||
96 | make_ipr_irq(PINT0_IRQ, PINT0_IPR_ADDR, PINT0_IPR_POS, PINT0_PRIORITY); | ||
97 | make_ipr_irq(PINT8_IRQ, PINT8_IPR_ADDR, PINT8_IPR_POS, PINT8_PRIORITY); | ||
98 | |||
99 | enable_irq(PINT0_IRQ); | ||
100 | enable_irq(PINT8_IRQ); | ||
101 | |||
102 | for(i = 0; i < 16; i++) | ||
103 | make_pint_irq(PINT_IRQ_BASE + i); | ||
104 | |||
105 | for(i = 0; i < 256; i++) { | ||
106 | if (i & 1) | ||
107 | pint_map[i] = 0; | ||
108 | else if (i & 2) | ||
109 | pint_map[i] = 1; | ||
110 | else if (i & 4) | ||
111 | pint_map[i] = 2; | ||
112 | else if (i & 8) | ||
113 | pint_map[i] = 3; | ||
114 | else if (i & 0x10) | ||
115 | pint_map[i] = 4; | ||
116 | else if (i & 0x20) | ||
117 | pint_map[i] = 5; | ||
118 | else if (i & 0x40) | ||
119 | pint_map[i] = 6; | ||
120 | else if (i & 0x80) | ||
121 | pint_map[i] = 7; | ||
122 | } | ||
123 | } | ||
124 | |||
125 | int ipr_irq_demux(int irq) | ||
126 | { | ||
127 | unsigned long creg, dreg, d, sav; | ||
128 | |||
129 | if (irq == PINT0_IRQ) { | ||
130 | #if defined(CONFIG_CPU_SUBTYPE_SH7707) | ||
131 | creg = PORT_PACR; | ||
132 | dreg = PORT_PADR; | ||
133 | #else | ||
134 | creg = PORT_PCCR; | ||
135 | dreg = PORT_PCDR; | ||
136 | #endif | ||
137 | sav = ctrl_inw(creg); | ||
138 | ctrl_outw(sav | portcr_mask, creg); | ||
139 | d = (~ctrl_inb(dreg) ^ ctrl_inw(INTC_ICR2)) & | ||
140 | ctrl_inw(INTC_INTER) & 0xff; | ||
141 | ctrl_outw(sav, creg); | ||
142 | |||
143 | if (d == 0) | ||
144 | return irq; | ||
145 | |||
146 | return PINT_IRQ_BASE + pint_map[d]; | ||
147 | } else if (irq == PINT8_IRQ) { | ||
148 | #if defined(CONFIG_CPU_SUBTYPE_SH7707) | ||
149 | creg = PORT_PBCR; | ||
150 | dreg = PORT_PBDR; | ||
151 | #else | ||
152 | creg = PORT_PFCR; | ||
153 | dreg = PORT_PFDR; | ||
154 | #endif | ||
155 | sav = ctrl_inw(creg); | ||
156 | ctrl_outw(sav | (portcr_mask >> 16), creg); | ||
157 | d = (~ctrl_inb(dreg) ^ (ctrl_inw(INTC_ICR2) >> 8)) & | ||
158 | (ctrl_inw(INTC_INTER) >> 8) & 0xff; | ||
159 | ctrl_outw(sav, creg); | ||
160 | |||
161 | if (d == 0) | ||
162 | return irq; | ||
163 | |||
164 | return PINT_IRQ_BASE + 8 + pint_map[d]; | ||
165 | } | ||
166 | |||
167 | return irq; | ||
168 | } | ||
169 | |||
diff --git a/arch/sh/kernel/cpu/sh4/irq_intc2.c b/arch/sh/kernel/cpu/sh4/irq_intc2.c deleted file mode 100644 index f6b16ba0193..00000000000 --- a/arch/sh/kernel/cpu/sh4/irq_intc2.c +++ /dev/null | |||
@@ -1,222 +0,0 @@ | |||
1 | /* | ||
2 | * linux/arch/sh/kernel/irq_intc2.c | ||
3 | * | ||
4 | * Copyright (C) 2001 David J. Mckay (david.mckay@st.com) | ||
5 | * | ||
6 | * May be copied or modified under the terms of the GNU General Public | ||
7 | * License. See linux/COPYING for more information. | ||
8 | * | ||
9 | * Interrupt handling for INTC2-based IRQ. | ||
10 | * | ||
11 | * These are the "new Hitachi style" interrupts, as present on the | ||
12 | * Hitachi 7751 and the STM ST40 STB1. | ||
13 | */ | ||
14 | |||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/init.h> | ||
17 | #include <linux/irq.h> | ||
18 | |||
19 | #include <asm/system.h> | ||
20 | #include <asm/io.h> | ||
21 | #include <asm/machvec.h> | ||
22 | |||
23 | |||
24 | struct intc2_data { | ||
25 | unsigned char msk_offset; | ||
26 | unsigned char msk_shift; | ||
27 | #ifdef CONFIG_CPU_SUBTYPE_ST40 | ||
28 | int (*clear_irq) (int); | ||
29 | #endif | ||
30 | }; | ||
31 | |||
32 | |||
33 | static struct intc2_data intc2_data[NR_INTC2_IRQS]; | ||
34 | |||
35 | static void enable_intc2_irq(unsigned int irq); | ||
36 | static void disable_intc2_irq(unsigned int irq); | ||
37 | |||
38 | /* shutdown is same as "disable" */ | ||
39 | #define shutdown_intc2_irq disable_intc2_irq | ||
40 | |||
41 | static void mask_and_ack_intc2(unsigned int); | ||
42 | static void end_intc2_irq(unsigned int irq); | ||
43 | |||
44 | static unsigned int startup_intc2_irq(unsigned int irq) | ||
45 | { | ||
46 | enable_intc2_irq(irq); | ||
47 | return 0; /* never anything pending */ | ||
48 | } | ||
49 | |||
50 | static struct hw_interrupt_type intc2_irq_type = { | ||
51 | .typename = "INTC2-IRQ", | ||
52 | .startup = startup_intc2_irq, | ||
53 | .shutdown = shutdown_intc2_irq, | ||
54 | .enable = enable_intc2_irq, | ||
55 | .disable = disable_intc2_irq, | ||
56 | .ack = mask_and_ack_intc2, | ||
57 | .end = end_intc2_irq | ||
58 | }; | ||
59 | |||
60 | static void disable_intc2_irq(unsigned int irq) | ||
61 | { | ||
62 | int irq_offset = irq - INTC2_FIRST_IRQ; | ||
63 | int msk_shift, msk_offset; | ||
64 | |||
65 | // Sanity check | ||
66 | if((irq_offset<0) || (irq_offset>=NR_INTC2_IRQS)) | ||
67 | return; | ||
68 | |||
69 | msk_shift = intc2_data[irq_offset].msk_shift; | ||
70 | msk_offset = intc2_data[irq_offset].msk_offset; | ||
71 | |||
72 | ctrl_outl(1<<msk_shift, | ||
73 | INTC2_BASE+INTC2_INTMSK_OFFSET+msk_offset); | ||
74 | } | ||
75 | |||
76 | static void enable_intc2_irq(unsigned int irq) | ||
77 | { | ||
78 | int irq_offset = irq - INTC2_FIRST_IRQ; | ||
79 | int msk_shift, msk_offset; | ||
80 | |||
81 | /* Sanity check */ | ||
82 | if((irq_offset<0) || (irq_offset>=NR_INTC2_IRQS)) | ||
83 | return; | ||
84 | |||
85 | msk_shift = intc2_data[irq_offset].msk_shift; | ||
86 | msk_offset = intc2_data[irq_offset].msk_offset; | ||
87 | |||
88 | ctrl_outl(1<<msk_shift, | ||
89 | INTC2_BASE+INTC2_INTMSKCLR_OFFSET+msk_offset); | ||
90 | } | ||
91 | |||
92 | static void mask_and_ack_intc2(unsigned int irq) | ||
93 | { | ||
94 | disable_intc2_irq(irq); | ||
95 | } | ||
96 | |||
97 | static void end_intc2_irq(unsigned int irq) | ||
98 | { | ||
99 | if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) | ||
100 | enable_intc2_irq(irq); | ||
101 | |||
102 | #ifdef CONFIG_CPU_SUBTYPE_ST40 | ||
103 | if (intc2_data[irq - INTC2_FIRST_IRQ].clear_irq) | ||
104 | intc2_data[irq - INTC2_FIRST_IRQ].clear_irq (irq); | ||
105 | #endif | ||
106 | } | ||
107 | |||
108 | /* | ||
109 | * Setup an INTC2 style interrupt. | ||
110 | * NOTE: Unlike IPR interrupts, parameters are not shifted by this code, | ||
111 | * allowing the use of the numbers straight out of the datasheet. | ||
112 | * For example: | ||
113 | * PIO1 which is INTPRI00[19,16] and INTMSK00[13] | ||
114 | * would be: ^ ^ ^ ^ | ||
115 | * | | | | | ||
116 | * make_intc2_irq(84, 0, 16, 0, 13); | ||
117 | */ | ||
118 | void make_intc2_irq(unsigned int irq, | ||
119 | unsigned int ipr_offset, unsigned int ipr_shift, | ||
120 | unsigned int msk_offset, unsigned int msk_shift, | ||
121 | unsigned int priority) | ||
122 | { | ||
123 | int irq_offset = irq - INTC2_FIRST_IRQ; | ||
124 | unsigned int flags; | ||
125 | unsigned long ipr; | ||
126 | |||
127 | if((irq_offset<0) || (irq_offset>=NR_INTC2_IRQS)) | ||
128 | return; | ||
129 | |||
130 | disable_irq_nosync(irq); | ||
131 | |||
132 | /* Fill the data we need */ | ||
133 | intc2_data[irq_offset].msk_offset = msk_offset; | ||
134 | intc2_data[irq_offset].msk_shift = msk_shift; | ||
135 | #ifdef CONFIG_CPU_SUBTYPE_ST40 | ||
136 | intc2_data[irq_offset].clear_irq = NULL; | ||
137 | #endif | ||
138 | |||
139 | /* Set the priority level */ | ||
140 | local_irq_save(flags); | ||
141 | |||
142 | ipr=ctrl_inl(INTC2_BASE+INTC2_INTPRI_OFFSET+ipr_offset); | ||
143 | ipr&=~(0xf<<ipr_shift); | ||
144 | ipr|=(priority)<<ipr_shift; | ||
145 | ctrl_outl(ipr, INTC2_BASE+INTC2_INTPRI_OFFSET+ipr_offset); | ||
146 | |||
147 | local_irq_restore(flags); | ||
148 | |||
149 | irq_desc[irq].handler=&intc2_irq_type; | ||
150 | |||
151 | disable_intc2_irq(irq); | ||
152 | } | ||
153 | |||
154 | #ifdef CONFIG_CPU_SUBTYPE_ST40 | ||
155 | |||
156 | struct intc2_init { | ||
157 | unsigned short irq; | ||
158 | unsigned char ipr_offset, ipr_shift; | ||
159 | unsigned char msk_offset, msk_shift; | ||
160 | }; | ||
161 | |||
162 | static struct intc2_init intc2_init_data[] __initdata = { | ||
163 | {64, 0, 0, 0, 0}, /* PCI serr */ | ||
164 | {65, 0, 4, 0, 1}, /* PCI err */ | ||
165 | {66, 0, 4, 0, 2}, /* PCI ad */ | ||
166 | {67, 0, 4, 0, 3}, /* PCI pwd down */ | ||
167 | {72, 0, 8, 0, 5}, /* DMAC INT0 */ | ||
168 | {73, 0, 8, 0, 6}, /* DMAC INT1 */ | ||
169 | {74, 0, 8, 0, 7}, /* DMAC INT2 */ | ||
170 | {75, 0, 8, 0, 8}, /* DMAC INT3 */ | ||
171 | {76, 0, 8, 0, 9}, /* DMAC INT4 */ | ||
172 | {78, 0, 8, 0, 11}, /* DMAC ERR */ | ||
173 | {80, 0, 12, 0, 12}, /* PIO0 */ | ||
174 | {84, 0, 16, 0, 13}, /* PIO1 */ | ||
175 | {88, 0, 20, 0, 14}, /* PIO2 */ | ||
176 | {112, 4, 0, 4, 0}, /* Mailbox */ | ||
177 | #ifdef CONFIG_CPU_SUBTYPE_ST40GX1 | ||
178 | {116, 4, 4, 4, 4}, /* SSC0 */ | ||
179 | {120, 4, 8, 4, 8}, /* IR Blaster */ | ||
180 | {124, 4, 12, 4, 12}, /* USB host */ | ||
181 | {128, 4, 16, 4, 16}, /* Video processor BLITTER */ | ||
182 | {132, 4, 20, 4, 20}, /* UART0 */ | ||
183 | {134, 4, 20, 4, 22}, /* UART2 */ | ||
184 | {136, 4, 24, 4, 24}, /* IO_PIO0 */ | ||
185 | {140, 4, 28, 4, 28}, /* EMPI */ | ||
186 | {144, 8, 0, 8, 0}, /* MAFE */ | ||
187 | {148, 8, 4, 8, 4}, /* PWM */ | ||
188 | {152, 8, 8, 8, 8}, /* SSC1 */ | ||
189 | {156, 8, 12, 8, 12}, /* IO_PIO1 */ | ||
190 | {160, 8, 16, 8, 16}, /* USB target */ | ||
191 | {164, 8, 20, 8, 20}, /* UART1 */ | ||
192 | {168, 8, 24, 8, 24}, /* Teletext */ | ||
193 | {172, 8, 28, 8, 28}, /* VideoSync VTG */ | ||
194 | {173, 8, 28, 8, 29}, /* VideoSync DVP0 */ | ||
195 | {174, 8, 28, 8, 30}, /* VideoSync DVP1 */ | ||
196 | #endif | ||
197 | }; | ||
198 | |||
199 | void __init init_IRQ_intc2(void) | ||
200 | { | ||
201 | struct intc2_init *p; | ||
202 | |||
203 | printk(KERN_ALERT "init_IRQ_intc2\n"); | ||
204 | |||
205 | for (p = intc2_init_data; | ||
206 | p<intc2_init_data+ARRAY_SIZE(intc2_init_data); | ||
207 | p++) { | ||
208 | make_intc2_irq(p->irq, p->ipr_offset, p->ipr_shift, | ||
209 | p-> msk_offset, p->msk_shift, 13); | ||
210 | } | ||
211 | } | ||
212 | |||
213 | /* Adds a termination callback to the interrupt */ | ||
214 | void intc2_add_clear_irq(int irq, int (*fn)(int)) | ||
215 | { | ||
216 | if (irq < INTC2_FIRST_IRQ) | ||
217 | return; | ||
218 | |||
219 | intc2_data[irq - INTC2_FIRST_IRQ].clear_irq = fn; | ||
220 | } | ||
221 | |||
222 | #endif /* CONFIG_CPU_SUBTYPE_ST40 */ | ||
diff --git a/arch/sh/kernel/irq.c b/arch/sh/kernel/irq.c index 54c171225b7..6883c00728c 100644 --- a/arch/sh/kernel/irq.c +++ b/arch/sh/kernel/irq.c | |||
@@ -8,38 +8,13 @@ | |||
8 | * SuperH version: Copyright (C) 1999 Niibe Yutaka | 8 | * SuperH version: Copyright (C) 1999 Niibe Yutaka |
9 | */ | 9 | */ |
10 | 10 | ||
11 | /* | 11 | #include <linux/irq.h> |
12 | * IRQs are in fact implemented a bit like signal handlers for the kernel. | ||
13 | * Naturally it's not a 1:1 relation, but there are similarities. | ||
14 | */ | ||
15 | |||
16 | #include <linux/config.h> | ||
17 | #include <linux/module.h> | ||
18 | #include <linux/ptrace.h> | ||
19 | #include <linux/errno.h> | ||
20 | #include <linux/kernel_stat.h> | ||
21 | #include <linux/signal.h> | ||
22 | #include <linux/sched.h> | ||
23 | #include <linux/ioport.h> | ||
24 | #include <linux/interrupt.h> | 12 | #include <linux/interrupt.h> |
25 | #include <linux/timex.h> | 13 | #include <linux/kernel_stat.h> |
26 | #include <linux/mm.h> | ||
27 | #include <linux/slab.h> | ||
28 | #include <linux/random.h> | ||
29 | #include <linux/smp.h> | ||
30 | #include <linux/smp_lock.h> | ||
31 | #include <linux/init.h> | ||
32 | #include <linux/seq_file.h> | 14 | #include <linux/seq_file.h> |
33 | #include <linux/kallsyms.h> | ||
34 | #include <linux/bitops.h> | ||
35 | |||
36 | #include <asm/system.h> | ||
37 | #include <asm/io.h> | ||
38 | #include <asm/pgalloc.h> | ||
39 | #include <asm/delay.h> | ||
40 | #include <asm/irq.h> | 15 | #include <asm/irq.h> |
41 | #include <linux/irq.h> | 16 | #include <asm/processor.h> |
42 | 17 | #include <asm/cpu/mmu_context.h> | |
43 | 18 | ||
44 | /* | 19 | /* |
45 | * 'what should we do if we get a hw irq event on an illegal vector'. | 20 | * 'what should we do if we get a hw irq event on an illegal vector'. |
@@ -66,7 +41,7 @@ int show_interrupts(struct seq_file *p, void *v) | |||
66 | seq_putc(p, '\n'); | 41 | seq_putc(p, '\n'); |
67 | } | 42 | } |
68 | 43 | ||
69 | if (i < ACTUAL_NR_IRQS) { | 44 | if (i < NR_IRQS) { |
70 | spin_lock_irqsave(&irq_desc[i].lock, flags); | 45 | spin_lock_irqsave(&irq_desc[i].lock, flags); |
71 | action = irq_desc[i].action; | 46 | action = irq_desc[i].action; |
72 | if (!action) | 47 | if (!action) |
@@ -86,19 +61,32 @@ unlock: | |||
86 | } | 61 | } |
87 | #endif | 62 | #endif |
88 | 63 | ||
64 | |||
89 | asmlinkage int do_IRQ(unsigned long r4, unsigned long r5, | 65 | asmlinkage int do_IRQ(unsigned long r4, unsigned long r5, |
90 | unsigned long r6, unsigned long r7, | 66 | unsigned long r6, unsigned long r7, |
91 | struct pt_regs regs) | 67 | struct pt_regs regs) |
92 | { | 68 | { |
93 | int irq; | 69 | int irq = r4; |
94 | 70 | ||
95 | irq_enter(); | 71 | irq_enter(); |
96 | asm volatile("stc r2_bank, %0\n\t" | 72 | |
97 | "shlr2 %0\n\t" | 73 | #ifdef CONFIG_CPU_HAS_INTEVT |
98 | "shlr2 %0\n\t" | 74 | __asm__ __volatile__ ( |
99 | "shlr %0\n\t" | 75 | #ifdef CONFIG_CPU_HAS_SR_RB |
100 | "add #-16, %0\n\t" | 76 | "stc r2_bank, %0\n\t" |
101 | :"=z" (irq)); | 77 | #else |
78 | "mov.l @%1, %0\n\t" | ||
79 | #endif | ||
80 | "shlr2 %0\n\t" | ||
81 | "shlr2 %0\n\t" | ||
82 | "shlr %0\n\t" | ||
83 | "add #-16, %0\n\t" | ||
84 | : "=z" (irq), "=r" (r4) | ||
85 | : "1" (INTEVT) | ||
86 | : "memory" | ||
87 | ); | ||
88 | #endif | ||
89 | |||
102 | irq = irq_demux(irq); | 90 | irq = irq_demux(irq); |
103 | __do_IRQ(irq, ®s); | 91 | __do_IRQ(irq, ®s); |
104 | irq_exit(); | 92 | irq_exit(); |
diff --git a/include/asm-sh/irq-sh7780.h b/include/asm-sh/irq-sh7780.h new file mode 100644 index 00000000000..8c8ca128108 --- /dev/null +++ b/include/asm-sh/irq-sh7780.h | |||
@@ -0,0 +1,349 @@ | |||
1 | #ifndef __ASM_SH_IRQ_SH7780_H | ||
2 | #define __ASM_SH_IRQ_SH7780_H | ||
3 | |||
4 | /* | ||
5 | * linux/include/asm-sh/irq-sh7780.h | ||
6 | * | ||
7 | * Copyright (C) 2004 Takashi SHUDO <shudo@hitachi-ul.co.jp> | ||
8 | */ | ||
9 | |||
10 | #ifdef CONFIG_IDE | ||
11 | # ifndef IRQ_CFCARD | ||
12 | # define IRQ_CFCARD 14 | ||
13 | # endif | ||
14 | # ifndef IRQ_PCMCIA | ||
15 | # define IRQ_PCMCIA 15 | ||
16 | # endif | ||
17 | #endif | ||
18 | |||
19 | #define INTC_BASE 0xffd00000 | ||
20 | #define INTC_ICR0 (INTC_BASE+0x0) | ||
21 | #define INTC_ICR1 (INTC_BASE+0x1c) | ||
22 | #define INTC_INTPRI (INTC_BASE+0x10) | ||
23 | #define INTC_INTREQ (INTC_BASE+0x24) | ||
24 | #define INTC_INTMSK0 (INTC_BASE+0x44) | ||
25 | #define INTC_INTMSK1 (INTC_BASE+0x48) | ||
26 | #define INTC_INTMSK2 (INTC_BASE+0x40080) | ||
27 | #define INTC_INTMSKCLR0 (INTC_BASE+0x64) | ||
28 | #define INTC_INTMSKCLR1 (INTC_BASE+0x68) | ||
29 | #define INTC_INTMSKCLR2 (INTC_BASE+0x40084) | ||
30 | #define INTC_NMIFCR (INTC_BASE+0xc0) | ||
31 | #define INTC_USERIMASK (INTC_BASE+0x30000) | ||
32 | |||
33 | #define INTC_INT2PRI0 (INTC_BASE+0x40000) | ||
34 | #define INTC_INT2PRI1 (INTC_BASE+0x40004) | ||
35 | #define INTC_INT2PRI2 (INTC_BASE+0x40008) | ||
36 | #define INTC_INT2PRI3 (INTC_BASE+0x4000c) | ||
37 | #define INTC_INT2PRI4 (INTC_BASE+0x40010) | ||
38 | #define INTC_INT2PRI5 (INTC_BASE+0x40014) | ||
39 | #define INTC_INT2PRI6 (INTC_BASE+0x40018) | ||
40 | #define INTC_INT2PRI7 (INTC_BASE+0x4001c) | ||
41 | #define INTC_INT2A0 (INTC_BASE+0x40030) | ||
42 | #define INTC_INT2A1 (INTC_BASE+0x40034) | ||
43 | #define INTC_INT2MSKR (INTC_BASE+0x40038) | ||
44 | #define INTC_INT2MSKCR (INTC_BASE+0x4003c) | ||
45 | #define INTC_INT2B0 (INTC_BASE+0x40040) | ||
46 | #define INTC_INT2B1 (INTC_BASE+0x40044) | ||
47 | #define INTC_INT2B2 (INTC_BASE+0x40048) | ||
48 | #define INTC_INT2B3 (INTC_BASE+0x4004c) | ||
49 | #define INTC_INT2B4 (INTC_BASE+0x40050) | ||
50 | #define INTC_INT2B5 (INTC_BASE+0x40054) | ||
51 | #define INTC_INT2B6 (INTC_BASE+0x40058) | ||
52 | #define INTC_INT2B7 (INTC_BASE+0x4005c) | ||
53 | #define INTC_INT2GPIC (INTC_BASE+0x40090) | ||
54 | /* | ||
55 | NOTE: | ||
56 | *_IRQ = (INTEVT2 - 0x200)/0x20 | ||
57 | */ | ||
58 | /* IRQ 0-7 line external int*/ | ||
59 | #define IRQ0_IRQ 2 | ||
60 | #define IRQ0_IPR_ADDR INTC_INTPRI | ||
61 | #define IRQ0_IPR_POS 7 | ||
62 | #define IRQ0_PRIORITY 2 | ||
63 | |||
64 | #define IRQ1_IRQ 4 | ||
65 | #define IRQ1_IPR_ADDR INTC_INTPRI | ||
66 | #define IRQ1_IPR_POS 6 | ||
67 | #define IRQ1_PRIORITY 2 | ||
68 | |||
69 | #define IRQ2_IRQ 6 | ||
70 | #define IRQ2_IPR_ADDR INTC_INTPRI | ||
71 | #define IRQ2_IPR_POS 5 | ||
72 | #define IRQ2_PRIORITY 2 | ||
73 | |||
74 | #define IRQ3_IRQ 8 | ||
75 | #define IRQ3_IPR_ADDR INTC_INTPRI | ||
76 | #define IRQ3_IPR_POS 4 | ||
77 | #define IRQ3_PRIORITY 2 | ||
78 | |||
79 | #define IRQ4_IRQ 10 | ||
80 | #define IRQ4_IPR_ADDR INTC_INTPRI | ||
81 | #define IRQ4_IPR_POS 3 | ||
82 | #define IRQ4_PRIORITY 2 | ||
83 | |||
84 | #define IRQ5_IRQ 12 | ||
85 | #define IRQ5_IPR_ADDR INTC_INTPRI | ||
86 | #define IRQ5_IPR_POS 2 | ||
87 | #define IRQ5_PRIORITY 2 | ||
88 | |||
89 | #define IRQ6_IRQ 14 | ||
90 | #define IRQ6_IPR_ADDR INTC_INTPRI | ||
91 | #define IRQ6_IPR_POS 1 | ||
92 | #define IRQ6_PRIORITY 2 | ||
93 | |||
94 | #define IRQ7_IRQ 0 | ||
95 | #define IRQ7_IPR_ADDR INTC_INTPRI | ||
96 | #define IRQ7_IPR_POS 0 | ||
97 | #define IRQ7_PRIORITY 2 | ||
98 | |||
99 | /* TMU */ | ||
100 | /* ch0 */ | ||
101 | #define TMU_IRQ 28 | ||
102 | #define TMU_IPR_ADDR INTC_INT2PRI0 | ||
103 | #define TMU_IPR_POS 3 | ||
104 | #define TMU_PRIORITY 2 | ||
105 | |||
106 | #define TIMER_IRQ 28 | ||
107 | #define TIMER_IPR_ADDR INTC_INT2PRI0 | ||
108 | #define TIMER_IPR_POS 3 | ||
109 | #define TIMER_PRIORITY 2 | ||
110 | |||
111 | /* ch 1*/ | ||
112 | #define TMU_CH1_IRQ 29 | ||
113 | #define TMU_CH1_IPR_ADDR INTC_INT2PRI0 | ||
114 | #define TMU_CH1_IPR_POS 2 | ||
115 | #define TMU_CH1_PRIORITY 2 | ||
116 | |||
117 | #define TIMER1_IRQ 29 | ||
118 | #define TIMER1_IPR_ADDR INTC_INT2PRI0 | ||
119 | #define TIMER1_IPR_POS 2 | ||
120 | #define TIMER1_PRIORITY 2 | ||
121 | |||
122 | /* ch 2*/ | ||
123 | #define TMU_CH2_IRQ 30 | ||
124 | #define TMU_CH2_IPR_ADDR INTC_INT2PRI0 | ||
125 | #define TMU_CH2_IPR_POS 1 | ||
126 | #define TMU_CH2_PRIORITY 2 | ||
127 | /* ch 2 Input capture */ | ||
128 | #define TMU_CH2IC_IRQ 31 | ||
129 | #define TMU_CH2IC_IPR_ADDR INTC_INT2PRI0 | ||
130 | #define TMU_CH2IC_IPR_POS 0 | ||
131 | #define TMU_CH2IC_PRIORITY 2 | ||
132 | /* ch 3 */ | ||
133 | #define TMU_CH3_IRQ 96 | ||
134 | #define TMU_CH3_IPR_ADDR INTC_INT2PRI1 | ||
135 | #define TMU_CH3_IPR_POS 3 | ||
136 | #define TMU_CH3_PRIORITY 2 | ||
137 | /* ch 4 */ | ||
138 | #define TMU_CH4_IRQ 97 | ||
139 | #define TMU_CH4_IPR_ADDR INTC_INT2PRI1 | ||
140 | #define TMU_CH4_IPR_POS 2 | ||
141 | #define TMU_CH4_PRIORITY 2 | ||
142 | /* ch 5*/ | ||
143 | #define TMU_CH5_IRQ 98 | ||
144 | #define TMU_CH5_IPR_ADDR INTC_INT2PRI1 | ||
145 | #define TMU_CH5_IPR_POS 1 | ||
146 | #define TMU_CH5_PRIORITY 2 | ||
147 | |||
148 | #define RTC_IRQ 22 | ||
149 | #define RTC_IPR_ADDR INTC_INT2PRI1 | ||
150 | #define RTC_IPR_POS 0 | ||
151 | #define RTC_PRIORITY TIMER_PRIORITY | ||
152 | |||
153 | /* SCIF0 */ | ||
154 | #define SCIF0_ERI_IRQ 40 | ||
155 | #define SCIF0_RXI_IRQ 41 | ||
156 | #define SCIF0_BRI_IRQ 42 | ||
157 | #define SCIF0_TXI_IRQ 43 | ||
158 | #define SCIF0_IPR_ADDR INTC_INT2PRI2 | ||
159 | #define SCIF0_IPR_POS 3 | ||
160 | #define SCIF0_PRIORITY 3 | ||
161 | |||
162 | /* SCIF1 */ | ||
163 | #define SCIF1_ERI_IRQ 76 | ||
164 | #define SCIF1_RXI_IRQ 77 | ||
165 | #define SCIF1_BRI_IRQ 78 | ||
166 | #define SCIF1_TXI_IRQ 79 | ||
167 | #define SCIF1_IPR_ADDR INTC_INT2PRI2 | ||
168 | #define SCIF1_IPR_POS 2 | ||
169 | #define SCIF1_PRIORITY 3 | ||
170 | |||
171 | #define WDT_IRQ 27 | ||
172 | #define WDT_IPR_ADDR INTC_INT2PRI2 | ||
173 | #define WDT_IPR_POS 1 | ||
174 | #define WDT_PRIORITY 2 | ||
175 | |||
176 | /* DMAC(0) */ | ||
177 | #define DMINT0_IRQ 34 | ||
178 | #define DMINT1_IRQ 35 | ||
179 | #define DMINT2_IRQ 36 | ||
180 | #define DMINT3_IRQ 37 | ||
181 | #define DMINT4_IRQ 44 | ||
182 | #define DMINT5_IRQ 45 | ||
183 | #define DMINT6_IRQ 46 | ||
184 | #define DMINT7_IRQ 47 | ||
185 | #define DMAE_IRQ 38 | ||
186 | #define DMA0_IPR_ADDR INTC_INT2PRI3 | ||
187 | #define DMA0_IPR_POS 2 | ||
188 | #define DMA0_PRIORITY 7 | ||
189 | |||
190 | /* DMAC(1) */ | ||
191 | #define DMINT8_IRQ 92 | ||
192 | #define DMINT9_IRQ 93 | ||
193 | #define DMINT10_IRQ 94 | ||
194 | #define DMINT11_IRQ 95 | ||
195 | #define DMA1_IPR_ADDR INTC_INT2PRI3 | ||
196 | #define DMA1_IPR_POS 1 | ||
197 | #define DMA1_PRIORITY 7 | ||
198 | |||
199 | #define DMTE0_IRQ DMINT0_IRQ | ||
200 | #define DMTE4_IRQ DMINT4_IRQ | ||
201 | #define DMA_IPR_ADDR DMA0_IPR_ADDR | ||
202 | #define DMA_IPR_POS DMA0_IPR_POS | ||
203 | #define DMA_PRIORITY DMA0_PRIORITY | ||
204 | |||
205 | /* CMT */ | ||
206 | #define CMT_IRQ 56 | ||
207 | #define CMT_IPR_ADDR INTC_INT2PRI4 | ||
208 | #define CMT_IPR_POS 3 | ||
209 | #define CMT_PRIORITY 0 | ||
210 | |||
211 | /* HAC */ | ||
212 | #define HAC_IRQ 60 | ||
213 | #define HAC_IPR_ADDR INTC_INT2PRI4 | ||
214 | #define HAC_IPR_POS 2 | ||
215 | #define CMT_PRIORITY 0 | ||
216 | |||
217 | /* PCIC(0) */ | ||
218 | #define PCIC0_IRQ 64 | ||
219 | #define PCIC0_IPR_ADDR INTC_INT2PRI4 | ||
220 | #define PCIC0_IPR_POS 1 | ||
221 | #define PCIC0_PRIORITY 2 | ||
222 | |||
223 | /* PCIC(1) */ | ||
224 | #define PCIC1_IRQ 65 | ||
225 | #define PCIC1_IPR_ADDR INTC_INT2PRI4 | ||
226 | #define PCIC1_IPR_POS 0 | ||
227 | #define PCIC1_PRIORITY 2 | ||
228 | |||
229 | /* PCIC(2) */ | ||
230 | #define PCIC2_IRQ 66 | ||
231 | #define PCIC2_IPR_ADDR INTC_INT2PRI5 | ||
232 | #define PCIC2_IPR_POS 3 | ||
233 | #define PCIC2_PRIORITY 2 | ||
234 | |||
235 | /* PCIC(3) */ | ||
236 | #define PCIC3_IRQ 67 | ||
237 | #define PCIC3_IPR_ADDR INTC_INT2PRI5 | ||
238 | #define PCIC3_IPR_POS 2 | ||
239 | #define PCIC3_PRIORITY 2 | ||
240 | |||
241 | /* PCIC(4) */ | ||
242 | #define PCIC4_IRQ 68 | ||
243 | #define PCIC4_IPR_ADDR INTC_INT2PRI5 | ||
244 | #define PCIC4_IPR_POS 1 | ||
245 | #define PCIC4_PRIORITY 2 | ||
246 | |||
247 | /* PCIC(5) */ | ||
248 | #define PCICERR_IRQ 69 | ||
249 | #define PCICPWD3_IRQ 70 | ||
250 | #define PCICPWD2_IRQ 71 | ||
251 | #define PCICPWD1_IRQ 72 | ||
252 | #define PCICPWD0_IRQ 73 | ||
253 | #define PCIC5_IPR_ADDR INTC_INT2PRI5 | ||
254 | #define PCIC5_IPR_POS 0 | ||
255 | #define PCIC5_PRIORITY 2 | ||
256 | |||
257 | /* SIOF */ | ||
258 | #define SIOF_IRQ 80 | ||
259 | #define SIOF_IPR_ADDR INTC_INT2PRI6 | ||
260 | #define SIOF_IPR_POS 3 | ||
261 | #define SIOF_PRIORITY 3 | ||
262 | |||
263 | /* HSPI */ | ||
264 | #define HSPI_IRQ 84 | ||
265 | #define HSPI_IPR_ADDR INTC_INT2PRI6 | ||
266 | #define HSPI_IPR_POS 2 | ||
267 | #define HSPI_PRIORITY 3 | ||
268 | |||
269 | /* MMCIF */ | ||
270 | #define MMCIF_FSTAT_IRQ 88 | ||
271 | #define MMCIF_TRAN_IRQ 89 | ||
272 | #define MMCIF_ERR_IRQ 90 | ||
273 | #define MMCIF_FRDY_IRQ 91 | ||
274 | #define MMCIF_IPR_ADDR INTC_INT2PRI6 | ||
275 | #define MMCIF_IPR_POS 1 | ||
276 | #define HSPI_PRIORITY 3 | ||
277 | |||
278 | /* SSI */ | ||
279 | #define SSI_IRQ 100 | ||
280 | #define SSI_IPR_ADDR INTC_INT2PRI6 | ||
281 | #define SSI_IPR_POS 0 | ||
282 | #define SSI_PRIORITY 3 | ||
283 | |||
284 | /* FLCTL */ | ||
285 | #define FLCTL_FLSTE_IRQ 104 | ||
286 | #define FLCTL_FLTEND_IRQ 105 | ||
287 | #define FLCTL_FLTRQ0_IRQ 106 | ||
288 | #define FLCTL_FLTRQ1_IRQ 107 | ||
289 | #define FLCTL_IPR_ADDR INTC_INT2PRI7 | ||
290 | #define FLCTL_IPR_POS 3 | ||
291 | #define FLCTL_PRIORITY 3 | ||
292 | |||
293 | /* GPIO */ | ||
294 | #define GPIO0_IRQ 108 | ||
295 | #define GPIO1_IRQ 109 | ||
296 | #define GPIO2_IRQ 110 | ||
297 | #define GPIO3_IRQ 111 | ||
298 | #define GPIO_IPR_ADDR INTC_INT2PRI7 | ||
299 | #define GPIO_IPR_POS 2 | ||
300 | #define GPIO_PRIORITY 3 | ||
301 | |||
302 | /* ONCHIP_NR_IRQS */ | ||
303 | #define NR_IRQS 150 /* 111 + 16 */ | ||
304 | |||
305 | /* In a generic kernel, NR_IRQS is an upper bound, and we should use | ||
306 | * ACTUAL_NR_IRQS (which uses the machine vector) to get the correct value. | ||
307 | */ | ||
308 | #define ACTUAL_NR_IRQS NR_IRQS | ||
309 | |||
310 | extern void disable_irq(unsigned int); | ||
311 | extern void disable_irq_nosync(unsigned int); | ||
312 | extern void enable_irq(unsigned int); | ||
313 | |||
314 | /* | ||
315 | * Simple Mask Register Support | ||
316 | */ | ||
317 | extern void make_maskreg_irq(unsigned int irq); | ||
318 | extern unsigned short *irq_mask_register; | ||
319 | |||
320 | /* | ||
321 | * Function for "on chip support modules". | ||
322 | */ | ||
323 | extern void make_imask_irq(unsigned int irq); | ||
324 | |||
325 | #define INTC_TMU0_MSK 0 | ||
326 | #define INTC_TMU3_MSK 1 | ||
327 | #define INTC_RTC_MSK 2 | ||
328 | #define INTC_SCIF0_MSK 3 | ||
329 | #define INTC_SCIF1_MSK 4 | ||
330 | #define INTC_WDT_MSK 5 | ||
331 | #define INTC_HUID_MSK 7 | ||
332 | #define INTC_DMAC0_MSK 8 | ||
333 | #define INTC_DMAC1_MSK 9 | ||
334 | #define INTC_CMT_MSK 12 | ||
335 | #define INTC_HAC_MSK 13 | ||
336 | #define INTC_PCIC0_MSK 14 | ||
337 | #define INTC_PCIC1_MSK 15 | ||
338 | #define INTC_PCIC2_MSK 16 | ||
339 | #define INTC_PCIC3_MSK 17 | ||
340 | #define INTC_PCIC4_MSK 18 | ||
341 | #define INTC_PCIC5_MSK 19 | ||
342 | #define INTC_SIOF_MSK 20 | ||
343 | #define INTC_HSPI_MSK 21 | ||
344 | #define INTC_MMCIF_MSK 22 | ||
345 | #define INTC_SSI_MSK 23 | ||
346 | #define INTC_FLCTL_MSK 24 | ||
347 | #define INTC_GPIO_MSK 25 | ||
348 | |||
349 | #endif /* __ASM_SH_IRQ_SH7780_H */ | ||
diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h index 614a8c13b72..060ec3c2720 100644 --- a/include/asm-sh/irq.h +++ b/include/asm-sh/irq.h | |||
@@ -15,13 +15,20 @@ | |||
15 | #include <asm/machvec.h> | 15 | #include <asm/machvec.h> |
16 | #include <asm/ptrace.h> /* for pt_regs */ | 16 | #include <asm/ptrace.h> /* for pt_regs */ |
17 | 17 | ||
18 | #if defined(CONFIG_SH_HP600) || \ | 18 | #if defined(CONFIG_SH_HP6XX) || \ |
19 | defined(CONFIG_SH_RTS7751R2D) || \ | 19 | defined(CONFIG_SH_RTS7751R2D) || \ |
20 | defined(CONFIG_SH_HS7751RVOIP) || \ | 20 | defined(CONFIG_SH_HS7751RVOIP) || \ |
21 | defined(CONFIG_SH_SH03) | 21 | defined(CONFIG_SH_HS7751RVOIP) || \ |
22 | defined(CONFIG_SH_SH03) || \ | ||
23 | defined(CONFIG_SH_R7780RP) || \ | ||
24 | defined(CONFIG_SH_LANDISK) | ||
22 | #include <asm/mach/ide.h> | 25 | #include <asm/mach/ide.h> |
23 | #endif | 26 | #endif |
24 | 27 | ||
28 | #ifndef CONFIG_CPU_SUBTYPE_SH7780 | ||
29 | |||
30 | #define INTC_DMAC0_MSK 0 | ||
31 | |||
25 | #if defined(CONFIG_CPU_SH3) | 32 | #if defined(CONFIG_CPU_SH3) |
26 | #define INTC_IPRA 0xfffffee2UL | 33 | #define INTC_IPRA 0xfffffee2UL |
27 | #define INTC_IPRB 0xfffffee4UL | 34 | #define INTC_IPRB 0xfffffee4UL |
@@ -235,8 +242,9 @@ | |||
235 | #define SCIF1_IPR_ADDR INTC_IPRB | 242 | #define SCIF1_IPR_ADDR INTC_IPRB |
236 | #define SCIF1_IPR_POS 1 | 243 | #define SCIF1_IPR_POS 1 |
237 | #define SCIF1_PRIORITY 3 | 244 | #define SCIF1_PRIORITY 3 |
238 | #endif | 245 | #endif /* ST40STB1 */ |
239 | #endif | 246 | |
247 | #endif /* 775x / SH4-202 / ST40STB1 */ | ||
240 | 248 | ||
241 | /* NR_IRQS is made from three components: | 249 | /* NR_IRQS is made from three components: |
242 | * 1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules | 250 | * 1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules |
@@ -245,37 +253,35 @@ | |||
245 | */ | 253 | */ |
246 | 254 | ||
247 | /* 1. ONCHIP_NR_IRQS */ | 255 | /* 1. ONCHIP_NR_IRQS */ |
248 | #ifdef CONFIG_SH_GENERIC | 256 | #if defined(CONFIG_CPU_SUBTYPE_SH7604) |
257 | # define ONCHIP_NR_IRQS 24 // Actually 21 | ||
258 | #elif defined(CONFIG_CPU_SUBTYPE_SH7707) | ||
259 | # define ONCHIP_NR_IRQS 64 | ||
260 | # define PINT_NR_IRQS 16 | ||
261 | #elif defined(CONFIG_CPU_SUBTYPE_SH7708) | ||
262 | # define ONCHIP_NR_IRQS 32 | ||
263 | #elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \ | ||
264 | defined(CONFIG_CPU_SUBTYPE_SH7705) | ||
265 | # define ONCHIP_NR_IRQS 64 // Actually 61 | ||
266 | # define PINT_NR_IRQS 16 | ||
267 | #elif defined(CONFIG_CPU_SUBTYPE_SH7750) | ||
268 | # define ONCHIP_NR_IRQS 48 // Actually 44 | ||
269 | #elif defined(CONFIG_CPU_SUBTYPE_SH7751) | ||
270 | # define ONCHIP_NR_IRQS 72 | ||
271 | #elif defined(CONFIG_CPU_SUBTYPE_SH7760) | ||
272 | # define ONCHIP_NR_IRQS 112 /* XXX */ | ||
273 | #elif defined(CONFIG_CPU_SUBTYPE_SH4_202) | ||
274 | # define ONCHIP_NR_IRQS 72 | ||
275 | #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1) | ||
276 | # define ONCHIP_NR_IRQS 144 | ||
277 | #elif defined(CONFIG_CPU_SUBTYPE_SH7300) | ||
278 | # define ONCHIP_NR_IRQS 109 | ||
279 | #elif defined(CONFIG_SH_UNKNOWN) /* Most be last */ | ||
249 | # define ONCHIP_NR_IRQS 144 | 280 | # define ONCHIP_NR_IRQS 144 |
250 | #else | ||
251 | # if defined(CONFIG_CPU_SUBTYPE_SH7604) | ||
252 | # define ONCHIP_NR_IRQS 24 // Actually 21 | ||
253 | # elif defined(CONFIG_CPU_SUBTYPE_SH7707) | ||
254 | # define ONCHIP_NR_IRQS 64 | ||
255 | # define PINT_NR_IRQS 16 | ||
256 | # elif defined(CONFIG_CPU_SUBTYPE_SH7708) | ||
257 | # define ONCHIP_NR_IRQS 32 | ||
258 | # elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \ | ||
259 | defined(CONFIG_CPU_SUBTYPE_SH7705) | ||
260 | # define ONCHIP_NR_IRQS 64 // Actually 61 | ||
261 | # define PINT_NR_IRQS 16 | ||
262 | # elif defined(CONFIG_CPU_SUBTYPE_SH7750) | ||
263 | # define ONCHIP_NR_IRQS 48 // Actually 44 | ||
264 | # elif defined(CONFIG_CPU_SUBTYPE_SH7751) | ||
265 | # define ONCHIP_NR_IRQS 72 | ||
266 | # elif defined(CONFIG_CPU_SUBTYPE_SH7760) | ||
267 | # define ONCHIP_NR_IRQS 110 | ||
268 | # elif defined(CONFIG_CPU_SUBTYPE_SH4_202) | ||
269 | # define ONCHIP_NR_IRQS 72 | ||
270 | # elif defined(CONFIG_CPU_SUBTYPE_ST40STB1) | ||
271 | # define ONCHIP_NR_IRQS 144 | ||
272 | # elif defined(CONFIG_CPU_SUBTYPE_SH7300) | ||
273 | # define ONCHIP_NR_IRQS 109 | ||
274 | # endif | ||
275 | #endif | 281 | #endif |
276 | 282 | ||
277 | /* 2. PINT_NR_IRQS */ | 283 | /* 2. PINT_NR_IRQS */ |
278 | #ifdef CONFIG_SH_GENERIC | 284 | #ifdef CONFIG_SH_UNKNOWN |
279 | # define PINT_NR_IRQS 16 | 285 | # define PINT_NR_IRQS 16 |
280 | #else | 286 | #else |
281 | # ifndef PINT_NR_IRQS | 287 | # ifndef PINT_NR_IRQS |
@@ -288,22 +294,22 @@ | |||
288 | #endif | 294 | #endif |
289 | 295 | ||
290 | /* 3. OFFCHIP_NR_IRQS */ | 296 | /* 3. OFFCHIP_NR_IRQS */ |
291 | #ifdef CONFIG_SH_GENERIC | 297 | #if defined(CONFIG_HD64461) |
298 | # define OFFCHIP_NR_IRQS 18 | ||
299 | #elif defined (CONFIG_SH_BIGSUR) /* must be before CONFIG_HD64465 */ | ||
300 | # define OFFCHIP_NR_IRQS 48 | ||
301 | #elif defined(CONFIG_HD64465) | ||
292 | # define OFFCHIP_NR_IRQS 16 | 302 | # define OFFCHIP_NR_IRQS 16 |
303 | #elif defined (CONFIG_SH_EC3104) | ||
304 | # define OFFCHIP_NR_IRQS 16 | ||
305 | #elif defined (CONFIG_SH_DREAMCAST) | ||
306 | # define OFFCHIP_NR_IRQS 96 | ||
307 | #elif defined (CONFIG_SH_TITAN) | ||
308 | # define OFFCHIP_NR_IRQS 4 | ||
309 | #elif defined(CONFIG_SH_UNKNOWN) | ||
310 | # define OFFCHIP_NR_IRQS 16 /* Must also be last */ | ||
293 | #else | 311 | #else |
294 | # if defined(CONFIG_HD64461) | 312 | # define OFFCHIP_NR_IRQS 0 |
295 | # define OFFCHIP_NR_IRQS 18 | ||
296 | # elif defined (CONFIG_SH_BIGSUR) /* must be before CONFIG_HD64465 */ | ||
297 | # define OFFCHIP_NR_IRQS 48 | ||
298 | # elif defined(CONFIG_HD64465) | ||
299 | # define OFFCHIP_NR_IRQS 16 | ||
300 | # elif defined (CONFIG_SH_EC3104) | ||
301 | # define OFFCHIP_NR_IRQS 16 | ||
302 | # elif defined (CONFIG_SH_DREAMCAST) | ||
303 | # define OFFCHIP_NR_IRQS 96 | ||
304 | # else | ||
305 | # define OFFCHIP_NR_IRQS 0 | ||
306 | # endif | ||
307 | #endif | 313 | #endif |
308 | 314 | ||
309 | #if OFFCHIP_NR_IRQS > 0 | 315 | #if OFFCHIP_NR_IRQS > 0 |
@@ -313,16 +319,6 @@ | |||
313 | /* NR_IRQS. 1+2+3 */ | 319 | /* NR_IRQS. 1+2+3 */ |
314 | #define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS) | 320 | #define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS) |
315 | 321 | ||
316 | /* In a generic kernel, NR_IRQS is an upper bound, and we should use | ||
317 | * ACTUAL_NR_IRQS (which uses the machine vector) to get the correct value. | ||
318 | */ | ||
319 | #ifdef CONFIG_SH_GENERIC | ||
320 | # define ACTUAL_NR_IRQS (sh_mv.mv_nr_irqs) | ||
321 | #else | ||
322 | # define ACTUAL_NR_IRQS NR_IRQS | ||
323 | #endif | ||
324 | |||
325 | |||
326 | extern void disable_irq(unsigned int); | 322 | extern void disable_irq(unsigned int); |
327 | extern void disable_irq_nosync(unsigned int); | 323 | extern void disable_irq_nosync(unsigned int); |
328 | extern void enable_irq(unsigned int); | 324 | extern void enable_irq(unsigned int); |
@@ -542,9 +538,6 @@ extern int ipr_irq_demux(int irq); | |||
542 | 538 | ||
543 | extern int ipr_irq_demux(int irq); | 539 | extern int ipr_irq_demux(int irq); |
544 | #define __irq_demux(irq) ipr_irq_demux(irq) | 540 | #define __irq_demux(irq) ipr_irq_demux(irq) |
545 | |||
546 | #else | ||
547 | #define __irq_demux(irq) irq | ||
548 | #endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */ | 541 | #endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */ |
549 | 542 | ||
550 | #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \ | 543 | #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \ |
@@ -557,18 +550,35 @@ extern int ipr_irq_demux(int irq); | |||
557 | #define INTC_ICR_IRLM (1<<7) | 550 | #define INTC_ICR_IRLM (1<<7) |
558 | #endif | 551 | #endif |
559 | 552 | ||
560 | #ifdef CONFIG_CPU_SUBTYPE_ST40STB1 | 553 | #else |
554 | #include <asm/irq-sh7780.h> | ||
555 | #endif | ||
561 | 556 | ||
557 | /* SH with INTC2-style interrupts */ | ||
558 | #ifdef CONFIG_CPU_HAS_INTC2_IRQ | ||
559 | #if defined(CONFIG_CPU_SUBTYPE_ST40STB1) | ||
560 | #define INTC2_BASE 0xfe080000 | ||
562 | #define INTC2_FIRST_IRQ 64 | 561 | #define INTC2_FIRST_IRQ 64 |
563 | #define NR_INTC2_IRQS 25 | 562 | #define INTC2_INTREQ_OFFSET 0x20 |
564 | 563 | #define INTC2_INTMSK_OFFSET 0x40 | |
564 | #define INTC2_INTMSKCLR_OFFSET 0x60 | ||
565 | #define NR_INTC2_IRQS 25 | ||
566 | #elif defined(CONFIG_CPU_SUBTYPE_SH7760) | ||
565 | #define INTC2_BASE 0xfe080000 | 567 | #define INTC2_BASE 0xfe080000 |
566 | #define INTC2_INTC2MODE (INTC2_BASE+0x80) | 568 | #define INTC2_FIRST_IRQ 48 /* INTEVT 0x800 */ |
567 | |||
568 | #define INTC2_INTPRI_OFFSET 0x00 | ||
569 | #define INTC2_INTREQ_OFFSET 0x20 | 569 | #define INTC2_INTREQ_OFFSET 0x20 |
570 | #define INTC2_INTMSK_OFFSET 0x40 | 570 | #define INTC2_INTMSK_OFFSET 0x40 |
571 | #define INTC2_INTMSKCLR_OFFSET 0x60 | 571 | #define INTC2_INTMSKCLR_OFFSET 0x60 |
572 | #define NR_INTC2_IRQS 64 | ||
573 | #elif defined(CONFIG_CPU_SUBTYPE_SH7780) | ||
574 | #define INTC2_BASE 0xffd40000 | ||
575 | #define INTC2_FIRST_IRQ 22 | ||
576 | #define INTC2_INTMSK_OFFSET (0x38) | ||
577 | #define INTC2_INTMSKCLR_OFFSET (0x3c) | ||
578 | #define NR_INTC2_IRQS 60 | ||
579 | #endif | ||
580 | |||
581 | #define INTC2_INTPRI_OFFSET 0x00 | ||
572 | 582 | ||
573 | void make_intc2_irq(unsigned int irq, | 583 | void make_intc2_irq(unsigned int irq, |
574 | unsigned int ipr_offset, unsigned int ipr_shift, | 584 | unsigned int ipr_offset, unsigned int ipr_shift, |
@@ -577,13 +587,16 @@ void make_intc2_irq(unsigned int irq, | |||
577 | void init_IRQ_intc2(void); | 587 | void init_IRQ_intc2(void); |
578 | void intc2_add_clear_irq(int irq, int (*fn)(int)); | 588 | void intc2_add_clear_irq(int irq, int (*fn)(int)); |
579 | 589 | ||
580 | #endif /* CONFIG_CPU_SUBTYPE_ST40STB1 */ | 590 | #endif |
581 | 591 | ||
582 | static inline int generic_irq_demux(int irq) | 592 | static inline int generic_irq_demux(int irq) |
583 | { | 593 | { |
584 | return irq; | 594 | return irq; |
585 | } | 595 | } |
586 | 596 | ||
597 | #ifndef __irq_demux | ||
598 | #define __irq_demux(irq) (irq) | ||
599 | #endif | ||
587 | #define irq_canonicalize(irq) (irq) | 600 | #define irq_canonicalize(irq) (irq) |
588 | #define irq_demux(irq) __irq_demux(sh_mv.mv_irq_demux(irq)) | 601 | #define irq_demux(irq) __irq_demux(sh_mv.mv_irq_demux(irq)) |
589 | 602 | ||