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-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c2
-rw-r--r--drivers/gpu/drm/radeon/r100.c140
-rw-r--r--drivers/gpu/drm/radeon/r600.c217
-rw-r--r--drivers/gpu/drm/radeon/radeon.h25
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c14
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h4
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c91
-rw-r--r--drivers/gpu/drm/radeon/radeon_combios.c11
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_crtc.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_pm.c153
10 files changed, 413 insertions, 246 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 12fb12a2bba..b11aa37ed6d 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -251,6 +251,7 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
251 atombios_blank_crtc(crtc, ATOM_DISABLE); 251 atombios_blank_crtc(crtc, ATOM_DISABLE);
252 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); 252 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
253 radeon_crtc_load_lut(crtc); 253 radeon_crtc_load_lut(crtc);
254 radeon_crtc->enabled = true;
254 break; 255 break;
255 case DRM_MODE_DPMS_STANDBY: 256 case DRM_MODE_DPMS_STANDBY:
256 case DRM_MODE_DPMS_SUSPEND: 257 case DRM_MODE_DPMS_SUSPEND:
@@ -260,6 +261,7 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
260 if (ASIC_IS_DCE3(rdev)) 261 if (ASIC_IS_DCE3(rdev))
261 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); 262 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
262 atombios_enable_crtc(crtc, ATOM_DISABLE); 263 atombios_enable_crtc(crtc, ATOM_DISABLE);
264 radeon_crtc->enabled = false;
263 break; 265 break;
264 } 266 }
265 267
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index b076b96f8b6..a6b2aca36b4 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -67,41 +67,133 @@ MODULE_FIRMWARE(FIRMWARE_R520);
67 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 67 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
68 */ 68 */
69 69
70void r100_get_power_state(struct radeon_device *rdev,
71 enum radeon_pm_action action)
72{
73 int i;
74 rdev->pm.can_upclock = true;
75 rdev->pm.can_downclock = true;
76
77 switch (action) {
78 case PM_ACTION_MINIMUM:
79 rdev->pm.requested_power_state_index = 0;
80 rdev->pm.can_downclock = false;
81 break;
82 case PM_ACTION_DOWNCLOCK:
83 if (rdev->pm.current_power_state_index == 0) {
84 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
85 rdev->pm.can_downclock = false;
86 } else {
87 if (rdev->pm.active_crtc_count > 1) {
88 for (i = 0; i < rdev->pm.num_power_states; i++) {
89 if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
90 continue;
91 else if (i >= rdev->pm.current_power_state_index) {
92 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
93 break;
94 } else {
95 rdev->pm.requested_power_state_index = i;
96 break;
97 }
98 }
99 } else
100 rdev->pm.requested_power_state_index =
101 rdev->pm.current_power_state_index - 1;
102 }
103 break;
104 case PM_ACTION_UPCLOCK:
105 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
106 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
107 rdev->pm.can_upclock = false;
108 } else {
109 if (rdev->pm.active_crtc_count > 1) {
110 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
111 if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
112 continue;
113 else if (i <= rdev->pm.current_power_state_index) {
114 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
115 break;
116 } else {
117 rdev->pm.requested_power_state_index = i;
118 break;
119 }
120 }
121 } else
122 rdev->pm.requested_power_state_index =
123 rdev->pm.current_power_state_index + 1;
124 }
125 break;
126 case PM_ACTION_NONE:
127 default:
128 DRM_ERROR("Requested mode for not defined action\n");
129 return;
130 }
131 /* only one clock mode per power state */
132 rdev->pm.requested_clock_mode_index = 0;
133
134 DRM_INFO("Requested: e: %d m: %d p: %d\n",
135 rdev->pm.power_state[rdev->pm.requested_power_state_index].
136 clock_info[rdev->pm.requested_clock_mode_index].sclk,
137 rdev->pm.power_state[rdev->pm.requested_power_state_index].
138 clock_info[rdev->pm.requested_clock_mode_index].mclk,
139 rdev->pm.power_state[rdev->pm.requested_power_state_index].
140 non_clock_info.pcie_lanes);
141}
142
70void r100_set_power_state(struct radeon_device *rdev) 143void r100_set_power_state(struct radeon_device *rdev)
71{ 144{
72 /* if *_clock_mode are the same, *_power_state are as well */ 145 u32 sclk, mclk;
73 if (rdev->pm.requested_clock_mode == rdev->pm.current_clock_mode) 146
147 if (rdev->pm.current_power_state_index == rdev->pm.requested_power_state_index)
74 return; 148 return;
75 149
76 DRM_INFO("Setting: e: %d m: %d p: %d\n", 150 if (radeon_gui_idle(rdev)) {
77 rdev->pm.requested_clock_mode->sclk,
78 rdev->pm.requested_clock_mode->mclk,
79 rdev->pm.requested_power_state->non_clock_info.pcie_lanes);
80 151
81 /* set pcie lanes */ 152 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
82 /* TODO */ 153 clock_info[rdev->pm.requested_clock_mode_index].sclk;
154 if (sclk > rdev->clock.default_sclk)
155 sclk = rdev->clock.default_sclk;
83 156
84 /* set voltage */ 157 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
85 /* TODO */ 158 clock_info[rdev->pm.requested_clock_mode_index].mclk;
159 if (mclk > rdev->clock.default_mclk)
160 mclk = rdev->clock.default_mclk;
161 /* don't change the mclk with multiple crtcs */
162 if (rdev->pm.active_crtc_count > 1)
163 mclk = rdev->clock.default_mclk;
86 164
87 /* set engine clock */ 165 /* set pcie lanes */
88 radeon_sync_with_vblank(rdev); 166 /* TODO */
89 radeon_pm_debug_check_in_vbl(rdev, false); 167
90 radeon_set_engine_clock(rdev, rdev->pm.requested_clock_mode->sclk); 168 /* set voltage */
91 radeon_pm_debug_check_in_vbl(rdev, true); 169 /* TODO */
170
171 /* set engine clock */
172 if (sclk != rdev->pm.current_sclk) {
173 radeon_sync_with_vblank(rdev);
174 radeon_pm_debug_check_in_vbl(rdev, false);
175 radeon_set_engine_clock(rdev, sclk);
176 radeon_pm_debug_check_in_vbl(rdev, true);
177 rdev->pm.current_sclk = sclk;
178 DRM_INFO("Setting: e: %d\n", sclk);
179 }
92 180
93#if 0 181#if 0
94 /* set memory clock */ 182 /* set memory clock */
95 if (rdev->asic->set_memory_clock) { 183 if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
96 radeon_sync_with_vblank(rdev); 184 radeon_sync_with_vblank(rdev);
97 radeon_pm_debug_check_in_vbl(rdev, false); 185 radeon_pm_debug_check_in_vbl(rdev, false);
98 radeon_set_memory_clock(rdev, rdev->pm.requested_clock_mode->mclk); 186 radeon_set_memory_clock(rdev, mclk);
99 radeon_pm_debug_check_in_vbl(rdev, true); 187 radeon_pm_debug_check_in_vbl(rdev, true);
100 } 188 rdev->pm.current_mclk = mclk;
189 DRM_INFO("Setting: m: %d\n", mclk);
190 }
101#endif 191#endif
102 192
103 rdev->pm.current_power_state = rdev->pm.requested_power_state; 193 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
104 rdev->pm.current_clock_mode = rdev->pm.requested_clock_mode; 194 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
195 } else
196 DRM_INFO("GUI not idle!!!\n");
105} 197}
106 198
107bool r100_gui_idle(struct radeon_device *rdev) 199bool r100_gui_idle(struct radeon_device *rdev)
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index c2d1946535a..cc2797949ee 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -92,41 +92,206 @@ void r600_gpu_init(struct radeon_device *rdev);
92void r600_fini(struct radeon_device *rdev); 92void r600_fini(struct radeon_device *rdev);
93void r600_irq_disable(struct radeon_device *rdev); 93void r600_irq_disable(struct radeon_device *rdev);
94 94
95void r600_set_power_state(struct radeon_device *rdev) 95void r600_get_power_state(struct radeon_device *rdev,
96 enum radeon_pm_action action)
96{ 97{
97 /* if *_clock_mode are the same, *_power_state are as well */ 98 int i;
98 if (rdev->pm.requested_clock_mode == rdev->pm.current_clock_mode) 99
99 return; 100 rdev->pm.can_upclock = true;
101 rdev->pm.can_downclock = true;
102
103 /* power state array is low to high, default is first */
104 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
105 int min_power_state_index = 0;
106
107 if (rdev->pm.num_power_states > 2)
108 min_power_state_index = 1;
109
110 switch (action) {
111 case PM_ACTION_MINIMUM:
112 rdev->pm.requested_power_state_index = min_power_state_index;
113 rdev->pm.requested_clock_mode_index = 0;
114 rdev->pm.can_downclock = false;
115 break;
116 case PM_ACTION_DOWNCLOCK:
117 if (rdev->pm.current_power_state_index == min_power_state_index) {
118 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
119 rdev->pm.can_downclock = false;
120 } else {
121 if (rdev->pm.active_crtc_count > 1) {
122 for (i = 0; i < rdev->pm.num_power_states; i++) {
123 if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
124 continue;
125 else if (i >= rdev->pm.current_power_state_index) {
126 rdev->pm.requested_power_state_index =
127 rdev->pm.current_power_state_index;
128 break;
129 } else {
130 rdev->pm.requested_power_state_index = i;
131 break;
132 }
133 }
134 } else
135 rdev->pm.requested_power_state_index =
136 rdev->pm.current_power_state_index - 1;
137 }
138 rdev->pm.requested_clock_mode_index = 0;
139 break;
140 case PM_ACTION_UPCLOCK:
141 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
142 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
143 rdev->pm.can_upclock = false;
144 } else {
145 if (rdev->pm.active_crtc_count > 1) {
146 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
147 if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
148 continue;
149 else if (i <= rdev->pm.current_power_state_index) {
150 rdev->pm.requested_power_state_index =
151 rdev->pm.current_power_state_index;
152 break;
153 } else {
154 rdev->pm.requested_power_state_index = i;
155 break;
156 }
157 }
158 } else
159 rdev->pm.requested_power_state_index =
160 rdev->pm.current_power_state_index + 1;
161 }
162 rdev->pm.requested_clock_mode_index = 0;
163 break;
164 case PM_ACTION_NONE:
165 default:
166 DRM_ERROR("Requested mode for not defined action\n");
167 return;
168 }
169 } else {
170 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
171 /* for now just select the first power state and switch between clock modes */
172 /* power state array is low to high, default is first (0) */
173 if (rdev->pm.active_crtc_count > 1) {
174 rdev->pm.requested_power_state_index = -1;
175 /* start at 1 as we don't want the default mode */
176 for (i = 1; i < rdev->pm.num_power_states; i++) {
177 if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
178 continue;
179 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
180 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
181 rdev->pm.requested_power_state_index = i;
182 break;
183 }
184 }
185 /* if nothing selected, grab the default state. */
186 if (rdev->pm.requested_power_state_index == -1)
187 rdev->pm.requested_power_state_index = 0;
188 } else
189 rdev->pm.requested_power_state_index = 1;
190
191 switch (action) {
192 case PM_ACTION_MINIMUM:
193 rdev->pm.requested_clock_mode_index = 0;
194 rdev->pm.can_downclock = false;
195 break;
196 case PM_ACTION_DOWNCLOCK:
197 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
198 if (rdev->pm.current_clock_mode_index == 0) {
199 rdev->pm.requested_clock_mode_index = 0;
200 rdev->pm.can_downclock = false;
201 } else
202 rdev->pm.requested_clock_mode_index =
203 rdev->pm.current_clock_mode_index - 1;
204 } else {
205 rdev->pm.requested_clock_mode_index = 0;
206 rdev->pm.can_downclock = false;
207 }
208 break;
209 case PM_ACTION_UPCLOCK:
210 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
211 if (rdev->pm.current_clock_mode_index ==
212 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
213 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
214 rdev->pm.can_upclock = false;
215 } else
216 rdev->pm.requested_clock_mode_index =
217 rdev->pm.current_clock_mode_index + 1;
218 } else {
219 rdev->pm.requested_clock_mode_index =
220 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
221 rdev->pm.can_upclock = false;
222 }
223 break;
224 case PM_ACTION_NONE:
225 default:
226 DRM_ERROR("Requested mode for not defined action\n");
227 return;
228 }
229 }
100 230
101 DRM_INFO("Setting: e: %d m: %d p: %d\n", 231 DRM_INFO("Requested: e: %d m: %d p: %d\n",
102 rdev->pm.requested_clock_mode->sclk, 232 rdev->pm.power_state[rdev->pm.requested_power_state_index].
103 rdev->pm.requested_clock_mode->mclk, 233 clock_info[rdev->pm.requested_clock_mode_index].sclk,
104 rdev->pm.requested_power_state->non_clock_info.pcie_lanes); 234 rdev->pm.power_state[rdev->pm.requested_power_state_index].
235 clock_info[rdev->pm.requested_clock_mode_index].mclk,
236 rdev->pm.power_state[rdev->pm.requested_power_state_index].
237 non_clock_info.pcie_lanes);
238}
105 239
106 /* set pcie lanes */ 240void r600_set_power_state(struct radeon_device *rdev)
107 /* TODO */ 241{
242 u32 sclk, mclk;
108 243
109 /* set voltage */ 244 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
110 /* TODO */ 245 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
246 return;
111 247
112 /* set engine clock */ 248 if (radeon_gui_idle(rdev)) {
113 radeon_sync_with_vblank(rdev); 249
114 radeon_pm_debug_check_in_vbl(rdev, false); 250 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
115 radeon_set_engine_clock(rdev, rdev->pm.requested_clock_mode->sclk); 251 clock_info[rdev->pm.requested_clock_mode_index].sclk;
116 radeon_pm_debug_check_in_vbl(rdev, true); 252 if (sclk > rdev->clock.default_sclk)
253 sclk = rdev->clock.default_sclk;
254
255 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
256 clock_info[rdev->pm.requested_clock_mode_index].mclk;
257 if (mclk > rdev->clock.default_mclk)
258 mclk = rdev->clock.default_mclk;
259 /* don't change the mclk with multiple crtcs */
260 if (rdev->pm.active_crtc_count > 1)
261 mclk = rdev->clock.default_mclk;
262
263 /* set pcie lanes */
264 /* TODO */
265
266 /* set voltage */
267 /* TODO */
268
269 /* set engine clock */
270 if (sclk != rdev->pm.current_sclk) {
271 radeon_sync_with_vblank(rdev);
272 radeon_pm_debug_check_in_vbl(rdev, false);
273 radeon_set_engine_clock(rdev, sclk);
274 radeon_pm_debug_check_in_vbl(rdev, true);
275 rdev->pm.current_sclk = sclk;
276 DRM_INFO("Setting: e: %d\n", sclk);
277 }
117 278
118#if 0 279#if 0
119 /* set memory clock */ 280 /* set memory clock */
120 if (rdev->asic->set_memory_clock) { 281 if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
121 radeon_sync_with_vblank(rdev); 282 radeon_sync_with_vblank(rdev);
122 radeon_pm_debug_check_in_vbl(rdev, false); 283 radeon_pm_debug_check_in_vbl(rdev, false);
123 radeon_set_memory_clock(rdev, rdev->pm.requested_clock_mode->mclk); 284 radeon_set_memory_clock(rdev, mclk);
124 radeon_pm_debug_check_in_vbl(rdev, true); 285 radeon_pm_debug_check_in_vbl(rdev, true);
125 } 286 rdev->pm.current_mclk = mclk;
287 DRM_INFO("Setting: m: %d\n", mclk);
288 }
126#endif 289#endif
127 290
128 rdev->pm.current_power_state = rdev->pm.requested_power_state; 291 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
129 rdev->pm.current_clock_mode = rdev->pm.requested_clock_mode; 292 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
293 } else
294 DRM_INFO("GUI not idle!!!\n");
130} 295}
131 296
132bool r600_gui_idle(struct radeon_device *rdev) 297bool r600_gui_idle(struct radeon_device *rdev)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 11fe1d1444c..b5eccc4094e 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -672,6 +672,9 @@ struct radeon_pm_clock_info {
672 u32 flags; 672 u32 flags;
673}; 673};
674 674
675/* state flags */
676#define RADEON_PM_SINGLE_DISPLAY_ONLY (1 << 0)
677
675struct radeon_power_state { 678struct radeon_power_state {
676 enum radeon_pm_state_type type; 679 enum radeon_pm_state_type type;
677 /* XXX: use a define for num clock modes */ 680 /* XXX: use a define for num clock modes */
@@ -682,6 +685,8 @@ struct radeon_power_state {
682 /* non clock info about this state */ 685 /* non clock info about this state */
683 struct radeon_pm_non_clock_info non_clock_info; 686 struct radeon_pm_non_clock_info non_clock_info;
684 bool voltage_drop_active; 687 bool voltage_drop_active;
688 /* standardized state flags */
689 u32 flags;
685}; 690};
686 691
687/* 692/*
@@ -695,8 +700,10 @@ struct radeon_pm {
695 enum radeon_pm_state state; 700 enum radeon_pm_state state;
696 enum radeon_pm_action planned_action; 701 enum radeon_pm_action planned_action;
697 unsigned long action_timeout; 702 unsigned long action_timeout;
698 bool downclocked; 703 bool can_upclock;
699 int active_crtcs; 704 bool can_downclock;
705 u32 active_crtcs;
706 int active_crtc_count;
700 int req_vblank; 707 int req_vblank;
701 bool vblank_sync; 708 bool vblank_sync;
702 bool gui_idle; 709 bool gui_idle;
@@ -716,11 +723,13 @@ struct radeon_pm {
716 struct radeon_power_state power_state[8]; 723 struct radeon_power_state power_state[8];
717 /* number of valid power states */ 724 /* number of valid power states */
718 int num_power_states; 725 int num_power_states;
719 struct radeon_power_state *current_power_state; 726 int current_power_state_index;
720 struct radeon_pm_clock_info *current_clock_mode; 727 int current_clock_mode_index;
721 struct radeon_power_state *requested_power_state; 728 int requested_power_state_index;
722 struct radeon_pm_clock_info *requested_clock_mode; 729 int requested_clock_mode_index;
723 struct radeon_power_state *default_power_state; 730 int default_power_state_index;
731 u32 current_sclk;
732 u32 current_mclk;
724 struct radeon_i2c_chan *i2c_bus; 733 struct radeon_i2c_chan *i2c_bus;
725}; 734};
726 735
@@ -810,6 +819,7 @@ struct radeon_asic {
810 */ 819 */
811 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); 820 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
812 bool (*gui_idle)(struct radeon_device *rdev); 821 bool (*gui_idle)(struct radeon_device *rdev);
822 void (*get_power_state)(struct radeon_device *rdev, enum radeon_pm_action action);
813 void (*set_power_state)(struct radeon_device *rdev); 823 void (*set_power_state)(struct radeon_device *rdev);
814}; 824};
815 825
@@ -1218,6 +1228,7 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1218#define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd)) 1228#define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1219#define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd)) 1229#define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1220#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 1230#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1231#define radeon_get_power_state(rdev, a) (rdev)->asic->get_power_state((rdev), (a))
1221#define radeon_set_power_state(rdev) (rdev)->asic->set_power_state((rdev)) 1232#define radeon_set_power_state(rdev) (rdev)->asic->set_power_state((rdev))
1222 1233
1223/* Common functions */ 1234/* Common functions */
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index 48893fbb658..1053115ba65 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -166,6 +166,7 @@ static struct radeon_asic r100_asic = {
166 .hpd_set_polarity = &r100_hpd_set_polarity, 166 .hpd_set_polarity = &r100_hpd_set_polarity,
167 .ioctl_wait_idle = NULL, 167 .ioctl_wait_idle = NULL,
168 .gui_idle = &r100_gui_idle, 168 .gui_idle = &r100_gui_idle,
169 .get_power_state = &r100_get_power_state,
169 .set_power_state = &r100_set_power_state, 170 .set_power_state = &r100_set_power_state,
170}; 171};
171 172
@@ -206,6 +207,7 @@ static struct radeon_asic r200_asic = {
206 .hpd_set_polarity = &r100_hpd_set_polarity, 207 .hpd_set_polarity = &r100_hpd_set_polarity,
207 .ioctl_wait_idle = NULL, 208 .ioctl_wait_idle = NULL,
208 .gui_idle = &r100_gui_idle, 209 .gui_idle = &r100_gui_idle,
210 .get_power_state = &r100_get_power_state,
209 .set_power_state = &r100_set_power_state, 211 .set_power_state = &r100_set_power_state,
210}; 212};
211 213
@@ -247,6 +249,7 @@ static struct radeon_asic r300_asic = {
247 .hpd_set_polarity = &r100_hpd_set_polarity, 249 .hpd_set_polarity = &r100_hpd_set_polarity,
248 .ioctl_wait_idle = NULL, 250 .ioctl_wait_idle = NULL,
249 .gui_idle = &r100_gui_idle, 251 .gui_idle = &r100_gui_idle,
252 .get_power_state = &r100_get_power_state,
250 .set_power_state = &r100_set_power_state, 253 .set_power_state = &r100_set_power_state,
251}; 254};
252 255
@@ -287,6 +290,7 @@ static struct radeon_asic r300_asic_pcie = {
287 .hpd_set_polarity = &r100_hpd_set_polarity, 290 .hpd_set_polarity = &r100_hpd_set_polarity,
288 .ioctl_wait_idle = NULL, 291 .ioctl_wait_idle = NULL,
289 .gui_idle = &r100_gui_idle, 292 .gui_idle = &r100_gui_idle,
293 .get_power_state = &r100_get_power_state,
290 .set_power_state = &r100_set_power_state, 294 .set_power_state = &r100_set_power_state,
291}; 295};
292 296
@@ -328,6 +332,7 @@ static struct radeon_asic r420_asic = {
328 .hpd_set_polarity = &r100_hpd_set_polarity, 332 .hpd_set_polarity = &r100_hpd_set_polarity,
329 .ioctl_wait_idle = NULL, 333 .ioctl_wait_idle = NULL,
330 .gui_idle = &r100_gui_idle, 334 .gui_idle = &r100_gui_idle,
335 .get_power_state = &r100_get_power_state,
331 .set_power_state = &r100_set_power_state, 336 .set_power_state = &r100_set_power_state,
332}; 337};
333 338
@@ -369,6 +374,7 @@ static struct radeon_asic rs400_asic = {
369 .hpd_set_polarity = &r100_hpd_set_polarity, 374 .hpd_set_polarity = &r100_hpd_set_polarity,
370 .ioctl_wait_idle = NULL, 375 .ioctl_wait_idle = NULL,
371 .gui_idle = &r100_gui_idle, 376 .gui_idle = &r100_gui_idle,
377 .get_power_state = &r100_get_power_state,
372 .set_power_state = &r100_set_power_state, 378 .set_power_state = &r100_set_power_state,
373}; 379};
374 380
@@ -410,6 +416,7 @@ static struct radeon_asic rs600_asic = {
410 .hpd_set_polarity = &rs600_hpd_set_polarity, 416 .hpd_set_polarity = &rs600_hpd_set_polarity,
411 .ioctl_wait_idle = NULL, 417 .ioctl_wait_idle = NULL,
412 .gui_idle = &r100_gui_idle, 418 .gui_idle = &r100_gui_idle,
419 .get_power_state = &r100_get_power_state,
413 .set_power_state = &r100_set_power_state, 420 .set_power_state = &r100_set_power_state,
414}; 421};
415 422
@@ -451,6 +458,7 @@ static struct radeon_asic rs690_asic = {
451 .hpd_set_polarity = &rs600_hpd_set_polarity, 458 .hpd_set_polarity = &rs600_hpd_set_polarity,
452 .ioctl_wait_idle = NULL, 459 .ioctl_wait_idle = NULL,
453 .gui_idle = &r100_gui_idle, 460 .gui_idle = &r100_gui_idle,
461 .get_power_state = &r100_get_power_state,
454 .set_power_state = &r100_set_power_state, 462 .set_power_state = &r100_set_power_state,
455}; 463};
456 464
@@ -492,6 +500,7 @@ static struct radeon_asic rv515_asic = {
492 .hpd_set_polarity = &rs600_hpd_set_polarity, 500 .hpd_set_polarity = &rs600_hpd_set_polarity,
493 .ioctl_wait_idle = NULL, 501 .ioctl_wait_idle = NULL,
494 .gui_idle = &r100_gui_idle, 502 .gui_idle = &r100_gui_idle,
503 .get_power_state = &r100_get_power_state,
495 .set_power_state = &r100_set_power_state, 504 .set_power_state = &r100_set_power_state,
496}; 505};
497 506
@@ -533,6 +542,7 @@ static struct radeon_asic r520_asic = {
533 .hpd_set_polarity = &rs600_hpd_set_polarity, 542 .hpd_set_polarity = &rs600_hpd_set_polarity,
534 .ioctl_wait_idle = NULL, 543 .ioctl_wait_idle = NULL,
535 .gui_idle = &r100_gui_idle, 544 .gui_idle = &r100_gui_idle,
545 .get_power_state = &r100_get_power_state,
536 .set_power_state = &r100_set_power_state, 546 .set_power_state = &r100_set_power_state,
537}; 547};
538 548
@@ -573,6 +583,7 @@ static struct radeon_asic r600_asic = {
573 .hpd_set_polarity = &r600_hpd_set_polarity, 583 .hpd_set_polarity = &r600_hpd_set_polarity,
574 .ioctl_wait_idle = r600_ioctl_wait_idle, 584 .ioctl_wait_idle = r600_ioctl_wait_idle,
575 .gui_idle = &r600_gui_idle, 585 .gui_idle = &r600_gui_idle,
586 .get_power_state = &r600_get_power_state,
576 .set_power_state = &r600_set_power_state, 587 .set_power_state = &r600_set_power_state,
577}; 588};
578 589
@@ -613,6 +624,7 @@ static struct radeon_asic rs780_asic = {
613 .hpd_set_polarity = &r600_hpd_set_polarity, 624 .hpd_set_polarity = &r600_hpd_set_polarity,
614 .ioctl_wait_idle = r600_ioctl_wait_idle, 625 .ioctl_wait_idle = r600_ioctl_wait_idle,
615 .gui_idle = &r600_gui_idle, 626 .gui_idle = &r600_gui_idle,
627 .get_power_state = &r600_get_power_state,
616 .set_power_state = &r600_set_power_state, 628 .set_power_state = &r600_set_power_state,
617}; 629};
618 630
@@ -653,6 +665,7 @@ static struct radeon_asic rv770_asic = {
653 .hpd_set_polarity = &r600_hpd_set_polarity, 665 .hpd_set_polarity = &r600_hpd_set_polarity,
654 .ioctl_wait_idle = r600_ioctl_wait_idle, 666 .ioctl_wait_idle = r600_ioctl_wait_idle,
655 .gui_idle = &r600_gui_idle, 667 .gui_idle = &r600_gui_idle,
668 .get_power_state = &r600_get_power_state,
656 .set_power_state = &r600_set_power_state, 669 .set_power_state = &r600_set_power_state,
657}; 670};
658 671
@@ -691,6 +704,7 @@ static struct radeon_asic evergreen_asic = {
691 .hpd_sense = &evergreen_hpd_sense, 704 .hpd_sense = &evergreen_hpd_sense,
692 .hpd_set_polarity = &evergreen_hpd_set_polarity, 705 .hpd_set_polarity = &evergreen_hpd_set_polarity,
693 .gui_idle = &r600_gui_idle, 706 .gui_idle = &r600_gui_idle,
707 .get_power_state = &r600_get_power_state,
694 .set_power_state = &r600_set_power_state, 708 .set_power_state = &r600_set_power_state,
695}; 709};
696 710
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 90d8e6dee52..71b21bb4e5f 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -128,6 +128,8 @@ void r100_set_common_regs(struct radeon_device *rdev);
128void r100_bm_disable(struct radeon_device *rdev); 128void r100_bm_disable(struct radeon_device *rdev);
129extern bool r100_gui_idle(struct radeon_device *rdev); 129extern bool r100_gui_idle(struct radeon_device *rdev);
130extern void r100_set_power_state(struct radeon_device *rdev); 130extern void r100_set_power_state(struct radeon_device *rdev);
131extern void r100_get_power_state(struct radeon_device *rdev,
132 enum radeon_pm_action action);
131 133
132/* 134/*
133 * r200,rv250,rs300,rv280 135 * r200,rv250,rs300,rv280
@@ -274,6 +276,8 @@ void r600_hpd_set_polarity(struct radeon_device *rdev,
274extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo); 276extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
275extern bool r600_gui_idle(struct radeon_device *rdev); 277extern bool r600_gui_idle(struct radeon_device *rdev);
276extern void r600_set_power_state(struct radeon_device *rdev); 278extern void r600_set_power_state(struct radeon_device *rdev);
279extern void r600_get_power_state(struct radeon_device *rdev,
280 enum radeon_pm_action action);
277 281
278/* 282/*
279 * rv770,rv730,rv710,rv740 283 * rv770,rv730,rv710,rv740
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index aa0a973a8af..dbfb837d224 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -1489,7 +1489,7 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1489 int state_index = 0, mode_index = 0; 1489 int state_index = 0, mode_index = 0;
1490 struct radeon_i2c_bus_rec i2c_bus; 1490 struct radeon_i2c_bus_rec i2c_bus;
1491 1491
1492 rdev->pm.default_power_state = NULL; 1492 rdev->pm.default_power_state_index = -1;
1493 1493
1494 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1494 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1495 &frev, &crev, &data_offset)) { 1495 &frev, &crev, &data_offset)) {
@@ -1520,12 +1520,6 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1520 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 1520 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1521 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 1521 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1522 continue; 1522 continue;
1523 /* skip overclock modes for now */
1524 if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1525 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1526 (rdev->pm.power_state[state_index].clock_info[0].sclk >
1527 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1528 continue;
1529 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 1523 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1530 power_info->info.asPowerPlayInfo[i].ucNumPciELanes; 1524 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1531 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo); 1525 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
@@ -1547,6 +1541,7 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1547 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 1541 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1548 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex; 1542 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1549 } 1543 }
1544 rdev->pm.power_state[state_index].flags = RADEON_PM_SINGLE_DISPLAY_ONLY;
1550 /* order matters! */ 1545 /* order matters! */
1551 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE) 1546 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1552 rdev->pm.power_state[state_index].type = 1547 rdev->pm.power_state[state_index].type =
@@ -1560,15 +1555,20 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1560 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN) 1555 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1561 rdev->pm.power_state[state_index].type = 1556 rdev->pm.power_state[state_index].type =
1562 POWER_STATE_TYPE_BALANCED; 1557 POWER_STATE_TYPE_BALANCED;
1563 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) 1558 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1564 rdev->pm.power_state[state_index].type = 1559 rdev->pm.power_state[state_index].type =
1565 POWER_STATE_TYPE_PERFORMANCE; 1560 POWER_STATE_TYPE_PERFORMANCE;
1561 rdev->pm.power_state[state_index].flags &=
1562 ~RADEON_PM_SINGLE_DISPLAY_ONLY;
1563 }
1566 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { 1564 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1567 rdev->pm.power_state[state_index].type = 1565 rdev->pm.power_state[state_index].type =
1568 POWER_STATE_TYPE_DEFAULT; 1566 POWER_STATE_TYPE_DEFAULT;
1569 rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; 1567 rdev->pm.default_power_state_index = state_index;
1570 rdev->pm.power_state[state_index].default_clock_mode = 1568 rdev->pm.power_state[state_index].default_clock_mode =
1571 &rdev->pm.power_state[state_index].clock_info[0]; 1569 &rdev->pm.power_state[state_index].clock_info[0];
1570 rdev->pm.power_state[state_index].flags &=
1571 ~RADEON_PM_SINGLE_DISPLAY_ONLY;
1572 } 1572 }
1573 state_index++; 1573 state_index++;
1574 break; 1574 break;
@@ -1582,12 +1582,6 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1582 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 1582 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1583 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 1583 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1584 continue; 1584 continue;
1585 /* skip overclock modes for now */
1586 if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1587 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1588 (rdev->pm.power_state[state_index].clock_info[0].sclk >
1589 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1590 continue;
1591 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 1585 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1592 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes; 1586 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1593 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo); 1587 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
@@ -1610,6 +1604,7 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1610 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 1604 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1611 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex; 1605 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1612 } 1606 }
1607 rdev->pm.power_state[state_index].flags = RADEON_PM_SINGLE_DISPLAY_ONLY;
1613 /* order matters! */ 1608 /* order matters! */
1614 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE) 1609 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1615 rdev->pm.power_state[state_index].type = 1610 rdev->pm.power_state[state_index].type =
@@ -1623,18 +1618,26 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1623 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN) 1618 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1624 rdev->pm.power_state[state_index].type = 1619 rdev->pm.power_state[state_index].type =
1625 POWER_STATE_TYPE_BALANCED; 1620 POWER_STATE_TYPE_BALANCED;
1626 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) 1621 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1627 rdev->pm.power_state[state_index].type = 1622 rdev->pm.power_state[state_index].type =
1628 POWER_STATE_TYPE_PERFORMANCE; 1623 POWER_STATE_TYPE_PERFORMANCE;
1624 rdev->pm.power_state[state_index].flags &=
1625 ~RADEON_PM_SINGLE_DISPLAY_ONLY;
1626 }
1629 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE) 1627 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1630 rdev->pm.power_state[state_index].type = 1628 rdev->pm.power_state[state_index].type =
1631 POWER_STATE_TYPE_BALANCED; 1629 POWER_STATE_TYPE_BALANCED;
1630 if (misc2 & ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT)
1631 rdev->pm.power_state[state_index].flags &=
1632 ~RADEON_PM_SINGLE_DISPLAY_ONLY;
1632 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { 1633 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1633 rdev->pm.power_state[state_index].type = 1634 rdev->pm.power_state[state_index].type =
1634 POWER_STATE_TYPE_DEFAULT; 1635 POWER_STATE_TYPE_DEFAULT;
1635 rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; 1636 rdev->pm.default_power_state_index = state_index;
1636 rdev->pm.power_state[state_index].default_clock_mode = 1637 rdev->pm.power_state[state_index].default_clock_mode =
1637 &rdev->pm.power_state[state_index].clock_info[0]; 1638 &rdev->pm.power_state[state_index].clock_info[0];
1639 rdev->pm.power_state[state_index].flags &=
1640 ~RADEON_PM_SINGLE_DISPLAY_ONLY;
1638 } 1641 }
1639 state_index++; 1642 state_index++;
1640 break; 1643 break;
@@ -1648,12 +1651,6 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1648 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 1651 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1649 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 1652 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1650 continue; 1653 continue;
1651 /* skip overclock modes for now */
1652 if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1653 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1654 (rdev->pm.power_state[state_index].clock_info[0].sclk >
1655 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1656 continue;
1657 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 1654 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1658 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes; 1655 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1659 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo); 1656 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
@@ -1682,6 +1679,7 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1682 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex; 1679 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1683 } 1680 }
1684 } 1681 }
1682 rdev->pm.power_state[state_index].flags = RADEON_PM_SINGLE_DISPLAY_ONLY;
1685 /* order matters! */ 1683 /* order matters! */
1686 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE) 1684 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1687 rdev->pm.power_state[state_index].type = 1685 rdev->pm.power_state[state_index].type =
@@ -1695,16 +1693,19 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1695 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN) 1693 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1696 rdev->pm.power_state[state_index].type = 1694 rdev->pm.power_state[state_index].type =
1697 POWER_STATE_TYPE_BALANCED; 1695 POWER_STATE_TYPE_BALANCED;
1698 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) 1696 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1699 rdev->pm.power_state[state_index].type = 1697 rdev->pm.power_state[state_index].type =
1700 POWER_STATE_TYPE_PERFORMANCE; 1698 POWER_STATE_TYPE_PERFORMANCE;
1699 rdev->pm.power_state[state_index].flags &=
1700 ~RADEON_PM_SINGLE_DISPLAY_ONLY;
1701 }
1701 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE) 1702 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1702 rdev->pm.power_state[state_index].type = 1703 rdev->pm.power_state[state_index].type =
1703 POWER_STATE_TYPE_BALANCED; 1704 POWER_STATE_TYPE_BALANCED;
1704 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { 1705 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1705 rdev->pm.power_state[state_index].type = 1706 rdev->pm.power_state[state_index].type =
1706 POWER_STATE_TYPE_DEFAULT; 1707 POWER_STATE_TYPE_DEFAULT;
1707 rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; 1708 rdev->pm.default_power_state_index = state_index;
1708 rdev->pm.power_state[state_index].default_clock_mode = 1709 rdev->pm.power_state[state_index].default_clock_mode =
1709 &rdev->pm.power_state[state_index].clock_info[0]; 1710 &rdev->pm.power_state[state_index].clock_info[0];
1710 } 1711 }
@@ -1713,12 +1714,14 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1713 } 1714 }
1714 } 1715 }
1715 /* last mode is usually default */ 1716 /* last mode is usually default */
1716 if (!rdev->pm.default_power_state) { 1717 if (rdev->pm.default_power_state_index == -1) {
1717 rdev->pm.power_state[state_index - 1].type = 1718 rdev->pm.power_state[state_index - 1].type =
1718 POWER_STATE_TYPE_DEFAULT; 1719 POWER_STATE_TYPE_DEFAULT;
1719 rdev->pm.default_power_state = &rdev->pm.power_state[state_index - 1]; 1720 rdev->pm.default_power_state_index = state_index - 1;
1720 rdev->pm.power_state[state_index - 1].default_clock_mode = 1721 rdev->pm.power_state[state_index - 1].default_clock_mode =
1721 &rdev->pm.power_state[state_index - 1].clock_info[0]; 1722 &rdev->pm.power_state[state_index - 1].clock_info[0];
1723 rdev->pm.power_state[state_index].flags &=
1724 ~RADEON_PM_SINGLE_DISPLAY_ONLY;
1722 } 1725 }
1723 } else { 1726 } else {
1724 /* add the i2c bus for thermal/fan chip */ 1727 /* add the i2c bus for thermal/fan chip */
@@ -1774,10 +1777,6 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1774 /* skip invalid modes */ 1777 /* skip invalid modes */
1775 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0) 1778 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
1776 continue; 1779 continue;
1777 /* skip overclock modes for now */
1778 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
1779 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN)
1780 continue;
1781 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 1780 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1782 VOLTAGE_SW; 1781 VOLTAGE_SW;
1783 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 1782 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
@@ -1801,12 +1800,6 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1801 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) || 1800 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
1802 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)) 1801 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
1803 continue; 1802 continue;
1804 /* skip overclock modes for now */
1805 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk >
1806 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1807 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
1808 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1809 continue;
1810 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 1803 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1811 VOLTAGE_SW; 1804 VOLTAGE_SW;
1812 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 1805 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
@@ -1831,12 +1824,6 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1831 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) || 1824 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
1832 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)) 1825 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
1833 continue; 1826 continue;
1834 /* skip overclock modes for now */
1835 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk >
1836 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1837 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
1838 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1839 continue;
1840 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 1827 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1841 VOLTAGE_SW; 1828 VOLTAGE_SW;
1842 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 1829 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
@@ -1865,10 +1852,14 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1865 POWER_STATE_TYPE_PERFORMANCE; 1852 POWER_STATE_TYPE_PERFORMANCE;
1866 break; 1853 break;
1867 } 1854 }
1855 rdev->pm.power_state[state_index].flags = 0;
1856 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
1857 rdev->pm.power_state[state_index].flags |=
1858 RADEON_PM_SINGLE_DISPLAY_ONLY;
1868 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) { 1859 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
1869 rdev->pm.power_state[state_index].type = 1860 rdev->pm.power_state[state_index].type =
1870 POWER_STATE_TYPE_DEFAULT; 1861 POWER_STATE_TYPE_DEFAULT;
1871 rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; 1862 rdev->pm.default_power_state_index = state_index;
1872 rdev->pm.power_state[state_index].default_clock_mode = 1863 rdev->pm.power_state[state_index].default_clock_mode =
1873 &rdev->pm.power_state[state_index].clock_info[mode_index - 1]; 1864 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
1874 } 1865 }
@@ -1876,10 +1867,10 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1876 } 1867 }
1877 } 1868 }
1878 /* first mode is usually default */ 1869 /* first mode is usually default */
1879 if (!rdev->pm.default_power_state) { 1870 if (rdev->pm.default_power_state_index == -1) {
1880 rdev->pm.power_state[0].type = 1871 rdev->pm.power_state[0].type =
1881 POWER_STATE_TYPE_DEFAULT; 1872 POWER_STATE_TYPE_DEFAULT;
1882 rdev->pm.default_power_state = &rdev->pm.power_state[0]; 1873 rdev->pm.default_power_state_index = 0;
1883 rdev->pm.power_state[0].default_clock_mode = 1874 rdev->pm.power_state[0].default_clock_mode =
1884 &rdev->pm.power_state[0].clock_info[0]; 1875 &rdev->pm.power_state[0].clock_info[0];
1885 } 1876 }
@@ -1898,15 +1889,15 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1898 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev); 1889 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev);
1899 else 1890 else
1900 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16; 1891 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16;
1901 rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; 1892 rdev->pm.default_power_state_index = state_index;
1893 rdev->pm.power_state[state_index].flags = 0;
1902 state_index++; 1894 state_index++;
1903 } 1895 }
1904 1896
1905 rdev->pm.num_power_states = state_index; 1897 rdev->pm.num_power_states = state_index;
1906 1898
1907 rdev->pm.current_power_state = rdev->pm.default_power_state; 1899 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1908 rdev->pm.current_clock_mode = 1900 rdev->pm.current_clock_mode_index = 0;
1909 rdev->pm.default_power_state->default_clock_mode;
1910} 1901}
1911 1902
1912void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable) 1903void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index 44198581ba9..6a9ec851126 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -2368,7 +2368,7 @@ void radeon_combios_get_power_modes(struct radeon_device *rdev)
2368 u8 rev, blocks, tmp; 2368 u8 rev, blocks, tmp;
2369 int state_index = 0; 2369 int state_index = 0;
2370 2370
2371 rdev->pm.default_power_state = NULL; 2371 rdev->pm.default_power_state_index = -1;
2372 2372
2373 if (rdev->flags & RADEON_IS_MOBILITY) { 2373 if (rdev->flags & RADEON_IS_MOBILITY) {
2374 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE); 2374 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
@@ -2441,6 +2441,7 @@ void radeon_combios_get_power_modes(struct radeon_device *rdev)
2441 if (rev > 6) 2441 if (rev > 6)
2442 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 2442 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
2443 RBIOS8(offset + 0x5 + 0x10); 2443 RBIOS8(offset + 0x5 + 0x10);
2444 rdev->pm.power_state[state_index].flags = RADEON_PM_SINGLE_DISPLAY_ONLY;
2444 state_index++; 2445 state_index++;
2445 } else { 2446 } else {
2446 /* XXX figure out some good default low power mode for mobility cards w/out power tables */ 2447 /* XXX figure out some good default low power mode for mobility cards w/out power tables */
@@ -2462,12 +2463,12 @@ default_mode:
2462 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev); 2463 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev);
2463 else 2464 else
2464 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16; 2465 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16;
2465 rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; 2466 rdev->pm.power_state[state_index].flags = 0;
2467 rdev->pm.default_power_state_index = state_index;
2466 rdev->pm.num_power_states = state_index + 1; 2468 rdev->pm.num_power_states = state_index + 1;
2467 2469
2468 rdev->pm.current_power_state = rdev->pm.default_power_state; 2470 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2469 rdev->pm.current_clock_mode = 2471 rdev->pm.current_clock_mode_index = 0;
2470 rdev->pm.default_power_state->default_clock_mode;
2471} 2472}
2472 2473
2473void radeon_external_tmds_setup(struct drm_encoder *encoder) 2474void radeon_external_tmds_setup(struct drm_encoder *encoder)
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index 60c0dcb8e11..f4f9cb297e3 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -323,6 +323,7 @@ void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
323 } 323 }
324 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); 324 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
325 radeon_crtc_load_lut(crtc); 325 radeon_crtc_load_lut(crtc);
326 radeon_crtc->enabled = true;
326 break; 327 break;
327 case DRM_MODE_DPMS_STANDBY: 328 case DRM_MODE_DPMS_STANDBY:
328 case DRM_MODE_DPMS_SUSPEND: 329 case DRM_MODE_DPMS_SUSPEND:
@@ -335,6 +336,7 @@ void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
335 RADEON_CRTC_DISP_REQ_EN_B)); 336 RADEON_CRTC_DISP_REQ_EN_B));
336 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask); 337 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
337 } 338 }
339 radeon_crtc->enabled = false;
338 break; 340 break;
339 } 341 }
340 342
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index 129956d003a..10ef8924799 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -56,7 +56,7 @@ static void radeon_print_power_mode_info(struct radeon_device *rdev)
56 56
57 DRM_INFO("%d Power State(s)\n", rdev->pm.num_power_states); 57 DRM_INFO("%d Power State(s)\n", rdev->pm.num_power_states);
58 for (i = 0; i < rdev->pm.num_power_states; i++) { 58 for (i = 0; i < rdev->pm.num_power_states; i++) {
59 if (rdev->pm.default_power_state == &rdev->pm.power_state[i]) 59 if (rdev->pm.default_power_state_index == i)
60 is_default = true; 60 is_default = true;
61 else 61 else
62 is_default = false; 62 is_default = false;
@@ -65,6 +65,8 @@ static void radeon_print_power_mode_info(struct radeon_device *rdev)
65 is_default ? "(default)" : ""); 65 is_default ? "(default)" : "");
66 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP)) 66 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
67 DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].non_clock_info.pcie_lanes); 67 DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].non_clock_info.pcie_lanes);
68 if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
69 DRM_INFO("\tSingle display only\n");
68 DRM_INFO("\t%d Clock Mode(s)\n", rdev->pm.power_state[i].num_clock_modes); 70 DRM_INFO("\t%d Clock Mode(s)\n", rdev->pm.power_state[i].num_clock_modes);
69 for (j = 0; j < rdev->pm.power_state[i].num_clock_modes; j++) { 71 for (j = 0; j < rdev->pm.power_state[i].num_clock_modes; j++) {
70 if (rdev->flags & RADEON_IS_IGP) 72 if (rdev->flags & RADEON_IS_IGP)
@@ -80,106 +82,6 @@ static void radeon_print_power_mode_info(struct radeon_device *rdev)
80 } 82 }
81} 83}
82 84
83static struct radeon_power_state * radeon_pick_power_state(struct radeon_device *rdev,
84 enum radeon_pm_state_type type)
85{
86 int i, j;
87 enum radeon_pm_state_type wanted_types[2];
88 int wanted_count;
89
90 switch (type) {
91 case POWER_STATE_TYPE_DEFAULT:
92 default:
93 return rdev->pm.default_power_state;
94 case POWER_STATE_TYPE_POWERSAVE:
95 if (rdev->flags & RADEON_IS_MOBILITY) {
96 wanted_types[0] = POWER_STATE_TYPE_POWERSAVE;
97 wanted_types[1] = POWER_STATE_TYPE_BATTERY;
98 wanted_count = 2;
99 } else {
100 wanted_types[0] = POWER_STATE_TYPE_PERFORMANCE;
101 wanted_count = 1;
102 }
103 break;
104 case POWER_STATE_TYPE_BATTERY:
105 if (rdev->flags & RADEON_IS_MOBILITY) {
106 wanted_types[0] = POWER_STATE_TYPE_BATTERY;
107 wanted_types[1] = POWER_STATE_TYPE_POWERSAVE;
108 wanted_count = 2;
109 } else {
110 wanted_types[0] = POWER_STATE_TYPE_PERFORMANCE;
111 wanted_count = 1;
112 }
113 break;
114 case POWER_STATE_TYPE_BALANCED:
115 case POWER_STATE_TYPE_PERFORMANCE:
116 wanted_types[0] = type;
117 wanted_count = 1;
118 break;
119 }
120
121 for (i = 0; i < wanted_count; i++) {
122 for (j = 0; j < rdev->pm.num_power_states; j++) {
123 if (rdev->pm.power_state[j].type == wanted_types[i])
124 return &rdev->pm.power_state[j];
125 }
126 }
127
128 return rdev->pm.default_power_state;
129}
130
131static struct radeon_pm_clock_info * radeon_pick_clock_mode(struct radeon_device *rdev,
132 struct radeon_power_state *power_state,
133 enum radeon_pm_clock_mode_type type)
134{
135 switch (type) {
136 case POWER_MODE_TYPE_DEFAULT:
137 default:
138 return power_state->default_clock_mode;
139 case POWER_MODE_TYPE_LOW:
140 return &power_state->clock_info[0];
141 case POWER_MODE_TYPE_MID:
142 if (power_state->num_clock_modes > 2)
143 return &power_state->clock_info[1];
144 else
145 return &power_state->clock_info[0];
146 break;
147 case POWER_MODE_TYPE_HIGH:
148 return &power_state->clock_info[power_state->num_clock_modes - 1];
149 }
150
151}
152
153static void radeon_get_power_state(struct radeon_device *rdev,
154 enum radeon_pm_action action)
155{
156 switch (action) {
157 case PM_ACTION_MINIMUM:
158 rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_BATTERY);
159 rdev->pm.requested_clock_mode =
160 radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_LOW);
161 break;
162 case PM_ACTION_DOWNCLOCK:
163 rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_POWERSAVE);
164 rdev->pm.requested_clock_mode =
165 radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_MID);
166 break;
167 case PM_ACTION_UPCLOCK:
168 rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_DEFAULT);
169 rdev->pm.requested_clock_mode =
170 radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_HIGH);
171 break;
172 case PM_ACTION_NONE:
173 default:
174 DRM_ERROR("Requested mode for not defined action\n");
175 return;
176 }
177 DRM_INFO("Requested: e: %d m: %d p: %d\n",
178 rdev->pm.requested_clock_mode->sclk,
179 rdev->pm.requested_clock_mode->mclk,
180 rdev->pm.requested_power_state->non_clock_info.pcie_lanes);
181}
182
183void radeon_sync_with_vblank(struct radeon_device *rdev) 85void radeon_sync_with_vblank(struct radeon_device *rdev)
184{ 86{
185 if (rdev->pm.active_crtcs) { 87 if (rdev->pm.active_crtcs) {
@@ -194,7 +96,8 @@ int radeon_pm_init(struct radeon_device *rdev)
194{ 96{
195 rdev->pm.state = PM_STATE_DISABLED; 97 rdev->pm.state = PM_STATE_DISABLED;
196 rdev->pm.planned_action = PM_ACTION_NONE; 98 rdev->pm.planned_action = PM_ACTION_NONE;
197 rdev->pm.downclocked = false; 99 rdev->pm.can_upclock = true;
100 rdev->pm.can_downclock = true;
198 101
199 if (rdev->bios) { 102 if (rdev->bios) {
200 if (rdev->is_atom_bios) 103 if (rdev->is_atom_bios)
@@ -229,9 +132,8 @@ void radeon_pm_fini(struct radeon_device *rdev)
229void radeon_pm_compute_clocks(struct radeon_device *rdev) 132void radeon_pm_compute_clocks(struct radeon_device *rdev)
230{ 133{
231 struct drm_device *ddev = rdev->ddev; 134 struct drm_device *ddev = rdev->ddev;
232 struct drm_connector *connector; 135 struct drm_crtc *crtc;
233 struct radeon_crtc *radeon_crtc; 136 struct radeon_crtc *radeon_crtc;
234 int count = 0;
235 137
236 if (rdev->pm.state == PM_STATE_DISABLED) 138 if (rdev->pm.state == PM_STATE_DISABLED)
237 return; 139 return;
@@ -239,29 +141,27 @@ void radeon_pm_compute_clocks(struct radeon_device *rdev)
239 mutex_lock(&rdev->pm.mutex); 141 mutex_lock(&rdev->pm.mutex);
240 142
241 rdev->pm.active_crtcs = 0; 143 rdev->pm.active_crtcs = 0;
242 list_for_each_entry(connector, 144 rdev->pm.active_crtc_count = 0;
243 &ddev->mode_config.connector_list, head) { 145 list_for_each_entry(crtc,
244 if (connector->encoder && 146 &ddev->mode_config.crtc_list, head) {
245 connector->encoder->crtc && 147 radeon_crtc = to_radeon_crtc(crtc);
246 connector->dpms != DRM_MODE_DPMS_OFF) { 148 if (radeon_crtc->enabled) {
247 radeon_crtc = to_radeon_crtc(connector->encoder->crtc);
248 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id); 149 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
249 ++count; 150 rdev->pm.active_crtc_count++;
250 } 151 }
251 } 152 }
252 153
253 if (count > 1) { 154 if (rdev->pm.active_crtc_count > 1) {
254 if (rdev->pm.state == PM_STATE_ACTIVE) { 155 if (rdev->pm.state == PM_STATE_ACTIVE) {
255 cancel_delayed_work(&rdev->pm.idle_work); 156 cancel_delayed_work(&rdev->pm.idle_work);
256 157
257 rdev->pm.state = PM_STATE_PAUSED; 158 rdev->pm.state = PM_STATE_PAUSED;
258 rdev->pm.planned_action = PM_ACTION_UPCLOCK; 159 rdev->pm.planned_action = PM_ACTION_UPCLOCK;
259 if (rdev->pm.downclocked) 160 radeon_pm_set_clocks(rdev);
260 radeon_pm_set_clocks(rdev);
261 161
262 DRM_DEBUG("radeon: dynamic power management deactivated\n"); 162 DRM_DEBUG("radeon: dynamic power management deactivated\n");
263 } 163 }
264 } else if (count == 1) { 164 } else if (rdev->pm.active_crtc_count == 1) {
265 /* TODO: Increase clocks if needed for current mode */ 165 /* TODO: Increase clocks if needed for current mode */
266 166
267 if (rdev->pm.state == PM_STATE_MINIMUM) { 167 if (rdev->pm.state == PM_STATE_MINIMUM) {
@@ -271,15 +171,13 @@ void radeon_pm_compute_clocks(struct radeon_device *rdev)
271 171
272 queue_delayed_work(rdev->wq, &rdev->pm.idle_work, 172 queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
273 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 173 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
274 } 174 } else if (rdev->pm.state == PM_STATE_PAUSED) {
275 else if (rdev->pm.state == PM_STATE_PAUSED) {
276 rdev->pm.state = PM_STATE_ACTIVE; 175 rdev->pm.state = PM_STATE_ACTIVE;
277 queue_delayed_work(rdev->wq, &rdev->pm.idle_work, 176 queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
278 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 177 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
279 DRM_DEBUG("radeon: dynamic power management activated\n"); 178 DRM_DEBUG("radeon: dynamic power management activated\n");
280 } 179 }
281 } 180 } else { /* count == 0 */
282 else { /* count == 0 */
283 if (rdev->pm.state != PM_STATE_MINIMUM) { 181 if (rdev->pm.state != PM_STATE_MINIMUM) {
284 cancel_delayed_work(&rdev->pm.idle_work); 182 cancel_delayed_work(&rdev->pm.idle_work);
285 183
@@ -359,19 +257,6 @@ bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
359static void radeon_pm_set_clocks_locked(struct radeon_device *rdev) 257static void radeon_pm_set_clocks_locked(struct radeon_device *rdev)
360{ 258{
361 /*radeon_fence_wait_last(rdev);*/ 259 /*radeon_fence_wait_last(rdev);*/
362 switch (rdev->pm.planned_action) {
363 case PM_ACTION_UPCLOCK:
364 rdev->pm.downclocked = false;
365 break;
366 case PM_ACTION_DOWNCLOCK:
367 rdev->pm.downclocked = true;
368 break;
369 case PM_ACTION_MINIMUM:
370 break;
371 case PM_ACTION_NONE:
372 DRM_ERROR("%s: PM_ACTION_NONE\n", __func__);
373 break;
374 }
375 260
376 radeon_set_power_state(rdev); 261 radeon_set_power_state(rdev);
377 rdev->pm.planned_action = PM_ACTION_NONE; 262 rdev->pm.planned_action = PM_ACTION_NONE;
@@ -437,7 +322,7 @@ static void radeon_pm_idle_work_handler(struct work_struct *work)
437 if (rdev->pm.planned_action == PM_ACTION_DOWNCLOCK) { 322 if (rdev->pm.planned_action == PM_ACTION_DOWNCLOCK) {
438 rdev->pm.planned_action = PM_ACTION_NONE; 323 rdev->pm.planned_action = PM_ACTION_NONE;
439 } else if (rdev->pm.planned_action == PM_ACTION_NONE && 324 } else if (rdev->pm.planned_action == PM_ACTION_NONE &&
440 rdev->pm.downclocked) { 325 rdev->pm.can_upclock) {
441 rdev->pm.planned_action = 326 rdev->pm.planned_action =
442 PM_ACTION_UPCLOCK; 327 PM_ACTION_UPCLOCK;
443 rdev->pm.action_timeout = jiffies + 328 rdev->pm.action_timeout = jiffies +
@@ -447,7 +332,7 @@ static void radeon_pm_idle_work_handler(struct work_struct *work)
447 if (rdev->pm.planned_action == PM_ACTION_UPCLOCK) { 332 if (rdev->pm.planned_action == PM_ACTION_UPCLOCK) {
448 rdev->pm.planned_action = PM_ACTION_NONE; 333 rdev->pm.planned_action = PM_ACTION_NONE;
449 } else if (rdev->pm.planned_action == PM_ACTION_NONE && 334 } else if (rdev->pm.planned_action == PM_ACTION_NONE &&
450 !rdev->pm.downclocked) { 335 rdev->pm.can_downclock) {
451 rdev->pm.planned_action = 336 rdev->pm.planned_action =
452 PM_ACTION_DOWNCLOCK; 337 PM_ACTION_DOWNCLOCK;
453 rdev->pm.action_timeout = jiffies + 338 rdev->pm.action_timeout = jiffies +
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 00:08:40 -0500