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-rw-r--r--MAINTAINERS6
-rw-r--r--arch/arm/Kconfig11
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/configs/cns3420vb_defconfig831
-rw-r--r--arch/arm/include/asm/elf.h2
-rw-r--r--arch/arm/kernel/entry-armv.S4
-rw-r--r--arch/arm/kernel/smp.c6
-rw-r--r--arch/arm/mach-cns3xxx/Kconfig12
-rw-r--r--arch/arm/mach-cns3xxx/Makefile2
-rw-r--r--arch/arm/mach-cns3xxx/Makefile.boot3
-rw-r--r--arch/arm/mach-cns3xxx/cns3420vb.c148
-rw-r--r--arch/arm/mach-cns3xxx/core.c249
-rw-r--r--arch/arm/mach-cns3xxx/core.h23
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/cns3xxx.h635
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/debug-macro.S21
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/entry-macro.S82
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/hardware.h22
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/io.h17
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/irqs.h24
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/memory.h26
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/system.h29
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/timex.h12
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/uncompress.h55
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/vmalloc.h11
-rw-r--r--arch/arm/mach-cns3xxx/pm.c86
-rw-r--r--arch/arm/mach-sa1100/Kconfig4
-rw-r--r--arch/arm/mach-sa1100/cpu-sa1110.c3
-rw-r--r--arch/arm/plat-pxa/dma.c2
-rw-r--r--arch/arm/tools/mach-types57
29 files changed, 2378 insertions, 6 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index d5b0b1b6dc5..27299d13947 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -586,6 +586,12 @@ F: drivers/mtd/nand/bcm_umi_bch.c
586F: drivers/mtd/nand/bcm_umi_hamming.c 586F: drivers/mtd/nand/bcm_umi_hamming.c
587F: drivers/mtd/nand/nand_bcm_umi.h 587F: drivers/mtd/nand/nand_bcm_umi.h
588 588
589ARM/CAVIUM NETWORKS CNS3XXX MACHINE SUPPORT
590M: Anton Vorontsov <avorontsov@mvista.com>
591S: Maintained
592F: arch/arm/mach-cns3xxx/
593T: git git://git.infradead.org/users/cbou/linux-cns3xxx.git
594
589ARM/CIRRUS LOGIC EP93XX ARM ARCHITECTURE 595ARM/CIRRUS LOGIC EP93XX ARM ARCHITECTURE
590M: Hartley Sweeten <hsweeten@visionengravers.com> 596M: Hartley Sweeten <hsweeten@visionengravers.com>
591M: Ryan Mallon <ryan@bluewatersys.com> 597M: Ryan Mallon <ryan@bluewatersys.com>
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 355bc5e6e6e..3806d636a40 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -297,6 +297,15 @@ config ARCH_CLPS711X
297 help 297 help
298 Support for Cirrus Logic 711x/721x based boards. 298 Support for Cirrus Logic 711x/721x based boards.
299 299
300config ARCH_CNS3XXX
301 bool "Cavium Networks CNS3XXX family"
302 select CPU_V6
303 select GENERIC_TIME
304 select GENERIC_CLOCKEVENTS
305 select ARM_GIC
306 help
307 Support for Cavium Networks CNS3XXX platform.
308
300config ARCH_GEMINI 309config ARCH_GEMINI
301 bool "Cortina Systems Gemini" 310 bool "Cortina Systems Gemini"
302 select CPU_FA526 311 select CPU_FA526
@@ -818,6 +827,8 @@ source "arch/arm/mach-bcmring/Kconfig"
818 827
819source "arch/arm/mach-clps711x/Kconfig" 828source "arch/arm/mach-clps711x/Kconfig"
820 829
830source "arch/arm/mach-cns3xxx/Kconfig"
831
821source "arch/arm/mach-davinci/Kconfig" 832source "arch/arm/mach-davinci/Kconfig"
822 833
823source "arch/arm/mach-dove/Kconfig" 834source "arch/arm/mach-dove/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index ed820e737a8..3e312ec8e62 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -121,6 +121,7 @@ machine-$(CONFIG_ARCH_AAEC2000) := aaec2000
121machine-$(CONFIG_ARCH_AT91) := at91 121machine-$(CONFIG_ARCH_AT91) := at91
122machine-$(CONFIG_ARCH_BCMRING) := bcmring 122machine-$(CONFIG_ARCH_BCMRING) := bcmring
123machine-$(CONFIG_ARCH_CLPS711X) := clps711x 123machine-$(CONFIG_ARCH_CLPS711X) := clps711x
124machine-$(CONFIG_ARCH_CNS3XXX) := cns3xxx
124machine-$(CONFIG_ARCH_DAVINCI) := davinci 125machine-$(CONFIG_ARCH_DAVINCI) := davinci
125machine-$(CONFIG_ARCH_DOVE) := dove 126machine-$(CONFIG_ARCH_DOVE) := dove
126machine-$(CONFIG_ARCH_EBSA110) := ebsa110 127machine-$(CONFIG_ARCH_EBSA110) := ebsa110
diff --git a/arch/arm/configs/cns3420vb_defconfig b/arch/arm/configs/cns3420vb_defconfig
new file mode 100644
index 00000000000..d5c088149e4
--- /dev/null
+++ b/arch/arm/configs/cns3420vb_defconfig
@@ -0,0 +1,831 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.34-rc6
4# Sun May 2 21:58:08 2010
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_TIME=y
9CONFIG_GENERIC_CLOCKEVENTS=y
10CONFIG_HAVE_PROC_CPU=y
11CONFIG_GENERIC_HARDIRQS=y
12CONFIG_STACKTRACE_SUPPORT=y
13CONFIG_HAVE_LATENCYTOP_SUPPORT=y
14CONFIG_LOCKDEP_SUPPORT=y
15CONFIG_TRACE_IRQFLAGS_SUPPORT=y
16CONFIG_HARDIRQS_SW_RESEND=y
17CONFIG_GENERIC_IRQ_PROBE=y
18CONFIG_RWSEM_GENERIC_SPINLOCK=y
19CONFIG_GENERIC_HWEIGHT=y
20CONFIG_GENERIC_CALIBRATE_DELAY=y
21CONFIG_NEED_DMA_MAP_STATE=y
22CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
23CONFIG_OPROFILE_ARMV6=y
24CONFIG_OPROFILE_ARM11_CORE=y
25CONFIG_VECTORS_BASE=0xffff0000
26CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
27CONFIG_CONSTRUCTORS=y
28
29#
30# General setup
31#
32CONFIG_EXPERIMENTAL=y
33CONFIG_BROKEN_ON_SMP=y
34CONFIG_INIT_ENV_ARG_LIMIT=32
35CONFIG_LOCALVERSION=""
36# CONFIG_LOCALVERSION_AUTO is not set
37CONFIG_HAVE_KERNEL_GZIP=y
38CONFIG_HAVE_KERNEL_LZO=y
39CONFIG_KERNEL_GZIP=y
40# CONFIG_KERNEL_BZIP2 is not set
41# CONFIG_KERNEL_LZMA is not set
42# CONFIG_KERNEL_LZO is not set
43# CONFIG_SWAP is not set
44CONFIG_SYSVIPC=y
45CONFIG_SYSVIPC_SYSCTL=y
46# CONFIG_BSD_PROCESS_ACCT is not set
47
48#
49# RCU Subsystem
50#
51CONFIG_TREE_RCU=y
52# CONFIG_TREE_PREEMPT_RCU is not set
53# CONFIG_TINY_RCU is not set
54# CONFIG_RCU_TRACE is not set
55CONFIG_RCU_FANOUT=32
56# CONFIG_RCU_FANOUT_EXACT is not set
57# CONFIG_TREE_RCU_TRACE is not set
58CONFIG_IKCONFIG=y
59CONFIG_IKCONFIG_PROC=y
60CONFIG_LOG_BUF_SHIFT=14
61CONFIG_CGROUPS=y
62# CONFIG_CGROUP_DEBUG is not set
63# CONFIG_CGROUP_NS is not set
64# CONFIG_CGROUP_FREEZER is not set
65# CONFIG_CGROUP_DEVICE is not set
66# CONFIG_CPUSETS is not set
67# CONFIG_CGROUP_CPUACCT is not set
68# CONFIG_RESOURCE_COUNTERS is not set
69# CONFIG_CGROUP_SCHED is not set
70CONFIG_SYSFS_DEPRECATED=y
71CONFIG_SYSFS_DEPRECATED_V2=y
72CONFIG_RELAY=y
73CONFIG_NAMESPACES=y
74# CONFIG_UTS_NS is not set
75# CONFIG_IPC_NS is not set
76# CONFIG_USER_NS is not set
77# CONFIG_PID_NS is not set
78CONFIG_BLK_DEV_INITRD=y
79CONFIG_INITRAMFS_SOURCE=""
80CONFIG_RD_GZIP=y
81CONFIG_RD_BZIP2=y
82CONFIG_RD_LZMA=y
83CONFIG_RD_LZO=y
84CONFIG_CC_OPTIMIZE_FOR_SIZE=y
85CONFIG_SYSCTL=y
86CONFIG_ANON_INODES=y
87# CONFIG_EMBEDDED is not set
88CONFIG_UID16=y
89CONFIG_SYSCTL_SYSCALL=y
90CONFIG_KALLSYMS=y
91# CONFIG_KALLSYMS_EXTRA_PASS is not set
92CONFIG_HOTPLUG=y
93CONFIG_PRINTK=y
94CONFIG_BUG=y
95CONFIG_ELF_CORE=y
96CONFIG_BASE_FULL=y
97CONFIG_FUTEX=y
98CONFIG_EPOLL=y
99CONFIG_SIGNALFD=y
100CONFIG_TIMERFD=y
101CONFIG_EVENTFD=y
102CONFIG_SHMEM=y
103CONFIG_AIO=y
104CONFIG_HAVE_PERF_EVENTS=y
105CONFIG_PERF_USE_VMALLOC=y
106
107#
108# Kernel Performance Events And Counters
109#
110# CONFIG_PERF_EVENTS is not set
111# CONFIG_PERF_COUNTERS is not set
112CONFIG_VM_EVENT_COUNTERS=y
113CONFIG_COMPAT_BRK=y
114CONFIG_SLAB=y
115# CONFIG_SLUB is not set
116# CONFIG_SLOB is not set
117CONFIG_PROFILING=y
118CONFIG_OPROFILE=m
119CONFIG_HAVE_OPROFILE=y
120# CONFIG_KPROBES is not set
121CONFIG_HAVE_KPROBES=y
122CONFIG_HAVE_KRETPROBES=y
123
124#
125# GCOV-based kernel profiling
126#
127# CONFIG_GCOV_KERNEL is not set
128CONFIG_SLOW_WORK=y
129# CONFIG_SLOW_WORK_DEBUG is not set
130CONFIG_HAVE_GENERIC_DMA_COHERENT=y
131CONFIG_SLABINFO=y
132CONFIG_RT_MUTEXES=y
133CONFIG_BASE_SMALL=0
134CONFIG_MODULES=y
135# CONFIG_MODULE_FORCE_LOAD is not set
136CONFIG_MODULE_UNLOAD=y
137CONFIG_MODULE_FORCE_UNLOAD=y
138CONFIG_MODVERSIONS=y
139# CONFIG_MODULE_SRCVERSION_ALL is not set
140CONFIG_BLOCK=y
141CONFIG_LBDAF=y
142# CONFIG_BLK_DEV_BSG is not set
143# CONFIG_BLK_DEV_INTEGRITY is not set
144
145#
146# IO Schedulers
147#
148CONFIG_IOSCHED_NOOP=y
149CONFIG_IOSCHED_DEADLINE=y
150CONFIG_IOSCHED_CFQ=m
151# CONFIG_CFQ_GROUP_IOSCHED is not set
152CONFIG_DEFAULT_DEADLINE=y
153# CONFIG_DEFAULT_CFQ is not set
154# CONFIG_DEFAULT_NOOP is not set
155CONFIG_DEFAULT_IOSCHED="deadline"
156# CONFIG_INLINE_SPIN_TRYLOCK is not set
157# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
158# CONFIG_INLINE_SPIN_LOCK is not set
159# CONFIG_INLINE_SPIN_LOCK_BH is not set
160# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
161# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
162CONFIG_INLINE_SPIN_UNLOCK=y
163# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
164CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
165# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
166# CONFIG_INLINE_READ_TRYLOCK is not set
167# CONFIG_INLINE_READ_LOCK is not set
168# CONFIG_INLINE_READ_LOCK_BH is not set
169# CONFIG_INLINE_READ_LOCK_IRQ is not set
170# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
171CONFIG_INLINE_READ_UNLOCK=y
172# CONFIG_INLINE_READ_UNLOCK_BH is not set
173CONFIG_INLINE_READ_UNLOCK_IRQ=y
174# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
175# CONFIG_INLINE_WRITE_TRYLOCK is not set
176# CONFIG_INLINE_WRITE_LOCK is not set
177# CONFIG_INLINE_WRITE_LOCK_BH is not set
178# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
179# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
180CONFIG_INLINE_WRITE_UNLOCK=y
181# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
182CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
183# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
184# CONFIG_MUTEX_SPIN_ON_OWNER is not set
185# CONFIG_FREEZER is not set
186
187#
188# System Type
189#
190CONFIG_MMU=y
191# CONFIG_ARCH_AAEC2000 is not set
192# CONFIG_ARCH_INTEGRATOR is not set
193# CONFIG_ARCH_REALVIEW is not set
194# CONFIG_ARCH_VERSATILE is not set
195# CONFIG_ARCH_AT91 is not set
196# CONFIG_ARCH_BCMRING is not set
197# CONFIG_ARCH_CLPS711X is not set
198CONFIG_ARCH_CNS3XXX=y
199# CONFIG_ARCH_GEMINI is not set
200# CONFIG_ARCH_EBSA110 is not set
201# CONFIG_ARCH_EP93XX is not set
202# CONFIG_ARCH_FOOTBRIDGE is not set
203# CONFIG_ARCH_MXC is not set
204# CONFIG_ARCH_STMP3XXX is not set
205# CONFIG_ARCH_NETX is not set
206# CONFIG_ARCH_H720X is not set
207# CONFIG_ARCH_IOP13XX is not set
208# CONFIG_ARCH_IOP32X is not set
209# CONFIG_ARCH_IOP33X is not set
210# CONFIG_ARCH_IXP23XX is not set
211# CONFIG_ARCH_IXP2000 is not set
212# CONFIG_ARCH_IXP4XX is not set
213# CONFIG_ARCH_L7200 is not set
214# CONFIG_ARCH_DOVE is not set
215# CONFIG_ARCH_KIRKWOOD is not set
216# CONFIG_ARCH_LOKI is not set
217# CONFIG_ARCH_MV78XX0 is not set
218# CONFIG_ARCH_ORION5X is not set
219# CONFIG_ARCH_MMP is not set
220# CONFIG_ARCH_KS8695 is not set
221# CONFIG_ARCH_NS9XXX is not set
222# CONFIG_ARCH_W90X900 is not set
223# CONFIG_ARCH_NUC93X is not set
224# CONFIG_ARCH_PNX4008 is not set
225# CONFIG_ARCH_PXA is not set
226# CONFIG_ARCH_MSM is not set
227# CONFIG_ARCH_SHMOBILE is not set
228# CONFIG_ARCH_RPC is not set
229# CONFIG_ARCH_SA1100 is not set
230# CONFIG_ARCH_S3C2410 is not set
231# CONFIG_ARCH_S3C64XX is not set
232# CONFIG_ARCH_S5P6440 is not set
233# CONFIG_ARCH_S5P6442 is not set
234# CONFIG_ARCH_S5PC1XX is not set
235# CONFIG_ARCH_S5PV210 is not set
236# CONFIG_ARCH_SHARK is not set
237# CONFIG_ARCH_LH7A40X is not set
238# CONFIG_ARCH_U300 is not set
239# CONFIG_ARCH_U8500 is not set
240# CONFIG_ARCH_NOMADIK is not set
241# CONFIG_ARCH_DAVINCI is not set
242# CONFIG_ARCH_OMAP is not set
243
244#
245# CNS3XXX platform type
246#
247CONFIG_MACH_CNS3420VB=y
248
249#
250# Processor Type
251#
252CONFIG_CPU_V6=y
253# CONFIG_CPU_32v6K is not set
254CONFIG_CPU_32v6=y
255CONFIG_CPU_ABRT_EV6=y
256CONFIG_CPU_PABRT_V6=y
257CONFIG_CPU_CACHE_V6=y
258CONFIG_CPU_CACHE_VIPT=y
259CONFIG_CPU_COPY_V6=y
260CONFIG_CPU_TLB_V6=y
261CONFIG_CPU_HAS_ASID=y
262CONFIG_CPU_CP15=y
263CONFIG_CPU_CP15_MMU=y
264
265#
266# Processor Features
267#
268CONFIG_ARM_THUMB=y
269# CONFIG_CPU_ICACHE_DISABLE is not set
270# CONFIG_CPU_DCACHE_DISABLE is not set
271# CONFIG_CPU_BPREDICT_DISABLE is not set
272CONFIG_ARM_L1_CACHE_SHIFT=5
273CONFIG_CPU_HAS_PMU=y
274# CONFIG_ARM_ERRATA_411920 is not set
275CONFIG_ARM_GIC=y
276
277#
278# Bus support
279#
280# CONFIG_PCI_SYSCALL is not set
281# CONFIG_ARCH_SUPPORTS_MSI is not set
282# CONFIG_PCCARD is not set
283
284#
285# Kernel Features
286#
287# CONFIG_NO_HZ is not set
288# CONFIG_HIGH_RES_TIMERS is not set
289CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
290CONFIG_VMSPLIT_3G=y
291# CONFIG_VMSPLIT_2G is not set
292# CONFIG_VMSPLIT_1G is not set
293CONFIG_PAGE_OFFSET=0xC0000000
294CONFIG_PREEMPT_NONE=y
295# CONFIG_PREEMPT_VOLUNTARY is not set
296# CONFIG_PREEMPT is not set
297CONFIG_HZ=100
298CONFIG_AEABI=y
299CONFIG_OABI_COMPAT=y
300# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
301# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
302# CONFIG_HIGHMEM is not set
303CONFIG_SELECT_MEMORY_MODEL=y
304CONFIG_FLATMEM_MANUAL=y
305# CONFIG_DISCONTIGMEM_MANUAL is not set
306# CONFIG_SPARSEMEM_MANUAL is not set
307CONFIG_FLATMEM=y
308CONFIG_FLAT_NODE_MEM_MAP=y
309CONFIG_PAGEFLAGS_EXTENDED=y
310CONFIG_SPLIT_PTLOCK_CPUS=4
311# CONFIG_PHYS_ADDR_T_64BIT is not set
312CONFIG_ZONE_DMA_FLAG=0
313CONFIG_VIRT_TO_BUS=y
314# CONFIG_KSM is not set
315CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
316CONFIG_ALIGNMENT_TRAP=y
317# CONFIG_UACCESS_WITH_MEMCPY is not set
318
319#
320# Boot options
321#
322CONFIG_ZBOOT_ROM_TEXT=0x0
323CONFIG_ZBOOT_ROM_BSS=0x0
324CONFIG_CMDLINE="console=ttyS0,38400 mem=128M root=/dev/mmcblk0p1 ro rootwait"
325# CONFIG_XIP_KERNEL is not set
326# CONFIG_KEXEC is not set
327
328#
329# CPU Power Management
330#
331# CONFIG_CPU_IDLE is not set
332
333#
334# Floating point emulation
335#
336
337#
338# At least one emulation must be selected
339#
340# CONFIG_FPE_NWFPE is not set
341# CONFIG_FPE_FASTFPE is not set
342# CONFIG_VFP is not set
343
344#
345# Userspace binary formats
346#
347CONFIG_BINFMT_ELF=y
348# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
349CONFIG_HAVE_AOUT=y
350# CONFIG_BINFMT_AOUT is not set
351# CONFIG_BINFMT_MISC is not set
352
353#
354# Power management options
355#
356# CONFIG_PM is not set
357CONFIG_ARCH_SUSPEND_POSSIBLE=y
358# CONFIG_NET is not set
359
360#
361# Device Drivers
362#
363
364#
365# Generic Driver Options
366#
367CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
368# CONFIG_DEVTMPFS is not set
369CONFIG_STANDALONE=y
370CONFIG_PREVENT_FIRMWARE_BUILD=y
371CONFIG_FW_LOADER=y
372# CONFIG_FIRMWARE_IN_KERNEL is not set
373CONFIG_EXTRA_FIRMWARE=""
374# CONFIG_SYS_HYPERVISOR is not set
375CONFIG_MTD=y
376# CONFIG_MTD_DEBUG is not set
377# CONFIG_MTD_TESTS is not set
378# CONFIG_MTD_CONCAT is not set
379CONFIG_MTD_PARTITIONS=y
380# CONFIG_MTD_REDBOOT_PARTS is not set
381CONFIG_MTD_CMDLINE_PARTS=y
382# CONFIG_MTD_AFS_PARTS is not set
383# CONFIG_MTD_AR7_PARTS is not set
384
385#
386# User Modules And Translation Layers
387#
388CONFIG_MTD_CHAR=y
389CONFIG_MTD_BLKDEVS=y
390CONFIG_MTD_BLOCK=y
391# CONFIG_FTL is not set
392# CONFIG_NFTL is not set
393# CONFIG_INFTL is not set
394# CONFIG_RFD_FTL is not set
395# CONFIG_SSFDC is not set
396# CONFIG_MTD_OOPS is not set
397
398#
399# RAM/ROM/Flash chip drivers
400#
401CONFIG_MTD_CFI=y
402# CONFIG_MTD_JEDECPROBE is not set
403CONFIG_MTD_GEN_PROBE=y
404# CONFIG_MTD_CFI_ADV_OPTIONS is not set
405CONFIG_MTD_MAP_BANK_WIDTH_1=y
406CONFIG_MTD_MAP_BANK_WIDTH_2=y
407CONFIG_MTD_MAP_BANK_WIDTH_4=y
408# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
409# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
410# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
411CONFIG_MTD_CFI_I1=y
412CONFIG_MTD_CFI_I2=y
413# CONFIG_MTD_CFI_I4 is not set
414# CONFIG_MTD_CFI_I8 is not set
415# CONFIG_MTD_CFI_INTELEXT is not set
416CONFIG_MTD_CFI_AMDSTD=y
417# CONFIG_MTD_CFI_STAA is not set
418CONFIG_MTD_CFI_UTIL=y
419# CONFIG_MTD_RAM is not set
420# CONFIG_MTD_ROM is not set
421# CONFIG_MTD_ABSENT is not set
422
423#
424# Mapping drivers for chip access
425#
426# CONFIG_MTD_COMPLEX_MAPPINGS is not set
427CONFIG_MTD_PHYSMAP=y
428# CONFIG_MTD_PHYSMAP_COMPAT is not set
429# CONFIG_MTD_ARM_INTEGRATOR is not set
430# CONFIG_MTD_PLATRAM is not set
431
432#
433# Self-contained MTD device drivers
434#
435# CONFIG_MTD_SLRAM is not set
436# CONFIG_MTD_PHRAM is not set
437# CONFIG_MTD_MTDRAM is not set
438# CONFIG_MTD_BLOCK2MTD is not set
439
440#
441# Disk-On-Chip Device Drivers
442#
443# CONFIG_MTD_DOC2000 is not set
444# CONFIG_MTD_DOC2001 is not set
445# CONFIG_MTD_DOC2001PLUS is not set
446# CONFIG_MTD_NAND is not set
447# CONFIG_MTD_ONENAND is not set
448
449#
450# LPDDR flash memory drivers
451#
452# CONFIG_MTD_LPDDR is not set
453
454#
455# UBI - Unsorted block images
456#
457# CONFIG_MTD_UBI is not set
458# CONFIG_PARPORT is not set
459CONFIG_BLK_DEV=y
460# CONFIG_BLK_DEV_COW_COMMON is not set
461CONFIG_BLK_DEV_LOOP=y
462# CONFIG_BLK_DEV_CRYPTOLOOP is not set
463
464#
465# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
466#
467CONFIG_BLK_DEV_RAM=y
468CONFIG_BLK_DEV_RAM_COUNT=16
469CONFIG_BLK_DEV_RAM_SIZE=20000
470# CONFIG_BLK_DEV_XIP is not set
471# CONFIG_CDROM_PKTCDVD is not set
472# CONFIG_MISC_DEVICES is not set
473CONFIG_HAVE_IDE=y
474# CONFIG_IDE is not set
475
476#
477# SCSI device support
478#
479CONFIG_SCSI_MOD=y
480# CONFIG_RAID_ATTRS is not set
481CONFIG_SCSI=y
482CONFIG_SCSI_DMA=y
483# CONFIG_SCSI_TGT is not set
484# CONFIG_SCSI_NETLINK is not set
485CONFIG_SCSI_PROC_FS=y
486
487#
488# SCSI support type (disk, tape, CD-ROM)
489#
490CONFIG_BLK_DEV_SD=y
491# CONFIG_CHR_DEV_ST is not set
492# CONFIG_CHR_DEV_OSST is not set
493# CONFIG_BLK_DEV_SR is not set
494# CONFIG_CHR_DEV_SG is not set
495# CONFIG_CHR_DEV_SCH is not set
496# CONFIG_SCSI_MULTI_LUN is not set
497# CONFIG_SCSI_CONSTANTS is not set
498# CONFIG_SCSI_LOGGING is not set
499# CONFIG_SCSI_SCAN_ASYNC is not set
500CONFIG_SCSI_WAIT_SCAN=m
501
502#
503# SCSI Transports
504#
505# CONFIG_SCSI_SPI_ATTRS is not set
506# CONFIG_SCSI_FC_ATTRS is not set
507# CONFIG_SCSI_SAS_LIBSAS is not set
508# CONFIG_SCSI_SRP_ATTRS is not set
509CONFIG_SCSI_LOWLEVEL=y
510# CONFIG_LIBFC is not set
511# CONFIG_LIBFCOE is not set
512# CONFIG_SCSI_DEBUG is not set
513# CONFIG_SCSI_DH is not set
514# CONFIG_SCSI_OSD_INITIATOR is not set
515CONFIG_ATA=y
516# CONFIG_ATA_NONSTANDARD is not set
517CONFIG_ATA_VERBOSE_ERROR=y
518# CONFIG_SATA_PMP is not set
519# CONFIG_ATA_SFF is not set
520# CONFIG_MD is not set
521# CONFIG_PHONE is not set
522
523#
524# Input device support
525#
526CONFIG_INPUT=y
527# CONFIG_INPUT_FF_MEMLESS is not set
528# CONFIG_INPUT_POLLDEV is not set
529# CONFIG_INPUT_SPARSEKMAP is not set
530
531#
532# Userland interfaces
533#
534CONFIG_INPUT_MOUSEDEV=y
535# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
536CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
537CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
538# CONFIG_INPUT_JOYDEV is not set
539# CONFIG_INPUT_EVDEV is not set
540# CONFIG_INPUT_EVBUG is not set
541
542#
543# Input Device Drivers
544#
545# CONFIG_INPUT_KEYBOARD is not set
546# CONFIG_INPUT_MOUSE is not set
547# CONFIG_INPUT_JOYSTICK is not set
548# CONFIG_INPUT_TABLET is not set
549# CONFIG_INPUT_TOUCHSCREEN is not set
550# CONFIG_INPUT_MISC is not set
551
552#
553# Hardware I/O ports
554#
555# CONFIG_SERIO is not set
556# CONFIG_GAMEPORT is not set
557
558#
559# Character devices
560#
561CONFIG_VT=y
562CONFIG_CONSOLE_TRANSLATIONS=y
563CONFIG_VT_CONSOLE=y
564CONFIG_HW_CONSOLE=y
565# CONFIG_VT_HW_CONSOLE_BINDING is not set
566CONFIG_DEVKMEM=y
567# CONFIG_SERIAL_NONSTANDARD is not set
568
569#
570# Serial drivers
571#
572CONFIG_SERIAL_8250=y
573CONFIG_SERIAL_8250_CONSOLE=y
574CONFIG_SERIAL_8250_NR_UARTS=4
575CONFIG_SERIAL_8250_RUNTIME_UARTS=4
576# CONFIG_SERIAL_8250_EXTENDED is not set
577
578#
579# Non-8250 serial port support
580#
581CONFIG_SERIAL_CORE=y
582CONFIG_SERIAL_CORE_CONSOLE=y
583# CONFIG_SERIAL_TIMBERDALE is not set
584CONFIG_UNIX98_PTYS=y
585# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
586CONFIG_LEGACY_PTYS=y
587CONFIG_LEGACY_PTY_COUNT=16
588# CONFIG_IPMI_HANDLER is not set
589# CONFIG_HW_RANDOM is not set
590# CONFIG_R3964 is not set
591# CONFIG_RAW_DRIVER is not set
592# CONFIG_TCG_TPM is not set
593# CONFIG_I2C is not set
594# CONFIG_SPI is not set
595
596#
597# PPS support
598#
599# CONFIG_PPS is not set
600# CONFIG_W1 is not set
601# CONFIG_POWER_SUPPLY is not set
602# CONFIG_HWMON is not set
603# CONFIG_THERMAL is not set
604# CONFIG_WATCHDOG is not set
605CONFIG_SSB_POSSIBLE=y
606
607#
608# Sonics Silicon Backplane
609#
610# CONFIG_SSB is not set
611
612#
613# Multifunction device drivers
614#
615# CONFIG_MFD_CORE is not set
616# CONFIG_MFD_SM501 is not set
617# CONFIG_HTC_PASIC3 is not set
618# CONFIG_MFD_TMIO is not set
619# CONFIG_REGULATOR is not set
620# CONFIG_MEDIA_SUPPORT is not set
621
622#
623# Graphics support
624#
625# CONFIG_VGASTATE is not set
626# CONFIG_VIDEO_OUTPUT_CONTROL is not set
627# CONFIG_FB is not set
628# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
629
630#
631# Display device support
632#
633# CONFIG_DISPLAY_SUPPORT is not set
634
635#
636# Console display driver support
637#
638# CONFIG_VGA_CONSOLE is not set
639CONFIG_DUMMY_CONSOLE=y
640# CONFIG_SOUND is not set
641# CONFIG_HID_SUPPORT is not set
642# CONFIG_USB_SUPPORT is not set
643CONFIG_MMC=y
644# CONFIG_MMC_DEBUG is not set
645# CONFIG_MMC_UNSAFE_RESUME is not set
646
647#
648# MMC/SD/SDIO Card Drivers
649#
650CONFIG_MMC_BLOCK=y
651CONFIG_MMC_BLOCK_BOUNCE=y
652# CONFIG_SDIO_UART is not set
653# CONFIG_MMC_TEST is not set
654
655#
656# MMC/SD/SDIO Host Controller Drivers
657#
658CONFIG_MMC_SDHCI=y
659CONFIG_MMC_SDHCI_PLTFM=y
660# CONFIG_MEMSTICK is not set
661# CONFIG_NEW_LEDS is not set
662# CONFIG_ACCESSIBILITY is not set
663CONFIG_RTC_LIB=y
664# CONFIG_RTC_CLASS is not set
665# CONFIG_DMADEVICES is not set
666# CONFIG_AUXDISPLAY is not set
667# CONFIG_UIO is not set
668
669#
670# TI VLYNQ
671#
672# CONFIG_STAGING is not set
673
674#
675# File systems
676#
677CONFIG_EXT2_FS=y
678CONFIG_EXT2_FS_XATTR=y
679# CONFIG_EXT2_FS_POSIX_ACL is not set
680# CONFIG_EXT2_FS_SECURITY is not set
681# CONFIG_EXT2_FS_XIP is not set
682# CONFIG_EXT3_FS is not set
683# CONFIG_EXT4_FS is not set
684CONFIG_FS_MBCACHE=y
685# CONFIG_REISERFS_FS is not set
686# CONFIG_JFS_FS is not set
687# CONFIG_FS_POSIX_ACL is not set
688# CONFIG_XFS_FS is not set
689# CONFIG_GFS2_FS is not set
690# CONFIG_BTRFS_FS is not set
691# CONFIG_NILFS2_FS is not set
692CONFIG_FILE_LOCKING=y
693CONFIG_FSNOTIFY=y
694CONFIG_DNOTIFY=y
695CONFIG_INOTIFY=y
696CONFIG_INOTIFY_USER=y
697# CONFIG_QUOTA is not set
698# CONFIG_AUTOFS_FS is not set
699CONFIG_AUTOFS4_FS=y
700# CONFIG_FUSE_FS is not set
701
702#
703# Caches
704#
705CONFIG_FSCACHE=y
706# CONFIG_FSCACHE_STATS is not set
707# CONFIG_FSCACHE_HISTOGRAM is not set
708# CONFIG_FSCACHE_DEBUG is not set
709# CONFIG_FSCACHE_OBJECT_LIST is not set
710# CONFIG_CACHEFILES is not set
711
712#
713# CD-ROM/DVD Filesystems
714#
715# CONFIG_ISO9660_FS is not set
716# CONFIG_UDF_FS is not set
717
718#
719# DOS/FAT/NT Filesystems
720#
721# CONFIG_MSDOS_FS is not set
722# CONFIG_VFAT_FS is not set
723# CONFIG_NTFS_FS is not set
724
725#
726# Pseudo filesystems
727#
728CONFIG_PROC_FS=y
729CONFIG_PROC_SYSCTL=y
730CONFIG_PROC_PAGE_MONITOR=y
731CONFIG_SYSFS=y
732CONFIG_TMPFS=y
733# CONFIG_TMPFS_POSIX_ACL is not set
734# CONFIG_HUGETLB_PAGE is not set
735# CONFIG_CONFIGFS_FS is not set
736CONFIG_MISC_FILESYSTEMS=y
737# CONFIG_ADFS_FS is not set
738# CONFIG_AFFS_FS is not set
739# CONFIG_HFS_FS is not set
740# CONFIG_HFSPLUS_FS is not set
741# CONFIG_BEFS_FS is not set
742# CONFIG_BFS_FS is not set
743# CONFIG_EFS_FS is not set
744# CONFIG_JFFS2_FS is not set
745# CONFIG_LOGFS is not set
746# CONFIG_CRAMFS is not set
747# CONFIG_SQUASHFS is not set
748# CONFIG_VXFS_FS is not set
749# CONFIG_MINIX_FS is not set
750# CONFIG_OMFS_FS is not set
751# CONFIG_HPFS_FS is not set
752# CONFIG_QNX4FS_FS is not set
753# CONFIG_ROMFS_FS is not set
754# CONFIG_SYSV_FS is not set
755# CONFIG_UFS_FS is not set
756
757#
758# Partition Types
759#
760# CONFIG_PARTITION_ADVANCED is not set
761CONFIG_MSDOS_PARTITION=y
762# CONFIG_NLS is not set
763
764#
765# Kernel hacking
766#
767# CONFIG_PRINTK_TIME is not set
768# CONFIG_ENABLE_WARN_DEPRECATED is not set
769# CONFIG_ENABLE_MUST_CHECK is not set
770CONFIG_FRAME_WARN=1024
771# CONFIG_MAGIC_SYSRQ is not set
772# CONFIG_STRIP_ASM_SYMS is not set
773# CONFIG_UNUSED_SYMBOLS is not set
774CONFIG_DEBUG_FS=y
775# CONFIG_HEADERS_CHECK is not set
776# CONFIG_DEBUG_KERNEL is not set
777CONFIG_DEBUG_BUGVERBOSE=y
778CONFIG_DEBUG_MEMORY_INIT=y
779CONFIG_FRAME_POINTER=y
780# CONFIG_RCU_CPU_STALL_DETECTOR is not set
781# CONFIG_LKDTM is not set
782# CONFIG_LATENCYTOP is not set
783# CONFIG_SYSCTL_SYSCALL_CHECK is not set
784CONFIG_HAVE_FUNCTION_TRACER=y
785CONFIG_RING_BUFFER=y
786CONFIG_RING_BUFFER_ALLOW_SWAP=y
787CONFIG_TRACING_SUPPORT=y
788# CONFIG_FTRACE is not set
789# CONFIG_DYNAMIC_DEBUG is not set
790# CONFIG_SAMPLES is not set
791CONFIG_HAVE_ARCH_KGDB=y
792# CONFIG_ARM_UNWIND is not set
793# CONFIG_DEBUG_USER is not set
794# CONFIG_OC_ETM is not set
795
796#
797# Security options
798#
799# CONFIG_KEYS is not set
800# CONFIG_SECURITY is not set
801# CONFIG_SECURITYFS is not set
802# CONFIG_DEFAULT_SECURITY_SELINUX is not set
803# CONFIG_DEFAULT_SECURITY_SMACK is not set
804# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
805CONFIG_DEFAULT_SECURITY_DAC=y
806CONFIG_DEFAULT_SECURITY=""
807# CONFIG_CRYPTO is not set
808# CONFIG_BINARY_PRINTF is not set
809
810#
811# Library routines
812#
813CONFIG_BITREVERSE=y
814CONFIG_GENERIC_FIND_LAST_BIT=y
815CONFIG_CRC_CCITT=y
816# CONFIG_CRC16 is not set
817# CONFIG_CRC_T10DIF is not set
818# CONFIG_CRC_ITU_T is not set
819CONFIG_CRC32=y
820# CONFIG_CRC7 is not set
821# CONFIG_LIBCRC32C is not set
822CONFIG_ZLIB_INFLATE=y
823CONFIG_LZO_DECOMPRESS=y
824CONFIG_DECOMPRESS_GZIP=y
825CONFIG_DECOMPRESS_BZIP2=y
826CONFIG_DECOMPRESS_LZMA=y
827CONFIG_DECOMPRESS_LZO=y
828CONFIG_HAS_IOMEM=y
829CONFIG_HAS_IOPORT=y
830CONFIG_HAS_DMA=y
831CONFIG_GENERIC_ATOMIC64=y
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index bff056489cc..51662feb9f1 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -9,6 +9,8 @@
9#include <asm/ptrace.h> 9#include <asm/ptrace.h>
10#include <asm/user.h> 10#include <asm/user.h>
11 11
12struct task_struct;
13
12typedef unsigned long elf_greg_t; 14typedef unsigned long elf_greg_t;
13typedef unsigned long elf_freg_t[3]; 15typedef unsigned long elf_freg_t[3];
14 16
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index e6a0fb0f392..7ee48e7f8f3 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -676,10 +676,10 @@ do_fpe:
676 * lr = unrecognised FP instruction return address 676 * lr = unrecognised FP instruction return address
677 */ 677 */
678 678
679 .data 679 .pushsection .data
680ENTRY(fp_enter) 680ENTRY(fp_enter)
681 .word no_fp 681 .word no_fp
682 .text 682 .popsection
683 683
684ENTRY(no_fp) 684ENTRY(no_fp)
685 mov pc, lr 685 mov pc, lr
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 577543f3857..a01194e583f 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -86,6 +86,12 @@ int __cpuinit __cpu_up(unsigned int cpu)
86 return PTR_ERR(idle); 86 return PTR_ERR(idle);
87 } 87 }
88 ci->idle = idle; 88 ci->idle = idle;
89 } else {
90 /*
91 * Since this idle thread is being re-used, call
92 * init_idle() to reinitialize the thread structure.
93 */
94 init_idle(idle, cpu);
89 } 95 }
90 96
91 /* 97 /*
diff --git a/arch/arm/mach-cns3xxx/Kconfig b/arch/arm/mach-cns3xxx/Kconfig
new file mode 100644
index 00000000000..9ebfcc46feb
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/Kconfig
@@ -0,0 +1,12 @@
1menu "CNS3XXX platform type"
2 depends on ARCH_CNS3XXX
3
4config MACH_CNS3420VB
5 bool "Support for CNS3420 Validation Board"
6 help
7 Include support for the Cavium Networks CNS3420 MPCore Platform
8 Baseboard.
9 This is a platform with an on-board ARM11 MPCore and has support
10 for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, etc.
11
12endmenu
diff --git a/arch/arm/mach-cns3xxx/Makefile b/arch/arm/mach-cns3xxx/Makefile
new file mode 100644
index 00000000000..427507a2d69
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/Makefile
@@ -0,0 +1,2 @@
1obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o
2obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
diff --git a/arch/arm/mach-cns3xxx/Makefile.boot b/arch/arm/mach-cns3xxx/Makefile.boot
new file mode 100644
index 00000000000..77701286522
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/Makefile.boot
@@ -0,0 +1,3 @@
1 zreladdr-y := 0x00008000
2params_phys-y := 0x00000100
3initrd_phys-y := 0x00C00000
diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c
new file mode 100644
index 00000000000..2e30c828874
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
@@ -0,0 +1,148 @@
1/*
2 * Cavium Networks CNS3420 Validation Board
3 *
4 * Copyright 2000 Deep Blue Solutions Ltd
5 * Copyright 2008 ARM Limited
6 * Copyright 2008 Cavium Networks
7 * Scott Shu
8 * Copyright 2010 MontaVista Software, LLC.
9 * Anton Vorontsov <avorontsov@mvista.com>
10 *
11 * This file is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License, Version 2, as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/compiler.h>
19#include <linux/io.h>
20#include <linux/serial_core.h>
21#include <linux/serial_8250.h>
22#include <linux/platform_device.h>
23#include <linux/mtd/mtd.h>
24#include <linux/mtd/physmap.h>
25#include <linux/mtd/partitions.h>
26#include <asm/setup.h>
27#include <asm/mach-types.h>
28#include <asm/mach/arch.h>
29#include <asm/mach/map.h>
30#include <asm/mach/time.h>
31#include <mach/hardware.h>
32#include <mach/cns3xxx.h>
33#include <mach/irqs.h>
34#include "core.h"
35
36/*
37 * NOR Flash
38 */
39static struct mtd_partition cns3420_nor_partitions[] = {
40 {
41 .name = "uboot",
42 .size = 0x00040000,
43 .offset = 0,
44 .mask_flags = MTD_WRITEABLE,
45 }, {
46 .name = "kernel",
47 .size = 0x004C0000,
48 .offset = MTDPART_OFS_APPEND,
49 }, {
50 .name = "filesystem",
51 .size = 0x7000000,
52 .offset = MTDPART_OFS_APPEND,
53 }, {
54 .name = "filesystem2",
55 .size = 0x0AE0000,
56 .offset = MTDPART_OFS_APPEND,
57 }, {
58 .name = "ubootenv",
59 .size = MTDPART_SIZ_FULL,
60 .offset = MTDPART_OFS_APPEND,
61 },
62};
63
64static struct physmap_flash_data cns3420_nor_pdata = {
65 .width = 2,
66 .parts = cns3420_nor_partitions,
67 .nr_parts = ARRAY_SIZE(cns3420_nor_partitions),
68};
69
70static struct resource cns3420_nor_res = {
71 .start = CNS3XXX_FLASH_BASE,
72 .end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
73 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
74};
75
76static struct platform_device cns3420_nor_pdev = {
77 .name = "physmap-flash",
78 .id = 0,
79 .resource = &cns3420_nor_res,
80 .num_resources = 1,
81 .dev = {
82 .platform_data = &cns3420_nor_pdata,
83 },
84};
85
86/*
87 * UART
88 */
89static void __init cns3420_early_serial_setup(void)
90{
91#ifdef CONFIG_SERIAL_8250_CONSOLE
92 static struct uart_port cns3420_serial_port = {
93 .membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
94 .mapbase = CNS3XXX_UART0_BASE,
95 .irq = IRQ_CNS3XXX_UART0,
96 .iotype = UPIO_MEM,
97 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
98 .regshift = 2,
99 .uartclk = 24000000,
100 .line = 0,
101 .type = PORT_16550A,
102 .fifosize = 16,
103 };
104
105 early_serial_setup(&cns3420_serial_port);
106#endif
107}
108
109/*
110 * Initialization
111 */
112static struct platform_device *cns3420_pdevs[] __initdata = {
113 &cns3420_nor_pdev,
114};
115
116static void __init cns3420_init(void)
117{
118 platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
119
120 pm_power_off = cns3xxx_power_off;
121}
122
123static struct map_desc cns3420_io_desc[] __initdata = {
124 {
125 .virtual = CNS3XXX_UART0_BASE_VIRT,
126 .pfn = __phys_to_pfn(CNS3XXX_UART0_BASE),
127 .length = SZ_4K,
128 .type = MT_DEVICE,
129 },
130};
131
132static void __init cns3420_map_io(void)
133{
134 cns3xxx_map_io();
135 iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc));
136
137 cns3420_early_serial_setup();
138}
139
140MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
141 .phys_io = CNS3XXX_UART0_BASE,
142 .io_pg_offst = (CNS3XXX_UART0_BASE_VIRT >> 18) & 0xfffc,
143 .boot_params = 0x00000100,
144 .map_io = cns3420_map_io,
145 .init_irq = cns3xxx_init_irq,
146 .timer = &cns3xxx_timer,
147 .init_machine = cns3420_init,
148MACHINE_END
diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c
new file mode 100644
index 00000000000..9ca4d581016
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -0,0 +1,249 @@
1/*
2 * Copyright 1999 - 2003 ARM Limited
3 * Copyright 2000 Deep Blue Solutions Ltd
4 * Copyright 2008 Cavium Networks
5 *
6 * This file is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License, Version 2, as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/clockchips.h>
14#include <linux/io.h>
15#include <asm/mach/map.h>
16#include <asm/mach/time.h>
17#include <asm/mach/irq.h>
18#include <asm/hardware/gic.h>
19#include <mach/cns3xxx.h>
20#include "core.h"
21
22static struct map_desc cns3xxx_io_desc[] __initdata = {
23 {
24 .virtual = CNS3XXX_TC11MP_TWD_BASE_VIRT,
25 .pfn = __phys_to_pfn(CNS3XXX_TC11MP_TWD_BASE),
26 .length = SZ_4K,
27 .type = MT_DEVICE,
28 }, {
29 .virtual = CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT,
30 .pfn = __phys_to_pfn(CNS3XXX_TC11MP_GIC_CPU_BASE),
31 .length = SZ_4K,
32 .type = MT_DEVICE,
33 }, {
34 .virtual = CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT,
35 .pfn = __phys_to_pfn(CNS3XXX_TC11MP_GIC_DIST_BASE),
36 .length = SZ_4K,
37 .type = MT_DEVICE,
38 }, {
39 .virtual = CNS3XXX_TIMER1_2_3_BASE_VIRT,
40 .pfn = __phys_to_pfn(CNS3XXX_TIMER1_2_3_BASE),
41 .length = SZ_4K,
42 .type = MT_DEVICE,
43 }, {
44 .virtual = CNS3XXX_GPIOA_BASE_VIRT,
45 .pfn = __phys_to_pfn(CNS3XXX_GPIOA_BASE),
46 .length = SZ_4K,
47 .type = MT_DEVICE,
48 }, {
49 .virtual = CNS3XXX_GPIOB_BASE_VIRT,
50 .pfn = __phys_to_pfn(CNS3XXX_GPIOB_BASE),
51 .length = SZ_4K,
52 .type = MT_DEVICE,
53 }, {
54 .virtual = CNS3XXX_MISC_BASE_VIRT,
55 .pfn = __phys_to_pfn(CNS3XXX_MISC_BASE),
56 .length = SZ_4K,
57 .type = MT_DEVICE,
58 }, {
59 .virtual = CNS3XXX_PM_BASE_VIRT,
60 .pfn = __phys_to_pfn(CNS3XXX_PM_BASE),
61 .length = SZ_4K,
62 .type = MT_DEVICE,
63 },
64};
65
66void __init cns3xxx_map_io(void)
67{
68 iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
69}
70
71/* used by entry-macro.S */
72void __iomem *gic_cpu_base_addr;
73
74void __init cns3xxx_init_irq(void)
75{
76 gic_cpu_base_addr = __io(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT);
77 gic_dist_init(0, __io(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT), 29);
78 gic_cpu_init(0, gic_cpu_base_addr);
79}
80
81void cns3xxx_power_off(void)
82{
83 u32 __iomem *pm_base = __io(CNS3XXX_PM_BASE_VIRT);
84 u32 clkctrl;
85
86 printk(KERN_INFO "powering system down...\n");
87
88 clkctrl = readl(pm_base + PM_SYS_CLK_CTRL_OFFSET);
89 clkctrl &= 0xfffff1ff;
90 clkctrl |= (0x5 << 9); /* Hibernate */
91 writel(clkctrl, pm_base + PM_SYS_CLK_CTRL_OFFSET);
92
93}
94
95/*
96 * Timer
97 */
98static void __iomem *cns3xxx_tmr1;
99
100static void cns3xxx_timer_set_mode(enum clock_event_mode mode,
101 struct clock_event_device *clk)
102{
103 unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
104 int pclk = cns3xxx_cpu_clock() / 8;
105 int reload;
106
107 switch (mode) {
108 case CLOCK_EVT_MODE_PERIODIC:
109 reload = pclk * 20 / (3 * HZ) * 0x25000;
110 writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
111 ctrl |= (1 << 0) | (1 << 2) | (1 << 9);
112 break;
113 case CLOCK_EVT_MODE_ONESHOT:
114 /* period set, and timer enabled in 'next_event' hook */
115 ctrl |= (1 << 2) | (1 << 9);
116 break;
117 case CLOCK_EVT_MODE_UNUSED:
118 case CLOCK_EVT_MODE_SHUTDOWN:
119 default:
120 ctrl = 0;
121 }
122
123 writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
124}
125
126static int cns3xxx_timer_set_next_event(unsigned long evt,
127 struct clock_event_device *unused)
128{
129 unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
130
131 writel(evt, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
132 writel(ctrl | (1 << 0), cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
133
134 return 0;
135}
136
137static struct clock_event_device cns3xxx_tmr1_clockevent = {
138 .name = "cns3xxx timer1",
139 .shift = 8,
140 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
141 .set_mode = cns3xxx_timer_set_mode,
142 .set_next_event = cns3xxx_timer_set_next_event,
143 .rating = 350,
144 .cpumask = cpu_all_mask,
145};
146
147static void __init cns3xxx_clockevents_init(unsigned int timer_irq)
148{
149 cns3xxx_tmr1_clockevent.irq = timer_irq;
150 cns3xxx_tmr1_clockevent.mult =
151 div_sc((cns3xxx_cpu_clock() >> 3) * 1000000, NSEC_PER_SEC,
152 cns3xxx_tmr1_clockevent.shift);
153 cns3xxx_tmr1_clockevent.max_delta_ns =
154 clockevent_delta2ns(0xffffffff, &cns3xxx_tmr1_clockevent);
155 cns3xxx_tmr1_clockevent.min_delta_ns =
156 clockevent_delta2ns(0xf, &cns3xxx_tmr1_clockevent);
157
158 clockevents_register_device(&cns3xxx_tmr1_clockevent);
159}
160
161/*
162 * IRQ handler for the timer
163 */
164static irqreturn_t cns3xxx_timer_interrupt(int irq, void *dev_id)
165{
166 struct clock_event_device *evt = &cns3xxx_tmr1_clockevent;
167 u32 __iomem *stat = cns3xxx_tmr1 + TIMER1_2_INTERRUPT_STATUS_OFFSET;
168 u32 val;
169
170 /* Clear the interrupt */
171 val = readl(stat);
172 writel(val & ~(1 << 2), stat);
173
174 evt->event_handler(evt);
175
176 return IRQ_HANDLED;
177}
178
179static struct irqaction cns3xxx_timer_irq = {
180 .name = "timer",
181 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
182 .handler = cns3xxx_timer_interrupt,
183};
184
185/*
186 * Set up the clock source and clock events devices
187 */
188static void __init __cns3xxx_timer_init(unsigned int timer_irq)
189{
190 u32 val;
191 u32 irq_mask;
192
193 /*
194 * Initialise to a known state (all timers off)
195 */
196
197 /* disable timer1 and timer2 */
198 writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
199 /* stop free running timer3 */
200 writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
201
202 /* timer1 */
203 writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET);
204 writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
205
206 writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET);
207 writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET);
208
209 /* mask irq, non-mask timer1 overflow */
210 irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
211 irq_mask &= ~(1 << 2);
212 irq_mask |= 0x03;
213 writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
214
215 /* down counter */
216 val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
217 val |= (1 << 9);
218 writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
219
220 /* timer2 */
221 writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET);
222 writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET);
223
224 /* mask irq */
225 irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
226 irq_mask |= ((1 << 3) | (1 << 4) | (1 << 5));
227 writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
228
229 /* down counter */
230 val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
231 val |= (1 << 10);
232 writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
233
234 /* Make irqs happen for the system timer */
235 setup_irq(timer_irq, &cns3xxx_timer_irq);
236
237 cns3xxx_clockevents_init(timer_irq);
238}
239
240static void __init cns3xxx_timer_init(void)
241{
242 cns3xxx_tmr1 = __io(CNS3XXX_TIMER1_2_3_BASE_VIRT);
243
244 __cns3xxx_timer_init(IRQ_CNS3XXX_TIMER0);
245}
246
247struct sys_timer cns3xxx_timer = {
248 .init = cns3xxx_timer_init,
249};
diff --git a/arch/arm/mach-cns3xxx/core.h b/arch/arm/mach-cns3xxx/core.h
new file mode 100644
index 00000000000..6b33ec11346
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/core.h
@@ -0,0 +1,23 @@
1/*
2 * Copyright 2000 Deep Blue Solutions Ltd
3 * Copyright 2004 ARM Limited
4 * Copyright 2008 Cavium Networks
5 *
6 * This file is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License, Version 2, as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __CNS3XXX_CORE_H
12#define __CNS3XXX_CORE_H
13
14extern void __iomem *gic_cpu_base_addr;
15extern struct sys_timer cns3xxx_timer;
16
17void __init cns3xxx_map_io(void);
18void __init cns3xxx_init_irq(void);
19void cns3xxx_power_off(void);
20void cns3xxx_pwr_power_up(unsigned int block);
21void cns3xxx_pwr_power_down(unsigned int block);
22
23#endif /* __CNS3XXX_CORE_H */
diff --git a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
new file mode 100644
index 00000000000..8a2f5a21d4e
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
@@ -0,0 +1,635 @@
1/*
2 * Copyright 2008 Cavium Networks
3 *
4 * This file is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License, Version 2, as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __MACH_BOARD_CNS3XXXH
10#define __MACH_BOARD_CNS3XXXH
11
12/*
13 * Memory map
14 */
15#define CNS3XXX_FLASH_BASE 0x10000000 /* Flash/SRAM Memory Bank 0 */
16#define CNS3XXX_FLASH_SIZE SZ_256M
17
18#define CNS3XXX_DDR2SDRAM_BASE 0x20000000 /* DDR2 SDRAM Memory */
19
20#define CNS3XXX_SPI_FLASH_BASE 0x60000000 /* SPI Serial Flash Memory */
21
22#define CNS3XXX_SWITCH_BASE 0x70000000 /* Switch and HNAT Control */
23#define CNS3XXX_SWITCH_BASE_VIRT 0xFFF00000
24
25#define CNS3XXX_PPE_BASE 0x70001000 /* HANT */
26#define CNS3XXX_PPE_BASE_VIRT 0xFFF50000
27
28#define CNS3XXX_EMBEDDED_SRAM_BASE 0x70002000 /* HANT Embedded SRAM */
29#define CNS3XXX_EMBEDDED_SRAM_BASE_VIRT 0xFFF60000
30
31#define CNS3XXX_SSP_BASE 0x71000000 /* Synchronous Serial Port - SPI/PCM/I2C */
32#define CNS3XXX_SSP_BASE_VIRT 0xFFF01000
33
34#define CNS3XXX_DMC_BASE 0x72000000 /* DMC Control (DDR2 SDRAM) */
35#define CNS3XXX_DMC_BASE_VIRT 0xFFF02000
36
37#define CNS3XXX_SMC_BASE 0x73000000 /* SMC Control */
38#define CNS3XXX_SMC_BASE_VIRT 0xFFF03000
39
40#define SMC_MEMC_STATUS_OFFSET 0x000
41#define SMC_MEMIF_CFG_OFFSET 0x004
42#define SMC_MEMC_CFG_SET_OFFSET 0x008
43#define SMC_MEMC_CFG_CLR_OFFSET 0x00C
44#define SMC_DIRECT_CMD_OFFSET 0x010
45#define SMC_SET_CYCLES_OFFSET 0x014
46#define SMC_SET_OPMODE_OFFSET 0x018
47#define SMC_REFRESH_PERIOD_0_OFFSET 0x020
48#define SMC_REFRESH_PERIOD_1_OFFSET 0x024
49#define SMC_SRAM_CYCLES0_0_OFFSET 0x100
50#define SMC_NAND_CYCLES0_0_OFFSET 0x100
51#define SMC_OPMODE0_0_OFFSET 0x104
52#define SMC_SRAM_CYCLES0_1_OFFSET 0x120
53#define SMC_NAND_CYCLES0_1_OFFSET 0x120
54#define SMC_OPMODE0_1_OFFSET 0x124
55#define SMC_USER_STATUS_OFFSET 0x200
56#define SMC_USER_CONFIG_OFFSET 0x204
57#define SMC_ECC_STATUS_OFFSET 0x300
58#define SMC_ECC_MEMCFG_OFFSET 0x304
59#define SMC_ECC_MEMCOMMAND1_OFFSET 0x308
60#define SMC_ECC_MEMCOMMAND2_OFFSET 0x30C
61#define SMC_ECC_ADDR0_OFFSET 0x310
62#define SMC_ECC_ADDR1_OFFSET 0x314
63#define SMC_ECC_VALUE0_OFFSET 0x318
64#define SMC_ECC_VALUE1_OFFSET 0x31C
65#define SMC_ECC_VALUE2_OFFSET 0x320
66#define SMC_ECC_VALUE3_OFFSET 0x324
67#define SMC_PERIPH_ID_0_OFFSET 0xFE0
68#define SMC_PERIPH_ID_1_OFFSET 0xFE4
69#define SMC_PERIPH_ID_2_OFFSET 0xFE8
70#define SMC_PERIPH_ID_3_OFFSET 0xFEC
71#define SMC_PCELL_ID_0_OFFSET 0xFF0
72#define SMC_PCELL_ID_1_OFFSET 0xFF4
73#define SMC_PCELL_ID_2_OFFSET 0xFF8
74#define SMC_PCELL_ID_3_OFFSET 0xFFC
75
76#define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */
77#define CNS3XXX_GPIOA_BASE_VIRT 0xFFF04000
78
79#define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */
80#define CNS3XXX_GPIOB_BASE_VIRT 0xFFF05000
81
82#define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */
83#define CNS3XXX_RTC_BASE_VIRT 0xFFF06000
84
85#define RTC_SEC_OFFSET 0x00
86#define RTC_MIN_OFFSET 0x04
87#define RTC_HOUR_OFFSET 0x08
88#define RTC_DAY_OFFSET 0x0C
89#define RTC_SEC_ALM_OFFSET 0x10
90#define RTC_MIN_ALM_OFFSET 0x14
91#define RTC_HOUR_ALM_OFFSET 0x18
92#define RTC_REC_OFFSET 0x1C
93#define RTC_CTRL_OFFSET 0x20
94#define RTC_INTR_STS_OFFSET 0x34
95
96#define CNS3XXX_MISC_BASE 0x76000000 /* Misc Control */
97#define CNS3XXX_MISC_BASE_VIRT 0xFFF07000 /* Misc Control */
98
99#define CNS3XXX_PM_BASE 0x77000000 /* Power Management Control */
100#define CNS3XXX_PM_BASE_VIRT 0xFFF08000
101
102#define PM_CLK_GATE_OFFSET 0x00
103#define PM_SOFT_RST_OFFSET 0x04
104#define PM_HS_CFG_OFFSET 0x08
105#define PM_CACTIVE_STA_OFFSET 0x0C
106#define PM_PWR_STA_OFFSET 0x10
107#define PM_SYS_CLK_CTRL_OFFSET 0x14
108#define PM_PLL_LCD_I2S_CTRL_OFFSET 0x18
109#define PM_PLL_HM_PD_OFFSET 0x1C
110
111#define CNS3XXX_UART0_BASE 0x78000000 /* UART 0 */
112#define CNS3XXX_UART0_BASE_VIRT 0xFFF09000
113
114#define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */
115#define CNS3XXX_UART1_BASE_VIRT 0xFFF0A000
116
117#define CNS3XXX_UART2_BASE 0x78800000 /* UART 2 */
118#define CNS3XXX_UART2_BASE_VIRT 0xFFF0B000
119
120#define CNS3XXX_DMAC_BASE 0x79000000 /* Generic DMA Control */
121#define CNS3XXX_DMAC_BASE_VIRT 0xFFF0D000
122
123#define CNS3XXX_CORESIGHT_BASE 0x7A000000 /* CoreSight */
124#define CNS3XXX_CORESIGHT_BASE_VIRT 0xFFF0E000
125
126#define CNS3XXX_CRYPTO_BASE 0x7B000000 /* Crypto */
127#define CNS3XXX_CRYPTO_BASE_VIRT 0xFFF0F000
128
129#define CNS3XXX_I2S_BASE 0x7C000000 /* I2S */
130#define CNS3XXX_I2S_BASE_VIRT 0xFFF10000
131
132#define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */
133#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFFF10800
134
135#define TIMER1_COUNTER_OFFSET 0x00
136#define TIMER1_AUTO_RELOAD_OFFSET 0x04
137#define TIMER1_MATCH_V1_OFFSET 0x08
138#define TIMER1_MATCH_V2_OFFSET 0x0C
139
140#define TIMER2_COUNTER_OFFSET 0x10
141#define TIMER2_AUTO_RELOAD_OFFSET 0x14
142#define TIMER2_MATCH_V1_OFFSET 0x18
143#define TIMER2_MATCH_V2_OFFSET 0x1C
144
145#define TIMER1_2_CONTROL_OFFSET 0x30
146#define TIMER1_2_INTERRUPT_STATUS_OFFSET 0x34
147#define TIMER1_2_INTERRUPT_MASK_OFFSET 0x38
148
149#define TIMER_FREERUN_OFFSET 0x40
150#define TIMER_FREERUN_CONTROL_OFFSET 0x44
151
152#define CNS3XXX_HCIE_BASE 0x7D000000 /* HCIE Control */
153#define CNS3XXX_HCIE_BASE_VIRT 0xFFF30000
154
155#define CNS3XXX_RAID_BASE 0x7E000000 /* RAID Control */
156#define CNS3XXX_RAID_BASE_VIRT 0xFFF12000
157
158#define CNS3XXX_AXI_IXC_BASE 0x7F000000 /* AXI IXC */
159#define CNS3XXX_AXI_IXC_BASE_VIRT 0xFFF13000
160
161#define CNS3XXX_CLCD_BASE 0x80000000 /* LCD Control */
162#define CNS3XXX_CLCD_BASE_VIRT 0xFFF14000
163
164#define CNS3XXX_USBOTG_BASE 0x81000000 /* USB OTG Control */
165#define CNS3XXX_USBOTG_BASE_VIRT 0xFFF15000
166
167#define CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */
168#define CNS3XXX_USB_BASE_VIRT 0xFFF16000
169
170#define CNS3XXX_SATA2_BASE 0x83000000 /* SATA */
171#define CNS3XXX_SATA2_SIZE SZ_16M
172#define CNS3XXX_SATA2_BASE_VIRT 0xFFF17000
173
174#define CNS3XXX_CAMERA_BASE 0x84000000 /* Camera Interface */
175#define CNS3XXX_CAMERA_BASE_VIRT 0xFFF18000
176
177#define CNS3XXX_SDIO_BASE 0x85000000 /* SDIO */
178#define CNS3XXX_SDIO_BASE_VIRT 0xFFF19000
179
180#define CNS3XXX_I2S_TDM_BASE 0x86000000 /* I2S TDM */
181#define CNS3XXX_I2S_TDM_BASE_VIRT 0xFFF1A000
182
183#define CNS3XXX_2DG_BASE 0x87000000 /* 2D Graphic Control */
184#define CNS3XXX_2DG_BASE_VIRT 0xFFF1B000
185
186#define CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */
187#define CNS3XXX_USB_OHCI_BASE_VIRT 0xFFF1C000
188
189#define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */
190#define CNS3XXX_L2C_BASE_VIRT 0xFFF27000
191
192#define CNS3XXX_PCIE0_MEM_BASE 0xA0000000 /* PCIe Port 0 IO/Memory Space */
193#define CNS3XXX_PCIE0_MEM_BASE_VIRT 0xE0000000
194
195#define CNS3XXX_PCIE0_HOST_BASE 0xAB000000 /* PCIe Port 0 RC Base */
196#define CNS3XXX_PCIE0_HOST_BASE_VIRT 0xE1000000
197
198#define CNS3XXX_PCIE0_IO_BASE 0xAC000000 /* PCIe Port 0 */
199#define CNS3XXX_PCIE0_IO_BASE_VIRT 0xE2000000
200
201#define CNS3XXX_PCIE0_CFG0_BASE 0xAD000000 /* PCIe Port 0 CFG Type 0 */
202#define CNS3XXX_PCIE0_CFG0_BASE_VIRT 0xE3000000
203
204#define CNS3XXX_PCIE0_CFG1_BASE 0xAE000000 /* PCIe Port 0 CFG Type 1 */
205#define CNS3XXX_PCIE0_CFG1_BASE_VIRT 0xE4000000
206
207#define CNS3XXX_PCIE0_MSG_BASE 0xAF000000 /* PCIe Port 0 Message Space */
208#define CNS3XXX_PCIE0_MSG_BASE_VIRT 0xE5000000
209
210#define CNS3XXX_PCIE1_MEM_BASE 0xB0000000 /* PCIe Port 1 IO/Memory Space */
211#define CNS3XXX_PCIE1_MEM_BASE_VIRT 0xE8000000
212
213#define CNS3XXX_PCIE1_HOST_BASE 0xBB000000 /* PCIe Port 1 RC Base */
214#define CNS3XXX_PCIE1_HOST_BASE_VIRT 0xE9000000
215
216#define CNS3XXX_PCIE1_IO_BASE 0xBC000000 /* PCIe Port 1 */
217#define CNS3XXX_PCIE1_IO_BASE_VIRT 0xEA000000
218
219#define CNS3XXX_PCIE1_CFG0_BASE 0xBD000000 /* PCIe Port 1 CFG Type 0 */
220#define CNS3XXX_PCIE1_CFG0_BASE_VIRT 0xEB000000
221
222#define CNS3XXX_PCIE1_CFG1_BASE 0xBE000000 /* PCIe Port 1 CFG Type 1 */
223#define CNS3XXX_PCIE1_CFG1_BASE_VIRT 0xEC000000
224
225#define CNS3XXX_PCIE1_MSG_BASE 0xBF000000 /* PCIe Port 1 Message Space */
226#define CNS3XXX_PCIE1_MSG_BASE_VIRT 0xED000000
227
228/*
229 * Testchip peripheral and fpga gic regions
230 */
231#define CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */
232#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFF000000
233
234#define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */
235#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT 0xFF000100
236
237#define CNS3XXX_TC11MP_TWD_BASE 0x90000600
238#define CNS3XXX_TC11MP_TWD_BASE_VIRT 0xFF000600
239
240#define CNS3XXX_TC11MP_GIC_DIST_BASE 0x90001000 /* Test chip interrupt controller distributor */
241#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT 0xFF001000
242
243#define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */
244#define CNS3XXX_TC11MP_L220_BASE_VIRT 0xFF002000
245
246/*
247 * Misc block
248 */
249#define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs))
250#define MISC_MEM_MAP_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_MISC_BASE_VIRT + (offset))))
251
252#define MISC_MEMORY_REMAP_REG MISC_MEM_MAP_VALUE(0x00)
253#define MISC_CHIP_CONFIG_REG MISC_MEM_MAP_VALUE(0x04)
254#define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP_VALUE(0x08)
255#define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP_VALUE(0x0C)
256#define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP_VALUE(0x10)
257#define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP_VALUE(0x14)
258#define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP_VALUE(0x18)
259#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP_VALUE(0x1C)
260#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP_VALUE(0x20)
261#define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x24)
262#define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x28)
263#define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x2C)
264#define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x30)
265#define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x34)
266#define MISC_E_FUSE_31_0_REG MISC_MEM_MAP_VALUE(0x40)
267#define MISC_E_FUSE_63_32_REG MISC_MEM_MAP_VALUE(0x44)
268#define MISC_E_FUSE_95_64_REG MISC_MEM_MAP_VALUE(0x48)
269#define MISC_E_FUSE_127_96_REG MISC_MEM_MAP_VALUE(0x4C)
270#define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP_VALUE(0x50)
271#define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP_VALUE(0x54)
272
273#define MISC_SATA_POWER_MODE MISC_MEM_MAP_VALUE(0x310)
274
275#define MISC_USB_CFG_REG MISC_MEM_MAP_VALUE(0x800)
276#define MISC_USB_STS_REG MISC_MEM_MAP_VALUE(0x804)
277#define MISC_USBPHY00_CFG_REG MISC_MEM_MAP_VALUE(0x808)
278#define MISC_USBPHY01_CFG_REG MISC_MEM_MAP_VALUE(0x80c)
279#define MISC_USBPHY10_CFG_REG MISC_MEM_MAP_VALUE(0x810)
280#define MISC_USBPHY11_CFG_REG MISC_MEM_MAP_VALUE(0x814)
281
282#define MISC_PCIEPHY_CMCTL(x) MISC_MEM_MAP(0x900 + (x) * 0x004)
283#define MISC_PCIEPHY_CTL(x) MISC_MEM_MAP(0x940 + (x) * 0x100)
284#define MISC_PCIE_AXIS_AWMISC(x) MISC_MEM_MAP(0x944 + (x) * 0x100)
285#define MISC_PCIE_AXIS_ARMISC(x) MISC_MEM_MAP(0x948 + (x) * 0x100)
286#define MISC_PCIE_AXIS_RMISC(x) MISC_MEM_MAP(0x94C + (x) * 0x100)
287#define MISC_PCIE_AXIS_BMISC(x) MISC_MEM_MAP(0x950 + (x) * 0x100)
288#define MISC_PCIE_AXIM_RMISC(x) MISC_MEM_MAP(0x954 + (x) * 0x100)
289#define MISC_PCIE_AXIM_BMISC(x) MISC_MEM_MAP(0x958 + (x) * 0x100)
290#define MISC_PCIE_CTRL(x) MISC_MEM_MAP(0x95C + (x) * 0x100)
291#define MISC_PCIE_PM_DEBUG(x) MISC_MEM_MAP(0x960 + (x) * 0x100)
292#define MISC_PCIE_RFC_DEBUG(x) MISC_MEM_MAP(0x964 + (x) * 0x100)
293#define MISC_PCIE_CXPL_DEBUGL(x) MISC_MEM_MAP(0x968 + (x) * 0x100)
294#define MISC_PCIE_CXPL_DEBUGH(x) MISC_MEM_MAP(0x96C + (x) * 0x100)
295#define MISC_PCIE_DIAG_DEBUGH(x) MISC_MEM_MAP(0x970 + (x) * 0x100)
296#define MISC_PCIE_W1CLR(x) MISC_MEM_MAP(0x974 + (x) * 0x100)
297#define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100)
298#define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100)
299
300/*
301 * Power management and clock control
302 */
303#define PMU_REG_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_PM_BASE_VIRT + (offset))))
304
305#define PM_CLK_GATE_REG PMU_REG_VALUE(0x000)
306#define PM_SOFT_RST_REG PMU_REG_VALUE(0x004)
307#define PM_HS_CFG_REG PMU_REG_VALUE(0x008)
308#define PM_CACTIVE_STA_REG PMU_REG_VALUE(0x00C)
309#define PM_PWR_STA_REG PMU_REG_VALUE(0x010)
310#define PM_CLK_CTRL_REG PMU_REG_VALUE(0x014)
311#define PM_PLL_LCD_I2S_CTRL_REG PMU_REG_VALUE(0x018)
312#define PM_PLL_HM_PD_CTRL_REG PMU_REG_VALUE(0x01C)
313#define PM_REGULAT_CTRL_REG PMU_REG_VALUE(0x020)
314#define PM_WDT_CTRL_REG PMU_REG_VALUE(0x024)
315#define PM_WU_CTRL0_REG PMU_REG_VALUE(0x028)
316#define PM_WU_CTRL1_REG PMU_REG_VALUE(0x02C)
317#define PM_CSR_REG PMU_REG_VALUE(0x030)
318
319/* PM_CLK_GATE_REG */
320#define PM_CLK_GATE_REG_OFFSET_SDIO (25)
321#define PM_CLK_GATE_REG_OFFSET_GPU (24)
322#define PM_CLK_GATE_REG_OFFSET_CIM (23)
323#define PM_CLK_GATE_REG_OFFSET_LCDC (22)
324#define PM_CLK_GATE_REG_OFFSET_I2S (21)
325#define PM_CLK_GATE_REG_OFFSET_RAID (20)
326#define PM_CLK_GATE_REG_OFFSET_SATA (19)
327#define PM_CLK_GATE_REG_OFFSET_PCIE(x) (17 + (x))
328#define PM_CLK_GATE_REG_OFFSET_USB_HOST (16)
329#define PM_CLK_GATE_REG_OFFSET_USB_OTG (15)
330#define PM_CLK_GATE_REG_OFFSET_TIMER (14)
331#define PM_CLK_GATE_REG_OFFSET_CRYPTO (13)
332#define PM_CLK_GATE_REG_OFFSET_HCIE (12)
333#define PM_CLK_GATE_REG_OFFSET_SWITCH (11)
334#define PM_CLK_GATE_REG_OFFSET_GPIO (10)
335#define PM_CLK_GATE_REG_OFFSET_UART3 (9)
336#define PM_CLK_GATE_REG_OFFSET_UART2 (8)
337#define PM_CLK_GATE_REG_OFFSET_UART1 (7)
338#define PM_CLK_GATE_REG_OFFSET_RTC (5)
339#define PM_CLK_GATE_REG_OFFSET_GDMA (4)
340#define PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C (3)
341#define PM_CLK_GATE_REG_OFFSET_SMC_NFI (1)
342#define PM_CLK_GATE_REG_MASK (0x03FFFFBA)
343
344/* PM_SOFT_RST_REG */
345#define PM_SOFT_RST_REG_OFFST_WARM_RST_FLAG (31)
346#define PM_SOFT_RST_REG_OFFST_CPU1 (29)
347#define PM_SOFT_RST_REG_OFFST_CPU0 (28)
348#define PM_SOFT_RST_REG_OFFST_SDIO (25)
349#define PM_SOFT_RST_REG_OFFST_GPU (24)
350#define PM_SOFT_RST_REG_OFFST_CIM (23)
351#define PM_SOFT_RST_REG_OFFST_LCDC (22)
352#define PM_SOFT_RST_REG_OFFST_I2S (21)
353#define PM_SOFT_RST_REG_OFFST_RAID (20)
354#define PM_SOFT_RST_REG_OFFST_SATA (19)
355#define PM_SOFT_RST_REG_OFFST_PCIE(x) (17 + (x))
356#define PM_SOFT_RST_REG_OFFST_USB_HOST (16)
357#define PM_SOFT_RST_REG_OFFST_USB_OTG (15)
358#define PM_SOFT_RST_REG_OFFST_TIMER (14)
359#define PM_SOFT_RST_REG_OFFST_CRYPTO (13)
360#define PM_SOFT_RST_REG_OFFST_HCIE (12)
361#define PM_SOFT_RST_REG_OFFST_SWITCH (11)
362#define PM_SOFT_RST_REG_OFFST_GPIO (10)
363#define PM_SOFT_RST_REG_OFFST_UART3 (9)
364#define PM_SOFT_RST_REG_OFFST_UART2 (8)
365#define PM_SOFT_RST_REG_OFFST_UART1 (7)
366#define PM_SOFT_RST_REG_OFFST_RTC (5)
367#define PM_SOFT_RST_REG_OFFST_GDMA (4)
368#define PM_SOFT_RST_REG_OFFST_SPI_PCM_I2C (3)
369#define PM_SOFT_RST_REG_OFFST_DMC (2)
370#define PM_SOFT_RST_REG_OFFST_SMC_NFI (1)
371#define PM_SOFT_RST_REG_OFFST_GLOBAL (0)
372#define PM_SOFT_RST_REG_MASK (0xF3FFFFBF)
373
374/* PMHS_CFG_REG */
375#define PM_HS_CFG_REG_OFFSET_SDIO (25)
376#define PM_HS_CFG_REG_OFFSET_GPU (24)
377#define PM_HS_CFG_REG_OFFSET_CIM (23)
378#define PM_HS_CFG_REG_OFFSET_LCDC (22)
379#define PM_HS_CFG_REG_OFFSET_I2S (21)
380#define PM_HS_CFG_REG_OFFSET_RAID (20)
381#define PM_HS_CFG_REG_OFFSET_SATA (19)
382#define PM_HS_CFG_REG_OFFSET_PCIE1 (18)
383#define PM_HS_CFG_REG_OFFSET_PCIE0 (17)
384#define PM_HS_CFG_REG_OFFSET_USB_HOST (16)
385#define PM_HS_CFG_REG_OFFSET_USB_OTG (15)
386#define PM_HS_CFG_REG_OFFSET_TIMER (14)
387#define PM_HS_CFG_REG_OFFSET_CRYPTO (13)
388#define PM_HS_CFG_REG_OFFSET_HCIE (12)
389#define PM_HS_CFG_REG_OFFSET_SWITCH (11)
390#define PM_HS_CFG_REG_OFFSET_GPIO (10)
391#define PM_HS_CFG_REG_OFFSET_UART3 (9)
392#define PM_HS_CFG_REG_OFFSET_UART2 (8)
393#define PM_HS_CFG_REG_OFFSET_UART1 (7)
394#define PM_HS_CFG_REG_OFFSET_RTC (5)
395#define PM_HS_CFG_REG_OFFSET_GDMA (4)
396#define PM_HS_CFG_REG_OFFSET_SPI_PCM_I2S (3)
397#define PM_HS_CFG_REG_OFFSET_DMC (2)
398#define PM_HS_CFG_REG_OFFSET_SMC_NFI (1)
399#define PM_HS_CFG_REG_MASK (0x03FFFFBE)
400#define PM_HS_CFG_REG_MASK_SUPPORT (0x01100806)
401
402/* PM_CACTIVE_STA_REG */
403#define PM_CACTIVE_STA_REG_OFFSET_SDIO (25)
404#define PM_CACTIVE_STA_REG_OFFSET_GPU (24)
405#define PM_CACTIVE_STA_REG_OFFSET_CIM (23)
406#define PM_CACTIVE_STA_REG_OFFSET_LCDC (22)
407#define PM_CACTIVE_STA_REG_OFFSET_I2S (21)
408#define PM_CACTIVE_STA_REG_OFFSET_RAID (20)
409#define PM_CACTIVE_STA_REG_OFFSET_SATA (19)
410#define PM_CACTIVE_STA_REG_OFFSET_PCIE1 (18)
411#define PM_CACTIVE_STA_REG_OFFSET_PCIE0 (17)
412#define PM_CACTIVE_STA_REG_OFFSET_USB_HOST (16)
413#define PM_CACTIVE_STA_REG_OFFSET_USB_OTG (15)
414#define PM_CACTIVE_STA_REG_OFFSET_TIMER (14)
415#define PM_CACTIVE_STA_REG_OFFSET_CRYPTO (13)
416#define PM_CACTIVE_STA_REG_OFFSET_HCIE (12)
417#define PM_CACTIVE_STA_REG_OFFSET_SWITCH (11)
418#define PM_CACTIVE_STA_REG_OFFSET_GPIO (10)
419#define PM_CACTIVE_STA_REG_OFFSET_UART3 (9)
420#define PM_CACTIVE_STA_REG_OFFSET_UART2 (8)
421#define PM_CACTIVE_STA_REG_OFFSET_UART1 (7)
422#define PM_CACTIVE_STA_REG_OFFSET_RTC (5)
423#define PM_CACTIVE_STA_REG_OFFSET_GDMA (4)
424#define PM_CACTIVE_STA_REG_OFFSET_SPI_PCM_I2S (3)
425#define PM_CACTIVE_STA_REG_OFFSET_DMC (2)
426#define PM_CACTIVE_STA_REG_OFFSET_SMC_NFI (1)
427#define PM_CACTIVE_STA_REG_MASK (0x03FFFFBE)
428
429/* PM_PWR_STA_REG */
430#define PM_PWR_STA_REG_REG_OFFSET_SDIO (25)
431#define PM_PWR_STA_REG_REG_OFFSET_GPU (24)
432#define PM_PWR_STA_REG_REG_OFFSET_CIM (23)
433#define PM_PWR_STA_REG_REG_OFFSET_LCDC (22)
434#define PM_PWR_STA_REG_REG_OFFSET_I2S (21)
435#define PM_PWR_STA_REG_REG_OFFSET_RAID (20)
436#define PM_PWR_STA_REG_REG_OFFSET_SATA (19)
437#define PM_PWR_STA_REG_REG_OFFSET_PCIE1 (18)
438#define PM_PWR_STA_REG_REG_OFFSET_PCIE0 (17)
439#define PM_PWR_STA_REG_REG_OFFSET_USB_HOST (16)
440#define PM_PWR_STA_REG_REG_OFFSET_USB_OTG (15)
441#define PM_PWR_STA_REG_REG_OFFSET_TIMER (14)
442#define PM_PWR_STA_REG_REG_OFFSET_CRYPTO (13)
443#define PM_PWR_STA_REG_REG_OFFSET_HCIE (12)
444#define PM_PWR_STA_REG_REG_OFFSET_SWITCH (11)
445#define PM_PWR_STA_REG_REG_OFFSET_GPIO (10)
446#define PM_PWR_STA_REG_REG_OFFSET_UART3 (9)
447#define PM_PWR_STA_REG_REG_OFFSET_UART2 (8)
448#define PM_PWR_STA_REG_REG_OFFSET_UART1 (7)
449#define PM_PWR_STA_REG_REG_OFFSET_RTC (5)
450#define PM_PWR_STA_REG_REG_OFFSET_GDMA (4)
451#define PM_PWR_STA_REG_REG_OFFSET_SPI_PCM_I2S (3)
452#define PM_PWR_STA_REG_REG_OFFSET_DMC (2)
453#define PM_PWR_STA_REG_REG_OFFSET_SMC_NFI (1)
454#define PM_PWR_STA_REG_REG_MASK (0x03FFFFBE)
455
456/* PM_CLK_CTRL_REG */
457#define PM_CLK_CTRL_REG_OFFSET_I2S_MCLK (31)
458#define PM_CLK_CTRL_REG_OFFSET_DDR2_CHG_EN (30)
459#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF1_EN (29)
460#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF0_EN (28)
461#define PM_CLK_CTRL_REG_OFFSET_TIMER_SIM_MODE (27)
462#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_DIV (24)
463#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_SEL (22)
464#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_DIV (20)
465#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_SEL (16)
466#define PM_CLK_CTRL_REG_OFFSET_MDC_DIV (14)
467#define PM_CLK_CTRL_REG_OFFSET_CRYPTO_CLK_SEL (12)
468#define PM_CLK_CTRL_REG_OFFSET_CPU_PWR_MODE (9)
469#define PM_CLK_CTRL_REG_OFFSET_PLL_DDR2_SEL (7)
470#define PM_CLK_CTRL_REG_OFFSET_DIV_IMMEDIATE (6)
471#define PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV (4)
472#define PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL (0)
473
474#define PM_CPU_CLK_DIV(DIV) { \
475 PM_CLK_CTRL_REG &= ~((0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \
476 PM_CLK_CTRL_REG |= (((DIV)&0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \
477}
478
479#define PM_PLL_CPU_SEL(CPU) { \
480 PM_CLK_CTRL_REG &= ~((0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \
481 PM_CLK_CTRL_REG |= (((CPU)&0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \
482}
483
484/* PM_PLL_LCD_I2S_CTRL_REG */
485#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_MCLK_SMC_DIV (22)
486#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_R_SEL (17)
487#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_P (11)
488#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_M (3)
489#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_S (0)
490
491/* PM_PLL_HM_PD_CTRL_REG */
492#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1 (11)
493#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0 (10)
494#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2SCD (6)
495#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2S (5)
496#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_LCD (4)
497#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB (3)
498#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_RGMII (2)
499#define PM_PLL_HM_PD_CTRL_REG_MASK (0x00000C7C)
500
501/* PM_WDT_CTRL_REG */
502#define PM_WDT_CTRL_REG_OFFSET_RESET_CPU_ONLY (0)
503
504/* PM_CSR_REG - Clock Scaling Register*/
505#define PM_CSR_REG_OFFSET_CSR_EN (30)
506#define PM_CSR_REG_OFFSET_CSR_NUM (0)
507
508#define CNS3XXX_PWR_CLK_EN(BLOCK) (0x1<<PM_CLK_GATE_REG_OFFSET_##BLOCK)
509
510/* Software reset*/
511#define CNS3XXX_PWR_SOFTWARE_RST(BLOCK) (0x1<<PM_SOFT_RST_REG_OFFST_##BLOCK)
512
513/*
514 * CNS3XXX support several power saving mode as following,
515 * DFS, IDLE, HALT, DOZE, SLEEP, Hibernate
516 */
517#define CNS3XXX_PWR_CPU_MODE_DFS (0)
518#define CNS3XXX_PWR_CPU_MODE_IDLE (1)
519#define CNS3XXX_PWR_CPU_MODE_HALT (2)
520#define CNS3XXX_PWR_CPU_MODE_DOZE (3)
521#define CNS3XXX_PWR_CPU_MODE_SLEEP (4)
522#define CNS3XXX_PWR_CPU_MODE_HIBERNATE (5)
523
524#define CNS3XXX_PWR_PLL(BLOCK) (0x1<<PM_PLL_HM_PD_CTRL_REG_OFFSET_##BLOCK)
525#define CNS3XXX_PWR_PLL_ALL PM_PLL_HM_PD_CTRL_REG_MASK
526
527/* Change CPU frequency and divider */
528#define CNS3XXX_PWR_PLL_CPU_300MHZ (0)
529#define CNS3XXX_PWR_PLL_CPU_333MHZ (1)
530#define CNS3XXX_PWR_PLL_CPU_366MHZ (2)
531#define CNS3XXX_PWR_PLL_CPU_400MHZ (3)
532#define CNS3XXX_PWR_PLL_CPU_433MHZ (4)
533#define CNS3XXX_PWR_PLL_CPU_466MHZ (5)
534#define CNS3XXX_PWR_PLL_CPU_500MHZ (6)
535#define CNS3XXX_PWR_PLL_CPU_533MHZ (7)
536#define CNS3XXX_PWR_PLL_CPU_566MHZ (8)
537#define CNS3XXX_PWR_PLL_CPU_600MHZ (9)
538#define CNS3XXX_PWR_PLL_CPU_633MHZ (10)
539#define CNS3XXX_PWR_PLL_CPU_666MHZ (11)
540#define CNS3XXX_PWR_PLL_CPU_700MHZ (12)
541
542#define CNS3XXX_PWR_CPU_CLK_DIV_BY1 (0)
543#define CNS3XXX_PWR_CPU_CLK_DIV_BY2 (1)
544#define CNS3XXX_PWR_CPU_CLK_DIV_BY4 (2)
545
546/* Change DDR2 frequency */
547#define CNS3XXX_PWR_PLL_DDR2_200MHZ (0)
548#define CNS3XXX_PWR_PLL_DDR2_266MHZ (1)
549#define CNS3XXX_PWR_PLL_DDR2_333MHZ (2)
550#define CNS3XXX_PWR_PLL_DDR2_400MHZ (3)
551
552void cns3xxx_pwr_soft_rst(unsigned int block);
553void cns3xxx_pwr_clk_en(unsigned int block);
554int cns3xxx_cpu_clock(void);
555
556/*
557 * ARM11 MPCore interrupt sources (primary GIC)
558 */
559#define IRQ_CNS3XXX_PMU (IRQ_TC11MP_GIC_START + 0)
560#define IRQ_CNS3XXX_SDIO (IRQ_TC11MP_GIC_START + 1)
561#define IRQ_CNS3XXX_L2CC (IRQ_TC11MP_GIC_START + 2)
562#define IRQ_CNS3XXX_RTC (IRQ_TC11MP_GIC_START + 3)
563#define IRQ_CNS3XXX_I2S (IRQ_TC11MP_GIC_START + 4)
564#define IRQ_CNS3XXX_PCM (IRQ_TC11MP_GIC_START + 5)
565#define IRQ_CNS3XXX_SPI (IRQ_TC11MP_GIC_START + 6)
566#define IRQ_CNS3XXX_I2C (IRQ_TC11MP_GIC_START + 7)
567#define IRQ_CNS3XXX_CIM (IRQ_TC11MP_GIC_START + 8)
568#define IRQ_CNS3XXX_GPU (IRQ_TC11MP_GIC_START + 9)
569#define IRQ_CNS3XXX_LCD (IRQ_TC11MP_GIC_START + 10)
570#define IRQ_CNS3XXX_GPIOA (IRQ_TC11MP_GIC_START + 11)
571#define IRQ_CNS3XXX_GPIOB (IRQ_TC11MP_GIC_START + 12)
572#define IRQ_CNS3XXX_UART0 (IRQ_TC11MP_GIC_START + 13)
573#define IRQ_CNS3XXX_UART1 (IRQ_TC11MP_GIC_START + 14)
574#define IRQ_CNS3XXX_UART2 (IRQ_TC11MP_GIC_START + 15)
575#define IRQ_CNS3XXX_ARM11 (IRQ_TC11MP_GIC_START + 16)
576
577#define IRQ_CNS3XXX_SW_STATUS (IRQ_TC11MP_GIC_START + 17)
578#define IRQ_CNS3XXX_SW_R0TXC (IRQ_TC11MP_GIC_START + 18)
579#define IRQ_CNS3XXX_SW_R0RXC (IRQ_TC11MP_GIC_START + 19)
580#define IRQ_CNS3XXX_SW_R0QE (IRQ_TC11MP_GIC_START + 20)
581#define IRQ_CNS3XXX_SW_R0QF (IRQ_TC11MP_GIC_START + 21)
582#define IRQ_CNS3XXX_SW_R1TXC (IRQ_TC11MP_GIC_START + 22)
583#define IRQ_CNS3XXX_SW_R1RXC (IRQ_TC11MP_GIC_START + 23)
584#define IRQ_CNS3XXX_SW_R1QE (IRQ_TC11MP_GIC_START + 24)
585#define IRQ_CNS3XXX_SW_R1QF (IRQ_TC11MP_GIC_START + 25)
586#define IRQ_CNS3XXX_SW_PPE (IRQ_TC11MP_GIC_START + 26)
587
588#define IRQ_CNS3XXX_CRYPTO (IRQ_TC11MP_GIC_START + 27)
589#define IRQ_CNS3XXX_HCIE (IRQ_TC11MP_GIC_START + 28)
590#define IRQ_CNS3XXX_PCIE0_DEVICE (IRQ_TC11MP_GIC_START + 29)
591#define IRQ_CNS3XXX_PCIE1_DEVICE (IRQ_TC11MP_GIC_START + 30)
592#define IRQ_CNS3XXX_USB_OTG (IRQ_TC11MP_GIC_START + 31)
593#define IRQ_CNS3XXX_USB_EHCI (IRQ_TC11MP_GIC_START + 32)
594#define IRQ_CNS3XXX_SATA (IRQ_TC11MP_GIC_START + 33)
595#define IRQ_CNS3XXX_RAID (IRQ_TC11MP_GIC_START + 34)
596#define IRQ_CNS3XXX_SMC (IRQ_TC11MP_GIC_START + 35)
597
598#define IRQ_CNS3XXX_DMAC_ABORT (IRQ_TC11MP_GIC_START + 36)
599#define IRQ_CNS3XXX_DMAC0 (IRQ_TC11MP_GIC_START + 37)
600#define IRQ_CNS3XXX_DMAC1 (IRQ_TC11MP_GIC_START + 38)
601#define IRQ_CNS3XXX_DMAC2 (IRQ_TC11MP_GIC_START + 39)
602#define IRQ_CNS3XXX_DMAC3 (IRQ_TC11MP_GIC_START + 40)
603#define IRQ_CNS3XXX_DMAC4 (IRQ_TC11MP_GIC_START + 41)
604#define IRQ_CNS3XXX_DMAC5 (IRQ_TC11MP_GIC_START + 42)
605#define IRQ_CNS3XXX_DMAC6 (IRQ_TC11MP_GIC_START + 43)
606#define IRQ_CNS3XXX_DMAC7 (IRQ_TC11MP_GIC_START + 44)
607#define IRQ_CNS3XXX_DMAC8 (IRQ_TC11MP_GIC_START + 45)
608#define IRQ_CNS3XXX_DMAC9 (IRQ_TC11MP_GIC_START + 46)
609#define IRQ_CNS3XXX_DMAC10 (IRQ_TC11MP_GIC_START + 47)
610#define IRQ_CNS3XXX_DMAC11 (IRQ_TC11MP_GIC_START + 48)
611#define IRQ_CNS3XXX_DMAC12 (IRQ_TC11MP_GIC_START + 49)
612#define IRQ_CNS3XXX_DMAC13 (IRQ_TC11MP_GIC_START + 50)
613#define IRQ_CNS3XXX_DMAC14 (IRQ_TC11MP_GIC_START + 51)
614#define IRQ_CNS3XXX_DMAC15 (IRQ_TC11MP_GIC_START + 52)
615#define IRQ_CNS3XXX_DMAC16 (IRQ_TC11MP_GIC_START + 53)
616#define IRQ_CNS3XXX_DMAC17 (IRQ_TC11MP_GIC_START + 54)
617
618#define IRQ_CNS3XXX_PCIE0_RC (IRQ_TC11MP_GIC_START + 55)
619#define IRQ_CNS3XXX_PCIE1_RC (IRQ_TC11MP_GIC_START + 56)
620#define IRQ_CNS3XXX_TIMER0 (IRQ_TC11MP_GIC_START + 57)
621#define IRQ_CNS3XXX_TIMER1 (IRQ_TC11MP_GIC_START + 58)
622#define IRQ_CNS3XXX_USB_OHCI (IRQ_TC11MP_GIC_START + 59)
623#define IRQ_CNS3XXX_TIMER2 (IRQ_TC11MP_GIC_START + 60)
624#define IRQ_CNS3XXX_EXTERNAL_PIN0 (IRQ_TC11MP_GIC_START + 61)
625#define IRQ_CNS3XXX_EXTERNAL_PIN1 (IRQ_TC11MP_GIC_START + 62)
626#define IRQ_CNS3XXX_EXTERNAL_PIN2 (IRQ_TC11MP_GIC_START + 63)
627
628#define NR_IRQS_CNS3XXX (IRQ_TC11MP_GIC_START + 64)
629
630#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_CNS3XXX)
631#undef NR_IRQS
632#define NR_IRQS NR_IRQS_CNS3XXX
633#endif
634
635#endif /* __MACH_BOARD_CNS3XXX_H */
diff --git a/arch/arm/mach-cns3xxx/include/mach/debug-macro.S b/arch/arm/mach-cns3xxx/include/mach/debug-macro.S
new file mode 100644
index 00000000000..d16ce7eb00e
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/debug-macro.S
@@ -0,0 +1,21 @@
1/*
2 * Debugging macro include header
3 *
4 * Copyright 1994-1999 Russell King
5 * Copyright 2008 Cavium Networks
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This file is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License, Version 2, as
10 * published by the Free Software Foundation.
11 */
12
13 .macro addruart,rx
14 mrc p15, 0, \rx, c1, c0
15 tst \rx, #1 @ MMU enabled?
16 moveq \rx, #0x10000000
17 movne \rx, #0xf0000000 @ virtual base
18 orr \rx, \rx, #0x00009000
19 .endm
20
21#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
new file mode 100644
index 00000000000..5e1c5545680
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
@@ -0,0 +1,82 @@
1/*
2 * Low-level IRQ helper macros for Cavium Networks platforms
3 *
4 * Copyright 2008 Cavium Networks
5 *
6 * This file is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License, Version 2, as
8 * published by the Free Software Foundation.
9 */
10
11#include <mach/hardware.h>
12#include <asm/hardware/gic.h>
13
14 .macro disable_fiq
15 .endm
16
17 .macro get_irqnr_preamble, base, tmp
18 ldr \base, =gic_cpu_base_addr
19 ldr \base, [\base]
20 .endm
21
22 .macro arch_ret_to_user, tmp1, tmp2
23 .endm
24
25 /*
26 * The interrupt numbering scheme is defined in the
27 * interrupt controller spec. To wit:
28 *
29 * Interrupts 0-15 are IPI
30 * 16-28 are reserved
31 * 29-31 are local. We allow 30 to be used for the watchdog.
32 * 32-1020 are global
33 * 1021-1022 are reserved
34 * 1023 is "spurious" (no interrupt)
35 *
36 * For now, we ignore all local interrupts so only return an interrupt if it's
37 * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
38 *
39 * A simple read from the controller will tell us the number of the highest
40 * priority enabled interrupt. We then just need to check whether it is in the
41 * valid range for an IRQ (30-1020 inclusive).
42 */
43
44 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
45
46 ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
47
48 ldr \tmp, =1021
49
50 bic \irqnr, \irqstat, #0x1c00
51
52 cmp \irqnr, #29
53 cmpcc \irqnr, \irqnr
54 cmpne \irqnr, \tmp
55 cmpcs \irqnr, \irqnr
56
57 .endm
58
59 /* We assume that irqstat (the raw value of the IRQ acknowledge
60 * register) is preserved from the macro above.
61 * If there is an IPI, we immediately signal end of interrupt on the
62 * controller, since this requires the original irqstat value which
63 * we won't easily be able to recreate later.
64 */
65
66 .macro test_for_ipi, irqnr, irqstat, base, tmp
67 bic \irqnr, \irqstat, #0x1c00
68 cmp \irqnr, #16
69 strcc \irqstat, [\base, #GIC_CPU_EOI]
70 cmpcs \irqnr, \irqnr
71 .endm
72
73 /* As above, this assumes that irqstat and base are preserved.. */
74
75 .macro test_for_ltirq, irqnr, irqstat, base, tmp
76 bic \irqnr, \irqstat, #0x1c00
77 mov \tmp, #0
78 cmp \irqnr, #29
79 moveq \tmp, #1
80 streq \irqstat, [\base, #GIC_CPU_EOI]
81 cmp \tmp, #0
82 .endm
diff --git a/arch/arm/mach-cns3xxx/include/mach/hardware.h b/arch/arm/mach-cns3xxx/include/mach/hardware.h
new file mode 100644
index 00000000000..57e09836f9d
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/hardware.h
@@ -0,0 +1,22 @@
1/*
2 * This file contains the hardware definitions of the Cavium Networks boards.
3 *
4 * Copyright 2003 ARM Limited.
5 * Copyright 2008 Cavium Networks
6 *
7 * This file is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License, Version 2, as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __MACH_HARDWARE_H
13#define __MACH_HARDWARE_H
14
15#include <asm/sizes.h>
16
17/* macro to get at IO space when running virtually */
18#define PCIBIOS_MIN_IO 0x00000000
19#define PCIBIOS_MIN_MEM 0x00000000
20#define pcibios_assign_all_busses() 1
21
22#endif
diff --git a/arch/arm/mach-cns3xxx/include/mach/io.h b/arch/arm/mach-cns3xxx/include/mach/io.h
new file mode 100644
index 00000000000..33b6fc1ece7
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/io.h
@@ -0,0 +1,17 @@
1/*
2 * Copyright 2008 Cavium Networks
3 * Copyright 2003 ARM Limited
4 *
5 * This file is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License, Version 2, as
7 * published by the Free Software Foundation.
8 */
9#ifndef __MACH_IO_H
10#define __MACH_IO_H
11
12#define IO_SPACE_LIMIT 0xffffffff
13
14#define __io(a) __typesafe_io(a)
15#define __mem_pci(a) (a)
16
17#endif
diff --git a/arch/arm/mach-cns3xxx/include/mach/irqs.h b/arch/arm/mach-cns3xxx/include/mach/irqs.h
new file mode 100644
index 00000000000..2ab96f8085c
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/irqs.h
@@ -0,0 +1,24 @@
1/*
2 * Copyright 2000 Deep Blue Solutions Ltd.
3 * Copyright 2003 ARM Limited
4 * Copyright 2008 Cavium Networks
5 *
6 * This file is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License, Version 2, as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __MACH_IRQS_H
12#define __MACH_IRQS_H
13
14#define IRQ_LOCALTIMER 29
15#define IRQ_LOCALWDOG 30
16#define IRQ_TC11MP_GIC_START 32
17
18#include <mach/cns3xxx.h>
19
20#ifndef NR_IRQS
21#error "NR_IRQS not defined by the board-specific files"
22#endif
23
24#endif
diff --git a/arch/arm/mach-cns3xxx/include/mach/memory.h b/arch/arm/mach-cns3xxx/include/mach/memory.h
new file mode 100644
index 00000000000..3b6b769b7a2
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/memory.h
@@ -0,0 +1,26 @@
1/*
2 * Copyright 2003 ARM Limited
3 * Copyright 2008 Cavium Networks
4 *
5 * This file is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License, Version 2, as
7 * published by the Free Software Foundation.
8 */
9
10#ifndef __MACH_MEMORY_H
11#define __MACH_MEMORY_H
12
13/*
14 * Physical DRAM offset.
15 */
16#define PHYS_OFFSET UL(0x00000000)
17
18#define __phys_to_bus(x) ((x) + PHYS_OFFSET)
19#define __bus_to_phys(x) ((x) - PHYS_OFFSET)
20
21#define __virt_to_bus(v) __phys_to_bus(__virt_to_phys(v))
22#define __bus_to_virt(b) __phys_to_virt(__bus_to_phys(b))
23#define __pfn_to_bus(p) __phys_to_bus(__pfn_to_phys(p))
24#define __bus_to_pfn(b) __phys_to_pfn(__bus_to_phys(b))
25
26#endif
diff --git a/arch/arm/mach-cns3xxx/include/mach/system.h b/arch/arm/mach-cns3xxx/include/mach/system.h
new file mode 100644
index 00000000000..58bb03ae3cf
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/system.h
@@ -0,0 +1,29 @@
1/*
2 * Copyright 2000 Deep Blue Solutions Ltd
3 * Copyright 2003 ARM Limited
4 * Copyright 2008 Cavium Networks
5 *
6 * This file is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License, Version 2, as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __MACH_SYSTEM_H
12#define __MACH_SYSTEM_H
13
14#include <linux/io.h>
15#include <asm/proc-fns.h>
16#include <mach/hardware.h>
17
18static inline void arch_idle(void)
19{
20 /*
21 * This should do all the clock switching
22 * and wait for interrupt tricks
23 */
24 cpu_do_idle();
25}
26
27void arch_reset(char mode, const char *cmd);
28
29#endif
diff --git a/arch/arm/mach-cns3xxx/include/mach/timex.h b/arch/arm/mach-cns3xxx/include/mach/timex.h
new file mode 100644
index 00000000000..1fd04217cac
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/timex.h
@@ -0,0 +1,12 @@
1/*
2 * Cavium Networks architecture timex specifications
3 *
4 * Copyright 2003 ARM Limited
5 * Copyright 2008 Cavium Networks
6 *
7 * This file is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License, Version 2, as
9 * published by the Free Software Foundation.
10 */
11
12#define CLOCK_TICK_RATE (50000000 / 16)
diff --git a/arch/arm/mach-cns3xxx/include/mach/uncompress.h b/arch/arm/mach-cns3xxx/include/mach/uncompress.h
new file mode 100644
index 00000000000..de8ead9b91f
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/uncompress.h
@@ -0,0 +1,55 @@
1/*
2 * Copyright 2003 ARM Limited
3 * Copyright 2008 Cavium Networks
4 *
5 * This file is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License, Version 2, as
7 * published by the Free Software Foundation.
8 */
9
10#include <asm/mach-types.h>
11#include <mach/hardware.h>
12#include <mach/cns3xxx.h>
13
14#define AMBA_UART_DR(base) (*(volatile unsigned char *)((base) + 0x00))
15#define AMBA_UART_LCRH(base) (*(volatile unsigned char *)((base) + 0x2c))
16#define AMBA_UART_CR(base) (*(volatile unsigned char *)((base) + 0x30))
17#define AMBA_UART_FR(base) (*(volatile unsigned char *)((base) + 0x18))
18
19/*
20 * Return the UART base address
21 */
22static inline unsigned long get_uart_base(void)
23{
24 if (machine_is_cns3420vb())
25 return CNS3XXX_UART0_BASE;
26 else
27 return 0;
28}
29
30/*
31 * This does not append a newline
32 */
33static inline void putc(int c)
34{
35 unsigned long base = get_uart_base();
36
37 while (AMBA_UART_FR(base) & (1 << 5))
38 barrier();
39
40 AMBA_UART_DR(base) = c;
41}
42
43static inline void flush(void)
44{
45 unsigned long base = get_uart_base();
46
47 while (AMBA_UART_FR(base) & (1 << 3))
48 barrier();
49}
50
51/*
52 * nothing to do
53 */
54#define arch_decomp_setup()
55#define arch_decomp_wdog()
diff --git a/arch/arm/mach-cns3xxx/include/mach/vmalloc.h b/arch/arm/mach-cns3xxx/include/mach/vmalloc.h
new file mode 100644
index 00000000000..4d381ec0527
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/vmalloc.h
@@ -0,0 +1,11 @@
1/*
2 * Copyright 2000 Russell King.
3 * Copyright 2003 ARM Limited
4 * Copyright 2008 Cavium Networks
5 *
6 * This file is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License, Version 2, as
8 * published by the Free Software Foundation.
9 */
10
11#define VMALLOC_END 0xd8000000
diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c
new file mode 100644
index 00000000000..725e1a4fc23
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/pm.c
@@ -0,0 +1,86 @@
1/*
2 * Copyright 2008 Cavium Networks
3 *
4 * This file is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License, Version 2, as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/delay.h>
10#include <mach/system.h>
11#include <mach/cns3xxx.h>
12
13void cns3xxx_pwr_clk_en(unsigned int block)
14{
15 PM_CLK_GATE_REG |= (block & PM_CLK_GATE_REG_MASK);
16}
17
18void cns3xxx_pwr_power_up(unsigned int block)
19{
20 PM_PLL_HM_PD_CTRL_REG &= ~(block & CNS3XXX_PWR_PLL_ALL);
21
22 /* Wait for 300us for the PLL output clock locked. */
23 udelay(300);
24};
25
26void cns3xxx_pwr_power_down(unsigned int block)
27{
28 /* write '1' to power down */
29 PM_PLL_HM_PD_CTRL_REG |= (block & CNS3XXX_PWR_PLL_ALL);
30};
31
32static void cns3xxx_pwr_soft_rst_force(unsigned int block)
33{
34 /*
35 * bit 0, 28, 29 => program low to reset,
36 * the other else program low and then high
37 */
38 if (block & 0x30000001) {
39 PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK);
40 } else {
41 PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK);
42 PM_SOFT_RST_REG |= (block & PM_SOFT_RST_REG_MASK);
43 }
44}
45
46void cns3xxx_pwr_soft_rst(unsigned int block)
47{
48 static unsigned int soft_reset;
49
50 if (soft_reset & block) {
51 /* SPI/I2C/GPIO use the same block, reset once. */
52 return;
53 } else {
54 soft_reset |= block;
55 }
56 cns3xxx_pwr_soft_rst_force(block);
57}
58
59void arch_reset(char mode, const char *cmd)
60{
61 /*
62 * To reset, we hit the on-board reset register
63 * in the system FPGA.
64 */
65 cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(GLOBAL));
66}
67
68/*
69 * cns3xxx_cpu_clock - return CPU/L2 clock
70 * aclk: cpu clock/2
71 * hclk: cpu clock/4
72 * pclk: cpu clock/8
73 */
74int cns3xxx_cpu_clock(void)
75{
76 int cpu;
77 int cpu_sel;
78 int div_sel;
79
80 cpu_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
81 div_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
82
83 cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel;
84
85 return cpu;
86}
diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig
index b17d52f7cc4..fd4c52b7ccb 100644
--- a/arch/arm/mach-sa1100/Kconfig
+++ b/arch/arm/mach-sa1100/Kconfig
@@ -57,7 +57,7 @@ config SA1100_COLLIE
57config SA1100_H3100 57config SA1100_H3100
58 bool "Compaq iPAQ H3100" 58 bool "Compaq iPAQ H3100"
59 select HTC_EGPIO 59 select HTC_EGPIO
60 select CPU_FREQ_SA1100 60 select CPU_FREQ_SA1110
61 help 61 help
62 Say Y here if you intend to run this kernel on the Compaq iPAQ 62 Say Y here if you intend to run this kernel on the Compaq iPAQ
63 H3100 handheld computer. Information about this machine and the 63 H3100 handheld computer. Information about this machine and the
@@ -68,7 +68,7 @@ config SA1100_H3100
68config SA1100_H3600 68config SA1100_H3600
69 bool "Compaq iPAQ H3600/H3700" 69 bool "Compaq iPAQ H3600/H3700"
70 select HTC_EGPIO 70 select HTC_EGPIO
71 select CPU_FREQ_SA1100 71 select CPU_FREQ_SA1110
72 help 72 help
73 Say Y here if you intend to run this kernel on the Compaq iPAQ 73 Say Y here if you intend to run this kernel on the Compaq iPAQ
74 H3600 handheld computer. Information about this machine and the 74 H3600 handheld computer. Information about this machine and the
diff --git a/arch/arm/mach-sa1100/cpu-sa1110.c b/arch/arm/mach-sa1100/cpu-sa1110.c
index 63b32b68b29..7252874d328 100644
--- a/arch/arm/mach-sa1100/cpu-sa1110.c
+++ b/arch/arm/mach-sa1100/cpu-sa1110.c
@@ -363,6 +363,9 @@ static int __init sa1110_clk_init(void)
363 struct sdram_params *sdram; 363 struct sdram_params *sdram;
364 const char *name = sdram_name; 364 const char *name = sdram_name;
365 365
366 if (!cpu_is_sa1110())
367 return -ENODEV;
368
366 if (!name[0]) { 369 if (!name[0]) {
367 if (machine_is_assabet()) 370 if (machine_is_assabet())
368 name = "TC59SM716-CL3"; 371 name = "TC59SM716-CL3";
diff --git a/arch/arm/plat-pxa/dma.c b/arch/arm/plat-pxa/dma.c
index 742350e0f2a..2d3c19d7c7b 100644
--- a/arch/arm/plat-pxa/dma.c
+++ b/arch/arm/plat-pxa/dma.c
@@ -245,7 +245,7 @@ static void pxa_dma_init_debugfs(void)
245 245
246 dbgfs_chan = kmalloc(sizeof(*dbgfs_state) * num_dma_channels, 246 dbgfs_chan = kmalloc(sizeof(*dbgfs_state) * num_dma_channels,
247 GFP_KERNEL); 247 GFP_KERNEL);
248 if (!dbgfs_state) 248 if (!dbgfs_chan)
249 goto err_alloc; 249 goto err_alloc;
250 250
251 chandir = debugfs_create_dir("channels", dbgfs_root); 251 chandir = debugfs_create_dir("channels", dbgfs_root);
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 1536f1784ca..8f10d24ae62 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -12,7 +12,7 @@
12# 12#
13# http://www.arm.linux.org.uk/developer/machines/?action=new 13# http://www.arm.linux.org.uk/developer/machines/?action=new
14# 14#
15# Last update: Sat Mar 20 15:35:41 2010 15# Last update: Sat May 1 10:36:42 2010
16# 16#
17# machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number 17# machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number
18# 18#
@@ -2749,3 +2749,58 @@ stamp9g45 MACH_STAMP9G45 STAMP9G45 2761
2749h6053 MACH_H6053 H6053 2762 2749h6053 MACH_H6053 H6053 2762
2750smint01 MACH_SMINT01 SMINT01 2763 2750smint01 MACH_SMINT01 SMINT01 2763
2751prtlvt2 MACH_PRTLVT2 PRTLVT2 2764 2751prtlvt2 MACH_PRTLVT2 PRTLVT2 2764
2752ap420 MACH_AP420 AP420 2765
2753htcshift MACH_HTCSHIFT HTCSHIFT 2766
2754davinci_dm365_fc MACH_DAVINCI_DM365_FC DAVINCI_DM365_FC 2767
2755msm8x55_surf MACH_MSM8X55_SURF MSM8X55_SURF 2768
2756msm8x55_ffa MACH_MSM8X55_FFA MSM8X55_FFA 2769
2757esl_vamana MACH_ESL_VAMANA ESL_VAMANA 2770
2758sbc35 MACH_SBC35 SBC35 2771
2759mpx6446 MACH_MPX6446 MPX6446 2772
2760oreo_controller MACH_OREO_CONTROLLER OREO_CONTROLLER 2773
2761kopin_models MACH_KOPIN_MODELS KOPIN_MODELS 2774
2762ttc_vision2 MACH_TTC_VISION2 TTC_VISION2 2775
2763cns3420vb MACH_CNS3420VB CNS3420VB 2776
2764lpc2 MACH_LPC2 LPC2 2777
2765olympus MACH_OLYMPUS OLYMPUS 2778
2766vortex MACH_VORTEX VORTEX 2779
2767s5pc200 MACH_S5PC200 S5PC200 2780
2768ecucore_9263 MACH_ECUCORE_9263 ECUCORE_9263 2781
2769smdkc200 MACH_SMDKC200 SMDKC200 2782
2770emsiso_sx27 MACH_EMSISO_SX27 EMSISO_SX27 2783
2771apx_som9g45_ek MACH_APX_SOM9G45_EK APX_SOM9G45_EK 2784
2772songshan MACH_SONGSHAN SONGSHAN 2785
2773tianshan MACH_TIANSHAN TIANSHAN 2786
2774vpx500 MACH_VPX500 VPX500 2787
2775am3517sam MACH_AM3517SAM AM3517SAM 2788
2776skat91_sim508 MACH_SKAT91_SIM508 SKAT91_SIM508 2789
2777skat91_s3e MACH_SKAT91_S3E SKAT91_S3E 2790
2778omap4_panda MACH_OMAP4_PANDA OMAP4_PANDA 2791
2779df7220 MACH_DF7220 DF7220 2792
2780nemini MACH_NEMINI NEMINI 2793
2781t8200 MACH_T8200 T8200 2794
2782apf51 MACH_APF51 APF51 2795
2783dr_rc_unit MACH_DR_RC_UNIT DR_RC_UNIT 2796
2784bordeaux MACH_BORDEAUX BORDEAUX 2797
2785catania_b MACH_CATANIA_B CATANIA_B 2798
2786mx51_ocean MACH_MX51_OCEAN MX51_OCEAN 2799
2787ti8168evm MACH_TI8168EVM TI8168EVM 2800
2788neocoreomap MACH_NEOCOREOMAP NEOCOREOMAP 2801
2789withings_wbp MACH_WITHINGS_WBP WITHINGS_WBP 2802
2790dbps MACH_DBPS DBPS 2803
2791sbc9261 MACH_SBC9261 SBC9261 2804
2792pcbfp0001 MACH_PCBFP0001 PCBFP0001 2805
2793speedy MACH_SPEEDY SPEEDY 2806
2794chrysaor MACH_CHRYSAOR CHRYSAOR 2807
2795tango MACH_TANGO TANGO 2808
2796synology_dsx11 MACH_SYNOLOGY_DSX11 SYNOLOGY_DSX11 2809
2797hanlin_v3ext MACH_HANLIN_V3EXT HANLIN_V3EXT 2810
2798hanlin_v5 MACH_HANLIN_V5 HANLIN_V5 2811
2799hanlin_v3plus MACH_HANLIN_V3PLUS HANLIN_V3PLUS 2812
2800iriver_story MACH_IRIVER_STORY IRIVER_STORY 2813
2801irex_iliad MACH_IREX_ILIAD IREX_ILIAD 2814
2802irex_dr1000 MACH_IREX_DR1000 IREX_DR1000 2815
2803teton_bga MACH_TETON_BGA TETON_BGA 2816
2804snapper9g45 MACH_SNAPPER9G45 SNAPPER9G45 2817
2805tam3517 MACH_TAM3517 TAM3517 2818
2806pdc100 MACH_PDC100 PDC100 2819
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-14 09:47:32 -0500