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-rw-r--r--arch/m32r/Kconfig26
-rw-r--r--arch/m32r/boot/compressed/head.S5
-rw-r--r--arch/m32r/boot/setup.S9
-rw-r--r--arch/m32r/kernel/Makefile1
-rw-r--r--arch/m32r/kernel/entry.S17
-rw-r--r--arch/m32r/kernel/io_m32104ut.c298
-rw-r--r--arch/m32r/kernel/setup.c7
-rw-r--r--arch/m32r/kernel/setup_m32104ut.c162
-rw-r--r--arch/m32r/kernel/time.c4
-rw-r--r--arch/m32r/m32104ut/defconfig.m32104ut657
-rw-r--r--arch/m32r/mm/cache.c10
-rw-r--r--include/asm-m32r/assembler.h10
-rw-r--r--include/asm-m32r/cacheflush.h2
-rw-r--r--include/asm-m32r/irq.h16
-rw-r--r--include/asm-m32r/m32102.h31
-rw-r--r--include/asm-m32r/m32104ut/m32104ut_pld.h163
-rw-r--r--include/asm-m32r/m32r.h6
-rw-r--r--include/asm-m32r/system.h12
18 files changed, 1407 insertions, 29 deletions
diff --git a/arch/m32r/Kconfig b/arch/m32r/Kconfig
index 4d100f3886e..fae67bbb52f 100644
--- a/arch/m32r/Kconfig
+++ b/arch/m32r/Kconfig
@@ -81,6 +81,12 @@ config PLAT_MAPPI2
81config PLAT_MAPPI3 81config PLAT_MAPPI3
82 bool "Mappi-III(M3A-2170)" 82 bool "Mappi-III(M3A-2170)"
83 83
84config PLAT_M32104UT
85 bool "M32104UT"
86 help
87 The M3T-M32104UT is an reference board based on uT-Engine
88 specification. This board has a M32104 chip.
89
84endchoice 90endchoice
85 91
86choice 92choice
@@ -93,6 +99,10 @@ config CHIP_M32700
93config CHIP_M32102 99config CHIP_M32102
94 bool "M32102" 100 bool "M32102"
95 101
102config CHIP_M32104
103 bool "M32104"
104 depends on PLAT_M32104UT
105
96config CHIP_VDEC2 106config CHIP_VDEC2
97 bool "VDEC2" 107 bool "VDEC2"
98 108
@@ -115,7 +125,7 @@ config TLB_ENTRIES
115 125
116config ISA_M32R 126config ISA_M32R
117 bool 127 bool
118 depends on CHIP_M32102 128 depends on CHIP_M32102 || CHIP_M32104
119 default y 129 default y
120 130
121config ISA_M32R2 131config ISA_M32R2
@@ -140,6 +150,7 @@ config BUS_CLOCK
140 default "50000000" if PLAT_MAPPI3 150 default "50000000" if PLAT_MAPPI3
141 default "50000000" if PLAT_M32700UT 151 default "50000000" if PLAT_M32700UT
142 default "50000000" if PLAT_OPSPUT 152 default "50000000" if PLAT_OPSPUT
153 default "54000000" if PLAT_M32104UT
143 default "33333333" if PLAT_OAKS32R 154 default "33333333" if PLAT_OAKS32R
144 default "20000000" if PLAT_MAPPI2 155 default "20000000" if PLAT_MAPPI2
145 156
@@ -157,6 +168,7 @@ config MEMORY_START
157 default "08000000" if PLAT_USRV 168 default "08000000" if PLAT_USRV
158 default "08000000" if PLAT_M32700UT 169 default "08000000" if PLAT_M32700UT
159 default "08000000" if PLAT_OPSPUT 170 default "08000000" if PLAT_OPSPUT
171 default "04000000" if PLAT_M32104UT
160 default "01000000" if PLAT_OAKS32R 172 default "01000000" if PLAT_OAKS32R
161 173
162config MEMORY_SIZE 174config MEMORY_SIZE
@@ -166,6 +178,7 @@ config MEMORY_SIZE
166 default "02000000" if PLAT_USRV 178 default "02000000" if PLAT_USRV
167 default "01000000" if PLAT_M32700UT 179 default "01000000" if PLAT_M32700UT
168 default "01000000" if PLAT_OPSPUT 180 default "01000000" if PLAT_OPSPUT
181 default "01000000" if PLAT_M32104UT
169 default "00800000" if PLAT_OAKS32R 182 default "00800000" if PLAT_OAKS32R
170 183
171config NOHIGHMEM 184config NOHIGHMEM
@@ -174,21 +187,22 @@ config NOHIGHMEM
174 187
175config ARCH_DISCONTIGMEM_ENABLE 188config ARCH_DISCONTIGMEM_ENABLE
176 bool "Internal RAM Support" 189 bool "Internal RAM Support"
177 depends on CHIP_M32700 || CHIP_M32102 || CHIP_VDEC2 || CHIP_OPSP 190 depends on CHIP_M32700 || CHIP_M32102 || CHIP_VDEC2 || CHIP_OPSP || CHIP_M32104
178 default y 191 default y
179 192
180source "mm/Kconfig" 193source "mm/Kconfig"
181 194
182config IRAM_START 195config IRAM_START
183 hex "Internal memory start address (hex)" 196 hex "Internal memory start address (hex)"
184 default "00f00000" 197 default "00f00000" if !CHIP_M32104
185 depends on (CHIP_M32700 || CHIP_M32102 || CHIP_VDEC2 || CHIP_OPSP) && DISCONTIGMEM 198 default "00700000" if CHIP_M32104
199 depends on (CHIP_M32700 || CHIP_M32102 || CHIP_VDEC2 || CHIP_OPSP || CHIP_M32104) && DISCONTIGMEM
186 200
187config IRAM_SIZE 201config IRAM_SIZE
188 hex "Internal memory size (hex)" 202 hex "Internal memory size (hex)"
189 depends on (CHIP_M32700 || CHIP_M32102 || CHIP_VDEC2 || CHIP_OPSP) && DISCONTIGMEM 203 depends on (CHIP_M32700 || CHIP_M32102 || CHIP_VDEC2 || CHIP_OPSP || CHIP_M32104) && DISCONTIGMEM
190 default "00080000" if CHIP_M32700 204 default "00080000" if CHIP_M32700
191 default "00010000" if CHIP_M32102 || CHIP_OPSP 205 default "00010000" if CHIP_M32102 || CHIP_OPSP || CHIP_M32104
192 default "00008000" if CHIP_VDEC2 206 default "00008000" if CHIP_VDEC2
193 207
194# 208#
diff --git a/arch/m32r/boot/compressed/head.S b/arch/m32r/boot/compressed/head.S
index 07cfd6ad1ae..234d8b1e0ac 100644
--- a/arch/m32r/boot/compressed/head.S
+++ b/arch/m32r/boot/compressed/head.S
@@ -143,6 +143,11 @@ startup:
143 ldi r0, -2 143 ldi r0, -2
144 ldi r1, 0x0100 ; invalidate 144 ldi r1, 0x0100 ; invalidate
145 stb r1, @r0 145 stb r1, @r0
146#elif defined(CONFIG_CHIP_M32104)
147 /* Cache flush */
148 ldi r0, -2
149 ldi r1, 0x0700 ; invalidate i-cache, copy back d-cache
150 sth r1, @r0
146#else 151#else
147#error "put your cache flush function, please" 152#error "put your cache flush function, please"
148#endif 153#endif
diff --git a/arch/m32r/boot/setup.S b/arch/m32r/boot/setup.S
index 5d256434b4a..742669fab8a 100644
--- a/arch/m32r/boot/setup.S
+++ b/arch/m32r/boot/setup.S
@@ -80,6 +80,10 @@ ENTRY(boot)
80 ldi r1, #0x101 ; cache on (with invalidation) 80 ldi r1, #0x101 ; cache on (with invalidation)
81; ldi r1, #0x00 ; cache off 81; ldi r1, #0x00 ; cache off
82 st r1, @r0 82 st r1, @r0
83#elif defined(CONFIG_CHIP_M32104)
84 ldi r0, #-4 ;LDIMM (r0, M32R_MCCR)
85 ldi r1, #0x703 ; cache on (with invalidation)
86 st r1, @r0
83#else 87#else
84#error unknown chip configuration 88#error unknown chip configuration
85#endif 89#endif
@@ -115,10 +119,15 @@ mmu_on:
115 st r1, @(MATM_offset,r0) ; Set MATM (T bit ON) 119 st r1, @(MATM_offset,r0) ; Set MATM (T bit ON)
116 ld r0, @(MATM_offset,r0) ; Check 120 ld r0, @(MATM_offset,r0) ; Check
117#else 121#else
122#if defined(CONFIG_CHIP_M32700)
118 seth r0,#high(M32R_MCDCAR) 123 seth r0,#high(M32R_MCDCAR)
119 or3 r0,r0,#low(M32R_MCDCAR) 124 or3 r0,r0,#low(M32R_MCDCAR)
120 ld24 r1,#0x8080 125 ld24 r1,#0x8080
121 st r1,@r0 126 st r1,@r0
127#elif defined(CONFIG_CHIP_M32104)
128 LDIMM (r2, eit_vector) ; set EVB(cr5)
129 mvtc r2, cr5
130#endif
122#endif /* CONFIG_MMU */ 131#endif /* CONFIG_MMU */
123 jmp r13 132 jmp r13
124 nop 133 nop
diff --git a/arch/m32r/kernel/Makefile b/arch/m32r/kernel/Makefile
index 6c6b6c37663..5a2fa886906 100644
--- a/arch/m32r/kernel/Makefile
+++ b/arch/m32r/kernel/Makefile
@@ -16,5 +16,6 @@ obj-$(CONFIG_PLAT_M32700UT) += setup_m32700ut.o io_m32700ut.o
16obj-$(CONFIG_PLAT_OPSPUT) += setup_opsput.o io_opsput.o 16obj-$(CONFIG_PLAT_OPSPUT) += setup_opsput.o io_opsput.o
17obj-$(CONFIG_MODULES) += module.o 17obj-$(CONFIG_MODULES) += module.o
18obj-$(CONFIG_PLAT_OAKS32R) += setup_oaks32r.o io_oaks32r.o 18obj-$(CONFIG_PLAT_OAKS32R) += setup_oaks32r.o io_oaks32r.o
19obj-$(CONFIG_PLAT_M32104UT) += setup_m32104ut.o io_m32104ut.o
19 20
20EXTRA_AFLAGS := -traditional 21EXTRA_AFLAGS := -traditional
diff --git a/arch/m32r/kernel/entry.S b/arch/m32r/kernel/entry.S
index f6d4a5821a2..3871b65f0c8 100644
--- a/arch/m32r/kernel/entry.S
+++ b/arch/m32r/kernel/entry.S
@@ -315,7 +315,7 @@ ENTRY(ei_handler)
315 mv r1, sp ; arg1(regs) 315 mv r1, sp ; arg1(regs)
316#if defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_XNUX2) \ 316#if defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_XNUX2) \
317 || defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32102) \ 317 || defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32102) \
318 || defined(CONFIG_CHIP_OPSP) 318 || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104)
319 319
320; GET_ICU_STATUS; 320; GET_ICU_STATUS;
321 seth r0, #shigh(M32R_ICU_ISTS_ADDR) 321 seth r0, #shigh(M32R_ICU_ISTS_ADDR)
@@ -541,7 +541,20 @@ check_int2:
541 bra check_end 541 bra check_end
542 .fillinsn 542 .fillinsn
543check_end: 543check_end:
544#endif /* CONFIG_PLAT_OPSPUT */ 544#elif defined(CONFIG_PLAT_M32104UT)
545 add3 r2, r0, #-(M32R_IRQ_INT1) ; INT1# interrupt
546 bnez r2, check_end
547 ; read ICU status register of PLD
548 seth r0, #high(PLD_ICUISTS)
549 or3 r0, r0, #low(PLD_ICUISTS)
550 lduh r0, @r0
551 slli r0, #21
552 srli r0, #27 ; ISN
553 addi r0, #(M32104UT_PLD_IRQ_BASE)
554 bra check_end
555 .fillinsn
556check_end:
557#endif /* CONFIG_PLAT_M32104UT */
545 bl do_IRQ 558 bl do_IRQ
546#endif /* CONFIG_SMP */ 559#endif /* CONFIG_SMP */
547 ld r14, @sp+ 560 ld r14, @sp+
diff --git a/arch/m32r/kernel/io_m32104ut.c b/arch/m32r/kernel/io_m32104ut.c
new file mode 100644
index 00000000000..3df4215f164
--- /dev/null
+++ b/arch/m32r/kernel/io_m32104ut.c
@@ -0,0 +1,298 @@
1/*
2 * linux/arch/m32r/kernel/io_m32104ut.c
3 *
4 * Typical I/O routines for M32104UT board.
5 *
6 * Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
7 * Hitoshi Yamamoto, Mamoru Sakugawa,
8 * Naoto Sugai, Hayato Fujiwara
9 */
10
11#include <linux/config.h>
12#include <asm/m32r.h>
13#include <asm/page.h>
14#include <asm/io.h>
15#include <asm/byteorder.h>
16
17#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
18#include <linux/types.h>
19
20#define M32R_PCC_IOMAP_SIZE 0x1000
21
22#define M32R_PCC_IOSTART0 0x1000
23#define M32R_PCC_IOEND0 (M32R_PCC_IOSTART0 + M32R_PCC_IOMAP_SIZE - 1)
24
25extern void pcc_ioread_byte(int, unsigned long, void *, size_t, size_t, int);
26extern void pcc_ioread_word(int, unsigned long, void *, size_t, size_t, int);
27extern void pcc_iowrite_byte(int, unsigned long, void *, size_t, size_t, int);
28extern void pcc_iowrite_word(int, unsigned long, void *, size_t, size_t, int);
29#endif /* CONFIG_PCMCIA && CONFIG_M32R_CFC */
30
31#define PORT2ADDR(port) _port2addr(port)
32
33static inline void *_port2addr(unsigned long port)
34{
35 return (void *)(port + NONCACHE_OFFSET);
36}
37
38#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
39static inline void *__port2addr_ata(unsigned long port)
40{
41 static int dummy_reg;
42
43 switch (port) {
44 case 0x1f0: return (void *)0xac002000;
45 case 0x1f1: return (void *)0xac012800;
46 case 0x1f2: return (void *)0xac012002;
47 case 0x1f3: return (void *)0xac012802;
48 case 0x1f4: return (void *)0xac012004;
49 case 0x1f5: return (void *)0xac012804;
50 case 0x1f6: return (void *)0xac012006;
51 case 0x1f7: return (void *)0xac012806;
52 case 0x3f6: return (void *)0xac01200e;
53 default: return (void *)&dummy_reg;
54 }
55}
56#endif
57
58/*
59 * M32104T-LAN is located in the extended bus space
60 * from 0x01000000 to 0x01ffffff on physical address.
61 * The base address of LAN controller(LAN91C111) is 0x300.
62 */
63#define LAN_IOSTART 0x300
64#define LAN_IOEND 0x320
65static inline void *_port2addr_ne(unsigned long port)
66{
67 return (void *)(port + NONCACHE_OFFSET + 0x01000000);
68}
69
70static inline void delay(void)
71{
72 __asm__ __volatile__ ("push r0; \n\t pop r0;" : : :"memory");
73}
74
75/*
76 * NIC I/O function
77 */
78
79#define PORT2ADDR_NE(port) _port2addr_ne(port)
80
81static inline unsigned char _ne_inb(void *portp)
82{
83 return *(volatile unsigned char *)portp;
84}
85
86static inline unsigned short _ne_inw(void *portp)
87{
88 return (unsigned short)le16_to_cpu(*(volatile unsigned short *)portp);
89}
90
91static inline void _ne_insb(void *portp, void *addr, unsigned long count)
92{
93 unsigned char *buf = (unsigned char *)addr;
94
95 while (count--)
96 *buf++ = _ne_inb(portp);
97}
98
99static inline void _ne_outb(unsigned char b, void *portp)
100{
101 *(volatile unsigned char *)portp = b;
102}
103
104static inline void _ne_outw(unsigned short w, void *portp)
105{
106 *(volatile unsigned short *)portp = cpu_to_le16(w);
107}
108
109unsigned char _inb(unsigned long port)
110{
111 if (port >= LAN_IOSTART && port < LAN_IOEND)
112 return _ne_inb(PORT2ADDR_NE(port));
113
114 return *(volatile unsigned char *)PORT2ADDR(port);
115}
116
117unsigned short _inw(unsigned long port)
118{
119 if (port >= LAN_IOSTART && port < LAN_IOEND)
120 return _ne_inw(PORT2ADDR_NE(port));
121
122 return *(volatile unsigned short *)PORT2ADDR(port);
123}
124
125unsigned long _inl(unsigned long port)
126{
127 return *(volatile unsigned long *)PORT2ADDR(port);
128}
129
130unsigned char _inb_p(unsigned long port)
131{
132 unsigned char v = _inb(port);
133 delay();
134 return (v);
135}
136
137unsigned short _inw_p(unsigned long port)
138{
139 unsigned short v = _inw(port);
140 delay();
141 return (v);
142}
143
144unsigned long _inl_p(unsigned long port)
145{
146 unsigned long v = _inl(port);
147 delay();
148 return (v);
149}
150
151void _outb(unsigned char b, unsigned long port)
152{
153 if (port >= LAN_IOSTART && port < LAN_IOEND)
154 _ne_outb(b, PORT2ADDR_NE(port));
155 else
156 *(volatile unsigned char *)PORT2ADDR(port) = b;
157}
158
159void _outw(unsigned short w, unsigned long port)
160{
161 if (port >= LAN_IOSTART && port < LAN_IOEND)
162 _ne_outw(w, PORT2ADDR_NE(port));
163 else
164 *(volatile unsigned short *)PORT2ADDR(port) = w;
165}
166
167void _outl(unsigned long l, unsigned long port)
168{
169 *(volatile unsigned long *)PORT2ADDR(port) = l;
170}
171
172void _outb_p(unsigned char b, unsigned long port)
173{
174 _outb(b, port);
175 delay();
176}
177
178void _outw_p(unsigned short w, unsigned long port)
179{
180 _outw(w, port);
181 delay();
182}
183
184void _outl_p(unsigned long l, unsigned long port)
185{
186 _outl(l, port);
187 delay();
188}
189
190void _insb(unsigned int port, void *addr, unsigned long count)
191{
192 if (port >= LAN_IOSTART && port < LAN_IOEND)
193 _ne_insb(PORT2ADDR_NE(port), addr, count);
194 else {
195 unsigned char *buf = addr;
196 unsigned char *portp = PORT2ADDR(port);
197 while (count--)
198 *buf++ = *(volatile unsigned char *)portp;
199 }
200}
201
202void _insw(unsigned int port, void *addr, unsigned long count)
203{
204 unsigned short *buf = addr;
205 unsigned short *portp;
206
207 if (port >= LAN_IOSTART && port < LAN_IOEND) {
208 /*
209 * This portion is only used by smc91111.c to read data
210 * from the DATA_REG. Do not swap the data.
211 */
212 portp = PORT2ADDR_NE(port);
213 while (count--)
214 *buf++ = *(volatile unsigned short *)portp;
215#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
216 } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
217 pcc_ioread_word(9, port, (void *)addr, sizeof(unsigned short),
218 count, 1);
219#endif
220#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
221 } else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
222 portp = __port2addr_ata(port);
223 while (count--)
224 *buf++ = *(volatile unsigned short *)portp;
225#endif
226 } else {
227 portp = PORT2ADDR(port);
228 while (count--)
229 *buf++ = *(volatile unsigned short *)portp;
230 }
231}
232
233void _insl(unsigned int port, void *addr, unsigned long count)
234{
235 unsigned long *buf = addr;
236 unsigned long *portp;
237
238 portp = PORT2ADDR(port);
239 while (count--)
240 *buf++ = *(volatile unsigned long *)portp;
241}
242
243void _outsb(unsigned int port, const void *addr, unsigned long count)
244{
245 const unsigned char *buf = addr;
246 unsigned char *portp;
247
248 if (port >= LAN_IOSTART && port < LAN_IOEND) {
249 portp = PORT2ADDR_NE(port);
250 while (count--)
251 _ne_outb(*buf++, portp);
252 } else {
253 portp = PORT2ADDR(port);
254 while (count--)
255 *(volatile unsigned char *)portp = *buf++;
256 }
257}
258
259void _outsw(unsigned int port, const void *addr, unsigned long count)
260{
261 const unsigned short *buf = addr;
262 unsigned short *portp;
263
264 if (port >= LAN_IOSTART && port < LAN_IOEND) {
265 /*
266 * This portion is only used by smc91111.c to write data
267 * into the DATA_REG. Do not swap the data.
268 */
269 portp = PORT2ADDR_NE(port);
270 while (count--)
271 *(volatile unsigned short *)portp = *buf++;
272#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
273 } else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
274 portp = __port2addr_ata(port);
275 while (count--)
276 *(volatile unsigned short *)portp = *buf++;
277#endif
278#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
279 } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
280 pcc_iowrite_word(9, port, (void *)addr, sizeof(unsigned short),
281 count, 1);
282#endif
283 } else {
284 portp = PORT2ADDR(port);
285 while (count--)
286 *(volatile unsigned short *)portp = *buf++;
287 }
288}
289
290void _outsl(unsigned int port, const void *addr, unsigned long count)
291{
292 const unsigned long *buf = addr;
293 unsigned char *portp;
294
295 portp = PORT2ADDR(port);
296 while (count--)
297 *(volatile unsigned long *)portp = *buf++;
298}
diff --git a/arch/m32r/kernel/setup.c b/arch/m32r/kernel/setup.c
index f722ec8eb02..c2e4dccf011 100644
--- a/arch/m32r/kernel/setup.c
+++ b/arch/m32r/kernel/setup.c
@@ -320,6 +320,9 @@ static int show_cpuinfo(struct seq_file *m, void *v)
320#elif defined(CONFIG_CHIP_MP) 320#elif defined(CONFIG_CHIP_MP)
321 seq_printf(m, "cpu family\t: M32R-MP\n" 321 seq_printf(m, "cpu family\t: M32R-MP\n"
322 "cache size\t: I-xxKB/D-xxKB\n"); 322 "cache size\t: I-xxKB/D-xxKB\n");
323#elif defined(CONFIG_CHIP_M32104)
324 seq_printf(m,"cpu family\t: M32104\n"
325 "cache size\t: I-8KB/D-8KB\n");
323#else 326#else
324 seq_printf(m, "cpu family\t: Unknown\n"); 327 seq_printf(m, "cpu family\t: Unknown\n");
325#endif 328#endif
@@ -340,6 +343,8 @@ static int show_cpuinfo(struct seq_file *m, void *v)
340 seq_printf(m, "Machine\t\t: uServer\n"); 343 seq_printf(m, "Machine\t\t: uServer\n");
341#elif defined(CONFIG_PLAT_OAKS32R) 344#elif defined(CONFIG_PLAT_OAKS32R)
342 seq_printf(m, "Machine\t\t: OAKS32R\n"); 345 seq_printf(m, "Machine\t\t: OAKS32R\n");
346#elif defined(CONFIG_PLAT_M32104UT)
347 seq_printf(m, "Machine\t\t: M3T-M32104UT uT Engine board\n");
343#else 348#else
344 seq_printf(m, "Machine\t\t: Unknown\n"); 349 seq_printf(m, "Machine\t\t: Unknown\n");
345#endif 350#endif
@@ -389,7 +394,7 @@ unsigned long cpu_initialized __initdata = 0;
389 */ 394 */
390#if defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_XNUX2) \ 395#if defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_XNUX2) \
391 || defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32102) \ 396 || defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32102) \
392 || defined(CONFIG_CHIP_OPSP) 397 || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104)
393void __init cpu_init (void) 398void __init cpu_init (void)
394{ 399{
395 int cpu_id = smp_processor_id(); 400 int cpu_id = smp_processor_id();
diff --git a/arch/m32r/kernel/setup_m32104ut.c b/arch/m32r/kernel/setup_m32104ut.c
new file mode 100644
index 00000000000..ab16c664609
--- /dev/null
+++ b/arch/m32r/kernel/setup_m32104ut.c
@@ -0,0 +1,162 @@
1/*
2 * linux/arch/m32r/kernel/setup_m32104ut.c
3 *
4 * Setup routines for M32104UT Board
5 *
6 * Copyright (c) 2002-2005 Hiroyuki Kondo, Hirokazu Takata,
7 * Hitoshi Yamamoto, Mamoru Sakugawa,
8 * Naoto Sugai, Hayato Fujiwara
9 */
10
11#include <linux/config.h>
12#include <linux/irq.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/device.h>
16
17#include <asm/system.h>
18#include <asm/m32r.h>
19#include <asm/io.h>
20
21#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
22
23#ifndef CONFIG_SMP
24typedef struct {
25 unsigned long icucr; /* ICU Control Register */
26} icu_data_t;
27#endif /* CONFIG_SMP */
28
29icu_data_t icu_data[NR_IRQS];
30
31static void disable_m32104ut_irq(unsigned int irq)
32{
33 unsigned long port, data;
34
35 port = irq2port(irq);
36 data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
37 outl(data, port);
38}
39
40static void enable_m32104ut_irq(unsigned int irq)
41{
42 unsigned long port, data;
43
44 port = irq2port(irq);
45 data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
46 outl(data, port);
47}
48
49static void mask_and_ack_m32104ut(unsigned int irq)
50{
51 disable_m32104ut_irq(irq);
52}
53
54static void end_m32104ut_irq(unsigned int irq)
55{
56 enable_m32104ut_irq(irq);
57}
58
59static unsigned int startup_m32104ut_irq(unsigned int irq)
60{
61 enable_m32104ut_irq(irq);
62 return (0);
63}
64
65static void shutdown_m32104ut_irq(unsigned int irq)
66{
67 unsigned long port;
68
69 port = irq2port(irq);
70 outl(M32R_ICUCR_ILEVEL7, port);
71}
72
73static struct hw_interrupt_type m32104ut_irq_type =
74{
75 .typename = "M32104UT-IRQ",
76 .startup = startup_m32104ut_irq,
77 .shutdown = shutdown_m32104ut_irq,
78 .enable = enable_m32104ut_irq,
79 .disable = disable_m32104ut_irq,
80 .ack = mask_and_ack_m32104ut,
81 .end = end_m32104ut_irq
82};
83
84void __init init_IRQ(void)
85{
86 static int once = 0;
87
88 if (once)
89 return;
90 else
91 once++;
92
93#if defined(CONFIG_SMC91X)
94 /* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/
95 irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED;
96 irq_desc[M32R_IRQ_INT0].handler = &m32104ut_irq_type;
97 irq_desc[M32R_IRQ_INT0].action = 0;
98 irq_desc[M32R_IRQ_INT0].depth = 1;
99 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11; /* "H" level sense */
100 disable_m32104ut_irq(M32R_IRQ_INT0);
101#endif /* CONFIG_SMC91X */
102
103 /* MFT2 : system timer */
104 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
105 irq_desc[M32R_IRQ_MFT2].handler = &m32104ut_irq_type;
106 irq_desc[M32R_IRQ_MFT2].action = 0;
107 irq_desc[M32R_IRQ_MFT2].depth = 1;
108 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
109 disable_m32104ut_irq(M32R_IRQ_MFT2);
110
111#ifdef CONFIG_SERIAL_M32R_SIO
112 /* SIO0_R : uart receive data */
113 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
114 irq_desc[M32R_IRQ_SIO0_R].handler = &m32104ut_irq_type;
115 irq_desc[M32R_IRQ_SIO0_R].action = 0;
116 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
117 icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN;
118 disable_m32104ut_irq(M32R_IRQ_SIO0_R);
119
120 /* SIO0_S : uart send data */
121 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
122 irq_desc[M32R_IRQ_SIO0_S].handler = &m32104ut_irq_type;
123 irq_desc[M32R_IRQ_SIO0_S].action = 0;
124 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
125 icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN;
126 disable_m32104ut_irq(M32R_IRQ_SIO0_S);
127#endif /* CONFIG_SERIAL_M32R_SIO */
128}
129
130#if defined(CONFIG_SMC91X)
131
132#define LAN_IOSTART 0x300
133#define LAN_IOEND 0x320
134static struct resource smc91x_resources[] = {
135 [0] = {
136 .start = (LAN_IOSTART),
137 .end = (LAN_IOEND),
138 .flags = IORESOURCE_MEM,
139 },
140 [1] = {
141 .start = M32R_IRQ_INT0,
142 .end = M32R_IRQ_INT0,
143 .flags = IORESOURCE_IRQ,
144 }
145};
146
147static struct platform_device smc91x_device = {
148 .name = "smc91x",
149 .id = 0,
150 .num_resources = ARRAY_SIZE(smc91x_resources),
151 .resource = smc91x_resources,
152};
153#endif
154
155static int __init platform_init(void)
156{
157#if defined(CONFIG_SMC91X)
158 platform_device_register(&smc91x_device);
159#endif
160 return 0;
161}
162arch_initcall(platform_init);
diff --git a/arch/m32r/kernel/time.c b/arch/m32r/kernel/time.c
index 2ebce2063fe..b8e68b54230 100644
--- a/arch/m32r/kernel/time.c
+++ b/arch/m32r/kernel/time.c
@@ -57,7 +57,7 @@ static unsigned long do_gettimeoffset(void)
57 57
58#if defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_XNUX2) \ 58#if defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_XNUX2) \
59 || defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_M32700) \ 59 || defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_M32700) \
60 || defined(CONFIG_CHIP_OPSP) 60 || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104)
61#ifndef CONFIG_SMP 61#ifndef CONFIG_SMP
62 62
63 unsigned long count; 63 unsigned long count;
@@ -268,7 +268,7 @@ void __init time_init(void)
268 268
269#if defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_XNUX2) \ 269#if defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_XNUX2) \
270 || defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_M32700) \ 270 || defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_M32700) \
271 || defined(CONFIG_CHIP_OPSP) 271 || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104)
272 272
273 /* M32102 MFT setup */ 273 /* M32102 MFT setup */
274 setup_irq(M32R_IRQ_MFT2, &irq0); 274 setup_irq(M32R_IRQ_MFT2, &irq0);
diff --git a/arch/m32r/m32104ut/defconfig.m32104ut b/arch/m32r/m32104ut/defconfig.m32104ut
new file mode 100644
index 00000000000..454de336803
--- /dev/null
+++ b/arch/m32r/m32104ut/defconfig.m32104ut
@@ -0,0 +1,657 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.14
4# Wed Nov 9 16:04:51 2005
5#
6CONFIG_M32R=y
7# CONFIG_UID16 is not set
8CONFIG_GENERIC_ISA_DMA=y
9CONFIG_GENERIC_HARDIRQS=y
10CONFIG_GENERIC_IRQ_PROBE=y
11
12#
13# Code maturity level options
14#
15CONFIG_EXPERIMENTAL=y
16CONFIG_CLEAN_COMPILE=y
17CONFIG_BROKEN_ON_SMP=y
18CONFIG_INIT_ENV_ARG_LIMIT=32
19
20#
21# General setup
22#
23CONFIG_LOCALVERSION=""
24CONFIG_LOCALVERSION_AUTO=y
25# CONFIG_POSIX_MQUEUE is not set
26# CONFIG_BSD_PROCESS_ACCT is not set
27CONFIG_SYSCTL=y
28# CONFIG_AUDIT is not set
29CONFIG_HOTPLUG=y
30# CONFIG_KOBJECT_UEVENT is not set
31# CONFIG_IKCONFIG is not set
32CONFIG_INITRAMFS_SOURCE=""
33CONFIG_EMBEDDED=y
34# CONFIG_KALLSYMS is not set
35CONFIG_PRINTK=y
36CONFIG_BUG=y
37CONFIG_BASE_FULL=y
38# CONFIG_FUTEX is not set
39# CONFIG_EPOLL is not set
40# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
41CONFIG_CC_ALIGN_FUNCTIONS=0
42CONFIG_CC_ALIGN_LABELS=0
43CONFIG_CC_ALIGN_LOOPS=0
44CONFIG_CC_ALIGN_JUMPS=0
45CONFIG_TINY_SHMEM=y
46CONFIG_BASE_SMALL=0
47
48#
49# Loadable module support
50#
51# CONFIG_MODULES is not set
52
53#
54# Processor type and features
55#
56# CONFIG_PLAT_MAPPI is not set
57# CONFIG_PLAT_USRV is not set
58# CONFIG_PLAT_M32700UT is not set
59# CONFIG_PLAT_OPSPUT is not set
60# CONFIG_PLAT_OAKS32R is not set
61# CONFIG_PLAT_MAPPI2 is not set
62# CONFIG_PLAT_MAPPI3 is not set
63CONFIG_PLAT_M32104UT=y
64# CONFIG_CHIP_M32700 is not set
65# CONFIG_CHIP_M32102 is not set
66CONFIG_CHIP_M32104=y
67# CONFIG_CHIP_VDEC2 is not set
68# CONFIG_CHIP_OPSP is not set
69CONFIG_ISA_M32R=y
70CONFIG_BUS_CLOCK=54000000
71CONFIG_TIMER_DIVIDE=128
72# CONFIG_CPU_LITTLE_ENDIAN is not set
73CONFIG_MEMORY_START=04000000
74CONFIG_MEMORY_SIZE=01000000
75CONFIG_NOHIGHMEM=y
76# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
77CONFIG_SELECT_MEMORY_MODEL=y
78CONFIG_FLATMEM_MANUAL=y
79# CONFIG_DISCONTIGMEM_MANUAL is not set
80# CONFIG_SPARSEMEM_MANUAL is not set
81CONFIG_FLATMEM=y
82CONFIG_FLAT_NODE_MEM_MAP=y
83# CONFIG_SPARSEMEM_STATIC is not set
84CONFIG_RWSEM_GENERIC_SPINLOCK=y
85# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
86CONFIG_GENERIC_CALIBRATE_DELAY=y
87# CONFIG_PREEMPT is not set
88# CONFIG_SMP is not set
89
90#
91# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
92#
93# CONFIG_ISA is not set
94
95#
96# PCCARD (PCMCIA/CardBus) support
97#
98CONFIG_PCCARD=y
99# CONFIG_PCMCIA_DEBUG is not set
100CONFIG_PCMCIA=y
101CONFIG_PCMCIA_LOAD_CIS=y
102CONFIG_PCMCIA_IOCTL=y
103
104#
105# PC-card bridges
106#
107
108#
109# PCI Hotplug Support
110#
111
112#
113# Executable file formats
114#
115CONFIG_BINFMT_FLAT=y
116# CONFIG_BINFMT_ZFLAT is not set
117# CONFIG_BINFMT_SHARED_FLAT is not set
118# CONFIG_BINFMT_MISC is not set
119
120#
121# Networking
122#
123CONFIG_NET=y
124
125#
126# Networking options
127#
128# CONFIG_PACKET is not set
129CONFIG_UNIX=y
130# CONFIG_NET_KEY is not set
131CONFIG_INET=y
132# CONFIG_IP_MULTICAST is not set
133# CONFIG_IP_ADVANCED_ROUTER is not set
134CONFIG_IP_FIB_HASH=y
135CONFIG_IP_PNP=y
136CONFIG_IP_PNP_DHCP=y
137# CONFIG_IP_PNP_BOOTP is not set
138# CONFIG_IP_PNP_RARP is not set
139# CONFIG_NET_IPIP is not set
140# CONFIG_NET_IPGRE is not set
141# CONFIG_ARPD is not set
142# CONFIG_SYN_COOKIES is not set
143# CONFIG_INET_AH is not set
144# CONFIG_INET_ESP is not set
145# CONFIG_INET_IPCOMP is not set
146# CONFIG_INET_TUNNEL is not set
147CONFIG_INET_DIAG=y
148CONFIG_INET_TCP_DIAG=y
149# CONFIG_TCP_CONG_ADVANCED is not set
150CONFIG_TCP_CONG_BIC=y
151# CONFIG_IPV6 is not set
152# CONFIG_NETFILTER is not set
153
154#
155# DCCP Configuration (EXPERIMENTAL)
156#
157# CONFIG_IP_DCCP is not set
158
159#
160# SCTP Configuration (EXPERIMENTAL)
161#
162# CONFIG_IP_SCTP is not set
163# CONFIG_ATM is not set
164# CONFIG_BRIDGE is not set
165# CONFIG_VLAN_8021Q is not set
166# CONFIG_DECNET is not set
167# CONFIG_LLC2 is not set
168# CONFIG_IPX is not set
169# CONFIG_ATALK is not set
170# CONFIG_X25 is not set
171# CONFIG_LAPB is not set
172# CONFIG_NET_DIVERT is not set
173# CONFIG_ECONET is not set
174# CONFIG_WAN_ROUTER is not set
175# CONFIG_NET_SCHED is not set
176# CONFIG_NET_CLS_ROUTE is not set
177
178#
179# Network testing
180#
181# CONFIG_NET_PKTGEN is not set
182# CONFIG_HAMRADIO is not set
183# CONFIG_IRDA is not set
184# CONFIG_BT is not set
185# CONFIG_IEEE80211 is not set
186
187#
188# Device Drivers
189#
190
191#
192# Generic Driver Options
193#
194CONFIG_STANDALONE=y
195CONFIG_PREVENT_FIRMWARE_BUILD=y
196CONFIG_FW_LOADER=y
197# CONFIG_DEBUG_DRIVER is not set
198
199#
200# Connector - unified userspace <-> kernelspace linker
201#
202# CONFIG_CONNECTOR is not set
203
204#
205# Memory Technology Devices (MTD)
206#
207# CONFIG_MTD is not set
208
209#
210# Parallel port support
211#
212# CONFIG_PARPORT is not set
213
214#
215# Plug and Play support
216#
217
218#
219# Block devices
220#
221# CONFIG_BLK_DEV_COW_COMMON is not set
222CONFIG_BLK_DEV_LOOP=y
223# CONFIG_BLK_DEV_CRYPTOLOOP is not set
224CONFIG_BLK_DEV_NBD=y
225CONFIG_BLK_DEV_RAM=y
226CONFIG_BLK_DEV_RAM_COUNT=16
227CONFIG_BLK_DEV_RAM_SIZE=4096
228CONFIG_BLK_DEV_INITRD=y
229# CONFIG_CDROM_PKTCDVD is not set
230
231#
232# IO Schedulers
233#
234CONFIG_IOSCHED_NOOP=y
235# CONFIG_IOSCHED_AS is not set
236# CONFIG_IOSCHED_DEADLINE is not set
237# CONFIG_IOSCHED_CFQ is not set
238# CONFIG_ATA_OVER_ETH is not set
239
240#
241# ATA/ATAPI/MFM/RLL support
242#
243# CONFIG_IDE is not set
244
245#
246# SCSI device support
247#
248# CONFIG_RAID_ATTRS is not set
249# CONFIG_SCSI is not set
250
251#
252# Multi-device support (RAID and LVM)
253#
254# CONFIG_MD is not set
255
256#
257# Fusion MPT device support
258#
259# CONFIG_FUSION is not set
260
261#
262# IEEE 1394 (FireWire) support
263#
264
265#
266# I2O device support
267#
268
269#
270# Network device support
271#
272CONFIG_NETDEVICES=y
273CONFIG_DUMMY=y
274# CONFIG_BONDING is not set
275# CONFIG_EQUALIZER is not set
276# CONFIG_TUN is not set
277
278#
279# PHY device support
280#
281# CONFIG_PHYLIB is not set
282
283#
284# Ethernet (10 or 100Mbit)
285#
286CONFIG_NET_ETHERNET=y
287CONFIG_MII=y
288CONFIG_SMC91X=y
289# CONFIG_NE2000 is not set
290
291#
292# Ethernet (1000 Mbit)
293#
294
295#
296# Ethernet (10000 Mbit)
297#
298
299#
300# Token Ring devices
301#
302
303#
304# Wireless LAN (non-hamradio)
305#
306# CONFIG_NET_RADIO is not set
307
308#
309# PCMCIA network device support
310#
311# CONFIG_NET_PCMCIA is not set
312
313#
314# Wan interfaces
315#
316# CONFIG_WAN is not set
317# CONFIG_PPP is not set
318# CONFIG_SLIP is not set
319# CONFIG_SHAPER is not set
320# CONFIG_NETCONSOLE is not set
321# CONFIG_NETPOLL is not set
322# CONFIG_NET_POLL_CONTROLLER is not set
323
324#
325# ISDN subsystem
326#
327# CONFIG_ISDN is not set
328
329#
330# Telephony Support
331#
332# CONFIG_PHONE is not set
333
334#
335# Input device support
336#
337# CONFIG_INPUT is not set
338
339#
340# Hardware I/O ports
341#
342# CONFIG_SERIO is not set
343# CONFIG_GAMEPORT is not set
344
345#
346# Character devices
347#
348# CONFIG_VT is not set
349# CONFIG_SERIAL_NONSTANDARD is not set
350
351#
352# Serial drivers
353#
354# CONFIG_SERIAL_8250 is not set
355
356#
357# Non-8250 serial port support
358#
359CONFIG_SERIAL_CORE=y
360CONFIG_SERIAL_CORE_CONSOLE=y
361CONFIG_SERIAL_M32R_SIO=y
362CONFIG_SERIAL_M32R_SIO_CONSOLE=y
363CONFIG_UNIX98_PTYS=y
364CONFIG_LEGACY_PTYS=y
365CONFIG_LEGACY_PTY_COUNT=256
366
367#
368# IPMI
369#
370# CONFIG_IPMI_HANDLER is not set
371
372#
373# Watchdog Cards
374#
375CONFIG_WATCHDOG=y
376# CONFIG_WATCHDOG_NOWAYOUT is not set
377
378#
379# Watchdog Device Drivers
380#
381CONFIG_SOFT_WATCHDOG=y
382# CONFIG_RTC is not set
383# CONFIG_DTLK is not set
384# CONFIG_R3964 is not set
385
386#
387# Ftape, the floppy tape device driver
388#
389
390#
391# PCMCIA character devices
392#
393# CONFIG_SYNCLINK_CS is not set
394# CONFIG_RAW_DRIVER is not set
395
396#
397# TPM devices
398#
399
400#
401# I2C support
402#
403# CONFIG_I2C is not set
404
405#
406# Dallas's 1-wire bus
407#
408# CONFIG_W1 is not set
409
410#
411# Hardware Monitoring support
412#
413# CONFIG_HWMON is not set
414# CONFIG_HWMON_VID is not set
415
416#
417# Misc devices
418#
419
420#
421# Multimedia Capabilities Port drivers
422#
423
424#
425# Multimedia devices
426#
427# CONFIG_VIDEO_DEV is not set
428
429#
430# Digital Video Broadcasting Devices
431#
432# CONFIG_DVB is not set
433
434#
435# Graphics support
436#
437# CONFIG_FB is not set
438
439#
440# Sound
441#
442# CONFIG_SOUND is not set
443
444#
445# USB support
446#
447# CONFIG_USB_ARCH_HAS_HCD is not set
448# CONFIG_USB_ARCH_HAS_OHCI is not set
449
450#
451# USB Gadget Support
452#
453# CONFIG_USB_GADGET is not set
454
455#
456# MMC/SD Card support
457#
458# CONFIG_MMC is not set
459
460#
461# InfiniBand support
462#
463
464#
465# SN Devices
466#
467
468#
469# File systems
470#
471CONFIG_EXT2_FS=y
472# CONFIG_EXT2_FS_XATTR is not set
473# CONFIG_EXT2_FS_XIP is not set
474CONFIG_EXT3_FS=y
475CONFIG_EXT3_FS_XATTR=y
476CONFIG_EXT3_FS_POSIX_ACL=y
477# CONFIG_EXT3_FS_SECURITY is not set
478CONFIG_JBD=y
479# CONFIG_JBD_DEBUG is not set
480CONFIG_FS_MBCACHE=y
481# CONFIG_REISERFS_FS is not set
482# CONFIG_JFS_FS is not set
483CONFIG_FS_POSIX_ACL=y
484# CONFIG_XFS_FS is not set
485# CONFIG_MINIX_FS is not set
486# CONFIG_ROMFS_FS is not set
487# CONFIG_INOTIFY is not set
488# CONFIG_QUOTA is not set
489CONFIG_DNOTIFY=y
490# CONFIG_AUTOFS_FS is not set
491# CONFIG_AUTOFS4_FS is not set
492# CONFIG_FUSE_FS is not set
493
494#
495# CD-ROM/DVD Filesystems
496#
497# CONFIG_ISO9660_FS is not set
498# CONFIG_UDF_FS is not set
499
500#
501# DOS/FAT/NT Filesystems
502#
503CONFIG_FAT_FS=y
504CONFIG_MSDOS_FS=y
505CONFIG_VFAT_FS=y
506CONFIG_FAT_DEFAULT_CODEPAGE=932
507CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
508# CONFIG_NTFS_FS is not set
509
510#
511# Pseudo filesystems
512#
513CONFIG_PROC_FS=y
514CONFIG_SYSFS=y
515CONFIG_TMPFS=y
516# CONFIG_HUGETLB_PAGE is not set
517CONFIG_RAMFS=y
518# CONFIG_RELAYFS_FS is not set
519
520#
521# Miscellaneous filesystems
522#
523# CONFIG_ADFS_FS is not set
524# CONFIG_AFFS_FS is not set
525# CONFIG_HFS_FS is not set
526# CONFIG_HFSPLUS_FS is not set
527# CONFIG_BEFS_FS is not set
528# CONFIG_BFS_FS is not set
529# CONFIG_EFS_FS is not set
530CONFIG_CRAMFS=y
531# CONFIG_VXFS_FS is not set
532# CONFIG_HPFS_FS is not set
533# CONFIG_QNX4FS_FS is not set
534# CONFIG_SYSV_FS is not set
535# CONFIG_UFS_FS is not set
536
537#
538# Network File Systems
539#
540CONFIG_NFS_FS=y
541CONFIG_NFS_V3=y
542# CONFIG_NFS_V3_ACL is not set
543# CONFIG_NFS_V4 is not set
544# CONFIG_NFS_DIRECTIO is not set
545# CONFIG_NFSD is not set
546CONFIG_ROOT_NFS=y
547CONFIG_LOCKD=y
548CONFIG_LOCKD_V4=y
549CONFIG_NFS_COMMON=y
550CONFIG_SUNRPC=y
551# CONFIG_RPCSEC_GSS_KRB5 is not set
552# CONFIG_RPCSEC_GSS_SPKM3 is not set
553# CONFIG_SMB_FS is not set
554# CONFIG_CIFS is not set
555# CONFIG_NCP_FS is not set
556# CONFIG_CODA_FS is not set
557# CONFIG_AFS_FS is not set
558# CONFIG_9P_FS is not set
559
560#
561# Partition Types
562#
563# CONFIG_PARTITION_ADVANCED is not set
564CONFIG_MSDOS_PARTITION=y
565
566#
567# Native Language Support
568#
569CONFIG_NLS=y
570CONFIG_NLS_DEFAULT="iso8859-1"
571CONFIG_NLS_CODEPAGE_437=y
572# CONFIG_NLS_CODEPAGE_737 is not set
573# CONFIG_NLS_CODEPAGE_775 is not set
574# CONFIG_NLS_CODEPAGE_850 is not set
575# CONFIG_NLS_CODEPAGE_852 is not set
576# CONFIG_NLS_CODEPAGE_855 is not set
577# CONFIG_NLS_CODEPAGE_857 is not set
578# CONFIG_NLS_CODEPAGE_860 is not set
579# CONFIG_NLS_CODEPAGE_861 is not set
580# CONFIG_NLS_CODEPAGE_862 is not set
581# CONFIG_NLS_CODEPAGE_863 is not set
582# CONFIG_NLS_CODEPAGE_864 is not set
583# CONFIG_NLS_CODEPAGE_865 is not set
584# CONFIG_NLS_CODEPAGE_866 is not set
585# CONFIG_NLS_CODEPAGE_869 is not set
586# CONFIG_NLS_CODEPAGE_936 is not set
587# CONFIG_NLS_CODEPAGE_950 is not set
588CONFIG_NLS_CODEPAGE_932=y
589# CONFIG_NLS_CODEPAGE_949 is not set
590# CONFIG_NLS_CODEPAGE_874 is not set
591# CONFIG_NLS_ISO8859_8 is not set
592# CONFIG_NLS_CODEPAGE_1250 is not set
593# CONFIG_NLS_CODEPAGE_1251 is not set
594# CONFIG_NLS_ASCII is not set
595# CONFIG_NLS_ISO8859_1 is not set
596# CONFIG_NLS_ISO8859_2 is not set
597# CONFIG_NLS_ISO8859_3 is not set
598# CONFIG_NLS_ISO8859_4 is not set
599# CONFIG_NLS_ISO8859_5 is not set
600# CONFIG_NLS_ISO8859_6 is not set
601# CONFIG_NLS_ISO8859_7 is not set
602# CONFIG_NLS_ISO8859_9 is not set
603# CONFIG_NLS_ISO8859_13 is not set
604# CONFIG_NLS_ISO8859_14 is not set
605# CONFIG_NLS_ISO8859_15 is not set
606# CONFIG_NLS_KOI8_R is not set
607# CONFIG_NLS_KOI8_U is not set
608CONFIG_NLS_UTF8=y
609
610#
611# Profiling support
612#
613# CONFIG_PROFILING is not set
614
615#
616# Kernel hacking
617#
618# CONFIG_PRINTK_TIME is not set
619CONFIG_DEBUG_KERNEL=y
620CONFIG_MAGIC_SYSRQ=y
621CONFIG_LOG_BUF_SHIFT=14
622CONFIG_DETECT_SOFTLOCKUP=y
623# CONFIG_SCHEDSTATS is not set
624# CONFIG_DEBUG_SLAB is not set
625# CONFIG_DEBUG_SPINLOCK is not set
626# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
627# CONFIG_DEBUG_KOBJECT is not set
628# CONFIG_DEBUG_BUGVERBOSE is not set
629CONFIG_DEBUG_INFO=y
630# CONFIG_DEBUG_FS is not set
631# CONFIG_FRAME_POINTER is not set
632# CONFIG_DEBUG_STACKOVERFLOW is not set
633# CONFIG_DEBUG_STACK_USAGE is not set
634
635#
636# Security options
637#
638# CONFIG_KEYS is not set
639# CONFIG_SECURITY is not set
640
641#
642# Cryptographic options
643#
644# CONFIG_CRYPTO is not set
645
646#
647# Hardware crypto devices
648#
649
650#
651# Library routines
652#
653# CONFIG_CRC_CCITT is not set
654# CONFIG_CRC16 is not set
655CONFIG_CRC32=y
656CONFIG_LIBCRC32C=y
657CONFIG_ZLIB_INFLATE=y
diff --git a/arch/m32r/mm/cache.c b/arch/m32r/mm/cache.c
index 31b0789c199..c6f72a64ae1 100644
--- a/arch/m32r/mm/cache.c
+++ b/arch/m32r/mm/cache.c
@@ -26,6 +26,16 @@
26#define MCCR ((volatile unsigned char*)0xfffffffe) 26#define MCCR ((volatile unsigned char*)0xfffffffe)
27#define MCCR_IIV (1UL << 0) /* I-cache invalidate */ 27#define MCCR_IIV (1UL << 0) /* I-cache invalidate */
28#define MCCR_ICACHE_INV MCCR_IIV 28#define MCCR_ICACHE_INV MCCR_IIV
29#elif defined(CONFIG_CHIP_M32104)
30#define MCCR ((volatile unsigned long*)0xfffffffc)
31#define MCCR_IIV (1UL << 8) /* I-cache invalidate */
32#define MCCR_DIV (1UL << 9) /* D-cache invalidate */
33#define MCCR_DCB (1UL << 10) /* D-cache copy back */
34#define MCCR_ICM (1UL << 0) /* I-cache mode [0:off,1:on] */
35#define MCCR_DCM (1UL << 1) /* D-cache mode [0:off,1:on] */
36#define MCCR_ICACHE_INV MCCR_IIV
37#define MCCR_DCACHE_CB MCCR_DCB
38#define MCCR_DCACHE_CBINV (MCCR_DIV|MCCR_DCB)
29#endif /* CONFIG_CHIP_XNUX2 || CONFIG_CHIP_M32700 */ 39#endif /* CONFIG_CHIP_XNUX2 || CONFIG_CHIP_M32700 */
30 40
31#ifndef MCCR 41#ifndef MCCR
diff --git a/include/asm-m32r/assembler.h b/include/asm-m32r/assembler.h
index e1dff9d6baa..b7f4d8aaeb4 100644
--- a/include/asm-m32r/assembler.h
+++ b/include/asm-m32r/assembler.h
@@ -52,7 +52,7 @@
52 or3 \reg, \reg, #low(\x) 52 or3 \reg, \reg, #low(\x)
53 .endm 53 .endm
54 54
55#if !defined(CONFIG_CHIP_M32102) 55#if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104))
56#define STI(reg) STI_M reg 56#define STI(reg) STI_M reg
57 .macro STI_M reg 57 .macro STI_M reg
58 setpsw #0x40 -> nop 58 setpsw #0x40 -> nop
@@ -64,7 +64,7 @@
64 clrpsw #0x40 -> nop 64 clrpsw #0x40 -> nop
65 ; WORKAROUND: "-> nop" is a workaround for the M32700(TS1). 65 ; WORKAROUND: "-> nop" is a workaround for the M32700(TS1).
66 .endm 66 .endm
67#else /* CONFIG_CHIP_M32102 */ 67#else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
68#define STI(reg) STI_M reg 68#define STI(reg) STI_M reg
69 .macro STI_M reg 69 .macro STI_M reg
70 mvfc \reg, psw 70 mvfc \reg, psw
@@ -191,12 +191,12 @@
191 and \reg, sp 191 and \reg, sp
192 .endm 192 .endm
193 193
194#if !defined(CONFIG_CHIP_M32102) 194#if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104))
195 .macro SWITCH_TO_KERNEL_STACK 195 .macro SWITCH_TO_KERNEL_STACK
196 ; switch to kernel stack (spi) 196 ; switch to kernel stack (spi)
197 clrpsw #0x80 -> nop 197 clrpsw #0x80 -> nop
198 .endm 198 .endm
199#else /* CONFIG_CHIP_M32102 */ 199#else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
200 .macro SWITCH_TO_KERNEL_STACK 200 .macro SWITCH_TO_KERNEL_STACK
201 push r0 ; save r0 for working 201 push r0 ; save r0 for working
202 mvfc r0, psw 202 mvfc r0, psw
@@ -218,7 +218,7 @@
218 .fillinsn 218 .fillinsn
2192: 2192:
220 .endm 220 .endm
221#endif /* CONFIG_CHIP_M32102 */ 221#endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
222 222
223#endif /* __ASSEMBLY__ */ 223#endif /* __ASSEMBLY__ */
224 224
diff --git a/include/asm-m32r/cacheflush.h b/include/asm-m32r/cacheflush.h
index 46fc4c32510..e57427b6e24 100644
--- a/include/asm-m32r/cacheflush.h
+++ b/include/asm-m32r/cacheflush.h
@@ -7,7 +7,7 @@
7extern void _flush_cache_all(void); 7extern void _flush_cache_all(void);
8extern void _flush_cache_copyback_all(void); 8extern void _flush_cache_copyback_all(void);
9 9
10#if defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_OPSP) 10#if defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104)
11#define flush_cache_all() do { } while (0) 11#define flush_cache_all() do { } while (0)
12#define flush_cache_mm(mm) do { } while (0) 12#define flush_cache_mm(mm) do { } while (0)
13#define flush_cache_range(vma, start, end) do { } while (0) 13#define flush_cache_range(vma, start, end) do { } while (0)
diff --git a/include/asm-m32r/irq.h b/include/asm-m32r/irq.h
index 8ed77968ecb..ca943954572 100644
--- a/include/asm-m32r/irq.h
+++ b/include/asm-m32r/irq.h
@@ -65,6 +65,22 @@
65#define NR_IRQS \ 65#define NR_IRQS \
66 (OPSPUT_NUM_CPU_IRQ + OPSPUT_NUM_PLD_IRQ \ 66 (OPSPUT_NUM_CPU_IRQ + OPSPUT_NUM_PLD_IRQ \
67 + OPSPUT_NUM_LCD_PLD_IRQ + OPSPUT_NUM_LAN_PLD_IRQ) 67 + OPSPUT_NUM_LCD_PLD_IRQ + OPSPUT_NUM_LAN_PLD_IRQ)
68
69#elif defined(CONFIG_PLAT_M32104UT)
70/*
71 * IRQ definitions for M32104UT
72 * M32104 Chip: 64 interrupts
73 * ICU of M32104UT-on-board PLD: 32 interrupts cascaded to INT1# chip pin
74 */
75#define M32104UT_NUM_CPU_IRQ (64)
76#define M32104UT_NUM_PLD_IRQ (32)
77#define M32104UT_IRQ_BASE 0
78#define M32104UT_CPU_IRQ_BASE M32104UT_IRQ_BASE
79#define M32104UT_PLD_IRQ_BASE (M32104UT_CPU_IRQ_BASE + M32104UT_NUM_CPU_IRQ)
80
81#define NR_IRQS \
82 (M32104UT_NUM_CPU_IRQ + M32104UT_NUM_PLD_IRQ)
83
68#else 84#else
69#define NR_IRQS 64 85#define NR_IRQS 64
70#endif 86#endif
diff --git a/include/asm-m32r/m32102.h b/include/asm-m32r/m32102.h
index cb98101f4f6..0bd0a3f1662 100644
--- a/include/asm-m32r/m32102.h
+++ b/include/asm-m32r/m32102.h
@@ -11,7 +11,11 @@
11/*======================================================================* 11/*======================================================================*
12 * Special Function Register 12 * Special Function Register
13 *======================================================================*/ 13 *======================================================================*/
14#if !defined(CONFIG_CHIP_M32104)
14#define M32R_SFR_OFFSET (0x00E00000) /* 0x00E00000-0x00EFFFFF 1[MB] */ 15#define M32R_SFR_OFFSET (0x00E00000) /* 0x00E00000-0x00EFFFFF 1[MB] */
16#else
17#define M32R_SFR_OFFSET (0x00700000) /* 0x00700000-0x007FFFFF 1[MB] */
18#endif
15 19
16/* 20/*
17 * Clock and Power Management registers. 21 * Clock and Power Management registers.
@@ -100,7 +104,7 @@
100#define M32R_MFT5RLD_PORTL (0x0C+M32R_MFT5_OFFSET) /* MFT4 reload */ 104#define M32R_MFT5RLD_PORTL (0x0C+M32R_MFT5_OFFSET) /* MFT4 reload */
101#define M32R_MFT5CMPRLD_PORTL (0x10+M32R_MFT5_OFFSET) /* MFT4 compare reload */ 105#define M32R_MFT5CMPRLD_PORTL (0x10+M32R_MFT5_OFFSET) /* MFT4 compare reload */
102 106
103#ifdef CONFIG_CHIP_M32700 107#if defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32104)
104#define M32R_MFTCR_MFT0MSK (1UL<<31) /* b0 */ 108#define M32R_MFTCR_MFT0MSK (1UL<<31) /* b0 */
105#define M32R_MFTCR_MFT1MSK (1UL<<30) /* b1 */ 109#define M32R_MFTCR_MFT1MSK (1UL<<30) /* b1 */
106#define M32R_MFTCR_MFT2MSK (1UL<<29) /* b2 */ 110#define M32R_MFTCR_MFT2MSK (1UL<<29) /* b2 */
@@ -113,7 +117,7 @@
113#define M32R_MFTCR_MFT3EN (1UL<<20) /* b11 */ 117#define M32R_MFTCR_MFT3EN (1UL<<20) /* b11 */
114#define M32R_MFTCR_MFT4EN (1UL<<19) /* b12 */ 118#define M32R_MFTCR_MFT4EN (1UL<<19) /* b12 */
115#define M32R_MFTCR_MFT5EN (1UL<<18) /* b13 */ 119#define M32R_MFTCR_MFT5EN (1UL<<18) /* b13 */
116#else /* not CONFIG_CHIP_M32700 */ 120#else /* not CONFIG_CHIP_M32700 && not CONFIG_CHIP_M32104 */
117#define M32R_MFTCR_MFT0MSK (1UL<<15) /* b16 */ 121#define M32R_MFTCR_MFT0MSK (1UL<<15) /* b16 */
118#define M32R_MFTCR_MFT1MSK (1UL<<14) /* b17 */ 122#define M32R_MFTCR_MFT1MSK (1UL<<14) /* b17 */
119#define M32R_MFTCR_MFT2MSK (1UL<<13) /* b18 */ 123#define M32R_MFTCR_MFT2MSK (1UL<<13) /* b18 */
@@ -126,7 +130,7 @@
126#define M32R_MFTCR_MFT3EN (1UL<<4) /* b27 */ 130#define M32R_MFTCR_MFT3EN (1UL<<4) /* b27 */
127#define M32R_MFTCR_MFT4EN (1UL<<3) /* b28 */ 131#define M32R_MFTCR_MFT4EN (1UL<<3) /* b28 */
128#define M32R_MFTCR_MFT5EN (1UL<<2) /* b29 */ 132#define M32R_MFTCR_MFT5EN (1UL<<2) /* b29 */
129#endif /* not CONFIG_CHIP_M32700 */ 133#endif /* not CONFIG_CHIP_M32700 && not CONFIG_CHIP_M32104 */
130 134
131#define M32R_MFTMOD_CC_MASK (1UL<<15) /* b16 */ 135#define M32R_MFTMOD_CC_MASK (1UL<<15) /* b16 */
132#define M32R_MFTMOD_TCCR (1UL<<13) /* b18 */ 136#define M32R_MFTMOD_TCCR (1UL<<13) /* b18 */
@@ -241,8 +245,24 @@
241#define M32R_IRQ_MFT1 (17) /* MFT1 */ 245#define M32R_IRQ_MFT1 (17) /* MFT1 */
242#define M32R_IRQ_MFT2 (18) /* MFT2 */ 246#define M32R_IRQ_MFT2 (18) /* MFT2 */
243#define M32R_IRQ_MFT3 (19) /* MFT3 */ 247#define M32R_IRQ_MFT3 (19) /* MFT3 */
244#define M32R_IRQ_MFT4 (20) /* MFT4 */ 248#ifdef CONFIG_CHIP_M32104
245#define M32R_IRQ_MFT5 (21) /* MFT5 */ 249#define M32R_IRQ_MFTX0 (24) /* MFTX0 */
250#define M32R_IRQ_MFTX1 (25) /* MFTX1 */
251#define M32R_IRQ_DMA0 (32) /* DMA0 */
252#define M32R_IRQ_DMA1 (33) /* DMA1 */
253#define M32R_IRQ_DMA2 (34) /* DMA2 */
254#define M32R_IRQ_DMA3 (35) /* DMA3 */
255#define M32R_IRQ_SIO0_R (40) /* SIO0 send */
256#define M32R_IRQ_SIO0_S (41) /* SIO0 receive */
257#define M32R_IRQ_SIO1_R (42) /* SIO1 send */
258#define M32R_IRQ_SIO1_S (43) /* SIO1 receive */
259#define M32R_IRQ_SIO2_R (44) /* SIO2 send */
260#define M32R_IRQ_SIO2_S (45) /* SIO2 receive */
261#define M32R_IRQ_SIO3_R (46) /* SIO3 send */
262#define M32R_IRQ_SIO3_S (47) /* SIO3 receive */
263#define M32R_IRQ_ADC (56) /* ADC */
264#define M32R_IRQ_PC (57) /* PC */
265#else /* ! M32104 */
246#define M32R_IRQ_DMA0 (32) /* DMA0 */ 266#define M32R_IRQ_DMA0 (32) /* DMA0 */
247#define M32R_IRQ_DMA1 (33) /* DMA1 */ 267#define M32R_IRQ_DMA1 (33) /* DMA1 */
248#define M32R_IRQ_SIO0_R (48) /* SIO0 send */ 268#define M32R_IRQ_SIO0_R (48) /* SIO0 send */
@@ -255,6 +275,7 @@
255#define M32R_IRQ_SIO3_S (55) /* SIO3 receive */ 275#define M32R_IRQ_SIO3_S (55) /* SIO3 receive */
256#define M32R_IRQ_SIO4_R (56) /* SIO4 send */ 276#define M32R_IRQ_SIO4_R (56) /* SIO4 send */
257#define M32R_IRQ_SIO4_S (57) /* SIO4 receive */ 277#define M32R_IRQ_SIO4_S (57) /* SIO4 receive */
278#endif /* ! M32104 */
258 279
259#ifdef CONFIG_SMP 280#ifdef CONFIG_SMP
260#define M32R_IRQ_IPI0 (56) 281#define M32R_IRQ_IPI0 (56)
diff --git a/include/asm-m32r/m32104ut/m32104ut_pld.h b/include/asm-m32r/m32104ut/m32104ut_pld.h
new file mode 100644
index 00000000000..a4eac20553d
--- /dev/null
+++ b/include/asm-m32r/m32104ut/m32104ut_pld.h
@@ -0,0 +1,163 @@
1/*
2 * include/asm/m32104ut/m32104ut_pld.h
3 *
4 * Definitions for Programable Logic Device(PLD) on M32104UT board.
5 * Based on m32700ut_pld.h
6 *
7 * Copyright (c) 2002 Takeo Takahashi
8 * Copyright (c) 2005 Naoto Sugai
9 *
10 * This file is subject to the terms and conditions of the GNU General
11 * Public License. See the file "COPYING" in the main directory of
12 * this archive for more details.
13 */
14
15#ifndef _M32104UT_M32104UT_PLD_H
16#define _M32104UT_M32104UT_PLD_H
17
18#include <linux/config.h>
19
20#if defined(CONFIG_PLAT_M32104UT)
21#define PLD_PLAT_BASE 0x02c00000
22#else
23#error "no platform configuration"
24#endif
25
26#ifndef __ASSEMBLY__
27/*
28 * C functions use non-cache address.
29 */
30#define PLD_BASE (PLD_PLAT_BASE /* + NONCACHE_OFFSET */)
31#define __reg8 (volatile unsigned char *)
32#define __reg16 (volatile unsigned short *)
33#define __reg32 (volatile unsigned int *)
34#else
35#define PLD_BASE (PLD_PLAT_BASE + NONCACHE_OFFSET)
36#define __reg8
37#define __reg16
38#define __reg32
39#endif /* __ASSEMBLY__ */
40
41/* CFC */
42#define PLD_CFRSTCR __reg16(PLD_BASE + 0x0000)
43#define PLD_CFSTS __reg16(PLD_BASE + 0x0002)
44#define PLD_CFIMASK __reg16(PLD_BASE + 0x0004)
45#define PLD_CFBUFCR __reg16(PLD_BASE + 0x0006)
46
47/* MMC */
48#define PLD_MMCCR __reg16(PLD_BASE + 0x4000)
49#define PLD_MMCMOD __reg16(PLD_BASE + 0x4002)
50#define PLD_MMCSTS __reg16(PLD_BASE + 0x4006)
51#define PLD_MMCBAUR __reg16(PLD_BASE + 0x400a)
52#define PLD_MMCCMDBCUT __reg16(PLD_BASE + 0x400c)
53#define PLD_MMCCDTBCUT __reg16(PLD_BASE + 0x400e)
54#define PLD_MMCDET __reg16(PLD_BASE + 0x4010)
55#define PLD_MMCWP __reg16(PLD_BASE + 0x4012)
56#define PLD_MMCWDATA __reg16(PLD_BASE + 0x5000)
57#define PLD_MMCRDATA __reg16(PLD_BASE + 0x6000)
58#define PLD_MMCCMDDATA __reg16(PLD_BASE + 0x7000)
59#define PLD_MMCRSPDATA __reg16(PLD_BASE + 0x7006)
60
61/* ICU
62 * ICUISTS: status register
63 * ICUIREQ0: request register
64 * ICUIREQ1: request register
65 * ICUCR3: control register for CFIREQ# interrupt
66 * ICUCR4: control register for CFC Card insert interrupt
67 * ICUCR5: control register for CFC Card eject interrupt
68 * ICUCR6: control register for external interrupt
69 * ICUCR11: control register for MMC Card insert/eject interrupt
70 * ICUCR13: control register for SC error interrupt
71 * ICUCR14: control register for SC receive interrupt
72 * ICUCR15: control register for SC send interrupt
73 */
74
75#define PLD_IRQ_INT0 (M32104UT_PLD_IRQ_BASE + 0) /* None */
76#define PLD_IRQ_CFIREQ (M32104UT_PLD_IRQ_BASE + 3) /* CF IREQ */
77#define PLD_IRQ_CFC_INSERT (M32104UT_PLD_IRQ_BASE + 4) /* CF Insert */
78#define PLD_IRQ_CFC_EJECT (M32104UT_PLD_IRQ_BASE + 5) /* CF Eject */
79#define PLD_IRQ_EXINT (M32104UT_PLD_IRQ_BASE + 6) /* EXINT */
80#define PLD_IRQ_MMCCARD (M32104UT_PLD_IRQ_BASE + 11) /* MMC Insert/Eject */
81#define PLD_IRQ_SC_ERROR (M32104UT_PLD_IRQ_BASE + 13) /* SC error */
82#define PLD_IRQ_SC_RCV (M32104UT_PLD_IRQ_BASE + 14) /* SC receive */
83#define PLD_IRQ_SC_SND (M32104UT_PLD_IRQ_BASE + 15) /* SC send */
84
85#define PLD_ICUISTS __reg16(PLD_BASE + 0x8002)
86#define PLD_ICUISTS_VECB_MASK (0xf000)
87#define PLD_ICUISTS_VECB(x) ((x) & PLD_ICUISTS_VECB_MASK)
88#define PLD_ICUISTS_ISN_MASK (0x07c0)
89#define PLD_ICUISTS_ISN(x) ((x) & PLD_ICUISTS_ISN_MASK)
90#define PLD_ICUCR3 __reg16(PLD_BASE + 0x8104)
91#define PLD_ICUCR4 __reg16(PLD_BASE + 0x8106)
92#define PLD_ICUCR5 __reg16(PLD_BASE + 0x8108)
93#define PLD_ICUCR6 __reg16(PLD_BASE + 0x810a)
94#define PLD_ICUCR11 __reg16(PLD_BASE + 0x8114)
95#define PLD_ICUCR13 __reg16(PLD_BASE + 0x8118)
96#define PLD_ICUCR14 __reg16(PLD_BASE + 0x811a)
97#define PLD_ICUCR15 __reg16(PLD_BASE + 0x811c)
98#define PLD_ICUCR_IEN (0x1000)
99#define PLD_ICUCR_IREQ (0x0100)
100#define PLD_ICUCR_ISMOD00 (0x0000) /* Low edge */
101#define PLD_ICUCR_ISMOD01 (0x0010) /* Low level */
102#define PLD_ICUCR_ISMOD02 (0x0020) /* High edge */
103#define PLD_ICUCR_ISMOD03 (0x0030) /* High level */
104#define PLD_ICUCR_ILEVEL0 (0x0000)
105#define PLD_ICUCR_ILEVEL1 (0x0001)
106#define PLD_ICUCR_ILEVEL2 (0x0002)
107#define PLD_ICUCR_ILEVEL3 (0x0003)
108#define PLD_ICUCR_ILEVEL4 (0x0004)
109#define PLD_ICUCR_ILEVEL5 (0x0005)
110#define PLD_ICUCR_ILEVEL6 (0x0006)
111#define PLD_ICUCR_ILEVEL7 (0x0007)
112
113/* Power Control of MMC and CF */
114#define PLD_CPCR __reg16(PLD_BASE + 0x14000)
115#define PLD_CPCR_CDP 0x0001
116
117/* LED Control
118 *
119 * 1: DIP swich side
120 * 2: Reset switch side
121 */
122#define PLD_IOLEDCR __reg16(PLD_BASE + 0x14002)
123#define PLD_IOLED_1_ON 0x001
124#define PLD_IOLED_1_OFF 0x000
125#define PLD_IOLED_2_ON 0x002
126#define PLD_IOLED_2_OFF 0x000
127
128/* DIP Switch
129 * 0: Write-protect of Flash Memory (0:protected, 1:non-protected)
130 * 1: -
131 * 2: -
132 * 3: -
133 */
134#define PLD_IOSWSTS __reg16(PLD_BASE + 0x14004)
135#define PLD_IOSWSTS_IOSW2 0x0200
136#define PLD_IOSWSTS_IOSW1 0x0100
137#define PLD_IOSWSTS_IOWP0 0x0001
138
139/* CRC */
140#define PLD_CRC7DATA __reg16(PLD_BASE + 0x18000)
141#define PLD_CRC7INDATA __reg16(PLD_BASE + 0x18002)
142#define PLD_CRC16DATA __reg16(PLD_BASE + 0x18004)
143#define PLD_CRC16INDATA __reg16(PLD_BASE + 0x18006)
144#define PLD_CRC16ADATA __reg16(PLD_BASE + 0x18008)
145#define PLD_CRC16AINDATA __reg16(PLD_BASE + 0x1800a)
146
147/* RTC */
148#define PLD_RTCCR __reg16(PLD_BASE + 0x1c000)
149#define PLD_RTCBAUR __reg16(PLD_BASE + 0x1c002)
150#define PLD_RTCWRDATA __reg16(PLD_BASE + 0x1c004)
151#define PLD_RTCRDDATA __reg16(PLD_BASE + 0x1c006)
152#define PLD_RTCRSTODT __reg16(PLD_BASE + 0x1c008)
153
154/* SIM Card */
155#define PLD_SCCR __reg16(PLD_BASE + 0x38000)
156#define PLD_SCMOD __reg16(PLD_BASE + 0x38004)
157#define PLD_SCSTS __reg16(PLD_BASE + 0x38006)
158#define PLD_SCINTCR __reg16(PLD_BASE + 0x38008)
159#define PLD_SCBAUR __reg16(PLD_BASE + 0x3800a)
160#define PLD_SCTXB __reg16(PLD_BASE + 0x3800c)
161#define PLD_SCRXB __reg16(PLD_BASE + 0x3800e)
162
163#endif /* _M32104UT_M32104UT_PLD_H */
diff --git a/include/asm-m32r/m32r.h b/include/asm-m32r/m32r.h
index ec142be0086..f9bb48ac9d7 100644
--- a/include/asm-m32r/m32r.h
+++ b/include/asm-m32r/m32r.h
@@ -14,7 +14,7 @@
14#include <asm/m32r_mp_fpga.h> 14#include <asm/m32r_mp_fpga.h>
15#elif defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_XNUX2) \ 15#elif defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_XNUX2) \
16 || defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32102) \ 16 || defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32102) \
17 || defined(CONFIG_CHIP_OPSP) 17 || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104)
18#include <asm/m32102.h> 18#include <asm/m32102.h>
19#endif 19#endif
20 20
@@ -43,6 +43,10 @@
43#include <asm/m32700ut/m32700ut_pld.h> 43#include <asm/m32700ut/m32700ut_pld.h>
44#endif 44#endif
45 45
46#if defined(CONFIG_PLAT_M32104UT)
47#include <asm/m32104ut/m32104ut_pld.h>
48#endif /* CONFIG_PLAT_M32104 */
49
46/* 50/*
47 * M32R Register 51 * M32R Register
48 */ 52 */
diff --git a/include/asm-m32r/system.h b/include/asm-m32r/system.h
index 5eee832b73a..dcf619a0a0b 100644
--- a/include/asm-m32r/system.h
+++ b/include/asm-m32r/system.h
@@ -69,12 +69,12 @@
69} while(0) 69} while(0)
70 70
71/* Interrupt Control */ 71/* Interrupt Control */
72#if !defined(CONFIG_CHIP_M32102) 72#if !defined(CONFIG_CHIP_M32102) && !defined(CONFIG_CHIP_M32104)
73#define local_irq_enable() \ 73#define local_irq_enable() \
74 __asm__ __volatile__ ("setpsw #0x40 -> nop": : :"memory") 74 __asm__ __volatile__ ("setpsw #0x40 -> nop": : :"memory")
75#define local_irq_disable() \ 75#define local_irq_disable() \
76 __asm__ __volatile__ ("clrpsw #0x40 -> nop": : :"memory") 76 __asm__ __volatile__ ("clrpsw #0x40 -> nop": : :"memory")
77#else /* CONFIG_CHIP_M32102 */ 77#else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
78static inline void local_irq_enable(void) 78static inline void local_irq_enable(void)
79{ 79{
80 unsigned long tmpreg; 80 unsigned long tmpreg;
@@ -96,7 +96,7 @@ static inline void local_irq_disable(void)
96 "mvtc %0, psw \n\t" 96 "mvtc %0, psw \n\t"
97 : "=&r" (tmpreg0), "=&r" (tmpreg1) : : "cbit", "memory"); 97 : "=&r" (tmpreg0), "=&r" (tmpreg1) : : "cbit", "memory");
98} 98}
99#endif /* CONFIG_CHIP_M32102 */ 99#endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
100 100
101#define local_save_flags(x) \ 101#define local_save_flags(x) \
102 __asm__ __volatile__("mvfc %0,psw" : "=r"(x) : /* no input */) 102 __asm__ __volatile__("mvfc %0,psw" : "=r"(x) : /* no input */)
@@ -105,13 +105,13 @@ static inline void local_irq_disable(void)
105 __asm__ __volatile__("mvtc %0,psw" : /* no outputs */ \ 105 __asm__ __volatile__("mvtc %0,psw" : /* no outputs */ \
106 : "r" (x) : "cbit", "memory") 106 : "r" (x) : "cbit", "memory")
107 107
108#if !defined(CONFIG_CHIP_M32102) 108#if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104))
109#define local_irq_save(x) \ 109#define local_irq_save(x) \
110 __asm__ __volatile__( \ 110 __asm__ __volatile__( \
111 "mvfc %0, psw; \n\t" \ 111 "mvfc %0, psw; \n\t" \
112 "clrpsw #0x40 -> nop; \n\t" \ 112 "clrpsw #0x40 -> nop; \n\t" \
113 : "=r" (x) : /* no input */ : "memory") 113 : "=r" (x) : /* no input */ : "memory")
114#else /* CONFIG_CHIP_M32102 */ 114#else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
115#define local_irq_save(x) \ 115#define local_irq_save(x) \
116 ({ \ 116 ({ \
117 unsigned long tmpreg; \ 117 unsigned long tmpreg; \
@@ -124,7 +124,7 @@ static inline void local_irq_disable(void)
124 : "=r" (x), "=&r" (tmpreg) \ 124 : "=r" (x), "=&r" (tmpreg) \
125 : : "cbit", "memory"); \ 125 : : "cbit", "memory"); \
126 }) 126 })
127#endif /* CONFIG_CHIP_M32102 */ 127#endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
128 128
129#define irqs_disabled() \ 129#define irqs_disabled() \
130 ({ \ 130 ({ \
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-04 15:24:29 -0500