diff options
-rw-r--r-- | drivers/usb/host/xhci-dbg.c | 229 | ||||
-rw-r--r-- | drivers/usb/host/xhci-ext-caps.h | 145 | ||||
-rw-r--r-- | drivers/usb/host/xhci.h | 452 |
3 files changed, 826 insertions, 0 deletions
diff --git a/drivers/usb/host/xhci-dbg.c b/drivers/usb/host/xhci-dbg.c new file mode 100644 index 00000000000..a7798b46049 --- /dev/null +++ b/drivers/usb/host/xhci-dbg.c | |||
@@ -0,0 +1,229 @@ | |||
1 | /* | ||
2 | * xHCI host controller driver | ||
3 | * | ||
4 | * Copyright (C) 2008 Intel Corp. | ||
5 | * | ||
6 | * Author: Sarah Sharp | ||
7 | * Some code borrowed from the Linux EHCI driver. | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, but | ||
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | ||
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
16 | * for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License | ||
19 | * along with this program; if not, write to the Free Software Foundation, | ||
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
21 | */ | ||
22 | |||
23 | #include "xhci.h" | ||
24 | |||
25 | #define XHCI_INIT_VALUE 0x0 | ||
26 | |||
27 | /* Add verbose debugging later, just print everything for now */ | ||
28 | |||
29 | void xhci_dbg_regs(struct xhci_hcd *xhci) | ||
30 | { | ||
31 | u32 temp; | ||
32 | |||
33 | xhci_dbg(xhci, "// xHCI capability registers at 0x%x:\n", | ||
34 | (unsigned int) xhci->cap_regs); | ||
35 | temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase); | ||
36 | xhci_dbg(xhci, "// @%x = 0x%x (CAPLENGTH AND HCIVERSION)\n", | ||
37 | (unsigned int) &xhci->cap_regs->hc_capbase, | ||
38 | (unsigned int) temp); | ||
39 | xhci_dbg(xhci, "// CAPLENGTH: 0x%x\n", | ||
40 | (unsigned int) HC_LENGTH(temp)); | ||
41 | #if 0 | ||
42 | xhci_dbg(xhci, "// HCIVERSION: 0x%x\n", | ||
43 | (unsigned int) HC_VERSION(temp)); | ||
44 | #endif | ||
45 | |||
46 | xhci_dbg(xhci, "// xHCI operational registers at 0x%x:\n", | ||
47 | (unsigned int) xhci->op_regs); | ||
48 | |||
49 | temp = xhci_readl(xhci, &xhci->cap_regs->run_regs_off); | ||
50 | xhci_dbg(xhci, "// @%x = 0x%x RTSOFF\n", | ||
51 | (unsigned int) &xhci->cap_regs->run_regs_off, | ||
52 | (unsigned int) temp & RTSOFF_MASK); | ||
53 | xhci_dbg(xhci, "// xHCI runtime registers at 0x%x:\n", | ||
54 | (unsigned int) xhci->run_regs); | ||
55 | |||
56 | temp = xhci_readl(xhci, &xhci->cap_regs->db_off); | ||
57 | xhci_dbg(xhci, "// @%x = 0x%x DBOFF\n", | ||
58 | (unsigned int) &xhci->cap_regs->db_off, temp); | ||
59 | } | ||
60 | |||
61 | void xhci_print_cap_regs(struct xhci_hcd *xhci) | ||
62 | { | ||
63 | u32 temp; | ||
64 | |||
65 | xhci_dbg(xhci, "xHCI capability registers at 0x%x:\n", | ||
66 | (unsigned int) xhci->cap_regs); | ||
67 | |||
68 | temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase); | ||
69 | xhci_dbg(xhci, "CAPLENGTH AND HCIVERSION 0x%x:\n", | ||
70 | (unsigned int) temp); | ||
71 | xhci_dbg(xhci, "CAPLENGTH: 0x%x\n", | ||
72 | (unsigned int) HC_LENGTH(temp)); | ||
73 | xhci_dbg(xhci, "HCIVERSION: 0x%x\n", | ||
74 | (unsigned int) HC_VERSION(temp)); | ||
75 | |||
76 | temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params1); | ||
77 | xhci_dbg(xhci, "HCSPARAMS 1: 0x%x\n", | ||
78 | (unsigned int) temp); | ||
79 | xhci_dbg(xhci, " Max device slots: %u\n", | ||
80 | (unsigned int) HCS_MAX_SLOTS(temp)); | ||
81 | xhci_dbg(xhci, " Max interrupters: %u\n", | ||
82 | (unsigned int) HCS_MAX_INTRS(temp)); | ||
83 | xhci_dbg(xhci, " Max ports: %u\n", | ||
84 | (unsigned int) HCS_MAX_PORTS(temp)); | ||
85 | |||
86 | temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params2); | ||
87 | xhci_dbg(xhci, "HCSPARAMS 2: 0x%x\n", | ||
88 | (unsigned int) temp); | ||
89 | xhci_dbg(xhci, " Isoc scheduling threshold: %u\n", | ||
90 | (unsigned int) HCS_IST(temp)); | ||
91 | xhci_dbg(xhci, " Maximum allowed segments in event ring: %u\n", | ||
92 | (unsigned int) HCS_ERST_MAX(temp)); | ||
93 | |||
94 | temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params3); | ||
95 | xhci_dbg(xhci, "HCSPARAMS 3 0x%x:\n", | ||
96 | (unsigned int) temp); | ||
97 | xhci_dbg(xhci, " Worst case U1 device exit latency: %u\n", | ||
98 | (unsigned int) HCS_U1_LATENCY(temp)); | ||
99 | xhci_dbg(xhci, " Worst case U2 device exit latency: %u\n", | ||
100 | (unsigned int) HCS_U2_LATENCY(temp)); | ||
101 | |||
102 | temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params); | ||
103 | xhci_dbg(xhci, "HCC PARAMS 0x%x:\n", (unsigned int) temp); | ||
104 | xhci_dbg(xhci, " HC generates %s bit addresses\n", | ||
105 | HCC_64BIT_ADDR(temp) ? "64" : "32"); | ||
106 | /* FIXME */ | ||
107 | xhci_dbg(xhci, " FIXME: more HCCPARAMS debugging\n"); | ||
108 | |||
109 | temp = xhci_readl(xhci, &xhci->cap_regs->run_regs_off); | ||
110 | xhci_dbg(xhci, "RTSOFF 0x%x:\n", temp & RTSOFF_MASK); | ||
111 | } | ||
112 | |||
113 | void xhci_print_command_reg(struct xhci_hcd *xhci) | ||
114 | { | ||
115 | u32 temp; | ||
116 | |||
117 | temp = xhci_readl(xhci, &xhci->op_regs->command); | ||
118 | xhci_dbg(xhci, "USBCMD 0x%x:\n", temp); | ||
119 | xhci_dbg(xhci, " HC is %s\n", | ||
120 | (temp & CMD_RUN) ? "running" : "being stopped"); | ||
121 | xhci_dbg(xhci, " HC has %sfinished hard reset\n", | ||
122 | (temp & CMD_RESET) ? "not " : ""); | ||
123 | xhci_dbg(xhci, " Event Interrupts %s\n", | ||
124 | (temp & CMD_EIE) ? "enabled " : "disabled"); | ||
125 | xhci_dbg(xhci, " Host System Error Interrupts %s\n", | ||
126 | (temp & CMD_EIE) ? "enabled " : "disabled"); | ||
127 | xhci_dbg(xhci, " HC has %sfinished light reset\n", | ||
128 | (temp & CMD_LRESET) ? "not " : ""); | ||
129 | } | ||
130 | |||
131 | void xhci_print_status(struct xhci_hcd *xhci) | ||
132 | { | ||
133 | u32 temp; | ||
134 | |||
135 | temp = xhci_readl(xhci, &xhci->op_regs->status); | ||
136 | xhci_dbg(xhci, "USBSTS 0x%x:\n", temp); | ||
137 | xhci_dbg(xhci, " Event ring is %sempty\n", | ||
138 | (temp & STS_EINT) ? "not " : ""); | ||
139 | xhci_dbg(xhci, " %sHost System Error\n", | ||
140 | (temp & STS_FATAL) ? "WARNING: " : "No "); | ||
141 | xhci_dbg(xhci, " HC is %s\n", | ||
142 | (temp & STS_HALT) ? "halted" : "running"); | ||
143 | } | ||
144 | |||
145 | void xhci_print_op_regs(struct xhci_hcd *xhci) | ||
146 | { | ||
147 | xhci_dbg(xhci, "xHCI operational registers at 0x%x:\n", | ||
148 | (unsigned int) xhci->op_regs); | ||
149 | xhci_print_command_reg(xhci); | ||
150 | xhci_print_status(xhci); | ||
151 | } | ||
152 | |||
153 | void xhci_print_ir_set(struct xhci_hcd *xhci, struct intr_reg *ir_set, int set_num) | ||
154 | { | ||
155 | void *addr; | ||
156 | u32 temp; | ||
157 | |||
158 | addr = &ir_set->irq_pending; | ||
159 | temp = xhci_readl(xhci, addr); | ||
160 | if (temp == XHCI_INIT_VALUE) | ||
161 | return; | ||
162 | |||
163 | xhci_dbg(xhci, " 0x%x: ir_set[%i]\n", (unsigned int) ir_set, set_num); | ||
164 | |||
165 | xhci_dbg(xhci, " 0x%x: ir_set.pending = 0x%x\n", | ||
166 | (unsigned int) addr, (unsigned int) temp); | ||
167 | |||
168 | addr = &ir_set->irq_control; | ||
169 | temp = xhci_readl(xhci, addr); | ||
170 | xhci_dbg(xhci, " 0x%x: ir_set.control = 0x%x\n", | ||
171 | (unsigned int) addr, (unsigned int) temp); | ||
172 | |||
173 | addr = &ir_set->erst_size; | ||
174 | temp = xhci_readl(xhci, addr); | ||
175 | xhci_dbg(xhci, " 0x%x: ir_set.erst_size = 0x%x\n", | ||
176 | (unsigned int) addr, (unsigned int) temp); | ||
177 | |||
178 | addr = &ir_set->rsvd; | ||
179 | temp = xhci_readl(xhci, addr); | ||
180 | if (temp != XHCI_INIT_VALUE) | ||
181 | xhci_dbg(xhci, " WARN: 0x%x: ir_set.rsvd = 0x%x\n", | ||
182 | (unsigned int) addr, (unsigned int) temp); | ||
183 | |||
184 | addr = &ir_set->erst_base[0]; | ||
185 | temp = xhci_readl(xhci, addr); | ||
186 | xhci_dbg(xhci, " 0x%x: ir_set.erst_base[0] = 0x%x\n", | ||
187 | (unsigned int) addr, (unsigned int) temp); | ||
188 | |||
189 | addr = &ir_set->erst_base[1]; | ||
190 | temp = xhci_readl(xhci, addr); | ||
191 | xhci_dbg(xhci, " 0x%x: ir_set.erst_base[1] = 0x%x\n", | ||
192 | (unsigned int) addr, (unsigned int) temp); | ||
193 | |||
194 | addr = &ir_set->erst_dequeue[0]; | ||
195 | temp = xhci_readl(xhci, addr); | ||
196 | xhci_dbg(xhci, " 0x%x: ir_set.erst_dequeue[0] = 0x%x\n", | ||
197 | (unsigned int) addr, (unsigned int) temp); | ||
198 | |||
199 | addr = &ir_set->erst_dequeue[1]; | ||
200 | temp = xhci_readl(xhci, addr); | ||
201 | xhci_dbg(xhci, " 0x%x: ir_set.erst_dequeue[1] = 0x%x\n", | ||
202 | (unsigned int) addr, (unsigned int) temp); | ||
203 | } | ||
204 | |||
205 | void xhci_print_run_regs(struct xhci_hcd *xhci) | ||
206 | { | ||
207 | u32 temp; | ||
208 | int i; | ||
209 | |||
210 | xhci_dbg(xhci, "xHCI runtime registers at 0x%x:\n", | ||
211 | (unsigned int) xhci->run_regs); | ||
212 | temp = xhci_readl(xhci, &xhci->run_regs->microframe_index); | ||
213 | xhci_dbg(xhci, " 0x%x: Microframe index = 0x%x\n", | ||
214 | (unsigned int) &xhci->run_regs->microframe_index, | ||
215 | (unsigned int) temp); | ||
216 | for (i = 0; i < 7; ++i) { | ||
217 | temp = xhci_readl(xhci, &xhci->run_regs->rsvd[i]); | ||
218 | if (temp != XHCI_INIT_VALUE) | ||
219 | xhci_dbg(xhci, " WARN: 0x%x: Rsvd[%i] = 0x%x\n", | ||
220 | (unsigned int) &xhci->run_regs->rsvd[i], | ||
221 | i, (unsigned int) temp); | ||
222 | } | ||
223 | } | ||
224 | |||
225 | void xhci_print_registers(struct xhci_hcd *xhci) | ||
226 | { | ||
227 | xhci_print_cap_regs(xhci); | ||
228 | xhci_print_op_regs(xhci); | ||
229 | } | ||
diff --git a/drivers/usb/host/xhci-ext-caps.h b/drivers/usb/host/xhci-ext-caps.h new file mode 100644 index 00000000000..ecc131c3fe3 --- /dev/null +++ b/drivers/usb/host/xhci-ext-caps.h | |||
@@ -0,0 +1,145 @@ | |||
1 | /* | ||
2 | * xHCI host controller driver | ||
3 | * | ||
4 | * Copyright (C) 2008 Intel Corp. | ||
5 | * | ||
6 | * Author: Sarah Sharp | ||
7 | * Some code borrowed from the Linux EHCI driver. | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, but | ||
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | ||
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
16 | * for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License | ||
19 | * along with this program; if not, write to the Free Software Foundation, | ||
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
21 | */ | ||
22 | /* Up to 16 microframes to halt an HC - one microframe is 125 microsectonds */ | ||
23 | #define XHCI_MAX_HALT_USEC (16*125) | ||
24 | /* HC not running - set to 1 when run/stop bit is cleared. */ | ||
25 | #define XHCI_STS_HALT (1<<0) | ||
26 | |||
27 | /* HCCPARAMS offset from PCI base address */ | ||
28 | #define XHCI_HCC_PARAMS_OFFSET 0x10 | ||
29 | /* HCCPARAMS contains the first extended capability pointer */ | ||
30 | #define XHCI_HCC_EXT_CAPS(p) (((p)>>16)&0xffff) | ||
31 | |||
32 | /* Command and Status registers offset from the Operational Registers address */ | ||
33 | #define XHCI_CMD_OFFSET 0x00 | ||
34 | #define XHCI_STS_OFFSET 0x04 | ||
35 | |||
36 | #define XHCI_MAX_EXT_CAPS 50 | ||
37 | |||
38 | /* Capability Register */ | ||
39 | /* bits 7:0 - how long is the Capabilities register */ | ||
40 | #define XHCI_HC_LENGTH(p) (((p)>>00)&0x00ff) | ||
41 | |||
42 | /* Extended capability register fields */ | ||
43 | #define XHCI_EXT_CAPS_ID(p) (((p)>>0)&0xff) | ||
44 | #define XHCI_EXT_CAPS_NEXT(p) (((p)>>8)&0xff) | ||
45 | #define XHCI_EXT_CAPS_VAL(p) ((p)>>16) | ||
46 | /* Extended capability IDs - ID 0 reserved */ | ||
47 | #define XHCI_EXT_CAPS_LEGACY 1 | ||
48 | #define XHCI_EXT_CAPS_PROTOCOL 2 | ||
49 | #define XHCI_EXT_CAPS_PM 3 | ||
50 | #define XHCI_EXT_CAPS_VIRT 4 | ||
51 | #define XHCI_EXT_CAPS_ROUTE 5 | ||
52 | /* IDs 6-9 reserved */ | ||
53 | #define XHCI_EXT_CAPS_DEBUG 10 | ||
54 | /* USB Legacy Support Capability - section 7.1.1 */ | ||
55 | #define XHCI_HC_BIOS_OWNED (1 << 16) | ||
56 | #define XHCI_HC_OS_OWNED (1 << 24) | ||
57 | |||
58 | /* USB Legacy Support Capability - section 7.1.1 */ | ||
59 | /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */ | ||
60 | #define XHCI_LEGACY_SUPPORT_OFFSET (0x00) | ||
61 | |||
62 | /* USB Legacy Support Control and Status Register - section 7.1.2 */ | ||
63 | /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */ | ||
64 | #define XHCI_LEGACY_CONTROL_OFFSET (0x04) | ||
65 | /* bits 1:2, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */ | ||
66 | #define XHCI_LEGACY_DISABLE_SMI ((0x3 << 1) + (0xff << 5) + (0x7 << 17)) | ||
67 | |||
68 | /* command register values to disable interrupts and halt the HC */ | ||
69 | /* start/stop HC execution - do not write unless HC is halted*/ | ||
70 | #define XHCI_CMD_RUN (1 << 0) | ||
71 | /* Event Interrupt Enable - get irq when EINT bit is set in USBSTS register */ | ||
72 | #define XHCI_CMD_EIE (1 << 2) | ||
73 | /* Host System Error Interrupt Enable - get irq when HSEIE bit set in USBSTS */ | ||
74 | #define XHCI_CMD_HSEIE (1 << 3) | ||
75 | /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ | ||
76 | #define XHCI_CMD_EWE (1 << 10) | ||
77 | |||
78 | #define XHCI_IRQS (XHCI_CMD_EIE | XHCI_CMD_HSEIE | XHCI_CMD_EWE) | ||
79 | |||
80 | /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ | ||
81 | #define XHCI_STS_CNR (1 << 11) | ||
82 | |||
83 | #include <linux/io.h> | ||
84 | |||
85 | /** | ||
86 | * Return the next extended capability pointer register. | ||
87 | * | ||
88 | * @base PCI register base address. | ||
89 | * | ||
90 | * @ext_offset Offset of the 32-bit register that contains the extended | ||
91 | * capabilites pointer. If searching for the first extended capability, pass | ||
92 | * in XHCI_HCC_PARAMS_OFFSET. If searching for the next extended capability, | ||
93 | * pass in the offset of the current extended capability register. | ||
94 | * | ||
95 | * Returns 0 if there is no next extended capability register or returns the register offset | ||
96 | * from the PCI registers base address. | ||
97 | */ | ||
98 | static inline int xhci_find_next_cap_offset(void __iomem *base, int ext_offset) | ||
99 | { | ||
100 | u32 next; | ||
101 | |||
102 | next = readl(base + ext_offset); | ||
103 | |||
104 | if (ext_offset == XHCI_HCC_PARAMS_OFFSET) | ||
105 | /* Find the first extended capability */ | ||
106 | next = XHCI_HCC_EXT_CAPS(next); | ||
107 | else | ||
108 | /* Find the next extended capability */ | ||
109 | next = XHCI_EXT_CAPS_NEXT(next); | ||
110 | if (!next) | ||
111 | return 0; | ||
112 | /* | ||
113 | * Address calculation from offset of extended capabilities | ||
114 | * (or HCCPARAMS) register - see section 5.3.6 and section 7. | ||
115 | */ | ||
116 | return ext_offset + (next << 2); | ||
117 | } | ||
118 | |||
119 | /** | ||
120 | * Find the offset of the extended capabilities with capability ID id. | ||
121 | * | ||
122 | * @base PCI MMIO registers base address. | ||
123 | * @ext_offset Offset from base of the first extended capability to look at, | ||
124 | * or the address of HCCPARAMS. | ||
125 | * @id Extended capability ID to search for. | ||
126 | * | ||
127 | * This uses an arbitrary limit of XHCI_MAX_EXT_CAPS extended capabilities | ||
128 | * to make sure that the list doesn't contain a loop. | ||
129 | */ | ||
130 | static inline int xhci_find_ext_cap_by_id(void __iomem *base, int ext_offset, int id) | ||
131 | { | ||
132 | u32 val; | ||
133 | int limit = XHCI_MAX_EXT_CAPS; | ||
134 | |||
135 | while (ext_offset && limit > 0) { | ||
136 | val = readl(base + ext_offset); | ||
137 | if (XHCI_EXT_CAPS_ID(val) == id) | ||
138 | break; | ||
139 | ext_offset = xhci_find_next_cap_offset(base, ext_offset); | ||
140 | limit--; | ||
141 | } | ||
142 | if (limit > 0) | ||
143 | return ext_offset; | ||
144 | return 0; | ||
145 | } | ||
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h new file mode 100644 index 00000000000..a4d44aad069 --- /dev/null +++ b/drivers/usb/host/xhci.h | |||
@@ -0,0 +1,452 @@ | |||
1 | /* | ||
2 | * xHCI host controller driver | ||
3 | * | ||
4 | * Copyright (C) 2008 Intel Corp. | ||
5 | * | ||
6 | * Author: Sarah Sharp | ||
7 | * Some code borrowed from the Linux EHCI driver. | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, but | ||
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | ||
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
16 | * for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License | ||
19 | * along with this program; if not, write to the Free Software Foundation, | ||
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
21 | */ | ||
22 | |||
23 | #ifndef __LINUX_XHCI_HCD_H | ||
24 | #define __LINUX_XHCI_HCD_H | ||
25 | |||
26 | #include <linux/usb.h> | ||
27 | |||
28 | #include "../core/hcd.h" | ||
29 | /* Code sharing between pci-quirks and xhci hcd */ | ||
30 | #include "xhci-ext-caps.h" | ||
31 | |||
32 | /* xHCI PCI Configuration Registers */ | ||
33 | #define XHCI_SBRN_OFFSET (0x60) | ||
34 | |||
35 | /* | ||
36 | * xHCI register interface. | ||
37 | * This corresponds to the eXtensible Host Controller Interface (xHCI) | ||
38 | * Revision 0.95 specification | ||
39 | * | ||
40 | * Registers should always be accessed with double word or quad word accesses. | ||
41 | * | ||
42 | * Some xHCI implementations may support 64-bit address pointers. Registers | ||
43 | * with 64-bit address pointers should be written to with dword accesses by | ||
44 | * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. | ||
45 | * xHCI implementations that do not support 64-bit address pointers will ignore | ||
46 | * the high dword, and write order is irrelevant. | ||
47 | */ | ||
48 | |||
49 | /** | ||
50 | * struct xhci_cap_regs - xHCI Host Controller Capability Registers. | ||
51 | * @hc_capbase: length of the capabilities register and HC version number | ||
52 | * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 | ||
53 | * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 | ||
54 | * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 | ||
55 | * @hcc_params: HCCPARAMS - Capability Parameters | ||
56 | * @db_off: DBOFF - Doorbell array offset | ||
57 | * @run_regs_off: RTSOFF - Runtime register space offset | ||
58 | */ | ||
59 | struct xhci_cap_regs { | ||
60 | u32 hc_capbase; | ||
61 | u32 hcs_params1; | ||
62 | u32 hcs_params2; | ||
63 | u32 hcs_params3; | ||
64 | u32 hcc_params; | ||
65 | u32 db_off; | ||
66 | u32 run_regs_off; | ||
67 | /* Reserved up to (CAPLENGTH - 0x1C) */ | ||
68 | } __attribute__ ((packed)); | ||
69 | |||
70 | /* hc_capbase bitmasks */ | ||
71 | /* bits 7:0 - how long is the Capabilities register */ | ||
72 | #define HC_LENGTH(p) XHCI_HC_LENGTH(p) | ||
73 | /* bits 31:16 */ | ||
74 | #define HC_VERSION(p) (((p) >> 16) & 0xffff) | ||
75 | |||
76 | /* HCSPARAMS1 - hcs_params1 - bitmasks */ | ||
77 | /* bits 0:7, Max Device Slots */ | ||
78 | #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) | ||
79 | #define HCS_SLOTS_MASK 0xff | ||
80 | /* bits 8:18, Max Interrupters */ | ||
81 | #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) | ||
82 | /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ | ||
83 | #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f) | ||
84 | |||
85 | /* HCSPARAMS2 - hcs_params2 - bitmasks */ | ||
86 | /* bits 0:3, frames or uframes that SW needs to queue transactions | ||
87 | * ahead of the HW to meet periodic deadlines */ | ||
88 | #define HCS_IST(p) (((p) >> 0) & 0xf) | ||
89 | /* bits 4:7, max number of Event Ring segments */ | ||
90 | #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) | ||
91 | /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ | ||
92 | /* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */ | ||
93 | |||
94 | /* HCSPARAMS3 - hcs_params3 - bitmasks */ | ||
95 | /* bits 0:7, Max U1 to U0 latency for the roothub ports */ | ||
96 | #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) | ||
97 | /* bits 16:31, Max U2 to U0 latency for the roothub ports */ | ||
98 | #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) | ||
99 | |||
100 | /* HCCPARAMS - hcc_params - bitmasks */ | ||
101 | /* true: HC can use 64-bit address pointers */ | ||
102 | #define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) | ||
103 | /* true: HC can do bandwidth negotiation */ | ||
104 | #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) | ||
105 | /* true: HC uses 64-byte Device Context structures | ||
106 | * FIXME 64-byte context structures aren't supported yet. | ||
107 | */ | ||
108 | #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) | ||
109 | /* true: HC has port power switches */ | ||
110 | #define HCC_PPC(p) ((p) & (1 << 3)) | ||
111 | /* true: HC has port indicators */ | ||
112 | #define HCS_INDICATOR(p) ((p) & (1 << 4)) | ||
113 | /* true: HC has Light HC Reset Capability */ | ||
114 | #define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) | ||
115 | /* true: HC supports latency tolerance messaging */ | ||
116 | #define HCC_LTC(p) ((p) & (1 << 6)) | ||
117 | /* true: no secondary Stream ID Support */ | ||
118 | #define HCC_NSS(p) ((p) & (1 << 7)) | ||
119 | /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ | ||
120 | #define HCC_MAX_PSA (1 << ((((p) >> 12) & 0xf) + 1)) | ||
121 | /* Extended Capabilities pointer from PCI base - section 5.3.6 */ | ||
122 | #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) | ||
123 | |||
124 | /* db_off bitmask - bits 0:1 reserved */ | ||
125 | #define DBOFF_MASK (~0x3) | ||
126 | |||
127 | /* run_regs_off bitmask - bits 0:4 reserved */ | ||
128 | #define RTSOFF_MASK (~0x1f) | ||
129 | |||
130 | |||
131 | /* Number of registers per port */ | ||
132 | #define NUM_PORT_REGS 4 | ||
133 | |||
134 | /** | ||
135 | * struct xhci_op_regs - xHCI Host Controller Operational Registers. | ||
136 | * @command: USBCMD - xHC command register | ||
137 | * @status: USBSTS - xHC status register | ||
138 | * @page_size: This indicates the page size that the host controller | ||
139 | * supports. If bit n is set, the HC supports a page size | ||
140 | * of 2^(n+12), up to a 128MB page size. | ||
141 | * 4K is the minimum page size. | ||
142 | * @cmd_ring: CRP - 64-bit Command Ring Pointer | ||
143 | * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer | ||
144 | * @config_reg: CONFIG - Configure Register | ||
145 | * @port_status_base: PORTSCn - base address for Port Status and Control | ||
146 | * Each port has a Port Status and Control register, | ||
147 | * followed by a Port Power Management Status and Control | ||
148 | * register, a Port Link Info register, and a reserved | ||
149 | * register. | ||
150 | * @port_power_base: PORTPMSCn - base address for | ||
151 | * Port Power Management Status and Control | ||
152 | * @port_link_base: PORTLIn - base address for Port Link Info (current | ||
153 | * Link PM state and control) for USB 2.1 and USB 3.0 | ||
154 | * devices. | ||
155 | */ | ||
156 | struct xhci_op_regs { | ||
157 | u32 command; | ||
158 | u32 status; | ||
159 | u32 page_size; | ||
160 | u32 reserved1; | ||
161 | u32 reserved2; | ||
162 | u32 dev_notification; | ||
163 | u32 cmd_ring[2]; | ||
164 | /* rsvd: offset 0x20-2F */ | ||
165 | u32 reserved3[4]; | ||
166 | u32 dcbaa_ptr[2]; | ||
167 | u32 config_reg; | ||
168 | /* rsvd: offset 0x3C-3FF */ | ||
169 | u32 reserved4[241]; | ||
170 | /* port 1 registers, which serve as a base address for other ports */ | ||
171 | u32 port_status_base; | ||
172 | u32 port_power_base; | ||
173 | u32 port_link_base; | ||
174 | u32 reserved5; | ||
175 | /* registers for ports 2-255 */ | ||
176 | u32 reserved6[NUM_PORT_REGS*254]; | ||
177 | } __attribute__ ((packed)); | ||
178 | |||
179 | /* USBCMD - USB command - command bitmasks */ | ||
180 | /* start/stop HC execution - do not write unless HC is halted*/ | ||
181 | #define CMD_RUN XHCI_CMD_RUN | ||
182 | /* Reset HC - resets internal HC state machine and all registers (except | ||
183 | * PCI config regs). HC does NOT drive a USB reset on the downstream ports. | ||
184 | * The xHCI driver must reinitialize the xHC after setting this bit. | ||
185 | */ | ||
186 | #define CMD_RESET (1 << 1) | ||
187 | /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ | ||
188 | #define CMD_EIE XHCI_CMD_EIE | ||
189 | /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ | ||
190 | #define CMD_HSEIE XHCI_CMD_HSEIE | ||
191 | /* bits 4:6 are reserved (and should be preserved on writes). */ | ||
192 | /* light reset (port status stays unchanged) - reset completed when this is 0 */ | ||
193 | #define CMD_LRESET (1 << 7) | ||
194 | /* FIXME: ignoring host controller save/restore state for now. */ | ||
195 | #define CMD_CSS (1 << 8) | ||
196 | #define CMD_CRS (1 << 9) | ||
197 | /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ | ||
198 | #define CMD_EWE XHCI_CMD_EWE | ||
199 | /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root | ||
200 | * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. | ||
201 | * '0' means the xHC can power it off if all ports are in the disconnect, | ||
202 | * disabled, or powered-off state. | ||
203 | */ | ||
204 | #define CMD_PM_INDEX (1 << 11) | ||
205 | /* bits 12:31 are reserved (and should be preserved on writes). */ | ||
206 | |||
207 | /* USBSTS - USB status - status bitmasks */ | ||
208 | /* HC not running - set to 1 when run/stop bit is cleared. */ | ||
209 | #define STS_HALT XHCI_STS_HALT | ||
210 | /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ | ||
211 | #define STS_FATAL (1 << 2) | ||
212 | /* event interrupt - clear this prior to clearing any IP flags in IR set*/ | ||
213 | #define STS_EINT (1 << 3) | ||
214 | /* port change detect */ | ||
215 | #define STS_PORT (1 << 4) | ||
216 | /* bits 5:7 reserved and zeroed */ | ||
217 | /* save state status - '1' means xHC is saving state */ | ||
218 | #define STS_SAVE (1 << 8) | ||
219 | /* restore state status - '1' means xHC is restoring state */ | ||
220 | #define STS_RESTORE (1 << 9) | ||
221 | /* true: save or restore error */ | ||
222 | #define STS_SRE (1 << 10) | ||
223 | /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ | ||
224 | #define STS_CNR XHCI_STS_CNR | ||
225 | /* true: internal Host Controller Error - SW needs to reset and reinitialize */ | ||
226 | #define STS_HCE (1 << 12) | ||
227 | /* bits 13:31 reserved and should be preserved */ | ||
228 | |||
229 | /* | ||
230 | * DNCTRL - Device Notification Control Register - dev_notification bitmasks | ||
231 | * Generate a device notification event when the HC sees a transaction with a | ||
232 | * notification type that matches a bit set in this bit field. | ||
233 | */ | ||
234 | #define DEV_NOTE_MASK (0xffff) | ||
235 | #define ENABLE_DEV_NOTE(x) (1 << x) | ||
236 | /* Most of the device notification types should only be used for debug. | ||
237 | * SW does need to pay attention to function wake notifications. | ||
238 | */ | ||
239 | #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) | ||
240 | |||
241 | /* CONFIG - Configure Register - config_reg bitmasks */ | ||
242 | /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ | ||
243 | #define MAX_DEVS(p) ((p) & 0xff) | ||
244 | /* bits 8:31 - reserved and should be preserved */ | ||
245 | |||
246 | /* PORTSC - Port Status and Control Register - port_status_base bitmasks */ | ||
247 | /* true: device connected */ | ||
248 | #define PORT_CONNECT (1 << 0) | ||
249 | /* true: port enabled */ | ||
250 | #define PORT_PE (1 << 1) | ||
251 | /* bit 2 reserved and zeroed */ | ||
252 | /* true: port has an over-current condition */ | ||
253 | #define PORT_OC (1 << 3) | ||
254 | /* true: port reset signaling asserted */ | ||
255 | #define PORT_RESET (1 << 4) | ||
256 | /* Port Link State - bits 5:8 | ||
257 | * A read gives the current link PM state of the port, | ||
258 | * a write with Link State Write Strobe set sets the link state. | ||
259 | */ | ||
260 | /* true: port has power (see HCC_PPC) */ | ||
261 | #define PORT_POWER (1 << 9) | ||
262 | /* bits 10:13 indicate device speed: | ||
263 | * 0 - undefined speed - port hasn't be initialized by a reset yet | ||
264 | * 1 - full speed | ||
265 | * 2 - low speed | ||
266 | * 3 - high speed | ||
267 | * 4 - super speed | ||
268 | * 5-15 reserved | ||
269 | */ | ||
270 | #define DEV_SPEED_MASK (0xf<<10) | ||
271 | #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) | ||
272 | #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == (0x1<<10)) | ||
273 | #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == (0x2<<10)) | ||
274 | #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == (0x3<<10)) | ||
275 | #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == (0x4<<10)) | ||
276 | /* Port Indicator Control */ | ||
277 | #define PORT_LED_OFF (0 << 14) | ||
278 | #define PORT_LED_AMBER (1 << 14) | ||
279 | #define PORT_LED_GREEN (2 << 14) | ||
280 | #define PORT_LED_MASK (3 << 14) | ||
281 | /* Port Link State Write Strobe - set this when changing link state */ | ||
282 | #define PORT_LINK_STROBE (1 << 16) | ||
283 | /* true: connect status change */ | ||
284 | #define PORT_CSC (1 << 17) | ||
285 | /* true: port enable change */ | ||
286 | #define PORT_PEC (1 << 18) | ||
287 | /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port | ||
288 | * into an enabled state, and the device into the default state. A "warm" reset | ||
289 | * also resets the link, forcing the device through the link training sequence. | ||
290 | * SW can also look at the Port Reset register to see when warm reset is done. | ||
291 | */ | ||
292 | #define PORT_WRC (1 << 19) | ||
293 | /* true: over-current change */ | ||
294 | #define PORT_OCC (1 << 20) | ||
295 | /* true: reset change - 1 to 0 transition of PORT_RESET */ | ||
296 | #define PORT_RC (1 << 21) | ||
297 | /* port link status change - set on some port link state transitions: | ||
298 | * Transition Reason | ||
299 | * ------------------------------------------------------------------------------ | ||
300 | * - U3 to Resume Wakeup signaling from a device | ||
301 | * - Resume to Recovery to U0 USB 3.0 device resume | ||
302 | * - Resume to U0 USB 2.0 device resume | ||
303 | * - U3 to Recovery to U0 Software resume of USB 3.0 device complete | ||
304 | * - U3 to U0 Software resume of USB 2.0 device complete | ||
305 | * - U2 to U0 L1 resume of USB 2.1 device complete | ||
306 | * - U0 to U0 (???) L1 entry rejection by USB 2.1 device | ||
307 | * - U0 to disabled L1 entry error with USB 2.1 device | ||
308 | * - Any state to inactive Error on USB 3.0 port | ||
309 | */ | ||
310 | #define PORT_PLC (1 << 22) | ||
311 | /* port configure error change - port failed to configure its link partner */ | ||
312 | #define PORT_CEC (1 << 23) | ||
313 | /* bit 24 reserved */ | ||
314 | /* wake on connect (enable) */ | ||
315 | #define PORT_WKCONN_E (1 << 25) | ||
316 | /* wake on disconnect (enable) */ | ||
317 | #define PORT_WKDISC_E (1 << 26) | ||
318 | /* wake on over-current (enable) */ | ||
319 | #define PORT_WKOC_E (1 << 27) | ||
320 | /* bits 28:29 reserved */ | ||
321 | /* true: device is removable - for USB 3.0 roothub emulation */ | ||
322 | #define PORT_DEV_REMOVE (1 << 30) | ||
323 | /* Initiate a warm port reset - complete when PORT_WRC is '1' */ | ||
324 | #define PORT_WR (1 << 31) | ||
325 | |||
326 | /* Port Power Management Status and Control - port_power_base bitmasks */ | ||
327 | /* Inactivity timer value for transitions into U1, in microseconds. | ||
328 | * Timeout can be up to 127us. 0xFF means an infinite timeout. | ||
329 | */ | ||
330 | #define PORT_U1_TIMEOUT(p) ((p) & 0xff) | ||
331 | /* Inactivity timer value for transitions into U2 */ | ||
332 | #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) | ||
333 | /* Bits 24:31 for port testing */ | ||
334 | |||
335 | |||
336 | /** | ||
337 | * struct intr_reg - Interrupt Register Set | ||
338 | * @irq_pending: IMAN - Interrupt Management Register. Used to enable | ||
339 | * interrupts and check for pending interrupts. | ||
340 | * @irq_control: IMOD - Interrupt Moderation Register. | ||
341 | * Used to throttle interrupts. | ||
342 | * @erst_size: Number of segments in the Event Ring Segment Table (ERST). | ||
343 | * @erst_base: ERST base address. | ||
344 | * @erst_dequeue: Event ring dequeue pointer. | ||
345 | * | ||
346 | * Each interrupter (defined by a MSI-X vector) has an event ring and an Event | ||
347 | * Ring Segment Table (ERST) associated with it. The event ring is comprised of | ||
348 | * multiple segments of the same size. The HC places events on the ring and | ||
349 | * "updates the Cycle bit in the TRBs to indicate to software the current | ||
350 | * position of the Enqueue Pointer." The HCD (Linux) processes those events and | ||
351 | * updates the dequeue pointer. | ||
352 | */ | ||
353 | struct intr_reg { | ||
354 | u32 irq_pending; | ||
355 | u32 irq_control; | ||
356 | u32 erst_size; | ||
357 | u32 rsvd; | ||
358 | u32 erst_base[2]; | ||
359 | u32 erst_dequeue[2]; | ||
360 | } __attribute__ ((packed)); | ||
361 | |||
362 | #define ER_IRQ_PENDING(p) ((p) & 0x1) | ||
363 | #define ER_IRQ_ENABLE(p) ((p) | 0x2) | ||
364 | /* Preserve bits 16:31 of erst_size */ | ||
365 | #define ERST_SIZE_MASK (0xffff<<16) | ||
366 | |||
367 | /** | ||
368 | * struct xhci_run_regs | ||
369 | * @microframe_index: | ||
370 | * MFINDEX - current microframe number | ||
371 | * | ||
372 | * Section 5.5 Host Controller Runtime Registers: | ||
373 | * "Software should read and write these registers using only Dword (32 bit) | ||
374 | * or larger accesses" | ||
375 | */ | ||
376 | struct xhci_run_regs { | ||
377 | u32 microframe_index; | ||
378 | u32 rsvd[7]; | ||
379 | struct intr_reg ir_set[128]; | ||
380 | } __attribute__ ((packed)); | ||
381 | |||
382 | |||
383 | /* There is one ehci_hci structure per controller */ | ||
384 | struct xhci_hcd { | ||
385 | /* glue to PCI and HCD framework */ | ||
386 | struct xhci_cap_regs __iomem *cap_regs; | ||
387 | struct xhci_op_regs __iomem *op_regs; | ||
388 | struct xhci_run_regs __iomem *run_regs; | ||
389 | |||
390 | /* Cached register copies of read-only HC data */ | ||
391 | __u32 hcs_params1; | ||
392 | __u32 hcs_params2; | ||
393 | __u32 hcs_params3; | ||
394 | __u32 hcc_params; | ||
395 | |||
396 | spinlock_t lock; | ||
397 | |||
398 | /* packed release number */ | ||
399 | u8 sbrn; | ||
400 | u16 hci_version; | ||
401 | u8 max_slots; | ||
402 | u8 max_interrupters; | ||
403 | u8 max_ports; | ||
404 | u8 isoc_threshold; | ||
405 | int event_ring_max; | ||
406 | int addr_64; | ||
407 | int page_size; | ||
408 | }; | ||
409 | |||
410 | /* convert between an HCD pointer and the corresponding EHCI_HCD */ | ||
411 | static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) | ||
412 | { | ||
413 | return (struct xhci_hcd *) (hcd->hcd_priv); | ||
414 | } | ||
415 | |||
416 | static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) | ||
417 | { | ||
418 | return container_of((void *) xhci, struct usb_hcd, hcd_priv); | ||
419 | } | ||
420 | |||
421 | #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING | ||
422 | #define XHCI_DEBUG 1 | ||
423 | #else | ||
424 | #define XHCI_DEBUG 0 | ||
425 | #endif | ||
426 | |||
427 | #define xhci_dbg(xhci, fmt, args...) \ | ||
428 | do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0) | ||
429 | #define xhci_info(xhci, fmt, args...) \ | ||
430 | do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0) | ||
431 | #define xhci_err(xhci, fmt, args...) \ | ||
432 | dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) | ||
433 | #define xhci_warn(xhci, fmt, args...) \ | ||
434 | dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) | ||
435 | |||
436 | /* TODO: copied from ehci.h - can be refactored? */ | ||
437 | /* xHCI spec says all registers are little endian */ | ||
438 | static inline unsigned int xhci_readl(const struct xhci_hcd *xhci, | ||
439 | __u32 __iomem *regs) | ||
440 | { | ||
441 | return readl(regs); | ||
442 | } | ||
443 | static inline void xhci_writel(const struct xhci_hcd *xhci, | ||
444 | const unsigned int val, __u32 __iomem *regs) | ||
445 | { | ||
446 | if (!in_interrupt()) | ||
447 | xhci_dbg(xhci, "`MEM_WRITE_DWORD(3'b000, 32'h%0x, 32'h%0x, 4'hf);\n", | ||
448 | (unsigned int) regs, val); | ||
449 | writel(val, regs); | ||
450 | } | ||
451 | |||
452 | #endif /* __LINUX_XHCI_HCD_H */ | ||