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-rw-r--r--drivers/net/tg3.c5
-rw-r--r--drivers/net/tg3.h13
2 files changed, 16 insertions, 2 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 46a3f86125b..e8def28877c 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -6719,6 +6719,11 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6719 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN | 6719 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
6720 PCIE_PWR_MGMT_L1_THRESH_4MS; 6720 PCIE_PWR_MGMT_L1_THRESH_4MS;
6721 tw32(PCIE_PWR_MGMT_THRESH, val); 6721 tw32(PCIE_PWR_MGMT_THRESH, val);
6722
6723 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
6724 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
6725
6726 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
6722 } 6727 }
6723 6728
6724 /* This works around an issue with Athlon chipsets on 6729 /* This works around an issue with Athlon chipsets on
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index b3347c41a1a..c613cbb40c2 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -214,9 +214,11 @@
214#define DUAL_MAC_CTRL_ID 0x00000004 214#define DUAL_MAC_CTRL_ID 0x00000004
215#define TG3PCI_PRODID_ASICREV 0x000000bc 215#define TG3PCI_PRODID_ASICREV 0x000000bc
216#define PROD_ID_ASIC_REV_MASK 0x0fffffff 216#define PROD_ID_ASIC_REV_MASK 0x0fffffff
217/* 0xc0 --> 0x100 unused */ 217/* 0xc0 --> 0x110 unused */
218 218
219/* 0x100 --> 0x200 unused */ 219#define TG3_CORR_ERR_STAT 0x00000110
220#define TG3_CORR_ERR_STAT_CLEAR 0xffffffff
221/* 0x114 --> 0x200 unused */
220 222
221/* Mailbox registers */ 223/* Mailbox registers */
222#define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */ 224#define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */
@@ -1696,11 +1698,18 @@
1696#define PCIE_TRANSACTION_CFG 0x00007c04 1698#define PCIE_TRANSACTION_CFG 0x00007c04
1697#define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000 1699#define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000
1698#define PCIE_TRANS_CFG_LOM 0x00000020 1700#define PCIE_TRANS_CFG_LOM 0x00000020
1701/* 0x7c08 --> 0x7d28 unused */
1699 1702
1700#define PCIE_PWR_MGMT_THRESH 0x00007d28 1703#define PCIE_PWR_MGMT_THRESH 0x00007d28
1701#define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00 1704#define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00
1702#define PCIE_PWR_MGMT_L1_THRESH_4MS 0x0000ff00 1705#define PCIE_PWR_MGMT_L1_THRESH_4MS 0x0000ff00
1703#define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN 0x01000000 1706#define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN 0x01000000
1707/* 0x7d2c --> 0x7e70 unused */
1708
1709#define TG3_PCIE_EIDLE_DELAY 0x00007e70
1710#define TG3_PCIE_EIDLE_DELAY_MASK 0x0000001f
1711#define TG3_PCIE_EIDLE_DELAY_13_CLKS 0x0000000c
1712/* 0x7e74 --> 0x8000 unused */
1704 1713
1705 1714
1706/* OTP bit definitions */ 1715/* OTP bit definitions */