diff options
-rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9003_eeprom.c | 22 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9003_eeprom.h | 37 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath9k/eeprom.c | 2 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath9k/eeprom.h | 45 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath9k/eeprom_4k.c | 36 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath9k/eeprom_9287.c | 54 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath9k/eeprom_def.c | 18 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath9k/hw.h | 1 |
8 files changed, 77 insertions, 138 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c index 1f5aa51b9ce..2fc3260579a 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c | |||
@@ -72,7 +72,7 @@ static const struct ar9300_eeprom ar9300_default = { | |||
72 | .regDmn = { LE16(0), LE16(0x1f) }, | 72 | .regDmn = { LE16(0), LE16(0x1f) }, |
73 | .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */ | 73 | .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */ |
74 | .opCapFlags = { | 74 | .opCapFlags = { |
75 | .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, | 75 | .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A, |
76 | .eepMisc = 0, | 76 | .eepMisc = 0, |
77 | }, | 77 | }, |
78 | .rfSilent = 0, | 78 | .rfSilent = 0, |
@@ -649,7 +649,7 @@ static const struct ar9300_eeprom ar9300_x113 = { | |||
649 | .regDmn = { LE16(0), LE16(0x1f) }, | 649 | .regDmn = { LE16(0), LE16(0x1f) }, |
650 | .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */ | 650 | .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */ |
651 | .opCapFlags = { | 651 | .opCapFlags = { |
652 | .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, | 652 | .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A, |
653 | .eepMisc = 0, | 653 | .eepMisc = 0, |
654 | }, | 654 | }, |
655 | .rfSilent = 0, | 655 | .rfSilent = 0, |
@@ -1227,7 +1227,7 @@ static const struct ar9300_eeprom ar9300_h112 = { | |||
1227 | .regDmn = { LE16(0), LE16(0x1f) }, | 1227 | .regDmn = { LE16(0), LE16(0x1f) }, |
1228 | .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */ | 1228 | .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */ |
1229 | .opCapFlags = { | 1229 | .opCapFlags = { |
1230 | .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, | 1230 | .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A, |
1231 | .eepMisc = 0, | 1231 | .eepMisc = 0, |
1232 | }, | 1232 | }, |
1233 | .rfSilent = 0, | 1233 | .rfSilent = 0, |
@@ -1805,7 +1805,7 @@ static const struct ar9300_eeprom ar9300_x112 = { | |||
1805 | .regDmn = { LE16(0), LE16(0x1f) }, | 1805 | .regDmn = { LE16(0), LE16(0x1f) }, |
1806 | .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */ | 1806 | .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */ |
1807 | .opCapFlags = { | 1807 | .opCapFlags = { |
1808 | .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, | 1808 | .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A, |
1809 | .eepMisc = 0, | 1809 | .eepMisc = 0, |
1810 | }, | 1810 | }, |
1811 | .rfSilent = 0, | 1811 | .rfSilent = 0, |
@@ -2382,7 +2382,7 @@ static const struct ar9300_eeprom ar9300_h116 = { | |||
2382 | .regDmn = { LE16(0), LE16(0x1f) }, | 2382 | .regDmn = { LE16(0), LE16(0x1f) }, |
2383 | .txrxMask = 0x33, /* 4 bits tx and 4 bits rx */ | 2383 | .txrxMask = 0x33, /* 4 bits tx and 4 bits rx */ |
2384 | .opCapFlags = { | 2384 | .opCapFlags = { |
2385 | .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, | 2385 | .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A, |
2386 | .eepMisc = 0, | 2386 | .eepMisc = 0, |
2387 | }, | 2387 | }, |
2388 | .rfSilent = 0, | 2388 | .rfSilent = 0, |
@@ -2974,7 +2974,7 @@ static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id) | |||
2974 | 2974 | ||
2975 | static u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz) | 2975 | static u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz) |
2976 | { | 2976 | { |
2977 | if (fbin == AR9300_BCHAN_UNUSED) | 2977 | if (fbin == AR5416_BCHAN_UNUSED) |
2978 | return fbin; | 2978 | return fbin; |
2979 | 2979 | ||
2980 | return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin)); | 2980 | return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin)); |
@@ -4485,7 +4485,7 @@ static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep, | |||
4485 | return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]); | 4485 | return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]); |
4486 | } | 4486 | } |
4487 | 4487 | ||
4488 | return AR9300_MAX_RATE_POWER; | 4488 | return MAX_RATE_POWER; |
4489 | } | 4489 | } |
4490 | 4490 | ||
4491 | /* | 4491 | /* |
@@ -4494,7 +4494,7 @@ static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep, | |||
4494 | static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep, | 4494 | static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep, |
4495 | u16 freq, int idx, bool is2GHz) | 4495 | u16 freq, int idx, bool is2GHz) |
4496 | { | 4496 | { |
4497 | u16 twiceMaxEdgePower = AR9300_MAX_RATE_POWER; | 4497 | u16 twiceMaxEdgePower = MAX_RATE_POWER; |
4498 | u8 *ctl_freqbin = is2GHz ? | 4498 | u8 *ctl_freqbin = is2GHz ? |
4499 | &eep->ctl_freqbin_2G[idx][0] : | 4499 | &eep->ctl_freqbin_2G[idx][0] : |
4500 | &eep->ctl_freqbin_5G[idx][0]; | 4500 | &eep->ctl_freqbin_5G[idx][0]; |
@@ -4504,7 +4504,7 @@ static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep, | |||
4504 | 4504 | ||
4505 | /* Get the edge power */ | 4505 | /* Get the edge power */ |
4506 | for (edge = 0; | 4506 | for (edge = 0; |
4507 | (edge < num_edges) && (ctl_freqbin[edge] != AR9300_BCHAN_UNUSED); | 4507 | (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED); |
4508 | edge++) { | 4508 | edge++) { |
4509 | /* | 4509 | /* |
4510 | * If there's an exact channel match or an inband flag set | 4510 | * If there's an exact channel match or an inband flag set |
@@ -4542,9 +4542,9 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah, | |||
4542 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); | 4542 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
4543 | struct ath_common *common = ath9k_hw_common(ah); | 4543 | struct ath_common *common = ath9k_hw_common(ah); |
4544 | struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep; | 4544 | struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep; |
4545 | u16 twiceMaxEdgePower = AR9300_MAX_RATE_POWER; | 4545 | u16 twiceMaxEdgePower = MAX_RATE_POWER; |
4546 | static const u16 tpScaleReductionTable[5] = { | 4546 | static const u16 tpScaleReductionTable[5] = { |
4547 | 0, 3, 6, 9, AR9300_MAX_RATE_POWER | 4547 | 0, 3, 6, 9, MAX_RATE_POWER |
4548 | }; | 4548 | }; |
4549 | int i; | 4549 | int i; |
4550 | int16_t twiceLargestAntenna; | 4550 | int16_t twiceLargestAntenna; |
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h index 33503217dab..620821ea692 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h | |||
@@ -20,48 +20,17 @@ | |||
20 | /* #define AR9300_NUM_CTLS 21 */ | 20 | /* #define AR9300_NUM_CTLS 21 */ |
21 | #define AR9300_NUM_CTLS_5G 9 | 21 | #define AR9300_NUM_CTLS_5G 9 |
22 | #define AR9300_NUM_CTLS_2G 12 | 22 | #define AR9300_NUM_CTLS_2G 12 |
23 | #define AR9300_CTL_MODE_M 0xF | ||
24 | #define AR9300_NUM_BAND_EDGES_5G 8 | 23 | #define AR9300_NUM_BAND_EDGES_5G 8 |
25 | #define AR9300_NUM_BAND_EDGES_2G 4 | 24 | #define AR9300_NUM_BAND_EDGES_2G 4 |
26 | #define AR9300_NUM_PD_GAINS 4 | ||
27 | #define AR9300_PD_GAINS_IN_MASK 4 | ||
28 | #define AR9300_PD_GAIN_ICEPTS 5 | ||
29 | #define AR9300_EEPROM_MODAL_SPURS 5 | ||
30 | #define AR9300_MAX_RATE_POWER 63 | ||
31 | #define AR9300_NUM_PDADC_VALUES 128 | ||
32 | #define AR9300_NUM_RATES 16 | ||
33 | #define AR9300_BCHAN_UNUSED 0xFF | ||
34 | #define AR9300_MAX_PWR_RANGE_IN_HALF_DB 64 | ||
35 | #define AR9300_OPFLAGS_11A 0x01 | ||
36 | #define AR9300_OPFLAGS_11G 0x02 | ||
37 | #define AR9300_OPFLAGS_5G_HT40 0x04 | ||
38 | #define AR9300_OPFLAGS_2G_HT40 0x08 | ||
39 | #define AR9300_OPFLAGS_5G_HT20 0x10 | ||
40 | #define AR9300_OPFLAGS_2G_HT20 0x20 | ||
41 | #define AR9300_EEPMISC_BIG_ENDIAN 0x01 | 25 | #define AR9300_EEPMISC_BIG_ENDIAN 0x01 |
42 | #define AR9300_EEPMISC_WOW 0x02 | 26 | #define AR9300_EEPMISC_WOW 0x02 |
43 | #define AR9300_CUSTOMER_DATA_SIZE 20 | 27 | #define AR9300_CUSTOMER_DATA_SIZE 20 |
44 | 28 | ||
45 | #define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5)) | ||
46 | #define FBIN2FREQ(x, y) ((y) ? (2300 + x) : (4800 + 5 * x)) | 29 | #define FBIN2FREQ(x, y) ((y) ? (2300 + x) : (4800 + 5 * x)) |
47 | #define AR9300_MAX_CHAINS 3 | 30 | #define AR9300_MAX_CHAINS 3 |
48 | #define AR9300_ANT_16S 25 | 31 | #define AR9300_ANT_16S 25 |
49 | #define AR9300_FUTURE_MODAL_SZ 6 | 32 | #define AR9300_FUTURE_MODAL_SZ 6 |
50 | 33 | ||
51 | #define AR9300_NUM_ANT_CHAIN_FIELDS 7 | ||
52 | #define AR9300_NUM_ANT_COMMON_FIELDS 4 | ||
53 | #define AR9300_SIZE_ANT_CHAIN_FIELD 3 | ||
54 | #define AR9300_SIZE_ANT_COMMON_FIELD 4 | ||
55 | #define AR9300_ANT_CHAIN_MASK 0x7 | ||
56 | #define AR9300_ANT_COMMON_MASK 0xf | ||
57 | #define AR9300_CHAIN_0_IDX 0 | ||
58 | #define AR9300_CHAIN_1_IDX 1 | ||
59 | #define AR9300_CHAIN_2_IDX 2 | ||
60 | |||
61 | #define AR928X_NUM_ANT_CHAIN_FIELDS 6 | ||
62 | #define AR928X_SIZE_ANT_CHAIN_FIELD 2 | ||
63 | #define AR928X_ANT_CHAIN_MASK 0x3 | ||
64 | |||
65 | /* Delta from which to start power to pdadc table */ | 34 | /* Delta from which to start power to pdadc table */ |
66 | /* This offset is used in both open loop and closed loop power control | 35 | /* This offset is used in both open loop and closed loop power control |
67 | * schemes. In open loop power control, it is not really needed, but for | 36 | * schemes. In open loop power control, it is not really needed, but for |
@@ -71,12 +40,8 @@ | |||
71 | */ | 40 | */ |
72 | #define AR9300_PWR_TABLE_OFFSET 0 | 41 | #define AR9300_PWR_TABLE_OFFSET 0 |
73 | 42 | ||
74 | /* enable flags for voltage and temp compensation */ | ||
75 | #define ENABLE_TEMP_COMPENSATION 0x01 | ||
76 | #define ENABLE_VOLT_COMPENSATION 0x02 | ||
77 | /* byte addressable */ | 43 | /* byte addressable */ |
78 | #define AR9300_EEPROM_SIZE (16*1024) | 44 | #define AR9300_EEPROM_SIZE (16*1024) |
79 | #define FIXED_CCA_THRESHOLD 15 | ||
80 | 45 | ||
81 | #define AR9300_BASE_ADDR_4K 0xfff | 46 | #define AR9300_BASE_ADDR_4K 0xfff |
82 | #define AR9300_BASE_ADDR 0x3ff | 47 | #define AR9300_BASE_ADDR 0x3ff |
@@ -226,7 +191,7 @@ struct ar9300_modal_eep_header { | |||
226 | int8_t tempSlope; | 191 | int8_t tempSlope; |
227 | int8_t voltSlope; | 192 | int8_t voltSlope; |
228 | /* spur channels in usual fbin coding format */ | 193 | /* spur channels in usual fbin coding format */ |
229 | u8 spurChans[AR9300_EEPROM_MODAL_SPURS]; | 194 | u8 spurChans[AR_EEPROM_MODAL_SPURS]; |
230 | /* 3 Check if the register is per chain */ | 195 | /* 3 Check if the register is per chain */ |
231 | int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS]; | 196 | int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS]; |
232 | u8 ob[AR9300_MAX_CHAINS]; | 197 | u8 ob[AR9300_MAX_CHAINS]; |
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.c b/drivers/net/wireless/ath/ath9k/eeprom.c index fda533cfd88..3d99b6cdd2c 100644 --- a/drivers/net/wireless/ath/ath9k/eeprom.c +++ b/drivers/net/wireless/ath/ath9k/eeprom.c | |||
@@ -234,7 +234,7 @@ void ath9k_hw_get_target_powers(struct ath_hw *ah, | |||
234 | u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower, | 234 | u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower, |
235 | bool is2GHz, int num_band_edges) | 235 | bool is2GHz, int num_band_edges) |
236 | { | 236 | { |
237 | u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; | 237 | u16 twiceMaxEdgePower = MAX_RATE_POWER; |
238 | int i; | 238 | int i; |
239 | 239 | ||
240 | for (i = 0; (i < num_band_edges) && | 240 | for (i = 0; (i < num_band_edges) && |
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.h b/drivers/net/wireless/ath/ath9k/eeprom.h index 8b9885b5243..833dd0c3feb 100644 --- a/drivers/net/wireless/ath/ath9k/eeprom.h +++ b/drivers/net/wireless/ath/ath9k/eeprom.h | |||
@@ -17,6 +17,8 @@ | |||
17 | #ifndef EEPROM_H | 17 | #ifndef EEPROM_H |
18 | #define EEPROM_H | 18 | #define EEPROM_H |
19 | 19 | ||
20 | #define AR_EEPROM_MODAL_SPURS 5 | ||
21 | |||
20 | #include "../ath.h" | 22 | #include "../ath.h" |
21 | #include <net/cfg80211.h> | 23 | #include <net/cfg80211.h> |
22 | #include "ar9003_eeprom.h" | 24 | #include "ar9003_eeprom.h" |
@@ -149,8 +151,6 @@ | |||
149 | #define AR5416_NUM_PD_GAINS 4 | 151 | #define AR5416_NUM_PD_GAINS 4 |
150 | #define AR5416_PD_GAINS_IN_MASK 4 | 152 | #define AR5416_PD_GAINS_IN_MASK 4 |
151 | #define AR5416_PD_GAIN_ICEPTS 5 | 153 | #define AR5416_PD_GAIN_ICEPTS 5 |
152 | #define AR5416_EEPROM_MODAL_SPURS 5 | ||
153 | #define AR5416_MAX_RATE_POWER 63 | ||
154 | #define AR5416_NUM_PDADC_VALUES 128 | 154 | #define AR5416_NUM_PDADC_VALUES 128 |
155 | #define AR5416_BCHAN_UNUSED 0xFF | 155 | #define AR5416_BCHAN_UNUSED 0xFF |
156 | #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64 | 156 | #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64 |
@@ -175,8 +175,6 @@ | |||
175 | #define AR5416_EEP4K_NUM_CTLS 12 | 175 | #define AR5416_EEP4K_NUM_CTLS 12 |
176 | #define AR5416_EEP4K_NUM_BAND_EDGES 4 | 176 | #define AR5416_EEP4K_NUM_BAND_EDGES 4 |
177 | #define AR5416_EEP4K_NUM_PD_GAINS 2 | 177 | #define AR5416_EEP4K_NUM_PD_GAINS 2 |
178 | #define AR5416_EEP4K_PD_GAINS_IN_MASK 4 | ||
179 | #define AR5416_EEP4K_PD_GAIN_ICEPTS 5 | ||
180 | #define AR5416_EEP4K_MAX_CHAINS 1 | 178 | #define AR5416_EEP4K_MAX_CHAINS 1 |
181 | 179 | ||
182 | #define AR9280_TX_GAIN_TABLE_SIZE 22 | 180 | #define AR9280_TX_GAIN_TABLE_SIZE 22 |
@@ -198,35 +196,12 @@ | |||
198 | #define AR9287_NUM_2G_40_TARGET_POWERS 3 | 196 | #define AR9287_NUM_2G_40_TARGET_POWERS 3 |
199 | #define AR9287_NUM_CTLS 12 | 197 | #define AR9287_NUM_CTLS 12 |
200 | #define AR9287_NUM_BAND_EDGES 4 | 198 | #define AR9287_NUM_BAND_EDGES 4 |
201 | #define AR9287_NUM_PD_GAINS 4 | ||
202 | #define AR9287_PD_GAINS_IN_MASK 4 | ||
203 | #define AR9287_PD_GAIN_ICEPTS 1 | 199 | #define AR9287_PD_GAIN_ICEPTS 1 |
204 | #define AR9287_EEPROM_MODAL_SPURS 5 | ||
205 | #define AR9287_MAX_RATE_POWER 63 | ||
206 | #define AR9287_NUM_PDADC_VALUES 128 | ||
207 | #define AR9287_NUM_RATES 16 | ||
208 | #define AR9287_BCHAN_UNUSED 0xFF | ||
209 | #define AR9287_MAX_PWR_RANGE_IN_HALF_DB 64 | ||
210 | #define AR9287_OPFLAGS_11A 0x01 | ||
211 | #define AR9287_OPFLAGS_11G 0x02 | ||
212 | #define AR9287_OPFLAGS_2G_HT40 0x08 | ||
213 | #define AR9287_OPFLAGS_2G_HT20 0x20 | ||
214 | #define AR9287_OPFLAGS_5G_HT40 0x04 | ||
215 | #define AR9287_OPFLAGS_5G_HT20 0x10 | ||
216 | #define AR9287_EEPMISC_BIG_ENDIAN 0x01 | 200 | #define AR9287_EEPMISC_BIG_ENDIAN 0x01 |
217 | #define AR9287_EEPMISC_WOW 0x02 | 201 | #define AR9287_EEPMISC_WOW 0x02 |
218 | #define AR9287_MAX_CHAINS 2 | 202 | #define AR9287_MAX_CHAINS 2 |
219 | #define AR9287_ANT_16S 32 | 203 | #define AR9287_ANT_16S 32 |
220 | #define AR9287_custdatasize 20 | 204 | |
221 | |||
222 | #define AR9287_NUM_ANT_CHAIN_FIELDS 6 | ||
223 | #define AR9287_NUM_ANT_COMMON_FIELDS 4 | ||
224 | #define AR9287_SIZE_ANT_CHAIN_FIELD 2 | ||
225 | #define AR9287_SIZE_ANT_COMMON_FIELD 4 | ||
226 | #define AR9287_ANT_CHAIN_MASK 0x3 | ||
227 | #define AR9287_ANT_COMMON_MASK 0xf | ||
228 | #define AR9287_CHAIN_0_IDX 0 | ||
229 | #define AR9287_CHAIN_1_IDX 1 | ||
230 | #define AR9287_DATA_SZ 32 | 205 | #define AR9287_DATA_SZ 32 |
231 | 206 | ||
232 | #define AR9287_PWR_TABLE_OFFSET_DB -5 | 207 | #define AR9287_PWR_TABLE_OFFSET_DB -5 |
@@ -396,7 +371,7 @@ struct modal_eep_header { | |||
396 | u16 xpaBiasLvlFreq[3]; | 371 | u16 xpaBiasLvlFreq[3]; |
397 | u8 futureModal[6]; | 372 | u8 futureModal[6]; |
398 | 373 | ||
399 | struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS]; | 374 | struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS]; |
400 | } __packed; | 375 | } __packed; |
401 | 376 | ||
402 | struct calDataPerFreqOpLoop { | 377 | struct calDataPerFreqOpLoop { |
@@ -464,7 +439,7 @@ struct modal_eep_4k_header { | |||
464 | u8 db2_4:4, reserved:4; | 439 | u8 db2_4:4, reserved:4; |
465 | #endif | 440 | #endif |
466 | u8 futureModal[4]; | 441 | u8 futureModal[4]; |
467 | struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS]; | 442 | struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS]; |
468 | } __packed; | 443 | } __packed; |
469 | 444 | ||
470 | struct base_eep_ar9287_header { | 445 | struct base_eep_ar9287_header { |
@@ -522,7 +497,7 @@ struct modal_eep_ar9287_header { | |||
522 | u8 ob_qam; | 497 | u8 ob_qam; |
523 | u8 ob_pal_off; | 498 | u8 ob_pal_off; |
524 | u8 futureModal[30]; | 499 | u8 futureModal[30]; |
525 | struct spur_chan spurChans[AR9287_EEPROM_MODAL_SPURS]; | 500 | struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS]; |
526 | } __packed; | 501 | } __packed; |
527 | 502 | ||
528 | struct cal_data_per_freq { | 503 | struct cal_data_per_freq { |
@@ -531,8 +506,8 @@ struct cal_data_per_freq { | |||
531 | } __packed; | 506 | } __packed; |
532 | 507 | ||
533 | struct cal_data_per_freq_4k { | 508 | struct cal_data_per_freq_4k { |
534 | u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS]; | 509 | u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; |
535 | u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS]; | 510 | u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; |
536 | } __packed; | 511 | } __packed; |
537 | 512 | ||
538 | struct cal_target_power_leg { | 513 | struct cal_target_power_leg { |
@@ -558,8 +533,8 @@ struct cal_data_op_loop_ar9287 { | |||
558 | } __packed; | 533 | } __packed; |
559 | 534 | ||
560 | struct cal_data_per_freq_ar9287 { | 535 | struct cal_data_per_freq_ar9287 { |
561 | u8 pwrPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]; | 536 | u8 pwrPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]; |
562 | u8 vpdPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]; | 537 | u8 vpdPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]; |
563 | } __packed; | 538 | } __packed; |
564 | 539 | ||
565 | union cal_data_per_freq_ar9287_u { | 540 | union cal_data_per_freq_ar9287_u { |
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_4k.c b/drivers/net/wireless/ath/ath9k/eeprom_4k.c index 939fc7af86f..6102309bc16 100644 --- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c +++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c | |||
@@ -153,7 +153,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) | |||
153 | eep->modalHeader.antCtrlChain[i] = integer; | 153 | eep->modalHeader.antCtrlChain[i] = integer; |
154 | } | 154 | } |
155 | 155 | ||
156 | for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { | 156 | for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { |
157 | word = swab16(eep->modalHeader.spurChans[i].spurChan); | 157 | word = swab16(eep->modalHeader.spurChans[i].spurChan); |
158 | eep->modalHeader.spurChans[i].spurChan = word; | 158 | eep->modalHeader.spurChans[i].spurChan = word; |
159 | } | 159 | } |
@@ -258,7 +258,7 @@ static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah, | |||
258 | struct chan_centers centers; | 258 | struct chan_centers centers; |
259 | #define PD_GAIN_BOUNDARY_DEFAULT 58; | 259 | #define PD_GAIN_BOUNDARY_DEFAULT 58; |
260 | 260 | ||
261 | memset(&minPwrT4, 0, AR9287_NUM_PD_GAINS); | 261 | memset(&minPwrT4, 0, AR5416_NUM_PD_GAINS); |
262 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | 262 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); |
263 | 263 | ||
264 | for (numPiers = 0; numPiers < availPiers; numPiers++) { | 264 | for (numPiers = 0; numPiers < availPiers; numPiers++) { |
@@ -278,7 +278,7 @@ static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah, | |||
278 | ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], | 278 | ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], |
279 | pRawDataSet[idxL].pwrPdg[i], | 279 | pRawDataSet[idxL].pwrPdg[i], |
280 | pRawDataSet[idxL].vpdPdg[i], | 280 | pRawDataSet[idxL].vpdPdg[i], |
281 | AR5416_EEP4K_PD_GAIN_ICEPTS, | 281 | AR5416_PD_GAIN_ICEPTS, |
282 | vpdTableI[i]); | 282 | vpdTableI[i]); |
283 | } | 283 | } |
284 | } else { | 284 | } else { |
@@ -291,17 +291,17 @@ static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah, | |||
291 | minPwrT4[i] = max(pPwrL[0], pPwrR[0]); | 291 | minPwrT4[i] = max(pPwrL[0], pPwrR[0]); |
292 | 292 | ||
293 | maxPwrT4[i] = | 293 | maxPwrT4[i] = |
294 | min(pPwrL[AR5416_EEP4K_PD_GAIN_ICEPTS - 1], | 294 | min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], |
295 | pPwrR[AR5416_EEP4K_PD_GAIN_ICEPTS - 1]); | 295 | pPwrR[AR5416_PD_GAIN_ICEPTS - 1]); |
296 | 296 | ||
297 | 297 | ||
298 | ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], | 298 | ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], |
299 | pPwrL, pVpdL, | 299 | pPwrL, pVpdL, |
300 | AR5416_EEP4K_PD_GAIN_ICEPTS, | 300 | AR5416_PD_GAIN_ICEPTS, |
301 | vpdTableL[i]); | 301 | vpdTableL[i]); |
302 | ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], | 302 | ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], |
303 | pPwrR, pVpdR, | 303 | pPwrR, pVpdR, |
304 | AR5416_EEP4K_PD_GAIN_ICEPTS, | 304 | AR5416_PD_GAIN_ICEPTS, |
305 | vpdTableR[i]); | 305 | vpdTableR[i]); |
306 | 306 | ||
307 | for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) { | 307 | for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) { |
@@ -328,7 +328,7 @@ static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah, | |||
328 | (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4); | 328 | (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4); |
329 | 329 | ||
330 | pPdGainBoundaries[i] = | 330 | pPdGainBoundaries[i] = |
331 | min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]); | 331 | min((u16)MAX_RATE_POWER, pPdGainBoundaries[i]); |
332 | 332 | ||
333 | if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) { | 333 | if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) { |
334 | minDelta = pPdGainBoundaries[0] - 23; | 334 | minDelta = pPdGainBoundaries[0] - 23; |
@@ -380,7 +380,7 @@ static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah, | |||
380 | } | 380 | } |
381 | } | 381 | } |
382 | 382 | ||
383 | while (i < AR5416_EEP4K_PD_GAINS_IN_MASK) { | 383 | while (i < AR5416_PD_GAINS_IN_MASK) { |
384 | pPdGainBoundaries[i] = PD_GAIN_BOUNDARY_DEFAULT; | 384 | pPdGainBoundaries[i] = PD_GAIN_BOUNDARY_DEFAULT; |
385 | i++; | 385 | i++; |
386 | } | 386 | } |
@@ -404,7 +404,7 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah, | |||
404 | u8 *pCalBChans = NULL; | 404 | u8 *pCalBChans = NULL; |
405 | u16 pdGainOverlap_t2; | 405 | u16 pdGainOverlap_t2; |
406 | static u8 pdadcValues[AR5416_NUM_PDADC_VALUES]; | 406 | static u8 pdadcValues[AR5416_NUM_PDADC_VALUES]; |
407 | u16 gainBoundaries[AR5416_EEP4K_PD_GAINS_IN_MASK]; | 407 | u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK]; |
408 | u16 numPiers, i, j; | 408 | u16 numPiers, i, j; |
409 | u16 numXpdGain, xpdMask; | 409 | u16 numXpdGain, xpdMask; |
410 | u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 }; | 410 | u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 }; |
@@ -426,12 +426,12 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah, | |||
426 | 426 | ||
427 | numXpdGain = 0; | 427 | numXpdGain = 0; |
428 | 428 | ||
429 | for (i = 1; i <= AR5416_EEP4K_PD_GAINS_IN_MASK; i++) { | 429 | for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { |
430 | if ((xpdMask >> (AR5416_EEP4K_PD_GAINS_IN_MASK - i)) & 1) { | 430 | if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { |
431 | if (numXpdGain >= AR5416_EEP4K_NUM_PD_GAINS) | 431 | if (numXpdGain >= AR5416_EEP4K_NUM_PD_GAINS) |
432 | break; | 432 | break; |
433 | xpdGainValues[numXpdGain] = | 433 | xpdGainValues[numXpdGain] = |
434 | (u16)(AR5416_EEP4K_PD_GAINS_IN_MASK - i); | 434 | (u16)(AR5416_PD_GAINS_IN_MASK - i); |
435 | numXpdGain++; | 435 | numXpdGain++; |
436 | } | 436 | } |
437 | } | 437 | } |
@@ -528,7 +528,7 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah, | |||
528 | int i; | 528 | int i; |
529 | int16_t twiceLargestAntenna; | 529 | int16_t twiceLargestAntenna; |
530 | u16 twiceMinEdgePower; | 530 | u16 twiceMinEdgePower; |
531 | u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; | 531 | u16 twiceMaxEdgePower = MAX_RATE_POWER; |
532 | u16 scaledPower = 0, minCtlPower, maxRegAllowedPower; | 532 | u16 scaledPower = 0, minCtlPower, maxRegAllowedPower; |
533 | u16 numCtlModes; | 533 | u16 numCtlModes; |
534 | const u16 *pCtlMode; | 534 | const u16 *pCtlMode; |
@@ -537,7 +537,7 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah, | |||
537 | struct cal_ctl_data_4k *rep; | 537 | struct cal_ctl_data_4k *rep; |
538 | struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; | 538 | struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; |
539 | static const u16 tpScaleReductionTable[5] = | 539 | static const u16 tpScaleReductionTable[5] = |
540 | { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; | 540 | { 0, 3, 6, 9, MAX_RATE_POWER }; |
541 | struct cal_target_power_leg targetPowerOfdm, targetPowerCck = { | 541 | struct cal_target_power_leg targetPowerOfdm, targetPowerCck = { |
542 | 0, { 0, 0, 0, 0} | 542 | 0, { 0, 0, 0, 0} |
543 | }; | 543 | }; |
@@ -613,7 +613,7 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah, | |||
613 | 613 | ||
614 | if (ah->eep_ops->get_eeprom_ver(ah) == 14 && | 614 | if (ah->eep_ops->get_eeprom_ver(ah) == 14 && |
615 | ah->eep_ops->get_eeprom_rev(ah) <= 2) | 615 | ah->eep_ops->get_eeprom_rev(ah) <= 2) |
616 | twiceMaxEdgePower = AR5416_MAX_RATE_POWER; | 616 | twiceMaxEdgePower = MAX_RATE_POWER; |
617 | 617 | ||
618 | for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) && | 618 | for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) && |
619 | pEepData->ctlIndex[i]; i++) { | 619 | pEepData->ctlIndex[i]; i++) { |
@@ -752,8 +752,8 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah, | |||
752 | regulatory->max_power_level = 0; | 752 | regulatory->max_power_level = 0; |
753 | for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { | 753 | for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { |
754 | ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); | 754 | ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); |
755 | if (ratesArray[i] > AR5416_MAX_RATE_POWER) | 755 | if (ratesArray[i] > MAX_RATE_POWER) |
756 | ratesArray[i] = AR5416_MAX_RATE_POWER; | 756 | ratesArray[i] = MAX_RATE_POWER; |
757 | 757 | ||
758 | if (ratesArray[i] > regulatory->max_power_level) | 758 | if (ratesArray[i] > regulatory->max_power_level) |
759 | regulatory->max_power_level = ratesArray[i]; | 759 | regulatory->max_power_level = ratesArray[i]; |
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_9287.c b/drivers/net/wireless/ath/ath9k/eeprom_9287.c index 065402f2e40..4ba07da3745 100644 --- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c +++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c | |||
@@ -150,7 +150,7 @@ static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah) | |||
150 | eep->modalHeader.antCtrlChain[i] = integer; | 150 | eep->modalHeader.antCtrlChain[i] = integer; |
151 | } | 151 | } |
152 | 152 | ||
153 | for (i = 0; i < AR9287_EEPROM_MODAL_SPURS; i++) { | 153 | for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { |
154 | word = swab16(eep->modalHeader.spurChans[i].spurChan); | 154 | word = swab16(eep->modalHeader.spurChans[i].spurChan); |
155 | eep->modalHeader.spurChans[i].spurChan = word; | 155 | eep->modalHeader.spurChans[i].spurChan = word; |
156 | } | 156 | } |
@@ -236,8 +236,8 @@ static void ath9k_hw_get_ar9287_gain_boundaries_pdadcs(struct ath_hw *ah, | |||
236 | int16_t ss; | 236 | int16_t ss; |
237 | u16 idxL = 0, idxR = 0, numPiers; | 237 | u16 idxL = 0, idxR = 0, numPiers; |
238 | u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR; | 238 | u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR; |
239 | u8 minPwrT4[AR9287_NUM_PD_GAINS]; | 239 | u8 minPwrT4[AR5416_NUM_PD_GAINS]; |
240 | u8 maxPwrT4[AR9287_NUM_PD_GAINS]; | 240 | u8 maxPwrT4[AR5416_NUM_PD_GAINS]; |
241 | int16_t vpdStep; | 241 | int16_t vpdStep; |
242 | int16_t tmpVal; | 242 | int16_t tmpVal; |
243 | u16 sizeCurrVpdTable, maxIndex, tgtIndex; | 243 | u16 sizeCurrVpdTable, maxIndex, tgtIndex; |
@@ -251,11 +251,11 @@ static void ath9k_hw_get_ar9287_gain_boundaries_pdadcs(struct ath_hw *ah, | |||
251 | static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS] | 251 | static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS] |
252 | [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; | 252 | [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; |
253 | 253 | ||
254 | memset(&minPwrT4, 0, AR9287_NUM_PD_GAINS); | 254 | memset(&minPwrT4, 0, AR5416_NUM_PD_GAINS); |
255 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | 255 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); |
256 | 256 | ||
257 | for (numPiers = 0; numPiers < availPiers; numPiers++) { | 257 | for (numPiers = 0; numPiers < availPiers; numPiers++) { |
258 | if (bChans[numPiers] == AR9287_BCHAN_UNUSED) | 258 | if (bChans[numPiers] == AR5416_BCHAN_UNUSED) |
259 | break; | 259 | break; |
260 | } | 260 | } |
261 | 261 | ||
@@ -314,7 +314,7 @@ static void ath9k_hw_get_ar9287_gain_boundaries_pdadcs(struct ath_hw *ah, | |||
314 | pPdGainBoundaries[i] = | 314 | pPdGainBoundaries[i] = |
315 | (u16)((maxPwrT4[i] + minPwrT4[i+1]) / 4); | 315 | (u16)((maxPwrT4[i] + minPwrT4[i+1]) / 4); |
316 | 316 | ||
317 | pPdGainBoundaries[i] = min((u16)AR5416_MAX_RATE_POWER, | 317 | pPdGainBoundaries[i] = min((u16)MAX_RATE_POWER, |
318 | pPdGainBoundaries[i]); | 318 | pPdGainBoundaries[i]); |
319 | 319 | ||
320 | 320 | ||
@@ -334,7 +334,7 @@ static void ath9k_hw_get_ar9287_gain_boundaries_pdadcs(struct ath_hw *ah, | |||
334 | vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]); | 334 | vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]); |
335 | vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); | 335 | vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); |
336 | 336 | ||
337 | while ((ss < 0) && (k < (AR9287_NUM_PDADC_VALUES - 1))) { | 337 | while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { |
338 | tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep); | 338 | tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep); |
339 | pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal); | 339 | pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal); |
340 | ss++; | 340 | ss++; |
@@ -346,7 +346,7 @@ static void ath9k_hw_get_ar9287_gain_boundaries_pdadcs(struct ath_hw *ah, | |||
346 | maxIndex = (tgtIndex < sizeCurrVpdTable) ? | 346 | maxIndex = (tgtIndex < sizeCurrVpdTable) ? |
347 | tgtIndex : sizeCurrVpdTable; | 347 | tgtIndex : sizeCurrVpdTable; |
348 | 348 | ||
349 | while ((ss < maxIndex) && (k < (AR9287_NUM_PDADC_VALUES - 1))) | 349 | while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) |
350 | pPDADCValues[k++] = vpdTableI[i][ss++]; | 350 | pPDADCValues[k++] = vpdTableI[i][ss++]; |
351 | 351 | ||
352 | vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - | 352 | vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - |
@@ -355,7 +355,7 @@ static void ath9k_hw_get_ar9287_gain_boundaries_pdadcs(struct ath_hw *ah, | |||
355 | 355 | ||
356 | if (tgtIndex > maxIndex) { | 356 | if (tgtIndex > maxIndex) { |
357 | while ((ss <= tgtIndex) && | 357 | while ((ss <= tgtIndex) && |
358 | (k < (AR9287_NUM_PDADC_VALUES - 1))) { | 358 | (k < (AR5416_NUM_PDADC_VALUES - 1))) { |
359 | tmpVal = (int16_t) TMP_VAL_VPD_TABLE; | 359 | tmpVal = (int16_t) TMP_VAL_VPD_TABLE; |
360 | pPDADCValues[k++] = | 360 | pPDADCValues[k++] = |
361 | (u8)((tmpVal > 255) ? 255 : tmpVal); | 361 | (u8)((tmpVal > 255) ? 255 : tmpVal); |
@@ -364,12 +364,12 @@ static void ath9k_hw_get_ar9287_gain_boundaries_pdadcs(struct ath_hw *ah, | |||
364 | } | 364 | } |
365 | } | 365 | } |
366 | 366 | ||
367 | while (i < AR9287_PD_GAINS_IN_MASK) { | 367 | while (i < AR5416_PD_GAINS_IN_MASK) { |
368 | pPdGainBoundaries[i] = pPdGainBoundaries[i-1]; | 368 | pPdGainBoundaries[i] = pPdGainBoundaries[i-1]; |
369 | i++; | 369 | i++; |
370 | } | 370 | } |
371 | 371 | ||
372 | while (k < AR9287_NUM_PDADC_VALUES) { | 372 | while (k < AR5416_NUM_PDADC_VALUES) { |
373 | pPDADCValues[k] = pPDADCValues[k-1]; | 373 | pPDADCValues[k] = pPDADCValues[k-1]; |
374 | k++; | 374 | k++; |
375 | } | 375 | } |
@@ -389,7 +389,7 @@ static void ar9287_eeprom_get_tx_gain_index(struct ath_hw *ah, | |||
389 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | 389 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); |
390 | 390 | ||
391 | for (numPiers = 0; numPiers < availPiers; numPiers++) { | 391 | for (numPiers = 0; numPiers < availPiers; numPiers++) { |
392 | if (pCalChans[numPiers] == AR9287_BCHAN_UNUSED) | 392 | if (pCalChans[numPiers] == AR5416_BCHAN_UNUSED) |
393 | break; | 393 | break; |
394 | } | 394 | } |
395 | 395 | ||
@@ -455,11 +455,11 @@ static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah, | |||
455 | struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop; | 455 | struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop; |
456 | u8 *pCalBChans = NULL; | 456 | u8 *pCalBChans = NULL; |
457 | u16 pdGainOverlap_t2; | 457 | u16 pdGainOverlap_t2; |
458 | u8 pdadcValues[AR9287_NUM_PDADC_VALUES]; | 458 | u8 pdadcValues[AR5416_NUM_PDADC_VALUES]; |
459 | u16 gainBoundaries[AR9287_PD_GAINS_IN_MASK]; | 459 | u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK]; |
460 | u16 numPiers = 0, i, j; | 460 | u16 numPiers = 0, i, j; |
461 | u16 numXpdGain, xpdMask; | 461 | u16 numXpdGain, xpdMask; |
462 | u16 xpdGainValues[AR9287_NUM_PD_GAINS] = {0, 0, 0, 0}; | 462 | u16 xpdGainValues[AR5416_NUM_PD_GAINS] = {0, 0, 0, 0}; |
463 | u32 reg32, regOffset, regChainOffset, regval; | 463 | u32 reg32, regOffset, regChainOffset, regval; |
464 | int16_t modalIdx, diff = 0; | 464 | int16_t modalIdx, diff = 0; |
465 | struct ar9287_eeprom *pEepData = &ah->eeprom.map9287; | 465 | struct ar9287_eeprom *pEepData = &ah->eeprom.map9287; |
@@ -487,12 +487,12 @@ static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah, | |||
487 | numXpdGain = 0; | 487 | numXpdGain = 0; |
488 | 488 | ||
489 | /* Calculate the value of xpdgains from the xpdGain Mask */ | 489 | /* Calculate the value of xpdgains from the xpdGain Mask */ |
490 | for (i = 1; i <= AR9287_PD_GAINS_IN_MASK; i++) { | 490 | for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { |
491 | if ((xpdMask >> (AR9287_PD_GAINS_IN_MASK - i)) & 1) { | 491 | if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { |
492 | if (numXpdGain >= AR9287_NUM_PD_GAINS) | 492 | if (numXpdGain >= AR5416_NUM_PD_GAINS) |
493 | break; | 493 | break; |
494 | xpdGainValues[numXpdGain] = | 494 | xpdGainValues[numXpdGain] = |
495 | (u16)(AR9287_PD_GAINS_IN_MASK-i); | 495 | (u16)(AR5416_PD_GAINS_IN_MASK-i); |
496 | numXpdGain++; | 496 | numXpdGain++; |
497 | } | 497 | } |
498 | } | 498 | } |
@@ -561,13 +561,13 @@ static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah, | |||
561 | (int32_t)AR9287_PWR_TABLE_OFFSET_DB); | 561 | (int32_t)AR9287_PWR_TABLE_OFFSET_DB); |
562 | diff *= 2; | 562 | diff *= 2; |
563 | 563 | ||
564 | for (j = 0; j < ((u16)AR9287_NUM_PDADC_VALUES-diff); j++) | 564 | for (j = 0; j < ((u16)AR5416_NUM_PDADC_VALUES-diff); j++) |
565 | pdadcValues[j] = pdadcValues[j+diff]; | 565 | pdadcValues[j] = pdadcValues[j+diff]; |
566 | 566 | ||
567 | for (j = (u16)(AR9287_NUM_PDADC_VALUES-diff); | 567 | for (j = (u16)(AR5416_NUM_PDADC_VALUES-diff); |
568 | j < AR9287_NUM_PDADC_VALUES; j++) | 568 | j < AR5416_NUM_PDADC_VALUES; j++) |
569 | pdadcValues[j] = | 569 | pdadcValues[j] = |
570 | pdadcValues[AR9287_NUM_PDADC_VALUES-diff]; | 570 | pdadcValues[AR5416_NUM_PDADC_VALUES-diff]; |
571 | } | 571 | } |
572 | 572 | ||
573 | if (!ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) { | 573 | if (!ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) { |
@@ -610,9 +610,9 @@ static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah, | |||
610 | #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10 | 610 | #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10 |
611 | 611 | ||
612 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); | 612 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
613 | u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; | 613 | u16 twiceMaxEdgePower = MAX_RATE_POWER; |
614 | static const u16 tpScaleReductionTable[5] = | 614 | static const u16 tpScaleReductionTable[5] = |
615 | { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; | 615 | { 0, 3, 6, 9, MAX_RATE_POWER }; |
616 | int i; | 616 | int i; |
617 | int16_t twiceLargestAntenna; | 617 | int16_t twiceLargestAntenna; |
618 | struct cal_ctl_data_ar9287 *rep; | 618 | struct cal_ctl_data_ar9287 *rep; |
@@ -877,8 +877,8 @@ static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah, | |||
877 | regulatory->max_power_level = 0; | 877 | regulatory->max_power_level = 0; |
878 | for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { | 878 | for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { |
879 | ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); | 879 | ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); |
880 | if (ratesArray[i] > AR9287_MAX_RATE_POWER) | 880 | if (ratesArray[i] > MAX_RATE_POWER) |
881 | ratesArray[i] = AR9287_MAX_RATE_POWER; | 881 | ratesArray[i] = MAX_RATE_POWER; |
882 | 882 | ||
883 | if (ratesArray[i] > regulatory->max_power_level) | 883 | if (ratesArray[i] > regulatory->max_power_level) |
884 | regulatory->max_power_level = ratesArray[i]; | 884 | regulatory->max_power_level = ratesArray[i]; |
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_def.c b/drivers/net/wireless/ath/ath9k/eeprom_def.c index 5bfa031545f..da96a78f996 100644 --- a/drivers/net/wireless/ath/ath9k/eeprom_def.c +++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c | |||
@@ -206,7 +206,7 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah) | |||
206 | pModal->antCtrlChain[i] = integer; | 206 | pModal->antCtrlChain[i] = integer; |
207 | } | 207 | } |
208 | 208 | ||
209 | for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { | 209 | for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { |
210 | word = swab16(pModal->spurChans[i].spurChan); | 210 | word = swab16(pModal->spurChans[i].spurChan); |
211 | pModal->spurChans[i].spurChan = word; | 211 | pModal->spurChans[i].spurChan = word; |
212 | } | 212 | } |
@@ -616,7 +616,7 @@ static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah, | |||
616 | int16_t minDelta = 0; | 616 | int16_t minDelta = 0; |
617 | struct chan_centers centers; | 617 | struct chan_centers centers; |
618 | 618 | ||
619 | memset(&minPwrT4, 0, AR9287_NUM_PD_GAINS); | 619 | memset(&minPwrT4, 0, AR5416_NUM_PD_GAINS); |
620 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | 620 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); |
621 | 621 | ||
622 | for (numPiers = 0; numPiers < availPiers; numPiers++) { | 622 | for (numPiers = 0; numPiers < availPiers; numPiers++) { |
@@ -685,7 +685,7 @@ static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah, | |||
685 | (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4); | 685 | (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4); |
686 | 686 | ||
687 | pPdGainBoundaries[i] = | 687 | pPdGainBoundaries[i] = |
688 | min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]); | 688 | min((u16)MAX_RATE_POWER, pPdGainBoundaries[i]); |
689 | 689 | ||
690 | if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) { | 690 | if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) { |
691 | minDelta = pPdGainBoundaries[0] - 23; | 691 | minDelta = pPdGainBoundaries[0] - 23; |
@@ -782,7 +782,7 @@ static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah, | |||
782 | /* Because of a hardware limitation, ensure the gain boundary | 782 | /* Because of a hardware limitation, ensure the gain boundary |
783 | * is not larger than (63 - overlap) | 783 | * is not larger than (63 - overlap) |
784 | */ | 784 | */ |
785 | gb_limit = (u16)(AR5416_MAX_RATE_POWER - pdGainOverlap_t2); | 785 | gb_limit = (u16)(MAX_RATE_POWER - pdGainOverlap_t2); |
786 | 786 | ||
787 | for (k = 0; k < numXpdGain; k++) | 787 | for (k = 0; k < numXpdGain; k++) |
788 | gb[k] = (u16)min(gb_limit, gb[k]); | 788 | gb[k] = (u16)min(gb_limit, gb[k]); |
@@ -1001,9 +1001,9 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah, | |||
1001 | 1001 | ||
1002 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); | 1002 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
1003 | struct ar5416_eeprom_def *pEepData = &ah->eeprom.def; | 1003 | struct ar5416_eeprom_def *pEepData = &ah->eeprom.def; |
1004 | u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; | 1004 | u16 twiceMaxEdgePower = MAX_RATE_POWER; |
1005 | static const u16 tpScaleReductionTable[5] = | 1005 | static const u16 tpScaleReductionTable[5] = |
1006 | { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; | 1006 | { 0, 3, 6, 9, MAX_RATE_POWER }; |
1007 | 1007 | ||
1008 | int i; | 1008 | int i; |
1009 | int16_t twiceLargestAntenna; | 1009 | int16_t twiceLargestAntenna; |
@@ -1148,7 +1148,7 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah, | |||
1148 | 1148 | ||
1149 | if (ah->eep_ops->get_eeprom_ver(ah) == 14 && | 1149 | if (ah->eep_ops->get_eeprom_ver(ah) == 14 && |
1150 | ah->eep_ops->get_eeprom_rev(ah) <= 2) | 1150 | ah->eep_ops->get_eeprom_rev(ah) <= 2) |
1151 | twiceMaxEdgePower = AR5416_MAX_RATE_POWER; | 1151 | twiceMaxEdgePower = MAX_RATE_POWER; |
1152 | 1152 | ||
1153 | for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) { | 1153 | for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) { |
1154 | if ((((cfgCtl & ~CTL_MODE_M) | | 1154 | if ((((cfgCtl & ~CTL_MODE_M) | |
@@ -1293,8 +1293,8 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah, | |||
1293 | regulatory->max_power_level = 0; | 1293 | regulatory->max_power_level = 0; |
1294 | for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { | 1294 | for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { |
1295 | ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); | 1295 | ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); |
1296 | if (ratesArray[i] > AR5416_MAX_RATE_POWER) | 1296 | if (ratesArray[i] > MAX_RATE_POWER) |
1297 | ratesArray[i] = AR5416_MAX_RATE_POWER; | 1297 | ratesArray[i] = MAX_RATE_POWER; |
1298 | if (ratesArray[i] > regulatory->max_power_level) | 1298 | if (ratesArray[i] > regulatory->max_power_level) |
1299 | regulatory->max_power_level = ratesArray[i]; | 1299 | regulatory->max_power_level = ratesArray[i]; |
1300 | } | 1300 | } |
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h index d83cc3b4685..157e6bc2651 100644 --- a/drivers/net/wireless/ath/ath9k/hw.h +++ b/drivers/net/wireless/ath/ath9k/hw.h | |||
@@ -238,7 +238,6 @@ struct ath9k_ops_config { | |||
238 | #define SPUR_DISABLE 0 | 238 | #define SPUR_DISABLE 0 |
239 | #define SPUR_ENABLE_IOCTL 1 | 239 | #define SPUR_ENABLE_IOCTL 1 |
240 | #define SPUR_ENABLE_EEPROM 2 | 240 | #define SPUR_ENABLE_EEPROM 2 |
241 | #define AR_EEPROM_MODAL_SPURS 5 | ||
242 | #define AR_SPUR_5413_1 1640 | 241 | #define AR_SPUR_5413_1 1640 |
243 | #define AR_SPUR_5413_2 1200 | 242 | #define AR_SPUR_5413_2 1200 |
244 | #define AR_NO_SPUR 0x8000 | 243 | #define AR_NO_SPUR 0x8000 |