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-rw-r--r--MAINTAINERS3
-rw-r--r--arch/mips/Makefile3
-rw-r--r--arch/mips/arc/misc.c19
-rw-r--r--arch/mips/au1000/common/reset.c10
-rw-r--r--arch/mips/kernel/time.c6
-rw-r--r--arch/mips/mm/c-r4k.c13
-rw-r--r--arch/mips/mm/c-tx39.c1
-rw-r--r--arch/mips/sibyte/sb1250/time.c77
-rw-r--r--arch/mips/sibyte/swarm/setup.c7
-rw-r--r--include/asm-mips/cpu-features.h3
-rw-r--r--include/asm-mips/cpu-info.h1
-rw-r--r--include/asm-mips/hazards.h180
-rw-r--r--include/asm-mips/io.h18
-rw-r--r--include/asm-mips/r4kcache.h3
-rw-r--r--include/asm-mips/sibyte/sb1250.h2
-rw-r--r--include/asm-mips/sibyte/sb1250_scd.h5
16 files changed, 217 insertions, 134 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 3d7d30dc543..8db5c339845 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1752,7 +1752,8 @@ P: Ralf Baechle
1752M: ralf@linux-mips.org 1752M: ralf@linux-mips.org
1753W: http://www.linux-mips.org/ 1753W: http://www.linux-mips.org/
1754L: linux-mips@linux-mips.org 1754L: linux-mips@linux-mips.org
1755S: Maintained 1755T: git www.linux-mips.org:/pub/scm/linux.git
1756S: Supported
1756 1757
1757MISCELLANEOUS MCA-SUPPORT 1758MISCELLANEOUS MCA-SUPPORT
1758P: James Bottomley 1759P: James Bottomley
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index fe9da16f3a4..3d8dac681c6 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -108,7 +108,8 @@ MODFLAGS += -mlong-calls
108cflags-$(CONFIG_CPU_BIG_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' && echo -EB) 108cflags-$(CONFIG_CPU_BIG_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' && echo -EB)
109cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' || echo -EL) 109cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' || echo -EL)
110 110
111cflags-$(CONFIG_SB1XXX_CORELIS) += -mno-sched-prolog -fno-omit-frame-pointer 111cflags-$(CONFIG_SB1XXX_CORELIS) += $(call cc-option,-mno-sched-prolog) \
112 -fno-omit-frame-pointer
112 113
113# 114#
114# Use: $(call set_gccflags,<cpu0>,<isa0>,<cpu1>,<isa1>,<isa2>) 115# Use: $(call set_gccflags,<cpu0>,<isa0>,<cpu1>,<isa1>,<isa2>)
diff --git a/arch/mips/arc/misc.c b/arch/mips/arc/misc.c
index 84867de2202..b2e10b9e945 100644
--- a/arch/mips/arc/misc.c
+++ b/arch/mips/arc/misc.c
@@ -9,7 +9,6 @@
9 * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org) 9 * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
10 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Copyright (C) 1999 Silicon Graphics, Inc.
11 */ 11 */
12#include <linux/config.h>
13#include <linux/init.h> 12#include <linux/init.h>
14#include <linux/kernel.h> 13#include <linux/kernel.h>
15 14
@@ -20,17 +19,11 @@
20#include <asm/bootinfo.h> 19#include <asm/bootinfo.h>
21#include <asm/system.h> 20#include <asm/system.h>
22 21
23extern void *sgiwd93_host;
24extern void reset_wd33c93(void *instance);
25
26VOID 22VOID
27ArcHalt(VOID) 23ArcHalt(VOID)
28{ 24{
29 bc_disable(); 25 bc_disable();
30 local_irq_disable(); 26 local_irq_disable();
31#ifdef CONFIG_SCSI_SGIWD93
32 reset_wd33c93(sgiwd93_host);
33#endif
34 ARC_CALL0(halt); 27 ARC_CALL0(halt);
35never: goto never; 28never: goto never;
36} 29}
@@ -40,9 +33,6 @@ ArcPowerDown(VOID)
40{ 33{
41 bc_disable(); 34 bc_disable();
42 local_irq_disable(); 35 local_irq_disable();
43#ifdef CONFIG_SCSI_SGIWD93
44 reset_wd33c93(sgiwd93_host);
45#endif
46 ARC_CALL0(pdown); 36 ARC_CALL0(pdown);
47never: goto never; 37never: goto never;
48} 38}
@@ -53,9 +43,6 @@ ArcRestart(VOID)
53{ 43{
54 bc_disable(); 44 bc_disable();
55 local_irq_disable(); 45 local_irq_disable();
56#ifdef CONFIG_SCSI_SGIWD93
57 reset_wd33c93(sgiwd93_host);
58#endif
59 ARC_CALL0(restart); 46 ARC_CALL0(restart);
60never: goto never; 47never: goto never;
61} 48}
@@ -65,9 +52,6 @@ ArcReboot(VOID)
65{ 52{
66 bc_disable(); 53 bc_disable();
67 local_irq_disable(); 54 local_irq_disable();
68#ifdef CONFIG_SCSI_SGIWD93
69 reset_wd33c93(sgiwd93_host);
70#endif
71 ARC_CALL0(reboot); 55 ARC_CALL0(reboot);
72never: goto never; 56never: goto never;
73} 57}
@@ -77,9 +61,6 @@ ArcEnterInteractiveMode(VOID)
77{ 61{
78 bc_disable(); 62 bc_disable();
79 local_irq_disable(); 63 local_irq_disable();
80#ifdef CONFIG_SCSI_SGIWD93
81 reset_wd33c93(sgiwd93_host);
82#endif
83 ARC_CALL0(imode); 64 ARC_CALL0(imode);
84never: goto never; 65never: goto never;
85} 66}
diff --git a/arch/mips/au1000/common/reset.c b/arch/mips/au1000/common/reset.c
index 4ffccedf596..c93af224c1b 100644
--- a/arch/mips/au1000/common/reset.c
+++ b/arch/mips/au1000/common/reset.c
@@ -164,17 +164,20 @@ void au1000_restart(char *command)
164 164
165void au1000_halt(void) 165void au1000_halt(void)
166{ 166{
167#if defined(CONFIG_MIPS_PB1550) 167#if defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_DB1550)
168 /* power off system */ 168 /* power off system */
169 printk("\n** Powering off Pb1550\n"); 169 printk("\n** Powering off...\n");
170 au_writew(au_readw(0xAF00001C) | (3<<14), 0xAF00001C); 170 au_writew(au_readw(0xAF00001C) | (3<<14), 0xAF00001C);
171 au_sync(); 171 au_sync();
172 while(1); /* should not get here */ 172 while(1); /* should not get here */
173#endif 173#else
174 printk(KERN_NOTICE "\n** You can safely turn off the power\n"); 174 printk(KERN_NOTICE "\n** You can safely turn off the power\n");
175#ifdef CONFIG_MIPS_MIRAGE 175#ifdef CONFIG_MIPS_MIRAGE
176 au_writel((1 << 26) | (1 << 10), GPIO2_OUTPUT); 176 au_writel((1 << 26) | (1 << 10), GPIO2_OUTPUT);
177#endif 177#endif
178#ifdef CONFIG_MIPS_DB1200
179 au_writew(au_readw(0xB980001C) | (1<<14), 0xB980001C);
180#endif
178#ifdef CONFIG_PM 181#ifdef CONFIG_PM
179 au_sleep(); 182 au_sleep();
180 183
@@ -187,6 +190,7 @@ void au1000_halt(void)
187 "wait\n\t" 190 "wait\n\t"
188 ".set\tmips0"); 191 ".set\tmips0");
189#endif 192#endif
193#endif /* defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_DB1550) */
190} 194}
191 195
192void au1000_power_off(void) 196void au1000_power_off(void)
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index 42c94c771af..51273b7297a 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -424,6 +424,8 @@ irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
424 unsigned long j; 424 unsigned long j;
425 unsigned int count; 425 unsigned int count;
426 426
427 write_seqlock(&xtime_lock);
428
427 count = mips_hpt_read(); 429 count = mips_hpt_read();
428 mips_timer_ack(); 430 mips_timer_ack();
429 431
@@ -441,7 +443,6 @@ irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
441 * CMOS clock accordingly every ~11 minutes. rtc_set_time() has to be 443 * CMOS clock accordingly every ~11 minutes. rtc_set_time() has to be
442 * called as close as possible to 500 ms before the new second starts. 444 * called as close as possible to 500 ms before the new second starts.
443 */ 445 */
444 write_seqlock(&xtime_lock);
445 if (ntp_synced() && 446 if (ntp_synced() &&
446 xtime.tv_sec > last_rtc_update + 660 && 447 xtime.tv_sec > last_rtc_update + 660 &&
447 (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 && 448 (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 &&
@@ -453,7 +454,6 @@ irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
453 last_rtc_update = xtime.tv_sec - 600; 454 last_rtc_update = xtime.tv_sec - 600;
454 } 455 }
455 } 456 }
456 write_sequnlock(&xtime_lock);
457 457
458 /* 458 /*
459 * If jiffies has overflown in this timer_interrupt, we must 459 * If jiffies has overflown in this timer_interrupt, we must
@@ -496,6 +496,8 @@ irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
496 } 496 }
497 } 497 }
498 498
499 write_sequnlock(&xtime_lock);
500
499 /* 501 /*
500 * In UP mode, we call local_timer_interrupt() to do profiling 502 * In UP mode, we call local_timer_interrupt() to do profiling
501 * and process accouting. 503 * and process accouting.
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 0668e9bfce4..9572ed44f0d 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -375,6 +375,7 @@ static void r4k_flush_cache_mm(struct mm_struct *mm)
375struct flush_cache_page_args { 375struct flush_cache_page_args {
376 struct vm_area_struct *vma; 376 struct vm_area_struct *vma;
377 unsigned long addr; 377 unsigned long addr;
378 unsigned long pfn;
378}; 379};
379 380
380static inline void local_r4k_flush_cache_page(void *args) 381static inline void local_r4k_flush_cache_page(void *args)
@@ -382,6 +383,7 @@ static inline void local_r4k_flush_cache_page(void *args)
382 struct flush_cache_page_args *fcp_args = args; 383 struct flush_cache_page_args *fcp_args = args;
383 struct vm_area_struct *vma = fcp_args->vma; 384 struct vm_area_struct *vma = fcp_args->vma;
384 unsigned long addr = fcp_args->addr; 385 unsigned long addr = fcp_args->addr;
386 unsigned long paddr = fcp_args->pfn << PAGE_SHIFT;
385 int exec = vma->vm_flags & VM_EXEC; 387 int exec = vma->vm_flags & VM_EXEC;
386 struct mm_struct *mm = vma->vm_mm; 388 struct mm_struct *mm = vma->vm_mm;
387 pgd_t *pgdp; 389 pgd_t *pgdp;
@@ -431,11 +433,12 @@ static inline void local_r4k_flush_cache_page(void *args)
431 * Do indexed flush, too much work to get the (possible) TLB refills 433 * Do indexed flush, too much work to get the (possible) TLB refills
432 * to work correctly. 434 * to work correctly.
433 */ 435 */
434 addr = INDEX_BASE + (addr & (dcache_size - 1));
435 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { 436 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
436 r4k_blast_dcache_page_indexed(addr); 437 r4k_blast_dcache_page_indexed(cpu_has_pindexed_dcache ?
437 if (exec && !cpu_icache_snoops_remote_store) 438 paddr : addr);
438 r4k_blast_scache_page_indexed(addr); 439 if (exec && !cpu_icache_snoops_remote_store) {
440 r4k_blast_scache_page_indexed(paddr);
441 }
439 } 442 }
440 if (exec) { 443 if (exec) {
441 if (cpu_has_vtag_icache) { 444 if (cpu_has_vtag_icache) {
@@ -455,6 +458,7 @@ static void r4k_flush_cache_page(struct vm_area_struct *vma,
455 458
456 args.vma = vma; 459 args.vma = vma;
457 args.addr = addr; 460 args.addr = addr;
461 args.pfn = pfn;
458 462
459 on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1); 463 on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1);
460} 464}
@@ -956,6 +960,7 @@ static void __init probe_pcache(void)
956 switch (c->cputype) { 960 switch (c->cputype) {
957 case CPU_20KC: 961 case CPU_20KC:
958 case CPU_25KF: 962 case CPU_25KF:
963 c->dcache.flags |= MIPS_CACHE_PINDEX;
959 case CPU_R10000: 964 case CPU_R10000:
960 case CPU_R12000: 965 case CPU_R12000:
961 case CPU_SB1: 966 case CPU_SB1:
diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c
index 7c572bea4a9..fe232e3988e 100644
--- a/arch/mips/mm/c-tx39.c
+++ b/arch/mips/mm/c-tx39.c
@@ -210,7 +210,6 @@ static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page
210 * Do indexed flush, too much work to get the (possible) TLB refills 210 * Do indexed flush, too much work to get the (possible) TLB refills
211 * to work correctly. 211 * to work correctly.
212 */ 212 */
213 page = (KSEG0 + (page & (dcache_size - 1)));
214 if (cpu_has_dc_aliases || exec) 213 if (cpu_has_dc_aliases || exec)
215 tx39_blast_dcache_page_indexed(page); 214 tx39_blast_dcache_page_indexed(page);
216 if (exec) 215 if (exec)
diff --git a/arch/mips/sibyte/sb1250/time.c b/arch/mips/sibyte/sb1250/time.c
index 511c89d65f3..1588f6debd9 100644
--- a/arch/mips/sibyte/sb1250/time.c
+++ b/arch/mips/sibyte/sb1250/time.c
@@ -47,23 +47,51 @@
47#define IMR_IP3_VAL K_INT_MAP_I1 47#define IMR_IP3_VAL K_INT_MAP_I1
48#define IMR_IP4_VAL K_INT_MAP_I2 48#define IMR_IP4_VAL K_INT_MAP_I2
49 49
50#define SB1250_HPT_NUM 3
51#define SB1250_HPT_VALUE M_SCD_TIMER_CNT /* max value */
52#define SB1250_HPT_SHIFT ((sizeof(unsigned int)*8)-V_SCD_TIMER_WIDTH)
53
54
50extern int sb1250_steal_irq(int irq); 55extern int sb1250_steal_irq(int irq);
51 56
57static unsigned int sb1250_hpt_read(void);
58static void sb1250_hpt_init(unsigned int);
59
60static unsigned int hpt_offset;
61
62void __init sb1250_hpt_setup(void)
63{
64 int cpu = smp_processor_id();
65
66 if (!cpu) {
67 /* Setup hpt using timer #3 but do not enable irq for it */
68 __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG)));
69 __raw_writeq(SB1250_HPT_VALUE,
70 IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_INIT)));
71 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
72 IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG)));
73
74 /*
75 * we need to fill 32 bits, so just use the upper 23 bits and pretend
76 * the timer is going 512Mhz instead of 1Mhz
77 */
78 mips_hpt_frequency = V_SCD_TIMER_FREQ << SB1250_HPT_SHIFT;
79 mips_hpt_init = sb1250_hpt_init;
80 mips_hpt_read = sb1250_hpt_read;
81 }
82}
83
84
52void sb1250_time_init(void) 85void sb1250_time_init(void)
53{ 86{
54 int cpu = smp_processor_id(); 87 int cpu = smp_processor_id();
55 int irq = K_INT_TIMER_0+cpu; 88 int irq = K_INT_TIMER_0+cpu;
56 89
57 /* Only have 4 general purpose timers */ 90 /* Only have 4 general purpose timers, and we use last one as hpt */
58 if (cpu > 3) { 91 if (cpu > 2) {
59 BUG(); 92 BUG();
60 } 93 }
61 94
62 if (!cpu) {
63 /* Use our own gettimeoffset() routine */
64 do_gettimeoffset = sb1250_gettimeoffset;
65 }
66
67 sb1250_mask_irq(cpu, irq); 95 sb1250_mask_irq(cpu, irq);
68 96
69 /* Map the timer interrupt to ip[4] of this cpu */ 97 /* Map the timer interrupt to ip[4] of this cpu */
@@ -75,10 +103,10 @@ void sb1250_time_init(void)
75 /* Disable the timer and set up the count */ 103 /* Disable the timer and set up the count */
76 __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); 104 __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
77#ifdef CONFIG_SIMULATION 105#ifdef CONFIG_SIMULATION
78 __raw_writeq(50000 / HZ, 106 __raw_writeq((50000 / HZ) - 1,
79 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); 107 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
80#else 108#else
81 __raw_writeq(1000000 / HZ, 109 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1,
82 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); 110 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
83#endif 111#endif
84 112
@@ -103,7 +131,7 @@ void sb1250_timer_interrupt(struct pt_regs *regs)
103 int cpu = smp_processor_id(); 131 int cpu = smp_processor_id();
104 int irq = K_INT_TIMER_0 + cpu; 132 int irq = K_INT_TIMER_0 + cpu;
105 133
106 /* Reset the timer */ 134 /* ACK interrupt */
107 ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, 135 ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
108 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); 136 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
109 137
@@ -122,15 +150,26 @@ void sb1250_timer_interrupt(struct pt_regs *regs)
122} 150}
123 151
124/* 152/*
125 * We use our own do_gettimeoffset() instead of the generic one, 153 * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over
126 * because the generic one does not work for SMP case. 154 * again. There's no easy way to set to a specific value so store init value
127 * In addition, since we use general timer 0 for system time, 155 * in hpt_offset and subtract each time.
128 * we can get accurate intra-jiffy offset without calibration. 156 *
157 * Note: Timer isn't full 32bits so shift it into the upper part making
158 * it appear to run at a higher frequency.
129 */ 159 */
130unsigned long sb1250_gettimeoffset(void) 160static unsigned int sb1250_hpt_read(void)
131{ 161{
132 unsigned long count = 162 unsigned int count;
133 __raw_readq(IOADDR(A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT)));
134 163
135 return 1000000/HZ - count; 164 count = G_SCD_TIMER_CNT(__raw_readq(IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CNT))));
136 } 165
166 count = (SB1250_HPT_VALUE - count) << SB1250_HPT_SHIFT;
167
168 return count - hpt_offset;
169}
170
171static void sb1250_hpt_init(unsigned int count)
172{
173 hpt_offset = count;
174 return;
175}
diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c
index b614ca0ddb6..b661d2425a3 100644
--- a/arch/mips/sibyte/swarm/setup.c
+++ b/arch/mips/sibyte/swarm/setup.c
@@ -70,6 +70,12 @@ const char *get_system_type(void)
70 return "SiByte " SIBYTE_BOARD_NAME; 70 return "SiByte " SIBYTE_BOARD_NAME;
71} 71}
72 72
73void __init swarm_time_init(void)
74{
75 /* Setup HPT */
76 sb1250_hpt_setup();
77}
78
73void __init swarm_timer_setup(struct irqaction *irq) 79void __init swarm_timer_setup(struct irqaction *irq)
74{ 80{
75 /* 81 /*
@@ -109,6 +115,7 @@ void __init plat_setup(void)
109 115
110 panic_timeout = 5; /* For debug. */ 116 panic_timeout = 5; /* For debug. */
111 117
118 board_time_init = swarm_time_init;
112 board_timer_setup = swarm_timer_setup; 119 board_timer_setup = swarm_timer_setup;
113 board_be_handler = swarm_be_handler; 120 board_be_handler = swarm_be_handler;
114 121
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h
index 78c9cc2735d..3f2b6d9ac45 100644
--- a/include/asm-mips/cpu-features.h
+++ b/include/asm-mips/cpu-features.h
@@ -96,6 +96,9 @@
96#ifndef cpu_has_ic_fills_f_dc 96#ifndef cpu_has_ic_fills_f_dc
97#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC) 97#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
98#endif 98#endif
99#ifndef cpu_has_pindexed_dcache
100#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
101#endif
99 102
100/* 103/*
101 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors 104 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h
index d5cf519f8fc..140be1c67da 100644
--- a/include/asm-mips/cpu-info.h
+++ b/include/asm-mips/cpu-info.h
@@ -39,6 +39,7 @@ struct cache_desc {
39#define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */ 39#define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */
40#define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */ 40#define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */
41#define MIPS_IC_SNOOPS_REMOTE 0x00000010 /* Ic snoops remote stores */ 41#define MIPS_IC_SNOOPS_REMOTE 0x00000010 /* Ic snoops remote stores */
42#define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */
42 43
43struct cpuinfo_mips { 44struct cpuinfo_mips {
44 unsigned long udelay_val; 45 unsigned long udelay_val;
diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h
index 6111a0ce58c..feb29a79388 100644
--- a/include/asm-mips/hazards.h
+++ b/include/asm-mips/hazards.h
@@ -3,7 +3,9 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2003, 2004 Ralf Baechle 6 * Copyright (C) 2003, 2004 Ralf Baechle <ralf@linux-mips.org>
7 * Copyright (C) MIPS Technologies, Inc.
8 * written by Ralf Baechle <ralf@linux-mips.org>
7 */ 9 */
8#ifndef _ASM_HAZARDS_H 10#ifndef _ASM_HAZARDS_H
9#define _ASM_HAZARDS_H 11#define _ASM_HAZARDS_H
@@ -74,8 +76,7 @@
74#define irq_disable_hazard 76#define irq_disable_hazard
75 _ehb 77 _ehb
76 78
77#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \ 79#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
78 defined(CONFIG_CPU_SB1)
79 80
80/* 81/*
81 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. 82 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
@@ -99,13 +100,13 @@
99#else /* __ASSEMBLY__ */ 100#else /* __ASSEMBLY__ */
100 101
101__asm__( 102__asm__(
102 " .macro _ssnop \n\t" 103 " .macro _ssnop \n"
103 " sll $0, $0, 1 \n\t" 104 " sll $0, $0, 1 \n"
104 " .endm \n\t" 105 " .endm \n"
105 " \n\t" 106 " \n"
106 " .macro _ehb \n\t" 107 " .macro _ehb \n"
107 " sll $0, $0, 3 \n\t" 108 " sll $0, $0, 3 \n"
108 " .endm \n\t"); 109 " .endm \n");
109 110
110#ifdef CONFIG_CPU_RM9000 111#ifdef CONFIG_CPU_RM9000
111 112
@@ -117,17 +118,21 @@ __asm__(
117 118
118#define mtc0_tlbw_hazard() \ 119#define mtc0_tlbw_hazard() \
119 __asm__ __volatile__( \ 120 __asm__ __volatile__( \
120 ".set\tmips32\n\t" \ 121 " .set mips32 \n" \
121 "_ssnop; _ssnop; _ssnop; _ssnop\n\t" \ 122 " _ssnop \n" \
122 ".set\tmips0") 123 " _ssnop \n" \
124 " _ssnop \n" \
125 " _ssnop \n" \
126 " .set mips0 \n")
123 127
124#define tlbw_use_hazard() \ 128#define tlbw_use_hazard() \
125 __asm__ __volatile__( \ 129 __asm__ __volatile__( \
126 ".set\tmips32\n\t" \ 130 " .set mips32 \n" \
127 "_ssnop; _ssnop; _ssnop; _ssnop\n\t" \ 131 " _ssnop \n" \
128 ".set\tmips0") 132 " _ssnop \n" \
129 133 " _ssnop \n" \
130#define back_to_back_c0_hazard() do { } while (0) 134 " _ssnop \n" \
135 " .set mips0 \n")
131 136
132#else 137#else
133 138
@@ -136,15 +141,25 @@ __asm__(
136 */ 141 */
137#define mtc0_tlbw_hazard() \ 142#define mtc0_tlbw_hazard() \
138 __asm__ __volatile__( \ 143 __asm__ __volatile__( \
139 ".set noreorder\n\t" \ 144 " .set noreorder \n" \
140 "nop; nop; nop; nop; nop; nop;\n\t" \ 145 " nop \n" \
141 ".set reorder\n\t") 146 " nop \n" \
147 " nop \n" \
148 " nop \n" \
149 " nop \n" \
150 " nop \n" \
151 " .set reorder \n")
142 152
143#define tlbw_use_hazard() \ 153#define tlbw_use_hazard() \
144 __asm__ __volatile__( \ 154 __asm__ __volatile__( \
145 ".set noreorder\n\t" \ 155 " .set noreorder \n" \
146 "nop; nop; nop; nop; nop; nop;\n\t" \ 156 " nop \n" \
147 ".set reorder\n\t") 157 " nop \n" \
158 " nop \n" \
159 " nop \n" \
160 " nop \n" \
161 " nop \n" \
162 " .set reorder \n")
148 163
149#endif 164#endif
150 165
@@ -156,49 +171,26 @@ __asm__(
156 171
157#ifdef CONFIG_CPU_MIPSR2 172#ifdef CONFIG_CPU_MIPSR2
158 173
159__asm__( 174__asm__(" .macro irq_enable_hazard \n"
160 " .macro\tirq_enable_hazard \n\t" 175 " _ehb \n"
161 " _ehb \n\t" 176 " .endm \n"
162 " .endm \n\t" 177 " \n"
163 " \n\t" 178 " .macro irq_disable_hazard \n"
164 " .macro\tirq_disable_hazard \n\t" 179 " _ehb \n"
165 " _ehb \n\t" 180 " .endm \n");
166 " .endm \n\t"
167 " \n\t"
168 " .macro\tback_to_back_c0_hazard \n\t"
169 " _ehb \n\t"
170 " .endm");
171
172#define irq_enable_hazard() \
173 __asm__ __volatile__( \
174 "irq_enable_hazard")
175 181
176#define irq_disable_hazard() \ 182#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
177 __asm__ __volatile__( \
178 "irq_disable_hazard")
179
180#define back_to_back_c0_hazard() \
181 __asm__ __volatile__( \
182 "back_to_back_c0_hazard")
183
184#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
185 defined(CONFIG_CPU_SB1)
186 183
187/* 184/*
188 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. 185 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
189 */ 186 */
190 187
191__asm__( 188__asm__(
192 " .macro\tirq_enable_hazard \n\t" 189 " .macro irq_enable_hazard \n"
193 " .endm \n\t" 190 " .endm \n"
194 " \n\t" 191 " \n"
195 " .macro\tirq_disable_hazard \n\t" 192 " .macro irq_disable_hazard \n"
196 " .endm"); 193 " .endm \n");
197
198#define irq_enable_hazard() do { } while (0)
199#define irq_disable_hazard() do { } while (0)
200
201#define back_to_back_c0_hazard() do { } while (0)
202 194
203#else 195#else
204 196
@@ -209,29 +201,63 @@ __asm__(
209 */ 201 */
210 202
211__asm__( 203__asm__(
212 " # \n\t" 204 " # \n"
213 " # There is a hazard but we do not care \n\t" 205 " # There is a hazard but we do not care \n"
214 " # \n\t" 206 " # \n"
215 " .macro\tirq_enable_hazard \n\t" 207 " .macro\tirq_enable_hazard \n"
216 " .endm \n\t" 208 " .endm \n"
217 " \n\t" 209 " \n"
218 " .macro\tirq_disable_hazard \n\t" 210 " .macro\tirq_disable_hazard \n"
219 " _ssnop; _ssnop; _ssnop \n\t" 211 " _ssnop \n"
220 " .endm"); 212 " _ssnop \n"
213 " _ssnop \n"
214 " .endm \n");
221 215
222#define irq_enable_hazard() do { } while (0) 216#endif
217
218#define irq_enable_hazard() \
219 __asm__ __volatile__("irq_enable_hazard")
223#define irq_disable_hazard() \ 220#define irq_disable_hazard() \
224 __asm__ __volatile__( \ 221 __asm__ __volatile__("irq_disable_hazard")
225 "irq_disable_hazard")
226 222
227#define back_to_back_c0_hazard() \ 223
228 __asm__ __volatile__( \ 224/*
229 " .set noreorder \n" \ 225 * Back-to-back hazards -
230 " nop; nop; nop \n" \ 226 *
231 " .set reorder \n") 227 * What is needed to separate a move to cp0 from a subsequent read from the
228 * same cp0 register?
229 */
230#ifdef CONFIG_CPU_MIPSR2
231
232__asm__(" .macro back_to_back_c0_hazard \n"
233 " _ehb \n"
234 " .endm \n");
235
236#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
237 defined(CONFIG_CPU_SB1)
238
239__asm__(" .macro back_to_back_c0_hazard \n"
240 " .endm \n");
241
242#else
243
244__asm__(" .macro back_to_back_c0_hazard \n"
245 " .set noreorder \n"
246 " _ssnop \n"
247 " _ssnop \n"
248 " _ssnop \n"
249 " .set reorder \n"
250 " .endm");
232 251
233#endif 252#endif
234 253
254#define back_to_back_c0_hazard() \
255 __asm__ __volatile__("back_to_back_c0_hazard")
256
257
258/*
259 * Instruction execution hazard
260 */
235#ifdef CONFIG_CPU_MIPSR2 261#ifdef CONFIG_CPU_MIPSR2
236/* 262/*
237 * gcc has a tradition of misscompiling the previous construct using the 263 * gcc has a tradition of misscompiling the previous construct using the
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
index 8c011aa61af..ba1d7bbc15d 100644
--- a/include/asm-mips/io.h
+++ b/include/asm-mips/io.h
@@ -4,7 +4,7 @@
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 1994, 1995 Waldorf GmbH 6 * Copyright (C) 1994, 1995 Waldorf GmbH
7 * Copyright (C) 1994 - 2000 Ralf Baechle 7 * Copyright (C) 1994 - 2000, 06 Ralf Baechle
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. 9 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
10 * Author: Maciej W. Rozycki <macro@mips.com> 10 * Author: Maciej W. Rozycki <macro@mips.com>
@@ -103,8 +103,20 @@
103 */ 103 */
104extern const unsigned long mips_io_port_base; 104extern const unsigned long mips_io_port_base;
105 105
106#define set_io_port_base(base) \ 106/*
107 do { * (unsigned long *) &mips_io_port_base = (base); } while (0) 107 * Gcc will generate code to load the value of mips_io_port_base after each
108 * function call which may be fairly wasteful in some cases. So we don't
109 * play quite by the book. We tell gcc mips_io_port_base is a long variable
110 * which solves the code generation issue. Now we need to violate the
111 * aliasing rules a little to make initialization possible and finally we
112 * will need the barrier() to fight side effects of the aliasing chat.
113 * This trickery will eventually collapse under gcc's optimizer. Oh well.
114 */
115static inline void set_io_port_base(unsigned long base)
116{
117 * (unsigned long *) &mips_io_port_base = base;
118 barrier();
119}
108 120
109/* 121/*
110 * Thanks to James van Artsdalen for a better timing-fix than 122 * Thanks to James van Artsdalen for a better timing-fix than
diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h
index 9632c27dad1..0bcb79a58ee 100644
--- a/include/asm-mips/r4kcache.h
+++ b/include/asm-mips/r4kcache.h
@@ -257,7 +257,8 @@ static inline void blast_##pfx##cache##lsize##_page(unsigned long page) \
257 \ 257 \
258static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \ 258static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \
259{ \ 259{ \
260 unsigned long start = page; \ 260 unsigned long indexmask = current_cpu_data.desc.waysize - 1; \
261 unsigned long start = INDEX_BASE + (page & indexmask); \
261 unsigned long end = start + PAGE_SIZE; \ 262 unsigned long end = start + PAGE_SIZE; \
262 unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \ 263 unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \
263 unsigned long ws_end = current_cpu_data.desc.ways << \ 264 unsigned long ws_end = current_cpu_data.desc.ways << \
diff --git a/include/asm-mips/sibyte/sb1250.h b/include/asm-mips/sibyte/sb1250.h
index a474c29cd70..b09e16c93ca 100644
--- a/include/asm-mips/sibyte/sb1250.h
+++ b/include/asm-mips/sibyte/sb1250.h
@@ -45,8 +45,8 @@ extern unsigned int soc_type;
45extern unsigned int periph_rev; 45extern unsigned int periph_rev;
46extern unsigned int zbbus_mhz; 46extern unsigned int zbbus_mhz;
47 47
48extern void sb1250_hpt_setup(void);
48extern void sb1250_time_init(void); 49extern void sb1250_time_init(void);
49extern unsigned long sb1250_gettimeoffset(void);
50extern void sb1250_mask_irq(int cpu, int irq); 50extern void sb1250_mask_irq(int cpu, int irq);
51extern void sb1250_unmask_irq(int cpu, int irq); 51extern void sb1250_unmask_irq(int cpu, int irq);
52extern void sb1250_smp_finish(void); 52extern void sb1250_smp_finish(void);
diff --git a/include/asm-mips/sibyte/sb1250_scd.h b/include/asm-mips/sibyte/sb1250_scd.h
index a667bc14a7c..f4178bdcfcb 100644
--- a/include/asm-mips/sibyte/sb1250_scd.h
+++ b/include/asm-mips/sibyte/sb1250_scd.h
@@ -359,14 +359,15 @@
359 */ 359 */
360 360
361#define V_SCD_TIMER_FREQ 1000000 361#define V_SCD_TIMER_FREQ 1000000
362#define V_SCD_TIMER_WIDTH 23
362 363
363#define S_SCD_TIMER_INIT 0 364#define S_SCD_TIMER_INIT 0
364#define M_SCD_TIMER_INIT _SB_MAKEMASK(20,S_SCD_TIMER_INIT) 365#define M_SCD_TIMER_INIT _SB_MAKEMASK(V_SCD_TIMER_WIDTH,S_SCD_TIMER_INIT)
365#define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT) 366#define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT)
366#define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT) 367#define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT)
367 368
368#define S_SCD_TIMER_CNT 0 369#define S_SCD_TIMER_CNT 0
369#define M_SCD_TIMER_CNT _SB_MAKEMASK(20,S_SCD_TIMER_CNT) 370#define M_SCD_TIMER_CNT _SB_MAKEMASK(V_SCD_TIMER_WIDTH,S_SCD_TIMER_CNT)
370#define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT) 371#define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT)
371#define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x,S_SCD_TIMER_CNT,M_SCD_TIMER_CNT) 372#define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x,S_SCD_TIMER_CNT,M_SCD_TIMER_CNT)
372 373
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 16:16:49 -0500