diff options
-rw-r--r-- | drivers/pci/hotplug/shpchp.h | 2 | ||||
-rw-r--r-- | drivers/pci/intel-iommu.c | 6 | ||||
-rw-r--r-- | drivers/pci/intr_remapping.c | 2 | ||||
-rw-r--r-- | drivers/pci/pci.c | 6 | ||||
-rw-r--r-- | drivers/pci/pcie/aer/aer_inject.c | 4 | ||||
-rw-r--r-- | drivers/pci/pcie/aer/aerdrv.c | 2 | ||||
-rw-r--r-- | drivers/pci/pcie/aer/aerdrv_acpi.c | 2 | ||||
-rw-r--r-- | drivers/pci/pcie/aer/aerdrv_core.c | 6 | ||||
-rw-r--r-- | drivers/pci/pcie/aspm.c | 4 | ||||
-rw-r--r-- | drivers/pci/search.c | 6 |
10 files changed, 20 insertions, 20 deletions
diff --git a/drivers/pci/hotplug/shpchp.h b/drivers/pci/hotplug/shpchp.h index bd588eb8e92..8e210cd76e5 100644 --- a/drivers/pci/hotplug/shpchp.h +++ b/drivers/pci/hotplug/shpchp.h | |||
@@ -121,7 +121,7 @@ struct controller { | |||
121 | #define PCI_DEVICE_ID_AMD_GOLAM_7450 0x7450 | 121 | #define PCI_DEVICE_ID_AMD_GOLAM_7450 0x7450 |
122 | #define PCI_DEVICE_ID_AMD_POGO_7458 0x7458 | 122 | #define PCI_DEVICE_ID_AMD_POGO_7458 0x7458 |
123 | 123 | ||
124 | /* AMD PCIX bridge registers */ | 124 | /* AMD PCI-X bridge registers */ |
125 | #define PCIX_MEM_BASE_LIMIT_OFFSET 0x1C | 125 | #define PCIX_MEM_BASE_LIMIT_OFFSET 0x1C |
126 | #define PCIX_MISCII_OFFSET 0x48 | 126 | #define PCIX_MISCII_OFFSET 0x48 |
127 | #define PCIX_MISC_BRIDGE_ERRORS_OFFSET 0x80 | 127 | #define PCIX_MISC_BRIDGE_ERRORS_OFFSET 0x80 |
diff --git a/drivers/pci/intel-iommu.c b/drivers/pci/intel-iommu.c index 8d615942631..25e15d518bd 100644 --- a/drivers/pci/intel-iommu.c +++ b/drivers/pci/intel-iommu.c | |||
@@ -304,7 +304,7 @@ struct device_domain_info { | |||
304 | int segment; /* PCI domain */ | 304 | int segment; /* PCI domain */ |
305 | u8 bus; /* PCI bus number */ | 305 | u8 bus; /* PCI bus number */ |
306 | u8 devfn; /* PCI devfn number */ | 306 | u8 devfn; /* PCI devfn number */ |
307 | struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */ | 307 | struct pci_dev *dev; /* it's NULL for PCIe-to-PCI bridge */ |
308 | struct intel_iommu *iommu; /* IOMMU used by this device */ | 308 | struct intel_iommu *iommu; /* IOMMU used by this device */ |
309 | struct dmar_domain *domain; /* pointer to domain */ | 309 | struct dmar_domain *domain; /* pointer to domain */ |
310 | }; | 310 | }; |
@@ -1611,7 +1611,7 @@ domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev, | |||
1611 | return ret; | 1611 | return ret; |
1612 | parent = parent->bus->self; | 1612 | parent = parent->bus->self; |
1613 | } | 1613 | } |
1614 | if (pci_is_pcie(tmp)) /* this is a PCIE-to-PCI bridge */ | 1614 | if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */ |
1615 | return domain_context_mapping_one(domain, | 1615 | return domain_context_mapping_one(domain, |
1616 | pci_domain_nr(tmp->subordinate), | 1616 | pci_domain_nr(tmp->subordinate), |
1617 | tmp->subordinate->number, 0, | 1617 | tmp->subordinate->number, 0, |
@@ -3319,7 +3319,7 @@ static void iommu_detach_dependent_devices(struct intel_iommu *iommu, | |||
3319 | parent->devfn); | 3319 | parent->devfn); |
3320 | parent = parent->bus->self; | 3320 | parent = parent->bus->self; |
3321 | } | 3321 | } |
3322 | if (pci_is_pcie(tmp)) /* this is a PCIE-to-PCI bridge */ | 3322 | if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */ |
3323 | iommu_detach_dev(iommu, | 3323 | iommu_detach_dev(iommu, |
3324 | tmp->subordinate->number, 0); | 3324 | tmp->subordinate->number, 0); |
3325 | else /* this is a legacy PCI bridge */ | 3325 | else /* this is a legacy PCI bridge */ |
diff --git a/drivers/pci/intr_remapping.c b/drivers/pci/intr_remapping.c index 1487bf2be86..c26caf18099 100644 --- a/drivers/pci/intr_remapping.c +++ b/drivers/pci/intr_remapping.c | |||
@@ -528,7 +528,7 @@ int set_msi_sid(struct irte *irte, struct pci_dev *dev) | |||
528 | 528 | ||
529 | bridge = pci_find_upstream_pcie_bridge(dev); | 529 | bridge = pci_find_upstream_pcie_bridge(dev); |
530 | if (bridge) { | 530 | if (bridge) { |
531 | if (pci_is_pcie(bridge))/* this is a PCIE-to-PCI/PCIX bridge */ | 531 | if (pci_is_pcie(bridge))/* this is a PCIe-to-PCI/PCIX bridge */ |
532 | set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16, | 532 | set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16, |
533 | (bridge->bus->number << 8) | dev->bus->number); | 533 | (bridge->bus->number << 8) | dev->bus->number); |
534 | else /* this is a legacy PCI bridge */ | 534 | else /* this is a legacy PCI bridge */ |
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 6011d064e89..d50522bf16b 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c | |||
@@ -1153,11 +1153,11 @@ pci_disable_device(struct pci_dev *dev) | |||
1153 | 1153 | ||
1154 | /** | 1154 | /** |
1155 | * pcibios_set_pcie_reset_state - set reset state for device dev | 1155 | * pcibios_set_pcie_reset_state - set reset state for device dev |
1156 | * @dev: the PCI-E device reset | 1156 | * @dev: the PCIe device reset |
1157 | * @state: Reset state to enter into | 1157 | * @state: Reset state to enter into |
1158 | * | 1158 | * |
1159 | * | 1159 | * |
1160 | * Sets the PCI-E reset state for the device. This is the default | 1160 | * Sets the PCIe reset state for the device. This is the default |
1161 | * implementation. Architecture implementations can override this. | 1161 | * implementation. Architecture implementations can override this. |
1162 | */ | 1162 | */ |
1163 | int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev, | 1163 | int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev, |
@@ -1168,7 +1168,7 @@ int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev, | |||
1168 | 1168 | ||
1169 | /** | 1169 | /** |
1170 | * pci_set_pcie_reset_state - set reset state for device dev | 1170 | * pci_set_pcie_reset_state - set reset state for device dev |
1171 | * @dev: the PCI-E device reset | 1171 | * @dev: the PCIe device reset |
1172 | * @state: Reset state to enter into | 1172 | * @state: Reset state to enter into |
1173 | * | 1173 | * |
1174 | * | 1174 | * |
diff --git a/drivers/pci/pcie/aer/aer_inject.c b/drivers/pci/pcie/aer/aer_inject.c index 7fcd5331b14..0cae0f2b353 100644 --- a/drivers/pci/pcie/aer/aer_inject.c +++ b/drivers/pci/pcie/aer/aer_inject.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * PCIE AER software error injection support. | 2 | * PCIe AER software error injection support. |
3 | * | 3 | * |
4 | * Debuging PCIE AER code is quite difficult because it is hard to | 4 | * Debuging PCIe AER code is quite difficult because it is hard to |
5 | * trigger various real hardware errors. Software based error | 5 | * trigger various real hardware errors. Software based error |
6 | * injection can fake almost all kinds of errors with the help of a | 6 | * injection can fake almost all kinds of errors with the help of a |
7 | * user space helper tool aer-inject, which can be gotten from: | 7 | * user space helper tool aer-inject, which can be gotten from: |
diff --git a/drivers/pci/pcie/aer/aerdrv.c b/drivers/pci/pcie/aer/aerdrv.c index 97a345927b5..21f215f4daa 100644 --- a/drivers/pci/pcie/aer/aerdrv.c +++ b/drivers/pci/pcie/aer/aerdrv.c | |||
@@ -155,7 +155,7 @@ static struct aer_rpc *aer_alloc_rpc(struct pcie_device *dev) | |||
155 | mutex_init(&rpc->rpc_mutex); | 155 | mutex_init(&rpc->rpc_mutex); |
156 | init_waitqueue_head(&rpc->wait_release); | 156 | init_waitqueue_head(&rpc->wait_release); |
157 | 157 | ||
158 | /* Use PCIE bus function to store rpc into PCIE device */ | 158 | /* Use PCIe bus function to store rpc into PCIe device */ |
159 | set_service_data(dev, rpc); | 159 | set_service_data(dev, rpc); |
160 | 160 | ||
161 | return rpc; | 161 | return rpc; |
diff --git a/drivers/pci/pcie/aer/aerdrv_acpi.c b/drivers/pci/pcie/aer/aerdrv_acpi.c index 8edb2f300e8..04814087658 100644 --- a/drivers/pci/pcie/aer/aerdrv_acpi.c +++ b/drivers/pci/pcie/aer/aerdrv_acpi.c | |||
@@ -24,7 +24,7 @@ | |||
24 | * | 24 | * |
25 | * @return: Zero on success. Nonzero otherwise. | 25 | * @return: Zero on success. Nonzero otherwise. |
26 | * | 26 | * |
27 | * Invoked when PCIE bus loads AER service driver. To avoid conflict with | 27 | * Invoked when PCIe bus loads AER service driver. To avoid conflict with |
28 | * BIOS AER support requires BIOS to yield AER control to OS native driver. | 28 | * BIOS AER support requires BIOS to yield AER control to OS native driver. |
29 | **/ | 29 | **/ |
30 | int aer_osc_setup(struct pcie_device *pciedev) | 30 | int aer_osc_setup(struct pcie_device *pciedev) |
diff --git a/drivers/pci/pcie/aer/aerdrv_core.c b/drivers/pci/pcie/aer/aerdrv_core.c index ae672ca8033..c843a799814 100644 --- a/drivers/pci/pcie/aer/aerdrv_core.c +++ b/drivers/pci/pcie/aer/aerdrv_core.c | |||
@@ -587,7 +587,7 @@ static void handle_error_source(struct pcie_device *aerdev, | |||
587 | * aer_enable_rootport - enable Root Port's interrupts when receiving messages | 587 | * aer_enable_rootport - enable Root Port's interrupts when receiving messages |
588 | * @rpc: pointer to a Root Port data structure | 588 | * @rpc: pointer to a Root Port data structure |
589 | * | 589 | * |
590 | * Invoked when PCIE bus loads AER service driver. | 590 | * Invoked when PCIe bus loads AER service driver. |
591 | */ | 591 | */ |
592 | void aer_enable_rootport(struct aer_rpc *rpc) | 592 | void aer_enable_rootport(struct aer_rpc *rpc) |
593 | { | 593 | { |
@@ -597,7 +597,7 @@ void aer_enable_rootport(struct aer_rpc *rpc) | |||
597 | u32 reg32; | 597 | u32 reg32; |
598 | 598 | ||
599 | pos = pci_pcie_cap(pdev); | 599 | pos = pci_pcie_cap(pdev); |
600 | /* Clear PCIE Capability's Device Status */ | 600 | /* Clear PCIe Capability's Device Status */ |
601 | pci_read_config_word(pdev, pos+PCI_EXP_DEVSTA, ®16); | 601 | pci_read_config_word(pdev, pos+PCI_EXP_DEVSTA, ®16); |
602 | pci_write_config_word(pdev, pos+PCI_EXP_DEVSTA, reg16); | 602 | pci_write_config_word(pdev, pos+PCI_EXP_DEVSTA, reg16); |
603 | 603 | ||
@@ -631,7 +631,7 @@ void aer_enable_rootport(struct aer_rpc *rpc) | |||
631 | * disable_root_aer - disable Root Port's interrupts when receiving messages | 631 | * disable_root_aer - disable Root Port's interrupts when receiving messages |
632 | * @rpc: pointer to a Root Port data structure | 632 | * @rpc: pointer to a Root Port data structure |
633 | * | 633 | * |
634 | * Invoked when PCIE bus unloads AER service driver. | 634 | * Invoked when PCIe bus unloads AER service driver. |
635 | */ | 635 | */ |
636 | static void disable_root_aer(struct aer_rpc *rpc) | 636 | static void disable_root_aer(struct aer_rpc *rpc) |
637 | { | 637 | { |
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 5a01fc7fbf0..be53d98fa38 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c | |||
@@ -1,6 +1,6 @@ | |||
1 | /* | 1 | /* |
2 | * File: drivers/pci/pcie/aspm.c | 2 | * File: drivers/pci/pcie/aspm.c |
3 | * Enabling PCIE link L0s/L1 state and Clock Power Management | 3 | * Enabling PCIe link L0s/L1 state and Clock Power Management |
4 | * | 4 | * |
5 | * Copyright (C) 2007 Intel | 5 | * Copyright (C) 2007 Intel |
6 | * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com) | 6 | * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com) |
@@ -499,7 +499,7 @@ static int pcie_aspm_sanity_check(struct pci_dev *pdev) | |||
499 | int pos; | 499 | int pos; |
500 | u32 reg32; | 500 | u32 reg32; |
501 | /* | 501 | /* |
502 | * Some functions in a slot might not all be PCIE functions, | 502 | * Some functions in a slot might not all be PCIe functions, |
503 | * very strange. Disable ASPM for the whole slot | 503 | * very strange. Disable ASPM for the whole slot |
504 | */ | 504 | */ |
505 | list_for_each_entry(child, &pdev->subordinate->devices, bus_list) { | 505 | list_for_each_entry(child, &pdev->subordinate->devices, bus_list) { |
diff --git a/drivers/pci/search.c b/drivers/pci/search.c index 6dae8714325..4a471dc4f4b 100644 --- a/drivers/pci/search.c +++ b/drivers/pci/search.c | |||
@@ -15,9 +15,9 @@ | |||
15 | 15 | ||
16 | DECLARE_RWSEM(pci_bus_sem); | 16 | DECLARE_RWSEM(pci_bus_sem); |
17 | /* | 17 | /* |
18 | * find the upstream PCIE-to-PCI bridge of a PCI device | 18 | * find the upstream PCIe-to-PCI bridge of a PCI device |
19 | * if the device is PCIE, return NULL | 19 | * if the device is PCIE, return NULL |
20 | * if the device isn't connected to a PCIE bridge (that is its parent is a | 20 | * if the device isn't connected to a PCIe bridge (that is its parent is a |
21 | * legacy PCI bridge and the bridge is directly connected to bus 0), return its | 21 | * legacy PCI bridge and the bridge is directly connected to bus 0), return its |
22 | * parent | 22 | * parent |
23 | */ | 23 | */ |
@@ -37,7 +37,7 @@ pci_find_upstream_pcie_bridge(struct pci_dev *pdev) | |||
37 | tmp = pdev; | 37 | tmp = pdev; |
38 | continue; | 38 | continue; |
39 | } | 39 | } |
40 | /* PCI device should connect to a PCIE bridge */ | 40 | /* PCI device should connect to a PCIe bridge */ |
41 | if (pdev->pcie_type != PCI_EXP_TYPE_PCI_BRIDGE) { | 41 | if (pdev->pcie_type != PCI_EXP_TYPE_PCI_BRIDGE) { |
42 | /* Busted hardware? */ | 42 | /* Busted hardware? */ |
43 | WARN_ON_ONCE(1); | 43 | WARN_ON_ONCE(1); |