diff options
| -rw-r--r-- | include/asm-arm/arch-at91rm9200/at91_rstc.h | 2 | ||||
| -rw-r--r-- | include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h | 2 | ||||
| -rw-r--r-- | include/asm-arm/arch-at91rm9200/at91sam926x_mc.h | 8 |
3 files changed, 6 insertions, 6 deletions
diff --git a/include/asm-arm/arch-at91rm9200/at91_rstc.h b/include/asm-arm/arch-at91rm9200/at91_rstc.h index ccdc52da973..237d3c40b31 100644 --- a/include/asm-arm/arch-at91rm9200/at91_rstc.h +++ b/include/asm-arm/arch-at91rm9200/at91_rstc.h | |||
| @@ -17,7 +17,7 @@ | |||
| 17 | #define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ | 17 | #define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ |
| 18 | #define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ | 18 | #define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ |
| 19 | #define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ | 19 | #define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ |
| 20 | #define AT01_RSTC_KEY (0xff << 24) /* KEY Password */ | 20 | #define AT91_RSTC_KEY (0xff << 24) /* KEY Password */ |
| 21 | 21 | ||
| 22 | #define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */ | 22 | #define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */ |
| 23 | #define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ | 23 | #define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ |
diff --git a/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h b/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h index 270a5dcdf1c..ab25f9e94d6 100644 --- a/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h +++ b/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h | |||
| @@ -15,7 +15,7 @@ | |||
| 15 | 15 | ||
| 16 | #define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */ | 16 | #define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */ |
| 17 | #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ | 17 | #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ |
| 18 | #define AT01_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ | 18 | #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ |
| 19 | 19 | ||
| 20 | #define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */ | 20 | #define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */ |
| 21 | #define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */ | 21 | #define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */ |
diff --git a/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h b/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h index 7d94968b5d5..8ac797e39a1 100644 --- a/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h +++ b/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h | |||
| @@ -110,10 +110,10 @@ | |||
| 110 | #define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ | 110 | #define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ |
| 111 | #define AT91_SMC_READMODE (1 << 0) /* Read Mode */ | 111 | #define AT91_SMC_READMODE (1 << 0) /* Read Mode */ |
| 112 | #define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ | 112 | #define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ |
| 113 | #define AT91_SMC_EXNWMODE (3 << 5) /* NWAIT Mode */ | 113 | #define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ |
| 114 | #define AT91_SMC_EXNWMODE_DISABLE (0 << 5) | 114 | #define AT91_SMC_EXNWMODE_DISABLE (0 << 4) |
| 115 | #define AT91_SMC_EXNWMODE_FROZEN (2 << 5) | 115 | #define AT91_SMC_EXNWMODE_FROZEN (2 << 4) |
| 116 | #define AT91_SMC_EXNWMODE_READY (3 << 5) | 116 | #define AT91_SMC_EXNWMODE_READY (3 << 4) |
| 117 | #define AT91_SMC_BAT (1 << 8) /* Byte Access Type */ | 117 | #define AT91_SMC_BAT (1 << 8) /* Byte Access Type */ |
| 118 | #define AT91_SMC_BAT_SELECT (0 << 8) | 118 | #define AT91_SMC_BAT_SELECT (0 << 8) |
| 119 | #define AT91_SMC_BAT_WRITE (1 << 8) | 119 | #define AT91_SMC_BAT_WRITE (1 << 8) |