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-rw-r--r--arch/arm/mach-integrator/Makefile1
-rw-r--r--arch/arm/mach-integrator/core.c18
-rw-r--r--arch/arm/mach-integrator/headsmp.S37
-rw-r--r--arch/arm/mach-integrator/platsmp.c204
-rw-r--r--include/asm-arm/arch-integrator/smp.h18
5 files changed, 1 insertions, 277 deletions
diff --git a/arch/arm/mach-integrator/Makefile b/arch/arm/mach-integrator/Makefile
index ebb255bdce8..158daaf9e3b 100644
--- a/arch/arm/mach-integrator/Makefile
+++ b/arch/arm/mach-integrator/Makefile
@@ -12,4 +12,3 @@ obj-$(CONFIG_LEDS) += leds.o
12obj-$(CONFIG_PCI) += pci_v3.o pci.o 12obj-$(CONFIG_PCI) += pci_v3.o pci.o
13obj-$(CONFIG_CPU_FREQ_INTEGRATOR) += cpu.o 13obj-$(CONFIG_CPU_FREQ_INTEGRATOR) += cpu.o
14obj-$(CONFIG_INTEGRATOR_IMPD1) += impd1.o 14obj-$(CONFIG_INTEGRATOR_IMPD1) += impd1.o
15obj-$(CONFIG_SMP) += platsmp.o headsmp.o
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 897c21c2fb5..e9c82deb791 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -257,23 +257,7 @@ integrator_timer_interrupt(int irq, void *dev_id)
257 */ 257 */
258 writel(1, TIMER1_VA_BASE + TIMER_INTCLR); 258 writel(1, TIMER1_VA_BASE + TIMER_INTCLR);
259 259
260 /* 260 timer_tick();
261 * the clock tick routines are only processed on the
262 * primary CPU
263 */
264 if (hard_smp_processor_id() == 0) {
265 timer_tick();
266#ifdef CONFIG_SMP
267 smp_send_timer();
268#endif
269 }
270
271#ifdef CONFIG_SMP
272 /*
273 * this is the ARM equivalent of the APIC timer interrupt
274 */
275 update_process_times(user_mode(get_irq_regs()));
276#endif /* CONFIG_SMP */
277 261
278 write_sequnlock(&xtime_lock); 262 write_sequnlock(&xtime_lock);
279 263
diff --git a/arch/arm/mach-integrator/headsmp.S b/arch/arm/mach-integrator/headsmp.S
deleted file mode 100644
index ceaa88e30d7..00000000000
--- a/arch/arm/mach-integrator/headsmp.S
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * linux/arch/arm/mach-integrator/headsmp.S
3 *
4 * Copyright (c) 2003 ARM Limited
5 * All Rights Reserved
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/linkage.h>
12#include <linux/init.h>
13
14 __INIT
15
16/*
17 * Integrator specific entry point for secondary CPUs. This provides
18 * a "holding pen" into which all secondary cores are held until we're
19 * ready for them to initialise.
20 */
21ENTRY(integrator_secondary_startup)
22 adr r4, 1f
23 ldmia r4, {r5, r6}
24 sub r4, r4, r5
25 ldr r6, [r6, r4]
26pen: ldr r7, [r6]
27 cmp r7, r0
28 bne pen
29
30 /*
31 * we've been released from the holding pen: secondary_stack
32 * should now contain the SVC stack for this core
33 */
34 b secondary_startup
35
361: .long .
37 .long phys_pen_release
diff --git a/arch/arm/mach-integrator/platsmp.c b/arch/arm/mach-integrator/platsmp.c
deleted file mode 100644
index 613b841a10f..00000000000
--- a/arch/arm/mach-integrator/platsmp.c
+++ /dev/null
@@ -1,204 +0,0 @@
1/*
2 * linux/arch/arm/mach-cintegrator/platsmp.c
3 *
4 * Copyright (C) 2002 ARM Ltd.
5 * All Rights Reserved
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/sched.h>
14#include <linux/errno.h>
15#include <linux/mm.h>
16
17#include <asm/atomic.h>
18#include <asm/cacheflush.h>
19#include <asm/delay.h>
20#include <asm/mmu_context.h>
21#include <asm/ptrace.h>
22#include <asm/smp.h>
23
24extern void integrator_secondary_startup(void);
25
26/*
27 * control for which core is the next to come out of the secondary
28 * boot "holding pen"
29 */
30volatile int __cpuinitdata pen_release = -1;
31unsigned long __cpuinitdata phys_pen_release = 0;
32
33static DEFINE_SPINLOCK(boot_lock);
34
35void __cpuinit platform_secondary_init(unsigned int cpu)
36{
37 /*
38 * the primary core may have used a "cross call" soft interrupt
39 * to get this processor out of WFI in the BootMonitor - make
40 * sure that we are no longer being sent this soft interrupt
41 */
42 smp_cross_call_done(cpumask_of_cpu(cpu));
43
44 /*
45 * if any interrupts are already enabled for the primary
46 * core (e.g. timer irq), then they will not have been enabled
47 * for us: do so
48 */
49 secondary_scan_irqs();
50
51 /*
52 * let the primary processor know we're out of the
53 * pen, then head off into the C entry point
54 */
55 pen_release = -1;
56
57 /*
58 * Synchronise with the boot thread.
59 */
60 spin_lock(&boot_lock);
61 spin_unlock(&boot_lock);
62}
63
64int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
65{
66 unsigned long timeout;
67
68 /*
69 * set synchronisation state between this boot processor
70 * and the secondary one
71 */
72 spin_lock(&boot_lock);
73
74 /*
75 * The secondary processor is waiting to be released from
76 * the holding pen - release it, then wait for it to flag
77 * that it has been released by resetting pen_release.
78 *
79 * Note that "pen_release" is the hardware CPU ID, whereas
80 * "cpu" is Linux's internal ID.
81 */
82 pen_release = cpu;
83 flush_cache_all();
84
85 /*
86 * XXX
87 *
88 * This is a later addition to the booting protocol: the
89 * bootMonitor now puts secondary cores into WFI, so
90 * poke_milo() no longer gets the cores moving; we need
91 * to send a soft interrupt to wake the secondary core.
92 * Use smp_cross_call() for this, since there's little
93 * point duplicating the code here
94 */
95 smp_cross_call(cpumask_of_cpu(cpu));
96
97 timeout = jiffies + (1 * HZ);
98 while (time_before(jiffies, timeout)) {
99 if (pen_release == -1)
100 break;
101
102 udelay(10);
103 }
104
105 /*
106 * now the secondary core is starting up let it run its
107 * calibrations, then wait for it to finish
108 */
109 spin_unlock(&boot_lock);
110
111 return pen_release != -1 ? -ENOSYS : 0;
112}
113
114static void __init poke_milo(void)
115{
116 extern void secondary_startup(void);
117
118 /* nobody is to be released from the pen yet */
119 pen_release = -1;
120
121 phys_pen_release = virt_to_phys(&pen_release);
122
123 /*
124 * write the address of secondary startup into the system-wide
125 * flags register, then clear the bottom two bits, which is what
126 * BootMonitor is waiting for
127 */
128#if 1
129#define CINTEGRATOR_HDR_FLAGSS_OFFSET 0x30
130 __raw_writel(virt_to_phys(integrator_secondary_startup),
131 (IO_ADDRESS(INTEGRATOR_HDR_BASE) +
132 CINTEGRATOR_HDR_FLAGSS_OFFSET));
133#define CINTEGRATOR_HDR_FLAGSC_OFFSET 0x34
134 __raw_writel(3,
135 (IO_ADDRESS(INTEGRATOR_HDR_BASE) +
136 CINTEGRATOR_HDR_FLAGSC_OFFSET));
137#endif
138
139 mb();
140}
141
142/*
143 * Initialise the CPU possible map early - this describes the CPUs
144 * which may be present or become present in the system.
145 */
146void __init smp_init_cpus(void)
147{
148 unsigned int i, ncores = get_core_count();
149
150 for (i = 0; i < ncores; i++)
151 cpu_set(i, cpu_possible_map);
152}
153
154void __init smp_prepare_cpus(unsigned int max_cpus)
155{
156 unsigned int ncores = get_core_count();
157 unsigned int cpu = smp_processor_id();
158 int i;
159
160 /* sanity check */
161 if (ncores == 0) {
162 printk(KERN_ERR
163 "Integrator/CP: strange CM count of 0? Default to 1\n");
164
165 ncores = 1;
166 }
167
168 if (ncores > NR_CPUS) {
169 printk(KERN_WARNING
170 "Integrator/CP: no. of cores (%d) greater than configured "
171 "maximum of %d - clipping\n",
172 ncores, NR_CPUS);
173 ncores = NR_CPUS;
174 }
175
176 /*
177 * start with some more config for the Boot CPU, now that
178 * the world is a bit more alive (which was not the case
179 * when smp_prepare_boot_cpu() was called)
180 */
181 smp_store_cpu_info(cpu);
182
183 /*
184 * are we trying to boot more cores than exist?
185 */
186 if (max_cpus > ncores)
187 max_cpus = ncores;
188
189 /*
190 * Initialise the present map, which describes the set of CPUs
191 * actually populated at the present time.
192 */
193 for (i = 0; i < max_cpus; i++)
194 cpu_set(i, cpu_present_map);
195
196 /*
197 * Do we need any more CPUs? If so, then let them know where
198 * to start. Note that, on modern versions of MILO, the "poke"
199 * doesn't actually do anything until each individual core is
200 * sent a soft interrupt to get it out of WFI
201 */
202 if (max_cpus > 1)
203 poke_milo();
204}
diff --git a/include/asm-arm/arch-integrator/smp.h b/include/asm-arm/arch-integrator/smp.h
deleted file mode 100644
index ab2c79bb950..00000000000
--- a/include/asm-arm/arch-integrator/smp.h
+++ /dev/null
@@ -1,18 +0,0 @@
1#ifndef ASMARM_ARCH_SMP_H
2#define ASMARM_ARCH_SMP_H
3
4
5#include <asm/hardware.h>
6#include <asm/io.h>
7
8#define hard_smp_processor_id() \
9 ({ \
10 unsigned int cpunum; \
11 __asm__("mrc p15, 0, %0, c0, c0, 5" \
12 : "=r" (cpunum)); \
13 cpunum &= 0x0F; \
14 })
15
16extern void secondary_scan_irqs(void);
17
18#endif
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