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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2008-08-07 04:55:03 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-08-07 04:55:03 -0400
commit4fb8af10d0fd09372d52966b76922b9e82bbc950 (patch)
treed240e4d40357583e3f3eb228dccf20122a5b31ed /include
parentf44f82e8a20b98558486eb14497b2f71c78fa325 (diff)
parent64a99d2a8c3ed5c4e39f3ae1cc682aa8fd3977fc (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/sam/kbuild-fixes
Diffstat (limited to 'include')
-rw-r--r--include/acpi/actbl.h1
-rw-r--r--include/asm-arm/arch-s3c2410/spi.h1
-rw-r--r--include/asm-arm/plat-s3c/iic.h1
-rw-r--r--include/asm-cris/dma-mapping.h2
-rw-r--r--include/asm-frv/unistd.h8
-rw-r--r--include/asm-generic/dma-coherent.h32
-rw-r--r--include/asm-generic/gpio.h1
-rw-r--r--include/asm-generic/pgtable-nopmd.h6
-rw-r--r--include/asm-generic/vmlinux.lds.h14
-rw-r--r--include/asm-ia64/Kbuild16
-rw-r--r--include/asm-ia64/a.out.h32
-rw-r--r--include/asm-ia64/acpi-ext.h21
-rw-r--r--include/asm-ia64/acpi.h167
-rw-r--r--include/asm-ia64/agp.h30
-rw-r--r--include/asm-ia64/asmmacro.h135
-rw-r--r--include/asm-ia64/atomic.h226
-rw-r--r--include/asm-ia64/auxvec.h11
-rw-r--r--include/asm-ia64/bitops.h468
-rw-r--r--include/asm-ia64/break.h23
-rw-r--r--include/asm-ia64/bug.h14
-rw-r--r--include/asm-ia64/bugs.h19
-rw-r--r--include/asm-ia64/byteorder.h42
-rw-r--r--include/asm-ia64/cache.h29
-rw-r--r--include/asm-ia64/cacheflush.h51
-rw-r--r--include/asm-ia64/checksum.h79
-rw-r--r--include/asm-ia64/compat.h207
-rw-r--r--include/asm-ia64/cpu.h22
-rw-r--r--include/asm-ia64/cputime.h110
-rw-r--r--include/asm-ia64/current.h17
-rw-r--r--include/asm-ia64/cyclone.h15
-rw-r--r--include/asm-ia64/delay.h88
-rw-r--r--include/asm-ia64/device.h15
-rw-r--r--include/asm-ia64/div64.h1
-rw-r--r--include/asm-ia64/dma-mapping.h97
-rw-r--r--include/asm-ia64/dma.h24
-rw-r--r--include/asm-ia64/dmi.h11
-rw-r--r--include/asm-ia64/elf.h269
-rw-r--r--include/asm-ia64/emergency-restart.h6
-rw-r--r--include/asm-ia64/errno.h1
-rw-r--r--include/asm-ia64/esi.h29
-rw-r--r--include/asm-ia64/fb.h23
-rw-r--r--include/asm-ia64/fcntl.h13
-rw-r--r--include/asm-ia64/fpswa.h73
-rw-r--r--include/asm-ia64/fpu.h66
-rw-r--r--include/asm-ia64/futex.h124
-rw-r--r--include/asm-ia64/gcc_intrin.h620
-rw-r--r--include/asm-ia64/hardirq.h37
-rw-r--r--include/asm-ia64/hpsim.h16
-rw-r--r--include/asm-ia64/hugetlb.h80
-rw-r--r--include/asm-ia64/hw_irq.h192
-rw-r--r--include/asm-ia64/ia32.h40
-rw-r--r--include/asm-ia64/ia64regs.h100
-rw-r--r--include/asm-ia64/intel_intrin.h161
-rw-r--r--include/asm-ia64/intrinsics.h241
-rw-r--r--include/asm-ia64/io.h459
-rw-r--r--include/asm-ia64/ioctl.h1
-rw-r--r--include/asm-ia64/ioctls.h93
-rw-r--r--include/asm-ia64/iosapic.h126
-rw-r--r--include/asm-ia64/ipcbuf.h28
-rw-r--r--include/asm-ia64/irq.h34
-rw-r--r--include/asm-ia64/irq_regs.h1
-rw-r--r--include/asm-ia64/kdebug.h59
-rw-r--r--include/asm-ia64/kexec.h44
-rw-r--r--include/asm-ia64/kmap_types.h30
-rw-r--r--include/asm-ia64/kprobes.h133
-rw-r--r--include/asm-ia64/kregs.h165
-rw-r--r--include/asm-ia64/kvm.h211
-rw-r--r--include/asm-ia64/kvm_host.h527
-rw-r--r--include/asm-ia64/kvm_para.h29
-rw-r--r--include/asm-ia64/libata-portmap.h12
-rw-r--r--include/asm-ia64/linkage.h14
-rw-r--r--include/asm-ia64/local.h1
-rw-r--r--include/asm-ia64/machvec.h460
-rw-r--r--include/asm-ia64/machvec_dig.h16
-rw-r--r--include/asm-ia64/machvec_hpsim.h18
-rw-r--r--include/asm-ia64/machvec_hpzx1.h37
-rw-r--r--include/asm-ia64/machvec_hpzx1_swiotlb.h42
-rw-r--r--include/asm-ia64/machvec_init.h33
-rw-r--r--include/asm-ia64/machvec_sn2.h139
-rw-r--r--include/asm-ia64/machvec_uv.h26
-rw-r--r--include/asm-ia64/mc146818rtc.h10
-rw-r--r--include/asm-ia64/mca.h179
-rw-r--r--include/asm-ia64/mca_asm.h242
-rw-r--r--include/asm-ia64/meminit.h75
-rw-r--r--include/asm-ia64/mman.h33
-rw-r--r--include/asm-ia64/mmu.h13
-rw-r--r--include/asm-ia64/mmu_context.h198
-rw-r--r--include/asm-ia64/mmzone.h50
-rw-r--r--include/asm-ia64/module.h36
-rw-r--r--include/asm-ia64/msgbuf.h27
-rw-r--r--include/asm-ia64/mutex.h92
-rw-r--r--include/asm-ia64/native/inst.h175
-rw-r--r--include/asm-ia64/native/irq.h35
-rw-r--r--include/asm-ia64/nodedata.h63
-rw-r--r--include/asm-ia64/numa.h82
-rw-r--r--include/asm-ia64/page.h223
-rw-r--r--include/asm-ia64/pal.h1827
-rw-r--r--include/asm-ia64/param.h33
-rw-r--r--include/asm-ia64/paravirt.h255
-rw-r--r--include/asm-ia64/paravirt_privop.h114
-rw-r--r--include/asm-ia64/parport.h20
-rw-r--r--include/asm-ia64/patch.h27
-rw-r--r--include/asm-ia64/pci.h167
-rw-r--r--include/asm-ia64/percpu.h51
-rw-r--r--include/asm-ia64/perfmon.h279
-rw-r--r--include/asm-ia64/perfmon_default_smpl.h83
-rw-r--r--include/asm-ia64/pgalloc.h122
-rw-r--r--include/asm-ia64/pgtable.h615
-rw-r--r--include/asm-ia64/poll.h1
-rw-r--r--include/asm-ia64/posix_types.h126
-rw-r--r--include/asm-ia64/processor.h771
-rw-r--r--include/asm-ia64/ptrace.h364
-rw-r--r--include/asm-ia64/ptrace_offsets.h268
-rw-r--r--include/asm-ia64/resource.h7
-rw-r--r--include/asm-ia64/rse.h66
-rw-r--r--include/asm-ia64/rwsem.h182
-rw-r--r--include/asm-ia64/sal.h905
-rw-r--r--include/asm-ia64/scatterlist.h38
-rw-r--r--include/asm-ia64/sections.h25
-rw-r--r--include/asm-ia64/segment.h6
-rw-r--r--include/asm-ia64/sembuf.h22
-rw-r--r--include/asm-ia64/serial.h19
-rw-r--r--include/asm-ia64/setup.h6
-rw-r--r--include/asm-ia64/shmbuf.h38
-rw-r--r--include/asm-ia64/shmparam.h12
-rw-r--r--include/asm-ia64/sigcontext.h70
-rw-r--r--include/asm-ia64/siginfo.h139
-rw-r--r--include/asm-ia64/signal.h160
-rw-r--r--include/asm-ia64/smp.h138
-rw-r--r--include/asm-ia64/sn/acpi.h17
-rw-r--r--include/asm-ia64/sn/addrs.h299
-rw-r--r--include/asm-ia64/sn/arch.h86
-rw-r--r--include/asm-ia64/sn/bte.h233
-rw-r--r--include/asm-ia64/sn/clksupport.h28
-rw-r--r--include/asm-ia64/sn/geo.h132
-rw-r--r--include/asm-ia64/sn/intr.h68
-rw-r--r--include/asm-ia64/sn/io.h274
-rw-r--r--include/asm-ia64/sn/ioc3.h241
-rw-r--r--include/asm-ia64/sn/klconfig.h246
-rw-r--r--include/asm-ia64/sn/l1.h51
-rw-r--r--include/asm-ia64/sn/leds.h33
-rw-r--r--include/asm-ia64/sn/module.h127
-rw-r--r--include/asm-ia64/sn/mspec.h59
-rw-r--r--include/asm-ia64/sn/nodepda.h82
-rw-r--r--include/asm-ia64/sn/pcibr_provider.h150
-rw-r--r--include/asm-ia64/sn/pcibus_provider_defs.h68
-rw-r--r--include/asm-ia64/sn/pcidev.h85
-rw-r--r--include/asm-ia64/sn/pda.h69
-rw-r--r--include/asm-ia64/sn/pic.h261
-rw-r--r--include/asm-ia64/sn/rw_mmr.h28
-rw-r--r--include/asm-ia64/sn/shub_mmr.h502
-rw-r--r--include/asm-ia64/sn/shubio.h3358
-rw-r--r--include/asm-ia64/sn/simulator.h25
-rw-r--r--include/asm-ia64/sn/sn2/sn_hwperf.h242
-rw-r--r--include/asm-ia64/sn/sn_cpuid.h132
-rw-r--r--include/asm-ia64/sn/sn_feature_sets.h58
-rw-r--r--include/asm-ia64/sn/sn_sal.h1188
-rw-r--r--include/asm-ia64/sn/tioca.h596
-rw-r--r--include/asm-ia64/sn/tioca_provider.h207
-rw-r--r--include/asm-ia64/sn/tioce.h760
-rw-r--r--include/asm-ia64/sn/tioce_provider.h63
-rw-r--r--include/asm-ia64/sn/tiocp.h257
-rw-r--r--include/asm-ia64/sn/tiocx.h72
-rw-r--r--include/asm-ia64/sn/types.h26
-rw-r--r--include/asm-ia64/socket.h66
-rw-r--r--include/asm-ia64/sockios.h20
-rw-r--r--include/asm-ia64/sparsemem.h20
-rw-r--r--include/asm-ia64/spinlock.h220
-rw-r--r--include/asm-ia64/spinlock_types.h21
-rw-r--r--include/asm-ia64/stat.h51
-rw-r--r--include/asm-ia64/statfs.h62
-rw-r--r--include/asm-ia64/string.h21
-rw-r--r--include/asm-ia64/suspend.h1
-rw-r--r--include/asm-ia64/system.h292
-rw-r--r--include/asm-ia64/termbits.h207
-rw-r--r--include/asm-ia64/termios.h97
-rw-r--r--include/asm-ia64/thread_info.h148
-rw-r--r--include/asm-ia64/timex.h42
-rw-r--r--include/asm-ia64/tlb.h257
-rw-r--r--include/asm-ia64/tlbflush.h102
-rw-r--r--include/asm-ia64/topology.h128
-rw-r--r--include/asm-ia64/types.h46
-rw-r--r--include/asm-ia64/uaccess.h401
-rw-r--r--include/asm-ia64/ucontext.h12
-rw-r--r--include/asm-ia64/unaligned.h11
-rw-r--r--include/asm-ia64/uncached.h12
-rw-r--r--include/asm-ia64/unistd.h384
-rw-r--r--include/asm-ia64/unwind.h233
-rw-r--r--include/asm-ia64/user.h58
-rw-r--r--include/asm-ia64/ustack.h20
-rw-r--r--include/asm-ia64/uv/uv_hub.h309
-rw-r--r--include/asm-ia64/uv/uv_mmrs.h673
-rw-r--r--include/asm-ia64/vga.h25
-rw-r--r--include/asm-ia64/xor.h33
-rw-r--r--include/asm-m68k/contregs.h51
-rw-r--r--include/asm-m68k/fbio.h331
-rw-r--r--include/asm-m68k/idprom.h21
-rw-r--r--include/asm-mips/gdb-stub.h215
-rw-r--r--include/asm-mips/kdebug.h14
-rw-r--r--include/asm-mips/kgdb.h44
-rw-r--r--include/asm-mips/pci.h2
-rw-r--r--include/asm-mips/txx9/generic.h14
-rw-r--r--include/asm-mips/txx9/jmr3927.h2
-rw-r--r--include/asm-mips/txx9/pci.h3
-rw-r--r--include/asm-mips/txx9/smsc_fdc37m81x.h2
-rw-r--r--include/asm-mips/txx9/tx3927.h25
-rw-r--r--include/asm-mips/txx9/tx4927.h5
-rw-r--r--include/asm-mips/txx9/tx4927pcic.h8
-rw-r--r--include/asm-mips/txx9/tx4938.h7
-rw-r--r--include/asm-mips/txx9/txx927.h121
-rw-r--r--include/asm-mips/txx9irq.h4
-rw-r--r--include/asm-mn10300/unistd.h6
-rw-r--r--include/asm-powerpc/8253pit.h10
-rw-r--r--include/asm-powerpc/8xx_immap.h564
-rw-r--r--include/asm-powerpc/Kbuild37
-rw-r--r--include/asm-powerpc/a.out.h20
-rw-r--r--include/asm-powerpc/abs_addr.h75
-rw-r--r--include/asm-powerpc/agp.h22
-rw-r--r--include/asm-powerpc/asm-compat.h69
-rw-r--r--include/asm-powerpc/atomic.h479
-rw-r--r--include/asm-powerpc/auxvec.h19
-rw-r--r--include/asm-powerpc/backlight.h41
-rw-r--r--include/asm-powerpc/bitops.h410
-rw-r--r--include/asm-powerpc/bootx.h171
-rw-r--r--include/asm-powerpc/btext.h28
-rw-r--r--include/asm-powerpc/bug.h121
-rw-r--r--include/asm-powerpc/bugs.h18
-rw-r--r--include/asm-powerpc/byteorder.h89
-rw-r--r--include/asm-powerpc/cache.h45
-rw-r--r--include/asm-powerpc/cacheflush.h75
-rw-r--r--include/asm-powerpc/cell-pmu.h105
-rw-r--r--include/asm-powerpc/cell-regs.h315
-rw-r--r--include/asm-powerpc/checksum.h117
-rw-r--r--include/asm-powerpc/clk_interface.h20
-rw-r--r--include/asm-powerpc/code-patching.h54
-rw-r--r--include/asm-powerpc/compat.h214
-rw-r--r--include/asm-powerpc/cpm.h103
-rw-r--r--include/asm-powerpc/cpm1.h652
-rw-r--r--include/asm-powerpc/cpm2.h1175
-rw-r--r--include/asm-powerpc/cputable.h514
-rw-r--r--include/asm-powerpc/cputhreads.h71
-rw-r--r--include/asm-powerpc/cputime.h235
-rw-r--r--include/asm-powerpc/current.h40
-rw-r--r--include/asm-powerpc/dbdma.h108
-rw-r--r--include/asm-powerpc/dcr-generic.h49
-rw-r--r--include/asm-powerpc/dcr-mmio.h61
-rw-r--r--include/asm-powerpc/dcr-native.h116
-rw-r--r--include/asm-powerpc/dcr-regs.h149
-rw-r--r--include/asm-powerpc/dcr.h82
-rw-r--r--include/asm-powerpc/delay.h34
-rw-r--r--include/asm-powerpc/device.h24
-rw-r--r--include/asm-powerpc/div64.h1
-rw-r--r--include/asm-powerpc/dma-mapping.h474
-rw-r--r--include/asm-powerpc/dma.h360
-rw-r--r--include/asm-powerpc/edac.h40
-rw-r--r--include/asm-powerpc/eeh.h211
-rw-r--r--include/asm-powerpc/eeh_event.h53
-rw-r--r--include/asm-powerpc/elf.h424
-rw-r--r--include/asm-powerpc/emergency-restart.h1
-rw-r--r--include/asm-powerpc/errno.h11
-rw-r--r--include/asm-powerpc/exception.h311
-rw-r--r--include/asm-powerpc/fb.h21
-rw-r--r--include/asm-powerpc/fcntl.h11
-rw-r--r--include/asm-powerpc/feature-fixups.h126
-rw-r--r--include/asm-powerpc/firmware.h132
-rw-r--r--include/asm-powerpc/fixmap.h106
-rw-r--r--include/asm-powerpc/floppy.h213
-rw-r--r--include/asm-powerpc/fs_pd.h50
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-rw-r--r--include/asm-powerpc/fsl_lbc.h311
-rw-r--r--include/asm-powerpc/ftrace.h14
-rw-r--r--include/asm-powerpc/futex.h117
-rw-r--r--include/asm-powerpc/gpio.h56
-rw-r--r--include/asm-powerpc/grackle.h12
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-rw-r--r--include/asm-powerpc/heathrow.h67
-rw-r--r--include/asm-powerpc/highmem.h138
-rw-r--r--include/asm-powerpc/hugetlb.h75
-rw-r--r--include/asm-powerpc/hvcall.h296
-rw-r--r--include/asm-powerpc/hvconsole.h41
-rw-r--r--include/asm-powerpc/hvcserver.h59
-rw-r--r--include/asm-powerpc/hw_irq.h135
-rw-r--r--include/asm-powerpc/hydra.h102
-rw-r--r--include/asm-powerpc/i8259.h17
-rw-r--r--include/asm-powerpc/ibmebus.h60
-rw-r--r--include/asm-powerpc/ide.h59
-rw-r--r--include/asm-powerpc/immap_86xx.h156
-rw-r--r--include/asm-powerpc/immap_cpm2.h650
-rw-r--r--include/asm-powerpc/immap_qe.h485
-rw-r--r--include/asm-powerpc/io-defs.h60
-rw-r--r--include/asm-powerpc/io.h787
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-rw-r--r--include/asm-powerpc/ioctls.h110
-rw-r--r--include/asm-powerpc/iommu.h131
-rw-r--r--include/asm-powerpc/ipcbuf.h34
-rw-r--r--include/asm-powerpc/ipic.h93
-rw-r--r--include/asm-powerpc/irq.h654
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-rw-r--r--include/asm-powerpc/iseries/hv_call.h111
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-rw-r--r--include/asm-powerpc/kvm_ppc.h95
-rw-r--r--include/asm-powerpc/libata-portmap.h12
-rw-r--r--include/asm-powerpc/linkage.h6
-rw-r--r--include/asm-powerpc/lmb.h15
-rw-r--r--include/asm-powerpc/local.h200
-rw-r--r--include/asm-powerpc/lppaca.h159
-rw-r--r--include/asm-powerpc/lv1call.h348
-rw-r--r--include/asm-powerpc/machdep.h365
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-rw-r--r--include/asm-powerpc/mmu_context.h280
-rw-r--r--include/asm-powerpc/mmzone.h47
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-rw-r--r--include/asm-sparc/system_32.h288
-rw-r--r--include/asm-sparc/system_64.h355
-rw-r--r--include/asm-sparc/termbits.h266
-rw-r--r--include/asm-sparc/termios.h186
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-rw-r--r--include/asm-sparc/thread_info_32.h153
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-rw-r--r--include/asm-sparc/tlbflush_32.h60
-rw-r--r--include/asm-sparc/tlbflush_64.h44
-rw-r--r--include/asm-sparc/topology.h8
-rw-r--r--include/asm-sparc/topology_32.h6
-rw-r--r--include/asm-sparc/topology_64.h86
-rw-r--r--include/asm-sparc/traps.h140
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-rw-r--r--include/asm-sparc/ttable.h658
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-rw-r--r--include/asm-sparc/types.h62
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-rw-r--r--include/asm-sparc/uaccess_32.h336
-rw-r--r--include/asm-sparc/uaccess_64.h273
-rw-r--r--include/asm-sparc/uctx.h71
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-rw-r--r--include/asm-sparc/unistd_32.h384
-rw-r--r--include/asm-sparc/unistd_64.h379
-rw-r--r--include/asm-sparc/upa.h109
-rw-r--r--include/asm-sparc/user.h6
-rw-r--r--include/asm-sparc/utrap.h51
-rw-r--r--include/asm-sparc/vac-ops.h134
-rw-r--r--include/asm-sparc/vaddrs.h64
-rw-r--r--include/asm-sparc/vfc_ioctls.h58
-rw-r--r--include/asm-sparc/vga.h33
-rw-r--r--include/asm-sparc/viking.h253
-rw-r--r--include/asm-sparc/vio.h406
-rw-r--r--include/asm-sparc/visasm.h62
-rw-r--r--include/asm-sparc/watchdog.h31
-rw-r--r--include/asm-sparc/winmacro.h135
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-rw-r--r--include/asm-sparc/xor_32.h269
-rw-r--r--include/asm-sparc/xor_64.h70
-rw-r--r--include/asm-sparc64/Kbuild1
-rw-r--r--include/asm-sparc64/agp.h1
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-rw-r--r--include/asm-sparc64/asi.h1
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-rw-r--r--include/asm-sparc64/chmctrl.h1
-rw-r--r--include/asm-sparc64/cmt.h1
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-rw-r--r--include/asm-sparc64/dcr.h1
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-rw-r--r--include/asm-sparc64/delay.h1
-rw-r--r--include/asm-sparc64/device.h1
-rw-r--r--include/asm-sparc64/display7seg.h1
-rw-r--r--include/asm-sparc64/div64.h1
-rw-r--r--include/asm-sparc64/dma-mapping.h1
-rw-r--r--include/asm-sparc64/dma.h1
-rw-r--r--include/asm-sparc64/ebus.h1
-rw-r--r--include/asm-sparc64/elf.h1
-rw-r--r--include/asm-sparc64/emergency-restart.h1
-rw-r--r--include/asm-sparc64/envctrl.h1
-rw-r--r--include/asm-sparc64/errno.h1
-rw-r--r--include/asm-sparc64/estate.h1
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-rw-r--r--include/asm-sparc64/fbio.h1
-rw-r--r--include/asm-sparc64/fcntl.h1
-rw-r--r--include/asm-sparc64/fhc.h1
-rw-r--r--include/asm-sparc64/floppy.h1
-rw-r--r--include/asm-sparc64/fpumacro.h1
-rw-r--r--include/asm-sparc64/ftrace.h14
-rw-r--r--include/asm-sparc64/futex.h1
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-rw-r--r--include/asm-sparc64/hugetlb.h1
-rw-r--r--include/asm-sparc64/hvtramp.h1
-rw-r--r--include/asm-sparc64/hw_irq.h1
-rw-r--r--include/asm-sparc64/hypervisor.h1
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-rw-r--r--include/asm-sparc64/idprom.h1
-rw-r--r--include/asm-sparc64/intr_queue.h1
-rw-r--r--include/asm-sparc64/io.h1
-rw-r--r--include/asm-sparc64/ioctl.h1
-rw-r--r--include/asm-sparc64/ioctls.h1
-rw-r--r--include/asm-sparc64/iommu.h1
-rw-r--r--include/asm-sparc64/ipcbuf.h1
-rw-r--r--include/asm-sparc64/irq.h1
-rw-r--r--include/asm-sparc64/irq_regs.h1
-rw-r--r--include/asm-sparc64/irqflags.h1
-rw-r--r--include/asm-sparc64/kdebug.h1
-rw-r--r--include/asm-sparc64/kgdb.h1
-rw-r--r--include/asm-sparc64/kmap_types.h1
-rw-r--r--include/asm-sparc64/kprobes.h1
-rw-r--r--include/asm-sparc64/ldc.h1
-rw-r--r--include/asm-sparc64/linkage.h1
-rw-r--r--include/asm-sparc64/lmb.h1
-rw-r--r--include/asm-sparc64/local.h1
-rw-r--r--include/asm-sparc64/lsu.h1
-rw-r--r--include/asm-sparc64/mc146818rtc.h1
-rw-r--r--include/asm-sparc64/mdesc.h1
-rw-r--r--include/asm-sparc64/mman.h1
-rw-r--r--include/asm-sparc64/mmu.h1
-rw-r--r--include/asm-sparc64/mmu_context.h1
-rw-r--r--include/asm-sparc64/mmzone.h1
-rw-r--r--include/asm-sparc64/module.h1
-rw-r--r--include/asm-sparc64/mostek.h1
-rw-r--r--include/asm-sparc64/msgbuf.h1
-rw-r--r--include/asm-sparc64/mutex.h1
-rw-r--r--include/asm-sparc64/ns87303.h1
-rw-r--r--include/asm-sparc64/of_device.h1
-rw-r--r--include/asm-sparc64/of_platform.h1
-rw-r--r--include/asm-sparc64/openprom.h1
-rw-r--r--include/asm-sparc64/openpromio.h1
-rw-r--r--include/asm-sparc64/oplib.h1
-rw-r--r--include/asm-sparc64/page.h1
-rw-r--r--include/asm-sparc64/param.h1
-rw-r--r--include/asm-sparc64/parport.h1
-rw-r--r--include/asm-sparc64/pci.h1
-rw-r--r--include/asm-sparc64/percpu.h1
-rw-r--r--include/asm-sparc64/perfctr.h1
-rw-r--r--include/asm-sparc64/pgalloc.h1
-rw-r--r--include/asm-sparc64/pgtable.h1
-rw-r--r--include/asm-sparc64/pil.h1
-rw-r--r--include/asm-sparc64/poll.h1
-rw-r--r--include/asm-sparc64/posix_types.h1
-rw-r--r--include/asm-sparc64/processor.h1
-rw-r--r--include/asm-sparc64/prom.h1
-rw-r--r--include/asm-sparc64/psrcompat.h1
-rw-r--r--include/asm-sparc64/pstate.h1
-rw-r--r--include/asm-sparc64/ptrace.h1
-rw-r--r--include/asm-sparc64/reboot.h1
-rw-r--r--include/asm-sparc64/reg.h1
-rw-r--r--include/asm-sparc64/resource.h1
-rw-r--r--include/asm-sparc64/rtc.h1
-rw-r--r--include/asm-sparc64/rwsem-const.h1
-rw-r--r--include/asm-sparc64/rwsem.h1
-rw-r--r--include/asm-sparc64/sbus.h1
-rw-r--r--include/asm-sparc64/scatterlist.h1
-rw-r--r--include/asm-sparc64/scratchpad.h1
-rw-r--r--include/asm-sparc64/seccomp.h1
-rw-r--r--include/asm-sparc64/sections.h1
-rw-r--r--include/asm-sparc64/sembuf.h1
-rw-r--r--include/asm-sparc64/setup.h1
-rw-r--r--include/asm-sparc64/sfafsr.h1
-rw-r--r--include/asm-sparc64/sfp-machine.h1
-rw-r--r--include/asm-sparc64/shmbuf.h1
-rw-r--r--include/asm-sparc64/shmparam.h1
-rw-r--r--include/asm-sparc64/sigcontext.h1
-rw-r--r--include/asm-sparc64/siginfo.h1
-rw-r--r--include/asm-sparc64/signal.h1
-rw-r--r--include/asm-sparc64/smp.h1
-rw-r--r--include/asm-sparc64/socket.h1
-rw-r--r--include/asm-sparc64/sockios.h1
-rw-r--r--include/asm-sparc64/sparsemem.h1
-rw-r--r--include/asm-sparc64/spinlock.h1
-rw-r--r--include/asm-sparc64/spinlock_types.h1
-rw-r--r--include/asm-sparc64/spitfire.h1
-rw-r--r--include/asm-sparc64/sstate.h1
-rw-r--r--include/asm-sparc64/stacktrace.h1
-rw-r--r--include/asm-sparc64/starfire.h1
-rw-r--r--include/asm-sparc64/stat.h1
-rw-r--r--include/asm-sparc64/statfs.h1
-rw-r--r--include/asm-sparc64/string.h1
-rw-r--r--include/asm-sparc64/sunbpp.h1
-rw-r--r--include/asm-sparc64/syscalls.h1
-rw-r--r--include/asm-sparc64/system.h1
-rw-r--r--include/asm-sparc64/termbits.h1
-rw-r--r--include/asm-sparc64/termios.h1
-rw-r--r--include/asm-sparc64/thread_info.h1
-rw-r--r--include/asm-sparc64/timer.h1
-rw-r--r--include/asm-sparc64/timex.h1
-rw-r--r--include/asm-sparc64/tlb.h1
-rw-r--r--include/asm-sparc64/tlbflush.h1
-rw-r--r--include/asm-sparc64/topology.h1
-rw-r--r--include/asm-sparc64/tsb.h1
-rw-r--r--include/asm-sparc64/ttable.h1
-rw-r--r--include/asm-sparc64/types.h1
-rw-r--r--include/asm-sparc64/uaccess.h1
-rw-r--r--include/asm-sparc64/uctx.h1
-rw-r--r--include/asm-sparc64/unaligned.h1
-rw-r--r--include/asm-sparc64/unistd.h1
-rw-r--r--include/asm-sparc64/upa.h1
-rw-r--r--include/asm-sparc64/user.h1
-rw-r--r--include/asm-sparc64/utrap.h1
-rw-r--r--include/asm-sparc64/vga.h1
-rw-r--r--include/asm-sparc64/vio.h1
-rw-r--r--include/asm-sparc64/visasm.h1
-rw-r--r--include/asm-sparc64/watchdog.h1
-rw-r--r--include/asm-sparc64/xor.h1
-rw-r--r--include/asm-x86/dma-mapping.h22
-rw-r--r--include/asm-x86/iommu.h2
-rw-r--r--include/asm-x86/kvm_host.h6
-rw-r--r--include/linux/Kbuild1
-rw-r--r--include/linux/blkdev.h1
-rw-r--r--include/linux/buffer_head.h10
-rw-r--r--include/linux/configfs.h68
-rw-r--r--include/linux/connector.h3
-rw-r--r--include/linux/cpufreq.h1
-rw-r--r--include/linux/cpumask.h63
-rw-r--r--include/linux/dcache.h1
-rw-r--r--include/linux/file.h3
-rw-r--r--include/linux/fs.h44
-rw-r--r--include/linux/ide.h40
-rw-r--r--include/linux/ieee80211.h13
-rw-r--r--include/linux/ihex.h2
-rw-r--r--include/linux/interrupt.h29
-rw-r--r--include/linux/ioport.h4
-rw-r--r--include/linux/ip_vs.h245
-rw-r--r--include/linux/kallsyms.h3
-rw-r--r--include/linux/kernel.h6
-rw-r--r--include/linux/kexec.h4
-rw-r--r--include/linux/kvm.h1
-rw-r--r--include/linux/kvm_host.h24
-rw-r--r--include/linux/libata.h9
-rw-r--r--include/linux/mISDNif.h32
-rw-r--r--include/linux/maple.h16
-rw-r--r--include/linux/mfd/core.h30
-rw-r--r--include/linux/mm.h6
-rw-r--r--include/linux/mm_types.h4
-rw-r--r--include/linux/mmu_notifier.h279
-rw-r--r--include/linux/mount.h3
-rw-r--r--include/linux/mtd/mtd.h6
-rw-r--r--include/linux/mtd/nand.h4
-rw-r--r--include/linux/netdevice.h90
-rw-r--r--include/linux/netfilter/nf_conntrack_tcp.h3
-rw-r--r--include/linux/of.h1
-rw-r--r--include/linux/of_spi.h18
-rw-r--r--include/linux/page-flags.h5
-rw-r--r--include/linux/pagemap.h91
-rw-r--r--include/linux/parser.h2
-rw-r--r--include/linux/pci-aspm.h5
-rw-r--r--include/linux/pci.h2
-rw-r--r--include/linux/pci_regs.h1
-rw-r--r--include/linux/pm_qos_params.h2
-rw-r--r--include/linux/power_supply.h1
-rw-r--r--include/linux/quotaops.h2
-rw-r--r--include/linux/raid/md_k.h1
-rw-r--r--include/linux/rculist.h28
-rw-r--r--include/linux/regulator/bq24022.h21
-rw-r--r--include/linux/regulator/consumer.h284
-rw-r--r--include/linux/regulator/driver.h99
-rw-r--r--include/linux/regulator/fixed.h22
-rw-r--r--include/linux/regulator/machine.h104
-rw-r--r--include/linux/rfkill.h8
-rw-r--r--include/linux/rmap.h8
-rw-r--r--include/linux/serio.h3
-rw-r--r--include/linux/skbuff.h6
-rw-r--r--include/linux/snmp.h2
-rw-r--r--include/linux/spi/orion_spi.h17
-rw-r--r--include/linux/spi/spi.h12
-rw-r--r--include/linux/stop_machine.h50
-rw-r--r--include/linux/tracehook.h22
-rw-r--r--include/linux/videodev.h15
-rw-r--r--include/linux/videodev2.h386
-rw-r--r--include/linux/videotext.h16
-rw-r--r--include/linux/vt_kern.h3
-rw-r--r--include/media/audiochip.h26
-rw-r--r--include/media/saa7146_vv.h1
-rw-r--r--include/media/tveeprom.h7
-rw-r--r--include/media/v4l2-chip-ident.h7
-rw-r--r--include/media/v4l2-common.h31
-rw-r--r--include/media/v4l2-dev.h325
-rw-r--r--include/media/v4l2-ioctl.h301
-rw-r--r--include/net/dst.h12
-rw-r--r--include/net/flow.h1
-rw-r--r--include/net/ip_vs.h253
-rw-r--r--include/net/mac80211.h20
-rw-r--r--include/net/sch_generic.h26
-rw-r--r--include/net/sctp/structs.h3
-rw-r--r--include/sound/soc-dapm.h3
-rw-r--r--include/video/radeon.h5
1426 files changed, 2794 insertions, 134047 deletions
diff --git a/include/acpi/actbl.h b/include/acpi/actbl.h
index 1ebbe883f78..13a3d9ad92d 100644
--- a/include/acpi/actbl.h
+++ b/include/acpi/actbl.h
@@ -277,6 +277,7 @@ enum acpi_prefered_pm_profiles {
277#define BAF_LEGACY_DEVICES 0x0001 277#define BAF_LEGACY_DEVICES 0x0001
278#define BAF_8042_KEYBOARD_CONTROLLER 0x0002 278#define BAF_8042_KEYBOARD_CONTROLLER 0x0002
279#define BAF_MSI_NOT_SUPPORTED 0x0008 279#define BAF_MSI_NOT_SUPPORTED 0x0008
280#define BAF_PCIE_ASPM_CONTROL 0x0010
280 281
281#define FADT2_REVISION_ID 3 282#define FADT2_REVISION_ID 3
282#define FADT2_MINUS_REVISION_ID 2 283#define FADT2_MINUS_REVISION_ID 2
diff --git a/include/asm-arm/arch-s3c2410/spi.h b/include/asm-arm/arch-s3c2410/spi.h
index 352d33860b6..442169887d3 100644
--- a/include/asm-arm/arch-s3c2410/spi.h
+++ b/include/asm-arm/arch-s3c2410/spi.h
@@ -16,6 +16,7 @@
16struct s3c2410_spi_info { 16struct s3c2410_spi_info {
17 unsigned long pin_cs; /* simple gpio cs */ 17 unsigned long pin_cs; /* simple gpio cs */
18 unsigned int num_cs; /* total chipselects */ 18 unsigned int num_cs; /* total chipselects */
19 int bus_num; /* bus number to use. */
19 20
20 void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol); 21 void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol);
21}; 22};
diff --git a/include/asm-arm/plat-s3c/iic.h b/include/asm-arm/plat-s3c/iic.h
index 71211c8b538..d08a1f2863e 100644
--- a/include/asm-arm/plat-s3c/iic.h
+++ b/include/asm-arm/plat-s3c/iic.h
@@ -21,6 +21,7 @@
21*/ 21*/
22 22
23struct s3c2410_platform_i2c { 23struct s3c2410_platform_i2c {
24 int bus_num; /* bus number to use */
24 unsigned int flags; 25 unsigned int flags;
25 unsigned int slave_addr; /* slave address for controller */ 26 unsigned int slave_addr; /* slave address for controller */
26 unsigned long bus_freq; /* standard bus frequency */ 27 unsigned long bus_freq; /* standard bus frequency */
diff --git a/include/asm-cris/dma-mapping.h b/include/asm-cris/dma-mapping.h
index cb2fb25ff8d..da8ef8e8f84 100644
--- a/include/asm-cris/dma-mapping.h
+++ b/include/asm-cris/dma-mapping.h
@@ -14,6 +14,8 @@
14#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) 14#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
15 15
16#ifdef CONFIG_PCI 16#ifdef CONFIG_PCI
17#include <asm-generic/dma-coherent.h>
18
17void *dma_alloc_coherent(struct device *dev, size_t size, 19void *dma_alloc_coherent(struct device *dev, size_t size,
18 dma_addr_t *dma_handle, gfp_t flag); 20 dma_addr_t *dma_handle, gfp_t flag);
19 21
diff --git a/include/asm-frv/unistd.h b/include/asm-frv/unistd.h
index f184eb8c047..edcfaf5f041 100644
--- a/include/asm-frv/unistd.h
+++ b/include/asm-frv/unistd.h
@@ -333,10 +333,16 @@
333#define __NR_fallocate 324 333#define __NR_fallocate 324
334#define __NR_timerfd_settime 325 334#define __NR_timerfd_settime 325
335#define __NR_timerfd_gettime 326 335#define __NR_timerfd_gettime 326
336#define __NR_signalfd4 327
337#define __NR_eventfd2 328
338#define __NR_epoll_create1 329
339#define __NR_dup3 330
340#define __NR_pipe2 331
341#define __NR_inotify_init1 332
336 342
337#ifdef __KERNEL__ 343#ifdef __KERNEL__
338 344
339#define NR_syscalls 325 345#define NR_syscalls 333
340 346
341#define __ARCH_WANT_IPC_PARSE_VERSION 347#define __ARCH_WANT_IPC_PARSE_VERSION
342/* #define __ARCH_WANT_OLD_READDIR */ 348/* #define __ARCH_WANT_OLD_READDIR */
diff --git a/include/asm-generic/dma-coherent.h b/include/asm-generic/dma-coherent.h
new file mode 100644
index 00000000000..85a3ffaa024
--- /dev/null
+++ b/include/asm-generic/dma-coherent.h
@@ -0,0 +1,32 @@
1#ifndef DMA_COHERENT_H
2#define DMA_COHERENT_H
3
4#ifdef CONFIG_HAVE_GENERIC_DMA_COHERENT
5/*
6 * These two functions are only for dma allocator.
7 * Don't use them in device drivers.
8 */
9int dma_alloc_from_coherent(struct device *dev, ssize_t size,
10 dma_addr_t *dma_handle, void **ret);
11int dma_release_from_coherent(struct device *dev, int order, void *vaddr);
12
13/*
14 * Standard interface
15 */
16#define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
17extern int
18dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
19 dma_addr_t device_addr, size_t size, int flags);
20
21extern void
22dma_release_declared_memory(struct device *dev);
23
24extern void *
25dma_mark_declared_memory_occupied(struct device *dev,
26 dma_addr_t device_addr, size_t size);
27#else
28#define dma_alloc_from_coherent(dev, size, handle, ret) (0)
29#define dma_release_from_coherent(dev, order, vaddr) (0)
30#endif
31
32#endif
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index c764a8fcb05..0f99ad38b01 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -2,6 +2,7 @@
2#define _ASM_GENERIC_GPIO_H 2#define _ASM_GENERIC_GPIO_H
3 3
4#include <linux/types.h> 4#include <linux/types.h>
5#include <linux/errno.h>
5 6
6#ifdef CONFIG_GPIOLIB 7#ifdef CONFIG_GPIOLIB
7 8
diff --git a/include/asm-generic/pgtable-nopmd.h b/include/asm-generic/pgtable-nopmd.h
index 087325ede76..a7cdc48e8b7 100644
--- a/include/asm-generic/pgtable-nopmd.h
+++ b/include/asm-generic/pgtable-nopmd.h
@@ -5,6 +5,8 @@
5 5
6#include <asm-generic/pgtable-nopud.h> 6#include <asm-generic/pgtable-nopud.h>
7 7
8struct mm_struct;
9
8#define __PAGETABLE_PMD_FOLDED 10#define __PAGETABLE_PMD_FOLDED
9 11
10/* 12/*
@@ -54,7 +56,9 @@ static inline pmd_t * pmd_offset(pud_t * pud, unsigned long address)
54 * inside the pud, so has no extra memory associated with it. 56 * inside the pud, so has no extra memory associated with it.
55 */ 57 */
56#define pmd_alloc_one(mm, address) NULL 58#define pmd_alloc_one(mm, address) NULL
57#define pmd_free(mm, x) do { } while (0) 59static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
60{
61}
58#define __pmd_free_tlb(tlb, x) do { } while (0) 62#define __pmd_free_tlb(tlb, x) do { } while (0)
59 63
60#undef pmd_addr_end 64#undef pmd_addr_end
diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h
index 6d88a923c94..cb752ba7246 100644
--- a/include/asm-generic/vmlinux.lds.h
+++ b/include/asm-generic/vmlinux.lds.h
@@ -333,9 +333,9 @@
333#define BUG_TABLE \ 333#define BUG_TABLE \
334 . = ALIGN(8); \ 334 . = ALIGN(8); \
335 __bug_table : AT(ADDR(__bug_table) - LOAD_OFFSET) { \ 335 __bug_table : AT(ADDR(__bug_table) - LOAD_OFFSET) { \
336 __start___bug_table = .; \ 336 VMLINUX_SYMBOL(__start___bug_table) = .; \
337 *(__bug_table) \ 337 *(__bug_table) \
338 __stop___bug_table = .; \ 338 VMLINUX_SYMBOL(__stop___bug_table) = .; \
339 } 339 }
340#else 340#else
341#define BUG_TABLE 341#define BUG_TABLE
@@ -345,9 +345,9 @@
345#define TRACEDATA \ 345#define TRACEDATA \
346 . = ALIGN(4); \ 346 . = ALIGN(4); \
347 .tracedata : AT(ADDR(.tracedata) - LOAD_OFFSET) { \ 347 .tracedata : AT(ADDR(.tracedata) - LOAD_OFFSET) { \
348 __tracedata_start = .; \ 348 VMLINUX_SYMBOL(__tracedata_start) = .; \
349 *(.tracedata) \ 349 *(.tracedata) \
350 __tracedata_end = .; \ 350 VMLINUX_SYMBOL(__tracedata_end) = .; \
351 } 351 }
352#else 352#else
353#define TRACEDATA 353#define TRACEDATA
@@ -362,7 +362,7 @@
362 362
363#define INITCALLS \ 363#define INITCALLS \
364 *(.initcallearly.init) \ 364 *(.initcallearly.init) \
365 __early_initcall_end = .; \ 365 VMLINUX_SYMBOL(__early_initcall_end) = .; \
366 *(.initcall0.init) \ 366 *(.initcall0.init) \
367 *(.initcall0s.init) \ 367 *(.initcall0s.init) \
368 *(.initcall1.init) \ 368 *(.initcall1.init) \
@@ -383,9 +383,9 @@
383 383
384#define PERCPU(align) \ 384#define PERCPU(align) \
385 . = ALIGN(align); \ 385 . = ALIGN(align); \
386 __per_cpu_start = .; \ 386 VMLINUX_SYMBOL(__per_cpu_start) = .; \
387 .data.percpu : AT(ADDR(.data.percpu) - LOAD_OFFSET) { \ 387 .data.percpu : AT(ADDR(.data.percpu) - LOAD_OFFSET) { \
388 *(.data.percpu) \ 388 *(.data.percpu) \
389 *(.data.percpu.shared_aligned) \ 389 *(.data.percpu.shared_aligned) \
390 } \ 390 } \
391 __per_cpu_end = .; 391 VMLINUX_SYMBOL(__per_cpu_end) = .;
diff --git a/include/asm-ia64/Kbuild b/include/asm-ia64/Kbuild
deleted file mode 100644
index ccbe8ae47a6..00000000000
--- a/include/asm-ia64/Kbuild
+++ /dev/null
@@ -1,16 +0,0 @@
1include include/asm-generic/Kbuild.asm
2
3header-y += break.h
4header-y += fpu.h
5header-y += fpswa.h
6header-y += ia64regs.h
7header-y += intel_intrin.h
8header-y += perfmon_default_smpl.h
9header-y += ptrace_offsets.h
10header-y += rse.h
11header-y += ucontext.h
12
13unifdef-y += gcc_intrin.h
14unifdef-y += intrinsics.h
15unifdef-y += perfmon.h
16unifdef-y += ustack.h
diff --git a/include/asm-ia64/a.out.h b/include/asm-ia64/a.out.h
deleted file mode 100644
index 193dcfb6759..00000000000
--- a/include/asm-ia64/a.out.h
+++ /dev/null
@@ -1,32 +0,0 @@
1#ifndef _ASM_IA64_A_OUT_H
2#define _ASM_IA64_A_OUT_H
3
4/*
5 * No a.out format has been (or should be) defined so this file is
6 * just a dummy that allows us to get binfmt_elf compiled. It
7 * probably would be better to clean up binfmt_elf.c so it does not
8 * necessarily depend on there being a.out support.
9 *
10 * Modified 1998-2002
11 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co.
12 */
13
14#include <linux/types.h>
15
16struct exec {
17 unsigned long a_info;
18 unsigned long a_text;
19 unsigned long a_data;
20 unsigned long a_bss;
21 unsigned long a_entry;
22};
23
24#define N_TXTADDR(x) 0
25#define N_DATADDR(x) 0
26#define N_BSSADDR(x) 0
27#define N_DRSIZE(x) 0
28#define N_TRSIZE(x) 0
29#define N_SYMSIZE(x) 0
30#define N_TXTOFF(x) 0
31
32#endif /* _ASM_IA64_A_OUT_H */
diff --git a/include/asm-ia64/acpi-ext.h b/include/asm-ia64/acpi-ext.h
deleted file mode 100644
index 734d137dda6..00000000000
--- a/include/asm-ia64/acpi-ext.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * (c) Copyright 2003, 2006 Hewlett-Packard Development Company, L.P.
3 * Alex Williamson <alex.williamson@hp.com>
4 * Bjorn Helgaas <bjorn.helgaas@hp.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Vendor specific extensions to ACPI.
11 */
12
13#ifndef _ASM_IA64_ACPI_EXT_H
14#define _ASM_IA64_ACPI_EXT_H
15
16#include <linux/types.h>
17#include <acpi/actypes.h>
18
19extern acpi_status hp_acpi_csr_space (acpi_handle, u64 *base, u64 *length);
20
21#endif /* _ASM_IA64_ACPI_EXT_H */
diff --git a/include/asm-ia64/acpi.h b/include/asm-ia64/acpi.h
deleted file mode 100644
index fcfad326f4c..00000000000
--- a/include/asm-ia64/acpi.h
+++ /dev/null
@@ -1,167 +0,0 @@
1/*
2 * asm-ia64/acpi.h
3 *
4 * Copyright (C) 1999 VA Linux Systems
5 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
6 * Copyright (C) 2000,2001 J.I. Lee <jung-ik.lee@intel.com>
7 * Copyright (C) 2001,2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
8 *
9 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
26 */
27
28#ifndef _ASM_ACPI_H
29#define _ASM_ACPI_H
30
31#ifdef __KERNEL__
32
33#include <acpi/pdc_intel.h>
34
35#include <linux/init.h>
36#include <linux/numa.h>
37#include <asm/system.h>
38#include <asm/numa.h>
39
40#define COMPILER_DEPENDENT_INT64 long
41#define COMPILER_DEPENDENT_UINT64 unsigned long
42
43/*
44 * Calling conventions:
45 *
46 * ACPI_SYSTEM_XFACE - Interfaces to host OS (handlers, threads)
47 * ACPI_EXTERNAL_XFACE - External ACPI interfaces
48 * ACPI_INTERNAL_XFACE - Internal ACPI interfaces
49 * ACPI_INTERNAL_VAR_XFACE - Internal variable-parameter list interfaces
50 */
51#define ACPI_SYSTEM_XFACE
52#define ACPI_EXTERNAL_XFACE
53#define ACPI_INTERNAL_XFACE
54#define ACPI_INTERNAL_VAR_XFACE
55
56/* Asm macros */
57
58#define ACPI_ASM_MACROS
59#define BREAKPOINT3
60#define ACPI_DISABLE_IRQS() local_irq_disable()
61#define ACPI_ENABLE_IRQS() local_irq_enable()
62#define ACPI_FLUSH_CPU_CACHE()
63
64static inline int
65ia64_acpi_acquire_global_lock (unsigned int *lock)
66{
67 unsigned int old, new, val;
68 do {
69 old = *lock;
70 new = (((old & ~0x3) + 2) + ((old >> 1) & 0x1));
71 val = ia64_cmpxchg4_acq(lock, new, old);
72 } while (unlikely (val != old));
73 return (new < 3) ? -1 : 0;
74}
75
76static inline int
77ia64_acpi_release_global_lock (unsigned int *lock)
78{
79 unsigned int old, new, val;
80 do {
81 old = *lock;
82 new = old & ~0x3;
83 val = ia64_cmpxchg4_acq(lock, new, old);
84 } while (unlikely (val != old));
85 return old & 0x1;
86}
87
88#define ACPI_ACQUIRE_GLOBAL_LOCK(facs, Acq) \
89 ((Acq) = ia64_acpi_acquire_global_lock(&facs->global_lock))
90
91#define ACPI_RELEASE_GLOBAL_LOCK(facs, Acq) \
92 ((Acq) = ia64_acpi_release_global_lock(&facs->global_lock))
93
94#define acpi_disabled 0 /* ACPI always enabled on IA64 */
95#define acpi_noirq 0 /* ACPI always enabled on IA64 */
96#define acpi_pci_disabled 0 /* ACPI PCI always enabled on IA64 */
97#define acpi_strict 1 /* no ACPI spec workarounds on IA64 */
98#define acpi_processor_cstate_check(x) (x) /* no idle limits on IA64 :) */
99static inline void disable_acpi(void) { }
100
101const char *acpi_get_sysname (void);
102int acpi_request_vector (u32 int_type);
103int acpi_gsi_to_irq (u32 gsi, unsigned int *irq);
104
105/* routines for saving/restoring kernel state */
106extern int acpi_save_state_mem(void);
107extern void acpi_restore_state_mem(void);
108extern unsigned long acpi_wakeup_address;
109
110/*
111 * Record the cpei override flag and current logical cpu. This is
112 * useful for CPU removal.
113 */
114extern unsigned int can_cpei_retarget(void);
115extern unsigned int is_cpu_cpei_target(unsigned int cpu);
116extern void set_cpei_target_cpu(unsigned int cpu);
117extern unsigned int get_cpei_target_cpu(void);
118extern void prefill_possible_map(void);
119#ifdef CONFIG_ACPI_HOTPLUG_CPU
120extern int additional_cpus;
121#else
122#define additional_cpus 0
123#endif
124
125#ifdef CONFIG_ACPI_NUMA
126#if MAX_NUMNODES > 256
127#define MAX_PXM_DOMAINS MAX_NUMNODES
128#else
129#define MAX_PXM_DOMAINS (256)
130#endif
131extern int __devinitdata pxm_to_nid_map[MAX_PXM_DOMAINS];
132extern int __initdata nid_to_pxm_map[MAX_NUMNODES];
133#endif
134
135#define acpi_unlazy_tlb(x)
136
137#ifdef CONFIG_ACPI_NUMA
138extern cpumask_t early_cpu_possible_map;
139#define for_each_possible_early_cpu(cpu) \
140 for_each_cpu_mask((cpu), early_cpu_possible_map)
141
142static inline void per_cpu_scan_finalize(int min_cpus, int reserve_cpus)
143{
144 int low_cpu, high_cpu;
145 int cpu;
146 int next_nid = 0;
147
148 low_cpu = cpus_weight(early_cpu_possible_map);
149
150 high_cpu = max(low_cpu, min_cpus);
151 high_cpu = min(high_cpu + reserve_cpus, NR_CPUS);
152
153 for (cpu = low_cpu; cpu < high_cpu; cpu++) {
154 cpu_set(cpu, early_cpu_possible_map);
155 if (node_cpuid[cpu].nid == NUMA_NO_NODE) {
156 node_cpuid[cpu].nid = next_nid;
157 next_nid++;
158 if (next_nid >= num_online_nodes())
159 next_nid = 0;
160 }
161 }
162}
163#endif /* CONFIG_ACPI_NUMA */
164
165#endif /*__KERNEL__*/
166
167#endif /*_ASM_ACPI_H*/
diff --git a/include/asm-ia64/agp.h b/include/asm-ia64/agp.h
deleted file mode 100644
index c11fdd8ab4d..00000000000
--- a/include/asm-ia64/agp.h
+++ /dev/null
@@ -1,30 +0,0 @@
1#ifndef _ASM_IA64_AGP_H
2#define _ASM_IA64_AGP_H
3
4/*
5 * IA-64 specific AGP definitions.
6 *
7 * Copyright (C) 2002-2003 Hewlett-Packard Co
8 * David Mosberger-Tang <davidm@hpl.hp.com>
9 */
10
11/*
12 * To avoid memory-attribute aliasing issues, we require that the AGPGART engine operate
13 * in coherent mode, which lets us map the AGP memory as normal (write-back) memory
14 * (unlike x86, where it gets mapped "write-coalescing").
15 */
16#define map_page_into_agp(page) /* nothing */
17#define unmap_page_from_agp(page) /* nothing */
18#define flush_agp_cache() mb()
19
20/* Convert a physical address to an address suitable for the GART. */
21#define phys_to_gart(x) (x)
22#define gart_to_phys(x) (x)
23
24/* GATT allocation. Returns/accepts GATT kernel virtual address. */
25#define alloc_gatt_pages(order) \
26 ((char *)__get_free_pages(GFP_KERNEL, (order)))
27#define free_gatt_pages(table, order) \
28 free_pages((unsigned long)(table), (order))
29
30#endif /* _ASM_IA64_AGP_H */
diff --git a/include/asm-ia64/asmmacro.h b/include/asm-ia64/asmmacro.h
deleted file mode 100644
index c1642fd6402..00000000000
--- a/include/asm-ia64/asmmacro.h
+++ /dev/null
@@ -1,135 +0,0 @@
1#ifndef _ASM_IA64_ASMMACRO_H
2#define _ASM_IA64_ASMMACRO_H
3
4/*
5 * Copyright (C) 2000-2001, 2003-2004 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 */
8
9
10#define ENTRY(name) \
11 .align 32; \
12 .proc name; \
13name:
14
15#define ENTRY_MIN_ALIGN(name) \
16 .align 16; \
17 .proc name; \
18name:
19
20#define GLOBAL_ENTRY(name) \
21 .global name; \
22 ENTRY(name)
23
24#define END(name) \
25 .endp name
26
27/*
28 * Helper macros to make unwind directives more readable:
29 */
30
31/* prologue_gr: */
32#define ASM_UNW_PRLG_RP 0x8
33#define ASM_UNW_PRLG_PFS 0x4
34#define ASM_UNW_PRLG_PSP 0x2
35#define ASM_UNW_PRLG_PR 0x1
36#define ASM_UNW_PRLG_GRSAVE(ninputs) (32+(ninputs))
37
38/*
39 * Helper macros for accessing user memory.
40 *
41 * When adding any new .section/.previous entries here, make sure to
42 * also add it to the DISCARD section in arch/ia64/kernel/gate.lds.S or
43 * unpleasant things will happen.
44 */
45
46 .section "__ex_table", "a" // declare section & section attributes
47 .previous
48
49# define EX(y,x...) \
50 .xdata4 "__ex_table", 99f-., y-.; \
51 [99:] x
52# define EXCLR(y,x...) \
53 .xdata4 "__ex_table", 99f-., y-.+4; \
54 [99:] x
55
56/*
57 * Tag MCA recoverable instruction ranges.
58 */
59
60 .section "__mca_table", "a" // declare section & section attributes
61 .previous
62
63# define MCA_RECOVER_RANGE(y) \
64 .xdata4 "__mca_table", y-., 99f-.; \
65 [99:]
66
67/*
68 * Mark instructions that need a load of a virtual address patched to be
69 * a load of a physical address. We use this either in critical performance
70 * path (ivt.S - TLB miss processing) or in places where it might not be
71 * safe to use a "tpa" instruction (mca_asm.S - error recovery).
72 */
73 .section ".data.patch.vtop", "a" // declare section & section attributes
74 .previous
75
76#define LOAD_PHYSICAL(pr, reg, obj) \
77[1:](pr)movl reg = obj; \
78 .xdata4 ".data.patch.vtop", 1b-.
79
80/*
81 * For now, we always put in the McKinley E9 workaround. On CPUs that don't need it,
82 * we'll patch out the work-around bundles with NOPs, so their impact is minimal.
83 */
84#define DO_MCKINLEY_E9_WORKAROUND
85
86#ifdef DO_MCKINLEY_E9_WORKAROUND
87 .section ".data.patch.mckinley_e9", "a"
88 .previous
89/* workaround for Itanium 2 Errata 9: */
90# define FSYS_RETURN \
91 .xdata4 ".data.patch.mckinley_e9", 1f-.; \
921:{ .mib; \
93 nop.m 0; \
94 mov r16=ar.pfs; \
95 br.call.sptk.many b7=2f;; \
96 }; \
972:{ .mib; \
98 nop.m 0; \
99 mov ar.pfs=r16; \
100 br.ret.sptk.many b6;; \
101 }
102#else
103# define FSYS_RETURN br.ret.sptk.many b6
104#endif
105
106/*
107 * If physical stack register size is different from DEF_NUM_STACK_REG,
108 * dynamically patch the kernel for correct size.
109 */
110 .section ".data.patch.phys_stack_reg", "a"
111 .previous
112#define LOAD_PHYS_STACK_REG_SIZE(reg) \
113[1:] adds reg=IA64_NUM_PHYS_STACK_REG*8+8,r0; \
114 .xdata4 ".data.patch.phys_stack_reg", 1b-.
115
116/*
117 * Up until early 2004, use of .align within a function caused bad unwind info.
118 * TEXT_ALIGN(n) expands into ".align n" if a fixed GAS is available or into nothing
119 * otherwise.
120 */
121#ifdef HAVE_WORKING_TEXT_ALIGN
122# define TEXT_ALIGN(n) .align n
123#else
124# define TEXT_ALIGN(n)
125#endif
126
127#ifdef HAVE_SERIALIZE_DIRECTIVE
128# define dv_serialize_data .serialize.data
129# define dv_serialize_instruction .serialize.instruction
130#else
131# define dv_serialize_data
132# define dv_serialize_instruction
133#endif
134
135#endif /* _ASM_IA64_ASMMACRO_H */
diff --git a/include/asm-ia64/atomic.h b/include/asm-ia64/atomic.h
deleted file mode 100644
index 50c2b83fd5a..00000000000
--- a/include/asm-ia64/atomic.h
+++ /dev/null
@@ -1,226 +0,0 @@
1#ifndef _ASM_IA64_ATOMIC_H
2#define _ASM_IA64_ATOMIC_H
3
4/*
5 * Atomic operations that C can't guarantee us. Useful for
6 * resource counting etc..
7 *
8 * NOTE: don't mess with the types below! The "unsigned long" and
9 * "int" types were carefully placed so as to ensure proper operation
10 * of the macros.
11 *
12 * Copyright (C) 1998, 1999, 2002-2003 Hewlett-Packard Co
13 * David Mosberger-Tang <davidm@hpl.hp.com>
14 */
15#include <linux/types.h>
16
17#include <asm/intrinsics.h>
18#include <asm/system.h>
19
20/*
21 * On IA-64, counter must always be volatile to ensure that that the
22 * memory accesses are ordered.
23 */
24typedef struct { volatile __s32 counter; } atomic_t;
25typedef struct { volatile __s64 counter; } atomic64_t;
26
27#define ATOMIC_INIT(i) ((atomic_t) { (i) })
28#define ATOMIC64_INIT(i) ((atomic64_t) { (i) })
29
30#define atomic_read(v) ((v)->counter)
31#define atomic64_read(v) ((v)->counter)
32
33#define atomic_set(v,i) (((v)->counter) = (i))
34#define atomic64_set(v,i) (((v)->counter) = (i))
35
36static __inline__ int
37ia64_atomic_add (int i, atomic_t *v)
38{
39 __s32 old, new;
40 CMPXCHG_BUGCHECK_DECL
41
42 do {
43 CMPXCHG_BUGCHECK(v);
44 old = atomic_read(v);
45 new = old + i;
46 } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic_t)) != old);
47 return new;
48}
49
50static __inline__ int
51ia64_atomic64_add (__s64 i, atomic64_t *v)
52{
53 __s64 old, new;
54 CMPXCHG_BUGCHECK_DECL
55
56 do {
57 CMPXCHG_BUGCHECK(v);
58 old = atomic64_read(v);
59 new = old + i;
60 } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic64_t)) != old);
61 return new;
62}
63
64static __inline__ int
65ia64_atomic_sub (int i, atomic_t *v)
66{
67 __s32 old, new;
68 CMPXCHG_BUGCHECK_DECL
69
70 do {
71 CMPXCHG_BUGCHECK(v);
72 old = atomic_read(v);
73 new = old - i;
74 } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic_t)) != old);
75 return new;
76}
77
78static __inline__ int
79ia64_atomic64_sub (__s64 i, atomic64_t *v)
80{
81 __s64 old, new;
82 CMPXCHG_BUGCHECK_DECL
83
84 do {
85 CMPXCHG_BUGCHECK(v);
86 old = atomic64_read(v);
87 new = old - i;
88 } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic64_t)) != old);
89 return new;
90}
91
92#define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new))
93#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
94
95#define atomic64_cmpxchg(v, old, new) \
96 (cmpxchg(&((v)->counter), old, new))
97#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
98
99static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
100{
101 int c, old;
102 c = atomic_read(v);
103 for (;;) {
104 if (unlikely(c == (u)))
105 break;
106 old = atomic_cmpxchg((v), c, c + (a));
107 if (likely(old == c))
108 break;
109 c = old;
110 }
111 return c != (u);
112}
113
114#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
115
116static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
117{
118 long c, old;
119 c = atomic64_read(v);
120 for (;;) {
121 if (unlikely(c == (u)))
122 break;
123 old = atomic64_cmpxchg((v), c, c + (a));
124 if (likely(old == c))
125 break;
126 c = old;
127 }
128 return c != (u);
129}
130
131#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
132
133#define atomic_add_return(i,v) \
134({ \
135 int __ia64_aar_i = (i); \
136 (__builtin_constant_p(i) \
137 && ( (__ia64_aar_i == 1) || (__ia64_aar_i == 4) \
138 || (__ia64_aar_i == 8) || (__ia64_aar_i == 16) \
139 || (__ia64_aar_i == -1) || (__ia64_aar_i == -4) \
140 || (__ia64_aar_i == -8) || (__ia64_aar_i == -16))) \
141 ? ia64_fetch_and_add(__ia64_aar_i, &(v)->counter) \
142 : ia64_atomic_add(__ia64_aar_i, v); \
143})
144
145#define atomic64_add_return(i,v) \
146({ \
147 long __ia64_aar_i = (i); \
148 (__builtin_constant_p(i) \
149 && ( (__ia64_aar_i == 1) || (__ia64_aar_i == 4) \
150 || (__ia64_aar_i == 8) || (__ia64_aar_i == 16) \
151 || (__ia64_aar_i == -1) || (__ia64_aar_i == -4) \
152 || (__ia64_aar_i == -8) || (__ia64_aar_i == -16))) \
153 ? ia64_fetch_and_add(__ia64_aar_i, &(v)->counter) \
154 : ia64_atomic64_add(__ia64_aar_i, v); \
155})
156
157/*
158 * Atomically add I to V and return TRUE if the resulting value is
159 * negative.
160 */
161static __inline__ int
162atomic_add_negative (int i, atomic_t *v)
163{
164 return atomic_add_return(i, v) < 0;
165}
166
167static __inline__ int
168atomic64_add_negative (__s64 i, atomic64_t *v)
169{
170 return atomic64_add_return(i, v) < 0;
171}
172
173#define atomic_sub_return(i,v) \
174({ \
175 int __ia64_asr_i = (i); \
176 (__builtin_constant_p(i) \
177 && ( (__ia64_asr_i == 1) || (__ia64_asr_i == 4) \
178 || (__ia64_asr_i == 8) || (__ia64_asr_i == 16) \
179 || (__ia64_asr_i == -1) || (__ia64_asr_i == -4) \
180 || (__ia64_asr_i == -8) || (__ia64_asr_i == -16))) \
181 ? ia64_fetch_and_add(-__ia64_asr_i, &(v)->counter) \
182 : ia64_atomic_sub(__ia64_asr_i, v); \
183})
184
185#define atomic64_sub_return(i,v) \
186({ \
187 long __ia64_asr_i = (i); \
188 (__builtin_constant_p(i) \
189 && ( (__ia64_asr_i == 1) || (__ia64_asr_i == 4) \
190 || (__ia64_asr_i == 8) || (__ia64_asr_i == 16) \
191 || (__ia64_asr_i == -1) || (__ia64_asr_i == -4) \
192 || (__ia64_asr_i == -8) || (__ia64_asr_i == -16))) \
193 ? ia64_fetch_and_add(-__ia64_asr_i, &(v)->counter) \
194 : ia64_atomic64_sub(__ia64_asr_i, v); \
195})
196
197#define atomic_dec_return(v) atomic_sub_return(1, (v))
198#define atomic_inc_return(v) atomic_add_return(1, (v))
199#define atomic64_dec_return(v) atomic64_sub_return(1, (v))
200#define atomic64_inc_return(v) atomic64_add_return(1, (v))
201
202#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
203#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
204#define atomic_inc_and_test(v) (atomic_add_return(1, (v)) == 0)
205#define atomic64_sub_and_test(i,v) (atomic64_sub_return((i), (v)) == 0)
206#define atomic64_dec_and_test(v) (atomic64_sub_return(1, (v)) == 0)
207#define atomic64_inc_and_test(v) (atomic64_add_return(1, (v)) == 0)
208
209#define atomic_add(i,v) atomic_add_return((i), (v))
210#define atomic_sub(i,v) atomic_sub_return((i), (v))
211#define atomic_inc(v) atomic_add(1, (v))
212#define atomic_dec(v) atomic_sub(1, (v))
213
214#define atomic64_add(i,v) atomic64_add_return((i), (v))
215#define atomic64_sub(i,v) atomic64_sub_return((i), (v))
216#define atomic64_inc(v) atomic64_add(1, (v))
217#define atomic64_dec(v) atomic64_sub(1, (v))
218
219/* Atomic operations are already serializing */
220#define smp_mb__before_atomic_dec() barrier()
221#define smp_mb__after_atomic_dec() barrier()
222#define smp_mb__before_atomic_inc() barrier()
223#define smp_mb__after_atomic_inc() barrier()
224
225#include <asm-generic/atomic.h>
226#endif /* _ASM_IA64_ATOMIC_H */
diff --git a/include/asm-ia64/auxvec.h b/include/asm-ia64/auxvec.h
deleted file mode 100644
index 23cebe5685b..00000000000
--- a/include/asm-ia64/auxvec.h
+++ /dev/null
@@ -1,11 +0,0 @@
1#ifndef _ASM_IA64_AUXVEC_H
2#define _ASM_IA64_AUXVEC_H
3
4/*
5 * Architecture-neutral AT_ values are in the range 0-17. Leave some room for more of
6 * them, start the architecture-specific ones at 32.
7 */
8#define AT_SYSINFO 32
9#define AT_SYSINFO_EHDR 33
10
11#endif /* _ASM_IA64_AUXVEC_H */
diff --git a/include/asm-ia64/bitops.h b/include/asm-ia64/bitops.h
deleted file mode 100644
index e2ca8003733..00000000000
--- a/include/asm-ia64/bitops.h
+++ /dev/null
@@ -1,468 +0,0 @@
1#ifndef _ASM_IA64_BITOPS_H
2#define _ASM_IA64_BITOPS_H
3
4/*
5 * Copyright (C) 1998-2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 *
8 * 02/06/02 find_next_bit() and find_first_bit() added from Erich Focht's ia64
9 * O(1) scheduler patch
10 */
11
12#ifndef _LINUX_BITOPS_H
13#error only <linux/bitops.h> can be included directly
14#endif
15
16#include <linux/compiler.h>
17#include <linux/types.h>
18#include <asm/intrinsics.h>
19
20/**
21 * set_bit - Atomically set a bit in memory
22 * @nr: the bit to set
23 * @addr: the address to start counting from
24 *
25 * This function is atomic and may not be reordered. See __set_bit()
26 * if you do not require the atomic guarantees.
27 * Note that @nr may be almost arbitrarily large; this function is not
28 * restricted to acting on a single-word quantity.
29 *
30 * The address must be (at least) "long" aligned.
31 * Note that there are driver (e.g., eepro100) which use these operations to
32 * operate on hw-defined data-structures, so we can't easily change these
33 * operations to force a bigger alignment.
34 *
35 * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
36 */
37static __inline__ void
38set_bit (int nr, volatile void *addr)
39{
40 __u32 bit, old, new;
41 volatile __u32 *m;
42 CMPXCHG_BUGCHECK_DECL
43
44 m = (volatile __u32 *) addr + (nr >> 5);
45 bit = 1 << (nr & 31);
46 do {
47 CMPXCHG_BUGCHECK(m);
48 old = *m;
49 new = old | bit;
50 } while (cmpxchg_acq(m, old, new) != old);
51}
52
53/**
54 * __set_bit - Set a bit in memory
55 * @nr: the bit to set
56 * @addr: the address to start counting from
57 *
58 * Unlike set_bit(), this function is non-atomic and may be reordered.
59 * If it's called on the same region of memory simultaneously, the effect
60 * may be that only one operation succeeds.
61 */
62static __inline__ void
63__set_bit (int nr, volatile void *addr)
64{
65 *((__u32 *) addr + (nr >> 5)) |= (1 << (nr & 31));
66}
67
68/*
69 * clear_bit() has "acquire" semantics.
70 */
71#define smp_mb__before_clear_bit() smp_mb()
72#define smp_mb__after_clear_bit() do { /* skip */; } while (0)
73
74/**
75 * clear_bit - Clears a bit in memory
76 * @nr: Bit to clear
77 * @addr: Address to start counting from
78 *
79 * clear_bit() is atomic and may not be reordered. However, it does
80 * not contain a memory barrier, so if it is used for locking purposes,
81 * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
82 * in order to ensure changes are visible on other processors.
83 */
84static __inline__ void
85clear_bit (int nr, volatile void *addr)
86{
87 __u32 mask, old, new;
88 volatile __u32 *m;
89 CMPXCHG_BUGCHECK_DECL
90
91 m = (volatile __u32 *) addr + (nr >> 5);
92 mask = ~(1 << (nr & 31));
93 do {
94 CMPXCHG_BUGCHECK(m);
95 old = *m;
96 new = old & mask;
97 } while (cmpxchg_acq(m, old, new) != old);
98}
99
100/**
101 * clear_bit_unlock - Clears a bit in memory with release
102 * @nr: Bit to clear
103 * @addr: Address to start counting from
104 *
105 * clear_bit_unlock() is atomic and may not be reordered. It does
106 * contain a memory barrier suitable for unlock type operations.
107 */
108static __inline__ void
109clear_bit_unlock (int nr, volatile void *addr)
110{
111 __u32 mask, old, new;
112 volatile __u32 *m;
113 CMPXCHG_BUGCHECK_DECL
114
115 m = (volatile __u32 *) addr + (nr >> 5);
116 mask = ~(1 << (nr & 31));
117 do {
118 CMPXCHG_BUGCHECK(m);
119 old = *m;
120 new = old & mask;
121 } while (cmpxchg_rel(m, old, new) != old);
122}
123
124/**
125 * __clear_bit_unlock - Non-atomically clears a bit in memory with release
126 * @nr: Bit to clear
127 * @addr: Address to start counting from
128 *
129 * Similarly to clear_bit_unlock, the implementation uses a store
130 * with release semantics. See also __raw_spin_unlock().
131 */
132static __inline__ void
133__clear_bit_unlock(int nr, void *addr)
134{
135 __u32 * const m = (__u32 *) addr + (nr >> 5);
136 __u32 const new = *m & ~(1 << (nr & 31));
137
138 ia64_st4_rel_nta(m, new);
139}
140
141/**
142 * __clear_bit - Clears a bit in memory (non-atomic version)
143 * @nr: the bit to clear
144 * @addr: the address to start counting from
145 *
146 * Unlike clear_bit(), this function is non-atomic and may be reordered.
147 * If it's called on the same region of memory simultaneously, the effect
148 * may be that only one operation succeeds.
149 */
150static __inline__ void
151__clear_bit (int nr, volatile void *addr)
152{
153 *((__u32 *) addr + (nr >> 5)) &= ~(1 << (nr & 31));
154}
155
156/**
157 * change_bit - Toggle a bit in memory
158 * @nr: Bit to toggle
159 * @addr: Address to start counting from
160 *
161 * change_bit() is atomic and may not be reordered.
162 * Note that @nr may be almost arbitrarily large; this function is not
163 * restricted to acting on a single-word quantity.
164 */
165static __inline__ void
166change_bit (int nr, volatile void *addr)
167{
168 __u32 bit, old, new;
169 volatile __u32 *m;
170 CMPXCHG_BUGCHECK_DECL
171
172 m = (volatile __u32 *) addr + (nr >> 5);
173 bit = (1 << (nr & 31));
174 do {
175 CMPXCHG_BUGCHECK(m);
176 old = *m;
177 new = old ^ bit;
178 } while (cmpxchg_acq(m, old, new) != old);
179}
180
181/**
182 * __change_bit - Toggle a bit in memory
183 * @nr: the bit to toggle
184 * @addr: the address to start counting from
185 *
186 * Unlike change_bit(), this function is non-atomic and may be reordered.
187 * If it's called on the same region of memory simultaneously, the effect
188 * may be that only one operation succeeds.
189 */
190static __inline__ void
191__change_bit (int nr, volatile void *addr)
192{
193 *((__u32 *) addr + (nr >> 5)) ^= (1 << (nr & 31));
194}
195
196/**
197 * test_and_set_bit - Set a bit and return its old value
198 * @nr: Bit to set
199 * @addr: Address to count from
200 *
201 * This operation is atomic and cannot be reordered.
202 * It also implies the acquisition side of the memory barrier.
203 */
204static __inline__ int
205test_and_set_bit (int nr, volatile void *addr)
206{
207 __u32 bit, old, new;
208 volatile __u32 *m;
209 CMPXCHG_BUGCHECK_DECL
210
211 m = (volatile __u32 *) addr + (nr >> 5);
212 bit = 1 << (nr & 31);
213 do {
214 CMPXCHG_BUGCHECK(m);
215 old = *m;
216 new = old | bit;
217 } while (cmpxchg_acq(m, old, new) != old);
218 return (old & bit) != 0;
219}
220
221/**
222 * test_and_set_bit_lock - Set a bit and return its old value for lock
223 * @nr: Bit to set
224 * @addr: Address to count from
225 *
226 * This is the same as test_and_set_bit on ia64
227 */
228#define test_and_set_bit_lock test_and_set_bit
229
230/**
231 * __test_and_set_bit - Set a bit and return its old value
232 * @nr: Bit to set
233 * @addr: Address to count from
234 *
235 * This operation is non-atomic and can be reordered.
236 * If two examples of this operation race, one can appear to succeed
237 * but actually fail. You must protect multiple accesses with a lock.
238 */
239static __inline__ int
240__test_and_set_bit (int nr, volatile void *addr)
241{
242 __u32 *p = (__u32 *) addr + (nr >> 5);
243 __u32 m = 1 << (nr & 31);
244 int oldbitset = (*p & m) != 0;
245
246 *p |= m;
247 return oldbitset;
248}
249
250/**
251 * test_and_clear_bit - Clear a bit and return its old value
252 * @nr: Bit to clear
253 * @addr: Address to count from
254 *
255 * This operation is atomic and cannot be reordered.
256 * It also implies the acquisition side of the memory barrier.
257 */
258static __inline__ int
259test_and_clear_bit (int nr, volatile void *addr)
260{
261 __u32 mask, old, new;
262 volatile __u32 *m;
263 CMPXCHG_BUGCHECK_DECL
264
265 m = (volatile __u32 *) addr + (nr >> 5);
266 mask = ~(1 << (nr & 31));
267 do {
268 CMPXCHG_BUGCHECK(m);
269 old = *m;
270 new = old & mask;
271 } while (cmpxchg_acq(m, old, new) != old);
272 return (old & ~mask) != 0;
273}
274
275/**
276 * __test_and_clear_bit - Clear a bit and return its old value
277 * @nr: Bit to clear
278 * @addr: Address to count from
279 *
280 * This operation is non-atomic and can be reordered.
281 * If two examples of this operation race, one can appear to succeed
282 * but actually fail. You must protect multiple accesses with a lock.
283 */
284static __inline__ int
285__test_and_clear_bit(int nr, volatile void * addr)
286{
287 __u32 *p = (__u32 *) addr + (nr >> 5);
288 __u32 m = 1 << (nr & 31);
289 int oldbitset = *p & m;
290
291 *p &= ~m;
292 return oldbitset;
293}
294
295/**
296 * test_and_change_bit - Change a bit and return its old value
297 * @nr: Bit to change
298 * @addr: Address to count from
299 *
300 * This operation is atomic and cannot be reordered.
301 * It also implies the acquisition side of the memory barrier.
302 */
303static __inline__ int
304test_and_change_bit (int nr, volatile void *addr)
305{
306 __u32 bit, old, new;
307 volatile __u32 *m;
308 CMPXCHG_BUGCHECK_DECL
309
310 m = (volatile __u32 *) addr + (nr >> 5);
311 bit = (1 << (nr & 31));
312 do {
313 CMPXCHG_BUGCHECK(m);
314 old = *m;
315 new = old ^ bit;
316 } while (cmpxchg_acq(m, old, new) != old);
317 return (old & bit) != 0;
318}
319
320/**
321 * __test_and_change_bit - Change a bit and return its old value
322 * @nr: Bit to change
323 * @addr: Address to count from
324 *
325 * This operation is non-atomic and can be reordered.
326 */
327static __inline__ int
328__test_and_change_bit (int nr, void *addr)
329{
330 __u32 old, bit = (1 << (nr & 31));
331 __u32 *m = (__u32 *) addr + (nr >> 5);
332
333 old = *m;
334 *m = old ^ bit;
335 return (old & bit) != 0;
336}
337
338static __inline__ int
339test_bit (int nr, const volatile void *addr)
340{
341 return 1 & (((const volatile __u32 *) addr)[nr >> 5] >> (nr & 31));
342}
343
344/**
345 * ffz - find the first zero bit in a long word
346 * @x: The long word to find the bit in
347 *
348 * Returns the bit-number (0..63) of the first (least significant) zero bit.
349 * Undefined if no zero exists, so code should check against ~0UL first...
350 */
351static inline unsigned long
352ffz (unsigned long x)
353{
354 unsigned long result;
355
356 result = ia64_popcnt(x & (~x - 1));
357 return result;
358}
359
360/**
361 * __ffs - find first bit in word.
362 * @x: The word to search
363 *
364 * Undefined if no bit exists, so code should check against 0 first.
365 */
366static __inline__ unsigned long
367__ffs (unsigned long x)
368{
369 unsigned long result;
370
371 result = ia64_popcnt((x-1) & ~x);
372 return result;
373}
374
375#ifdef __KERNEL__
376
377/*
378 * Return bit number of last (most-significant) bit set. Undefined
379 * for x==0. Bits are numbered from 0..63 (e.g., ia64_fls(9) == 3).
380 */
381static inline unsigned long
382ia64_fls (unsigned long x)
383{
384 long double d = x;
385 long exp;
386
387 exp = ia64_getf_exp(d);
388 return exp - 0xffff;
389}
390
391/*
392 * Find the last (most significant) bit set. Returns 0 for x==0 and
393 * bits are numbered from 1..32 (e.g., fls(9) == 4).
394 */
395static inline int
396fls (int t)
397{
398 unsigned long x = t & 0xffffffffu;
399
400 if (!x)
401 return 0;
402 x |= x >> 1;
403 x |= x >> 2;
404 x |= x >> 4;
405 x |= x >> 8;
406 x |= x >> 16;
407 return ia64_popcnt(x);
408}
409
410/*
411 * Find the last (most significant) bit set. Undefined for x==0.
412 * Bits are numbered from 0..63 (e.g., __fls(9) == 3).
413 */
414static inline unsigned long
415__fls (unsigned long x)
416{
417 x |= x >> 1;
418 x |= x >> 2;
419 x |= x >> 4;
420 x |= x >> 8;
421 x |= x >> 16;
422 x |= x >> 32;
423 return ia64_popcnt(x) - 1;
424}
425
426#include <asm-generic/bitops/fls64.h>
427
428/*
429 * ffs: find first bit set. This is defined the same way as the libc and
430 * compiler builtin ffs routines, therefore differs in spirit from the above
431 * ffz (man ffs): it operates on "int" values only and the result value is the
432 * bit number + 1. ffs(0) is defined to return zero.
433 */
434#define ffs(x) __builtin_ffs(x)
435
436/*
437 * hweightN: returns the hamming weight (i.e. the number
438 * of bits set) of a N-bit word
439 */
440static __inline__ unsigned long
441hweight64 (unsigned long x)
442{
443 unsigned long result;
444 result = ia64_popcnt(x);
445 return result;
446}
447
448#define hweight32(x) (unsigned int) hweight64((x) & 0xfffffffful)
449#define hweight16(x) (unsigned int) hweight64((x) & 0xfffful)
450#define hweight8(x) (unsigned int) hweight64((x) & 0xfful)
451
452#endif /* __KERNEL__ */
453
454#include <asm-generic/bitops/find.h>
455
456#ifdef __KERNEL__
457
458#include <asm-generic/bitops/ext2-non-atomic.h>
459
460#define ext2_set_bit_atomic(l,n,a) test_and_set_bit(n,a)
461#define ext2_clear_bit_atomic(l,n,a) test_and_clear_bit(n,a)
462
463#include <asm-generic/bitops/minix.h>
464#include <asm-generic/bitops/sched.h>
465
466#endif /* __KERNEL__ */
467
468#endif /* _ASM_IA64_BITOPS_H */
diff --git a/include/asm-ia64/break.h b/include/asm-ia64/break.h
deleted file mode 100644
index f0340203989..00000000000
--- a/include/asm-ia64/break.h
+++ /dev/null
@@ -1,23 +0,0 @@
1#ifndef _ASM_IA64_BREAK_H
2#define _ASM_IA64_BREAK_H
3
4/*
5 * IA-64 Linux break numbers.
6 *
7 * Copyright (C) 1999 Hewlett-Packard Co
8 * Copyright (C) 1999 David Mosberger-Tang <davidm@hpl.hp.com>
9 */
10
11/*
12 * OS-specific debug break numbers:
13 */
14#define __IA64_BREAK_KDB 0x80100
15#define __IA64_BREAK_KPROBE 0x81000 /* .. 0x81fff */
16#define __IA64_BREAK_JPROBE 0x82000
17
18/*
19 * OS-specific break numbers:
20 */
21#define __IA64_BREAK_SYSCALL 0x100000
22
23#endif /* _ASM_IA64_BREAK_H */
diff --git a/include/asm-ia64/bug.h b/include/asm-ia64/bug.h
deleted file mode 100644
index 823616b5020..00000000000
--- a/include/asm-ia64/bug.h
+++ /dev/null
@@ -1,14 +0,0 @@
1#ifndef _ASM_IA64_BUG_H
2#define _ASM_IA64_BUG_H
3
4#ifdef CONFIG_BUG
5#define ia64_abort() __builtin_trap()
6#define BUG() do { printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); ia64_abort(); } while (0)
7
8/* should this BUG be made generic? */
9#define HAVE_ARCH_BUG
10#endif
11
12#include <asm-generic/bug.h>
13
14#endif
diff --git a/include/asm-ia64/bugs.h b/include/asm-ia64/bugs.h
deleted file mode 100644
index 433523e3b2e..00000000000
--- a/include/asm-ia64/bugs.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * This is included by init/main.c to check for architecture-dependent bugs.
3 *
4 * Needs:
5 * void check_bugs(void);
6 *
7 * Based on <asm-alpha/bugs.h>.
8 *
9 * Modified 1998, 1999, 2003
10 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co.
11 */
12#ifndef _ASM_IA64_BUGS_H
13#define _ASM_IA64_BUGS_H
14
15#include <asm/processor.h>
16
17extern void check_bugs (void);
18
19#endif /* _ASM_IA64_BUGS_H */
diff --git a/include/asm-ia64/byteorder.h b/include/asm-ia64/byteorder.h
deleted file mode 100644
index 69bd41d7c26..00000000000
--- a/include/asm-ia64/byteorder.h
+++ /dev/null
@@ -1,42 +0,0 @@
1#ifndef _ASM_IA64_BYTEORDER_H
2#define _ASM_IA64_BYTEORDER_H
3
4/*
5 * Modified 1998, 1999
6 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co.
7 */
8
9#include <asm/types.h>
10#include <asm/intrinsics.h>
11#include <linux/compiler.h>
12
13static __inline__ __attribute_const__ __u64
14__ia64_swab64 (__u64 x)
15{
16 __u64 result;
17
18 result = ia64_mux1(x, ia64_mux1_rev);
19 return result;
20}
21
22static __inline__ __attribute_const__ __u32
23__ia64_swab32 (__u32 x)
24{
25 return __ia64_swab64(x) >> 32;
26}
27
28static __inline__ __attribute_const__ __u16
29__ia64_swab16(__u16 x)
30{
31 return __ia64_swab64(x) >> 48;
32}
33
34#define __arch__swab64(x) __ia64_swab64(x)
35#define __arch__swab32(x) __ia64_swab32(x)
36#define __arch__swab16(x) __ia64_swab16(x)
37
38#define __BYTEORDER_HAS_U64__
39
40#include <linux/byteorder/little_endian.h>
41
42#endif /* _ASM_IA64_BYTEORDER_H */
diff --git a/include/asm-ia64/cache.h b/include/asm-ia64/cache.h
deleted file mode 100644
index e7482bd628f..00000000000
--- a/include/asm-ia64/cache.h
+++ /dev/null
@@ -1,29 +0,0 @@
1#ifndef _ASM_IA64_CACHE_H
2#define _ASM_IA64_CACHE_H
3
4
5/*
6 * Copyright (C) 1998-2000 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
8 */
9
10/* Bytes per L1 (data) cache line. */
11#define L1_CACHE_SHIFT CONFIG_IA64_L1_CACHE_SHIFT
12#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
13
14#ifdef CONFIG_SMP
15# define SMP_CACHE_SHIFT L1_CACHE_SHIFT
16# define SMP_CACHE_BYTES L1_CACHE_BYTES
17#else
18 /*
19 * The "aligned" directive can only _increase_ alignment, so this is
20 * safe and provides an easy way to avoid wasting space on a
21 * uni-processor:
22 */
23# define SMP_CACHE_SHIFT 3
24# define SMP_CACHE_BYTES (1 << 3)
25#endif
26
27#define __read_mostly __attribute__((__section__(".data.read_mostly")))
28
29#endif /* _ASM_IA64_CACHE_H */
diff --git a/include/asm-ia64/cacheflush.h b/include/asm-ia64/cacheflush.h
deleted file mode 100644
index afcfbda76e2..00000000000
--- a/include/asm-ia64/cacheflush.h
+++ /dev/null
@@ -1,51 +0,0 @@
1#ifndef _ASM_IA64_CACHEFLUSH_H
2#define _ASM_IA64_CACHEFLUSH_H
3
4/*
5 * Copyright (C) 2002 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 */
8
9#include <linux/page-flags.h>
10#include <linux/bitops.h>
11
12#include <asm/page.h>
13
14/*
15 * Cache flushing routines. This is the kind of stuff that can be very expensive, so try
16 * to avoid them whenever possible.
17 */
18
19#define flush_cache_all() do { } while (0)
20#define flush_cache_mm(mm) do { } while (0)
21#define flush_cache_dup_mm(mm) do { } while (0)
22#define flush_cache_range(vma, start, end) do { } while (0)
23#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
24#define flush_icache_page(vma,page) do { } while (0)
25#define flush_cache_vmap(start, end) do { } while (0)
26#define flush_cache_vunmap(start, end) do { } while (0)
27
28#define flush_dcache_page(page) \
29do { \
30 clear_bit(PG_arch_1, &(page)->flags); \
31} while (0)
32
33#define flush_dcache_mmap_lock(mapping) do { } while (0)
34#define flush_dcache_mmap_unlock(mapping) do { } while (0)
35
36extern void flush_icache_range (unsigned long start, unsigned long end);
37
38#define flush_icache_user_range(vma, page, user_addr, len) \
39do { \
40 unsigned long _addr = (unsigned long) page_address(page) + ((user_addr) & ~PAGE_MASK); \
41 flush_icache_range(_addr, _addr + (len)); \
42} while (0)
43
44#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
45do { memcpy(dst, src, len); \
46 flush_icache_user_range(vma, page, vaddr, len); \
47} while (0)
48#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
49 memcpy(dst, src, len)
50
51#endif /* _ASM_IA64_CACHEFLUSH_H */
diff --git a/include/asm-ia64/checksum.h b/include/asm-ia64/checksum.h
deleted file mode 100644
index 97af155057e..00000000000
--- a/include/asm-ia64/checksum.h
+++ /dev/null
@@ -1,79 +0,0 @@
1#ifndef _ASM_IA64_CHECKSUM_H
2#define _ASM_IA64_CHECKSUM_H
3
4/*
5 * Modified 1998, 1999
6 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
7 */
8
9/*
10 * This is a version of ip_compute_csum() optimized for IP headers,
11 * which always checksum on 4 octet boundaries.
12 */
13extern __sum16 ip_fast_csum(const void *iph, unsigned int ihl);
14
15/*
16 * Computes the checksum of the TCP/UDP pseudo-header returns a 16-bit
17 * checksum, already complemented
18 */
19extern __sum16 csum_tcpudp_magic (__be32 saddr, __be32 daddr,
20 unsigned short len,
21 unsigned short proto,
22 __wsum sum);
23
24extern __wsum csum_tcpudp_nofold (__be32 saddr, __be32 daddr,
25 unsigned short len,
26 unsigned short proto,
27 __wsum sum);
28
29/*
30 * Computes the checksum of a memory block at buff, length len,
31 * and adds in "sum" (32-bit)
32 *
33 * returns a 32-bit number suitable for feeding into itself
34 * or csum_tcpudp_magic
35 *
36 * this function must be called with even lengths, except
37 * for the last fragment, which may be odd
38 *
39 * it's best to have buff aligned on a 32-bit boundary
40 */
41extern __wsum csum_partial(const void *buff, int len, __wsum sum);
42
43/*
44 * Same as csum_partial, but copies from src while it checksums.
45 *
46 * Here it is even more important to align src and dst on a 32-bit (or
47 * even better 64-bit) boundary.
48 */
49extern __wsum csum_partial_copy_from_user(const void __user *src, void *dst,
50 int len, __wsum sum,
51 int *errp);
52
53extern __wsum csum_partial_copy_nocheck(const void *src, void *dst,
54 int len, __wsum sum);
55
56/*
57 * This routine is used for miscellaneous IP-like checksums, mainly in
58 * icmp.c
59 */
60extern __sum16 ip_compute_csum(const void *buff, int len);
61
62/*
63 * Fold a partial checksum without adding pseudo headers.
64 */
65static inline __sum16 csum_fold(__wsum csum)
66{
67 u32 sum = (__force u32)csum;
68 sum = (sum & 0xffff) + (sum >> 16);
69 sum = (sum & 0xffff) + (sum >> 16);
70 return (__force __sum16)~sum;
71}
72
73#define _HAVE_ARCH_IPV6_CSUM 1
74struct in6_addr;
75extern __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
76 const struct in6_addr *daddr, __u32 len, unsigned short proto,
77 __wsum csum);
78
79#endif /* _ASM_IA64_CHECKSUM_H */
diff --git a/include/asm-ia64/compat.h b/include/asm-ia64/compat.h
deleted file mode 100644
index dfcf75b8426..00000000000
--- a/include/asm-ia64/compat.h
+++ /dev/null
@@ -1,207 +0,0 @@
1#ifndef _ASM_IA64_COMPAT_H
2#define _ASM_IA64_COMPAT_H
3/*
4 * Architecture specific compatibility types
5 */
6#include <linux/types.h>
7
8#define COMPAT_USER_HZ 100
9
10typedef u32 compat_size_t;
11typedef s32 compat_ssize_t;
12typedef s32 compat_time_t;
13typedef s32 compat_clock_t;
14typedef s32 compat_key_t;
15typedef s32 compat_pid_t;
16typedef u16 __compat_uid_t;
17typedef u16 __compat_gid_t;
18typedef u32 __compat_uid32_t;
19typedef u32 __compat_gid32_t;
20typedef u16 compat_mode_t;
21typedef u32 compat_ino_t;
22typedef u16 compat_dev_t;
23typedef s32 compat_off_t;
24typedef s64 compat_loff_t;
25typedef u16 compat_nlink_t;
26typedef u16 compat_ipc_pid_t;
27typedef s32 compat_daddr_t;
28typedef u32 compat_caddr_t;
29typedef __kernel_fsid_t compat_fsid_t;
30typedef s32 compat_timer_t;
31
32typedef s32 compat_int_t;
33typedef s32 compat_long_t;
34typedef s64 __attribute__((aligned(4))) compat_s64;
35typedef u32 compat_uint_t;
36typedef u32 compat_ulong_t;
37typedef u64 __attribute__((aligned(4))) compat_u64;
38
39struct compat_timespec {
40 compat_time_t tv_sec;
41 s32 tv_nsec;
42};
43
44struct compat_timeval {
45 compat_time_t tv_sec;
46 s32 tv_usec;
47};
48
49struct compat_stat {
50 compat_dev_t st_dev;
51 u16 __pad1;
52 compat_ino_t st_ino;
53 compat_mode_t st_mode;
54 compat_nlink_t st_nlink;
55 __compat_uid_t st_uid;
56 __compat_gid_t st_gid;
57 compat_dev_t st_rdev;
58 u16 __pad2;
59 u32 st_size;
60 u32 st_blksize;
61 u32 st_blocks;
62 u32 st_atime;
63 u32 st_atime_nsec;
64 u32 st_mtime;
65 u32 st_mtime_nsec;
66 u32 st_ctime;
67 u32 st_ctime_nsec;
68 u32 __unused4;
69 u32 __unused5;
70};
71
72struct compat_flock {
73 short l_type;
74 short l_whence;
75 compat_off_t l_start;
76 compat_off_t l_len;
77 compat_pid_t l_pid;
78};
79
80#define F_GETLK64 12
81#define F_SETLK64 13
82#define F_SETLKW64 14
83
84/*
85 * IA32 uses 4 byte alignment for 64 bit quantities,
86 * so we need to pack this structure.
87 */
88struct compat_flock64 {
89 short l_type;
90 short l_whence;
91 compat_loff_t l_start;
92 compat_loff_t l_len;
93 compat_pid_t l_pid;
94} __attribute__((packed));
95
96struct compat_statfs {
97 int f_type;
98 int f_bsize;
99 int f_blocks;
100 int f_bfree;
101 int f_bavail;
102 int f_files;
103 int f_ffree;
104 compat_fsid_t f_fsid;
105 int f_namelen; /* SunOS ignores this field. */
106 int f_frsize;
107 int f_spare[5];
108};
109
110#define COMPAT_RLIM_OLD_INFINITY 0x7fffffff
111#define COMPAT_RLIM_INFINITY 0xffffffff
112
113typedef u32 compat_old_sigset_t; /* at least 32 bits */
114
115#define _COMPAT_NSIG 64
116#define _COMPAT_NSIG_BPW 32
117
118typedef u32 compat_sigset_word;
119
120#define COMPAT_OFF_T_MAX 0x7fffffff
121#define COMPAT_LOFF_T_MAX 0x7fffffffffffffffL
122
123struct compat_ipc64_perm {
124 compat_key_t key;
125 __compat_uid32_t uid;
126 __compat_gid32_t gid;
127 __compat_uid32_t cuid;
128 __compat_gid32_t cgid;
129 unsigned short mode;
130 unsigned short __pad1;
131 unsigned short seq;
132 unsigned short __pad2;
133 compat_ulong_t unused1;
134 compat_ulong_t unused2;
135};
136
137struct compat_semid64_ds {
138 struct compat_ipc64_perm sem_perm;
139 compat_time_t sem_otime;
140 compat_ulong_t __unused1;
141 compat_time_t sem_ctime;
142 compat_ulong_t __unused2;
143 compat_ulong_t sem_nsems;
144 compat_ulong_t __unused3;
145 compat_ulong_t __unused4;
146};
147
148struct compat_msqid64_ds {
149 struct compat_ipc64_perm msg_perm;
150 compat_time_t msg_stime;
151 compat_ulong_t __unused1;
152 compat_time_t msg_rtime;
153 compat_ulong_t __unused2;
154 compat_time_t msg_ctime;
155 compat_ulong_t __unused3;
156 compat_ulong_t msg_cbytes;
157 compat_ulong_t msg_qnum;
158 compat_ulong_t msg_qbytes;
159 compat_pid_t msg_lspid;
160 compat_pid_t msg_lrpid;
161 compat_ulong_t __unused4;
162 compat_ulong_t __unused5;
163};
164
165struct compat_shmid64_ds {
166 struct compat_ipc64_perm shm_perm;
167 compat_size_t shm_segsz;
168 compat_time_t shm_atime;
169 compat_ulong_t __unused1;
170 compat_time_t shm_dtime;
171 compat_ulong_t __unused2;
172 compat_time_t shm_ctime;
173 compat_ulong_t __unused3;
174 compat_pid_t shm_cpid;
175 compat_pid_t shm_lpid;
176 compat_ulong_t shm_nattch;
177 compat_ulong_t __unused4;
178 compat_ulong_t __unused5;
179};
180
181/*
182 * A pointer passed in from user mode. This should not be used for syscall parameters,
183 * just declare them as pointers because the syscall entry code will have appropriately
184 * converted them already.
185 */
186typedef u32 compat_uptr_t;
187
188static inline void __user *
189compat_ptr (compat_uptr_t uptr)
190{
191 return (void __user *) (unsigned long) uptr;
192}
193
194static inline compat_uptr_t
195ptr_to_compat(void __user *uptr)
196{
197 return (u32)(unsigned long)uptr;
198}
199
200static __inline__ void __user *
201compat_alloc_user_space (long len)
202{
203 struct pt_regs *regs = task_pt_regs(current);
204 return (void __user *) (((regs->r12 & 0xffffffff) & -16) - len);
205}
206
207#endif /* _ASM_IA64_COMPAT_H */
diff --git a/include/asm-ia64/cpu.h b/include/asm-ia64/cpu.h
deleted file mode 100644
index fcca30b9f11..00000000000
--- a/include/asm-ia64/cpu.h
+++ /dev/null
@@ -1,22 +0,0 @@
1#ifndef _ASM_IA64_CPU_H_
2#define _ASM_IA64_CPU_H_
3
4#include <linux/device.h>
5#include <linux/cpu.h>
6#include <linux/topology.h>
7#include <linux/percpu.h>
8
9struct ia64_cpu {
10 struct cpu cpu;
11};
12
13DECLARE_PER_CPU(struct ia64_cpu, cpu_devices);
14
15DECLARE_PER_CPU(int, cpu_state);
16
17#ifdef CONFIG_HOTPLUG_CPU
18extern int arch_register_cpu(int num);
19extern void arch_unregister_cpu(int);
20#endif
21
22#endif /* _ASM_IA64_CPU_H_ */
diff --git a/include/asm-ia64/cputime.h b/include/asm-ia64/cputime.h
deleted file mode 100644
index f9abdec6577..00000000000
--- a/include/asm-ia64/cputime.h
+++ /dev/null
@@ -1,110 +0,0 @@
1/*
2 * include/asm-ia64/cputime.h:
3 * Definitions for measuring cputime on ia64 machines.
4 *
5 * Based on <asm-powerpc/cputime.h>.
6 *
7 * Copyright (C) 2007 FUJITSU LIMITED
8 * Copyright (C) 2007 Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 *
15 * If we have CONFIG_VIRT_CPU_ACCOUNTING, we measure cpu time in nsec.
16 * Otherwise we measure cpu time in jiffies using the generic definitions.
17 */
18
19#ifndef __IA64_CPUTIME_H
20#define __IA64_CPUTIME_H
21
22#ifndef CONFIG_VIRT_CPU_ACCOUNTING
23#include <asm-generic/cputime.h>
24#else
25
26#include <linux/time.h>
27#include <linux/jiffies.h>
28#include <asm/processor.h>
29
30typedef u64 cputime_t;
31typedef u64 cputime64_t;
32
33#define cputime_zero ((cputime_t)0)
34#define cputime_max ((~((cputime_t)0) >> 1) - 1)
35#define cputime_add(__a, __b) ((__a) + (__b))
36#define cputime_sub(__a, __b) ((__a) - (__b))
37#define cputime_div(__a, __n) ((__a) / (__n))
38#define cputime_halve(__a) ((__a) >> 1)
39#define cputime_eq(__a, __b) ((__a) == (__b))
40#define cputime_gt(__a, __b) ((__a) > (__b))
41#define cputime_ge(__a, __b) ((__a) >= (__b))
42#define cputime_lt(__a, __b) ((__a) < (__b))
43#define cputime_le(__a, __b) ((__a) <= (__b))
44
45#define cputime64_zero ((cputime64_t)0)
46#define cputime64_add(__a, __b) ((__a) + (__b))
47#define cputime64_sub(__a, __b) ((__a) - (__b))
48#define cputime_to_cputime64(__ct) (__ct)
49
50/*
51 * Convert cputime <-> jiffies (HZ)
52 */
53#define cputime_to_jiffies(__ct) ((__ct) / (NSEC_PER_SEC / HZ))
54#define jiffies_to_cputime(__jif) ((__jif) * (NSEC_PER_SEC / HZ))
55#define cputime64_to_jiffies64(__ct) ((__ct) / (NSEC_PER_SEC / HZ))
56#define jiffies64_to_cputime64(__jif) ((__jif) * (NSEC_PER_SEC / HZ))
57
58/*
59 * Convert cputime <-> milliseconds
60 */
61#define cputime_to_msecs(__ct) ((__ct) / NSEC_PER_MSEC)
62#define msecs_to_cputime(__msecs) ((__msecs) * NSEC_PER_MSEC)
63
64/*
65 * Convert cputime <-> seconds
66 */
67#define cputime_to_secs(__ct) ((__ct) / NSEC_PER_SEC)
68#define secs_to_cputime(__secs) ((__secs) * NSEC_PER_SEC)
69
70/*
71 * Convert cputime <-> timespec (nsec)
72 */
73static inline cputime_t timespec_to_cputime(const struct timespec *val)
74{
75 cputime_t ret = val->tv_sec * NSEC_PER_SEC;
76 return (ret + val->tv_nsec);
77}
78static inline void cputime_to_timespec(const cputime_t ct, struct timespec *val)
79{
80 val->tv_sec = ct / NSEC_PER_SEC;
81 val->tv_nsec = ct % NSEC_PER_SEC;
82}
83
84/*
85 * Convert cputime <-> timeval (msec)
86 */
87static inline cputime_t timeval_to_cputime(struct timeval *val)
88{
89 cputime_t ret = val->tv_sec * NSEC_PER_SEC;
90 return (ret + val->tv_usec * NSEC_PER_USEC);
91}
92static inline void cputime_to_timeval(const cputime_t ct, struct timeval *val)
93{
94 val->tv_sec = ct / NSEC_PER_SEC;
95 val->tv_usec = (ct % NSEC_PER_SEC) / NSEC_PER_USEC;
96}
97
98/*
99 * Convert cputime <-> clock (USER_HZ)
100 */
101#define cputime_to_clock_t(__ct) ((__ct) / (NSEC_PER_SEC / USER_HZ))
102#define clock_t_to_cputime(__x) ((__x) * (NSEC_PER_SEC / USER_HZ))
103
104/*
105 * Convert cputime64 to clock.
106 */
107#define cputime64_to_clock_t(__ct) cputime_to_clock_t((cputime_t)__ct)
108
109#endif /* CONFIG_VIRT_CPU_ACCOUNTING */
110#endif /* __IA64_CPUTIME_H */
diff --git a/include/asm-ia64/current.h b/include/asm-ia64/current.h
deleted file mode 100644
index c659f90fbfd..00000000000
--- a/include/asm-ia64/current.h
+++ /dev/null
@@ -1,17 +0,0 @@
1#ifndef _ASM_IA64_CURRENT_H
2#define _ASM_IA64_CURRENT_H
3
4/*
5 * Modified 1998-2000
6 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
7 */
8
9#include <asm/intrinsics.h>
10
11/*
12 * In kernel mode, thread pointer (r13) is used to point to the current task
13 * structure.
14 */
15#define current ((struct task_struct *) ia64_getreg(_IA64_REG_TP))
16
17#endif /* _ASM_IA64_CURRENT_H */
diff --git a/include/asm-ia64/cyclone.h b/include/asm-ia64/cyclone.h
deleted file mode 100644
index 88f6500e84a..00000000000
--- a/include/asm-ia64/cyclone.h
+++ /dev/null
@@ -1,15 +0,0 @@
1#ifndef ASM_IA64_CYCLONE_H
2#define ASM_IA64_CYCLONE_H
3
4#ifdef CONFIG_IA64_CYCLONE
5extern int use_cyclone;
6extern void __init cyclone_setup(void);
7#else /* CONFIG_IA64_CYCLONE */
8#define use_cyclone 0
9static inline void cyclone_setup(void)
10{
11 printk(KERN_ERR "Cyclone Counter: System not configured"
12 " w/ CONFIG_IA64_CYCLONE.\n");
13}
14#endif /* CONFIG_IA64_CYCLONE */
15#endif /* !ASM_IA64_CYCLONE_H */
diff --git a/include/asm-ia64/delay.h b/include/asm-ia64/delay.h
deleted file mode 100644
index a30a62f235e..00000000000
--- a/include/asm-ia64/delay.h
+++ /dev/null
@@ -1,88 +0,0 @@
1#ifndef _ASM_IA64_DELAY_H
2#define _ASM_IA64_DELAY_H
3
4/*
5 * Delay routines using a pre-computed "cycles/usec" value.
6 *
7 * Copyright (C) 1998, 1999 Hewlett-Packard Co
8 * David Mosberger-Tang <davidm@hpl.hp.com>
9 * Copyright (C) 1999 VA Linux Systems
10 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
11 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
12 * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
13 */
14
15#include <linux/kernel.h>
16#include <linux/sched.h>
17#include <linux/compiler.h>
18
19#include <asm/intrinsics.h>
20#include <asm/processor.h>
21
22static __inline__ void
23ia64_set_itm (unsigned long val)
24{
25 ia64_setreg(_IA64_REG_CR_ITM, val);
26 ia64_srlz_d();
27}
28
29static __inline__ unsigned long
30ia64_get_itm (void)
31{
32 unsigned long result;
33
34 result = ia64_getreg(_IA64_REG_CR_ITM);
35 ia64_srlz_d();
36 return result;
37}
38
39static __inline__ void
40ia64_set_itv (unsigned long val)
41{
42 ia64_setreg(_IA64_REG_CR_ITV, val);
43 ia64_srlz_d();
44}
45
46static __inline__ unsigned long
47ia64_get_itv (void)
48{
49 return ia64_getreg(_IA64_REG_CR_ITV);
50}
51
52static __inline__ void
53ia64_set_itc (unsigned long val)
54{
55 ia64_setreg(_IA64_REG_AR_ITC, val);
56 ia64_srlz_d();
57}
58
59static __inline__ unsigned long
60ia64_get_itc (void)
61{
62 unsigned long result;
63
64 result = ia64_getreg(_IA64_REG_AR_ITC);
65 ia64_barrier();
66#ifdef CONFIG_ITANIUM
67 while (unlikely((__s32) result == -1)) {
68 result = ia64_getreg(_IA64_REG_AR_ITC);
69 ia64_barrier();
70 }
71#endif
72 return result;
73}
74
75extern void ia64_delay_loop (unsigned long loops);
76
77static __inline__ void
78__delay (unsigned long loops)
79{
80 if (unlikely(loops < 1))
81 return;
82
83 ia64_delay_loop (loops - 1);
84}
85
86extern void udelay (unsigned long usecs);
87
88#endif /* _ASM_IA64_DELAY_H */
diff --git a/include/asm-ia64/device.h b/include/asm-ia64/device.h
deleted file mode 100644
index 3db6daf7f25..00000000000
--- a/include/asm-ia64/device.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/*
2 * Arch specific extensions to struct device
3 *
4 * This file is released under the GPLv2
5 */
6#ifndef _ASM_IA64_DEVICE_H
7#define _ASM_IA64_DEVICE_H
8
9struct dev_archdata {
10#ifdef CONFIG_ACPI
11 void *acpi_handle;
12#endif
13};
14
15#endif /* _ASM_IA64_DEVICE_H */
diff --git a/include/asm-ia64/div64.h b/include/asm-ia64/div64.h
deleted file mode 100644
index 6cd978cefb2..00000000000
--- a/include/asm-ia64/div64.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/div64.h>
diff --git a/include/asm-ia64/dma-mapping.h b/include/asm-ia64/dma-mapping.h
deleted file mode 100644
index 9f0df9bd46b..00000000000
--- a/include/asm-ia64/dma-mapping.h
+++ /dev/null
@@ -1,97 +0,0 @@
1#ifndef _ASM_IA64_DMA_MAPPING_H
2#define _ASM_IA64_DMA_MAPPING_H
3
4/*
5 * Copyright (C) 2003-2004 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 */
8#include <asm/machvec.h>
9#include <linux/scatterlist.h>
10
11#define dma_alloc_coherent platform_dma_alloc_coherent
12/* coherent mem. is cheap */
13static inline void *
14dma_alloc_noncoherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
15 gfp_t flag)
16{
17 return dma_alloc_coherent(dev, size, dma_handle, flag);
18}
19#define dma_free_coherent platform_dma_free_coherent
20static inline void
21dma_free_noncoherent(struct device *dev, size_t size, void *cpu_addr,
22 dma_addr_t dma_handle)
23{
24 dma_free_coherent(dev, size, cpu_addr, dma_handle);
25}
26#define dma_map_single_attrs platform_dma_map_single_attrs
27static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
28 size_t size, int dir)
29{
30 return dma_map_single_attrs(dev, cpu_addr, size, dir, NULL);
31}
32#define dma_map_sg_attrs platform_dma_map_sg_attrs
33static inline int dma_map_sg(struct device *dev, struct scatterlist *sgl,
34 int nents, int dir)
35{
36 return dma_map_sg_attrs(dev, sgl, nents, dir, NULL);
37}
38#define dma_unmap_single_attrs platform_dma_unmap_single_attrs
39static inline void dma_unmap_single(struct device *dev, dma_addr_t cpu_addr,
40 size_t size, int dir)
41{
42 return dma_unmap_single_attrs(dev, cpu_addr, size, dir, NULL);
43}
44#define dma_unmap_sg_attrs platform_dma_unmap_sg_attrs
45static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sgl,
46 int nents, int dir)
47{
48 return dma_unmap_sg_attrs(dev, sgl, nents, dir, NULL);
49}
50#define dma_sync_single_for_cpu platform_dma_sync_single_for_cpu
51#define dma_sync_sg_for_cpu platform_dma_sync_sg_for_cpu
52#define dma_sync_single_for_device platform_dma_sync_single_for_device
53#define dma_sync_sg_for_device platform_dma_sync_sg_for_device
54#define dma_mapping_error platform_dma_mapping_error
55
56#define dma_map_page(dev, pg, off, size, dir) \
57 dma_map_single(dev, page_address(pg) + (off), (size), (dir))
58#define dma_unmap_page(dev, dma_addr, size, dir) \
59 dma_unmap_single(dev, dma_addr, size, dir)
60
61/*
62 * Rest of this file is part of the "Advanced DMA API". Use at your own risk.
63 * See Documentation/DMA-API.txt for details.
64 */
65
66#define dma_sync_single_range_for_cpu(dev, dma_handle, offset, size, dir) \
67 dma_sync_single_for_cpu(dev, dma_handle, size, dir)
68#define dma_sync_single_range_for_device(dev, dma_handle, offset, size, dir) \
69 dma_sync_single_for_device(dev, dma_handle, size, dir)
70
71#define dma_supported platform_dma_supported
72
73static inline int
74dma_set_mask (struct device *dev, u64 mask)
75{
76 if (!dev->dma_mask || !dma_supported(dev, mask))
77 return -EIO;
78 *dev->dma_mask = mask;
79 return 0;
80}
81
82extern int dma_get_cache_alignment(void);
83
84static inline void
85dma_cache_sync (struct device *dev, void *vaddr, size_t size,
86 enum dma_data_direction dir)
87{
88 /*
89 * IA-64 is cache-coherent, so this is mostly a no-op. However, we do need to
90 * ensure that dma_cache_sync() enforces order, hence the mb().
91 */
92 mb();
93}
94
95#define dma_is_consistent(d, h) (1) /* all we do is coherent memory... */
96
97#endif /* _ASM_IA64_DMA_MAPPING_H */
diff --git a/include/asm-ia64/dma.h b/include/asm-ia64/dma.h
deleted file mode 100644
index 4d97f60f1ef..00000000000
--- a/include/asm-ia64/dma.h
+++ /dev/null
@@ -1,24 +0,0 @@
1#ifndef _ASM_IA64_DMA_H
2#define _ASM_IA64_DMA_H
3
4/*
5 * Copyright (C) 1998-2002 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 */
8
9
10#include <asm/io.h> /* need byte IO */
11
12extern unsigned long MAX_DMA_ADDRESS;
13
14#ifdef CONFIG_PCI
15 extern int isa_dma_bridge_buggy;
16#else
17# define isa_dma_bridge_buggy (0)
18#endif
19
20#define free_dma(x)
21
22void dma_mark_clean(void *addr, size_t size);
23
24#endif /* _ASM_IA64_DMA_H */
diff --git a/include/asm-ia64/dmi.h b/include/asm-ia64/dmi.h
deleted file mode 100644
index 00eb1b130b6..00000000000
--- a/include/asm-ia64/dmi.h
+++ /dev/null
@@ -1,11 +0,0 @@
1#ifndef _ASM_DMI_H
2#define _ASM_DMI_H 1
3
4#include <asm/io.h>
5
6/* Use normal IO mappings for DMI */
7#define dmi_ioremap ioremap
8#define dmi_iounmap(x,l) iounmap(x)
9#define dmi_alloc(l) kmalloc(l, GFP_ATOMIC)
10
11#endif
diff --git a/include/asm-ia64/elf.h b/include/asm-ia64/elf.h
deleted file mode 100644
index 5e0c1a6bce8..00000000000
--- a/include/asm-ia64/elf.h
+++ /dev/null
@@ -1,269 +0,0 @@
1#ifndef _ASM_IA64_ELF_H
2#define _ASM_IA64_ELF_H
3
4/*
5 * ELF-specific definitions.
6 *
7 * Copyright (C) 1998-1999, 2002-2004 Hewlett-Packard Co
8 * David Mosberger-Tang <davidm@hpl.hp.com>
9 */
10
11
12#include <asm/fpu.h>
13#include <asm/page.h>
14#include <asm/auxvec.h>
15
16/*
17 * This is used to ensure we don't load something for the wrong architecture.
18 */
19#define elf_check_arch(x) ((x)->e_machine == EM_IA_64)
20
21/*
22 * These are used to set parameters in the core dumps.
23 */
24#define ELF_CLASS ELFCLASS64
25#define ELF_DATA ELFDATA2LSB
26#define ELF_ARCH EM_IA_64
27
28#define USE_ELF_CORE_DUMP
29#define CORE_DUMP_USE_REGSET
30
31/* Least-significant four bits of ELF header's e_flags are OS-specific. The bits are
32 interpreted as follows by Linux: */
33#define EF_IA_64_LINUX_EXECUTABLE_STACK 0x1 /* is stack (& heap) executable by default? */
34
35#define ELF_EXEC_PAGESIZE PAGE_SIZE
36
37/*
38 * This is the location that an ET_DYN program is loaded if exec'ed.
39 * Typical use of this is to invoke "./ld.so someprog" to test out a
40 * new version of the loader. We need to make sure that it is out of
41 * the way of the program that it will "exec", and that there is
42 * sufficient room for the brk.
43 */
44#define ELF_ET_DYN_BASE (TASK_UNMAPPED_BASE + 0x800000000UL)
45
46#define PT_IA_64_UNWIND 0x70000001
47
48/* IA-64 relocations: */
49#define R_IA64_NONE 0x00 /* none */
50#define R_IA64_IMM14 0x21 /* symbol + addend, add imm14 */
51#define R_IA64_IMM22 0x22 /* symbol + addend, add imm22 */
52#define R_IA64_IMM64 0x23 /* symbol + addend, mov imm64 */
53#define R_IA64_DIR32MSB 0x24 /* symbol + addend, data4 MSB */
54#define R_IA64_DIR32LSB 0x25 /* symbol + addend, data4 LSB */
55#define R_IA64_DIR64MSB 0x26 /* symbol + addend, data8 MSB */
56#define R_IA64_DIR64LSB 0x27 /* symbol + addend, data8 LSB */
57#define R_IA64_GPREL22 0x2a /* @gprel(sym+add), add imm22 */
58#define R_IA64_GPREL64I 0x2b /* @gprel(sym+add), mov imm64 */
59#define R_IA64_GPREL32MSB 0x2c /* @gprel(sym+add), data4 MSB */
60#define R_IA64_GPREL32LSB 0x2d /* @gprel(sym+add), data4 LSB */
61#define R_IA64_GPREL64MSB 0x2e /* @gprel(sym+add), data8 MSB */
62#define R_IA64_GPREL64LSB 0x2f /* @gprel(sym+add), data8 LSB */
63#define R_IA64_LTOFF22 0x32 /* @ltoff(sym+add), add imm22 */
64#define R_IA64_LTOFF64I 0x33 /* @ltoff(sym+add), mov imm64 */
65#define R_IA64_PLTOFF22 0x3a /* @pltoff(sym+add), add imm22 */
66#define R_IA64_PLTOFF64I 0x3b /* @pltoff(sym+add), mov imm64 */
67#define R_IA64_PLTOFF64MSB 0x3e /* @pltoff(sym+add), data8 MSB */
68#define R_IA64_PLTOFF64LSB 0x3f /* @pltoff(sym+add), data8 LSB */
69#define R_IA64_FPTR64I 0x43 /* @fptr(sym+add), mov imm64 */
70#define R_IA64_FPTR32MSB 0x44 /* @fptr(sym+add), data4 MSB */
71#define R_IA64_FPTR32LSB 0x45 /* @fptr(sym+add), data4 LSB */
72#define R_IA64_FPTR64MSB 0x46 /* @fptr(sym+add), data8 MSB */
73#define R_IA64_FPTR64LSB 0x47 /* @fptr(sym+add), data8 LSB */
74#define R_IA64_PCREL60B 0x48 /* @pcrel(sym+add), brl */
75#define R_IA64_PCREL21B 0x49 /* @pcrel(sym+add), ptb, call */
76#define R_IA64_PCREL21M 0x4a /* @pcrel(sym+add), chk.s */
77#define R_IA64_PCREL21F 0x4b /* @pcrel(sym+add), fchkf */
78#define R_IA64_PCREL32MSB 0x4c /* @pcrel(sym+add), data4 MSB */
79#define R_IA64_PCREL32LSB 0x4d /* @pcrel(sym+add), data4 LSB */
80#define R_IA64_PCREL64MSB 0x4e /* @pcrel(sym+add), data8 MSB */
81#define R_IA64_PCREL64LSB 0x4f /* @pcrel(sym+add), data8 LSB */
82#define R_IA64_LTOFF_FPTR22 0x52 /* @ltoff(@fptr(s+a)), imm22 */
83#define R_IA64_LTOFF_FPTR64I 0x53 /* @ltoff(@fptr(s+a)), imm64 */
84#define R_IA64_LTOFF_FPTR32MSB 0x54 /* @ltoff(@fptr(s+a)), 4 MSB */
85#define R_IA64_LTOFF_FPTR32LSB 0x55 /* @ltoff(@fptr(s+a)), 4 LSB */
86#define R_IA64_LTOFF_FPTR64MSB 0x56 /* @ltoff(@fptr(s+a)), 8 MSB */
87#define R_IA64_LTOFF_FPTR64LSB 0x57 /* @ltoff(@fptr(s+a)), 8 LSB */
88#define R_IA64_SEGREL32MSB 0x5c /* @segrel(sym+add), data4 MSB */
89#define R_IA64_SEGREL32LSB 0x5d /* @segrel(sym+add), data4 LSB */
90#define R_IA64_SEGREL64MSB 0x5e /* @segrel(sym+add), data8 MSB */
91#define R_IA64_SEGREL64LSB 0x5f /* @segrel(sym+add), data8 LSB */
92#define R_IA64_SECREL32MSB 0x64 /* @secrel(sym+add), data4 MSB */
93#define R_IA64_SECREL32LSB 0x65 /* @secrel(sym+add), data4 LSB */
94#define R_IA64_SECREL64MSB 0x66 /* @secrel(sym+add), data8 MSB */
95#define R_IA64_SECREL64LSB 0x67 /* @secrel(sym+add), data8 LSB */
96#define R_IA64_REL32MSB 0x6c /* data 4 + REL */
97#define R_IA64_REL32LSB 0x6d /* data 4 + REL */
98#define R_IA64_REL64MSB 0x6e /* data 8 + REL */
99#define R_IA64_REL64LSB 0x6f /* data 8 + REL */
100#define R_IA64_LTV32MSB 0x74 /* symbol + addend, data4 MSB */
101#define R_IA64_LTV32LSB 0x75 /* symbol + addend, data4 LSB */
102#define R_IA64_LTV64MSB 0x76 /* symbol + addend, data8 MSB */
103#define R_IA64_LTV64LSB 0x77 /* symbol + addend, data8 LSB */
104#define R_IA64_PCREL21BI 0x79 /* @pcrel(sym+add), ptb, call */
105#define R_IA64_PCREL22 0x7a /* @pcrel(sym+add), imm22 */
106#define R_IA64_PCREL64I 0x7b /* @pcrel(sym+add), imm64 */
107#define R_IA64_IPLTMSB 0x80 /* dynamic reloc, imported PLT, MSB */
108#define R_IA64_IPLTLSB 0x81 /* dynamic reloc, imported PLT, LSB */
109#define R_IA64_COPY 0x84 /* dynamic reloc, data copy */
110#define R_IA64_SUB 0x85 /* -symbol + addend, add imm22 */
111#define R_IA64_LTOFF22X 0x86 /* LTOFF22, relaxable. */
112#define R_IA64_LDXMOV 0x87 /* Use of LTOFF22X. */
113#define R_IA64_TPREL14 0x91 /* @tprel(sym+add), add imm14 */
114#define R_IA64_TPREL22 0x92 /* @tprel(sym+add), add imm22 */
115#define R_IA64_TPREL64I 0x93 /* @tprel(sym+add), add imm64 */
116#define R_IA64_TPREL64MSB 0x96 /* @tprel(sym+add), data8 MSB */
117#define R_IA64_TPREL64LSB 0x97 /* @tprel(sym+add), data8 LSB */
118#define R_IA64_LTOFF_TPREL22 0x9a /* @ltoff(@tprel(s+a)), add imm22 */
119#define R_IA64_DTPMOD64MSB 0xa6 /* @dtpmod(sym+add), data8 MSB */
120#define R_IA64_DTPMOD64LSB 0xa7 /* @dtpmod(sym+add), data8 LSB */
121#define R_IA64_LTOFF_DTPMOD22 0xaa /* @ltoff(@dtpmod(s+a)), imm22 */
122#define R_IA64_DTPREL14 0xb1 /* @dtprel(sym+add), imm14 */
123#define R_IA64_DTPREL22 0xb2 /* @dtprel(sym+add), imm22 */
124#define R_IA64_DTPREL64I 0xb3 /* @dtprel(sym+add), imm64 */
125#define R_IA64_DTPREL32MSB 0xb4 /* @dtprel(sym+add), data4 MSB */
126#define R_IA64_DTPREL32LSB 0xb5 /* @dtprel(sym+add), data4 LSB */
127#define R_IA64_DTPREL64MSB 0xb6 /* @dtprel(sym+add), data8 MSB */
128#define R_IA64_DTPREL64LSB 0xb7 /* @dtprel(sym+add), data8 LSB */
129#define R_IA64_LTOFF_DTPREL22 0xba /* @ltoff(@dtprel(s+a)), imm22 */
130
131/* IA-64 specific section flags: */
132#define SHF_IA_64_SHORT 0x10000000 /* section near gp */
133
134/*
135 * We use (abuse?) this macro to insert the (empty) vm_area that is
136 * used to map the register backing store. I don't see any better
137 * place to do this, but we should discuss this with Linus once we can
138 * talk to him...
139 */
140extern void ia64_init_addr_space (void);
141#define ELF_PLAT_INIT(_r, load_addr) ia64_init_addr_space()
142
143/* ELF register definitions. This is needed for core dump support. */
144
145/*
146 * elf_gregset_t contains the application-level state in the following order:
147 * r0-r31
148 * NaT bits (for r0-r31; bit N == 1 iff rN is a NaT)
149 * predicate registers (p0-p63)
150 * b0-b7
151 * ip cfm psr
152 * ar.rsc ar.bsp ar.bspstore ar.rnat
153 * ar.ccv ar.unat ar.fpsr ar.pfs ar.lc ar.ec ar.csd ar.ssd
154 */
155#define ELF_NGREG 128 /* we really need just 72 but let's leave some headroom... */
156#define ELF_NFPREG 128 /* f0 and f1 could be omitted, but so what... */
157
158/* elf_gregset_t register offsets */
159#define ELF_GR_0_OFFSET 0
160#define ELF_NAT_OFFSET (32 * sizeof(elf_greg_t))
161#define ELF_PR_OFFSET (33 * sizeof(elf_greg_t))
162#define ELF_BR_0_OFFSET (34 * sizeof(elf_greg_t))
163#define ELF_CR_IIP_OFFSET (42 * sizeof(elf_greg_t))
164#define ELF_CFM_OFFSET (43 * sizeof(elf_greg_t))
165#define ELF_CR_IPSR_OFFSET (44 * sizeof(elf_greg_t))
166#define ELF_GR_OFFSET(i) (ELF_GR_0_OFFSET + i * sizeof(elf_greg_t))
167#define ELF_BR_OFFSET(i) (ELF_BR_0_OFFSET + i * sizeof(elf_greg_t))
168#define ELF_AR_RSC_OFFSET (45 * sizeof(elf_greg_t))
169#define ELF_AR_BSP_OFFSET (46 * sizeof(elf_greg_t))
170#define ELF_AR_BSPSTORE_OFFSET (47 * sizeof(elf_greg_t))
171#define ELF_AR_RNAT_OFFSET (48 * sizeof(elf_greg_t))
172#define ELF_AR_CCV_OFFSET (49 * sizeof(elf_greg_t))
173#define ELF_AR_UNAT_OFFSET (50 * sizeof(elf_greg_t))
174#define ELF_AR_FPSR_OFFSET (51 * sizeof(elf_greg_t))
175#define ELF_AR_PFS_OFFSET (52 * sizeof(elf_greg_t))
176#define ELF_AR_LC_OFFSET (53 * sizeof(elf_greg_t))
177#define ELF_AR_EC_OFFSET (54 * sizeof(elf_greg_t))
178#define ELF_AR_CSD_OFFSET (55 * sizeof(elf_greg_t))
179#define ELF_AR_SSD_OFFSET (56 * sizeof(elf_greg_t))
180#define ELF_AR_END_OFFSET (57 * sizeof(elf_greg_t))
181
182typedef unsigned long elf_fpxregset_t;
183
184typedef unsigned long elf_greg_t;
185typedef elf_greg_t elf_gregset_t[ELF_NGREG];
186
187typedef struct ia64_fpreg elf_fpreg_t;
188typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
189
190
191
192struct pt_regs; /* forward declaration... */
193extern void ia64_elf_core_copy_regs (struct pt_regs *src, elf_gregset_t dst);
194#define ELF_CORE_COPY_REGS(_dest,_regs) ia64_elf_core_copy_regs(_regs, _dest);
195
196/* This macro yields a bitmask that programs can use to figure out
197 what instruction set this CPU supports. */
198#define ELF_HWCAP 0
199
200/* This macro yields a string that ld.so will use to load
201 implementation specific libraries for optimization. Not terribly
202 relevant until we have real hardware to play with... */
203#define ELF_PLATFORM NULL
204
205#define SET_PERSONALITY(ex, ibcs2) set_personality(PER_LINUX)
206#define elf_read_implies_exec(ex, executable_stack) \
207 ((executable_stack!=EXSTACK_DISABLE_X) && ((ex).e_flags & EF_IA_64_LINUX_EXECUTABLE_STACK) != 0)
208
209struct task_struct;
210
211#define GATE_EHDR ((const struct elfhdr *) GATE_ADDR)
212
213/* update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes */
214#define ARCH_DLINFO \
215do { \
216 extern char __kernel_syscall_via_epc[]; \
217 NEW_AUX_ENT(AT_SYSINFO, (unsigned long) __kernel_syscall_via_epc); \
218 NEW_AUX_ENT(AT_SYSINFO_EHDR, (unsigned long) GATE_EHDR); \
219} while (0)
220
221
222/*
223 * These macros parameterize elf_core_dump in fs/binfmt_elf.c to write out
224 * extra segments containing the gate DSO contents. Dumping its
225 * contents makes post-mortem fully interpretable later without matching up
226 * the same kernel and hardware config to see what PC values meant.
227 * Dumping its extra ELF program headers includes all the other information
228 * a debugger needs to easily find how the gate DSO was being used.
229 */
230#define ELF_CORE_EXTRA_PHDRS (GATE_EHDR->e_phnum)
231#define ELF_CORE_WRITE_EXTRA_PHDRS \
232do { \
233 const struct elf_phdr *const gate_phdrs = \
234 (const struct elf_phdr *) (GATE_ADDR + GATE_EHDR->e_phoff); \
235 int i; \
236 Elf64_Off ofs = 0; \
237 for (i = 0; i < GATE_EHDR->e_phnum; ++i) { \
238 struct elf_phdr phdr = gate_phdrs[i]; \
239 if (phdr.p_type == PT_LOAD) { \
240 phdr.p_memsz = PAGE_ALIGN(phdr.p_memsz); \
241 phdr.p_filesz = phdr.p_memsz; \
242 if (ofs == 0) { \
243 ofs = phdr.p_offset = offset; \
244 offset += phdr.p_filesz; \
245 } \
246 else \
247 phdr.p_offset = ofs; \
248 } \
249 else \
250 phdr.p_offset += ofs; \
251 phdr.p_paddr = 0; /* match other core phdrs */ \
252 DUMP_WRITE(&phdr, sizeof(phdr)); \
253 } \
254} while (0)
255#define ELF_CORE_WRITE_EXTRA_DATA \
256do { \
257 const struct elf_phdr *const gate_phdrs = \
258 (const struct elf_phdr *) (GATE_ADDR + GATE_EHDR->e_phoff); \
259 int i; \
260 for (i = 0; i < GATE_EHDR->e_phnum; ++i) { \
261 if (gate_phdrs[i].p_type == PT_LOAD) { \
262 DUMP_WRITE((void *) gate_phdrs[i].p_vaddr, \
263 PAGE_ALIGN(gate_phdrs[i].p_memsz)); \
264 break; \
265 } \
266 } \
267} while (0)
268
269#endif /* _ASM_IA64_ELF_H */
diff --git a/include/asm-ia64/emergency-restart.h b/include/asm-ia64/emergency-restart.h
deleted file mode 100644
index 108d8c48e42..00000000000
--- a/include/asm-ia64/emergency-restart.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _ASM_EMERGENCY_RESTART_H
2#define _ASM_EMERGENCY_RESTART_H
3
4#include <asm-generic/emergency-restart.h>
5
6#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-ia64/errno.h b/include/asm-ia64/errno.h
deleted file mode 100644
index 4c82b503d92..00000000000
--- a/include/asm-ia64/errno.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/errno.h>
diff --git a/include/asm-ia64/esi.h b/include/asm-ia64/esi.h
deleted file mode 100644
index 40991c6ba64..00000000000
--- a/include/asm-ia64/esi.h
+++ /dev/null
@@ -1,29 +0,0 @@
1/*
2 * ESI service calls.
3 *
4 * Copyright (c) Copyright 2005-2006 Hewlett-Packard Development Company, L.P.
5 * Alex Williamson <alex.williamson@hp.com>
6 */
7#ifndef esi_h
8#define esi_h
9
10#include <linux/efi.h>
11
12#define ESI_QUERY 0x00000001
13#define ESI_OPEN_HANDLE 0x02000000
14#define ESI_CLOSE_HANDLE 0x02000001
15
16enum esi_proc_type {
17 ESI_PROC_SERIALIZED, /* calls need to be serialized */
18 ESI_PROC_MP_SAFE, /* MP-safe, but not reentrant */
19 ESI_PROC_REENTRANT /* MP-safe and reentrant */
20};
21
22extern struct ia64_sal_retval esi_call_phys (void *, u64 *);
23extern int ia64_esi_call(efi_guid_t, struct ia64_sal_retval *,
24 enum esi_proc_type,
25 u64, u64, u64, u64, u64, u64, u64, u64);
26extern int ia64_esi_call_phys(efi_guid_t, struct ia64_sal_retval *, u64, u64,
27 u64, u64, u64, u64, u64, u64);
28
29#endif /* esi_h */
diff --git a/include/asm-ia64/fb.h b/include/asm-ia64/fb.h
deleted file mode 100644
index 89a397cee90..00000000000
--- a/include/asm-ia64/fb.h
+++ /dev/null
@@ -1,23 +0,0 @@
1#ifndef _ASM_FB_H_
2#define _ASM_FB_H_
3
4#include <linux/fb.h>
5#include <linux/fs.h>
6#include <linux/efi.h>
7#include <asm/page.h>
8
9static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
10 unsigned long off)
11{
12 if (efi_range_is_wc(vma->vm_start, vma->vm_end - vma->vm_start))
13 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
14 else
15 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
16}
17
18static inline int fb_is_primary_device(struct fb_info *info)
19{
20 return 0;
21}
22
23#endif /* _ASM_FB_H_ */
diff --git a/include/asm-ia64/fcntl.h b/include/asm-ia64/fcntl.h
deleted file mode 100644
index 1dd275dc8f6..00000000000
--- a/include/asm-ia64/fcntl.h
+++ /dev/null
@@ -1,13 +0,0 @@
1#ifndef _ASM_IA64_FCNTL_H
2#define _ASM_IA64_FCNTL_H
3/*
4 * Modified 1998-2000
5 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co.
6 */
7
8#define force_o_largefile() \
9 (personality(current->personality) != PER_LINUX32)
10
11#include <asm-generic/fcntl.h>
12
13#endif /* _ASM_IA64_FCNTL_H */
diff --git a/include/asm-ia64/fpswa.h b/include/asm-ia64/fpswa.h
deleted file mode 100644
index 62edfceadaa..00000000000
--- a/include/asm-ia64/fpswa.h
+++ /dev/null
@@ -1,73 +0,0 @@
1#ifndef _ASM_IA64_FPSWA_H
2#define _ASM_IA64_FPSWA_H
3
4/*
5 * Floating-point Software Assist
6 *
7 * Copyright (C) 1999 Intel Corporation.
8 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
9 * Copyright (C) 1999 Goutham Rao <goutham.rao@intel.com>
10 */
11
12typedef struct {
13 /* 4 * 128 bits */
14 unsigned long fp_lp[4*2];
15} fp_state_low_preserved_t;
16
17typedef struct {
18 /* 10 * 128 bits */
19 unsigned long fp_lv[10 * 2];
20} fp_state_low_volatile_t;
21
22typedef struct {
23 /* 16 * 128 bits */
24 unsigned long fp_hp[16 * 2];
25} fp_state_high_preserved_t;
26
27typedef struct {
28 /* 96 * 128 bits */
29 unsigned long fp_hv[96 * 2];
30} fp_state_high_volatile_t;
31
32/**
33 * floating point state to be passed to the FP emulation library by
34 * the trap/fault handler
35 */
36typedef struct {
37 unsigned long bitmask_low64;
38 unsigned long bitmask_high64;
39 fp_state_low_preserved_t *fp_state_low_preserved;
40 fp_state_low_volatile_t *fp_state_low_volatile;
41 fp_state_high_preserved_t *fp_state_high_preserved;
42 fp_state_high_volatile_t *fp_state_high_volatile;
43} fp_state_t;
44
45typedef struct {
46 unsigned long status;
47 unsigned long err0;
48 unsigned long err1;
49 unsigned long err2;
50} fpswa_ret_t;
51
52/**
53 * function header for the Floating Point software assist
54 * library. This function is invoked by the Floating point software
55 * assist trap/fault handler.
56 */
57typedef fpswa_ret_t (*efi_fpswa_t) (unsigned long trap_type, void *bundle, unsigned long *ipsr,
58 unsigned long *fsr, unsigned long *isr, unsigned long *preds,
59 unsigned long *ifs, fp_state_t *fp_state);
60
61/**
62 * This is the FPSWA library interface as defined by EFI. We need to pass a
63 * pointer to the interface itself on a call to the assist library
64 */
65typedef struct {
66 unsigned int revision;
67 unsigned int reserved;
68 efi_fpswa_t fpswa;
69} fpswa_interface_t;
70
71extern fpswa_interface_t *fpswa_interface;
72
73#endif /* _ASM_IA64_FPSWA_H */
diff --git a/include/asm-ia64/fpu.h b/include/asm-ia64/fpu.h
deleted file mode 100644
index 3859558ff0a..00000000000
--- a/include/asm-ia64/fpu.h
+++ /dev/null
@@ -1,66 +0,0 @@
1#ifndef _ASM_IA64_FPU_H
2#define _ASM_IA64_FPU_H
3
4/*
5 * Copyright (C) 1998, 1999, 2002, 2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 */
8
9#include <asm/types.h>
10
11/* floating point status register: */
12#define FPSR_TRAP_VD (1 << 0) /* invalid op trap disabled */
13#define FPSR_TRAP_DD (1 << 1) /* denormal trap disabled */
14#define FPSR_TRAP_ZD (1 << 2) /* zero-divide trap disabled */
15#define FPSR_TRAP_OD (1 << 3) /* overflow trap disabled */
16#define FPSR_TRAP_UD (1 << 4) /* underflow trap disabled */
17#define FPSR_TRAP_ID (1 << 5) /* inexact trap disabled */
18#define FPSR_S0(x) ((x) << 6)
19#define FPSR_S1(x) ((x) << 19)
20#define FPSR_S2(x) (__IA64_UL(x) << 32)
21#define FPSR_S3(x) (__IA64_UL(x) << 45)
22
23/* floating-point status field controls: */
24#define FPSF_FTZ (1 << 0) /* flush-to-zero */
25#define FPSF_WRE (1 << 1) /* widest-range exponent */
26#define FPSF_PC(x) (((x) & 0x3) << 2) /* precision control */
27#define FPSF_RC(x) (((x) & 0x3) << 4) /* rounding control */
28#define FPSF_TD (1 << 6) /* trap disabled */
29
30/* floating-point status field flags: */
31#define FPSF_V (1 << 7) /* invalid operation flag */
32#define FPSF_D (1 << 8) /* denormal/unnormal operand flag */
33#define FPSF_Z (1 << 9) /* zero divide (IEEE) flag */
34#define FPSF_O (1 << 10) /* overflow (IEEE) flag */
35#define FPSF_U (1 << 11) /* underflow (IEEE) flag */
36#define FPSF_I (1 << 12) /* inexact (IEEE) flag) */
37
38/* floating-point rounding control: */
39#define FPRC_NEAREST 0x0
40#define FPRC_NEGINF 0x1
41#define FPRC_POSINF 0x2
42#define FPRC_TRUNC 0x3
43
44#define FPSF_DEFAULT (FPSF_PC (0x3) | FPSF_RC (FPRC_NEAREST))
45
46/* This default value is the same as HP-UX uses. Don't change it
47 without a very good reason. */
48#define FPSR_DEFAULT (FPSR_TRAP_VD | FPSR_TRAP_DD | FPSR_TRAP_ZD \
49 | FPSR_TRAP_OD | FPSR_TRAP_UD | FPSR_TRAP_ID \
50 | FPSR_S0 (FPSF_DEFAULT) \
51 | FPSR_S1 (FPSF_DEFAULT | FPSF_TD | FPSF_WRE) \
52 | FPSR_S2 (FPSF_DEFAULT | FPSF_TD) \
53 | FPSR_S3 (FPSF_DEFAULT | FPSF_TD))
54
55# ifndef __ASSEMBLY__
56
57struct ia64_fpreg {
58 union {
59 unsigned long bits[2];
60 long double __dummy; /* force 16-byte alignment */
61 } u;
62};
63
64# endif /* __ASSEMBLY__ */
65
66#endif /* _ASM_IA64_FPU_H */
diff --git a/include/asm-ia64/futex.h b/include/asm-ia64/futex.h
deleted file mode 100644
index c7f0f062239..00000000000
--- a/include/asm-ia64/futex.h
+++ /dev/null
@@ -1,124 +0,0 @@
1#ifndef _ASM_FUTEX_H
2#define _ASM_FUTEX_H
3
4#include <linux/futex.h>
5#include <linux/uaccess.h>
6#include <asm/errno.h>
7#include <asm/system.h>
8
9#define __futex_atomic_op1(insn, ret, oldval, uaddr, oparg) \
10do { \
11 register unsigned long r8 __asm ("r8") = 0; \
12 __asm__ __volatile__( \
13 " mf;; \n" \
14 "[1:] " insn ";; \n" \
15 " .xdata4 \"__ex_table\", 1b-., 2f-. \n" \
16 "[2:]" \
17 : "+r" (r8), "=r" (oldval) \
18 : "r" (uaddr), "r" (oparg) \
19 : "memory"); \
20 ret = r8; \
21} while (0)
22
23#define __futex_atomic_op2(insn, ret, oldval, uaddr, oparg) \
24do { \
25 register unsigned long r8 __asm ("r8") = 0; \
26 int val, newval; \
27 do { \
28 __asm__ __volatile__( \
29 " mf;; \n" \
30 "[1:] ld4 %3=[%4];; \n" \
31 " mov %2=%3 \n" \
32 insn ";; \n" \
33 " mov ar.ccv=%2;; \n" \
34 "[2:] cmpxchg4.acq %1=[%4],%3,ar.ccv;; \n" \
35 " .xdata4 \"__ex_table\", 1b-., 3f-.\n" \
36 " .xdata4 \"__ex_table\", 2b-., 3f-.\n" \
37 "[3:]" \
38 : "+r" (r8), "=r" (val), "=&r" (oldval), \
39 "=&r" (newval) \
40 : "r" (uaddr), "r" (oparg) \
41 : "memory"); \
42 if (unlikely (r8)) \
43 break; \
44 } while (unlikely (val != oldval)); \
45 ret = r8; \
46} while (0)
47
48static inline int
49futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
50{
51 int op = (encoded_op >> 28) & 7;
52 int cmp = (encoded_op >> 24) & 15;
53 int oparg = (encoded_op << 8) >> 20;
54 int cmparg = (encoded_op << 20) >> 20;
55 int oldval = 0, ret;
56 if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
57 oparg = 1 << oparg;
58
59 if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
60 return -EFAULT;
61
62 pagefault_disable();
63
64 switch (op) {
65 case FUTEX_OP_SET:
66 __futex_atomic_op1("xchg4 %1=[%2],%3", ret, oldval, uaddr,
67 oparg);
68 break;
69 case FUTEX_OP_ADD:
70 __futex_atomic_op2("add %3=%3,%5", ret, oldval, uaddr, oparg);
71 break;
72 case FUTEX_OP_OR:
73 __futex_atomic_op2("or %3=%3,%5", ret, oldval, uaddr, oparg);
74 break;
75 case FUTEX_OP_ANDN:
76 __futex_atomic_op2("and %3=%3,%5", ret, oldval, uaddr,
77 ~oparg);
78 break;
79 case FUTEX_OP_XOR:
80 __futex_atomic_op2("xor %3=%3,%5", ret, oldval, uaddr, oparg);
81 break;
82 default:
83 ret = -ENOSYS;
84 }
85
86 pagefault_enable();
87
88 if (!ret) {
89 switch (cmp) {
90 case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
91 case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
92 case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
93 case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
94 case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
95 case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
96 default: ret = -ENOSYS;
97 }
98 }
99 return ret;
100}
101
102static inline int
103futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
104{
105 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
106 return -EFAULT;
107
108 {
109 register unsigned long r8 __asm ("r8");
110 __asm__ __volatile__(
111 " mf;; \n"
112 " mov ar.ccv=%3;; \n"
113 "[1:] cmpxchg4.acq %0=[%1],%2,ar.ccv \n"
114 " .xdata4 \"__ex_table\", 1b-., 2f-. \n"
115 "[2:]"
116 : "=r" (r8)
117 : "r" (uaddr), "r" (newval),
118 "rO" ((long) (unsigned) oldval)
119 : "memory");
120 return r8;
121 }
122}
123
124#endif /* _ASM_FUTEX_H */
diff --git a/include/asm-ia64/gcc_intrin.h b/include/asm-ia64/gcc_intrin.h
deleted file mode 100644
index 0f5b5592175..00000000000
--- a/include/asm-ia64/gcc_intrin.h
+++ /dev/null
@@ -1,620 +0,0 @@
1#ifndef _ASM_IA64_GCC_INTRIN_H
2#define _ASM_IA64_GCC_INTRIN_H
3/*
4 *
5 * Copyright (C) 2002,2003 Jun Nakajima <jun.nakajima@intel.com>
6 * Copyright (C) 2002,2003 Suresh Siddha <suresh.b.siddha@intel.com>
7 */
8
9#include <linux/compiler.h>
10
11/* define this macro to get some asm stmts included in 'c' files */
12#define ASM_SUPPORTED
13
14/* Optimization barrier */
15/* The "volatile" is due to gcc bugs */
16#define ia64_barrier() asm volatile ("":::"memory")
17
18#define ia64_stop() asm volatile (";;"::)
19
20#define ia64_invala_gr(regnum) asm volatile ("invala.e r%0" :: "i"(regnum))
21
22#define ia64_invala_fr(regnum) asm volatile ("invala.e f%0" :: "i"(regnum))
23
24#define ia64_flushrs() asm volatile ("flushrs;;":::"memory")
25
26#define ia64_loadrs() asm volatile ("loadrs;;":::"memory")
27
28extern void ia64_bad_param_for_setreg (void);
29extern void ia64_bad_param_for_getreg (void);
30
31#ifdef __KERNEL__
32register unsigned long ia64_r13 asm ("r13") __used;
33#endif
34
35#define ia64_native_setreg(regnum, val) \
36({ \
37 switch (regnum) { \
38 case _IA64_REG_PSR_L: \
39 asm volatile ("mov psr.l=%0" :: "r"(val) : "memory"); \
40 break; \
41 case _IA64_REG_AR_KR0 ... _IA64_REG_AR_EC: \
42 asm volatile ("mov ar%0=%1" :: \
43 "i" (regnum - _IA64_REG_AR_KR0), \
44 "r"(val): "memory"); \
45 break; \
46 case _IA64_REG_CR_DCR ... _IA64_REG_CR_LRR1: \
47 asm volatile ("mov cr%0=%1" :: \
48 "i" (regnum - _IA64_REG_CR_DCR), \
49 "r"(val): "memory" ); \
50 break; \
51 case _IA64_REG_SP: \
52 asm volatile ("mov r12=%0" :: \
53 "r"(val): "memory"); \
54 break; \
55 case _IA64_REG_GP: \
56 asm volatile ("mov gp=%0" :: "r"(val) : "memory"); \
57 break; \
58 default: \
59 ia64_bad_param_for_setreg(); \
60 break; \
61 } \
62})
63
64#define ia64_native_getreg(regnum) \
65({ \
66 __u64 ia64_intri_res; \
67 \
68 switch (regnum) { \
69 case _IA64_REG_GP: \
70 asm volatile ("mov %0=gp" : "=r"(ia64_intri_res)); \
71 break; \
72 case _IA64_REG_IP: \
73 asm volatile ("mov %0=ip" : "=r"(ia64_intri_res)); \
74 break; \
75 case _IA64_REG_PSR: \
76 asm volatile ("mov %0=psr" : "=r"(ia64_intri_res)); \
77 break; \
78 case _IA64_REG_TP: /* for current() */ \
79 ia64_intri_res = ia64_r13; \
80 break; \
81 case _IA64_REG_AR_KR0 ... _IA64_REG_AR_EC: \
82 asm volatile ("mov %0=ar%1" : "=r" (ia64_intri_res) \
83 : "i"(regnum - _IA64_REG_AR_KR0)); \
84 break; \
85 case _IA64_REG_CR_DCR ... _IA64_REG_CR_LRR1: \
86 asm volatile ("mov %0=cr%1" : "=r" (ia64_intri_res) \
87 : "i" (regnum - _IA64_REG_CR_DCR)); \
88 break; \
89 case _IA64_REG_SP: \
90 asm volatile ("mov %0=sp" : "=r" (ia64_intri_res)); \
91 break; \
92 default: \
93 ia64_bad_param_for_getreg(); \
94 break; \
95 } \
96 ia64_intri_res; \
97})
98
99#define ia64_hint_pause 0
100
101#define ia64_hint(mode) \
102({ \
103 switch (mode) { \
104 case ia64_hint_pause: \
105 asm volatile ("hint @pause" ::: "memory"); \
106 break; \
107 } \
108})
109
110
111/* Integer values for mux1 instruction */
112#define ia64_mux1_brcst 0
113#define ia64_mux1_mix 8
114#define ia64_mux1_shuf 9
115#define ia64_mux1_alt 10
116#define ia64_mux1_rev 11
117
118#define ia64_mux1(x, mode) \
119({ \
120 __u64 ia64_intri_res; \
121 \
122 switch (mode) { \
123 case ia64_mux1_brcst: \
124 asm ("mux1 %0=%1,@brcst" : "=r" (ia64_intri_res) : "r" (x)); \
125 break; \
126 case ia64_mux1_mix: \
127 asm ("mux1 %0=%1,@mix" : "=r" (ia64_intri_res) : "r" (x)); \
128 break; \
129 case ia64_mux1_shuf: \
130 asm ("mux1 %0=%1,@shuf" : "=r" (ia64_intri_res) : "r" (x)); \
131 break; \
132 case ia64_mux1_alt: \
133 asm ("mux1 %0=%1,@alt" : "=r" (ia64_intri_res) : "r" (x)); \
134 break; \
135 case ia64_mux1_rev: \
136 asm ("mux1 %0=%1,@rev" : "=r" (ia64_intri_res) : "r" (x)); \
137 break; \
138 } \
139 ia64_intri_res; \
140})
141
142#if __GNUC__ >= 4 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4)
143# define ia64_popcnt(x) __builtin_popcountl(x)
144#else
145# define ia64_popcnt(x) \
146 ({ \
147 __u64 ia64_intri_res; \
148 asm ("popcnt %0=%1" : "=r" (ia64_intri_res) : "r" (x)); \
149 \
150 ia64_intri_res; \
151 })
152#endif
153
154#define ia64_getf_exp(x) \
155({ \
156 long ia64_intri_res; \
157 \
158 asm ("getf.exp %0=%1" : "=r"(ia64_intri_res) : "f"(x)); \
159 \
160 ia64_intri_res; \
161})
162
163#define ia64_shrp(a, b, count) \
164({ \
165 __u64 ia64_intri_res; \
166 asm ("shrp %0=%1,%2,%3" : "=r"(ia64_intri_res) : "r"(a), "r"(b), "i"(count)); \
167 ia64_intri_res; \
168})
169
170#define ia64_ldfs(regnum, x) \
171({ \
172 register double __f__ asm ("f"#regnum); \
173 asm volatile ("ldfs %0=[%1]" :"=f"(__f__): "r"(x)); \
174})
175
176#define ia64_ldfd(regnum, x) \
177({ \
178 register double __f__ asm ("f"#regnum); \
179 asm volatile ("ldfd %0=[%1]" :"=f"(__f__): "r"(x)); \
180})
181
182#define ia64_ldfe(regnum, x) \
183({ \
184 register double __f__ asm ("f"#regnum); \
185 asm volatile ("ldfe %0=[%1]" :"=f"(__f__): "r"(x)); \
186})
187
188#define ia64_ldf8(regnum, x) \
189({ \
190 register double __f__ asm ("f"#regnum); \
191 asm volatile ("ldf8 %0=[%1]" :"=f"(__f__): "r"(x)); \
192})
193
194#define ia64_ldf_fill(regnum, x) \
195({ \
196 register double __f__ asm ("f"#regnum); \
197 asm volatile ("ldf.fill %0=[%1]" :"=f"(__f__): "r"(x)); \
198})
199
200#define ia64_st4_rel_nta(m, val) \
201({ \
202 asm volatile ("st4.rel.nta [%0] = %1\n\t" :: "r"(m), "r"(val)); \
203})
204
205#define ia64_stfs(x, regnum) \
206({ \
207 register double __f__ asm ("f"#regnum); \
208 asm volatile ("stfs [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \
209})
210
211#define ia64_stfd(x, regnum) \
212({ \
213 register double __f__ asm ("f"#regnum); \
214 asm volatile ("stfd [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \
215})
216
217#define ia64_stfe(x, regnum) \
218({ \
219 register double __f__ asm ("f"#regnum); \
220 asm volatile ("stfe [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \
221})
222
223#define ia64_stf8(x, regnum) \
224({ \
225 register double __f__ asm ("f"#regnum); \
226 asm volatile ("stf8 [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \
227})
228
229#define ia64_stf_spill(x, regnum) \
230({ \
231 register double __f__ asm ("f"#regnum); \
232 asm volatile ("stf.spill [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \
233})
234
235#define ia64_fetchadd4_acq(p, inc) \
236({ \
237 \
238 __u64 ia64_intri_res; \
239 asm volatile ("fetchadd4.acq %0=[%1],%2" \
240 : "=r"(ia64_intri_res) : "r"(p), "i" (inc) \
241 : "memory"); \
242 \
243 ia64_intri_res; \
244})
245
246#define ia64_fetchadd4_rel(p, inc) \
247({ \
248 __u64 ia64_intri_res; \
249 asm volatile ("fetchadd4.rel %0=[%1],%2" \
250 : "=r"(ia64_intri_res) : "r"(p), "i" (inc) \
251 : "memory"); \
252 \
253 ia64_intri_res; \
254})
255
256#define ia64_fetchadd8_acq(p, inc) \
257({ \
258 \
259 __u64 ia64_intri_res; \
260 asm volatile ("fetchadd8.acq %0=[%1],%2" \
261 : "=r"(ia64_intri_res) : "r"(p), "i" (inc) \
262 : "memory"); \
263 \
264 ia64_intri_res; \
265})
266
267#define ia64_fetchadd8_rel(p, inc) \
268({ \
269 __u64 ia64_intri_res; \
270 asm volatile ("fetchadd8.rel %0=[%1],%2" \
271 : "=r"(ia64_intri_res) : "r"(p), "i" (inc) \
272 : "memory"); \
273 \
274 ia64_intri_res; \
275})
276
277#define ia64_xchg1(ptr,x) \
278({ \
279 __u64 ia64_intri_res; \
280 asm volatile ("xchg1 %0=[%1],%2" \
281 : "=r" (ia64_intri_res) : "r" (ptr), "r" (x) : "memory"); \
282 ia64_intri_res; \
283})
284
285#define ia64_xchg2(ptr,x) \
286({ \
287 __u64 ia64_intri_res; \
288 asm volatile ("xchg2 %0=[%1],%2" : "=r" (ia64_intri_res) \
289 : "r" (ptr), "r" (x) : "memory"); \
290 ia64_intri_res; \
291})
292
293#define ia64_xchg4(ptr,x) \
294({ \
295 __u64 ia64_intri_res; \
296 asm volatile ("xchg4 %0=[%1],%2" : "=r" (ia64_intri_res) \
297 : "r" (ptr), "r" (x) : "memory"); \
298 ia64_intri_res; \
299})
300
301#define ia64_xchg8(ptr,x) \
302({ \
303 __u64 ia64_intri_res; \
304 asm volatile ("xchg8 %0=[%1],%2" : "=r" (ia64_intri_res) \
305 : "r" (ptr), "r" (x) : "memory"); \
306 ia64_intri_res; \
307})
308
309#define ia64_cmpxchg1_acq(ptr, new, old) \
310({ \
311 __u64 ia64_intri_res; \
312 asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
313 asm volatile ("cmpxchg1.acq %0=[%1],%2,ar.ccv": \
314 "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
315 ia64_intri_res; \
316})
317
318#define ia64_cmpxchg1_rel(ptr, new, old) \
319({ \
320 __u64 ia64_intri_res; \
321 asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
322 asm volatile ("cmpxchg1.rel %0=[%1],%2,ar.ccv": \
323 "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
324 ia64_intri_res; \
325})
326
327#define ia64_cmpxchg2_acq(ptr, new, old) \
328({ \
329 __u64 ia64_intri_res; \
330 asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
331 asm volatile ("cmpxchg2.acq %0=[%1],%2,ar.ccv": \
332 "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
333 ia64_intri_res; \
334})
335
336#define ia64_cmpxchg2_rel(ptr, new, old) \
337({ \
338 __u64 ia64_intri_res; \
339 asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
340 \
341 asm volatile ("cmpxchg2.rel %0=[%1],%2,ar.ccv": \
342 "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
343 ia64_intri_res; \
344})
345
346#define ia64_cmpxchg4_acq(ptr, new, old) \
347({ \
348 __u64 ia64_intri_res; \
349 asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
350 asm volatile ("cmpxchg4.acq %0=[%1],%2,ar.ccv": \
351 "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
352 ia64_intri_res; \
353})
354
355#define ia64_cmpxchg4_rel(ptr, new, old) \
356({ \
357 __u64 ia64_intri_res; \
358 asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
359 asm volatile ("cmpxchg4.rel %0=[%1],%2,ar.ccv": \
360 "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
361 ia64_intri_res; \
362})
363
364#define ia64_cmpxchg8_acq(ptr, new, old) \
365({ \
366 __u64 ia64_intri_res; \
367 asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
368 asm volatile ("cmpxchg8.acq %0=[%1],%2,ar.ccv": \
369 "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
370 ia64_intri_res; \
371})
372
373#define ia64_cmpxchg8_rel(ptr, new, old) \
374({ \
375 __u64 ia64_intri_res; \
376 asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
377 \
378 asm volatile ("cmpxchg8.rel %0=[%1],%2,ar.ccv": \
379 "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
380 ia64_intri_res; \
381})
382
383#define ia64_mf() asm volatile ("mf" ::: "memory")
384#define ia64_mfa() asm volatile ("mf.a" ::: "memory")
385
386#define ia64_invala() asm volatile ("invala" ::: "memory")
387
388#define ia64_native_thash(addr) \
389({ \
390 __u64 ia64_intri_res; \
391 asm volatile ("thash %0=%1" : "=r"(ia64_intri_res) : "r" (addr)); \
392 ia64_intri_res; \
393})
394
395#define ia64_srlz_i() asm volatile (";; srlz.i ;;" ::: "memory")
396#define ia64_srlz_d() asm volatile (";; srlz.d" ::: "memory");
397
398#ifdef HAVE_SERIALIZE_DIRECTIVE
399# define ia64_dv_serialize_data() asm volatile (".serialize.data");
400# define ia64_dv_serialize_instruction() asm volatile (".serialize.instruction");
401#else
402# define ia64_dv_serialize_data()
403# define ia64_dv_serialize_instruction()
404#endif
405
406#define ia64_nop(x) asm volatile ("nop %0"::"i"(x));
407
408#define ia64_itci(addr) asm volatile ("itc.i %0;;" :: "r"(addr) : "memory")
409
410#define ia64_itcd(addr) asm volatile ("itc.d %0;;" :: "r"(addr) : "memory")
411
412
413#define ia64_itri(trnum, addr) asm volatile ("itr.i itr[%0]=%1" \
414 :: "r"(trnum), "r"(addr) : "memory")
415
416#define ia64_itrd(trnum, addr) asm volatile ("itr.d dtr[%0]=%1" \
417 :: "r"(trnum), "r"(addr) : "memory")
418
419#define ia64_tpa(addr) \
420({ \
421 __u64 ia64_pa; \
422 asm volatile ("tpa %0 = %1" : "=r"(ia64_pa) : "r"(addr) : "memory"); \
423 ia64_pa; \
424})
425
426#define __ia64_set_dbr(index, val) \
427 asm volatile ("mov dbr[%0]=%1" :: "r"(index), "r"(val) : "memory")
428
429#define ia64_set_ibr(index, val) \
430 asm volatile ("mov ibr[%0]=%1" :: "r"(index), "r"(val) : "memory")
431
432#define ia64_set_pkr(index, val) \
433 asm volatile ("mov pkr[%0]=%1" :: "r"(index), "r"(val) : "memory")
434
435#define ia64_set_pmc(index, val) \
436 asm volatile ("mov pmc[%0]=%1" :: "r"(index), "r"(val) : "memory")
437
438#define ia64_set_pmd(index, val) \
439 asm volatile ("mov pmd[%0]=%1" :: "r"(index), "r"(val) : "memory")
440
441#define ia64_native_set_rr(index, val) \
442 asm volatile ("mov rr[%0]=%1" :: "r"(index), "r"(val) : "memory");
443
444#define ia64_native_get_cpuid(index) \
445({ \
446 __u64 ia64_intri_res; \
447 asm volatile ("mov %0=cpuid[%r1]" : "=r"(ia64_intri_res) : "rO"(index)); \
448 ia64_intri_res; \
449})
450
451#define __ia64_get_dbr(index) \
452({ \
453 __u64 ia64_intri_res; \
454 asm volatile ("mov %0=dbr[%1]" : "=r"(ia64_intri_res) : "r"(index)); \
455 ia64_intri_res; \
456})
457
458#define ia64_get_ibr(index) \
459({ \
460 __u64 ia64_intri_res; \
461 asm volatile ("mov %0=ibr[%1]" : "=r"(ia64_intri_res) : "r"(index)); \
462 ia64_intri_res; \
463})
464
465#define ia64_get_pkr(index) \
466({ \
467 __u64 ia64_intri_res; \
468 asm volatile ("mov %0=pkr[%1]" : "=r"(ia64_intri_res) : "r"(index)); \
469 ia64_intri_res; \
470})
471
472#define ia64_get_pmc(index) \
473({ \
474 __u64 ia64_intri_res; \
475 asm volatile ("mov %0=pmc[%1]" : "=r"(ia64_intri_res) : "r"(index)); \
476 ia64_intri_res; \
477})
478
479
480#define ia64_native_get_pmd(index) \
481({ \
482 __u64 ia64_intri_res; \
483 asm volatile ("mov %0=pmd[%1]" : "=r"(ia64_intri_res) : "r"(index)); \
484 ia64_intri_res; \
485})
486
487#define ia64_native_get_rr(index) \
488({ \
489 __u64 ia64_intri_res; \
490 asm volatile ("mov %0=rr[%1]" : "=r"(ia64_intri_res) : "r" (index)); \
491 ia64_intri_res; \
492})
493
494#define ia64_native_fc(addr) asm volatile ("fc %0" :: "r"(addr) : "memory")
495
496
497#define ia64_sync_i() asm volatile (";; sync.i" ::: "memory")
498
499#define ia64_native_ssm(mask) asm volatile ("ssm %0":: "i"((mask)) : "memory")
500#define ia64_native_rsm(mask) asm volatile ("rsm %0":: "i"((mask)) : "memory")
501#define ia64_sum(mask) asm volatile ("sum %0":: "i"((mask)) : "memory")
502#define ia64_rum(mask) asm volatile ("rum %0":: "i"((mask)) : "memory")
503
504#define ia64_ptce(addr) asm volatile ("ptc.e %0" :: "r"(addr))
505
506#define ia64_native_ptcga(addr, size) \
507do { \
508 asm volatile ("ptc.ga %0,%1" :: "r"(addr), "r"(size) : "memory"); \
509 ia64_dv_serialize_data(); \
510} while (0)
511
512#define ia64_ptcl(addr, size) \
513do { \
514 asm volatile ("ptc.l %0,%1" :: "r"(addr), "r"(size) : "memory"); \
515 ia64_dv_serialize_data(); \
516} while (0)
517
518#define ia64_ptri(addr, size) \
519 asm volatile ("ptr.i %0,%1" :: "r"(addr), "r"(size) : "memory")
520
521#define ia64_ptrd(addr, size) \
522 asm volatile ("ptr.d %0,%1" :: "r"(addr), "r"(size) : "memory")
523
524#define ia64_ttag(addr) \
525({ \
526 __u64 ia64_intri_res; \
527 asm volatile ("ttag %0=%1" : "=r"(ia64_intri_res) : "r" (addr)); \
528 ia64_intri_res; \
529})
530
531
532/* Values for lfhint in ia64_lfetch and ia64_lfetch_fault */
533
534#define ia64_lfhint_none 0
535#define ia64_lfhint_nt1 1
536#define ia64_lfhint_nt2 2
537#define ia64_lfhint_nta 3
538
539#define ia64_lfetch(lfhint, y) \
540({ \
541 switch (lfhint) { \
542 case ia64_lfhint_none: \
543 asm volatile ("lfetch [%0]" : : "r"(y)); \
544 break; \
545 case ia64_lfhint_nt1: \
546 asm volatile ("lfetch.nt1 [%0]" : : "r"(y)); \
547 break; \
548 case ia64_lfhint_nt2: \
549 asm volatile ("lfetch.nt2 [%0]" : : "r"(y)); \
550 break; \
551 case ia64_lfhint_nta: \
552 asm volatile ("lfetch.nta [%0]" : : "r"(y)); \
553 break; \
554 } \
555})
556
557#define ia64_lfetch_excl(lfhint, y) \
558({ \
559 switch (lfhint) { \
560 case ia64_lfhint_none: \
561 asm volatile ("lfetch.excl [%0]" :: "r"(y)); \
562 break; \
563 case ia64_lfhint_nt1: \
564 asm volatile ("lfetch.excl.nt1 [%0]" :: "r"(y)); \
565 break; \
566 case ia64_lfhint_nt2: \
567 asm volatile ("lfetch.excl.nt2 [%0]" :: "r"(y)); \
568 break; \
569 case ia64_lfhint_nta: \
570 asm volatile ("lfetch.excl.nta [%0]" :: "r"(y)); \
571 break; \
572 } \
573})
574
575#define ia64_lfetch_fault(lfhint, y) \
576({ \
577 switch (lfhint) { \
578 case ia64_lfhint_none: \
579 asm volatile ("lfetch.fault [%0]" : : "r"(y)); \
580 break; \
581 case ia64_lfhint_nt1: \
582 asm volatile ("lfetch.fault.nt1 [%0]" : : "r"(y)); \
583 break; \
584 case ia64_lfhint_nt2: \
585 asm volatile ("lfetch.fault.nt2 [%0]" : : "r"(y)); \
586 break; \
587 case ia64_lfhint_nta: \
588 asm volatile ("lfetch.fault.nta [%0]" : : "r"(y)); \
589 break; \
590 } \
591})
592
593#define ia64_lfetch_fault_excl(lfhint, y) \
594({ \
595 switch (lfhint) { \
596 case ia64_lfhint_none: \
597 asm volatile ("lfetch.fault.excl [%0]" :: "r"(y)); \
598 break; \
599 case ia64_lfhint_nt1: \
600 asm volatile ("lfetch.fault.excl.nt1 [%0]" :: "r"(y)); \
601 break; \
602 case ia64_lfhint_nt2: \
603 asm volatile ("lfetch.fault.excl.nt2 [%0]" :: "r"(y)); \
604 break; \
605 case ia64_lfhint_nta: \
606 asm volatile ("lfetch.fault.excl.nta [%0]" :: "r"(y)); \
607 break; \
608 } \
609})
610
611#define ia64_native_intrin_local_irq_restore(x) \
612do { \
613 asm volatile (";; cmp.ne p6,p7=%0,r0;;" \
614 "(p6) ssm psr.i;" \
615 "(p7) rsm psr.i;;" \
616 "(p6) srlz.d" \
617 :: "r"((x)) : "p6", "p7", "memory"); \
618} while (0)
619
620#endif /* _ASM_IA64_GCC_INTRIN_H */
diff --git a/include/asm-ia64/hardirq.h b/include/asm-ia64/hardirq.h
deleted file mode 100644
index 140e495b8e0..00000000000
--- a/include/asm-ia64/hardirq.h
+++ /dev/null
@@ -1,37 +0,0 @@
1#ifndef _ASM_IA64_HARDIRQ_H
2#define _ASM_IA64_HARDIRQ_H
3
4/*
5 * Modified 1998-2002, 2004 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 */
8
9
10#include <linux/threads.h>
11#include <linux/irq.h>
12
13#include <asm/processor.h>
14
15/*
16 * No irq_cpustat_t for IA-64. The data is held in the per-CPU data structure.
17 */
18
19#define __ARCH_IRQ_STAT 1
20
21#define local_softirq_pending() (local_cpu_data->softirq_pending)
22
23#define HARDIRQ_BITS 14
24
25/*
26 * The hardirq mask has to be large enough to have space for potentially all IRQ sources
27 * in the system nesting on a single CPU:
28 */
29#if (1 << HARDIRQ_BITS) < NR_IRQS
30# error HARDIRQ_BITS is too low!
31#endif
32
33extern void __iomem *ipi_base_addr;
34
35void ack_bad_irq(unsigned int irq);
36
37#endif /* _ASM_IA64_HARDIRQ_H */
diff --git a/include/asm-ia64/hpsim.h b/include/asm-ia64/hpsim.h
deleted file mode 100644
index 892ab198a9d..00000000000
--- a/include/asm-ia64/hpsim.h
+++ /dev/null
@@ -1,16 +0,0 @@
1#ifndef _ASMIA64_HPSIM_H
2#define _ASMIA64_HPSIM_H
3
4#ifndef CONFIG_HP_SIMSERIAL_CONSOLE
5static inline int simcons_register(void) { return 1; }
6#else
7int simcons_register(void);
8#endif
9
10struct tty_driver;
11extern struct tty_driver *hp_simserial_driver;
12
13void ia64_ssc_connect_irq(long intr, long irq);
14void ia64_ctl_trace(long on);
15
16#endif
diff --git a/include/asm-ia64/hugetlb.h b/include/asm-ia64/hugetlb.h
deleted file mode 100644
index da55c63728e..00000000000
--- a/include/asm-ia64/hugetlb.h
+++ /dev/null
@@ -1,80 +0,0 @@
1#ifndef _ASM_IA64_HUGETLB_H
2#define _ASM_IA64_HUGETLB_H
3
4#include <asm/page.h>
5
6
7void hugetlb_free_pgd_range(struct mmu_gather *tlb, unsigned long addr,
8 unsigned long end, unsigned long floor,
9 unsigned long ceiling);
10
11int prepare_hugepage_range(struct file *file,
12 unsigned long addr, unsigned long len);
13
14static inline int is_hugepage_only_range(struct mm_struct *mm,
15 unsigned long addr,
16 unsigned long len)
17{
18 return (REGION_NUMBER(addr) == RGN_HPAGE ||
19 REGION_NUMBER((addr)+(len)-1) == RGN_HPAGE);
20}
21
22static inline void hugetlb_prefault_arch_hook(struct mm_struct *mm)
23{
24}
25
26static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
27 pte_t *ptep, pte_t pte)
28{
29 set_pte_at(mm, addr, ptep, pte);
30}
31
32static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
33 unsigned long addr, pte_t *ptep)
34{
35 return ptep_get_and_clear(mm, addr, ptep);
36}
37
38static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
39 unsigned long addr, pte_t *ptep)
40{
41}
42
43static inline int huge_pte_none(pte_t pte)
44{
45 return pte_none(pte);
46}
47
48static inline pte_t huge_pte_wrprotect(pte_t pte)
49{
50 return pte_wrprotect(pte);
51}
52
53static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
54 unsigned long addr, pte_t *ptep)
55{
56 ptep_set_wrprotect(mm, addr, ptep);
57}
58
59static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
60 unsigned long addr, pte_t *ptep,
61 pte_t pte, int dirty)
62{
63 return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
64}
65
66static inline pte_t huge_ptep_get(pte_t *ptep)
67{
68 return *ptep;
69}
70
71static inline int arch_prepare_hugepage(struct page *page)
72{
73 return 0;
74}
75
76static inline void arch_release_hugepage(struct page *page)
77{
78}
79
80#endif /* _ASM_IA64_HUGETLB_H */
diff --git a/include/asm-ia64/hw_irq.h b/include/asm-ia64/hw_irq.h
deleted file mode 100644
index 5c99cbcb8a0..00000000000
--- a/include/asm-ia64/hw_irq.h
+++ /dev/null
@@ -1,192 +0,0 @@
1#ifndef _ASM_IA64_HW_IRQ_H
2#define _ASM_IA64_HW_IRQ_H
3
4/*
5 * Copyright (C) 2001-2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 */
8
9#include <linux/interrupt.h>
10#include <linux/sched.h>
11#include <linux/types.h>
12#include <linux/profile.h>
13
14#include <asm/machvec.h>
15#include <asm/ptrace.h>
16#include <asm/smp.h>
17
18#ifndef CONFIG_PARAVIRT
19typedef u8 ia64_vector;
20#else
21typedef u16 ia64_vector;
22#endif
23
24/*
25 * 0 special
26 *
27 * 1,3-14 are reserved from firmware
28 *
29 * 16-255 (vectored external interrupts) are available
30 *
31 * 15 spurious interrupt (see IVR)
32 *
33 * 16 lowest priority, 255 highest priority
34 *
35 * 15 classes of 16 interrupts each.
36 */
37#define IA64_MIN_VECTORED_IRQ 16
38#define IA64_MAX_VECTORED_IRQ 255
39#define IA64_NUM_VECTORS 256
40
41#define AUTO_ASSIGN -1
42
43#define IA64_SPURIOUS_INT_VECTOR 0x0f
44
45/*
46 * Vectors 0x10-0x1f are used for low priority interrupts, e.g. CMCI.
47 */
48#define IA64_CPEP_VECTOR 0x1c /* corrected platform error polling vector */
49#define IA64_CMCP_VECTOR 0x1d /* corrected machine-check polling vector */
50#define IA64_CPE_VECTOR 0x1e /* corrected platform error interrupt vector */
51#define IA64_CMC_VECTOR 0x1f /* corrected machine-check interrupt vector */
52/*
53 * Vectors 0x20-0x2f are reserved for legacy ISA IRQs.
54 * Use vectors 0x30-0xe7 as the default device vector range for ia64.
55 * Platforms may choose to reduce this range in platform_irq_setup, but the
56 * platform range must fall within
57 * [IA64_DEF_FIRST_DEVICE_VECTOR..IA64_DEF_LAST_DEVICE_VECTOR]
58 */
59extern int ia64_first_device_vector;
60extern int ia64_last_device_vector;
61
62#define IA64_DEF_FIRST_DEVICE_VECTOR 0x30
63#define IA64_DEF_LAST_DEVICE_VECTOR 0xe7
64#define IA64_FIRST_DEVICE_VECTOR ia64_first_device_vector
65#define IA64_LAST_DEVICE_VECTOR ia64_last_device_vector
66#define IA64_MAX_DEVICE_VECTORS (IA64_DEF_LAST_DEVICE_VECTOR - IA64_DEF_FIRST_DEVICE_VECTOR + 1)
67#define IA64_NUM_DEVICE_VECTORS (IA64_LAST_DEVICE_VECTOR - IA64_FIRST_DEVICE_VECTOR + 1)
68
69#define IA64_MCA_RENDEZ_VECTOR 0xe8 /* MCA rendez interrupt */
70#define IA64_PERFMON_VECTOR 0xee /* performance monitor interrupt vector */
71#define IA64_TIMER_VECTOR 0xef /* use highest-prio group 15 interrupt for timer */
72#define IA64_MCA_WAKEUP_VECTOR 0xf0 /* MCA wakeup (must be >MCA_RENDEZ_VECTOR) */
73#define IA64_IPI_LOCAL_TLB_FLUSH 0xfc /* SMP flush local TLB */
74#define IA64_IPI_RESCHEDULE 0xfd /* SMP reschedule */
75#define IA64_IPI_VECTOR 0xfe /* inter-processor interrupt vector */
76
77/* Used for encoding redirected irqs */
78
79#define IA64_IRQ_REDIRECTED (1 << 31)
80
81/* IA64 inter-cpu interrupt related definitions */
82
83#define IA64_IPI_DEFAULT_BASE_ADDR 0xfee00000
84
85/* Delivery modes for inter-cpu interrupts */
86enum {
87 IA64_IPI_DM_INT = 0x0, /* pend an external interrupt */
88 IA64_IPI_DM_PMI = 0x2, /* pend a PMI */
89 IA64_IPI_DM_NMI = 0x4, /* pend an NMI (vector 2) */
90 IA64_IPI_DM_INIT = 0x5, /* pend an INIT interrupt */
91 IA64_IPI_DM_EXTINT = 0x7, /* pend an 8259-compatible interrupt. */
92};
93
94extern __u8 isa_irq_to_vector_map[16];
95#define isa_irq_to_vector(x) isa_irq_to_vector_map[(x)]
96
97struct irq_cfg {
98 ia64_vector vector;
99 cpumask_t domain;
100 cpumask_t old_domain;
101 unsigned move_cleanup_count;
102 u8 move_in_progress : 1;
103};
104extern spinlock_t vector_lock;
105extern struct irq_cfg irq_cfg[NR_IRQS];
106#define irq_to_domain(x) irq_cfg[(x)].domain
107DECLARE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq);
108
109extern struct hw_interrupt_type irq_type_ia64_lsapic; /* CPU-internal interrupt controller */
110
111#ifdef CONFIG_PARAVIRT_GUEST
112#include <asm/paravirt.h>
113#else
114#define ia64_register_ipi ia64_native_register_ipi
115#define assign_irq_vector ia64_native_assign_irq_vector
116#define free_irq_vector ia64_native_free_irq_vector
117#define register_percpu_irq ia64_native_register_percpu_irq
118#define ia64_resend_irq ia64_native_resend_irq
119#endif
120
121extern void ia64_native_register_ipi(void);
122extern int bind_irq_vector(int irq, int vector, cpumask_t domain);
123extern int ia64_native_assign_irq_vector (int irq); /* allocate a free vector */
124extern void ia64_native_free_irq_vector (int vector);
125extern int reserve_irq_vector (int vector);
126extern void __setup_vector_irq(int cpu);
127extern void ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect);
128extern void ia64_native_register_percpu_irq (ia64_vector vec, struct irqaction *action);
129extern int check_irq_used (int irq);
130extern void destroy_and_reserve_irq (unsigned int irq);
131
132#if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG))
133extern int irq_prepare_move(int irq, int cpu);
134extern void irq_complete_move(unsigned int irq);
135#else
136static inline int irq_prepare_move(int irq, int cpu) { return 0; }
137static inline void irq_complete_move(unsigned int irq) {}
138#endif
139
140static inline void ia64_native_resend_irq(unsigned int vector)
141{
142 platform_send_ipi(smp_processor_id(), vector, IA64_IPI_DM_INT, 0);
143}
144
145/*
146 * Default implementations for the irq-descriptor API:
147 */
148
149extern irq_desc_t irq_desc[NR_IRQS];
150
151#ifndef CONFIG_IA64_GENERIC
152static inline ia64_vector __ia64_irq_to_vector(int irq)
153{
154 return irq_cfg[irq].vector;
155}
156
157static inline unsigned int
158__ia64_local_vector_to_irq (ia64_vector vec)
159{
160 return __get_cpu_var(vector_irq)[vec];
161}
162#endif
163
164/*
165 * Next follows the irq descriptor interface. On IA-64, each CPU supports 256 interrupt
166 * vectors. On smaller systems, there is a one-to-one correspondence between interrupt
167 * vectors and the Linux irq numbers. However, larger systems may have multiple interrupt
168 * domains meaning that the translation from vector number to irq number depends on the
169 * interrupt domain that a CPU belongs to. This API abstracts such platform-dependent
170 * differences and provides a uniform means to translate between vector and irq numbers
171 * and to obtain the irq descriptor for a given irq number.
172 */
173
174/* Extract the IA-64 vector that corresponds to IRQ. */
175static inline ia64_vector
176irq_to_vector (int irq)
177{
178 return platform_irq_to_vector(irq);
179}
180
181/*
182 * Convert the local IA-64 vector to the corresponding irq number. This translation is
183 * done in the context of the interrupt domain that the currently executing CPU belongs
184 * to.
185 */
186static inline unsigned int
187local_vector_to_irq (ia64_vector vec)
188{
189 return platform_local_vector_to_irq(vec);
190}
191
192#endif /* _ASM_IA64_HW_IRQ_H */
diff --git a/include/asm-ia64/ia32.h b/include/asm-ia64/ia32.h
deleted file mode 100644
index 2390ee145aa..00000000000
--- a/include/asm-ia64/ia32.h
+++ /dev/null
@@ -1,40 +0,0 @@
1#ifndef _ASM_IA64_IA32_H
2#define _ASM_IA64_IA32_H
3
4
5#include <asm/ptrace.h>
6#include <asm/signal.h>
7
8#define IA32_NR_syscalls 285 /* length of syscall table */
9#define IA32_PAGE_SHIFT 12 /* 4KB pages */
10
11#ifndef __ASSEMBLY__
12
13# ifdef CONFIG_IA32_SUPPORT
14
15#define IA32_PAGE_OFFSET 0xc0000000
16
17extern void ia32_cpu_init (void);
18extern void ia32_mem_init (void);
19extern void ia32_gdt_init (void);
20extern int ia32_exception (struct pt_regs *regs, unsigned long isr);
21extern int ia32_intercept (struct pt_regs *regs, unsigned long isr);
22extern int ia32_clone_tls (struct task_struct *child, struct pt_regs *childregs);
23
24# endif /* !CONFIG_IA32_SUPPORT */
25
26/* Declare this unconditionally, so we don't get warnings for unreachable code. */
27extern int ia32_setup_frame1 (int sig, struct k_sigaction *ka, siginfo_t *info,
28 sigset_t *set, struct pt_regs *regs);
29#if PAGE_SHIFT > IA32_PAGE_SHIFT
30extern int ia32_copy_ia64_partial_page_list(struct task_struct *,
31 unsigned long);
32extern void ia32_drop_ia64_partial_page_list(struct task_struct *);
33#else
34# define ia32_copy_ia64_partial_page_list(a1, a2) 0
35# define ia32_drop_ia64_partial_page_list(a1) do { ; } while (0)
36#endif
37
38#endif /* !__ASSEMBLY__ */
39
40#endif /* _ASM_IA64_IA32_H */
diff --git a/include/asm-ia64/ia64regs.h b/include/asm-ia64/ia64regs.h
deleted file mode 100644
index 1757f1c11ad..00000000000
--- a/include/asm-ia64/ia64regs.h
+++ /dev/null
@@ -1,100 +0,0 @@
1/*
2 * Copyright (C) 2002,2003 Intel Corp.
3 * Jun Nakajima <jun.nakajima@intel.com>
4 * Suresh Siddha <suresh.b.siddha@intel.com>
5 */
6
7#ifndef _ASM_IA64_IA64REGS_H
8#define _ASM_IA64_IA64REGS_H
9
10/*
11 * Register Names for getreg() and setreg().
12 *
13 * The "magic" numbers happen to match the values used by the Intel compiler's
14 * getreg()/setreg() intrinsics.
15 */
16
17/* Special Registers */
18
19#define _IA64_REG_IP 1016 /* getreg only */
20#define _IA64_REG_PSR 1019
21#define _IA64_REG_PSR_L 1019
22
23/* General Integer Registers */
24
25#define _IA64_REG_GP 1025 /* R1 */
26#define _IA64_REG_R8 1032 /* R8 */
27#define _IA64_REG_R9 1033 /* R9 */
28#define _IA64_REG_SP 1036 /* R12 */
29#define _IA64_REG_TP 1037 /* R13 */
30
31/* Application Registers */
32
33#define _IA64_REG_AR_KR0 3072
34#define _IA64_REG_AR_KR1 3073
35#define _IA64_REG_AR_KR2 3074
36#define _IA64_REG_AR_KR3 3075
37#define _IA64_REG_AR_KR4 3076
38#define _IA64_REG_AR_KR5 3077
39#define _IA64_REG_AR_KR6 3078
40#define _IA64_REG_AR_KR7 3079
41#define _IA64_REG_AR_RSC 3088
42#define _IA64_REG_AR_BSP 3089
43#define _IA64_REG_AR_BSPSTORE 3090
44#define _IA64_REG_AR_RNAT 3091
45#define _IA64_REG_AR_FCR 3093
46#define _IA64_REG_AR_EFLAG 3096
47#define _IA64_REG_AR_CSD 3097
48#define _IA64_REG_AR_SSD 3098
49#define _IA64_REG_AR_CFLAG 3099
50#define _IA64_REG_AR_FSR 3100
51#define _IA64_REG_AR_FIR 3101
52#define _IA64_REG_AR_FDR 3102
53#define _IA64_REG_AR_CCV 3104
54#define _IA64_REG_AR_UNAT 3108
55#define _IA64_REG_AR_FPSR 3112
56#define _IA64_REG_AR_ITC 3116
57#define _IA64_REG_AR_PFS 3136
58#define _IA64_REG_AR_LC 3137
59#define _IA64_REG_AR_EC 3138
60
61/* Control Registers */
62
63#define _IA64_REG_CR_DCR 4096
64#define _IA64_REG_CR_ITM 4097
65#define _IA64_REG_CR_IVA 4098
66#define _IA64_REG_CR_PTA 4104
67#define _IA64_REG_CR_IPSR 4112
68#define _IA64_REG_CR_ISR 4113
69#define _IA64_REG_CR_IIP 4115
70#define _IA64_REG_CR_IFA 4116
71#define _IA64_REG_CR_ITIR 4117
72#define _IA64_REG_CR_IIPA 4118
73#define _IA64_REG_CR_IFS 4119
74#define _IA64_REG_CR_IIM 4120
75#define _IA64_REG_CR_IHA 4121
76#define _IA64_REG_CR_LID 4160
77#define _IA64_REG_CR_IVR 4161 /* getreg only */
78#define _IA64_REG_CR_TPR 4162
79#define _IA64_REG_CR_EOI 4163
80#define _IA64_REG_CR_IRR0 4164 /* getreg only */
81#define _IA64_REG_CR_IRR1 4165 /* getreg only */
82#define _IA64_REG_CR_IRR2 4166 /* getreg only */
83#define _IA64_REG_CR_IRR3 4167 /* getreg only */
84#define _IA64_REG_CR_ITV 4168
85#define _IA64_REG_CR_PMV 4169
86#define _IA64_REG_CR_CMCV 4170
87#define _IA64_REG_CR_LRR0 4176
88#define _IA64_REG_CR_LRR1 4177
89
90/* Indirect Registers for getindreg() and setindreg() */
91
92#define _IA64_REG_INDR_CPUID 9000 /* getindreg only */
93#define _IA64_REG_INDR_DBR 9001
94#define _IA64_REG_INDR_IBR 9002
95#define _IA64_REG_INDR_PKR 9003
96#define _IA64_REG_INDR_PMC 9004
97#define _IA64_REG_INDR_PMD 9005
98#define _IA64_REG_INDR_RR 9006
99
100#endif /* _ASM_IA64_IA64REGS_H */
diff --git a/include/asm-ia64/intel_intrin.h b/include/asm-ia64/intel_intrin.h
deleted file mode 100644
index 53cec577558..00000000000
--- a/include/asm-ia64/intel_intrin.h
+++ /dev/null
@@ -1,161 +0,0 @@
1#ifndef _ASM_IA64_INTEL_INTRIN_H
2#define _ASM_IA64_INTEL_INTRIN_H
3/*
4 * Intel Compiler Intrinsics
5 *
6 * Copyright (C) 2002,2003 Jun Nakajima <jun.nakajima@intel.com>
7 * Copyright (C) 2002,2003 Suresh Siddha <suresh.b.siddha@intel.com>
8 * Copyright (C) 2005,2006 Hongjiu Lu <hongjiu.lu@intel.com>
9 *
10 */
11#include <ia64intrin.h>
12
13#define ia64_barrier() __memory_barrier()
14
15#define ia64_stop() /* Nothing: As of now stop bit is generated for each
16 * intrinsic
17 */
18
19#define ia64_native_getreg __getReg
20#define ia64_native_setreg __setReg
21
22#define ia64_hint __hint
23#define ia64_hint_pause __hint_pause
24
25#define ia64_mux1_brcst _m64_mux1_brcst
26#define ia64_mux1_mix _m64_mux1_mix
27#define ia64_mux1_shuf _m64_mux1_shuf
28#define ia64_mux1_alt _m64_mux1_alt
29#define ia64_mux1_rev _m64_mux1_rev
30
31#define ia64_mux1(x,v) _m_to_int64(_m64_mux1(_m_from_int64(x), (v)))
32#define ia64_popcnt _m64_popcnt
33#define ia64_getf_exp __getf_exp
34#define ia64_shrp _m64_shrp
35
36#define ia64_tpa __tpa
37#define ia64_invala __invala
38#define ia64_invala_gr __invala_gr
39#define ia64_invala_fr __invala_fr
40#define ia64_nop __nop
41#define ia64_sum __sum
42#define ia64_native_ssm __ssm
43#define ia64_rum __rum
44#define ia64_native_rsm __rsm
45#define ia64_native_fc __fc
46
47#define ia64_ldfs __ldfs
48#define ia64_ldfd __ldfd
49#define ia64_ldfe __ldfe
50#define ia64_ldf8 __ldf8
51#define ia64_ldf_fill __ldf_fill
52
53#define ia64_stfs __stfs
54#define ia64_stfd __stfd
55#define ia64_stfe __stfe
56#define ia64_stf8 __stf8
57#define ia64_stf_spill __stf_spill
58
59#define ia64_mf __mf
60#define ia64_mfa __mfa
61
62#define ia64_fetchadd4_acq __fetchadd4_acq
63#define ia64_fetchadd4_rel __fetchadd4_rel
64#define ia64_fetchadd8_acq __fetchadd8_acq
65#define ia64_fetchadd8_rel __fetchadd8_rel
66
67#define ia64_xchg1 _InterlockedExchange8
68#define ia64_xchg2 _InterlockedExchange16
69#define ia64_xchg4 _InterlockedExchange
70#define ia64_xchg8 _InterlockedExchange64
71
72#define ia64_cmpxchg1_rel _InterlockedCompareExchange8_rel
73#define ia64_cmpxchg1_acq _InterlockedCompareExchange8_acq
74#define ia64_cmpxchg2_rel _InterlockedCompareExchange16_rel
75#define ia64_cmpxchg2_acq _InterlockedCompareExchange16_acq
76#define ia64_cmpxchg4_rel _InterlockedCompareExchange_rel
77#define ia64_cmpxchg4_acq _InterlockedCompareExchange_acq
78#define ia64_cmpxchg8_rel _InterlockedCompareExchange64_rel
79#define ia64_cmpxchg8_acq _InterlockedCompareExchange64_acq
80
81#define __ia64_set_dbr(index, val) \
82 __setIndReg(_IA64_REG_INDR_DBR, index, val)
83#define ia64_set_ibr(index, val) \
84 __setIndReg(_IA64_REG_INDR_IBR, index, val)
85#define ia64_set_pkr(index, val) \
86 __setIndReg(_IA64_REG_INDR_PKR, index, val)
87#define ia64_set_pmc(index, val) \
88 __setIndReg(_IA64_REG_INDR_PMC, index, val)
89#define ia64_set_pmd(index, val) \
90 __setIndReg(_IA64_REG_INDR_PMD, index, val)
91#define ia64_native_set_rr(index, val) \
92 __setIndReg(_IA64_REG_INDR_RR, index, val)
93
94#define ia64_native_get_cpuid(index) \
95 __getIndReg(_IA64_REG_INDR_CPUID, index)
96#define __ia64_get_dbr(index) __getIndReg(_IA64_REG_INDR_DBR, index)
97#define ia64_get_ibr(index) __getIndReg(_IA64_REG_INDR_IBR, index)
98#define ia64_get_pkr(index) __getIndReg(_IA64_REG_INDR_PKR, index)
99#define ia64_get_pmc(index) __getIndReg(_IA64_REG_INDR_PMC, index)
100#define ia64_native_get_pmd(index) __getIndReg(_IA64_REG_INDR_PMD, index)
101#define ia64_native_get_rr(index) __getIndReg(_IA64_REG_INDR_RR, index)
102
103#define ia64_srlz_d __dsrlz
104#define ia64_srlz_i __isrlz
105
106#define ia64_dv_serialize_data()
107#define ia64_dv_serialize_instruction()
108
109#define ia64_st1_rel __st1_rel
110#define ia64_st2_rel __st2_rel
111#define ia64_st4_rel __st4_rel
112#define ia64_st8_rel __st8_rel
113
114/* FIXME: need st4.rel.nta intrinsic */
115#define ia64_st4_rel_nta __st4_rel
116
117#define ia64_ld1_acq __ld1_acq
118#define ia64_ld2_acq __ld2_acq
119#define ia64_ld4_acq __ld4_acq
120#define ia64_ld8_acq __ld8_acq
121
122#define ia64_sync_i __synci
123#define ia64_native_thash __thash
124#define ia64_native_ttag __ttag
125#define ia64_itcd __itcd
126#define ia64_itci __itci
127#define ia64_itrd __itrd
128#define ia64_itri __itri
129#define ia64_ptce __ptce
130#define ia64_ptcl __ptcl
131#define ia64_native_ptcg __ptcg
132#define ia64_native_ptcga __ptcga
133#define ia64_ptri __ptri
134#define ia64_ptrd __ptrd
135#define ia64_dep_mi _m64_dep_mi
136
137/* Values for lfhint in __lfetch and __lfetch_fault */
138
139#define ia64_lfhint_none __lfhint_none
140#define ia64_lfhint_nt1 __lfhint_nt1
141#define ia64_lfhint_nt2 __lfhint_nt2
142#define ia64_lfhint_nta __lfhint_nta
143
144#define ia64_lfetch __lfetch
145#define ia64_lfetch_excl __lfetch_excl
146#define ia64_lfetch_fault __lfetch_fault
147#define ia64_lfetch_fault_excl __lfetch_fault_excl
148
149#define ia64_native_intrin_local_irq_restore(x) \
150do { \
151 if ((x) != 0) { \
152 ia64_native_ssm(IA64_PSR_I); \
153 ia64_srlz_d(); \
154 } else { \
155 ia64_native_rsm(IA64_PSR_I); \
156 } \
157} while (0)
158
159#define __builtin_trap() __break(0);
160
161#endif /* _ASM_IA64_INTEL_INTRIN_H */
diff --git a/include/asm-ia64/intrinsics.h b/include/asm-ia64/intrinsics.h
deleted file mode 100644
index 47d686dba1e..00000000000
--- a/include/asm-ia64/intrinsics.h
+++ /dev/null
@@ -1,241 +0,0 @@
1#ifndef _ASM_IA64_INTRINSICS_H
2#define _ASM_IA64_INTRINSICS_H
3
4/*
5 * Compiler-dependent intrinsics.
6 *
7 * Copyright (C) 2002-2003 Hewlett-Packard Co
8 * David Mosberger-Tang <davidm@hpl.hp.com>
9 */
10
11#ifndef __ASSEMBLY__
12
13/* include compiler specific intrinsics */
14#include <asm/ia64regs.h>
15#ifdef __INTEL_COMPILER
16# include <asm/intel_intrin.h>
17#else
18# include <asm/gcc_intrin.h>
19#endif
20
21#define ia64_native_get_psr_i() (ia64_native_getreg(_IA64_REG_PSR) & IA64_PSR_I)
22
23#define ia64_native_set_rr0_to_rr4(val0, val1, val2, val3, val4) \
24do { \
25 ia64_native_set_rr(0x0000000000000000UL, (val0)); \
26 ia64_native_set_rr(0x2000000000000000UL, (val1)); \
27 ia64_native_set_rr(0x4000000000000000UL, (val2)); \
28 ia64_native_set_rr(0x6000000000000000UL, (val3)); \
29 ia64_native_set_rr(0x8000000000000000UL, (val4)); \
30} while (0)
31
32/*
33 * Force an unresolved reference if someone tries to use
34 * ia64_fetch_and_add() with a bad value.
35 */
36extern unsigned long __bad_size_for_ia64_fetch_and_add (void);
37extern unsigned long __bad_increment_for_ia64_fetch_and_add (void);
38
39#define IA64_FETCHADD(tmp,v,n,sz,sem) \
40({ \
41 switch (sz) { \
42 case 4: \
43 tmp = ia64_fetchadd4_##sem((unsigned int *) v, n); \
44 break; \
45 \
46 case 8: \
47 tmp = ia64_fetchadd8_##sem((unsigned long *) v, n); \
48 break; \
49 \
50 default: \
51 __bad_size_for_ia64_fetch_and_add(); \
52 } \
53})
54
55#define ia64_fetchadd(i,v,sem) \
56({ \
57 __u64 _tmp; \
58 volatile __typeof__(*(v)) *_v = (v); \
59 /* Can't use a switch () here: gcc isn't always smart enough for that... */ \
60 if ((i) == -16) \
61 IA64_FETCHADD(_tmp, _v, -16, sizeof(*(v)), sem); \
62 else if ((i) == -8) \
63 IA64_FETCHADD(_tmp, _v, -8, sizeof(*(v)), sem); \
64 else if ((i) == -4) \
65 IA64_FETCHADD(_tmp, _v, -4, sizeof(*(v)), sem); \
66 else if ((i) == -1) \
67 IA64_FETCHADD(_tmp, _v, -1, sizeof(*(v)), sem); \
68 else if ((i) == 1) \
69 IA64_FETCHADD(_tmp, _v, 1, sizeof(*(v)), sem); \
70 else if ((i) == 4) \
71 IA64_FETCHADD(_tmp, _v, 4, sizeof(*(v)), sem); \
72 else if ((i) == 8) \
73 IA64_FETCHADD(_tmp, _v, 8, sizeof(*(v)), sem); \
74 else if ((i) == 16) \
75 IA64_FETCHADD(_tmp, _v, 16, sizeof(*(v)), sem); \
76 else \
77 _tmp = __bad_increment_for_ia64_fetch_and_add(); \
78 (__typeof__(*(v))) (_tmp); /* return old value */ \
79})
80
81#define ia64_fetch_and_add(i,v) (ia64_fetchadd(i, v, rel) + (i)) /* return new value */
82
83/*
84 * This function doesn't exist, so you'll get a linker error if
85 * something tries to do an invalid xchg().
86 */
87extern void ia64_xchg_called_with_bad_pointer (void);
88
89#define __xchg(x,ptr,size) \
90({ \
91 unsigned long __xchg_result; \
92 \
93 switch (size) { \
94 case 1: \
95 __xchg_result = ia64_xchg1((__u8 *)ptr, x); \
96 break; \
97 \
98 case 2: \
99 __xchg_result = ia64_xchg2((__u16 *)ptr, x); \
100 break; \
101 \
102 case 4: \
103 __xchg_result = ia64_xchg4((__u32 *)ptr, x); \
104 break; \
105 \
106 case 8: \
107 __xchg_result = ia64_xchg8((__u64 *)ptr, x); \
108 break; \
109 default: \
110 ia64_xchg_called_with_bad_pointer(); \
111 } \
112 __xchg_result; \
113})
114
115#define xchg(ptr,x) \
116 ((__typeof__(*(ptr))) __xchg ((unsigned long) (x), (ptr), sizeof(*(ptr))))
117
118/*
119 * Atomic compare and exchange. Compare OLD with MEM, if identical,
120 * store NEW in MEM. Return the initial value in MEM. Success is
121 * indicated by comparing RETURN with OLD.
122 */
123
124#define __HAVE_ARCH_CMPXCHG 1
125
126/*
127 * This function doesn't exist, so you'll get a linker error
128 * if something tries to do an invalid cmpxchg().
129 */
130extern long ia64_cmpxchg_called_with_bad_pointer (void);
131
132#define ia64_cmpxchg(sem,ptr,old,new,size) \
133({ \
134 __u64 _o_, _r_; \
135 \
136 switch (size) { \
137 case 1: _o_ = (__u8 ) (long) (old); break; \
138 case 2: _o_ = (__u16) (long) (old); break; \
139 case 4: _o_ = (__u32) (long) (old); break; \
140 case 8: _o_ = (__u64) (long) (old); break; \
141 default: break; \
142 } \
143 switch (size) { \
144 case 1: \
145 _r_ = ia64_cmpxchg1_##sem((__u8 *) ptr, new, _o_); \
146 break; \
147 \
148 case 2: \
149 _r_ = ia64_cmpxchg2_##sem((__u16 *) ptr, new, _o_); \
150 break; \
151 \
152 case 4: \
153 _r_ = ia64_cmpxchg4_##sem((__u32 *) ptr, new, _o_); \
154 break; \
155 \
156 case 8: \
157 _r_ = ia64_cmpxchg8_##sem((__u64 *) ptr, new, _o_); \
158 break; \
159 \
160 default: \
161 _r_ = ia64_cmpxchg_called_with_bad_pointer(); \
162 break; \
163 } \
164 (__typeof__(old)) _r_; \
165})
166
167#define cmpxchg_acq(ptr, o, n) \
168 ia64_cmpxchg(acq, (ptr), (o), (n), sizeof(*(ptr)))
169#define cmpxchg_rel(ptr, o, n) \
170 ia64_cmpxchg(rel, (ptr), (o), (n), sizeof(*(ptr)))
171
172/* for compatibility with other platforms: */
173#define cmpxchg(ptr, o, n) cmpxchg_acq((ptr), (o), (n))
174#define cmpxchg64(ptr, o, n) cmpxchg_acq((ptr), (o), (n))
175
176#define cmpxchg_local cmpxchg
177#define cmpxchg64_local cmpxchg64
178
179#ifdef CONFIG_IA64_DEBUG_CMPXCHG
180# define CMPXCHG_BUGCHECK_DECL int _cmpxchg_bugcheck_count = 128;
181# define CMPXCHG_BUGCHECK(v) \
182 do { \
183 if (_cmpxchg_bugcheck_count-- <= 0) { \
184 void *ip; \
185 extern int printk(const char *fmt, ...); \
186 ip = (void *) ia64_getreg(_IA64_REG_IP); \
187 printk("CMPXCHG_BUGCHECK: stuck at %p on word %p\n", ip, (v)); \
188 break; \
189 } \
190 } while (0)
191#else /* !CONFIG_IA64_DEBUG_CMPXCHG */
192# define CMPXCHG_BUGCHECK_DECL
193# define CMPXCHG_BUGCHECK(v)
194#endif /* !CONFIG_IA64_DEBUG_CMPXCHG */
195
196#endif
197
198#ifdef __KERNEL__
199#include <asm/paravirt_privop.h>
200#endif
201
202#ifndef __ASSEMBLY__
203#if defined(CONFIG_PARAVIRT) && defined(__KERNEL__)
204#define IA64_INTRINSIC_API(name) pv_cpu_ops.name
205#define IA64_INTRINSIC_MACRO(name) paravirt_ ## name
206#else
207#define IA64_INTRINSIC_API(name) ia64_native_ ## name
208#define IA64_INTRINSIC_MACRO(name) ia64_native_ ## name
209#endif
210
211/************************************************/
212/* Instructions paravirtualized for correctness */
213/************************************************/
214/* fc, thash, get_cpuid, get_pmd, get_eflags, set_eflags */
215/* Note that "ttag" and "cover" are also privilege-sensitive; "ttag"
216 * is not currently used (though it may be in a long-format VHPT system!)
217 */
218#define ia64_fc IA64_INTRINSIC_API(fc)
219#define ia64_thash IA64_INTRINSIC_API(thash)
220#define ia64_get_cpuid IA64_INTRINSIC_API(get_cpuid)
221#define ia64_get_pmd IA64_INTRINSIC_API(get_pmd)
222
223
224/************************************************/
225/* Instructions paravirtualized for performance */
226/************************************************/
227#define ia64_ssm IA64_INTRINSIC_MACRO(ssm)
228#define ia64_rsm IA64_INTRINSIC_MACRO(rsm)
229#define ia64_getreg IA64_INTRINSIC_API(getreg)
230#define ia64_setreg IA64_INTRINSIC_API(setreg)
231#define ia64_set_rr IA64_INTRINSIC_API(set_rr)
232#define ia64_get_rr IA64_INTRINSIC_API(get_rr)
233#define ia64_ptcga IA64_INTRINSIC_API(ptcga)
234#define ia64_get_psr_i IA64_INTRINSIC_API(get_psr_i)
235#define ia64_intrin_local_irq_restore \
236 IA64_INTRINSIC_API(intrin_local_irq_restore)
237#define ia64_set_rr0_to_rr4 IA64_INTRINSIC_API(set_rr0_to_rr4)
238
239#endif /* !__ASSEMBLY__ */
240
241#endif /* _ASM_IA64_INTRINSICS_H */
diff --git a/include/asm-ia64/io.h b/include/asm-ia64/io.h
deleted file mode 100644
index 260a85ac9d6..00000000000
--- a/include/asm-ia64/io.h
+++ /dev/null
@@ -1,459 +0,0 @@
1#ifndef _ASM_IA64_IO_H
2#define _ASM_IA64_IO_H
3
4/*
5 * This file contains the definitions for the emulated IO instructions
6 * inb/inw/inl/outb/outw/outl and the "string versions" of the same
7 * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
8 * versions of the single-IO instructions (inb_p/inw_p/..).
9 *
10 * This file is not meant to be obfuscating: it's just complicated to
11 * (a) handle it all in a way that makes gcc able to optimize it as
12 * well as possible and (b) trying to avoid writing the same thing
13 * over and over again with slight variations and possibly making a
14 * mistake somewhere.
15 *
16 * Copyright (C) 1998-2003 Hewlett-Packard Co
17 * David Mosberger-Tang <davidm@hpl.hp.com>
18 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
19 * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
20 */
21
22/* We don't use IO slowdowns on the ia64, but.. */
23#define __SLOW_DOWN_IO do { } while (0)
24#define SLOW_DOWN_IO do { } while (0)
25
26#define __IA64_UNCACHED_OFFSET RGN_BASE(RGN_UNCACHED)
27
28/*
29 * The legacy I/O space defined by the ia64 architecture supports only 65536 ports, but
30 * large machines may have multiple other I/O spaces so we can't place any a priori limit
31 * on IO_SPACE_LIMIT. These additional spaces are described in ACPI.
32 */
33#define IO_SPACE_LIMIT 0xffffffffffffffffUL
34
35#define MAX_IO_SPACES_BITS 8
36#define MAX_IO_SPACES (1UL << MAX_IO_SPACES_BITS)
37#define IO_SPACE_BITS 24
38#define IO_SPACE_SIZE (1UL << IO_SPACE_BITS)
39
40#define IO_SPACE_NR(port) ((port) >> IO_SPACE_BITS)
41#define IO_SPACE_BASE(space) ((space) << IO_SPACE_BITS)
42#define IO_SPACE_PORT(port) ((port) & (IO_SPACE_SIZE - 1))
43
44#define IO_SPACE_SPARSE_ENCODING(p) ((((p) >> 2) << 12) | ((p) & 0xfff))
45
46struct io_space {
47 unsigned long mmio_base; /* base in MMIO space */
48 int sparse;
49};
50
51extern struct io_space io_space[];
52extern unsigned int num_io_spaces;
53
54# ifdef __KERNEL__
55
56/*
57 * All MMIO iomem cookies are in region 6; anything less is a PIO cookie:
58 * 0xCxxxxxxxxxxxxxxx MMIO cookie (return from ioremap)
59 * 0x000000001SPPPPPP PIO cookie (S=space number, P..P=port)
60 *
61 * ioread/writeX() uses the leading 1 in PIO cookies (PIO_OFFSET) to catch
62 * code that uses bare port numbers without the prerequisite pci_iomap().
63 */
64#define PIO_OFFSET (1UL << (MAX_IO_SPACES_BITS + IO_SPACE_BITS))
65#define PIO_MASK (PIO_OFFSET - 1)
66#define PIO_RESERVED __IA64_UNCACHED_OFFSET
67#define HAVE_ARCH_PIO_SIZE
68
69#include <asm/intrinsics.h>
70#include <asm/machvec.h>
71#include <asm/page.h>
72#include <asm/system.h>
73#include <asm-generic/iomap.h>
74
75/*
76 * Change virtual addresses to physical addresses and vv.
77 */
78static inline unsigned long
79virt_to_phys (volatile void *address)
80{
81 return (unsigned long) address - PAGE_OFFSET;
82}
83
84static inline void*
85phys_to_virt (unsigned long address)
86{
87 return (void *) (address + PAGE_OFFSET);
88}
89
90#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
91extern u64 kern_mem_attribute (unsigned long phys_addr, unsigned long size);
92extern int valid_phys_addr_range (unsigned long addr, size_t count); /* efi.c */
93extern int valid_mmap_phys_addr_range (unsigned long pfn, size_t count);
94
95/*
96 * The following two macros are deprecated and scheduled for removal.
97 * Please use the PCI-DMA interface defined in <asm/pci.h> instead.
98 */
99#define bus_to_virt phys_to_virt
100#define virt_to_bus virt_to_phys
101#define page_to_bus page_to_phys
102
103# endif /* KERNEL */
104
105/*
106 * Memory fence w/accept. This should never be used in code that is
107 * not IA-64 specific.
108 */
109#define __ia64_mf_a() ia64_mfa()
110
111/**
112 * ___ia64_mmiowb - I/O write barrier
113 *
114 * Ensure ordering of I/O space writes. This will make sure that writes
115 * following the barrier will arrive after all previous writes. For most
116 * ia64 platforms, this is a simple 'mf.a' instruction.
117 *
118 * See Documentation/DocBook/deviceiobook.tmpl for more information.
119 */
120static inline void ___ia64_mmiowb(void)
121{
122 ia64_mfa();
123}
124
125static inline void*
126__ia64_mk_io_addr (unsigned long port)
127{
128 struct io_space *space;
129 unsigned long offset;
130
131 space = &io_space[IO_SPACE_NR(port)];
132 port = IO_SPACE_PORT(port);
133 if (space->sparse)
134 offset = IO_SPACE_SPARSE_ENCODING(port);
135 else
136 offset = port;
137
138 return (void *) (space->mmio_base | offset);
139}
140
141#define __ia64_inb ___ia64_inb
142#define __ia64_inw ___ia64_inw
143#define __ia64_inl ___ia64_inl
144#define __ia64_outb ___ia64_outb
145#define __ia64_outw ___ia64_outw
146#define __ia64_outl ___ia64_outl
147#define __ia64_readb ___ia64_readb
148#define __ia64_readw ___ia64_readw
149#define __ia64_readl ___ia64_readl
150#define __ia64_readq ___ia64_readq
151#define __ia64_readb_relaxed ___ia64_readb
152#define __ia64_readw_relaxed ___ia64_readw
153#define __ia64_readl_relaxed ___ia64_readl
154#define __ia64_readq_relaxed ___ia64_readq
155#define __ia64_writeb ___ia64_writeb
156#define __ia64_writew ___ia64_writew
157#define __ia64_writel ___ia64_writel
158#define __ia64_writeq ___ia64_writeq
159#define __ia64_mmiowb ___ia64_mmiowb
160
161/*
162 * For the in/out routines, we need to do "mf.a" _after_ doing the I/O access to ensure
163 * that the access has completed before executing other I/O accesses. Since we're doing
164 * the accesses through an uncachable (UC) translation, the CPU will execute them in
165 * program order. However, we still need to tell the compiler not to shuffle them around
166 * during optimization, which is why we use "volatile" pointers.
167 */
168
169static inline unsigned int
170___ia64_inb (unsigned long port)
171{
172 volatile unsigned char *addr = __ia64_mk_io_addr(port);
173 unsigned char ret;
174
175 ret = *addr;
176 __ia64_mf_a();
177 return ret;
178}
179
180static inline unsigned int
181___ia64_inw (unsigned long port)
182{
183 volatile unsigned short *addr = __ia64_mk_io_addr(port);
184 unsigned short ret;
185
186 ret = *addr;
187 __ia64_mf_a();
188 return ret;
189}
190
191static inline unsigned int
192___ia64_inl (unsigned long port)
193{
194 volatile unsigned int *addr = __ia64_mk_io_addr(port);
195 unsigned int ret;
196
197 ret = *addr;
198 __ia64_mf_a();
199 return ret;
200}
201
202static inline void
203___ia64_outb (unsigned char val, unsigned long port)
204{
205 volatile unsigned char *addr = __ia64_mk_io_addr(port);
206
207 *addr = val;
208 __ia64_mf_a();
209}
210
211static inline void
212___ia64_outw (unsigned short val, unsigned long port)
213{
214 volatile unsigned short *addr = __ia64_mk_io_addr(port);
215
216 *addr = val;
217 __ia64_mf_a();
218}
219
220static inline void
221___ia64_outl (unsigned int val, unsigned long port)
222{
223 volatile unsigned int *addr = __ia64_mk_io_addr(port);
224
225 *addr = val;
226 __ia64_mf_a();
227}
228
229static inline void
230__insb (unsigned long port, void *dst, unsigned long count)
231{
232 unsigned char *dp = dst;
233
234 while (count--)
235 *dp++ = platform_inb(port);
236}
237
238static inline void
239__insw (unsigned long port, void *dst, unsigned long count)
240{
241 unsigned short *dp = dst;
242
243 while (count--)
244 *dp++ = platform_inw(port);
245}
246
247static inline void
248__insl (unsigned long port, void *dst, unsigned long count)
249{
250 unsigned int *dp = dst;
251
252 while (count--)
253 *dp++ = platform_inl(port);
254}
255
256static inline void
257__outsb (unsigned long port, const void *src, unsigned long count)
258{
259 const unsigned char *sp = src;
260
261 while (count--)
262 platform_outb(*sp++, port);
263}
264
265static inline void
266__outsw (unsigned long port, const void *src, unsigned long count)
267{
268 const unsigned short *sp = src;
269
270 while (count--)
271 platform_outw(*sp++, port);
272}
273
274static inline void
275__outsl (unsigned long port, const void *src, unsigned long count)
276{
277 const unsigned int *sp = src;
278
279 while (count--)
280 platform_outl(*sp++, port);
281}
282
283/*
284 * Unfortunately, some platforms are broken and do not follow the IA-64 architecture
285 * specification regarding legacy I/O support. Thus, we have to make these operations
286 * platform dependent...
287 */
288#define __inb platform_inb
289#define __inw platform_inw
290#define __inl platform_inl
291#define __outb platform_outb
292#define __outw platform_outw
293#define __outl platform_outl
294#define __mmiowb platform_mmiowb
295
296#define inb(p) __inb(p)
297#define inw(p) __inw(p)
298#define inl(p) __inl(p)
299#define insb(p,d,c) __insb(p,d,c)
300#define insw(p,d,c) __insw(p,d,c)
301#define insl(p,d,c) __insl(p,d,c)
302#define outb(v,p) __outb(v,p)
303#define outw(v,p) __outw(v,p)
304#define outl(v,p) __outl(v,p)
305#define outsb(p,s,c) __outsb(p,s,c)
306#define outsw(p,s,c) __outsw(p,s,c)
307#define outsl(p,s,c) __outsl(p,s,c)
308#define mmiowb() __mmiowb()
309
310/*
311 * The address passed to these functions are ioremap()ped already.
312 *
313 * We need these to be machine vectors since some platforms don't provide
314 * DMA coherence via PIO reads (PCI drivers and the spec imply that this is
315 * a good idea). Writes are ok though for all existing ia64 platforms (and
316 * hopefully it'll stay that way).
317 */
318static inline unsigned char
319___ia64_readb (const volatile void __iomem *addr)
320{
321 return *(volatile unsigned char __force *)addr;
322}
323
324static inline unsigned short
325___ia64_readw (const volatile void __iomem *addr)
326{
327 return *(volatile unsigned short __force *)addr;
328}
329
330static inline unsigned int
331___ia64_readl (const volatile void __iomem *addr)
332{
333 return *(volatile unsigned int __force *) addr;
334}
335
336static inline unsigned long
337___ia64_readq (const volatile void __iomem *addr)
338{
339 return *(volatile unsigned long __force *) addr;
340}
341
342static inline void
343__writeb (unsigned char val, volatile void __iomem *addr)
344{
345 *(volatile unsigned char __force *) addr = val;
346}
347
348static inline void
349__writew (unsigned short val, volatile void __iomem *addr)
350{
351 *(volatile unsigned short __force *) addr = val;
352}
353
354static inline void
355__writel (unsigned int val, volatile void __iomem *addr)
356{
357 *(volatile unsigned int __force *) addr = val;
358}
359
360static inline void
361__writeq (unsigned long val, volatile void __iomem *addr)
362{
363 *(volatile unsigned long __force *) addr = val;
364}
365
366#define __readb platform_readb
367#define __readw platform_readw
368#define __readl platform_readl
369#define __readq platform_readq
370#define __readb_relaxed platform_readb_relaxed
371#define __readw_relaxed platform_readw_relaxed
372#define __readl_relaxed platform_readl_relaxed
373#define __readq_relaxed platform_readq_relaxed
374
375#define readb(a) __readb((a))
376#define readw(a) __readw((a))
377#define readl(a) __readl((a))
378#define readq(a) __readq((a))
379#define readb_relaxed(a) __readb_relaxed((a))
380#define readw_relaxed(a) __readw_relaxed((a))
381#define readl_relaxed(a) __readl_relaxed((a))
382#define readq_relaxed(a) __readq_relaxed((a))
383#define __raw_readb readb
384#define __raw_readw readw
385#define __raw_readl readl
386#define __raw_readq readq
387#define __raw_readb_relaxed readb_relaxed
388#define __raw_readw_relaxed readw_relaxed
389#define __raw_readl_relaxed readl_relaxed
390#define __raw_readq_relaxed readq_relaxed
391#define writeb(v,a) __writeb((v), (a))
392#define writew(v,a) __writew((v), (a))
393#define writel(v,a) __writel((v), (a))
394#define writeq(v,a) __writeq((v), (a))
395#define __raw_writeb writeb
396#define __raw_writew writew
397#define __raw_writel writel
398#define __raw_writeq writeq
399
400#ifndef inb_p
401# define inb_p inb
402#endif
403#ifndef inw_p
404# define inw_p inw
405#endif
406#ifndef inl_p
407# define inl_p inl
408#endif
409
410#ifndef outb_p
411# define outb_p outb
412#endif
413#ifndef outw_p
414# define outw_p outw
415#endif
416#ifndef outl_p
417# define outl_p outl
418#endif
419
420# ifdef __KERNEL__
421
422extern void __iomem * ioremap(unsigned long offset, unsigned long size);
423extern void __iomem * ioremap_nocache (unsigned long offset, unsigned long size);
424extern void iounmap (volatile void __iomem *addr);
425
426/*
427 * String version of IO memory access ops:
428 */
429extern void memcpy_fromio(void *dst, const volatile void __iomem *src, long n);
430extern void memcpy_toio(volatile void __iomem *dst, const void *src, long n);
431extern void memset_io(volatile void __iomem *s, int c, long n);
432
433# endif /* __KERNEL__ */
434
435/*
436 * Enabling BIO_VMERGE_BOUNDARY forces us to turn off I/O MMU bypassing. It is said that
437 * BIO-level virtual merging can give up to 4% performance boost (not verified for ia64).
438 * On the other hand, we know that I/O MMU bypassing gives ~8% performance improvement on
439 * SPECweb-like workloads on zx1-based machines. Thus, for now we favor I/O MMU bypassing
440 * over BIO-level virtual merging.
441 */
442extern unsigned long ia64_max_iommu_merge_mask;
443#if 1
444#define BIO_VMERGE_BOUNDARY 0
445#else
446/*
447 * It makes no sense at all to have this BIO_VMERGE_BOUNDARY macro here. Should be
448 * replaced by dma_merge_mask() or something of that sort. Note: the only way
449 * BIO_VMERGE_BOUNDARY is used is to mask off bits. Effectively, our definition gets
450 * expanded into:
451 *
452 * addr & ((ia64_max_iommu_merge_mask + 1) - 1) == (addr & ia64_max_iommu_vmerge_mask)
453 *
454 * which is precisely what we want.
455 */
456#define BIO_VMERGE_BOUNDARY (ia64_max_iommu_merge_mask + 1)
457#endif
458
459#endif /* _ASM_IA64_IO_H */
diff --git a/include/asm-ia64/ioctl.h b/include/asm-ia64/ioctl.h
deleted file mode 100644
index b279fe06dfe..00000000000
--- a/include/asm-ia64/ioctl.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/ioctl.h>
diff --git a/include/asm-ia64/ioctls.h b/include/asm-ia64/ioctls.h
deleted file mode 100644
index f41b636a0bf..00000000000
--- a/include/asm-ia64/ioctls.h
+++ /dev/null
@@ -1,93 +0,0 @@
1#ifndef _ASM_IA64_IOCTLS_H
2#define _ASM_IA64_IOCTLS_H
3
4/*
5 * Based on <asm-i386/ioctls.h>
6 *
7 * Modified 1998, 1999, 2002
8 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
9 */
10
11#include <asm/ioctl.h>
12
13/* 0x54 is just a magic number to make these relatively unique ('T') */
14
15#define TCGETS 0x5401
16#define TCSETS 0x5402 /* Clashes with SNDCTL_TMR_START sound ioctl */
17#define TCSETSW 0x5403
18#define TCSETSF 0x5404
19#define TCGETA 0x5405
20#define TCSETA 0x5406
21#define TCSETAW 0x5407
22#define TCSETAF 0x5408
23#define TCSBRK 0x5409
24#define TCXONC 0x540A
25#define TCFLSH 0x540B
26#define TIOCEXCL 0x540C
27#define TIOCNXCL 0x540D
28#define TIOCSCTTY 0x540E
29#define TIOCGPGRP 0x540F
30#define TIOCSPGRP 0x5410
31#define TIOCOUTQ 0x5411
32#define TIOCSTI 0x5412
33#define TIOCGWINSZ 0x5413
34#define TIOCSWINSZ 0x5414
35#define TIOCMGET 0x5415
36#define TIOCMBIS 0x5416
37#define TIOCMBIC 0x5417
38#define TIOCMSET 0x5418
39#define TIOCGSOFTCAR 0x5419
40#define TIOCSSOFTCAR 0x541A
41#define FIONREAD 0x541B
42#define TIOCINQ FIONREAD
43#define TIOCLINUX 0x541C
44#define TIOCCONS 0x541D
45#define TIOCGSERIAL 0x541E
46#define TIOCSSERIAL 0x541F
47#define TIOCPKT 0x5420
48#define FIONBIO 0x5421
49#define TIOCNOTTY 0x5422
50#define TIOCSETD 0x5423
51#define TIOCGETD 0x5424
52#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */
53#define TIOCSBRK 0x5427 /* BSD compatibility */
54#define TIOCCBRK 0x5428 /* BSD compatibility */
55#define TIOCGSID 0x5429 /* Return the session ID of FD */
56#define TCGETS2 _IOR('T',0x2A, struct termios2)
57#define TCSETS2 _IOW('T',0x2B, struct termios2)
58#define TCSETSW2 _IOW('T',0x2C, struct termios2)
59#define TCSETSF2 _IOW('T',0x2D, struct termios2)
60#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
61#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */
62
63#define FIONCLEX 0x5450 /* these numbers need to be adjusted. */
64#define FIOCLEX 0x5451
65#define FIOASYNC 0x5452
66#define TIOCSERCONFIG 0x5453
67#define TIOCSERGWILD 0x5454
68#define TIOCSERSWILD 0x5455
69#define TIOCGLCKTRMIOS 0x5456
70#define TIOCSLCKTRMIOS 0x5457
71#define TIOCSERGSTRUCT 0x5458 /* For debugging only */
72#define TIOCSERGETLSR 0x5459 /* Get line status register */
73#define TIOCSERGETMULTI 0x545A /* Get multiport config */
74#define TIOCSERSETMULTI 0x545B /* Set multiport config */
75
76#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */
77#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */
78#define TIOCGHAYESESP 0x545E /* Get Hayes ESP configuration */
79#define TIOCSHAYESESP 0x545F /* Set Hayes ESP configuration */
80#define FIOQSIZE 0x5460
81
82/* Used for packet mode */
83#define TIOCPKT_DATA 0
84#define TIOCPKT_FLUSHREAD 1
85#define TIOCPKT_FLUSHWRITE 2
86#define TIOCPKT_STOP 4
87#define TIOCPKT_START 8
88#define TIOCPKT_NOSTOP 16
89#define TIOCPKT_DOSTOP 32
90
91#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */
92
93#endif /* _ASM_IA64_IOCTLS_H */
diff --git a/include/asm-ia64/iosapic.h b/include/asm-ia64/iosapic.h
deleted file mode 100644
index b9c102e15f2..00000000000
--- a/include/asm-ia64/iosapic.h
+++ /dev/null
@@ -1,126 +0,0 @@
1#ifndef __ASM_IA64_IOSAPIC_H
2#define __ASM_IA64_IOSAPIC_H
3
4#define IOSAPIC_REG_SELECT 0x0
5#define IOSAPIC_WINDOW 0x10
6#define IOSAPIC_EOI 0x40
7
8#define IOSAPIC_VERSION 0x1
9
10/*
11 * Redirection table entry
12 */
13#define IOSAPIC_RTE_LOW(i) (0x10+i*2)
14#define IOSAPIC_RTE_HIGH(i) (0x11+i*2)
15
16#define IOSAPIC_DEST_SHIFT 16
17
18/*
19 * Delivery mode
20 */
21#define IOSAPIC_DELIVERY_SHIFT 8
22#define IOSAPIC_FIXED 0x0
23#define IOSAPIC_LOWEST_PRIORITY 0x1
24#define IOSAPIC_PMI 0x2
25#define IOSAPIC_NMI 0x4
26#define IOSAPIC_INIT 0x5
27#define IOSAPIC_EXTINT 0x7
28
29/*
30 * Interrupt polarity
31 */
32#define IOSAPIC_POLARITY_SHIFT 13
33#define IOSAPIC_POL_HIGH 0
34#define IOSAPIC_POL_LOW 1
35
36/*
37 * Trigger mode
38 */
39#define IOSAPIC_TRIGGER_SHIFT 15
40#define IOSAPIC_EDGE 0
41#define IOSAPIC_LEVEL 1
42
43/*
44 * Mask bit
45 */
46
47#define IOSAPIC_MASK_SHIFT 16
48#define IOSAPIC_MASK (1<<IOSAPIC_MASK_SHIFT)
49
50#define IOSAPIC_VECTOR_MASK 0xffffff00
51
52#ifndef __ASSEMBLY__
53
54#ifdef CONFIG_IOSAPIC
55
56#define NR_IOSAPICS 256
57
58#ifdef CONFIG_PARAVIRT_GUEST
59#include <asm/paravirt.h>
60#else
61#define iosapic_pcat_compat_init ia64_native_iosapic_pcat_compat_init
62#define __iosapic_read __ia64_native_iosapic_read
63#define __iosapic_write __ia64_native_iosapic_write
64#define iosapic_get_irq_chip ia64_native_iosapic_get_irq_chip
65#endif
66
67extern void __init ia64_native_iosapic_pcat_compat_init(void);
68extern struct irq_chip *ia64_native_iosapic_get_irq_chip(unsigned long trigger);
69
70static inline unsigned int
71__ia64_native_iosapic_read(char __iomem *iosapic, unsigned int reg)
72{
73 writel(reg, iosapic + IOSAPIC_REG_SELECT);
74 return readl(iosapic + IOSAPIC_WINDOW);
75}
76
77static inline void
78__ia64_native_iosapic_write(char __iomem *iosapic, unsigned int reg, u32 val)
79{
80 writel(reg, iosapic + IOSAPIC_REG_SELECT);
81 writel(val, iosapic + IOSAPIC_WINDOW);
82}
83
84static inline void iosapic_eoi(char __iomem *iosapic, u32 vector)
85{
86 writel(vector, iosapic + IOSAPIC_EOI);
87}
88
89extern void __init iosapic_system_init (int pcat_compat);
90extern int __devinit iosapic_init (unsigned long address,
91 unsigned int gsi_base);
92#ifdef CONFIG_HOTPLUG
93extern int iosapic_remove (unsigned int gsi_base);
94#else
95#define iosapic_remove(gsi_base) (-EINVAL)
96#endif /* CONFIG_HOTPLUG */
97extern int gsi_to_irq (unsigned int gsi);
98extern int iosapic_register_intr (unsigned int gsi, unsigned long polarity,
99 unsigned long trigger);
100extern void iosapic_unregister_intr (unsigned int irq);
101extern void __devinit iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi,
102 unsigned long polarity,
103 unsigned long trigger);
104extern int __init iosapic_register_platform_intr (u32 int_type,
105 unsigned int gsi,
106 int pmi_vector,
107 u16 eid, u16 id,
108 unsigned long polarity,
109 unsigned long trigger);
110
111#ifdef CONFIG_NUMA
112extern void __devinit map_iosapic_to_node (unsigned int, int);
113#endif
114#else
115#define iosapic_system_init(pcat_compat) do { } while (0)
116#define iosapic_init(address,gsi_base) (-EINVAL)
117#define iosapic_remove(gsi_base) (-ENODEV)
118#define iosapic_register_intr(gsi,polarity,trigger) (gsi)
119#define iosapic_unregister_intr(irq) do { } while (0)
120#define iosapic_override_isa_irq(isa_irq,gsi,polarity,trigger) do { } while (0)
121#define iosapic_register_platform_intr(type,gsi,pmi,eid,id, \
122 polarity,trigger) (gsi)
123#endif
124
125# endif /* !__ASSEMBLY__ */
126#endif /* __ASM_IA64_IOSAPIC_H */
diff --git a/include/asm-ia64/ipcbuf.h b/include/asm-ia64/ipcbuf.h
deleted file mode 100644
index 079899ae7d3..00000000000
--- a/include/asm-ia64/ipcbuf.h
+++ /dev/null
@@ -1,28 +0,0 @@
1#ifndef _ASM_IA64_IPCBUF_H
2#define _ASM_IA64_IPCBUF_H
3
4/*
5 * The ipc64_perm structure for IA-64 architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 32-bit seq
11 * - 2 miscellaneous 64-bit values
12 */
13
14struct ipc64_perm
15{
16 __kernel_key_t key;
17 __kernel_uid_t uid;
18 __kernel_gid_t gid;
19 __kernel_uid_t cuid;
20 __kernel_gid_t cgid;
21 __kernel_mode_t mode;
22 unsigned short seq;
23 unsigned short __pad1;
24 unsigned long __unused1;
25 unsigned long __unused2;
26};
27
28#endif /* _ASM_IA64_IPCBUF_H */
diff --git a/include/asm-ia64/irq.h b/include/asm-ia64/irq.h
deleted file mode 100644
index 3627116fb0e..00000000000
--- a/include/asm-ia64/irq.h
+++ /dev/null
@@ -1,34 +0,0 @@
1#ifndef _ASM_IA64_IRQ_H
2#define _ASM_IA64_IRQ_H
3
4/*
5 * Copyright (C) 1999-2000, 2002 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 * Stephane Eranian <eranian@hpl.hp.com>
8 *
9 * 11/24/98 S.Eranian updated TIMER_IRQ and irq_canonicalize
10 * 01/20/99 S.Eranian added keyboard interrupt
11 * 02/29/00 D.Mosberger moved most things into hw_irq.h
12 */
13
14#include <linux/types.h>
15#include <linux/cpumask.h>
16#include <asm-ia64/nr-irqs.h>
17
18static __inline__ int
19irq_canonicalize (int irq)
20{
21 /*
22 * We do the legacy thing here of pretending that irqs < 16
23 * are 8259 irqs. This really shouldn't be necessary at all,
24 * but we keep it here as serial.c still uses it...
25 */
26 return ((irq == 2) ? 9 : irq);
27}
28
29extern void set_irq_affinity_info (unsigned int irq, int dest, int redir);
30bool is_affinity_mask_valid(cpumask_t cpumask);
31
32#define is_affinity_mask_valid is_affinity_mask_valid
33
34#endif /* _ASM_IA64_IRQ_H */
diff --git a/include/asm-ia64/irq_regs.h b/include/asm-ia64/irq_regs.h
deleted file mode 100644
index 3dd9c0b7027..00000000000
--- a/include/asm-ia64/irq_regs.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/irq_regs.h>
diff --git a/include/asm-ia64/kdebug.h b/include/asm-ia64/kdebug.h
deleted file mode 100644
index 35e49407d06..00000000000
--- a/include/asm-ia64/kdebug.h
+++ /dev/null
@@ -1,59 +0,0 @@
1#ifndef _IA64_KDEBUG_H
2#define _IA64_KDEBUG_H 1
3/*
4 * include/asm-ia64/kdebug.h
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 *
20 * Copyright (C) Intel Corporation, 2005
21 *
22 * 2005-Apr Rusty Lynch <rusty.lynch@intel.com> and Anil S Keshavamurthy
23 * <anil.s.keshavamurthy@intel.com> adopted from
24 * include/asm-x86_64/kdebug.h
25 *
26 * 2005-Oct Keith Owens <kaos@sgi.com>. Expand notify_die to cover more
27 * events.
28 */
29
30enum die_val {
31 DIE_BREAK = 1,
32 DIE_FAULT,
33 DIE_OOPS,
34 DIE_MACHINE_HALT,
35 DIE_MACHINE_RESTART,
36 DIE_MCA_MONARCH_ENTER,
37 DIE_MCA_MONARCH_PROCESS,
38 DIE_MCA_MONARCH_LEAVE,
39 DIE_MCA_SLAVE_ENTER,
40 DIE_MCA_SLAVE_PROCESS,
41 DIE_MCA_SLAVE_LEAVE,
42 DIE_MCA_RENDZVOUS_ENTER,
43 DIE_MCA_RENDZVOUS_PROCESS,
44 DIE_MCA_RENDZVOUS_LEAVE,
45 DIE_MCA_NEW_TIMEOUT,
46 DIE_INIT_ENTER,
47 DIE_INIT_MONARCH_ENTER,
48 DIE_INIT_MONARCH_PROCESS,
49 DIE_INIT_MONARCH_LEAVE,
50 DIE_INIT_SLAVE_ENTER,
51 DIE_INIT_SLAVE_PROCESS,
52 DIE_INIT_SLAVE_LEAVE,
53 DIE_KDEBUG_ENTER,
54 DIE_KDEBUG_LEAVE,
55 DIE_KDUMP_ENTER,
56 DIE_KDUMP_LEAVE,
57};
58
59#endif
diff --git a/include/asm-ia64/kexec.h b/include/asm-ia64/kexec.h
deleted file mode 100644
index 541be835fc5..00000000000
--- a/include/asm-ia64/kexec.h
+++ /dev/null
@@ -1,44 +0,0 @@
1#ifndef _ASM_IA64_KEXEC_H
2#define _ASM_IA64_KEXEC_H
3
4
5/* Maximum physical address we can use pages from */
6#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
7/* Maximum address we can reach in physical address mode */
8#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
9/* Maximum address we can use for the control code buffer */
10#define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE
11
12#define KEXEC_CONTROL_CODE_SIZE (8192 + 8192 + 4096)
13
14/* The native architecture */
15#define KEXEC_ARCH KEXEC_ARCH_IA_64
16
17#define kexec_flush_icache_page(page) do { \
18 unsigned long page_addr = (unsigned long)page_address(page); \
19 flush_icache_range(page_addr, page_addr + PAGE_SIZE); \
20 } while(0)
21
22extern struct kimage *ia64_kimage;
23extern const unsigned int relocate_new_kernel_size;
24extern void relocate_new_kernel(unsigned long, unsigned long,
25 struct ia64_boot_param *, unsigned long);
26static inline void
27crash_setup_regs(struct pt_regs *newregs, struct pt_regs *oldregs)
28{
29}
30extern struct resource efi_memmap_res;
31extern struct resource boot_param_res;
32extern void kdump_smp_send_stop(void);
33extern void kdump_smp_send_init(void);
34extern void kexec_disable_iosapic(void);
35extern void crash_save_this_cpu(void);
36struct rsvd_region;
37extern unsigned long kdump_find_rsvd_region(unsigned long size,
38 struct rsvd_region *rsvd_regions, int n);
39extern void kdump_cpu_freeze(struct unw_frame_info *info, void *arg);
40extern int kdump_status[];
41extern atomic_t kdump_cpu_freezed;
42extern atomic_t kdump_in_progress;
43
44#endif /* _ASM_IA64_KEXEC_H */
diff --git a/include/asm-ia64/kmap_types.h b/include/asm-ia64/kmap_types.h
deleted file mode 100644
index 5d1658aa2b3..00000000000
--- a/include/asm-ia64/kmap_types.h
+++ /dev/null
@@ -1,30 +0,0 @@
1#ifndef _ASM_IA64_KMAP_TYPES_H
2#define _ASM_IA64_KMAP_TYPES_H
3
4
5#ifdef CONFIG_DEBUG_HIGHMEM
6# define D(n) __KM_FENCE_##n ,
7#else
8# define D(n)
9#endif
10
11enum km_type {
12D(0) KM_BOUNCE_READ,
13D(1) KM_SKB_SUNRPC_DATA,
14D(2) KM_SKB_DATA_SOFTIRQ,
15D(3) KM_USER0,
16D(4) KM_USER1,
17D(5) KM_BIO_SRC_IRQ,
18D(6) KM_BIO_DST_IRQ,
19D(7) KM_PTE0,
20D(8) KM_PTE1,
21D(9) KM_IRQ0,
22D(10) KM_IRQ1,
23D(11) KM_SOFTIRQ0,
24D(12) KM_SOFTIRQ1,
25D(13) KM_TYPE_NR
26};
27
28#undef D
29
30#endif /* _ASM_IA64_KMAP_TYPES_H */
diff --git a/include/asm-ia64/kprobes.h b/include/asm-ia64/kprobes.h
deleted file mode 100644
index ef71b57fc2f..00000000000
--- a/include/asm-ia64/kprobes.h
+++ /dev/null
@@ -1,133 +0,0 @@
1#ifndef _ASM_KPROBES_H
2#define _ASM_KPROBES_H
3/*
4 * Kernel Probes (KProbes)
5 * include/asm-ia64/kprobes.h
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 *
21 * Copyright (C) IBM Corporation, 2002, 2004
22 * Copyright (C) Intel Corporation, 2005
23 *
24 * 2005-Apr Rusty Lynch <rusty.lynch@intel.com> and Anil S Keshavamurthy
25 * <anil.s.keshavamurthy@intel.com> adapted from i386
26 */
27#include <linux/types.h>
28#include <linux/ptrace.h>
29#include <linux/percpu.h>
30#include <asm/break.h>
31
32#define __ARCH_WANT_KPROBES_INSN_SLOT
33#define MAX_INSN_SIZE 2 /* last half is for kprobe-booster */
34#define BREAK_INST (long)(__IA64_BREAK_KPROBE << 6)
35#define NOP_M_INST (long)(1<<27)
36#define BRL_INST(i1, i2) ((long)((0xcL << 37) | /* brl */ \
37 (0x1L << 12) | /* many */ \
38 (((i1) & 1) << 36) | ((i2) << 13))) /* imm */
39
40typedef union cmp_inst {
41 struct {
42 unsigned long long qp : 6;
43 unsigned long long p1 : 6;
44 unsigned long long c : 1;
45 unsigned long long r2 : 7;
46 unsigned long long r3 : 7;
47 unsigned long long p2 : 6;
48 unsigned long long ta : 1;
49 unsigned long long x2 : 2;
50 unsigned long long tb : 1;
51 unsigned long long opcode : 4;
52 unsigned long long reserved : 23;
53 }f;
54 unsigned long long l;
55} cmp_inst_t;
56
57struct kprobe;
58
59typedef struct _bundle {
60 struct {
61 unsigned long long template : 5;
62 unsigned long long slot0 : 41;
63 unsigned long long slot1_p0 : 64-46;
64 } quad0;
65 struct {
66 unsigned long long slot1_p1 : 41 - (64-46);
67 unsigned long long slot2 : 41;
68 } quad1;
69} __attribute__((__aligned__(16))) bundle_t;
70
71struct prev_kprobe {
72 struct kprobe *kp;
73 unsigned long status;
74};
75
76#define MAX_PARAM_RSE_SIZE (0x60+0x60/0x3f)
77/* per-cpu kprobe control block */
78#define ARCH_PREV_KPROBE_SZ 2
79struct kprobe_ctlblk {
80 unsigned long kprobe_status;
81 struct pt_regs jprobe_saved_regs;
82 unsigned long jprobes_saved_stacked_regs[MAX_PARAM_RSE_SIZE];
83 unsigned long *bsp;
84 unsigned long cfm;
85 atomic_t prev_kprobe_index;
86 struct prev_kprobe prev_kprobe[ARCH_PREV_KPROBE_SZ];
87};
88
89#define kretprobe_blacklist_size 0
90
91#define SLOT0_OPCODE_SHIFT (37)
92#define SLOT1_p1_OPCODE_SHIFT (37 - (64-46))
93#define SLOT2_OPCODE_SHIFT (37)
94
95#define INDIRECT_CALL_OPCODE (1)
96#define IP_RELATIVE_CALL_OPCODE (5)
97#define IP_RELATIVE_BRANCH_OPCODE (4)
98#define IP_RELATIVE_PREDICT_OPCODE (7)
99#define LONG_BRANCH_OPCODE (0xC)
100#define LONG_CALL_OPCODE (0xD)
101#define flush_insn_slot(p) do { } while (0)
102
103typedef struct kprobe_opcode {
104 bundle_t bundle;
105} kprobe_opcode_t;
106
107struct fnptr {
108 unsigned long ip;
109 unsigned long gp;
110};
111
112/* Architecture specific copy of original instruction*/
113struct arch_specific_insn {
114 /* copy of the instruction to be emulated */
115 kprobe_opcode_t *insn;
116 #define INST_FLAG_FIX_RELATIVE_IP_ADDR 1
117 #define INST_FLAG_FIX_BRANCH_REG 2
118 #define INST_FLAG_BREAK_INST 4
119 #define INST_FLAG_BOOSTABLE 8
120 unsigned long inst_flag;
121 unsigned short target_br_reg;
122 unsigned short slot;
123};
124
125extern int kprobe_fault_handler(struct pt_regs *regs, int trapnr);
126extern int kprobe_exceptions_notify(struct notifier_block *self,
127 unsigned long val, void *data);
128
129extern void invalidate_stacked_regs(void);
130extern void flush_register_stack(void);
131extern void arch_remove_kprobe(struct kprobe *p);
132
133#endif /* _ASM_KPROBES_H */
diff --git a/include/asm-ia64/kregs.h b/include/asm-ia64/kregs.h
deleted file mode 100644
index aefcdfee7f2..00000000000
--- a/include/asm-ia64/kregs.h
+++ /dev/null
@@ -1,165 +0,0 @@
1#ifndef _ASM_IA64_KREGS_H
2#define _ASM_IA64_KREGS_H
3
4/*
5 * Copyright (C) 2001-2002 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 */
8/*
9 * This file defines the kernel register usage convention used by Linux/ia64.
10 */
11
12/*
13 * Kernel registers:
14 */
15#define IA64_KR_IO_BASE 0 /* ar.k0: legacy I/O base address */
16#define IA64_KR_TSSD 1 /* ar.k1: IVE uses this as the TSSD */
17#define IA64_KR_PER_CPU_DATA 3 /* ar.k3: physical per-CPU base */
18#define IA64_KR_CURRENT_STACK 4 /* ar.k4: what's mapped in IA64_TR_CURRENT_STACK */
19#define IA64_KR_FPU_OWNER 5 /* ar.k5: fpu-owner (UP only, at the moment) */
20#define IA64_KR_CURRENT 6 /* ar.k6: "current" task pointer */
21#define IA64_KR_PT_BASE 7 /* ar.k7: page table base address (physical) */
22
23#define _IA64_KR_PASTE(x,y) x##y
24#define _IA64_KR_PREFIX(n) _IA64_KR_PASTE(ar.k, n)
25#define IA64_KR(n) _IA64_KR_PREFIX(IA64_KR_##n)
26
27/*
28 * Translation registers:
29 */
30#define IA64_TR_KERNEL 0 /* itr0, dtr0: maps kernel image (code & data) */
31#define IA64_TR_PALCODE 1 /* itr1: maps PALcode as required by EFI */
32#define IA64_TR_CURRENT_STACK 1 /* dtr1: maps kernel's memory- & register-stacks */
33
34#define IA64_TR_ALLOC_BASE 2 /* itr&dtr: Base of dynamic TR resource*/
35#define IA64_TR_ALLOC_MAX 32 /* Max number for dynamic use*/
36
37/* Processor status register bits: */
38#define IA64_PSR_BE_BIT 1
39#define IA64_PSR_UP_BIT 2
40#define IA64_PSR_AC_BIT 3
41#define IA64_PSR_MFL_BIT 4
42#define IA64_PSR_MFH_BIT 5
43#define IA64_PSR_IC_BIT 13
44#define IA64_PSR_I_BIT 14
45#define IA64_PSR_PK_BIT 15
46#define IA64_PSR_DT_BIT 17
47#define IA64_PSR_DFL_BIT 18
48#define IA64_PSR_DFH_BIT 19
49#define IA64_PSR_SP_BIT 20
50#define IA64_PSR_PP_BIT 21
51#define IA64_PSR_DI_BIT 22
52#define IA64_PSR_SI_BIT 23
53#define IA64_PSR_DB_BIT 24
54#define IA64_PSR_LP_BIT 25
55#define IA64_PSR_TB_BIT 26
56#define IA64_PSR_RT_BIT 27
57/* The following are not affected by save_flags()/restore_flags(): */
58#define IA64_PSR_CPL0_BIT 32
59#define IA64_PSR_CPL1_BIT 33
60#define IA64_PSR_IS_BIT 34
61#define IA64_PSR_MC_BIT 35
62#define IA64_PSR_IT_BIT 36
63#define IA64_PSR_ID_BIT 37
64#define IA64_PSR_DA_BIT 38
65#define IA64_PSR_DD_BIT 39
66#define IA64_PSR_SS_BIT 40
67#define IA64_PSR_RI_BIT 41
68#define IA64_PSR_ED_BIT 43
69#define IA64_PSR_BN_BIT 44
70#define IA64_PSR_IA_BIT 45
71
72/* A mask of PSR bits that we generally don't want to inherit across a clone2() or an
73 execve(). Only list flags here that need to be cleared/set for BOTH clone2() and
74 execve(). */
75#define IA64_PSR_BITS_TO_CLEAR (IA64_PSR_MFL | IA64_PSR_MFH | IA64_PSR_DB | IA64_PSR_LP | \
76 IA64_PSR_TB | IA64_PSR_ID | IA64_PSR_DA | IA64_PSR_DD | \
77 IA64_PSR_SS | IA64_PSR_ED | IA64_PSR_IA)
78#define IA64_PSR_BITS_TO_SET (IA64_PSR_DFH | IA64_PSR_SP)
79
80#define IA64_PSR_BE (__IA64_UL(1) << IA64_PSR_BE_BIT)
81#define IA64_PSR_UP (__IA64_UL(1) << IA64_PSR_UP_BIT)
82#define IA64_PSR_AC (__IA64_UL(1) << IA64_PSR_AC_BIT)
83#define IA64_PSR_MFL (__IA64_UL(1) << IA64_PSR_MFL_BIT)
84#define IA64_PSR_MFH (__IA64_UL(1) << IA64_PSR_MFH_BIT)
85#define IA64_PSR_IC (__IA64_UL(1) << IA64_PSR_IC_BIT)
86#define IA64_PSR_I (__IA64_UL(1) << IA64_PSR_I_BIT)
87#define IA64_PSR_PK (__IA64_UL(1) << IA64_PSR_PK_BIT)
88#define IA64_PSR_DT (__IA64_UL(1) << IA64_PSR_DT_BIT)
89#define IA64_PSR_DFL (__IA64_UL(1) << IA64_PSR_DFL_BIT)
90#define IA64_PSR_DFH (__IA64_UL(1) << IA64_PSR_DFH_BIT)
91#define IA64_PSR_SP (__IA64_UL(1) << IA64_PSR_SP_BIT)
92#define IA64_PSR_PP (__IA64_UL(1) << IA64_PSR_PP_BIT)
93#define IA64_PSR_DI (__IA64_UL(1) << IA64_PSR_DI_BIT)
94#define IA64_PSR_SI (__IA64_UL(1) << IA64_PSR_SI_BIT)
95#define IA64_PSR_DB (__IA64_UL(1) << IA64_PSR_DB_BIT)
96#define IA64_PSR_LP (__IA64_UL(1) << IA64_PSR_LP_BIT)
97#define IA64_PSR_TB (__IA64_UL(1) << IA64_PSR_TB_BIT)
98#define IA64_PSR_RT (__IA64_UL(1) << IA64_PSR_RT_BIT)
99/* The following are not affected by save_flags()/restore_flags(): */
100#define IA64_PSR_CPL (__IA64_UL(3) << IA64_PSR_CPL0_BIT)
101#define IA64_PSR_IS (__IA64_UL(1) << IA64_PSR_IS_BIT)
102#define IA64_PSR_MC (__IA64_UL(1) << IA64_PSR_MC_BIT)
103#define IA64_PSR_IT (__IA64_UL(1) << IA64_PSR_IT_BIT)
104#define IA64_PSR_ID (__IA64_UL(1) << IA64_PSR_ID_BIT)
105#define IA64_PSR_DA (__IA64_UL(1) << IA64_PSR_DA_BIT)
106#define IA64_PSR_DD (__IA64_UL(1) << IA64_PSR_DD_BIT)
107#define IA64_PSR_SS (__IA64_UL(1) << IA64_PSR_SS_BIT)
108#define IA64_PSR_RI (__IA64_UL(3) << IA64_PSR_RI_BIT)
109#define IA64_PSR_ED (__IA64_UL(1) << IA64_PSR_ED_BIT)
110#define IA64_PSR_BN (__IA64_UL(1) << IA64_PSR_BN_BIT)
111#define IA64_PSR_IA (__IA64_UL(1) << IA64_PSR_IA_BIT)
112
113/* User mask bits: */
114#define IA64_PSR_UM (IA64_PSR_BE | IA64_PSR_UP | IA64_PSR_AC | IA64_PSR_MFL | IA64_PSR_MFH)
115
116/* Default Control Register */
117#define IA64_DCR_PP_BIT 0 /* privileged performance monitor default */
118#define IA64_DCR_BE_BIT 1 /* big-endian default */
119#define IA64_DCR_LC_BIT 2 /* ia32 lock-check enable */
120#define IA64_DCR_DM_BIT 8 /* defer TLB miss faults */
121#define IA64_DCR_DP_BIT 9 /* defer page-not-present faults */
122#define IA64_DCR_DK_BIT 10 /* defer key miss faults */
123#define IA64_DCR_DX_BIT 11 /* defer key permission faults */
124#define IA64_DCR_DR_BIT 12 /* defer access right faults */
125#define IA64_DCR_DA_BIT 13 /* defer access bit faults */
126#define IA64_DCR_DD_BIT 14 /* defer debug faults */
127
128#define IA64_DCR_PP (__IA64_UL(1) << IA64_DCR_PP_BIT)
129#define IA64_DCR_BE (__IA64_UL(1) << IA64_DCR_BE_BIT)
130#define IA64_DCR_LC (__IA64_UL(1) << IA64_DCR_LC_BIT)
131#define IA64_DCR_DM (__IA64_UL(1) << IA64_DCR_DM_BIT)
132#define IA64_DCR_DP (__IA64_UL(1) << IA64_DCR_DP_BIT)
133#define IA64_DCR_DK (__IA64_UL(1) << IA64_DCR_DK_BIT)
134#define IA64_DCR_DX (__IA64_UL(1) << IA64_DCR_DX_BIT)
135#define IA64_DCR_DR (__IA64_UL(1) << IA64_DCR_DR_BIT)
136#define IA64_DCR_DA (__IA64_UL(1) << IA64_DCR_DA_BIT)
137#define IA64_DCR_DD (__IA64_UL(1) << IA64_DCR_DD_BIT)
138
139/* Interrupt Status Register */
140#define IA64_ISR_X_BIT 32 /* execute access */
141#define IA64_ISR_W_BIT 33 /* write access */
142#define IA64_ISR_R_BIT 34 /* read access */
143#define IA64_ISR_NA_BIT 35 /* non-access */
144#define IA64_ISR_SP_BIT 36 /* speculative load exception */
145#define IA64_ISR_RS_BIT 37 /* mandatory register-stack exception */
146#define IA64_ISR_IR_BIT 38 /* invalid register frame exception */
147#define IA64_ISR_CODE_MASK 0xf
148
149#define IA64_ISR_X (__IA64_UL(1) << IA64_ISR_X_BIT)
150#define IA64_ISR_W (__IA64_UL(1) << IA64_ISR_W_BIT)
151#define IA64_ISR_R (__IA64_UL(1) << IA64_ISR_R_BIT)
152#define IA64_ISR_NA (__IA64_UL(1) << IA64_ISR_NA_BIT)
153#define IA64_ISR_SP (__IA64_UL(1) << IA64_ISR_SP_BIT)
154#define IA64_ISR_RS (__IA64_UL(1) << IA64_ISR_RS_BIT)
155#define IA64_ISR_IR (__IA64_UL(1) << IA64_ISR_IR_BIT)
156
157/* ISR code field for non-access instructions */
158#define IA64_ISR_CODE_TPA 0
159#define IA64_ISR_CODE_FC 1
160#define IA64_ISR_CODE_PROBE 2
161#define IA64_ISR_CODE_TAK 3
162#define IA64_ISR_CODE_LFETCH 4
163#define IA64_ISR_CODE_PROBEF 5
164
165#endif /* _ASM_IA64_kREGS_H */
diff --git a/include/asm-ia64/kvm.h b/include/asm-ia64/kvm.h
deleted file mode 100644
index 3f6a090cbd9..00000000000
--- a/include/asm-ia64/kvm.h
+++ /dev/null
@@ -1,211 +0,0 @@
1#ifndef __ASM_IA64_KVM_H
2#define __ASM_IA64_KVM_H
3
4/*
5 * asm-ia64/kvm.h: kvm structure definitions for ia64
6 *
7 * Copyright (C) 2007 Xiantao Zhang <xiantao.zhang@intel.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
20 * Place - Suite 330, Boston, MA 02111-1307 USA.
21 *
22 */
23
24#include <asm/types.h>
25
26#include <linux/ioctl.h>
27
28/* Architectural interrupt line count. */
29#define KVM_NR_INTERRUPTS 256
30
31#define KVM_IOAPIC_NUM_PINS 48
32
33struct kvm_ioapic_state {
34 __u64 base_address;
35 __u32 ioregsel;
36 __u32 id;
37 __u32 irr;
38 __u32 pad;
39 union {
40 __u64 bits;
41 struct {
42 __u8 vector;
43 __u8 delivery_mode:3;
44 __u8 dest_mode:1;
45 __u8 delivery_status:1;
46 __u8 polarity:1;
47 __u8 remote_irr:1;
48 __u8 trig_mode:1;
49 __u8 mask:1;
50 __u8 reserve:7;
51 __u8 reserved[4];
52 __u8 dest_id;
53 } fields;
54 } redirtbl[KVM_IOAPIC_NUM_PINS];
55};
56
57#define KVM_IRQCHIP_PIC_MASTER 0
58#define KVM_IRQCHIP_PIC_SLAVE 1
59#define KVM_IRQCHIP_IOAPIC 2
60
61#define KVM_CONTEXT_SIZE 8*1024
62
63struct kvm_fpreg {
64 union {
65 unsigned long bits[2];
66 long double __dummy; /* force 16-byte alignment */
67 } u;
68};
69
70union context {
71 /* 8K size */
72 char dummy[KVM_CONTEXT_SIZE];
73 struct {
74 unsigned long psr;
75 unsigned long pr;
76 unsigned long caller_unat;
77 unsigned long pad;
78 unsigned long gr[32];
79 unsigned long ar[128];
80 unsigned long br[8];
81 unsigned long cr[128];
82 unsigned long rr[8];
83 unsigned long ibr[8];
84 unsigned long dbr[8];
85 unsigned long pkr[8];
86 struct kvm_fpreg fr[128];
87 };
88};
89
90struct thash_data {
91 union {
92 struct {
93 unsigned long p : 1; /* 0 */
94 unsigned long rv1 : 1; /* 1 */
95 unsigned long ma : 3; /* 2-4 */
96 unsigned long a : 1; /* 5 */
97 unsigned long d : 1; /* 6 */
98 unsigned long pl : 2; /* 7-8 */
99 unsigned long ar : 3; /* 9-11 */
100 unsigned long ppn : 38; /* 12-49 */
101 unsigned long rv2 : 2; /* 50-51 */
102 unsigned long ed : 1; /* 52 */
103 unsigned long ig1 : 11; /* 53-63 */
104 };
105 struct {
106 unsigned long __rv1 : 53; /* 0-52 */
107 unsigned long contiguous : 1; /*53 */
108 unsigned long tc : 1; /* 54 TR or TC */
109 unsigned long cl : 1;
110 /* 55 I side or D side cache line */
111 unsigned long len : 4; /* 56-59 */
112 unsigned long io : 1; /* 60 entry is for io or not */
113 unsigned long nomap : 1;
114 /* 61 entry cann't be inserted into machine TLB.*/
115 unsigned long checked : 1;
116 /* 62 for VTLB/VHPT sanity check */
117 unsigned long invalid : 1;
118 /* 63 invalid entry */
119 };
120 unsigned long page_flags;
121 }; /* same for VHPT and TLB */
122
123 union {
124 struct {
125 unsigned long rv3 : 2;
126 unsigned long ps : 6;
127 unsigned long key : 24;
128 unsigned long rv4 : 32;
129 };
130 unsigned long itir;
131 };
132 union {
133 struct {
134 unsigned long ig2 : 12;
135 unsigned long vpn : 49;
136 unsigned long vrn : 3;
137 };
138 unsigned long ifa;
139 unsigned long vadr;
140 struct {
141 unsigned long tag : 63;
142 unsigned long ti : 1;
143 };
144 unsigned long etag;
145 };
146 union {
147 struct thash_data *next;
148 unsigned long rid;
149 unsigned long gpaddr;
150 };
151};
152
153#define NITRS 8
154#define NDTRS 8
155
156struct saved_vpd {
157 unsigned long vhpi;
158 unsigned long vgr[16];
159 unsigned long vbgr[16];
160 unsigned long vnat;
161 unsigned long vbnat;
162 unsigned long vcpuid[5];
163 unsigned long vpsr;
164 unsigned long vpr;
165 unsigned long vcr[128];
166};
167
168struct kvm_regs {
169 char *saved_guest;
170 char *saved_stack;
171 struct saved_vpd vpd;
172 /*Arch-regs*/
173 int mp_state;
174 unsigned long vmm_rr;
175 /* TR and TC. */
176 struct thash_data itrs[NITRS];
177 struct thash_data dtrs[NDTRS];
178 /* Bit is set if there is a tr/tc for the region. */
179 unsigned char itr_regions;
180 unsigned char dtr_regions;
181 unsigned char tc_regions;
182
183 char irq_check;
184 unsigned long saved_itc;
185 unsigned long itc_check;
186 unsigned long timer_check;
187 unsigned long timer_pending;
188 unsigned long last_itc;
189
190 unsigned long vrr[8];
191 unsigned long ibr[8];
192 unsigned long dbr[8];
193 unsigned long insvc[4]; /* Interrupt in service. */
194 unsigned long xtp;
195
196 unsigned long metaphysical_rr0; /* from kvm_arch (so is pinned) */
197 unsigned long metaphysical_rr4; /* from kvm_arch (so is pinned) */
198 unsigned long metaphysical_saved_rr0; /* from kvm_arch */
199 unsigned long metaphysical_saved_rr4; /* from kvm_arch */
200 unsigned long fp_psr; /*used for lazy float register */
201 unsigned long saved_gp;
202 /*for phycial emulation */
203};
204
205struct kvm_sregs {
206};
207
208struct kvm_fpu {
209};
210
211#endif
diff --git a/include/asm-ia64/kvm_host.h b/include/asm-ia64/kvm_host.h
deleted file mode 100644
index 1efe513a994..00000000000
--- a/include/asm-ia64/kvm_host.h
+++ /dev/null
@@ -1,527 +0,0 @@
1/*
2 * kvm_host.h: used for kvm module, and hold ia64-specific sections.
3 *
4 * Copyright (C) 2007, Intel Corporation.
5 *
6 * Xiantao Zhang <xiantao.zhang@intel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
19 * Place - Suite 330, Boston, MA 02111-1307 USA.
20 *
21 */
22
23#ifndef __ASM_KVM_HOST_H
24#define __ASM_KVM_HOST_H
25
26
27#include <linux/types.h>
28#include <linux/mm.h>
29#include <linux/kvm.h>
30#include <linux/kvm_para.h>
31#include <linux/kvm_types.h>
32
33#include <asm/pal.h>
34#include <asm/sal.h>
35
36#define KVM_MAX_VCPUS 4
37#define KVM_MEMORY_SLOTS 32
38/* memory slots that does not exposed to userspace */
39#define KVM_PRIVATE_MEM_SLOTS 4
40
41#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
42
43/* define exit reasons from vmm to kvm*/
44#define EXIT_REASON_VM_PANIC 0
45#define EXIT_REASON_MMIO_INSTRUCTION 1
46#define EXIT_REASON_PAL_CALL 2
47#define EXIT_REASON_SAL_CALL 3
48#define EXIT_REASON_SWITCH_RR6 4
49#define EXIT_REASON_VM_DESTROY 5
50#define EXIT_REASON_EXTERNAL_INTERRUPT 6
51#define EXIT_REASON_IPI 7
52#define EXIT_REASON_PTC_G 8
53
54/*Define vmm address space and vm data space.*/
55#define KVM_VMM_SIZE (16UL<<20)
56#define KVM_VMM_SHIFT 24
57#define KVM_VMM_BASE 0xD000000000000000UL
58#define VMM_SIZE (8UL<<20)
59
60/*
61 * Define vm_buffer, used by PAL Services, base address.
62 * Note: vmbuffer is in the VMM-BLOCK, the size must be < 8M
63 */
64#define KVM_VM_BUFFER_BASE (KVM_VMM_BASE + VMM_SIZE)
65#define KVM_VM_BUFFER_SIZE (8UL<<20)
66
67/*Define Virtual machine data layout.*/
68#define KVM_VM_DATA_SHIFT 24
69#define KVM_VM_DATA_SIZE (1UL << KVM_VM_DATA_SHIFT)
70#define KVM_VM_DATA_BASE (KVM_VMM_BASE + KVM_VMM_SIZE)
71
72
73#define KVM_P2M_BASE KVM_VM_DATA_BASE
74#define KVM_P2M_OFS 0
75#define KVM_P2M_SIZE (8UL << 20)
76
77#define KVM_VHPT_BASE (KVM_P2M_BASE + KVM_P2M_SIZE)
78#define KVM_VHPT_OFS KVM_P2M_SIZE
79#define KVM_VHPT_BLOCK_SIZE (2UL << 20)
80#define VHPT_SHIFT 18
81#define VHPT_SIZE (1UL << VHPT_SHIFT)
82#define VHPT_NUM_ENTRIES (1<<(VHPT_SHIFT-5))
83
84#define KVM_VTLB_BASE (KVM_VHPT_BASE+KVM_VHPT_BLOCK_SIZE)
85#define KVM_VTLB_OFS (KVM_VHPT_OFS+KVM_VHPT_BLOCK_SIZE)
86#define KVM_VTLB_BLOCK_SIZE (1UL<<20)
87#define VTLB_SHIFT 17
88#define VTLB_SIZE (1UL<<VTLB_SHIFT)
89#define VTLB_NUM_ENTRIES (1<<(VTLB_SHIFT-5))
90
91#define KVM_VPD_BASE (KVM_VTLB_BASE+KVM_VTLB_BLOCK_SIZE)
92#define KVM_VPD_OFS (KVM_VTLB_OFS+KVM_VTLB_BLOCK_SIZE)
93#define KVM_VPD_BLOCK_SIZE (2UL<<20)
94#define VPD_SHIFT 16
95#define VPD_SIZE (1UL<<VPD_SHIFT)
96
97#define KVM_VCPU_BASE (KVM_VPD_BASE+KVM_VPD_BLOCK_SIZE)
98#define KVM_VCPU_OFS (KVM_VPD_OFS+KVM_VPD_BLOCK_SIZE)
99#define KVM_VCPU_BLOCK_SIZE (2UL<<20)
100#define VCPU_SHIFT 18
101#define VCPU_SIZE (1UL<<VCPU_SHIFT)
102#define MAX_VCPU_NUM KVM_VCPU_BLOCK_SIZE/VCPU_SIZE
103
104#define KVM_VM_BASE (KVM_VCPU_BASE+KVM_VCPU_BLOCK_SIZE)
105#define KVM_VM_OFS (KVM_VCPU_OFS+KVM_VCPU_BLOCK_SIZE)
106#define KVM_VM_BLOCK_SIZE (1UL<<19)
107
108#define KVM_MEM_DIRTY_LOG_BASE (KVM_VM_BASE+KVM_VM_BLOCK_SIZE)
109#define KVM_MEM_DIRTY_LOG_OFS (KVM_VM_OFS+KVM_VM_BLOCK_SIZE)
110#define KVM_MEM_DIRTY_LOG_SIZE (1UL<<19)
111
112/* Get vpd, vhpt, tlb, vcpu, base*/
113#define VPD_ADDR(n) (KVM_VPD_BASE+n*VPD_SIZE)
114#define VHPT_ADDR(n) (KVM_VHPT_BASE+n*VHPT_SIZE)
115#define VTLB_ADDR(n) (KVM_VTLB_BASE+n*VTLB_SIZE)
116#define VCPU_ADDR(n) (KVM_VCPU_BASE+n*VCPU_SIZE)
117
118/*IO section definitions*/
119#define IOREQ_READ 1
120#define IOREQ_WRITE 0
121
122#define STATE_IOREQ_NONE 0
123#define STATE_IOREQ_READY 1
124#define STATE_IOREQ_INPROCESS 2
125#define STATE_IORESP_READY 3
126
127/*Guest Physical address layout.*/
128#define GPFN_MEM (0UL << 60) /* Guest pfn is normal mem */
129#define GPFN_FRAME_BUFFER (1UL << 60) /* VGA framebuffer */
130#define GPFN_LOW_MMIO (2UL << 60) /* Low MMIO range */
131#define GPFN_PIB (3UL << 60) /* PIB base */
132#define GPFN_IOSAPIC (4UL << 60) /* IOSAPIC base */
133#define GPFN_LEGACY_IO (5UL << 60) /* Legacy I/O base */
134#define GPFN_GFW (6UL << 60) /* Guest Firmware */
135#define GPFN_HIGH_MMIO (7UL << 60) /* High MMIO range */
136
137#define GPFN_IO_MASK (7UL << 60) /* Guest pfn is I/O type */
138#define GPFN_INV_MASK (1UL << 63) /* Guest pfn is invalid */
139#define INVALID_MFN (~0UL)
140#define MEM_G (1UL << 30)
141#define MEM_M (1UL << 20)
142#define MMIO_START (3 * MEM_G)
143#define MMIO_SIZE (512 * MEM_M)
144#define VGA_IO_START 0xA0000UL
145#define VGA_IO_SIZE 0x20000
146#define LEGACY_IO_START (MMIO_START + MMIO_SIZE)
147#define LEGACY_IO_SIZE (64 * MEM_M)
148#define IO_SAPIC_START 0xfec00000UL
149#define IO_SAPIC_SIZE 0x100000
150#define PIB_START 0xfee00000UL
151#define PIB_SIZE 0x200000
152#define GFW_START (4 * MEM_G - 16 * MEM_M)
153#define GFW_SIZE (16 * MEM_M)
154
155/*Deliver mode, defined for ioapic.c*/
156#define dest_Fixed IOSAPIC_FIXED
157#define dest_LowestPrio IOSAPIC_LOWEST_PRIORITY
158
159#define NMI_VECTOR 2
160#define ExtINT_VECTOR 0
161#define NULL_VECTOR (-1)
162#define IA64_SPURIOUS_INT_VECTOR 0x0f
163
164#define VCPU_LID(v) (((u64)(v)->vcpu_id) << 24)
165
166/*
167 *Delivery mode
168 */
169#define SAPIC_DELIV_SHIFT 8
170#define SAPIC_FIXED 0x0
171#define SAPIC_LOWEST_PRIORITY 0x1
172#define SAPIC_PMI 0x2
173#define SAPIC_NMI 0x4
174#define SAPIC_INIT 0x5
175#define SAPIC_EXTINT 0x7
176
177/*
178 * vcpu->requests bit members for arch
179 */
180#define KVM_REQ_PTC_G 32
181#define KVM_REQ_RESUME 33
182
183#define KVM_PAGES_PER_HPAGE 1
184
185struct kvm;
186struct kvm_vcpu;
187struct kvm_guest_debug{
188};
189
190struct kvm_mmio_req {
191 uint64_t addr; /* physical address */
192 uint64_t size; /* size in bytes */
193 uint64_t data; /* data (or paddr of data) */
194 uint8_t state:4;
195 uint8_t dir:1; /* 1=read, 0=write */
196};
197
198/*Pal data struct */
199struct kvm_pal_call{
200 /*In area*/
201 uint64_t gr28;
202 uint64_t gr29;
203 uint64_t gr30;
204 uint64_t gr31;
205 /*Out area*/
206 struct ia64_pal_retval ret;
207};
208
209/* Sal data structure */
210struct kvm_sal_call{
211 /*In area*/
212 uint64_t in0;
213 uint64_t in1;
214 uint64_t in2;
215 uint64_t in3;
216 uint64_t in4;
217 uint64_t in5;
218 uint64_t in6;
219 uint64_t in7;
220 struct sal_ret_values ret;
221};
222
223/*Guest change rr6*/
224struct kvm_switch_rr6 {
225 uint64_t old_rr;
226 uint64_t new_rr;
227};
228
229union ia64_ipi_a{
230 unsigned long val;
231 struct {
232 unsigned long rv : 3;
233 unsigned long ir : 1;
234 unsigned long eid : 8;
235 unsigned long id : 8;
236 unsigned long ib_base : 44;
237 };
238};
239
240union ia64_ipi_d {
241 unsigned long val;
242 struct {
243 unsigned long vector : 8;
244 unsigned long dm : 3;
245 unsigned long ig : 53;
246 };
247};
248
249/*ipi check exit data*/
250struct kvm_ipi_data{
251 union ia64_ipi_a addr;
252 union ia64_ipi_d data;
253};
254
255/*global purge data*/
256struct kvm_ptc_g {
257 unsigned long vaddr;
258 unsigned long rr;
259 unsigned long ps;
260 struct kvm_vcpu *vcpu;
261};
262
263/*Exit control data */
264struct exit_ctl_data{
265 uint32_t exit_reason;
266 uint32_t vm_status;
267 union {
268 struct kvm_mmio_req ioreq;
269 struct kvm_pal_call pal_data;
270 struct kvm_sal_call sal_data;
271 struct kvm_switch_rr6 rr_data;
272 struct kvm_ipi_data ipi_data;
273 struct kvm_ptc_g ptc_g_data;
274 } u;
275};
276
277union pte_flags {
278 unsigned long val;
279 struct {
280 unsigned long p : 1; /*0 */
281 unsigned long : 1; /* 1 */
282 unsigned long ma : 3; /* 2-4 */
283 unsigned long a : 1; /* 5 */
284 unsigned long d : 1; /* 6 */
285 unsigned long pl : 2; /* 7-8 */
286 unsigned long ar : 3; /* 9-11 */
287 unsigned long ppn : 38; /* 12-49 */
288 unsigned long : 2; /* 50-51 */
289 unsigned long ed : 1; /* 52 */
290 };
291};
292
293union ia64_pta {
294 unsigned long val;
295 struct {
296 unsigned long ve : 1;
297 unsigned long reserved0 : 1;
298 unsigned long size : 6;
299 unsigned long vf : 1;
300 unsigned long reserved1 : 6;
301 unsigned long base : 49;
302 };
303};
304
305struct thash_cb {
306 /* THASH base information */
307 struct thash_data *hash; /* hash table pointer */
308 union ia64_pta pta;
309 int num;
310};
311
312struct kvm_vcpu_stat {
313};
314
315struct kvm_vcpu_arch {
316 int launched;
317 int last_exit;
318 int last_run_cpu;
319 int vmm_tr_slot;
320 int vm_tr_slot;
321
322#define KVM_MP_STATE_RUNNABLE 0
323#define KVM_MP_STATE_UNINITIALIZED 1
324#define KVM_MP_STATE_INIT_RECEIVED 2
325#define KVM_MP_STATE_HALTED 3
326 int mp_state;
327
328#define MAX_PTC_G_NUM 3
329 int ptc_g_count;
330 struct kvm_ptc_g ptc_g_data[MAX_PTC_G_NUM];
331
332 /*halt timer to wake up sleepy vcpus*/
333 struct hrtimer hlt_timer;
334 long ht_active;
335
336 struct kvm_lapic *apic; /* kernel irqchip context */
337 struct vpd *vpd;
338
339 /* Exit data for vmm_transition*/
340 struct exit_ctl_data exit_data;
341
342 cpumask_t cache_coherent_map;
343
344 unsigned long vmm_rr;
345 unsigned long host_rr6;
346 unsigned long psbits[8];
347 unsigned long cr_iipa;
348 unsigned long cr_isr;
349 unsigned long vsa_base;
350 unsigned long dirty_log_lock_pa;
351 unsigned long __gp;
352 /* TR and TC. */
353 struct thash_data itrs[NITRS];
354 struct thash_data dtrs[NDTRS];
355 /* Bit is set if there is a tr/tc for the region. */
356 unsigned char itr_regions;
357 unsigned char dtr_regions;
358 unsigned char tc_regions;
359 /* purge all */
360 unsigned long ptce_base;
361 unsigned long ptce_count[2];
362 unsigned long ptce_stride[2];
363 /* itc/itm */
364 unsigned long last_itc;
365 long itc_offset;
366 unsigned long itc_check;
367 unsigned long timer_check;
368 unsigned long timer_pending;
369
370 unsigned long vrr[8];
371 unsigned long ibr[8];
372 unsigned long dbr[8];
373 unsigned long insvc[4]; /* Interrupt in service. */
374 unsigned long xtp;
375
376 unsigned long metaphysical_rr0; /* from kvm_arch (so is pinned) */
377 unsigned long metaphysical_rr4; /* from kvm_arch (so is pinned) */
378 unsigned long metaphysical_saved_rr0; /* from kvm_arch */
379 unsigned long metaphysical_saved_rr4; /* from kvm_arch */
380 unsigned long fp_psr; /*used for lazy float register */
381 unsigned long saved_gp;
382 /*for phycial emulation */
383 int mode_flags;
384 struct thash_cb vtlb;
385 struct thash_cb vhpt;
386 char irq_check;
387 char irq_new_pending;
388
389 unsigned long opcode;
390 unsigned long cause;
391 union context host;
392 union context guest;
393};
394
395struct kvm_vm_stat {
396 u64 remote_tlb_flush;
397};
398
399struct kvm_sal_data {
400 unsigned long boot_ip;
401 unsigned long boot_gp;
402};
403
404struct kvm_arch {
405 unsigned long vm_base;
406 unsigned long metaphysical_rr0;
407 unsigned long metaphysical_rr4;
408 unsigned long vmm_init_rr;
409 unsigned long vhpt_base;
410 unsigned long vtlb_base;
411 unsigned long vpd_base;
412 spinlock_t dirty_log_lock;
413 struct kvm_ioapic *vioapic;
414 struct kvm_vm_stat stat;
415 struct kvm_sal_data rdv_sal_data;
416};
417
418union cpuid3_t {
419 u64 value;
420 struct {
421 u64 number : 8;
422 u64 revision : 8;
423 u64 model : 8;
424 u64 family : 8;
425 u64 archrev : 8;
426 u64 rv : 24;
427 };
428};
429
430struct kvm_pt_regs {
431 /* The following registers are saved by SAVE_MIN: */
432 unsigned long b6; /* scratch */
433 unsigned long b7; /* scratch */
434
435 unsigned long ar_csd; /* used by cmp8xchg16 (scratch) */
436 unsigned long ar_ssd; /* reserved for future use (scratch) */
437
438 unsigned long r8; /* scratch (return value register 0) */
439 unsigned long r9; /* scratch (return value register 1) */
440 unsigned long r10; /* scratch (return value register 2) */
441 unsigned long r11; /* scratch (return value register 3) */
442
443 unsigned long cr_ipsr; /* interrupted task's psr */
444 unsigned long cr_iip; /* interrupted task's instruction pointer */
445 unsigned long cr_ifs; /* interrupted task's function state */
446
447 unsigned long ar_unat; /* interrupted task's NaT register (preserved) */
448 unsigned long ar_pfs; /* prev function state */
449 unsigned long ar_rsc; /* RSE configuration */
450 /* The following two are valid only if cr_ipsr.cpl > 0: */
451 unsigned long ar_rnat; /* RSE NaT */
452 unsigned long ar_bspstore; /* RSE bspstore */
453
454 unsigned long pr; /* 64 predicate registers (1 bit each) */
455 unsigned long b0; /* return pointer (bp) */
456 unsigned long loadrs; /* size of dirty partition << 16 */
457
458 unsigned long r1; /* the gp pointer */
459 unsigned long r12; /* interrupted task's memory stack pointer */
460 unsigned long r13; /* thread pointer */
461
462 unsigned long ar_fpsr; /* floating point status (preserved) */
463 unsigned long r15; /* scratch */
464
465 /* The remaining registers are NOT saved for system calls. */
466 unsigned long r14; /* scratch */
467 unsigned long r2; /* scratch */
468 unsigned long r3; /* scratch */
469 unsigned long r16; /* scratch */
470 unsigned long r17; /* scratch */
471 unsigned long r18; /* scratch */
472 unsigned long r19; /* scratch */
473 unsigned long r20; /* scratch */
474 unsigned long r21; /* scratch */
475 unsigned long r22; /* scratch */
476 unsigned long r23; /* scratch */
477 unsigned long r24; /* scratch */
478 unsigned long r25; /* scratch */
479 unsigned long r26; /* scratch */
480 unsigned long r27; /* scratch */
481 unsigned long r28; /* scratch */
482 unsigned long r29; /* scratch */
483 unsigned long r30; /* scratch */
484 unsigned long r31; /* scratch */
485 unsigned long ar_ccv; /* compare/exchange value (scratch) */
486
487 /*
488 * Floating point registers that the kernel considers scratch:
489 */
490 struct ia64_fpreg f6; /* scratch */
491 struct ia64_fpreg f7; /* scratch */
492 struct ia64_fpreg f8; /* scratch */
493 struct ia64_fpreg f9; /* scratch */
494 struct ia64_fpreg f10; /* scratch */
495 struct ia64_fpreg f11; /* scratch */
496
497 unsigned long r4; /* preserved */
498 unsigned long r5; /* preserved */
499 unsigned long r6; /* preserved */
500 unsigned long r7; /* preserved */
501 unsigned long eml_unat; /* used for emulating instruction */
502 unsigned long pad0; /* alignment pad */
503};
504
505static inline struct kvm_pt_regs *vcpu_regs(struct kvm_vcpu *v)
506{
507 return (struct kvm_pt_regs *) ((unsigned long) v + IA64_STK_OFFSET) - 1;
508}
509
510typedef int kvm_vmm_entry(void);
511typedef void kvm_tramp_entry(union context *host, union context *guest);
512
513struct kvm_vmm_info{
514 struct module *module;
515 kvm_vmm_entry *vmm_entry;
516 kvm_tramp_entry *tramp_entry;
517 unsigned long vmm_ivt;
518};
519
520int kvm_highest_pending_irq(struct kvm_vcpu *vcpu);
521int kvm_emulate_halt(struct kvm_vcpu *vcpu);
522int kvm_pal_emul(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run);
523void kvm_sal_emul(struct kvm_vcpu *vcpu);
524
525static inline void kvm_inject_nmi(struct kvm_vcpu *vcpu) {}
526
527#endif
diff --git a/include/asm-ia64/kvm_para.h b/include/asm-ia64/kvm_para.h
deleted file mode 100644
index 9f9796bb344..00000000000
--- a/include/asm-ia64/kvm_para.h
+++ /dev/null
@@ -1,29 +0,0 @@
1#ifndef __IA64_KVM_PARA_H
2#define __IA64_KVM_PARA_H
3
4/*
5 * asm-ia64/kvm_para.h
6 *
7 * Copyright (C) 2007 Xiantao Zhang <xiantao.zhang@intel.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
20 * Place - Suite 330, Boston, MA 02111-1307 USA.
21 *
22 */
23
24static inline unsigned int kvm_arch_para_features(void)
25{
26 return 0;
27}
28
29#endif
diff --git a/include/asm-ia64/libata-portmap.h b/include/asm-ia64/libata-portmap.h
deleted file mode 100644
index 0e00c9a9f41..00000000000
--- a/include/asm-ia64/libata-portmap.h
+++ /dev/null
@@ -1,12 +0,0 @@
1#ifndef __ASM_IA64_LIBATA_PORTMAP_H
2#define __ASM_IA64_LIBATA_PORTMAP_H
3
4#define ATA_PRIMARY_CMD 0x1F0
5#define ATA_PRIMARY_CTL 0x3F6
6#define ATA_PRIMARY_IRQ(dev) isa_irq_to_vector(14)
7
8#define ATA_SECONDARY_CMD 0x170
9#define ATA_SECONDARY_CTL 0x376
10#define ATA_SECONDARY_IRQ(dev) isa_irq_to_vector(15)
11
12#endif
diff --git a/include/asm-ia64/linkage.h b/include/asm-ia64/linkage.h
deleted file mode 100644
index ef22a45c189..00000000000
--- a/include/asm-ia64/linkage.h
+++ /dev/null
@@ -1,14 +0,0 @@
1#ifndef __ASM_LINKAGE_H
2#define __ASM_LINKAGE_H
3
4#ifndef __ASSEMBLY__
5
6#define asmlinkage CPP_ASMLINKAGE __attribute__((syscall_linkage))
7
8#else
9
10#include <asm/asmmacro.h>
11
12#endif
13
14#endif
diff --git a/include/asm-ia64/local.h b/include/asm-ia64/local.h
deleted file mode 100644
index c11c530f74d..00000000000
--- a/include/asm-ia64/local.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/local.h>
diff --git a/include/asm-ia64/machvec.h b/include/asm-ia64/machvec.h
deleted file mode 100644
index a6d50c77b6b..00000000000
--- a/include/asm-ia64/machvec.h
+++ /dev/null
@@ -1,460 +0,0 @@
1/*
2 * Machine vector for IA-64.
3 *
4 * Copyright (C) 1999 Silicon Graphics, Inc.
5 * Copyright (C) Srinivasa Thirumalachar <sprasad@engr.sgi.com>
6 * Copyright (C) Vijay Chander <vijay@engr.sgi.com>
7 * Copyright (C) 1999-2001, 2003-2004 Hewlett-Packard Co.
8 * David Mosberger-Tang <davidm@hpl.hp.com>
9 */
10#ifndef _ASM_IA64_MACHVEC_H
11#define _ASM_IA64_MACHVEC_H
12
13#include <linux/types.h>
14
15/* forward declarations: */
16struct device;
17struct pt_regs;
18struct scatterlist;
19struct page;
20struct mm_struct;
21struct pci_bus;
22struct task_struct;
23struct pci_dev;
24struct msi_desc;
25struct dma_attrs;
26
27typedef void ia64_mv_setup_t (char **);
28typedef void ia64_mv_cpu_init_t (void);
29typedef void ia64_mv_irq_init_t (void);
30typedef void ia64_mv_send_ipi_t (int, int, int, int);
31typedef void ia64_mv_timer_interrupt_t (int, void *);
32typedef void ia64_mv_global_tlb_purge_t (struct mm_struct *, unsigned long, unsigned long, unsigned long);
33typedef void ia64_mv_tlb_migrate_finish_t (struct mm_struct *);
34typedef u8 ia64_mv_irq_to_vector (int);
35typedef unsigned int ia64_mv_local_vector_to_irq (u8);
36typedef char *ia64_mv_pci_get_legacy_mem_t (struct pci_bus *);
37typedef int ia64_mv_pci_legacy_read_t (struct pci_bus *, u16 port, u32 *val,
38 u8 size);
39typedef int ia64_mv_pci_legacy_write_t (struct pci_bus *, u16 port, u32 val,
40 u8 size);
41typedef void ia64_mv_migrate_t(struct task_struct * task);
42typedef void ia64_mv_pci_fixup_bus_t (struct pci_bus *);
43typedef void ia64_mv_kernel_launch_event_t(void);
44
45/* DMA-mapping interface: */
46typedef void ia64_mv_dma_init (void);
47typedef void *ia64_mv_dma_alloc_coherent (struct device *, size_t, dma_addr_t *, gfp_t);
48typedef void ia64_mv_dma_free_coherent (struct device *, size_t, void *, dma_addr_t);
49typedef dma_addr_t ia64_mv_dma_map_single (struct device *, void *, size_t, int);
50typedef void ia64_mv_dma_unmap_single (struct device *, dma_addr_t, size_t, int);
51typedef int ia64_mv_dma_map_sg (struct device *, struct scatterlist *, int, int);
52typedef void ia64_mv_dma_unmap_sg (struct device *, struct scatterlist *, int, int);
53typedef void ia64_mv_dma_sync_single_for_cpu (struct device *, dma_addr_t, size_t, int);
54typedef void ia64_mv_dma_sync_sg_for_cpu (struct device *, struct scatterlist *, int, int);
55typedef void ia64_mv_dma_sync_single_for_device (struct device *, dma_addr_t, size_t, int);
56typedef void ia64_mv_dma_sync_sg_for_device (struct device *, struct scatterlist *, int, int);
57typedef int ia64_mv_dma_mapping_error(struct device *, dma_addr_t dma_addr);
58typedef int ia64_mv_dma_supported (struct device *, u64);
59
60typedef dma_addr_t ia64_mv_dma_map_single_attrs (struct device *, void *, size_t, int, struct dma_attrs *);
61typedef void ia64_mv_dma_unmap_single_attrs (struct device *, dma_addr_t, size_t, int, struct dma_attrs *);
62typedef int ia64_mv_dma_map_sg_attrs (struct device *, struct scatterlist *, int, int, struct dma_attrs *);
63typedef void ia64_mv_dma_unmap_sg_attrs (struct device *, struct scatterlist *, int, int, struct dma_attrs *);
64
65/*
66 * WARNING: The legacy I/O space is _architected_. Platforms are
67 * expected to follow this architected model (see Section 10.7 in the
68 * IA-64 Architecture Software Developer's Manual). Unfortunately,
69 * some broken machines do not follow that model, which is why we have
70 * to make the inX/outX operations part of the machine vector.
71 * Platform designers should follow the architected model whenever
72 * possible.
73 */
74typedef unsigned int ia64_mv_inb_t (unsigned long);
75typedef unsigned int ia64_mv_inw_t (unsigned long);
76typedef unsigned int ia64_mv_inl_t (unsigned long);
77typedef void ia64_mv_outb_t (unsigned char, unsigned long);
78typedef void ia64_mv_outw_t (unsigned short, unsigned long);
79typedef void ia64_mv_outl_t (unsigned int, unsigned long);
80typedef void ia64_mv_mmiowb_t (void);
81typedef unsigned char ia64_mv_readb_t (const volatile void __iomem *);
82typedef unsigned short ia64_mv_readw_t (const volatile void __iomem *);
83typedef unsigned int ia64_mv_readl_t (const volatile void __iomem *);
84typedef unsigned long ia64_mv_readq_t (const volatile void __iomem *);
85typedef unsigned char ia64_mv_readb_relaxed_t (const volatile void __iomem *);
86typedef unsigned short ia64_mv_readw_relaxed_t (const volatile void __iomem *);
87typedef unsigned int ia64_mv_readl_relaxed_t (const volatile void __iomem *);
88typedef unsigned long ia64_mv_readq_relaxed_t (const volatile void __iomem *);
89
90typedef int ia64_mv_setup_msi_irq_t (struct pci_dev *pdev, struct msi_desc *);
91typedef void ia64_mv_teardown_msi_irq_t (unsigned int irq);
92
93static inline void
94machvec_noop (void)
95{
96}
97
98static inline void
99machvec_noop_mm (struct mm_struct *mm)
100{
101}
102
103static inline void
104machvec_noop_task (struct task_struct *task)
105{
106}
107
108static inline void
109machvec_noop_bus (struct pci_bus *bus)
110{
111}
112
113extern void machvec_setup (char **);
114extern void machvec_timer_interrupt (int, void *);
115extern void machvec_dma_sync_single (struct device *, dma_addr_t, size_t, int);
116extern void machvec_dma_sync_sg (struct device *, struct scatterlist *, int, int);
117extern void machvec_tlb_migrate_finish (struct mm_struct *);
118
119# if defined (CONFIG_IA64_HP_SIM)
120# include <asm/machvec_hpsim.h>
121# elif defined (CONFIG_IA64_DIG)
122# include <asm/machvec_dig.h>
123# elif defined (CONFIG_IA64_HP_ZX1)
124# include <asm/machvec_hpzx1.h>
125# elif defined (CONFIG_IA64_HP_ZX1_SWIOTLB)
126# include <asm/machvec_hpzx1_swiotlb.h>
127# elif defined (CONFIG_IA64_SGI_SN2)
128# include <asm/machvec_sn2.h>
129# elif defined (CONFIG_IA64_SGI_UV)
130# include <asm/machvec_uv.h>
131# elif defined (CONFIG_IA64_GENERIC)
132
133# ifdef MACHVEC_PLATFORM_HEADER
134# include MACHVEC_PLATFORM_HEADER
135# else
136# define platform_name ia64_mv.name
137# define platform_setup ia64_mv.setup
138# define platform_cpu_init ia64_mv.cpu_init
139# define platform_irq_init ia64_mv.irq_init
140# define platform_send_ipi ia64_mv.send_ipi
141# define platform_timer_interrupt ia64_mv.timer_interrupt
142# define platform_global_tlb_purge ia64_mv.global_tlb_purge
143# define platform_tlb_migrate_finish ia64_mv.tlb_migrate_finish
144# define platform_dma_init ia64_mv.dma_init
145# define platform_dma_alloc_coherent ia64_mv.dma_alloc_coherent
146# define platform_dma_free_coherent ia64_mv.dma_free_coherent
147# define platform_dma_map_single_attrs ia64_mv.dma_map_single_attrs
148# define platform_dma_unmap_single_attrs ia64_mv.dma_unmap_single_attrs
149# define platform_dma_map_sg_attrs ia64_mv.dma_map_sg_attrs
150# define platform_dma_unmap_sg_attrs ia64_mv.dma_unmap_sg_attrs
151# define platform_dma_sync_single_for_cpu ia64_mv.dma_sync_single_for_cpu
152# define platform_dma_sync_sg_for_cpu ia64_mv.dma_sync_sg_for_cpu
153# define platform_dma_sync_single_for_device ia64_mv.dma_sync_single_for_device
154# define platform_dma_sync_sg_for_device ia64_mv.dma_sync_sg_for_device
155# define platform_dma_mapping_error ia64_mv.dma_mapping_error
156# define platform_dma_supported ia64_mv.dma_supported
157# define platform_irq_to_vector ia64_mv.irq_to_vector
158# define platform_local_vector_to_irq ia64_mv.local_vector_to_irq
159# define platform_pci_get_legacy_mem ia64_mv.pci_get_legacy_mem
160# define platform_pci_legacy_read ia64_mv.pci_legacy_read
161# define platform_pci_legacy_write ia64_mv.pci_legacy_write
162# define platform_inb ia64_mv.inb
163# define platform_inw ia64_mv.inw
164# define platform_inl ia64_mv.inl
165# define platform_outb ia64_mv.outb
166# define platform_outw ia64_mv.outw
167# define platform_outl ia64_mv.outl
168# define platform_mmiowb ia64_mv.mmiowb
169# define platform_readb ia64_mv.readb
170# define platform_readw ia64_mv.readw
171# define platform_readl ia64_mv.readl
172# define platform_readq ia64_mv.readq
173# define platform_readb_relaxed ia64_mv.readb_relaxed
174# define platform_readw_relaxed ia64_mv.readw_relaxed
175# define platform_readl_relaxed ia64_mv.readl_relaxed
176# define platform_readq_relaxed ia64_mv.readq_relaxed
177# define platform_migrate ia64_mv.migrate
178# define platform_setup_msi_irq ia64_mv.setup_msi_irq
179# define platform_teardown_msi_irq ia64_mv.teardown_msi_irq
180# define platform_pci_fixup_bus ia64_mv.pci_fixup_bus
181# define platform_kernel_launch_event ia64_mv.kernel_launch_event
182# endif
183
184/* __attribute__((__aligned__(16))) is required to make size of the
185 * structure multiple of 16 bytes.
186 * This will fillup the holes created because of section 3.3.1 in
187 * Software Conventions guide.
188 */
189struct ia64_machine_vector {
190 const char *name;
191 ia64_mv_setup_t *setup;
192 ia64_mv_cpu_init_t *cpu_init;
193 ia64_mv_irq_init_t *irq_init;
194 ia64_mv_send_ipi_t *send_ipi;
195 ia64_mv_timer_interrupt_t *timer_interrupt;
196 ia64_mv_global_tlb_purge_t *global_tlb_purge;
197 ia64_mv_tlb_migrate_finish_t *tlb_migrate_finish;
198 ia64_mv_dma_init *dma_init;
199 ia64_mv_dma_alloc_coherent *dma_alloc_coherent;
200 ia64_mv_dma_free_coherent *dma_free_coherent;
201 ia64_mv_dma_map_single_attrs *dma_map_single_attrs;
202 ia64_mv_dma_unmap_single_attrs *dma_unmap_single_attrs;
203 ia64_mv_dma_map_sg_attrs *dma_map_sg_attrs;
204 ia64_mv_dma_unmap_sg_attrs *dma_unmap_sg_attrs;
205 ia64_mv_dma_sync_single_for_cpu *dma_sync_single_for_cpu;
206 ia64_mv_dma_sync_sg_for_cpu *dma_sync_sg_for_cpu;
207 ia64_mv_dma_sync_single_for_device *dma_sync_single_for_device;
208 ia64_mv_dma_sync_sg_for_device *dma_sync_sg_for_device;
209 ia64_mv_dma_mapping_error *dma_mapping_error;
210 ia64_mv_dma_supported *dma_supported;
211 ia64_mv_irq_to_vector *irq_to_vector;
212 ia64_mv_local_vector_to_irq *local_vector_to_irq;
213 ia64_mv_pci_get_legacy_mem_t *pci_get_legacy_mem;
214 ia64_mv_pci_legacy_read_t *pci_legacy_read;
215 ia64_mv_pci_legacy_write_t *pci_legacy_write;
216 ia64_mv_inb_t *inb;
217 ia64_mv_inw_t *inw;
218 ia64_mv_inl_t *inl;
219 ia64_mv_outb_t *outb;
220 ia64_mv_outw_t *outw;
221 ia64_mv_outl_t *outl;
222 ia64_mv_mmiowb_t *mmiowb;
223 ia64_mv_readb_t *readb;
224 ia64_mv_readw_t *readw;
225 ia64_mv_readl_t *readl;
226 ia64_mv_readq_t *readq;
227 ia64_mv_readb_relaxed_t *readb_relaxed;
228 ia64_mv_readw_relaxed_t *readw_relaxed;
229 ia64_mv_readl_relaxed_t *readl_relaxed;
230 ia64_mv_readq_relaxed_t *readq_relaxed;
231 ia64_mv_migrate_t *migrate;
232 ia64_mv_setup_msi_irq_t *setup_msi_irq;
233 ia64_mv_teardown_msi_irq_t *teardown_msi_irq;
234 ia64_mv_pci_fixup_bus_t *pci_fixup_bus;
235 ia64_mv_kernel_launch_event_t *kernel_launch_event;
236} __attribute__((__aligned__(16))); /* align attrib? see above comment */
237
238#define MACHVEC_INIT(name) \
239{ \
240 #name, \
241 platform_setup, \
242 platform_cpu_init, \
243 platform_irq_init, \
244 platform_send_ipi, \
245 platform_timer_interrupt, \
246 platform_global_tlb_purge, \
247 platform_tlb_migrate_finish, \
248 platform_dma_init, \
249 platform_dma_alloc_coherent, \
250 platform_dma_free_coherent, \
251 platform_dma_map_single_attrs, \
252 platform_dma_unmap_single_attrs, \
253 platform_dma_map_sg_attrs, \
254 platform_dma_unmap_sg_attrs, \
255 platform_dma_sync_single_for_cpu, \
256 platform_dma_sync_sg_for_cpu, \
257 platform_dma_sync_single_for_device, \
258 platform_dma_sync_sg_for_device, \
259 platform_dma_mapping_error, \
260 platform_dma_supported, \
261 platform_irq_to_vector, \
262 platform_local_vector_to_irq, \
263 platform_pci_get_legacy_mem, \
264 platform_pci_legacy_read, \
265 platform_pci_legacy_write, \
266 platform_inb, \
267 platform_inw, \
268 platform_inl, \
269 platform_outb, \
270 platform_outw, \
271 platform_outl, \
272 platform_mmiowb, \
273 platform_readb, \
274 platform_readw, \
275 platform_readl, \
276 platform_readq, \
277 platform_readb_relaxed, \
278 platform_readw_relaxed, \
279 platform_readl_relaxed, \
280 platform_readq_relaxed, \
281 platform_migrate, \
282 platform_setup_msi_irq, \
283 platform_teardown_msi_irq, \
284 platform_pci_fixup_bus, \
285 platform_kernel_launch_event \
286}
287
288extern struct ia64_machine_vector ia64_mv;
289extern void machvec_init (const char *name);
290extern void machvec_init_from_cmdline(const char *cmdline);
291
292# else
293# error Unknown configuration. Update asm-ia64/machvec.h.
294# endif /* CONFIG_IA64_GENERIC */
295
296/*
297 * Declare default routines which aren't declared anywhere else:
298 */
299extern ia64_mv_dma_init swiotlb_init;
300extern ia64_mv_dma_alloc_coherent swiotlb_alloc_coherent;
301extern ia64_mv_dma_free_coherent swiotlb_free_coherent;
302extern ia64_mv_dma_map_single swiotlb_map_single;
303extern ia64_mv_dma_map_single_attrs swiotlb_map_single_attrs;
304extern ia64_mv_dma_unmap_single swiotlb_unmap_single;
305extern ia64_mv_dma_unmap_single_attrs swiotlb_unmap_single_attrs;
306extern ia64_mv_dma_map_sg swiotlb_map_sg;
307extern ia64_mv_dma_map_sg_attrs swiotlb_map_sg_attrs;
308extern ia64_mv_dma_unmap_sg swiotlb_unmap_sg;
309extern ia64_mv_dma_unmap_sg_attrs swiotlb_unmap_sg_attrs;
310extern ia64_mv_dma_sync_single_for_cpu swiotlb_sync_single_for_cpu;
311extern ia64_mv_dma_sync_sg_for_cpu swiotlb_sync_sg_for_cpu;
312extern ia64_mv_dma_sync_single_for_device swiotlb_sync_single_for_device;
313extern ia64_mv_dma_sync_sg_for_device swiotlb_sync_sg_for_device;
314extern ia64_mv_dma_mapping_error swiotlb_dma_mapping_error;
315extern ia64_mv_dma_supported swiotlb_dma_supported;
316
317/*
318 * Define default versions so we can extend machvec for new platforms without having
319 * to update the machvec files for all existing platforms.
320 */
321#ifndef platform_setup
322# define platform_setup machvec_setup
323#endif
324#ifndef platform_cpu_init
325# define platform_cpu_init machvec_noop
326#endif
327#ifndef platform_irq_init
328# define platform_irq_init machvec_noop
329#endif
330
331#ifndef platform_send_ipi
332# define platform_send_ipi ia64_send_ipi /* default to architected version */
333#endif
334#ifndef platform_timer_interrupt
335# define platform_timer_interrupt machvec_timer_interrupt
336#endif
337#ifndef platform_global_tlb_purge
338# define platform_global_tlb_purge ia64_global_tlb_purge /* default to architected version */
339#endif
340#ifndef platform_tlb_migrate_finish
341# define platform_tlb_migrate_finish machvec_noop_mm
342#endif
343#ifndef platform_kernel_launch_event
344# define platform_kernel_launch_event machvec_noop
345#endif
346#ifndef platform_dma_init
347# define platform_dma_init swiotlb_init
348#endif
349#ifndef platform_dma_alloc_coherent
350# define platform_dma_alloc_coherent swiotlb_alloc_coherent
351#endif
352#ifndef platform_dma_free_coherent
353# define platform_dma_free_coherent swiotlb_free_coherent
354#endif
355#ifndef platform_dma_map_single_attrs
356# define platform_dma_map_single_attrs swiotlb_map_single_attrs
357#endif
358#ifndef platform_dma_unmap_single_attrs
359# define platform_dma_unmap_single_attrs swiotlb_unmap_single_attrs
360#endif
361#ifndef platform_dma_map_sg_attrs
362# define platform_dma_map_sg_attrs swiotlb_map_sg_attrs
363#endif
364#ifndef platform_dma_unmap_sg_attrs
365# define platform_dma_unmap_sg_attrs swiotlb_unmap_sg_attrs
366#endif
367#ifndef platform_dma_sync_single_for_cpu
368# define platform_dma_sync_single_for_cpu swiotlb_sync_single_for_cpu
369#endif
370#ifndef platform_dma_sync_sg_for_cpu
371# define platform_dma_sync_sg_for_cpu swiotlb_sync_sg_for_cpu
372#endif
373#ifndef platform_dma_sync_single_for_device
374# define platform_dma_sync_single_for_device swiotlb_sync_single_for_device
375#endif
376#ifndef platform_dma_sync_sg_for_device
377# define platform_dma_sync_sg_for_device swiotlb_sync_sg_for_device
378#endif
379#ifndef platform_dma_mapping_error
380# define platform_dma_mapping_error swiotlb_dma_mapping_error
381#endif
382#ifndef platform_dma_supported
383# define platform_dma_supported swiotlb_dma_supported
384#endif
385#ifndef platform_irq_to_vector
386# define platform_irq_to_vector __ia64_irq_to_vector
387#endif
388#ifndef platform_local_vector_to_irq
389# define platform_local_vector_to_irq __ia64_local_vector_to_irq
390#endif
391#ifndef platform_pci_get_legacy_mem
392# define platform_pci_get_legacy_mem ia64_pci_get_legacy_mem
393#endif
394#ifndef platform_pci_legacy_read
395# define platform_pci_legacy_read ia64_pci_legacy_read
396extern int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size);
397#endif
398#ifndef platform_pci_legacy_write
399# define platform_pci_legacy_write ia64_pci_legacy_write
400extern int ia64_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size);
401#endif
402#ifndef platform_inb
403# define platform_inb __ia64_inb
404#endif
405#ifndef platform_inw
406# define platform_inw __ia64_inw
407#endif
408#ifndef platform_inl
409# define platform_inl __ia64_inl
410#endif
411#ifndef platform_outb
412# define platform_outb __ia64_outb
413#endif
414#ifndef platform_outw
415# define platform_outw __ia64_outw
416#endif
417#ifndef platform_outl
418# define platform_outl __ia64_outl
419#endif
420#ifndef platform_mmiowb
421# define platform_mmiowb __ia64_mmiowb
422#endif
423#ifndef platform_readb
424# define platform_readb __ia64_readb
425#endif
426#ifndef platform_readw
427# define platform_readw __ia64_readw
428#endif
429#ifndef platform_readl
430# define platform_readl __ia64_readl
431#endif
432#ifndef platform_readq
433# define platform_readq __ia64_readq
434#endif
435#ifndef platform_readb_relaxed
436# define platform_readb_relaxed __ia64_readb_relaxed
437#endif
438#ifndef platform_readw_relaxed
439# define platform_readw_relaxed __ia64_readw_relaxed
440#endif
441#ifndef platform_readl_relaxed
442# define platform_readl_relaxed __ia64_readl_relaxed
443#endif
444#ifndef platform_readq_relaxed
445# define platform_readq_relaxed __ia64_readq_relaxed
446#endif
447#ifndef platform_migrate
448# define platform_migrate machvec_noop_task
449#endif
450#ifndef platform_setup_msi_irq
451# define platform_setup_msi_irq ((ia64_mv_setup_msi_irq_t*)NULL)
452#endif
453#ifndef platform_teardown_msi_irq
454# define platform_teardown_msi_irq ((ia64_mv_teardown_msi_irq_t*)NULL)
455#endif
456#ifndef platform_pci_fixup_bus
457# define platform_pci_fixup_bus machvec_noop_bus
458#endif
459
460#endif /* _ASM_IA64_MACHVEC_H */
diff --git a/include/asm-ia64/machvec_dig.h b/include/asm-ia64/machvec_dig.h
deleted file mode 100644
index 8a0752f4098..00000000000
--- a/include/asm-ia64/machvec_dig.h
+++ /dev/null
@@ -1,16 +0,0 @@
1#ifndef _ASM_IA64_MACHVEC_DIG_h
2#define _ASM_IA64_MACHVEC_DIG_h
3
4extern ia64_mv_setup_t dig_setup;
5
6/*
7 * This stuff has dual use!
8 *
9 * For a generic kernel, the macros are used to initialize the
10 * platform's machvec structure. When compiling a non-generic kernel,
11 * the macros are used directly.
12 */
13#define platform_name "dig"
14#define platform_setup dig_setup
15
16#endif /* _ASM_IA64_MACHVEC_DIG_h */
diff --git a/include/asm-ia64/machvec_hpsim.h b/include/asm-ia64/machvec_hpsim.h
deleted file mode 100644
index cf72fc87fdf..00000000000
--- a/include/asm-ia64/machvec_hpsim.h
+++ /dev/null
@@ -1,18 +0,0 @@
1#ifndef _ASM_IA64_MACHVEC_HPSIM_h
2#define _ASM_IA64_MACHVEC_HPSIM_h
3
4extern ia64_mv_setup_t hpsim_setup;
5extern ia64_mv_irq_init_t hpsim_irq_init;
6
7/*
8 * This stuff has dual use!
9 *
10 * For a generic kernel, the macros are used to initialize the
11 * platform's machvec structure. When compiling a non-generic kernel,
12 * the macros are used directly.
13 */
14#define platform_name "hpsim"
15#define platform_setup hpsim_setup
16#define platform_irq_init hpsim_irq_init
17
18#endif /* _ASM_IA64_MACHVEC_HPSIM_h */
diff --git a/include/asm-ia64/machvec_hpzx1.h b/include/asm-ia64/machvec_hpzx1.h
deleted file mode 100644
index 2f57f5144b9..00000000000
--- a/include/asm-ia64/machvec_hpzx1.h
+++ /dev/null
@@ -1,37 +0,0 @@
1#ifndef _ASM_IA64_MACHVEC_HPZX1_h
2#define _ASM_IA64_MACHVEC_HPZX1_h
3
4extern ia64_mv_setup_t dig_setup;
5extern ia64_mv_dma_alloc_coherent sba_alloc_coherent;
6extern ia64_mv_dma_free_coherent sba_free_coherent;
7extern ia64_mv_dma_map_single_attrs sba_map_single_attrs;
8extern ia64_mv_dma_unmap_single_attrs sba_unmap_single_attrs;
9extern ia64_mv_dma_map_sg_attrs sba_map_sg_attrs;
10extern ia64_mv_dma_unmap_sg_attrs sba_unmap_sg_attrs;
11extern ia64_mv_dma_supported sba_dma_supported;
12extern ia64_mv_dma_mapping_error sba_dma_mapping_error;
13
14/*
15 * This stuff has dual use!
16 *
17 * For a generic kernel, the macros are used to initialize the
18 * platform's machvec structure. When compiling a non-generic kernel,
19 * the macros are used directly.
20 */
21#define platform_name "hpzx1"
22#define platform_setup dig_setup
23#define platform_dma_init machvec_noop
24#define platform_dma_alloc_coherent sba_alloc_coherent
25#define platform_dma_free_coherent sba_free_coherent
26#define platform_dma_map_single_attrs sba_map_single_attrs
27#define platform_dma_unmap_single_attrs sba_unmap_single_attrs
28#define platform_dma_map_sg_attrs sba_map_sg_attrs
29#define platform_dma_unmap_sg_attrs sba_unmap_sg_attrs
30#define platform_dma_sync_single_for_cpu machvec_dma_sync_single
31#define platform_dma_sync_sg_for_cpu machvec_dma_sync_sg
32#define platform_dma_sync_single_for_device machvec_dma_sync_single
33#define platform_dma_sync_sg_for_device machvec_dma_sync_sg
34#define platform_dma_supported sba_dma_supported
35#define platform_dma_mapping_error sba_dma_mapping_error
36
37#endif /* _ASM_IA64_MACHVEC_HPZX1_h */
diff --git a/include/asm-ia64/machvec_hpzx1_swiotlb.h b/include/asm-ia64/machvec_hpzx1_swiotlb.h
deleted file mode 100644
index a842cdda827..00000000000
--- a/include/asm-ia64/machvec_hpzx1_swiotlb.h
+++ /dev/null
@@ -1,42 +0,0 @@
1#ifndef _ASM_IA64_MACHVEC_HPZX1_SWIOTLB_h
2#define _ASM_IA64_MACHVEC_HPZX1_SWIOTLB_h
3
4extern ia64_mv_setup_t dig_setup;
5extern ia64_mv_dma_alloc_coherent hwsw_alloc_coherent;
6extern ia64_mv_dma_free_coherent hwsw_free_coherent;
7extern ia64_mv_dma_map_single_attrs hwsw_map_single_attrs;
8extern ia64_mv_dma_unmap_single_attrs hwsw_unmap_single_attrs;
9extern ia64_mv_dma_map_sg_attrs hwsw_map_sg_attrs;
10extern ia64_mv_dma_unmap_sg_attrs hwsw_unmap_sg_attrs;
11extern ia64_mv_dma_supported hwsw_dma_supported;
12extern ia64_mv_dma_mapping_error hwsw_dma_mapping_error;
13extern ia64_mv_dma_sync_single_for_cpu hwsw_sync_single_for_cpu;
14extern ia64_mv_dma_sync_sg_for_cpu hwsw_sync_sg_for_cpu;
15extern ia64_mv_dma_sync_single_for_device hwsw_sync_single_for_device;
16extern ia64_mv_dma_sync_sg_for_device hwsw_sync_sg_for_device;
17
18/*
19 * This stuff has dual use!
20 *
21 * For a generic kernel, the macros are used to initialize the
22 * platform's machvec structure. When compiling a non-generic kernel,
23 * the macros are used directly.
24 */
25#define platform_name "hpzx1_swiotlb"
26
27#define platform_setup dig_setup
28#define platform_dma_init machvec_noop
29#define platform_dma_alloc_coherent hwsw_alloc_coherent
30#define platform_dma_free_coherent hwsw_free_coherent
31#define platform_dma_map_single_attrs hwsw_map_single_attrs
32#define platform_dma_unmap_single_attrs hwsw_unmap_single_attrs
33#define platform_dma_map_sg_attrs hwsw_map_sg_attrs
34#define platform_dma_unmap_sg_attrs hwsw_unmap_sg_attrs
35#define platform_dma_supported hwsw_dma_supported
36#define platform_dma_mapping_error hwsw_dma_mapping_error
37#define platform_dma_sync_single_for_cpu hwsw_sync_single_for_cpu
38#define platform_dma_sync_sg_for_cpu hwsw_sync_sg_for_cpu
39#define platform_dma_sync_single_for_device hwsw_sync_single_for_device
40#define platform_dma_sync_sg_for_device hwsw_sync_sg_for_device
41
42#endif /* _ASM_IA64_MACHVEC_HPZX1_SWIOTLB_h */
diff --git a/include/asm-ia64/machvec_init.h b/include/asm-ia64/machvec_init.h
deleted file mode 100644
index 7f21249fba3..00000000000
--- a/include/asm-ia64/machvec_init.h
+++ /dev/null
@@ -1,33 +0,0 @@
1#include <asm/machvec.h>
2
3extern ia64_mv_send_ipi_t ia64_send_ipi;
4extern ia64_mv_global_tlb_purge_t ia64_global_tlb_purge;
5extern ia64_mv_irq_to_vector __ia64_irq_to_vector;
6extern ia64_mv_local_vector_to_irq __ia64_local_vector_to_irq;
7extern ia64_mv_pci_get_legacy_mem_t ia64_pci_get_legacy_mem;
8extern ia64_mv_pci_legacy_read_t ia64_pci_legacy_read;
9extern ia64_mv_pci_legacy_write_t ia64_pci_legacy_write;
10
11extern ia64_mv_inb_t __ia64_inb;
12extern ia64_mv_inw_t __ia64_inw;
13extern ia64_mv_inl_t __ia64_inl;
14extern ia64_mv_outb_t __ia64_outb;
15extern ia64_mv_outw_t __ia64_outw;
16extern ia64_mv_outl_t __ia64_outl;
17extern ia64_mv_mmiowb_t __ia64_mmiowb;
18extern ia64_mv_readb_t __ia64_readb;
19extern ia64_mv_readw_t __ia64_readw;
20extern ia64_mv_readl_t __ia64_readl;
21extern ia64_mv_readq_t __ia64_readq;
22extern ia64_mv_readb_t __ia64_readb_relaxed;
23extern ia64_mv_readw_t __ia64_readw_relaxed;
24extern ia64_mv_readl_t __ia64_readl_relaxed;
25extern ia64_mv_readq_t __ia64_readq_relaxed;
26
27#define MACHVEC_HELPER(name) \
28 struct ia64_machine_vector machvec_##name __attribute__ ((unused, __section__ (".machvec"))) \
29 = MACHVEC_INIT(name);
30
31#define MACHVEC_DEFINE(name) MACHVEC_HELPER(name)
32
33MACHVEC_DEFINE(MACHVEC_PLATFORM_NAME)
diff --git a/include/asm-ia64/machvec_sn2.h b/include/asm-ia64/machvec_sn2.h
deleted file mode 100644
index 781308ea7b8..00000000000
--- a/include/asm-ia64/machvec_sn2.h
+++ /dev/null
@@ -1,139 +0,0 @@
1/*
2 * Copyright (c) 2002-2003,2006 Silicon Graphics, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it would be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
11 *
12 * Further, this software is distributed without any warranty that it is
13 * free of the rightful claim of any third person regarding infringement
14 * or the like. Any license provided herein, whether implied or
15 * otherwise, applies only to this software file. Patent licenses, if
16 * any, provided herein do not apply to combinations of this program with
17 * other software, or any other product whatsoever.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this program; if not, write the Free Software
21 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 *
23 * For further information regarding this notice, see:
24 *
25 * http://oss.sgi.com/projects/GenInfo/NoticeExplan
26 */
27
28#ifndef _ASM_IA64_MACHVEC_SN2_H
29#define _ASM_IA64_MACHVEC_SN2_H
30
31extern ia64_mv_setup_t sn_setup;
32extern ia64_mv_cpu_init_t sn_cpu_init;
33extern ia64_mv_irq_init_t sn_irq_init;
34extern ia64_mv_send_ipi_t sn2_send_IPI;
35extern ia64_mv_timer_interrupt_t sn_timer_interrupt;
36extern ia64_mv_global_tlb_purge_t sn2_global_tlb_purge;
37extern ia64_mv_tlb_migrate_finish_t sn_tlb_migrate_finish;
38extern ia64_mv_irq_to_vector sn_irq_to_vector;
39extern ia64_mv_local_vector_to_irq sn_local_vector_to_irq;
40extern ia64_mv_pci_get_legacy_mem_t sn_pci_get_legacy_mem;
41extern ia64_mv_pci_legacy_read_t sn_pci_legacy_read;
42extern ia64_mv_pci_legacy_write_t sn_pci_legacy_write;
43extern ia64_mv_inb_t __sn_inb;
44extern ia64_mv_inw_t __sn_inw;
45extern ia64_mv_inl_t __sn_inl;
46extern ia64_mv_outb_t __sn_outb;
47extern ia64_mv_outw_t __sn_outw;
48extern ia64_mv_outl_t __sn_outl;
49extern ia64_mv_mmiowb_t __sn_mmiowb;
50extern ia64_mv_readb_t __sn_readb;
51extern ia64_mv_readw_t __sn_readw;
52extern ia64_mv_readl_t __sn_readl;
53extern ia64_mv_readq_t __sn_readq;
54extern ia64_mv_readb_t __sn_readb_relaxed;
55extern ia64_mv_readw_t __sn_readw_relaxed;
56extern ia64_mv_readl_t __sn_readl_relaxed;
57extern ia64_mv_readq_t __sn_readq_relaxed;
58extern ia64_mv_dma_alloc_coherent sn_dma_alloc_coherent;
59extern ia64_mv_dma_free_coherent sn_dma_free_coherent;
60extern ia64_mv_dma_map_single_attrs sn_dma_map_single_attrs;
61extern ia64_mv_dma_unmap_single_attrs sn_dma_unmap_single_attrs;
62extern ia64_mv_dma_map_sg_attrs sn_dma_map_sg_attrs;
63extern ia64_mv_dma_unmap_sg_attrs sn_dma_unmap_sg_attrs;
64extern ia64_mv_dma_sync_single_for_cpu sn_dma_sync_single_for_cpu;
65extern ia64_mv_dma_sync_sg_for_cpu sn_dma_sync_sg_for_cpu;
66extern ia64_mv_dma_sync_single_for_device sn_dma_sync_single_for_device;
67extern ia64_mv_dma_sync_sg_for_device sn_dma_sync_sg_for_device;
68extern ia64_mv_dma_mapping_error sn_dma_mapping_error;
69extern ia64_mv_dma_supported sn_dma_supported;
70extern ia64_mv_migrate_t sn_migrate;
71extern ia64_mv_kernel_launch_event_t sn_kernel_launch_event;
72extern ia64_mv_setup_msi_irq_t sn_setup_msi_irq;
73extern ia64_mv_teardown_msi_irq_t sn_teardown_msi_irq;
74extern ia64_mv_pci_fixup_bus_t sn_pci_fixup_bus;
75
76
77/*
78 * This stuff has dual use!
79 *
80 * For a generic kernel, the macros are used to initialize the
81 * platform's machvec structure. When compiling a non-generic kernel,
82 * the macros are used directly.
83 */
84#define platform_name "sn2"
85#define platform_setup sn_setup
86#define platform_cpu_init sn_cpu_init
87#define platform_irq_init sn_irq_init
88#define platform_send_ipi sn2_send_IPI
89#define platform_timer_interrupt sn_timer_interrupt
90#define platform_global_tlb_purge sn2_global_tlb_purge
91#define platform_tlb_migrate_finish sn_tlb_migrate_finish
92#define platform_pci_fixup sn_pci_fixup
93#define platform_inb __sn_inb
94#define platform_inw __sn_inw
95#define platform_inl __sn_inl
96#define platform_outb __sn_outb
97#define platform_outw __sn_outw
98#define platform_outl __sn_outl
99#define platform_mmiowb __sn_mmiowb
100#define platform_readb __sn_readb
101#define platform_readw __sn_readw
102#define platform_readl __sn_readl
103#define platform_readq __sn_readq
104#define platform_readb_relaxed __sn_readb_relaxed
105#define platform_readw_relaxed __sn_readw_relaxed
106#define platform_readl_relaxed __sn_readl_relaxed
107#define platform_readq_relaxed __sn_readq_relaxed
108#define platform_irq_to_vector sn_irq_to_vector
109#define platform_local_vector_to_irq sn_local_vector_to_irq
110#define platform_pci_get_legacy_mem sn_pci_get_legacy_mem
111#define platform_pci_legacy_read sn_pci_legacy_read
112#define platform_pci_legacy_write sn_pci_legacy_write
113#define platform_dma_init machvec_noop
114#define platform_dma_alloc_coherent sn_dma_alloc_coherent
115#define platform_dma_free_coherent sn_dma_free_coherent
116#define platform_dma_map_single_attrs sn_dma_map_single_attrs
117#define platform_dma_unmap_single_attrs sn_dma_unmap_single_attrs
118#define platform_dma_map_sg_attrs sn_dma_map_sg_attrs
119#define platform_dma_unmap_sg_attrs sn_dma_unmap_sg_attrs
120#define platform_dma_sync_single_for_cpu sn_dma_sync_single_for_cpu
121#define platform_dma_sync_sg_for_cpu sn_dma_sync_sg_for_cpu
122#define platform_dma_sync_single_for_device sn_dma_sync_single_for_device
123#define platform_dma_sync_sg_for_device sn_dma_sync_sg_for_device
124#define platform_dma_mapping_error sn_dma_mapping_error
125#define platform_dma_supported sn_dma_supported
126#define platform_migrate sn_migrate
127#define platform_kernel_launch_event sn_kernel_launch_event
128#ifdef CONFIG_PCI_MSI
129#define platform_setup_msi_irq sn_setup_msi_irq
130#define platform_teardown_msi_irq sn_teardown_msi_irq
131#else
132#define platform_setup_msi_irq ((ia64_mv_setup_msi_irq_t*)NULL)
133#define platform_teardown_msi_irq ((ia64_mv_teardown_msi_irq_t*)NULL)
134#endif
135#define platform_pci_fixup_bus sn_pci_fixup_bus
136
137#include <asm/sn/io.h>
138
139#endif /* _ASM_IA64_MACHVEC_SN2_H */
diff --git a/include/asm-ia64/machvec_uv.h b/include/asm-ia64/machvec_uv.h
deleted file mode 100644
index 2931447f381..00000000000
--- a/include/asm-ia64/machvec_uv.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV Core Functions
7 *
8 * Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved.
9 */
10
11#ifndef _ASM_IA64_MACHVEC_UV_H
12#define _ASM_IA64_MACHVEC_UV_H
13
14extern ia64_mv_setup_t uv_setup;
15
16/*
17 * This stuff has dual use!
18 *
19 * For a generic kernel, the macros are used to initialize the
20 * platform's machvec structure. When compiling a non-generic kernel,
21 * the macros are used directly.
22 */
23#define platform_name "uv"
24#define platform_setup uv_setup
25
26#endif /* _ASM_IA64_MACHVEC_UV_H */
diff --git a/include/asm-ia64/mc146818rtc.h b/include/asm-ia64/mc146818rtc.h
deleted file mode 100644
index 407787a237b..00000000000
--- a/include/asm-ia64/mc146818rtc.h
+++ /dev/null
@@ -1,10 +0,0 @@
1#ifndef _ASM_IA64_MC146818RTC_H
2#define _ASM_IA64_MC146818RTC_H
3
4/*
5 * Machine dependent access functions for RTC registers.
6 */
7
8/* empty include file to satisfy the include in genrtc.c */
9
10#endif /* _ASM_IA64_MC146818RTC_H */
diff --git a/include/asm-ia64/mca.h b/include/asm-ia64/mca.h
deleted file mode 100644
index 18a4321349a..00000000000
--- a/include/asm-ia64/mca.h
+++ /dev/null
@@ -1,179 +0,0 @@
1/*
2 * File: mca.h
3 * Purpose: Machine check handling specific defines
4 *
5 * Copyright (C) 1999, 2004 Silicon Graphics, Inc.
6 * Copyright (C) Vijay Chander <vijay@engr.sgi.com>
7 * Copyright (C) Srinivasa Thirumalachar <sprasad@engr.sgi.com>
8 * Copyright (C) Russ Anderson <rja@sgi.com>
9 */
10
11#ifndef _ASM_IA64_MCA_H
12#define _ASM_IA64_MCA_H
13
14#if !defined(__ASSEMBLY__)
15
16#include <linux/interrupt.h>
17#include <linux/types.h>
18
19#include <asm/param.h>
20#include <asm/sal.h>
21#include <asm/processor.h>
22#include <asm/mca_asm.h>
23
24#define IA64_MCA_RENDEZ_TIMEOUT (20 * 1000) /* value in milliseconds - 20 seconds */
25
26typedef struct ia64_fptr {
27 unsigned long fp;
28 unsigned long gp;
29} ia64_fptr_t;
30
31typedef union cmcv_reg_u {
32 u64 cmcv_regval;
33 struct {
34 u64 cmcr_vector : 8;
35 u64 cmcr_reserved1 : 4;
36 u64 cmcr_ignored1 : 1;
37 u64 cmcr_reserved2 : 3;
38 u64 cmcr_mask : 1;
39 u64 cmcr_ignored2 : 47;
40 } cmcv_reg_s;
41
42} cmcv_reg_t;
43
44#define cmcv_mask cmcv_reg_s.cmcr_mask
45#define cmcv_vector cmcv_reg_s.cmcr_vector
46
47enum {
48 IA64_MCA_RENDEZ_CHECKIN_NOTDONE = 0x0,
49 IA64_MCA_RENDEZ_CHECKIN_DONE = 0x1,
50 IA64_MCA_RENDEZ_CHECKIN_INIT = 0x2,
51 IA64_MCA_RENDEZ_CHECKIN_CONCURRENT_MCA = 0x3,
52};
53
54/* Information maintained by the MC infrastructure */
55typedef struct ia64_mc_info_s {
56 u64 imi_mca_handler;
57 size_t imi_mca_handler_size;
58 u64 imi_monarch_init_handler;
59 size_t imi_monarch_init_handler_size;
60 u64 imi_slave_init_handler;
61 size_t imi_slave_init_handler_size;
62 u8 imi_rendez_checkin[NR_CPUS];
63
64} ia64_mc_info_t;
65
66/* Handover state from SAL to OS and vice versa, for both MCA and INIT events.
67 * Besides the handover state, it also contains some saved registers from the
68 * time of the event.
69 * Note: mca_asm.S depends on the precise layout of this structure.
70 */
71
72struct ia64_sal_os_state {
73
74 /* SAL to OS */
75 u64 os_gp; /* GP of the os registered with the SAL, physical */
76 u64 pal_proc; /* PAL_PROC entry point, physical */
77 u64 sal_proc; /* SAL_PROC entry point, physical */
78 u64 rv_rc; /* MCA - Rendezvous state, INIT - reason code */
79 u64 proc_state_param; /* from R18 */
80 u64 monarch; /* 1 for a monarch event, 0 for a slave */
81
82 /* common */
83 u64 sal_ra; /* Return address in SAL, physical */
84 u64 sal_gp; /* GP of the SAL - physical */
85 pal_min_state_area_t *pal_min_state; /* from R17. physical in asm, virtual in C */
86 /* Previous values of IA64_KR(CURRENT) and IA64_KR(CURRENT_STACK).
87 * Note: if the MCA/INIT recovery code wants to resume to a new context
88 * then it must change these values to reflect the new kernel stack.
89 */
90 u64 prev_IA64_KR_CURRENT; /* previous value of IA64_KR(CURRENT) */
91 u64 prev_IA64_KR_CURRENT_STACK;
92 struct task_struct *prev_task; /* previous task, NULL if it is not useful */
93 /* Some interrupt registers are not saved in minstate, pt_regs or
94 * switch_stack. Because MCA/INIT can occur when interrupts are
95 * disabled, we need to save the additional interrupt registers over
96 * MCA/INIT and resume.
97 */
98 u64 isr;
99 u64 ifa;
100 u64 itir;
101 u64 iipa;
102 u64 iim;
103 u64 iha;
104
105 /* OS to SAL */
106 u64 os_status; /* OS status to SAL, enum below */
107 u64 context; /* 0 if return to same context
108 1 if return to new context */
109};
110
111enum {
112 IA64_MCA_CORRECTED = 0x0, /* Error has been corrected by OS_MCA */
113 IA64_MCA_WARM_BOOT = -1, /* Warm boot of the system need from SAL */
114 IA64_MCA_COLD_BOOT = -2, /* Cold boot of the system need from SAL */
115 IA64_MCA_HALT = -3 /* System to be halted by SAL */
116};
117
118enum {
119 IA64_INIT_RESUME = 0x0, /* Resume after return from INIT */
120 IA64_INIT_WARM_BOOT = -1, /* Warm boot of the system need from SAL */
121};
122
123enum {
124 IA64_MCA_SAME_CONTEXT = 0x0, /* SAL to return to same context */
125 IA64_MCA_NEW_CONTEXT = -1 /* SAL to return to new context */
126};
127
128/* Per-CPU MCA state that is too big for normal per-CPU variables. */
129
130struct ia64_mca_cpu {
131 u64 mca_stack[KERNEL_STACK_SIZE/8];
132 u64 init_stack[KERNEL_STACK_SIZE/8];
133};
134
135/* Array of physical addresses of each CPU's MCA area. */
136extern unsigned long __per_cpu_mca[NR_CPUS];
137
138extern int cpe_vector;
139extern int ia64_cpe_irq;
140extern void ia64_mca_init(void);
141extern void ia64_mca_cpu_init(void *);
142extern void ia64_os_mca_dispatch(void);
143extern void ia64_os_mca_dispatch_end(void);
144extern void ia64_mca_ucmc_handler(struct pt_regs *, struct ia64_sal_os_state *);
145extern void ia64_init_handler(struct pt_regs *,
146 struct switch_stack *,
147 struct ia64_sal_os_state *);
148extern void ia64_monarch_init_handler(void);
149extern void ia64_slave_init_handler(void);
150extern void ia64_mca_cmc_vector_setup(void);
151extern int ia64_reg_MCA_extension(int (*fn)(void *, struct ia64_sal_os_state *));
152extern void ia64_unreg_MCA_extension(void);
153extern u64 ia64_get_rnat(u64 *);
154extern void ia64_mca_printk(const char * fmt, ...)
155 __attribute__ ((format (printf, 1, 2)));
156
157struct ia64_mca_notify_die {
158 struct ia64_sal_os_state *sos;
159 int *monarch_cpu;
160 int *data;
161};
162
163DECLARE_PER_CPU(u64, ia64_mca_pal_base);
164
165#else /* __ASSEMBLY__ */
166
167#define IA64_MCA_CORRECTED 0x0 /* Error has been corrected by OS_MCA */
168#define IA64_MCA_WARM_BOOT -1 /* Warm boot of the system need from SAL */
169#define IA64_MCA_COLD_BOOT -2 /* Cold boot of the system need from SAL */
170#define IA64_MCA_HALT -3 /* System to be halted by SAL */
171
172#define IA64_INIT_RESUME 0x0 /* Resume after return from INIT */
173#define IA64_INIT_WARM_BOOT -1 /* Warm boot of the system need from SAL */
174
175#define IA64_MCA_SAME_CONTEXT 0x0 /* SAL to return to same context */
176#define IA64_MCA_NEW_CONTEXT -1 /* SAL to return to new context */
177
178#endif /* !__ASSEMBLY__ */
179#endif /* _ASM_IA64_MCA_H */
diff --git a/include/asm-ia64/mca_asm.h b/include/asm-ia64/mca_asm.h
deleted file mode 100644
index dd2a5b13439..00000000000
--- a/include/asm-ia64/mca_asm.h
+++ /dev/null
@@ -1,242 +0,0 @@
1/*
2 * File: mca_asm.h
3 * Purpose: Machine check handling specific defines
4 *
5 * Copyright (C) 1999 Silicon Graphics, Inc.
6 * Copyright (C) Vijay Chander <vijay@engr.sgi.com>
7 * Copyright (C) Srinivasa Thirumalachar <sprasad@engr.sgi.com>
8 * Copyright (C) 2000 Hewlett-Packard Co.
9 * Copyright (C) 2000 David Mosberger-Tang <davidm@hpl.hp.com>
10 * Copyright (C) 2002 Intel Corp.
11 * Copyright (C) 2002 Jenna Hall <jenna.s.hall@intel.com>
12 * Copyright (C) 2005 Silicon Graphics, Inc
13 * Copyright (C) 2005 Keith Owens <kaos@sgi.com>
14 */
15#ifndef _ASM_IA64_MCA_ASM_H
16#define _ASM_IA64_MCA_ASM_H
17
18#define PSR_IC 13
19#define PSR_I 14
20#define PSR_DT 17
21#define PSR_RT 27
22#define PSR_MC 35
23#define PSR_IT 36
24#define PSR_BN 44
25
26/*
27 * This macro converts a instruction virtual address to a physical address
28 * Right now for simulation purposes the virtual addresses are
29 * direct mapped to physical addresses.
30 * 1. Lop off bits 61 thru 63 in the virtual address
31 */
32#define INST_VA_TO_PA(addr) \
33 dep addr = 0, addr, 61, 3
34/*
35 * This macro converts a data virtual address to a physical address
36 * Right now for simulation purposes the virtual addresses are
37 * direct mapped to physical addresses.
38 * 1. Lop off bits 61 thru 63 in the virtual address
39 */
40#define DATA_VA_TO_PA(addr) \
41 tpa addr = addr
42/*
43 * This macro converts a data physical address to a virtual address
44 * Right now for simulation purposes the virtual addresses are
45 * direct mapped to physical addresses.
46 * 1. Put 0x7 in bits 61 thru 63.
47 */
48#define DATA_PA_TO_VA(addr,temp) \
49 mov temp = 0x7 ;; \
50 dep addr = temp, addr, 61, 3
51
52#define GET_THIS_PADDR(reg, var) \
53 mov reg = IA64_KR(PER_CPU_DATA);; \
54 addl reg = THIS_CPU(var), reg
55
56/*
57 * This macro jumps to the instruction at the given virtual address
58 * and starts execution in physical mode with all the address
59 * translations turned off.
60 * 1. Save the current psr
61 * 2. Make sure that all the upper 32 bits are off
62 *
63 * 3. Clear the interrupt enable and interrupt state collection bits
64 * in the psr before updating the ipsr and iip.
65 *
66 * 4. Turn off the instruction, data and rse translation bits of the psr
67 * and store the new value into ipsr
68 * Also make sure that the interrupts are disabled.
69 * Ensure that we are in little endian mode.
70 * [psr.{rt, it, dt, i, be} = 0]
71 *
72 * 5. Get the physical address corresponding to the virtual address
73 * of the next instruction bundle and put it in iip.
74 * (Using magic numbers 24 and 40 in the deposint instruction since
75 * the IA64_SDK code directly maps to lower 24bits as physical address
76 * from a virtual address).
77 *
78 * 6. Do an rfi to move the values from ipsr to psr and iip to ip.
79 */
80#define PHYSICAL_MODE_ENTER(temp1, temp2, start_addr, old_psr) \
81 mov old_psr = psr; \
82 ;; \
83 dep old_psr = 0, old_psr, 32, 32; \
84 \
85 mov ar.rsc = 0 ; \
86 ;; \
87 srlz.d; \
88 mov temp2 = ar.bspstore; \
89 ;; \
90 DATA_VA_TO_PA(temp2); \
91 ;; \
92 mov temp1 = ar.rnat; \
93 ;; \
94 mov ar.bspstore = temp2; \
95 ;; \
96 mov ar.rnat = temp1; \
97 mov temp1 = psr; \
98 mov temp2 = psr; \
99 ;; \
100 \
101 dep temp2 = 0, temp2, PSR_IC, 2; \
102 ;; \
103 mov psr.l = temp2; \
104 ;; \
105 srlz.d; \
106 dep temp1 = 0, temp1, 32, 32; \
107 ;; \
108 dep temp1 = 0, temp1, PSR_IT, 1; \
109 ;; \
110 dep temp1 = 0, temp1, PSR_DT, 1; \
111 ;; \
112 dep temp1 = 0, temp1, PSR_RT, 1; \
113 ;; \
114 dep temp1 = 0, temp1, PSR_I, 1; \
115 ;; \
116 dep temp1 = 0, temp1, PSR_IC, 1; \
117 ;; \
118 dep temp1 = -1, temp1, PSR_MC, 1; \
119 ;; \
120 mov cr.ipsr = temp1; \
121 ;; \
122 LOAD_PHYSICAL(p0, temp2, start_addr); \
123 ;; \
124 mov cr.iip = temp2; \
125 mov cr.ifs = r0; \
126 DATA_VA_TO_PA(sp); \
127 DATA_VA_TO_PA(gp); \
128 ;; \
129 srlz.i; \
130 ;; \
131 nop 1; \
132 nop 2; \
133 nop 1; \
134 nop 2; \
135 rfi; \
136 ;;
137
138/*
139 * This macro jumps to the instruction at the given virtual address
140 * and starts execution in virtual mode with all the address
141 * translations turned on.
142 * 1. Get the old saved psr
143 *
144 * 2. Clear the interrupt state collection bit in the current psr.
145 *
146 * 3. Set the instruction translation bit back in the old psr
147 * Note we have to do this since we are right now saving only the
148 * lower 32-bits of old psr.(Also the old psr has the data and
149 * rse translation bits on)
150 *
151 * 4. Set ipsr to this old_psr with "it" bit set and "bn" = 1.
152 *
153 * 5. Reset the current thread pointer (r13).
154 *
155 * 6. Set iip to the virtual address of the next instruction bundle.
156 *
157 * 7. Do an rfi to move ipsr to psr and iip to ip.
158 */
159
160#define VIRTUAL_MODE_ENTER(temp1, temp2, start_addr, old_psr) \
161 mov temp2 = psr; \
162 ;; \
163 mov old_psr = temp2; \
164 ;; \
165 dep temp2 = 0, temp2, PSR_IC, 2; \
166 ;; \
167 mov psr.l = temp2; \
168 mov ar.rsc = 0; \
169 ;; \
170 srlz.d; \
171 mov r13 = ar.k6; \
172 mov temp2 = ar.bspstore; \
173 ;; \
174 DATA_PA_TO_VA(temp2,temp1); \
175 ;; \
176 mov temp1 = ar.rnat; \
177 ;; \
178 mov ar.bspstore = temp2; \
179 ;; \
180 mov ar.rnat = temp1; \
181 ;; \
182 mov temp1 = old_psr; \
183 ;; \
184 mov temp2 = 1; \
185 ;; \
186 dep temp1 = temp2, temp1, PSR_IC, 1; \
187 ;; \
188 dep temp1 = temp2, temp1, PSR_IT, 1; \
189 ;; \
190 dep temp1 = temp2, temp1, PSR_DT, 1; \
191 ;; \
192 dep temp1 = temp2, temp1, PSR_RT, 1; \
193 ;; \
194 dep temp1 = temp2, temp1, PSR_BN, 1; \
195 ;; \
196 \
197 mov cr.ipsr = temp1; \
198 movl temp2 = start_addr; \
199 ;; \
200 mov cr.iip = temp2; \
201 movl gp = __gp \
202 ;; \
203 DATA_PA_TO_VA(sp, temp1); \
204 srlz.i; \
205 ;; \
206 nop 1; \
207 nop 2; \
208 nop 1; \
209 rfi \
210 ;;
211
212/*
213 * The MCA and INIT stacks in struct ia64_mca_cpu look like normal kernel
214 * stacks, except that the SAL/OS state and a switch_stack are stored near the
215 * top of the MCA/INIT stack. To support concurrent entry to MCA or INIT, as
216 * well as MCA over INIT, each event needs its own SAL/OS state. All entries
217 * are 16 byte aligned.
218 *
219 * +---------------------------+
220 * | pt_regs |
221 * +---------------------------+
222 * | switch_stack |
223 * +---------------------------+
224 * | SAL/OS state |
225 * +---------------------------+
226 * | 16 byte scratch area |
227 * +---------------------------+ <-------- SP at start of C MCA handler
228 * | ..... |
229 * +---------------------------+
230 * | RBS for MCA/INIT handler |
231 * +---------------------------+
232 * | struct task for MCA/INIT |
233 * +---------------------------+ <-------- Bottom of MCA/INIT stack
234 */
235
236#define ALIGN16(x) ((x)&~15)
237#define MCA_PT_REGS_OFFSET ALIGN16(KERNEL_STACK_SIZE-IA64_PT_REGS_SIZE)
238#define MCA_SWITCH_STACK_OFFSET ALIGN16(MCA_PT_REGS_OFFSET-IA64_SWITCH_STACK_SIZE)
239#define MCA_SOS_OFFSET ALIGN16(MCA_SWITCH_STACK_OFFSET-IA64_SAL_OS_STATE_SIZE)
240#define MCA_SP_OFFSET ALIGN16(MCA_SOS_OFFSET-16)
241
242#endif /* _ASM_IA64_MCA_ASM_H */
diff --git a/include/asm-ia64/meminit.h b/include/asm-ia64/meminit.h
deleted file mode 100644
index 7245a578159..00000000000
--- a/include/asm-ia64/meminit.h
+++ /dev/null
@@ -1,75 +0,0 @@
1#ifndef meminit_h
2#define meminit_h
3
4/*
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 */
9
10
11/*
12 * Entries defined so far:
13 * - boot param structure itself
14 * - memory map
15 * - initrd (optional)
16 * - command line string
17 * - kernel code & data
18 * - crash dumping code reserved region
19 * - Kernel memory map built from EFI memory map
20 * - ELF core header
21 *
22 * More could be added if necessary
23 */
24#define IA64_MAX_RSVD_REGIONS 8
25
26struct rsvd_region {
27 unsigned long start; /* virtual address of beginning of element */
28 unsigned long end; /* virtual address of end of element + 1 */
29};
30
31extern struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1];
32extern int num_rsvd_regions;
33
34extern void find_memory (void);
35extern void reserve_memory (void);
36extern void find_initrd (void);
37extern int filter_rsvd_memory (unsigned long start, unsigned long end, void *arg);
38extern int filter_memory (unsigned long start, unsigned long end, void *arg);
39extern unsigned long efi_memmap_init(unsigned long *s, unsigned long *e);
40extern int find_max_min_low_pfn (unsigned long , unsigned long, void *);
41
42extern unsigned long vmcore_find_descriptor_size(unsigned long address);
43extern int reserve_elfcorehdr(unsigned long *start, unsigned long *end);
44
45/*
46 * For rounding an address to the next IA64_GRANULE_SIZE or order
47 */
48#define GRANULEROUNDDOWN(n) ((n) & ~(IA64_GRANULE_SIZE-1))
49#define GRANULEROUNDUP(n) (((n)+IA64_GRANULE_SIZE-1) & ~(IA64_GRANULE_SIZE-1))
50#define ORDERROUNDDOWN(n) ((n) & ~((PAGE_SIZE<<MAX_ORDER)-1))
51
52#ifdef CONFIG_NUMA
53 extern void call_pernode_memory (unsigned long start, unsigned long len, void *func);
54#else
55# define call_pernode_memory(start, len, func) (*func)(start, len, 0)
56#endif
57
58#define IGNORE_PFN0 1 /* XXX fix me: ignore pfn 0 until TLB miss handler is updated... */
59
60extern int register_active_ranges(u64 start, u64 len, int nid);
61
62#ifdef CONFIG_VIRTUAL_MEM_MAP
63# define LARGE_GAP 0x40000000 /* Use virtual mem map if hole is > than this */
64 extern unsigned long vmalloc_end;
65 extern struct page *vmem_map;
66 extern int find_largest_hole (u64 start, u64 end, void *arg);
67 extern int create_mem_map_page_table (u64 start, u64 end, void *arg);
68 extern int vmemmap_find_next_valid_pfn(int, int);
69#else
70static inline int vmemmap_find_next_valid_pfn(int node, int i)
71{
72 return i + 1;
73}
74#endif
75#endif /* meminit_h */
diff --git a/include/asm-ia64/mman.h b/include/asm-ia64/mman.h
deleted file mode 100644
index c73b87832a1..00000000000
--- a/include/asm-ia64/mman.h
+++ /dev/null
@@ -1,33 +0,0 @@
1#ifndef _ASM_IA64_MMAN_H
2#define _ASM_IA64_MMAN_H
3
4/*
5 * Based on <asm-i386/mman.h>.
6 *
7 * Modified 1998-2000, 2002
8 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
9 */
10
11#include <asm-generic/mman.h>
12
13#define MAP_GROWSDOWN 0x00100 /* stack-like segment */
14#define MAP_GROWSUP 0x00200 /* register stack-like segment */
15#define MAP_DENYWRITE 0x00800 /* ETXTBSY */
16#define MAP_EXECUTABLE 0x01000 /* mark it as an executable */
17#define MAP_LOCKED 0x02000 /* pages are locked */
18#define MAP_NORESERVE 0x04000 /* don't check for reservations */
19#define MAP_POPULATE 0x08000 /* populate (prefault) pagetables */
20#define MAP_NONBLOCK 0x10000 /* do not block on IO */
21
22#define MCL_CURRENT 1 /* lock all current mappings */
23#define MCL_FUTURE 2 /* lock all future mappings */
24
25#ifdef __KERNEL__
26#ifndef __ASSEMBLY__
27#define arch_mmap_check ia64_mmap_check
28int ia64_mmap_check(unsigned long addr, unsigned long len,
29 unsigned long flags);
30#endif
31#endif
32
33#endif /* _ASM_IA64_MMAN_H */
diff --git a/include/asm-ia64/mmu.h b/include/asm-ia64/mmu.h
deleted file mode 100644
index 611432ba579..00000000000
--- a/include/asm-ia64/mmu.h
+++ /dev/null
@@ -1,13 +0,0 @@
1#ifndef __MMU_H
2#define __MMU_H
3
4/*
5 * Type for a context number. We declare it volatile to ensure proper
6 * ordering when it's accessed outside of spinlock'd critical sections
7 * (e.g., as done in activate_mm() and init_new_context()).
8 */
9typedef volatile unsigned long mm_context_t;
10
11typedef unsigned long nv_mm_context_t;
12
13#endif
diff --git a/include/asm-ia64/mmu_context.h b/include/asm-ia64/mmu_context.h
deleted file mode 100644
index 040bc87db93..00000000000
--- a/include/asm-ia64/mmu_context.h
+++ /dev/null
@@ -1,198 +0,0 @@
1#ifndef _ASM_IA64_MMU_CONTEXT_H
2#define _ASM_IA64_MMU_CONTEXT_H
3
4/*
5 * Copyright (C) 1998-2002 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 */
8
9/*
10 * Routines to manage the allocation of task context numbers. Task context
11 * numbers are used to reduce or eliminate the need to perform TLB flushes
12 * due to context switches. Context numbers are implemented using ia-64
13 * region ids. Since the IA-64 TLB does not consider the region number when
14 * performing a TLB lookup, we need to assign a unique region id to each
15 * region in a process. We use the least significant three bits in aregion
16 * id for this purpose.
17 */
18
19#define IA64_REGION_ID_KERNEL 0 /* the kernel's region id (tlb.c depends on this being 0) */
20
21#define ia64_rid(ctx,addr) (((ctx) << 3) | (addr >> 61))
22
23# include <asm/page.h>
24# ifndef __ASSEMBLY__
25
26#include <linux/compiler.h>
27#include <linux/percpu.h>
28#include <linux/sched.h>
29#include <linux/spinlock.h>
30
31#include <asm/processor.h>
32#include <asm-generic/mm_hooks.h>
33
34struct ia64_ctx {
35 spinlock_t lock;
36 unsigned int next; /* next context number to use */
37 unsigned int limit; /* available free range */
38 unsigned int max_ctx; /* max. context value supported by all CPUs */
39 /* call wrap_mmu_context when next >= max */
40 unsigned long *bitmap; /* bitmap size is max_ctx+1 */
41 unsigned long *flushmap;/* pending rid to be flushed */
42};
43
44extern struct ia64_ctx ia64_ctx;
45DECLARE_PER_CPU(u8, ia64_need_tlb_flush);
46
47extern void mmu_context_init (void);
48extern void wrap_mmu_context (struct mm_struct *mm);
49
50static inline void
51enter_lazy_tlb (struct mm_struct *mm, struct task_struct *tsk)
52{
53}
54
55/*
56 * When the context counter wraps around all TLBs need to be flushed because
57 * an old context number might have been reused. This is signalled by the
58 * ia64_need_tlb_flush per-CPU variable, which is checked in the routine
59 * below. Called by activate_mm(). <efocht@ess.nec.de>
60 */
61static inline void
62delayed_tlb_flush (void)
63{
64 extern void local_flush_tlb_all (void);
65 unsigned long flags;
66
67 if (unlikely(__ia64_per_cpu_var(ia64_need_tlb_flush))) {
68 spin_lock_irqsave(&ia64_ctx.lock, flags);
69 if (__ia64_per_cpu_var(ia64_need_tlb_flush)) {
70 local_flush_tlb_all();
71 __ia64_per_cpu_var(ia64_need_tlb_flush) = 0;
72 }
73 spin_unlock_irqrestore(&ia64_ctx.lock, flags);
74 }
75}
76
77static inline nv_mm_context_t
78get_mmu_context (struct mm_struct *mm)
79{
80 unsigned long flags;
81 nv_mm_context_t context = mm->context;
82
83 if (likely(context))
84 goto out;
85
86 spin_lock_irqsave(&ia64_ctx.lock, flags);
87 /* re-check, now that we've got the lock: */
88 context = mm->context;
89 if (context == 0) {
90 cpus_clear(mm->cpu_vm_mask);
91 if (ia64_ctx.next >= ia64_ctx.limit) {
92 ia64_ctx.next = find_next_zero_bit(ia64_ctx.bitmap,
93 ia64_ctx.max_ctx, ia64_ctx.next);
94 ia64_ctx.limit = find_next_bit(ia64_ctx.bitmap,
95 ia64_ctx.max_ctx, ia64_ctx.next);
96 if (ia64_ctx.next >= ia64_ctx.max_ctx)
97 wrap_mmu_context(mm);
98 }
99 mm->context = context = ia64_ctx.next++;
100 __set_bit(context, ia64_ctx.bitmap);
101 }
102 spin_unlock_irqrestore(&ia64_ctx.lock, flags);
103out:
104 /*
105 * Ensure we're not starting to use "context" before any old
106 * uses of it are gone from our TLB.
107 */
108 delayed_tlb_flush();
109
110 return context;
111}
112
113/*
114 * Initialize context number to some sane value. MM is guaranteed to be a
115 * brand-new address-space, so no TLB flushing is needed, ever.
116 */
117static inline int
118init_new_context (struct task_struct *p, struct mm_struct *mm)
119{
120 mm->context = 0;
121 return 0;
122}
123
124static inline void
125destroy_context (struct mm_struct *mm)
126{
127 /* Nothing to do. */
128}
129
130static inline void
131reload_context (nv_mm_context_t context)
132{
133 unsigned long rid;
134 unsigned long rid_incr = 0;
135 unsigned long rr0, rr1, rr2, rr3, rr4, old_rr4;
136
137 old_rr4 = ia64_get_rr(RGN_BASE(RGN_HPAGE));
138 rid = context << 3; /* make space for encoding the region number */
139 rid_incr = 1 << 8;
140
141 /* encode the region id, preferred page size, and VHPT enable bit: */
142 rr0 = (rid << 8) | (PAGE_SHIFT << 2) | 1;
143 rr1 = rr0 + 1*rid_incr;
144 rr2 = rr0 + 2*rid_incr;
145 rr3 = rr0 + 3*rid_incr;
146 rr4 = rr0 + 4*rid_incr;
147#ifdef CONFIG_HUGETLB_PAGE
148 rr4 = (rr4 & (~(0xfcUL))) | (old_rr4 & 0xfc);
149
150# if RGN_HPAGE != 4
151# error "reload_context assumes RGN_HPAGE is 4"
152# endif
153#endif
154
155 ia64_set_rr0_to_rr4(rr0, rr1, rr2, rr3, rr4);
156 ia64_srlz_i(); /* srlz.i implies srlz.d */
157}
158
159/*
160 * Must be called with preemption off
161 */
162static inline void
163activate_context (struct mm_struct *mm)
164{
165 nv_mm_context_t context;
166
167 do {
168 context = get_mmu_context(mm);
169 if (!cpu_isset(smp_processor_id(), mm->cpu_vm_mask))
170 cpu_set(smp_processor_id(), mm->cpu_vm_mask);
171 reload_context(context);
172 /*
173 * in the unlikely event of a TLB-flush by another thread,
174 * redo the load.
175 */
176 } while (unlikely(context != mm->context));
177}
178
179#define deactivate_mm(tsk,mm) do { } while (0)
180
181/*
182 * Switch from address space PREV to address space NEXT.
183 */
184static inline void
185activate_mm (struct mm_struct *prev, struct mm_struct *next)
186{
187 /*
188 * We may get interrupts here, but that's OK because interrupt
189 * handlers cannot touch user-space.
190 */
191 ia64_set_kr(IA64_KR_PT_BASE, __pa(next->pgd));
192 activate_context(next);
193}
194
195#define switch_mm(prev_mm,next_mm,next_task) activate_mm(prev_mm, next_mm)
196
197# endif /* ! __ASSEMBLY__ */
198#endif /* _ASM_IA64_MMU_CONTEXT_H */
diff --git a/include/asm-ia64/mmzone.h b/include/asm-ia64/mmzone.h
deleted file mode 100644
index 34efe88eb84..00000000000
--- a/include/asm-ia64/mmzone.h
+++ /dev/null
@@ -1,50 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (c) 2000,2003 Silicon Graphics, Inc. All rights reserved.
7 * Copyright (c) 2002 NEC Corp.
8 * Copyright (c) 2002 Erich Focht <efocht@ess.nec.de>
9 * Copyright (c) 2002 Kimio Suganuma <k-suganuma@da.jp.nec.com>
10 */
11#ifndef _ASM_IA64_MMZONE_H
12#define _ASM_IA64_MMZONE_H
13
14#include <linux/numa.h>
15#include <asm/page.h>
16#include <asm/meminit.h>
17
18#ifdef CONFIG_NUMA
19
20static inline int pfn_to_nid(unsigned long pfn)
21{
22#ifdef CONFIG_NUMA
23 extern int paddr_to_nid(unsigned long);
24 int nid = paddr_to_nid(pfn << PAGE_SHIFT);
25 if (nid < 0)
26 return 0;
27 else
28 return nid;
29#else
30 return 0;
31#endif
32}
33
34#ifdef CONFIG_HAVE_ARCH_EARLY_PFN_TO_NID
35extern int early_pfn_to_nid(unsigned long pfn);
36#endif
37
38#ifdef CONFIG_IA64_DIG /* DIG systems are small */
39# define MAX_PHYSNODE_ID 8
40# define NR_NODE_MEMBLKS (MAX_NUMNODES * 8)
41#else /* sn2 is the biggest case, so we use that if !DIG */
42# define MAX_PHYSNODE_ID 2048
43# define NR_NODE_MEMBLKS (MAX_NUMNODES * 4)
44#endif
45
46#else /* CONFIG_NUMA */
47# define NR_NODE_MEMBLKS (MAX_NUMNODES * 4)
48#endif /* CONFIG_NUMA */
49
50#endif /* _ASM_IA64_MMZONE_H */
diff --git a/include/asm-ia64/module.h b/include/asm-ia64/module.h
deleted file mode 100644
index d2da61e4c49..00000000000
--- a/include/asm-ia64/module.h
+++ /dev/null
@@ -1,36 +0,0 @@
1#ifndef _ASM_IA64_MODULE_H
2#define _ASM_IA64_MODULE_H
3
4/*
5 * IA-64-specific support for kernel module loader.
6 *
7 * Copyright (C) 2003 Hewlett-Packard Co
8 * David Mosberger-Tang <davidm@hpl.hp.com>
9 */
10
11struct elf64_shdr; /* forward declration */
12
13struct mod_arch_specific {
14 struct elf64_shdr *core_plt; /* core PLT section */
15 struct elf64_shdr *init_plt; /* init PLT section */
16 struct elf64_shdr *got; /* global offset table */
17 struct elf64_shdr *opd; /* official procedure descriptors */
18 struct elf64_shdr *unwind; /* unwind-table section */
19 unsigned long gp; /* global-pointer for module */
20
21 void *core_unw_table; /* core unwind-table cookie returned by unwinder */
22 void *init_unw_table; /* init unwind-table cookie returned by unwinder */
23 unsigned int next_got_entry; /* index of next available got entry */
24};
25
26#define Elf_Shdr Elf64_Shdr
27#define Elf_Sym Elf64_Sym
28#define Elf_Ehdr Elf64_Ehdr
29
30#define MODULE_PROC_FAMILY "ia64"
31#define MODULE_ARCH_VERMAGIC MODULE_PROC_FAMILY \
32 "gcc-" __stringify(__GNUC__) "." __stringify(__GNUC_MINOR__)
33
34#define ARCH_SHF_SMALL SHF_IA_64_SHORT
35
36#endif /* _ASM_IA64_MODULE_H */
diff --git a/include/asm-ia64/msgbuf.h b/include/asm-ia64/msgbuf.h
deleted file mode 100644
index 6c64c0d2aae..00000000000
--- a/include/asm-ia64/msgbuf.h
+++ /dev/null
@@ -1,27 +0,0 @@
1#ifndef _ASM_IA64_MSGBUF_H
2#define _ASM_IA64_MSGBUF_H
3
4/*
5 * The msqid64_ds structure for IA-64 architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 2 miscellaneous 64-bit values
11 */
12
13struct msqid64_ds {
14 struct ipc64_perm msg_perm;
15 __kernel_time_t msg_stime; /* last msgsnd time */
16 __kernel_time_t msg_rtime; /* last msgrcv time */
17 __kernel_time_t msg_ctime; /* last change time */
18 unsigned long msg_cbytes; /* current number of bytes on queue */
19 unsigned long msg_qnum; /* number of messages in queue */
20 unsigned long msg_qbytes; /* max number of bytes on queue */
21 __kernel_pid_t msg_lspid; /* pid of last msgsnd */
22 __kernel_pid_t msg_lrpid; /* last receive pid */
23 unsigned long __unused1;
24 unsigned long __unused2;
25};
26
27#endif /* _ASM_IA64_MSGBUF_H */
diff --git a/include/asm-ia64/mutex.h b/include/asm-ia64/mutex.h
deleted file mode 100644
index bed73a643a5..00000000000
--- a/include/asm-ia64/mutex.h
+++ /dev/null
@@ -1,92 +0,0 @@
1/*
2 * ia64 implementation of the mutex fastpath.
3 *
4 * Copyright (C) 2006 Ken Chen <kenneth.w.chen@intel.com>
5 *
6 */
7
8#ifndef _ASM_MUTEX_H
9#define _ASM_MUTEX_H
10
11/**
12 * __mutex_fastpath_lock - try to take the lock by moving the count
13 * from 1 to a 0 value
14 * @count: pointer of type atomic_t
15 * @fail_fn: function to call if the original value was not 1
16 *
17 * Change the count from 1 to a value lower than 1, and call <fail_fn> if
18 * it wasn't 1 originally. This function MUST leave the value lower than
19 * 1 even when the "1" assertion wasn't true.
20 */
21static inline void
22__mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *))
23{
24 if (unlikely(ia64_fetchadd4_acq(count, -1) != 1))
25 fail_fn(count);
26}
27
28/**
29 * __mutex_fastpath_lock_retval - try to take the lock by moving the count
30 * from 1 to a 0 value
31 * @count: pointer of type atomic_t
32 * @fail_fn: function to call if the original value was not 1
33 *
34 * Change the count from 1 to a value lower than 1, and call <fail_fn> if
35 * it wasn't 1 originally. This function returns 0 if the fastpath succeeds,
36 * or anything the slow path function returns.
37 */
38static inline int
39__mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *))
40{
41 if (unlikely(ia64_fetchadd4_acq(count, -1) != 1))
42 return fail_fn(count);
43 return 0;
44}
45
46/**
47 * __mutex_fastpath_unlock - try to promote the count from 0 to 1
48 * @count: pointer of type atomic_t
49 * @fail_fn: function to call if the original value was not 0
50 *
51 * Try to promote the count from 0 to 1. If it wasn't 0, call <fail_fn>.
52 * In the failure case, this function is allowed to either set the value to
53 * 1, or to set it to a value lower than 1.
54 *
55 * If the implementation sets it to a value of lower than 1, then the
56 * __mutex_slowpath_needs_to_unlock() macro needs to return 1, it needs
57 * to return 0 otherwise.
58 */
59static inline void
60__mutex_fastpath_unlock(atomic_t *count, void (*fail_fn)(atomic_t *))
61{
62 int ret = ia64_fetchadd4_rel(count, 1);
63 if (unlikely(ret < 0))
64 fail_fn(count);
65}
66
67#define __mutex_slowpath_needs_to_unlock() 1
68
69/**
70 * __mutex_fastpath_trylock - try to acquire the mutex, without waiting
71 *
72 * @count: pointer of type atomic_t
73 * @fail_fn: fallback function
74 *
75 * Change the count from 1 to a value lower than 1, and return 0 (failure)
76 * if it wasn't 1 originally, or return 1 (success) otherwise. This function
77 * MUST leave the value lower than 1 even when the "1" assertion wasn't true.
78 * Additionally, if the value was < 0 originally, this function must not leave
79 * it to 0 on failure.
80 *
81 * If the architecture has no effective trylock variant, it should call the
82 * <fail_fn> spinlock-based trylock variant unconditionally.
83 */
84static inline int
85__mutex_fastpath_trylock(atomic_t *count, int (*fail_fn)(atomic_t *))
86{
87 if (cmpxchg_acq(count, 1, 0) == 1)
88 return 1;
89 return 0;
90}
91
92#endif
diff --git a/include/asm-ia64/native/inst.h b/include/asm-ia64/native/inst.h
deleted file mode 100644
index c953a2ca4fc..00000000000
--- a/include/asm-ia64/native/inst.h
+++ /dev/null
@@ -1,175 +0,0 @@
1/******************************************************************************
2 * include/asm-ia64/native/inst.h
3 *
4 * Copyright (c) 2008 Isaku Yamahata <yamahata at valinux co jp>
5 * VA Linux Systems Japan K.K.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22
23#define DO_SAVE_MIN IA64_NATIVE_DO_SAVE_MIN
24
25#define __paravirt_switch_to ia64_native_switch_to
26#define __paravirt_leave_syscall ia64_native_leave_syscall
27#define __paravirt_work_processed_syscall ia64_native_work_processed_syscall
28#define __paravirt_leave_kernel ia64_native_leave_kernel
29#define __paravirt_pending_syscall_end ia64_work_pending_syscall_end
30#define __paravirt_work_processed_syscall_target \
31 ia64_work_processed_syscall
32
33#ifdef CONFIG_PARAVIRT_GUEST_ASM_CLOBBER_CHECK
34# define PARAVIRT_POISON 0xdeadbeefbaadf00d
35# define CLOBBER(clob) \
36 ;; \
37 movl clob = PARAVIRT_POISON; \
38 ;;
39#else
40# define CLOBBER(clob) /* nothing */
41#endif
42
43#define MOV_FROM_IFA(reg) \
44 mov reg = cr.ifa
45
46#define MOV_FROM_ITIR(reg) \
47 mov reg = cr.itir
48
49#define MOV_FROM_ISR(reg) \
50 mov reg = cr.isr
51
52#define MOV_FROM_IHA(reg) \
53 mov reg = cr.iha
54
55#define MOV_FROM_IPSR(pred, reg) \
56(pred) mov reg = cr.ipsr
57
58#define MOV_FROM_IIM(reg) \
59 mov reg = cr.iim
60
61#define MOV_FROM_IIP(reg) \
62 mov reg = cr.iip
63
64#define MOV_FROM_IVR(reg, clob) \
65 mov reg = cr.ivr \
66 CLOBBER(clob)
67
68#define MOV_FROM_PSR(pred, reg, clob) \
69(pred) mov reg = psr \
70 CLOBBER(clob)
71
72#define MOV_TO_IFA(reg, clob) \
73 mov cr.ifa = reg \
74 CLOBBER(clob)
75
76#define MOV_TO_ITIR(pred, reg, clob) \
77(pred) mov cr.itir = reg \
78 CLOBBER(clob)
79
80#define MOV_TO_IHA(pred, reg, clob) \
81(pred) mov cr.iha = reg \
82 CLOBBER(clob)
83
84#define MOV_TO_IPSR(pred, reg, clob) \
85(pred) mov cr.ipsr = reg \
86 CLOBBER(clob)
87
88#define MOV_TO_IFS(pred, reg, clob) \
89(pred) mov cr.ifs = reg \
90 CLOBBER(clob)
91
92#define MOV_TO_IIP(reg, clob) \
93 mov cr.iip = reg \
94 CLOBBER(clob)
95
96#define MOV_TO_KR(kr, reg, clob0, clob1) \
97 mov IA64_KR(kr) = reg \
98 CLOBBER(clob0) \
99 CLOBBER(clob1)
100
101#define ITC_I(pred, reg, clob) \
102(pred) itc.i reg \
103 CLOBBER(clob)
104
105#define ITC_D(pred, reg, clob) \
106(pred) itc.d reg \
107 CLOBBER(clob)
108
109#define ITC_I_AND_D(pred_i, pred_d, reg, clob) \
110(pred_i) itc.i reg; \
111(pred_d) itc.d reg \
112 CLOBBER(clob)
113
114#define THASH(pred, reg0, reg1, clob) \
115(pred) thash reg0 = reg1 \
116 CLOBBER(clob)
117
118#define SSM_PSR_IC_AND_DEFAULT_BITS_AND_SRLZ_I(clob0, clob1) \
119 ssm psr.ic | PSR_DEFAULT_BITS \
120 CLOBBER(clob0) \
121 CLOBBER(clob1) \
122 ;; \
123 srlz.i /* guarantee that interruption collectin is on */ \
124 ;;
125
126#define SSM_PSR_IC_AND_SRLZ_D(clob0, clob1) \
127 ssm psr.ic \
128 CLOBBER(clob0) \
129 CLOBBER(clob1) \
130 ;; \
131 srlz.d
132
133#define RSM_PSR_IC(clob) \
134 rsm psr.ic \
135 CLOBBER(clob)
136
137#define SSM_PSR_I(pred, pred_clob, clob) \
138(pred) ssm psr.i \
139 CLOBBER(clob)
140
141#define RSM_PSR_I(pred, clob0, clob1) \
142(pred) rsm psr.i \
143 CLOBBER(clob0) \
144 CLOBBER(clob1)
145
146#define RSM_PSR_I_IC(clob0, clob1, clob2) \
147 rsm psr.i | psr.ic \
148 CLOBBER(clob0) \
149 CLOBBER(clob1) \
150 CLOBBER(clob2)
151
152#define RSM_PSR_DT \
153 rsm psr.dt
154
155#define SSM_PSR_DT_AND_SRLZ_I \
156 ssm psr.dt \
157 ;; \
158 srlz.i
159
160#define BSW_0(clob0, clob1, clob2) \
161 bsw.0 \
162 CLOBBER(clob0) \
163 CLOBBER(clob1) \
164 CLOBBER(clob2)
165
166#define BSW_1(clob0, clob1) \
167 bsw.1 \
168 CLOBBER(clob0) \
169 CLOBBER(clob1)
170
171#define COVER \
172 cover
173
174#define RFI \
175 rfi
diff --git a/include/asm-ia64/native/irq.h b/include/asm-ia64/native/irq.h
deleted file mode 100644
index efe9ff74a3c..00000000000
--- a/include/asm-ia64/native/irq.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/******************************************************************************
2 * include/asm-ia64/native/irq.h
3 *
4 * Copyright (c) 2008 Isaku Yamahata <yamahata at valinux co jp>
5 * VA Linux Systems Japan K.K.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 * moved from linux/include/asm-ia64/irq.h.
22 */
23
24#ifndef _ASM_IA64_NATIVE_IRQ_H
25#define _ASM_IA64_NATIVE_IRQ_H
26
27#define NR_VECTORS 256
28
29#if (NR_VECTORS + 32 * NR_CPUS) < 1024
30#define IA64_NATIVE_NR_IRQS (NR_VECTORS + 32 * NR_CPUS)
31#else
32#define IA64_NATIVE_NR_IRQS 1024
33#endif
34
35#endif /* _ASM_IA64_NATIVE_IRQ_H */
diff --git a/include/asm-ia64/nodedata.h b/include/asm-ia64/nodedata.h
deleted file mode 100644
index 2fb337b0e9b..00000000000
--- a/include/asm-ia64/nodedata.h
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (c) 2000 Silicon Graphics, Inc. All rights reserved.
7 * Copyright (c) 2002 NEC Corp.
8 * Copyright (c) 2002 Erich Focht <efocht@ess.nec.de>
9 * Copyright (c) 2002 Kimio Suganuma <k-suganuma@da.jp.nec.com>
10 */
11#ifndef _ASM_IA64_NODEDATA_H
12#define _ASM_IA64_NODEDATA_H
13
14#include <linux/numa.h>
15
16#include <asm/percpu.h>
17#include <asm/mmzone.h>
18
19#ifdef CONFIG_NUMA
20
21/*
22 * Node Data. One of these structures is located on each node of a NUMA system.
23 */
24
25struct pglist_data;
26struct ia64_node_data {
27 short active_cpu_count;
28 short node;
29 struct pglist_data *pg_data_ptrs[MAX_NUMNODES];
30};
31
32
33/*
34 * Return a pointer to the node_data structure for the executing cpu.
35 */
36#define local_node_data (local_cpu_data->node_data)
37
38/*
39 * Given a node id, return a pointer to the pg_data_t for the node.
40 *
41 * NODE_DATA - should be used in all code not related to system
42 * initialization. It uses pernode data structures to minimize
43 * offnode memory references. However, these structure are not
44 * present during boot. This macro can be used once cpu_init
45 * completes.
46 */
47#define NODE_DATA(nid) (local_node_data->pg_data_ptrs[nid])
48
49/*
50 * LOCAL_DATA_ADDR - This is to calculate the address of other node's
51 * "local_node_data" at hot-plug phase. The local_node_data
52 * is pointed by per_cpu_page. Kernel usually use it for
53 * just executing cpu. However, when new node is hot-added,
54 * the addresses of local data for other nodes are necessary
55 * to update all of them.
56 */
57#define LOCAL_DATA_ADDR(pgdat) \
58 ((struct ia64_node_data *)((u64)(pgdat) + \
59 L1_CACHE_ALIGN(sizeof(struct pglist_data))))
60
61#endif /* CONFIG_NUMA */
62
63#endif /* _ASM_IA64_NODEDATA_H */
diff --git a/include/asm-ia64/numa.h b/include/asm-ia64/numa.h
deleted file mode 100644
index 3499ff57bf4..00000000000
--- a/include/asm-ia64/numa.h
+++ /dev/null
@@ -1,82 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * This file contains NUMA specific prototypes and definitions.
7 *
8 * 2002/08/05 Erich Focht <efocht@ess.nec.de>
9 *
10 */
11#ifndef _ASM_IA64_NUMA_H
12#define _ASM_IA64_NUMA_H
13
14
15#ifdef CONFIG_NUMA
16
17#include <linux/cache.h>
18#include <linux/cpumask.h>
19#include <linux/numa.h>
20#include <linux/smp.h>
21#include <linux/threads.h>
22
23#include <asm/mmzone.h>
24
25#define NUMA_NO_NODE -1
26
27extern u16 cpu_to_node_map[NR_CPUS] __cacheline_aligned;
28extern cpumask_t node_to_cpu_mask[MAX_NUMNODES] __cacheline_aligned;
29extern pg_data_t *pgdat_list[MAX_NUMNODES];
30
31/* Stuff below this line could be architecture independent */
32
33extern int num_node_memblks; /* total number of memory chunks */
34
35/*
36 * List of node memory chunks. Filled when parsing SRAT table to
37 * obtain information about memory nodes.
38*/
39
40struct node_memblk_s {
41 unsigned long start_paddr;
42 unsigned long size;
43 int nid; /* which logical node contains this chunk? */
44 int bank; /* which mem bank on this node */
45};
46
47struct node_cpuid_s {
48 u16 phys_id; /* id << 8 | eid */
49 int nid; /* logical node containing this CPU */
50};
51
52extern struct node_memblk_s node_memblk[NR_NODE_MEMBLKS];
53extern struct node_cpuid_s node_cpuid[NR_CPUS];
54
55/*
56 * ACPI 2.0 SLIT (System Locality Information Table)
57 * http://devresource.hp.com/devresource/Docs/TechPapers/IA64/slit.pdf
58 *
59 * This is a matrix with "distances" between nodes, they should be
60 * proportional to the memory access latency ratios.
61 */
62
63extern u8 numa_slit[MAX_NUMNODES * MAX_NUMNODES];
64#define node_distance(from,to) (numa_slit[(from) * num_online_nodes() + (to)])
65
66extern int paddr_to_nid(unsigned long paddr);
67
68#define local_nodeid (cpu_to_node_map[smp_processor_id()])
69
70extern void map_cpu_to_node(int cpu, int nid);
71extern void unmap_cpu_from_node(int cpu, int nid);
72
73
74#else /* !CONFIG_NUMA */
75#define map_cpu_to_node(cpu, nid) do{}while(0)
76#define unmap_cpu_from_node(cpu, nid) do{}while(0)
77
78#define paddr_to_nid(addr) 0
79
80#endif /* CONFIG_NUMA */
81
82#endif /* _ASM_IA64_NUMA_H */
diff --git a/include/asm-ia64/page.h b/include/asm-ia64/page.h
deleted file mode 100644
index 5f271bc712e..00000000000
--- a/include/asm-ia64/page.h
+++ /dev/null
@@ -1,223 +0,0 @@
1#ifndef _ASM_IA64_PAGE_H
2#define _ASM_IA64_PAGE_H
3/*
4 * Pagetable related stuff.
5 *
6 * Copyright (C) 1998, 1999, 2002 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
8 */
9
10#include <asm/intrinsics.h>
11#include <asm/types.h>
12
13/*
14 * The top three bits of an IA64 address are its Region Number.
15 * Different regions are assigned to different purposes.
16 */
17#define RGN_SHIFT (61)
18#define RGN_BASE(r) (__IA64_UL_CONST(r)<<RGN_SHIFT)
19#define RGN_BITS (RGN_BASE(-1))
20
21#define RGN_KERNEL 7 /* Identity mapped region */
22#define RGN_UNCACHED 6 /* Identity mapped I/O region */
23#define RGN_GATE 5 /* Gate page, Kernel text, etc */
24#define RGN_HPAGE 4 /* For Huge TLB pages */
25
26/*
27 * PAGE_SHIFT determines the actual kernel page size.
28 */
29#if defined(CONFIG_IA64_PAGE_SIZE_4KB)
30# define PAGE_SHIFT 12
31#elif defined(CONFIG_IA64_PAGE_SIZE_8KB)
32# define PAGE_SHIFT 13
33#elif defined(CONFIG_IA64_PAGE_SIZE_16KB)
34# define PAGE_SHIFT 14
35#elif defined(CONFIG_IA64_PAGE_SIZE_64KB)
36# define PAGE_SHIFT 16
37#else
38# error Unsupported page size!
39#endif
40
41#define PAGE_SIZE (__IA64_UL_CONST(1) << PAGE_SHIFT)
42#define PAGE_MASK (~(PAGE_SIZE - 1))
43
44#define PERCPU_PAGE_SHIFT 16 /* log2() of max. size of per-CPU area */
45#define PERCPU_PAGE_SIZE (__IA64_UL_CONST(1) << PERCPU_PAGE_SHIFT)
46
47
48#ifdef CONFIG_HUGETLB_PAGE
49# define HPAGE_REGION_BASE RGN_BASE(RGN_HPAGE)
50# define HPAGE_SHIFT hpage_shift
51# define HPAGE_SHIFT_DEFAULT 28 /* check ia64 SDM for architecture supported size */
52# define HPAGE_SIZE (__IA64_UL_CONST(1) << HPAGE_SHIFT)
53# define HPAGE_MASK (~(HPAGE_SIZE - 1))
54
55# define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
56#endif /* CONFIG_HUGETLB_PAGE */
57
58#ifdef __ASSEMBLY__
59# define __pa(x) ((x) - PAGE_OFFSET)
60# define __va(x) ((x) + PAGE_OFFSET)
61#else /* !__ASSEMBLY */
62# define STRICT_MM_TYPECHECKS
63
64extern void clear_page (void *page);
65extern void copy_page (void *to, void *from);
66
67/*
68 * clear_user_page() and copy_user_page() can't be inline functions because
69 * flush_dcache_page() can't be defined until later...
70 */
71#define clear_user_page(addr, vaddr, page) \
72do { \
73 clear_page(addr); \
74 flush_dcache_page(page); \
75} while (0)
76
77#define copy_user_page(to, from, vaddr, page) \
78do { \
79 copy_page((to), (from)); \
80 flush_dcache_page(page); \
81} while (0)
82
83
84#define __alloc_zeroed_user_highpage(movableflags, vma, vaddr) \
85({ \
86 struct page *page = alloc_page_vma( \
87 GFP_HIGHUSER | __GFP_ZERO | movableflags, vma, vaddr); \
88 if (page) \
89 flush_dcache_page(page); \
90 page; \
91})
92
93#define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE
94
95#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
96
97#ifdef CONFIG_VIRTUAL_MEM_MAP
98extern int ia64_pfn_valid (unsigned long pfn);
99#else
100# define ia64_pfn_valid(pfn) 1
101#endif
102
103#ifdef CONFIG_VIRTUAL_MEM_MAP
104extern struct page *vmem_map;
105#ifdef CONFIG_DISCONTIGMEM
106# define page_to_pfn(page) ((unsigned long) (page - vmem_map))
107# define pfn_to_page(pfn) (vmem_map + (pfn))
108#else
109# include <asm-generic/memory_model.h>
110#endif
111#else
112# include <asm-generic/memory_model.h>
113#endif
114
115#ifdef CONFIG_FLATMEM
116# define pfn_valid(pfn) (((pfn) < max_mapnr) && ia64_pfn_valid(pfn))
117#elif defined(CONFIG_DISCONTIGMEM)
118extern unsigned long min_low_pfn;
119extern unsigned long max_low_pfn;
120# define pfn_valid(pfn) (((pfn) >= min_low_pfn) && ((pfn) < max_low_pfn) && ia64_pfn_valid(pfn))
121#endif
122
123#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
124#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
125#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
126
127typedef union ia64_va {
128 struct {
129 unsigned long off : 61; /* intra-region offset */
130 unsigned long reg : 3; /* region number */
131 } f;
132 unsigned long l;
133 void *p;
134} ia64_va;
135
136/*
137 * Note: These macros depend on the fact that PAGE_OFFSET has all
138 * region bits set to 1 and all other bits set to zero. They are
139 * expressed in this way to ensure they result in a single "dep"
140 * instruction.
141 */
142#define __pa(x) ({ia64_va _v; _v.l = (long) (x); _v.f.reg = 0; _v.l;})
143#define __va(x) ({ia64_va _v; _v.l = (long) (x); _v.f.reg = -1; _v.p;})
144
145#define REGION_NUMBER(x) ({ia64_va _v; _v.l = (long) (x); _v.f.reg;})
146#define REGION_OFFSET(x) ({ia64_va _v; _v.l = (long) (x); _v.f.off;})
147
148#ifdef CONFIG_HUGETLB_PAGE
149# define htlbpage_to_page(x) (((unsigned long) REGION_NUMBER(x) << 61) \
150 | (REGION_OFFSET(x) >> (HPAGE_SHIFT-PAGE_SHIFT)))
151# define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
152extern unsigned int hpage_shift;
153#endif
154
155static __inline__ int
156get_order (unsigned long size)
157{
158 long double d = size - 1;
159 long order;
160
161 order = ia64_getf_exp(d);
162 order = order - PAGE_SHIFT - 0xffff + 1;
163 if (order < 0)
164 order = 0;
165 return order;
166}
167
168#endif /* !__ASSEMBLY__ */
169
170#ifdef STRICT_MM_TYPECHECKS
171 /*
172 * These are used to make use of C type-checking..
173 */
174 typedef struct { unsigned long pte; } pte_t;
175 typedef struct { unsigned long pmd; } pmd_t;
176#ifdef CONFIG_PGTABLE_4
177 typedef struct { unsigned long pud; } pud_t;
178#endif
179 typedef struct { unsigned long pgd; } pgd_t;
180 typedef struct { unsigned long pgprot; } pgprot_t;
181 typedef struct page *pgtable_t;
182
183# define pte_val(x) ((x).pte)
184# define pmd_val(x) ((x).pmd)
185#ifdef CONFIG_PGTABLE_4
186# define pud_val(x) ((x).pud)
187#endif
188# define pgd_val(x) ((x).pgd)
189# define pgprot_val(x) ((x).pgprot)
190
191# define __pte(x) ((pte_t) { (x) } )
192# define __pgprot(x) ((pgprot_t) { (x) } )
193
194#else /* !STRICT_MM_TYPECHECKS */
195 /*
196 * .. while these make it easier on the compiler
197 */
198# ifndef __ASSEMBLY__
199 typedef unsigned long pte_t;
200 typedef unsigned long pmd_t;
201 typedef unsigned long pgd_t;
202 typedef unsigned long pgprot_t;
203 typedef struct page *pgtable_t;
204# endif
205
206# define pte_val(x) (x)
207# define pmd_val(x) (x)
208# define pgd_val(x) (x)
209# define pgprot_val(x) (x)
210
211# define __pte(x) (x)
212# define __pgd(x) (x)
213# define __pgprot(x) (x)
214#endif /* !STRICT_MM_TYPECHECKS */
215
216#define PAGE_OFFSET RGN_BASE(RGN_KERNEL)
217
218#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | \
219 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC | \
220 (((current->personality & READ_IMPLIES_EXEC) != 0) \
221 ? VM_EXEC : 0))
222
223#endif /* _ASM_IA64_PAGE_H */
diff --git a/include/asm-ia64/pal.h b/include/asm-ia64/pal.h
deleted file mode 100644
index 67b02901ead..00000000000
--- a/include/asm-ia64/pal.h
+++ /dev/null
@@ -1,1827 +0,0 @@
1#ifndef _ASM_IA64_PAL_H
2#define _ASM_IA64_PAL_H
3
4/*
5 * Processor Abstraction Layer definitions.
6 *
7 * This is based on Intel IA-64 Architecture Software Developer's Manual rev 1.0
8 * chapter 11 IA-64 Processor Abstraction Layer
9 *
10 * Copyright (C) 1998-2001 Hewlett-Packard Co
11 * David Mosberger-Tang <davidm@hpl.hp.com>
12 * Stephane Eranian <eranian@hpl.hp.com>
13 * Copyright (C) 1999 VA Linux Systems
14 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
15 * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com>
16 * Copyright (C) 2008 Silicon Graphics, Inc. (SGI)
17 *
18 * 99/10/01 davidm Make sure we pass zero for reserved parameters.
19 * 00/03/07 davidm Updated pal_cache_flush() to be in sync with PAL v2.6.
20 * 00/03/23 cfleck Modified processor min-state save area to match updated PAL & SAL info
21 * 00/05/24 eranian Updated to latest PAL spec, fix structures bugs, added
22 * 00/05/25 eranian Support for stack calls, and static physical calls
23 * 00/06/18 eranian Support for stacked physical calls
24 * 06/10/26 rja Support for Intel Itanium Architecture Software Developer's
25 * Manual Rev 2.2 (Jan 2006)
26 */
27
28/*
29 * Note that some of these calls use a static-register only calling
30 * convention which has nothing to do with the regular calling
31 * convention.
32 */
33#define PAL_CACHE_FLUSH 1 /* flush i/d cache */
34#define PAL_CACHE_INFO 2 /* get detailed i/d cache info */
35#define PAL_CACHE_INIT 3 /* initialize i/d cache */
36#define PAL_CACHE_SUMMARY 4 /* get summary of cache hierarchy */
37#define PAL_MEM_ATTRIB 5 /* list supported memory attributes */
38#define PAL_PTCE_INFO 6 /* purge TLB info */
39#define PAL_VM_INFO 7 /* return supported virtual memory features */
40#define PAL_VM_SUMMARY 8 /* return summary on supported vm features */
41#define PAL_BUS_GET_FEATURES 9 /* return processor bus interface features settings */
42#define PAL_BUS_SET_FEATURES 10 /* set processor bus features */
43#define PAL_DEBUG_INFO 11 /* get number of debug registers */
44#define PAL_FIXED_ADDR 12 /* get fixed component of processors's directed address */
45#define PAL_FREQ_BASE 13 /* base frequency of the platform */
46#define PAL_FREQ_RATIOS 14 /* ratio of processor, bus and ITC frequency */
47#define PAL_PERF_MON_INFO 15 /* return performance monitor info */
48#define PAL_PLATFORM_ADDR 16 /* set processor interrupt block and IO port space addr */
49#define PAL_PROC_GET_FEATURES 17 /* get configurable processor features & settings */
50#define PAL_PROC_SET_FEATURES 18 /* enable/disable configurable processor features */
51#define PAL_RSE_INFO 19 /* return rse information */
52#define PAL_VERSION 20 /* return version of PAL code */
53#define PAL_MC_CLEAR_LOG 21 /* clear all processor log info */
54#define PAL_MC_DRAIN 22 /* drain operations which could result in an MCA */
55#define PAL_MC_EXPECTED 23 /* set/reset expected MCA indicator */
56#define PAL_MC_DYNAMIC_STATE 24 /* get processor dynamic state */
57#define PAL_MC_ERROR_INFO 25 /* get processor MCA info and static state */
58#define PAL_MC_RESUME 26 /* Return to interrupted process */
59#define PAL_MC_REGISTER_MEM 27 /* Register memory for PAL to use during MCAs and inits */
60#define PAL_HALT 28 /* enter the low power HALT state */
61#define PAL_HALT_LIGHT 29 /* enter the low power light halt state*/
62#define PAL_COPY_INFO 30 /* returns info needed to relocate PAL */
63#define PAL_CACHE_LINE_INIT 31 /* init tags & data of cache line */
64#define PAL_PMI_ENTRYPOINT 32 /* register PMI memory entry points with the processor */
65#define PAL_ENTER_IA_32_ENV 33 /* enter IA-32 system environment */
66#define PAL_VM_PAGE_SIZE 34 /* return vm TC and page walker page sizes */
67
68#define PAL_MEM_FOR_TEST 37 /* get amount of memory needed for late processor test */
69#define PAL_CACHE_PROT_INFO 38 /* get i/d cache protection info */
70#define PAL_REGISTER_INFO 39 /* return AR and CR register information*/
71#define PAL_SHUTDOWN 40 /* enter processor shutdown state */
72#define PAL_PREFETCH_VISIBILITY 41 /* Make Processor Prefetches Visible */
73#define PAL_LOGICAL_TO_PHYSICAL 42 /* returns information on logical to physical processor mapping */
74#define PAL_CACHE_SHARED_INFO 43 /* returns information on caches shared by logical processor */
75#define PAL_GET_HW_POLICY 48 /* Get current hardware resource sharing policy */
76#define PAL_SET_HW_POLICY 49 /* Set current hardware resource sharing policy */
77#define PAL_VP_INFO 50 /* Information about virtual processor features */
78#define PAL_MC_HW_TRACKING 51 /* Hardware tracking status */
79
80#define PAL_COPY_PAL 256 /* relocate PAL procedures and PAL PMI */
81#define PAL_HALT_INFO 257 /* return the low power capabilities of processor */
82#define PAL_TEST_PROC 258 /* perform late processor self-test */
83#define PAL_CACHE_READ 259 /* read tag & data of cacheline for diagnostic testing */
84#define PAL_CACHE_WRITE 260 /* write tag & data of cacheline for diagnostic testing */
85#define PAL_VM_TR_READ 261 /* read contents of translation register */
86#define PAL_GET_PSTATE 262 /* get the current P-state */
87#define PAL_SET_PSTATE 263 /* set the P-state */
88#define PAL_BRAND_INFO 274 /* Processor branding information */
89
90#define PAL_GET_PSTATE_TYPE_LASTSET 0
91#define PAL_GET_PSTATE_TYPE_AVGANDRESET 1
92#define PAL_GET_PSTATE_TYPE_AVGNORESET 2
93#define PAL_GET_PSTATE_TYPE_INSTANT 3
94
95#define PAL_MC_ERROR_INJECT 276 /* Injects processor error or returns injection capabilities */
96
97#ifndef __ASSEMBLY__
98
99#include <linux/types.h>
100#include <asm/fpu.h>
101
102/*
103 * Data types needed to pass information into PAL procedures and
104 * interpret information returned by them.
105 */
106
107/* Return status from the PAL procedure */
108typedef s64 pal_status_t;
109
110#define PAL_STATUS_SUCCESS 0 /* No error */
111#define PAL_STATUS_UNIMPLEMENTED (-1) /* Unimplemented procedure */
112#define PAL_STATUS_EINVAL (-2) /* Invalid argument */
113#define PAL_STATUS_ERROR (-3) /* Error */
114#define PAL_STATUS_CACHE_INIT_FAIL (-4) /* Could not initialize the
115 * specified level and type of
116 * cache without sideeffects
117 * and "restrict" was 1
118 */
119#define PAL_STATUS_REQUIRES_MEMORY (-9) /* Call requires PAL memory buffer */
120
121/* Processor cache level in the hierarchy */
122typedef u64 pal_cache_level_t;
123#define PAL_CACHE_LEVEL_L0 0 /* L0 */
124#define PAL_CACHE_LEVEL_L1 1 /* L1 */
125#define PAL_CACHE_LEVEL_L2 2 /* L2 */
126
127
128/* Processor cache type at a particular level in the hierarchy */
129
130typedef u64 pal_cache_type_t;
131#define PAL_CACHE_TYPE_INSTRUCTION 1 /* Instruction cache */
132#define PAL_CACHE_TYPE_DATA 2 /* Data or unified cache */
133#define PAL_CACHE_TYPE_INSTRUCTION_DATA 3 /* Both Data & Instruction */
134
135
136#define PAL_CACHE_FLUSH_INVALIDATE 1 /* Invalidate clean lines */
137#define PAL_CACHE_FLUSH_CHK_INTRS 2 /* check for interrupts/mc while flushing */
138
139/* Processor cache line size in bytes */
140typedef int pal_cache_line_size_t;
141
142/* Processor cache line state */
143typedef u64 pal_cache_line_state_t;
144#define PAL_CACHE_LINE_STATE_INVALID 0 /* Invalid */
145#define PAL_CACHE_LINE_STATE_SHARED 1 /* Shared */
146#define PAL_CACHE_LINE_STATE_EXCLUSIVE 2 /* Exclusive */
147#define PAL_CACHE_LINE_STATE_MODIFIED 3 /* Modified */
148
149typedef struct pal_freq_ratio {
150 u32 den, num; /* numerator & denominator */
151} itc_ratio, proc_ratio;
152
153typedef union pal_cache_config_info_1_s {
154 struct {
155 u64 u : 1, /* 0 Unified cache ? */
156 at : 2, /* 2-1 Cache mem attr*/
157 reserved : 5, /* 7-3 Reserved */
158 associativity : 8, /* 16-8 Associativity*/
159 line_size : 8, /* 23-17 Line size */
160 stride : 8, /* 31-24 Stride */
161 store_latency : 8, /*39-32 Store latency*/
162 load_latency : 8, /* 47-40 Load latency*/
163 store_hints : 8, /* 55-48 Store hints*/
164 load_hints : 8; /* 63-56 Load hints */
165 } pcci1_bits;
166 u64 pcci1_data;
167} pal_cache_config_info_1_t;
168
169typedef union pal_cache_config_info_2_s {
170 struct {
171 u32 cache_size; /*cache size in bytes*/
172
173
174 u32 alias_boundary : 8, /* 39-32 aliased addr
175 * separation for max
176 * performance.
177 */
178 tag_ls_bit : 8, /* 47-40 LSb of addr*/
179 tag_ms_bit : 8, /* 55-48 MSb of addr*/
180 reserved : 8; /* 63-56 Reserved */
181 } pcci2_bits;
182 u64 pcci2_data;
183} pal_cache_config_info_2_t;
184
185
186typedef struct pal_cache_config_info_s {
187 pal_status_t pcci_status;
188 pal_cache_config_info_1_t pcci_info_1;
189 pal_cache_config_info_2_t pcci_info_2;
190 u64 pcci_reserved;
191} pal_cache_config_info_t;
192
193#define pcci_ld_hints pcci_info_1.pcci1_bits.load_hints
194#define pcci_st_hints pcci_info_1.pcci1_bits.store_hints
195#define pcci_ld_latency pcci_info_1.pcci1_bits.load_latency
196#define pcci_st_latency pcci_info_1.pcci1_bits.store_latency
197#define pcci_stride pcci_info_1.pcci1_bits.stride
198#define pcci_line_size pcci_info_1.pcci1_bits.line_size
199#define pcci_assoc pcci_info_1.pcci1_bits.associativity
200#define pcci_cache_attr pcci_info_1.pcci1_bits.at
201#define pcci_unified pcci_info_1.pcci1_bits.u
202#define pcci_tag_msb pcci_info_2.pcci2_bits.tag_ms_bit
203#define pcci_tag_lsb pcci_info_2.pcci2_bits.tag_ls_bit
204#define pcci_alias_boundary pcci_info_2.pcci2_bits.alias_boundary
205#define pcci_cache_size pcci_info_2.pcci2_bits.cache_size
206
207
208
209/* Possible values for cache attributes */
210
211#define PAL_CACHE_ATTR_WT 0 /* Write through cache */
212#define PAL_CACHE_ATTR_WB 1 /* Write back cache */
213#define PAL_CACHE_ATTR_WT_OR_WB 2 /* Either write thru or write
214 * back depending on TLB
215 * memory attributes
216 */
217
218
219/* Possible values for cache hints */
220
221#define PAL_CACHE_HINT_TEMP_1 0 /* Temporal level 1 */
222#define PAL_CACHE_HINT_NTEMP_1 1 /* Non-temporal level 1 */
223#define PAL_CACHE_HINT_NTEMP_ALL 3 /* Non-temporal all levels */
224
225/* Processor cache protection information */
226typedef union pal_cache_protection_element_u {
227 u32 pcpi_data;
228 struct {
229 u32 data_bits : 8, /* # data bits covered by
230 * each unit of protection
231 */
232
233 tagprot_lsb : 6, /* Least -do- */
234 tagprot_msb : 6, /* Most Sig. tag address
235 * bit that this
236 * protection covers.
237 */
238 prot_bits : 6, /* # of protection bits */
239 method : 4, /* Protection method */
240 t_d : 2; /* Indicates which part
241 * of the cache this
242 * protection encoding
243 * applies.
244 */
245 } pcp_info;
246} pal_cache_protection_element_t;
247
248#define pcpi_cache_prot_part pcp_info.t_d
249#define pcpi_prot_method pcp_info.method
250#define pcpi_prot_bits pcp_info.prot_bits
251#define pcpi_tagprot_msb pcp_info.tagprot_msb
252#define pcpi_tagprot_lsb pcp_info.tagprot_lsb
253#define pcpi_data_bits pcp_info.data_bits
254
255/* Processor cache part encodings */
256#define PAL_CACHE_PROT_PART_DATA 0 /* Data protection */
257#define PAL_CACHE_PROT_PART_TAG 1 /* Tag protection */
258#define PAL_CACHE_PROT_PART_TAG_DATA 2 /* Tag+data protection (tag is
259 * more significant )
260 */
261#define PAL_CACHE_PROT_PART_DATA_TAG 3 /* Data+tag protection (data is
262 * more significant )
263 */
264#define PAL_CACHE_PROT_PART_MAX 6
265
266
267typedef struct pal_cache_protection_info_s {
268 pal_status_t pcpi_status;
269 pal_cache_protection_element_t pcp_info[PAL_CACHE_PROT_PART_MAX];
270} pal_cache_protection_info_t;
271
272
273/* Processor cache protection method encodings */
274#define PAL_CACHE_PROT_METHOD_NONE 0 /* No protection */
275#define PAL_CACHE_PROT_METHOD_ODD_PARITY 1 /* Odd parity */
276#define PAL_CACHE_PROT_METHOD_EVEN_PARITY 2 /* Even parity */
277#define PAL_CACHE_PROT_METHOD_ECC 3 /* ECC protection */
278
279
280/* Processor cache line identification in the hierarchy */
281typedef union pal_cache_line_id_u {
282 u64 pclid_data;
283 struct {
284 u64 cache_type : 8, /* 7-0 cache type */
285 level : 8, /* 15-8 level of the
286 * cache in the
287 * hierarchy.
288 */
289 way : 8, /* 23-16 way in the set
290 */
291 part : 8, /* 31-24 part of the
292 * cache
293 */
294 reserved : 32; /* 63-32 is reserved*/
295 } pclid_info_read;
296 struct {
297 u64 cache_type : 8, /* 7-0 cache type */
298 level : 8, /* 15-8 level of the
299 * cache in the
300 * hierarchy.
301 */
302 way : 8, /* 23-16 way in the set
303 */
304 part : 8, /* 31-24 part of the
305 * cache
306 */
307 mesi : 8, /* 39-32 cache line
308 * state
309 */
310 start : 8, /* 47-40 lsb of data to
311 * invert
312 */
313 length : 8, /* 55-48 #bits to
314 * invert
315 */
316 trigger : 8; /* 63-56 Trigger error
317 * by doing a load
318 * after the write
319 */
320
321 } pclid_info_write;
322} pal_cache_line_id_u_t;
323
324#define pclid_read_part pclid_info_read.part
325#define pclid_read_way pclid_info_read.way
326#define pclid_read_level pclid_info_read.level
327#define pclid_read_cache_type pclid_info_read.cache_type
328
329#define pclid_write_trigger pclid_info_write.trigger
330#define pclid_write_length pclid_info_write.length
331#define pclid_write_start pclid_info_write.start
332#define pclid_write_mesi pclid_info_write.mesi
333#define pclid_write_part pclid_info_write.part
334#define pclid_write_way pclid_info_write.way
335#define pclid_write_level pclid_info_write.level
336#define pclid_write_cache_type pclid_info_write.cache_type
337
338/* Processor cache line part encodings */
339#define PAL_CACHE_LINE_ID_PART_DATA 0 /* Data */
340#define PAL_CACHE_LINE_ID_PART_TAG 1 /* Tag */
341#define PAL_CACHE_LINE_ID_PART_DATA_PROT 2 /* Data protection */
342#define PAL_CACHE_LINE_ID_PART_TAG_PROT 3 /* Tag protection */
343#define PAL_CACHE_LINE_ID_PART_DATA_TAG_PROT 4 /* Data+tag
344 * protection
345 */
346typedef struct pal_cache_line_info_s {
347 pal_status_t pcli_status; /* Return status of the read cache line
348 * info call.
349 */
350 u64 pcli_data; /* 64-bit data, tag, protection bits .. */
351 u64 pcli_data_len; /* data length in bits */
352 pal_cache_line_state_t pcli_cache_line_state; /* mesi state */
353
354} pal_cache_line_info_t;
355
356
357/* Machine Check related crap */
358
359/* Pending event status bits */
360typedef u64 pal_mc_pending_events_t;
361
362#define PAL_MC_PENDING_MCA (1 << 0)
363#define PAL_MC_PENDING_INIT (1 << 1)
364
365/* Error information type */
366typedef u64 pal_mc_info_index_t;
367
368#define PAL_MC_INFO_PROCESSOR 0 /* Processor */
369#define PAL_MC_INFO_CACHE_CHECK 1 /* Cache check */
370#define PAL_MC_INFO_TLB_CHECK 2 /* Tlb check */
371#define PAL_MC_INFO_BUS_CHECK 3 /* Bus check */
372#define PAL_MC_INFO_REQ_ADDR 4 /* Requestor address */
373#define PAL_MC_INFO_RESP_ADDR 5 /* Responder address */
374#define PAL_MC_INFO_TARGET_ADDR 6 /* Target address */
375#define PAL_MC_INFO_IMPL_DEP 7 /* Implementation
376 * dependent
377 */
378
379#define PAL_TLB_CHECK_OP_PURGE 8
380
381typedef struct pal_process_state_info_s {
382 u64 reserved1 : 2,
383 rz : 1, /* PAL_CHECK processor
384 * rendezvous
385 * successful.
386 */
387
388 ra : 1, /* PAL_CHECK attempted
389 * a rendezvous.
390 */
391 me : 1, /* Distinct multiple
392 * errors occurred
393 */
394
395 mn : 1, /* Min. state save
396 * area has been
397 * registered with PAL
398 */
399
400 sy : 1, /* Storage integrity
401 * synched
402 */
403
404
405 co : 1, /* Continuable */
406 ci : 1, /* MC isolated */
407 us : 1, /* Uncontained storage
408 * damage.
409 */
410
411
412 hd : 1, /* Non-essential hw
413 * lost (no loss of
414 * functionality)
415 * causing the
416 * processor to run in
417 * degraded mode.
418 */
419
420 tl : 1, /* 1 => MC occurred
421 * after an instr was
422 * executed but before
423 * the trap that
424 * resulted from instr
425 * execution was
426 * generated.
427 * (Trap Lost )
428 */
429 mi : 1, /* More information available
430 * call PAL_MC_ERROR_INFO
431 */
432 pi : 1, /* Precise instruction pointer */
433 pm : 1, /* Precise min-state save area */
434
435 dy : 1, /* Processor dynamic
436 * state valid
437 */
438
439
440 in : 1, /* 0 = MC, 1 = INIT */
441 rs : 1, /* RSE valid */
442 cm : 1, /* MC corrected */
443 ex : 1, /* MC is expected */
444 cr : 1, /* Control regs valid*/
445 pc : 1, /* Perf cntrs valid */
446 dr : 1, /* Debug regs valid */
447 tr : 1, /* Translation regs
448 * valid
449 */
450 rr : 1, /* Region regs valid */
451 ar : 1, /* App regs valid */
452 br : 1, /* Branch regs valid */
453 pr : 1, /* Predicate registers
454 * valid
455 */
456
457 fp : 1, /* fp registers valid*/
458 b1 : 1, /* Preserved bank one
459 * general registers
460 * are valid
461 */
462 b0 : 1, /* Preserved bank zero
463 * general registers
464 * are valid
465 */
466 gr : 1, /* General registers
467 * are valid
468 * (excl. banked regs)
469 */
470 dsize : 16, /* size of dynamic
471 * state returned
472 * by the processor
473 */
474
475 se : 1, /* Shared error. MCA in a
476 shared structure */
477 reserved2 : 10,
478 cc : 1, /* Cache check */
479 tc : 1, /* TLB check */
480 bc : 1, /* Bus check */
481 rc : 1, /* Register file check */
482 uc : 1; /* Uarch check */
483
484} pal_processor_state_info_t;
485
486typedef struct pal_cache_check_info_s {
487 u64 op : 4, /* Type of cache
488 * operation that
489 * caused the machine
490 * check.
491 */
492 level : 2, /* Cache level */
493 reserved1 : 2,
494 dl : 1, /* Failure in data part
495 * of cache line
496 */
497 tl : 1, /* Failure in tag part
498 * of cache line
499 */
500 dc : 1, /* Failure in dcache */
501 ic : 1, /* Failure in icache */
502 mesi : 3, /* Cache line state */
503 mv : 1, /* mesi valid */
504 way : 5, /* Way in which the
505 * error occurred
506 */
507 wiv : 1, /* Way field valid */
508 reserved2 : 1,
509 dp : 1, /* Data poisoned on MBE */
510 reserved3 : 6,
511 hlth : 2, /* Health indicator */
512
513 index : 20, /* Cache line index */
514 reserved4 : 2,
515
516 is : 1, /* instruction set (1 == ia32) */
517 iv : 1, /* instruction set field valid */
518 pl : 2, /* privilege level */
519 pv : 1, /* privilege level field valid */
520 mcc : 1, /* Machine check corrected */
521 tv : 1, /* Target address
522 * structure is valid
523 */
524 rq : 1, /* Requester identifier
525 * structure is valid
526 */
527 rp : 1, /* Responder identifier
528 * structure is valid
529 */
530 pi : 1; /* Precise instruction pointer
531 * structure is valid
532 */
533} pal_cache_check_info_t;
534
535typedef struct pal_tlb_check_info_s {
536
537 u64 tr_slot : 8, /* Slot# of TR where
538 * error occurred
539 */
540 trv : 1, /* tr_slot field is valid */
541 reserved1 : 1,
542 level : 2, /* TLB level where failure occurred */
543 reserved2 : 4,
544 dtr : 1, /* Fail in data TR */
545 itr : 1, /* Fail in inst TR */
546 dtc : 1, /* Fail in data TC */
547 itc : 1, /* Fail in inst. TC */
548 op : 4, /* Cache operation */
549 reserved3 : 6,
550 hlth : 2, /* Health indicator */
551 reserved4 : 22,
552
553 is : 1, /* instruction set (1 == ia32) */
554 iv : 1, /* instruction set field valid */
555 pl : 2, /* privilege level */
556 pv : 1, /* privilege level field valid */
557 mcc : 1, /* Machine check corrected */
558 tv : 1, /* Target address
559 * structure is valid
560 */
561 rq : 1, /* Requester identifier
562 * structure is valid
563 */
564 rp : 1, /* Responder identifier
565 * structure is valid
566 */
567 pi : 1; /* Precise instruction pointer
568 * structure is valid
569 */
570} pal_tlb_check_info_t;
571
572typedef struct pal_bus_check_info_s {
573 u64 size : 5, /* Xaction size */
574 ib : 1, /* Internal bus error */
575 eb : 1, /* External bus error */
576 cc : 1, /* Error occurred
577 * during cache-cache
578 * transfer.
579 */
580 type : 8, /* Bus xaction type*/
581 sev : 5, /* Bus error severity*/
582 hier : 2, /* Bus hierarchy level */
583 dp : 1, /* Data poisoned on MBE */
584 bsi : 8, /* Bus error status
585 * info
586 */
587 reserved2 : 22,
588
589 is : 1, /* instruction set (1 == ia32) */
590 iv : 1, /* instruction set field valid */
591 pl : 2, /* privilege level */
592 pv : 1, /* privilege level field valid */
593 mcc : 1, /* Machine check corrected */
594 tv : 1, /* Target address
595 * structure is valid
596 */
597 rq : 1, /* Requester identifier
598 * structure is valid
599 */
600 rp : 1, /* Responder identifier
601 * structure is valid
602 */
603 pi : 1; /* Precise instruction pointer
604 * structure is valid
605 */
606} pal_bus_check_info_t;
607
608typedef struct pal_reg_file_check_info_s {
609 u64 id : 4, /* Register file identifier */
610 op : 4, /* Type of register
611 * operation that
612 * caused the machine
613 * check.
614 */
615 reg_num : 7, /* Register number */
616 rnv : 1, /* reg_num valid */
617 reserved2 : 38,
618
619 is : 1, /* instruction set (1 == ia32) */
620 iv : 1, /* instruction set field valid */
621 pl : 2, /* privilege level */
622 pv : 1, /* privilege level field valid */
623 mcc : 1, /* Machine check corrected */
624 reserved3 : 3,
625 pi : 1; /* Precise instruction pointer
626 * structure is valid
627 */
628} pal_reg_file_check_info_t;
629
630typedef struct pal_uarch_check_info_s {
631 u64 sid : 5, /* Structure identification */
632 level : 3, /* Level of failure */
633 array_id : 4, /* Array identification */
634 op : 4, /* Type of
635 * operation that
636 * caused the machine
637 * check.
638 */
639 way : 6, /* Way of structure */
640 wv : 1, /* way valid */
641 xv : 1, /* index valid */
642 reserved1 : 6,
643 hlth : 2, /* Health indicator */
644 index : 8, /* Index or set of the uarch
645 * structure that failed.
646 */
647 reserved2 : 24,
648
649 is : 1, /* instruction set (1 == ia32) */
650 iv : 1, /* instruction set field valid */
651 pl : 2, /* privilege level */
652 pv : 1, /* privilege level field valid */
653 mcc : 1, /* Machine check corrected */
654 tv : 1, /* Target address
655 * structure is valid
656 */
657 rq : 1, /* Requester identifier
658 * structure is valid
659 */
660 rp : 1, /* Responder identifier
661 * structure is valid
662 */
663 pi : 1; /* Precise instruction pointer
664 * structure is valid
665 */
666} pal_uarch_check_info_t;
667
668typedef union pal_mc_error_info_u {
669 u64 pmei_data;
670 pal_processor_state_info_t pme_processor;
671 pal_cache_check_info_t pme_cache;
672 pal_tlb_check_info_t pme_tlb;
673 pal_bus_check_info_t pme_bus;
674 pal_reg_file_check_info_t pme_reg_file;
675 pal_uarch_check_info_t pme_uarch;
676} pal_mc_error_info_t;
677
678#define pmci_proc_unknown_check pme_processor.uc
679#define pmci_proc_bus_check pme_processor.bc
680#define pmci_proc_tlb_check pme_processor.tc
681#define pmci_proc_cache_check pme_processor.cc
682#define pmci_proc_dynamic_state_size pme_processor.dsize
683#define pmci_proc_gpr_valid pme_processor.gr
684#define pmci_proc_preserved_bank0_gpr_valid pme_processor.b0
685#define pmci_proc_preserved_bank1_gpr_valid pme_processor.b1
686#define pmci_proc_fp_valid pme_processor.fp
687#define pmci_proc_predicate_regs_valid pme_processor.pr
688#define pmci_proc_branch_regs_valid pme_processor.br
689#define pmci_proc_app_regs_valid pme_processor.ar
690#define pmci_proc_region_regs_valid pme_processor.rr
691#define pmci_proc_translation_regs_valid pme_processor.tr
692#define pmci_proc_debug_regs_valid pme_processor.dr
693#define pmci_proc_perf_counters_valid pme_processor.pc
694#define pmci_proc_control_regs_valid pme_processor.cr
695#define pmci_proc_machine_check_expected pme_processor.ex
696#define pmci_proc_machine_check_corrected pme_processor.cm
697#define pmci_proc_rse_valid pme_processor.rs
698#define pmci_proc_machine_check_or_init pme_processor.in
699#define pmci_proc_dynamic_state_valid pme_processor.dy
700#define pmci_proc_operation pme_processor.op
701#define pmci_proc_trap_lost pme_processor.tl
702#define pmci_proc_hardware_damage pme_processor.hd
703#define pmci_proc_uncontained_storage_damage pme_processor.us
704#define pmci_proc_machine_check_isolated pme_processor.ci
705#define pmci_proc_continuable pme_processor.co
706#define pmci_proc_storage_intergrity_synced pme_processor.sy
707#define pmci_proc_min_state_save_area_regd pme_processor.mn
708#define pmci_proc_distinct_multiple_errors pme_processor.me
709#define pmci_proc_pal_attempted_rendezvous pme_processor.ra
710#define pmci_proc_pal_rendezvous_complete pme_processor.rz
711
712
713#define pmci_cache_level pme_cache.level
714#define pmci_cache_line_state pme_cache.mesi
715#define pmci_cache_line_state_valid pme_cache.mv
716#define pmci_cache_line_index pme_cache.index
717#define pmci_cache_instr_cache_fail pme_cache.ic
718#define pmci_cache_data_cache_fail pme_cache.dc
719#define pmci_cache_line_tag_fail pme_cache.tl
720#define pmci_cache_line_data_fail pme_cache.dl
721#define pmci_cache_operation pme_cache.op
722#define pmci_cache_way_valid pme_cache.wv
723#define pmci_cache_target_address_valid pme_cache.tv
724#define pmci_cache_way pme_cache.way
725#define pmci_cache_mc pme_cache.mc
726
727#define pmci_tlb_instr_translation_cache_fail pme_tlb.itc
728#define pmci_tlb_data_translation_cache_fail pme_tlb.dtc
729#define pmci_tlb_instr_translation_reg_fail pme_tlb.itr
730#define pmci_tlb_data_translation_reg_fail pme_tlb.dtr
731#define pmci_tlb_translation_reg_slot pme_tlb.tr_slot
732#define pmci_tlb_mc pme_tlb.mc
733
734#define pmci_bus_status_info pme_bus.bsi
735#define pmci_bus_req_address_valid pme_bus.rq
736#define pmci_bus_resp_address_valid pme_bus.rp
737#define pmci_bus_target_address_valid pme_bus.tv
738#define pmci_bus_error_severity pme_bus.sev
739#define pmci_bus_transaction_type pme_bus.type
740#define pmci_bus_cache_cache_transfer pme_bus.cc
741#define pmci_bus_transaction_size pme_bus.size
742#define pmci_bus_internal_error pme_bus.ib
743#define pmci_bus_external_error pme_bus.eb
744#define pmci_bus_mc pme_bus.mc
745
746/*
747 * NOTE: this min_state_save area struct only includes the 1KB
748 * architectural state save area. The other 3 KB is scratch space
749 * for PAL.
750 */
751
752typedef struct pal_min_state_area_s {
753 u64 pmsa_nat_bits; /* nat bits for saved GRs */
754 u64 pmsa_gr[15]; /* GR1 - GR15 */
755 u64 pmsa_bank0_gr[16]; /* GR16 - GR31 */
756 u64 pmsa_bank1_gr[16]; /* GR16 - GR31 */
757 u64 pmsa_pr; /* predicate registers */
758 u64 pmsa_br0; /* branch register 0 */
759 u64 pmsa_rsc; /* ar.rsc */
760 u64 pmsa_iip; /* cr.iip */
761 u64 pmsa_ipsr; /* cr.ipsr */
762 u64 pmsa_ifs; /* cr.ifs */
763 u64 pmsa_xip; /* previous iip */
764 u64 pmsa_xpsr; /* previous psr */
765 u64 pmsa_xfs; /* previous ifs */
766 u64 pmsa_br1; /* branch register 1 */
767 u64 pmsa_reserved[70]; /* pal_min_state_area should total to 1KB */
768} pal_min_state_area_t;
769
770
771struct ia64_pal_retval {
772 /*
773 * A zero status value indicates call completed without error.
774 * A negative status value indicates reason of call failure.
775 * A positive status value indicates success but an
776 * informational value should be printed (e.g., "reboot for
777 * change to take effect").
778 */
779 s64 status;
780 u64 v0;
781 u64 v1;
782 u64 v2;
783};
784
785/*
786 * Note: Currently unused PAL arguments are generally labeled
787 * "reserved" so the value specified in the PAL documentation
788 * (generally 0) MUST be passed. Reserved parameters are not optional
789 * parameters.
790 */
791extern struct ia64_pal_retval ia64_pal_call_static (u64, u64, u64, u64);
792extern struct ia64_pal_retval ia64_pal_call_stacked (u64, u64, u64, u64);
793extern struct ia64_pal_retval ia64_pal_call_phys_static (u64, u64, u64, u64);
794extern struct ia64_pal_retval ia64_pal_call_phys_stacked (u64, u64, u64, u64);
795extern void ia64_save_scratch_fpregs (struct ia64_fpreg *);
796extern void ia64_load_scratch_fpregs (struct ia64_fpreg *);
797
798#define PAL_CALL(iprv,a0,a1,a2,a3) do { \
799 struct ia64_fpreg fr[6]; \
800 ia64_save_scratch_fpregs(fr); \
801 iprv = ia64_pal_call_static(a0, a1, a2, a3); \
802 ia64_load_scratch_fpregs(fr); \
803} while (0)
804
805#define PAL_CALL_STK(iprv,a0,a1,a2,a3) do { \
806 struct ia64_fpreg fr[6]; \
807 ia64_save_scratch_fpregs(fr); \
808 iprv = ia64_pal_call_stacked(a0, a1, a2, a3); \
809 ia64_load_scratch_fpregs(fr); \
810} while (0)
811
812#define PAL_CALL_PHYS(iprv,a0,a1,a2,a3) do { \
813 struct ia64_fpreg fr[6]; \
814 ia64_save_scratch_fpregs(fr); \
815 iprv = ia64_pal_call_phys_static(a0, a1, a2, a3); \
816 ia64_load_scratch_fpregs(fr); \
817} while (0)
818
819#define PAL_CALL_PHYS_STK(iprv,a0,a1,a2,a3) do { \
820 struct ia64_fpreg fr[6]; \
821 ia64_save_scratch_fpregs(fr); \
822 iprv = ia64_pal_call_phys_stacked(a0, a1, a2, a3); \
823 ia64_load_scratch_fpregs(fr); \
824} while (0)
825
826typedef int (*ia64_pal_handler) (u64, ...);
827extern ia64_pal_handler ia64_pal;
828extern void ia64_pal_handler_init (void *);
829
830extern ia64_pal_handler ia64_pal;
831
832extern pal_cache_config_info_t l0d_cache_config_info;
833extern pal_cache_config_info_t l0i_cache_config_info;
834extern pal_cache_config_info_t l1_cache_config_info;
835extern pal_cache_config_info_t l2_cache_config_info;
836
837extern pal_cache_protection_info_t l0d_cache_protection_info;
838extern pal_cache_protection_info_t l0i_cache_protection_info;
839extern pal_cache_protection_info_t l1_cache_protection_info;
840extern pal_cache_protection_info_t l2_cache_protection_info;
841
842extern pal_cache_config_info_t pal_cache_config_info_get(pal_cache_level_t,
843 pal_cache_type_t);
844
845extern pal_cache_protection_info_t pal_cache_protection_info_get(pal_cache_level_t,
846 pal_cache_type_t);
847
848
849extern void pal_error(int);
850
851
852/* Useful wrappers for the current list of pal procedures */
853
854typedef union pal_bus_features_u {
855 u64 pal_bus_features_val;
856 struct {
857 u64 pbf_reserved1 : 29;
858 u64 pbf_req_bus_parking : 1;
859 u64 pbf_bus_lock_mask : 1;
860 u64 pbf_enable_half_xfer_rate : 1;
861 u64 pbf_reserved2 : 20;
862 u64 pbf_enable_shared_line_replace : 1;
863 u64 pbf_enable_exclusive_line_replace : 1;
864 u64 pbf_disable_xaction_queueing : 1;
865 u64 pbf_disable_resp_err_check : 1;
866 u64 pbf_disable_berr_check : 1;
867 u64 pbf_disable_bus_req_internal_err_signal : 1;
868 u64 pbf_disable_bus_req_berr_signal : 1;
869 u64 pbf_disable_bus_init_event_check : 1;
870 u64 pbf_disable_bus_init_event_signal : 1;
871 u64 pbf_disable_bus_addr_err_check : 1;
872 u64 pbf_disable_bus_addr_err_signal : 1;
873 u64 pbf_disable_bus_data_err_check : 1;
874 } pal_bus_features_s;
875} pal_bus_features_u_t;
876
877extern void pal_bus_features_print (u64);
878
879/* Provide information about configurable processor bus features */
880static inline s64
881ia64_pal_bus_get_features (pal_bus_features_u_t *features_avail,
882 pal_bus_features_u_t *features_status,
883 pal_bus_features_u_t *features_control)
884{
885 struct ia64_pal_retval iprv;
886 PAL_CALL_PHYS(iprv, PAL_BUS_GET_FEATURES, 0, 0, 0);
887 if (features_avail)
888 features_avail->pal_bus_features_val = iprv.v0;
889 if (features_status)
890 features_status->pal_bus_features_val = iprv.v1;
891 if (features_control)
892 features_control->pal_bus_features_val = iprv.v2;
893 return iprv.status;
894}
895
896/* Enables/disables specific processor bus features */
897static inline s64
898ia64_pal_bus_set_features (pal_bus_features_u_t feature_select)
899{
900 struct ia64_pal_retval iprv;
901 PAL_CALL_PHYS(iprv, PAL_BUS_SET_FEATURES, feature_select.pal_bus_features_val, 0, 0);
902 return iprv.status;
903}
904
905/* Get detailed cache information */
906static inline s64
907ia64_pal_cache_config_info (u64 cache_level, u64 cache_type, pal_cache_config_info_t *conf)
908{
909 struct ia64_pal_retval iprv;
910
911 PAL_CALL(iprv, PAL_CACHE_INFO, cache_level, cache_type, 0);
912
913 if (iprv.status == 0) {
914 conf->pcci_status = iprv.status;
915 conf->pcci_info_1.pcci1_data = iprv.v0;
916 conf->pcci_info_2.pcci2_data = iprv.v1;
917 conf->pcci_reserved = iprv.v2;
918 }
919 return iprv.status;
920
921}
922
923/* Get detailed cche protection information */
924static inline s64
925ia64_pal_cache_prot_info (u64 cache_level, u64 cache_type, pal_cache_protection_info_t *prot)
926{
927 struct ia64_pal_retval iprv;
928
929 PAL_CALL(iprv, PAL_CACHE_PROT_INFO, cache_level, cache_type, 0);
930
931 if (iprv.status == 0) {
932 prot->pcpi_status = iprv.status;
933 prot->pcp_info[0].pcpi_data = iprv.v0 & 0xffffffff;
934 prot->pcp_info[1].pcpi_data = iprv.v0 >> 32;
935 prot->pcp_info[2].pcpi_data = iprv.v1 & 0xffffffff;
936 prot->pcp_info[3].pcpi_data = iprv.v1 >> 32;
937 prot->pcp_info[4].pcpi_data = iprv.v2 & 0xffffffff;
938 prot->pcp_info[5].pcpi_data = iprv.v2 >> 32;
939 }
940 return iprv.status;
941}
942
943/*
944 * Flush the processor instruction or data caches. *PROGRESS must be
945 * initialized to zero before calling this for the first time..
946 */
947static inline s64
948ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector)
949{
950 struct ia64_pal_retval iprv;
951 PAL_CALL(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
952 if (vector)
953 *vector = iprv.v0;
954 *progress = iprv.v1;
955 return iprv.status;
956}
957
958
959/* Initialize the processor controlled caches */
960static inline s64
961ia64_pal_cache_init (u64 level, u64 cache_type, u64 rest)
962{
963 struct ia64_pal_retval iprv;
964 PAL_CALL(iprv, PAL_CACHE_INIT, level, cache_type, rest);
965 return iprv.status;
966}
967
968/* Initialize the tags and data of a data or unified cache line of
969 * processor controlled cache to known values without the availability
970 * of backing memory.
971 */
972static inline s64
973ia64_pal_cache_line_init (u64 physical_addr, u64 data_value)
974{
975 struct ia64_pal_retval iprv;
976 PAL_CALL(iprv, PAL_CACHE_LINE_INIT, physical_addr, data_value, 0);
977 return iprv.status;
978}
979
980
981/* Read the data and tag of a processor controlled cache line for diags */
982static inline s64
983ia64_pal_cache_read (pal_cache_line_id_u_t line_id, u64 physical_addr)
984{
985 struct ia64_pal_retval iprv;
986 PAL_CALL_PHYS_STK(iprv, PAL_CACHE_READ, line_id.pclid_data,
987 physical_addr, 0);
988 return iprv.status;
989}
990
991/* Return summary information about the hierarchy of caches controlled by the processor */
992static inline s64
993ia64_pal_cache_summary (u64 *cache_levels, u64 *unique_caches)
994{
995 struct ia64_pal_retval iprv;
996 PAL_CALL(iprv, PAL_CACHE_SUMMARY, 0, 0, 0);
997 if (cache_levels)
998 *cache_levels = iprv.v0;
999 if (unique_caches)
1000 *unique_caches = iprv.v1;
1001 return iprv.status;
1002}
1003
1004/* Write the data and tag of a processor-controlled cache line for diags */
1005static inline s64
1006ia64_pal_cache_write (pal_cache_line_id_u_t line_id, u64 physical_addr, u64 data)
1007{
1008 struct ia64_pal_retval iprv;
1009 PAL_CALL_PHYS_STK(iprv, PAL_CACHE_WRITE, line_id.pclid_data,
1010 physical_addr, data);
1011 return iprv.status;
1012}
1013
1014
1015/* Return the parameters needed to copy relocatable PAL procedures from ROM to memory */
1016static inline s64
1017ia64_pal_copy_info (u64 copy_type, u64 num_procs, u64 num_iopics,
1018 u64 *buffer_size, u64 *buffer_align)
1019{
1020 struct ia64_pal_retval iprv;
1021 PAL_CALL(iprv, PAL_COPY_INFO, copy_type, num_procs, num_iopics);
1022 if (buffer_size)
1023 *buffer_size = iprv.v0;
1024 if (buffer_align)
1025 *buffer_align = iprv.v1;
1026 return iprv.status;
1027}
1028
1029/* Copy relocatable PAL procedures from ROM to memory */
1030static inline s64
1031ia64_pal_copy_pal (u64 target_addr, u64 alloc_size, u64 processor, u64 *pal_proc_offset)
1032{
1033 struct ia64_pal_retval iprv;
1034 PAL_CALL(iprv, PAL_COPY_PAL, target_addr, alloc_size, processor);
1035 if (pal_proc_offset)
1036 *pal_proc_offset = iprv.v0;
1037 return iprv.status;
1038}
1039
1040/* Return the number of instruction and data debug register pairs */
1041static inline s64
1042ia64_pal_debug_info (u64 *inst_regs, u64 *data_regs)
1043{
1044 struct ia64_pal_retval iprv;
1045 PAL_CALL(iprv, PAL_DEBUG_INFO, 0, 0, 0);
1046 if (inst_regs)
1047 *inst_regs = iprv.v0;
1048 if (data_regs)
1049 *data_regs = iprv.v1;
1050
1051 return iprv.status;
1052}
1053
1054#ifdef TBD
1055/* Switch from IA64-system environment to IA-32 system environment */
1056static inline s64
1057ia64_pal_enter_ia32_env (ia32_env1, ia32_env2, ia32_env3)
1058{
1059 struct ia64_pal_retval iprv;
1060 PAL_CALL(iprv, PAL_ENTER_IA_32_ENV, ia32_env1, ia32_env2, ia32_env3);
1061 return iprv.status;
1062}
1063#endif
1064
1065/* Get unique geographical address of this processor on its bus */
1066static inline s64
1067ia64_pal_fixed_addr (u64 *global_unique_addr)
1068{
1069 struct ia64_pal_retval iprv;
1070 PAL_CALL(iprv, PAL_FIXED_ADDR, 0, 0, 0);
1071 if (global_unique_addr)
1072 *global_unique_addr = iprv.v0;
1073 return iprv.status;
1074}
1075
1076/* Get base frequency of the platform if generated by the processor */
1077static inline s64
1078ia64_pal_freq_base (u64 *platform_base_freq)
1079{
1080 struct ia64_pal_retval iprv;
1081 PAL_CALL(iprv, PAL_FREQ_BASE, 0, 0, 0);
1082 if (platform_base_freq)
1083 *platform_base_freq = iprv.v0;
1084 return iprv.status;
1085}
1086
1087/*
1088 * Get the ratios for processor frequency, bus frequency and interval timer to
1089 * to base frequency of the platform
1090 */
1091static inline s64
1092ia64_pal_freq_ratios (struct pal_freq_ratio *proc_ratio, struct pal_freq_ratio *bus_ratio,
1093 struct pal_freq_ratio *itc_ratio)
1094{
1095 struct ia64_pal_retval iprv;
1096 PAL_CALL(iprv, PAL_FREQ_RATIOS, 0, 0, 0);
1097 if (proc_ratio)
1098 *(u64 *)proc_ratio = iprv.v0;
1099 if (bus_ratio)
1100 *(u64 *)bus_ratio = iprv.v1;
1101 if (itc_ratio)
1102 *(u64 *)itc_ratio = iprv.v2;
1103 return iprv.status;
1104}
1105
1106/*
1107 * Get the current hardware resource sharing policy of the processor
1108 */
1109static inline s64
1110ia64_pal_get_hw_policy (u64 proc_num, u64 *cur_policy, u64 *num_impacted,
1111 u64 *la)
1112{
1113 struct ia64_pal_retval iprv;
1114 PAL_CALL(iprv, PAL_GET_HW_POLICY, proc_num, 0, 0);
1115 if (cur_policy)
1116 *cur_policy = iprv.v0;
1117 if (num_impacted)
1118 *num_impacted = iprv.v1;
1119 if (la)
1120 *la = iprv.v2;
1121 return iprv.status;
1122}
1123
1124/* Make the processor enter HALT or one of the implementation dependent low
1125 * power states where prefetching and execution are suspended and cache and
1126 * TLB coherency is not maintained.
1127 */
1128static inline s64
1129ia64_pal_halt (u64 halt_state)
1130{
1131 struct ia64_pal_retval iprv;
1132 PAL_CALL(iprv, PAL_HALT, halt_state, 0, 0);
1133 return iprv.status;
1134}
1135
1136typedef union pal_power_mgmt_info_u {
1137 u64 ppmi_data;
1138 struct {
1139 u64 exit_latency : 16,
1140 entry_latency : 16,
1141 power_consumption : 28,
1142 im : 1,
1143 co : 1,
1144 reserved : 2;
1145 } pal_power_mgmt_info_s;
1146} pal_power_mgmt_info_u_t;
1147
1148/* Return information about processor's optional power management capabilities. */
1149static inline s64
1150ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf)
1151{
1152 struct ia64_pal_retval iprv;
1153 PAL_CALL_STK(iprv, PAL_HALT_INFO, (unsigned long) power_buf, 0, 0);
1154 return iprv.status;
1155}
1156
1157/* Get the current P-state information */
1158static inline s64
1159ia64_pal_get_pstate (u64 *pstate_index, unsigned long type)
1160{
1161 struct ia64_pal_retval iprv;
1162 PAL_CALL_STK(iprv, PAL_GET_PSTATE, type, 0, 0);
1163 *pstate_index = iprv.v0;
1164 return iprv.status;
1165}
1166
1167/* Set the P-state */
1168static inline s64
1169ia64_pal_set_pstate (u64 pstate_index)
1170{
1171 struct ia64_pal_retval iprv;
1172 PAL_CALL_STK(iprv, PAL_SET_PSTATE, pstate_index, 0, 0);
1173 return iprv.status;
1174}
1175
1176/* Processor branding information*/
1177static inline s64
1178ia64_pal_get_brand_info (char *brand_info)
1179{
1180 struct ia64_pal_retval iprv;
1181 PAL_CALL_STK(iprv, PAL_BRAND_INFO, 0, (u64)brand_info, 0);
1182 return iprv.status;
1183}
1184
1185/* Cause the processor to enter LIGHT HALT state, where prefetching and execution are
1186 * suspended, but cache and TLB coherency is maintained.
1187 */
1188static inline s64
1189ia64_pal_halt_light (void)
1190{
1191 struct ia64_pal_retval iprv;
1192 PAL_CALL(iprv, PAL_HALT_LIGHT, 0, 0, 0);
1193 return iprv.status;
1194}
1195
1196/* Clear all the processor error logging registers and reset the indicator that allows
1197 * the error logging registers to be written. This procedure also checks the pending
1198 * machine check bit and pending INIT bit and reports their states.
1199 */
1200static inline s64
1201ia64_pal_mc_clear_log (u64 *pending_vector)
1202{
1203 struct ia64_pal_retval iprv;
1204 PAL_CALL(iprv, PAL_MC_CLEAR_LOG, 0, 0, 0);
1205 if (pending_vector)
1206 *pending_vector = iprv.v0;
1207 return iprv.status;
1208}
1209
1210/* Ensure that all outstanding transactions in a processor are completed or that any
1211 * MCA due to thes outstanding transaction is taken.
1212 */
1213static inline s64
1214ia64_pal_mc_drain (void)
1215{
1216 struct ia64_pal_retval iprv;
1217 PAL_CALL(iprv, PAL_MC_DRAIN, 0, 0, 0);
1218 return iprv.status;
1219}
1220
1221/* Return the machine check dynamic processor state */
1222static inline s64
1223ia64_pal_mc_dynamic_state (u64 info_type, u64 dy_buffer, u64 *size)
1224{
1225 struct ia64_pal_retval iprv;
1226 PAL_CALL(iprv, PAL_MC_DYNAMIC_STATE, info_type, dy_buffer, 0);
1227 if (size)
1228 *size = iprv.v0;
1229 return iprv.status;
1230}
1231
1232/* Return processor machine check information */
1233static inline s64
1234ia64_pal_mc_error_info (u64 info_index, u64 type_index, u64 *size, u64 *error_info)
1235{
1236 struct ia64_pal_retval iprv;
1237 PAL_CALL(iprv, PAL_MC_ERROR_INFO, info_index, type_index, 0);
1238 if (size)
1239 *size = iprv.v0;
1240 if (error_info)
1241 *error_info = iprv.v1;
1242 return iprv.status;
1243}
1244
1245/* Injects the requested processor error or returns info on
1246 * supported injection capabilities for current processor implementation
1247 */
1248static inline s64
1249ia64_pal_mc_error_inject_phys (u64 err_type_info, u64 err_struct_info,
1250 u64 err_data_buffer, u64 *capabilities, u64 *resources)
1251{
1252 struct ia64_pal_retval iprv;
1253 PAL_CALL_PHYS_STK(iprv, PAL_MC_ERROR_INJECT, err_type_info,
1254 err_struct_info, err_data_buffer);
1255 if (capabilities)
1256 *capabilities= iprv.v0;
1257 if (resources)
1258 *resources= iprv.v1;
1259 return iprv.status;
1260}
1261
1262static inline s64
1263ia64_pal_mc_error_inject_virt (u64 err_type_info, u64 err_struct_info,
1264 u64 err_data_buffer, u64 *capabilities, u64 *resources)
1265{
1266 struct ia64_pal_retval iprv;
1267 PAL_CALL_STK(iprv, PAL_MC_ERROR_INJECT, err_type_info,
1268 err_struct_info, err_data_buffer);
1269 if (capabilities)
1270 *capabilities= iprv.v0;
1271 if (resources)
1272 *resources= iprv.v1;
1273 return iprv.status;
1274}
1275
1276/* Inform PALE_CHECK whether a machine check is expected so that PALE_CHECK willnot
1277 * attempt to correct any expected machine checks.
1278 */
1279static inline s64
1280ia64_pal_mc_expected (u64 expected, u64 *previous)
1281{
1282 struct ia64_pal_retval iprv;
1283 PAL_CALL(iprv, PAL_MC_EXPECTED, expected, 0, 0);
1284 if (previous)
1285 *previous = iprv.v0;
1286 return iprv.status;
1287}
1288
1289typedef union pal_hw_tracking_u {
1290 u64 pht_data;
1291 struct {
1292 u64 itc :4, /* Instruction cache tracking */
1293 dct :4, /* Date cache tracking */
1294 itt :4, /* Instruction TLB tracking */
1295 ddt :4, /* Data TLB tracking */
1296 reserved:48;
1297 } pal_hw_tracking_s;
1298} pal_hw_tracking_u_t;
1299
1300/*
1301 * Hardware tracking status.
1302 */
1303static inline s64
1304ia64_pal_mc_hw_tracking (u64 *status)
1305{
1306 struct ia64_pal_retval iprv;
1307 PAL_CALL(iprv, PAL_MC_HW_TRACKING, 0, 0, 0);
1308 if (status)
1309 *status = iprv.v0;
1310 return iprv.status;
1311}
1312
1313/* Register a platform dependent location with PAL to which it can save
1314 * minimal processor state in the event of a machine check or initialization
1315 * event.
1316 */
1317static inline s64
1318ia64_pal_mc_register_mem (u64 physical_addr, u64 size, u64 *req_size)
1319{
1320 struct ia64_pal_retval iprv;
1321 PAL_CALL(iprv, PAL_MC_REGISTER_MEM, physical_addr, size, 0);
1322 if (req_size)
1323 *req_size = iprv.v0;
1324 return iprv.status;
1325}
1326
1327/* Restore minimal architectural processor state, set CMC interrupt if necessary
1328 * and resume execution
1329 */
1330static inline s64
1331ia64_pal_mc_resume (u64 set_cmci, u64 save_ptr)
1332{
1333 struct ia64_pal_retval iprv;
1334 PAL_CALL(iprv, PAL_MC_RESUME, set_cmci, save_ptr, 0);
1335 return iprv.status;
1336}
1337
1338/* Return the memory attributes implemented by the processor */
1339static inline s64
1340ia64_pal_mem_attrib (u64 *mem_attrib)
1341{
1342 struct ia64_pal_retval iprv;
1343 PAL_CALL(iprv, PAL_MEM_ATTRIB, 0, 0, 0);
1344 if (mem_attrib)
1345 *mem_attrib = iprv.v0 & 0xff;
1346 return iprv.status;
1347}
1348
1349/* Return the amount of memory needed for second phase of processor
1350 * self-test and the required alignment of memory.
1351 */
1352static inline s64
1353ia64_pal_mem_for_test (u64 *bytes_needed, u64 *alignment)
1354{
1355 struct ia64_pal_retval iprv;
1356 PAL_CALL(iprv, PAL_MEM_FOR_TEST, 0, 0, 0);
1357 if (bytes_needed)
1358 *bytes_needed = iprv.v0;
1359 if (alignment)
1360 *alignment = iprv.v1;
1361 return iprv.status;
1362}
1363
1364typedef union pal_perf_mon_info_u {
1365 u64 ppmi_data;
1366 struct {
1367 u64 generic : 8,
1368 width : 8,
1369 cycles : 8,
1370 retired : 8,
1371 reserved : 32;
1372 } pal_perf_mon_info_s;
1373} pal_perf_mon_info_u_t;
1374
1375/* Return the performance monitor information about what can be counted
1376 * and how to configure the monitors to count the desired events.
1377 */
1378static inline s64
1379ia64_pal_perf_mon_info (u64 *pm_buffer, pal_perf_mon_info_u_t *pm_info)
1380{
1381 struct ia64_pal_retval iprv;
1382 PAL_CALL(iprv, PAL_PERF_MON_INFO, (unsigned long) pm_buffer, 0, 0);
1383 if (pm_info)
1384 pm_info->ppmi_data = iprv.v0;
1385 return iprv.status;
1386}
1387
1388/* Specifies the physical address of the processor interrupt block
1389 * and I/O port space.
1390 */
1391static inline s64
1392ia64_pal_platform_addr (u64 type, u64 physical_addr)
1393{
1394 struct ia64_pal_retval iprv;
1395 PAL_CALL(iprv, PAL_PLATFORM_ADDR, type, physical_addr, 0);
1396 return iprv.status;
1397}
1398
1399/* Set the SAL PMI entrypoint in memory */
1400static inline s64
1401ia64_pal_pmi_entrypoint (u64 sal_pmi_entry_addr)
1402{
1403 struct ia64_pal_retval iprv;
1404 PAL_CALL(iprv, PAL_PMI_ENTRYPOINT, sal_pmi_entry_addr, 0, 0);
1405 return iprv.status;
1406}
1407
1408struct pal_features_s;
1409/* Provide information about configurable processor features */
1410static inline s64
1411ia64_pal_proc_get_features (u64 *features_avail,
1412 u64 *features_status,
1413 u64 *features_control,
1414 u64 features_set)
1415{
1416 struct ia64_pal_retval iprv;
1417 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, features_set, 0);
1418 if (iprv.status == 0) {
1419 *features_avail = iprv.v0;
1420 *features_status = iprv.v1;
1421 *features_control = iprv.v2;
1422 }
1423 return iprv.status;
1424}
1425
1426/* Enable/disable processor dependent features */
1427static inline s64
1428ia64_pal_proc_set_features (u64 feature_select)
1429{
1430 struct ia64_pal_retval iprv;
1431 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, feature_select, 0, 0);
1432 return iprv.status;
1433}
1434
1435/*
1436 * Put everything in a struct so we avoid the global offset table whenever
1437 * possible.
1438 */
1439typedef struct ia64_ptce_info_s {
1440 u64 base;
1441 u32 count[2];
1442 u32 stride[2];
1443} ia64_ptce_info_t;
1444
1445/* Return the information required for the architected loop used to purge
1446 * (initialize) the entire TC
1447 */
1448static inline s64
1449ia64_get_ptce (ia64_ptce_info_t *ptce)
1450{
1451 struct ia64_pal_retval iprv;
1452
1453 if (!ptce)
1454 return -1;
1455
1456 PAL_CALL(iprv, PAL_PTCE_INFO, 0, 0, 0);
1457 if (iprv.status == 0) {
1458 ptce->base = iprv.v0;
1459 ptce->count[0] = iprv.v1 >> 32;
1460 ptce->count[1] = iprv.v1 & 0xffffffff;
1461 ptce->stride[0] = iprv.v2 >> 32;
1462 ptce->stride[1] = iprv.v2 & 0xffffffff;
1463 }
1464 return iprv.status;
1465}
1466
1467/* Return info about implemented application and control registers. */
1468static inline s64
1469ia64_pal_register_info (u64 info_request, u64 *reg_info_1, u64 *reg_info_2)
1470{
1471 struct ia64_pal_retval iprv;
1472 PAL_CALL(iprv, PAL_REGISTER_INFO, info_request, 0, 0);
1473 if (reg_info_1)
1474 *reg_info_1 = iprv.v0;
1475 if (reg_info_2)
1476 *reg_info_2 = iprv.v1;
1477 return iprv.status;
1478}
1479
1480typedef union pal_hints_u {
1481 u64 ph_data;
1482 struct {
1483 u64 si : 1,
1484 li : 1,
1485 reserved : 62;
1486 } pal_hints_s;
1487} pal_hints_u_t;
1488
1489/* Return information about the register stack and RSE for this processor
1490 * implementation.
1491 */
1492static inline s64
1493ia64_pal_rse_info (u64 *num_phys_stacked, pal_hints_u_t *hints)
1494{
1495 struct ia64_pal_retval iprv;
1496 PAL_CALL(iprv, PAL_RSE_INFO, 0, 0, 0);
1497 if (num_phys_stacked)
1498 *num_phys_stacked = iprv.v0;
1499 if (hints)
1500 hints->ph_data = iprv.v1;
1501 return iprv.status;
1502}
1503
1504/*
1505 * Set the current hardware resource sharing policy of the processor
1506 */
1507static inline s64
1508ia64_pal_set_hw_policy (u64 policy)
1509{
1510 struct ia64_pal_retval iprv;
1511 PAL_CALL(iprv, PAL_SET_HW_POLICY, policy, 0, 0);
1512 return iprv.status;
1513}
1514
1515/* Cause the processor to enter SHUTDOWN state, where prefetching and execution are
1516 * suspended, but cause cache and TLB coherency to be maintained.
1517 * This is usually called in IA-32 mode.
1518 */
1519static inline s64
1520ia64_pal_shutdown (void)
1521{
1522 struct ia64_pal_retval iprv;
1523 PAL_CALL(iprv, PAL_SHUTDOWN, 0, 0, 0);
1524 return iprv.status;
1525}
1526
1527/* Perform the second phase of processor self-test. */
1528static inline s64
1529ia64_pal_test_proc (u64 test_addr, u64 test_size, u64 attributes, u64 *self_test_state)
1530{
1531 struct ia64_pal_retval iprv;
1532 PAL_CALL(iprv, PAL_TEST_PROC, test_addr, test_size, attributes);
1533 if (self_test_state)
1534 *self_test_state = iprv.v0;
1535 return iprv.status;
1536}
1537
1538typedef union pal_version_u {
1539 u64 pal_version_val;
1540 struct {
1541 u64 pv_pal_b_rev : 8;
1542 u64 pv_pal_b_model : 8;
1543 u64 pv_reserved1 : 8;
1544 u64 pv_pal_vendor : 8;
1545 u64 pv_pal_a_rev : 8;
1546 u64 pv_pal_a_model : 8;
1547 u64 pv_reserved2 : 16;
1548 } pal_version_s;
1549} pal_version_u_t;
1550
1551
1552/*
1553 * Return PAL version information. While the documentation states that
1554 * PAL_VERSION can be called in either physical or virtual mode, some
1555 * implementations only allow physical calls. We don't call it very often,
1556 * so the overhead isn't worth eliminating.
1557 */
1558static inline s64
1559ia64_pal_version (pal_version_u_t *pal_min_version, pal_version_u_t *pal_cur_version)
1560{
1561 struct ia64_pal_retval iprv;
1562 PAL_CALL_PHYS(iprv, PAL_VERSION, 0, 0, 0);
1563 if (pal_min_version)
1564 pal_min_version->pal_version_val = iprv.v0;
1565
1566 if (pal_cur_version)
1567 pal_cur_version->pal_version_val = iprv.v1;
1568
1569 return iprv.status;
1570}
1571
1572typedef union pal_tc_info_u {
1573 u64 pti_val;
1574 struct {
1575 u64 num_sets : 8,
1576 associativity : 8,
1577 num_entries : 16,
1578 pf : 1,
1579 unified : 1,
1580 reduce_tr : 1,
1581 reserved : 29;
1582 } pal_tc_info_s;
1583} pal_tc_info_u_t;
1584
1585#define tc_reduce_tr pal_tc_info_s.reduce_tr
1586#define tc_unified pal_tc_info_s.unified
1587#define tc_pf pal_tc_info_s.pf
1588#define tc_num_entries pal_tc_info_s.num_entries
1589#define tc_associativity pal_tc_info_s.associativity
1590#define tc_num_sets pal_tc_info_s.num_sets
1591
1592
1593/* Return information about the virtual memory characteristics of the processor
1594 * implementation.
1595 */
1596static inline s64
1597ia64_pal_vm_info (u64 tc_level, u64 tc_type, pal_tc_info_u_t *tc_info, u64 *tc_pages)
1598{
1599 struct ia64_pal_retval iprv;
1600 PAL_CALL(iprv, PAL_VM_INFO, tc_level, tc_type, 0);
1601 if (tc_info)
1602 tc_info->pti_val = iprv.v0;
1603 if (tc_pages)
1604 *tc_pages = iprv.v1;
1605 return iprv.status;
1606}
1607
1608/* Get page size information about the virtual memory characteristics of the processor
1609 * implementation.
1610 */
1611static inline s64
1612ia64_pal_vm_page_size (u64 *tr_pages, u64 *vw_pages)
1613{
1614 struct ia64_pal_retval iprv;
1615 PAL_CALL(iprv, PAL_VM_PAGE_SIZE, 0, 0, 0);
1616 if (tr_pages)
1617 *tr_pages = iprv.v0;
1618 if (vw_pages)
1619 *vw_pages = iprv.v1;
1620 return iprv.status;
1621}
1622
1623typedef union pal_vm_info_1_u {
1624 u64 pvi1_val;
1625 struct {
1626 u64 vw : 1,
1627 phys_add_size : 7,
1628 key_size : 8,
1629 max_pkr : 8,
1630 hash_tag_id : 8,
1631 max_dtr_entry : 8,
1632 max_itr_entry : 8,
1633 max_unique_tcs : 8,
1634 num_tc_levels : 8;
1635 } pal_vm_info_1_s;
1636} pal_vm_info_1_u_t;
1637
1638#define PAL_MAX_PURGES 0xFFFF /* all ones is means unlimited */
1639
1640typedef union pal_vm_info_2_u {
1641 u64 pvi2_val;
1642 struct {
1643 u64 impl_va_msb : 8,
1644 rid_size : 8,
1645 max_purges : 16,
1646 reserved : 32;
1647 } pal_vm_info_2_s;
1648} pal_vm_info_2_u_t;
1649
1650/* Get summary information about the virtual memory characteristics of the processor
1651 * implementation.
1652 */
1653static inline s64
1654ia64_pal_vm_summary (pal_vm_info_1_u_t *vm_info_1, pal_vm_info_2_u_t *vm_info_2)
1655{
1656 struct ia64_pal_retval iprv;
1657 PAL_CALL(iprv, PAL_VM_SUMMARY, 0, 0, 0);
1658 if (vm_info_1)
1659 vm_info_1->pvi1_val = iprv.v0;
1660 if (vm_info_2)
1661 vm_info_2->pvi2_val = iprv.v1;
1662 return iprv.status;
1663}
1664
1665typedef union pal_vp_info_u {
1666 u64 pvi_val;
1667 struct {
1668 u64 index: 48, /* virtual feature set info */
1669 vmm_id: 16; /* feature set id */
1670 } pal_vp_info_s;
1671} pal_vp_info_u_t;
1672
1673/*
1674 * Returns infomation about virtual processor features
1675 */
1676static inline s64
1677ia64_pal_vp_info (u64 feature_set, u64 vp_buffer, u64 *vp_info, u64 *vmm_id)
1678{
1679 struct ia64_pal_retval iprv;
1680 PAL_CALL(iprv, PAL_VP_INFO, feature_set, vp_buffer, 0);
1681 if (vp_info)
1682 *vp_info = iprv.v0;
1683 if (vmm_id)
1684 *vmm_id = iprv.v1;
1685 return iprv.status;
1686}
1687
1688typedef union pal_itr_valid_u {
1689 u64 piv_val;
1690 struct {
1691 u64 access_rights_valid : 1,
1692 priv_level_valid : 1,
1693 dirty_bit_valid : 1,
1694 mem_attr_valid : 1,
1695 reserved : 60;
1696 } pal_tr_valid_s;
1697} pal_tr_valid_u_t;
1698
1699/* Read a translation register */
1700static inline s64
1701ia64_pal_tr_read (u64 reg_num, u64 tr_type, u64 *tr_buffer, pal_tr_valid_u_t *tr_valid)
1702{
1703 struct ia64_pal_retval iprv;
1704 PAL_CALL_PHYS_STK(iprv, PAL_VM_TR_READ, reg_num, tr_type,(u64)ia64_tpa(tr_buffer));
1705 if (tr_valid)
1706 tr_valid->piv_val = iprv.v0;
1707 return iprv.status;
1708}
1709
1710/*
1711 * PAL_PREFETCH_VISIBILITY transaction types
1712 */
1713#define PAL_VISIBILITY_VIRTUAL 0
1714#define PAL_VISIBILITY_PHYSICAL 1
1715
1716/*
1717 * PAL_PREFETCH_VISIBILITY return codes
1718 */
1719#define PAL_VISIBILITY_OK 1
1720#define PAL_VISIBILITY_OK_REMOTE_NEEDED 0
1721#define PAL_VISIBILITY_INVAL_ARG -2
1722#define PAL_VISIBILITY_ERROR -3
1723
1724static inline s64
1725ia64_pal_prefetch_visibility (s64 trans_type)
1726{
1727 struct ia64_pal_retval iprv;
1728 PAL_CALL(iprv, PAL_PREFETCH_VISIBILITY, trans_type, 0, 0);
1729 return iprv.status;
1730}
1731
1732/* data structure for getting information on logical to physical mappings */
1733typedef union pal_log_overview_u {
1734 struct {
1735 u64 num_log :16, /* Total number of logical
1736 * processors on this die
1737 */
1738 tpc :8, /* Threads per core */
1739 reserved3 :8, /* Reserved */
1740 cpp :8, /* Cores per processor */
1741 reserved2 :8, /* Reserved */
1742 ppid :8, /* Physical processor ID */
1743 reserved1 :8; /* Reserved */
1744 } overview_bits;
1745 u64 overview_data;
1746} pal_log_overview_t;
1747
1748typedef union pal_proc_n_log_info1_u{
1749 struct {
1750 u64 tid :16, /* Thread id */
1751 reserved2 :16, /* Reserved */
1752 cid :16, /* Core id */
1753 reserved1 :16; /* Reserved */
1754 } ppli1_bits;
1755 u64 ppli1_data;
1756} pal_proc_n_log_info1_t;
1757
1758typedef union pal_proc_n_log_info2_u {
1759 struct {
1760 u64 la :16, /* Logical address */
1761 reserved :48; /* Reserved */
1762 } ppli2_bits;
1763 u64 ppli2_data;
1764} pal_proc_n_log_info2_t;
1765
1766typedef struct pal_logical_to_physical_s
1767{
1768 pal_log_overview_t overview;
1769 pal_proc_n_log_info1_t ppli1;
1770 pal_proc_n_log_info2_t ppli2;
1771} pal_logical_to_physical_t;
1772
1773#define overview_num_log overview.overview_bits.num_log
1774#define overview_tpc overview.overview_bits.tpc
1775#define overview_cpp overview.overview_bits.cpp
1776#define overview_ppid overview.overview_bits.ppid
1777#define log1_tid ppli1.ppli1_bits.tid
1778#define log1_cid ppli1.ppli1_bits.cid
1779#define log2_la ppli2.ppli2_bits.la
1780
1781/* Get information on logical to physical processor mappings. */
1782static inline s64
1783ia64_pal_logical_to_phys(u64 proc_number, pal_logical_to_physical_t *mapping)
1784{
1785 struct ia64_pal_retval iprv;
1786
1787 PAL_CALL(iprv, PAL_LOGICAL_TO_PHYSICAL, proc_number, 0, 0);
1788
1789 if (iprv.status == PAL_STATUS_SUCCESS)
1790 {
1791 mapping->overview.overview_data = iprv.v0;
1792 mapping->ppli1.ppli1_data = iprv.v1;
1793 mapping->ppli2.ppli2_data = iprv.v2;
1794 }
1795
1796 return iprv.status;
1797}
1798
1799typedef struct pal_cache_shared_info_s
1800{
1801 u64 num_shared;
1802 pal_proc_n_log_info1_t ppli1;
1803 pal_proc_n_log_info2_t ppli2;
1804} pal_cache_shared_info_t;
1805
1806/* Get information on logical to physical processor mappings. */
1807static inline s64
1808ia64_pal_cache_shared_info(u64 level,
1809 u64 type,
1810 u64 proc_number,
1811 pal_cache_shared_info_t *info)
1812{
1813 struct ia64_pal_retval iprv;
1814
1815 PAL_CALL(iprv, PAL_CACHE_SHARED_INFO, level, type, proc_number);
1816
1817 if (iprv.status == PAL_STATUS_SUCCESS) {
1818 info->num_shared = iprv.v0;
1819 info->ppli1.ppli1_data = iprv.v1;
1820 info->ppli2.ppli2_data = iprv.v2;
1821 }
1822
1823 return iprv.status;
1824}
1825#endif /* __ASSEMBLY__ */
1826
1827#endif /* _ASM_IA64_PAL_H */
diff --git a/include/asm-ia64/param.h b/include/asm-ia64/param.h
deleted file mode 100644
index 0964c32c135..00000000000
--- a/include/asm-ia64/param.h
+++ /dev/null
@@ -1,33 +0,0 @@
1#ifndef _ASM_IA64_PARAM_H
2#define _ASM_IA64_PARAM_H
3
4/*
5 * Fundamental kernel parameters.
6 *
7 * Based on <asm-i386/param.h>.
8 *
9 * Modified 1998, 1999, 2002-2003
10 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
11 */
12
13#define EXEC_PAGESIZE 65536
14
15#ifndef NOGROUP
16# define NOGROUP (-1)
17#endif
18
19#define MAXHOSTNAMELEN 64 /* max length of hostname */
20
21#ifdef __KERNEL__
22# define HZ CONFIG_HZ
23# define USER_HZ HZ
24# define CLOCKS_PER_SEC HZ /* frequency at which times() counts */
25#else
26 /*
27 * Technically, this is wrong, but some old apps still refer to it. The proper way to
28 * get the HZ value is via sysconf(_SC_CLK_TCK).
29 */
30# define HZ 1024
31#endif
32
33#endif /* _ASM_IA64_PARAM_H */
diff --git a/include/asm-ia64/paravirt.h b/include/asm-ia64/paravirt.h
deleted file mode 100644
index 1b4df129f57..00000000000
--- a/include/asm-ia64/paravirt.h
+++ /dev/null
@@ -1,255 +0,0 @@
1/******************************************************************************
2 * include/asm-ia64/paravirt.h
3 *
4 * Copyright (c) 2008 Isaku Yamahata <yamahata at valinux co jp>
5 * VA Linux Systems Japan K.K.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22
23
24#ifndef __ASM_PARAVIRT_H
25#define __ASM_PARAVIRT_H
26
27#ifdef CONFIG_PARAVIRT_GUEST
28
29#define PARAVIRT_HYPERVISOR_TYPE_DEFAULT 0
30#define PARAVIRT_HYPERVISOR_TYPE_XEN 1
31
32#ifndef __ASSEMBLY__
33
34#include <asm/hw_irq.h>
35#include <asm/meminit.h>
36
37/******************************************************************************
38 * general info
39 */
40struct pv_info {
41 unsigned int kernel_rpl;
42 int paravirt_enabled;
43 const char *name;
44};
45
46extern struct pv_info pv_info;
47
48static inline int paravirt_enabled(void)
49{
50 return pv_info.paravirt_enabled;
51}
52
53static inline unsigned int get_kernel_rpl(void)
54{
55 return pv_info.kernel_rpl;
56}
57
58/******************************************************************************
59 * initialization hooks.
60 */
61struct rsvd_region;
62
63struct pv_init_ops {
64 void (*banner)(void);
65
66 int (*reserve_memory)(struct rsvd_region *region);
67
68 void (*arch_setup_early)(void);
69 void (*arch_setup_console)(char **cmdline_p);
70 int (*arch_setup_nomca)(void);
71
72 void (*post_smp_prepare_boot_cpu)(void);
73};
74
75extern struct pv_init_ops pv_init_ops;
76
77static inline void paravirt_banner(void)
78{
79 if (pv_init_ops.banner)
80 pv_init_ops.banner();
81}
82
83static inline int paravirt_reserve_memory(struct rsvd_region *region)
84{
85 if (pv_init_ops.reserve_memory)
86 return pv_init_ops.reserve_memory(region);
87 return 0;
88}
89
90static inline void paravirt_arch_setup_early(void)
91{
92 if (pv_init_ops.arch_setup_early)
93 pv_init_ops.arch_setup_early();
94}
95
96static inline void paravirt_arch_setup_console(char **cmdline_p)
97{
98 if (pv_init_ops.arch_setup_console)
99 pv_init_ops.arch_setup_console(cmdline_p);
100}
101
102static inline int paravirt_arch_setup_nomca(void)
103{
104 if (pv_init_ops.arch_setup_nomca)
105 return pv_init_ops.arch_setup_nomca();
106 return 0;
107}
108
109static inline void paravirt_post_smp_prepare_boot_cpu(void)
110{
111 if (pv_init_ops.post_smp_prepare_boot_cpu)
112 pv_init_ops.post_smp_prepare_boot_cpu();
113}
114
115/******************************************************************************
116 * replacement of iosapic operations.
117 */
118
119struct pv_iosapic_ops {
120 void (*pcat_compat_init)(void);
121
122 struct irq_chip *(*get_irq_chip)(unsigned long trigger);
123
124 unsigned int (*__read)(char __iomem *iosapic, unsigned int reg);
125 void (*__write)(char __iomem *iosapic, unsigned int reg, u32 val);
126};
127
128extern struct pv_iosapic_ops pv_iosapic_ops;
129
130static inline void
131iosapic_pcat_compat_init(void)
132{
133 if (pv_iosapic_ops.pcat_compat_init)
134 pv_iosapic_ops.pcat_compat_init();
135}
136
137static inline struct irq_chip*
138iosapic_get_irq_chip(unsigned long trigger)
139{
140 return pv_iosapic_ops.get_irq_chip(trigger);
141}
142
143static inline unsigned int
144__iosapic_read(char __iomem *iosapic, unsigned int reg)
145{
146 return pv_iosapic_ops.__read(iosapic, reg);
147}
148
149static inline void
150__iosapic_write(char __iomem *iosapic, unsigned int reg, u32 val)
151{
152 return pv_iosapic_ops.__write(iosapic, reg, val);
153}
154
155/******************************************************************************
156 * replacement of irq operations.
157 */
158
159struct pv_irq_ops {
160 void (*register_ipi)(void);
161
162 int (*assign_irq_vector)(int irq);
163 void (*free_irq_vector)(int vector);
164
165 void (*register_percpu_irq)(ia64_vector vec,
166 struct irqaction *action);
167
168 void (*resend_irq)(unsigned int vector);
169};
170
171extern struct pv_irq_ops pv_irq_ops;
172
173static inline void
174ia64_register_ipi(void)
175{
176 pv_irq_ops.register_ipi();
177}
178
179static inline int
180assign_irq_vector(int irq)
181{
182 return pv_irq_ops.assign_irq_vector(irq);
183}
184
185static inline void
186free_irq_vector(int vector)
187{
188 return pv_irq_ops.free_irq_vector(vector);
189}
190
191static inline void
192register_percpu_irq(ia64_vector vec, struct irqaction *action)
193{
194 pv_irq_ops.register_percpu_irq(vec, action);
195}
196
197static inline void
198ia64_resend_irq(unsigned int vector)
199{
200 pv_irq_ops.resend_irq(vector);
201}
202
203/******************************************************************************
204 * replacement of time operations.
205 */
206
207extern struct itc_jitter_data_t itc_jitter_data;
208extern volatile int time_keeper_id;
209
210struct pv_time_ops {
211 void (*init_missing_ticks_accounting)(int cpu);
212 int (*do_steal_accounting)(unsigned long *new_itm);
213
214 void (*clocksource_resume)(void);
215};
216
217extern struct pv_time_ops pv_time_ops;
218
219static inline void
220paravirt_init_missing_ticks_accounting(int cpu)
221{
222 if (pv_time_ops.init_missing_ticks_accounting)
223 pv_time_ops.init_missing_ticks_accounting(cpu);
224}
225
226static inline int
227paravirt_do_steal_accounting(unsigned long *new_itm)
228{
229 return pv_time_ops.do_steal_accounting(new_itm);
230}
231
232#endif /* !__ASSEMBLY__ */
233
234#else
235/* fallback for native case */
236
237#ifndef __ASSEMBLY__
238
239#define paravirt_banner() do { } while (0)
240#define paravirt_reserve_memory(region) 0
241
242#define paravirt_arch_setup_early() do { } while (0)
243#define paravirt_arch_setup_console(cmdline_p) do { } while (0)
244#define paravirt_arch_setup_nomca() 0
245#define paravirt_post_smp_prepare_boot_cpu() do { } while (0)
246
247#define paravirt_init_missing_ticks_accounting(cpu) do { } while (0)
248#define paravirt_do_steal_accounting(new_itm) 0
249
250#endif /* __ASSEMBLY__ */
251
252
253#endif /* CONFIG_PARAVIRT_GUEST */
254
255#endif /* __ASM_PARAVIRT_H */
diff --git a/include/asm-ia64/paravirt_privop.h b/include/asm-ia64/paravirt_privop.h
deleted file mode 100644
index 52482e6940a..00000000000
--- a/include/asm-ia64/paravirt_privop.h
+++ /dev/null
@@ -1,114 +0,0 @@
1/******************************************************************************
2 * include/asm-ia64/paravirt_privops.h
3 *
4 * Copyright (c) 2008 Isaku Yamahata <yamahata at valinux co jp>
5 * VA Linux Systems Japan K.K.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22
23#ifndef _ASM_IA64_PARAVIRT_PRIVOP_H
24#define _ASM_IA64_PARAVIRT_PRIVOP_H
25
26#ifdef CONFIG_PARAVIRT
27
28#ifndef __ASSEMBLY__
29
30#include <linux/types.h>
31#include <asm/kregs.h> /* for IA64_PSR_I */
32
33/******************************************************************************
34 * replacement of intrinsics operations.
35 */
36
37struct pv_cpu_ops {
38 void (*fc)(unsigned long addr);
39 unsigned long (*thash)(unsigned long addr);
40 unsigned long (*get_cpuid)(int index);
41 unsigned long (*get_pmd)(int index);
42 unsigned long (*getreg)(int reg);
43 void (*setreg)(int reg, unsigned long val);
44 void (*ptcga)(unsigned long addr, unsigned long size);
45 unsigned long (*get_rr)(unsigned long index);
46 void (*set_rr)(unsigned long index, unsigned long val);
47 void (*set_rr0_to_rr4)(unsigned long val0, unsigned long val1,
48 unsigned long val2, unsigned long val3,
49 unsigned long val4);
50 void (*ssm_i)(void);
51 void (*rsm_i)(void);
52 unsigned long (*get_psr_i)(void);
53 void (*intrin_local_irq_restore)(unsigned long flags);
54};
55
56extern struct pv_cpu_ops pv_cpu_ops;
57
58extern void ia64_native_setreg_func(int regnum, unsigned long val);
59extern unsigned long ia64_native_getreg_func(int regnum);
60
61/************************************************/
62/* Instructions paravirtualized for performance */
63/************************************************/
64
65/* mask for ia64_native_ssm/rsm() must be constant.("i" constraing).
66 * static inline function doesn't satisfy it. */
67#define paravirt_ssm(mask) \
68 do { \
69 if ((mask) == IA64_PSR_I) \
70 pv_cpu_ops.ssm_i(); \
71 else \
72 ia64_native_ssm(mask); \
73 } while (0)
74
75#define paravirt_rsm(mask) \
76 do { \
77 if ((mask) == IA64_PSR_I) \
78 pv_cpu_ops.rsm_i(); \
79 else \
80 ia64_native_rsm(mask); \
81 } while (0)
82
83/******************************************************************************
84 * replacement of hand written assembly codes.
85 */
86struct pv_cpu_asm_switch {
87 unsigned long switch_to;
88 unsigned long leave_syscall;
89 unsigned long work_processed_syscall;
90 unsigned long leave_kernel;
91};
92void paravirt_cpu_asm_init(const struct pv_cpu_asm_switch *cpu_asm_switch);
93
94#endif /* __ASSEMBLY__ */
95
96#define IA64_PARAVIRT_ASM_FUNC(name) paravirt_ ## name
97
98#else
99
100/* fallback for native case */
101#define IA64_PARAVIRT_ASM_FUNC(name) ia64_native_ ## name
102
103#endif /* CONFIG_PARAVIRT */
104
105/* these routines utilize privilege-sensitive or performance-sensitive
106 * privileged instructions so the code must be replaced with
107 * paravirtualized versions */
108#define ia64_switch_to IA64_PARAVIRT_ASM_FUNC(switch_to)
109#define ia64_leave_syscall IA64_PARAVIRT_ASM_FUNC(leave_syscall)
110#define ia64_work_processed_syscall \
111 IA64_PARAVIRT_ASM_FUNC(work_processed_syscall)
112#define ia64_leave_kernel IA64_PARAVIRT_ASM_FUNC(leave_kernel)
113
114#endif /* _ASM_IA64_PARAVIRT_PRIVOP_H */
diff --git a/include/asm-ia64/parport.h b/include/asm-ia64/parport.h
deleted file mode 100644
index 67e16adfcd2..00000000000
--- a/include/asm-ia64/parport.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * parport.h: platform-specific PC-style parport initialisation
3 *
4 * Copyright (C) 1999, 2000 Tim Waugh <tim@cyberelk.demon.co.uk>
5 *
6 * This file should only be included by drivers/parport/parport_pc.c.
7 */
8
9#ifndef _ASM_IA64_PARPORT_H
10#define _ASM_IA64_PARPORT_H 1
11
12static int __devinit parport_pc_find_isa_ports (int autoirq, int autodma);
13
14static int __devinit
15parport_pc_find_nonpci_ports (int autoirq, int autodma)
16{
17 return parport_pc_find_isa_ports(autoirq, autodma);
18}
19
20#endif /* _ASM_IA64_PARPORT_H */
diff --git a/include/asm-ia64/patch.h b/include/asm-ia64/patch.h
deleted file mode 100644
index 295fe6ab458..00000000000
--- a/include/asm-ia64/patch.h
+++ /dev/null
@@ -1,27 +0,0 @@
1#ifndef _ASM_IA64_PATCH_H
2#define _ASM_IA64_PATCH_H
3
4/*
5 * Copyright (C) 2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 *
8 * There are a number of reasons for patching instructions. Rather than duplicating code
9 * all over the place, we put the common stuff here. Reasons for patching: in-kernel
10 * module-loader, virtual-to-physical patch-list, McKinley Errata 9 workaround, and gate
11 * shared library. Undoubtedly, some of these reasons will disappear and others will
12 * be added over time.
13 */
14#include <linux/elf.h>
15#include <linux/types.h>
16
17extern void ia64_patch (u64 insn_addr, u64 mask, u64 val); /* patch any insn slot */
18extern void ia64_patch_imm64 (u64 insn_addr, u64 val); /* patch "movl" w/abs. value*/
19extern void ia64_patch_imm60 (u64 insn_addr, u64 val); /* patch "brl" w/ip-rel value */
20
21extern void ia64_patch_mckinley_e9 (unsigned long start, unsigned long end);
22extern void ia64_patch_vtop (unsigned long start, unsigned long end);
23extern void ia64_patch_phys_stack_reg(unsigned long val);
24extern void ia64_patch_rse (unsigned long start, unsigned long end);
25extern void ia64_patch_gate (void);
26
27#endif /* _ASM_IA64_PATCH_H */
diff --git a/include/asm-ia64/pci.h b/include/asm-ia64/pci.h
deleted file mode 100644
index 0149097b736..00000000000
--- a/include/asm-ia64/pci.h
+++ /dev/null
@@ -1,167 +0,0 @@
1#ifndef _ASM_IA64_PCI_H
2#define _ASM_IA64_PCI_H
3
4#include <linux/mm.h>
5#include <linux/slab.h>
6#include <linux/spinlock.h>
7#include <linux/string.h>
8#include <linux/types.h>
9
10#include <asm/io.h>
11#include <asm/scatterlist.h>
12#include <asm/hw_irq.h>
13
14/*
15 * Can be used to override the logic in pci_scan_bus for skipping already-configured bus
16 * numbers - to be used for buggy BIOSes or architectures with incomplete PCI setup by the
17 * loader.
18 */
19#define pcibios_assign_all_busses() 0
20#define pcibios_scan_all_fns(a, b) 0
21
22#define PCIBIOS_MIN_IO 0x1000
23#define PCIBIOS_MIN_MEM 0x10000000
24
25void pcibios_config_init(void);
26
27struct pci_dev;
28
29/*
30 * PCI_DMA_BUS_IS_PHYS should be set to 1 if there is _necessarily_ a direct
31 * correspondence between device bus addresses and CPU physical addresses.
32 * Platforms with a hardware I/O MMU _must_ turn this off to suppress the
33 * bounce buffer handling code in the block and network device layers.
34 * Platforms with separate bus address spaces _must_ turn this off and provide
35 * a device DMA mapping implementation that takes care of the necessary
36 * address translation.
37 *
38 * For now, the ia64 platforms which may have separate/multiple bus address
39 * spaces all have I/O MMUs which support the merging of physically
40 * discontiguous buffers, so we can use that as the sole factor to determine
41 * the setting of PCI_DMA_BUS_IS_PHYS.
42 */
43extern unsigned long ia64_max_iommu_merge_mask;
44#define PCI_DMA_BUS_IS_PHYS (ia64_max_iommu_merge_mask == ~0UL)
45
46static inline void
47pcibios_set_master (struct pci_dev *dev)
48{
49 /* No special bus mastering setup handling */
50}
51
52static inline void
53pcibios_penalize_isa_irq (int irq, int active)
54{
55 /* We don't do dynamic PCI IRQ allocation */
56}
57
58#include <asm-generic/pci-dma-compat.h>
59
60/* pci_unmap_{single,page} is not a nop, thus... */
61#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
62 dma_addr_t ADDR_NAME;
63#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
64 __u32 LEN_NAME;
65#define pci_unmap_addr(PTR, ADDR_NAME) \
66 ((PTR)->ADDR_NAME)
67#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
68 (((PTR)->ADDR_NAME) = (VAL))
69#define pci_unmap_len(PTR, LEN_NAME) \
70 ((PTR)->LEN_NAME)
71#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
72 (((PTR)->LEN_NAME) = (VAL))
73
74#ifdef CONFIG_PCI
75static inline void pci_dma_burst_advice(struct pci_dev *pdev,
76 enum pci_dma_burst_strategy *strat,
77 unsigned long *strategy_parameter)
78{
79 unsigned long cacheline_size;
80 u8 byte;
81
82 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
83 if (byte == 0)
84 cacheline_size = 1024;
85 else
86 cacheline_size = (int) byte * 4;
87
88 *strat = PCI_DMA_BURST_MULTIPLE;
89 *strategy_parameter = cacheline_size;
90}
91#endif
92
93#define HAVE_PCI_MMAP
94extern int pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
95 enum pci_mmap_state mmap_state, int write_combine);
96#define HAVE_PCI_LEGACY
97extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
98 struct vm_area_struct *vma);
99extern ssize_t pci_read_legacy_io(struct kobject *kobj,
100 struct bin_attribute *bin_attr,
101 char *buf, loff_t off, size_t count);
102extern ssize_t pci_write_legacy_io(struct kobject *kobj,
103 struct bin_attribute *bin_attr,
104 char *buf, loff_t off, size_t count);
105extern int pci_mmap_legacy_mem(struct kobject *kobj,
106 struct bin_attribute *attr,
107 struct vm_area_struct *vma);
108
109#define pci_get_legacy_mem platform_pci_get_legacy_mem
110#define pci_legacy_read platform_pci_legacy_read
111#define pci_legacy_write platform_pci_legacy_write
112
113struct pci_window {
114 struct resource resource;
115 u64 offset;
116};
117
118struct pci_controller {
119 void *acpi_handle;
120 void *iommu;
121 int segment;
122 int node; /* nearest node with memory or -1 for global allocation */
123
124 unsigned int windows;
125 struct pci_window *window;
126
127 void *platform_data;
128};
129
130#define PCI_CONTROLLER(busdev) ((struct pci_controller *) busdev->sysdata)
131#define pci_domain_nr(busdev) (PCI_CONTROLLER(busdev)->segment)
132
133extern struct pci_ops pci_root_ops;
134
135static inline int pci_proc_domain(struct pci_bus *bus)
136{
137 return (pci_domain_nr(bus) != 0);
138}
139
140extern void pcibios_resource_to_bus(struct pci_dev *dev,
141 struct pci_bus_region *region, struct resource *res);
142
143extern void pcibios_bus_to_resource(struct pci_dev *dev,
144 struct resource *res, struct pci_bus_region *region);
145
146static inline struct resource *
147pcibios_select_root(struct pci_dev *pdev, struct resource *res)
148{
149 struct resource *root = NULL;
150
151 if (res->flags & IORESOURCE_IO)
152 root = &ioport_resource;
153 if (res->flags & IORESOURCE_MEM)
154 root = &iomem_resource;
155
156 return root;
157}
158
159#define pcibios_scan_all_fns(a, b) 0
160
161#define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
162static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
163{
164 return channel ? isa_irq_to_vector(15) : isa_irq_to_vector(14);
165}
166
167#endif /* _ASM_IA64_PCI_H */
diff --git a/include/asm-ia64/percpu.h b/include/asm-ia64/percpu.h
deleted file mode 100644
index 77f30b664b4..00000000000
--- a/include/asm-ia64/percpu.h
+++ /dev/null
@@ -1,51 +0,0 @@
1#ifndef _ASM_IA64_PERCPU_H
2#define _ASM_IA64_PERCPU_H
3
4/*
5 * Copyright (C) 2002-2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 */
8
9#define PERCPU_ENOUGH_ROOM PERCPU_PAGE_SIZE
10
11#ifdef __ASSEMBLY__
12# define THIS_CPU(var) (per_cpu__##var) /* use this to mark accesses to per-CPU variables... */
13#else /* !__ASSEMBLY__ */
14
15
16#include <linux/threads.h>
17
18#ifdef CONFIG_SMP
19
20#ifdef HAVE_MODEL_SMALL_ATTRIBUTE
21# define PER_CPU_ATTRIBUTES __attribute__((__model__ (__small__)))
22#endif
23
24#define __my_cpu_offset __ia64_per_cpu_var(local_per_cpu_offset)
25
26extern void *per_cpu_init(void);
27
28#else /* ! SMP */
29
30#define PER_CPU_ATTRIBUTES __attribute__((__section__(".data.percpu")))
31
32#define per_cpu_init() (__phys_per_cpu_start)
33
34#endif /* SMP */
35
36/*
37 * Be extremely careful when taking the address of this variable! Due to virtual
38 * remapping, it is different from the canonical address returned by __get_cpu_var(var)!
39 * On the positive side, using __ia64_per_cpu_var() instead of __get_cpu_var() is slightly
40 * more efficient.
41 */
42#define __ia64_per_cpu_var(var) per_cpu__##var
43
44#include <asm-generic/percpu.h>
45
46/* Equal to __per_cpu_offset[smp_processor_id()], but faster to access: */
47DECLARE_PER_CPU(unsigned long, local_per_cpu_offset);
48
49#endif /* !__ASSEMBLY__ */
50
51#endif /* _ASM_IA64_PERCPU_H */
diff --git a/include/asm-ia64/perfmon.h b/include/asm-ia64/perfmon.h
deleted file mode 100644
index 7f3333dd00e..00000000000
--- a/include/asm-ia64/perfmon.h
+++ /dev/null
@@ -1,279 +0,0 @@
1/*
2 * Copyright (C) 2001-2003 Hewlett-Packard Co
3 * Stephane Eranian <eranian@hpl.hp.com>
4 */
5
6#ifndef _ASM_IA64_PERFMON_H
7#define _ASM_IA64_PERFMON_H
8
9/*
10 * perfmon comamnds supported on all CPU models
11 */
12#define PFM_WRITE_PMCS 0x01
13#define PFM_WRITE_PMDS 0x02
14#define PFM_READ_PMDS 0x03
15#define PFM_STOP 0x04
16#define PFM_START 0x05
17#define PFM_ENABLE 0x06 /* obsolete */
18#define PFM_DISABLE 0x07 /* obsolete */
19#define PFM_CREATE_CONTEXT 0x08
20#define PFM_DESTROY_CONTEXT 0x09 /* obsolete use close() */
21#define PFM_RESTART 0x0a
22#define PFM_PROTECT_CONTEXT 0x0b /* obsolete */
23#define PFM_GET_FEATURES 0x0c
24#define PFM_DEBUG 0x0d
25#define PFM_UNPROTECT_CONTEXT 0x0e /* obsolete */
26#define PFM_GET_PMC_RESET_VAL 0x0f
27#define PFM_LOAD_CONTEXT 0x10
28#define PFM_UNLOAD_CONTEXT 0x11
29
30/*
31 * PMU model specific commands (may not be supported on all PMU models)
32 */
33#define PFM_WRITE_IBRS 0x20
34#define PFM_WRITE_DBRS 0x21
35
36/*
37 * context flags
38 */
39#define PFM_FL_NOTIFY_BLOCK 0x01 /* block task on user level notifications */
40#define PFM_FL_SYSTEM_WIDE 0x02 /* create a system wide context */
41#define PFM_FL_OVFL_NO_MSG 0x80 /* do not post overflow/end messages for notification */
42
43/*
44 * event set flags
45 */
46#define PFM_SETFL_EXCL_IDLE 0x01 /* exclude idle task (syswide only) XXX: DO NOT USE YET */
47
48/*
49 * PMC flags
50 */
51#define PFM_REGFL_OVFL_NOTIFY 0x1 /* send notification on overflow */
52#define PFM_REGFL_RANDOM 0x2 /* randomize sampling interval */
53
54/*
55 * PMD/PMC/IBR/DBR return flags (ignored on input)
56 *
57 * Those flags are used on output and must be checked in case EAGAIN is returned
58 * by any of the calls using a pfarg_reg_t or pfarg_dbreg_t structure.
59 */
60#define PFM_REG_RETFL_NOTAVAIL (1UL<<31) /* set if register is implemented but not available */
61#define PFM_REG_RETFL_EINVAL (1UL<<30) /* set if register entry is invalid */
62#define PFM_REG_RETFL_MASK (PFM_REG_RETFL_NOTAVAIL|PFM_REG_RETFL_EINVAL)
63
64#define PFM_REG_HAS_ERROR(flag) (((flag) & PFM_REG_RETFL_MASK) != 0)
65
66typedef unsigned char pfm_uuid_t[16]; /* custom sampling buffer identifier type */
67
68/*
69 * Request structure used to define a context
70 */
71typedef struct {
72 pfm_uuid_t ctx_smpl_buf_id; /* which buffer format to use (if needed) */
73 unsigned long ctx_flags; /* noblock/block */
74 unsigned short ctx_nextra_sets; /* number of extra event sets (you always get 1) */
75 unsigned short ctx_reserved1; /* for future use */
76 int ctx_fd; /* return arg: unique identification for context */
77 void *ctx_smpl_vaddr; /* return arg: virtual address of sampling buffer, is used */
78 unsigned long ctx_reserved2[11];/* for future use */
79} pfarg_context_t;
80
81/*
82 * Request structure used to write/read a PMC or PMD
83 */
84typedef struct {
85 unsigned int reg_num; /* which register */
86 unsigned short reg_set; /* event set for this register */
87 unsigned short reg_reserved1; /* for future use */
88
89 unsigned long reg_value; /* initial pmc/pmd value */
90 unsigned long reg_flags; /* input: pmc/pmd flags, return: reg error */
91
92 unsigned long reg_long_reset; /* reset after buffer overflow notification */
93 unsigned long reg_short_reset; /* reset after counter overflow */
94
95 unsigned long reg_reset_pmds[4]; /* which other counters to reset on overflow */
96 unsigned long reg_random_seed; /* seed value when randomization is used */
97 unsigned long reg_random_mask; /* bitmask used to limit random value */
98 unsigned long reg_last_reset_val;/* return: PMD last reset value */
99
100 unsigned long reg_smpl_pmds[4]; /* which pmds are accessed when PMC overflows */
101 unsigned long reg_smpl_eventid; /* opaque sampling event identifier */
102
103 unsigned long reg_reserved2[3]; /* for future use */
104} pfarg_reg_t;
105
106typedef struct {
107 unsigned int dbreg_num; /* which debug register */
108 unsigned short dbreg_set; /* event set for this register */
109 unsigned short dbreg_reserved1; /* for future use */
110 unsigned long dbreg_value; /* value for debug register */
111 unsigned long dbreg_flags; /* return: dbreg error */
112 unsigned long dbreg_reserved2[1]; /* for future use */
113} pfarg_dbreg_t;
114
115typedef struct {
116 unsigned int ft_version; /* perfmon: major [16-31], minor [0-15] */
117 unsigned int ft_reserved; /* reserved for future use */
118 unsigned long reserved[4]; /* for future use */
119} pfarg_features_t;
120
121typedef struct {
122 pid_t load_pid; /* process to load the context into */
123 unsigned short load_set; /* first event set to load */
124 unsigned short load_reserved1; /* for future use */
125 unsigned long load_reserved2[3]; /* for future use */
126} pfarg_load_t;
127
128typedef struct {
129 int msg_type; /* generic message header */
130 int msg_ctx_fd; /* generic message header */
131 unsigned long msg_ovfl_pmds[4]; /* which PMDs overflowed */
132 unsigned short msg_active_set; /* active set at the time of overflow */
133 unsigned short msg_reserved1; /* for future use */
134 unsigned int msg_reserved2; /* for future use */
135 unsigned long msg_tstamp; /* for perf tuning/debug */
136} pfm_ovfl_msg_t;
137
138typedef struct {
139 int msg_type; /* generic message header */
140 int msg_ctx_fd; /* generic message header */
141 unsigned long msg_tstamp; /* for perf tuning */
142} pfm_end_msg_t;
143
144typedef struct {
145 int msg_type; /* type of the message */
146 int msg_ctx_fd; /* unique identifier for the context */
147 unsigned long msg_tstamp; /* for perf tuning */
148} pfm_gen_msg_t;
149
150#define PFM_MSG_OVFL 1 /* an overflow happened */
151#define PFM_MSG_END 2 /* task to which context was attached ended */
152
153typedef union {
154 pfm_ovfl_msg_t pfm_ovfl_msg;
155 pfm_end_msg_t pfm_end_msg;
156 pfm_gen_msg_t pfm_gen_msg;
157} pfm_msg_t;
158
159/*
160 * Define the version numbers for both perfmon as a whole and the sampling buffer format.
161 */
162#define PFM_VERSION_MAJ 2U
163#define PFM_VERSION_MIN 0U
164#define PFM_VERSION (((PFM_VERSION_MAJ&0xffff)<<16)|(PFM_VERSION_MIN & 0xffff))
165#define PFM_VERSION_MAJOR(x) (((x)>>16) & 0xffff)
166#define PFM_VERSION_MINOR(x) ((x) & 0xffff)
167
168
169/*
170 * miscellaneous architected definitions
171 */
172#define PMU_FIRST_COUNTER 4 /* first counting monitor (PMC/PMD) */
173#define PMU_MAX_PMCS 256 /* maximum architected number of PMC registers */
174#define PMU_MAX_PMDS 256 /* maximum architected number of PMD registers */
175
176#ifdef __KERNEL__
177
178extern long perfmonctl(int fd, int cmd, void *arg, int narg);
179
180typedef struct {
181 void (*handler)(int irq, void *arg, struct pt_regs *regs);
182} pfm_intr_handler_desc_t;
183
184extern void pfm_save_regs (struct task_struct *);
185extern void pfm_load_regs (struct task_struct *);
186
187extern void pfm_exit_thread(struct task_struct *);
188extern int pfm_use_debug_registers(struct task_struct *);
189extern int pfm_release_debug_registers(struct task_struct *);
190extern void pfm_syst_wide_update_task(struct task_struct *, unsigned long info, int is_ctxswin);
191extern void pfm_inherit(struct task_struct *task, struct pt_regs *regs);
192extern void pfm_init_percpu(void);
193extern void pfm_handle_work(void);
194extern int pfm_install_alt_pmu_interrupt(pfm_intr_handler_desc_t *h);
195extern int pfm_remove_alt_pmu_interrupt(pfm_intr_handler_desc_t *h);
196
197
198
199/*
200 * Reset PMD register flags
201 */
202#define PFM_PMD_SHORT_RESET 0
203#define PFM_PMD_LONG_RESET 1
204
205typedef union {
206 unsigned int val;
207 struct {
208 unsigned int notify_user:1; /* notify user program of overflow */
209 unsigned int reset_ovfl_pmds:1; /* reset overflowed PMDs */
210 unsigned int block_task:1; /* block monitored task on kernel exit */
211 unsigned int mask_monitoring:1; /* mask monitors via PMCx.plm */
212 unsigned int reserved:28; /* for future use */
213 } bits;
214} pfm_ovfl_ctrl_t;
215
216typedef struct {
217 unsigned char ovfl_pmd; /* index of overflowed PMD */
218 unsigned char ovfl_notify; /* =1 if monitor requested overflow notification */
219 unsigned short active_set; /* event set active at the time of the overflow */
220 pfm_ovfl_ctrl_t ovfl_ctrl; /* return: perfmon controls to set by handler */
221
222 unsigned long pmd_last_reset; /* last reset value of of the PMD */
223 unsigned long smpl_pmds[4]; /* bitmask of other PMD of interest on overflow */
224 unsigned long smpl_pmds_values[PMU_MAX_PMDS]; /* values for the other PMDs of interest */
225 unsigned long pmd_value; /* current 64-bit value of the PMD */
226 unsigned long pmd_eventid; /* eventid associated with PMD */
227} pfm_ovfl_arg_t;
228
229
230typedef struct {
231 char *fmt_name;
232 pfm_uuid_t fmt_uuid;
233 size_t fmt_arg_size;
234 unsigned long fmt_flags;
235
236 int (*fmt_validate)(struct task_struct *task, unsigned int flags, int cpu, void *arg);
237 int (*fmt_getsize)(struct task_struct *task, unsigned int flags, int cpu, void *arg, unsigned long *size);
238 int (*fmt_init)(struct task_struct *task, void *buf, unsigned int flags, int cpu, void *arg);
239 int (*fmt_handler)(struct task_struct *task, void *buf, pfm_ovfl_arg_t *arg, struct pt_regs *regs, unsigned long stamp);
240 int (*fmt_restart)(struct task_struct *task, pfm_ovfl_ctrl_t *ctrl, void *buf, struct pt_regs *regs);
241 int (*fmt_restart_active)(struct task_struct *task, pfm_ovfl_ctrl_t *ctrl, void *buf, struct pt_regs *regs);
242 int (*fmt_exit)(struct task_struct *task, void *buf, struct pt_regs *regs);
243
244 struct list_head fmt_list;
245} pfm_buffer_fmt_t;
246
247extern int pfm_register_buffer_fmt(pfm_buffer_fmt_t *fmt);
248extern int pfm_unregister_buffer_fmt(pfm_uuid_t uuid);
249
250/*
251 * perfmon interface exported to modules
252 */
253extern int pfm_mod_read_pmds(struct task_struct *, void *req, unsigned int nreq, struct pt_regs *regs);
254extern int pfm_mod_write_pmcs(struct task_struct *, void *req, unsigned int nreq, struct pt_regs *regs);
255extern int pfm_mod_write_ibrs(struct task_struct *task, void *req, unsigned int nreq, struct pt_regs *regs);
256extern int pfm_mod_write_dbrs(struct task_struct *task, void *req, unsigned int nreq, struct pt_regs *regs);
257
258/*
259 * describe the content of the local_cpu_date->pfm_syst_info field
260 */
261#define PFM_CPUINFO_SYST_WIDE 0x1 /* if set a system wide session exists */
262#define PFM_CPUINFO_DCR_PP 0x2 /* if set the system wide session has started */
263#define PFM_CPUINFO_EXCL_IDLE 0x4 /* the system wide session excludes the idle task */
264
265/*
266 * sysctl control structure. visible to sampling formats
267 */
268typedef struct {
269 int debug; /* turn on/off debugging via syslog */
270 int debug_ovfl; /* turn on/off debug printk in overflow handler */
271 int fastctxsw; /* turn on/off fast (unsecure) ctxsw */
272 int expert_mode; /* turn on/off value checking */
273} pfm_sysctl_t;
274extern pfm_sysctl_t pfm_sysctl;
275
276
277#endif /* __KERNEL__ */
278
279#endif /* _ASM_IA64_PERFMON_H */
diff --git a/include/asm-ia64/perfmon_default_smpl.h b/include/asm-ia64/perfmon_default_smpl.h
deleted file mode 100644
index 48822c0811d..00000000000
--- a/include/asm-ia64/perfmon_default_smpl.h
+++ /dev/null
@@ -1,83 +0,0 @@
1/*
2 * Copyright (C) 2002-2003 Hewlett-Packard Co
3 * Stephane Eranian <eranian@hpl.hp.com>
4 *
5 * This file implements the default sampling buffer format
6 * for Linux/ia64 perfmon subsystem.
7 */
8#ifndef __PERFMON_DEFAULT_SMPL_H__
9#define __PERFMON_DEFAULT_SMPL_H__ 1
10
11#define PFM_DEFAULT_SMPL_UUID { \
12 0x4d, 0x72, 0xbe, 0xc0, 0x06, 0x64, 0x41, 0x43, 0x82, 0xb4, 0xd3, 0xfd, 0x27, 0x24, 0x3c, 0x97}
13
14/*
15 * format specific parameters (passed at context creation)
16 */
17typedef struct {
18 unsigned long buf_size; /* size of the buffer in bytes */
19 unsigned int flags; /* buffer specific flags */
20 unsigned int res1; /* for future use */
21 unsigned long reserved[2]; /* for future use */
22} pfm_default_smpl_arg_t;
23
24/*
25 * combined context+format specific structure. Can be passed
26 * to PFM_CONTEXT_CREATE
27 */
28typedef struct {
29 pfarg_context_t ctx_arg;
30 pfm_default_smpl_arg_t buf_arg;
31} pfm_default_smpl_ctx_arg_t;
32
33/*
34 * This header is at the beginning of the sampling buffer returned to the user.
35 * It is directly followed by the first record.
36 */
37typedef struct {
38 unsigned long hdr_count; /* how many valid entries */
39 unsigned long hdr_cur_offs; /* current offset from top of buffer */
40 unsigned long hdr_reserved2; /* reserved for future use */
41
42 unsigned long hdr_overflows; /* how many times the buffer overflowed */
43 unsigned long hdr_buf_size; /* how many bytes in the buffer */
44
45 unsigned int hdr_version; /* contains perfmon version (smpl format diffs) */
46 unsigned int hdr_reserved1; /* for future use */
47 unsigned long hdr_reserved[10]; /* for future use */
48} pfm_default_smpl_hdr_t;
49
50/*
51 * Entry header in the sampling buffer. The header is directly followed
52 * with the values of the PMD registers of interest saved in increasing
53 * index order: PMD4, PMD5, and so on. How many PMDs are present depends
54 * on how the session was programmed.
55 *
56 * In the case where multiple counters overflow at the same time, multiple
57 * entries are written consecutively.
58 *
59 * last_reset_value member indicates the initial value of the overflowed PMD.
60 */
61typedef struct {
62 int pid; /* thread id (for NPTL, this is gettid()) */
63 unsigned char reserved1[3]; /* reserved for future use */
64 unsigned char ovfl_pmd; /* index of overflowed PMD */
65
66 unsigned long last_reset_val; /* initial value of overflowed PMD */
67 unsigned long ip; /* where did the overflow interrupt happened */
68 unsigned long tstamp; /* ar.itc when entering perfmon intr. handler */
69
70 unsigned short cpu; /* cpu on which the overfow occured */
71 unsigned short set; /* event set active when overflow ocurred */
72 int tgid; /* thread group id (for NPTL, this is getpid()) */
73} pfm_default_smpl_entry_t;
74
75#define PFM_DEFAULT_MAX_PMDS 64 /* how many pmds supported by data structures (sizeof(unsigned long) */
76#define PFM_DEFAULT_MAX_ENTRY_SIZE (sizeof(pfm_default_smpl_entry_t)+(sizeof(unsigned long)*PFM_DEFAULT_MAX_PMDS))
77#define PFM_DEFAULT_SMPL_MIN_BUF_SIZE (sizeof(pfm_default_smpl_hdr_t)+PFM_DEFAULT_MAX_ENTRY_SIZE)
78
79#define PFM_DEFAULT_SMPL_VERSION_MAJ 2U
80#define PFM_DEFAULT_SMPL_VERSION_MIN 0U
81#define PFM_DEFAULT_SMPL_VERSION (((PFM_DEFAULT_SMPL_VERSION_MAJ&0xffff)<<16)|(PFM_DEFAULT_SMPL_VERSION_MIN & 0xffff))
82
83#endif /* __PERFMON_DEFAULT_SMPL_H__ */
diff --git a/include/asm-ia64/pgalloc.h b/include/asm-ia64/pgalloc.h
deleted file mode 100644
index b9ac1a6fc21..00000000000
--- a/include/asm-ia64/pgalloc.h
+++ /dev/null
@@ -1,122 +0,0 @@
1#ifndef _ASM_IA64_PGALLOC_H
2#define _ASM_IA64_PGALLOC_H
3
4/*
5 * This file contains the functions and defines necessary to allocate
6 * page tables.
7 *
8 * This hopefully works with any (fixed) ia-64 page-size, as defined
9 * in <asm/page.h> (currently 8192).
10 *
11 * Copyright (C) 1998-2001 Hewlett-Packard Co
12 * David Mosberger-Tang <davidm@hpl.hp.com>
13 * Copyright (C) 2000, Goutham Rao <goutham.rao@intel.com>
14 */
15
16
17#include <linux/compiler.h>
18#include <linux/mm.h>
19#include <linux/page-flags.h>
20#include <linux/threads.h>
21#include <linux/quicklist.h>
22
23#include <asm/mmu_context.h>
24
25static inline pgd_t *pgd_alloc(struct mm_struct *mm)
26{
27 return quicklist_alloc(0, GFP_KERNEL, NULL);
28}
29
30static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
31{
32 quicklist_free(0, NULL, pgd);
33}
34
35#ifdef CONFIG_PGTABLE_4
36static inline void
37pgd_populate(struct mm_struct *mm, pgd_t * pgd_entry, pud_t * pud)
38{
39 pgd_val(*pgd_entry) = __pa(pud);
40}
41
42static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
43{
44 return quicklist_alloc(0, GFP_KERNEL, NULL);
45}
46
47static inline void pud_free(struct mm_struct *mm, pud_t *pud)
48{
49 quicklist_free(0, NULL, pud);
50}
51#define __pud_free_tlb(tlb, pud) pud_free((tlb)->mm, pud)
52#endif /* CONFIG_PGTABLE_4 */
53
54static inline void
55pud_populate(struct mm_struct *mm, pud_t * pud_entry, pmd_t * pmd)
56{
57 pud_val(*pud_entry) = __pa(pmd);
58}
59
60static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
61{
62 return quicklist_alloc(0, GFP_KERNEL, NULL);
63}
64
65static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
66{
67 quicklist_free(0, NULL, pmd);
68}
69
70#define __pmd_free_tlb(tlb, pmd) pmd_free((tlb)->mm, pmd)
71
72static inline void
73pmd_populate(struct mm_struct *mm, pmd_t * pmd_entry, pgtable_t pte)
74{
75 pmd_val(*pmd_entry) = page_to_phys(pte);
76}
77#define pmd_pgtable(pmd) pmd_page(pmd)
78
79static inline void
80pmd_populate_kernel(struct mm_struct *mm, pmd_t * pmd_entry, pte_t * pte)
81{
82 pmd_val(*pmd_entry) = __pa(pte);
83}
84
85static inline pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long addr)
86{
87 struct page *page;
88 void *pg;
89
90 pg = quicklist_alloc(0, GFP_KERNEL, NULL);
91 if (!pg)
92 return NULL;
93 page = virt_to_page(pg);
94 pgtable_page_ctor(page);
95 return page;
96}
97
98static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
99 unsigned long addr)
100{
101 return quicklist_alloc(0, GFP_KERNEL, NULL);
102}
103
104static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
105{
106 pgtable_page_dtor(pte);
107 quicklist_free_page(0, NULL, pte);
108}
109
110static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
111{
112 quicklist_free(0, NULL, pte);
113}
114
115static inline void check_pgt_cache(void)
116{
117 quicklist_trim(0, NULL, 25, 16);
118}
119
120#define __pte_free_tlb(tlb, pte) pte_free((tlb)->mm, pte)
121
122#endif /* _ASM_IA64_PGALLOC_H */
diff --git a/include/asm-ia64/pgtable.h b/include/asm-ia64/pgtable.h
deleted file mode 100644
index 7a9bff47564..00000000000
--- a/include/asm-ia64/pgtable.h
+++ /dev/null
@@ -1,615 +0,0 @@
1#ifndef _ASM_IA64_PGTABLE_H
2#define _ASM_IA64_PGTABLE_H
3
4/*
5 * This file contains the functions and defines necessary to modify and use
6 * the IA-64 page table tree.
7 *
8 * This hopefully works with any (fixed) IA-64 page-size, as defined
9 * in <asm/page.h>.
10 *
11 * Copyright (C) 1998-2005 Hewlett-Packard Co
12 * David Mosberger-Tang <davidm@hpl.hp.com>
13 */
14
15
16#include <asm/mman.h>
17#include <asm/page.h>
18#include <asm/processor.h>
19#include <asm/system.h>
20#include <asm/types.h>
21
22#define IA64_MAX_PHYS_BITS 50 /* max. number of physical address bits (architected) */
23
24/*
25 * First, define the various bits in a PTE. Note that the PTE format
26 * matches the VHPT short format, the firt doubleword of the VHPD long
27 * format, and the first doubleword of the TLB insertion format.
28 */
29#define _PAGE_P_BIT 0
30#define _PAGE_A_BIT 5
31#define _PAGE_D_BIT 6
32
33#define _PAGE_P (1 << _PAGE_P_BIT) /* page present bit */
34#define _PAGE_MA_WB (0x0 << 2) /* write back memory attribute */
35#define _PAGE_MA_UC (0x4 << 2) /* uncacheable memory attribute */
36#define _PAGE_MA_UCE (0x5 << 2) /* UC exported attribute */
37#define _PAGE_MA_WC (0x6 << 2) /* write coalescing memory attribute */
38#define _PAGE_MA_NAT (0x7 << 2) /* not-a-thing attribute */
39#define _PAGE_MA_MASK (0x7 << 2)
40#define _PAGE_PL_0 (0 << 7) /* privilege level 0 (kernel) */
41#define _PAGE_PL_1 (1 << 7) /* privilege level 1 (unused) */
42#define _PAGE_PL_2 (2 << 7) /* privilege level 2 (unused) */
43#define _PAGE_PL_3 (3 << 7) /* privilege level 3 (user) */
44#define _PAGE_PL_MASK (3 << 7)
45#define _PAGE_AR_R (0 << 9) /* read only */
46#define _PAGE_AR_RX (1 << 9) /* read & execute */
47#define _PAGE_AR_RW (2 << 9) /* read & write */
48#define _PAGE_AR_RWX (3 << 9) /* read, write & execute */
49#define _PAGE_AR_R_RW (4 << 9) /* read / read & write */
50#define _PAGE_AR_RX_RWX (5 << 9) /* read & exec / read, write & exec */
51#define _PAGE_AR_RWX_RW (6 << 9) /* read, write & exec / read & write */
52#define _PAGE_AR_X_RX (7 << 9) /* exec & promote / read & exec */
53#define _PAGE_AR_MASK (7 << 9)
54#define _PAGE_AR_SHIFT 9
55#define _PAGE_A (1 << _PAGE_A_BIT) /* page accessed bit */
56#define _PAGE_D (1 << _PAGE_D_BIT) /* page dirty bit */
57#define _PAGE_PPN_MASK (((__IA64_UL(1) << IA64_MAX_PHYS_BITS) - 1) & ~0xfffUL)
58#define _PAGE_ED (__IA64_UL(1) << 52) /* exception deferral */
59#define _PAGE_PROTNONE (__IA64_UL(1) << 63)
60
61/* Valid only for a PTE with the present bit cleared: */
62#define _PAGE_FILE (1 << 1) /* see swap & file pte remarks below */
63
64#define _PFN_MASK _PAGE_PPN_MASK
65/* Mask of bits which may be changed by pte_modify(); the odd bits are there for _PAGE_PROTNONE */
66#define _PAGE_CHG_MASK (_PAGE_P | _PAGE_PROTNONE | _PAGE_PL_MASK | _PAGE_AR_MASK | _PAGE_ED)
67
68#define _PAGE_SIZE_4K 12
69#define _PAGE_SIZE_8K 13
70#define _PAGE_SIZE_16K 14
71#define _PAGE_SIZE_64K 16
72#define _PAGE_SIZE_256K 18
73#define _PAGE_SIZE_1M 20
74#define _PAGE_SIZE_4M 22
75#define _PAGE_SIZE_16M 24
76#define _PAGE_SIZE_64M 26
77#define _PAGE_SIZE_256M 28
78#define _PAGE_SIZE_1G 30
79#define _PAGE_SIZE_4G 32
80
81#define __ACCESS_BITS _PAGE_ED | _PAGE_A | _PAGE_P | _PAGE_MA_WB
82#define __DIRTY_BITS_NO_ED _PAGE_A | _PAGE_P | _PAGE_D | _PAGE_MA_WB
83#define __DIRTY_BITS _PAGE_ED | __DIRTY_BITS_NO_ED
84
85/*
86 * How many pointers will a page table level hold expressed in shift
87 */
88#define PTRS_PER_PTD_SHIFT (PAGE_SHIFT-3)
89
90/*
91 * Definitions for fourth level:
92 */
93#define PTRS_PER_PTE (__IA64_UL(1) << (PTRS_PER_PTD_SHIFT))
94
95/*
96 * Definitions for third level:
97 *
98 * PMD_SHIFT determines the size of the area a third-level page table
99 * can map.
100 */
101#define PMD_SHIFT (PAGE_SHIFT + (PTRS_PER_PTD_SHIFT))
102#define PMD_SIZE (1UL << PMD_SHIFT)
103#define PMD_MASK (~(PMD_SIZE-1))
104#define PTRS_PER_PMD (1UL << (PTRS_PER_PTD_SHIFT))
105
106#ifdef CONFIG_PGTABLE_4
107/*
108 * Definitions for second level:
109 *
110 * PUD_SHIFT determines the size of the area a second-level page table
111 * can map.
112 */
113#define PUD_SHIFT (PMD_SHIFT + (PTRS_PER_PTD_SHIFT))
114#define PUD_SIZE (1UL << PUD_SHIFT)
115#define PUD_MASK (~(PUD_SIZE-1))
116#define PTRS_PER_PUD (1UL << (PTRS_PER_PTD_SHIFT))
117#endif
118
119/*
120 * Definitions for first level:
121 *
122 * PGDIR_SHIFT determines what a first-level page table entry can map.
123 */
124#ifdef CONFIG_PGTABLE_4
125#define PGDIR_SHIFT (PUD_SHIFT + (PTRS_PER_PTD_SHIFT))
126#else
127#define PGDIR_SHIFT (PMD_SHIFT + (PTRS_PER_PTD_SHIFT))
128#endif
129#define PGDIR_SIZE (__IA64_UL(1) << PGDIR_SHIFT)
130#define PGDIR_MASK (~(PGDIR_SIZE-1))
131#define PTRS_PER_PGD_SHIFT PTRS_PER_PTD_SHIFT
132#define PTRS_PER_PGD (1UL << PTRS_PER_PGD_SHIFT)
133#define USER_PTRS_PER_PGD (5*PTRS_PER_PGD/8) /* regions 0-4 are user regions */
134#define FIRST_USER_ADDRESS 0
135
136/*
137 * All the normal masks have the "page accessed" bits on, as any time
138 * they are used, the page is accessed. They are cleared only by the
139 * page-out routines.
140 */
141#define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_A)
142#define PAGE_SHARED __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RW)
143#define PAGE_READONLY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R)
144#define PAGE_COPY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R)
145#define PAGE_COPY_EXEC __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
146#define PAGE_GATE __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_X_RX)
147#define PAGE_KERNEL __pgprot(__DIRTY_BITS | _PAGE_PL_0 | _PAGE_AR_RWX)
148#define PAGE_KERNELRX __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_RX)
149
150# ifndef __ASSEMBLY__
151
152#include <linux/sched.h> /* for mm_struct */
153#include <linux/bitops.h>
154#include <asm/cacheflush.h>
155#include <asm/mmu_context.h>
156#include <asm/processor.h>
157
158/*
159 * Next come the mappings that determine how mmap() protection bits
160 * (PROT_EXEC, PROT_READ, PROT_WRITE, PROT_NONE) get implemented. The
161 * _P version gets used for a private shared memory segment, the _S
162 * version gets used for a shared memory segment with MAP_SHARED on.
163 * In a private shared memory segment, we do a copy-on-write if a task
164 * attempts to write to the page.
165 */
166 /* xwr */
167#define __P000 PAGE_NONE
168#define __P001 PAGE_READONLY
169#define __P010 PAGE_READONLY /* write to priv pg -> copy & make writable */
170#define __P011 PAGE_READONLY /* ditto */
171#define __P100 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX)
172#define __P101 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
173#define __P110 PAGE_COPY_EXEC
174#define __P111 PAGE_COPY_EXEC
175
176#define __S000 PAGE_NONE
177#define __S001 PAGE_READONLY
178#define __S010 PAGE_SHARED /* we don't have (and don't need) write-only */
179#define __S011 PAGE_SHARED
180#define __S100 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX)
181#define __S101 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
182#define __S110 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX)
183#define __S111 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX)
184
185#define pgd_ERROR(e) printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
186#ifdef CONFIG_PGTABLE_4
187#define pud_ERROR(e) printk("%s:%d: bad pud %016lx.\n", __FILE__, __LINE__, pud_val(e))
188#endif
189#define pmd_ERROR(e) printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
190#define pte_ERROR(e) printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
191
192
193/*
194 * Some definitions to translate between mem_map, PTEs, and page addresses:
195 */
196
197
198/* Quick test to see if ADDR is a (potentially) valid physical address. */
199static inline long
200ia64_phys_addr_valid (unsigned long addr)
201{
202 return (addr & (local_cpu_data->unimpl_pa_mask)) == 0;
203}
204
205/*
206 * kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel
207 * memory. For the return value to be meaningful, ADDR must be >=
208 * PAGE_OFFSET. This operation can be relatively expensive (e.g.,
209 * require a hash-, or multi-level tree-lookup or something of that
210 * sort) but it guarantees to return TRUE only if accessing the page
211 * at that address does not cause an error. Note that there may be
212 * addresses for which kern_addr_valid() returns FALSE even though an
213 * access would not cause an error (e.g., this is typically true for
214 * memory mapped I/O regions.
215 *
216 * XXX Need to implement this for IA-64.
217 */
218#define kern_addr_valid(addr) (1)
219
220
221/*
222 * Now come the defines and routines to manage and access the three-level
223 * page table.
224 */
225
226
227#define VMALLOC_START (RGN_BASE(RGN_GATE) + 0x200000000UL)
228#ifdef CONFIG_VIRTUAL_MEM_MAP
229# define VMALLOC_END_INIT (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 9)))
230# define VMALLOC_END vmalloc_end
231 extern unsigned long vmalloc_end;
232#else
233#if defined(CONFIG_SPARSEMEM) && defined(CONFIG_SPARSEMEM_VMEMMAP)
234/* SPARSEMEM_VMEMMAP uses half of vmalloc... */
235# define VMALLOC_END (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 10)))
236# define vmemmap ((struct page *)VMALLOC_END)
237#else
238# define VMALLOC_END (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 9)))
239#endif
240#endif
241
242/* fs/proc/kcore.c */
243#define kc_vaddr_to_offset(v) ((v) - RGN_BASE(RGN_GATE))
244#define kc_offset_to_vaddr(o) ((o) + RGN_BASE(RGN_GATE))
245
246#define RGN_MAP_SHIFT (PGDIR_SHIFT + PTRS_PER_PGD_SHIFT - 3)
247#define RGN_MAP_LIMIT ((1UL << RGN_MAP_SHIFT) - PAGE_SIZE) /* per region addr limit */
248
249/*
250 * Conversion functions: convert page frame number (pfn) and a protection value to a page
251 * table entry (pte).
252 */
253#define pfn_pte(pfn, pgprot) \
254({ pte_t __pte; pte_val(__pte) = ((pfn) << PAGE_SHIFT) | pgprot_val(pgprot); __pte; })
255
256/* Extract pfn from pte. */
257#define pte_pfn(_pte) ((pte_val(_pte) & _PFN_MASK) >> PAGE_SHIFT)
258
259#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
260
261/* This takes a physical page address that is used by the remapping functions */
262#define mk_pte_phys(physpage, pgprot) \
263({ pte_t __pte; pte_val(__pte) = physpage + pgprot_val(pgprot); __pte; })
264
265#define pte_modify(_pte, newprot) \
266 (__pte((pte_val(_pte) & ~_PAGE_CHG_MASK) | (pgprot_val(newprot) & _PAGE_CHG_MASK)))
267
268#define pte_none(pte) (!pte_val(pte))
269#define pte_present(pte) (pte_val(pte) & (_PAGE_P | _PAGE_PROTNONE))
270#define pte_clear(mm,addr,pte) (pte_val(*(pte)) = 0UL)
271/* pte_page() returns the "struct page *" corresponding to the PTE: */
272#define pte_page(pte) virt_to_page(((pte_val(pte) & _PFN_MASK) + PAGE_OFFSET))
273
274#define pmd_none(pmd) (!pmd_val(pmd))
275#define pmd_bad(pmd) (!ia64_phys_addr_valid(pmd_val(pmd)))
276#define pmd_present(pmd) (pmd_val(pmd) != 0UL)
277#define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL)
278#define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_val(pmd) & _PFN_MASK))
279#define pmd_page(pmd) virt_to_page((pmd_val(pmd) + PAGE_OFFSET))
280
281#define pud_none(pud) (!pud_val(pud))
282#define pud_bad(pud) (!ia64_phys_addr_valid(pud_val(pud)))
283#define pud_present(pud) (pud_val(pud) != 0UL)
284#define pud_clear(pudp) (pud_val(*(pudp)) = 0UL)
285#define pud_page_vaddr(pud) ((unsigned long) __va(pud_val(pud) & _PFN_MASK))
286#define pud_page(pud) virt_to_page((pud_val(pud) + PAGE_OFFSET))
287
288#ifdef CONFIG_PGTABLE_4
289#define pgd_none(pgd) (!pgd_val(pgd))
290#define pgd_bad(pgd) (!ia64_phys_addr_valid(pgd_val(pgd)))
291#define pgd_present(pgd) (pgd_val(pgd) != 0UL)
292#define pgd_clear(pgdp) (pgd_val(*(pgdp)) = 0UL)
293#define pgd_page_vaddr(pgd) ((unsigned long) __va(pgd_val(pgd) & _PFN_MASK))
294#define pgd_page(pgd) virt_to_page((pgd_val(pgd) + PAGE_OFFSET))
295#endif
296
297/*
298 * The following have defined behavior only work if pte_present() is true.
299 */
300#define pte_write(pte) ((unsigned) (((pte_val(pte) & _PAGE_AR_MASK) >> _PAGE_AR_SHIFT) - 2) <= 4)
301#define pte_exec(pte) ((pte_val(pte) & _PAGE_AR_RX) != 0)
302#define pte_dirty(pte) ((pte_val(pte) & _PAGE_D) != 0)
303#define pte_young(pte) ((pte_val(pte) & _PAGE_A) != 0)
304#define pte_file(pte) ((pte_val(pte) & _PAGE_FILE) != 0)
305#define pte_special(pte) 0
306
307/*
308 * Note: we convert AR_RWX to AR_RX and AR_RW to AR_R by clearing the 2nd bit in the
309 * access rights:
310 */
311#define pte_wrprotect(pte) (__pte(pte_val(pte) & ~_PAGE_AR_RW))
312#define pte_mkwrite(pte) (__pte(pte_val(pte) | _PAGE_AR_RW))
313#define pte_mkold(pte) (__pte(pte_val(pte) & ~_PAGE_A))
314#define pte_mkyoung(pte) (__pte(pte_val(pte) | _PAGE_A))
315#define pte_mkclean(pte) (__pte(pte_val(pte) & ~_PAGE_D))
316#define pte_mkdirty(pte) (__pte(pte_val(pte) | _PAGE_D))
317#define pte_mkhuge(pte) (__pte(pte_val(pte)))
318#define pte_mkspecial(pte) (pte)
319
320/*
321 * Because ia64's Icache and Dcache is not coherent (on a cpu), we need to
322 * sync icache and dcache when we insert *new* executable page.
323 * __ia64_sync_icache_dcache() check Pg_arch_1 bit and flush icache
324 * if necessary.
325 *
326 * set_pte() is also called by the kernel, but we can expect that the kernel
327 * flushes icache explicitly if necessary.
328 */
329#define pte_present_exec_user(pte)\
330 ((pte_val(pte) & (_PAGE_P | _PAGE_PL_MASK | _PAGE_AR_RX)) == \
331 (_PAGE_P | _PAGE_PL_3 | _PAGE_AR_RX))
332
333extern void __ia64_sync_icache_dcache(pte_t pteval);
334static inline void set_pte(pte_t *ptep, pte_t pteval)
335{
336 /* page is present && page is user && page is executable
337 * && (page swapin or new page or page migraton
338 * || copy_on_write with page copying.)
339 */
340 if (pte_present_exec_user(pteval) &&
341 (!pte_present(*ptep) ||
342 pte_pfn(*ptep) != pte_pfn(pteval)))
343 /* load_module() calles flush_icache_range() explicitly*/
344 __ia64_sync_icache_dcache(pteval);
345 *ptep = pteval;
346}
347
348#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
349
350/*
351 * Make page protection values cacheable, uncacheable, or write-
352 * combining. Note that "protection" is really a misnomer here as the
353 * protection value contains the memory attribute bits, dirty bits, and
354 * various other bits as well.
355 */
356#define pgprot_cacheable(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WB)
357#define pgprot_noncached(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_UC)
358#define pgprot_writecombine(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WC)
359
360struct file;
361extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
362 unsigned long size, pgprot_t vma_prot);
363#define __HAVE_PHYS_MEM_ACCESS_PROT
364
365static inline unsigned long
366pgd_index (unsigned long address)
367{
368 unsigned long region = address >> 61;
369 unsigned long l1index = (address >> PGDIR_SHIFT) & ((PTRS_PER_PGD >> 3) - 1);
370
371 return (region << (PAGE_SHIFT - 6)) | l1index;
372}
373
374/* The offset in the 1-level directory is given by the 3 region bits
375 (61..63) and the level-1 bits. */
376static inline pgd_t*
377pgd_offset (const struct mm_struct *mm, unsigned long address)
378{
379 return mm->pgd + pgd_index(address);
380}
381
382/* In the kernel's mapped region we completely ignore the region number
383 (since we know it's in region number 5). */
384#define pgd_offset_k(addr) \
385 (init_mm.pgd + (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)))
386
387/* Look up a pgd entry in the gate area. On IA-64, the gate-area
388 resides in the kernel-mapped segment, hence we use pgd_offset_k()
389 here. */
390#define pgd_offset_gate(mm, addr) pgd_offset_k(addr)
391
392#ifdef CONFIG_PGTABLE_4
393/* Find an entry in the second-level page table.. */
394#define pud_offset(dir,addr) \
395 ((pud_t *) pgd_page_vaddr(*(dir)) + (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)))
396#endif
397
398/* Find an entry in the third-level page table.. */
399#define pmd_offset(dir,addr) \
400 ((pmd_t *) pud_page_vaddr(*(dir)) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
401
402/*
403 * Find an entry in the third-level page table. This looks more complicated than it
404 * should be because some platforms place page tables in high memory.
405 */
406#define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
407#define pte_offset_kernel(dir,addr) ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr))
408#define pte_offset_map(dir,addr) pte_offset_kernel(dir, addr)
409#define pte_offset_map_nested(dir,addr) pte_offset_map(dir, addr)
410#define pte_unmap(pte) do { } while (0)
411#define pte_unmap_nested(pte) do { } while (0)
412
413/* atomic versions of the some PTE manipulations: */
414
415static inline int
416ptep_test_and_clear_young (struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
417{
418#ifdef CONFIG_SMP
419 if (!pte_young(*ptep))
420 return 0;
421 return test_and_clear_bit(_PAGE_A_BIT, ptep);
422#else
423 pte_t pte = *ptep;
424 if (!pte_young(pte))
425 return 0;
426 set_pte_at(vma->vm_mm, addr, ptep, pte_mkold(pte));
427 return 1;
428#endif
429}
430
431static inline pte_t
432ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
433{
434#ifdef CONFIG_SMP
435 return __pte(xchg((long *) ptep, 0));
436#else
437 pte_t pte = *ptep;
438 pte_clear(mm, addr, ptep);
439 return pte;
440#endif
441}
442
443static inline void
444ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
445{
446#ifdef CONFIG_SMP
447 unsigned long new, old;
448
449 do {
450 old = pte_val(*ptep);
451 new = pte_val(pte_wrprotect(__pte (old)));
452 } while (cmpxchg((unsigned long *) ptep, old, new) != old);
453#else
454 pte_t old_pte = *ptep;
455 set_pte_at(mm, addr, ptep, pte_wrprotect(old_pte));
456#endif
457}
458
459static inline int
460pte_same (pte_t a, pte_t b)
461{
462 return pte_val(a) == pte_val(b);
463}
464
465#define update_mmu_cache(vma, address, pte) do { } while (0)
466
467extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
468extern void paging_init (void);
469
470/*
471 * Note: The macros below rely on the fact that MAX_SWAPFILES_SHIFT <= number of
472 * bits in the swap-type field of the swap pte. It would be nice to
473 * enforce that, but we can't easily include <linux/swap.h> here.
474 * (Of course, better still would be to define MAX_SWAPFILES_SHIFT here...).
475 *
476 * Format of swap pte:
477 * bit 0 : present bit (must be zero)
478 * bit 1 : _PAGE_FILE (must be zero)
479 * bits 2- 8: swap-type
480 * bits 9-62: swap offset
481 * bit 63 : _PAGE_PROTNONE bit
482 *
483 * Format of file pte:
484 * bit 0 : present bit (must be zero)
485 * bit 1 : _PAGE_FILE (must be one)
486 * bits 2-62: file_offset/PAGE_SIZE
487 * bit 63 : _PAGE_PROTNONE bit
488 */
489#define __swp_type(entry) (((entry).val >> 2) & 0x7f)
490#define __swp_offset(entry) (((entry).val << 1) >> 10)
491#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 2) | ((long) (offset) << 9) })
492#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
493#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
494
495#define PTE_FILE_MAX_BITS 61
496#define pte_to_pgoff(pte) ((pte_val(pte) << 1) >> 3)
497#define pgoff_to_pte(off) ((pte_t) { ((off) << 2) | _PAGE_FILE })
498
499#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
500 remap_pfn_range(vma, vaddr, pfn, size, prot)
501
502/*
503 * ZERO_PAGE is a global shared page that is always zero: used
504 * for zero-mapped memory areas etc..
505 */
506extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)];
507extern struct page *zero_page_memmap_ptr;
508#define ZERO_PAGE(vaddr) (zero_page_memmap_ptr)
509
510/* We provide our own get_unmapped_area to cope with VA holes for userland */
511#define HAVE_ARCH_UNMAPPED_AREA
512
513#ifdef CONFIG_HUGETLB_PAGE
514#define HUGETLB_PGDIR_SHIFT (HPAGE_SHIFT + 2*(PAGE_SHIFT-3))
515#define HUGETLB_PGDIR_SIZE (__IA64_UL(1) << HUGETLB_PGDIR_SHIFT)
516#define HUGETLB_PGDIR_MASK (~(HUGETLB_PGDIR_SIZE-1))
517#endif
518
519
520#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
521/*
522 * Update PTEP with ENTRY, which is guaranteed to be a less
523 * restrictive PTE. That is, ENTRY may have the ACCESSED, DIRTY, and
524 * WRITABLE bits turned on, when the value at PTEP did not. The
525 * WRITABLE bit may only be turned if SAFELY_WRITABLE is TRUE.
526 *
527 * SAFELY_WRITABLE is TRUE if we can update the value at PTEP without
528 * having to worry about races. On SMP machines, there are only two
529 * cases where this is true:
530 *
531 * (1) *PTEP has the PRESENT bit turned OFF
532 * (2) ENTRY has the DIRTY bit turned ON
533 *
534 * On ia64, we could implement this routine with a cmpxchg()-loop
535 * which ORs in the _PAGE_A/_PAGE_D bit if they're set in ENTRY.
536 * However, like on x86, we can get a more streamlined version by
537 * observing that it is OK to drop ACCESSED bit updates when
538 * SAFELY_WRITABLE is FALSE. Besides being rare, all that would do is
539 * result in an extra Access-bit fault, which would then turn on the
540 * ACCESSED bit in the low-level fault handler (iaccess_bit or
541 * daccess_bit in ivt.S).
542 */
543#ifdef CONFIG_SMP
544# define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \
545({ \
546 int __changed = !pte_same(*(__ptep), __entry); \
547 if (__changed && __safely_writable) { \
548 set_pte(__ptep, __entry); \
549 flush_tlb_page(__vma, __addr); \
550 } \
551 __changed; \
552})
553#else
554# define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \
555({ \
556 int __changed = !pte_same(*(__ptep), __entry); \
557 if (__changed) { \
558 set_pte_at((__vma)->vm_mm, (__addr), __ptep, __entry); \
559 flush_tlb_page(__vma, __addr); \
560 } \
561 __changed; \
562})
563#endif
564
565# ifdef CONFIG_VIRTUAL_MEM_MAP
566 /* arch mem_map init routine is needed due to holes in a virtual mem_map */
567# define __HAVE_ARCH_MEMMAP_INIT
568 extern void memmap_init (unsigned long size, int nid, unsigned long zone,
569 unsigned long start_pfn);
570# endif /* CONFIG_VIRTUAL_MEM_MAP */
571# endif /* !__ASSEMBLY__ */
572
573/*
574 * Identity-mapped regions use a large page size. We'll call such large pages
575 * "granules". If you can think of a better name that's unambiguous, let me
576 * know...
577 */
578#if defined(CONFIG_IA64_GRANULE_64MB)
579# define IA64_GRANULE_SHIFT _PAGE_SIZE_64M
580#elif defined(CONFIG_IA64_GRANULE_16MB)
581# define IA64_GRANULE_SHIFT _PAGE_SIZE_16M
582#endif
583#define IA64_GRANULE_SIZE (1 << IA64_GRANULE_SHIFT)
584/*
585 * log2() of the page size we use to map the kernel image (IA64_TR_KERNEL):
586 */
587#define KERNEL_TR_PAGE_SHIFT _PAGE_SIZE_64M
588#define KERNEL_TR_PAGE_SIZE (1 << KERNEL_TR_PAGE_SHIFT)
589
590/*
591 * No page table caches to initialise
592 */
593#define pgtable_cache_init() do { } while (0)
594
595/* These tell get_user_pages() that the first gate page is accessible from user-level. */
596#define FIXADDR_USER_START GATE_ADDR
597#ifdef HAVE_BUGGY_SEGREL
598# define FIXADDR_USER_END (GATE_ADDR + 2*PAGE_SIZE)
599#else
600# define FIXADDR_USER_END (GATE_ADDR + 2*PERCPU_PAGE_SIZE)
601#endif
602
603#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
604#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
605#define __HAVE_ARCH_PTEP_SET_WRPROTECT
606#define __HAVE_ARCH_PTE_SAME
607#define __HAVE_ARCH_PGD_OFFSET_GATE
608
609
610#ifndef CONFIG_PGTABLE_4
611#include <asm-generic/pgtable-nopud.h>
612#endif
613#include <asm-generic/pgtable.h>
614
615#endif /* _ASM_IA64_PGTABLE_H */
diff --git a/include/asm-ia64/poll.h b/include/asm-ia64/poll.h
deleted file mode 100644
index c98509d3149..00000000000
--- a/include/asm-ia64/poll.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/poll.h>
diff --git a/include/asm-ia64/posix_types.h b/include/asm-ia64/posix_types.h
deleted file mode 100644
index 17885567b73..00000000000
--- a/include/asm-ia64/posix_types.h
+++ /dev/null
@@ -1,126 +0,0 @@
1#ifndef _ASM_IA64_POSIX_TYPES_H
2#define _ASM_IA64_POSIX_TYPES_H
3
4/*
5 * This file is generally used by user-level software, so you need to
6 * be a little careful about namespace pollution etc. Also, we cannot
7 * assume GCC is being used.
8 *
9 * Based on <asm-alpha/posix_types.h>.
10 *
11 * Modified 1998-2000, 2003
12 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
13 */
14
15typedef unsigned long __kernel_ino_t;
16typedef unsigned int __kernel_mode_t;
17typedef unsigned int __kernel_nlink_t;
18typedef long __kernel_off_t;
19typedef long long __kernel_loff_t;
20typedef int __kernel_pid_t;
21typedef int __kernel_ipc_pid_t;
22typedef unsigned int __kernel_uid_t;
23typedef unsigned int __kernel_gid_t;
24typedef unsigned long __kernel_size_t;
25typedef long __kernel_ssize_t;
26typedef long __kernel_ptrdiff_t;
27typedef long __kernel_time_t;
28typedef long __kernel_suseconds_t;
29typedef long __kernel_clock_t;
30typedef int __kernel_timer_t;
31typedef int __kernel_clockid_t;
32typedef int __kernel_daddr_t;
33typedef char * __kernel_caddr_t;
34typedef unsigned long __kernel_sigset_t; /* at least 32 bits */
35typedef unsigned short __kernel_uid16_t;
36typedef unsigned short __kernel_gid16_t;
37
38typedef struct {
39 int val[2];
40} __kernel_fsid_t;
41
42typedef __kernel_uid_t __kernel_old_uid_t;
43typedef __kernel_gid_t __kernel_old_gid_t;
44typedef __kernel_uid_t __kernel_uid32_t;
45typedef __kernel_gid_t __kernel_gid32_t;
46
47typedef unsigned int __kernel_old_dev_t;
48
49# ifdef __KERNEL__
50
51# ifndef __GNUC__
52
53#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
54#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
55#define __FD_ISSET(d, set) (((set)->fds_bits[__FDELT(d)] & __FDMASK(d)) != 0)
56#define __FD_ZERO(set) \
57 ((void) memset ((void *) (set), 0, sizeof (__kernel_fd_set)))
58
59# else /* !__GNUC__ */
60
61/* With GNU C, use inline functions instead so args are evaluated only once: */
62
63#undef __FD_SET
64static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
65{
66 unsigned long _tmp = fd / __NFDBITS;
67 unsigned long _rem = fd % __NFDBITS;
68 fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
69}
70
71#undef __FD_CLR
72static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
73{
74 unsigned long _tmp = fd / __NFDBITS;
75 unsigned long _rem = fd % __NFDBITS;
76 fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
77}
78
79#undef __FD_ISSET
80static __inline__ int __FD_ISSET(unsigned long fd, const __kernel_fd_set *p)
81{
82 unsigned long _tmp = fd / __NFDBITS;
83 unsigned long _rem = fd % __NFDBITS;
84 return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
85}
86
87/*
88 * This will unroll the loop for the normal constant case (8 ints,
89 * for a 256-bit fd_set)
90 */
91#undef __FD_ZERO
92static __inline__ void __FD_ZERO(__kernel_fd_set *p)
93{
94 unsigned long *tmp = p->fds_bits;
95 int i;
96
97 if (__builtin_constant_p(__FDSET_LONGS)) {
98 switch (__FDSET_LONGS) {
99 case 16:
100 tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
101 tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
102 tmp[ 8] = 0; tmp[ 9] = 0; tmp[10] = 0; tmp[11] = 0;
103 tmp[12] = 0; tmp[13] = 0; tmp[14] = 0; tmp[15] = 0;
104 return;
105
106 case 8:
107 tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
108 tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
109 return;
110
111 case 4:
112 tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
113 return;
114 }
115 }
116 i = __FDSET_LONGS;
117 while (i) {
118 i--;
119 *tmp = 0;
120 tmp++;
121 }
122}
123
124# endif /* !__GNUC__ */
125# endif /* __KERNEL__ */
126#endif /* _ASM_IA64_POSIX_TYPES_H */
diff --git a/include/asm-ia64/processor.h b/include/asm-ia64/processor.h
deleted file mode 100644
index f88fa054d01..00000000000
--- a/include/asm-ia64/processor.h
+++ /dev/null
@@ -1,771 +0,0 @@
1#ifndef _ASM_IA64_PROCESSOR_H
2#define _ASM_IA64_PROCESSOR_H
3
4/*
5 * Copyright (C) 1998-2004 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 * Stephane Eranian <eranian@hpl.hp.com>
8 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
9 * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
10 *
11 * 11/24/98 S.Eranian added ia64_set_iva()
12 * 12/03/99 D. Mosberger implement thread_saved_pc() via kernel unwind API
13 * 06/16/00 A. Mallick added csd/ssd/tssd for ia32 support
14 */
15
16
17#include <asm/intrinsics.h>
18#include <asm/kregs.h>
19#include <asm/ptrace.h>
20#include <asm/ustack.h>
21
22#define IA64_NUM_PHYS_STACK_REG 96
23#define IA64_NUM_DBG_REGS 8
24
25#define DEFAULT_MAP_BASE __IA64_UL_CONST(0x2000000000000000)
26#define DEFAULT_TASK_SIZE __IA64_UL_CONST(0xa000000000000000)
27
28/*
29 * TASK_SIZE really is a mis-named. It really is the maximum user
30 * space address (plus one). On IA-64, there are five regions of 2TB
31 * each (assuming 8KB page size), for a total of 8TB of user virtual
32 * address space.
33 */
34#define TASK_SIZE_OF(tsk) ((tsk)->thread.task_size)
35#define TASK_SIZE TASK_SIZE_OF(current)
36
37/*
38 * This decides where the kernel will search for a free chunk of vm
39 * space during mmap's.
40 */
41#define TASK_UNMAPPED_BASE (current->thread.map_base)
42
43#define IA64_THREAD_FPH_VALID (__IA64_UL(1) << 0) /* floating-point high state valid? */
44#define IA64_THREAD_DBG_VALID (__IA64_UL(1) << 1) /* debug registers valid? */
45#define IA64_THREAD_PM_VALID (__IA64_UL(1) << 2) /* performance registers valid? */
46#define IA64_THREAD_UAC_NOPRINT (__IA64_UL(1) << 3) /* don't log unaligned accesses */
47#define IA64_THREAD_UAC_SIGBUS (__IA64_UL(1) << 4) /* generate SIGBUS on unaligned acc. */
48#define IA64_THREAD_MIGRATION (__IA64_UL(1) << 5) /* require migration
49 sync at ctx sw */
50#define IA64_THREAD_FPEMU_NOPRINT (__IA64_UL(1) << 6) /* don't log any fpswa faults */
51#define IA64_THREAD_FPEMU_SIGFPE (__IA64_UL(1) << 7) /* send a SIGFPE for fpswa faults */
52
53#define IA64_THREAD_UAC_SHIFT 3
54#define IA64_THREAD_UAC_MASK (IA64_THREAD_UAC_NOPRINT | IA64_THREAD_UAC_SIGBUS)
55#define IA64_THREAD_FPEMU_SHIFT 6
56#define IA64_THREAD_FPEMU_MASK (IA64_THREAD_FPEMU_NOPRINT | IA64_THREAD_FPEMU_SIGFPE)
57
58
59/*
60 * This shift should be large enough to be able to represent 1000000000/itc_freq with good
61 * accuracy while being small enough to fit 10*1000000000<<IA64_NSEC_PER_CYC_SHIFT in 64 bits
62 * (this will give enough slack to represent 10 seconds worth of time as a scaled number).
63 */
64#define IA64_NSEC_PER_CYC_SHIFT 30
65
66#ifndef __ASSEMBLY__
67
68#include <linux/cache.h>
69#include <linux/compiler.h>
70#include <linux/threads.h>
71#include <linux/types.h>
72
73#include <asm/fpu.h>
74#include <asm/page.h>
75#include <asm/percpu.h>
76#include <asm/rse.h>
77#include <asm/unwind.h>
78#include <asm/atomic.h>
79#ifdef CONFIG_NUMA
80#include <asm/nodedata.h>
81#endif
82
83/* like above but expressed as bitfields for more efficient access: */
84struct ia64_psr {
85 __u64 reserved0 : 1;
86 __u64 be : 1;
87 __u64 up : 1;
88 __u64 ac : 1;
89 __u64 mfl : 1;
90 __u64 mfh : 1;
91 __u64 reserved1 : 7;
92 __u64 ic : 1;
93 __u64 i : 1;
94 __u64 pk : 1;
95 __u64 reserved2 : 1;
96 __u64 dt : 1;
97 __u64 dfl : 1;
98 __u64 dfh : 1;
99 __u64 sp : 1;
100 __u64 pp : 1;
101 __u64 di : 1;
102 __u64 si : 1;
103 __u64 db : 1;
104 __u64 lp : 1;
105 __u64 tb : 1;
106 __u64 rt : 1;
107 __u64 reserved3 : 4;
108 __u64 cpl : 2;
109 __u64 is : 1;
110 __u64 mc : 1;
111 __u64 it : 1;
112 __u64 id : 1;
113 __u64 da : 1;
114 __u64 dd : 1;
115 __u64 ss : 1;
116 __u64 ri : 2;
117 __u64 ed : 1;
118 __u64 bn : 1;
119 __u64 reserved4 : 19;
120};
121
122union ia64_isr {
123 __u64 val;
124 struct {
125 __u64 code : 16;
126 __u64 vector : 8;
127 __u64 reserved1 : 8;
128 __u64 x : 1;
129 __u64 w : 1;
130 __u64 r : 1;
131 __u64 na : 1;
132 __u64 sp : 1;
133 __u64 rs : 1;
134 __u64 ir : 1;
135 __u64 ni : 1;
136 __u64 so : 1;
137 __u64 ei : 2;
138 __u64 ed : 1;
139 __u64 reserved2 : 20;
140 };
141};
142
143union ia64_lid {
144 __u64 val;
145 struct {
146 __u64 rv : 16;
147 __u64 eid : 8;
148 __u64 id : 8;
149 __u64 ig : 32;
150 };
151};
152
153union ia64_tpr {
154 __u64 val;
155 struct {
156 __u64 ig0 : 4;
157 __u64 mic : 4;
158 __u64 rsv : 8;
159 __u64 mmi : 1;
160 __u64 ig1 : 47;
161 };
162};
163
164union ia64_itir {
165 __u64 val;
166 struct {
167 __u64 rv3 : 2; /* 0-1 */
168 __u64 ps : 6; /* 2-7 */
169 __u64 key : 24; /* 8-31 */
170 __u64 rv4 : 32; /* 32-63 */
171 };
172};
173
174union ia64_rr {
175 __u64 val;
176 struct {
177 __u64 ve : 1; /* enable hw walker */
178 __u64 reserved0: 1; /* reserved */
179 __u64 ps : 6; /* log page size */
180 __u64 rid : 24; /* region id */
181 __u64 reserved1: 32; /* reserved */
182 };
183};
184
185/*
186 * CPU type, hardware bug flags, and per-CPU state. Frequently used
187 * state comes earlier:
188 */
189struct cpuinfo_ia64 {
190 __u32 softirq_pending;
191 __u64 itm_delta; /* # of clock cycles between clock ticks */
192 __u64 itm_next; /* interval timer mask value to use for next clock tick */
193 __u64 nsec_per_cyc; /* (1000000000<<IA64_NSEC_PER_CYC_SHIFT)/itc_freq */
194 __u64 unimpl_va_mask; /* mask of unimplemented virtual address bits (from PAL) */
195 __u64 unimpl_pa_mask; /* mask of unimplemented physical address bits (from PAL) */
196 __u64 itc_freq; /* frequency of ITC counter */
197 __u64 proc_freq; /* frequency of processor */
198 __u64 cyc_per_usec; /* itc_freq/1000000 */
199 __u64 ptce_base;
200 __u32 ptce_count[2];
201 __u32 ptce_stride[2];
202 struct task_struct *ksoftirqd; /* kernel softirq daemon for this CPU */
203
204#ifdef CONFIG_SMP
205 __u64 loops_per_jiffy;
206 int cpu;
207 __u32 socket_id; /* physical processor socket id */
208 __u16 core_id; /* core id */
209 __u16 thread_id; /* thread id */
210 __u16 num_log; /* Total number of logical processors on
211 * this socket that were successfully booted */
212 __u8 cores_per_socket; /* Cores per processor socket */
213 __u8 threads_per_core; /* Threads per core */
214#endif
215
216 /* CPUID-derived information: */
217 __u64 ppn;
218 __u64 features;
219 __u8 number;
220 __u8 revision;
221 __u8 model;
222 __u8 family;
223 __u8 archrev;
224 char vendor[16];
225 char *model_name;
226
227#ifdef CONFIG_NUMA
228 struct ia64_node_data *node_data;
229#endif
230};
231
232DECLARE_PER_CPU(struct cpuinfo_ia64, cpu_info);
233
234/*
235 * The "local" data variable. It refers to the per-CPU data of the currently executing
236 * CPU, much like "current" points to the per-task data of the currently executing task.
237 * Do not use the address of local_cpu_data, since it will be different from
238 * cpu_data(smp_processor_id())!
239 */
240#define local_cpu_data (&__ia64_per_cpu_var(cpu_info))
241#define cpu_data(cpu) (&per_cpu(cpu_info, cpu))
242
243extern void print_cpu_info (struct cpuinfo_ia64 *);
244
245typedef struct {
246 unsigned long seg;
247} mm_segment_t;
248
249#define SET_UNALIGN_CTL(task,value) \
250({ \
251 (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_UAC_MASK) \
252 | (((value) << IA64_THREAD_UAC_SHIFT) & IA64_THREAD_UAC_MASK)); \
253 0; \
254})
255#define GET_UNALIGN_CTL(task,addr) \
256({ \
257 put_user(((task)->thread.flags & IA64_THREAD_UAC_MASK) >> IA64_THREAD_UAC_SHIFT, \
258 (int __user *) (addr)); \
259})
260
261#define SET_FPEMU_CTL(task,value) \
262({ \
263 (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_FPEMU_MASK) \
264 | (((value) << IA64_THREAD_FPEMU_SHIFT) & IA64_THREAD_FPEMU_MASK)); \
265 0; \
266})
267#define GET_FPEMU_CTL(task,addr) \
268({ \
269 put_user(((task)->thread.flags & IA64_THREAD_FPEMU_MASK) >> IA64_THREAD_FPEMU_SHIFT, \
270 (int __user *) (addr)); \
271})
272
273#ifdef CONFIG_IA32_SUPPORT
274struct desc_struct {
275 unsigned int a, b;
276};
277
278#define desc_empty(desc) (!((desc)->a | (desc)->b))
279#define desc_equal(desc1, desc2) (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
280
281#define GDT_ENTRY_TLS_ENTRIES 3
282#define GDT_ENTRY_TLS_MIN 6
283#define GDT_ENTRY_TLS_MAX (GDT_ENTRY_TLS_MIN + GDT_ENTRY_TLS_ENTRIES - 1)
284
285#define TLS_SIZE (GDT_ENTRY_TLS_ENTRIES * 8)
286
287struct ia64_partial_page_list;
288#endif
289
290struct thread_struct {
291 __u32 flags; /* various thread flags (see IA64_THREAD_*) */
292 /* writing on_ustack is performance-critical, so it's worth spending 8 bits on it... */
293 __u8 on_ustack; /* executing on user-stacks? */
294 __u8 pad[3];
295 __u64 ksp; /* kernel stack pointer */
296 __u64 map_base; /* base address for get_unmapped_area() */
297 __u64 task_size; /* limit for task size */
298 __u64 rbs_bot; /* the base address for the RBS */
299 int last_fph_cpu; /* CPU that may hold the contents of f32-f127 */
300
301#ifdef CONFIG_IA32_SUPPORT
302 __u64 eflag; /* IA32 EFLAGS reg */
303 __u64 fsr; /* IA32 floating pt status reg */
304 __u64 fcr; /* IA32 floating pt control reg */
305 __u64 fir; /* IA32 fp except. instr. reg */
306 __u64 fdr; /* IA32 fp except. data reg */
307 __u64 old_k1; /* old value of ar.k1 */
308 __u64 old_iob; /* old IOBase value */
309 struct ia64_partial_page_list *ppl; /* partial page list for 4K page size issue */
310 /* cached TLS descriptors. */
311 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
312
313# define INIT_THREAD_IA32 .eflag = 0, \
314 .fsr = 0, \
315 .fcr = 0x17800000037fULL, \
316 .fir = 0, \
317 .fdr = 0, \
318 .old_k1 = 0, \
319 .old_iob = 0, \
320 .ppl = NULL,
321#else
322# define INIT_THREAD_IA32
323#endif /* CONFIG_IA32_SUPPORT */
324#ifdef CONFIG_PERFMON
325 void *pfm_context; /* pointer to detailed PMU context */
326 unsigned long pfm_needs_checking; /* when >0, pending perfmon work on kernel exit */
327# define INIT_THREAD_PM .pfm_context = NULL, \
328 .pfm_needs_checking = 0UL,
329#else
330# define INIT_THREAD_PM
331#endif
332 __u64 dbr[IA64_NUM_DBG_REGS];
333 __u64 ibr[IA64_NUM_DBG_REGS];
334 struct ia64_fpreg fph[96]; /* saved/loaded on demand */
335};
336
337#define INIT_THREAD { \
338 .flags = 0, \
339 .on_ustack = 0, \
340 .ksp = 0, \
341 .map_base = DEFAULT_MAP_BASE, \
342 .rbs_bot = STACK_TOP - DEFAULT_USER_STACK_SIZE, \
343 .task_size = DEFAULT_TASK_SIZE, \
344 .last_fph_cpu = -1, \
345 INIT_THREAD_IA32 \
346 INIT_THREAD_PM \
347 .dbr = {0, }, \
348 .ibr = {0, }, \
349 .fph = {{{{0}}}, } \
350}
351
352#define start_thread(regs,new_ip,new_sp) do { \
353 set_fs(USER_DS); \
354 regs->cr_ipsr = ((regs->cr_ipsr | (IA64_PSR_BITS_TO_SET | IA64_PSR_CPL)) \
355 & ~(IA64_PSR_BITS_TO_CLEAR | IA64_PSR_RI | IA64_PSR_IS)); \
356 regs->cr_iip = new_ip; \
357 regs->ar_rsc = 0xf; /* eager mode, privilege level 3 */ \
358 regs->ar_rnat = 0; \
359 regs->ar_bspstore = current->thread.rbs_bot; \
360 regs->ar_fpsr = FPSR_DEFAULT; \
361 regs->loadrs = 0; \
362 regs->r8 = get_dumpable(current->mm); /* set "don't zap registers" flag */ \
363 regs->r12 = new_sp - 16; /* allocate 16 byte scratch area */ \
364 if (unlikely(!get_dumpable(current->mm))) { \
365 /* \
366 * Zap scratch regs to avoid leaking bits between processes with different \
367 * uid/privileges. \
368 */ \
369 regs->ar_pfs = 0; regs->b0 = 0; regs->pr = 0; \
370 regs->r1 = 0; regs->r9 = 0; regs->r11 = 0; regs->r13 = 0; regs->r15 = 0; \
371 } \
372} while (0)
373
374/* Forward declarations, a strange C thing... */
375struct mm_struct;
376struct task_struct;
377
378/*
379 * Free all resources held by a thread. This is called after the
380 * parent of DEAD_TASK has collected the exit status of the task via
381 * wait().
382 */
383#define release_thread(dead_task)
384
385/* Prepare to copy thread state - unlazy all lazy status */
386#define prepare_to_copy(tsk) do { } while (0)
387
388/*
389 * This is the mechanism for creating a new kernel thread.
390 *
391 * NOTE 1: Only a kernel-only process (ie the swapper or direct
392 * descendants who haven't done an "execve()") should use this: it
393 * will work within a system call from a "real" process, but the
394 * process memory space will not be free'd until both the parent and
395 * the child have exited.
396 *
397 * NOTE 2: This MUST NOT be an inlined function. Otherwise, we get
398 * into trouble in init/main.c when the child thread returns to
399 * do_basic_setup() and the timing is such that free_initmem() has
400 * been called already.
401 */
402extern pid_t kernel_thread (int (*fn)(void *), void *arg, unsigned long flags);
403
404/* Get wait channel for task P. */
405extern unsigned long get_wchan (struct task_struct *p);
406
407/* Return instruction pointer of blocked task TSK. */
408#define KSTK_EIP(tsk) \
409 ({ \
410 struct pt_regs *_regs = task_pt_regs(tsk); \
411 _regs->cr_iip + ia64_psr(_regs)->ri; \
412 })
413
414/* Return stack pointer of blocked task TSK. */
415#define KSTK_ESP(tsk) ((tsk)->thread.ksp)
416
417extern void ia64_getreg_unknown_kr (void);
418extern void ia64_setreg_unknown_kr (void);
419
420#define ia64_get_kr(regnum) \
421({ \
422 unsigned long r = 0; \
423 \
424 switch (regnum) { \
425 case 0: r = ia64_getreg(_IA64_REG_AR_KR0); break; \
426 case 1: r = ia64_getreg(_IA64_REG_AR_KR1); break; \
427 case 2: r = ia64_getreg(_IA64_REG_AR_KR2); break; \
428 case 3: r = ia64_getreg(_IA64_REG_AR_KR3); break; \
429 case 4: r = ia64_getreg(_IA64_REG_AR_KR4); break; \
430 case 5: r = ia64_getreg(_IA64_REG_AR_KR5); break; \
431 case 6: r = ia64_getreg(_IA64_REG_AR_KR6); break; \
432 case 7: r = ia64_getreg(_IA64_REG_AR_KR7); break; \
433 default: ia64_getreg_unknown_kr(); break; \
434 } \
435 r; \
436})
437
438#define ia64_set_kr(regnum, r) \
439({ \
440 switch (regnum) { \
441 case 0: ia64_setreg(_IA64_REG_AR_KR0, r); break; \
442 case 1: ia64_setreg(_IA64_REG_AR_KR1, r); break; \
443 case 2: ia64_setreg(_IA64_REG_AR_KR2, r); break; \
444 case 3: ia64_setreg(_IA64_REG_AR_KR3, r); break; \
445 case 4: ia64_setreg(_IA64_REG_AR_KR4, r); break; \
446 case 5: ia64_setreg(_IA64_REG_AR_KR5, r); break; \
447 case 6: ia64_setreg(_IA64_REG_AR_KR6, r); break; \
448 case 7: ia64_setreg(_IA64_REG_AR_KR7, r); break; \
449 default: ia64_setreg_unknown_kr(); break; \
450 } \
451})
452
453/*
454 * The following three macros can't be inline functions because we don't have struct
455 * task_struct at this point.
456 */
457
458/*
459 * Return TRUE if task T owns the fph partition of the CPU we're running on.
460 * Must be called from code that has preemption disabled.
461 */
462#define ia64_is_local_fpu_owner(t) \
463({ \
464 struct task_struct *__ia64_islfo_task = (t); \
465 (__ia64_islfo_task->thread.last_fph_cpu == smp_processor_id() \
466 && __ia64_islfo_task == (struct task_struct *) ia64_get_kr(IA64_KR_FPU_OWNER)); \
467})
468
469/*
470 * Mark task T as owning the fph partition of the CPU we're running on.
471 * Must be called from code that has preemption disabled.
472 */
473#define ia64_set_local_fpu_owner(t) do { \
474 struct task_struct *__ia64_slfo_task = (t); \
475 __ia64_slfo_task->thread.last_fph_cpu = smp_processor_id(); \
476 ia64_set_kr(IA64_KR_FPU_OWNER, (unsigned long) __ia64_slfo_task); \
477} while (0)
478
479/* Mark the fph partition of task T as being invalid on all CPUs. */
480#define ia64_drop_fpu(t) ((t)->thread.last_fph_cpu = -1)
481
482extern void __ia64_init_fpu (void);
483extern void __ia64_save_fpu (struct ia64_fpreg *fph);
484extern void __ia64_load_fpu (struct ia64_fpreg *fph);
485extern void ia64_save_debug_regs (unsigned long *save_area);
486extern void ia64_load_debug_regs (unsigned long *save_area);
487
488#ifdef CONFIG_IA32_SUPPORT
489extern void ia32_save_state (struct task_struct *task);
490extern void ia32_load_state (struct task_struct *task);
491#endif
492
493#define ia64_fph_enable() do { ia64_rsm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
494#define ia64_fph_disable() do { ia64_ssm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
495
496/* load fp 0.0 into fph */
497static inline void
498ia64_init_fpu (void) {
499 ia64_fph_enable();
500 __ia64_init_fpu();
501 ia64_fph_disable();
502}
503
504/* save f32-f127 at FPH */
505static inline void
506ia64_save_fpu (struct ia64_fpreg *fph) {
507 ia64_fph_enable();
508 __ia64_save_fpu(fph);
509 ia64_fph_disable();
510}
511
512/* load f32-f127 from FPH */
513static inline void
514ia64_load_fpu (struct ia64_fpreg *fph) {
515 ia64_fph_enable();
516 __ia64_load_fpu(fph);
517 ia64_fph_disable();
518}
519
520static inline __u64
521ia64_clear_ic (void)
522{
523 __u64 psr;
524 psr = ia64_getreg(_IA64_REG_PSR);
525 ia64_stop();
526 ia64_rsm(IA64_PSR_I | IA64_PSR_IC);
527 ia64_srlz_i();
528 return psr;
529}
530
531/*
532 * Restore the psr.
533 */
534static inline void
535ia64_set_psr (__u64 psr)
536{
537 ia64_stop();
538 ia64_setreg(_IA64_REG_PSR_L, psr);
539 ia64_srlz_i();
540}
541
542/*
543 * Insert a translation into an instruction and/or data translation
544 * register.
545 */
546static inline void
547ia64_itr (__u64 target_mask, __u64 tr_num,
548 __u64 vmaddr, __u64 pte,
549 __u64 log_page_size)
550{
551 ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
552 ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
553 ia64_stop();
554 if (target_mask & 0x1)
555 ia64_itri(tr_num, pte);
556 if (target_mask & 0x2)
557 ia64_itrd(tr_num, pte);
558}
559
560/*
561 * Insert a translation into the instruction and/or data translation
562 * cache.
563 */
564static inline void
565ia64_itc (__u64 target_mask, __u64 vmaddr, __u64 pte,
566 __u64 log_page_size)
567{
568 ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
569 ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
570 ia64_stop();
571 /* as per EAS2.6, itc must be the last instruction in an instruction group */
572 if (target_mask & 0x1)
573 ia64_itci(pte);
574 if (target_mask & 0x2)
575 ia64_itcd(pte);
576}
577
578/*
579 * Purge a range of addresses from instruction and/or data translation
580 * register(s).
581 */
582static inline void
583ia64_ptr (__u64 target_mask, __u64 vmaddr, __u64 log_size)
584{
585 if (target_mask & 0x1)
586 ia64_ptri(vmaddr, (log_size << 2));
587 if (target_mask & 0x2)
588 ia64_ptrd(vmaddr, (log_size << 2));
589}
590
591/* Set the interrupt vector address. The address must be suitably aligned (32KB). */
592static inline void
593ia64_set_iva (void *ivt_addr)
594{
595 ia64_setreg(_IA64_REG_CR_IVA, (__u64) ivt_addr);
596 ia64_srlz_i();
597}
598
599/* Set the page table address and control bits. */
600static inline void
601ia64_set_pta (__u64 pta)
602{
603 /* Note: srlz.i implies srlz.d */
604 ia64_setreg(_IA64_REG_CR_PTA, pta);
605 ia64_srlz_i();
606}
607
608static inline void
609ia64_eoi (void)
610{
611 ia64_setreg(_IA64_REG_CR_EOI, 0);
612 ia64_srlz_d();
613}
614
615#define cpu_relax() ia64_hint(ia64_hint_pause)
616
617static inline int
618ia64_get_irr(unsigned int vector)
619{
620 unsigned int reg = vector / 64;
621 unsigned int bit = vector % 64;
622 u64 irr;
623
624 switch (reg) {
625 case 0: irr = ia64_getreg(_IA64_REG_CR_IRR0); break;
626 case 1: irr = ia64_getreg(_IA64_REG_CR_IRR1); break;
627 case 2: irr = ia64_getreg(_IA64_REG_CR_IRR2); break;
628 case 3: irr = ia64_getreg(_IA64_REG_CR_IRR3); break;
629 }
630
631 return test_bit(bit, &irr);
632}
633
634static inline void
635ia64_set_lrr0 (unsigned long val)
636{
637 ia64_setreg(_IA64_REG_CR_LRR0, val);
638 ia64_srlz_d();
639}
640
641static inline void
642ia64_set_lrr1 (unsigned long val)
643{
644 ia64_setreg(_IA64_REG_CR_LRR1, val);
645 ia64_srlz_d();
646}
647
648
649/*
650 * Given the address to which a spill occurred, return the unat bit
651 * number that corresponds to this address.
652 */
653static inline __u64
654ia64_unat_pos (void *spill_addr)
655{
656 return ((__u64) spill_addr >> 3) & 0x3f;
657}
658
659/*
660 * Set the NaT bit of an integer register which was spilled at address
661 * SPILL_ADDR. UNAT is the mask to be updated.
662 */
663static inline void
664ia64_set_unat (__u64 *unat, void *spill_addr, unsigned long nat)
665{
666 __u64 bit = ia64_unat_pos(spill_addr);
667 __u64 mask = 1UL << bit;
668
669 *unat = (*unat & ~mask) | (nat << bit);
670}
671
672/*
673 * Return saved PC of a blocked thread.
674 * Note that the only way T can block is through a call to schedule() -> switch_to().
675 */
676static inline unsigned long
677thread_saved_pc (struct task_struct *t)
678{
679 struct unw_frame_info info;
680 unsigned long ip;
681
682 unw_init_from_blocked_task(&info, t);
683 if (unw_unwind(&info) < 0)
684 return 0;
685 unw_get_ip(&info, &ip);
686 return ip;
687}
688
689/*
690 * Get the current instruction/program counter value.
691 */
692#define current_text_addr() \
693 ({ void *_pc; _pc = (void *)ia64_getreg(_IA64_REG_IP); _pc; })
694
695static inline __u64
696ia64_get_ivr (void)
697{
698 __u64 r;
699 ia64_srlz_d();
700 r = ia64_getreg(_IA64_REG_CR_IVR);
701 ia64_srlz_d();
702 return r;
703}
704
705static inline void
706ia64_set_dbr (__u64 regnum, __u64 value)
707{
708 __ia64_set_dbr(regnum, value);
709#ifdef CONFIG_ITANIUM
710 ia64_srlz_d();
711#endif
712}
713
714static inline __u64
715ia64_get_dbr (__u64 regnum)
716{
717 __u64 retval;
718
719 retval = __ia64_get_dbr(regnum);
720#ifdef CONFIG_ITANIUM
721 ia64_srlz_d();
722#endif
723 return retval;
724}
725
726static inline __u64
727ia64_rotr (__u64 w, __u64 n)
728{
729 return (w >> n) | (w << (64 - n));
730}
731
732#define ia64_rotl(w,n) ia64_rotr((w), (64) - (n))
733
734/*
735 * Take a mapped kernel address and return the equivalent address
736 * in the region 7 identity mapped virtual area.
737 */
738static inline void *
739ia64_imva (void *addr)
740{
741 void *result;
742 result = (void *) ia64_tpa(addr);
743 return __va(result);
744}
745
746#define ARCH_HAS_PREFETCH
747#define ARCH_HAS_PREFETCHW
748#define ARCH_HAS_SPINLOCK_PREFETCH
749#define PREFETCH_STRIDE L1_CACHE_BYTES
750
751static inline void
752prefetch (const void *x)
753{
754 ia64_lfetch(ia64_lfhint_none, x);
755}
756
757static inline void
758prefetchw (const void *x)
759{
760 ia64_lfetch_excl(ia64_lfhint_none, x);
761}
762
763#define spin_lock_prefetch(x) prefetchw(x)
764
765extern unsigned long boot_option_idle_override;
766extern unsigned long idle_halt;
767extern unsigned long idle_nomwait;
768
769#endif /* !__ASSEMBLY__ */
770
771#endif /* _ASM_IA64_PROCESSOR_H */
diff --git a/include/asm-ia64/ptrace.h b/include/asm-ia64/ptrace.h
deleted file mode 100644
index 15f8dcfe6ee..00000000000
--- a/include/asm-ia64/ptrace.h
+++ /dev/null
@@ -1,364 +0,0 @@
1#ifndef _ASM_IA64_PTRACE_H
2#define _ASM_IA64_PTRACE_H
3
4/*
5 * Copyright (C) 1998-2004 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 * Stephane Eranian <eranian@hpl.hp.com>
8 * Copyright (C) 2003 Intel Co
9 * Suresh Siddha <suresh.b.siddha@intel.com>
10 * Fenghua Yu <fenghua.yu@intel.com>
11 * Arun Sharma <arun.sharma@intel.com>
12 *
13 * 12/07/98 S. Eranian added pt_regs & switch_stack
14 * 12/21/98 D. Mosberger updated to match latest code
15 * 6/17/99 D. Mosberger added second unat member to "struct switch_stack"
16 *
17 */
18/*
19 * When a user process is blocked, its state looks as follows:
20 *
21 * +----------------------+ ------- IA64_STK_OFFSET
22 * | | ^
23 * | struct pt_regs | |
24 * | | |
25 * +----------------------+ |
26 * | | |
27 * | memory stack | |
28 * | (growing downwards) | |
29 * //.....................// |
30 * |
31 * //.....................// |
32 * | | |
33 * +----------------------+ |
34 * | struct switch_stack | |
35 * | | |
36 * +----------------------+ |
37 * | | |
38 * //.....................// |
39 * |
40 * //.....................// |
41 * | | |
42 * | register stack | |
43 * | (growing upwards) | |
44 * | | |
45 * +----------------------+ | --- IA64_RBS_OFFSET
46 * | struct thread_info | | ^
47 * +----------------------+ | |
48 * | | | |
49 * | struct task_struct | | |
50 * current -> | | | |
51 * +----------------------+ -------
52 *
53 * Note that ar.ec is not saved explicitly in pt_reg or switch_stack.
54 * This is because ar.ec is saved as part of ar.pfs.
55 */
56
57
58#include <asm/fpu.h>
59
60#ifdef __KERNEL__
61#ifndef ASM_OFFSETS_C
62#include <asm/asm-offsets.h>
63#endif
64
65/*
66 * Base-2 logarithm of number of pages to allocate per task structure
67 * (including register backing store and memory stack):
68 */
69#if defined(CONFIG_IA64_PAGE_SIZE_4KB)
70# define KERNEL_STACK_SIZE_ORDER 3
71#elif defined(CONFIG_IA64_PAGE_SIZE_8KB)
72# define KERNEL_STACK_SIZE_ORDER 2
73#elif defined(CONFIG_IA64_PAGE_SIZE_16KB)
74# define KERNEL_STACK_SIZE_ORDER 1
75#else
76# define KERNEL_STACK_SIZE_ORDER 0
77#endif
78
79#define IA64_RBS_OFFSET ((IA64_TASK_SIZE + IA64_THREAD_INFO_SIZE + 31) & ~31)
80#define IA64_STK_OFFSET ((1 << KERNEL_STACK_SIZE_ORDER)*PAGE_SIZE)
81
82#define KERNEL_STACK_SIZE IA64_STK_OFFSET
83
84#endif /* __KERNEL__ */
85
86#ifndef __ASSEMBLY__
87
88/*
89 * This struct defines the way the registers are saved on system
90 * calls.
91 *
92 * We don't save all floating point register because the kernel
93 * is compiled to use only a very small subset, so the other are
94 * untouched.
95 *
96 * THIS STRUCTURE MUST BE A MULTIPLE 16-BYTE IN SIZE
97 * (because the memory stack pointer MUST ALWAYS be aligned this way)
98 *
99 */
100struct pt_regs {
101 /* The following registers are saved by SAVE_MIN: */
102 unsigned long b6; /* scratch */
103 unsigned long b7; /* scratch */
104
105 unsigned long ar_csd; /* used by cmp8xchg16 (scratch) */
106 unsigned long ar_ssd; /* reserved for future use (scratch) */
107
108 unsigned long r8; /* scratch (return value register 0) */
109 unsigned long r9; /* scratch (return value register 1) */
110 unsigned long r10; /* scratch (return value register 2) */
111 unsigned long r11; /* scratch (return value register 3) */
112
113 unsigned long cr_ipsr; /* interrupted task's psr */
114 unsigned long cr_iip; /* interrupted task's instruction pointer */
115 /*
116 * interrupted task's function state; if bit 63 is cleared, it
117 * contains syscall's ar.pfs.pfm:
118 */
119 unsigned long cr_ifs;
120
121 unsigned long ar_unat; /* interrupted task's NaT register (preserved) */
122 unsigned long ar_pfs; /* prev function state */
123 unsigned long ar_rsc; /* RSE configuration */
124 /* The following two are valid only if cr_ipsr.cpl > 0 || ti->flags & _TIF_MCA_INIT */
125 unsigned long ar_rnat; /* RSE NaT */
126 unsigned long ar_bspstore; /* RSE bspstore */
127
128 unsigned long pr; /* 64 predicate registers (1 bit each) */
129 unsigned long b0; /* return pointer (bp) */
130 unsigned long loadrs; /* size of dirty partition << 16 */
131
132 unsigned long r1; /* the gp pointer */
133 unsigned long r12; /* interrupted task's memory stack pointer */
134 unsigned long r13; /* thread pointer */
135
136 unsigned long ar_fpsr; /* floating point status (preserved) */
137 unsigned long r15; /* scratch */
138
139 /* The remaining registers are NOT saved for system calls. */
140
141 unsigned long r14; /* scratch */
142 unsigned long r2; /* scratch */
143 unsigned long r3; /* scratch */
144
145 /* The following registers are saved by SAVE_REST: */
146 unsigned long r16; /* scratch */
147 unsigned long r17; /* scratch */
148 unsigned long r18; /* scratch */
149 unsigned long r19; /* scratch */
150 unsigned long r20; /* scratch */
151 unsigned long r21; /* scratch */
152 unsigned long r22; /* scratch */
153 unsigned long r23; /* scratch */
154 unsigned long r24; /* scratch */
155 unsigned long r25; /* scratch */
156 unsigned long r26; /* scratch */
157 unsigned long r27; /* scratch */
158 unsigned long r28; /* scratch */
159 unsigned long r29; /* scratch */
160 unsigned long r30; /* scratch */
161 unsigned long r31; /* scratch */
162
163 unsigned long ar_ccv; /* compare/exchange value (scratch) */
164
165 /*
166 * Floating point registers that the kernel considers scratch:
167 */
168 struct ia64_fpreg f6; /* scratch */
169 struct ia64_fpreg f7; /* scratch */
170 struct ia64_fpreg f8; /* scratch */
171 struct ia64_fpreg f9; /* scratch */
172 struct ia64_fpreg f10; /* scratch */
173 struct ia64_fpreg f11; /* scratch */
174};
175
176/*
177 * This structure contains the addition registers that need to
178 * preserved across a context switch. This generally consists of
179 * "preserved" registers.
180 */
181struct switch_stack {
182 unsigned long caller_unat; /* user NaT collection register (preserved) */
183 unsigned long ar_fpsr; /* floating-point status register */
184
185 struct ia64_fpreg f2; /* preserved */
186 struct ia64_fpreg f3; /* preserved */
187 struct ia64_fpreg f4; /* preserved */
188 struct ia64_fpreg f5; /* preserved */
189
190 struct ia64_fpreg f12; /* scratch, but untouched by kernel */
191 struct ia64_fpreg f13; /* scratch, but untouched by kernel */
192 struct ia64_fpreg f14; /* scratch, but untouched by kernel */
193 struct ia64_fpreg f15; /* scratch, but untouched by kernel */
194 struct ia64_fpreg f16; /* preserved */
195 struct ia64_fpreg f17; /* preserved */
196 struct ia64_fpreg f18; /* preserved */
197 struct ia64_fpreg f19; /* preserved */
198 struct ia64_fpreg f20; /* preserved */
199 struct ia64_fpreg f21; /* preserved */
200 struct ia64_fpreg f22; /* preserved */
201 struct ia64_fpreg f23; /* preserved */
202 struct ia64_fpreg f24; /* preserved */
203 struct ia64_fpreg f25; /* preserved */
204 struct ia64_fpreg f26; /* preserved */
205 struct ia64_fpreg f27; /* preserved */
206 struct ia64_fpreg f28; /* preserved */
207 struct ia64_fpreg f29; /* preserved */
208 struct ia64_fpreg f30; /* preserved */
209 struct ia64_fpreg f31; /* preserved */
210
211 unsigned long r4; /* preserved */
212 unsigned long r5; /* preserved */
213 unsigned long r6; /* preserved */
214 unsigned long r7; /* preserved */
215
216 unsigned long b0; /* so we can force a direct return in copy_thread */
217 unsigned long b1;
218 unsigned long b2;
219 unsigned long b3;
220 unsigned long b4;
221 unsigned long b5;
222
223 unsigned long ar_pfs; /* previous function state */
224 unsigned long ar_lc; /* loop counter (preserved) */
225 unsigned long ar_unat; /* NaT bits for r4-r7 */
226 unsigned long ar_rnat; /* RSE NaT collection register */
227 unsigned long ar_bspstore; /* RSE dirty base (preserved) */
228 unsigned long pr; /* 64 predicate registers (1 bit each) */
229};
230
231#ifdef __KERNEL__
232
233#include <asm/current.h>
234#include <asm/page.h>
235
236/*
237 * We use the ia64_psr(regs)->ri to determine which of the three
238 * instructions in bundle (16 bytes) took the sample. Generate
239 * the canonical representation by adding to instruction pointer.
240 */
241# define instruction_pointer(regs) ((regs)->cr_iip + ia64_psr(regs)->ri)
242
243#define regs_return_value(regs) ((regs)->r8)
244
245/* Conserve space in histogram by encoding slot bits in address
246 * bits 2 and 3 rather than bits 0 and 1.
247 */
248#define profile_pc(regs) \
249({ \
250 unsigned long __ip = instruction_pointer(regs); \
251 (__ip & ~3UL) + ((__ip & 3UL) << 2); \
252})
253
254 /* given a pointer to a task_struct, return the user's pt_regs */
255# define task_pt_regs(t) (((struct pt_regs *) ((char *) (t) + IA64_STK_OFFSET)) - 1)
256# define ia64_psr(regs) ((struct ia64_psr *) &(regs)->cr_ipsr)
257# define user_mode(regs) (((struct ia64_psr *) &(regs)->cr_ipsr)->cpl != 0)
258# define user_stack(task,regs) ((long) regs - (long) task == IA64_STK_OFFSET - sizeof(*regs))
259# define fsys_mode(task,regs) \
260 ({ \
261 struct task_struct *_task = (task); \
262 struct pt_regs *_regs = (regs); \
263 !user_mode(_regs) && user_stack(_task, _regs); \
264 })
265
266 /*
267 * System call handlers that, upon successful completion, need to return a negative value
268 * should call force_successful_syscall_return() right before returning. On architectures
269 * where the syscall convention provides for a separate error flag (e.g., alpha, ia64,
270 * ppc{,64}, sparc{,64}, possibly others), this macro can be used to ensure that the error
271 * flag will not get set. On architectures which do not support a separate error flag,
272 * the macro is a no-op and the spurious error condition needs to be filtered out by some
273 * other means (e.g., in user-level, by passing an extra argument to the syscall handler,
274 * or something along those lines).
275 *
276 * On ia64, we can clear the user's pt_regs->r8 to force a successful syscall.
277 */
278# define force_successful_syscall_return() (task_pt_regs(current)->r8 = 0)
279
280 struct task_struct; /* forward decl */
281 struct unw_frame_info; /* forward decl */
282
283 extern void show_regs (struct pt_regs *);
284 extern void ia64_do_show_stack (struct unw_frame_info *, void *);
285 extern unsigned long ia64_get_user_rbs_end (struct task_struct *, struct pt_regs *,
286 unsigned long *);
287 extern long ia64_peek (struct task_struct *, struct switch_stack *, unsigned long,
288 unsigned long, long *);
289 extern long ia64_poke (struct task_struct *, struct switch_stack *, unsigned long,
290 unsigned long, long);
291 extern void ia64_flush_fph (struct task_struct *);
292 extern void ia64_sync_fph (struct task_struct *);
293 extern void ia64_sync_krbs(void);
294 extern long ia64_sync_user_rbs (struct task_struct *, struct switch_stack *,
295 unsigned long, unsigned long);
296
297 /* get nat bits for scratch registers such that bit N==1 iff scratch register rN is a NaT */
298 extern unsigned long ia64_get_scratch_nat_bits (struct pt_regs *pt, unsigned long scratch_unat);
299 /* put nat bits for scratch registers such that scratch register rN is a NaT iff bit N==1 */
300 extern unsigned long ia64_put_scratch_nat_bits (struct pt_regs *pt, unsigned long nat);
301
302 extern void ia64_increment_ip (struct pt_regs *pt);
303 extern void ia64_decrement_ip (struct pt_regs *pt);
304
305 extern void ia64_ptrace_stop(void);
306 #define arch_ptrace_stop(code, info) \
307 ia64_ptrace_stop()
308 #define arch_ptrace_stop_needed(code, info) \
309 (!test_thread_flag(TIF_RESTORE_RSE))
310
311 extern void ptrace_attach_sync_user_rbs (struct task_struct *);
312 #define arch_ptrace_attach(child) \
313 ptrace_attach_sync_user_rbs(child)
314
315 #define arch_has_single_step() (1)
316 extern void user_enable_single_step(struct task_struct *);
317 extern void user_disable_single_step(struct task_struct *);
318
319 #define arch_has_block_step() (1)
320 extern void user_enable_block_step(struct task_struct *);
321
322#endif /* !__KERNEL__ */
323
324/* pt_all_user_regs is used for PTRACE_GETREGS PTRACE_SETREGS */
325struct pt_all_user_regs {
326 unsigned long nat;
327 unsigned long cr_iip;
328 unsigned long cfm;
329 unsigned long cr_ipsr;
330 unsigned long pr;
331
332 unsigned long gr[32];
333 unsigned long br[8];
334 unsigned long ar[128];
335 struct ia64_fpreg fr[128];
336};
337
338#endif /* !__ASSEMBLY__ */
339
340/* indices to application-registers array in pt_all_user_regs */
341#define PT_AUR_RSC 16
342#define PT_AUR_BSP 17
343#define PT_AUR_BSPSTORE 18
344#define PT_AUR_RNAT 19
345#define PT_AUR_CCV 32
346#define PT_AUR_UNAT 36
347#define PT_AUR_FPSR 40
348#define PT_AUR_PFS 64
349#define PT_AUR_LC 65
350#define PT_AUR_EC 66
351
352/*
353 * The numbers chosen here are somewhat arbitrary but absolutely MUST
354 * not overlap with any of the number assigned in <linux/ptrace.h>.
355 */
356#define PTRACE_SINGLEBLOCK 12 /* resume execution until next branch */
357#define PTRACE_OLD_GETSIGINFO 13 /* (replaced by PTRACE_GETSIGINFO in <linux/ptrace.h>) */
358#define PTRACE_OLD_SETSIGINFO 14 /* (replaced by PTRACE_SETSIGINFO in <linux/ptrace.h>) */
359#define PTRACE_GETREGS 18 /* get all registers (pt_all_user_regs) in one shot */
360#define PTRACE_SETREGS 19 /* set all registers (pt_all_user_regs) in one shot */
361
362#define PTRACE_OLDSETOPTIONS 21
363
364#endif /* _ASM_IA64_PTRACE_H */
diff --git a/include/asm-ia64/ptrace_offsets.h b/include/asm-ia64/ptrace_offsets.h
deleted file mode 100644
index b712773c759..00000000000
--- a/include/asm-ia64/ptrace_offsets.h
+++ /dev/null
@@ -1,268 +0,0 @@
1#ifndef _ASM_IA64_PTRACE_OFFSETS_H
2#define _ASM_IA64_PTRACE_OFFSETS_H
3
4/*
5 * Copyright (C) 1999, 2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 */
8/*
9 * The "uarea" that can be accessed via PEEKUSER and POKEUSER is a
10 * virtual structure that would have the following definition:
11 *
12 * struct uarea {
13 * struct ia64_fpreg fph[96]; // f32-f127
14 * unsigned long nat_bits;
15 * unsigned long empty1;
16 * struct ia64_fpreg f2; // f2-f5
17 * :
18 * struct ia64_fpreg f5;
19 * struct ia64_fpreg f10; // f10-f31
20 * :
21 * struct ia64_fpreg f31;
22 * unsigned long r4; // r4-r7
23 * :
24 * unsigned long r7;
25 * unsigned long b1; // b1-b5
26 * :
27 * unsigned long b5;
28 * unsigned long ar_ec;
29 * unsigned long ar_lc;
30 * unsigned long empty2[5];
31 * unsigned long cr_ipsr;
32 * unsigned long cr_iip;
33 * unsigned long cfm;
34 * unsigned long ar_unat;
35 * unsigned long ar_pfs;
36 * unsigned long ar_rsc;
37 * unsigned long ar_rnat;
38 * unsigned long ar_bspstore;
39 * unsigned long pr;
40 * unsigned long b6;
41 * unsigned long ar_bsp;
42 * unsigned long r1;
43 * unsigned long r2;
44 * unsigned long r3;
45 * unsigned long r12;
46 * unsigned long r13;
47 * unsigned long r14;
48 * unsigned long r15;
49 * unsigned long r8;
50 * unsigned long r9;
51 * unsigned long r10;
52 * unsigned long r11;
53 * unsigned long r16;
54 * :
55 * unsigned long r31;
56 * unsigned long ar_ccv;
57 * unsigned long ar_fpsr;
58 * unsigned long b0;
59 * unsigned long b7;
60 * unsigned long f6;
61 * unsigned long f7;
62 * unsigned long f8;
63 * unsigned long f9;
64 * unsigned long ar_csd;
65 * unsigned long ar_ssd;
66 * unsigned long rsvd1[710];
67 * unsigned long dbr[8];
68 * unsigned long rsvd2[504];
69 * unsigned long ibr[8];
70 * unsigned long rsvd3[504];
71 * unsigned long pmd[4];
72 * }
73 */
74
75/* fph: */
76#define PT_F32 0x0000
77#define PT_F33 0x0010
78#define PT_F34 0x0020
79#define PT_F35 0x0030
80#define PT_F36 0x0040
81#define PT_F37 0x0050
82#define PT_F38 0x0060
83#define PT_F39 0x0070
84#define PT_F40 0x0080
85#define PT_F41 0x0090
86#define PT_F42 0x00a0
87#define PT_F43 0x00b0
88#define PT_F44 0x00c0
89#define PT_F45 0x00d0
90#define PT_F46 0x00e0
91#define PT_F47 0x00f0
92#define PT_F48 0x0100
93#define PT_F49 0x0110
94#define PT_F50 0x0120
95#define PT_F51 0x0130
96#define PT_F52 0x0140
97#define PT_F53 0x0150
98#define PT_F54 0x0160
99#define PT_F55 0x0170
100#define PT_F56 0x0180
101#define PT_F57 0x0190
102#define PT_F58 0x01a0
103#define PT_F59 0x01b0
104#define PT_F60 0x01c0
105#define PT_F61 0x01d0
106#define PT_F62 0x01e0
107#define PT_F63 0x01f0
108#define PT_F64 0x0200
109#define PT_F65 0x0210
110#define PT_F66 0x0220
111#define PT_F67 0x0230
112#define PT_F68 0x0240
113#define PT_F69 0x0250
114#define PT_F70 0x0260
115#define PT_F71 0x0270
116#define PT_F72 0x0280
117#define PT_F73 0x0290
118#define PT_F74 0x02a0
119#define PT_F75 0x02b0
120#define PT_F76 0x02c0
121#define PT_F77 0x02d0
122#define PT_F78 0x02e0
123#define PT_F79 0x02f0
124#define PT_F80 0x0300
125#define PT_F81 0x0310
126#define PT_F82 0x0320
127#define PT_F83 0x0330
128#define PT_F84 0x0340
129#define PT_F85 0x0350
130#define PT_F86 0x0360
131#define PT_F87 0x0370
132#define PT_F88 0x0380
133#define PT_F89 0x0390
134#define PT_F90 0x03a0
135#define PT_F91 0x03b0
136#define PT_F92 0x03c0
137#define PT_F93 0x03d0
138#define PT_F94 0x03e0
139#define PT_F95 0x03f0
140#define PT_F96 0x0400
141#define PT_F97 0x0410
142#define PT_F98 0x0420
143#define PT_F99 0x0430
144#define PT_F100 0x0440
145#define PT_F101 0x0450
146#define PT_F102 0x0460
147#define PT_F103 0x0470
148#define PT_F104 0x0480
149#define PT_F105 0x0490
150#define PT_F106 0x04a0
151#define PT_F107 0x04b0
152#define PT_F108 0x04c0
153#define PT_F109 0x04d0
154#define PT_F110 0x04e0
155#define PT_F111 0x04f0
156#define PT_F112 0x0500
157#define PT_F113 0x0510
158#define PT_F114 0x0520
159#define PT_F115 0x0530
160#define PT_F116 0x0540
161#define PT_F117 0x0550
162#define PT_F118 0x0560
163#define PT_F119 0x0570
164#define PT_F120 0x0580
165#define PT_F121 0x0590
166#define PT_F122 0x05a0
167#define PT_F123 0x05b0
168#define PT_F124 0x05c0
169#define PT_F125 0x05d0
170#define PT_F126 0x05e0
171#define PT_F127 0x05f0
172
173#define PT_NAT_BITS 0x0600
174
175#define PT_F2 0x0610
176#define PT_F3 0x0620
177#define PT_F4 0x0630
178#define PT_F5 0x0640
179#define PT_F10 0x0650
180#define PT_F11 0x0660
181#define PT_F12 0x0670
182#define PT_F13 0x0680
183#define PT_F14 0x0690
184#define PT_F15 0x06a0
185#define PT_F16 0x06b0
186#define PT_F17 0x06c0
187#define PT_F18 0x06d0
188#define PT_F19 0x06e0
189#define PT_F20 0x06f0
190#define PT_F21 0x0700
191#define PT_F22 0x0710
192#define PT_F23 0x0720
193#define PT_F24 0x0730
194#define PT_F25 0x0740
195#define PT_F26 0x0750
196#define PT_F27 0x0760
197#define PT_F28 0x0770
198#define PT_F29 0x0780
199#define PT_F30 0x0790
200#define PT_F31 0x07a0
201#define PT_R4 0x07b0
202#define PT_R5 0x07b8
203#define PT_R6 0x07c0
204#define PT_R7 0x07c8
205
206#define PT_B1 0x07d8
207#define PT_B2 0x07e0
208#define PT_B3 0x07e8
209#define PT_B4 0x07f0
210#define PT_B5 0x07f8
211
212#define PT_AR_EC 0x0800
213#define PT_AR_LC 0x0808
214
215#define PT_CR_IPSR 0x0830
216#define PT_CR_IIP 0x0838
217#define PT_CFM 0x0840
218#define PT_AR_UNAT 0x0848
219#define PT_AR_PFS 0x0850
220#define PT_AR_RSC 0x0858
221#define PT_AR_RNAT 0x0860
222#define PT_AR_BSPSTORE 0x0868
223#define PT_PR 0x0870
224#define PT_B6 0x0878
225#define PT_AR_BSP 0x0880 /* note: this points to the *end* of the backing store! */
226#define PT_R1 0x0888
227#define PT_R2 0x0890
228#define PT_R3 0x0898
229#define PT_R12 0x08a0
230#define PT_R13 0x08a8
231#define PT_R14 0x08b0
232#define PT_R15 0x08b8
233#define PT_R8 0x08c0
234#define PT_R9 0x08c8
235#define PT_R10 0x08d0
236#define PT_R11 0x08d8
237#define PT_R16 0x08e0
238#define PT_R17 0x08e8
239#define PT_R18 0x08f0
240#define PT_R19 0x08f8
241#define PT_R20 0x0900
242#define PT_R21 0x0908
243#define PT_R22 0x0910
244#define PT_R23 0x0918
245#define PT_R24 0x0920
246#define PT_R25 0x0928
247#define PT_R26 0x0930
248#define PT_R27 0x0938
249#define PT_R28 0x0940
250#define PT_R29 0x0948
251#define PT_R30 0x0950
252#define PT_R31 0x0958
253#define PT_AR_CCV 0x0960
254#define PT_AR_FPSR 0x0968
255#define PT_B0 0x0970
256#define PT_B7 0x0978
257#define PT_F6 0x0980
258#define PT_F7 0x0990
259#define PT_F8 0x09a0
260#define PT_F9 0x09b0
261#define PT_AR_CSD 0x09c0
262#define PT_AR_SSD 0x09c8
263
264#define PT_DBR 0x2000 /* data breakpoint registers */
265#define PT_IBR 0x3000 /* instruction breakpoint registers */
266#define PT_PMD 0x4000 /* performance monitoring counters */
267
268#endif /* _ASM_IA64_PTRACE_OFFSETS_H */
diff --git a/include/asm-ia64/resource.h b/include/asm-ia64/resource.h
deleted file mode 100644
index ba2272a87fc..00000000000
--- a/include/asm-ia64/resource.h
+++ /dev/null
@@ -1,7 +0,0 @@
1#ifndef _ASM_IA64_RESOURCE_H
2#define _ASM_IA64_RESOURCE_H
3
4#include <asm/ustack.h>
5#include <asm-generic/resource.h>
6
7#endif /* _ASM_IA64_RESOURCE_H */
diff --git a/include/asm-ia64/rse.h b/include/asm-ia64/rse.h
deleted file mode 100644
index 02830a3b019..00000000000
--- a/include/asm-ia64/rse.h
+++ /dev/null
@@ -1,66 +0,0 @@
1#ifndef _ASM_IA64_RSE_H
2#define _ASM_IA64_RSE_H
3
4/*
5 * Copyright (C) 1998, 1999 Hewlett-Packard Co
6 * Copyright (C) 1998, 1999 David Mosberger-Tang <davidm@hpl.hp.com>
7 *
8 * Register stack engine related helper functions. This file may be
9 * used in applications, so be careful about the name-space and give
10 * some consideration to non-GNU C compilers (though __inline__ is
11 * fine).
12 */
13
14static __inline__ unsigned long
15ia64_rse_slot_num (unsigned long *addr)
16{
17 return (((unsigned long) addr) >> 3) & 0x3f;
18}
19
20/*
21 * Return TRUE if ADDR is the address of an RNAT slot.
22 */
23static __inline__ unsigned long
24ia64_rse_is_rnat_slot (unsigned long *addr)
25{
26 return ia64_rse_slot_num(addr) == 0x3f;
27}
28
29/*
30 * Returns the address of the RNAT slot that covers the slot at
31 * address SLOT_ADDR.
32 */
33static __inline__ unsigned long *
34ia64_rse_rnat_addr (unsigned long *slot_addr)
35{
36 return (unsigned long *) ((unsigned long) slot_addr | (0x3f << 3));
37}
38
39/*
40 * Calculate the number of registers in the dirty partition starting at BSPSTORE and
41 * ending at BSP. This isn't simply (BSP-BSPSTORE)/8 because every 64th slot stores
42 * ar.rnat.
43 */
44static __inline__ unsigned long
45ia64_rse_num_regs (unsigned long *bspstore, unsigned long *bsp)
46{
47 unsigned long slots = (bsp - bspstore);
48
49 return slots - (ia64_rse_slot_num(bspstore) + slots)/0x40;
50}
51
52/*
53 * The inverse of the above: given bspstore and the number of
54 * registers, calculate ar.bsp.
55 */
56static __inline__ unsigned long *
57ia64_rse_skip_regs (unsigned long *addr, long num_regs)
58{
59 long delta = ia64_rse_slot_num(addr) + num_regs;
60
61 if (num_regs < 0)
62 delta -= 0x3e;
63 return addr + num_regs + delta/0x3f;
64}
65
66#endif /* _ASM_IA64_RSE_H */
diff --git a/include/asm-ia64/rwsem.h b/include/asm-ia64/rwsem.h
deleted file mode 100644
index 8aba06a7b03..00000000000
--- a/include/asm-ia64/rwsem.h
+++ /dev/null
@@ -1,182 +0,0 @@
1/*
2 * asm-ia64/rwsem.h: R/W semaphores for ia64
3 *
4 * Copyright (C) 2003 Ken Chen <kenneth.w.chen@intel.com>
5 * Copyright (C) 2003 Asit Mallick <asit.k.mallick@intel.com>
6 * Copyright (C) 2005 Christoph Lameter <clameter@sgi.com>
7 *
8 * Based on asm-i386/rwsem.h and other architecture implementation.
9 *
10 * The MSW of the count is the negated number of active writers and
11 * waiting lockers, and the LSW is the total number of active locks.
12 *
13 * The lock count is initialized to 0 (no active and no waiting lockers).
14 *
15 * When a writer subtracts WRITE_BIAS, it'll get 0xffffffff00000001 for
16 * the case of an uncontended lock. Readers increment by 1 and see a positive
17 * value when uncontended, negative if there are writers (and maybe) readers
18 * waiting (in which case it goes to sleep).
19 */
20
21#ifndef _ASM_IA64_RWSEM_H
22#define _ASM_IA64_RWSEM_H
23
24#ifndef _LINUX_RWSEM_H
25#error "Please don't include <asm/rwsem.h> directly, use <linux/rwsem.h> instead."
26#endif
27
28#include <linux/list.h>
29#include <linux/spinlock.h>
30
31#include <asm/intrinsics.h>
32
33/*
34 * the semaphore definition
35 */
36struct rw_semaphore {
37 signed long count;
38 spinlock_t wait_lock;
39 struct list_head wait_list;
40};
41
42#define RWSEM_UNLOCKED_VALUE __IA64_UL_CONST(0x0000000000000000)
43#define RWSEM_ACTIVE_BIAS __IA64_UL_CONST(0x0000000000000001)
44#define RWSEM_ACTIVE_MASK __IA64_UL_CONST(0x00000000ffffffff)
45#define RWSEM_WAITING_BIAS -__IA64_UL_CONST(0x0000000100000000)
46#define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS
47#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
48
49#define __RWSEM_INITIALIZER(name) \
50 { RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, \
51 LIST_HEAD_INIT((name).wait_list) }
52
53#define DECLARE_RWSEM(name) \
54 struct rw_semaphore name = __RWSEM_INITIALIZER(name)
55
56extern struct rw_semaphore *rwsem_down_read_failed(struct rw_semaphore *sem);
57extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem);
58extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem);
59extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem);
60
61static inline void
62init_rwsem (struct rw_semaphore *sem)
63{
64 sem->count = RWSEM_UNLOCKED_VALUE;
65 spin_lock_init(&sem->wait_lock);
66 INIT_LIST_HEAD(&sem->wait_list);
67}
68
69/*
70 * lock for reading
71 */
72static inline void
73__down_read (struct rw_semaphore *sem)
74{
75 long result = ia64_fetchadd8_acq((unsigned long *)&sem->count, 1);
76
77 if (result < 0)
78 rwsem_down_read_failed(sem);
79}
80
81/*
82 * lock for writing
83 */
84static inline void
85__down_write (struct rw_semaphore *sem)
86{
87 long old, new;
88
89 do {
90 old = sem->count;
91 new = old + RWSEM_ACTIVE_WRITE_BIAS;
92 } while (cmpxchg_acq(&sem->count, old, new) != old);
93
94 if (old != 0)
95 rwsem_down_write_failed(sem);
96}
97
98/*
99 * unlock after reading
100 */
101static inline void
102__up_read (struct rw_semaphore *sem)
103{
104 long result = ia64_fetchadd8_rel((unsigned long *)&sem->count, -1);
105
106 if (result < 0 && (--result & RWSEM_ACTIVE_MASK) == 0)
107 rwsem_wake(sem);
108}
109
110/*
111 * unlock after writing
112 */
113static inline void
114__up_write (struct rw_semaphore *sem)
115{
116 long old, new;
117
118 do {
119 old = sem->count;
120 new = old - RWSEM_ACTIVE_WRITE_BIAS;
121 } while (cmpxchg_rel(&sem->count, old, new) != old);
122
123 if (new < 0 && (new & RWSEM_ACTIVE_MASK) == 0)
124 rwsem_wake(sem);
125}
126
127/*
128 * trylock for reading -- returns 1 if successful, 0 if contention
129 */
130static inline int
131__down_read_trylock (struct rw_semaphore *sem)
132{
133 long tmp;
134 while ((tmp = sem->count) >= 0) {
135 if (tmp == cmpxchg_acq(&sem->count, tmp, tmp+1)) {
136 return 1;
137 }
138 }
139 return 0;
140}
141
142/*
143 * trylock for writing -- returns 1 if successful, 0 if contention
144 */
145static inline int
146__down_write_trylock (struct rw_semaphore *sem)
147{
148 long tmp = cmpxchg_acq(&sem->count, RWSEM_UNLOCKED_VALUE,
149 RWSEM_ACTIVE_WRITE_BIAS);
150 return tmp == RWSEM_UNLOCKED_VALUE;
151}
152
153/*
154 * downgrade write lock to read lock
155 */
156static inline void
157__downgrade_write (struct rw_semaphore *sem)
158{
159 long old, new;
160
161 do {
162 old = sem->count;
163 new = old - RWSEM_WAITING_BIAS;
164 } while (cmpxchg_rel(&sem->count, old, new) != old);
165
166 if (old < 0)
167 rwsem_downgrade_wake(sem);
168}
169
170/*
171 * Implement atomic add functionality. These used to be "inline" functions, but GCC v3.1
172 * doesn't quite optimize this stuff right and ends up with bad calls to fetchandadd.
173 */
174#define rwsem_atomic_add(delta, sem) atomic64_add(delta, (atomic64_t *)(&(sem)->count))
175#define rwsem_atomic_update(delta, sem) atomic64_add_return(delta, (atomic64_t *)(&(sem)->count))
176
177static inline int rwsem_is_locked(struct rw_semaphore *sem)
178{
179 return (sem->count != 0);
180}
181
182#endif /* _ASM_IA64_RWSEM_H */
diff --git a/include/asm-ia64/sal.h b/include/asm-ia64/sal.h
deleted file mode 100644
index 89594b442f8..00000000000
--- a/include/asm-ia64/sal.h
+++ /dev/null
@@ -1,905 +0,0 @@
1#ifndef _ASM_IA64_SAL_H
2#define _ASM_IA64_SAL_H
3
4/*
5 * System Abstraction Layer definitions.
6 *
7 * This is based on version 2.5 of the manual "IA-64 System
8 * Abstraction Layer".
9 *
10 * Copyright (C) 2001 Intel
11 * Copyright (C) 2002 Jenna Hall <jenna.s.hall@intel.com>
12 * Copyright (C) 2001 Fred Lewis <frederick.v.lewis@intel.com>
13 * Copyright (C) 1998, 1999, 2001, 2003 Hewlett-Packard Co
14 * David Mosberger-Tang <davidm@hpl.hp.com>
15 * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com>
16 *
17 * 02/01/04 J. Hall Updated Error Record Structures to conform to July 2001
18 * revision of the SAL spec.
19 * 01/01/03 fvlewis Updated Error Record Structures to conform with Nov. 2000
20 * revision of the SAL spec.
21 * 99/09/29 davidm Updated for SAL 2.6.
22 * 00/03/29 cfleck Updated SAL Error Logging info for processor (SAL 2.6)
23 * (plus examples of platform error info structures from smariset @ Intel)
24 */
25
26#define IA64_SAL_PLATFORM_FEATURE_BUS_LOCK_BIT 0
27#define IA64_SAL_PLATFORM_FEATURE_IRQ_REDIR_HINT_BIT 1
28#define IA64_SAL_PLATFORM_FEATURE_IPI_REDIR_HINT_BIT 2
29#define IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT_BIT 3
30
31#define IA64_SAL_PLATFORM_FEATURE_BUS_LOCK (1<<IA64_SAL_PLATFORM_FEATURE_BUS_LOCK_BIT)
32#define IA64_SAL_PLATFORM_FEATURE_IRQ_REDIR_HINT (1<<IA64_SAL_PLATFORM_FEATURE_IRQ_REDIR_HINT_BIT)
33#define IA64_SAL_PLATFORM_FEATURE_IPI_REDIR_HINT (1<<IA64_SAL_PLATFORM_FEATURE_IPI_REDIR_HINT_BIT)
34#define IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT (1<<IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT_BIT)
35
36#ifndef __ASSEMBLY__
37
38#include <linux/bcd.h>
39#include <linux/spinlock.h>
40#include <linux/efi.h>
41
42#include <asm/pal.h>
43#include <asm/system.h>
44#include <asm/fpu.h>
45
46extern spinlock_t sal_lock;
47
48/* SAL spec _requires_ eight args for each call. */
49#define __IA64_FW_CALL(entry,result,a0,a1,a2,a3,a4,a5,a6,a7) \
50 result = (*entry)(a0,a1,a2,a3,a4,a5,a6,a7)
51
52# define IA64_FW_CALL(entry,result,args...) do { \
53 unsigned long __ia64_sc_flags; \
54 struct ia64_fpreg __ia64_sc_fr[6]; \
55 ia64_save_scratch_fpregs(__ia64_sc_fr); \
56 spin_lock_irqsave(&sal_lock, __ia64_sc_flags); \
57 __IA64_FW_CALL(entry, result, args); \
58 spin_unlock_irqrestore(&sal_lock, __ia64_sc_flags); \
59 ia64_load_scratch_fpregs(__ia64_sc_fr); \
60} while (0)
61
62# define SAL_CALL(result,args...) \
63 IA64_FW_CALL(ia64_sal, result, args);
64
65# define SAL_CALL_NOLOCK(result,args...) do { \
66 unsigned long __ia64_scn_flags; \
67 struct ia64_fpreg __ia64_scn_fr[6]; \
68 ia64_save_scratch_fpregs(__ia64_scn_fr); \
69 local_irq_save(__ia64_scn_flags); \
70 __IA64_FW_CALL(ia64_sal, result, args); \
71 local_irq_restore(__ia64_scn_flags); \
72 ia64_load_scratch_fpregs(__ia64_scn_fr); \
73} while (0)
74
75# define SAL_CALL_REENTRANT(result,args...) do { \
76 struct ia64_fpreg __ia64_scs_fr[6]; \
77 ia64_save_scratch_fpregs(__ia64_scs_fr); \
78 preempt_disable(); \
79 __IA64_FW_CALL(ia64_sal, result, args); \
80 preempt_enable(); \
81 ia64_load_scratch_fpregs(__ia64_scs_fr); \
82} while (0)
83
84#define SAL_SET_VECTORS 0x01000000
85#define SAL_GET_STATE_INFO 0x01000001
86#define SAL_GET_STATE_INFO_SIZE 0x01000002
87#define SAL_CLEAR_STATE_INFO 0x01000003
88#define SAL_MC_RENDEZ 0x01000004
89#define SAL_MC_SET_PARAMS 0x01000005
90#define SAL_REGISTER_PHYSICAL_ADDR 0x01000006
91
92#define SAL_CACHE_FLUSH 0x01000008
93#define SAL_CACHE_INIT 0x01000009
94#define SAL_PCI_CONFIG_READ 0x01000010
95#define SAL_PCI_CONFIG_WRITE 0x01000011
96#define SAL_FREQ_BASE 0x01000012
97#define SAL_PHYSICAL_ID_INFO 0x01000013
98
99#define SAL_UPDATE_PAL 0x01000020
100
101struct ia64_sal_retval {
102 /*
103 * A zero status value indicates call completed without error.
104 * A negative status value indicates reason of call failure.
105 * A positive status value indicates success but an
106 * informational value should be printed (e.g., "reboot for
107 * change to take effect").
108 */
109 s64 status;
110 u64 v0;
111 u64 v1;
112 u64 v2;
113};
114
115typedef struct ia64_sal_retval (*ia64_sal_handler) (u64, ...);
116
117enum {
118 SAL_FREQ_BASE_PLATFORM = 0,
119 SAL_FREQ_BASE_INTERVAL_TIMER = 1,
120 SAL_FREQ_BASE_REALTIME_CLOCK = 2
121};
122
123/*
124 * The SAL system table is followed by a variable number of variable
125 * length descriptors. The structure of these descriptors follows
126 * below.
127 * The defininition follows SAL specs from July 2000
128 */
129struct ia64_sal_systab {
130 u8 signature[4]; /* should be "SST_" */
131 u32 size; /* size of this table in bytes */
132 u8 sal_rev_minor;
133 u8 sal_rev_major;
134 u16 entry_count; /* # of entries in variable portion */
135 u8 checksum;
136 u8 reserved1[7];
137 u8 sal_a_rev_minor;
138 u8 sal_a_rev_major;
139 u8 sal_b_rev_minor;
140 u8 sal_b_rev_major;
141 /* oem_id & product_id: terminating NUL is missing if string is exactly 32 bytes long. */
142 u8 oem_id[32];
143 u8 product_id[32]; /* ASCII product id */
144 u8 reserved2[8];
145};
146
147enum sal_systab_entry_type {
148 SAL_DESC_ENTRY_POINT = 0,
149 SAL_DESC_MEMORY = 1,
150 SAL_DESC_PLATFORM_FEATURE = 2,
151 SAL_DESC_TR = 3,
152 SAL_DESC_PTC = 4,
153 SAL_DESC_AP_WAKEUP = 5
154};
155
156/*
157 * Entry type: Size:
158 * 0 48
159 * 1 32
160 * 2 16
161 * 3 32
162 * 4 16
163 * 5 16
164 */
165#define SAL_DESC_SIZE(type) "\060\040\020\040\020\020"[(unsigned) type]
166
167typedef struct ia64_sal_desc_entry_point {
168 u8 type;
169 u8 reserved1[7];
170 u64 pal_proc;
171 u64 sal_proc;
172 u64 gp;
173 u8 reserved2[16];
174}ia64_sal_desc_entry_point_t;
175
176typedef struct ia64_sal_desc_memory {
177 u8 type;
178 u8 used_by_sal; /* needs to be mapped for SAL? */
179 u8 mem_attr; /* current memory attribute setting */
180 u8 access_rights; /* access rights set up by SAL */
181 u8 mem_attr_mask; /* mask of supported memory attributes */
182 u8 reserved1;
183 u8 mem_type; /* memory type */
184 u8 mem_usage; /* memory usage */
185 u64 addr; /* physical address of memory */
186 u32 length; /* length (multiple of 4KB pages) */
187 u32 reserved2;
188 u8 oem_reserved[8];
189} ia64_sal_desc_memory_t;
190
191typedef struct ia64_sal_desc_platform_feature {
192 u8 type;
193 u8 feature_mask;
194 u8 reserved1[14];
195} ia64_sal_desc_platform_feature_t;
196
197typedef struct ia64_sal_desc_tr {
198 u8 type;
199 u8 tr_type; /* 0 == instruction, 1 == data */
200 u8 regnum; /* translation register number */
201 u8 reserved1[5];
202 u64 addr; /* virtual address of area covered */
203 u64 page_size; /* encoded page size */
204 u8 reserved2[8];
205} ia64_sal_desc_tr_t;
206
207typedef struct ia64_sal_desc_ptc {
208 u8 type;
209 u8 reserved1[3];
210 u32 num_domains; /* # of coherence domains */
211 u64 domain_info; /* physical address of domain info table */
212} ia64_sal_desc_ptc_t;
213
214typedef struct ia64_sal_ptc_domain_info {
215 u64 proc_count; /* number of processors in domain */
216 u64 proc_list; /* physical address of LID array */
217} ia64_sal_ptc_domain_info_t;
218
219typedef struct ia64_sal_ptc_domain_proc_entry {
220 u64 id : 8; /* id of processor */
221 u64 eid : 8; /* eid of processor */
222} ia64_sal_ptc_domain_proc_entry_t;
223
224
225#define IA64_SAL_AP_EXTERNAL_INT 0
226
227typedef struct ia64_sal_desc_ap_wakeup {
228 u8 type;
229 u8 mechanism; /* 0 == external interrupt */
230 u8 reserved1[6];
231 u64 vector; /* interrupt vector in range 0x10-0xff */
232} ia64_sal_desc_ap_wakeup_t ;
233
234extern ia64_sal_handler ia64_sal;
235extern struct ia64_sal_desc_ptc *ia64_ptc_domain_info;
236
237extern unsigned short sal_revision; /* supported SAL spec revision */
238extern unsigned short sal_version; /* SAL version; OEM dependent */
239#define SAL_VERSION_CODE(major, minor) ((BIN2BCD(major) << 8) | BIN2BCD(minor))
240
241extern const char *ia64_sal_strerror (long status);
242extern void ia64_sal_init (struct ia64_sal_systab *sal_systab);
243
244/* SAL information type encodings */
245enum {
246 SAL_INFO_TYPE_MCA = 0, /* Machine check abort information */
247 SAL_INFO_TYPE_INIT = 1, /* Init information */
248 SAL_INFO_TYPE_CMC = 2, /* Corrected machine check information */
249 SAL_INFO_TYPE_CPE = 3 /* Corrected platform error information */
250};
251
252/* Encodings for machine check parameter types */
253enum {
254 SAL_MC_PARAM_RENDEZ_INT = 1, /* Rendezvous interrupt */
255 SAL_MC_PARAM_RENDEZ_WAKEUP = 2, /* Wakeup */
256 SAL_MC_PARAM_CPE_INT = 3 /* Corrected Platform Error Int */
257};
258
259/* Encodings for rendezvous mechanisms */
260enum {
261 SAL_MC_PARAM_MECHANISM_INT = 1, /* Use interrupt */
262 SAL_MC_PARAM_MECHANISM_MEM = 2 /* Use memory synchronization variable*/
263};
264
265/* Encodings for vectors which can be registered by the OS with SAL */
266enum {
267 SAL_VECTOR_OS_MCA = 0,
268 SAL_VECTOR_OS_INIT = 1,
269 SAL_VECTOR_OS_BOOT_RENDEZ = 2
270};
271
272/* Encodings for mca_opt parameter sent to SAL_MC_SET_PARAMS */
273#define SAL_MC_PARAM_RZ_ALWAYS 0x1
274#define SAL_MC_PARAM_BINIT_ESCALATE 0x10
275
276/*
277 * Definition of the SAL Error Log from the SAL spec
278 */
279
280/* SAL Error Record Section GUID Definitions */
281#define SAL_PROC_DEV_ERR_SECT_GUID \
282 EFI_GUID(0xe429faf1, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
283#define SAL_PLAT_MEM_DEV_ERR_SECT_GUID \
284 EFI_GUID(0xe429faf2, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
285#define SAL_PLAT_SEL_DEV_ERR_SECT_GUID \
286 EFI_GUID(0xe429faf3, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
287#define SAL_PLAT_PCI_BUS_ERR_SECT_GUID \
288 EFI_GUID(0xe429faf4, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
289#define SAL_PLAT_SMBIOS_DEV_ERR_SECT_GUID \
290 EFI_GUID(0xe429faf5, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
291#define SAL_PLAT_PCI_COMP_ERR_SECT_GUID \
292 EFI_GUID(0xe429faf6, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
293#define SAL_PLAT_SPECIFIC_ERR_SECT_GUID \
294 EFI_GUID(0xe429faf7, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
295#define SAL_PLAT_HOST_CTLR_ERR_SECT_GUID \
296 EFI_GUID(0xe429faf8, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
297#define SAL_PLAT_BUS_ERR_SECT_GUID \
298 EFI_GUID(0xe429faf9, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
299#define PROCESSOR_ABSTRACTION_LAYER_OVERWRITE_GUID \
300 EFI_GUID(0x6cb0a200, 0x893a, 0x11da, 0x96, 0xd2, 0x0, 0x10, 0x83, 0xff, \
301 0xca, 0x4d)
302
303#define MAX_CACHE_ERRORS 6
304#define MAX_TLB_ERRORS 6
305#define MAX_BUS_ERRORS 1
306
307/* Definition of version according to SAL spec for logging purposes */
308typedef struct sal_log_revision {
309 u8 minor; /* BCD (0..99) */
310 u8 major; /* BCD (0..99) */
311} sal_log_revision_t;
312
313/* Definition of timestamp according to SAL spec for logging purposes */
314typedef struct sal_log_timestamp {
315 u8 slh_second; /* Second (0..59) */
316 u8 slh_minute; /* Minute (0..59) */
317 u8 slh_hour; /* Hour (0..23) */
318 u8 slh_reserved;
319 u8 slh_day; /* Day (1..31) */
320 u8 slh_month; /* Month (1..12) */
321 u8 slh_year; /* Year (00..99) */
322 u8 slh_century; /* Century (19, 20, 21, ...) */
323} sal_log_timestamp_t;
324
325/* Definition of log record header structures */
326typedef struct sal_log_record_header {
327 u64 id; /* Unique monotonically increasing ID */
328 sal_log_revision_t revision; /* Major and Minor revision of header */
329 u8 severity; /* Error Severity */
330 u8 validation_bits; /* 0: platform_guid, 1: !timestamp */
331 u32 len; /* Length of this error log in bytes */
332 sal_log_timestamp_t timestamp; /* Timestamp */
333 efi_guid_t platform_guid; /* Unique OEM Platform ID */
334} sal_log_record_header_t;
335
336#define sal_log_severity_recoverable 0
337#define sal_log_severity_fatal 1
338#define sal_log_severity_corrected 2
339
340/* Definition of log section header structures */
341typedef struct sal_log_sec_header {
342 efi_guid_t guid; /* Unique Section ID */
343 sal_log_revision_t revision; /* Major and Minor revision of Section */
344 u16 reserved;
345 u32 len; /* Section length */
346} sal_log_section_hdr_t;
347
348typedef struct sal_log_mod_error_info {
349 struct {
350 u64 check_info : 1,
351 requestor_identifier : 1,
352 responder_identifier : 1,
353 target_identifier : 1,
354 precise_ip : 1,
355 reserved : 59;
356 } valid;
357 u64 check_info;
358 u64 requestor_identifier;
359 u64 responder_identifier;
360 u64 target_identifier;
361 u64 precise_ip;
362} sal_log_mod_error_info_t;
363
364typedef struct sal_processor_static_info {
365 struct {
366 u64 minstate : 1,
367 br : 1,
368 cr : 1,
369 ar : 1,
370 rr : 1,
371 fr : 1,
372 reserved : 58;
373 } valid;
374 pal_min_state_area_t min_state_area;
375 u64 br[8];
376 u64 cr[128];
377 u64 ar[128];
378 u64 rr[8];
379 struct ia64_fpreg __attribute__ ((packed)) fr[128];
380} sal_processor_static_info_t;
381
382struct sal_cpuid_info {
383 u64 regs[5];
384 u64 reserved;
385};
386
387typedef struct sal_log_processor_info {
388 sal_log_section_hdr_t header;
389 struct {
390 u64 proc_error_map : 1,
391 proc_state_param : 1,
392 proc_cr_lid : 1,
393 psi_static_struct : 1,
394 num_cache_check : 4,
395 num_tlb_check : 4,
396 num_bus_check : 4,
397 num_reg_file_check : 4,
398 num_ms_check : 4,
399 cpuid_info : 1,
400 reserved1 : 39;
401 } valid;
402 u64 proc_error_map;
403 u64 proc_state_parameter;
404 u64 proc_cr_lid;
405 /*
406 * The rest of this structure consists of variable-length arrays, which can't be
407 * expressed in C.
408 */
409 sal_log_mod_error_info_t info[0];
410 /*
411 * This is what the rest looked like if C supported variable-length arrays:
412 *
413 * sal_log_mod_error_info_t cache_check_info[.valid.num_cache_check];
414 * sal_log_mod_error_info_t tlb_check_info[.valid.num_tlb_check];
415 * sal_log_mod_error_info_t bus_check_info[.valid.num_bus_check];
416 * sal_log_mod_error_info_t reg_file_check_info[.valid.num_reg_file_check];
417 * sal_log_mod_error_info_t ms_check_info[.valid.num_ms_check];
418 * struct sal_cpuid_info cpuid_info;
419 * sal_processor_static_info_t processor_static_info;
420 */
421} sal_log_processor_info_t;
422
423/* Given a sal_log_processor_info_t pointer, return a pointer to the processor_static_info: */
424#define SAL_LPI_PSI_INFO(l) \
425({ sal_log_processor_info_t *_l = (l); \
426 ((sal_processor_static_info_t *) \
427 ((char *) _l->info + ((_l->valid.num_cache_check + _l->valid.num_tlb_check \
428 + _l->valid.num_bus_check + _l->valid.num_reg_file_check \
429 + _l->valid.num_ms_check) * sizeof(sal_log_mod_error_info_t) \
430 + sizeof(struct sal_cpuid_info)))); \
431})
432
433/* platform error log structures */
434
435typedef struct sal_log_mem_dev_err_info {
436 sal_log_section_hdr_t header;
437 struct {
438 u64 error_status : 1,
439 physical_addr : 1,
440 addr_mask : 1,
441 node : 1,
442 card : 1,
443 module : 1,
444 bank : 1,
445 device : 1,
446 row : 1,
447 column : 1,
448 bit_position : 1,
449 requestor_id : 1,
450 responder_id : 1,
451 target_id : 1,
452 bus_spec_data : 1,
453 oem_id : 1,
454 oem_data : 1,
455 reserved : 47;
456 } valid;
457 u64 error_status;
458 u64 physical_addr;
459 u64 addr_mask;
460 u16 node;
461 u16 card;
462 u16 module;
463 u16 bank;
464 u16 device;
465 u16 row;
466 u16 column;
467 u16 bit_position;
468 u64 requestor_id;
469 u64 responder_id;
470 u64 target_id;
471 u64 bus_spec_data;
472 u8 oem_id[16];
473 u8 oem_data[1]; /* Variable length data */
474} sal_log_mem_dev_err_info_t;
475
476typedef struct sal_log_sel_dev_err_info {
477 sal_log_section_hdr_t header;
478 struct {
479 u64 record_id : 1,
480 record_type : 1,
481 generator_id : 1,
482 evm_rev : 1,
483 sensor_type : 1,
484 sensor_num : 1,
485 event_dir : 1,
486 event_data1 : 1,
487 event_data2 : 1,
488 event_data3 : 1,
489 reserved : 54;
490 } valid;
491 u16 record_id;
492 u8 record_type;
493 u8 timestamp[4];
494 u16 generator_id;
495 u8 evm_rev;
496 u8 sensor_type;
497 u8 sensor_num;
498 u8 event_dir;
499 u8 event_data1;
500 u8 event_data2;
501 u8 event_data3;
502} sal_log_sel_dev_err_info_t;
503
504typedef struct sal_log_pci_bus_err_info {
505 sal_log_section_hdr_t header;
506 struct {
507 u64 err_status : 1,
508 err_type : 1,
509 bus_id : 1,
510 bus_address : 1,
511 bus_data : 1,
512 bus_cmd : 1,
513 requestor_id : 1,
514 responder_id : 1,
515 target_id : 1,
516 oem_data : 1,
517 reserved : 54;
518 } valid;
519 u64 err_status;
520 u16 err_type;
521 u16 bus_id;
522 u32 reserved;
523 u64 bus_address;
524 u64 bus_data;
525 u64 bus_cmd;
526 u64 requestor_id;
527 u64 responder_id;
528 u64 target_id;
529 u8 oem_data[1]; /* Variable length data */
530} sal_log_pci_bus_err_info_t;
531
532typedef struct sal_log_smbios_dev_err_info {
533 sal_log_section_hdr_t header;
534 struct {
535 u64 event_type : 1,
536 length : 1,
537 time_stamp : 1,
538 data : 1,
539 reserved1 : 60;
540 } valid;
541 u8 event_type;
542 u8 length;
543 u8 time_stamp[6];
544 u8 data[1]; /* data of variable length, length == slsmb_length */
545} sal_log_smbios_dev_err_info_t;
546
547typedef struct sal_log_pci_comp_err_info {
548 sal_log_section_hdr_t header;
549 struct {
550 u64 err_status : 1,
551 comp_info : 1,
552 num_mem_regs : 1,
553 num_io_regs : 1,
554 reg_data_pairs : 1,
555 oem_data : 1,
556 reserved : 58;
557 } valid;
558 u64 err_status;
559 struct {
560 u16 vendor_id;
561 u16 device_id;
562 u8 class_code[3];
563 u8 func_num;
564 u8 dev_num;
565 u8 bus_num;
566 u8 seg_num;
567 u8 reserved[5];
568 } comp_info;
569 u32 num_mem_regs;
570 u32 num_io_regs;
571 u64 reg_data_pairs[1];
572 /*
573 * array of address/data register pairs is num_mem_regs + num_io_regs elements
574 * long. Each array element consists of a u64 address followed by a u64 data
575 * value. The oem_data array immediately follows the reg_data_pairs array
576 */
577 u8 oem_data[1]; /* Variable length data */
578} sal_log_pci_comp_err_info_t;
579
580typedef struct sal_log_plat_specific_err_info {
581 sal_log_section_hdr_t header;
582 struct {
583 u64 err_status : 1,
584 guid : 1,
585 oem_data : 1,
586 reserved : 61;
587 } valid;
588 u64 err_status;
589 efi_guid_t guid;
590 u8 oem_data[1]; /* platform specific variable length data */
591} sal_log_plat_specific_err_info_t;
592
593typedef struct sal_log_host_ctlr_err_info {
594 sal_log_section_hdr_t header;
595 struct {
596 u64 err_status : 1,
597 requestor_id : 1,
598 responder_id : 1,
599 target_id : 1,
600 bus_spec_data : 1,
601 oem_data : 1,
602 reserved : 58;
603 } valid;
604 u64 err_status;
605 u64 requestor_id;
606 u64 responder_id;
607 u64 target_id;
608 u64 bus_spec_data;
609 u8 oem_data[1]; /* Variable length OEM data */
610} sal_log_host_ctlr_err_info_t;
611
612typedef struct sal_log_plat_bus_err_info {
613 sal_log_section_hdr_t header;
614 struct {
615 u64 err_status : 1,
616 requestor_id : 1,
617 responder_id : 1,
618 target_id : 1,
619 bus_spec_data : 1,
620 oem_data : 1,
621 reserved : 58;
622 } valid;
623 u64 err_status;
624 u64 requestor_id;
625 u64 responder_id;
626 u64 target_id;
627 u64 bus_spec_data;
628 u8 oem_data[1]; /* Variable length OEM data */
629} sal_log_plat_bus_err_info_t;
630
631/* Overall platform error section structure */
632typedef union sal_log_platform_err_info {
633 sal_log_mem_dev_err_info_t mem_dev_err;
634 sal_log_sel_dev_err_info_t sel_dev_err;
635 sal_log_pci_bus_err_info_t pci_bus_err;
636 sal_log_smbios_dev_err_info_t smbios_dev_err;
637 sal_log_pci_comp_err_info_t pci_comp_err;
638 sal_log_plat_specific_err_info_t plat_specific_err;
639 sal_log_host_ctlr_err_info_t host_ctlr_err;
640 sal_log_plat_bus_err_info_t plat_bus_err;
641} sal_log_platform_err_info_t;
642
643/* SAL log over-all, multi-section error record structure (processor+platform) */
644typedef struct err_rec {
645 sal_log_record_header_t sal_elog_header;
646 sal_log_processor_info_t proc_err;
647 sal_log_platform_err_info_t plat_err;
648 u8 oem_data_pad[1024];
649} ia64_err_rec_t;
650
651/*
652 * Now define a couple of inline functions for improved type checking
653 * and convenience.
654 */
655
656extern s64 ia64_sal_cache_flush (u64 cache_type);
657extern void __init check_sal_cache_flush (void);
658
659/* Initialize all the processor and platform level instruction and data caches */
660static inline s64
661ia64_sal_cache_init (void)
662{
663 struct ia64_sal_retval isrv;
664 SAL_CALL(isrv, SAL_CACHE_INIT, 0, 0, 0, 0, 0, 0, 0);
665 return isrv.status;
666}
667
668/*
669 * Clear the processor and platform information logged by SAL with respect to the machine
670 * state at the time of MCA's, INITs, CMCs, or CPEs.
671 */
672static inline s64
673ia64_sal_clear_state_info (u64 sal_info_type)
674{
675 struct ia64_sal_retval isrv;
676 SAL_CALL_REENTRANT(isrv, SAL_CLEAR_STATE_INFO, sal_info_type, 0,
677 0, 0, 0, 0, 0);
678 return isrv.status;
679}
680
681
682/* Get the processor and platform information logged by SAL with respect to the machine
683 * state at the time of the MCAs, INITs, CMCs, or CPEs.
684 */
685static inline u64
686ia64_sal_get_state_info (u64 sal_info_type, u64 *sal_info)
687{
688 struct ia64_sal_retval isrv;
689 SAL_CALL_REENTRANT(isrv, SAL_GET_STATE_INFO, sal_info_type, 0,
690 sal_info, 0, 0, 0, 0);
691 if (isrv.status)
692 return 0;
693
694 return isrv.v0;
695}
696
697/*
698 * Get the maximum size of the information logged by SAL with respect to the machine state
699 * at the time of MCAs, INITs, CMCs, or CPEs.
700 */
701static inline u64
702ia64_sal_get_state_info_size (u64 sal_info_type)
703{
704 struct ia64_sal_retval isrv;
705 SAL_CALL_REENTRANT(isrv, SAL_GET_STATE_INFO_SIZE, sal_info_type, 0,
706 0, 0, 0, 0, 0);
707 if (isrv.status)
708 return 0;
709 return isrv.v0;
710}
711
712/*
713 * Causes the processor to go into a spin loop within SAL where SAL awaits a wakeup from
714 * the monarch processor. Must not lock, because it will not return on any cpu until the
715 * monarch processor sends a wake up.
716 */
717static inline s64
718ia64_sal_mc_rendez (void)
719{
720 struct ia64_sal_retval isrv;
721 SAL_CALL_NOLOCK(isrv, SAL_MC_RENDEZ, 0, 0, 0, 0, 0, 0, 0);
722 return isrv.status;
723}
724
725/*
726 * Allow the OS to specify the interrupt number to be used by SAL to interrupt OS during
727 * the machine check rendezvous sequence as well as the mechanism to wake up the
728 * non-monarch processor at the end of machine check processing.
729 * Returns the complete ia64_sal_retval because some calls return more than just a status
730 * value.
731 */
732static inline struct ia64_sal_retval
733ia64_sal_mc_set_params (u64 param_type, u64 i_or_m, u64 i_or_m_val, u64 timeout, u64 rz_always)
734{
735 struct ia64_sal_retval isrv;
736 SAL_CALL(isrv, SAL_MC_SET_PARAMS, param_type, i_or_m, i_or_m_val,
737 timeout, rz_always, 0, 0);
738 return isrv;
739}
740
741/* Read from PCI configuration space */
742static inline s64
743ia64_sal_pci_config_read (u64 pci_config_addr, int type, u64 size, u64 *value)
744{
745 struct ia64_sal_retval isrv;
746 SAL_CALL(isrv, SAL_PCI_CONFIG_READ, pci_config_addr, size, type, 0, 0, 0, 0);
747 if (value)
748 *value = isrv.v0;
749 return isrv.status;
750}
751
752/* Write to PCI configuration space */
753static inline s64
754ia64_sal_pci_config_write (u64 pci_config_addr, int type, u64 size, u64 value)
755{
756 struct ia64_sal_retval isrv;
757 SAL_CALL(isrv, SAL_PCI_CONFIG_WRITE, pci_config_addr, size, value,
758 type, 0, 0, 0);
759 return isrv.status;
760}
761
762/*
763 * Register physical addresses of locations needed by SAL when SAL procedures are invoked
764 * in virtual mode.
765 */
766static inline s64
767ia64_sal_register_physical_addr (u64 phys_entry, u64 phys_addr)
768{
769 struct ia64_sal_retval isrv;
770 SAL_CALL(isrv, SAL_REGISTER_PHYSICAL_ADDR, phys_entry, phys_addr,
771 0, 0, 0, 0, 0);
772 return isrv.status;
773}
774
775/*
776 * Register software dependent code locations within SAL. These locations are handlers or
777 * entry points where SAL will pass control for the specified event. These event handlers
778 * are for the bott rendezvous, MCAs and INIT scenarios.
779 */
780static inline s64
781ia64_sal_set_vectors (u64 vector_type,
782 u64 handler_addr1, u64 gp1, u64 handler_len1,
783 u64 handler_addr2, u64 gp2, u64 handler_len2)
784{
785 struct ia64_sal_retval isrv;
786 SAL_CALL(isrv, SAL_SET_VECTORS, vector_type,
787 handler_addr1, gp1, handler_len1,
788 handler_addr2, gp2, handler_len2);
789
790 return isrv.status;
791}
792
793/* Update the contents of PAL block in the non-volatile storage device */
794static inline s64
795ia64_sal_update_pal (u64 param_buf, u64 scratch_buf, u64 scratch_buf_size,
796 u64 *error_code, u64 *scratch_buf_size_needed)
797{
798 struct ia64_sal_retval isrv;
799 SAL_CALL(isrv, SAL_UPDATE_PAL, param_buf, scratch_buf, scratch_buf_size,
800 0, 0, 0, 0);
801 if (error_code)
802 *error_code = isrv.v0;
803 if (scratch_buf_size_needed)
804 *scratch_buf_size_needed = isrv.v1;
805 return isrv.status;
806}
807
808/* Get physical processor die mapping in the platform. */
809static inline s64
810ia64_sal_physical_id_info(u16 *splid)
811{
812 struct ia64_sal_retval isrv;
813
814 if (sal_revision < SAL_VERSION_CODE(3,2))
815 return -1;
816
817 SAL_CALL(isrv, SAL_PHYSICAL_ID_INFO, 0, 0, 0, 0, 0, 0, 0);
818 if (splid)
819 *splid = isrv.v0;
820 return isrv.status;
821}
822
823extern unsigned long sal_platform_features;
824
825extern int (*salinfo_platform_oemdata)(const u8 *, u8 **, u64 *);
826
827struct sal_ret_values {
828 long r8; long r9; long r10; long r11;
829};
830
831#define IA64_SAL_OEMFUNC_MIN 0x02000000
832#define IA64_SAL_OEMFUNC_MAX 0x03ffffff
833
834extern int ia64_sal_oemcall(struct ia64_sal_retval *, u64, u64, u64, u64, u64,
835 u64, u64, u64);
836extern int ia64_sal_oemcall_nolock(struct ia64_sal_retval *, u64, u64, u64,
837 u64, u64, u64, u64, u64);
838extern int ia64_sal_oemcall_reentrant(struct ia64_sal_retval *, u64, u64, u64,
839 u64, u64, u64, u64, u64);
840extern long
841ia64_sal_freq_base (unsigned long which, unsigned long *ticks_per_second,
842 unsigned long *drift_info);
843#ifdef CONFIG_HOTPLUG_CPU
844/*
845 * System Abstraction Layer Specification
846 * Section 3.2.5.1: OS_BOOT_RENDEZ to SAL return State.
847 * Note: region regs are stored first in head.S _start. Hence they must
848 * stay up front.
849 */
850struct sal_to_os_boot {
851 u64 rr[8]; /* Region Registers */
852 u64 br[6]; /* br0:
853 * return addr into SAL boot rendez routine */
854 u64 gr1; /* SAL:GP */
855 u64 gr12; /* SAL:SP */
856 u64 gr13; /* SAL: Task Pointer */
857 u64 fpsr;
858 u64 pfs;
859 u64 rnat;
860 u64 unat;
861 u64 bspstore;
862 u64 dcr; /* Default Control Register */
863 u64 iva;
864 u64 pta;
865 u64 itv;
866 u64 pmv;
867 u64 cmcv;
868 u64 lrr[2];
869 u64 gr[4];
870 u64 pr; /* Predicate registers */
871 u64 lc; /* Loop Count */
872 struct ia64_fpreg fp[20];
873};
874
875/*
876 * Global array allocated for NR_CPUS at boot time
877 */
878extern struct sal_to_os_boot sal_boot_rendez_state[NR_CPUS];
879
880extern void ia64_jump_to_sal(struct sal_to_os_boot *);
881#endif
882
883extern void ia64_sal_handler_init(void *entry_point, void *gpval);
884
885#define PALO_MAX_TLB_PURGES 0xFFFF
886#define PALO_SIG "PALO"
887
888struct palo_table {
889 u8 signature[4]; /* Should be "PALO" */
890 u32 length;
891 u8 minor_revision;
892 u8 major_revision;
893 u8 checksum;
894 u8 reserved1[5];
895 u16 max_tlb_purges;
896 u8 reserved2[6];
897};
898
899#define NPTCG_FROM_PAL 0
900#define NPTCG_FROM_PALO 1
901#define NPTCG_FROM_KERNEL_PARAMETER 2
902
903#endif /* __ASSEMBLY__ */
904
905#endif /* _ASM_IA64_SAL_H */
diff --git a/include/asm-ia64/scatterlist.h b/include/asm-ia64/scatterlist.h
deleted file mode 100644
index d6f57874041..00000000000
--- a/include/asm-ia64/scatterlist.h
+++ /dev/null
@@ -1,38 +0,0 @@
1#ifndef _ASM_IA64_SCATTERLIST_H
2#define _ASM_IA64_SCATTERLIST_H
3
4/*
5 * Modified 1998-1999, 2001-2002, 2004
6 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
7 */
8
9#include <asm/types.h>
10
11struct scatterlist {
12#ifdef CONFIG_DEBUG_SG
13 unsigned long sg_magic;
14#endif
15 unsigned long page_link;
16 unsigned int offset;
17 unsigned int length; /* buffer length */
18
19 dma_addr_t dma_address;
20 unsigned int dma_length;
21};
22
23/*
24 * It used to be that ISA_DMA_THRESHOLD had something to do with the
25 * DMA-limits of ISA-devices. Nowadays, its only remaining use (apart
26 * from the aha1542.c driver, which isn't 64-bit clean anyhow) is to
27 * tell the block-layer (via BLK_BOUNCE_ISA) what the max. physical
28 * address of a page is that is allocated with GFP_DMA. On IA-64,
29 * that's 4GB - 1.
30 */
31#define ISA_DMA_THRESHOLD 0xffffffff
32
33#define sg_dma_len(sg) ((sg)->dma_length)
34#define sg_dma_address(sg) ((sg)->dma_address)
35
36#define ARCH_HAS_SG_CHAIN
37
38#endif /* _ASM_IA64_SCATTERLIST_H */
diff --git a/include/asm-ia64/sections.h b/include/asm-ia64/sections.h
deleted file mode 100644
index 7286e4a9fe8..00000000000
--- a/include/asm-ia64/sections.h
+++ /dev/null
@@ -1,25 +0,0 @@
1#ifndef _ASM_IA64_SECTIONS_H
2#define _ASM_IA64_SECTIONS_H
3
4/*
5 * Copyright (C) 1998-2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 */
8
9#include <asm-generic/sections.h>
10
11extern char __per_cpu_start[], __per_cpu_end[], __phys_per_cpu_start[];
12extern char __start___vtop_patchlist[], __end___vtop_patchlist[];
13extern char __start___rse_patchlist[], __end___rse_patchlist[];
14extern char __start___mckinley_e9_bundles[], __end___mckinley_e9_bundles[];
15extern char __start___phys_stack_reg_patchlist[], __end___phys_stack_reg_patchlist[];
16extern char __start_gate_section[];
17extern char __start_gate_mckinley_e9_patchlist[], __end_gate_mckinley_e9_patchlist[];
18extern char __start_gate_vtop_patchlist[], __end_gate_vtop_patchlist[];
19extern char __start_gate_fsyscall_patchlist[], __end_gate_fsyscall_patchlist[];
20extern char __start_gate_brl_fsys_bubble_down_patchlist[], __end_gate_brl_fsys_bubble_down_patchlist[];
21extern char __start_unwind[], __end_unwind[];
22extern char __start_ivt_text[], __end_ivt_text[];
23
24#endif /* _ASM_IA64_SECTIONS_H */
25
diff --git a/include/asm-ia64/segment.h b/include/asm-ia64/segment.h
deleted file mode 100644
index b89e2b3d648..00000000000
--- a/include/asm-ia64/segment.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _ASM_IA64_SEGMENT_H
2#define _ASM_IA64_SEGMENT_H
3
4/* Only here because we have some old header files that expect it.. */
5
6#endif /* _ASM_IA64_SEGMENT_H */
diff --git a/include/asm-ia64/sembuf.h b/include/asm-ia64/sembuf.h
deleted file mode 100644
index 1340fbc04d3..00000000000
--- a/include/asm-ia64/sembuf.h
+++ /dev/null
@@ -1,22 +0,0 @@
1#ifndef _ASM_IA64_SEMBUF_H
2#define _ASM_IA64_SEMBUF_H
3
4/*
5 * The semid64_ds structure for IA-64 architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 2 miscellaneous 64-bit values
11 */
12
13struct semid64_ds {
14 struct ipc64_perm sem_perm; /* permissions .. see ipc.h */
15 __kernel_time_t sem_otime; /* last semop time */
16 __kernel_time_t sem_ctime; /* last change time */
17 unsigned long sem_nsems; /* no. of semaphores in array */
18 unsigned long __unused1;
19 unsigned long __unused2;
20};
21
22#endif /* _ASM_IA64_SEMBUF_H */
diff --git a/include/asm-ia64/serial.h b/include/asm-ia64/serial.h
deleted file mode 100644
index 0c7a2f3dcf1..00000000000
--- a/include/asm-ia64/serial.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * include/asm-ia64/serial.h
3 *
4 * Derived from the i386 version.
5 */
6
7/*
8 * This assumes you have a 1.8432 MHz clock for your UART.
9 *
10 * It'd be nice if someone built a serial card with a 24.576 MHz
11 * clock, since the 16550A is capable of handling a top speed of 1.5
12 * megabits/second; but this requires the faster clock.
13 */
14#define BASE_BAUD ( 1843200 / 16 )
15
16/*
17 * All legacy serial ports should be enumerated via ACPI namespace, so
18 * we need not list them here.
19 */
diff --git a/include/asm-ia64/setup.h b/include/asm-ia64/setup.h
deleted file mode 100644
index 4399a44355b..00000000000
--- a/include/asm-ia64/setup.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef __IA64_SETUP_H
2#define __IA64_SETUP_H
3
4#define COMMAND_LINE_SIZE 2048
5
6#endif
diff --git a/include/asm-ia64/shmbuf.h b/include/asm-ia64/shmbuf.h
deleted file mode 100644
index 585002a77ac..00000000000
--- a/include/asm-ia64/shmbuf.h
+++ /dev/null
@@ -1,38 +0,0 @@
1#ifndef _ASM_IA64_SHMBUF_H
2#define _ASM_IA64_SHMBUF_H
3
4/*
5 * The shmid64_ds structure for IA-64 architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 2 miscellaneous 64-bit values
11 */
12
13struct shmid64_ds {
14 struct ipc64_perm shm_perm; /* operation perms */
15 size_t shm_segsz; /* size of segment (bytes) */
16 __kernel_time_t shm_atime; /* last attach time */
17 __kernel_time_t shm_dtime; /* last detach time */
18 __kernel_time_t shm_ctime; /* last change time */
19 __kernel_pid_t shm_cpid; /* pid of creator */
20 __kernel_pid_t shm_lpid; /* pid of last operator */
21 unsigned long shm_nattch; /* no. of current attaches */
22 unsigned long __unused1;
23 unsigned long __unused2;
24};
25
26struct shminfo64 {
27 unsigned long shmmax;
28 unsigned long shmmin;
29 unsigned long shmmni;
30 unsigned long shmseg;
31 unsigned long shmall;
32 unsigned long __unused1;
33 unsigned long __unused2;
34 unsigned long __unused3;
35 unsigned long __unused4;
36};
37
38#endif /* _ASM_IA64_SHMBUF_H */
diff --git a/include/asm-ia64/shmparam.h b/include/asm-ia64/shmparam.h
deleted file mode 100644
index d07508dc54a..00000000000
--- a/include/asm-ia64/shmparam.h
+++ /dev/null
@@ -1,12 +0,0 @@
1#ifndef _ASM_IA64_SHMPARAM_H
2#define _ASM_IA64_SHMPARAM_H
3
4/*
5 * SHMLBA controls minimum alignment at which shared memory segments
6 * get attached. The IA-64 architecture says that there may be a
7 * performance degradation when there are virtual aliases within 1MB.
8 * To reduce the chance of this, we set SHMLBA to 1MB. --davidm 00/12/20
9 */
10#define SHMLBA (1024*1024)
11
12#endif /* _ASM_IA64_SHMPARAM_H */
diff --git a/include/asm-ia64/sigcontext.h b/include/asm-ia64/sigcontext.h
deleted file mode 100644
index 57ff777bcc4..00000000000
--- a/include/asm-ia64/sigcontext.h
+++ /dev/null
@@ -1,70 +0,0 @@
1#ifndef _ASM_IA64_SIGCONTEXT_H
2#define _ASM_IA64_SIGCONTEXT_H
3
4/*
5 * Copyright (C) 1998, 1999, 2001 Hewlett-Packard Co
6 * Copyright (C) 1998, 1999, 2001 David Mosberger-Tang <davidm@hpl.hp.com>
7 */
8
9#include <asm/fpu.h>
10
11#define IA64_SC_FLAG_ONSTACK_BIT 0 /* is handler running on signal stack? */
12#define IA64_SC_FLAG_IN_SYSCALL_BIT 1 /* did signal interrupt a syscall? */
13#define IA64_SC_FLAG_FPH_VALID_BIT 2 /* is state in f[32]-f[127] valid? */
14
15#define IA64_SC_FLAG_ONSTACK (1 << IA64_SC_FLAG_ONSTACK_BIT)
16#define IA64_SC_FLAG_IN_SYSCALL (1 << IA64_SC_FLAG_IN_SYSCALL_BIT)
17#define IA64_SC_FLAG_FPH_VALID (1 << IA64_SC_FLAG_FPH_VALID_BIT)
18
19# ifndef __ASSEMBLY__
20
21/*
22 * Note on handling of register backing store: sc_ar_bsp contains the address that would
23 * be found in ar.bsp after executing a "cover" instruction the context in which the
24 * signal was raised. If signal delivery required switching to an alternate signal stack
25 * (sc_rbs_base is not NULL), the "dirty" partition (as it would exist after executing the
26 * imaginary "cover" instruction) is backed by the *alternate* signal stack, not the
27 * original one. In this case, sc_rbs_base contains the base address of the new register
28 * backing store. The number of registers in the dirty partition can be calculated as:
29 *
30 * ndirty = ia64_rse_num_regs(sc_rbs_base, sc_rbs_base + (sc_loadrs >> 16))
31 *
32 */
33
34struct sigcontext {
35 unsigned long sc_flags; /* see manifest constants above */
36 unsigned long sc_nat; /* bit i == 1 iff scratch reg gr[i] is a NaT */
37 stack_t sc_stack; /* previously active stack */
38
39 unsigned long sc_ip; /* instruction pointer */
40 unsigned long sc_cfm; /* current frame marker */
41 unsigned long sc_um; /* user mask bits */
42 unsigned long sc_ar_rsc; /* register stack configuration register */
43 unsigned long sc_ar_bsp; /* backing store pointer */
44 unsigned long sc_ar_rnat; /* RSE NaT collection register */
45 unsigned long sc_ar_ccv; /* compare and exchange compare value register */
46 unsigned long sc_ar_unat; /* ar.unat of interrupted context */
47 unsigned long sc_ar_fpsr; /* floating-point status register */
48 unsigned long sc_ar_pfs; /* previous function state */
49 unsigned long sc_ar_lc; /* loop count register */
50 unsigned long sc_pr; /* predicate registers */
51 unsigned long sc_br[8]; /* branch registers */
52 /* Note: sc_gr[0] is used as the "uc_link" member of ucontext_t */
53 unsigned long sc_gr[32]; /* general registers (static partition) */
54 struct ia64_fpreg sc_fr[128]; /* floating-point registers */
55
56 unsigned long sc_rbs_base; /* NULL or new base of sighandler's rbs */
57 unsigned long sc_loadrs; /* see description above */
58
59 unsigned long sc_ar25; /* cmp8xchg16 uses this */
60 unsigned long sc_ar26; /* rsvd for scratch use */
61 unsigned long sc_rsvd[12]; /* reserved for future use */
62 /*
63 * The mask must come last so we can increase _NSIG_WORDS
64 * without breaking binary compatibility.
65 */
66 sigset_t sc_mask; /* signal mask to restore after handler returns */
67};
68
69# endif /* __ASSEMBLY__ */
70#endif /* _ASM_IA64_SIGCONTEXT_H */
diff --git a/include/asm-ia64/siginfo.h b/include/asm-ia64/siginfo.h
deleted file mode 100644
index 9294e4b0c8b..00000000000
--- a/include/asm-ia64/siginfo.h
+++ /dev/null
@@ -1,139 +0,0 @@
1#ifndef _ASM_IA64_SIGINFO_H
2#define _ASM_IA64_SIGINFO_H
3
4/*
5 * Based on <asm-i386/siginfo.h>.
6 *
7 * Modified 1998-2002
8 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
9 */
10
11#define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
12
13#define HAVE_ARCH_SIGINFO_T
14#define HAVE_ARCH_COPY_SIGINFO
15#define HAVE_ARCH_COPY_SIGINFO_TO_USER
16
17#include <asm-generic/siginfo.h>
18
19typedef struct siginfo {
20 int si_signo;
21 int si_errno;
22 int si_code;
23 int __pad0;
24
25 union {
26 int _pad[SI_PAD_SIZE];
27
28 /* kill() */
29 struct {
30 pid_t _pid; /* sender's pid */
31 uid_t _uid; /* sender's uid */
32 } _kill;
33
34 /* POSIX.1b timers */
35 struct {
36 timer_t _tid; /* timer id */
37 int _overrun; /* overrun count */
38 char _pad[sizeof(__ARCH_SI_UID_T) - sizeof(int)];
39 sigval_t _sigval; /* must overlay ._rt._sigval! */
40 int _sys_private; /* not to be passed to user */
41 } _timer;
42
43 /* POSIX.1b signals */
44 struct {
45 pid_t _pid; /* sender's pid */
46 uid_t _uid; /* sender's uid */
47 sigval_t _sigval;
48 } _rt;
49
50 /* SIGCHLD */
51 struct {
52 pid_t _pid; /* which child */
53 uid_t _uid; /* sender's uid */
54 int _status; /* exit code */
55 clock_t _utime;
56 clock_t _stime;
57 } _sigchld;
58
59 /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
60 struct {
61 void __user *_addr; /* faulting insn/memory ref. */
62 int _imm; /* immediate value for "break" */
63 unsigned int _flags; /* see below */
64 unsigned long _isr; /* isr */
65 } _sigfault;
66
67 /* SIGPOLL */
68 struct {
69 long _band; /* POLL_IN, POLL_OUT, POLL_MSG (XPG requires a "long") */
70 int _fd;
71 } _sigpoll;
72 } _sifields;
73} siginfo_t;
74
75#define si_imm _sifields._sigfault._imm /* as per UNIX SysV ABI spec */
76#define si_flags _sifields._sigfault._flags
77/*
78 * si_isr is valid for SIGILL, SIGFPE, SIGSEGV, SIGBUS, and SIGTRAP provided that
79 * si_code is non-zero and __ISR_VALID is set in si_flags.
80 */
81#define si_isr _sifields._sigfault._isr
82
83/*
84 * Flag values for si_flags:
85 */
86#define __ISR_VALID_BIT 0
87#define __ISR_VALID (1 << __ISR_VALID_BIT)
88
89/*
90 * SIGILL si_codes
91 */
92#define ILL_BADIADDR (__SI_FAULT|9) /* unimplemented instruction address */
93#define __ILL_BREAK (__SI_FAULT|10) /* illegal break */
94#define __ILL_BNDMOD (__SI_FAULT|11) /* bundle-update (modification) in progress */
95#undef NSIGILL
96#define NSIGILL 11
97
98/*
99 * SIGFPE si_codes
100 */
101#define __FPE_DECOVF (__SI_FAULT|9) /* decimal overflow */
102#define __FPE_DECDIV (__SI_FAULT|10) /* decimal division by zero */
103#define __FPE_DECERR (__SI_FAULT|11) /* packed decimal error */
104#define __FPE_INVASC (__SI_FAULT|12) /* invalid ASCII digit */
105#define __FPE_INVDEC (__SI_FAULT|13) /* invalid decimal digit */
106#undef NSIGFPE
107#define NSIGFPE 13
108
109/*
110 * SIGSEGV si_codes
111 */
112#define __SEGV_PSTKOVF (__SI_FAULT|3) /* paragraph stack overflow */
113#undef NSIGSEGV
114#define NSIGSEGV 3
115
116/*
117 * SIGTRAP si_codes
118 */
119#define TRAP_BRANCH (__SI_FAULT|3) /* process taken branch trap */
120#define TRAP_HWBKPT (__SI_FAULT|4) /* hardware breakpoint or watchpoint */
121#undef NSIGTRAP
122#define NSIGTRAP 4
123
124#ifdef __KERNEL__
125#include <linux/string.h>
126
127static inline void
128copy_siginfo (siginfo_t *to, siginfo_t *from)
129{
130 if (from->si_code < 0)
131 memcpy(to, from, sizeof(siginfo_t));
132 else
133 /* _sigchld is currently the largest know union member */
134 memcpy(to, from, 4*sizeof(int) + sizeof(from->_sifields._sigchld));
135}
136
137#endif /* __KERNEL__ */
138
139#endif /* _ASM_IA64_SIGINFO_H */
diff --git a/include/asm-ia64/signal.h b/include/asm-ia64/signal.h
deleted file mode 100644
index 4f5ca5643cb..00000000000
--- a/include/asm-ia64/signal.h
+++ /dev/null
@@ -1,160 +0,0 @@
1#ifndef _ASM_IA64_SIGNAL_H
2#define _ASM_IA64_SIGNAL_H
3
4/*
5 * Modified 1998-2001, 2003
6 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
7 *
8 * Unfortunately, this file is being included by bits/signal.h in
9 * glibc-2.x. Hence the #ifdef __KERNEL__ ugliness.
10 */
11
12#define SIGHUP 1
13#define SIGINT 2
14#define SIGQUIT 3
15#define SIGILL 4
16#define SIGTRAP 5
17#define SIGABRT 6
18#define SIGIOT 6
19#define SIGBUS 7
20#define SIGFPE 8
21#define SIGKILL 9
22#define SIGUSR1 10
23#define SIGSEGV 11
24#define SIGUSR2 12
25#define SIGPIPE 13
26#define SIGALRM 14
27#define SIGTERM 15
28#define SIGSTKFLT 16
29#define SIGCHLD 17
30#define SIGCONT 18
31#define SIGSTOP 19
32#define SIGTSTP 20
33#define SIGTTIN 21
34#define SIGTTOU 22
35#define SIGURG 23
36#define SIGXCPU 24
37#define SIGXFSZ 25
38#define SIGVTALRM 26
39#define SIGPROF 27
40#define SIGWINCH 28
41#define SIGIO 29
42#define SIGPOLL SIGIO
43/*
44#define SIGLOST 29
45*/
46#define SIGPWR 30
47#define SIGSYS 31
48/* signal 31 is no longer "unused", but the SIGUNUSED macro remains for backwards compatibility */
49#define SIGUNUSED 31
50
51/* These should not be considered constants from userland. */
52#define SIGRTMIN 32
53#define SIGRTMAX _NSIG
54
55/*
56 * SA_FLAGS values:
57 *
58 * SA_ONSTACK indicates that a registered stack_t will be used.
59 * SA_RESTART flag to get restarting signals (which were the default long ago)
60 * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
61 * SA_RESETHAND clears the handler when the signal is delivered.
62 * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
63 * SA_NODEFER prevents the current signal from being masked in the handler.
64 *
65 * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
66 * Unix names RESETHAND and NODEFER respectively.
67 */
68#define SA_NOCLDSTOP 0x00000001
69#define SA_NOCLDWAIT 0x00000002
70#define SA_SIGINFO 0x00000004
71#define SA_ONSTACK 0x08000000
72#define SA_RESTART 0x10000000
73#define SA_NODEFER 0x40000000
74#define SA_RESETHAND 0x80000000
75
76#define SA_NOMASK SA_NODEFER
77#define SA_ONESHOT SA_RESETHAND
78
79#define SA_RESTORER 0x04000000
80
81/*
82 * sigaltstack controls
83 */
84#define SS_ONSTACK 1
85#define SS_DISABLE 2
86
87/*
88 * The minimum stack size needs to be fairly large because we want to
89 * be sure that an app compiled for today's CPUs will continue to run
90 * on all future CPU models. The CPU model matters because the signal
91 * frame needs to have space for the complete machine state, including
92 * all physical stacked registers. The number of physical stacked
93 * registers is CPU model dependent, but given that the width of
94 * ar.rsc.loadrs is 14 bits, we can assume that they'll never take up
95 * more than 16KB of space.
96 */
97#if 1
98 /*
99 * This is a stupid typo: the value was _meant_ to be 131072 (0x20000), but I typed it
100 * in wrong. ;-( To preserve backwards compatibility, we leave the kernel at the
101 * incorrect value and fix libc only.
102 */
103# define MINSIGSTKSZ 131027 /* min. stack size for sigaltstack() */
104#else
105# define MINSIGSTKSZ 131072 /* min. stack size for sigaltstack() */
106#endif
107#define SIGSTKSZ 262144 /* default stack size for sigaltstack() */
108
109#ifdef __KERNEL__
110
111#define _NSIG 64
112#define _NSIG_BPW 64
113#define _NSIG_WORDS (_NSIG / _NSIG_BPW)
114
115#endif /* __KERNEL__ */
116
117#include <asm-generic/signal.h>
118
119# ifndef __ASSEMBLY__
120
121# include <linux/types.h>
122
123/* Avoid too many header ordering problems. */
124struct siginfo;
125
126typedef struct sigaltstack {
127 void __user *ss_sp;
128 int ss_flags;
129 size_t ss_size;
130} stack_t;
131
132#ifdef __KERNEL__
133
134/* Most things should be clean enough to redefine this at will, if care
135 is taken to make libc match. */
136
137typedef unsigned long old_sigset_t;
138
139typedef struct {
140 unsigned long sig[_NSIG_WORDS];
141} sigset_t;
142
143struct sigaction {
144 __sighandler_t sa_handler;
145 unsigned long sa_flags;
146 sigset_t sa_mask; /* mask last for extensibility */
147};
148
149struct k_sigaction {
150 struct sigaction sa;
151};
152
153# include <asm/sigcontext.h>
154
155#define ptrace_signal_deliver(regs, cookie) do { } while (0)
156
157#endif /* __KERNEL__ */
158
159# endif /* !__ASSEMBLY__ */
160#endif /* _ASM_IA64_SIGNAL_H */
diff --git a/include/asm-ia64/smp.h b/include/asm-ia64/smp.h
deleted file mode 100644
index 12d96e0cd51..00000000000
--- a/include/asm-ia64/smp.h
+++ /dev/null
@@ -1,138 +0,0 @@
1/*
2 * SMP Support
3 *
4 * Copyright (C) 1999 VA Linux Systems
5 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
6 * (c) Copyright 2001-2003, 2005 Hewlett-Packard Development Company, L.P.
7 * David Mosberger-Tang <davidm@hpl.hp.com>
8 * Bjorn Helgaas <bjorn.helgaas@hp.com>
9 */
10#ifndef _ASM_IA64_SMP_H
11#define _ASM_IA64_SMP_H
12
13#include <linux/init.h>
14#include <linux/threads.h>
15#include <linux/kernel.h>
16#include <linux/cpumask.h>
17#include <linux/bitops.h>
18#include <linux/irqreturn.h>
19
20#include <asm/io.h>
21#include <asm/param.h>
22#include <asm/processor.h>
23#include <asm/ptrace.h>
24
25static inline unsigned int
26ia64_get_lid (void)
27{
28 union {
29 struct {
30 unsigned long reserved : 16;
31 unsigned long eid : 8;
32 unsigned long id : 8;
33 unsigned long ignored : 32;
34 } f;
35 unsigned long bits;
36 } lid;
37
38 lid.bits = ia64_getreg(_IA64_REG_CR_LID);
39 return lid.f.id << 8 | lid.f.eid;
40}
41
42#define hard_smp_processor_id() ia64_get_lid()
43
44#ifdef CONFIG_SMP
45
46#define XTP_OFFSET 0x1e0008
47
48#define SMP_IRQ_REDIRECTION (1 << 0)
49#define SMP_IPI_REDIRECTION (1 << 1)
50
51#define raw_smp_processor_id() (current_thread_info()->cpu)
52
53extern struct smp_boot_data {
54 int cpu_count;
55 int cpu_phys_id[NR_CPUS];
56} smp_boot_data __initdata;
57
58extern char no_int_routing __devinitdata;
59
60extern cpumask_t cpu_online_map;
61extern cpumask_t cpu_core_map[NR_CPUS];
62DECLARE_PER_CPU(cpumask_t, cpu_sibling_map);
63extern int smp_num_siblings;
64extern void __iomem *ipi_base_addr;
65extern unsigned char smp_int_redirect;
66
67extern volatile int ia64_cpu_to_sapicid[];
68#define cpu_physical_id(i) ia64_cpu_to_sapicid[i]
69
70extern unsigned long ap_wakeup_vector;
71
72/*
73 * Function to map hard smp processor id to logical id. Slow, so don't use this in
74 * performance-critical code.
75 */
76static inline int
77cpu_logical_id (int cpuid)
78{
79 int i;
80
81 for (i = 0; i < NR_CPUS; ++i)
82 if (cpu_physical_id(i) == cpuid)
83 break;
84 return i;
85}
86
87/*
88 * XTP control functions:
89 * min_xtp : route all interrupts to this CPU
90 * normal_xtp: nominal XTP value
91 * max_xtp : never deliver interrupts to this CPU.
92 */
93
94static inline void
95min_xtp (void)
96{
97 if (smp_int_redirect & SMP_IRQ_REDIRECTION)
98 writeb(0x00, ipi_base_addr + XTP_OFFSET); /* XTP to min */
99}
100
101static inline void
102normal_xtp (void)
103{
104 if (smp_int_redirect & SMP_IRQ_REDIRECTION)
105 writeb(0x08, ipi_base_addr + XTP_OFFSET); /* XTP normal */
106}
107
108static inline void
109max_xtp (void)
110{
111 if (smp_int_redirect & SMP_IRQ_REDIRECTION)
112 writeb(0x0f, ipi_base_addr + XTP_OFFSET); /* Set XTP to max */
113}
114
115/* Upping and downing of CPUs */
116extern int __cpu_disable (void);
117extern void __cpu_die (unsigned int cpu);
118extern void cpu_die (void) __attribute__ ((noreturn));
119extern void __init smp_build_cpu_map(void);
120
121extern void __init init_smp_config (void);
122extern void smp_do_timer (struct pt_regs *regs);
123
124extern irqreturn_t handle_IPI(int irq, void *dev_id);
125extern void smp_send_reschedule (int cpu);
126extern void identify_siblings (struct cpuinfo_ia64 *);
127extern int is_multithreading_enabled(void);
128
129extern void arch_send_call_function_single_ipi(int cpu);
130extern void arch_send_call_function_ipi(cpumask_t mask);
131
132#else /* CONFIG_SMP */
133
134#define cpu_logical_id(i) 0
135#define cpu_physical_id(i) ia64_get_lid()
136
137#endif /* CONFIG_SMP */
138#endif /* _ASM_IA64_SMP_H */
diff --git a/include/asm-ia64/sn/acpi.h b/include/asm-ia64/sn/acpi.h
deleted file mode 100644
index 9ce2801cbd5..00000000000
--- a/include/asm-ia64/sn/acpi.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2006 Silicon Graphics, Inc. All rights reserved.
7 */
8
9#ifndef _ASM_IA64_SN_ACPI_H
10#define _ASM_IA64_SN_ACPI_H
11
12#include "acpi/acglobal.h"
13
14extern int sn_acpi_rev;
15#define SN_ACPI_BASE_SUPPORT() (sn_acpi_rev >= 0x20101)
16
17#endif /* _ASM_IA64_SN_ACPI_H */
diff --git a/include/asm-ia64/sn/addrs.h b/include/asm-ia64/sn/addrs.h
deleted file mode 100644
index e715c794b18..00000000000
--- a/include/asm-ia64/sn/addrs.h
+++ /dev/null
@@ -1,299 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (c) 1992-1999,2001-2005 Silicon Graphics, Inc. All rights reserved.
7 */
8
9#ifndef _ASM_IA64_SN_ADDRS_H
10#define _ASM_IA64_SN_ADDRS_H
11
12#include <asm/percpu.h>
13#include <asm/sn/types.h>
14#include <asm/sn/arch.h>
15#include <asm/sn/pda.h>
16
17/*
18 * Memory/SHUB Address Format:
19 * +-+---------+--+--------------+
20 * |0| NASID |AS| NodeOffset |
21 * +-+---------+--+--------------+
22 *
23 * NASID: (low NASID bit is 0) Memory and SHUB MMRs
24 * AS: 2-bit Address Space Identifier. Used only if low NASID bit is 0
25 * 00: Local Resources and MMR space
26 * Top bit of NodeOffset
27 * 0: Local resources space
28 * node id:
29 * 0: IA64/NT compatibility space
30 * 2: Local MMR Space
31 * 4: Local memory, regardless of local node id
32 * 1: Global MMR space
33 * 01: GET space.
34 * 10: AMO space.
35 * 11: Cacheable memory space.
36 *
37 * NodeOffset: byte offset
38 *
39 *
40 * TIO address format:
41 * +-+----------+--+--------------+
42 * |0| NASID |AS| Nodeoffset |
43 * +-+----------+--+--------------+
44 *
45 * NASID: (low NASID bit is 1) TIO
46 * AS: 2-bit Chiplet Identifier
47 * 00: TIO LB (Indicates TIO MMR access.)
48 * 01: TIO ICE (indicates coretalk space access.)
49 *
50 * NodeOffset: top bit must be set.
51 *
52 *
53 * Note that in both of the above address formats, the low
54 * NASID bit indicates if the reference is to the SHUB or TIO MMRs.
55 */
56
57
58/*
59 * Define basic shift & mask constants for manipulating NASIDs and AS values.
60 */
61#define NASID_BITMASK (sn_hub_info->nasid_bitmask)
62#define NASID_SHIFT (sn_hub_info->nasid_shift)
63#define AS_SHIFT (sn_hub_info->as_shift)
64#define AS_BITMASK 0x3UL
65
66#define NASID_MASK ((u64)NASID_BITMASK << NASID_SHIFT)
67#define AS_MASK ((u64)AS_BITMASK << AS_SHIFT)
68
69
70/*
71 * AS values. These are the same on both SHUB1 & SHUB2.
72 */
73#define AS_GET_VAL 1UL
74#define AS_AMO_VAL 2UL
75#define AS_CAC_VAL 3UL
76#define AS_GET_SPACE (AS_GET_VAL << AS_SHIFT)
77#define AS_AMO_SPACE (AS_AMO_VAL << AS_SHIFT)
78#define AS_CAC_SPACE (AS_CAC_VAL << AS_SHIFT)
79
80
81/*
82 * Virtual Mode Local & Global MMR space.
83 */
84#define SH1_LOCAL_MMR_OFFSET 0x8000000000UL
85#define SH2_LOCAL_MMR_OFFSET 0x0200000000UL
86#define LOCAL_MMR_OFFSET (is_shub2() ? SH2_LOCAL_MMR_OFFSET : SH1_LOCAL_MMR_OFFSET)
87#define LOCAL_MMR_SPACE (__IA64_UNCACHED_OFFSET | LOCAL_MMR_OFFSET)
88#define LOCAL_PHYS_MMR_SPACE (RGN_BASE(RGN_HPAGE) | LOCAL_MMR_OFFSET)
89
90#define SH1_GLOBAL_MMR_OFFSET 0x0800000000UL
91#define SH2_GLOBAL_MMR_OFFSET 0x0300000000UL
92#define GLOBAL_MMR_OFFSET (is_shub2() ? SH2_GLOBAL_MMR_OFFSET : SH1_GLOBAL_MMR_OFFSET)
93#define GLOBAL_MMR_SPACE (__IA64_UNCACHED_OFFSET | GLOBAL_MMR_OFFSET)
94
95/*
96 * Physical mode addresses
97 */
98#define GLOBAL_PHYS_MMR_SPACE (RGN_BASE(RGN_HPAGE) | GLOBAL_MMR_OFFSET)
99
100
101/*
102 * Clear region & AS bits.
103 */
104#define TO_PHYS_MASK (~(RGN_BITS | AS_MASK))
105
106
107/*
108 * Misc NASID manipulation.
109 */
110#define NASID_SPACE(n) ((u64)(n) << NASID_SHIFT)
111#define REMOTE_ADDR(n,a) (NASID_SPACE(n) | (a))
112#define NODE_OFFSET(x) ((x) & (NODE_ADDRSPACE_SIZE - 1))
113#define NODE_ADDRSPACE_SIZE (1UL << AS_SHIFT)
114#define NASID_GET(x) (int) (((u64) (x) >> NASID_SHIFT) & NASID_BITMASK)
115#define LOCAL_MMR_ADDR(a) (LOCAL_MMR_SPACE | (a))
116#define GLOBAL_MMR_ADDR(n,a) (GLOBAL_MMR_SPACE | REMOTE_ADDR(n,a))
117#define GLOBAL_MMR_PHYS_ADDR(n,a) (GLOBAL_PHYS_MMR_SPACE | REMOTE_ADDR(n,a))
118#define GLOBAL_CAC_ADDR(n,a) (CAC_BASE | REMOTE_ADDR(n,a))
119#define CHANGE_NASID(n,x) ((void *)(((u64)(x) & ~NASID_MASK) | NASID_SPACE(n)))
120#define IS_TIO_NASID(n) ((n) & 1)
121
122
123/* non-II mmr's start at top of big window space (4G) */
124#define BWIN_TOP 0x0000000100000000UL
125
126/*
127 * general address defines
128 */
129#define CAC_BASE (PAGE_OFFSET | AS_CAC_SPACE)
130#define AMO_BASE (__IA64_UNCACHED_OFFSET | AS_AMO_SPACE)
131#define AMO_PHYS_BASE (RGN_BASE(RGN_HPAGE) | AS_AMO_SPACE)
132#define GET_BASE (PAGE_OFFSET | AS_GET_SPACE)
133
134/*
135 * Convert Memory addresses between various addressing modes.
136 */
137#define TO_PHYS(x) (TO_PHYS_MASK & (x))
138#define TO_CAC(x) (CAC_BASE | TO_PHYS(x))
139#ifdef CONFIG_SGI_SN
140#define TO_AMO(x) (AMO_BASE | TO_PHYS(x))
141#define TO_GET(x) (GET_BASE | TO_PHYS(x))
142#else
143#define TO_AMO(x) ({ BUG(); x; })
144#define TO_GET(x) ({ BUG(); x; })
145#endif
146
147/*
148 * Covert from processor physical address to II/TIO physical address:
149 * II - squeeze out the AS bits
150 * TIO- requires a chiplet id in bits 38-39. For DMA to memory,
151 * the chiplet id is zero. If we implement TIO-TIO dma, we might need
152 * to insert a chiplet id into this macro. However, it is our belief
153 * right now that this chiplet id will be ICE, which is also zero.
154 */
155#define SH1_TIO_PHYS_TO_DMA(x) \
156 ((((u64)(NASID_GET(x))) << 40) | NODE_OFFSET(x))
157
158#define SH2_NETWORK_BANK_OFFSET(x) \
159 ((u64)(x) & ((1UL << (sn_hub_info->nasid_shift - 4)) -1))
160
161#define SH2_NETWORK_BANK_SELECT(x) \
162 ((((u64)(x) & (0x3UL << (sn_hub_info->nasid_shift - 4))) \
163 >> (sn_hub_info->nasid_shift - 4)) << 36)
164
165#define SH2_NETWORK_ADDRESS(x) \
166 (SH2_NETWORK_BANK_OFFSET(x) | SH2_NETWORK_BANK_SELECT(x))
167
168#define SH2_TIO_PHYS_TO_DMA(x) \
169 (((u64)(NASID_GET(x)) << 40) | SH2_NETWORK_ADDRESS(x))
170
171#define PHYS_TO_TIODMA(x) \
172 (is_shub1() ? SH1_TIO_PHYS_TO_DMA(x) : SH2_TIO_PHYS_TO_DMA(x))
173
174#define PHYS_TO_DMA(x) \
175 ((((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x))
176
177
178/*
179 * Macros to test for address type.
180 */
181#define IS_AMO_ADDRESS(x) (((u64)(x) & (RGN_BITS | AS_MASK)) == AMO_BASE)
182#define IS_AMO_PHYS_ADDRESS(x) (((u64)(x) & (RGN_BITS | AS_MASK)) == AMO_PHYS_BASE)
183
184
185/*
186 * The following definitions pertain to the IO special address
187 * space. They define the location of the big and little windows
188 * of any given node.
189 */
190#define BWIN_SIZE_BITS 29 /* big window size: 512M */
191#define TIO_BWIN_SIZE_BITS 30 /* big window size: 1G */
192#define NODE_SWIN_BASE(n, w) ((w == 0) ? NODE_BWIN_BASE((n), SWIN0_BIGWIN) \
193 : RAW_NODE_SWIN_BASE(n, w))
194#define TIO_SWIN_BASE(n, w) (TIO_IO_BASE(n) + \
195 ((u64) (w) << TIO_SWIN_SIZE_BITS))
196#define NODE_IO_BASE(n) (GLOBAL_MMR_SPACE | NASID_SPACE(n))
197#define TIO_IO_BASE(n) (__IA64_UNCACHED_OFFSET | NASID_SPACE(n))
198#define BWIN_SIZE (1UL << BWIN_SIZE_BITS)
199#define NODE_BWIN_BASE0(n) (NODE_IO_BASE(n) + BWIN_SIZE)
200#define NODE_BWIN_BASE(n, w) (NODE_BWIN_BASE0(n) + ((u64) (w) << BWIN_SIZE_BITS))
201#define RAW_NODE_SWIN_BASE(n, w) (NODE_IO_BASE(n) + ((u64) (w) << SWIN_SIZE_BITS))
202#define BWIN_WIDGET_MASK 0x7
203#define BWIN_WINDOWNUM(x) (((x) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
204#define SH1_IS_BIG_WINDOW_ADDR(x) ((x) & BWIN_TOP)
205
206#define TIO_BWIN_WINDOW_SELECT_MASK 0x7
207#define TIO_BWIN_WINDOWNUM(x) (((x) >> TIO_BWIN_SIZE_BITS) & TIO_BWIN_WINDOW_SELECT_MASK)
208
209#define TIO_HWIN_SHIFT_BITS 33
210#define TIO_HWIN(x) (NODE_OFFSET(x) >> TIO_HWIN_SHIFT_BITS)
211
212/*
213 * The following definitions pertain to the IO special address
214 * space. They define the location of the big and little windows
215 * of any given node.
216 */
217
218#define SWIN_SIZE_BITS 24
219#define SWIN_WIDGET_MASK 0xF
220
221#define TIO_SWIN_SIZE_BITS 28
222#define TIO_SWIN_SIZE (1UL << TIO_SWIN_SIZE_BITS)
223#define TIO_SWIN_WIDGET_MASK 0x3
224
225/*
226 * Convert smallwindow address to xtalk address.
227 *
228 * 'addr' can be physical or virtual address, but will be converted
229 * to Xtalk address in the range 0 -> SWINZ_SIZEMASK
230 */
231#define SWIN_WIDGETNUM(x) (((x) >> SWIN_SIZE_BITS) & SWIN_WIDGET_MASK)
232#define TIO_SWIN_WIDGETNUM(x) (((x) >> TIO_SWIN_SIZE_BITS) & TIO_SWIN_WIDGET_MASK)
233
234
235/*
236 * The following macros produce the correct base virtual address for
237 * the hub registers. The REMOTE_HUB_* macro produce
238 * the address for the specified hub's registers. The intent is
239 * that the appropriate PI, MD, NI, or II register would be substituted
240 * for x.
241 *
242 * WARNING:
243 * When certain Hub chip workaround are defined, it's not sufficient
244 * to dereference the *_HUB_ADDR() macros. You should instead use
245 * HUB_L() and HUB_S() if you must deal with pointers to hub registers.
246 * Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
247 * They're always safe.
248 */
249/* Shub1 TIO & MMR addressing macros */
250#define SH1_TIO_IOSPACE_ADDR(n,x) \
251 GLOBAL_MMR_ADDR(n,x)
252
253#define SH1_REMOTE_BWIN_MMR(n,x) \
254 GLOBAL_MMR_ADDR(n,x)
255
256#define SH1_REMOTE_SWIN_MMR(n,x) \
257 (NODE_SWIN_BASE(n,1) + 0x800000UL + (x))
258
259#define SH1_REMOTE_MMR(n,x) \
260 (SH1_IS_BIG_WINDOW_ADDR(x) ? SH1_REMOTE_BWIN_MMR(n,x) : \
261 SH1_REMOTE_SWIN_MMR(n,x))
262
263/* Shub1 TIO & MMR addressing macros */
264#define SH2_TIO_IOSPACE_ADDR(n,x) \
265 ((__IA64_UNCACHED_OFFSET | REMOTE_ADDR(n,x) | 1UL << (NASID_SHIFT - 2)))
266
267#define SH2_REMOTE_MMR(n,x) \
268 GLOBAL_MMR_ADDR(n,x)
269
270
271/* TIO & MMR addressing macros that work on both shub1 & shub2 */
272#define TIO_IOSPACE_ADDR(n,x) \
273 ((u64 *)(is_shub1() ? SH1_TIO_IOSPACE_ADDR(n,x) : \
274 SH2_TIO_IOSPACE_ADDR(n,x)))
275
276#define SH_REMOTE_MMR(n,x) \
277 (is_shub1() ? SH1_REMOTE_MMR(n,x) : SH2_REMOTE_MMR(n,x))
278
279#define REMOTE_HUB_ADDR(n,x) \
280 (IS_TIO_NASID(n) ? ((volatile u64*)TIO_IOSPACE_ADDR(n,x)) : \
281 ((volatile u64*)SH_REMOTE_MMR(n,x)))
282
283
284#define HUB_L(x) (*((volatile typeof(*x) *)x))
285#define HUB_S(x,d) (*((volatile typeof(*x) *)x) = (d))
286
287#define REMOTE_HUB_L(n, a) HUB_L(REMOTE_HUB_ADDR((n), (a)))
288#define REMOTE_HUB_S(n, a, d) HUB_S(REMOTE_HUB_ADDR((n), (a)), (d))
289
290/*
291 * Coretalk address breakdown
292 */
293#define CTALK_NASID_SHFT 40
294#define CTALK_NASID_MASK (0x3FFFULL << CTALK_NASID_SHFT)
295#define CTALK_CID_SHFT 38
296#define CTALK_CID_MASK (0x3ULL << CTALK_CID_SHFT)
297#define CTALK_NODE_OFFSET 0x3FFFFFFFFF
298
299#endif /* _ASM_IA64_SN_ADDRS_H */
diff --git a/include/asm-ia64/sn/arch.h b/include/asm-ia64/sn/arch.h
deleted file mode 100644
index 7caa1f44cd9..00000000000
--- a/include/asm-ia64/sn/arch.h
+++ /dev/null
@@ -1,86 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI specific setup.
7 *
8 * Copyright (C) 1995-1997,1999,2001-2005 Silicon Graphics, Inc. All rights reserved.
9 * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
10 */
11#ifndef _ASM_IA64_SN_ARCH_H
12#define _ASM_IA64_SN_ARCH_H
13
14#include <linux/numa.h>
15#include <asm/types.h>
16#include <asm/percpu.h>
17#include <asm/sn/types.h>
18#include <asm/sn/sn_cpuid.h>
19
20/*
21 * This is the maximum number of NUMALINK nodes that can be part of a single
22 * SSI kernel. This number includes C-brick, M-bricks, and TIOs. Nodes in
23 * remote partitions are NOT included in this number.
24 * The number of compact nodes cannot exceed size of a coherency domain.
25 * The purpose of this define is to specify a node count that includes
26 * all C/M/TIO nodes in an SSI system.
27 *
28 * SGI system can currently support up to 256 C/M nodes plus additional TIO nodes.
29 *
30 * Note: ACPI20 has an architectural limit of 256 nodes. When we upgrade
31 * to ACPI3.0, this limit will be removed. The notion of "compact nodes"
32 * should be deleted and TIOs should be included in MAX_NUMNODES.
33 */
34#define MAX_TIO_NODES MAX_NUMNODES
35#define MAX_COMPACT_NODES (MAX_NUMNODES + MAX_TIO_NODES)
36
37/*
38 * Maximum number of nodes in all partitions and in all coherency domains.
39 * This is the total number of nodes accessible in the numalink fabric. It
40 * includes all C & M bricks, plus all TIOs.
41 *
42 * This value is also the value of the maximum number of NASIDs in the numalink
43 * fabric.
44 */
45#define MAX_NUMALINK_NODES 16384
46
47/*
48 * The following defines attributes of the HUB chip. These attributes are
49 * frequently referenced. They are kept in the per-cpu data areas of each cpu.
50 * They are kept together in a struct to minimize cache misses.
51 */
52struct sn_hub_info_s {
53 u8 shub2;
54 u8 nasid_shift;
55 u8 as_shift;
56 u8 shub_1_1_found;
57 u16 nasid_bitmask;
58};
59DECLARE_PER_CPU(struct sn_hub_info_s, __sn_hub_info);
60#define sn_hub_info (&__get_cpu_var(__sn_hub_info))
61#define is_shub2() (sn_hub_info->shub2)
62#define is_shub1() (sn_hub_info->shub2 == 0)
63
64/*
65 * Use this macro to test if shub 1.1 wars should be enabled
66 */
67#define enable_shub_wars_1_1() (sn_hub_info->shub_1_1_found)
68
69
70/*
71 * Compact node ID to nasid mappings kept in the per-cpu data areas of each
72 * cpu.
73 */
74DECLARE_PER_CPU(short, __sn_cnodeid_to_nasid[MAX_COMPACT_NODES]);
75#define sn_cnodeid_to_nasid (&__get_cpu_var(__sn_cnodeid_to_nasid[0]))
76
77
78extern u8 sn_partition_id;
79extern u8 sn_system_size;
80extern u8 sn_sharing_domain_size;
81extern u8 sn_region_size;
82
83extern void sn_flush_all_caches(long addr, long bytes);
84extern bool sn_cpu_disable_allowed(int cpu);
85
86#endif /* _ASM_IA64_SN_ARCH_H */
diff --git a/include/asm-ia64/sn/bte.h b/include/asm-ia64/sn/bte.h
deleted file mode 100644
index a0d214f4311..00000000000
--- a/include/asm-ia64/sn/bte.h
+++ /dev/null
@@ -1,233 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (c) 2000-2007 Silicon Graphics, Inc. All Rights Reserved.
7 */
8
9
10#ifndef _ASM_IA64_SN_BTE_H
11#define _ASM_IA64_SN_BTE_H
12
13#include <linux/timer.h>
14#include <linux/spinlock.h>
15#include <linux/cache.h>
16#include <asm/sn/pda.h>
17#include <asm/sn/types.h>
18#include <asm/sn/shub_mmr.h>
19
20#define IBCT_NOTIFY (0x1UL << 4)
21#define IBCT_ZFIL_MODE (0x1UL << 0)
22
23/* #define BTE_DEBUG */
24/* #define BTE_DEBUG_VERBOSE */
25
26#ifdef BTE_DEBUG
27# define BTE_PRINTK(x) printk x /* Terse */
28# ifdef BTE_DEBUG_VERBOSE
29# define BTE_PRINTKV(x) printk x /* Verbose */
30# else
31# define BTE_PRINTKV(x)
32# endif /* BTE_DEBUG_VERBOSE */
33#else
34# define BTE_PRINTK(x)
35# define BTE_PRINTKV(x)
36#endif /* BTE_DEBUG */
37
38
39/* BTE status register only supports 16 bits for length field */
40#define BTE_LEN_BITS (16)
41#define BTE_LEN_MASK ((1 << BTE_LEN_BITS) - 1)
42#define BTE_MAX_XFER ((1 << BTE_LEN_BITS) * L1_CACHE_BYTES)
43
44
45/* Define hardware */
46#define BTES_PER_NODE (is_shub2() ? 4 : 2)
47#define MAX_BTES_PER_NODE 4
48
49#define BTE2OFF_CTRL 0
50#define BTE2OFF_SRC (SH2_BT_ENG_SRC_ADDR_0 - SH2_BT_ENG_CSR_0)
51#define BTE2OFF_DEST (SH2_BT_ENG_DEST_ADDR_0 - SH2_BT_ENG_CSR_0)
52#define BTE2OFF_NOTIFY (SH2_BT_ENG_NOTIF_ADDR_0 - SH2_BT_ENG_CSR_0)
53
54#define BTE_BASE_ADDR(interface) \
55 (is_shub2() ? (interface == 0) ? SH2_BT_ENG_CSR_0 : \
56 (interface == 1) ? SH2_BT_ENG_CSR_1 : \
57 (interface == 2) ? SH2_BT_ENG_CSR_2 : \
58 SH2_BT_ENG_CSR_3 \
59 : (interface == 0) ? IIO_IBLS0 : IIO_IBLS1)
60
61#define BTE_SOURCE_ADDR(base) \
62 (is_shub2() ? base + (BTE2OFF_SRC/8) \
63 : base + (BTEOFF_SRC/8))
64
65#define BTE_DEST_ADDR(base) \
66 (is_shub2() ? base + (BTE2OFF_DEST/8) \
67 : base + (BTEOFF_DEST/8))
68
69#define BTE_CTRL_ADDR(base) \
70 (is_shub2() ? base + (BTE2OFF_CTRL/8) \
71 : base + (BTEOFF_CTRL/8))
72
73#define BTE_NOTIF_ADDR(base) \
74 (is_shub2() ? base + (BTE2OFF_NOTIFY/8) \
75 : base + (BTEOFF_NOTIFY/8))
76
77/* Define hardware modes */
78#define BTE_NOTIFY IBCT_NOTIFY
79#define BTE_NORMAL BTE_NOTIFY
80#define BTE_ZERO_FILL (BTE_NOTIFY | IBCT_ZFIL_MODE)
81/* Use a reserved bit to let the caller specify a wait for any BTE */
82#define BTE_WACQUIRE 0x4000
83/* Use the BTE on the node with the destination memory */
84#define BTE_USE_DEST (BTE_WACQUIRE << 1)
85/* Use any available BTE interface on any node for the transfer */
86#define BTE_USE_ANY (BTE_USE_DEST << 1)
87/* macro to force the IBCT0 value valid */
88#define BTE_VALID_MODE(x) ((x) & (IBCT_NOTIFY | IBCT_ZFIL_MODE))
89
90#define BTE_ACTIVE (IBLS_BUSY | IBLS_ERROR)
91#define BTE_WORD_AVAILABLE (IBLS_BUSY << 1)
92#define BTE_WORD_BUSY (~BTE_WORD_AVAILABLE)
93
94/*
95 * Some macros to simplify reading.
96 * Start with macros to locate the BTE control registers.
97 */
98#define BTE_LNSTAT_LOAD(_bte) \
99 HUB_L(_bte->bte_base_addr)
100#define BTE_LNSTAT_STORE(_bte, _x) \
101 HUB_S(_bte->bte_base_addr, (_x))
102#define BTE_SRC_STORE(_bte, _x) \
103({ \
104 u64 __addr = ((_x) & ~AS_MASK); \
105 if (is_shub2()) \
106 __addr = SH2_TIO_PHYS_TO_DMA(__addr); \
107 HUB_S(_bte->bte_source_addr, __addr); \
108})
109#define BTE_DEST_STORE(_bte, _x) \
110({ \
111 u64 __addr = ((_x) & ~AS_MASK); \
112 if (is_shub2()) \
113 __addr = SH2_TIO_PHYS_TO_DMA(__addr); \
114 HUB_S(_bte->bte_destination_addr, __addr); \
115})
116#define BTE_CTRL_STORE(_bte, _x) \
117 HUB_S(_bte->bte_control_addr, (_x))
118#define BTE_NOTIF_STORE(_bte, _x) \
119({ \
120 u64 __addr = ia64_tpa((_x) & ~AS_MASK); \
121 if (is_shub2()) \
122 __addr = SH2_TIO_PHYS_TO_DMA(__addr); \
123 HUB_S(_bte->bte_notify_addr, __addr); \
124})
125
126#define BTE_START_TRANSFER(_bte, _len, _mode) \
127 is_shub2() ? BTE_CTRL_STORE(_bte, IBLS_BUSY | (_mode << 24) | _len) \
128 : BTE_LNSTAT_STORE(_bte, _len); \
129 BTE_CTRL_STORE(_bte, _mode)
130
131/* Possible results from bte_copy and bte_unaligned_copy */
132/* The following error codes map into the BTE hardware codes
133 * IIO_ICRB_ECODE_* (in shubio.h). The hardware uses
134 * an error code of 0 (IIO_ICRB_ECODE_DERR), but we want zero
135 * to mean BTE_SUCCESS, so add one (BTEFAIL_OFFSET) to the error
136 * codes to give the following error codes.
137 */
138#define BTEFAIL_OFFSET 1
139
140typedef enum {
141 BTE_SUCCESS, /* 0 is success */
142 BTEFAIL_DIR, /* Directory error due to IIO access*/
143 BTEFAIL_POISON, /* poison error on IO access (write to poison page) */
144 BTEFAIL_WERR, /* Write error (ie WINV to a Read only line) */
145 BTEFAIL_ACCESS, /* access error (protection violation) */
146 BTEFAIL_PWERR, /* Partial Write Error */
147 BTEFAIL_PRERR, /* Partial Read Error */
148 BTEFAIL_TOUT, /* CRB Time out */
149 BTEFAIL_XTERR, /* Incoming xtalk pkt had error bit */
150 BTEFAIL_NOTAVAIL, /* BTE not available */
151} bte_result_t;
152
153#define BTEFAIL_SH2_RESP_SHORT 0x1 /* bit 000001 */
154#define BTEFAIL_SH2_RESP_LONG 0x2 /* bit 000010 */
155#define BTEFAIL_SH2_RESP_DSP 0x4 /* bit 000100 */
156#define BTEFAIL_SH2_RESP_ACCESS 0x8 /* bit 001000 */
157#define BTEFAIL_SH2_CRB_TO 0x10 /* bit 010000 */
158#define BTEFAIL_SH2_NACK_LIMIT 0x20 /* bit 100000 */
159#define BTEFAIL_SH2_ALL 0x3F /* bit 111111 */
160
161#define BTE_ERR_BITS 0x3FUL
162#define BTE_ERR_SHIFT 36
163#define BTE_ERR_MASK (BTE_ERR_BITS << BTE_ERR_SHIFT)
164
165#define BTE_ERROR_RETRY(value) \
166 (is_shub2() ? (value != BTEFAIL_SH2_CRB_TO) \
167 : (value != BTEFAIL_TOUT))
168
169/*
170 * On shub1 BTE_ERR_MASK will always be false, so no need for is_shub2()
171 */
172#define BTE_SHUB2_ERROR(_status) \
173 ((_status & BTE_ERR_MASK) \
174 ? (((_status >> BTE_ERR_SHIFT) & BTE_ERR_BITS) | IBLS_ERROR) \
175 : _status)
176
177#define BTE_GET_ERROR_STATUS(_status) \
178 (BTE_SHUB2_ERROR(_status) & ~IBLS_ERROR)
179
180#define BTE_VALID_SH2_ERROR(value) \
181 ((value >= BTEFAIL_SH2_RESP_SHORT) && (value <= BTEFAIL_SH2_ALL))
182
183/*
184 * Structure defining a bte. An instance of this
185 * structure is created in the nodepda for each
186 * bte on that node (as defined by BTES_PER_NODE)
187 * This structure contains everything necessary
188 * to work with a BTE.
189 */
190struct bteinfo_s {
191 volatile u64 notify ____cacheline_aligned;
192 u64 *bte_base_addr ____cacheline_aligned;
193 u64 *bte_source_addr;
194 u64 *bte_destination_addr;
195 u64 *bte_control_addr;
196 u64 *bte_notify_addr;
197 spinlock_t spinlock;
198 cnodeid_t bte_cnode; /* cnode */
199 int bte_error_count; /* Number of errors encountered */
200 int bte_num; /* 0 --> BTE0, 1 --> BTE1 */
201 int cleanup_active; /* Interface is locked for cleanup */
202 volatile bte_result_t bh_error; /* error while processing */
203 volatile u64 *most_rcnt_na;
204 struct bteinfo_s *btes_to_try[MAX_BTES_PER_NODE];
205};
206
207
208/*
209 * Function prototypes (functions defined in bte.c, used elsewhere)
210 */
211extern bte_result_t bte_copy(u64, u64, u64, u64, void *);
212extern bte_result_t bte_unaligned_copy(u64, u64, u64, u64);
213extern void bte_error_handler(unsigned long);
214
215#define bte_zero(dest, len, mode, notification) \
216 bte_copy(0, dest, len, ((mode) | BTE_ZERO_FILL), notification)
217
218/*
219 * The following is the prefered way of calling bte_unaligned_copy
220 * If the copy is fully cache line aligned, then bte_copy is
221 * used instead. Since bte_copy is inlined, this saves a call
222 * stack. NOTE: bte_copy is called synchronously and does block
223 * until the transfer is complete. In order to get the asynch
224 * version of bte_copy, you must perform this check yourself.
225 */
226#define BTE_UNALIGNED_COPY(src, dest, len, mode) \
227 (((len & L1_CACHE_MASK) || (src & L1_CACHE_MASK) || \
228 (dest & L1_CACHE_MASK)) ? \
229 bte_unaligned_copy(src, dest, len, mode) : \
230 bte_copy(src, dest, len, mode, NULL))
231
232
233#endif /* _ASM_IA64_SN_BTE_H */
diff --git a/include/asm-ia64/sn/clksupport.h b/include/asm-ia64/sn/clksupport.h
deleted file mode 100644
index d340c365a82..00000000000
--- a/include/asm-ia64/sn/clksupport.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
7 */
8
9/*
10 * This file contains definitions for accessing a platform supported high resolution
11 * clock. The clock is monitonically increasing and can be accessed from any node
12 * in the system. The clock is synchronized across nodes - all nodes see the
13 * same value.
14 *
15 * RTC_COUNTER_ADDR - contains the address of the counter
16 *
17 */
18
19#ifndef _ASM_IA64_SN_CLKSUPPORT_H
20#define _ASM_IA64_SN_CLKSUPPORT_H
21
22extern unsigned long sn_rtc_cycles_per_second;
23
24#define RTC_COUNTER_ADDR ((long *)LOCAL_MMR_ADDR(SH_RTC))
25
26#define rtc_time() (*RTC_COUNTER_ADDR)
27
28#endif /* _ASM_IA64_SN_CLKSUPPORT_H */
diff --git a/include/asm-ia64/sn/geo.h b/include/asm-ia64/sn/geo.h
deleted file mode 100644
index f083c943406..00000000000
--- a/include/asm-ia64/sn/geo.h
+++ /dev/null
@@ -1,132 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
7 */
8
9#ifndef _ASM_IA64_SN_GEO_H
10#define _ASM_IA64_SN_GEO_H
11
12/* The geoid_t implementation below is based loosely on the pcfg_t
13 implementation in sys/SN/promcfg.h. */
14
15/* Type declaractions */
16
17/* Size of a geoid_t structure (must be before decl. of geoid_u) */
18#define GEOID_SIZE 8 /* Would 16 be better? The size can
19 be different on different platforms. */
20
21#define MAX_SLOTS 0xf /* slots per module */
22#define MAX_SLABS 0xf /* slabs per slot */
23
24typedef unsigned char geo_type_t;
25
26/* Fields common to all substructures */
27typedef struct geo_common_s {
28 moduleid_t module; /* The module (box) this h/w lives in */
29 geo_type_t type; /* What type of h/w is named by this geoid_t */
30 slabid_t slab:4; /* slab (ASIC), 0 .. 15 within slot */
31 slotid_t slot:4; /* slot (Blade), 0 .. 15 within module */
32} geo_common_t;
33
34/* Additional fields for particular types of hardware */
35typedef struct geo_node_s {
36 geo_common_t common; /* No additional fields needed */
37} geo_node_t;
38
39typedef struct geo_rtr_s {
40 geo_common_t common; /* No additional fields needed */
41} geo_rtr_t;
42
43typedef struct geo_iocntl_s {
44 geo_common_t common; /* No additional fields needed */
45} geo_iocntl_t;
46
47typedef struct geo_pcicard_s {
48 geo_iocntl_t common;
49 char bus; /* Bus/widget number */
50 char slot; /* PCI slot number */
51} geo_pcicard_t;
52
53/* Subcomponents of a node */
54typedef struct geo_cpu_s {
55 geo_node_t node;
56 char slice; /* Which CPU on the node */
57} geo_cpu_t;
58
59typedef struct geo_mem_s {
60 geo_node_t node;
61 char membus; /* The memory bus on the node */
62 char memslot; /* The memory slot on the bus */
63} geo_mem_t;
64
65
66typedef union geoid_u {
67 geo_common_t common;
68 geo_node_t node;
69 geo_iocntl_t iocntl;
70 geo_pcicard_t pcicard;
71 geo_rtr_t rtr;
72 geo_cpu_t cpu;
73 geo_mem_t mem;
74 char padsize[GEOID_SIZE];
75} geoid_t;
76
77
78/* Preprocessor macros */
79
80#define GEO_MAX_LEN 48 /* max. formatted length, plus some pad:
81 module/001c07/slab/5/node/memory/2/slot/4 */
82
83/* Values for geo_type_t */
84#define GEO_TYPE_INVALID 0
85#define GEO_TYPE_MODULE 1
86#define GEO_TYPE_NODE 2
87#define GEO_TYPE_RTR 3
88#define GEO_TYPE_IOCNTL 4
89#define GEO_TYPE_IOCARD 5
90#define GEO_TYPE_CPU 6
91#define GEO_TYPE_MEM 7
92#define GEO_TYPE_MAX (GEO_TYPE_MEM+1)
93
94/* Parameter for hwcfg_format_geoid_compt() */
95#define GEO_COMPT_MODULE 1
96#define GEO_COMPT_SLAB 2
97#define GEO_COMPT_IOBUS 3
98#define GEO_COMPT_IOSLOT 4
99#define GEO_COMPT_CPU 5
100#define GEO_COMPT_MEMBUS 6
101#define GEO_COMPT_MEMSLOT 7
102
103#define GEO_INVALID_STR "<invalid>"
104
105#define INVALID_NASID ((nasid_t)-1)
106#define INVALID_CNODEID ((cnodeid_t)-1)
107#define INVALID_PNODEID ((pnodeid_t)-1)
108#define INVALID_SLAB (slabid_t)-1
109#define INVALID_SLOT (slotid_t)-1
110#define INVALID_MODULE ((moduleid_t)-1)
111
112static inline slabid_t geo_slab(geoid_t g)
113{
114 return (g.common.type == GEO_TYPE_INVALID) ?
115 INVALID_SLAB : g.common.slab;
116}
117
118static inline slotid_t geo_slot(geoid_t g)
119{
120 return (g.common.type == GEO_TYPE_INVALID) ?
121 INVALID_SLOT : g.common.slot;
122}
123
124static inline moduleid_t geo_module(geoid_t g)
125{
126 return (g.common.type == GEO_TYPE_INVALID) ?
127 INVALID_MODULE : g.common.module;
128}
129
130extern geoid_t cnodeid_get_geoid(cnodeid_t cnode);
131
132#endif /* _ASM_IA64_SN_GEO_H */
diff --git a/include/asm-ia64/sn/intr.h b/include/asm-ia64/sn/intr.h
deleted file mode 100644
index e0487aa9741..00000000000
--- a/include/asm-ia64/sn/intr.h
+++ /dev/null
@@ -1,68 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2006 Silicon Graphics, Inc. All rights reserved.
7 */
8
9#ifndef _ASM_IA64_SN_INTR_H
10#define _ASM_IA64_SN_INTR_H
11
12#include <linux/rcupdate.h>
13#include <asm/sn/types.h>
14
15#define SGI_UART_VECTOR 0xe9
16
17/* Reserved IRQs : Note, not to exceed IA64_SN2_FIRST_DEVICE_VECTOR */
18#define SGI_XPC_ACTIVATE 0x30
19#define SGI_II_ERROR 0x31
20#define SGI_XBOW_ERROR 0x32
21#define SGI_PCIASIC_ERROR 0x33
22#define SGI_ACPI_SCI_INT 0x34
23#define SGI_TIOCA_ERROR 0x35
24#define SGI_TIO_ERROR 0x36
25#define SGI_TIOCX_ERROR 0x37
26#define SGI_MMTIMER_VECTOR 0x38
27#define SGI_XPC_NOTIFY 0xe7
28
29#define IA64_SN2_FIRST_DEVICE_VECTOR 0x3c
30#define IA64_SN2_LAST_DEVICE_VECTOR 0xe6
31
32#define SN2_IRQ_RESERVED 0x1
33#define SN2_IRQ_CONNECTED 0x2
34#define SN2_IRQ_SHARED 0x4
35
36// The SN PROM irq struct
37struct sn_irq_info {
38 struct sn_irq_info *irq_next; /* deprecated DO NOT USE */
39 short irq_nasid; /* Nasid IRQ is assigned to */
40 int irq_slice; /* slice IRQ is assigned to */
41 int irq_cpuid; /* kernel logical cpuid */
42 int irq_irq; /* the IRQ number */
43 int irq_int_bit; /* Bridge interrupt pin */
44 /* <0 means MSI */
45 u64 irq_xtalkaddr; /* xtalkaddr IRQ is sent to */
46 int irq_bridge_type;/* pciio asic type (pciio.h) */
47 void *irq_bridge; /* bridge generating irq */
48 void *irq_pciioinfo; /* associated pciio_info_t */
49 int irq_last_intr; /* For Shub lb lost intr WAR */
50 int irq_cookie; /* unique cookie */
51 int irq_flags; /* flags */
52 int irq_share_cnt; /* num devices sharing IRQ */
53 struct list_head list; /* list of sn_irq_info structs */
54 struct rcu_head rcu; /* rcu callback list */
55};
56
57extern void sn_send_IPI_phys(int, long, int, int);
58extern u64 sn_intr_alloc(nasid_t, int,
59 struct sn_irq_info *,
60 int, nasid_t, int);
61extern void sn_intr_free(nasid_t, int, struct sn_irq_info *);
62extern struct sn_irq_info *sn_retarget_vector(struct sn_irq_info *, nasid_t, int);
63extern void sn_set_err_irq_affinity(unsigned int);
64extern struct list_head **sn_irq_lh;
65
66#define CPU_VECTOR_TO_IRQ(cpuid,vector) (vector)
67
68#endif /* _ASM_IA64_SN_INTR_H */
diff --git a/include/asm-ia64/sn/io.h b/include/asm-ia64/sn/io.h
deleted file mode 100644
index 41c73a73562..00000000000
--- a/include/asm-ia64/sn/io.h
+++ /dev/null
@@ -1,274 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
7 */
8
9#ifndef _ASM_SN_IO_H
10#define _ASM_SN_IO_H
11#include <linux/compiler.h>
12#include <asm/intrinsics.h>
13
14extern void * sn_io_addr(unsigned long port) __attribute_const__; /* Forward definition */
15extern void __sn_mmiowb(void); /* Forward definition */
16
17extern int num_cnodes;
18
19#define __sn_mf_a() ia64_mfa()
20
21extern void sn_dma_flush(unsigned long);
22
23#define __sn_inb ___sn_inb
24#define __sn_inw ___sn_inw
25#define __sn_inl ___sn_inl
26#define __sn_outb ___sn_outb
27#define __sn_outw ___sn_outw
28#define __sn_outl ___sn_outl
29#define __sn_readb ___sn_readb
30#define __sn_readw ___sn_readw
31#define __sn_readl ___sn_readl
32#define __sn_readq ___sn_readq
33#define __sn_readb_relaxed ___sn_readb_relaxed
34#define __sn_readw_relaxed ___sn_readw_relaxed
35#define __sn_readl_relaxed ___sn_readl_relaxed
36#define __sn_readq_relaxed ___sn_readq_relaxed
37
38/*
39 * Convenience macros for setting/clearing bits using the above accessors
40 */
41
42#define __sn_setq_relaxed(addr, val) \
43 writeq((__sn_readq_relaxed(addr) | (val)), (addr))
44#define __sn_clrq_relaxed(addr, val) \
45 writeq((__sn_readq_relaxed(addr) & ~(val)), (addr))
46
47/*
48 * The following routines are SN Platform specific, called when
49 * a reference is made to inX/outX set macros. SN Platform
50 * inX set of macros ensures that Posted DMA writes on the
51 * Bridge is flushed.
52 *
53 * The routines should be self explainatory.
54 */
55
56static inline unsigned int
57___sn_inb (unsigned long port)
58{
59 volatile unsigned char *addr;
60 unsigned char ret = -1;
61
62 if ((addr = sn_io_addr(port))) {
63 ret = *addr;
64 __sn_mf_a();
65 sn_dma_flush((unsigned long)addr);
66 }
67 return ret;
68}
69
70static inline unsigned int
71___sn_inw (unsigned long port)
72{
73 volatile unsigned short *addr;
74 unsigned short ret = -1;
75
76 if ((addr = sn_io_addr(port))) {
77 ret = *addr;
78 __sn_mf_a();
79 sn_dma_flush((unsigned long)addr);
80 }
81 return ret;
82}
83
84static inline unsigned int
85___sn_inl (unsigned long port)
86{
87 volatile unsigned int *addr;
88 unsigned int ret = -1;
89
90 if ((addr = sn_io_addr(port))) {
91 ret = *addr;
92 __sn_mf_a();
93 sn_dma_flush((unsigned long)addr);
94 }
95 return ret;
96}
97
98static inline void
99___sn_outb (unsigned char val, unsigned long port)
100{
101 volatile unsigned char *addr;
102
103 if ((addr = sn_io_addr(port))) {
104 *addr = val;
105 __sn_mmiowb();
106 }
107}
108
109static inline void
110___sn_outw (unsigned short val, unsigned long port)
111{
112 volatile unsigned short *addr;
113
114 if ((addr = sn_io_addr(port))) {
115 *addr = val;
116 __sn_mmiowb();
117 }
118}
119
120static inline void
121___sn_outl (unsigned int val, unsigned long port)
122{
123 volatile unsigned int *addr;
124
125 if ((addr = sn_io_addr(port))) {
126 *addr = val;
127 __sn_mmiowb();
128 }
129}
130
131/*
132 * The following routines are SN Platform specific, called when
133 * a reference is made to readX/writeX set macros. SN Platform
134 * readX set of macros ensures that Posted DMA writes on the
135 * Bridge is flushed.
136 *
137 * The routines should be self explainatory.
138 */
139
140static inline unsigned char
141___sn_readb (const volatile void __iomem *addr)
142{
143 unsigned char val;
144
145 val = *(volatile unsigned char __force *)addr;
146 __sn_mf_a();
147 sn_dma_flush((unsigned long)addr);
148 return val;
149}
150
151static inline unsigned short
152___sn_readw (const volatile void __iomem *addr)
153{
154 unsigned short val;
155
156 val = *(volatile unsigned short __force *)addr;
157 __sn_mf_a();
158 sn_dma_flush((unsigned long)addr);
159 return val;
160}
161
162static inline unsigned int
163___sn_readl (const volatile void __iomem *addr)
164{
165 unsigned int val;
166
167 val = *(volatile unsigned int __force *)addr;
168 __sn_mf_a();
169 sn_dma_flush((unsigned long)addr);
170 return val;
171}
172
173static inline unsigned long
174___sn_readq (const volatile void __iomem *addr)
175{
176 unsigned long val;
177
178 val = *(volatile unsigned long __force *)addr;
179 __sn_mf_a();
180 sn_dma_flush((unsigned long)addr);
181 return val;
182}
183
184/*
185 * For generic and SN2 kernels, we have a set of fast access
186 * PIO macros. These macros are provided on SN Platform
187 * because the normal inX and readX macros perform an
188 * additional task of flushing Post DMA request on the Bridge.
189 *
190 * These routines should be self explainatory.
191 */
192
193static inline unsigned int
194sn_inb_fast (unsigned long port)
195{
196 volatile unsigned char *addr = (unsigned char *)port;
197 unsigned char ret;
198
199 ret = *addr;
200 __sn_mf_a();
201 return ret;
202}
203
204static inline unsigned int
205sn_inw_fast (unsigned long port)
206{
207 volatile unsigned short *addr = (unsigned short *)port;
208 unsigned short ret;
209
210 ret = *addr;
211 __sn_mf_a();
212 return ret;
213}
214
215static inline unsigned int
216sn_inl_fast (unsigned long port)
217{
218 volatile unsigned int *addr = (unsigned int *)port;
219 unsigned int ret;
220
221 ret = *addr;
222 __sn_mf_a();
223 return ret;
224}
225
226static inline unsigned char
227___sn_readb_relaxed (const volatile void __iomem *addr)
228{
229 return *(volatile unsigned char __force *)addr;
230}
231
232static inline unsigned short
233___sn_readw_relaxed (const volatile void __iomem *addr)
234{
235 return *(volatile unsigned short __force *)addr;
236}
237
238static inline unsigned int
239___sn_readl_relaxed (const volatile void __iomem *addr)
240{
241 return *(volatile unsigned int __force *) addr;
242}
243
244static inline unsigned long
245___sn_readq_relaxed (const volatile void __iomem *addr)
246{
247 return *(volatile unsigned long __force *) addr;
248}
249
250struct pci_dev;
251
252static inline int
253sn_pci_set_vchan(struct pci_dev *pci_dev, unsigned long *addr, int vchan)
254{
255
256 if (vchan > 1) {
257 return -1;
258 }
259
260 if (!(*addr >> 32)) /* Using a mask here would be cleaner */
261 return 0; /* but this generates better code */
262
263 if (vchan == 1) {
264 /* Set Bit 57 */
265 *addr |= (1UL << 57);
266 } else {
267 /* Clear Bit 57 */
268 *addr &= ~(1UL << 57);
269 }
270
271 return 0;
272}
273
274#endif /* _ASM_SN_IO_H */
diff --git a/include/asm-ia64/sn/ioc3.h b/include/asm-ia64/sn/ioc3.h
deleted file mode 100644
index 95ed6cc83cf..00000000000
--- a/include/asm-ia64/sn/ioc3.h
+++ /dev/null
@@ -1,241 +0,0 @@
1/*
2 * Copyright (C) 2005 Silicon Graphics, Inc.
3 */
4#ifndef IA64_SN_IOC3_H
5#define IA64_SN_IOC3_H
6
7/* serial port register map */
8struct ioc3_serialregs {
9 uint32_t sscr;
10 uint32_t stpir;
11 uint32_t stcir;
12 uint32_t srpir;
13 uint32_t srcir;
14 uint32_t srtr;
15 uint32_t shadow;
16};
17
18/* SUPERIO uart register map */
19struct ioc3_uartregs {
20 char iu_lcr;
21 union {
22 char iir; /* read only */
23 char fcr; /* write only */
24 } u3;
25 union {
26 char ier; /* DLAB == 0 */
27 char dlm; /* DLAB == 1 */
28 } u2;
29 union {
30 char rbr; /* read only, DLAB == 0 */
31 char thr; /* write only, DLAB == 0 */
32 char dll; /* DLAB == 1 */
33 } u1;
34 char iu_scr;
35 char iu_msr;
36 char iu_lsr;
37 char iu_mcr;
38};
39
40#define iu_rbr u1.rbr
41#define iu_thr u1.thr
42#define iu_dll u1.dll
43#define iu_ier u2.ier
44#define iu_dlm u2.dlm
45#define iu_iir u3.iir
46#define iu_fcr u3.fcr
47
48struct ioc3_sioregs {
49 char fill[0x170];
50 struct ioc3_uartregs uartb;
51 struct ioc3_uartregs uarta;
52};
53
54/* PCI IO/mem space register map */
55struct ioc3 {
56 uint32_t pci_id;
57 uint32_t pci_scr;
58 uint32_t pci_rev;
59 uint32_t pci_lat;
60 uint32_t pci_addr;
61 uint32_t pci_err_addr_l;
62 uint32_t pci_err_addr_h;
63
64 uint32_t sio_ir;
65 /* these registers are read-only for general kernel code. To
66 * modify them use the functions in ioc3.c
67 */
68 uint32_t sio_ies;
69 uint32_t sio_iec;
70 uint32_t sio_cr;
71 uint32_t int_out;
72 uint32_t mcr;
73 uint32_t gpcr_s;
74 uint32_t gpcr_c;
75 uint32_t gpdr;
76 uint32_t gppr[9];
77 char fill[0x4c];
78
79 /* serial port registers */
80 uint32_t sbbr_h;
81 uint32_t sbbr_l;
82
83 struct ioc3_serialregs port_a;
84 struct ioc3_serialregs port_b;
85 char fill1[0x1ff10];
86 /* superio registers */
87 struct ioc3_sioregs sregs;
88};
89
90/* These don't exist on the ioc3 serial card... */
91#define eier fill1[8]
92#define eisr fill1[4]
93
94#define PCI_LAT 0xc /* Latency Timer */
95#define PCI_SCR_DROP_MODE_EN 0x00008000 /* drop pios on parity err */
96#define UARTA_BASE 0x178
97#define UARTB_BASE 0x170
98
99
100/* bitmasks for serial RX status byte */
101#define RXSB_OVERRUN 0x01 /* char(s) lost */
102#define RXSB_PAR_ERR 0x02 /* parity error */
103#define RXSB_FRAME_ERR 0x04 /* framing error */
104#define RXSB_BREAK 0x08 /* break character */
105#define RXSB_CTS 0x10 /* state of CTS */
106#define RXSB_DCD 0x20 /* state of DCD */
107#define RXSB_MODEM_VALID 0x40 /* DCD, CTS and OVERRUN are valid */
108#define RXSB_DATA_VALID 0x80 /* FRAME_ERR PAR_ERR & BREAK valid */
109
110/* bitmasks for serial TX control byte */
111#define TXCB_INT_WHEN_DONE 0x20 /* interrupt after this byte is sent */
112#define TXCB_INVALID 0x00 /* byte is invalid */
113#define TXCB_VALID 0x40 /* byte is valid */
114#define TXCB_MCR 0x80 /* data<7:0> to modem cntrl register */
115#define TXCB_DELAY 0xc0 /* delay data<7:0> mSec */
116
117/* bitmasks for SBBR_L */
118#define SBBR_L_SIZE 0x00000001 /* 0 1KB rings, 1 4KB rings */
119
120/* bitmasks for SSCR_<A:B> */
121#define SSCR_RX_THRESHOLD 0x000001ff /* hiwater mark */
122#define SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */
123#define SSCR_HFC_EN 0x00020000 /* h/w flow cntrl enabled */
124#define SSCR_RX_RING_DCD 0x00040000 /* postRX record on delta-DCD */
125#define SSCR_RX_RING_CTS 0x00080000 /* postRX record on delta-CTS */
126#define SSCR_HIGH_SPD 0x00100000 /* 4X speed */
127#define SSCR_DIAG 0x00200000 /* bypass clock divider */
128#define SSCR_RX_DRAIN 0x08000000 /* drain RX buffer to memory */
129#define SSCR_DMA_EN 0x10000000 /* enable ring buffer DMA */
130#define SSCR_DMA_PAUSE 0x20000000 /* pause DMA */
131#define SSCR_PAUSE_STATE 0x40000000 /* set when PAUSE takes effect*/
132#define SSCR_RESET 0x80000000 /* reset DMA channels */
133
134/* all producer/comsumer pointers are the same bitfield */
135#define PROD_CONS_PTR_4K 0x00000ff8 /* for 4K buffers */
136#define PROD_CONS_PTR_1K 0x000003f8 /* for 1K buffers */
137#define PROD_CONS_PTR_OFF 3
138
139/* bitmasks for SRCIR_<A:B> */
140#define SRCIR_ARM 0x80000000 /* arm RX timer */
141
142/* bitmasks for SHADOW_<A:B> */
143#define SHADOW_DR 0x00000001 /* data ready */
144#define SHADOW_OE 0x00000002 /* overrun error */
145#define SHADOW_PE 0x00000004 /* parity error */
146#define SHADOW_FE 0x00000008 /* framing error */
147#define SHADOW_BI 0x00000010 /* break interrupt */
148#define SHADOW_THRE 0x00000020 /* transmit holding reg empty */
149#define SHADOW_TEMT 0x00000040 /* transmit shift reg empty */
150#define SHADOW_RFCE 0x00000080 /* char in RX fifo has error */
151#define SHADOW_DCTS 0x00010000 /* delta clear to send */
152#define SHADOW_DDCD 0x00080000 /* delta data carrier detect */
153#define SHADOW_CTS 0x00100000 /* clear to send */
154#define SHADOW_DCD 0x00800000 /* data carrier detect */
155#define SHADOW_DTR 0x01000000 /* data terminal ready */
156#define SHADOW_RTS 0x02000000 /* request to send */
157#define SHADOW_OUT1 0x04000000 /* 16550 OUT1 bit */
158#define SHADOW_OUT2 0x08000000 /* 16550 OUT2 bit */
159#define SHADOW_LOOP 0x10000000 /* loopback enabled */
160
161/* bitmasks for SRTR_<A:B> */
162#define SRTR_CNT 0x00000fff /* reload value for RX timer */
163#define SRTR_CNT_VAL 0x0fff0000 /* current value of RX timer */
164#define SRTR_CNT_VAL_SHIFT 16
165#define SRTR_HZ 16000 /* SRTR clock frequency */
166
167/* bitmasks for SIO_IR, SIO_IEC and SIO_IES */
168#define SIO_IR_SA_TX_MT 0x00000001 /* Serial port A TX empty */
169#define SIO_IR_SA_RX_FULL 0x00000002 /* port A RX buf full */
170#define SIO_IR_SA_RX_HIGH 0x00000004 /* port A RX hiwat */
171#define SIO_IR_SA_RX_TIMER 0x00000008 /* port A RX timeout */
172#define SIO_IR_SA_DELTA_DCD 0x00000010 /* port A delta DCD */
173#define SIO_IR_SA_DELTA_CTS 0x00000020 /* port A delta CTS */
174#define SIO_IR_SA_INT 0x00000040 /* port A pass-thru intr */
175#define SIO_IR_SA_TX_EXPLICIT 0x00000080 /* port A explicit TX thru */
176#define SIO_IR_SA_MEMERR 0x00000100 /* port A PCI error */
177#define SIO_IR_SB_TX_MT 0x00000200
178#define SIO_IR_SB_RX_FULL 0x00000400
179#define SIO_IR_SB_RX_HIGH 0x00000800
180#define SIO_IR_SB_RX_TIMER 0x00001000
181#define SIO_IR_SB_DELTA_DCD 0x00002000
182#define SIO_IR_SB_DELTA_CTS 0x00004000
183#define SIO_IR_SB_INT 0x00008000
184#define SIO_IR_SB_TX_EXPLICIT 0x00010000
185#define SIO_IR_SB_MEMERR 0x00020000
186#define SIO_IR_PP_INT 0x00040000 /* P port pass-thru intr */
187#define SIO_IR_PP_INTA 0x00080000 /* PP context A thru */
188#define SIO_IR_PP_INTB 0x00100000 /* PP context B thru */
189#define SIO_IR_PP_MEMERR 0x00200000 /* PP PCI error */
190#define SIO_IR_KBD_INT 0x00400000 /* kbd/mouse intr */
191#define SIO_IR_RT_INT 0x08000000 /* RT output pulse */
192#define SIO_IR_GEN_INT1 0x10000000 /* RT input pulse */
193#define SIO_IR_GEN_INT_SHIFT 28
194
195/* per device interrupt masks */
196#define SIO_IR_SA (SIO_IR_SA_TX_MT | \
197 SIO_IR_SA_RX_FULL | \
198 SIO_IR_SA_RX_HIGH | \
199 SIO_IR_SA_RX_TIMER | \
200 SIO_IR_SA_DELTA_DCD | \
201 SIO_IR_SA_DELTA_CTS | \
202 SIO_IR_SA_INT | \
203 SIO_IR_SA_TX_EXPLICIT | \
204 SIO_IR_SA_MEMERR)
205
206#define SIO_IR_SB (SIO_IR_SB_TX_MT | \
207 SIO_IR_SB_RX_FULL | \
208 SIO_IR_SB_RX_HIGH | \
209 SIO_IR_SB_RX_TIMER | \
210 SIO_IR_SB_DELTA_DCD | \
211 SIO_IR_SB_DELTA_CTS | \
212 SIO_IR_SB_INT | \
213 SIO_IR_SB_TX_EXPLICIT | \
214 SIO_IR_SB_MEMERR)
215
216#define SIO_IR_PP (SIO_IR_PP_INT | SIO_IR_PP_INTA | \
217 SIO_IR_PP_INTB | SIO_IR_PP_MEMERR)
218#define SIO_IR_RT (SIO_IR_RT_INT | SIO_IR_GEN_INT1)
219
220/* bitmasks for SIO_CR */
221#define SIO_CR_CMD_PULSE_SHIFT 15
222#define SIO_CR_SER_A_BASE_SHIFT 1
223#define SIO_CR_SER_B_BASE_SHIFT 8
224#define SIO_CR_ARB_DIAG 0x00380000 /* cur !enet PCI requet (ro) */
225#define SIO_CR_ARB_DIAG_TXA 0x00000000
226#define SIO_CR_ARB_DIAG_RXA 0x00080000
227#define SIO_CR_ARB_DIAG_TXB 0x00100000
228#define SIO_CR_ARB_DIAG_RXB 0x00180000
229#define SIO_CR_ARB_DIAG_PP 0x00200000
230#define SIO_CR_ARB_DIAG_IDLE 0x00400000 /* 0 -> active request (ro) */
231
232/* defs for some of the generic I/O pins */
233#define GPCR_PHY_RESET 0x20 /* pin is output to PHY reset */
234#define GPCR_UARTB_MODESEL 0x40 /* pin is output to port B mode sel */
235#define GPCR_UARTA_MODESEL 0x80 /* pin is output to port A mode sel */
236
237#define GPPR_PHY_RESET_PIN 5 /* GIO pin controlling phy reset */
238#define GPPR_UARTB_MODESEL_PIN 6 /* GIO pin cntrling uartb modeselect */
239#define GPPR_UARTA_MODESEL_PIN 7 /* GIO pin cntrling uarta modeselect */
240
241#endif /* IA64_SN_IOC3_H */
diff --git a/include/asm-ia64/sn/klconfig.h b/include/asm-ia64/sn/klconfig.h
deleted file mode 100644
index bcbf209d63b..00000000000
--- a/include/asm-ia64/sn/klconfig.h
+++ /dev/null
@@ -1,246 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Derived from IRIX <sys/SN/klconfig.h>.
7 *
8 * Copyright (C) 1992-1997,1999,2001-2004 Silicon Graphics, Inc. All Rights Reserved.
9 * Copyright (C) 1999 by Ralf Baechle
10 */
11#ifndef _ASM_IA64_SN_KLCONFIG_H
12#define _ASM_IA64_SN_KLCONFIG_H
13
14/*
15 * The KLCONFIG structures store info about the various BOARDs found
16 * during Hardware Discovery. In addition, it stores info about the
17 * components found on the BOARDs.
18 */
19
20typedef s32 klconf_off_t;
21
22
23/* Functions/macros needed to use this structure */
24
25typedef struct kl_config_hdr {
26 char pad[20];
27 klconf_off_t ch_board_info; /* the link list of boards */
28 char pad0[88];
29} kl_config_hdr_t;
30
31
32#define NODE_OFFSET_TO_LBOARD(nasid,off) (lboard_t*)(GLOBAL_CAC_ADDR((nasid), (off)))
33
34/*
35 * The KLCONFIG area is organized as a LINKED LIST of BOARDs. A BOARD
36 * can be either 'LOCAL' or 'REMOTE'. LOCAL means it is attached to
37 * the LOCAL/current NODE. REMOTE means it is attached to a different
38 * node.(TBD - Need a way to treat ROUTER boards.)
39 *
40 * There are 2 different structures to represent these boards -
41 * lboard - Local board, rboard - remote board. These 2 structures
42 * can be arbitrarily mixed in the LINKED LIST of BOARDs. (Refer
43 * Figure below). The first byte of the rboard or lboard structure
44 * is used to find out its type - no unions are used.
45 * If it is a lboard, then the config info of this board will be found
46 * on the local node. (LOCAL NODE BASE + offset value gives pointer to
47 * the structure.
48 * If it is a rboard, the local structure contains the node number
49 * and the offset of the beginning of the LINKED LIST on the remote node.
50 * The details of the hardware on a remote node can be built locally,
51 * if required, by reading the LINKED LIST on the remote node and
52 * ignoring all the rboards on that node.
53 *
54 * The local node uses the REMOTE NODE NUMBER + OFFSET to point to the
55 * First board info on the remote node. The remote node list is
56 * traversed as the local list, using the REMOTE BASE ADDRESS and not
57 * the local base address and ignoring all rboard values.
58 *
59 *
60 KLCONFIG
61
62 +------------+ +------------+ +------------+ +------------+
63 | lboard | +-->| lboard | +-->| rboard | +-->| lboard |
64 +------------+ | +------------+ | +------------+ | +------------+
65 | board info | | | board info | | |errinfo,bptr| | | board info |
66 +------------+ | +------------+ | +------------+ | +------------+
67 | offset |--+ | offset |--+ | offset |--+ |offset=NULL |
68 +------------+ +------------+ +------------+ +------------+
69
70
71 +------------+
72 | board info |
73 +------------+ +--------------------------------+
74 | compt 1 |------>| type, rev, diaginfo, size ... | (CPU)
75 +------------+ +--------------------------------+
76 | compt 2 |--+
77 +------------+ | +--------------------------------+
78 | ... | +--->| type, rev, diaginfo, size ... | (MEM_BANK)
79 +------------+ +--------------------------------+
80 | errinfo |--+
81 +------------+ | +--------------------------------+
82 +--->|r/l brd errinfo,compt err flags |
83 +--------------------------------+
84
85 *
86 * Each BOARD consists of COMPONENTs and the BOARD structure has
87 * pointers (offsets) to its COMPONENT structure.
88 * The COMPONENT structure has version info, size and speed info, revision,
89 * error info and the NIC info. This structure can accommodate any
90 * BOARD with arbitrary COMPONENT composition.
91 *
92 * The ERRORINFO part of each BOARD has error information
93 * that describes errors about the BOARD itself. It also has flags to
94 * indicate the COMPONENT(s) on the board that have errors. The error
95 * information specific to the COMPONENT is present in the respective
96 * COMPONENT structure.
97 *
98 * The ERRORINFO structure is also treated like a COMPONENT, ie. the
99 * BOARD has pointers(offset) to the ERRORINFO structure. The rboard
100 * structure also has a pointer to the ERRORINFO structure. This is
101 * the place to store ERRORINFO about a REMOTE NODE, if the HUB on
102 * that NODE is not working or if the REMOTE MEMORY is BAD. In cases where
103 * only the CPU of the REMOTE NODE is disabled, the ERRORINFO pointer can
104 * be a NODE NUMBER, REMOTE OFFSET combination, pointing to error info
105 * which is present on the REMOTE NODE.(TBD)
106 * REMOTE ERRINFO can be stored on any of the nearest nodes
107 * or on all the nearest nodes.(TBD)
108 * Like BOARD structures, REMOTE ERRINFO structures can be built locally
109 * using the rboard errinfo pointer.
110 *
111 * In order to get useful information from this Data organization, a set of
112 * interface routines are provided (TBD). The important thing to remember while
113 * manipulating the structures, is that, the NODE number information should
114 * be used. If the NODE is non-zero (remote) then each offset should
115 * be added to the REMOTE BASE ADDR else it should be added to the LOCAL BASE ADDR.
116 * This includes offsets for BOARDS, COMPONENTS and ERRORINFO.
117 *
118 * Note that these structures do not provide much info about connectivity.
119 * That info will be part of HWGRAPH, which is an extension of the cfg_t
120 * data structure. (ref IP27prom/cfg.h) It has to be extended to include
121 * the IO part of the Network(TBD).
122 *
123 * The data structures below define the above concepts.
124 */
125
126
127/*
128 * BOARD classes
129 */
130
131#define KLCLASS_MASK 0xf0
132#define KLCLASS_NONE 0x00
133#define KLCLASS_NODE 0x10 /* CPU, Memory and HUB board */
134#define KLCLASS_CPU KLCLASS_NODE
135#define KLCLASS_IO 0x20 /* BaseIO, 4 ch SCSI, ethernet, FDDI
136 and the non-graphics widget boards */
137#define KLCLASS_ROUTER 0x30 /* Router board */
138#define KLCLASS_MIDPLANE 0x40 /* We need to treat this as a board
139 so that we can record error info */
140#define KLCLASS_IOBRICK 0x70 /* IP35 iobrick */
141#define KLCLASS_MAX 8 /* Bump this if a new CLASS is added */
142
143#define KLCLASS(_x) ((_x) & KLCLASS_MASK)
144
145
146/*
147 * board types
148 */
149
150#define KLTYPE_MASK 0x0f
151#define KLTYPE(_x) ((_x) & KLTYPE_MASK)
152
153#define KLTYPE_SNIA (KLCLASS_CPU | 0x1)
154#define KLTYPE_TIO (KLCLASS_CPU | 0x2)
155
156#define KLTYPE_ROUTER (KLCLASS_ROUTER | 0x1)
157#define KLTYPE_META_ROUTER (KLCLASS_ROUTER | 0x3)
158#define KLTYPE_REPEATER_ROUTER (KLCLASS_ROUTER | 0x4)
159
160#define KLTYPE_IOBRICK_XBOW (KLCLASS_MIDPLANE | 0x2)
161
162#define KLTYPE_IOBRICK (KLCLASS_IOBRICK | 0x0)
163#define KLTYPE_NBRICK (KLCLASS_IOBRICK | 0x4)
164#define KLTYPE_PXBRICK (KLCLASS_IOBRICK | 0x6)
165#define KLTYPE_IXBRICK (KLCLASS_IOBRICK | 0x7)
166#define KLTYPE_CGBRICK (KLCLASS_IOBRICK | 0x8)
167#define KLTYPE_OPUSBRICK (KLCLASS_IOBRICK | 0x9)
168#define KLTYPE_SABRICK (KLCLASS_IOBRICK | 0xa)
169#define KLTYPE_IABRICK (KLCLASS_IOBRICK | 0xb)
170#define KLTYPE_PABRICK (KLCLASS_IOBRICK | 0xc)
171#define KLTYPE_GABRICK (KLCLASS_IOBRICK | 0xd)
172
173
174/*
175 * board structures
176 */
177
178#define MAX_COMPTS_PER_BRD 24
179
180typedef struct lboard_s {
181 klconf_off_t brd_next_any; /* Next BOARD */
182 unsigned char struct_type; /* type of structure, local or remote */
183 unsigned char brd_type; /* type+class */
184 unsigned char brd_sversion; /* version of this structure */
185 unsigned char brd_brevision; /* board revision */
186 unsigned char brd_promver; /* board prom version, if any */
187 unsigned char brd_flags; /* Enabled, Disabled etc */
188 unsigned char brd_slot; /* slot number */
189 unsigned short brd_debugsw; /* Debug switches */
190 geoid_t brd_geoid; /* geo id */
191 partid_t brd_partition; /* Partition number */
192 unsigned short brd_diagval; /* diagnostic value */
193 unsigned short brd_diagparm; /* diagnostic parameter */
194 unsigned char brd_inventory; /* inventory history */
195 unsigned char brd_numcompts; /* Number of components */
196 nic_t brd_nic; /* Number in CAN */
197 nasid_t brd_nasid; /* passed parameter */
198 klconf_off_t brd_compts[MAX_COMPTS_PER_BRD]; /* pointers to COMPONENTS */
199 klconf_off_t brd_errinfo; /* Board's error information */
200 struct lboard_s *brd_parent; /* Logical parent for this brd */
201 char pad0[4];
202 unsigned char brd_confidence; /* confidence that the board is bad */
203 nasid_t brd_owner; /* who owns this board */
204 unsigned char brd_nic_flags; /* To handle 8 more NICs */
205 char pad1[24]; /* future expansion */
206 char brd_name[32];
207 nasid_t brd_next_same_host; /* host of next brd w/same nasid */
208 klconf_off_t brd_next_same; /* Next BOARD with same nasid */
209} lboard_t;
210
211/*
212 * Generic info structure. This stores common info about a
213 * component.
214 */
215
216typedef struct klinfo_s { /* Generic info */
217 unsigned char struct_type; /* type of this structure */
218 unsigned char struct_version; /* version of this structure */
219 unsigned char flags; /* Enabled, disabled etc */
220 unsigned char revision; /* component revision */
221 unsigned short diagval; /* result of diagnostics */
222 unsigned short diagparm; /* diagnostic parameter */
223 unsigned char inventory; /* previous inventory status */
224 unsigned short partid; /* widget part number */
225 nic_t nic; /* MUst be aligned properly */
226 unsigned char physid; /* physical id of component */
227 unsigned int virtid; /* virtual id as seen by system */
228 unsigned char widid; /* Widget id - if applicable */
229 nasid_t nasid; /* node number - from parent */
230 char pad1; /* pad out structure. */
231 char pad2; /* pad out structure. */
232 void *data;
233 klconf_off_t errinfo; /* component specific errors */
234 unsigned short pad3; /* pci fields have moved over to */
235 unsigned short pad4; /* klbri_t */
236} klinfo_t ;
237
238
239static inline lboard_t *find_lboard_next(lboard_t * brd)
240{
241 if (brd && brd->brd_next_any)
242 return NODE_OFFSET_TO_LBOARD(NASID_GET(brd), brd->brd_next_any);
243 return NULL;
244}
245
246#endif /* _ASM_IA64_SN_KLCONFIG_H */
diff --git a/include/asm-ia64/sn/l1.h b/include/asm-ia64/sn/l1.h
deleted file mode 100644
index 344bf44bb35..00000000000
--- a/include/asm-ia64/sn/l1.h
+++ /dev/null
@@ -1,51 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992-1997,2000-2004 Silicon Graphics, Inc. All Rights Reserved.
7 */
8
9#ifndef _ASM_IA64_SN_L1_H
10#define _ASM_IA64_SN_L1_H
11
12/* brick type response codes */
13#define L1_BRICKTYPE_PX 0x23 /* # */
14#define L1_BRICKTYPE_PE 0x25 /* % */
15#define L1_BRICKTYPE_N_p0 0x26 /* & */
16#define L1_BRICKTYPE_IP45 0x34 /* 4 */
17#define L1_BRICKTYPE_IP41 0x35 /* 5 */
18#define L1_BRICKTYPE_TWISTER 0x36 /* 6 */ /* IP53 & ROUTER */
19#define L1_BRICKTYPE_IX 0x3d /* = */
20#define L1_BRICKTYPE_IP34 0x61 /* a */
21#define L1_BRICKTYPE_GA 0x62 /* b */
22#define L1_BRICKTYPE_C 0x63 /* c */
23#define L1_BRICKTYPE_OPUS_TIO 0x66 /* f */
24#define L1_BRICKTYPE_I 0x69 /* i */
25#define L1_BRICKTYPE_N 0x6e /* n */
26#define L1_BRICKTYPE_OPUS 0x6f /* o */
27#define L1_BRICKTYPE_P 0x70 /* p */
28#define L1_BRICKTYPE_R 0x72 /* r */
29#define L1_BRICKTYPE_CHI_CG 0x76 /* v */
30#define L1_BRICKTYPE_X 0x78 /* x */
31#define L1_BRICKTYPE_X2 0x79 /* y */
32#define L1_BRICKTYPE_SA 0x5e /* ^ */
33#define L1_BRICKTYPE_PA 0x6a /* j */
34#define L1_BRICKTYPE_IA 0x6b /* k */
35#define L1_BRICKTYPE_ATHENA 0x2b /* + */
36#define L1_BRICKTYPE_DAYTONA 0x7a /* z */
37#define L1_BRICKTYPE_1932 0x2c /* . */
38#define L1_BRICKTYPE_191010 0x2e /* , */
39
40/* board type response codes */
41#define L1_BOARDTYPE_IP69 0x0100 /* CA */
42#define L1_BOARDTYPE_IP63 0x0200 /* CB */
43#define L1_BOARDTYPE_BASEIO 0x0300 /* IB */
44#define L1_BOARDTYPE_PCIE2SLOT 0x0400 /* IC */
45#define L1_BOARDTYPE_PCIX3SLOT 0x0500 /* ID */
46#define L1_BOARDTYPE_PCIXPCIE4SLOT 0x0600 /* IE */
47#define L1_BOARDTYPE_ABACUS 0x0700 /* AB */
48#define L1_BOARDTYPE_DAYTONA 0x0800 /* AD */
49#define L1_BOARDTYPE_INVAL (-1) /* invalid brick type */
50
51#endif /* _ASM_IA64_SN_L1_H */
diff --git a/include/asm-ia64/sn/leds.h b/include/asm-ia64/sn/leds.h
deleted file mode 100644
index 66cf8c4d92c..00000000000
--- a/include/asm-ia64/sn/leds.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
6 */
7#ifndef _ASM_IA64_SN_LEDS_H
8#define _ASM_IA64_SN_LEDS_H
9
10#include <asm/sn/addrs.h>
11#include <asm/sn/pda.h>
12#include <asm/sn/shub_mmr.h>
13
14#define LED0 (LOCAL_MMR_ADDR(SH_REAL_JUNK_BUS_LED0))
15#define LED_CPU_SHIFT 16
16
17#define LED_CPU_HEARTBEAT 0x01
18#define LED_CPU_ACTIVITY 0x02
19#define LED_ALWAYS_SET 0x00
20
21/*
22 * Basic macros for flashing the LEDS on an SGI SN.
23 */
24
25static __inline__ void
26set_led_bits(u8 value, u8 mask)
27{
28 pda->led_state = (pda->led_state & ~mask) | (value & mask);
29 *pda->led_address = (short) pda->led_state;
30}
31
32#endif /* _ASM_IA64_SN_LEDS_H */
33
diff --git a/include/asm-ia64/sn/module.h b/include/asm-ia64/sn/module.h
deleted file mode 100644
index 734e980ece2..00000000000
--- a/include/asm-ia64/sn/module.h
+++ /dev/null
@@ -1,127 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_MODULE_H
9#define _ASM_IA64_SN_MODULE_H
10
11/* parameter for format_module_id() */
12#define MODULE_FORMAT_BRIEF 1
13#define MODULE_FORMAT_LONG 2
14#define MODULE_FORMAT_LCD 3
15
16/*
17 * Module id format
18 *
19 * 31-16 Rack ID (encoded class, group, number - 16-bit unsigned int)
20 * 15-8 Brick type (8-bit ascii character)
21 * 7-0 Bay (brick position in rack (0-63) - 8-bit unsigned int)
22 *
23 */
24
25/*
26 * Macros for getting the brick type
27 */
28#define MODULE_BTYPE_MASK 0xff00
29#define MODULE_BTYPE_SHFT 8
30#define MODULE_GET_BTYPE(_m) (((_m) & MODULE_BTYPE_MASK) >> MODULE_BTYPE_SHFT)
31#define MODULE_BT_TO_CHAR(_b) ((char)(_b))
32#define MODULE_GET_BTCHAR(_m) (MODULE_BT_TO_CHAR(MODULE_GET_BTYPE(_m)))
33
34/*
35 * Macros for getting the rack ID.
36 */
37#define MODULE_RACK_MASK 0xffff0000
38#define MODULE_RACK_SHFT 16
39#define MODULE_GET_RACK(_m) (((_m) & MODULE_RACK_MASK) >> MODULE_RACK_SHFT)
40
41/*
42 * Macros for getting the brick position
43 */
44#define MODULE_BPOS_MASK 0x00ff
45#define MODULE_BPOS_SHFT 0
46#define MODULE_GET_BPOS(_m) (((_m) & MODULE_BPOS_MASK) >> MODULE_BPOS_SHFT)
47
48/*
49 * Macros for encoding and decoding rack IDs
50 * A rack number consists of three parts:
51 * class (0==CPU/mixed, 1==I/O), group, number
52 *
53 * Rack number is stored just as it is displayed on the screen:
54 * a 3-decimal-digit number.
55 */
56#define RACK_CLASS_DVDR 100
57#define RACK_GROUP_DVDR 10
58#define RACK_NUM_DVDR 1
59
60#define RACK_CREATE_RACKID(_c, _g, _n) ((_c) * RACK_CLASS_DVDR + \
61 (_g) * RACK_GROUP_DVDR + (_n) * RACK_NUM_DVDR)
62
63#define RACK_GET_CLASS(_r) ((_r) / RACK_CLASS_DVDR)
64#define RACK_GET_GROUP(_r) (((_r) - RACK_GET_CLASS(_r) * \
65 RACK_CLASS_DVDR) / RACK_GROUP_DVDR)
66#define RACK_GET_NUM(_r) (((_r) - RACK_GET_CLASS(_r) * \
67 RACK_CLASS_DVDR - RACK_GET_GROUP(_r) * \
68 RACK_GROUP_DVDR) / RACK_NUM_DVDR)
69
70/*
71 * Macros for encoding and decoding rack IDs
72 * A rack number consists of three parts:
73 * class 1 bit, 0==CPU/mixed, 1==I/O
74 * group 2 bits for CPU/mixed, 3 bits for I/O
75 * number 3 bits for CPU/mixed, 2 bits for I/O (1 based)
76 */
77#define RACK_GROUP_BITS(_r) (RACK_GET_CLASS(_r) ? 3 : 2)
78#define RACK_NUM_BITS(_r) (RACK_GET_CLASS(_r) ? 2 : 3)
79
80#define RACK_CLASS_MASK(_r) 0x20
81#define RACK_CLASS_SHFT(_r) 5
82#define RACK_ADD_CLASS(_r, _c) \
83 ((_r) |= (_c) << RACK_CLASS_SHFT(_r) & RACK_CLASS_MASK(_r))
84
85#define RACK_GROUP_SHFT(_r) RACK_NUM_BITS(_r)
86#define RACK_GROUP_MASK(_r) \
87 ( (((unsigned)1<<RACK_GROUP_BITS(_r)) - 1) << RACK_GROUP_SHFT(_r) )
88#define RACK_ADD_GROUP(_r, _g) \
89 ((_r) |= (_g) << RACK_GROUP_SHFT(_r) & RACK_GROUP_MASK(_r))
90
91#define RACK_NUM_SHFT(_r) 0
92#define RACK_NUM_MASK(_r) \
93 ( (((unsigned)1<<RACK_NUM_BITS(_r)) - 1) << RACK_NUM_SHFT(_r) )
94#define RACK_ADD_NUM(_r, _n) \
95 ((_r) |= ((_n) - 1) << RACK_NUM_SHFT(_r) & RACK_NUM_MASK(_r))
96
97
98/*
99 * Brick type definitions
100 */
101#define MAX_BRICK_TYPES 256 /* brick type is stored as uchar */
102
103extern char brick_types[];
104
105#define MODULE_CBRICK 0
106#define MODULE_RBRICK 1
107#define MODULE_IBRICK 2
108#define MODULE_KBRICK 3
109#define MODULE_XBRICK 4
110#define MODULE_DBRICK 5
111#define MODULE_PBRICK 6
112#define MODULE_NBRICK 7
113#define MODULE_PEBRICK 8
114#define MODULE_PXBRICK 9
115#define MODULE_IXBRICK 10
116#define MODULE_CGBRICK 11
117#define MODULE_OPUSBRICK 12
118#define MODULE_SABRICK 13 /* TIO BringUp Brick */
119#define MODULE_IABRICK 14
120#define MODULE_PABRICK 15
121#define MODULE_GABRICK 16
122#define MODULE_OPUS_TIO 17 /* OPUS TIO Riser */
123
124extern char brick_types[];
125extern void format_module_id(char *, moduleid_t, int);
126
127#endif /* _ASM_IA64_SN_MODULE_H */
diff --git a/include/asm-ia64/sn/mspec.h b/include/asm-ia64/sn/mspec.h
deleted file mode 100644
index dbe13c6121a..00000000000
--- a/include/asm-ia64/sn/mspec.h
+++ /dev/null
@@ -1,59 +0,0 @@
1/*
2 *
3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
5 * for more details.
6 *
7 * Copyright (c) 2001-2004 Silicon Graphics, Inc. All rights reserved.
8 */
9
10#ifndef _ASM_IA64_SN_MSPEC_H
11#define _ASM_IA64_SN_MSPEC_H
12
13#define FETCHOP_VAR_SIZE 64 /* 64 byte per fetchop variable */
14
15#define FETCHOP_LOAD 0
16#define FETCHOP_INCREMENT 8
17#define FETCHOP_DECREMENT 16
18#define FETCHOP_CLEAR 24
19
20#define FETCHOP_STORE 0
21#define FETCHOP_AND 24
22#define FETCHOP_OR 32
23
24#define FETCHOP_CLEAR_CACHE 56
25
26#define FETCHOP_LOAD_OP(addr, op) ( \
27 *(volatile long *)((char*) (addr) + (op)))
28
29#define FETCHOP_STORE_OP(addr, op, x) ( \
30 *(volatile long *)((char*) (addr) + (op)) = (long) (x))
31
32#ifdef __KERNEL__
33
34/*
35 * Each Atomic Memory Operation (AMO formerly known as fetchop)
36 * variable is 64 bytes long. The first 8 bytes are used. The
37 * remaining 56 bytes are unaddressable due to the operation taking
38 * that portion of the address.
39 *
40 * NOTE: The AMO_t _MUST_ be placed in either the first or second half
41 * of the cache line. The cache line _MUST NOT_ be used for anything
42 * other than additional AMO_t entries. This is because there are two
43 * addresses which reference the same physical cache line. One will
44 * be a cached entry with the memory type bits all set. This address
45 * may be loaded into processor cache. The AMO_t will be referenced
46 * uncached via the memory special memory type. If any portion of the
47 * cached cache-line is modified, when that line is flushed, it will
48 * overwrite the uncached value in physical memory and lead to
49 * inconsistency.
50 */
51typedef struct {
52 u64 variable;
53 u64 unused[7];
54} AMO_t;
55
56
57#endif /* __KERNEL__ */
58
59#endif /* _ASM_IA64_SN_MSPEC_H */
diff --git a/include/asm-ia64/sn/nodepda.h b/include/asm-ia64/sn/nodepda.h
deleted file mode 100644
index ee118b901de..00000000000
--- a/include/asm-ia64/sn/nodepda.h
+++ /dev/null
@@ -1,82 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_NODEPDA_H
9#define _ASM_IA64_SN_NODEPDA_H
10
11
12#include <asm/irq.h>
13#include <asm/sn/arch.h>
14#include <asm/sn/intr.h>
15#include <asm/sn/bte.h>
16
17/*
18 * NUMA Node-Specific Data structures are defined in this file.
19 * In particular, this is the location of the node PDA.
20 * A pointer to the right node PDA is saved in each CPU PDA.
21 */
22
23/*
24 * Node-specific data structure.
25 *
26 * One of these structures is allocated on each node of a NUMA system.
27 *
28 * This structure provides a convenient way of keeping together
29 * all per-node data structures.
30 */
31struct phys_cpuid {
32 short nasid;
33 char subnode;
34 char slice;
35};
36
37struct nodepda_s {
38 void *pdinfo; /* Platform-dependent per-node info */
39
40 /*
41 * The BTEs on this node are shared by the local cpus
42 */
43 struct bteinfo_s bte_if[MAX_BTES_PER_NODE]; /* Virtual Interface */
44 struct timer_list bte_recovery_timer;
45 spinlock_t bte_recovery_lock;
46
47 /*
48 * Array of pointers to the nodepdas for each node.
49 */
50 struct nodepda_s *pernode_pdaindr[MAX_COMPACT_NODES];
51
52 /*
53 * Array of physical cpu identifiers. Indexed by cpuid.
54 */
55 struct phys_cpuid phys_cpuid[NR_CPUS];
56 spinlock_t ptc_lock ____cacheline_aligned_in_smp;
57};
58
59typedef struct nodepda_s nodepda_t;
60
61/*
62 * Access Functions for node PDA.
63 * Since there is one nodepda for each node, we need a convenient mechanism
64 * to access these nodepdas without cluttering code with #ifdefs.
65 * The next set of definitions provides this.
66 * Routines are expected to use
67 *
68 * sn_nodepda - to access node PDA for the node on which code is running
69 * NODEPDA(cnodeid) - to access node PDA for cnodeid
70 */
71
72DECLARE_PER_CPU(struct nodepda_s *, __sn_nodepda);
73#define sn_nodepda (__get_cpu_var(__sn_nodepda))
74#define NODEPDA(cnodeid) (sn_nodepda->pernode_pdaindr[cnodeid])
75
76/*
77 * Check if given a compact node id the corresponding node has all the
78 * cpus disabled.
79 */
80#define is_headless_node(cnodeid) (nr_cpus_node(cnodeid) == 0)
81
82#endif /* _ASM_IA64_SN_NODEPDA_H */
diff --git a/include/asm-ia64/sn/pcibr_provider.h b/include/asm-ia64/sn/pcibr_provider.h
deleted file mode 100644
index da205b7cdaa..00000000000
--- a/include/asm-ia64/sn/pcibr_provider.h
+++ /dev/null
@@ -1,150 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992-1997,2000-2006 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
9#define _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
10
11#include <asm/sn/intr.h>
12#include <asm/sn/pcibus_provider_defs.h>
13
14/* Workarounds */
15#define PV907516 (1 << 1) /* TIOCP: Don't write the write buffer flush reg */
16
17#define BUSTYPE_MASK 0x1
18
19/* Macros given a pcibus structure */
20#define IS_PCIX(ps) ((ps)->pbi_bridge_mode & BUSTYPE_MASK)
21#define IS_PCI_BRIDGE_ASIC(asic) (asic == PCIIO_ASIC_TYPE_PIC || \
22 asic == PCIIO_ASIC_TYPE_TIOCP)
23#define IS_PIC_SOFT(ps) (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_PIC)
24#define IS_TIOCP_SOFT(ps) (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_TIOCP)
25
26
27/*
28 * The different PCI Bridge types supported on the SGI Altix platforms
29 */
30#define PCIBR_BRIDGETYPE_UNKNOWN -1
31#define PCIBR_BRIDGETYPE_PIC 2
32#define PCIBR_BRIDGETYPE_TIOCP 3
33
34/*
35 * Bridge 64bit Direct Map Attributes
36 */
37#define PCI64_ATTR_PREF (1ull << 59)
38#define PCI64_ATTR_PREC (1ull << 58)
39#define PCI64_ATTR_VIRTUAL (1ull << 57)
40#define PCI64_ATTR_BAR (1ull << 56)
41#define PCI64_ATTR_SWAP (1ull << 55)
42#define PCI64_ATTR_VIRTUAL1 (1ull << 54)
43
44#define PCI32_LOCAL_BASE 0
45#define PCI32_MAPPED_BASE 0x40000000
46#define PCI32_DIRECT_BASE 0x80000000
47
48#define IS_PCI32_MAPPED(x) ((u64)(x) < PCI32_DIRECT_BASE && \
49 (u64)(x) >= PCI32_MAPPED_BASE)
50#define IS_PCI32_DIRECT(x) ((u64)(x) >= PCI32_MAPPED_BASE)
51
52
53/*
54 * Bridge PMU Address Transaltion Entry Attibutes
55 */
56#define PCI32_ATE_V (0x1 << 0)
57#define PCI32_ATE_CO (0x1 << 1) /* PIC ASIC ONLY */
58#define PCI32_ATE_PIO (0x1 << 1) /* TIOCP ASIC ONLY */
59#define PCI32_ATE_MSI (0x1 << 2)
60#define PCI32_ATE_PREF (0x1 << 3)
61#define PCI32_ATE_BAR (0x1 << 4)
62#define PCI32_ATE_ADDR_SHFT 12
63
64#define MINIMAL_ATES_REQUIRED(addr, size) \
65 (IOPG(IOPGOFF(addr) + (size) - 1) == IOPG((size) - 1))
66
67#define MINIMAL_ATE_FLAG(addr, size) \
68 (MINIMAL_ATES_REQUIRED((u64)addr, size) ? 1 : 0)
69
70/* bit 29 of the pci address is the SWAP bit */
71#define ATE_SWAPSHIFT 29
72#define ATE_SWAP_ON(x) ((x) |= (1 << ATE_SWAPSHIFT))
73#define ATE_SWAP_OFF(x) ((x) &= ~(1 << ATE_SWAPSHIFT))
74
75/*
76 * I/O page size
77 */
78#if PAGE_SIZE < 16384
79#define IOPFNSHIFT 12 /* 4K per mapped page */
80#else
81#define IOPFNSHIFT 14 /* 16K per mapped page */
82#endif
83
84#define IOPGSIZE (1 << IOPFNSHIFT)
85#define IOPG(x) ((x) >> IOPFNSHIFT)
86#define IOPGOFF(x) ((x) & (IOPGSIZE-1))
87
88#define PCIBR_DEV_SWAP_DIR (1ull << 19)
89#define PCIBR_CTRL_PAGE_SIZE (0x1 << 21)
90
91/*
92 * PMU resources.
93 */
94struct ate_resource{
95 u64 *ate;
96 u64 num_ate;
97 u64 lowest_free_index;
98};
99
100struct pcibus_info {
101 struct pcibus_bussoft pbi_buscommon; /* common header */
102 u32 pbi_moduleid;
103 short pbi_bridge_type;
104 short pbi_bridge_mode;
105
106 struct ate_resource pbi_int_ate_resource;
107 u64 pbi_int_ate_size;
108
109 u64 pbi_dir_xbase;
110 char pbi_hub_xid;
111
112 u64 pbi_devreg[8];
113
114 u32 pbi_valid_devices;
115 u32 pbi_enabled_devices;
116
117 spinlock_t pbi_lock;
118};
119
120extern int pcibr_init_provider(void);
121extern void *pcibr_bus_fixup(struct pcibus_bussoft *, struct pci_controller *);
122extern dma_addr_t pcibr_dma_map(struct pci_dev *, unsigned long, size_t, int type);
123extern dma_addr_t pcibr_dma_map_consistent(struct pci_dev *, unsigned long, size_t, int type);
124extern void pcibr_dma_unmap(struct pci_dev *, dma_addr_t, int);
125
126/*
127 * prototypes for the bridge asic register access routines in pcibr_reg.c
128 */
129extern void pcireg_control_bit_clr(struct pcibus_info *, u64);
130extern void pcireg_control_bit_set(struct pcibus_info *, u64);
131extern u64 pcireg_tflush_get(struct pcibus_info *);
132extern u64 pcireg_intr_status_get(struct pcibus_info *);
133extern void pcireg_intr_enable_bit_clr(struct pcibus_info *, u64);
134extern void pcireg_intr_enable_bit_set(struct pcibus_info *, u64);
135extern void pcireg_intr_addr_addr_set(struct pcibus_info *, int, u64);
136extern void pcireg_force_intr_set(struct pcibus_info *, int);
137extern u64 pcireg_wrb_flush_get(struct pcibus_info *, int);
138extern void pcireg_int_ate_set(struct pcibus_info *, int, u64);
139extern u64 __iomem * pcireg_int_ate_addr(struct pcibus_info *, int);
140extern void pcibr_force_interrupt(struct sn_irq_info *sn_irq_info);
141extern void pcibr_change_devices_irq(struct sn_irq_info *sn_irq_info);
142extern int pcibr_ate_alloc(struct pcibus_info *, int);
143extern void pcibr_ate_free(struct pcibus_info *, int);
144extern void ate_write(struct pcibus_info *, int, int, u64);
145extern int sal_pcibr_slot_enable(struct pcibus_info *soft, int device,
146 void *resp, char **ssdt);
147extern int sal_pcibr_slot_disable(struct pcibus_info *soft, int device,
148 int action, void *resp);
149extern u16 sn_ioboard_to_pci_bus(struct pci_bus *pci_bus);
150#endif
diff --git a/include/asm-ia64/sn/pcibus_provider_defs.h b/include/asm-ia64/sn/pcibus_provider_defs.h
deleted file mode 100644
index 8f7c83d0f6d..00000000000
--- a/include/asm-ia64/sn/pcibus_provider_defs.h
+++ /dev/null
@@ -1,68 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H
9#define _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H
10
11/*
12 * SN pci asic types. Do not ever renumber these or reuse values. The
13 * values must agree with what prom thinks they are.
14 */
15
16#define PCIIO_ASIC_TYPE_UNKNOWN 0
17#define PCIIO_ASIC_TYPE_PPB 1
18#define PCIIO_ASIC_TYPE_PIC 2
19#define PCIIO_ASIC_TYPE_TIOCP 3
20#define PCIIO_ASIC_TYPE_TIOCA 4
21#define PCIIO_ASIC_TYPE_TIOCE 5
22
23#define PCIIO_ASIC_MAX_TYPES 6
24
25/*
26 * Common pciio bus provider data. There should be one of these as the
27 * first field in any pciio based provider soft structure (e.g. pcibr_soft
28 * tioca_soft, etc).
29 */
30
31struct pcibus_bussoft {
32 u32 bs_asic_type; /* chipset type */
33 u32 bs_xid; /* xwidget id */
34 u32 bs_persist_busnum; /* Persistent Bus Number */
35 u32 bs_persist_segment; /* Segment Number */
36 u64 bs_legacy_io; /* legacy io pio addr */
37 u64 bs_legacy_mem; /* legacy mem pio addr */
38 u64 bs_base; /* widget base */
39 struct xwidget_info *bs_xwidget_info;
40};
41
42struct pci_controller;
43/*
44 * SN pci bus indirection
45 */
46
47struct sn_pcibus_provider {
48 dma_addr_t (*dma_map)(struct pci_dev *, unsigned long, size_t, int flags);
49 dma_addr_t (*dma_map_consistent)(struct pci_dev *, unsigned long, size_t, int flags);
50 void (*dma_unmap)(struct pci_dev *, dma_addr_t, int);
51 void * (*bus_fixup)(struct pcibus_bussoft *, struct pci_controller *);
52 void (*force_interrupt)(struct sn_irq_info *);
53 void (*target_interrupt)(struct sn_irq_info *);
54};
55
56/*
57 * Flags used by the map interfaces
58 * bits 3:0 specifies format of passed in address
59 * bit 4 specifies that address is to be used for MSI
60 */
61
62#define SN_DMA_ADDRTYPE(x) ((x) & 0xf)
63#define SN_DMA_ADDR_PHYS 1 /* address is an xio address. */
64#define SN_DMA_ADDR_XIO 2 /* address is phys memory */
65#define SN_DMA_MSI 0x10 /* Bus address is to be used for MSI */
66
67extern struct sn_pcibus_provider *sn_pci_provider[];
68#endif /* _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H */
diff --git a/include/asm-ia64/sn/pcidev.h b/include/asm-ia64/sn/pcidev.h
deleted file mode 100644
index 1c2382cea80..00000000000
--- a/include/asm-ia64/sn/pcidev.h
+++ /dev/null
@@ -1,85 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2006 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_PCI_PCIDEV_H
9#define _ASM_IA64_SN_PCI_PCIDEV_H
10
11#include <linux/pci.h>
12
13/*
14 * In ia64, pci_dev->sysdata must be a *pci_controller. To provide access to
15 * the pcidev_info structs for all devices under a controller, we keep a
16 * list of pcidev_info under pci_controller->platform_data.
17 */
18struct sn_platform_data {
19 void *provider_soft;
20 struct list_head pcidev_info;
21};
22
23#define SN_PLATFORM_DATA(busdev) \
24 ((struct sn_platform_data *)(PCI_CONTROLLER(busdev)->platform_data))
25
26#define SN_PCIDEV_INFO(dev) sn_pcidev_info_get(dev)
27
28/*
29 * Given a pci_bus, return the sn pcibus_bussoft struct. Note that
30 * this only works for root busses, not for busses represented by PPB's.
31 */
32
33#define SN_PCIBUS_BUSSOFT(pci_bus) \
34 ((struct pcibus_bussoft *)(SN_PLATFORM_DATA(pci_bus)->provider_soft))
35
36#define SN_PCIBUS_BUSSOFT_INFO(pci_bus) \
37 ((struct pcibus_info *)(SN_PLATFORM_DATA(pci_bus)->provider_soft))
38/*
39 * Given a struct pci_dev, return the sn pcibus_bussoft struct. Note
40 * that this is not equivalent to SN_PCIBUS_BUSSOFT(pci_dev->bus) due
41 * due to possible PPB's in the path.
42 */
43
44#define SN_PCIDEV_BUSSOFT(pci_dev) \
45 (SN_PCIDEV_INFO(pci_dev)->pdi_host_pcidev_info->pdi_pcibus_info)
46
47#define SN_PCIDEV_BUSPROVIDER(pci_dev) \
48 (SN_PCIDEV_INFO(pci_dev)->pdi_provider)
49
50#define PCIIO_BUS_NONE 255 /* bus 255 reserved */
51#define PCIIO_SLOT_NONE 255
52#define PCIIO_FUNC_NONE 255
53#define PCIIO_VENDOR_ID_NONE (-1)
54
55struct pcidev_info {
56 u64 pdi_pio_mapped_addr[7]; /* 6 BARs PLUS 1 ROM */
57 u64 pdi_slot_host_handle; /* Bus and devfn Host pci_dev */
58
59 struct pcibus_bussoft *pdi_pcibus_info; /* Kernel common bus soft */
60 struct pcidev_info *pdi_host_pcidev_info; /* Kernel Host pci_dev */
61 struct pci_dev *pdi_linux_pcidev; /* Kernel pci_dev */
62
63 struct sn_irq_info *pdi_sn_irq_info;
64 struct sn_pcibus_provider *pdi_provider; /* sn pci ops */
65 struct pci_dev *host_pci_dev; /* host bus link */
66 struct list_head pdi_list; /* List of pcidev_info */
67};
68
69extern void sn_irq_fixup(struct pci_dev *pci_dev,
70 struct sn_irq_info *sn_irq_info);
71extern void sn_irq_unfixup(struct pci_dev *pci_dev);
72extern struct pcidev_info * sn_pcidev_info_get(struct pci_dev *);
73extern void sn_bus_fixup(struct pci_bus *);
74extern void sn_acpi_bus_fixup(struct pci_bus *);
75extern void sn_common_bus_fixup(struct pci_bus *, struct pcibus_bussoft *);
76extern void sn_bus_store_sysdata(struct pci_dev *dev);
77extern void sn_bus_free_sysdata(void);
78extern void sn_generate_path(struct pci_bus *pci_bus, char *address);
79extern void sn_io_slot_fixup(struct pci_dev *);
80extern void sn_acpi_slot_fixup(struct pci_dev *);
81extern void sn_pci_fixup_slot(struct pci_dev *dev, struct pcidev_info *,
82 struct sn_irq_info *);
83extern void sn_pci_unfixup_slot(struct pci_dev *dev);
84extern void sn_irq_lh_init(void);
85#endif /* _ASM_IA64_SN_PCI_PCIDEV_H */
diff --git a/include/asm-ia64/sn/pda.h b/include/asm-ia64/sn/pda.h
deleted file mode 100644
index 1c5108d44d8..00000000000
--- a/include/asm-ia64/sn/pda.h
+++ /dev/null
@@ -1,69 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_PDA_H
9#define _ASM_IA64_SN_PDA_H
10
11#include <linux/cache.h>
12#include <asm/percpu.h>
13#include <asm/system.h>
14
15
16/*
17 * CPU-specific data structure.
18 *
19 * One of these structures is allocated for each cpu of a NUMA system.
20 *
21 * This structure provides a convenient way of keeping together
22 * all SN per-cpu data structures.
23 */
24
25typedef struct pda_s {
26
27 /*
28 * Support for SN LEDs
29 */
30 volatile short *led_address;
31 u8 led_state;
32 u8 hb_state; /* supports blinking heartbeat leds */
33 unsigned int hb_count;
34
35 unsigned int idle_flag;
36
37 volatile unsigned long *bedrock_rev_id;
38 volatile unsigned long *pio_write_status_addr;
39 unsigned long pio_write_status_val;
40 volatile unsigned long *pio_shub_war_cam_addr;
41
42 unsigned long sn_in_service_ivecs[4];
43 int sn_lb_int_war_ticks;
44 int sn_last_irq;
45 int sn_first_irq;
46} pda_t;
47
48
49#define CACHE_ALIGN(x) (((x) + SMP_CACHE_BYTES-1) & ~(SMP_CACHE_BYTES-1))
50
51/*
52 * PDA
53 * Per-cpu private data area for each cpu. The PDA is located immediately after
54 * the IA64 cpu_data area. A full page is allocated for the cp_data area for each
55 * cpu but only a small amout of the page is actually used. We put the SNIA PDA
56 * in the same page as the cpu_data area. Note that there is a check in the setup
57 * code to verify that we don't overflow the page.
58 *
59 * Seems like we should should cache-line align the pda so that any changes in the
60 * size of the cpu_data area don't change cache layout. Should we align to 32, 64, 128
61 * or 512 boundary. Each has merits. For now, pick 128 but should be revisited later.
62 */
63DECLARE_PER_CPU(struct pda_s, pda_percpu);
64
65#define pda (&__ia64_per_cpu_var(pda_percpu))
66
67#define pdacpu(cpu) (&per_cpu(pda_percpu, cpu))
68
69#endif /* _ASM_IA64_SN_PDA_H */
diff --git a/include/asm-ia64/sn/pic.h b/include/asm-ia64/sn/pic.h
deleted file mode 100644
index 5f9da5fd6e5..00000000000
--- a/include/asm-ia64/sn/pic.h
+++ /dev/null
@@ -1,261 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_PCI_PIC_H
9#define _ASM_IA64_SN_PCI_PIC_H
10
11/*
12 * PIC AS DEVICE ZERO
13 * ------------------
14 *
15 * PIC handles PCI/X busses. PCI/X requires that the 'bridge' (i.e. PIC)
16 * be designated as 'device 0'. That is a departure from earlier SGI
17 * PCI bridges. Because of that we use config space 1 to access the
18 * config space of the first actual PCI device on the bus.
19 * Here's what the PIC manual says:
20 *
21 * The current PCI-X bus specification now defines that the parent
22 * hosts bus bridge (PIC for example) must be device 0 on bus 0. PIC
23 * reduced the total number of devices from 8 to 4 and removed the
24 * device registers and windows, now only supporting devices 0,1,2, and
25 * 3. PIC did leave all 8 configuration space windows. The reason was
26 * there was nothing to gain by removing them. Here in lies the problem.
27 * The device numbering we do using 0 through 3 is unrelated to the device
28 * numbering which PCI-X requires in configuration space. In the past we
29 * correlated Configs pace and our device space 0 <-> 0, 1 <-> 1, etc.
30 * PCI-X requires we start a 1, not 0 and currently the PX brick
31 * does associate our:
32 *
33 * device 0 with configuration space window 1,
34 * device 1 with configuration space window 2,
35 * device 2 with configuration space window 3,
36 * device 3 with configuration space window 4.
37 *
38 * The net effect is that all config space access are off-by-one with
39 * relation to other per-slot accesses on the PIC.
40 * Here is a table that shows some of that:
41 *
42 * Internal Slot#
43 * |
44 * | 0 1 2 3
45 * ----------|---------------------------------------
46 * config | 0x21000 0x22000 0x23000 0x24000
47 * |
48 * even rrb | 0[0] n/a 1[0] n/a [] == implied even/odd
49 * |
50 * odd rrb | n/a 0[1] n/a 1[1]
51 * |
52 * int dev | 00 01 10 11
53 * |
54 * ext slot# | 1 2 3 4
55 * ----------|---------------------------------------
56 */
57
58#define PIC_ATE_TARGETID_SHFT 8
59#define PIC_HOST_INTR_ADDR 0x0000FFFFFFFFFFFFUL
60#define PIC_PCI64_ATTR_TARG_SHFT 60
61
62
63/*****************************************************************************
64 *********************** PIC MMR structure mapping ***************************
65 *****************************************************************************/
66
67/* NOTE: PIC WAR. PV#854697. PIC does not allow writes just to [31:0]
68 * of a 64-bit register. When writing PIC registers, always write the
69 * entire 64 bits.
70 */
71
72struct pic {
73
74 /* 0x000000-0x00FFFF -- Local Registers */
75
76 /* 0x000000-0x000057 -- Standard Widget Configuration */
77 u64 p_wid_id; /* 0x000000 */
78 u64 p_wid_stat; /* 0x000008 */
79 u64 p_wid_err_upper; /* 0x000010 */
80 u64 p_wid_err_lower; /* 0x000018 */
81 #define p_wid_err p_wid_err_lower
82 u64 p_wid_control; /* 0x000020 */
83 u64 p_wid_req_timeout; /* 0x000028 */
84 u64 p_wid_int_upper; /* 0x000030 */
85 u64 p_wid_int_lower; /* 0x000038 */
86 #define p_wid_int p_wid_int_lower
87 u64 p_wid_err_cmdword; /* 0x000040 */
88 u64 p_wid_llp; /* 0x000048 */
89 u64 p_wid_tflush; /* 0x000050 */
90
91 /* 0x000058-0x00007F -- Bridge-specific Widget Configuration */
92 u64 p_wid_aux_err; /* 0x000058 */
93 u64 p_wid_resp_upper; /* 0x000060 */
94 u64 p_wid_resp_lower; /* 0x000068 */
95 #define p_wid_resp p_wid_resp_lower
96 u64 p_wid_tst_pin_ctrl; /* 0x000070 */
97 u64 p_wid_addr_lkerr; /* 0x000078 */
98
99 /* 0x000080-0x00008F -- PMU & MAP */
100 u64 p_dir_map; /* 0x000080 */
101 u64 _pad_000088; /* 0x000088 */
102
103 /* 0x000090-0x00009F -- SSRAM */
104 u64 p_map_fault; /* 0x000090 */
105 u64 _pad_000098; /* 0x000098 */
106
107 /* 0x0000A0-0x0000AF -- Arbitration */
108 u64 p_arb; /* 0x0000A0 */
109 u64 _pad_0000A8; /* 0x0000A8 */
110
111 /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
112 u64 p_ate_parity_err; /* 0x0000B0 */
113 u64 _pad_0000B8; /* 0x0000B8 */
114
115 /* 0x0000C0-0x0000FF -- PCI/GIO */
116 u64 p_bus_timeout; /* 0x0000C0 */
117 u64 p_pci_cfg; /* 0x0000C8 */
118 u64 p_pci_err_upper; /* 0x0000D0 */
119 u64 p_pci_err_lower; /* 0x0000D8 */
120 #define p_pci_err p_pci_err_lower
121 u64 _pad_0000E0[4]; /* 0x0000{E0..F8} */
122
123 /* 0x000100-0x0001FF -- Interrupt */
124 u64 p_int_status; /* 0x000100 */
125 u64 p_int_enable; /* 0x000108 */
126 u64 p_int_rst_stat; /* 0x000110 */
127 u64 p_int_mode; /* 0x000118 */
128 u64 p_int_device; /* 0x000120 */
129 u64 p_int_host_err; /* 0x000128 */
130 u64 p_int_addr[8]; /* 0x0001{30,,,68} */
131 u64 p_err_int_view; /* 0x000170 */
132 u64 p_mult_int; /* 0x000178 */
133 u64 p_force_always[8]; /* 0x0001{80,,,B8} */
134 u64 p_force_pin[8]; /* 0x0001{C0,,,F8} */
135
136 /* 0x000200-0x000298 -- Device */
137 u64 p_device[4]; /* 0x0002{00,,,18} */
138 u64 _pad_000220[4]; /* 0x0002{20,,,38} */
139 u64 p_wr_req_buf[4]; /* 0x0002{40,,,58} */
140 u64 _pad_000260[4]; /* 0x0002{60,,,78} */
141 u64 p_rrb_map[2]; /* 0x0002{80,,,88} */
142 #define p_even_resp p_rrb_map[0] /* 0x000280 */
143 #define p_odd_resp p_rrb_map[1] /* 0x000288 */
144 u64 p_resp_status; /* 0x000290 */
145 u64 p_resp_clear; /* 0x000298 */
146
147 u64 _pad_0002A0[12]; /* 0x0002{A0..F8} */
148
149 /* 0x000300-0x0003F8 -- Buffer Address Match Registers */
150 struct {
151 u64 upper; /* 0x0003{00,,,F0} */
152 u64 lower; /* 0x0003{08,,,F8} */
153 } p_buf_addr_match[16];
154
155 /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
156 struct {
157 u64 flush_w_touch; /* 0x000{400,,,5C0} */
158 u64 flush_wo_touch; /* 0x000{408,,,5C8} */
159 u64 inflight; /* 0x000{410,,,5D0} */
160 u64 prefetch; /* 0x000{418,,,5D8} */
161 u64 total_pci_retry; /* 0x000{420,,,5E0} */
162 u64 max_pci_retry; /* 0x000{428,,,5E8} */
163 u64 max_latency; /* 0x000{430,,,5F0} */
164 u64 clear_all; /* 0x000{438,,,5F8} */
165 } p_buf_count[8];
166
167
168 /* 0x000600-0x0009FF -- PCI/X registers */
169 u64 p_pcix_bus_err_addr; /* 0x000600 */
170 u64 p_pcix_bus_err_attr; /* 0x000608 */
171 u64 p_pcix_bus_err_data; /* 0x000610 */
172 u64 p_pcix_pio_split_addr; /* 0x000618 */
173 u64 p_pcix_pio_split_attr; /* 0x000620 */
174 u64 p_pcix_dma_req_err_attr; /* 0x000628 */
175 u64 p_pcix_dma_req_err_addr; /* 0x000630 */
176 u64 p_pcix_timeout; /* 0x000638 */
177
178 u64 _pad_000640[120]; /* 0x000{640,,,9F8} */
179
180 /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
181 struct {
182 u64 p_buf_addr; /* 0x000{A00,,,AF0} */
183 u64 p_buf_attr; /* 0X000{A08,,,AF8} */
184 } p_pcix_read_buf_64[16];
185
186 struct {
187 u64 p_buf_addr; /* 0x000{B00,,,BE0} */
188 u64 p_buf_attr; /* 0x000{B08,,,BE8} */
189 u64 p_buf_valid; /* 0x000{B10,,,BF0} */
190 u64 __pad1; /* 0x000{B18,,,BF8} */
191 } p_pcix_write_buf_64[8];
192
193 /* End of Local Registers -- Start of Address Map space */
194
195 char _pad_000c00[0x010000 - 0x000c00];
196
197 /* 0x010000-0x011fff -- Internal ATE RAM (Auto Parity Generation) */
198 u64 p_int_ate_ram[1024]; /* 0x010000-0x011fff */
199
200 /* 0x012000-0x013fff -- Internal ATE RAM (Manual Parity Generation) */
201 u64 p_int_ate_ram_mp[1024]; /* 0x012000-0x013fff */
202
203 char _pad_014000[0x18000 - 0x014000];
204
205 /* 0x18000-0x197F8 -- PIC Write Request Ram */
206 u64 p_wr_req_lower[256]; /* 0x18000 - 0x187F8 */
207 u64 p_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */
208 u64 p_wr_req_parity[256]; /* 0x19000 - 0x197F8 */
209
210 char _pad_019800[0x20000 - 0x019800];
211
212 /* 0x020000-0x027FFF -- PCI Device Configuration Spaces */
213 union {
214 u8 c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */
215 u16 s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */
216 u32 l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */
217 u64 d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */
218 union {
219 u8 c[0x100 / 1];
220 u16 s[0x100 / 2];
221 u32 l[0x100 / 4];
222 u64 d[0x100 / 8];
223 } f[8];
224 } p_type0_cfg_dev[8]; /* 0x02{0000,,,7FFF} */
225
226 /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
227 union {
228 u8 c[0x1000 / 1]; /* 0x028000-0x029000 */
229 u16 s[0x1000 / 2]; /* 0x028000-0x029000 */
230 u32 l[0x1000 / 4]; /* 0x028000-0x029000 */
231 u64 d[0x1000 / 8]; /* 0x028000-0x029000 */
232 union {
233 u8 c[0x100 / 1];
234 u16 s[0x100 / 2];
235 u32 l[0x100 / 4];
236 u64 d[0x100 / 8];
237 } f[8];
238 } p_type1_cfg; /* 0x028000-0x029000 */
239
240 char _pad_029000[0x030000-0x029000];
241
242 /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
243 union {
244 u8 c[8 / 1];
245 u16 s[8 / 2];
246 u32 l[8 / 4];
247 u64 d[8 / 8];
248 } p_pci_iack; /* 0x030000-0x030007 */
249
250 char _pad_030007[0x040000-0x030008];
251
252 /* 0x040000-0x030007 -- PCIX Special Cycle */
253 union {
254 u8 c[8 / 1];
255 u16 s[8 / 2];
256 u32 l[8 / 4];
257 u64 d[8 / 8];
258 } p_pcix_cycle; /* 0x040000-0x040007 */
259};
260
261#endif /* _ASM_IA64_SN_PCI_PIC_H */
diff --git a/include/asm-ia64/sn/rw_mmr.h b/include/asm-ia64/sn/rw_mmr.h
deleted file mode 100644
index 2d78f4c5a45..00000000000
--- a/include/asm-ia64/sn/rw_mmr.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002-2006 Silicon Graphics, Inc. All Rights Reserved.
7 */
8#ifndef _ASM_IA64_SN_RW_MMR_H
9#define _ASM_IA64_SN_RW_MMR_H
10
11
12/*
13 * This file that access MMRs via uncached physical addresses.
14 * pio_phys_read_mmr - read an MMR
15 * pio_phys_write_mmr - write an MMR
16 * pio_atomic_phys_write_mmrs - atomically write 1 or 2 MMRs with psr.ic=0
17 * Second MMR will be skipped if address is NULL
18 *
19 * Addresses passed to these routines should be uncached physical addresses
20 * ie., 0x80000....
21 */
22
23
24extern long pio_phys_read_mmr(volatile long *mmr);
25extern void pio_phys_write_mmr(volatile long *mmr, long val);
26extern void pio_atomic_phys_write_mmrs(volatile long *mmr1, long val1, volatile long *mmr2, long val2);
27
28#endif /* _ASM_IA64_SN_RW_MMR_H */
diff --git a/include/asm-ia64/sn/shub_mmr.h b/include/asm-ia64/sn/shub_mmr.h
deleted file mode 100644
index 7de1d1d4b71..00000000000
--- a/include/asm-ia64/sn/shub_mmr.h
+++ /dev/null
@@ -1,502 +0,0 @@
1/*
2 *
3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
5 * for more details.
6 *
7 * Copyright (c) 2001-2005 Silicon Graphics, Inc. All rights reserved.
8 */
9
10#ifndef _ASM_IA64_SN_SHUB_MMR_H
11#define _ASM_IA64_SN_SHUB_MMR_H
12
13/* ==================================================================== */
14/* Register "SH_IPI_INT" */
15/* SHub Inter-Processor Interrupt Registers */
16/* ==================================================================== */
17#define SH1_IPI_INT __IA64_UL_CONST(0x0000000110000380)
18#define SH2_IPI_INT __IA64_UL_CONST(0x0000000010000380)
19
20/* SH_IPI_INT_TYPE */
21/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
22#define SH_IPI_INT_TYPE_SHFT 0
23#define SH_IPI_INT_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
24
25/* SH_IPI_INT_AGT */
26/* Description: Agent, must be 0 for SHub */
27#define SH_IPI_INT_AGT_SHFT 3
28#define SH_IPI_INT_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
29
30/* SH_IPI_INT_PID */
31/* Description: Processor ID, same setting as on targeted McKinley */
32#define SH_IPI_INT_PID_SHFT 4
33#define SH_IPI_INT_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
34
35/* SH_IPI_INT_BASE */
36/* Description: Optional interrupt vector area, 2MB aligned */
37#define SH_IPI_INT_BASE_SHFT 21
38#define SH_IPI_INT_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
39
40/* SH_IPI_INT_IDX */
41/* Description: Targeted McKinley interrupt vector */
42#define SH_IPI_INT_IDX_SHFT 52
43#define SH_IPI_INT_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
44
45/* SH_IPI_INT_SEND */
46/* Description: Send Interrupt Message to PI, This generates a puls */
47#define SH_IPI_INT_SEND_SHFT 63
48#define SH_IPI_INT_SEND_MASK __IA64_UL_CONST(0x8000000000000000)
49
50/* ==================================================================== */
51/* Register "SH_EVENT_OCCURRED" */
52/* SHub Interrupt Event Occurred */
53/* ==================================================================== */
54#define SH1_EVENT_OCCURRED __IA64_UL_CONST(0x0000000110010000)
55#define SH1_EVENT_OCCURRED_ALIAS __IA64_UL_CONST(0x0000000110010008)
56#define SH2_EVENT_OCCURRED __IA64_UL_CONST(0x0000000010010000)
57#define SH2_EVENT_OCCURRED_ALIAS __IA64_UL_CONST(0x0000000010010008)
58
59/* ==================================================================== */
60/* Register "SH_PI_CAM_CONTROL" */
61/* CRB CAM MMR Access Control */
62/* ==================================================================== */
63#define SH1_PI_CAM_CONTROL __IA64_UL_CONST(0x0000000120050300)
64
65/* ==================================================================== */
66/* Register "SH_SHUB_ID" */
67/* SHub ID Number */
68/* ==================================================================== */
69#define SH1_SHUB_ID __IA64_UL_CONST(0x0000000110060580)
70#define SH1_SHUB_ID_REVISION_SHFT 28
71#define SH1_SHUB_ID_REVISION_MASK __IA64_UL_CONST(0x00000000f0000000)
72
73/* ==================================================================== */
74/* Register "SH_RTC" */
75/* Real-time Clock */
76/* ==================================================================== */
77#define SH1_RTC __IA64_UL_CONST(0x00000001101c0000)
78#define SH2_RTC __IA64_UL_CONST(0x00000002101c0000)
79#define SH_RTC_MASK __IA64_UL_CONST(0x007fffffffffffff)
80
81/* ==================================================================== */
82/* Register "SH_PIO_WRITE_STATUS_0|1" */
83/* PIO Write Status for CPU 0 & 1 */
84/* ==================================================================== */
85#define SH1_PIO_WRITE_STATUS_0 __IA64_UL_CONST(0x0000000120070200)
86#define SH1_PIO_WRITE_STATUS_1 __IA64_UL_CONST(0x0000000120070280)
87#define SH2_PIO_WRITE_STATUS_0 __IA64_UL_CONST(0x0000000020070200)
88#define SH2_PIO_WRITE_STATUS_1 __IA64_UL_CONST(0x0000000020070280)
89#define SH2_PIO_WRITE_STATUS_2 __IA64_UL_CONST(0x0000000020070300)
90#define SH2_PIO_WRITE_STATUS_3 __IA64_UL_CONST(0x0000000020070380)
91
92/* SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK */
93/* Description: Deadlock response detected */
94#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT 1
95#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK \
96 __IA64_UL_CONST(0x0000000000000002)
97
98/* SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT */
99/* Description: Count of currently pending PIO writes */
100#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_SHFT 56
101#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK \
102 __IA64_UL_CONST(0x3f00000000000000)
103
104/* ==================================================================== */
105/* Register "SH_PIO_WRITE_STATUS_0_ALIAS" */
106/* ==================================================================== */
107#define SH1_PIO_WRITE_STATUS_0_ALIAS __IA64_UL_CONST(0x0000000120070208)
108#define SH2_PIO_WRITE_STATUS_0_ALIAS __IA64_UL_CONST(0x0000000020070208)
109
110/* ==================================================================== */
111/* Register "SH_EVENT_OCCURRED" */
112/* SHub Interrupt Event Occurred */
113/* ==================================================================== */
114/* SH_EVENT_OCCURRED_UART_INT */
115/* Description: Pending Junk Bus UART Interrupt */
116#define SH_EVENT_OCCURRED_UART_INT_SHFT 20
117#define SH_EVENT_OCCURRED_UART_INT_MASK __IA64_UL_CONST(0x0000000000100000)
118
119/* SH_EVENT_OCCURRED_IPI_INT */
120/* Description: Pending IPI Interrupt */
121#define SH_EVENT_OCCURRED_IPI_INT_SHFT 28
122#define SH_EVENT_OCCURRED_IPI_INT_MASK __IA64_UL_CONST(0x0000000010000000)
123
124/* SH_EVENT_OCCURRED_II_INT0 */
125/* Description: Pending II 0 Interrupt */
126#define SH_EVENT_OCCURRED_II_INT0_SHFT 29
127#define SH_EVENT_OCCURRED_II_INT0_MASK __IA64_UL_CONST(0x0000000020000000)
128
129/* SH_EVENT_OCCURRED_II_INT1 */
130/* Description: Pending II 1 Interrupt */
131#define SH_EVENT_OCCURRED_II_INT1_SHFT 30
132#define SH_EVENT_OCCURRED_II_INT1_MASK __IA64_UL_CONST(0x0000000040000000)
133
134/* SH2_EVENT_OCCURRED_EXTIO_INT2 */
135/* Description: Pending SHUB 2 EXT IO INT2 */
136#define SH2_EVENT_OCCURRED_EXTIO_INT2_SHFT 33
137#define SH2_EVENT_OCCURRED_EXTIO_INT2_MASK __IA64_UL_CONST(0x0000000200000000)
138
139/* SH2_EVENT_OCCURRED_EXTIO_INT3 */
140/* Description: Pending SHUB 2 EXT IO INT3 */
141#define SH2_EVENT_OCCURRED_EXTIO_INT3_SHFT 34
142#define SH2_EVENT_OCCURRED_EXTIO_INT3_MASK __IA64_UL_CONST(0x0000000400000000)
143
144#define SH_ALL_INT_MASK \
145 (SH_EVENT_OCCURRED_UART_INT_MASK | SH_EVENT_OCCURRED_IPI_INT_MASK | \
146 SH_EVENT_OCCURRED_II_INT0_MASK | SH_EVENT_OCCURRED_II_INT1_MASK | \
147 SH_EVENT_OCCURRED_II_INT1_MASK | SH2_EVENT_OCCURRED_EXTIO_INT2_MASK | \
148 SH2_EVENT_OCCURRED_EXTIO_INT3_MASK)
149
150
151/* ==================================================================== */
152/* LEDS */
153/* ==================================================================== */
154#define SH1_REAL_JUNK_BUS_LED0 0x7fed00000UL
155#define SH1_REAL_JUNK_BUS_LED1 0x7fed10000UL
156#define SH1_REAL_JUNK_BUS_LED2 0x7fed20000UL
157#define SH1_REAL_JUNK_BUS_LED3 0x7fed30000UL
158
159#define SH2_REAL_JUNK_BUS_LED0 0xf0000000UL
160#define SH2_REAL_JUNK_BUS_LED1 0xf0010000UL
161#define SH2_REAL_JUNK_BUS_LED2 0xf0020000UL
162#define SH2_REAL_JUNK_BUS_LED3 0xf0030000UL
163
164/* ==================================================================== */
165/* Register "SH1_PTC_0" */
166/* Puge Translation Cache Message Configuration Information */
167/* ==================================================================== */
168#define SH1_PTC_0 __IA64_UL_CONST(0x00000001101a0000)
169
170/* SH1_PTC_0_A */
171/* Description: Type */
172#define SH1_PTC_0_A_SHFT 0
173
174/* SH1_PTC_0_PS */
175/* Description: Page Size */
176#define SH1_PTC_0_PS_SHFT 2
177
178/* SH1_PTC_0_RID */
179/* Description: Region ID */
180#define SH1_PTC_0_RID_SHFT 8
181
182/* SH1_PTC_0_START */
183/* Description: Start */
184#define SH1_PTC_0_START_SHFT 63
185
186/* ==================================================================== */
187/* Register "SH1_PTC_1" */
188/* Puge Translation Cache Message Configuration Information */
189/* ==================================================================== */
190#define SH1_PTC_1 __IA64_UL_CONST(0x00000001101a0080)
191
192/* SH1_PTC_1_START */
193/* Description: PTC_1 Start */
194#define SH1_PTC_1_START_SHFT 63
195
196/* ==================================================================== */
197/* Register "SH2_PTC" */
198/* Puge Translation Cache Message Configuration Information */
199/* ==================================================================== */
200#define SH2_PTC __IA64_UL_CONST(0x0000000170000000)
201
202/* SH2_PTC_A */
203/* Description: Type */
204#define SH2_PTC_A_SHFT 0
205
206/* SH2_PTC_PS */
207/* Description: Page Size */
208#define SH2_PTC_PS_SHFT 2
209
210/* SH2_PTC_RID */
211/* Description: Region ID */
212#define SH2_PTC_RID_SHFT 4
213
214/* SH2_PTC_START */
215/* Description: Start */
216#define SH2_PTC_START_SHFT 63
217
218/* SH2_PTC_ADDR_RID */
219/* Description: Region ID */
220#define SH2_PTC_ADDR_SHFT 4
221#define SH2_PTC_ADDR_MASK __IA64_UL_CONST(0x1ffffffffffff000)
222
223/* ==================================================================== */
224/* Register "SH_RTC1_INT_CONFIG" */
225/* SHub RTC 1 Interrupt Config Registers */
226/* ==================================================================== */
227
228#define SH1_RTC1_INT_CONFIG __IA64_UL_CONST(0x0000000110001480)
229#define SH2_RTC1_INT_CONFIG __IA64_UL_CONST(0x0000000010001480)
230#define SH_RTC1_INT_CONFIG_MASK __IA64_UL_CONST(0x0ff3ffffffefffff)
231#define SH_RTC1_INT_CONFIG_INIT __IA64_UL_CONST(0x0000000000000000)
232
233/* SH_RTC1_INT_CONFIG_TYPE */
234/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
235#define SH_RTC1_INT_CONFIG_TYPE_SHFT 0
236#define SH_RTC1_INT_CONFIG_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
237
238/* SH_RTC1_INT_CONFIG_AGT */
239/* Description: Agent, must be 0 for SHub */
240#define SH_RTC1_INT_CONFIG_AGT_SHFT 3
241#define SH_RTC1_INT_CONFIG_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
242
243/* SH_RTC1_INT_CONFIG_PID */
244/* Description: Processor ID, same setting as on targeted McKinley */
245#define SH_RTC1_INT_CONFIG_PID_SHFT 4
246#define SH_RTC1_INT_CONFIG_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
247
248/* SH_RTC1_INT_CONFIG_BASE */
249/* Description: Optional interrupt vector area, 2MB aligned */
250#define SH_RTC1_INT_CONFIG_BASE_SHFT 21
251#define SH_RTC1_INT_CONFIG_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
252
253/* SH_RTC1_INT_CONFIG_IDX */
254/* Description: Targeted McKinley interrupt vector */
255#define SH_RTC1_INT_CONFIG_IDX_SHFT 52
256#define SH_RTC1_INT_CONFIG_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
257
258/* ==================================================================== */
259/* Register "SH_RTC1_INT_ENABLE" */
260/* SHub RTC 1 Interrupt Enable Registers */
261/* ==================================================================== */
262
263#define SH1_RTC1_INT_ENABLE __IA64_UL_CONST(0x0000000110001500)
264#define SH2_RTC1_INT_ENABLE __IA64_UL_CONST(0x0000000010001500)
265#define SH_RTC1_INT_ENABLE_MASK __IA64_UL_CONST(0x0000000000000001)
266#define SH_RTC1_INT_ENABLE_INIT __IA64_UL_CONST(0x0000000000000000)
267
268/* SH_RTC1_INT_ENABLE_RTC1_ENABLE */
269/* Description: Enable RTC 1 Interrupt */
270#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_SHFT 0
271#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_MASK \
272 __IA64_UL_CONST(0x0000000000000001)
273
274/* ==================================================================== */
275/* Register "SH_RTC2_INT_CONFIG" */
276/* SHub RTC 2 Interrupt Config Registers */
277/* ==================================================================== */
278
279#define SH1_RTC2_INT_CONFIG __IA64_UL_CONST(0x0000000110001580)
280#define SH2_RTC2_INT_CONFIG __IA64_UL_CONST(0x0000000010001580)
281#define SH_RTC2_INT_CONFIG_MASK __IA64_UL_CONST(0x0ff3ffffffefffff)
282#define SH_RTC2_INT_CONFIG_INIT __IA64_UL_CONST(0x0000000000000000)
283
284/* SH_RTC2_INT_CONFIG_TYPE */
285/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
286#define SH_RTC2_INT_CONFIG_TYPE_SHFT 0
287#define SH_RTC2_INT_CONFIG_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
288
289/* SH_RTC2_INT_CONFIG_AGT */
290/* Description: Agent, must be 0 for SHub */
291#define SH_RTC2_INT_CONFIG_AGT_SHFT 3
292#define SH_RTC2_INT_CONFIG_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
293
294/* SH_RTC2_INT_CONFIG_PID */
295/* Description: Processor ID, same setting as on targeted McKinley */
296#define SH_RTC2_INT_CONFIG_PID_SHFT 4
297#define SH_RTC2_INT_CONFIG_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
298
299/* SH_RTC2_INT_CONFIG_BASE */
300/* Description: Optional interrupt vector area, 2MB aligned */
301#define SH_RTC2_INT_CONFIG_BASE_SHFT 21
302#define SH_RTC2_INT_CONFIG_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
303
304/* SH_RTC2_INT_CONFIG_IDX */
305/* Description: Targeted McKinley interrupt vector */
306#define SH_RTC2_INT_CONFIG_IDX_SHFT 52
307#define SH_RTC2_INT_CONFIG_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
308
309/* ==================================================================== */
310/* Register "SH_RTC2_INT_ENABLE" */
311/* SHub RTC 2 Interrupt Enable Registers */
312/* ==================================================================== */
313
314#define SH1_RTC2_INT_ENABLE __IA64_UL_CONST(0x0000000110001600)
315#define SH2_RTC2_INT_ENABLE __IA64_UL_CONST(0x0000000010001600)
316#define SH_RTC2_INT_ENABLE_MASK __IA64_UL_CONST(0x0000000000000001)
317#define SH_RTC2_INT_ENABLE_INIT __IA64_UL_CONST(0x0000000000000000)
318
319/* SH_RTC2_INT_ENABLE_RTC2_ENABLE */
320/* Description: Enable RTC 2 Interrupt */
321#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_SHFT 0
322#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_MASK \
323 __IA64_UL_CONST(0x0000000000000001)
324
325/* ==================================================================== */
326/* Register "SH_RTC3_INT_CONFIG" */
327/* SHub RTC 3 Interrupt Config Registers */
328/* ==================================================================== */
329
330#define SH1_RTC3_INT_CONFIG __IA64_UL_CONST(0x0000000110001680)
331#define SH2_RTC3_INT_CONFIG __IA64_UL_CONST(0x0000000010001680)
332#define SH_RTC3_INT_CONFIG_MASK __IA64_UL_CONST(0x0ff3ffffffefffff)
333#define SH_RTC3_INT_CONFIG_INIT __IA64_UL_CONST(0x0000000000000000)
334
335/* SH_RTC3_INT_CONFIG_TYPE */
336/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
337#define SH_RTC3_INT_CONFIG_TYPE_SHFT 0
338#define SH_RTC3_INT_CONFIG_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
339
340/* SH_RTC3_INT_CONFIG_AGT */
341/* Description: Agent, must be 0 for SHub */
342#define SH_RTC3_INT_CONFIG_AGT_SHFT 3
343#define SH_RTC3_INT_CONFIG_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
344
345/* SH_RTC3_INT_CONFIG_PID */
346/* Description: Processor ID, same setting as on targeted McKinley */
347#define SH_RTC3_INT_CONFIG_PID_SHFT 4
348#define SH_RTC3_INT_CONFIG_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
349
350/* SH_RTC3_INT_CONFIG_BASE */
351/* Description: Optional interrupt vector area, 2MB aligned */
352#define SH_RTC3_INT_CONFIG_BASE_SHFT 21
353#define SH_RTC3_INT_CONFIG_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
354
355/* SH_RTC3_INT_CONFIG_IDX */
356/* Description: Targeted McKinley interrupt vector */
357#define SH_RTC3_INT_CONFIG_IDX_SHFT 52
358#define SH_RTC3_INT_CONFIG_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
359
360/* ==================================================================== */
361/* Register "SH_RTC3_INT_ENABLE" */
362/* SHub RTC 3 Interrupt Enable Registers */
363/* ==================================================================== */
364
365#define SH1_RTC3_INT_ENABLE __IA64_UL_CONST(0x0000000110001700)
366#define SH2_RTC3_INT_ENABLE __IA64_UL_CONST(0x0000000010001700)
367#define SH_RTC3_INT_ENABLE_MASK __IA64_UL_CONST(0x0000000000000001)
368#define SH_RTC3_INT_ENABLE_INIT __IA64_UL_CONST(0x0000000000000000)
369
370/* SH_RTC3_INT_ENABLE_RTC3_ENABLE */
371/* Description: Enable RTC 3 Interrupt */
372#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_SHFT 0
373#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_MASK \
374 __IA64_UL_CONST(0x0000000000000001)
375
376/* SH_EVENT_OCCURRED_RTC1_INT */
377/* Description: Pending RTC 1 Interrupt */
378#define SH_EVENT_OCCURRED_RTC1_INT_SHFT 24
379#define SH_EVENT_OCCURRED_RTC1_INT_MASK __IA64_UL_CONST(0x0000000001000000)
380
381/* SH_EVENT_OCCURRED_RTC2_INT */
382/* Description: Pending RTC 2 Interrupt */
383#define SH_EVENT_OCCURRED_RTC2_INT_SHFT 25
384#define SH_EVENT_OCCURRED_RTC2_INT_MASK __IA64_UL_CONST(0x0000000002000000)
385
386/* SH_EVENT_OCCURRED_RTC3_INT */
387/* Description: Pending RTC 3 Interrupt */
388#define SH_EVENT_OCCURRED_RTC3_INT_SHFT 26
389#define SH_EVENT_OCCURRED_RTC3_INT_MASK __IA64_UL_CONST(0x0000000004000000)
390
391/* ==================================================================== */
392/* Register "SH_IPI_ACCESS" */
393/* CPU interrupt Access Permission Bits */
394/* ==================================================================== */
395
396#define SH1_IPI_ACCESS __IA64_UL_CONST(0x0000000110060480)
397#define SH2_IPI_ACCESS0 __IA64_UL_CONST(0x0000000010060c00)
398#define SH2_IPI_ACCESS1 __IA64_UL_CONST(0x0000000010060c80)
399#define SH2_IPI_ACCESS2 __IA64_UL_CONST(0x0000000010060d00)
400#define SH2_IPI_ACCESS3 __IA64_UL_CONST(0x0000000010060d80)
401
402/* ==================================================================== */
403/* Register "SH_INT_CMPB" */
404/* RTC Compare Value for Processor B */
405/* ==================================================================== */
406
407#define SH1_INT_CMPB __IA64_UL_CONST(0x00000001101b0080)
408#define SH2_INT_CMPB __IA64_UL_CONST(0x00000000101b0080)
409#define SH_INT_CMPB_MASK __IA64_UL_CONST(0x007fffffffffffff)
410#define SH_INT_CMPB_INIT __IA64_UL_CONST(0x0000000000000000)
411
412/* SH_INT_CMPB_REAL_TIME_CMPB */
413/* Description: Real Time Clock Compare */
414#define SH_INT_CMPB_REAL_TIME_CMPB_SHFT 0
415#define SH_INT_CMPB_REAL_TIME_CMPB_MASK __IA64_UL_CONST(0x007fffffffffffff)
416
417/* ==================================================================== */
418/* Register "SH_INT_CMPC" */
419/* RTC Compare Value for Processor C */
420/* ==================================================================== */
421
422#define SH1_INT_CMPC __IA64_UL_CONST(0x00000001101b0100)
423#define SH2_INT_CMPC __IA64_UL_CONST(0x00000000101b0100)
424#define SH_INT_CMPC_MASK __IA64_UL_CONST(0x007fffffffffffff)
425#define SH_INT_CMPC_INIT __IA64_UL_CONST(0x0000000000000000)
426
427/* SH_INT_CMPC_REAL_TIME_CMPC */
428/* Description: Real Time Clock Compare */
429#define SH_INT_CMPC_REAL_TIME_CMPC_SHFT 0
430#define SH_INT_CMPC_REAL_TIME_CMPC_MASK __IA64_UL_CONST(0x007fffffffffffff)
431
432/* ==================================================================== */
433/* Register "SH_INT_CMPD" */
434/* RTC Compare Value for Processor D */
435/* ==================================================================== */
436
437#define SH1_INT_CMPD __IA64_UL_CONST(0x00000001101b0180)
438#define SH2_INT_CMPD __IA64_UL_CONST(0x00000000101b0180)
439#define SH_INT_CMPD_MASK __IA64_UL_CONST(0x007fffffffffffff)
440#define SH_INT_CMPD_INIT __IA64_UL_CONST(0x0000000000000000)
441
442/* SH_INT_CMPD_REAL_TIME_CMPD */
443/* Description: Real Time Clock Compare */
444#define SH_INT_CMPD_REAL_TIME_CMPD_SHFT 0
445#define SH_INT_CMPD_REAL_TIME_CMPD_MASK __IA64_UL_CONST(0x007fffffffffffff)
446
447/* ==================================================================== */
448/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC0" */
449/* privilege vector for acc=0 */
450/* ==================================================================== */
451#define SH1_MD_DQLP_MMR_DIR_PRIVEC0 __IA64_UL_CONST(0x0000000100030300)
452
453/* ==================================================================== */
454/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC0" */
455/* privilege vector for acc=0 */
456/* ==================================================================== */
457#define SH1_MD_DQRP_MMR_DIR_PRIVEC0 __IA64_UL_CONST(0x0000000100050300)
458
459/* ==================================================================== */
460/* Some MMRs are functionally identical (or close enough) on both SHUB1 */
461/* and SHUB2 that it makes sense to define a geberic name for the MMR. */
462/* It is acceptible to use (for example) SH_IPI_INT to reference the */
463/* the IPI MMR. The value of SH_IPI_INT is determined at runtime based */
464/* on the type of the SHUB. Do not use these #defines in performance */
465/* critical code or loops - there is a small performance penalty. */
466/* ==================================================================== */
467#define shubmmr(a,b) (is_shub2() ? a##2_##b : a##1_##b)
468
469#define SH_REAL_JUNK_BUS_LED0 shubmmr(SH, REAL_JUNK_BUS_LED0)
470#define SH_IPI_INT shubmmr(SH, IPI_INT)
471#define SH_EVENT_OCCURRED shubmmr(SH, EVENT_OCCURRED)
472#define SH_EVENT_OCCURRED_ALIAS shubmmr(SH, EVENT_OCCURRED_ALIAS)
473#define SH_RTC shubmmr(SH, RTC)
474#define SH_RTC1_INT_CONFIG shubmmr(SH, RTC1_INT_CONFIG)
475#define SH_RTC1_INT_ENABLE shubmmr(SH, RTC1_INT_ENABLE)
476#define SH_RTC2_INT_CONFIG shubmmr(SH, RTC2_INT_CONFIG)
477#define SH_RTC2_INT_ENABLE shubmmr(SH, RTC2_INT_ENABLE)
478#define SH_RTC3_INT_CONFIG shubmmr(SH, RTC3_INT_CONFIG)
479#define SH_RTC3_INT_ENABLE shubmmr(SH, RTC3_INT_ENABLE)
480#define SH_INT_CMPB shubmmr(SH, INT_CMPB)
481#define SH_INT_CMPC shubmmr(SH, INT_CMPC)
482#define SH_INT_CMPD shubmmr(SH, INT_CMPD)
483
484/* ========================================================================== */
485/* Register "SH2_BT_ENG_CSR_0" */
486/* Engine 0 Control and Status Register */
487/* ========================================================================== */
488
489#define SH2_BT_ENG_CSR_0 __IA64_UL_CONST(0x0000000030040000)
490#define SH2_BT_ENG_SRC_ADDR_0 __IA64_UL_CONST(0x0000000030040080)
491#define SH2_BT_ENG_DEST_ADDR_0 __IA64_UL_CONST(0x0000000030040100)
492#define SH2_BT_ENG_NOTIF_ADDR_0 __IA64_UL_CONST(0x0000000030040180)
493
494/* ========================================================================== */
495/* BTE interfaces 1-3 */
496/* ========================================================================== */
497
498#define SH2_BT_ENG_CSR_1 __IA64_UL_CONST(0x0000000030050000)
499#define SH2_BT_ENG_CSR_2 __IA64_UL_CONST(0x0000000030060000)
500#define SH2_BT_ENG_CSR_3 __IA64_UL_CONST(0x0000000030070000)
501
502#endif /* _ASM_IA64_SN_SHUB_MMR_H */
diff --git a/include/asm-ia64/sn/shubio.h b/include/asm-ia64/sn/shubio.h
deleted file mode 100644
index 22a6f18a531..00000000000
--- a/include/asm-ia64/sn/shubio.h
+++ /dev/null
@@ -1,3358 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
7 */
8
9#ifndef _ASM_IA64_SN_SHUBIO_H
10#define _ASM_IA64_SN_SHUBIO_H
11
12#define HUB_WIDGET_ID_MAX 0xf
13#define IIO_NUM_ITTES 7
14#define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1)
15
16#define IIO_WID 0x00400000 /* Crosstalk Widget Identification */
17 /* This register is also accessible from
18 * Crosstalk at address 0x0. */
19#define IIO_WSTAT 0x00400008 /* Crosstalk Widget Status */
20#define IIO_WCR 0x00400020 /* Crosstalk Widget Control Register */
21#define IIO_ILAPR 0x00400100 /* IO Local Access Protection Register */
22#define IIO_ILAPO 0x00400108 /* IO Local Access Protection Override */
23#define IIO_IOWA 0x00400110 /* IO Outbound Widget Access */
24#define IIO_IIWA 0x00400118 /* IO Inbound Widget Access */
25#define IIO_IIDEM 0x00400120 /* IO Inbound Device Error Mask */
26#define IIO_ILCSR 0x00400128 /* IO LLP Control and Status Register */
27#define IIO_ILLR 0x00400130 /* IO LLP Log Register */
28#define IIO_IIDSR 0x00400138 /* IO Interrupt Destination */
29
30#define IIO_IGFX0 0x00400140 /* IO Graphics Node-Widget Map 0 */
31#define IIO_IGFX1 0x00400148 /* IO Graphics Node-Widget Map 1 */
32
33#define IIO_ISCR0 0x00400150 /* IO Scratch Register 0 */
34#define IIO_ISCR1 0x00400158 /* IO Scratch Register 1 */
35
36#define IIO_ITTE1 0x00400160 /* IO Translation Table Entry 1 */
37#define IIO_ITTE2 0x00400168 /* IO Translation Table Entry 2 */
38#define IIO_ITTE3 0x00400170 /* IO Translation Table Entry 3 */
39#define IIO_ITTE4 0x00400178 /* IO Translation Table Entry 4 */
40#define IIO_ITTE5 0x00400180 /* IO Translation Table Entry 5 */
41#define IIO_ITTE6 0x00400188 /* IO Translation Table Entry 6 */
42#define IIO_ITTE7 0x00400190 /* IO Translation Table Entry 7 */
43
44#define IIO_IPRB0 0x00400198 /* IO PRB Entry 0 */
45#define IIO_IPRB8 0x004001A0 /* IO PRB Entry 8 */
46#define IIO_IPRB9 0x004001A8 /* IO PRB Entry 9 */
47#define IIO_IPRBA 0x004001B0 /* IO PRB Entry A */
48#define IIO_IPRBB 0x004001B8 /* IO PRB Entry B */
49#define IIO_IPRBC 0x004001C0 /* IO PRB Entry C */
50#define IIO_IPRBD 0x004001C8 /* IO PRB Entry D */
51#define IIO_IPRBE 0x004001D0 /* IO PRB Entry E */
52#define IIO_IPRBF 0x004001D8 /* IO PRB Entry F */
53
54#define IIO_IXCC 0x004001E0 /* IO Crosstalk Credit Count Timeout */
55#define IIO_IMEM 0x004001E8 /* IO Miscellaneous Error Mask */
56#define IIO_IXTT 0x004001F0 /* IO Crosstalk Timeout Threshold */
57#define IIO_IECLR 0x004001F8 /* IO Error Clear Register */
58#define IIO_IBCR 0x00400200 /* IO BTE Control Register */
59
60#define IIO_IXSM 0x00400208 /* IO Crosstalk Spurious Message */
61#define IIO_IXSS 0x00400210 /* IO Crosstalk Spurious Sideband */
62
63#define IIO_ILCT 0x00400218 /* IO LLP Channel Test */
64
65#define IIO_IIEPH1 0x00400220 /* IO Incoming Error Packet Header, Part 1 */
66#define IIO_IIEPH2 0x00400228 /* IO Incoming Error Packet Header, Part 2 */
67
68#define IIO_ISLAPR 0x00400230 /* IO SXB Local Access Protection Regster */
69#define IIO_ISLAPO 0x00400238 /* IO SXB Local Access Protection Override */
70
71#define IIO_IWI 0x00400240 /* IO Wrapper Interrupt Register */
72#define IIO_IWEL 0x00400248 /* IO Wrapper Error Log Register */
73#define IIO_IWC 0x00400250 /* IO Wrapper Control Register */
74#define IIO_IWS 0x00400258 /* IO Wrapper Status Register */
75#define IIO_IWEIM 0x00400260 /* IO Wrapper Error Interrupt Masking Register */
76
77#define IIO_IPCA 0x00400300 /* IO PRB Counter Adjust */
78
79#define IIO_IPRTE0_A 0x00400308 /* IO PIO Read Address Table Entry 0, Part A */
80#define IIO_IPRTE1_A 0x00400310 /* IO PIO Read Address Table Entry 1, Part A */
81#define IIO_IPRTE2_A 0x00400318 /* IO PIO Read Address Table Entry 2, Part A */
82#define IIO_IPRTE3_A 0x00400320 /* IO PIO Read Address Table Entry 3, Part A */
83#define IIO_IPRTE4_A 0x00400328 /* IO PIO Read Address Table Entry 4, Part A */
84#define IIO_IPRTE5_A 0x00400330 /* IO PIO Read Address Table Entry 5, Part A */
85#define IIO_IPRTE6_A 0x00400338 /* IO PIO Read Address Table Entry 6, Part A */
86#define IIO_IPRTE7_A 0x00400340 /* IO PIO Read Address Table Entry 7, Part A */
87
88#define IIO_IPRTE0_B 0x00400348 /* IO PIO Read Address Table Entry 0, Part B */
89#define IIO_IPRTE1_B 0x00400350 /* IO PIO Read Address Table Entry 1, Part B */
90#define IIO_IPRTE2_B 0x00400358 /* IO PIO Read Address Table Entry 2, Part B */
91#define IIO_IPRTE3_B 0x00400360 /* IO PIO Read Address Table Entry 3, Part B */
92#define IIO_IPRTE4_B 0x00400368 /* IO PIO Read Address Table Entry 4, Part B */
93#define IIO_IPRTE5_B 0x00400370 /* IO PIO Read Address Table Entry 5, Part B */
94#define IIO_IPRTE6_B 0x00400378 /* IO PIO Read Address Table Entry 6, Part B */
95#define IIO_IPRTE7_B 0x00400380 /* IO PIO Read Address Table Entry 7, Part B */
96
97#define IIO_IPDR 0x00400388 /* IO PIO Deallocation Register */
98#define IIO_ICDR 0x00400390 /* IO CRB Entry Deallocation Register */
99#define IIO_IFDR 0x00400398 /* IO IOQ FIFO Depth Register */
100#define IIO_IIAP 0x004003A0 /* IO IIQ Arbitration Parameters */
101#define IIO_ICMR 0x004003A8 /* IO CRB Management Register */
102#define IIO_ICCR 0x004003B0 /* IO CRB Control Register */
103#define IIO_ICTO 0x004003B8 /* IO CRB Timeout */
104#define IIO_ICTP 0x004003C0 /* IO CRB Timeout Prescalar */
105
106#define IIO_ICRB0_A 0x00400400 /* IO CRB Entry 0_A */
107#define IIO_ICRB0_B 0x00400408 /* IO CRB Entry 0_B */
108#define IIO_ICRB0_C 0x00400410 /* IO CRB Entry 0_C */
109#define IIO_ICRB0_D 0x00400418 /* IO CRB Entry 0_D */
110#define IIO_ICRB0_E 0x00400420 /* IO CRB Entry 0_E */
111
112#define IIO_ICRB1_A 0x00400430 /* IO CRB Entry 1_A */
113#define IIO_ICRB1_B 0x00400438 /* IO CRB Entry 1_B */
114#define IIO_ICRB1_C 0x00400440 /* IO CRB Entry 1_C */
115#define IIO_ICRB1_D 0x00400448 /* IO CRB Entry 1_D */
116#define IIO_ICRB1_E 0x00400450 /* IO CRB Entry 1_E */
117
118#define IIO_ICRB2_A 0x00400460 /* IO CRB Entry 2_A */
119#define IIO_ICRB2_B 0x00400468 /* IO CRB Entry 2_B */
120#define IIO_ICRB2_C 0x00400470 /* IO CRB Entry 2_C */
121#define IIO_ICRB2_D 0x00400478 /* IO CRB Entry 2_D */
122#define IIO_ICRB2_E 0x00400480 /* IO CRB Entry 2_E */
123
124#define IIO_ICRB3_A 0x00400490 /* IO CRB Entry 3_A */
125#define IIO_ICRB3_B 0x00400498 /* IO CRB Entry 3_B */
126#define IIO_ICRB3_C 0x004004a0 /* IO CRB Entry 3_C */
127#define IIO_ICRB3_D 0x004004a8 /* IO CRB Entry 3_D */
128#define IIO_ICRB3_E 0x004004b0 /* IO CRB Entry 3_E */
129
130#define IIO_ICRB4_A 0x004004c0 /* IO CRB Entry 4_A */
131#define IIO_ICRB4_B 0x004004c8 /* IO CRB Entry 4_B */
132#define IIO_ICRB4_C 0x004004d0 /* IO CRB Entry 4_C */
133#define IIO_ICRB4_D 0x004004d8 /* IO CRB Entry 4_D */
134#define IIO_ICRB4_E 0x004004e0 /* IO CRB Entry 4_E */
135
136#define IIO_ICRB5_A 0x004004f0 /* IO CRB Entry 5_A */
137#define IIO_ICRB5_B 0x004004f8 /* IO CRB Entry 5_B */
138#define IIO_ICRB5_C 0x00400500 /* IO CRB Entry 5_C */
139#define IIO_ICRB5_D 0x00400508 /* IO CRB Entry 5_D */
140#define IIO_ICRB5_E 0x00400510 /* IO CRB Entry 5_E */
141
142#define IIO_ICRB6_A 0x00400520 /* IO CRB Entry 6_A */
143#define IIO_ICRB6_B 0x00400528 /* IO CRB Entry 6_B */
144#define IIO_ICRB6_C 0x00400530 /* IO CRB Entry 6_C */
145#define IIO_ICRB6_D 0x00400538 /* IO CRB Entry 6_D */
146#define IIO_ICRB6_E 0x00400540 /* IO CRB Entry 6_E */
147
148#define IIO_ICRB7_A 0x00400550 /* IO CRB Entry 7_A */
149#define IIO_ICRB7_B 0x00400558 /* IO CRB Entry 7_B */
150#define IIO_ICRB7_C 0x00400560 /* IO CRB Entry 7_C */
151#define IIO_ICRB7_D 0x00400568 /* IO CRB Entry 7_D */
152#define IIO_ICRB7_E 0x00400570 /* IO CRB Entry 7_E */
153
154#define IIO_ICRB8_A 0x00400580 /* IO CRB Entry 8_A */
155#define IIO_ICRB8_B 0x00400588 /* IO CRB Entry 8_B */
156#define IIO_ICRB8_C 0x00400590 /* IO CRB Entry 8_C */
157#define IIO_ICRB8_D 0x00400598 /* IO CRB Entry 8_D */
158#define IIO_ICRB8_E 0x004005a0 /* IO CRB Entry 8_E */
159
160#define IIO_ICRB9_A 0x004005b0 /* IO CRB Entry 9_A */
161#define IIO_ICRB9_B 0x004005b8 /* IO CRB Entry 9_B */
162#define IIO_ICRB9_C 0x004005c0 /* IO CRB Entry 9_C */
163#define IIO_ICRB9_D 0x004005c8 /* IO CRB Entry 9_D */
164#define IIO_ICRB9_E 0x004005d0 /* IO CRB Entry 9_E */
165
166#define IIO_ICRBA_A 0x004005e0 /* IO CRB Entry A_A */
167#define IIO_ICRBA_B 0x004005e8 /* IO CRB Entry A_B */
168#define IIO_ICRBA_C 0x004005f0 /* IO CRB Entry A_C */
169#define IIO_ICRBA_D 0x004005f8 /* IO CRB Entry A_D */
170#define IIO_ICRBA_E 0x00400600 /* IO CRB Entry A_E */
171
172#define IIO_ICRBB_A 0x00400610 /* IO CRB Entry B_A */
173#define IIO_ICRBB_B 0x00400618 /* IO CRB Entry B_B */
174#define IIO_ICRBB_C 0x00400620 /* IO CRB Entry B_C */
175#define IIO_ICRBB_D 0x00400628 /* IO CRB Entry B_D */
176#define IIO_ICRBB_E 0x00400630 /* IO CRB Entry B_E */
177
178#define IIO_ICRBC_A 0x00400640 /* IO CRB Entry C_A */
179#define IIO_ICRBC_B 0x00400648 /* IO CRB Entry C_B */
180#define IIO_ICRBC_C 0x00400650 /* IO CRB Entry C_C */
181#define IIO_ICRBC_D 0x00400658 /* IO CRB Entry C_D */
182#define IIO_ICRBC_E 0x00400660 /* IO CRB Entry C_E */
183
184#define IIO_ICRBD_A 0x00400670 /* IO CRB Entry D_A */
185#define IIO_ICRBD_B 0x00400678 /* IO CRB Entry D_B */
186#define IIO_ICRBD_C 0x00400680 /* IO CRB Entry D_C */
187#define IIO_ICRBD_D 0x00400688 /* IO CRB Entry D_D */
188#define IIO_ICRBD_E 0x00400690 /* IO CRB Entry D_E */
189
190#define IIO_ICRBE_A 0x004006a0 /* IO CRB Entry E_A */
191#define IIO_ICRBE_B 0x004006a8 /* IO CRB Entry E_B */
192#define IIO_ICRBE_C 0x004006b0 /* IO CRB Entry E_C */
193#define IIO_ICRBE_D 0x004006b8 /* IO CRB Entry E_D */
194#define IIO_ICRBE_E 0x004006c0 /* IO CRB Entry E_E */
195
196#define IIO_ICSML 0x00400700 /* IO CRB Spurious Message Low */
197#define IIO_ICSMM 0x00400708 /* IO CRB Spurious Message Middle */
198#define IIO_ICSMH 0x00400710 /* IO CRB Spurious Message High */
199
200#define IIO_IDBSS 0x00400718 /* IO Debug Submenu Select */
201
202#define IIO_IBLS0 0x00410000 /* IO BTE Length Status 0 */
203#define IIO_IBSA0 0x00410008 /* IO BTE Source Address 0 */
204#define IIO_IBDA0 0x00410010 /* IO BTE Destination Address 0 */
205#define IIO_IBCT0 0x00410018 /* IO BTE Control Terminate 0 */
206#define IIO_IBNA0 0x00410020 /* IO BTE Notification Address 0 */
207#define IIO_IBIA0 0x00410028 /* IO BTE Interrupt Address 0 */
208#define IIO_IBLS1 0x00420000 /* IO BTE Length Status 1 */
209#define IIO_IBSA1 0x00420008 /* IO BTE Source Address 1 */
210#define IIO_IBDA1 0x00420010 /* IO BTE Destination Address 1 */
211#define IIO_IBCT1 0x00420018 /* IO BTE Control Terminate 1 */
212#define IIO_IBNA1 0x00420020 /* IO BTE Notification Address 1 */
213#define IIO_IBIA1 0x00420028 /* IO BTE Interrupt Address 1 */
214
215#define IIO_IPCR 0x00430000 /* IO Performance Control */
216#define IIO_IPPR 0x00430008 /* IO Performance Profiling */
217
218/************************************************************************
219 * *
220 * Description: This register echoes some information from the *
221 * LB_REV_ID register. It is available through Crosstalk as described *
222 * above. The REV_NUM and MFG_NUM fields receive their values from *
223 * the REVISION and MANUFACTURER fields in the LB_REV_ID register. *
224 * The PART_NUM field's value is the Crosstalk device ID number that *
225 * Steve Miller assigned to the SHub chip. *
226 * *
227 ************************************************************************/
228
229typedef union ii_wid_u {
230 u64 ii_wid_regval;
231 struct {
232 u64 w_rsvd_1:1;
233 u64 w_mfg_num:11;
234 u64 w_part_num:16;
235 u64 w_rev_num:4;
236 u64 w_rsvd:32;
237 } ii_wid_fld_s;
238} ii_wid_u_t;
239
240/************************************************************************
241 * *
242 * The fields in this register are set upon detection of an error *
243 * and cleared by various mechanisms, as explained in the *
244 * description. *
245 * *
246 ************************************************************************/
247
248typedef union ii_wstat_u {
249 u64 ii_wstat_regval;
250 struct {
251 u64 w_pending:4;
252 u64 w_xt_crd_to:1;
253 u64 w_xt_tail_to:1;
254 u64 w_rsvd_3:3;
255 u64 w_tx_mx_rty:1;
256 u64 w_rsvd_2:6;
257 u64 w_llp_tx_cnt:8;
258 u64 w_rsvd_1:8;
259 u64 w_crazy:1;
260 u64 w_rsvd:31;
261 } ii_wstat_fld_s;
262} ii_wstat_u_t;
263
264/************************************************************************
265 * *
266 * Description: This is a read-write enabled register. It controls *
267 * various aspects of the Crosstalk flow control. *
268 * *
269 ************************************************************************/
270
271typedef union ii_wcr_u {
272 u64 ii_wcr_regval;
273 struct {
274 u64 w_wid:4;
275 u64 w_tag:1;
276 u64 w_rsvd_1:8;
277 u64 w_dst_crd:3;
278 u64 w_f_bad_pkt:1;
279 u64 w_dir_con:1;
280 u64 w_e_thresh:5;
281 u64 w_rsvd:41;
282 } ii_wcr_fld_s;
283} ii_wcr_u_t;
284
285/************************************************************************
286 * *
287 * Description: This register's value is a bit vector that guards *
288 * access to local registers within the II as well as to external *
289 * Crosstalk widgets. Each bit in the register corresponds to a *
290 * particular region in the system; a region consists of one, two or *
291 * four nodes (depending on the value of the REGION_SIZE field in the *
292 * LB_REV_ID register, which is documented in Section 8.3.1.1). The *
293 * protection provided by this register applies to PIO read *
294 * operations as well as PIO write operations. The II will perform a *
295 * PIO read or write request only if the bit for the requestor's *
296 * region is set; otherwise, the II will not perform the requested *
297 * operation and will return an error response. When a PIO read or *
298 * write request targets an external Crosstalk widget, then not only *
299 * must the bit for the requestor's region be set in the ILAPR, but *
300 * also the target widget's bit in the IOWA register must be set in *
301 * order for the II to perform the requested operation; otherwise, *
302 * the II will return an error response. Hence, the protection *
303 * provided by the IOWA register supplements the protection provided *
304 * by the ILAPR for requests that target external Crosstalk widgets. *
305 * This register itself can be accessed only by the nodes whose *
306 * region ID bits are enabled in this same register. It can also be *
307 * accessed through the IAlias space by the local processors. *
308 * The reset value of this register allows access by all nodes. *
309 * *
310 ************************************************************************/
311
312typedef union ii_ilapr_u {
313 u64 ii_ilapr_regval;
314 struct {
315 u64 i_region:64;
316 } ii_ilapr_fld_s;
317} ii_ilapr_u_t;
318
319/************************************************************************
320 * *
321 * Description: A write to this register of the 64-bit value *
322 * "SGIrules" in ASCII, will cause the bit in the ILAPR register *
323 * corresponding to the region of the requestor to be set (allow *
324 * access). A write of any other value will be ignored. Access *
325 * protection for this register is "SGIrules". *
326 * This register can also be accessed through the IAlias space. *
327 * However, this access will not change the access permissions in the *
328 * ILAPR. *
329 * *
330 ************************************************************************/
331
332typedef union ii_ilapo_u {
333 u64 ii_ilapo_regval;
334 struct {
335 u64 i_io_ovrride:64;
336 } ii_ilapo_fld_s;
337} ii_ilapo_u_t;
338
339/************************************************************************
340 * *
341 * This register qualifies all the PIO and Graphics writes launched *
342 * from the SHUB towards a widget. *
343 * *
344 ************************************************************************/
345
346typedef union ii_iowa_u {
347 u64 ii_iowa_regval;
348 struct {
349 u64 i_w0_oac:1;
350 u64 i_rsvd_1:7;
351 u64 i_wx_oac:8;
352 u64 i_rsvd:48;
353 } ii_iowa_fld_s;
354} ii_iowa_u_t;
355
356/************************************************************************
357 * *
358 * Description: This register qualifies all the requests launched *
359 * from a widget towards the Shub. This register is intended to be *
360 * used by software in case of misbehaving widgets. *
361 * *
362 * *
363 ************************************************************************/
364
365typedef union ii_iiwa_u {
366 u64 ii_iiwa_regval;
367 struct {
368 u64 i_w0_iac:1;
369 u64 i_rsvd_1:7;
370 u64 i_wx_iac:8;
371 u64 i_rsvd:48;
372 } ii_iiwa_fld_s;
373} ii_iiwa_u_t;
374
375/************************************************************************
376 * *
377 * Description: This register qualifies all the operations launched *
378 * from a widget towards the SHub. It allows individual access *
379 * control for up to 8 devices per widget. A device refers to *
380 * individual DMA master hosted by a widget. *
381 * The bits in each field of this register are cleared by the Shub *
382 * upon detection of an error which requires the device to be *
383 * disabled. These fields assume that 0=TNUM=7 (i.e., Bridge-centric *
384 * Crosstalk). Whether or not a device has access rights to this *
385 * Shub is determined by an AND of the device enable bit in the *
386 * appropriate field of this register and the corresponding bit in *
387 * the Wx_IAC field (for the widget which this device belongs to). *
388 * The bits in this field are set by writing a 1 to them. Incoming *
389 * replies from Crosstalk are not subject to this access control *
390 * mechanism. *
391 * *
392 ************************************************************************/
393
394typedef union ii_iidem_u {
395 u64 ii_iidem_regval;
396 struct {
397 u64 i_w8_dxs:8;
398 u64 i_w9_dxs:8;
399 u64 i_wa_dxs:8;
400 u64 i_wb_dxs:8;
401 u64 i_wc_dxs:8;
402 u64 i_wd_dxs:8;
403 u64 i_we_dxs:8;
404 u64 i_wf_dxs:8;
405 } ii_iidem_fld_s;
406} ii_iidem_u_t;
407
408/************************************************************************
409 * *
410 * This register contains the various programmable fields necessary *
411 * for controlling and observing the LLP signals. *
412 * *
413 ************************************************************************/
414
415typedef union ii_ilcsr_u {
416 u64 ii_ilcsr_regval;
417 struct {
418 u64 i_nullto:6;
419 u64 i_rsvd_4:2;
420 u64 i_wrmrst:1;
421 u64 i_rsvd_3:1;
422 u64 i_llp_en:1;
423 u64 i_bm8:1;
424 u64 i_llp_stat:2;
425 u64 i_remote_power:1;
426 u64 i_rsvd_2:1;
427 u64 i_maxrtry:10;
428 u64 i_d_avail_sel:2;
429 u64 i_rsvd_1:4;
430 u64 i_maxbrst:10;
431 u64 i_rsvd:22;
432
433 } ii_ilcsr_fld_s;
434} ii_ilcsr_u_t;
435
436/************************************************************************
437 * *
438 * This is simply a status registers that monitors the LLP error *
439 * rate. *
440 * *
441 ************************************************************************/
442
443typedef union ii_illr_u {
444 u64 ii_illr_regval;
445 struct {
446 u64 i_sn_cnt:16;
447 u64 i_cb_cnt:16;
448 u64 i_rsvd:32;
449 } ii_illr_fld_s;
450} ii_illr_u_t;
451
452/************************************************************************
453 * *
454 * Description: All II-detected non-BTE error interrupts are *
455 * specified via this register. *
456 * NOTE: The PI interrupt register address is hardcoded in the II. If *
457 * PI_ID==0, then the II sends an interrupt request (Duplonet PWRI *
458 * packet) to address offset 0x0180_0090 within the local register *
459 * address space of PI0 on the node specified by the NODE field. If *
460 * PI_ID==1, then the II sends the interrupt request to address *
461 * offset 0x01A0_0090 within the local register address space of PI1 *
462 * on the node specified by the NODE field. *
463 * *
464 ************************************************************************/
465
466typedef union ii_iidsr_u {
467 u64 ii_iidsr_regval;
468 struct {
469 u64 i_level:8;
470 u64 i_pi_id:1;
471 u64 i_node:11;
472 u64 i_rsvd_3:4;
473 u64 i_enable:1;
474 u64 i_rsvd_2:3;
475 u64 i_int_sent:2;
476 u64 i_rsvd_1:2;
477 u64 i_pi0_forward_int:1;
478 u64 i_pi1_forward_int:1;
479 u64 i_rsvd:30;
480 } ii_iidsr_fld_s;
481} ii_iidsr_u_t;
482
483/************************************************************************
484 * *
485 * There are two instances of this register. This register is used *
486 * for matching up the incoming responses from the graphics widget to *
487 * the processor that initiated the graphics operation. The *
488 * write-responses are converted to graphics credits and returned to *
489 * the processor so that the processor interface can manage the flow *
490 * control. *
491 * *
492 ************************************************************************/
493
494typedef union ii_igfx0_u {
495 u64 ii_igfx0_regval;
496 struct {
497 u64 i_w_num:4;
498 u64 i_pi_id:1;
499 u64 i_n_num:12;
500 u64 i_p_num:1;
501 u64 i_rsvd:46;
502 } ii_igfx0_fld_s;
503} ii_igfx0_u_t;
504
505/************************************************************************
506 * *
507 * There are two instances of this register. This register is used *
508 * for matching up the incoming responses from the graphics widget to *
509 * the processor that initiated the graphics operation. The *
510 * write-responses are converted to graphics credits and returned to *
511 * the processor so that the processor interface can manage the flow *
512 * control. *
513 * *
514 ************************************************************************/
515
516typedef union ii_igfx1_u {
517 u64 ii_igfx1_regval;
518 struct {
519 u64 i_w_num:4;
520 u64 i_pi_id:1;
521 u64 i_n_num:12;
522 u64 i_p_num:1;
523 u64 i_rsvd:46;
524 } ii_igfx1_fld_s;
525} ii_igfx1_u_t;
526
527/************************************************************************
528 * *
529 * There are two instances of this registers. These registers are *
530 * used as scratch registers for software use. *
531 * *
532 ************************************************************************/
533
534typedef union ii_iscr0_u {
535 u64 ii_iscr0_regval;
536 struct {
537 u64 i_scratch:64;
538 } ii_iscr0_fld_s;
539} ii_iscr0_u_t;
540
541/************************************************************************
542 * *
543 * There are two instances of this registers. These registers are *
544 * used as scratch registers for software use. *
545 * *
546 ************************************************************************/
547
548typedef union ii_iscr1_u {
549 u64 ii_iscr1_regval;
550 struct {
551 u64 i_scratch:64;
552 } ii_iscr1_fld_s;
553} ii_iscr1_u_t;
554
555/************************************************************************
556 * *
557 * Description: There are seven instances of translation table entry *
558 * registers. Each register maps a Shub Big Window to a 48-bit *
559 * address on Crosstalk. *
560 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
561 * number) are used to select one of these 7 registers. The Widget *
562 * number field is then derived from the W_NUM field for synthesizing *
563 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
564 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
565 * are padded with zeros. Although the maximum Crosstalk space *
566 * addressable by the SHub is thus the lower 16 GBytes per widget *
567 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
568 * space can be accessed. *
569 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
570 * Window number) are used to select one of these 7 registers. The *
571 * Widget number field is then derived from the W_NUM field for *
572 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
573 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
574 * field is used as Crosstalk[47], and remainder of the Crosstalk *
575 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
576 * Crosstalk space addressable by the Shub is thus the lower *
577 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
578 * of this space can be accessed. *
579 * *
580 ************************************************************************/
581
582typedef union ii_itte1_u {
583 u64 ii_itte1_regval;
584 struct {
585 u64 i_offset:5;
586 u64 i_rsvd_1:3;
587 u64 i_w_num:4;
588 u64 i_iosp:1;
589 u64 i_rsvd:51;
590 } ii_itte1_fld_s;
591} ii_itte1_u_t;
592
593/************************************************************************
594 * *
595 * Description: There are seven instances of translation table entry *
596 * registers. Each register maps a Shub Big Window to a 48-bit *
597 * address on Crosstalk. *
598 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
599 * number) are used to select one of these 7 registers. The Widget *
600 * number field is then derived from the W_NUM field for synthesizing *
601 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
602 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
603 * are padded with zeros. Although the maximum Crosstalk space *
604 * addressable by the Shub is thus the lower 16 GBytes per widget *
605 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
606 * space can be accessed. *
607 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
608 * Window number) are used to select one of these 7 registers. The *
609 * Widget number field is then derived from the W_NUM field for *
610 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
611 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
612 * field is used as Crosstalk[47], and remainder of the Crosstalk *
613 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
614 * Crosstalk space addressable by the Shub is thus the lower *
615 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
616 * of this space can be accessed. *
617 * *
618 ************************************************************************/
619
620typedef union ii_itte2_u {
621 u64 ii_itte2_regval;
622 struct {
623 u64 i_offset:5;
624 u64 i_rsvd_1:3;
625 u64 i_w_num:4;
626 u64 i_iosp:1;
627 u64 i_rsvd:51;
628 } ii_itte2_fld_s;
629} ii_itte2_u_t;
630
631/************************************************************************
632 * *
633 * Description: There are seven instances of translation table entry *
634 * registers. Each register maps a Shub Big Window to a 48-bit *
635 * address on Crosstalk. *
636 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
637 * number) are used to select one of these 7 registers. The Widget *
638 * number field is then derived from the W_NUM field for synthesizing *
639 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
640 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
641 * are padded with zeros. Although the maximum Crosstalk space *
642 * addressable by the Shub is thus the lower 16 GBytes per widget *
643 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
644 * space can be accessed. *
645 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
646 * Window number) are used to select one of these 7 registers. The *
647 * Widget number field is then derived from the W_NUM field for *
648 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
649 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
650 * field is used as Crosstalk[47], and remainder of the Crosstalk *
651 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
652 * Crosstalk space addressable by the SHub is thus the lower *
653 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
654 * of this space can be accessed. *
655 * *
656 ************************************************************************/
657
658typedef union ii_itte3_u {
659 u64 ii_itte3_regval;
660 struct {
661 u64 i_offset:5;
662 u64 i_rsvd_1:3;
663 u64 i_w_num:4;
664 u64 i_iosp:1;
665 u64 i_rsvd:51;
666 } ii_itte3_fld_s;
667} ii_itte3_u_t;
668
669/************************************************************************
670 * *
671 * Description: There are seven instances of translation table entry *
672 * registers. Each register maps a SHub Big Window to a 48-bit *
673 * address on Crosstalk. *
674 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
675 * number) are used to select one of these 7 registers. The Widget *
676 * number field is then derived from the W_NUM field for synthesizing *
677 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
678 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
679 * are padded with zeros. Although the maximum Crosstalk space *
680 * addressable by the SHub is thus the lower 16 GBytes per widget *
681 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
682 * space can be accessed. *
683 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
684 * Window number) are used to select one of these 7 registers. The *
685 * Widget number field is then derived from the W_NUM field for *
686 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
687 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
688 * field is used as Crosstalk[47], and remainder of the Crosstalk *
689 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
690 * Crosstalk space addressable by the SHub is thus the lower *
691 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
692 * of this space can be accessed. *
693 * *
694 ************************************************************************/
695
696typedef union ii_itte4_u {
697 u64 ii_itte4_regval;
698 struct {
699 u64 i_offset:5;
700 u64 i_rsvd_1:3;
701 u64 i_w_num:4;
702 u64 i_iosp:1;
703 u64 i_rsvd:51;
704 } ii_itte4_fld_s;
705} ii_itte4_u_t;
706
707/************************************************************************
708 * *
709 * Description: There are seven instances of translation table entry *
710 * registers. Each register maps a SHub Big Window to a 48-bit *
711 * address on Crosstalk. *
712 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
713 * number) are used to select one of these 7 registers. The Widget *
714 * number field is then derived from the W_NUM field for synthesizing *
715 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
716 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
717 * are padded with zeros. Although the maximum Crosstalk space *
718 * addressable by the Shub is thus the lower 16 GBytes per widget *
719 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
720 * space can be accessed. *
721 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
722 * Window number) are used to select one of these 7 registers. The *
723 * Widget number field is then derived from the W_NUM field for *
724 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
725 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
726 * field is used as Crosstalk[47], and remainder of the Crosstalk *
727 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
728 * Crosstalk space addressable by the Shub is thus the lower *
729 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
730 * of this space can be accessed. *
731 * *
732 ************************************************************************/
733
734typedef union ii_itte5_u {
735 u64 ii_itte5_regval;
736 struct {
737 u64 i_offset:5;
738 u64 i_rsvd_1:3;
739 u64 i_w_num:4;
740 u64 i_iosp:1;
741 u64 i_rsvd:51;
742 } ii_itte5_fld_s;
743} ii_itte5_u_t;
744
745/************************************************************************
746 * *
747 * Description: There are seven instances of translation table entry *
748 * registers. Each register maps a Shub Big Window to a 48-bit *
749 * address on Crosstalk. *
750 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
751 * number) are used to select one of these 7 registers. The Widget *
752 * number field is then derived from the W_NUM field for synthesizing *
753 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
754 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
755 * are padded with zeros. Although the maximum Crosstalk space *
756 * addressable by the Shub is thus the lower 16 GBytes per widget *
757 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
758 * space can be accessed. *
759 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
760 * Window number) are used to select one of these 7 registers. The *
761 * Widget number field is then derived from the W_NUM field for *
762 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
763 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
764 * field is used as Crosstalk[47], and remainder of the Crosstalk *
765 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
766 * Crosstalk space addressable by the Shub is thus the lower *
767 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
768 * of this space can be accessed. *
769 * *
770 ************************************************************************/
771
772typedef union ii_itte6_u {
773 u64 ii_itte6_regval;
774 struct {
775 u64 i_offset:5;
776 u64 i_rsvd_1:3;
777 u64 i_w_num:4;
778 u64 i_iosp:1;
779 u64 i_rsvd:51;
780 } ii_itte6_fld_s;
781} ii_itte6_u_t;
782
783/************************************************************************
784 * *
785 * Description: There are seven instances of translation table entry *
786 * registers. Each register maps a Shub Big Window to a 48-bit *
787 * address on Crosstalk. *
788 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
789 * number) are used to select one of these 7 registers. The Widget *
790 * number field is then derived from the W_NUM field for synthesizing *
791 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
792 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
793 * are padded with zeros. Although the maximum Crosstalk space *
794 * addressable by the Shub is thus the lower 16 GBytes per widget *
795 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
796 * space can be accessed. *
797 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
798 * Window number) are used to select one of these 7 registers. The *
799 * Widget number field is then derived from the W_NUM field for *
800 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
801 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
802 * field is used as Crosstalk[47], and remainder of the Crosstalk *
803 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
804 * Crosstalk space addressable by the SHub is thus the lower *
805 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
806 * of this space can be accessed. *
807 * *
808 ************************************************************************/
809
810typedef union ii_itte7_u {
811 u64 ii_itte7_regval;
812 struct {
813 u64 i_offset:5;
814 u64 i_rsvd_1:3;
815 u64 i_w_num:4;
816 u64 i_iosp:1;
817 u64 i_rsvd:51;
818 } ii_itte7_fld_s;
819} ii_itte7_u_t;
820
821/************************************************************************
822 * *
823 * Description: There are 9 instances of this register, one per *
824 * actual widget in this implementation of SHub and Crossbow. *
825 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
826 * refers to Crossbow's internal space. *
827 * This register contains the state elements per widget that are *
828 * necessary to manage the PIO flow control on Crosstalk and on the *
829 * Router Network. See the PIO Flow Control chapter for a complete *
830 * description of this register *
831 * The SPUR_WR bit requires some explanation. When this register is *
832 * written, the new value of the C field is captured in an internal *
833 * register so the hardware can remember what the programmer wrote *
834 * into the credit counter. The SPUR_WR bit sets whenever the C field *
835 * increments above this stored value, which indicates that there *
836 * have been more responses received than requests sent. The SPUR_WR *
837 * bit cannot be cleared until a value is written to the IPRBx *
838 * register; the write will correct the C field and capture its new *
839 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
840 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
841 * . *
842 * *
843 ************************************************************************/
844
845typedef union ii_iprb0_u {
846 u64 ii_iprb0_regval;
847 struct {
848 u64 i_c:8;
849 u64 i_na:14;
850 u64 i_rsvd_2:2;
851 u64 i_nb:14;
852 u64 i_rsvd_1:2;
853 u64 i_m:2;
854 u64 i_f:1;
855 u64 i_of_cnt:5;
856 u64 i_error:1;
857 u64 i_rd_to:1;
858 u64 i_spur_wr:1;
859 u64 i_spur_rd:1;
860 u64 i_rsvd:11;
861 u64 i_mult_err:1;
862 } ii_iprb0_fld_s;
863} ii_iprb0_u_t;
864
865/************************************************************************
866 * *
867 * Description: There are 9 instances of this register, one per *
868 * actual widget in this implementation of SHub and Crossbow. *
869 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
870 * refers to Crossbow's internal space. *
871 * This register contains the state elements per widget that are *
872 * necessary to manage the PIO flow control on Crosstalk and on the *
873 * Router Network. See the PIO Flow Control chapter for a complete *
874 * description of this register *
875 * The SPUR_WR bit requires some explanation. When this register is *
876 * written, the new value of the C field is captured in an internal *
877 * register so the hardware can remember what the programmer wrote *
878 * into the credit counter. The SPUR_WR bit sets whenever the C field *
879 * increments above this stored value, which indicates that there *
880 * have been more responses received than requests sent. The SPUR_WR *
881 * bit cannot be cleared until a value is written to the IPRBx *
882 * register; the write will correct the C field and capture its new *
883 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
884 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
885 * . *
886 * *
887 ************************************************************************/
888
889typedef union ii_iprb8_u {
890 u64 ii_iprb8_regval;
891 struct {
892 u64 i_c:8;
893 u64 i_na:14;
894 u64 i_rsvd_2:2;
895 u64 i_nb:14;
896 u64 i_rsvd_1:2;
897 u64 i_m:2;
898 u64 i_f:1;
899 u64 i_of_cnt:5;
900 u64 i_error:1;
901 u64 i_rd_to:1;
902 u64 i_spur_wr:1;
903 u64 i_spur_rd:1;
904 u64 i_rsvd:11;
905 u64 i_mult_err:1;
906 } ii_iprb8_fld_s;
907} ii_iprb8_u_t;
908
909/************************************************************************
910 * *
911 * Description: There are 9 instances of this register, one per *
912 * actual widget in this implementation of SHub and Crossbow. *
913 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
914 * refers to Crossbow's internal space. *
915 * This register contains the state elements per widget that are *
916 * necessary to manage the PIO flow control on Crosstalk and on the *
917 * Router Network. See the PIO Flow Control chapter for a complete *
918 * description of this register *
919 * The SPUR_WR bit requires some explanation. When this register is *
920 * written, the new value of the C field is captured in an internal *
921 * register so the hardware can remember what the programmer wrote *
922 * into the credit counter. The SPUR_WR bit sets whenever the C field *
923 * increments above this stored value, which indicates that there *
924 * have been more responses received than requests sent. The SPUR_WR *
925 * bit cannot be cleared until a value is written to the IPRBx *
926 * register; the write will correct the C field and capture its new *
927 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
928 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
929 * . *
930 * *
931 ************************************************************************/
932
933typedef union ii_iprb9_u {
934 u64 ii_iprb9_regval;
935 struct {
936 u64 i_c:8;
937 u64 i_na:14;
938 u64 i_rsvd_2:2;
939 u64 i_nb:14;
940 u64 i_rsvd_1:2;
941 u64 i_m:2;
942 u64 i_f:1;
943 u64 i_of_cnt:5;
944 u64 i_error:1;
945 u64 i_rd_to:1;
946 u64 i_spur_wr:1;
947 u64 i_spur_rd:1;
948 u64 i_rsvd:11;
949 u64 i_mult_err:1;
950 } ii_iprb9_fld_s;
951} ii_iprb9_u_t;
952
953/************************************************************************
954 * *
955 * Description: There are 9 instances of this register, one per *
956 * actual widget in this implementation of SHub and Crossbow. *
957 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
958 * refers to Crossbow's internal space. *
959 * This register contains the state elements per widget that are *
960 * necessary to manage the PIO flow control on Crosstalk and on the *
961 * Router Network. See the PIO Flow Control chapter for a complete *
962 * description of this register *
963 * The SPUR_WR bit requires some explanation. When this register is *
964 * written, the new value of the C field is captured in an internal *
965 * register so the hardware can remember what the programmer wrote *
966 * into the credit counter. The SPUR_WR bit sets whenever the C field *
967 * increments above this stored value, which indicates that there *
968 * have been more responses received than requests sent. The SPUR_WR *
969 * bit cannot be cleared until a value is written to the IPRBx *
970 * register; the write will correct the C field and capture its new *
971 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
972 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
973 * *
974 * *
975 ************************************************************************/
976
977typedef union ii_iprba_u {
978 u64 ii_iprba_regval;
979 struct {
980 u64 i_c:8;
981 u64 i_na:14;
982 u64 i_rsvd_2:2;
983 u64 i_nb:14;
984 u64 i_rsvd_1:2;
985 u64 i_m:2;
986 u64 i_f:1;
987 u64 i_of_cnt:5;
988 u64 i_error:1;
989 u64 i_rd_to:1;
990 u64 i_spur_wr:1;
991 u64 i_spur_rd:1;
992 u64 i_rsvd:11;
993 u64 i_mult_err:1;
994 } ii_iprba_fld_s;
995} ii_iprba_u_t;
996
997/************************************************************************
998 * *
999 * Description: There are 9 instances of this register, one per *
1000 * actual widget in this implementation of SHub and Crossbow. *
1001 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
1002 * refers to Crossbow's internal space. *
1003 * This register contains the state elements per widget that are *
1004 * necessary to manage the PIO flow control on Crosstalk and on the *
1005 * Router Network. See the PIO Flow Control chapter for a complete *
1006 * description of this register *
1007 * The SPUR_WR bit requires some explanation. When this register is *
1008 * written, the new value of the C field is captured in an internal *
1009 * register so the hardware can remember what the programmer wrote *
1010 * into the credit counter. The SPUR_WR bit sets whenever the C field *
1011 * increments above this stored value, which indicates that there *
1012 * have been more responses received than requests sent. The SPUR_WR *
1013 * bit cannot be cleared until a value is written to the IPRBx *
1014 * register; the write will correct the C field and capture its new *
1015 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
1016 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
1017 * . *
1018 * *
1019 ************************************************************************/
1020
1021typedef union ii_iprbb_u {
1022 u64 ii_iprbb_regval;
1023 struct {
1024 u64 i_c:8;
1025 u64 i_na:14;
1026 u64 i_rsvd_2:2;
1027 u64 i_nb:14;
1028 u64 i_rsvd_1:2;
1029 u64 i_m:2;
1030 u64 i_f:1;
1031 u64 i_of_cnt:5;
1032 u64 i_error:1;
1033 u64 i_rd_to:1;
1034 u64 i_spur_wr:1;
1035 u64 i_spur_rd:1;
1036 u64 i_rsvd:11;
1037 u64 i_mult_err:1;
1038 } ii_iprbb_fld_s;
1039} ii_iprbb_u_t;
1040
1041/************************************************************************
1042 * *
1043 * Description: There are 9 instances of this register, one per *
1044 * actual widget in this implementation of SHub and Crossbow. *
1045 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
1046 * refers to Crossbow's internal space. *
1047 * This register contains the state elements per widget that are *
1048 * necessary to manage the PIO flow control on Crosstalk and on the *
1049 * Router Network. See the PIO Flow Control chapter for a complete *
1050 * description of this register *
1051 * The SPUR_WR bit requires some explanation. When this register is *
1052 * written, the new value of the C field is captured in an internal *
1053 * register so the hardware can remember what the programmer wrote *
1054 * into the credit counter. The SPUR_WR bit sets whenever the C field *
1055 * increments above this stored value, which indicates that there *
1056 * have been more responses received than requests sent. The SPUR_WR *
1057 * bit cannot be cleared until a value is written to the IPRBx *
1058 * register; the write will correct the C field and capture its new *
1059 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
1060 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
1061 * . *
1062 * *
1063 ************************************************************************/
1064
1065typedef union ii_iprbc_u {
1066 u64 ii_iprbc_regval;
1067 struct {
1068 u64 i_c:8;
1069 u64 i_na:14;
1070 u64 i_rsvd_2:2;
1071 u64 i_nb:14;
1072 u64 i_rsvd_1:2;
1073 u64 i_m:2;
1074 u64 i_f:1;
1075 u64 i_of_cnt:5;
1076 u64 i_error:1;
1077 u64 i_rd_to:1;
1078 u64 i_spur_wr:1;
1079 u64 i_spur_rd:1;
1080 u64 i_rsvd:11;
1081 u64 i_mult_err:1;
1082 } ii_iprbc_fld_s;
1083} ii_iprbc_u_t;
1084
1085/************************************************************************
1086 * *
1087 * Description: There are 9 instances of this register, one per *
1088 * actual widget in this implementation of SHub and Crossbow. *
1089 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
1090 * refers to Crossbow's internal space. *
1091 * This register contains the state elements per widget that are *
1092 * necessary to manage the PIO flow control on Crosstalk and on the *
1093 * Router Network. See the PIO Flow Control chapter for a complete *
1094 * description of this register *
1095 * The SPUR_WR bit requires some explanation. When this register is *
1096 * written, the new value of the C field is captured in an internal *
1097 * register so the hardware can remember what the programmer wrote *
1098 * into the credit counter. The SPUR_WR bit sets whenever the C field *
1099 * increments above this stored value, which indicates that there *
1100 * have been more responses received than requests sent. The SPUR_WR *
1101 * bit cannot be cleared until a value is written to the IPRBx *
1102 * register; the write will correct the C field and capture its new *
1103 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
1104 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
1105 * . *
1106 * *
1107 ************************************************************************/
1108
1109typedef union ii_iprbd_u {
1110 u64 ii_iprbd_regval;
1111 struct {
1112 u64 i_c:8;
1113 u64 i_na:14;
1114 u64 i_rsvd_2:2;
1115 u64 i_nb:14;
1116 u64 i_rsvd_1:2;
1117 u64 i_m:2;
1118 u64 i_f:1;
1119 u64 i_of_cnt:5;
1120 u64 i_error:1;
1121 u64 i_rd_to:1;
1122 u64 i_spur_wr:1;
1123 u64 i_spur_rd:1;
1124 u64 i_rsvd:11;
1125 u64 i_mult_err:1;
1126 } ii_iprbd_fld_s;
1127} ii_iprbd_u_t;
1128
1129/************************************************************************
1130 * *
1131 * Description: There are 9 instances of this register, one per *
1132 * actual widget in this implementation of SHub and Crossbow. *
1133 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
1134 * refers to Crossbow's internal space. *
1135 * This register contains the state elements per widget that are *
1136 * necessary to manage the PIO flow control on Crosstalk and on the *
1137 * Router Network. See the PIO Flow Control chapter for a complete *
1138 * description of this register *
1139 * The SPUR_WR bit requires some explanation. When this register is *
1140 * written, the new value of the C field is captured in an internal *
1141 * register so the hardware can remember what the programmer wrote *
1142 * into the credit counter. The SPUR_WR bit sets whenever the C field *
1143 * increments above this stored value, which indicates that there *
1144 * have been more responses received than requests sent. The SPUR_WR *
1145 * bit cannot be cleared until a value is written to the IPRBx *
1146 * register; the write will correct the C field and capture its new *
1147 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
1148 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
1149 * . *
1150 * *
1151 ************************************************************************/
1152
1153typedef union ii_iprbe_u {
1154 u64 ii_iprbe_regval;
1155 struct {
1156 u64 i_c:8;
1157 u64 i_na:14;
1158 u64 i_rsvd_2:2;
1159 u64 i_nb:14;
1160 u64 i_rsvd_1:2;
1161 u64 i_m:2;
1162 u64 i_f:1;
1163 u64 i_of_cnt:5;
1164 u64 i_error:1;
1165 u64 i_rd_to:1;
1166 u64 i_spur_wr:1;
1167 u64 i_spur_rd:1;
1168 u64 i_rsvd:11;
1169 u64 i_mult_err:1;
1170 } ii_iprbe_fld_s;
1171} ii_iprbe_u_t;
1172
1173/************************************************************************
1174 * *
1175 * Description: There are 9 instances of this register, one per *
1176 * actual widget in this implementation of Shub and Crossbow. *
1177 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
1178 * refers to Crossbow's internal space. *
1179 * This register contains the state elements per widget that are *
1180 * necessary to manage the PIO flow control on Crosstalk and on the *
1181 * Router Network. See the PIO Flow Control chapter for a complete *
1182 * description of this register *
1183 * The SPUR_WR bit requires some explanation. When this register is *
1184 * written, the new value of the C field is captured in an internal *
1185 * register so the hardware can remember what the programmer wrote *
1186 * into the credit counter. The SPUR_WR bit sets whenever the C field *
1187 * increments above this stored value, which indicates that there *
1188 * have been more responses received than requests sent. The SPUR_WR *
1189 * bit cannot be cleared until a value is written to the IPRBx *
1190 * register; the write will correct the C field and capture its new *
1191 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
1192 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
1193 * . *
1194 * *
1195 ************************************************************************/
1196
1197typedef union ii_iprbf_u {
1198 u64 ii_iprbf_regval;
1199 struct {
1200 u64 i_c:8;
1201 u64 i_na:14;
1202 u64 i_rsvd_2:2;
1203 u64 i_nb:14;
1204 u64 i_rsvd_1:2;
1205 u64 i_m:2;
1206 u64 i_f:1;
1207 u64 i_of_cnt:5;
1208 u64 i_error:1;
1209 u64 i_rd_to:1;
1210 u64 i_spur_wr:1;
1211 u64 i_spur_rd:1;
1212 u64 i_rsvd:11;
1213 u64 i_mult_err:1;
1214 } ii_iprbe_fld_s;
1215} ii_iprbf_u_t;
1216
1217/************************************************************************
1218 * *
1219 * This register specifies the timeout value to use for monitoring *
1220 * Crosstalk credits which are used outbound to Crosstalk. An *
1221 * internal counter called the Crosstalk Credit Timeout Counter *
1222 * increments every 128 II clocks. The counter starts counting *
1223 * anytime the credit count drops below a threshold, and resets to *
1224 * zero (stops counting) anytime the credit count is at or above the *
1225 * threshold. The threshold is 1 credit in direct connect mode and 2 *
1226 * in Crossbow connect mode. When the internal Crosstalk Credit *
1227 * Timeout Counter reaches the value programmed in this register, a *
1228 * Crosstalk Credit Timeout has occurred. The internal counter is not *
1229 * readable from software, and stops counting at its maximum value, *
1230 * so it cannot cause more than one interrupt. *
1231 * *
1232 ************************************************************************/
1233
1234typedef union ii_ixcc_u {
1235 u64 ii_ixcc_regval;
1236 struct {
1237 u64 i_time_out:26;
1238 u64 i_rsvd:38;
1239 } ii_ixcc_fld_s;
1240} ii_ixcc_u_t;
1241
1242/************************************************************************
1243 * *
1244 * Description: This register qualifies all the PIO and DMA *
1245 * operations launched from widget 0 towards the SHub. In *
1246 * addition, it also qualifies accesses by the BTE streams. *
1247 * The bits in each field of this register are cleared by the SHub *
1248 * upon detection of an error which requires widget 0 or the BTE *
1249 * streams to be terminated. Whether or not widget x has access *
1250 * rights to this SHub is determined by an AND of the device *
1251 * enable bit in the appropriate field of this register and bit 0 in *
1252 * the Wx_IAC field. The bits in this field are set by writing a 1 to *
1253 * them. Incoming replies from Crosstalk are not subject to this *
1254 * access control mechanism. *
1255 * *
1256 ************************************************************************/
1257
1258typedef union ii_imem_u {
1259 u64 ii_imem_regval;
1260 struct {
1261 u64 i_w0_esd:1;
1262 u64 i_rsvd_3:3;
1263 u64 i_b0_esd:1;
1264 u64 i_rsvd_2:3;
1265 u64 i_b1_esd:1;
1266 u64 i_rsvd_1:3;
1267 u64 i_clr_precise:1;
1268 u64 i_rsvd:51;
1269 } ii_imem_fld_s;
1270} ii_imem_u_t;
1271
1272/************************************************************************
1273 * *
1274 * Description: This register specifies the timeout value to use for *
1275 * monitoring Crosstalk tail flits coming into the Shub in the *
1276 * TAIL_TO field. An internal counter associated with this register *
1277 * is incremented every 128 II internal clocks (7 bits). The counter *
1278 * starts counting anytime a header micropacket is received and stops *
1279 * counting (and resets to zero) any time a micropacket with a Tail *
1280 * bit is received. Once the counter reaches the threshold value *
1281 * programmed in this register, it generates an interrupt to the *
1282 * processor that is programmed into the IIDSR. The counter saturates *
1283 * (does not roll over) at its maximum value, so it cannot cause *
1284 * another interrupt until after it is cleared. *
1285 * The register also contains the Read Response Timeout values. The *
1286 * Prescalar is 23 bits, and counts II clocks. An internal counter *
1287 * increments on every II clock and when it reaches the value in the *
1288 * Prescalar field, all IPRTE registers with their valid bits set *
1289 * have their Read Response timers bumped. Whenever any of them match *
1290 * the value in the RRSP_TO field, a Read Response Timeout has *
1291 * occurred, and error handling occurs as described in the Error *
1292 * Handling section of this document. *
1293 * *
1294 ************************************************************************/
1295
1296typedef union ii_ixtt_u {
1297 u64 ii_ixtt_regval;
1298 struct {
1299 u64 i_tail_to:26;
1300 u64 i_rsvd_1:6;
1301 u64 i_rrsp_ps:23;
1302 u64 i_rrsp_to:5;
1303 u64 i_rsvd:4;
1304 } ii_ixtt_fld_s;
1305} ii_ixtt_u_t;
1306
1307/************************************************************************
1308 * *
1309 * Writing a 1 to the fields of this register clears the appropriate *
1310 * error bits in other areas of SHub. Note that when the *
1311 * E_PRB_x bits are used to clear error bits in PRB registers, *
1312 * SPUR_RD and SPUR_WR may persist, because they require additional *
1313 * action to clear them. See the IPRBx and IXSS Register *
1314 * specifications. *
1315 * *
1316 ************************************************************************/
1317
1318typedef union ii_ieclr_u {
1319 u64 ii_ieclr_regval;
1320 struct {
1321 u64 i_e_prb_0:1;
1322 u64 i_rsvd:7;
1323 u64 i_e_prb_8:1;
1324 u64 i_e_prb_9:1;
1325 u64 i_e_prb_a:1;
1326 u64 i_e_prb_b:1;
1327 u64 i_e_prb_c:1;
1328 u64 i_e_prb_d:1;
1329 u64 i_e_prb_e:1;
1330 u64 i_e_prb_f:1;
1331 u64 i_e_crazy:1;
1332 u64 i_e_bte_0:1;
1333 u64 i_e_bte_1:1;
1334 u64 i_reserved_1:10;
1335 u64 i_spur_rd_hdr:1;
1336 u64 i_cam_intr_to:1;
1337 u64 i_cam_overflow:1;
1338 u64 i_cam_read_miss:1;
1339 u64 i_ioq_rep_underflow:1;
1340 u64 i_ioq_req_underflow:1;
1341 u64 i_ioq_rep_overflow:1;
1342 u64 i_ioq_req_overflow:1;
1343 u64 i_iiq_rep_overflow:1;
1344 u64 i_iiq_req_overflow:1;
1345 u64 i_ii_xn_rep_cred_overflow:1;
1346 u64 i_ii_xn_req_cred_overflow:1;
1347 u64 i_ii_xn_invalid_cmd:1;
1348 u64 i_xn_ii_invalid_cmd:1;
1349 u64 i_reserved_2:21;
1350 } ii_ieclr_fld_s;
1351} ii_ieclr_u_t;
1352
1353/************************************************************************
1354 * *
1355 * This register controls both BTEs. SOFT_RESET is intended for *
1356 * recovery after an error. COUNT controls the total number of CRBs *
1357 * that both BTEs (combined) can use, which affects total BTE *
1358 * bandwidth. *
1359 * *
1360 ************************************************************************/
1361
1362typedef union ii_ibcr_u {
1363 u64 ii_ibcr_regval;
1364 struct {
1365 u64 i_count:4;
1366 u64 i_rsvd_1:4;
1367 u64 i_soft_reset:1;
1368 u64 i_rsvd:55;
1369 } ii_ibcr_fld_s;
1370} ii_ibcr_u_t;
1371
1372/************************************************************************
1373 * *
1374 * This register contains the header of a spurious read response *
1375 * received from Crosstalk. A spurious read response is defined as a *
1376 * read response received by II from a widget for which (1) the SIDN *
1377 * has a value between 1 and 7, inclusive (II never sends requests to *
1378 * these widgets (2) there is no valid IPRTE register which *
1379 * corresponds to the TNUM, or (3) the widget indicated in SIDN is *
1380 * not the same as the widget recorded in the IPRTE register *
1381 * referenced by the TNUM. If this condition is true, and if the *
1382 * IXSS[VALID] bit is clear, then the header of the spurious read *
1383 * response is capture in IXSM and IXSS, and IXSS[VALID] is set. The *
1384 * errant header is thereby captured, and no further spurious read *
1385 * respones are captured until IXSS[VALID] is cleared by setting the *
1386 * appropriate bit in IECLR.Everytime a spurious read response is *
1387 * detected, the SPUR_RD bit of the PRB corresponding to the incoming *
1388 * message's SIDN field is set. This always happens, regarless of *
1389 * whether a header is captured. The programmer should check *
1390 * IXSM[SIDN] to determine which widget sent the spurious response, *
1391 * because there may be more than one SPUR_RD bit set in the PRB *
1392 * registers. The widget indicated by IXSM[SIDN] was the first *
1393 * spurious read response to be received since the last time *
1394 * IXSS[VALID] was clear. The SPUR_RD bit of the corresponding PRB *
1395 * will be set. Any SPUR_RD bits in any other PRB registers indicate *
1396 * spurious messages from other widets which were detected after the *
1397 * header was captured.. *
1398 * *
1399 ************************************************************************/
1400
1401typedef union ii_ixsm_u {
1402 u64 ii_ixsm_regval;
1403 struct {
1404 u64 i_byte_en:32;
1405 u64 i_reserved:1;
1406 u64 i_tag:3;
1407 u64 i_alt_pactyp:4;
1408 u64 i_bo:1;
1409 u64 i_error:1;
1410 u64 i_vbpm:1;
1411 u64 i_gbr:1;
1412 u64 i_ds:2;
1413 u64 i_ct:1;
1414 u64 i_tnum:5;
1415 u64 i_pactyp:4;
1416 u64 i_sidn:4;
1417 u64 i_didn:4;
1418 } ii_ixsm_fld_s;
1419} ii_ixsm_u_t;
1420
1421/************************************************************************
1422 * *
1423 * This register contains the sideband bits of a spurious read *
1424 * response received from Crosstalk. *
1425 * *
1426 ************************************************************************/
1427
1428typedef union ii_ixss_u {
1429 u64 ii_ixss_regval;
1430 struct {
1431 u64 i_sideband:8;
1432 u64 i_rsvd:55;
1433 u64 i_valid:1;
1434 } ii_ixss_fld_s;
1435} ii_ixss_u_t;
1436
1437/************************************************************************
1438 * *
1439 * This register enables software to access the II LLP's test port. *
1440 * Refer to the LLP 2.5 documentation for an explanation of the test *
1441 * port. Software can write to this register to program the values *
1442 * for the control fields (TestErrCapture, TestClear, TestFlit, *
1443 * TestMask and TestSeed). Similarly, software can read from this *
1444 * register to obtain the values of the test port's status outputs *
1445 * (TestCBerr, TestValid and TestData). *
1446 * *
1447 ************************************************************************/
1448
1449typedef union ii_ilct_u {
1450 u64 ii_ilct_regval;
1451 struct {
1452 u64 i_test_seed:20;
1453 u64 i_test_mask:8;
1454 u64 i_test_data:20;
1455 u64 i_test_valid:1;
1456 u64 i_test_cberr:1;
1457 u64 i_test_flit:3;
1458 u64 i_test_clear:1;
1459 u64 i_test_err_capture:1;
1460 u64 i_rsvd:9;
1461 } ii_ilct_fld_s;
1462} ii_ilct_u_t;
1463
1464/************************************************************************
1465 * *
1466 * If the II detects an illegal incoming Duplonet packet (request or *
1467 * reply) when VALID==0 in the IIEPH1 register, then it saves the *
1468 * contents of the packet's header flit in the IIEPH1 and IIEPH2 *
1469 * registers, sets the VALID bit in IIEPH1, clears the OVERRUN bit, *
1470 * and assigns a value to the ERR_TYPE field which indicates the *
1471 * specific nature of the error. The II recognizes four different *
1472 * types of errors: short request packets (ERR_TYPE==2), short reply *
1473 * packets (ERR_TYPE==3), long request packets (ERR_TYPE==4) and long *
1474 * reply packets (ERR_TYPE==5). The encodings for these types of *
1475 * errors were chosen to be consistent with the same types of errors *
1476 * indicated by the ERR_TYPE field in the LB_ERROR_HDR1 register (in *
1477 * the LB unit). If the II detects an illegal incoming Duplonet *
1478 * packet when VALID==1 in the IIEPH1 register, then it merely sets *
1479 * the OVERRUN bit to indicate that a subsequent error has happened, *
1480 * and does nothing further. *
1481 * *
1482 ************************************************************************/
1483
1484typedef union ii_iieph1_u {
1485 u64 ii_iieph1_regval;
1486 struct {
1487 u64 i_command:7;
1488 u64 i_rsvd_5:1;
1489 u64 i_suppl:14;
1490 u64 i_rsvd_4:1;
1491 u64 i_source:14;
1492 u64 i_rsvd_3:1;
1493 u64 i_err_type:4;
1494 u64 i_rsvd_2:4;
1495 u64 i_overrun:1;
1496 u64 i_rsvd_1:3;
1497 u64 i_valid:1;
1498 u64 i_rsvd:13;
1499 } ii_iieph1_fld_s;
1500} ii_iieph1_u_t;
1501
1502/************************************************************************
1503 * *
1504 * This register holds the Address field from the header flit of an *
1505 * incoming erroneous Duplonet packet, along with the tail bit which *
1506 * accompanied this header flit. This register is essentially an *
1507 * extension of IIEPH1. Two registers were necessary because the 64 *
1508 * bits available in only a single register were insufficient to *
1509 * capture the entire header flit of an erroneous packet. *
1510 * *
1511 ************************************************************************/
1512
1513typedef union ii_iieph2_u {
1514 u64 ii_iieph2_regval;
1515 struct {
1516 u64 i_rsvd_0:3;
1517 u64 i_address:47;
1518 u64 i_rsvd_1:10;
1519 u64 i_tail:1;
1520 u64 i_rsvd:3;
1521 } ii_iieph2_fld_s;
1522} ii_iieph2_u_t;
1523
1524/******************************/
1525
1526/************************************************************************
1527 * *
1528 * This register's value is a bit vector that guards access from SXBs *
1529 * to local registers within the II as well as to external Crosstalk *
1530 * widgets *
1531 * *
1532 ************************************************************************/
1533
1534typedef union ii_islapr_u {
1535 u64 ii_islapr_regval;
1536 struct {
1537 u64 i_region:64;
1538 } ii_islapr_fld_s;
1539} ii_islapr_u_t;
1540
1541/************************************************************************
1542 * *
1543 * A write to this register of the 56-bit value "Pup+Bun" will cause *
1544 * the bit in the ISLAPR register corresponding to the region of the *
1545 * requestor to be set (access allowed). (
1546 * *
1547 ************************************************************************/
1548
1549typedef union ii_islapo_u {
1550 u64 ii_islapo_regval;
1551 struct {
1552 u64 i_io_sbx_ovrride:56;
1553 u64 i_rsvd:8;
1554 } ii_islapo_fld_s;
1555} ii_islapo_u_t;
1556
1557/************************************************************************
1558 * *
1559 * Determines how long the wrapper will wait aftr an interrupt is *
1560 * initially issued from the II before it times out the outstanding *
1561 * interrupt and drops it from the interrupt queue. *
1562 * *
1563 ************************************************************************/
1564
1565typedef union ii_iwi_u {
1566 u64 ii_iwi_regval;
1567 struct {
1568 u64 i_prescale:24;
1569 u64 i_rsvd:8;
1570 u64 i_timeout:8;
1571 u64 i_rsvd1:8;
1572 u64 i_intrpt_retry_period:8;
1573 u64 i_rsvd2:8;
1574 } ii_iwi_fld_s;
1575} ii_iwi_u_t;
1576
1577/************************************************************************
1578 * *
1579 * Log errors which have occurred in the II wrapper. The errors are *
1580 * cleared by writing to the IECLR register. *
1581 * *
1582 ************************************************************************/
1583
1584typedef union ii_iwel_u {
1585 u64 ii_iwel_regval;
1586 struct {
1587 u64 i_intr_timed_out:1;
1588 u64 i_rsvd:7;
1589 u64 i_cam_overflow:1;
1590 u64 i_cam_read_miss:1;
1591 u64 i_rsvd1:2;
1592 u64 i_ioq_rep_underflow:1;
1593 u64 i_ioq_req_underflow:1;
1594 u64 i_ioq_rep_overflow:1;
1595 u64 i_ioq_req_overflow:1;
1596 u64 i_iiq_rep_overflow:1;
1597 u64 i_iiq_req_overflow:1;
1598 u64 i_rsvd2:6;
1599 u64 i_ii_xn_rep_cred_over_under:1;
1600 u64 i_ii_xn_req_cred_over_under:1;
1601 u64 i_rsvd3:6;
1602 u64 i_ii_xn_invalid_cmd:1;
1603 u64 i_xn_ii_invalid_cmd:1;
1604 u64 i_rsvd4:30;
1605 } ii_iwel_fld_s;
1606} ii_iwel_u_t;
1607
1608/************************************************************************
1609 * *
1610 * Controls the II wrapper. *
1611 * *
1612 ************************************************************************/
1613
1614typedef union ii_iwc_u {
1615 u64 ii_iwc_regval;
1616 struct {
1617 u64 i_dma_byte_swap:1;
1618 u64 i_rsvd:3;
1619 u64 i_cam_read_lines_reset:1;
1620 u64 i_rsvd1:3;
1621 u64 i_ii_xn_cred_over_under_log:1;
1622 u64 i_rsvd2:19;
1623 u64 i_xn_rep_iq_depth:5;
1624 u64 i_rsvd3:3;
1625 u64 i_xn_req_iq_depth:5;
1626 u64 i_rsvd4:3;
1627 u64 i_iiq_depth:6;
1628 u64 i_rsvd5:12;
1629 u64 i_force_rep_cred:1;
1630 u64 i_force_req_cred:1;
1631 } ii_iwc_fld_s;
1632} ii_iwc_u_t;
1633
1634/************************************************************************
1635 * *
1636 * Status in the II wrapper. *
1637 * *
1638 ************************************************************************/
1639
1640typedef union ii_iws_u {
1641 u64 ii_iws_regval;
1642 struct {
1643 u64 i_xn_rep_iq_credits:5;
1644 u64 i_rsvd:3;
1645 u64 i_xn_req_iq_credits:5;
1646 u64 i_rsvd1:51;
1647 } ii_iws_fld_s;
1648} ii_iws_u_t;
1649
1650/************************************************************************
1651 * *
1652 * Masks errors in the IWEL register. *
1653 * *
1654 ************************************************************************/
1655
1656typedef union ii_iweim_u {
1657 u64 ii_iweim_regval;
1658 struct {
1659 u64 i_intr_timed_out:1;
1660 u64 i_rsvd:7;
1661 u64 i_cam_overflow:1;
1662 u64 i_cam_read_miss:1;
1663 u64 i_rsvd1:2;
1664 u64 i_ioq_rep_underflow:1;
1665 u64 i_ioq_req_underflow:1;
1666 u64 i_ioq_rep_overflow:1;
1667 u64 i_ioq_req_overflow:1;
1668 u64 i_iiq_rep_overflow:1;
1669 u64 i_iiq_req_overflow:1;
1670 u64 i_rsvd2:6;
1671 u64 i_ii_xn_rep_cred_overflow:1;
1672 u64 i_ii_xn_req_cred_overflow:1;
1673 u64 i_rsvd3:6;
1674 u64 i_ii_xn_invalid_cmd:1;
1675 u64 i_xn_ii_invalid_cmd:1;
1676 u64 i_rsvd4:30;
1677 } ii_iweim_fld_s;
1678} ii_iweim_u_t;
1679
1680/************************************************************************
1681 * *
1682 * A write to this register causes a particular field in the *
1683 * corresponding widget's PRB entry to be adjusted up or down by 1. *
1684 * This counter should be used when recovering from error and reset *
1685 * conditions. Note that software would be capable of causing *
1686 * inadvertent overflow or underflow of these counters. *
1687 * *
1688 ************************************************************************/
1689
1690typedef union ii_ipca_u {
1691 u64 ii_ipca_regval;
1692 struct {
1693 u64 i_wid:4;
1694 u64 i_adjust:1;
1695 u64 i_rsvd_1:3;
1696 u64 i_field:2;
1697 u64 i_rsvd:54;
1698 } ii_ipca_fld_s;
1699} ii_ipca_u_t;
1700
1701/************************************************************************
1702 * *
1703 * There are 8 instances of this register. This register contains *
1704 * the information that the II has to remember once it has launched a *
1705 * PIO Read operation. The contents are used to form the correct *
1706 * Router Network packet and direct the Crosstalk reply to the *
1707 * appropriate processor. *
1708 * *
1709 ************************************************************************/
1710
1711typedef union ii_iprte0a_u {
1712 u64 ii_iprte0a_regval;
1713 struct {
1714 u64 i_rsvd_1:54;
1715 u64 i_widget:4;
1716 u64 i_to_cnt:5;
1717 u64 i_vld:1;
1718 } ii_iprte0a_fld_s;
1719} ii_iprte0a_u_t;
1720
1721/************************************************************************
1722 * *
1723 * There are 8 instances of this register. This register contains *
1724 * the information that the II has to remember once it has launched a *
1725 * PIO Read operation. The contents are used to form the correct *
1726 * Router Network packet and direct the Crosstalk reply to the *
1727 * appropriate processor. *
1728 * *
1729 ************************************************************************/
1730
1731typedef union ii_iprte1a_u {
1732 u64 ii_iprte1a_regval;
1733 struct {
1734 u64 i_rsvd_1:54;
1735 u64 i_widget:4;
1736 u64 i_to_cnt:5;
1737 u64 i_vld:1;
1738 } ii_iprte1a_fld_s;
1739} ii_iprte1a_u_t;
1740
1741/************************************************************************
1742 * *
1743 * There are 8 instances of this register. This register contains *
1744 * the information that the II has to remember once it has launched a *
1745 * PIO Read operation. The contents are used to form the correct *
1746 * Router Network packet and direct the Crosstalk reply to the *
1747 * appropriate processor. *
1748 * *
1749 ************************************************************************/
1750
1751typedef union ii_iprte2a_u {
1752 u64 ii_iprte2a_regval;
1753 struct {
1754 u64 i_rsvd_1:54;
1755 u64 i_widget:4;
1756 u64 i_to_cnt:5;
1757 u64 i_vld:1;
1758 } ii_iprte2a_fld_s;
1759} ii_iprte2a_u_t;
1760
1761/************************************************************************
1762 * *
1763 * There are 8 instances of this register. This register contains *
1764 * the information that the II has to remember once it has launched a *
1765 * PIO Read operation. The contents are used to form the correct *
1766 * Router Network packet and direct the Crosstalk reply to the *
1767 * appropriate processor. *
1768 * *
1769 ************************************************************************/
1770
1771typedef union ii_iprte3a_u {
1772 u64 ii_iprte3a_regval;
1773 struct {
1774 u64 i_rsvd_1:54;
1775 u64 i_widget:4;
1776 u64 i_to_cnt:5;
1777 u64 i_vld:1;
1778 } ii_iprte3a_fld_s;
1779} ii_iprte3a_u_t;
1780
1781/************************************************************************
1782 * *
1783 * There are 8 instances of this register. This register contains *
1784 * the information that the II has to remember once it has launched a *
1785 * PIO Read operation. The contents are used to form the correct *
1786 * Router Network packet and direct the Crosstalk reply to the *
1787 * appropriate processor. *
1788 * *
1789 ************************************************************************/
1790
1791typedef union ii_iprte4a_u {
1792 u64 ii_iprte4a_regval;
1793 struct {
1794 u64 i_rsvd_1:54;
1795 u64 i_widget:4;
1796 u64 i_to_cnt:5;
1797 u64 i_vld:1;
1798 } ii_iprte4a_fld_s;
1799} ii_iprte4a_u_t;
1800
1801/************************************************************************
1802 * *
1803 * There are 8 instances of this register. This register contains *
1804 * the information that the II has to remember once it has launched a *
1805 * PIO Read operation. The contents are used to form the correct *
1806 * Router Network packet and direct the Crosstalk reply to the *
1807 * appropriate processor. *
1808 * *
1809 ************************************************************************/
1810
1811typedef union ii_iprte5a_u {
1812 u64 ii_iprte5a_regval;
1813 struct {
1814 u64 i_rsvd_1:54;
1815 u64 i_widget:4;
1816 u64 i_to_cnt:5;
1817 u64 i_vld:1;
1818 } ii_iprte5a_fld_s;
1819} ii_iprte5a_u_t;
1820
1821/************************************************************************
1822 * *
1823 * There are 8 instances of this register. This register contains *
1824 * the information that the II has to remember once it has launched a *
1825 * PIO Read operation. The contents are used to form the correct *
1826 * Router Network packet and direct the Crosstalk reply to the *
1827 * appropriate processor. *
1828 * *
1829 ************************************************************************/
1830
1831typedef union ii_iprte6a_u {
1832 u64 ii_iprte6a_regval;
1833 struct {
1834 u64 i_rsvd_1:54;
1835 u64 i_widget:4;
1836 u64 i_to_cnt:5;
1837 u64 i_vld:1;
1838 } ii_iprte6a_fld_s;
1839} ii_iprte6a_u_t;
1840
1841/************************************************************************
1842 * *
1843 * There are 8 instances of this register. This register contains *
1844 * the information that the II has to remember once it has launched a *
1845 * PIO Read operation. The contents are used to form the correct *
1846 * Router Network packet and direct the Crosstalk reply to the *
1847 * appropriate processor. *
1848 * *
1849 ************************************************************************/
1850
1851typedef union ii_iprte7a_u {
1852 u64 ii_iprte7a_regval;
1853 struct {
1854 u64 i_rsvd_1:54;
1855 u64 i_widget:4;
1856 u64 i_to_cnt:5;
1857 u64 i_vld:1;
1858 } ii_iprtea7_fld_s;
1859} ii_iprte7a_u_t;
1860
1861/************************************************************************
1862 * *
1863 * There are 8 instances of this register. This register contains *
1864 * the information that the II has to remember once it has launched a *
1865 * PIO Read operation. The contents are used to form the correct *
1866 * Router Network packet and direct the Crosstalk reply to the *
1867 * appropriate processor. *
1868 * *
1869 ************************************************************************/
1870
1871typedef union ii_iprte0b_u {
1872 u64 ii_iprte0b_regval;
1873 struct {
1874 u64 i_rsvd_1:3;
1875 u64 i_address:47;
1876 u64 i_init:3;
1877 u64 i_source:11;
1878 } ii_iprte0b_fld_s;
1879} ii_iprte0b_u_t;
1880
1881/************************************************************************
1882 * *
1883 * There are 8 instances of this register. This register contains *
1884 * the information that the II has to remember once it has launched a *
1885 * PIO Read operation. The contents are used to form the correct *
1886 * Router Network packet and direct the Crosstalk reply to the *
1887 * appropriate processor. *
1888 * *
1889 ************************************************************************/
1890
1891typedef union ii_iprte1b_u {
1892 u64 ii_iprte1b_regval;
1893 struct {
1894 u64 i_rsvd_1:3;
1895 u64 i_address:47;
1896 u64 i_init:3;
1897 u64 i_source:11;
1898 } ii_iprte1b_fld_s;
1899} ii_iprte1b_u_t;
1900
1901/************************************************************************
1902 * *
1903 * There are 8 instances of this register. This register contains *
1904 * the information that the II has to remember once it has launched a *
1905 * PIO Read operation. The contents are used to form the correct *
1906 * Router Network packet and direct the Crosstalk reply to the *
1907 * appropriate processor. *
1908 * *
1909 ************************************************************************/
1910
1911typedef union ii_iprte2b_u {
1912 u64 ii_iprte2b_regval;
1913 struct {
1914 u64 i_rsvd_1:3;
1915 u64 i_address:47;
1916 u64 i_init:3;
1917 u64 i_source:11;
1918 } ii_iprte2b_fld_s;
1919} ii_iprte2b_u_t;
1920
1921/************************************************************************
1922 * *
1923 * There are 8 instances of this register. This register contains *
1924 * the information that the II has to remember once it has launched a *
1925 * PIO Read operation. The contents are used to form the correct *
1926 * Router Network packet and direct the Crosstalk reply to the *
1927 * appropriate processor. *
1928 * *
1929 ************************************************************************/
1930
1931typedef union ii_iprte3b_u {
1932 u64 ii_iprte3b_regval;
1933 struct {
1934 u64 i_rsvd_1:3;
1935 u64 i_address:47;
1936 u64 i_init:3;
1937 u64 i_source:11;
1938 } ii_iprte3b_fld_s;
1939} ii_iprte3b_u_t;
1940
1941/************************************************************************
1942 * *
1943 * There are 8 instances of this register. This register contains *
1944 * the information that the II has to remember once it has launched a *
1945 * PIO Read operation. The contents are used to form the correct *
1946 * Router Network packet and direct the Crosstalk reply to the *
1947 * appropriate processor. *
1948 * *
1949 ************************************************************************/
1950
1951typedef union ii_iprte4b_u {
1952 u64 ii_iprte4b_regval;
1953 struct {
1954 u64 i_rsvd_1:3;
1955 u64 i_address:47;
1956 u64 i_init:3;
1957 u64 i_source:11;
1958 } ii_iprte4b_fld_s;
1959} ii_iprte4b_u_t;
1960
1961/************************************************************************
1962 * *
1963 * There are 8 instances of this register. This register contains *
1964 * the information that the II has to remember once it has launched a *
1965 * PIO Read operation. The contents are used to form the correct *
1966 * Router Network packet and direct the Crosstalk reply to the *
1967 * appropriate processor. *
1968 * *
1969 ************************************************************************/
1970
1971typedef union ii_iprte5b_u {
1972 u64 ii_iprte5b_regval;
1973 struct {
1974 u64 i_rsvd_1:3;
1975 u64 i_address:47;
1976 u64 i_init:3;
1977 u64 i_source:11;
1978 } ii_iprte5b_fld_s;
1979} ii_iprte5b_u_t;
1980
1981/************************************************************************
1982 * *
1983 * There are 8 instances of this register. This register contains *
1984 * the information that the II has to remember once it has launched a *
1985 * PIO Read operation. The contents are used to form the correct *
1986 * Router Network packet and direct the Crosstalk reply to the *
1987 * appropriate processor. *
1988 * *
1989 ************************************************************************/
1990
1991typedef union ii_iprte6b_u {
1992 u64 ii_iprte6b_regval;
1993 struct {
1994 u64 i_rsvd_1:3;
1995 u64 i_address:47;
1996 u64 i_init:3;
1997 u64 i_source:11;
1998
1999 } ii_iprte6b_fld_s;
2000} ii_iprte6b_u_t;
2001
2002/************************************************************************
2003 * *
2004 * There are 8 instances of this register. This register contains *
2005 * the information that the II has to remember once it has launched a *
2006 * PIO Read operation. The contents are used to form the correct *
2007 * Router Network packet and direct the Crosstalk reply to the *
2008 * appropriate processor. *
2009 * *
2010 ************************************************************************/
2011
2012typedef union ii_iprte7b_u {
2013 u64 ii_iprte7b_regval;
2014 struct {
2015 u64 i_rsvd_1:3;
2016 u64 i_address:47;
2017 u64 i_init:3;
2018 u64 i_source:11;
2019 } ii_iprte7b_fld_s;
2020} ii_iprte7b_u_t;
2021
2022/************************************************************************
2023 * *
2024 * Description: SHub II contains a feature which did not exist in *
2025 * the Hub which automatically cleans up after a Read Response *
2026 * timeout, including deallocation of the IPRTE and recovery of IBuf *
2027 * space. The inclusion of this register in SHub is for backward *
2028 * compatibility *
2029 * A write to this register causes an entry from the table of *
2030 * outstanding PIO Read Requests to be freed and returned to the *
2031 * stack of free entries. This register is used in handling the *
2032 * timeout errors that result in a PIO Reply never returning from *
2033 * Crosstalk. *
2034 * Note that this register does not affect the contents of the IPRTE *
2035 * registers. The Valid bits in those registers have to be *
2036 * specifically turned off by software. *
2037 * *
2038 ************************************************************************/
2039
2040typedef union ii_ipdr_u {
2041 u64 ii_ipdr_regval;
2042 struct {
2043 u64 i_te:3;
2044 u64 i_rsvd_1:1;
2045 u64 i_pnd:1;
2046 u64 i_init_rpcnt:1;
2047 u64 i_rsvd:58;
2048 } ii_ipdr_fld_s;
2049} ii_ipdr_u_t;
2050
2051/************************************************************************
2052 * *
2053 * A write to this register causes a CRB entry to be returned to the *
2054 * queue of free CRBs. The entry should have previously been cleared *
2055 * (mark bit) via backdoor access to the pertinent CRB entry. This *
2056 * register is used in the last step of handling the errors that are *
2057 * captured and marked in CRB entries. Briefly: 1) first error for *
2058 * DMA write from a particular device, and first error for a *
2059 * particular BTE stream, lead to a marked CRB entry, and processor *
2060 * interrupt, 2) software reads the error information captured in the *
2061 * CRB entry, and presumably takes some corrective action, 3) *
2062 * software clears the mark bit, and finally 4) software writes to *
2063 * the ICDR register to return the CRB entry to the list of free CRB *
2064 * entries. *
2065 * *
2066 ************************************************************************/
2067
2068typedef union ii_icdr_u {
2069 u64 ii_icdr_regval;
2070 struct {
2071 u64 i_crb_num:4;
2072 u64 i_pnd:1;
2073 u64 i_rsvd:59;
2074 } ii_icdr_fld_s;
2075} ii_icdr_u_t;
2076
2077/************************************************************************
2078 * *
2079 * This register provides debug access to two FIFOs inside of II. *
2080 * Both IOQ_MAX* fields of this register contain the instantaneous *
2081 * depth (in units of the number of available entries) of the *
2082 * associated IOQ FIFO. A read of this register will return the *
2083 * number of free entries on each FIFO at the time of the read. So *
2084 * when a FIFO is idle, the associated field contains the maximum *
2085 * depth of the FIFO. This register is writable for debug reasons *
2086 * and is intended to be written with the maximum desired FIFO depth *
2087 * while the FIFO is idle. Software must assure that II is idle when *
2088 * this register is written. If there are any active entries in any *
2089 * of these FIFOs when this register is written, the results are *
2090 * undefined. *
2091 * *
2092 ************************************************************************/
2093
2094typedef union ii_ifdr_u {
2095 u64 ii_ifdr_regval;
2096 struct {
2097 u64 i_ioq_max_rq:7;
2098 u64 i_set_ioq_rq:1;
2099 u64 i_ioq_max_rp:7;
2100 u64 i_set_ioq_rp:1;
2101 u64 i_rsvd:48;
2102 } ii_ifdr_fld_s;
2103} ii_ifdr_u_t;
2104
2105/************************************************************************
2106 * *
2107 * This register allows the II to become sluggish in removing *
2108 * messages from its inbound queue (IIQ). This will cause messages to *
2109 * back up in either virtual channel. Disabling the "molasses" mode *
2110 * subsequently allows the II to be tested under stress. In the *
2111 * sluggish ("Molasses") mode, the localized effects of congestion *
2112 * can be observed. *
2113 * *
2114 ************************************************************************/
2115
2116typedef union ii_iiap_u {
2117 u64 ii_iiap_regval;
2118 struct {
2119 u64 i_rq_mls:6;
2120 u64 i_rsvd_1:2;
2121 u64 i_rp_mls:6;
2122 u64 i_rsvd:50;
2123 } ii_iiap_fld_s;
2124} ii_iiap_u_t;
2125
2126/************************************************************************
2127 * *
2128 * This register allows several parameters of CRB operation to be *
2129 * set. Note that writing to this register can have catastrophic side *
2130 * effects, if the CRB is not quiescent, i.e. if the CRB is *
2131 * processing protocol messages when the write occurs. *
2132 * *
2133 ************************************************************************/
2134
2135typedef union ii_icmr_u {
2136 u64 ii_icmr_regval;
2137 struct {
2138 u64 i_sp_msg:1;
2139 u64 i_rd_hdr:1;
2140 u64 i_rsvd_4:2;
2141 u64 i_c_cnt:4;
2142 u64 i_rsvd_3:4;
2143 u64 i_clr_rqpd:1;
2144 u64 i_clr_rppd:1;
2145 u64 i_rsvd_2:2;
2146 u64 i_fc_cnt:4;
2147 u64 i_crb_vld:15;
2148 u64 i_crb_mark:15;
2149 u64 i_rsvd_1:2;
2150 u64 i_precise:1;
2151 u64 i_rsvd:11;
2152 } ii_icmr_fld_s;
2153} ii_icmr_u_t;
2154
2155/************************************************************************
2156 * *
2157 * This register allows control of the table portion of the CRB *
2158 * logic via software. Control operations from this register have *
2159 * priority over all incoming Crosstalk or BTE requests. *
2160 * *
2161 ************************************************************************/
2162
2163typedef union ii_iccr_u {
2164 u64 ii_iccr_regval;
2165 struct {
2166 u64 i_crb_num:4;
2167 u64 i_rsvd_1:4;
2168 u64 i_cmd:8;
2169 u64 i_pending:1;
2170 u64 i_rsvd:47;
2171 } ii_iccr_fld_s;
2172} ii_iccr_u_t;
2173
2174/************************************************************************
2175 * *
2176 * This register allows the maximum timeout value to be programmed. *
2177 * *
2178 ************************************************************************/
2179
2180typedef union ii_icto_u {
2181 u64 ii_icto_regval;
2182 struct {
2183 u64 i_timeout:8;
2184 u64 i_rsvd:56;
2185 } ii_icto_fld_s;
2186} ii_icto_u_t;
2187
2188/************************************************************************
2189 * *
2190 * This register allows the timeout prescalar to be programmed. An *
2191 * internal counter is associated with this register. When the *
2192 * internal counter reaches the value of the PRESCALE field, the *
2193 * timer registers in all valid CRBs are incremented (CRBx_D[TIMEOUT] *
2194 * field). The internal counter resets to zero, and then continues *
2195 * counting. *
2196 * *
2197 ************************************************************************/
2198
2199typedef union ii_ictp_u {
2200 u64 ii_ictp_regval;
2201 struct {
2202 u64 i_prescale:24;
2203 u64 i_rsvd:40;
2204 } ii_ictp_fld_s;
2205} ii_ictp_u_t;
2206
2207/************************************************************************
2208 * *
2209 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
2210 * used for Crosstalk operations (both cacheline and partial *
2211 * operations) or BTE/IO. Because the CRB entries are very wide, five *
2212 * registers (_A to _E) are required to read and write each entry. *
2213 * The CRB Entry registers can be conceptualized as rows and columns *
2214 * (illustrated in the table above). Each row contains the 4 *
2215 * registers required for a single CRB Entry. The first doubleword *
2216 * (column) for each entry is labeled A, and the second doubleword *
2217 * (higher address) is labeled B, the third doubleword is labeled C, *
2218 * the fourth doubleword is labeled D and the fifth doubleword is *
2219 * labeled E. All CRB entries have their addresses on a quarter *
2220 * cacheline aligned boundary. *
2221 * Upon reset, only the following fields are initialized: valid *
2222 * (VLD), priority count, timeout, timeout valid, and context valid. *
2223 * All other bits should be cleared by software before use (after *
2224 * recovering any potential error state from before the reset). *
2225 * The following four tables summarize the format for the four *
2226 * registers that are used for each ICRB# Entry. *
2227 * *
2228 ************************************************************************/
2229
2230typedef union ii_icrb0_a_u {
2231 u64 ii_icrb0_a_regval;
2232 struct {
2233 u64 ia_iow:1;
2234 u64 ia_vld:1;
2235 u64 ia_addr:47;
2236 u64 ia_tnum:5;
2237 u64 ia_sidn:4;
2238 u64 ia_rsvd:6;
2239 } ii_icrb0_a_fld_s;
2240} ii_icrb0_a_u_t;
2241
2242/************************************************************************
2243 * *
2244 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
2245 * used for Crosstalk operations (both cacheline and partial *
2246 * operations) or BTE/IO. Because the CRB entries are very wide, five *
2247 * registers (_A to _E) are required to read and write each entry. *
2248 * *
2249 ************************************************************************/
2250
2251typedef union ii_icrb0_b_u {
2252 u64 ii_icrb0_b_regval;
2253 struct {
2254 u64 ib_xt_err:1;
2255 u64 ib_mark:1;
2256 u64 ib_ln_uce:1;
2257 u64 ib_errcode:3;
2258 u64 ib_error:1;
2259 u64 ib_stall__bte_1:1;
2260 u64 ib_stall__bte_0:1;
2261 u64 ib_stall__intr:1;
2262 u64 ib_stall_ib:1;
2263 u64 ib_intvn:1;
2264 u64 ib_wb:1;
2265 u64 ib_hold:1;
2266 u64 ib_ack:1;
2267 u64 ib_resp:1;
2268 u64 ib_ack_cnt:11;
2269 u64 ib_rsvd:7;
2270 u64 ib_exc:5;
2271 u64 ib_init:3;
2272 u64 ib_imsg:8;
2273 u64 ib_imsgtype:2;
2274 u64 ib_use_old:1;
2275 u64 ib_rsvd_1:11;
2276 } ii_icrb0_b_fld_s;
2277} ii_icrb0_b_u_t;
2278
2279/************************************************************************
2280 * *
2281 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
2282 * used for Crosstalk operations (both cacheline and partial *
2283 * operations) or BTE/IO. Because the CRB entries are very wide, five *
2284 * registers (_A to _E) are required to read and write each entry. *
2285 * *
2286 ************************************************************************/
2287
2288typedef union ii_icrb0_c_u {
2289 u64 ii_icrb0_c_regval;
2290 struct {
2291 u64 ic_source:15;
2292 u64 ic_size:2;
2293 u64 ic_ct:1;
2294 u64 ic_bte_num:1;
2295 u64 ic_gbr:1;
2296 u64 ic_resprqd:1;
2297 u64 ic_bo:1;
2298 u64 ic_suppl:15;
2299 u64 ic_rsvd:27;
2300 } ii_icrb0_c_fld_s;
2301} ii_icrb0_c_u_t;
2302
2303/************************************************************************
2304 * *
2305 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
2306 * used for Crosstalk operations (both cacheline and partial *
2307 * operations) or BTE/IO. Because the CRB entries are very wide, five *
2308 * registers (_A to _E) are required to read and write each entry. *
2309 * *
2310 ************************************************************************/
2311
2312typedef union ii_icrb0_d_u {
2313 u64 ii_icrb0_d_regval;
2314 struct {
2315 u64 id_pa_be:43;
2316 u64 id_bte_op:1;
2317 u64 id_pr_psc:4;
2318 u64 id_pr_cnt:4;
2319 u64 id_sleep:1;
2320 u64 id_rsvd:11;
2321 } ii_icrb0_d_fld_s;
2322} ii_icrb0_d_u_t;
2323
2324/************************************************************************
2325 * *
2326 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
2327 * used for Crosstalk operations (both cacheline and partial *
2328 * operations) or BTE/IO. Because the CRB entries are very wide, five *
2329 * registers (_A to _E) are required to read and write each entry. *
2330 * *
2331 ************************************************************************/
2332
2333typedef union ii_icrb0_e_u {
2334 u64 ii_icrb0_e_regval;
2335 struct {
2336 u64 ie_timeout:8;
2337 u64 ie_context:15;
2338 u64 ie_rsvd:1;
2339 u64 ie_tvld:1;
2340 u64 ie_cvld:1;
2341 u64 ie_rsvd_0:38;
2342 } ii_icrb0_e_fld_s;
2343} ii_icrb0_e_u_t;
2344
2345/************************************************************************
2346 * *
2347 * This register contains the lower 64 bits of the header of the *
2348 * spurious message captured by II. Valid when the SP_MSG bit in ICMR *
2349 * register is set. *
2350 * *
2351 ************************************************************************/
2352
2353typedef union ii_icsml_u {
2354 u64 ii_icsml_regval;
2355 struct {
2356 u64 i_tt_addr:47;
2357 u64 i_newsuppl_ex:14;
2358 u64 i_reserved:2;
2359 u64 i_overflow:1;
2360 } ii_icsml_fld_s;
2361} ii_icsml_u_t;
2362
2363/************************************************************************
2364 * *
2365 * This register contains the middle 64 bits of the header of the *
2366 * spurious message captured by II. Valid when the SP_MSG bit in ICMR *
2367 * register is set. *
2368 * *
2369 ************************************************************************/
2370
2371typedef union ii_icsmm_u {
2372 u64 ii_icsmm_regval;
2373 struct {
2374 u64 i_tt_ack_cnt:11;
2375 u64 i_reserved:53;
2376 } ii_icsmm_fld_s;
2377} ii_icsmm_u_t;
2378
2379/************************************************************************
2380 * *
2381 * This register contains the microscopic state, all the inputs to *
2382 * the protocol table, captured with the spurious message. Valid when *
2383 * the SP_MSG bit in the ICMR register is set. *
2384 * *
2385 ************************************************************************/
2386
2387typedef union ii_icsmh_u {
2388 u64 ii_icsmh_regval;
2389 struct {
2390 u64 i_tt_vld:1;
2391 u64 i_xerr:1;
2392 u64 i_ft_cwact_o:1;
2393 u64 i_ft_wact_o:1;
2394 u64 i_ft_active_o:1;
2395 u64 i_sync:1;
2396 u64 i_mnusg:1;
2397 u64 i_mnusz:1;
2398 u64 i_plusz:1;
2399 u64 i_plusg:1;
2400 u64 i_tt_exc:5;
2401 u64 i_tt_wb:1;
2402 u64 i_tt_hold:1;
2403 u64 i_tt_ack:1;
2404 u64 i_tt_resp:1;
2405 u64 i_tt_intvn:1;
2406 u64 i_g_stall_bte1:1;
2407 u64 i_g_stall_bte0:1;
2408 u64 i_g_stall_il:1;
2409 u64 i_g_stall_ib:1;
2410 u64 i_tt_imsg:8;
2411 u64 i_tt_imsgtype:2;
2412 u64 i_tt_use_old:1;
2413 u64 i_tt_respreqd:1;
2414 u64 i_tt_bte_num:1;
2415 u64 i_cbn:1;
2416 u64 i_match:1;
2417 u64 i_rpcnt_lt_34:1;
2418 u64 i_rpcnt_ge_34:1;
2419 u64 i_rpcnt_lt_18:1;
2420 u64 i_rpcnt_ge_18:1;
2421 u64 i_rpcnt_lt_2:1;
2422 u64 i_rpcnt_ge_2:1;
2423 u64 i_rqcnt_lt_18:1;
2424 u64 i_rqcnt_ge_18:1;
2425 u64 i_rqcnt_lt_2:1;
2426 u64 i_rqcnt_ge_2:1;
2427 u64 i_tt_device:7;
2428 u64 i_tt_init:3;
2429 u64 i_reserved:5;
2430 } ii_icsmh_fld_s;
2431} ii_icsmh_u_t;
2432
2433/************************************************************************
2434 * *
2435 * The Shub DEBUG unit provides a 3-bit selection signal to the *
2436 * II core and a 3-bit selection signal to the fsbclk domain in the II *
2437 * wrapper. *
2438 * *
2439 ************************************************************************/
2440
2441typedef union ii_idbss_u {
2442 u64 ii_idbss_regval;
2443 struct {
2444 u64 i_iioclk_core_submenu:3;
2445 u64 i_rsvd:5;
2446 u64 i_fsbclk_wrapper_submenu:3;
2447 u64 i_rsvd_1:5;
2448 u64 i_iioclk_menu:5;
2449 u64 i_rsvd_2:43;
2450 } ii_idbss_fld_s;
2451} ii_idbss_u_t;
2452
2453/************************************************************************
2454 * *
2455 * Description: This register is used to set up the length for a *
2456 * transfer and then to monitor the progress of that transfer. This *
2457 * register needs to be initialized before a transfer is started. A *
2458 * legitimate write to this register will set the Busy bit, clear the *
2459 * Error bit, and initialize the length to the value desired. *
2460 * While the transfer is in progress, hardware will decrement the *
2461 * length field with each successful block that is copied. Once the *
2462 * transfer completes, hardware will clear the Busy bit. The length *
2463 * field will also contain the number of cache lines left to be *
2464 * transferred. *
2465 * *
2466 ************************************************************************/
2467
2468typedef union ii_ibls0_u {
2469 u64 ii_ibls0_regval;
2470 struct {
2471 u64 i_length:16;
2472 u64 i_error:1;
2473 u64 i_rsvd_1:3;
2474 u64 i_busy:1;
2475 u64 i_rsvd:43;
2476 } ii_ibls0_fld_s;
2477} ii_ibls0_u_t;
2478
2479/************************************************************************
2480 * *
2481 * This register should be loaded before a transfer is started. The *
2482 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical *
2483 * address as described in Section 1.3, Figure2 and Figure3. Since *
2484 * the bottom 7 bits of the address are always taken to be zero, BTE *
2485 * transfers are always cacheline-aligned. *
2486 * *
2487 ************************************************************************/
2488
2489typedef union ii_ibsa0_u {
2490 u64 ii_ibsa0_regval;
2491 struct {
2492 u64 i_rsvd_1:7;
2493 u64 i_addr:42;
2494 u64 i_rsvd:15;
2495 } ii_ibsa0_fld_s;
2496} ii_ibsa0_u_t;
2497
2498/************************************************************************
2499 * *
2500 * This register should be loaded before a transfer is started. The *
2501 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical *
2502 * address as described in Section 1.3, Figure2 and Figure3. Since *
2503 * the bottom 7 bits of the address are always taken to be zero, BTE *
2504 * transfers are always cacheline-aligned. *
2505 * *
2506 ************************************************************************/
2507
2508typedef union ii_ibda0_u {
2509 u64 ii_ibda0_regval;
2510 struct {
2511 u64 i_rsvd_1:7;
2512 u64 i_addr:42;
2513 u64 i_rsvd:15;
2514 } ii_ibda0_fld_s;
2515} ii_ibda0_u_t;
2516
2517/************************************************************************
2518 * *
2519 * Writing to this register sets up the attributes of the transfer *
2520 * and initiates the transfer operation. Reading this register has *
2521 * the side effect of terminating any transfer in progress. Note: *
2522 * stopping a transfer midstream could have an adverse impact on the *
2523 * other BTE. If a BTE stream has to be stopped (due to error *
2524 * handling for example), both BTE streams should be stopped and *
2525 * their transfers discarded. *
2526 * *
2527 ************************************************************************/
2528
2529typedef union ii_ibct0_u {
2530 u64 ii_ibct0_regval;
2531 struct {
2532 u64 i_zerofill:1;
2533 u64 i_rsvd_2:3;
2534 u64 i_notify:1;
2535 u64 i_rsvd_1:3;
2536 u64 i_poison:1;
2537 u64 i_rsvd:55;
2538 } ii_ibct0_fld_s;
2539} ii_ibct0_u_t;
2540
2541/************************************************************************
2542 * *
2543 * This register contains the address to which the WINV is sent. *
2544 * This address has to be cache line aligned. *
2545 * *
2546 ************************************************************************/
2547
2548typedef union ii_ibna0_u {
2549 u64 ii_ibna0_regval;
2550 struct {
2551 u64 i_rsvd_1:7;
2552 u64 i_addr:42;
2553 u64 i_rsvd:15;
2554 } ii_ibna0_fld_s;
2555} ii_ibna0_u_t;
2556
2557/************************************************************************
2558 * *
2559 * This register contains the programmable level as well as the node *
2560 * ID and PI unit of the processor to which the interrupt will be *
2561 * sent. *
2562 * *
2563 ************************************************************************/
2564
2565typedef union ii_ibia0_u {
2566 u64 ii_ibia0_regval;
2567 struct {
2568 u64 i_rsvd_2:1;
2569 u64 i_node_id:11;
2570 u64 i_rsvd_1:4;
2571 u64 i_level:7;
2572 u64 i_rsvd:41;
2573 } ii_ibia0_fld_s;
2574} ii_ibia0_u_t;
2575
2576/************************************************************************
2577 * *
2578 * Description: This register is used to set up the length for a *
2579 * transfer and then to monitor the progress of that transfer. This *
2580 * register needs to be initialized before a transfer is started. A *
2581 * legitimate write to this register will set the Busy bit, clear the *
2582 * Error bit, and initialize the length to the value desired. *
2583 * While the transfer is in progress, hardware will decrement the *
2584 * length field with each successful block that is copied. Once the *
2585 * transfer completes, hardware will clear the Busy bit. The length *
2586 * field will also contain the number of cache lines left to be *
2587 * transferred. *
2588 * *
2589 ************************************************************************/
2590
2591typedef union ii_ibls1_u {
2592 u64 ii_ibls1_regval;
2593 struct {
2594 u64 i_length:16;
2595 u64 i_error:1;
2596 u64 i_rsvd_1:3;
2597 u64 i_busy:1;
2598 u64 i_rsvd:43;
2599 } ii_ibls1_fld_s;
2600} ii_ibls1_u_t;
2601
2602/************************************************************************
2603 * *
2604 * This register should be loaded before a transfer is started. The *
2605 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical *
2606 * address as described in Section 1.3, Figure2 and Figure3. Since *
2607 * the bottom 7 bits of the address are always taken to be zero, BTE *
2608 * transfers are always cacheline-aligned. *
2609 * *
2610 ************************************************************************/
2611
2612typedef union ii_ibsa1_u {
2613 u64 ii_ibsa1_regval;
2614 struct {
2615 u64 i_rsvd_1:7;
2616 u64 i_addr:33;
2617 u64 i_rsvd:24;
2618 } ii_ibsa1_fld_s;
2619} ii_ibsa1_u_t;
2620
2621/************************************************************************
2622 * *
2623 * This register should be loaded before a transfer is started. The *
2624 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical *
2625 * address as described in Section 1.3, Figure2 and Figure3. Since *
2626 * the bottom 7 bits of the address are always taken to be zero, BTE *
2627 * transfers are always cacheline-aligned. *
2628 * *
2629 ************************************************************************/
2630
2631typedef union ii_ibda1_u {
2632 u64 ii_ibda1_regval;
2633 struct {
2634 u64 i_rsvd_1:7;
2635 u64 i_addr:33;
2636 u64 i_rsvd:24;
2637 } ii_ibda1_fld_s;
2638} ii_ibda1_u_t;
2639
2640/************************************************************************
2641 * *
2642 * Writing to this register sets up the attributes of the transfer *
2643 * and initiates the transfer operation. Reading this register has *
2644 * the side effect of terminating any transfer in progress. Note: *
2645 * stopping a transfer midstream could have an adverse impact on the *
2646 * other BTE. If a BTE stream has to be stopped (due to error *
2647 * handling for example), both BTE streams should be stopped and *
2648 * their transfers discarded. *
2649 * *
2650 ************************************************************************/
2651
2652typedef union ii_ibct1_u {
2653 u64 ii_ibct1_regval;
2654 struct {
2655 u64 i_zerofill:1;
2656 u64 i_rsvd_2:3;
2657 u64 i_notify:1;
2658 u64 i_rsvd_1:3;
2659 u64 i_poison:1;
2660 u64 i_rsvd:55;
2661 } ii_ibct1_fld_s;
2662} ii_ibct1_u_t;
2663
2664/************************************************************************
2665 * *
2666 * This register contains the address to which the WINV is sent. *
2667 * This address has to be cache line aligned. *
2668 * *
2669 ************************************************************************/
2670
2671typedef union ii_ibna1_u {
2672 u64 ii_ibna1_regval;
2673 struct {
2674 u64 i_rsvd_1:7;
2675 u64 i_addr:33;
2676 u64 i_rsvd:24;
2677 } ii_ibna1_fld_s;
2678} ii_ibna1_u_t;
2679
2680/************************************************************************
2681 * *
2682 * This register contains the programmable level as well as the node *
2683 * ID and PI unit of the processor to which the interrupt will be *
2684 * sent. *
2685 * *
2686 ************************************************************************/
2687
2688typedef union ii_ibia1_u {
2689 u64 ii_ibia1_regval;
2690 struct {
2691 u64 i_pi_id:1;
2692 u64 i_node_id:8;
2693 u64 i_rsvd_1:7;
2694 u64 i_level:7;
2695 u64 i_rsvd:41;
2696 } ii_ibia1_fld_s;
2697} ii_ibia1_u_t;
2698
2699/************************************************************************
2700 * *
2701 * This register defines the resources that feed information into *
2702 * the two performance counters located in the IO Performance *
2703 * Profiling Register. There are 17 different quantities that can be *
2704 * measured. Given these 17 different options, the two performance *
2705 * counters have 15 of them in common; menu selections 0 through 0xE *
2706 * are identical for each performance counter. As for the other two *
2707 * options, one is available from one performance counter and the *
2708 * other is available from the other performance counter. Hence, the *
2709 * II supports all 17*16=272 possible combinations of quantities to *
2710 * measure. *
2711 * *
2712 ************************************************************************/
2713
2714typedef union ii_ipcr_u {
2715 u64 ii_ipcr_regval;
2716 struct {
2717 u64 i_ippr0_c:4;
2718 u64 i_ippr1_c:4;
2719 u64 i_icct:8;
2720 u64 i_rsvd:48;
2721 } ii_ipcr_fld_s;
2722} ii_ipcr_u_t;
2723
2724/************************************************************************
2725 * *
2726 * *
2727 * *
2728 ************************************************************************/
2729
2730typedef union ii_ippr_u {
2731 u64 ii_ippr_regval;
2732 struct {
2733 u64 i_ippr0:32;
2734 u64 i_ippr1:32;
2735 } ii_ippr_fld_s;
2736} ii_ippr_u_t;
2737
2738/************************************************************************
2739 * *
2740 * The following defines which were not formed into structures are *
2741 * probably indentical to another register, and the name of the *
2742 * register is provided against each of these registers. This *
2743 * information needs to be checked carefully *
2744 * *
2745 * IIO_ICRB1_A IIO_ICRB0_A *
2746 * IIO_ICRB1_B IIO_ICRB0_B *
2747 * IIO_ICRB1_C IIO_ICRB0_C *
2748 * IIO_ICRB1_D IIO_ICRB0_D *
2749 * IIO_ICRB1_E IIO_ICRB0_E *
2750 * IIO_ICRB2_A IIO_ICRB0_A *
2751 * IIO_ICRB2_B IIO_ICRB0_B *
2752 * IIO_ICRB2_C IIO_ICRB0_C *
2753 * IIO_ICRB2_D IIO_ICRB0_D *
2754 * IIO_ICRB2_E IIO_ICRB0_E *
2755 * IIO_ICRB3_A IIO_ICRB0_A *
2756 * IIO_ICRB3_B IIO_ICRB0_B *
2757 * IIO_ICRB3_C IIO_ICRB0_C *
2758 * IIO_ICRB3_D IIO_ICRB0_D *
2759 * IIO_ICRB3_E IIO_ICRB0_E *
2760 * IIO_ICRB4_A IIO_ICRB0_A *
2761 * IIO_ICRB4_B IIO_ICRB0_B *
2762 * IIO_ICRB4_C IIO_ICRB0_C *
2763 * IIO_ICRB4_D IIO_ICRB0_D *
2764 * IIO_ICRB4_E IIO_ICRB0_E *
2765 * IIO_ICRB5_A IIO_ICRB0_A *
2766 * IIO_ICRB5_B IIO_ICRB0_B *
2767 * IIO_ICRB5_C IIO_ICRB0_C *
2768 * IIO_ICRB5_D IIO_ICRB0_D *
2769 * IIO_ICRB5_E IIO_ICRB0_E *
2770 * IIO_ICRB6_A IIO_ICRB0_A *
2771 * IIO_ICRB6_B IIO_ICRB0_B *
2772 * IIO_ICRB6_C IIO_ICRB0_C *
2773 * IIO_ICRB6_D IIO_ICRB0_D *
2774 * IIO_ICRB6_E IIO_ICRB0_E *
2775 * IIO_ICRB7_A IIO_ICRB0_A *
2776 * IIO_ICRB7_B IIO_ICRB0_B *
2777 * IIO_ICRB7_C IIO_ICRB0_C *
2778 * IIO_ICRB7_D IIO_ICRB0_D *
2779 * IIO_ICRB7_E IIO_ICRB0_E *
2780 * IIO_ICRB8_A IIO_ICRB0_A *
2781 * IIO_ICRB8_B IIO_ICRB0_B *
2782 * IIO_ICRB8_C IIO_ICRB0_C *
2783 * IIO_ICRB8_D IIO_ICRB0_D *
2784 * IIO_ICRB8_E IIO_ICRB0_E *
2785 * IIO_ICRB9_A IIO_ICRB0_A *
2786 * IIO_ICRB9_B IIO_ICRB0_B *
2787 * IIO_ICRB9_C IIO_ICRB0_C *
2788 * IIO_ICRB9_D IIO_ICRB0_D *
2789 * IIO_ICRB9_E IIO_ICRB0_E *
2790 * IIO_ICRBA_A IIO_ICRB0_A *
2791 * IIO_ICRBA_B IIO_ICRB0_B *
2792 * IIO_ICRBA_C IIO_ICRB0_C *
2793 * IIO_ICRBA_D IIO_ICRB0_D *
2794 * IIO_ICRBA_E IIO_ICRB0_E *
2795 * IIO_ICRBB_A IIO_ICRB0_A *
2796 * IIO_ICRBB_B IIO_ICRB0_B *
2797 * IIO_ICRBB_C IIO_ICRB0_C *
2798 * IIO_ICRBB_D IIO_ICRB0_D *
2799 * IIO_ICRBB_E IIO_ICRB0_E *
2800 * IIO_ICRBC_A IIO_ICRB0_A *
2801 * IIO_ICRBC_B IIO_ICRB0_B *
2802 * IIO_ICRBC_C IIO_ICRB0_C *
2803 * IIO_ICRBC_D IIO_ICRB0_D *
2804 * IIO_ICRBC_E IIO_ICRB0_E *
2805 * IIO_ICRBD_A IIO_ICRB0_A *
2806 * IIO_ICRBD_B IIO_ICRB0_B *
2807 * IIO_ICRBD_C IIO_ICRB0_C *
2808 * IIO_ICRBD_D IIO_ICRB0_D *
2809 * IIO_ICRBD_E IIO_ICRB0_E *
2810 * IIO_ICRBE_A IIO_ICRB0_A *
2811 * IIO_ICRBE_B IIO_ICRB0_B *
2812 * IIO_ICRBE_C IIO_ICRB0_C *
2813 * IIO_ICRBE_D IIO_ICRB0_D *
2814 * IIO_ICRBE_E IIO_ICRB0_E *
2815 * *
2816 ************************************************************************/
2817
2818/*
2819 * Slightly friendlier names for some common registers.
2820 */
2821#define IIO_WIDGET IIO_WID /* Widget identification */
2822#define IIO_WIDGET_STAT IIO_WSTAT /* Widget status register */
2823#define IIO_WIDGET_CTRL IIO_WCR /* Widget control register */
2824#define IIO_PROTECT IIO_ILAPR /* IO interface protection */
2825#define IIO_PROTECT_OVRRD IIO_ILAPO /* IO protect override */
2826#define IIO_OUTWIDGET_ACCESS IIO_IOWA /* Outbound widget access */
2827#define IIO_INWIDGET_ACCESS IIO_IIWA /* Inbound widget access */
2828#define IIO_INDEV_ERR_MASK IIO_IIDEM /* Inbound device error mask */
2829#define IIO_LLP_CSR IIO_ILCSR /* LLP control and status */
2830#define IIO_LLP_LOG IIO_ILLR /* LLP log */
2831#define IIO_XTALKCC_TOUT IIO_IXCC /* Xtalk credit count timeout */
2832#define IIO_XTALKTT_TOUT IIO_IXTT /* Xtalk tail timeout */
2833#define IIO_IO_ERR_CLR IIO_IECLR /* IO error clear */
2834#define IIO_IGFX_0 IIO_IGFX0
2835#define IIO_IGFX_1 IIO_IGFX1
2836#define IIO_IBCT_0 IIO_IBCT0
2837#define IIO_IBCT_1 IIO_IBCT1
2838#define IIO_IBLS_0 IIO_IBLS0
2839#define IIO_IBLS_1 IIO_IBLS1
2840#define IIO_IBSA_0 IIO_IBSA0
2841#define IIO_IBSA_1 IIO_IBSA1
2842#define IIO_IBDA_0 IIO_IBDA0
2843#define IIO_IBDA_1 IIO_IBDA1
2844#define IIO_IBNA_0 IIO_IBNA0
2845#define IIO_IBNA_1 IIO_IBNA1
2846#define IIO_IBIA_0 IIO_IBIA0
2847#define IIO_IBIA_1 IIO_IBIA1
2848#define IIO_IOPRB_0 IIO_IPRB0
2849
2850#define IIO_PRTE_A(_x) (IIO_IPRTE0_A + (8 * (_x)))
2851#define IIO_PRTE_B(_x) (IIO_IPRTE0_B + (8 * (_x)))
2852#define IIO_NUM_PRTES 8 /* Total number of PRB table entries */
2853#define IIO_WIDPRTE_A(x) IIO_PRTE_A(((x) - 8)) /* widget ID to its PRTE num */
2854#define IIO_WIDPRTE_B(x) IIO_PRTE_B(((x) - 8)) /* widget ID to its PRTE num */
2855
2856#define IIO_NUM_IPRBS 9
2857
2858#define IIO_LLP_CSR_IS_UP 0x00002000
2859#define IIO_LLP_CSR_LLP_STAT_MASK 0x00003000
2860#define IIO_LLP_CSR_LLP_STAT_SHFT 12
2861
2862#define IIO_LLP_CB_MAX 0xffff /* in ILLR CB_CNT, Max Check Bit errors */
2863#define IIO_LLP_SN_MAX 0xffff /* in ILLR SN_CNT, Max Sequence Number errors */
2864
2865/* key to IIO_PROTECT_OVRRD */
2866#define IIO_PROTECT_OVRRD_KEY 0x53474972756c6573ull /* "SGIrules" */
2867
2868/* BTE register names */
2869#define IIO_BTE_STAT_0 IIO_IBLS_0 /* Also BTE length/status 0 */
2870#define IIO_BTE_SRC_0 IIO_IBSA_0 /* Also BTE source address 0 */
2871#define IIO_BTE_DEST_0 IIO_IBDA_0 /* Also BTE dest. address 0 */
2872#define IIO_BTE_CTRL_0 IIO_IBCT_0 /* Also BTE control/terminate 0 */
2873#define IIO_BTE_NOTIFY_0 IIO_IBNA_0 /* Also BTE notification 0 */
2874#define IIO_BTE_INT_0 IIO_IBIA_0 /* Also BTE interrupt 0 */
2875#define IIO_BTE_OFF_0 0 /* Base offset from BTE 0 regs. */
2876#define IIO_BTE_OFF_1 (IIO_IBLS_1 - IIO_IBLS_0) /* Offset from base to BTE 1 */
2877
2878/* BTE register offsets from base */
2879#define BTEOFF_STAT 0
2880#define BTEOFF_SRC (IIO_BTE_SRC_0 - IIO_BTE_STAT_0)
2881#define BTEOFF_DEST (IIO_BTE_DEST_0 - IIO_BTE_STAT_0)
2882#define BTEOFF_CTRL (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0)
2883#define BTEOFF_NOTIFY (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0)
2884#define BTEOFF_INT (IIO_BTE_INT_0 - IIO_BTE_STAT_0)
2885
2886/* names used in shub diags */
2887#define IIO_BASE_BTE0 IIO_IBLS_0
2888#define IIO_BASE_BTE1 IIO_IBLS_1
2889
2890/*
2891 * Macro which takes the widget number, and returns the
2892 * IO PRB address of that widget.
2893 * value _x is expected to be a widget number in the range
2894 * 0, 8 - 0xF
2895 */
2896#define IIO_IOPRB(_x) (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \
2897 (_x) : \
2898 (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )
2899
2900/* GFX Flow Control Node/Widget Register */
2901#define IIO_IGFX_W_NUM_BITS 4 /* size of widget num field */
2902#define IIO_IGFX_W_NUM_MASK ((1<<IIO_IGFX_W_NUM_BITS)-1)
2903#define IIO_IGFX_W_NUM_SHIFT 0
2904#define IIO_IGFX_PI_NUM_BITS 1 /* size of PI num field */
2905#define IIO_IGFX_PI_NUM_MASK ((1<<IIO_IGFX_PI_NUM_BITS)-1)
2906#define IIO_IGFX_PI_NUM_SHIFT 4
2907#define IIO_IGFX_N_NUM_BITS 8 /* size of node num field */
2908#define IIO_IGFX_N_NUM_MASK ((1<<IIO_IGFX_N_NUM_BITS)-1)
2909#define IIO_IGFX_N_NUM_SHIFT 5
2910#define IIO_IGFX_P_NUM_BITS 1 /* size of processor num field */
2911#define IIO_IGFX_P_NUM_MASK ((1<<IIO_IGFX_P_NUM_BITS)-1)
2912#define IIO_IGFX_P_NUM_SHIFT 16
2913#define IIO_IGFX_INIT(widget, pi, node, cpu) (\
2914 (((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) | \
2915 (((pi) & IIO_IGFX_PI_NUM_MASK)<< IIO_IGFX_PI_NUM_SHIFT)| \
2916 (((node) & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) | \
2917 (((cpu) & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT))
2918
2919/* Scratch registers (all bits available) */
2920#define IIO_SCRATCH_REG0 IIO_ISCR0
2921#define IIO_SCRATCH_REG1 IIO_ISCR1
2922#define IIO_SCRATCH_MASK 0xffffffffffffffffUL
2923
2924#define IIO_SCRATCH_BIT0_0 0x0000000000000001UL
2925#define IIO_SCRATCH_BIT0_1 0x0000000000000002UL
2926#define IIO_SCRATCH_BIT0_2 0x0000000000000004UL
2927#define IIO_SCRATCH_BIT0_3 0x0000000000000008UL
2928#define IIO_SCRATCH_BIT0_4 0x0000000000000010UL
2929#define IIO_SCRATCH_BIT0_5 0x0000000000000020UL
2930#define IIO_SCRATCH_BIT0_6 0x0000000000000040UL
2931#define IIO_SCRATCH_BIT0_7 0x0000000000000080UL
2932#define IIO_SCRATCH_BIT0_8 0x0000000000000100UL
2933#define IIO_SCRATCH_BIT0_9 0x0000000000000200UL
2934#define IIO_SCRATCH_BIT0_A 0x0000000000000400UL
2935
2936#define IIO_SCRATCH_BIT1_0 0x0000000000000001UL
2937#define IIO_SCRATCH_BIT1_1 0x0000000000000002UL
2938/* IO Translation Table Entries */
2939#define IIO_NUM_ITTES 7 /* ITTEs numbered 0..6 */
2940 /* Hw manuals number them 1..7! */
2941/*
2942 * IIO_IMEM Register fields.
2943 */
2944#define IIO_IMEM_W0ESD 0x1UL /* Widget 0 shut down due to error */
2945#define IIO_IMEM_B0ESD (1UL << 4) /* BTE 0 shut down due to error */
2946#define IIO_IMEM_B1ESD (1UL << 8) /* BTE 1 Shut down due to error */
2947
2948/*
2949 * As a permanent workaround for a bug in the PI side of the shub, we've
2950 * redefined big window 7 as small window 0.
2951 XXX does this still apply for SN1??
2952 */
2953#define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1)
2954
2955/*
2956 * Use the top big window as a surrogate for the first small window
2957 */
2958#define SWIN0_BIGWIN HUB_NUM_BIG_WINDOW
2959
2960#define ILCSR_WARM_RESET 0x100
2961
2962/*
2963 * CRB manipulation macros
2964 * The CRB macros are slightly complicated, since there are up to
2965 * four registers associated with each CRB entry.
2966 */
2967#define IIO_NUM_CRBS 15 /* Number of CRBs */
2968#define IIO_NUM_PC_CRBS 4 /* Number of partial cache CRBs */
2969#define IIO_ICRB_OFFSET 8
2970#define IIO_ICRB_0 IIO_ICRB0_A
2971#define IIO_ICRB_ADDR_SHFT 2 /* Shift to get proper address */
2972/* XXX - This is now tuneable:
2973 #define IIO_FIRST_PC_ENTRY 12
2974 */
2975
2976#define IIO_ICRB_A(_x) ((u64)(IIO_ICRB_0 + (6 * IIO_ICRB_OFFSET * (_x))))
2977#define IIO_ICRB_B(_x) ((u64)((char *)IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET))
2978#define IIO_ICRB_C(_x) ((u64)((char *)IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET))
2979#define IIO_ICRB_D(_x) ((u64)((char *)IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET))
2980#define IIO_ICRB_E(_x) ((u64)((char *)IIO_ICRB_A(_x) + 4*IIO_ICRB_OFFSET))
2981
2982#define TNUM_TO_WIDGET_DEV(_tnum) (_tnum & 0x7)
2983
2984/*
2985 * values for "ecode" field
2986 */
2987#define IIO_ICRB_ECODE_DERR 0 /* Directory error due to IIO access */
2988#define IIO_ICRB_ECODE_PERR 1 /* Poison error on IO access */
2989#define IIO_ICRB_ECODE_WERR 2 /* Write error by IIO access
2990 * e.g. WINV to a Read only line. */
2991#define IIO_ICRB_ECODE_AERR 3 /* Access error caused by IIO access */
2992#define IIO_ICRB_ECODE_PWERR 4 /* Error on partial write */
2993#define IIO_ICRB_ECODE_PRERR 5 /* Error on partial read */
2994#define IIO_ICRB_ECODE_TOUT 6 /* CRB timeout before deallocating */
2995#define IIO_ICRB_ECODE_XTERR 7 /* Incoming xtalk pkt had error bit */
2996
2997/*
2998 * Values for field imsgtype
2999 */
3000#define IIO_ICRB_IMSGT_XTALK 0 /* Incoming Meessage from Xtalk */
3001#define IIO_ICRB_IMSGT_BTE 1 /* Incoming message from BTE */
3002#define IIO_ICRB_IMSGT_SN1NET 2 /* Incoming message from SN1 net */
3003#define IIO_ICRB_IMSGT_CRB 3 /* Incoming message from CRB ??? */
3004
3005/*
3006 * values for field initiator.
3007 */
3008#define IIO_ICRB_INIT_XTALK 0 /* Message originated in xtalk */
3009#define IIO_ICRB_INIT_BTE0 0x1 /* Message originated in BTE 0 */
3010#define IIO_ICRB_INIT_SN1NET 0x2 /* Message originated in SN1net */
3011#define IIO_ICRB_INIT_CRB 0x3 /* Message originated in CRB ? */
3012#define IIO_ICRB_INIT_BTE1 0x5 /* MEssage originated in BTE 1 */
3013
3014/*
3015 * Number of credits Hub widget has while sending req/response to
3016 * xbow.
3017 * Value of 3 is required by Xbow 1.1
3018 * We may be able to increase this to 4 with Xbow 1.2.
3019 */
3020#define HUBII_XBOW_CREDIT 3
3021#define HUBII_XBOW_REV2_CREDIT 4
3022
3023/*
3024 * Number of credits that xtalk devices should use when communicating
3025 * with a SHub (depth of SHub's queue).
3026 */
3027#define HUB_CREDIT 4
3028
3029/*
3030 * Some IIO_PRB fields
3031 */
3032#define IIO_PRB_MULTI_ERR (1LL << 63)
3033#define IIO_PRB_SPUR_RD (1LL << 51)
3034#define IIO_PRB_SPUR_WR (1LL << 50)
3035#define IIO_PRB_RD_TO (1LL << 49)
3036#define IIO_PRB_ERROR (1LL << 48)
3037
3038/*************************************************************************
3039
3040 Some of the IIO field masks and shifts are defined here.
3041 This is in order to maintain compatibility in SN0 and SN1 code
3042
3043**************************************************************************/
3044
3045/*
3046 * ICMR register fields
3047 * (Note: the IIO_ICMR_P_CNT and IIO_ICMR_PC_VLD from Hub are not
3048 * present in SHub)
3049 */
3050
3051#define IIO_ICMR_CRB_VLD_SHFT 20
3052#define IIO_ICMR_CRB_VLD_MASK (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT)
3053
3054#define IIO_ICMR_FC_CNT_SHFT 16
3055#define IIO_ICMR_FC_CNT_MASK (0xf << IIO_ICMR_FC_CNT_SHFT)
3056
3057#define IIO_ICMR_C_CNT_SHFT 4
3058#define IIO_ICMR_C_CNT_MASK (0xf << IIO_ICMR_C_CNT_SHFT)
3059
3060#define IIO_ICMR_PRECISE (1UL << 52)
3061#define IIO_ICMR_CLR_RPPD (1UL << 13)
3062#define IIO_ICMR_CLR_RQPD (1UL << 12)
3063
3064/*
3065 * IIO PIO Deallocation register field masks : (IIO_IPDR)
3066 XXX present but not needed in bedrock? See the manual.
3067 */
3068#define IIO_IPDR_PND (1 << 4)
3069
3070/*
3071 * IIO CRB deallocation register field masks: (IIO_ICDR)
3072 */
3073#define IIO_ICDR_PND (1 << 4)
3074
3075/*
3076 * IO BTE Length/Status (IIO_IBLS) register bit field definitions
3077 */
3078#define IBLS_BUSY (0x1UL << 20)
3079#define IBLS_ERROR_SHFT 16
3080#define IBLS_ERROR (0x1UL << IBLS_ERROR_SHFT)
3081#define IBLS_LENGTH_MASK 0xffff
3082
3083/*
3084 * IO BTE Control/Terminate register (IBCT) register bit field definitions
3085 */
3086#define IBCT_POISON (0x1UL << 8)
3087#define IBCT_NOTIFY (0x1UL << 4)
3088#define IBCT_ZFIL_MODE (0x1UL << 0)
3089
3090/*
3091 * IIO Incoming Error Packet Header (IIO_IIEPH1/IIO_IIEPH2)
3092 */
3093#define IIEPH1_VALID (1UL << 44)
3094#define IIEPH1_OVERRUN (1UL << 40)
3095#define IIEPH1_ERR_TYPE_SHFT 32
3096#define IIEPH1_ERR_TYPE_MASK 0xf
3097#define IIEPH1_SOURCE_SHFT 20
3098#define IIEPH1_SOURCE_MASK 11
3099#define IIEPH1_SUPPL_SHFT 8
3100#define IIEPH1_SUPPL_MASK 11
3101#define IIEPH1_CMD_SHFT 0
3102#define IIEPH1_CMD_MASK 7
3103
3104#define IIEPH2_TAIL (1UL << 40)
3105#define IIEPH2_ADDRESS_SHFT 0
3106#define IIEPH2_ADDRESS_MASK 38
3107
3108#define IIEPH1_ERR_SHORT_REQ 2
3109#define IIEPH1_ERR_SHORT_REPLY 3
3110#define IIEPH1_ERR_LONG_REQ 4
3111#define IIEPH1_ERR_LONG_REPLY 5
3112
3113/*
3114 * IO Error Clear register bit field definitions
3115 */
3116#define IECLR_PI1_FWD_INT (1UL << 31) /* clear PI1_FORWARD_INT in iidsr */
3117#define IECLR_PI0_FWD_INT (1UL << 30) /* clear PI0_FORWARD_INT in iidsr */
3118#define IECLR_SPUR_RD_HDR (1UL << 29) /* clear valid bit in ixss reg */
3119#define IECLR_BTE1 (1UL << 18) /* clear bte error 1 */
3120#define IECLR_BTE0 (1UL << 17) /* clear bte error 0 */
3121#define IECLR_CRAZY (1UL << 16) /* clear crazy bit in wstat reg */
3122#define IECLR_PRB_F (1UL << 15) /* clear err bit in PRB_F reg */
3123#define IECLR_PRB_E (1UL << 14) /* clear err bit in PRB_E reg */
3124#define IECLR_PRB_D (1UL << 13) /* clear err bit in PRB_D reg */
3125#define IECLR_PRB_C (1UL << 12) /* clear err bit in PRB_C reg */
3126#define IECLR_PRB_B (1UL << 11) /* clear err bit in PRB_B reg */
3127#define IECLR_PRB_A (1UL << 10) /* clear err bit in PRB_A reg */
3128#define IECLR_PRB_9 (1UL << 9) /* clear err bit in PRB_9 reg */
3129#define IECLR_PRB_8 (1UL << 8) /* clear err bit in PRB_8 reg */
3130#define IECLR_PRB_0 (1UL << 0) /* clear err bit in PRB_0 reg */
3131
3132/*
3133 * IIO CRB control register Fields: IIO_ICCR
3134 */
3135#define IIO_ICCR_PENDING 0x10000
3136#define IIO_ICCR_CMD_MASK 0xFF
3137#define IIO_ICCR_CMD_SHFT 7
3138#define IIO_ICCR_CMD_NOP 0x0 /* No Op */
3139#define IIO_ICCR_CMD_WAKE 0x100 /* Reactivate CRB entry and process */
3140#define IIO_ICCR_CMD_TIMEOUT 0x200 /* Make CRB timeout & mark invalid */
3141#define IIO_ICCR_CMD_EJECT 0x400 /* Contents of entry written to memory
3142 * via a WB
3143 */
3144#define IIO_ICCR_CMD_FLUSH 0x800
3145
3146/*
3147 *
3148 * CRB Register description.
3149 *
3150 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
3151 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
3152 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
3153 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
3154 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
3155 *
3156 * Many of the fields in CRB are status bits used by hardware
3157 * for implementation of the protocol. It's very dangerous to
3158 * mess around with the CRB registers.
3159 *
3160 * It's OK to read the CRB registers and try to make sense out of the
3161 * fields in CRB.
3162 *
3163 * Updating CRB requires all activities in Hub IIO to be quiesced.
3164 * otherwise, a write to CRB could corrupt other CRB entries.
3165 * CRBs are here only as a back door peek to shub IIO's status.
3166 * Quiescing implies no dmas no PIOs
3167 * either directly from the cpu or from sn0net.
3168 * this is not something that can be done easily. So, AVOID updating
3169 * CRBs.
3170 */
3171
3172/*
3173 * Easy access macros for CRBs, all 5 registers (A-E)
3174 */
3175typedef ii_icrb0_a_u_t icrba_t;
3176#define a_sidn ii_icrb0_a_fld_s.ia_sidn
3177#define a_tnum ii_icrb0_a_fld_s.ia_tnum
3178#define a_addr ii_icrb0_a_fld_s.ia_addr
3179#define a_valid ii_icrb0_a_fld_s.ia_vld
3180#define a_iow ii_icrb0_a_fld_s.ia_iow
3181#define a_regvalue ii_icrb0_a_regval
3182
3183typedef ii_icrb0_b_u_t icrbb_t;
3184#define b_use_old ii_icrb0_b_fld_s.ib_use_old
3185#define b_imsgtype ii_icrb0_b_fld_s.ib_imsgtype
3186#define b_imsg ii_icrb0_b_fld_s.ib_imsg
3187#define b_initiator ii_icrb0_b_fld_s.ib_init
3188#define b_exc ii_icrb0_b_fld_s.ib_exc
3189#define b_ackcnt ii_icrb0_b_fld_s.ib_ack_cnt
3190#define b_resp ii_icrb0_b_fld_s.ib_resp
3191#define b_ack ii_icrb0_b_fld_s.ib_ack
3192#define b_hold ii_icrb0_b_fld_s.ib_hold
3193#define b_wb ii_icrb0_b_fld_s.ib_wb
3194#define b_intvn ii_icrb0_b_fld_s.ib_intvn
3195#define b_stall_ib ii_icrb0_b_fld_s.ib_stall_ib
3196#define b_stall_int ii_icrb0_b_fld_s.ib_stall__intr
3197#define b_stall_bte_0 ii_icrb0_b_fld_s.ib_stall__bte_0
3198#define b_stall_bte_1 ii_icrb0_b_fld_s.ib_stall__bte_1
3199#define b_error ii_icrb0_b_fld_s.ib_error
3200#define b_ecode ii_icrb0_b_fld_s.ib_errcode
3201#define b_lnetuce ii_icrb0_b_fld_s.ib_ln_uce
3202#define b_mark ii_icrb0_b_fld_s.ib_mark
3203#define b_xerr ii_icrb0_b_fld_s.ib_xt_err
3204#define b_regvalue ii_icrb0_b_regval
3205
3206typedef ii_icrb0_c_u_t icrbc_t;
3207#define c_suppl ii_icrb0_c_fld_s.ic_suppl
3208#define c_barrop ii_icrb0_c_fld_s.ic_bo
3209#define c_doresp ii_icrb0_c_fld_s.ic_resprqd
3210#define c_gbr ii_icrb0_c_fld_s.ic_gbr
3211#define c_btenum ii_icrb0_c_fld_s.ic_bte_num
3212#define c_cohtrans ii_icrb0_c_fld_s.ic_ct
3213#define c_xtsize ii_icrb0_c_fld_s.ic_size
3214#define c_source ii_icrb0_c_fld_s.ic_source
3215#define c_regvalue ii_icrb0_c_regval
3216
3217typedef ii_icrb0_d_u_t icrbd_t;
3218#define d_sleep ii_icrb0_d_fld_s.id_sleep
3219#define d_pricnt ii_icrb0_d_fld_s.id_pr_cnt
3220#define d_pripsc ii_icrb0_d_fld_s.id_pr_psc
3221#define d_bteop ii_icrb0_d_fld_s.id_bte_op
3222#define d_bteaddr ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names */
3223#define d_benable ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names */
3224#define d_regvalue ii_icrb0_d_regval
3225
3226typedef ii_icrb0_e_u_t icrbe_t;
3227#define icrbe_ctxtvld ii_icrb0_e_fld_s.ie_cvld
3228#define icrbe_toutvld ii_icrb0_e_fld_s.ie_tvld
3229#define icrbe_context ii_icrb0_e_fld_s.ie_context
3230#define icrbe_timeout ii_icrb0_e_fld_s.ie_timeout
3231#define e_regvalue ii_icrb0_e_regval
3232
3233/* Number of widgets supported by shub */
3234#define HUB_NUM_WIDGET 9
3235#define HUB_WIDGET_ID_MIN 0x8
3236#define HUB_WIDGET_ID_MAX 0xf
3237
3238#define HUB_WIDGET_PART_NUM 0xc120
3239#define MAX_HUBS_PER_XBOW 2
3240
3241/* A few more #defines for backwards compatibility */
3242#define iprb_t ii_iprb0_u_t
3243#define iprb_regval ii_iprb0_regval
3244#define iprb_mult_err ii_iprb0_fld_s.i_mult_err
3245#define iprb_spur_rd ii_iprb0_fld_s.i_spur_rd
3246#define iprb_spur_wr ii_iprb0_fld_s.i_spur_wr
3247#define iprb_rd_to ii_iprb0_fld_s.i_rd_to
3248#define iprb_ovflow ii_iprb0_fld_s.i_of_cnt
3249#define iprb_error ii_iprb0_fld_s.i_error
3250#define iprb_ff ii_iprb0_fld_s.i_f
3251#define iprb_mode ii_iprb0_fld_s.i_m
3252#define iprb_bnakctr ii_iprb0_fld_s.i_nb
3253#define iprb_anakctr ii_iprb0_fld_s.i_na
3254#define iprb_xtalkctr ii_iprb0_fld_s.i_c
3255
3256#define LNK_STAT_WORKING 0x2 /* LLP is working */
3257
3258#define IIO_WSTAT_ECRAZY (1ULL << 32) /* Hub gone crazy */
3259#define IIO_WSTAT_TXRETRY (1ULL << 9) /* Hub Tx Retry timeout */
3260#define IIO_WSTAT_TXRETRY_MASK 0x7F /* should be 0xFF?? */
3261#define IIO_WSTAT_TXRETRY_SHFT 16
3262#define IIO_WSTAT_TXRETRY_CNT(w) (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \
3263 IIO_WSTAT_TXRETRY_MASK)
3264
3265/* Number of II perf. counters we can multiplex at once */
3266
3267#define IO_PERF_SETS 32
3268
3269/* Bit for the widget in inbound access register */
3270#define IIO_IIWA_WIDGET(_w) ((u64)(1ULL << _w))
3271/* Bit for the widget in outbound access register */
3272#define IIO_IOWA_WIDGET(_w) ((u64)(1ULL << _w))
3273
3274/* NOTE: The following define assumes that we are going to get
3275 * widget numbers from 8 thru F and the device numbers within
3276 * widget from 0 thru 7.
3277 */
3278#define IIO_IIDEM_WIDGETDEV_MASK(w, d) ((u64)(1ULL << (8 * ((w) - 8) + (d))))
3279
3280/* IO Interrupt Destination Register */
3281#define IIO_IIDSR_SENT_SHIFT 28
3282#define IIO_IIDSR_SENT_MASK 0x30000000
3283#define IIO_IIDSR_ENB_SHIFT 24
3284#define IIO_IIDSR_ENB_MASK 0x01000000
3285#define IIO_IIDSR_NODE_SHIFT 9
3286#define IIO_IIDSR_NODE_MASK 0x000ff700
3287#define IIO_IIDSR_PI_ID_SHIFT 8
3288#define IIO_IIDSR_PI_ID_MASK 0x00000100
3289#define IIO_IIDSR_LVL_SHIFT 0
3290#define IIO_IIDSR_LVL_MASK 0x000000ff
3291
3292/* Xtalk timeout threshhold register (IIO_IXTT) */
3293#define IXTT_RRSP_TO_SHFT 55 /* read response timeout */
3294#define IXTT_RRSP_TO_MASK (0x1FULL << IXTT_RRSP_TO_SHFT)
3295#define IXTT_RRSP_PS_SHFT 32 /* read responsed TO prescalar */
3296#define IXTT_RRSP_PS_MASK (0x7FFFFFULL << IXTT_RRSP_PS_SHFT)
3297#define IXTT_TAIL_TO_SHFT 0 /* tail timeout counter threshold */
3298#define IXTT_TAIL_TO_MASK (0x3FFFFFFULL << IXTT_TAIL_TO_SHFT)
3299
3300/*
3301 * The IO LLP control status register and widget control register
3302 */
3303
3304typedef union hubii_wcr_u {
3305 u64 wcr_reg_value;
3306 struct {
3307 u64 wcr_widget_id:4, /* LLP crossbar credit */
3308 wcr_tag_mode:1, /* Tag mode */
3309 wcr_rsvd1:8, /* Reserved */
3310 wcr_xbar_crd:3, /* LLP crossbar credit */
3311 wcr_f_bad_pkt:1, /* Force bad llp pkt enable */
3312 wcr_dir_con:1, /* widget direct connect */
3313 wcr_e_thresh:5, /* elasticity threshold */
3314 wcr_rsvd:41; /* unused */
3315 } wcr_fields_s;
3316} hubii_wcr_t;
3317
3318#define iwcr_dir_con wcr_fields_s.wcr_dir_con
3319
3320/* The structures below are defined to extract and modify the ii
3321performance registers */
3322
3323/* io_perf_sel allows the caller to specify what tests will be
3324 performed */
3325
3326typedef union io_perf_sel {
3327 u64 perf_sel_reg;
3328 struct {
3329 u64 perf_ippr0:4, perf_ippr1:4, perf_icct:8, perf_rsvd:48;
3330 } perf_sel_bits;
3331} io_perf_sel_t;
3332
3333/* io_perf_cnt is to extract the count from the shub registers. Due to
3334 hardware problems there is only one counter, not two. */
3335
3336typedef union io_perf_cnt {
3337 u64 perf_cnt;
3338 struct {
3339 u64 perf_cnt:20, perf_rsvd2:12, perf_rsvd1:32;
3340 } perf_cnt_bits;
3341
3342} io_perf_cnt_t;
3343
3344typedef union iprte_a {
3345 u64 entry;
3346 struct {
3347 u64 i_rsvd_1:3;
3348 u64 i_addr:38;
3349 u64 i_init:3;
3350 u64 i_source:8;
3351 u64 i_rsvd:2;
3352 u64 i_widget:4;
3353 u64 i_to_cnt:5;
3354 u64 i_vld:1;
3355 } iprte_fields;
3356} iprte_a_t;
3357
3358#endif /* _ASM_IA64_SN_SHUBIO_H */
diff --git a/include/asm-ia64/sn/simulator.h b/include/asm-ia64/sn/simulator.h
deleted file mode 100644
index c2611f6cfe3..00000000000
--- a/include/asm-ia64/sn/simulator.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
6 */
7
8#ifndef _ASM_IA64_SN_SIMULATOR_H
9#define _ASM_IA64_SN_SIMULATOR_H
10
11#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2) || defined(CONFIG_IA64_SGI_UV)
12#define SNMAGIC 0xaeeeeeee8badbeefL
13#define IS_MEDUSA() ({long sn; asm("mov %0=cpuid[%1]" : "=r"(sn) : "r"(2)); sn == SNMAGIC;})
14
15#define SIMULATOR_SLEEP() asm("nop.i 0x8beef")
16#define IS_RUNNING_ON_SIMULATOR() (sn_prom_type)
17#define IS_RUNNING_ON_FAKE_PROM() (sn_prom_type == 2)
18extern int sn_prom_type; /* 0=hardware, 1=medusa/realprom, 2=medusa/fakeprom */
19#else
20#define IS_MEDUSA() 0
21#define SIMULATOR_SLEEP()
22#define IS_RUNNING_ON_SIMULATOR() 0
23#endif
24
25#endif /* _ASM_IA64_SN_SIMULATOR_H */
diff --git a/include/asm-ia64/sn/sn2/sn_hwperf.h b/include/asm-ia64/sn/sn2/sn_hwperf.h
deleted file mode 100644
index e61ebac38cd..00000000000
--- a/include/asm-ia64/sn/sn2/sn_hwperf.h
+++ /dev/null
@@ -1,242 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004 Silicon Graphics, Inc. All rights reserved.
7 *
8 * Data types used by the SN_SAL_HWPERF_OP SAL call for monitoring
9 * SGI Altix node and router hardware
10 *
11 * Mark Goodwin <markgw@sgi.com> Mon Aug 30 12:23:46 EST 2004
12 */
13
14#ifndef SN_HWPERF_H
15#define SN_HWPERF_H
16
17/*
18 * object structure. SN_HWPERF_ENUM_OBJECTS and SN_HWPERF_GET_CPU_INFO
19 * return an array of these. Do not change this without also
20 * changing the corresponding SAL code.
21 */
22#define SN_HWPERF_MAXSTRING 128
23struct sn_hwperf_object_info {
24 u32 id;
25 union {
26 struct {
27 u64 this_part:1;
28 u64 is_shared:1;
29 } fields;
30 struct {
31 u64 flags;
32 u64 reserved;
33 } b;
34 } f;
35 char name[SN_HWPERF_MAXSTRING];
36 char location[SN_HWPERF_MAXSTRING];
37 u32 ports;
38};
39
40#define sn_hwp_this_part f.fields.this_part
41#define sn_hwp_is_shared f.fields.is_shared
42#define sn_hwp_flags f.b.flags
43
44/* macros for object classification */
45#define SN_HWPERF_IS_NODE(x) ((x) && strstr((x)->name, "SHub"))
46#define SN_HWPERF_IS_NODE_SHUB2(x) ((x) && strstr((x)->name, "SHub 2."))
47#define SN_HWPERF_IS_IONODE(x) ((x) && strstr((x)->name, "TIO"))
48#define SN_HWPERF_IS_NL3ROUTER(x) ((x) && strstr((x)->name, "NL3Router"))
49#define SN_HWPERF_IS_NL4ROUTER(x) ((x) && strstr((x)->name, "NL4Router"))
50#define SN_HWPERF_IS_OLDROUTER(x) ((x) && strstr((x)->name, "Router"))
51#define SN_HWPERF_IS_ROUTER(x) (SN_HWPERF_IS_NL3ROUTER(x) || \
52 SN_HWPERF_IS_NL4ROUTER(x) || \
53 SN_HWPERF_IS_OLDROUTER(x))
54#define SN_HWPERF_FOREIGN(x) ((x) && !(x)->sn_hwp_this_part && !(x)->sn_hwp_is_shared)
55#define SN_HWPERF_SAME_OBJTYPE(x,y) ((SN_HWPERF_IS_NODE(x) && SN_HWPERF_IS_NODE(y)) ||\
56 (SN_HWPERF_IS_IONODE(x) && SN_HWPERF_IS_IONODE(y)) ||\
57 (SN_HWPERF_IS_ROUTER(x) && SN_HWPERF_IS_ROUTER(y)))
58
59/* numa port structure, SN_HWPERF_ENUM_PORTS returns an array of these */
60struct sn_hwperf_port_info {
61 u32 port;
62 u32 conn_id;
63 u32 conn_port;
64};
65
66/* for HWPERF_{GET,SET}_MMRS */
67struct sn_hwperf_data {
68 u64 addr;
69 u64 data;
70};
71
72/* user ioctl() argument, see below */
73struct sn_hwperf_ioctl_args {
74 u64 arg; /* argument, usually an object id */
75 u64 sz; /* size of transfer */
76 void *ptr; /* pointer to source/target */
77 u32 v0; /* second return value */
78};
79
80/*
81 * For SN_HWPERF_{GET,SET}_MMRS and SN_HWPERF_OBJECT_DISTANCE,
82 * sn_hwperf_ioctl_args.arg can be used to specify a CPU on which
83 * to call SAL, and whether to use an interprocessor interrupt
84 * or task migration in order to do so. If the CPU specified is
85 * SN_HWPERF_ARG_ANY_CPU, then the current CPU will be used.
86 */
87#define SN_HWPERF_ARG_ANY_CPU 0x7fffffffUL
88#define SN_HWPERF_ARG_CPU_MASK 0x7fffffff00000000ULL
89#define SN_HWPERF_ARG_USE_IPI_MASK 0x8000000000000000ULL
90#define SN_HWPERF_ARG_OBJID_MASK 0x00000000ffffffffULL
91
92/*
93 * ioctl requests on the "sn_hwperf" misc device that call SAL.
94 */
95#define SN_HWPERF_OP_MEM_COPYIN 0x1000
96#define SN_HWPERF_OP_MEM_COPYOUT 0x2000
97#define SN_HWPERF_OP_MASK 0x0fff
98
99/*
100 * Determine mem requirement.
101 * arg don't care
102 * sz 8
103 * p pointer to u64 integer
104 */
105#define SN_HWPERF_GET_HEAPSIZE 1
106
107/*
108 * Install mem for SAL drvr
109 * arg don't care
110 * sz sizeof buffer pointed to by p
111 * p pointer to buffer for scratch area
112 */
113#define SN_HWPERF_INSTALL_HEAP 2
114
115/*
116 * Determine number of objects
117 * arg don't care
118 * sz 8
119 * p pointer to u64 integer
120 */
121#define SN_HWPERF_OBJECT_COUNT (10|SN_HWPERF_OP_MEM_COPYOUT)
122
123/*
124 * Determine object "distance", relative to a cpu. This operation can
125 * execute on a designated logical cpu number, using either an IPI or
126 * via task migration. If the cpu number is SN_HWPERF_ANY_CPU, then
127 * the current CPU is used. See the SN_HWPERF_ARG_* macros above.
128 *
129 * arg bitmap of IPI flag, cpu number and object id
130 * sz 8
131 * p pointer to u64 integer
132 */
133#define SN_HWPERF_OBJECT_DISTANCE (11|SN_HWPERF_OP_MEM_COPYOUT)
134
135/*
136 * Enumerate objects. Special case if sz == 8, returns the required
137 * buffer size.
138 * arg don't care
139 * sz sizeof buffer pointed to by p
140 * p pointer to array of struct sn_hwperf_object_info
141 */
142#define SN_HWPERF_ENUM_OBJECTS (12|SN_HWPERF_OP_MEM_COPYOUT)
143
144/*
145 * Enumerate NumaLink ports for an object. Special case if sz == 8,
146 * returns the required buffer size.
147 * arg object id
148 * sz sizeof buffer pointed to by p
149 * p pointer to array of struct sn_hwperf_port_info
150 */
151#define SN_HWPERF_ENUM_PORTS (13|SN_HWPERF_OP_MEM_COPYOUT)
152
153/*
154 * SET/GET memory mapped registers. These operations can execute
155 * on a designated logical cpu number, using either an IPI or via
156 * task migration. If the cpu number is SN_HWPERF_ANY_CPU, then
157 * the current CPU is used. See the SN_HWPERF_ARG_* macros above.
158 *
159 * arg bitmap of ipi flag, cpu number and object id
160 * sz sizeof buffer pointed to by p
161 * p pointer to array of struct sn_hwperf_data
162 */
163#define SN_HWPERF_SET_MMRS (14|SN_HWPERF_OP_MEM_COPYIN)
164#define SN_HWPERF_GET_MMRS (15|SN_HWPERF_OP_MEM_COPYOUT| \
165 SN_HWPERF_OP_MEM_COPYIN)
166/*
167 * Lock a shared object
168 * arg object id
169 * sz don't care
170 * p don't care
171 */
172#define SN_HWPERF_ACQUIRE 16
173
174/*
175 * Unlock a shared object
176 * arg object id
177 * sz don't care
178 * p don't care
179 */
180#define SN_HWPERF_RELEASE 17
181
182/*
183 * Break a lock on a shared object
184 * arg object id
185 * sz don't care
186 * p don't care
187 */
188#define SN_HWPERF_FORCE_RELEASE 18
189
190/*
191 * ioctl requests on "sn_hwperf" that do not call SAL
192 */
193
194/*
195 * get cpu info as an array of hwperf_object_info_t.
196 * id is logical CPU number, name is description, location
197 * is geoid (e.g. 001c04#1c). Special case if sz == 8,
198 * returns the required buffer size.
199 *
200 * arg don't care
201 * sz sizeof buffer pointed to by p
202 * p pointer to array of struct sn_hwperf_object_info
203 */
204#define SN_HWPERF_GET_CPU_INFO (100|SN_HWPERF_OP_MEM_COPYOUT)
205
206/*
207 * Given an object id, return it's node number (aka cnode).
208 * arg object id
209 * sz 8
210 * p pointer to u64 integer
211 */
212#define SN_HWPERF_GET_OBJ_NODE (101|SN_HWPERF_OP_MEM_COPYOUT)
213
214/*
215 * Given a node number (cnode), return it's nasid.
216 * arg ordinal node number (aka cnodeid)
217 * sz 8
218 * p pointer to u64 integer
219 */
220#define SN_HWPERF_GET_NODE_NASID (102|SN_HWPERF_OP_MEM_COPYOUT)
221
222/*
223 * Given a node id, determine the id of the nearest node with CPUs
224 * and the id of the nearest node that has memory. The argument
225 * node would normally be a "headless" node, e.g. an "IO node".
226 * Return 0 on success.
227 */
228extern int sn_hwperf_get_nearest_node(cnodeid_t node,
229 cnodeid_t *near_mem, cnodeid_t *near_cpu);
230
231/* return codes */
232#define SN_HWPERF_OP_OK 0
233#define SN_HWPERF_OP_NOMEM 1
234#define SN_HWPERF_OP_NO_PERM 2
235#define SN_HWPERF_OP_IO_ERROR 3
236#define SN_HWPERF_OP_BUSY 4
237#define SN_HWPERF_OP_RECONFIGURE 253
238#define SN_HWPERF_OP_INVAL 254
239
240int sn_topology_open(struct inode *inode, struct file *file);
241int sn_topology_release(struct inode *inode, struct file *file);
242#endif /* SN_HWPERF_H */
diff --git a/include/asm-ia64/sn/sn_cpuid.h b/include/asm-ia64/sn/sn_cpuid.h
deleted file mode 100644
index a676dd9ace3..00000000000
--- a/include/asm-ia64/sn/sn_cpuid.h
+++ /dev/null
@@ -1,132 +0,0 @@
1/*
2 *
3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
5 * for more details.
6 *
7 * Copyright (C) 2000-2005 Silicon Graphics, Inc. All rights reserved.
8 */
9
10
11#ifndef _ASM_IA64_SN_SN_CPUID_H
12#define _ASM_IA64_SN_SN_CPUID_H
13
14#include <linux/smp.h>
15#include <asm/sn/addrs.h>
16#include <asm/sn/pda.h>
17#include <asm/intrinsics.h>
18
19
20/*
21 * Functions for converting between cpuids, nodeids and NASIDs.
22 *
23 * These are for SGI platforms only.
24 *
25 */
26
27
28
29
30/*
31 * Definitions of terms (these definitions are for IA64 ONLY. Other architectures
32 * use cpuid/cpunum quite defferently):
33 *
34 * CPUID - a number in range of 0..NR_CPUS-1 that uniquely identifies
35 * the cpu. The value cpuid has no significance on IA64 other than
36 * the boot cpu is 0.
37 * smp_processor_id() returns the cpuid of the current cpu.
38 *
39 * CPU_PHYSICAL_ID (also known as HARD_PROCESSOR_ID)
40 * This is the same as 31:24 of the processor LID register
41 * hard_smp_processor_id()- cpu_physical_id of current processor
42 * cpu_physical_id(cpuid) - convert a <cpuid> to a <physical_cpuid>
43 * cpu_logical_id(phy_id) - convert a <physical_cpuid> to a <cpuid>
44 * * not real efficient - don't use in perf critical code
45 *
46 * SLICE - a number in the range of 0 - 3 (typically) that represents the
47 * cpu number on a brick.
48 *
49 * SUBNODE - (almost obsolete) the number of the FSB that a cpu is
50 * connected to. This is also the same as the PI number. Usually 0 or 1.
51 *
52 * NOTE!!!: the value of the bits in the cpu physical id (SAPICid or LID) of a cpu has no
53 * significance. The SAPIC id (LID) is a 16-bit cookie that has meaning only to the PROM.
54 *
55 *
56 * The macros convert between cpu physical ids & slice/nasid/cnodeid.
57 * These terms are described below:
58 *
59 *
60 * Brick
61 * ----- ----- ----- ----- CPU
62 * | 0 | | 1 | | 0 | | 1 | SLICE
63 * ----- ----- ----- -----
64 * | | | |
65 * | | | |
66 * 0 | | 2 0 | | 2 FSB SLOT
67 * ------- -------
68 * | |
69 * | |
70 * | |
71 * ------------ -------------
72 * | | | |
73 * | SHUB | | SHUB | NASID (0..MAX_NASIDS)
74 * | |----- | | CNODEID (0..num_compact_nodes-1)
75 * | | | |
76 * | | | |
77 * ------------ -------------
78 * | |
79 *
80 *
81 */
82
83#define get_node_number(addr) NASID_GET(addr)
84
85/*
86 * NOTE: on non-MP systems, only cpuid 0 exists
87 */
88
89extern short physical_node_map[]; /* indexed by nasid to get cnode */
90
91/*
92 * Macros for retrieving info about current cpu
93 */
94#define get_nasid() (sn_nodepda->phys_cpuid[smp_processor_id()].nasid)
95#define get_subnode() (sn_nodepda->phys_cpuid[smp_processor_id()].subnode)
96#define get_slice() (sn_nodepda->phys_cpuid[smp_processor_id()].slice)
97#define get_cnode() (sn_nodepda->phys_cpuid[smp_processor_id()].cnode)
98#define get_sapicid() ((ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff)
99
100/*
101 * Macros for retrieving info about an arbitrary cpu
102 * cpuid - logical cpu id
103 */
104#define cpuid_to_nasid(cpuid) (sn_nodepda->phys_cpuid[cpuid].nasid)
105#define cpuid_to_subnode(cpuid) (sn_nodepda->phys_cpuid[cpuid].subnode)
106#define cpuid_to_slice(cpuid) (sn_nodepda->phys_cpuid[cpuid].slice)
107
108
109/*
110 * Dont use the following in performance critical code. They require scans
111 * of potentially large tables.
112 */
113extern int nasid_slice_to_cpuid(int, int);
114
115/*
116 * cnodeid_to_nasid - convert a cnodeid to a NASID
117 */
118#define cnodeid_to_nasid(cnodeid) (sn_cnodeid_to_nasid[cnodeid])
119
120/*
121 * nasid_to_cnodeid - convert a NASID to a cnodeid
122 */
123#define nasid_to_cnodeid(nasid) (physical_node_map[nasid])
124
125/*
126 * partition_coherence_id - get the coherence ID of the current partition
127 */
128extern u8 sn_coherency_id;
129#define partition_coherence_id() (sn_coherency_id)
130
131#endif /* _ASM_IA64_SN_SN_CPUID_H */
132
diff --git a/include/asm-ia64/sn/sn_feature_sets.h b/include/asm-ia64/sn/sn_feature_sets.h
deleted file mode 100644
index 8e83ac117ac..00000000000
--- a/include/asm-ia64/sn/sn_feature_sets.h
+++ /dev/null
@@ -1,58 +0,0 @@
1#ifndef _ASM_IA64_SN_FEATURE_SETS_H
2#define _ASM_IA64_SN_FEATURE_SETS_H
3
4/*
5 * SN PROM Features
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 *
11 * Copyright (c) 2005-2006 Silicon Graphics, Inc. All rights reserved.
12 */
13
14
15/* --------------------- PROM Features -----------------------------*/
16extern int sn_prom_feature_available(int id);
17
18#define MAX_PROM_FEATURE_SETS 2
19
20/*
21 * The following defines features that may or may not be supported by the
22 * current PROM. The OS uses sn_prom_feature_available(feature) to test for
23 * the presence of a PROM feature. Down rev (old) PROMs will always test
24 * "false" for new features.
25 *
26 * Use:
27 * if (sn_prom_feature_available(PRF_XXX))
28 * ...
29 */
30
31#define PRF_PAL_CACHE_FLUSH_SAFE 0
32#define PRF_DEVICE_FLUSH_LIST 1
33#define PRF_HOTPLUG_SUPPORT 2
34#define PRF_CPU_DISABLE_SUPPORT 3
35
36/* --------------------- OS Features -------------------------------*/
37
38/*
39 * The following defines OS features that are optionally present in
40 * the operating system.
41 * During boot, PROM is notified of these features via a series of calls:
42 *
43 * ia64_sn_set_os_feature(feature1);
44 *
45 * Once enabled, a feature cannot be disabled.
46 *
47 * By default, features are disabled unless explicitly enabled.
48 *
49 * These defines must be kept in sync with the corresponding
50 * PROM definitions in feature_sets.h.
51 */
52#define OSF_MCA_SLV_TO_OS_INIT_SLV 0
53#define OSF_FEAT_LOG_SBES 1
54#define OSF_ACPI_ENABLE 2
55#define OSF_PCISEGMENT_ENABLE 3
56
57
58#endif /* _ASM_IA64_SN_FEATURE_SETS_H */
diff --git a/include/asm-ia64/sn/sn_sal.h b/include/asm-ia64/sn/sn_sal.h
deleted file mode 100644
index 676b31a08c6..00000000000
--- a/include/asm-ia64/sn/sn_sal.h
+++ /dev/null
@@ -1,1188 +0,0 @@
1#ifndef _ASM_IA64_SN_SN_SAL_H
2#define _ASM_IA64_SN_SN_SAL_H
3
4/*
5 * System Abstraction Layer definitions for IA64
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 *
11 * Copyright (c) 2000-2006 Silicon Graphics, Inc. All rights reserved.
12 */
13
14
15#include <asm/sal.h>
16#include <asm/sn/sn_cpuid.h>
17#include <asm/sn/arch.h>
18#include <asm/sn/geo.h>
19#include <asm/sn/nodepda.h>
20#include <asm/sn/shub_mmr.h>
21
22// SGI Specific Calls
23#define SN_SAL_POD_MODE 0x02000001
24#define SN_SAL_SYSTEM_RESET 0x02000002
25#define SN_SAL_PROBE 0x02000003
26#define SN_SAL_GET_MASTER_NASID 0x02000004
27#define SN_SAL_GET_KLCONFIG_ADDR 0x02000005
28#define SN_SAL_LOG_CE 0x02000006
29#define SN_SAL_REGISTER_CE 0x02000007
30#define SN_SAL_GET_PARTITION_ADDR 0x02000009
31#define SN_SAL_XP_ADDR_REGION 0x0200000f
32#define SN_SAL_NO_FAULT_ZONE_VIRTUAL 0x02000010
33#define SN_SAL_NO_FAULT_ZONE_PHYSICAL 0x02000011
34#define SN_SAL_PRINT_ERROR 0x02000012
35#define SN_SAL_REGISTER_PMI_HANDLER 0x02000014
36#define SN_SAL_SET_ERROR_HANDLING_FEATURES 0x0200001a // reentrant
37#define SN_SAL_GET_FIT_COMPT 0x0200001b // reentrant
38#define SN_SAL_GET_SAPIC_INFO 0x0200001d
39#define SN_SAL_GET_SN_INFO 0x0200001e
40#define SN_SAL_CONSOLE_PUTC 0x02000021
41#define SN_SAL_CONSOLE_GETC 0x02000022
42#define SN_SAL_CONSOLE_PUTS 0x02000023
43#define SN_SAL_CONSOLE_GETS 0x02000024
44#define SN_SAL_CONSOLE_GETS_TIMEOUT 0x02000025
45#define SN_SAL_CONSOLE_POLL 0x02000026
46#define SN_SAL_CONSOLE_INTR 0x02000027
47#define SN_SAL_CONSOLE_PUTB 0x02000028
48#define SN_SAL_CONSOLE_XMIT_CHARS 0x0200002a
49#define SN_SAL_CONSOLE_READC 0x0200002b
50#define SN_SAL_SYSCTL_OP 0x02000030
51#define SN_SAL_SYSCTL_MODID_GET 0x02000031
52#define SN_SAL_SYSCTL_GET 0x02000032
53#define SN_SAL_SYSCTL_IOBRICK_MODULE_GET 0x02000033
54#define SN_SAL_SYSCTL_IO_PORTSPEED_GET 0x02000035
55#define SN_SAL_SYSCTL_SLAB_GET 0x02000036
56#define SN_SAL_BUS_CONFIG 0x02000037
57#define SN_SAL_SYS_SERIAL_GET 0x02000038
58#define SN_SAL_PARTITION_SERIAL_GET 0x02000039
59#define SN_SAL_SYSCTL_PARTITION_GET 0x0200003a
60#define SN_SAL_SYSTEM_POWER_DOWN 0x0200003b
61#define SN_SAL_GET_MASTER_BASEIO_NASID 0x0200003c
62#define SN_SAL_COHERENCE 0x0200003d
63#define SN_SAL_MEMPROTECT 0x0200003e
64#define SN_SAL_SYSCTL_FRU_CAPTURE 0x0200003f
65
66#define SN_SAL_SYSCTL_IOBRICK_PCI_OP 0x02000042 // reentrant
67#define SN_SAL_IROUTER_OP 0x02000043
68#define SN_SAL_SYSCTL_EVENT 0x02000044
69#define SN_SAL_IOIF_INTERRUPT 0x0200004a
70#define SN_SAL_HWPERF_OP 0x02000050 // lock
71#define SN_SAL_IOIF_ERROR_INTERRUPT 0x02000051
72#define SN_SAL_IOIF_PCI_SAFE 0x02000052
73#define SN_SAL_IOIF_SLOT_ENABLE 0x02000053
74#define SN_SAL_IOIF_SLOT_DISABLE 0x02000054
75#define SN_SAL_IOIF_GET_HUBDEV_INFO 0x02000055
76#define SN_SAL_IOIF_GET_PCIBUS_INFO 0x02000056
77#define SN_SAL_IOIF_GET_PCIDEV_INFO 0x02000057
78#define SN_SAL_IOIF_GET_WIDGET_DMAFLUSH_LIST 0x02000058 // deprecated
79#define SN_SAL_IOIF_GET_DEVICE_DMAFLUSH_LIST 0x0200005a
80
81#define SN_SAL_IOIF_INIT 0x0200005f
82#define SN_SAL_HUB_ERROR_INTERRUPT 0x02000060
83#define SN_SAL_BTE_RECOVER 0x02000061
84#define SN_SAL_RESERVED_DO_NOT_USE 0x02000062
85#define SN_SAL_IOIF_GET_PCI_TOPOLOGY 0x02000064
86
87#define SN_SAL_GET_PROM_FEATURE_SET 0x02000065
88#define SN_SAL_SET_OS_FEATURE_SET 0x02000066
89#define SN_SAL_INJECT_ERROR 0x02000067
90#define SN_SAL_SET_CPU_NUMBER 0x02000068
91
92#define SN_SAL_KERNEL_LAUNCH_EVENT 0x02000069
93
94/*
95 * Service-specific constants
96 */
97
98/* Console interrupt manipulation */
99 /* action codes */
100#define SAL_CONSOLE_INTR_OFF 0 /* turn the interrupt off */
101#define SAL_CONSOLE_INTR_ON 1 /* turn the interrupt on */
102#define SAL_CONSOLE_INTR_STATUS 2 /* retrieve the interrupt status */
103 /* interrupt specification & status return codes */
104#define SAL_CONSOLE_INTR_XMIT 1 /* output interrupt */
105#define SAL_CONSOLE_INTR_RECV 2 /* input interrupt */
106
107/* interrupt handling */
108#define SAL_INTR_ALLOC 1
109#define SAL_INTR_FREE 2
110#define SAL_INTR_REDIRECT 3
111
112/*
113 * operations available on the generic SN_SAL_SYSCTL_OP
114 * runtime service
115 */
116#define SAL_SYSCTL_OP_IOBOARD 0x0001 /* retrieve board type */
117#define SAL_SYSCTL_OP_TIO_JLCK_RST 0x0002 /* issue TIO clock reset */
118
119/*
120 * IRouter (i.e. generalized system controller) operations
121 */
122#define SAL_IROUTER_OPEN 0 /* open a subchannel */
123#define SAL_IROUTER_CLOSE 1 /* close a subchannel */
124#define SAL_IROUTER_SEND 2 /* send part of an IRouter packet */
125#define SAL_IROUTER_RECV 3 /* receive part of an IRouter packet */
126#define SAL_IROUTER_INTR_STATUS 4 /* check the interrupt status for
127 * an open subchannel
128 */
129#define SAL_IROUTER_INTR_ON 5 /* enable an interrupt */
130#define SAL_IROUTER_INTR_OFF 6 /* disable an interrupt */
131#define SAL_IROUTER_INIT 7 /* initialize IRouter driver */
132
133/* IRouter interrupt mask bits */
134#define SAL_IROUTER_INTR_XMIT SAL_CONSOLE_INTR_XMIT
135#define SAL_IROUTER_INTR_RECV SAL_CONSOLE_INTR_RECV
136
137/*
138 * Error Handling Features
139 */
140#define SAL_ERR_FEAT_MCA_SLV_TO_OS_INIT_SLV 0x1 // obsolete
141#define SAL_ERR_FEAT_LOG_SBES 0x2 // obsolete
142#define SAL_ERR_FEAT_MFR_OVERRIDE 0x4
143#define SAL_ERR_FEAT_SBE_THRESHOLD 0xffff0000
144
145/*
146 * SAL Error Codes
147 */
148#define SALRET_MORE_PASSES 1
149#define SALRET_OK 0
150#define SALRET_NOT_IMPLEMENTED (-1)
151#define SALRET_INVALID_ARG (-2)
152#define SALRET_ERROR (-3)
153
154#define SN_SAL_FAKE_PROM 0x02009999
155
156/**
157 * sn_sal_revision - get the SGI SAL revision number
158 *
159 * The SGI PROM stores its version in the sal_[ab]_rev_(major|minor).
160 * This routine simply extracts the major and minor values and
161 * presents them in a u32 format.
162 *
163 * For example, version 4.05 would be represented at 0x0405.
164 */
165static inline u32
166sn_sal_rev(void)
167{
168 struct ia64_sal_systab *systab = __va(efi.sal_systab);
169
170 return (u32)(systab->sal_b_rev_major << 8 | systab->sal_b_rev_minor);
171}
172
173/*
174 * Returns the master console nasid, if the call fails, return an illegal
175 * value.
176 */
177static inline u64
178ia64_sn_get_console_nasid(void)
179{
180 struct ia64_sal_retval ret_stuff;
181
182 ret_stuff.status = 0;
183 ret_stuff.v0 = 0;
184 ret_stuff.v1 = 0;
185 ret_stuff.v2 = 0;
186 SAL_CALL(ret_stuff, SN_SAL_GET_MASTER_NASID, 0, 0, 0, 0, 0, 0, 0);
187
188 if (ret_stuff.status < 0)
189 return ret_stuff.status;
190
191 /* Master console nasid is in 'v0' */
192 return ret_stuff.v0;
193}
194
195/*
196 * Returns the master baseio nasid, if the call fails, return an illegal
197 * value.
198 */
199static inline u64
200ia64_sn_get_master_baseio_nasid(void)
201{
202 struct ia64_sal_retval ret_stuff;
203
204 ret_stuff.status = 0;
205 ret_stuff.v0 = 0;
206 ret_stuff.v1 = 0;
207 ret_stuff.v2 = 0;
208 SAL_CALL(ret_stuff, SN_SAL_GET_MASTER_BASEIO_NASID, 0, 0, 0, 0, 0, 0, 0);
209
210 if (ret_stuff.status < 0)
211 return ret_stuff.status;
212
213 /* Master baseio nasid is in 'v0' */
214 return ret_stuff.v0;
215}
216
217static inline void *
218ia64_sn_get_klconfig_addr(nasid_t nasid)
219{
220 struct ia64_sal_retval ret_stuff;
221
222 ret_stuff.status = 0;
223 ret_stuff.v0 = 0;
224 ret_stuff.v1 = 0;
225 ret_stuff.v2 = 0;
226 SAL_CALL(ret_stuff, SN_SAL_GET_KLCONFIG_ADDR, (u64)nasid, 0, 0, 0, 0, 0, 0);
227 return ret_stuff.v0 ? __va(ret_stuff.v0) : NULL;
228}
229
230/*
231 * Returns the next console character.
232 */
233static inline u64
234ia64_sn_console_getc(int *ch)
235{
236 struct ia64_sal_retval ret_stuff;
237
238 ret_stuff.status = 0;
239 ret_stuff.v0 = 0;
240 ret_stuff.v1 = 0;
241 ret_stuff.v2 = 0;
242 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_GETC, 0, 0, 0, 0, 0, 0, 0);
243
244 /* character is in 'v0' */
245 *ch = (int)ret_stuff.v0;
246
247 return ret_stuff.status;
248}
249
250/*
251 * Read a character from the SAL console device, after a previous interrupt
252 * or poll operation has given us to know that a character is available
253 * to be read.
254 */
255static inline u64
256ia64_sn_console_readc(void)
257{
258 struct ia64_sal_retval ret_stuff;
259
260 ret_stuff.status = 0;
261 ret_stuff.v0 = 0;
262 ret_stuff.v1 = 0;
263 ret_stuff.v2 = 0;
264 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_READC, 0, 0, 0, 0, 0, 0, 0);
265
266 /* character is in 'v0' */
267 return ret_stuff.v0;
268}
269
270/*
271 * Sends the given character to the console.
272 */
273static inline u64
274ia64_sn_console_putc(char ch)
275{
276 struct ia64_sal_retval ret_stuff;
277
278 ret_stuff.status = 0;
279 ret_stuff.v0 = 0;
280 ret_stuff.v1 = 0;
281 ret_stuff.v2 = 0;
282 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTC, (u64)ch, 0, 0, 0, 0, 0, 0);
283
284 return ret_stuff.status;
285}
286
287/*
288 * Sends the given buffer to the console.
289 */
290static inline u64
291ia64_sn_console_putb(const char *buf, int len)
292{
293 struct ia64_sal_retval ret_stuff;
294
295 ret_stuff.status = 0;
296 ret_stuff.v0 = 0;
297 ret_stuff.v1 = 0;
298 ret_stuff.v2 = 0;
299 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTB, (u64)buf, (u64)len, 0, 0, 0, 0, 0);
300
301 if ( ret_stuff.status == 0 ) {
302 return ret_stuff.v0;
303 }
304 return (u64)0;
305}
306
307/*
308 * Print a platform error record
309 */
310static inline u64
311ia64_sn_plat_specific_err_print(int (*hook)(const char*, ...), char *rec)
312{
313 struct ia64_sal_retval ret_stuff;
314
315 ret_stuff.status = 0;
316 ret_stuff.v0 = 0;
317 ret_stuff.v1 = 0;
318 ret_stuff.v2 = 0;
319 SAL_CALL_REENTRANT(ret_stuff, SN_SAL_PRINT_ERROR, (u64)hook, (u64)rec, 0, 0, 0, 0, 0);
320
321 return ret_stuff.status;
322}
323
324/*
325 * Check for Platform errors
326 */
327static inline u64
328ia64_sn_plat_cpei_handler(void)
329{
330 struct ia64_sal_retval ret_stuff;
331
332 ret_stuff.status = 0;
333 ret_stuff.v0 = 0;
334 ret_stuff.v1 = 0;
335 ret_stuff.v2 = 0;
336 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_LOG_CE, 0, 0, 0, 0, 0, 0, 0);
337
338 return ret_stuff.status;
339}
340
341/*
342 * Set Error Handling Features (Obsolete)
343 */
344static inline u64
345ia64_sn_plat_set_error_handling_features(void)
346{
347 struct ia64_sal_retval ret_stuff;
348
349 ret_stuff.status = 0;
350 ret_stuff.v0 = 0;
351 ret_stuff.v1 = 0;
352 ret_stuff.v2 = 0;
353 SAL_CALL_REENTRANT(ret_stuff, SN_SAL_SET_ERROR_HANDLING_FEATURES,
354 SAL_ERR_FEAT_LOG_SBES,
355 0, 0, 0, 0, 0, 0);
356
357 return ret_stuff.status;
358}
359
360/*
361 * Checks for console input.
362 */
363static inline u64
364ia64_sn_console_check(int *result)
365{
366 struct ia64_sal_retval ret_stuff;
367
368 ret_stuff.status = 0;
369 ret_stuff.v0 = 0;
370 ret_stuff.v1 = 0;
371 ret_stuff.v2 = 0;
372 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_POLL, 0, 0, 0, 0, 0, 0, 0);
373
374 /* result is in 'v0' */
375 *result = (int)ret_stuff.v0;
376
377 return ret_stuff.status;
378}
379
380/*
381 * Checks console interrupt status
382 */
383static inline u64
384ia64_sn_console_intr_status(void)
385{
386 struct ia64_sal_retval ret_stuff;
387
388 ret_stuff.status = 0;
389 ret_stuff.v0 = 0;
390 ret_stuff.v1 = 0;
391 ret_stuff.v2 = 0;
392 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_INTR,
393 0, SAL_CONSOLE_INTR_STATUS,
394 0, 0, 0, 0, 0);
395
396 if (ret_stuff.status == 0) {
397 return ret_stuff.v0;
398 }
399
400 return 0;
401}
402
403/*
404 * Enable an interrupt on the SAL console device.
405 */
406static inline void
407ia64_sn_console_intr_enable(u64 intr)
408{
409 struct ia64_sal_retval ret_stuff;
410
411 ret_stuff.status = 0;
412 ret_stuff.v0 = 0;
413 ret_stuff.v1 = 0;
414 ret_stuff.v2 = 0;
415 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_INTR,
416 intr, SAL_CONSOLE_INTR_ON,
417 0, 0, 0, 0, 0);
418}
419
420/*
421 * Disable an interrupt on the SAL console device.
422 */
423static inline void
424ia64_sn_console_intr_disable(u64 intr)
425{
426 struct ia64_sal_retval ret_stuff;
427
428 ret_stuff.status = 0;
429 ret_stuff.v0 = 0;
430 ret_stuff.v1 = 0;
431 ret_stuff.v2 = 0;
432 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_INTR,
433 intr, SAL_CONSOLE_INTR_OFF,
434 0, 0, 0, 0, 0);
435}
436
437/*
438 * Sends a character buffer to the console asynchronously.
439 */
440static inline u64
441ia64_sn_console_xmit_chars(char *buf, int len)
442{
443 struct ia64_sal_retval ret_stuff;
444
445 ret_stuff.status = 0;
446 ret_stuff.v0 = 0;
447 ret_stuff.v1 = 0;
448 ret_stuff.v2 = 0;
449 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_XMIT_CHARS,
450 (u64)buf, (u64)len,
451 0, 0, 0, 0, 0);
452
453 if (ret_stuff.status == 0) {
454 return ret_stuff.v0;
455 }
456
457 return 0;
458}
459
460/*
461 * Returns the iobrick module Id
462 */
463static inline u64
464ia64_sn_sysctl_iobrick_module_get(nasid_t nasid, int *result)
465{
466 struct ia64_sal_retval ret_stuff;
467
468 ret_stuff.status = 0;
469 ret_stuff.v0 = 0;
470 ret_stuff.v1 = 0;
471 ret_stuff.v2 = 0;
472 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_SYSCTL_IOBRICK_MODULE_GET, nasid, 0, 0, 0, 0, 0, 0);
473
474 /* result is in 'v0' */
475 *result = (int)ret_stuff.v0;
476
477 return ret_stuff.status;
478}
479
480/**
481 * ia64_sn_pod_mode - call the SN_SAL_POD_MODE function
482 *
483 * SN_SAL_POD_MODE actually takes an argument, but it's always
484 * 0 when we call it from the kernel, so we don't have to expose
485 * it to the caller.
486 */
487static inline u64
488ia64_sn_pod_mode(void)
489{
490 struct ia64_sal_retval isrv;
491 SAL_CALL_REENTRANT(isrv, SN_SAL_POD_MODE, 0, 0, 0, 0, 0, 0, 0);
492 if (isrv.status)
493 return 0;
494 return isrv.v0;
495}
496
497/**
498 * ia64_sn_probe_mem - read from memory safely
499 * @addr: address to probe
500 * @size: number bytes to read (1,2,4,8)
501 * @data_ptr: address to store value read by probe (-1 returned if probe fails)
502 *
503 * Call into the SAL to do a memory read. If the read generates a machine
504 * check, this routine will recover gracefully and return -1 to the caller.
505 * @addr is usually a kernel virtual address in uncached space (i.e. the
506 * address starts with 0xc), but if called in physical mode, @addr should
507 * be a physical address.
508 *
509 * Return values:
510 * 0 - probe successful
511 * 1 - probe failed (generated MCA)
512 * 2 - Bad arg
513 * <0 - PAL error
514 */
515static inline u64
516ia64_sn_probe_mem(long addr, long size, void *data_ptr)
517{
518 struct ia64_sal_retval isrv;
519
520 SAL_CALL(isrv, SN_SAL_PROBE, addr, size, 0, 0, 0, 0, 0);
521
522 if (data_ptr) {
523 switch (size) {
524 case 1:
525 *((u8*)data_ptr) = (u8)isrv.v0;
526 break;
527 case 2:
528 *((u16*)data_ptr) = (u16)isrv.v0;
529 break;
530 case 4:
531 *((u32*)data_ptr) = (u32)isrv.v0;
532 break;
533 case 8:
534 *((u64*)data_ptr) = (u64)isrv.v0;
535 break;
536 default:
537 isrv.status = 2;
538 }
539 }
540 return isrv.status;
541}
542
543/*
544 * Retrieve the system serial number as an ASCII string.
545 */
546static inline u64
547ia64_sn_sys_serial_get(char *buf)
548{
549 struct ia64_sal_retval ret_stuff;
550 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_SYS_SERIAL_GET, buf, 0, 0, 0, 0, 0, 0);
551 return ret_stuff.status;
552}
553
554extern char sn_system_serial_number_string[];
555extern u64 sn_partition_serial_number;
556
557static inline char *
558sn_system_serial_number(void) {
559 if (sn_system_serial_number_string[0]) {
560 return(sn_system_serial_number_string);
561 } else {
562 ia64_sn_sys_serial_get(sn_system_serial_number_string);
563 return(sn_system_serial_number_string);
564 }
565}
566
567
568/*
569 * Returns a unique id number for this system and partition (suitable for
570 * use with license managers), based in part on the system serial number.
571 */
572static inline u64
573ia64_sn_partition_serial_get(void)
574{
575 struct ia64_sal_retval ret_stuff;
576 ia64_sal_oemcall_reentrant(&ret_stuff, SN_SAL_PARTITION_SERIAL_GET, 0,
577 0, 0, 0, 0, 0, 0);
578 if (ret_stuff.status != 0)
579 return 0;
580 return ret_stuff.v0;
581}
582
583static inline u64
584sn_partition_serial_number_val(void) {
585 if (unlikely(sn_partition_serial_number == 0)) {
586 sn_partition_serial_number = ia64_sn_partition_serial_get();
587 }
588 return sn_partition_serial_number;
589}
590
591/*
592 * Returns the partition id of the nasid passed in as an argument,
593 * or INVALID_PARTID if the partition id cannot be retrieved.
594 */
595static inline partid_t
596ia64_sn_sysctl_partition_get(nasid_t nasid)
597{
598 struct ia64_sal_retval ret_stuff;
599 SAL_CALL(ret_stuff, SN_SAL_SYSCTL_PARTITION_GET, nasid,
600 0, 0, 0, 0, 0, 0);
601 if (ret_stuff.status != 0)
602 return -1;
603 return ((partid_t)ret_stuff.v0);
604}
605
606/*
607 * Returns the physical address of the partition's reserved page through
608 * an iterative number of calls.
609 *
610 * On first call, 'cookie' and 'len' should be set to 0, and 'addr'
611 * set to the nasid of the partition whose reserved page's address is
612 * being sought.
613 * On subsequent calls, pass the values, that were passed back on the
614 * previous call.
615 *
616 * While the return status equals SALRET_MORE_PASSES, keep calling
617 * this function after first copying 'len' bytes starting at 'addr'
618 * into 'buf'. Once the return status equals SALRET_OK, 'addr' will
619 * be the physical address of the partition's reserved page. If the
620 * return status equals neither of these, an error as occurred.
621 */
622static inline s64
623sn_partition_reserved_page_pa(u64 buf, u64 *cookie, u64 *addr, u64 *len)
624{
625 struct ia64_sal_retval rv;
626 ia64_sal_oemcall_reentrant(&rv, SN_SAL_GET_PARTITION_ADDR, *cookie,
627 *addr, buf, *len, 0, 0, 0);
628 *cookie = rv.v0;
629 *addr = rv.v1;
630 *len = rv.v2;
631 return rv.status;
632}
633
634/*
635 * Register or unregister a physical address range being referenced across
636 * a partition boundary for which certain SAL errors should be scanned for,
637 * cleaned up and ignored. This is of value for kernel partitioning code only.
638 * Values for the operation argument:
639 * 1 = register this address range with SAL
640 * 0 = unregister this address range with SAL
641 *
642 * SAL maintains a reference count on an address range in case it is registered
643 * multiple times.
644 *
645 * On success, returns the reference count of the address range after the SAL
646 * call has performed the current registration/unregistration. Returns a
647 * negative value if an error occurred.
648 */
649static inline int
650sn_register_xp_addr_region(u64 paddr, u64 len, int operation)
651{
652 struct ia64_sal_retval ret_stuff;
653 ia64_sal_oemcall(&ret_stuff, SN_SAL_XP_ADDR_REGION, paddr, len,
654 (u64)operation, 0, 0, 0, 0);
655 return ret_stuff.status;
656}
657
658/*
659 * Register or unregister an instruction range for which SAL errors should
660 * be ignored. If an error occurs while in the registered range, SAL jumps
661 * to return_addr after ignoring the error. Values for the operation argument:
662 * 1 = register this instruction range with SAL
663 * 0 = unregister this instruction range with SAL
664 *
665 * Returns 0 on success, or a negative value if an error occurred.
666 */
667static inline int
668sn_register_nofault_code(u64 start_addr, u64 end_addr, u64 return_addr,
669 int virtual, int operation)
670{
671 struct ia64_sal_retval ret_stuff;
672 u64 call;
673 if (virtual) {
674 call = SN_SAL_NO_FAULT_ZONE_VIRTUAL;
675 } else {
676 call = SN_SAL_NO_FAULT_ZONE_PHYSICAL;
677 }
678 ia64_sal_oemcall(&ret_stuff, call, start_addr, end_addr, return_addr,
679 (u64)1, 0, 0, 0);
680 return ret_stuff.status;
681}
682
683/*
684 * Register or unregister a function to handle a PMI received by a CPU.
685 * Before calling the registered handler, SAL sets r1 to the value that
686 * was passed in as the global_pointer.
687 *
688 * If the handler pointer is NULL, then the currently registered handler
689 * will be unregistered.
690 *
691 * Returns 0 on success, or a negative value if an error occurred.
692 */
693static inline int
694sn_register_pmi_handler(u64 handler, u64 global_pointer)
695{
696 struct ia64_sal_retval ret_stuff;
697 ia64_sal_oemcall(&ret_stuff, SN_SAL_REGISTER_PMI_HANDLER, handler,
698 global_pointer, 0, 0, 0, 0, 0);
699 return ret_stuff.status;
700}
701
702/*
703 * Change or query the coherence domain for this partition. Each cpu-based
704 * nasid is represented by a bit in an array of 64-bit words:
705 * 0 = not in this partition's coherency domain
706 * 1 = in this partition's coherency domain
707 *
708 * It is not possible for the local system's nasids to be removed from
709 * the coherency domain. Purpose of the domain arguments:
710 * new_domain = set the coherence domain to the given nasids
711 * old_domain = return the current coherence domain
712 *
713 * Returns 0 on success, or a negative value if an error occurred.
714 */
715static inline int
716sn_change_coherence(u64 *new_domain, u64 *old_domain)
717{
718 struct ia64_sal_retval ret_stuff;
719 ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_COHERENCE, (u64)new_domain,
720 (u64)old_domain, 0, 0, 0, 0, 0);
721 return ret_stuff.status;
722}
723
724/*
725 * Change memory access protections for a physical address range.
726 * nasid_array is not used on Altix, but may be in future architectures.
727 * Available memory protection access classes are defined after the function.
728 */
729static inline int
730sn_change_memprotect(u64 paddr, u64 len, u64 perms, u64 *nasid_array)
731{
732 struct ia64_sal_retval ret_stuff;
733
734 ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_MEMPROTECT, paddr, len,
735 (u64)nasid_array, perms, 0, 0, 0);
736 return ret_stuff.status;
737}
738#define SN_MEMPROT_ACCESS_CLASS_0 0x14a080
739#define SN_MEMPROT_ACCESS_CLASS_1 0x2520c2
740#define SN_MEMPROT_ACCESS_CLASS_2 0x14a1ca
741#define SN_MEMPROT_ACCESS_CLASS_3 0x14a290
742#define SN_MEMPROT_ACCESS_CLASS_6 0x084080
743#define SN_MEMPROT_ACCESS_CLASS_7 0x021080
744
745/*
746 * Turns off system power.
747 */
748static inline void
749ia64_sn_power_down(void)
750{
751 struct ia64_sal_retval ret_stuff;
752 SAL_CALL(ret_stuff, SN_SAL_SYSTEM_POWER_DOWN, 0, 0, 0, 0, 0, 0, 0);
753 while(1)
754 cpu_relax();
755 /* never returns */
756}
757
758/**
759 * ia64_sn_fru_capture - tell the system controller to capture hw state
760 *
761 * This routine will call the SAL which will tell the system controller(s)
762 * to capture hw mmr information from each SHub in the system.
763 */
764static inline u64
765ia64_sn_fru_capture(void)
766{
767 struct ia64_sal_retval isrv;
768 SAL_CALL(isrv, SN_SAL_SYSCTL_FRU_CAPTURE, 0, 0, 0, 0, 0, 0, 0);
769 if (isrv.status)
770 return 0;
771 return isrv.v0;
772}
773
774/*
775 * Performs an operation on a PCI bus or slot -- power up, power down
776 * or reset.
777 */
778static inline u64
779ia64_sn_sysctl_iobrick_pci_op(nasid_t n, u64 connection_type,
780 u64 bus, char slot,
781 u64 action)
782{
783 struct ia64_sal_retval rv = {0, 0, 0, 0};
784
785 SAL_CALL_NOLOCK(rv, SN_SAL_SYSCTL_IOBRICK_PCI_OP, connection_type, n, action,
786 bus, (u64) slot, 0, 0);
787 if (rv.status)
788 return rv.v0;
789 return 0;
790}
791
792
793/*
794 * Open a subchannel for sending arbitrary data to the system
795 * controller network via the system controller device associated with
796 * 'nasid'. Return the subchannel number or a negative error code.
797 */
798static inline int
799ia64_sn_irtr_open(nasid_t nasid)
800{
801 struct ia64_sal_retval rv;
802 SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_OPEN, nasid,
803 0, 0, 0, 0, 0);
804 return (int) rv.v0;
805}
806
807/*
808 * Close system controller subchannel 'subch' previously opened on 'nasid'.
809 */
810static inline int
811ia64_sn_irtr_close(nasid_t nasid, int subch)
812{
813 struct ia64_sal_retval rv;
814 SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_CLOSE,
815 (u64) nasid, (u64) subch, 0, 0, 0, 0);
816 return (int) rv.status;
817}
818
819/*
820 * Read data from system controller associated with 'nasid' on
821 * subchannel 'subch'. The buffer to be filled is pointed to by
822 * 'buf', and its capacity is in the integer pointed to by 'len'. The
823 * referent of 'len' is set to the number of bytes read by the SAL
824 * call. The return value is either SALRET_OK (for bytes read) or
825 * SALRET_ERROR (for error or "no data available").
826 */
827static inline int
828ia64_sn_irtr_recv(nasid_t nasid, int subch, char *buf, int *len)
829{
830 struct ia64_sal_retval rv;
831 SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_RECV,
832 (u64) nasid, (u64) subch, (u64) buf, (u64) len,
833 0, 0);
834 return (int) rv.status;
835}
836
837/*
838 * Write data to the system controller network via the system
839 * controller associated with 'nasid' on suchannel 'subch'. The
840 * buffer to be written out is pointed to by 'buf', and 'len' is the
841 * number of bytes to be written. The return value is either the
842 * number of bytes written (which could be zero) or a negative error
843 * code.
844 */
845static inline int
846ia64_sn_irtr_send(nasid_t nasid, int subch, char *buf, int len)
847{
848 struct ia64_sal_retval rv;
849 SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_SEND,
850 (u64) nasid, (u64) subch, (u64) buf, (u64) len,
851 0, 0);
852 return (int) rv.v0;
853}
854
855/*
856 * Check whether any interrupts are pending for the system controller
857 * associated with 'nasid' and its subchannel 'subch'. The return
858 * value is a mask of pending interrupts (SAL_IROUTER_INTR_XMIT and/or
859 * SAL_IROUTER_INTR_RECV).
860 */
861static inline int
862ia64_sn_irtr_intr(nasid_t nasid, int subch)
863{
864 struct ia64_sal_retval rv;
865 SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_INTR_STATUS,
866 (u64) nasid, (u64) subch, 0, 0, 0, 0);
867 return (int) rv.v0;
868}
869
870/*
871 * Enable the interrupt indicated by the intr parameter (either
872 * SAL_IROUTER_INTR_XMIT or SAL_IROUTER_INTR_RECV).
873 */
874static inline int
875ia64_sn_irtr_intr_enable(nasid_t nasid, int subch, u64 intr)
876{
877 struct ia64_sal_retval rv;
878 SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_INTR_ON,
879 (u64) nasid, (u64) subch, intr, 0, 0, 0);
880 return (int) rv.v0;
881}
882
883/*
884 * Disable the interrupt indicated by the intr parameter (either
885 * SAL_IROUTER_INTR_XMIT or SAL_IROUTER_INTR_RECV).
886 */
887static inline int
888ia64_sn_irtr_intr_disable(nasid_t nasid, int subch, u64 intr)
889{
890 struct ia64_sal_retval rv;
891 SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_INTR_OFF,
892 (u64) nasid, (u64) subch, intr, 0, 0, 0);
893 return (int) rv.v0;
894}
895
896/*
897 * Set up a node as the point of contact for system controller
898 * environmental event delivery.
899 */
900static inline int
901ia64_sn_sysctl_event_init(nasid_t nasid)
902{
903 struct ia64_sal_retval rv;
904 SAL_CALL_REENTRANT(rv, SN_SAL_SYSCTL_EVENT, (u64) nasid,
905 0, 0, 0, 0, 0, 0);
906 return (int) rv.v0;
907}
908
909/*
910 * Ask the system controller on the specified nasid to reset
911 * the CX corelet clock. Only valid on TIO nodes.
912 */
913static inline int
914ia64_sn_sysctl_tio_clock_reset(nasid_t nasid)
915{
916 struct ia64_sal_retval rv;
917 SAL_CALL_REENTRANT(rv, SN_SAL_SYSCTL_OP, SAL_SYSCTL_OP_TIO_JLCK_RST,
918 nasid, 0, 0, 0, 0, 0);
919 if (rv.status != 0)
920 return (int)rv.status;
921 if (rv.v0 != 0)
922 return (int)rv.v0;
923
924 return 0;
925}
926
927/*
928 * Get the associated ioboard type for a given nasid.
929 */
930static inline s64
931ia64_sn_sysctl_ioboard_get(nasid_t nasid, u16 *ioboard)
932{
933 struct ia64_sal_retval isrv;
934 SAL_CALL_REENTRANT(isrv, SN_SAL_SYSCTL_OP, SAL_SYSCTL_OP_IOBOARD,
935 nasid, 0, 0, 0, 0, 0);
936 if (isrv.v0 != 0) {
937 *ioboard = isrv.v0;
938 return isrv.status;
939 }
940 if (isrv.v1 != 0) {
941 *ioboard = isrv.v1;
942 return isrv.status;
943 }
944
945 return isrv.status;
946}
947
948/**
949 * ia64_sn_get_fit_compt - read a FIT entry from the PROM header
950 * @nasid: NASID of node to read
951 * @index: FIT entry index to be retrieved (0..n)
952 * @fitentry: 16 byte buffer where FIT entry will be stored.
953 * @banbuf: optional buffer for retrieving banner
954 * @banlen: length of banner buffer
955 *
956 * Access to the physical PROM chips needs to be serialized since reads and
957 * writes can't occur at the same time, so we need to call into the SAL when
958 * we want to look at the FIT entries on the chips.
959 *
960 * Returns:
961 * %SALRET_OK if ok
962 * %SALRET_INVALID_ARG if index too big
963 * %SALRET_NOT_IMPLEMENTED if running on older PROM
964 * ??? if nasid invalid OR banner buffer not large enough
965 */
966static inline int
967ia64_sn_get_fit_compt(u64 nasid, u64 index, void *fitentry, void *banbuf,
968 u64 banlen)
969{
970 struct ia64_sal_retval rv;
971 SAL_CALL_NOLOCK(rv, SN_SAL_GET_FIT_COMPT, nasid, index, fitentry,
972 banbuf, banlen, 0, 0);
973 return (int) rv.status;
974}
975
976/*
977 * Initialize the SAL components of the system controller
978 * communication driver; specifically pass in a sizable buffer that
979 * can be used for allocation of subchannel queues as new subchannels
980 * are opened. "buf" points to the buffer, and "len" specifies its
981 * length.
982 */
983static inline int
984ia64_sn_irtr_init(nasid_t nasid, void *buf, int len)
985{
986 struct ia64_sal_retval rv;
987 SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_INIT,
988 (u64) nasid, (u64) buf, (u64) len, 0, 0, 0);
989 return (int) rv.status;
990}
991
992/*
993 * Returns the nasid, subnode & slice corresponding to a SAPIC ID
994 *
995 * In:
996 * arg0 - SN_SAL_GET_SAPIC_INFO
997 * arg1 - sapicid (lid >> 16)
998 * Out:
999 * v0 - nasid
1000 * v1 - subnode
1001 * v2 - slice
1002 */
1003static inline u64
1004ia64_sn_get_sapic_info(int sapicid, int *nasid, int *subnode, int *slice)
1005{
1006 struct ia64_sal_retval ret_stuff;
1007
1008 ret_stuff.status = 0;
1009 ret_stuff.v0 = 0;
1010 ret_stuff.v1 = 0;
1011 ret_stuff.v2 = 0;
1012 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_GET_SAPIC_INFO, sapicid, 0, 0, 0, 0, 0, 0);
1013
1014/***** BEGIN HACK - temp til old proms no longer supported ********/
1015 if (ret_stuff.status == SALRET_NOT_IMPLEMENTED) {
1016 if (nasid) *nasid = sapicid & 0xfff;
1017 if (subnode) *subnode = (sapicid >> 13) & 1;
1018 if (slice) *slice = (sapicid >> 12) & 3;
1019 return 0;
1020 }
1021/***** END HACK *******/
1022
1023 if (ret_stuff.status < 0)
1024 return ret_stuff.status;
1025
1026 if (nasid) *nasid = (int) ret_stuff.v0;
1027 if (subnode) *subnode = (int) ret_stuff.v1;
1028 if (slice) *slice = (int) ret_stuff.v2;
1029 return 0;
1030}
1031
1032/*
1033 * Returns information about the HUB/SHUB.
1034 * In:
1035 * arg0 - SN_SAL_GET_SN_INFO
1036 * arg1 - 0 (other values reserved for future use)
1037 * Out:
1038 * v0
1039 * [7:0] - shub type (0=shub1, 1=shub2)
1040 * [15:8] - Log2 max number of nodes in entire system (includes
1041 * C-bricks, I-bricks, etc)
1042 * [23:16] - Log2 of nodes per sharing domain
1043 * [31:24] - partition ID
1044 * [39:32] - coherency_id
1045 * [47:40] - regionsize
1046 * v1
1047 * [15:0] - nasid mask (ex., 0x7ff for 11 bit nasid)
1048 * [23:15] - bit position of low nasid bit
1049 */
1050static inline u64
1051ia64_sn_get_sn_info(int fc, u8 *shubtype, u16 *nasid_bitmask, u8 *nasid_shift,
1052 u8 *systemsize, u8 *sharing_domain_size, u8 *partid, u8 *coher, u8 *reg)
1053{
1054 struct ia64_sal_retval ret_stuff;
1055
1056 ret_stuff.status = 0;
1057 ret_stuff.v0 = 0;
1058 ret_stuff.v1 = 0;
1059 ret_stuff.v2 = 0;
1060 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_GET_SN_INFO, fc, 0, 0, 0, 0, 0, 0);
1061
1062/***** BEGIN HACK - temp til old proms no longer supported ********/
1063 if (ret_stuff.status == SALRET_NOT_IMPLEMENTED) {
1064 int nasid = get_sapicid() & 0xfff;
1065#define SH_SHUB_ID_NODES_PER_BIT_MASK 0x001f000000000000UL
1066#define SH_SHUB_ID_NODES_PER_BIT_SHFT 48
1067 if (shubtype) *shubtype = 0;
1068 if (nasid_bitmask) *nasid_bitmask = 0x7ff;
1069 if (nasid_shift) *nasid_shift = 38;
1070 if (systemsize) *systemsize = 10;
1071 if (sharing_domain_size) *sharing_domain_size = 8;
1072 if (partid) *partid = ia64_sn_sysctl_partition_get(nasid);
1073 if (coher) *coher = nasid >> 9;
1074 if (reg) *reg = (HUB_L((u64 *) LOCAL_MMR_ADDR(SH1_SHUB_ID)) & SH_SHUB_ID_NODES_PER_BIT_MASK) >>
1075 SH_SHUB_ID_NODES_PER_BIT_SHFT;
1076 return 0;
1077 }
1078/***** END HACK *******/
1079
1080 if (ret_stuff.status < 0)
1081 return ret_stuff.status;
1082
1083 if (shubtype) *shubtype = ret_stuff.v0 & 0xff;
1084 if (systemsize) *systemsize = (ret_stuff.v0 >> 8) & 0xff;
1085 if (sharing_domain_size) *sharing_domain_size = (ret_stuff.v0 >> 16) & 0xff;
1086 if (partid) *partid = (ret_stuff.v0 >> 24) & 0xff;
1087 if (coher) *coher = (ret_stuff.v0 >> 32) & 0xff;
1088 if (reg) *reg = (ret_stuff.v0 >> 40) & 0xff;
1089 if (nasid_bitmask) *nasid_bitmask = (ret_stuff.v1 & 0xffff);
1090 if (nasid_shift) *nasid_shift = (ret_stuff.v1 >> 16) & 0xff;
1091 return 0;
1092}
1093
1094/*
1095 * This is the access point to the Altix PROM hardware performance
1096 * and status monitoring interface. For info on using this, see
1097 * include/asm-ia64/sn/sn2/sn_hwperf.h
1098 */
1099static inline int
1100ia64_sn_hwperf_op(nasid_t nasid, u64 opcode, u64 a0, u64 a1, u64 a2,
1101 u64 a3, u64 a4, int *v0)
1102{
1103 struct ia64_sal_retval rv;
1104 SAL_CALL_NOLOCK(rv, SN_SAL_HWPERF_OP, (u64)nasid,
1105 opcode, a0, a1, a2, a3, a4);
1106 if (v0)
1107 *v0 = (int) rv.v0;
1108 return (int) rv.status;
1109}
1110
1111static inline int
1112ia64_sn_ioif_get_pci_topology(u64 buf, u64 len)
1113{
1114 struct ia64_sal_retval rv;
1115 SAL_CALL_NOLOCK(rv, SN_SAL_IOIF_GET_PCI_TOPOLOGY, buf, len, 0, 0, 0, 0, 0);
1116 return (int) rv.status;
1117}
1118
1119/*
1120 * BTE error recovery is implemented in SAL
1121 */
1122static inline int
1123ia64_sn_bte_recovery(nasid_t nasid)
1124{
1125 struct ia64_sal_retval rv;
1126
1127 rv.status = 0;
1128 SAL_CALL_NOLOCK(rv, SN_SAL_BTE_RECOVER, (u64)nasid, 0, 0, 0, 0, 0, 0);
1129 if (rv.status == SALRET_NOT_IMPLEMENTED)
1130 return 0;
1131 return (int) rv.status;
1132}
1133
1134static inline int
1135ia64_sn_is_fake_prom(void)
1136{
1137 struct ia64_sal_retval rv;
1138 SAL_CALL_NOLOCK(rv, SN_SAL_FAKE_PROM, 0, 0, 0, 0, 0, 0, 0);
1139 return (rv.status == 0);
1140}
1141
1142static inline int
1143ia64_sn_get_prom_feature_set(int set, unsigned long *feature_set)
1144{
1145 struct ia64_sal_retval rv;
1146
1147 SAL_CALL_NOLOCK(rv, SN_SAL_GET_PROM_FEATURE_SET, set, 0, 0, 0, 0, 0, 0);
1148 if (rv.status != 0)
1149 return rv.status;
1150 *feature_set = rv.v0;
1151 return 0;
1152}
1153
1154static inline int
1155ia64_sn_set_os_feature(int feature)
1156{
1157 struct ia64_sal_retval rv;
1158
1159 SAL_CALL_NOLOCK(rv, SN_SAL_SET_OS_FEATURE_SET, feature, 0, 0, 0, 0, 0, 0);
1160 return rv.status;
1161}
1162
1163static inline int
1164sn_inject_error(u64 paddr, u64 *data, u64 *ecc)
1165{
1166 struct ia64_sal_retval ret_stuff;
1167
1168 ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_INJECT_ERROR, paddr, (u64)data,
1169 (u64)ecc, 0, 0, 0, 0);
1170 return ret_stuff.status;
1171}
1172
1173static inline int
1174ia64_sn_set_cpu_number(int cpu)
1175{
1176 struct ia64_sal_retval rv;
1177
1178 SAL_CALL_NOLOCK(rv, SN_SAL_SET_CPU_NUMBER, cpu, 0, 0, 0, 0, 0, 0);
1179 return rv.status;
1180}
1181static inline int
1182ia64_sn_kernel_launch_event(void)
1183{
1184 struct ia64_sal_retval rv;
1185 SAL_CALL_NOLOCK(rv, SN_SAL_KERNEL_LAUNCH_EVENT, 0, 0, 0, 0, 0, 0, 0);
1186 return rv.status;
1187}
1188#endif /* _ASM_IA64_SN_SN_SAL_H */
diff --git a/include/asm-ia64/sn/tioca.h b/include/asm-ia64/sn/tioca.h
deleted file mode 100644
index 666222d7f0f..00000000000
--- a/include/asm-ia64/sn/tioca.h
+++ /dev/null
@@ -1,596 +0,0 @@
1#ifndef _ASM_IA64_SN_TIO_TIOCA_H
2#define _ASM_IA64_SN_TIO_TIOCA_H
3
4/*
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 *
9 * Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved.
10 */
11
12
13#define TIOCA_PART_NUM 0xE020
14#define TIOCA_MFGR_NUM 0x24
15#define TIOCA_REV_A 0x1
16
17/*
18 * Register layout for TIO:CA. See below for bitmasks for each register.
19 */
20
21struct tioca {
22 u64 ca_id; /* 0x000000 */
23 u64 ca_control1; /* 0x000008 */
24 u64 ca_control2; /* 0x000010 */
25 u64 ca_status1; /* 0x000018 */
26 u64 ca_status2; /* 0x000020 */
27 u64 ca_gart_aperature; /* 0x000028 */
28 u64 ca_gfx_detach; /* 0x000030 */
29 u64 ca_inta_dest_addr; /* 0x000038 */
30 u64 ca_intb_dest_addr; /* 0x000040 */
31 u64 ca_err_int_dest_addr; /* 0x000048 */
32 u64 ca_int_status; /* 0x000050 */
33 u64 ca_int_status_alias; /* 0x000058 */
34 u64 ca_mult_error; /* 0x000060 */
35 u64 ca_mult_error_alias; /* 0x000068 */
36 u64 ca_first_error; /* 0x000070 */
37 u64 ca_int_mask; /* 0x000078 */
38 u64 ca_crm_pkterr_type; /* 0x000080 */
39 u64 ca_crm_pkterr_type_alias; /* 0x000088 */
40 u64 ca_crm_ct_error_detail_1; /* 0x000090 */
41 u64 ca_crm_ct_error_detail_2; /* 0x000098 */
42 u64 ca_crm_tnumto; /* 0x0000A0 */
43 u64 ca_gart_err; /* 0x0000A8 */
44 u64 ca_pcierr_type; /* 0x0000B0 */
45 u64 ca_pcierr_addr; /* 0x0000B8 */
46
47 u64 ca_pad_0000C0[3]; /* 0x0000{C0..D0} */
48
49 u64 ca_pci_rd_buf_flush; /* 0x0000D8 */
50 u64 ca_pci_dma_addr_extn; /* 0x0000E0 */
51 u64 ca_agp_dma_addr_extn; /* 0x0000E8 */
52 u64 ca_force_inta; /* 0x0000F0 */
53 u64 ca_force_intb; /* 0x0000F8 */
54 u64 ca_debug_vector_sel; /* 0x000100 */
55 u64 ca_debug_mux_core_sel; /* 0x000108 */
56 u64 ca_debug_mux_pci_sel; /* 0x000110 */
57 u64 ca_debug_domain_sel; /* 0x000118 */
58
59 u64 ca_pad_000120[28]; /* 0x0001{20..F8} */
60
61 u64 ca_gart_ptr_table; /* 0x200 */
62 u64 ca_gart_tlb_addr[8]; /* 0x2{08..40} */
63};
64
65/*
66 * Mask/shift definitions for TIO:CA registers. The convention here is
67 * to mainly use the names as they appear in the "TIO AEGIS Programmers'
68 * Reference" with a CA_ prefix added. Some exceptions were made to fix
69 * duplicate field names or to generalize fields that are common to
70 * different registers (ca_debug_mux_core_sel and ca_debug_mux_pci_sel for
71 * example).
72 *
73 * Fields consisting of a single bit have a single #define have a single
74 * macro declaration to mask the bit. Fields consisting of multiple bits
75 * have two declarations: one to mask the proper bits in a register, and
76 * a second with the suffix "_SHFT" to identify how far the mask needs to
77 * be shifted right to get its base value.
78 */
79
80/* ==== ca_control1 */
81#define CA_SYS_BIG_END (1ull << 0)
82#define CA_DMA_AGP_SWAP (1ull << 1)
83#define CA_DMA_PCI_SWAP (1ull << 2)
84#define CA_PIO_IO_SWAP (1ull << 3)
85#define CA_PIO_MEM_SWAP (1ull << 4)
86#define CA_GFX_WR_SWAP (1ull << 5)
87#define CA_AGP_FW_ENABLE (1ull << 6)
88#define CA_AGP_CAL_CYCLE (0x7ull << 7)
89#define CA_AGP_CAL_CYCLE_SHFT 7
90#define CA_AGP_CAL_PRSCL_BYP (1ull << 10)
91#define CA_AGP_INIT_CAL_ENB (1ull << 11)
92#define CA_INJ_ADDR_PERR (1ull << 12)
93#define CA_INJ_DATA_PERR (1ull << 13)
94 /* bits 15:14 unused */
95#define CA_PCIM_IO_NBE_AD (0x7ull << 16)
96#define CA_PCIM_IO_NBE_AD_SHFT 16
97#define CA_PCIM_FAST_BTB_ENB (1ull << 19)
98 /* bits 23:20 unused */
99#define CA_PIO_ADDR_OFFSET (0xffull << 24)
100#define CA_PIO_ADDR_OFFSET_SHFT 24
101 /* bits 35:32 unused */
102#define CA_AGPDMA_OP_COMBDELAY (0x1full << 36)
103#define CA_AGPDMA_OP_COMBDELAY_SHFT 36
104 /* bit 41 unused */
105#define CA_AGPDMA_OP_ENB_COMBDELAY (1ull << 42)
106#define CA_PCI_INT_LPCNT (0xffull << 44)
107#define CA_PCI_INT_LPCNT_SHFT 44
108 /* bits 63:52 unused */
109
110/* ==== ca_control2 */
111#define CA_AGP_LATENCY_TO (0xffull << 0)
112#define CA_AGP_LATENCY_TO_SHFT 0
113#define CA_PCI_LATENCY_TO (0xffull << 8)
114#define CA_PCI_LATENCY_TO_SHFT 8
115#define CA_PCI_MAX_RETRY (0x3ffull << 16)
116#define CA_PCI_MAX_RETRY_SHFT 16
117 /* bits 27:26 unused */
118#define CA_RT_INT_EN (0x3ull << 28)
119#define CA_RT_INT_EN_SHFT 28
120#define CA_MSI_INT_ENB (1ull << 30)
121#define CA_PCI_ARB_ERR_ENB (1ull << 31)
122#define CA_GART_MEM_PARAM (0x3ull << 32)
123#define CA_GART_MEM_PARAM_SHFT 32
124#define CA_GART_RD_PREFETCH_ENB (1ull << 34)
125#define CA_GART_WR_PREFETCH_ENB (1ull << 35)
126#define CA_GART_FLUSH_TLB (1ull << 36)
127 /* bits 39:37 unused */
128#define CA_CRM_TNUMTO_PERIOD (0x1fffull << 40)
129#define CA_CRM_TNUMTO_PERIOD_SHFT 40
130 /* bits 55:53 unused */
131#define CA_CRM_TNUMTO_ENB (1ull << 56)
132#define CA_CRM_PRESCALER_BYP (1ull << 57)
133 /* bits 59:58 unused */
134#define CA_CRM_MAX_CREDIT (0x7ull << 60)
135#define CA_CRM_MAX_CREDIT_SHFT 60
136 /* bit 63 unused */
137
138/* ==== ca_status1 */
139#define CA_CORELET_ID (0x3ull << 0)
140#define CA_CORELET_ID_SHFT 0
141#define CA_INTA_N (1ull << 2)
142#define CA_INTB_N (1ull << 3)
143#define CA_CRM_CREDIT_AVAIL (0x7ull << 4)
144#define CA_CRM_CREDIT_AVAIL_SHFT 4
145 /* bit 7 unused */
146#define CA_CRM_SPACE_AVAIL (0x7full << 8)
147#define CA_CRM_SPACE_AVAIL_SHFT 8
148 /* bit 15 unused */
149#define CA_GART_TLB_VAL (0xffull << 16)
150#define CA_GART_TLB_VAL_SHFT 16
151 /* bits 63:24 unused */
152
153/* ==== ca_status2 */
154#define CA_GFX_CREDIT_AVAIL (0xffull << 0)
155#define CA_GFX_CREDIT_AVAIL_SHFT 0
156#define CA_GFX_OPQ_AVAIL (0xffull << 8)
157#define CA_GFX_OPQ_AVAIL_SHFT 8
158#define CA_GFX_WRBUFF_AVAIL (0xffull << 16)
159#define CA_GFX_WRBUFF_AVAIL_SHFT 16
160#define CA_ADMA_OPQ_AVAIL (0xffull << 24)
161#define CA_ADMA_OPQ_AVAIL_SHFT 24
162#define CA_ADMA_WRBUFF_AVAIL (0xffull << 32)
163#define CA_ADMA_WRBUFF_AVAIL_SHFT 32
164#define CA_ADMA_RDBUFF_AVAIL (0x7full << 40)
165#define CA_ADMA_RDBUFF_AVAIL_SHFT 40
166#define CA_PCI_PIO_OP_STAT (1ull << 47)
167#define CA_PDMA_OPQ_AVAIL (0xfull << 48)
168#define CA_PDMA_OPQ_AVAIL_SHFT 48
169#define CA_PDMA_WRBUFF_AVAIL (0xfull << 52)
170#define CA_PDMA_WRBUFF_AVAIL_SHFT 52
171#define CA_PDMA_RDBUFF_AVAIL (0x3ull << 56)
172#define CA_PDMA_RDBUFF_AVAIL_SHFT 56
173 /* bits 63:58 unused */
174
175/* ==== ca_gart_aperature */
176#define CA_GART_AP_ENB_AGP (1ull << 0)
177#define CA_GART_PAGE_SIZE (1ull << 1)
178#define CA_GART_AP_ENB_PCI (1ull << 2)
179 /* bits 11:3 unused */
180#define CA_GART_AP_SIZE (0x3ffull << 12)
181#define CA_GART_AP_SIZE_SHFT 12
182#define CA_GART_AP_BASE (0x3ffffffffffull << 22)
183#define CA_GART_AP_BASE_SHFT 22
184
185/* ==== ca_inta_dest_addr
186 ==== ca_intb_dest_addr
187 ==== ca_err_int_dest_addr */
188 /* bits 2:0 unused */
189#define CA_INT_DEST_ADDR (0x7ffffffffffffull << 3)
190#define CA_INT_DEST_ADDR_SHFT 3
191 /* bits 55:54 unused */
192#define CA_INT_DEST_VECT (0xffull << 56)
193#define CA_INT_DEST_VECT_SHFT 56
194
195/* ==== ca_int_status */
196/* ==== ca_int_status_alias */
197/* ==== ca_mult_error */
198/* ==== ca_mult_error_alias */
199/* ==== ca_first_error */
200/* ==== ca_int_mask */
201#define CA_PCI_ERR (1ull << 0)
202 /* bits 3:1 unused */
203#define CA_GART_FETCH_ERR (1ull << 4)
204#define CA_GFX_WR_OVFLW (1ull << 5)
205#define CA_PIO_REQ_OVFLW (1ull << 6)
206#define CA_CRM_PKTERR (1ull << 7)
207#define CA_CRM_DVERR (1ull << 8)
208#define CA_TNUMTO (1ull << 9)
209#define CA_CXM_RSP_CRED_OVFLW (1ull << 10)
210#define CA_CXM_REQ_CRED_OVFLW (1ull << 11)
211#define CA_PIO_INVALID_ADDR (1ull << 12)
212#define CA_PCI_ARB_TO (1ull << 13)
213#define CA_AGP_REQ_OFLOW (1ull << 14)
214#define CA_SBA_TYPE1_ERR (1ull << 15)
215 /* bit 16 unused */
216#define CA_INTA (1ull << 17)
217#define CA_INTB (1ull << 18)
218#define CA_MULT_INTA (1ull << 19)
219#define CA_MULT_INTB (1ull << 20)
220#define CA_GFX_CREDIT_OVFLW (1ull << 21)
221 /* bits 63:22 unused */
222
223/* ==== ca_crm_pkterr_type */
224/* ==== ca_crm_pkterr_type_alias */
225#define CA_CRM_PKTERR_SBERR_HDR (1ull << 0)
226#define CA_CRM_PKTERR_DIDN (1ull << 1)
227#define CA_CRM_PKTERR_PACTYPE (1ull << 2)
228#define CA_CRM_PKTERR_INV_TNUM (1ull << 3)
229#define CA_CRM_PKTERR_ADDR_RNG (1ull << 4)
230#define CA_CRM_PKTERR_ADDR_ALGN (1ull << 5)
231#define CA_CRM_PKTERR_HDR_PARAM (1ull << 6)
232#define CA_CRM_PKTERR_CW_ERR (1ull << 7)
233#define CA_CRM_PKTERR_SBERR_NH (1ull << 8)
234#define CA_CRM_PKTERR_EARLY_TERM (1ull << 9)
235#define CA_CRM_PKTERR_EARLY_TAIL (1ull << 10)
236#define CA_CRM_PKTERR_MSSNG_TAIL (1ull << 11)
237#define CA_CRM_PKTERR_MSSNG_HDR (1ull << 12)
238 /* bits 15:13 unused */
239#define CA_FIRST_CRM_PKTERR_SBERR_HDR (1ull << 16)
240#define CA_FIRST_CRM_PKTERR_DIDN (1ull << 17)
241#define CA_FIRST_CRM_PKTERR_PACTYPE (1ull << 18)
242#define CA_FIRST_CRM_PKTERR_INV_TNUM (1ull << 19)
243#define CA_FIRST_CRM_PKTERR_ADDR_RNG (1ull << 20)
244#define CA_FIRST_CRM_PKTERR_ADDR_ALGN (1ull << 21)
245#define CA_FIRST_CRM_PKTERR_HDR_PARAM (1ull << 22)
246#define CA_FIRST_CRM_PKTERR_CW_ERR (1ull << 23)
247#define CA_FIRST_CRM_PKTERR_SBERR_NH (1ull << 24)
248#define CA_FIRST_CRM_PKTERR_EARLY_TERM (1ull << 25)
249#define CA_FIRST_CRM_PKTERR_EARLY_TAIL (1ull << 26)
250#define CA_FIRST_CRM_PKTERR_MSSNG_TAIL (1ull << 27)
251#define CA_FIRST_CRM_PKTERR_MSSNG_HDR (1ull << 28)
252 /* bits 63:29 unused */
253
254/* ==== ca_crm_ct_error_detail_1 */
255#define CA_PKT_TYPE (0xfull << 0)
256#define CA_PKT_TYPE_SHFT 0
257#define CA_SRC_ID (0x3ull << 4)
258#define CA_SRC_ID_SHFT 4
259#define CA_DATA_SZ (0x3ull << 6)
260#define CA_DATA_SZ_SHFT 6
261#define CA_TNUM (0xffull << 8)
262#define CA_TNUM_SHFT 8
263#define CA_DW_DATA_EN (0xffull << 16)
264#define CA_DW_DATA_EN_SHFT 16
265#define CA_GFX_CRED (0xffull << 24)
266#define CA_GFX_CRED_SHFT 24
267#define CA_MEM_RD_PARAM (0x3ull << 32)
268#define CA_MEM_RD_PARAM_SHFT 32
269#define CA_PIO_OP (1ull << 34)
270#define CA_CW_ERR (1ull << 35)
271 /* bits 62:36 unused */
272#define CA_VALID (1ull << 63)
273
274/* ==== ca_crm_ct_error_detail_2 */
275 /* bits 2:0 unused */
276#define CA_PKT_ADDR (0x1fffffffffffffull << 3)
277#define CA_PKT_ADDR_SHFT 3
278 /* bits 63:56 unused */
279
280/* ==== ca_crm_tnumto */
281#define CA_CRM_TNUMTO_VAL (0xffull << 0)
282#define CA_CRM_TNUMTO_VAL_SHFT 0
283#define CA_CRM_TNUMTO_WR (1ull << 8)
284 /* bits 63:9 unused */
285
286/* ==== ca_gart_err */
287#define CA_GART_ERR_SOURCE (0x3ull << 0)
288#define CA_GART_ERR_SOURCE_SHFT 0
289 /* bits 3:2 unused */
290#define CA_GART_ERR_ADDR (0xfffffffffull << 4)
291#define CA_GART_ERR_ADDR_SHFT 4
292 /* bits 63:40 unused */
293
294/* ==== ca_pcierr_type */
295#define CA_PCIERR_DATA (0xffffffffull << 0)
296#define CA_PCIERR_DATA_SHFT 0
297#define CA_PCIERR_ENB (0xfull << 32)
298#define CA_PCIERR_ENB_SHFT 32
299#define CA_PCIERR_CMD (0xfull << 36)
300#define CA_PCIERR_CMD_SHFT 36
301#define CA_PCIERR_A64 (1ull << 40)
302#define CA_PCIERR_SLV_SERR (1ull << 41)
303#define CA_PCIERR_SLV_WR_PERR (1ull << 42)
304#define CA_PCIERR_SLV_RD_PERR (1ull << 43)
305#define CA_PCIERR_MST_SERR (1ull << 44)
306#define CA_PCIERR_MST_WR_PERR (1ull << 45)
307#define CA_PCIERR_MST_RD_PERR (1ull << 46)
308#define CA_PCIERR_MST_MABT (1ull << 47)
309#define CA_PCIERR_MST_TABT (1ull << 48)
310#define CA_PCIERR_MST_RETRY_TOUT (1ull << 49)
311
312#define CA_PCIERR_TYPES \
313 (CA_PCIERR_A64|CA_PCIERR_SLV_SERR| \
314 CA_PCIERR_SLV_WR_PERR|CA_PCIERR_SLV_RD_PERR| \
315 CA_PCIERR_MST_SERR|CA_PCIERR_MST_WR_PERR|CA_PCIERR_MST_RD_PERR| \
316 CA_PCIERR_MST_MABT|CA_PCIERR_MST_TABT|CA_PCIERR_MST_RETRY_TOUT)
317
318 /* bits 63:50 unused */
319
320/* ==== ca_pci_dma_addr_extn */
321#define CA_UPPER_NODE_OFFSET (0x3full << 0)
322#define CA_UPPER_NODE_OFFSET_SHFT 0
323 /* bits 7:6 unused */
324#define CA_CHIPLET_ID (0x3ull << 8)
325#define CA_CHIPLET_ID_SHFT 8
326 /* bits 11:10 unused */
327#define CA_PCI_DMA_NODE_ID (0xffffull << 12)
328#define CA_PCI_DMA_NODE_ID_SHFT 12
329 /* bits 27:26 unused */
330#define CA_PCI_DMA_PIO_MEM_TYPE (1ull << 28)
331 /* bits 63:29 unused */
332
333
334/* ==== ca_agp_dma_addr_extn */
335 /* bits 19:0 unused */
336#define CA_AGP_DMA_NODE_ID (0xffffull << 20)
337#define CA_AGP_DMA_NODE_ID_SHFT 20
338 /* bits 27:26 unused */
339#define CA_AGP_DMA_PIO_MEM_TYPE (1ull << 28)
340 /* bits 63:29 unused */
341
342/* ==== ca_debug_vector_sel */
343#define CA_DEBUG_MN_VSEL (0xfull << 0)
344#define CA_DEBUG_MN_VSEL_SHFT 0
345#define CA_DEBUG_PP_VSEL (0xfull << 4)
346#define CA_DEBUG_PP_VSEL_SHFT 4
347#define CA_DEBUG_GW_VSEL (0xfull << 8)
348#define CA_DEBUG_GW_VSEL_SHFT 8
349#define CA_DEBUG_GT_VSEL (0xfull << 12)
350#define CA_DEBUG_GT_VSEL_SHFT 12
351#define CA_DEBUG_PD_VSEL (0xfull << 16)
352#define CA_DEBUG_PD_VSEL_SHFT 16
353#define CA_DEBUG_AD_VSEL (0xfull << 20)
354#define CA_DEBUG_AD_VSEL_SHFT 20
355#define CA_DEBUG_CX_VSEL (0xfull << 24)
356#define CA_DEBUG_CX_VSEL_SHFT 24
357#define CA_DEBUG_CR_VSEL (0xfull << 28)
358#define CA_DEBUG_CR_VSEL_SHFT 28
359#define CA_DEBUG_BA_VSEL (0xfull << 32)
360#define CA_DEBUG_BA_VSEL_SHFT 32
361#define CA_DEBUG_PE_VSEL (0xfull << 36)
362#define CA_DEBUG_PE_VSEL_SHFT 36
363#define CA_DEBUG_BO_VSEL (0xfull << 40)
364#define CA_DEBUG_BO_VSEL_SHFT 40
365#define CA_DEBUG_BI_VSEL (0xfull << 44)
366#define CA_DEBUG_BI_VSEL_SHFT 44
367#define CA_DEBUG_AS_VSEL (0xfull << 48)
368#define CA_DEBUG_AS_VSEL_SHFT 48
369#define CA_DEBUG_PS_VSEL (0xfull << 52)
370#define CA_DEBUG_PS_VSEL_SHFT 52
371#define CA_DEBUG_PM_VSEL (0xfull << 56)
372#define CA_DEBUG_PM_VSEL_SHFT 56
373 /* bits 63:60 unused */
374
375/* ==== ca_debug_mux_core_sel */
376/* ==== ca_debug_mux_pci_sel */
377#define CA_DEBUG_MSEL0 (0x7ull << 0)
378#define CA_DEBUG_MSEL0_SHFT 0
379 /* bit 3 unused */
380#define CA_DEBUG_NSEL0 (0x7ull << 4)
381#define CA_DEBUG_NSEL0_SHFT 4
382 /* bit 7 unused */
383#define CA_DEBUG_MSEL1 (0x7ull << 8)
384#define CA_DEBUG_MSEL1_SHFT 8
385 /* bit 11 unused */
386#define CA_DEBUG_NSEL1 (0x7ull << 12)
387#define CA_DEBUG_NSEL1_SHFT 12
388 /* bit 15 unused */
389#define CA_DEBUG_MSEL2 (0x7ull << 16)
390#define CA_DEBUG_MSEL2_SHFT 16
391 /* bit 19 unused */
392#define CA_DEBUG_NSEL2 (0x7ull << 20)
393#define CA_DEBUG_NSEL2_SHFT 20
394 /* bit 23 unused */
395#define CA_DEBUG_MSEL3 (0x7ull << 24)
396#define CA_DEBUG_MSEL3_SHFT 24
397 /* bit 27 unused */
398#define CA_DEBUG_NSEL3 (0x7ull << 28)
399#define CA_DEBUG_NSEL3_SHFT 28
400 /* bit 31 unused */
401#define CA_DEBUG_MSEL4 (0x7ull << 32)
402#define CA_DEBUG_MSEL4_SHFT 32
403 /* bit 35 unused */
404#define CA_DEBUG_NSEL4 (0x7ull << 36)
405#define CA_DEBUG_NSEL4_SHFT 36
406 /* bit 39 unused */
407#define CA_DEBUG_MSEL5 (0x7ull << 40)
408#define CA_DEBUG_MSEL5_SHFT 40
409 /* bit 43 unused */
410#define CA_DEBUG_NSEL5 (0x7ull << 44)
411#define CA_DEBUG_NSEL5_SHFT 44
412 /* bit 47 unused */
413#define CA_DEBUG_MSEL6 (0x7ull << 48)
414#define CA_DEBUG_MSEL6_SHFT 48
415 /* bit 51 unused */
416#define CA_DEBUG_NSEL6 (0x7ull << 52)
417#define CA_DEBUG_NSEL6_SHFT 52
418 /* bit 55 unused */
419#define CA_DEBUG_MSEL7 (0x7ull << 56)
420#define CA_DEBUG_MSEL7_SHFT 56
421 /* bit 59 unused */
422#define CA_DEBUG_NSEL7 (0x7ull << 60)
423#define CA_DEBUG_NSEL7_SHFT 60
424 /* bit 63 unused */
425
426
427/* ==== ca_debug_domain_sel */
428#define CA_DEBUG_DOMAIN_L (1ull << 0)
429#define CA_DEBUG_DOMAIN_H (1ull << 1)
430 /* bits 63:2 unused */
431
432/* ==== ca_gart_ptr_table */
433#define CA_GART_PTR_VAL (1ull << 0)
434 /* bits 11:1 unused */
435#define CA_GART_PTR_ADDR (0xfffffffffffull << 12)
436#define CA_GART_PTR_ADDR_SHFT 12
437 /* bits 63:56 unused */
438
439/* ==== ca_gart_tlb_addr[0-7] */
440#define CA_GART_TLB_ADDR (0xffffffffffffffull << 0)
441#define CA_GART_TLB_ADDR_SHFT 0
442 /* bits 62:56 unused */
443#define CA_GART_TLB_ENTRY_VAL (1ull << 63)
444
445/*
446 * PIO address space ranges for TIO:CA
447 */
448
449/* CA internal registers */
450#define CA_PIO_ADMIN 0x00000000
451#define CA_PIO_ADMIN_LEN 0x00010000
452
453/* GFX Write Buffer - Diagnostics */
454#define CA_PIO_GFX 0x00010000
455#define CA_PIO_GFX_LEN 0x00010000
456
457/* AGP DMA Write Buffer - Diagnostics */
458#define CA_PIO_AGP_DMAWRITE 0x00020000
459#define CA_PIO_AGP_DMAWRITE_LEN 0x00010000
460
461/* AGP DMA READ Buffer - Diagnostics */
462#define CA_PIO_AGP_DMAREAD 0x00030000
463#define CA_PIO_AGP_DMAREAD_LEN 0x00010000
464
465/* PCI Config Type 0 */
466#define CA_PIO_PCI_TYPE0_CONFIG 0x01000000
467#define CA_PIO_PCI_TYPE0_CONFIG_LEN 0x01000000
468
469/* PCI Config Type 1 */
470#define CA_PIO_PCI_TYPE1_CONFIG 0x02000000
471#define CA_PIO_PCI_TYPE1_CONFIG_LEN 0x01000000
472
473/* PCI I/O Cycles - mapped to PCI Address 0x00000000-0x04ffffff */
474#define CA_PIO_PCI_IO 0x03000000
475#define CA_PIO_PCI_IO_LEN 0x05000000
476
477/* PCI MEM Cycles - mapped to PCI with CA_PIO_ADDR_OFFSET of ca_control1 */
478/* use Fast Write if enabled and coretalk packet type is a GFX request */
479#define CA_PIO_PCI_MEM_OFFSET 0x08000000
480#define CA_PIO_PCI_MEM_OFFSET_LEN 0x08000000
481
482/* PCI MEM Cycles - mapped to PCI Address 0x00000000-0xbfffffff */
483/* use Fast Write if enabled and coretalk packet type is a GFX request */
484#define CA_PIO_PCI_MEM 0x40000000
485#define CA_PIO_PCI_MEM_LEN 0xc0000000
486
487/*
488 * DMA space
489 *
490 * The CA aperature (ie. bus address range) mapped by the GART is segmented into
491 * two parts. The lower portion of the aperature is used for mapping 32 bit
492 * PCI addresses which are managed by the dma interfaces in this file. The
493 * upper poprtion of the aperature is used for mapping 48 bit AGP addresses.
494 * The AGP portion of the aperature is managed by the agpgart_be.c driver
495 * in drivers/linux/agp. There are ca-specific hooks in that driver to
496 * manipulate the gart, but management of the AGP portion of the aperature
497 * is the responsibility of that driver.
498 *
499 * CA allows three main types of DMA mapping:
500 *
501 * PCI 64-bit Managed by this driver
502 * PCI 32-bit Managed by this driver
503 * AGP 48-bit Managed by hooks in the /dev/agpgart driver
504 *
505 * All of the above can optionally be remapped through the GART. The following
506 * table lists the combinations of addressing types and GART remapping that
507 * is currently supported by the driver (h/w supports all, s/w limits this):
508 *
509 * PCI64 PCI32 AGP48
510 * GART no yes yes
511 * Direct yes yes no
512 *
513 * GART remapping of PCI64 is not done because there is no need to. The
514 * 64 bit PCI address holds all of the information necessary to target any
515 * memory in the system.
516 *
517 * AGP48 is always mapped through the GART. Management of the AGP48 portion
518 * of the aperature is the responsibility of code in the agpgart_be driver.
519 *
520 * The non-64 bit bus address space will currently be partitioned like this:
521 *
522 * 0xffff_ffff_ffff +--------
523 * | AGP48 direct
524 * | Space managed by this driver
525 * CA_AGP_DIRECT_BASE +--------
526 * | AGP GART mapped (gfx aperature)
527 * | Space managed by /dev/agpgart driver
528 * | This range is exposed to the agpgart
529 * | driver as the "graphics aperature"
530 * CA_AGP_MAPPED_BASE +-----
531 * | PCI GART mapped
532 * | Space managed by this driver
533 * CA_PCI32_MAPPED_BASE +----
534 * | PCI32 direct
535 * | Space managed by this driver
536 * 0xC000_0000 +--------
537 * (CA_PCI32_DIRECT_BASE)
538 *
539 * The bus address range CA_PCI32_MAPPED_BASE through CA_AGP_DIRECT_BASE
540 * is what we call the CA aperature. Addresses falling in this range will
541 * be remapped using the GART.
542 *
543 * The bus address range CA_AGP_MAPPED_BASE through CA_AGP_DIRECT_BASE
544 * is what we call the graphics aperature. This is a subset of the CA
545 * aperature and is under the control of the agpgart_be driver.
546 *
547 * CA_PCI32_MAPPED_BASE, CA_AGP_MAPPED_BASE, and CA_AGP_DIRECT_BASE are
548 * somewhat arbitrary values. The known constraints on choosing these is:
549 *
550 * 1) CA_AGP_DIRECT_BASE-CA_PCI32_MAPPED_BASE+1 (the CA aperature size)
551 * must be one of the values supported by the ca_gart_aperature register.
552 * Currently valid values are: 4MB through 4096MB in powers of 2 increments
553 *
554 * 2) CA_AGP_DIRECT_BASE-CA_AGP_MAPPED_BASE+1 (the gfx aperature size)
555 * must be in MB units since that's what the agpgart driver assumes.
556 */
557
558/*
559 * Define Bus DMA ranges. These are configurable (see constraints above)
560 * and will probably need tuning based on experience.
561 */
562
563
564/*
565 * 11/24/03
566 * CA has an addressing glitch w.r.t. PCI direct 32 bit DMA that makes it
567 * generally unusable. The problem is that for PCI direct 32
568 * DMA's, all 32 bits of the bus address are used to form the lower 32 bits
569 * of the coretalk address, and coretalk bits 38:32 come from a register.
570 * Since only PCI bus addresses 0xC0000000-0xFFFFFFFF (1GB) are available
571 * for DMA (the rest is allocated to PIO), host node addresses need to be
572 * such that their lower 32 bits fall in the 0xC0000000-0xffffffff range
573 * as well. So there can be no PCI32 direct DMA below 3GB!! For this
574 * reason we set the CA_PCI32_DIRECT_SIZE to 0 which essentially makes
575 * tioca_dma_direct32() a noop but preserves the code flow should this issue
576 * be fixed in a respin.
577 *
578 * For now, all PCI32 DMA's must be mapped through the GART.
579 */
580
581#define CA_PCI32_DIRECT_BASE 0xC0000000UL /* BASE not configurable */
582#define CA_PCI32_DIRECT_SIZE 0x00000000UL /* 0 MB */
583
584#define CA_PCI32_MAPPED_BASE 0xC0000000UL
585#define CA_PCI32_MAPPED_SIZE 0x40000000UL /* 2GB */
586
587#define CA_AGP_MAPPED_BASE 0x80000000UL
588#define CA_AGP_MAPPED_SIZE 0x40000000UL /* 2GB */
589
590#define CA_AGP_DIRECT_BASE 0x40000000UL /* 2GB */
591#define CA_AGP_DIRECT_SIZE 0x40000000UL
592
593#define CA_APERATURE_BASE (CA_AGP_MAPPED_BASE)
594#define CA_APERATURE_SIZE (CA_AGP_MAPPED_SIZE+CA_PCI32_MAPPED_SIZE)
595
596#endif /* _ASM_IA64_SN_TIO_TIOCA_H */
diff --git a/include/asm-ia64/sn/tioca_provider.h b/include/asm-ia64/sn/tioca_provider.h
deleted file mode 100644
index 9a820ac61be..00000000000
--- a/include/asm-ia64/sn/tioca_provider.h
+++ /dev/null
@@ -1,207 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved.
7 */
8
9#ifndef _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H
10#define _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H
11
12#include <asm/sn/tioca.h>
13
14/*
15 * WAR enables
16 * Defines for individual WARs. Each is a bitmask of applicable
17 * part revision numbers. (1 << 1) == rev A, (1 << 2) == rev B,
18 * (3 << 1) == (rev A or rev B), etc
19 */
20
21#define TIOCA_WAR_ENABLED(pv, tioca_common) \
22 ((1 << tioca_common->ca_rev) & pv)
23
24 /* TIO:ICE:FRZ:Freezer loses a PIO data ucred on PIO RD RSP with CW error */
25#define PV907908 (1 << 1)
26 /* ATI config space problems after BIOS execution starts */
27#define PV908234 (1 << 1)
28 /* CA:AGPDMA write request data mismatch with ABC1CL merge */
29#define PV895469 (1 << 1)
30 /* TIO:CA TLB invalidate of written GART entries possibly not occurring in CA*/
31#define PV910244 (1 << 1)
32
33struct tioca_dmamap{
34 struct list_head cad_list; /* headed by ca_list */
35
36 dma_addr_t cad_dma_addr; /* Linux dma handle */
37 uint cad_gart_entry; /* start entry in ca_gart_pagemap */
38 uint cad_gart_size; /* #entries for this map */
39};
40
41/*
42 * Kernel only fields. Prom may look at this stuff for debugging only.
43 * Access this structure through the ca_kernel_private ptr.
44 */
45
46struct tioca_common ;
47
48struct tioca_kernel {
49 struct tioca_common *ca_common; /* tioca this belongs to */
50 struct list_head ca_list; /* list of all ca's */
51 struct list_head ca_dmamaps;
52 spinlock_t ca_lock; /* Kernel lock */
53 cnodeid_t ca_closest_node;
54 struct list_head *ca_devices; /* bus->devices */
55
56 /*
57 * General GART stuff
58 */
59 u64 ca_ap_size; /* size of aperature in bytes */
60 u32 ca_gart_entries; /* # u64 entries in gart */
61 u32 ca_ap_pagesize; /* aperature page size in bytes */
62 u64 ca_ap_bus_base; /* bus address of CA aperature */
63 u64 ca_gart_size; /* gart size in bytes */
64 u64 *ca_gart; /* gart table vaddr */
65 u64 ca_gart_coretalk_addr; /* gart coretalk addr */
66 u8 ca_gart_iscoherent; /* used in tioca_tlbflush */
67
68 /* PCI GART convenience values */
69 u64 ca_pciap_base; /* pci aperature bus base address */
70 u64 ca_pciap_size; /* pci aperature size (bytes) */
71 u64 ca_pcigart_base; /* gfx GART bus base address */
72 u64 *ca_pcigart; /* gfx GART vm address */
73 u32 ca_pcigart_entries;
74 u32 ca_pcigart_start; /* PCI start index in ca_gart */
75 void *ca_pcigart_pagemap;
76
77 /* AGP GART convenience values */
78 u64 ca_gfxap_base; /* gfx aperature bus base address */
79 u64 ca_gfxap_size; /* gfx aperature size (bytes) */
80 u64 ca_gfxgart_base; /* gfx GART bus base address */
81 u64 *ca_gfxgart; /* gfx GART vm address */
82 u32 ca_gfxgart_entries;
83 u32 ca_gfxgart_start; /* agpgart start index in ca_gart */
84};
85
86/*
87 * Common tioca info shared between kernel and prom
88 *
89 * DO NOT CHANGE THIS STRUCT WITHOUT MAKING CORRESPONDING CHANGES
90 * TO THE PROM VERSION.
91 */
92
93struct tioca_common {
94 struct pcibus_bussoft ca_common; /* common pciio header */
95
96 u32 ca_rev;
97 u32 ca_closest_nasid;
98
99 u64 ca_prom_private;
100 u64 ca_kernel_private;
101};
102
103/**
104 * tioca_paddr_to_gart - Convert an SGI coretalk address to a CA GART entry
105 * @paddr: page address to convert
106 *
107 * Convert a system [coretalk] address to a GART entry. GART entries are
108 * formed using the following:
109 *
110 * data = ( (1<<63) | ( (REMAP_NODE_ID << 40) | (MD_CHIPLET_ID << 38) |
111 * (REMAP_SYS_ADDR) ) >> 12 )
112 *
113 * DATA written to 1 GART TABLE Entry in system memory is remapped system
114 * addr for 1 page
115 *
116 * The data is for coretalk address format right shifted 12 bits with a
117 * valid bit.
118 *
119 * GART_TABLE_ENTRY [ 25:0 ] -- REMAP_SYS_ADDRESS[37:12].
120 * GART_TABLE_ENTRY [ 27:26 ] -- SHUB MD chiplet id.
121 * GART_TABLE_ENTRY [ 41:28 ] -- REMAP_NODE_ID.
122 * GART_TABLE_ENTRY [ 63 ] -- Valid Bit
123 */
124static inline u64
125tioca_paddr_to_gart(unsigned long paddr)
126{
127 /*
128 * We are assuming right now that paddr already has the correct
129 * format since the address from xtalk_dmaXXX should already have
130 * NODE_ID, CHIPLET_ID, and SYS_ADDR in the correct locations.
131 */
132
133 return ((paddr) >> 12) | (1UL << 63);
134}
135
136/**
137 * tioca_physpage_to_gart - Map a host physical page for SGI CA based DMA
138 * @page_addr: system page address to map
139 */
140
141static inline unsigned long
142tioca_physpage_to_gart(u64 page_addr)
143{
144 u64 coretalk_addr;
145
146 coretalk_addr = PHYS_TO_TIODMA(page_addr);
147 if (!coretalk_addr) {
148 return 0;
149 }
150
151 return tioca_paddr_to_gart(coretalk_addr);
152}
153
154/**
155 * tioca_tlbflush - invalidate cached SGI CA GART TLB entries
156 * @tioca_kernel: CA context
157 *
158 * Invalidate tlb entries for a given CA GART. Main complexity is to account
159 * for revA bug.
160 */
161static inline void
162tioca_tlbflush(struct tioca_kernel *tioca_kernel)
163{
164 volatile u64 tmp;
165 volatile struct tioca __iomem *ca_base;
166 struct tioca_common *tioca_common;
167
168 tioca_common = tioca_kernel->ca_common;
169 ca_base = (struct tioca __iomem *)tioca_common->ca_common.bs_base;
170
171 /*
172 * Explicit flushes not needed if GART is in cached mode
173 */
174 if (tioca_kernel->ca_gart_iscoherent) {
175 if (TIOCA_WAR_ENABLED(PV910244, tioca_common)) {
176 /*
177 * PV910244: RevA CA needs explicit flushes.
178 * Need to put GART into uncached mode before
179 * flushing otherwise the explicit flush is ignored.
180 *
181 * Alternate WAR would be to leave GART cached and
182 * touch every CL aligned GART entry.
183 */
184
185 __sn_clrq_relaxed(&ca_base->ca_control2, CA_GART_MEM_PARAM);
186 __sn_setq_relaxed(&ca_base->ca_control2, CA_GART_FLUSH_TLB);
187 __sn_setq_relaxed(&ca_base->ca_control2,
188 (0x2ull << CA_GART_MEM_PARAM_SHFT));
189 tmp = __sn_readq_relaxed(&ca_base->ca_control2);
190 }
191
192 return;
193 }
194
195 /*
196 * Gart in uncached mode ... need an explicit flush.
197 */
198
199 __sn_setq_relaxed(&ca_base->ca_control2, CA_GART_FLUSH_TLB);
200 tmp = __sn_readq_relaxed(&ca_base->ca_control2);
201}
202
203extern u32 tioca_gart_found;
204extern struct list_head tioca_list;
205extern int tioca_init_provider(void);
206extern void tioca_fastwrite_enable(struct tioca_kernel *tioca_kern);
207#endif /* _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H */
diff --git a/include/asm-ia64/sn/tioce.h b/include/asm-ia64/sn/tioce.h
deleted file mode 100644
index 893468e1b41..00000000000
--- a/include/asm-ia64/sn/tioce.h
+++ /dev/null
@@ -1,760 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved.
7 */
8
9#ifndef __ASM_IA64_SN_TIOCE_H__
10#define __ASM_IA64_SN_TIOCE_H__
11
12/* CE ASIC part & mfgr information */
13#define TIOCE_PART_NUM 0xCE00
14#define TIOCE_SRC_ID 0x01
15#define TIOCE_REV_A 0x1
16
17/* CE Virtual PPB Vendor/Device IDs */
18#define CE_VIRT_PPB_VENDOR_ID 0x10a9
19#define CE_VIRT_PPB_DEVICE_ID 0x4002
20
21/* CE Host Bridge Vendor/Device IDs */
22#define CE_HOST_BRIDGE_VENDOR_ID 0x10a9
23#define CE_HOST_BRIDGE_DEVICE_ID 0x4001
24
25
26#define TIOCE_NUM_M40_ATES 4096
27#define TIOCE_NUM_M3240_ATES 2048
28#define TIOCE_NUM_PORTS 2
29
30/*
31 * Register layout for TIOCE. MMR offsets are shown at the far right of the
32 * structure definition.
33 */
34typedef volatile struct tioce {
35 /*
36 * ADMIN : Administration Registers
37 */
38 u64 ce_adm_id; /* 0x000000 */
39 u64 ce_pad_000008; /* 0x000008 */
40 u64 ce_adm_dyn_credit_status; /* 0x000010 */
41 u64 ce_adm_last_credit_status; /* 0x000018 */
42 u64 ce_adm_credit_limit; /* 0x000020 */
43 u64 ce_adm_force_credit; /* 0x000028 */
44 u64 ce_adm_control; /* 0x000030 */
45 u64 ce_adm_mmr_chn_timeout; /* 0x000038 */
46 u64 ce_adm_ssp_ure_timeout; /* 0x000040 */
47 u64 ce_adm_ssp_dre_timeout; /* 0x000048 */
48 u64 ce_adm_ssp_debug_sel; /* 0x000050 */
49 u64 ce_adm_int_status; /* 0x000058 */
50 u64 ce_adm_int_status_alias; /* 0x000060 */
51 u64 ce_adm_int_mask; /* 0x000068 */
52 u64 ce_adm_int_pending; /* 0x000070 */
53 u64 ce_adm_force_int; /* 0x000078 */
54 u64 ce_adm_ure_ups_buf_barrier_flush; /* 0x000080 */
55 u64 ce_adm_int_dest[15]; /* 0x000088 -- 0x0000F8 */
56 u64 ce_adm_error_summary; /* 0x000100 */
57 u64 ce_adm_error_summary_alias; /* 0x000108 */
58 u64 ce_adm_error_mask; /* 0x000110 */
59 u64 ce_adm_first_error; /* 0x000118 */
60 u64 ce_adm_error_overflow; /* 0x000120 */
61 u64 ce_adm_error_overflow_alias; /* 0x000128 */
62 u64 ce_pad_000130[2]; /* 0x000130 -- 0x000138 */
63 u64 ce_adm_tnum_error; /* 0x000140 */
64 u64 ce_adm_mmr_err_detail; /* 0x000148 */
65 u64 ce_adm_msg_sram_perr_detail; /* 0x000150 */
66 u64 ce_adm_bap_sram_perr_detail; /* 0x000158 */
67 u64 ce_adm_ce_sram_perr_detail; /* 0x000160 */
68 u64 ce_adm_ce_credit_oflow_detail; /* 0x000168 */
69 u64 ce_adm_tx_link_idle_max_timer; /* 0x000170 */
70 u64 ce_adm_pcie_debug_sel; /* 0x000178 */
71 u64 ce_pad_000180[16]; /* 0x000180 -- 0x0001F8 */
72
73 u64 ce_adm_pcie_debug_sel_top; /* 0x000200 */
74 u64 ce_adm_pcie_debug_lat_sel_lo_top; /* 0x000208 */
75 u64 ce_adm_pcie_debug_lat_sel_hi_top; /* 0x000210 */
76 u64 ce_adm_pcie_debug_trig_sel_top; /* 0x000218 */
77 u64 ce_adm_pcie_debug_trig_lat_sel_lo_top; /* 0x000220 */
78 u64 ce_adm_pcie_debug_trig_lat_sel_hi_top; /* 0x000228 */
79 u64 ce_adm_pcie_trig_compare_top; /* 0x000230 */
80 u64 ce_adm_pcie_trig_compare_en_top; /* 0x000238 */
81 u64 ce_adm_ssp_debug_sel_top; /* 0x000240 */
82 u64 ce_adm_ssp_debug_lat_sel_lo_top; /* 0x000248 */
83 u64 ce_adm_ssp_debug_lat_sel_hi_top; /* 0x000250 */
84 u64 ce_adm_ssp_debug_trig_sel_top; /* 0x000258 */
85 u64 ce_adm_ssp_debug_trig_lat_sel_lo_top; /* 0x000260 */
86 u64 ce_adm_ssp_debug_trig_lat_sel_hi_top; /* 0x000268 */
87 u64 ce_adm_ssp_trig_compare_top; /* 0x000270 */
88 u64 ce_adm_ssp_trig_compare_en_top; /* 0x000278 */
89 u64 ce_pad_000280[48]; /* 0x000280 -- 0x0003F8 */
90
91 u64 ce_adm_bap_ctrl; /* 0x000400 */
92 u64 ce_pad_000408[127]; /* 0x000408 -- 0x0007F8 */
93
94 u64 ce_msg_buf_data63_0[35]; /* 0x000800 -- 0x000918 */
95 u64 ce_pad_000920[29]; /* 0x000920 -- 0x0009F8 */
96
97 u64 ce_msg_buf_data127_64[35]; /* 0x000A00 -- 0x000B18 */
98 u64 ce_pad_000B20[29]; /* 0x000B20 -- 0x000BF8 */
99
100 u64 ce_msg_buf_parity[35]; /* 0x000C00 -- 0x000D18 */
101 u64 ce_pad_000D20[29]; /* 0x000D20 -- 0x000DF8 */
102
103 u64 ce_pad_000E00[576]; /* 0x000E00 -- 0x001FF8 */
104
105 /*
106 * LSI : LSI's PCI Express Link Registers (Link#1 and Link#2)
107 * Link#1 MMRs at start at 0x002000, Link#2 MMRs at 0x003000
108 * NOTE: the comment offsets at far right: let 'z' = {2 or 3}
109 */
110 #define ce_lsi(link_num) ce_lsi[link_num-1]
111 struct ce_lsi_reg {
112 u64 ce_lsi_lpu_id; /* 0x00z000 */
113 u64 ce_lsi_rst; /* 0x00z008 */
114 u64 ce_lsi_dbg_stat; /* 0x00z010 */
115 u64 ce_lsi_dbg_cfg; /* 0x00z018 */
116 u64 ce_lsi_ltssm_ctrl; /* 0x00z020 */
117 u64 ce_lsi_lk_stat; /* 0x00z028 */
118 u64 ce_pad_00z030[2]; /* 0x00z030 -- 0x00z038 */
119 u64 ce_lsi_int_and_stat; /* 0x00z040 */
120 u64 ce_lsi_int_mask; /* 0x00z048 */
121 u64 ce_pad_00z050[22]; /* 0x00z050 -- 0x00z0F8 */
122 u64 ce_lsi_lk_perf_cnt_sel; /* 0x00z100 */
123 u64 ce_pad_00z108; /* 0x00z108 */
124 u64 ce_lsi_lk_perf_cnt_ctrl; /* 0x00z110 */
125 u64 ce_pad_00z118; /* 0x00z118 */
126 u64 ce_lsi_lk_perf_cnt1; /* 0x00z120 */
127 u64 ce_lsi_lk_perf_cnt1_test; /* 0x00z128 */
128 u64 ce_lsi_lk_perf_cnt2; /* 0x00z130 */
129 u64 ce_lsi_lk_perf_cnt2_test; /* 0x00z138 */
130 u64 ce_pad_00z140[24]; /* 0x00z140 -- 0x00z1F8 */
131 u64 ce_lsi_lk_lyr_cfg; /* 0x00z200 */
132 u64 ce_lsi_lk_lyr_status; /* 0x00z208 */
133 u64 ce_lsi_lk_lyr_int_stat; /* 0x00z210 */
134 u64 ce_lsi_lk_ly_int_stat_test; /* 0x00z218 */
135 u64 ce_lsi_lk_ly_int_stat_mask; /* 0x00z220 */
136 u64 ce_pad_00z228[3]; /* 0x00z228 -- 0x00z238 */
137 u64 ce_lsi_fc_upd_ctl; /* 0x00z240 */
138 u64 ce_pad_00z248[3]; /* 0x00z248 -- 0x00z258 */
139 u64 ce_lsi_flw_ctl_upd_to_timer; /* 0x00z260 */
140 u64 ce_lsi_flw_ctl_upd_timer0; /* 0x00z268 */
141 u64 ce_lsi_flw_ctl_upd_timer1; /* 0x00z270 */
142 u64 ce_pad_00z278[49]; /* 0x00z278 -- 0x00z3F8 */
143 u64 ce_lsi_freq_nak_lat_thrsh; /* 0x00z400 */
144 u64 ce_lsi_ack_nak_lat_tmr; /* 0x00z408 */
145 u64 ce_lsi_rply_tmr_thr; /* 0x00z410 */
146 u64 ce_lsi_rply_tmr; /* 0x00z418 */
147 u64 ce_lsi_rply_num_stat; /* 0x00z420 */
148 u64 ce_lsi_rty_buf_max_addr; /* 0x00z428 */
149 u64 ce_lsi_rty_fifo_ptr; /* 0x00z430 */
150 u64 ce_lsi_rty_fifo_rd_wr_ptr; /* 0x00z438 */
151 u64 ce_lsi_rty_fifo_cred; /* 0x00z440 */
152 u64 ce_lsi_seq_cnt; /* 0x00z448 */
153 u64 ce_lsi_ack_sent_seq_num; /* 0x00z450 */
154 u64 ce_lsi_seq_cnt_fifo_max_addr; /* 0x00z458 */
155 u64 ce_lsi_seq_cnt_fifo_ptr; /* 0x00z460 */
156 u64 ce_lsi_seq_cnt_rd_wr_ptr; /* 0x00z468 */
157 u64 ce_lsi_tx_lk_ts_ctl; /* 0x00z470 */
158 u64 ce_pad_00z478; /* 0x00z478 */
159 u64 ce_lsi_mem_addr_ctl; /* 0x00z480 */
160 u64 ce_lsi_mem_d_ld0; /* 0x00z488 */
161 u64 ce_lsi_mem_d_ld1; /* 0x00z490 */
162 u64 ce_lsi_mem_d_ld2; /* 0x00z498 */
163 u64 ce_lsi_mem_d_ld3; /* 0x00z4A0 */
164 u64 ce_lsi_mem_d_ld4; /* 0x00z4A8 */
165 u64 ce_pad_00z4B0[2]; /* 0x00z4B0 -- 0x00z4B8 */
166 u64 ce_lsi_rty_d_cnt; /* 0x00z4C0 */
167 u64 ce_lsi_seq_buf_cnt; /* 0x00z4C8 */
168 u64 ce_lsi_seq_buf_bt_d; /* 0x00z4D0 */
169 u64 ce_pad_00z4D8; /* 0x00z4D8 */
170 u64 ce_lsi_ack_lat_thr; /* 0x00z4E0 */
171 u64 ce_pad_00z4E8[3]; /* 0x00z4E8 -- 0x00z4F8 */
172 u64 ce_lsi_nxt_rcv_seq_1_cntr; /* 0x00z500 */
173 u64 ce_lsi_unsp_dllp_rcvd; /* 0x00z508 */
174 u64 ce_lsi_rcv_lk_ts_ctl; /* 0x00z510 */
175 u64 ce_pad_00z518[29]; /* 0x00z518 -- 0x00z5F8 */
176 u64 ce_lsi_phy_lyr_cfg; /* 0x00z600 */
177 u64 ce_pad_00z608; /* 0x00z608 */
178 u64 ce_lsi_phy_lyr_int_stat; /* 0x00z610 */
179 u64 ce_lsi_phy_lyr_int_stat_test; /* 0x00z618 */
180 u64 ce_lsi_phy_lyr_int_mask; /* 0x00z620 */
181 u64 ce_pad_00z628[11]; /* 0x00z628 -- 0x00z678 */
182 u64 ce_lsi_rcv_phy_cfg; /* 0x00z680 */
183 u64 ce_lsi_rcv_phy_stat1; /* 0x00z688 */
184 u64 ce_lsi_rcv_phy_stat2; /* 0x00z690 */
185 u64 ce_lsi_rcv_phy_stat3; /* 0x00z698 */
186 u64 ce_lsi_rcv_phy_int_stat; /* 0x00z6A0 */
187 u64 ce_lsi_rcv_phy_int_stat_test; /* 0x00z6A8 */
188 u64 ce_lsi_rcv_phy_int_mask; /* 0x00z6B0 */
189 u64 ce_pad_00z6B8[9]; /* 0x00z6B8 -- 0x00z6F8 */
190 u64 ce_lsi_tx_phy_cfg; /* 0x00z700 */
191 u64 ce_lsi_tx_phy_stat; /* 0x00z708 */
192 u64 ce_lsi_tx_phy_int_stat; /* 0x00z710 */
193 u64 ce_lsi_tx_phy_int_stat_test; /* 0x00z718 */
194 u64 ce_lsi_tx_phy_int_mask; /* 0x00z720 */
195 u64 ce_lsi_tx_phy_stat2; /* 0x00z728 */
196 u64 ce_pad_00z730[10]; /* 0x00z730 -- 0x00z77F */
197 u64 ce_lsi_ltssm_cfg1; /* 0x00z780 */
198 u64 ce_lsi_ltssm_cfg2; /* 0x00z788 */
199 u64 ce_lsi_ltssm_cfg3; /* 0x00z790 */
200 u64 ce_lsi_ltssm_cfg4; /* 0x00z798 */
201 u64 ce_lsi_ltssm_cfg5; /* 0x00z7A0 */
202 u64 ce_lsi_ltssm_stat1; /* 0x00z7A8 */
203 u64 ce_lsi_ltssm_stat2; /* 0x00z7B0 */
204 u64 ce_lsi_ltssm_int_stat; /* 0x00z7B8 */
205 u64 ce_lsi_ltssm_int_stat_test; /* 0x00z7C0 */
206 u64 ce_lsi_ltssm_int_mask; /* 0x00z7C8 */
207 u64 ce_lsi_ltssm_stat_wr_en; /* 0x00z7D0 */
208 u64 ce_pad_00z7D8[5]; /* 0x00z7D8 -- 0x00z7F8 */
209 u64 ce_lsi_gb_cfg1; /* 0x00z800 */
210 u64 ce_lsi_gb_cfg2; /* 0x00z808 */
211 u64 ce_lsi_gb_cfg3; /* 0x00z810 */
212 u64 ce_lsi_gb_cfg4; /* 0x00z818 */
213 u64 ce_lsi_gb_stat; /* 0x00z820 */
214 u64 ce_lsi_gb_int_stat; /* 0x00z828 */
215 u64 ce_lsi_gb_int_stat_test; /* 0x00z830 */
216 u64 ce_lsi_gb_int_mask; /* 0x00z838 */
217 u64 ce_lsi_gb_pwr_dn1; /* 0x00z840 */
218 u64 ce_lsi_gb_pwr_dn2; /* 0x00z848 */
219 u64 ce_pad_00z850[246]; /* 0x00z850 -- 0x00zFF8 */
220 } ce_lsi[2];
221
222 u64 ce_pad_004000[10]; /* 0x004000 -- 0x004048 */
223
224 /*
225 * CRM: Coretalk Receive Module Registers
226 */
227 u64 ce_crm_debug_mux; /* 0x004050 */
228 u64 ce_pad_004058; /* 0x004058 */
229 u64 ce_crm_ssp_err_cmd_wrd; /* 0x004060 */
230 u64 ce_crm_ssp_err_addr; /* 0x004068 */
231 u64 ce_crm_ssp_err_syn; /* 0x004070 */
232
233 u64 ce_pad_004078[499]; /* 0x004078 -- 0x005008 */
234
235 /*
236 * CXM: Coretalk Xmit Module Registers
237 */
238 u64 ce_cxm_dyn_credit_status; /* 0x005010 */
239 u64 ce_cxm_last_credit_status; /* 0x005018 */
240 u64 ce_cxm_credit_limit; /* 0x005020 */
241 u64 ce_cxm_force_credit; /* 0x005028 */
242 u64 ce_cxm_disable_bypass; /* 0x005030 */
243 u64 ce_pad_005038[3]; /* 0x005038 -- 0x005048 */
244 u64 ce_cxm_debug_mux; /* 0x005050 */
245
246 u64 ce_pad_005058[501]; /* 0x005058 -- 0x005FF8 */
247
248 /*
249 * DTL: Downstream Transaction Layer Regs (Link#1 and Link#2)
250 * DTL: Link#1 MMRs at start at 0x006000, Link#2 MMRs at 0x008000
251 * DTL: the comment offsets at far right: let 'y' = {6 or 8}
252 *
253 * UTL: Downstream Transaction Layer Regs (Link#1 and Link#2)
254 * UTL: Link#1 MMRs at start at 0x007000, Link#2 MMRs at 0x009000
255 * UTL: the comment offsets at far right: let 'z' = {7 or 9}
256 */
257 #define ce_dtl(link_num) ce_dtl_utl[link_num-1]
258 #define ce_utl(link_num) ce_dtl_utl[link_num-1]
259 struct ce_dtl_utl_reg {
260 /* DTL */
261 u64 ce_dtl_dtdr_credit_limit; /* 0x00y000 */
262 u64 ce_dtl_dtdr_credit_force; /* 0x00y008 */
263 u64 ce_dtl_dyn_credit_status; /* 0x00y010 */
264 u64 ce_dtl_dtl_last_credit_stat; /* 0x00y018 */
265 u64 ce_dtl_dtl_ctrl; /* 0x00y020 */
266 u64 ce_pad_00y028[5]; /* 0x00y028 -- 0x00y048 */
267 u64 ce_dtl_debug_sel; /* 0x00y050 */
268 u64 ce_pad_00y058[501]; /* 0x00y058 -- 0x00yFF8 */
269
270 /* UTL */
271 u64 ce_utl_utl_ctrl; /* 0x00z000 */
272 u64 ce_utl_debug_sel; /* 0x00z008 */
273 u64 ce_pad_00z010[510]; /* 0x00z010 -- 0x00zFF8 */
274 } ce_dtl_utl[2];
275
276 u64 ce_pad_00A000[514]; /* 0x00A000 -- 0x00B008 */
277
278 /*
279 * URE: Upstream Request Engine
280 */
281 u64 ce_ure_dyn_credit_status; /* 0x00B010 */
282 u64 ce_ure_last_credit_status; /* 0x00B018 */
283 u64 ce_ure_credit_limit; /* 0x00B020 */
284 u64 ce_pad_00B028; /* 0x00B028 */
285 u64 ce_ure_control; /* 0x00B030 */
286 u64 ce_ure_status; /* 0x00B038 */
287 u64 ce_pad_00B040[2]; /* 0x00B040 -- 0x00B048 */
288 u64 ce_ure_debug_sel; /* 0x00B050 */
289 u64 ce_ure_pcie_debug_sel; /* 0x00B058 */
290 u64 ce_ure_ssp_err_cmd_wrd; /* 0x00B060 */
291 u64 ce_ure_ssp_err_addr; /* 0x00B068 */
292 u64 ce_ure_page_map; /* 0x00B070 */
293 u64 ce_ure_dir_map[TIOCE_NUM_PORTS]; /* 0x00B078 */
294 u64 ce_ure_pipe_sel1; /* 0x00B088 */
295 u64 ce_ure_pipe_mask1; /* 0x00B090 */
296 u64 ce_ure_pipe_sel2; /* 0x00B098 */
297 u64 ce_ure_pipe_mask2; /* 0x00B0A0 */
298 u64 ce_ure_pcie1_credits_sent; /* 0x00B0A8 */
299 u64 ce_ure_pcie1_credits_used; /* 0x00B0B0 */
300 u64 ce_ure_pcie1_credit_limit; /* 0x00B0B8 */
301 u64 ce_ure_pcie2_credits_sent; /* 0x00B0C0 */
302 u64 ce_ure_pcie2_credits_used; /* 0x00B0C8 */
303 u64 ce_ure_pcie2_credit_limit; /* 0x00B0D0 */
304 u64 ce_ure_pcie_force_credit; /* 0x00B0D8 */
305 u64 ce_ure_rd_tnum_val; /* 0x00B0E0 */
306 u64 ce_ure_rd_tnum_rsp_rcvd; /* 0x00B0E8 */
307 u64 ce_ure_rd_tnum_esent_timer; /* 0x00B0F0 */
308 u64 ce_ure_rd_tnum_error; /* 0x00B0F8 */
309 u64 ce_ure_rd_tnum_first_cl; /* 0x00B100 */
310 u64 ce_ure_rd_tnum_link_buf; /* 0x00B108 */
311 u64 ce_ure_wr_tnum_val; /* 0x00B110 */
312 u64 ce_ure_sram_err_addr0; /* 0x00B118 */
313 u64 ce_ure_sram_err_addr1; /* 0x00B120 */
314 u64 ce_ure_sram_err_addr2; /* 0x00B128 */
315 u64 ce_ure_sram_rd_addr0; /* 0x00B130 */
316 u64 ce_ure_sram_rd_addr1; /* 0x00B138 */
317 u64 ce_ure_sram_rd_addr2; /* 0x00B140 */
318 u64 ce_ure_sram_wr_addr0; /* 0x00B148 */
319 u64 ce_ure_sram_wr_addr1; /* 0x00B150 */
320 u64 ce_ure_sram_wr_addr2; /* 0x00B158 */
321 u64 ce_ure_buf_flush10; /* 0x00B160 */
322 u64 ce_ure_buf_flush11; /* 0x00B168 */
323 u64 ce_ure_buf_flush12; /* 0x00B170 */
324 u64 ce_ure_buf_flush13; /* 0x00B178 */
325 u64 ce_ure_buf_flush20; /* 0x00B180 */
326 u64 ce_ure_buf_flush21; /* 0x00B188 */
327 u64 ce_ure_buf_flush22; /* 0x00B190 */
328 u64 ce_ure_buf_flush23; /* 0x00B198 */
329 u64 ce_ure_pcie_control1; /* 0x00B1A0 */
330 u64 ce_ure_pcie_control2; /* 0x00B1A8 */
331
332 u64 ce_pad_00B1B0[458]; /* 0x00B1B0 -- 0x00BFF8 */
333
334 /* Upstream Data Buffer, Port1 */
335 struct ce_ure_maint_ups_dat1_data {
336 u64 data63_0[512]; /* 0x00C000 -- 0x00CFF8 */
337 u64 data127_64[512]; /* 0x00D000 -- 0x00DFF8 */
338 u64 parity[512]; /* 0x00E000 -- 0x00EFF8 */
339 } ce_ure_maint_ups_dat1;
340
341 /* Upstream Header Buffer, Port1 */
342 struct ce_ure_maint_ups_hdr1_data {
343 u64 data63_0[512]; /* 0x00F000 -- 0x00FFF8 */
344 u64 data127_64[512]; /* 0x010000 -- 0x010FF8 */
345 u64 parity[512]; /* 0x011000 -- 0x011FF8 */
346 } ce_ure_maint_ups_hdr1;
347
348 /* Upstream Data Buffer, Port2 */
349 struct ce_ure_maint_ups_dat2_data {
350 u64 data63_0[512]; /* 0x012000 -- 0x012FF8 */
351 u64 data127_64[512]; /* 0x013000 -- 0x013FF8 */
352 u64 parity[512]; /* 0x014000 -- 0x014FF8 */
353 } ce_ure_maint_ups_dat2;
354
355 /* Upstream Header Buffer, Port2 */
356 struct ce_ure_maint_ups_hdr2_data {
357 u64 data63_0[512]; /* 0x015000 -- 0x015FF8 */
358 u64 data127_64[512]; /* 0x016000 -- 0x016FF8 */
359 u64 parity[512]; /* 0x017000 -- 0x017FF8 */
360 } ce_ure_maint_ups_hdr2;
361
362 /* Downstream Data Buffer */
363 struct ce_ure_maint_dns_dat_data {
364 u64 data63_0[512]; /* 0x018000 -- 0x018FF8 */
365 u64 data127_64[512]; /* 0x019000 -- 0x019FF8 */
366 u64 parity[512]; /* 0x01A000 -- 0x01AFF8 */
367 } ce_ure_maint_dns_dat;
368
369 /* Downstream Header Buffer */
370 struct ce_ure_maint_dns_hdr_data {
371 u64 data31_0[64]; /* 0x01B000 -- 0x01B1F8 */
372 u64 data95_32[64]; /* 0x01B200 -- 0x01B3F8 */
373 u64 parity[64]; /* 0x01B400 -- 0x01B5F8 */
374 } ce_ure_maint_dns_hdr;
375
376 /* RCI Buffer Data */
377 struct ce_ure_maint_rci_data {
378 u64 data41_0[64]; /* 0x01B600 -- 0x01B7F8 */
379 u64 data69_42[64]; /* 0x01B800 -- 0x01B9F8 */
380 } ce_ure_maint_rci;
381
382 /* Response Queue */
383 u64 ce_ure_maint_rspq[64]; /* 0x01BA00 -- 0x01BBF8 */
384
385 u64 ce_pad_01C000[4224]; /* 0x01BC00 -- 0x023FF8 */
386
387 /* Admin Build-a-Packet Buffer */
388 struct ce_adm_maint_bap_buf_data {
389 u64 data63_0[258]; /* 0x024000 -- 0x024808 */
390 u64 data127_64[258]; /* 0x024810 -- 0x025018 */
391 u64 parity[258]; /* 0x025020 -- 0x025828 */
392 } ce_adm_maint_bap_buf;
393
394 u64 ce_pad_025830[5370]; /* 0x025830 -- 0x02FFF8 */
395
396 /* URE: 40bit PMU ATE Buffer */ /* 0x030000 -- 0x037FF8 */
397 u64 ce_ure_ate40[TIOCE_NUM_M40_ATES];
398
399 /* URE: 32/40bit PMU ATE Buffer */ /* 0x038000 -- 0x03BFF8 */
400 u64 ce_ure_ate3240[TIOCE_NUM_M3240_ATES];
401
402 u64 ce_pad_03C000[2050]; /* 0x03C000 -- 0x040008 */
403
404 /*
405 * DRE: Down Stream Request Engine
406 */
407 u64 ce_dre_dyn_credit_status1; /* 0x040010 */
408 u64 ce_dre_dyn_credit_status2; /* 0x040018 */
409 u64 ce_dre_last_credit_status1; /* 0x040020 */
410 u64 ce_dre_last_credit_status2; /* 0x040028 */
411 u64 ce_dre_credit_limit1; /* 0x040030 */
412 u64 ce_dre_credit_limit2; /* 0x040038 */
413 u64 ce_dre_force_credit1; /* 0x040040 */
414 u64 ce_dre_force_credit2; /* 0x040048 */
415 u64 ce_dre_debug_mux1; /* 0x040050 */
416 u64 ce_dre_debug_mux2; /* 0x040058 */
417 u64 ce_dre_ssp_err_cmd_wrd; /* 0x040060 */
418 u64 ce_dre_ssp_err_addr; /* 0x040068 */
419 u64 ce_dre_comp_err_cmd_wrd; /* 0x040070 */
420 u64 ce_dre_comp_err_addr; /* 0x040078 */
421 u64 ce_dre_req_status; /* 0x040080 */
422 u64 ce_dre_config1; /* 0x040088 */
423 u64 ce_dre_config2; /* 0x040090 */
424 u64 ce_dre_config_req_status; /* 0x040098 */
425 u64 ce_pad_0400A0[12]; /* 0x0400A0 -- 0x0400F8 */
426 u64 ce_dre_dyn_fifo; /* 0x040100 */
427 u64 ce_pad_040108[3]; /* 0x040108 -- 0x040118 */
428 u64 ce_dre_last_fifo; /* 0x040120 */
429
430 u64 ce_pad_040128[27]; /* 0x040128 -- 0x0401F8 */
431
432 /* DRE Downstream Head Queue */
433 struct ce_dre_maint_ds_head_queue {
434 u64 data63_0[32]; /* 0x040200 -- 0x0402F8 */
435 u64 data127_64[32]; /* 0x040300 -- 0x0403F8 */
436 u64 parity[32]; /* 0x040400 -- 0x0404F8 */
437 } ce_dre_maint_ds_head_q;
438
439 u64 ce_pad_040500[352]; /* 0x040500 -- 0x040FF8 */
440
441 /* DRE Downstream Data Queue */
442 struct ce_dre_maint_ds_data_queue {
443 u64 data63_0[256]; /* 0x041000 -- 0x0417F8 */
444 u64 ce_pad_041800[256]; /* 0x041800 -- 0x041FF8 */
445 u64 data127_64[256]; /* 0x042000 -- 0x0427F8 */
446 u64 ce_pad_042800[256]; /* 0x042800 -- 0x042FF8 */
447 u64 parity[256]; /* 0x043000 -- 0x0437F8 */
448 u64 ce_pad_043800[256]; /* 0x043800 -- 0x043FF8 */
449 } ce_dre_maint_ds_data_q;
450
451 /* DRE URE Upstream Response Queue */
452 struct ce_dre_maint_ure_us_rsp_queue {
453 u64 data63_0[8]; /* 0x044000 -- 0x044038 */
454 u64 ce_pad_044040[24]; /* 0x044040 -- 0x0440F8 */
455 u64 data127_64[8]; /* 0x044100 -- 0x044138 */
456 u64 ce_pad_044140[24]; /* 0x044140 -- 0x0441F8 */
457 u64 parity[8]; /* 0x044200 -- 0x044238 */
458 u64 ce_pad_044240[24]; /* 0x044240 -- 0x0442F8 */
459 } ce_dre_maint_ure_us_rsp_q;
460
461 u64 ce_dre_maint_us_wrt_rsp[32];/* 0x044300 -- 0x0443F8 */
462
463 u64 ce_end_of_struct; /* 0x044400 */
464} tioce_t;
465
466/* ce_lsiX_gb_cfg1 register bit masks & shifts */
467#define CE_LSI_GB_CFG1_RXL0S_THS_SHFT 0
468#define CE_LSI_GB_CFG1_RXL0S_THS_MASK (0xffULL << 0)
469#define CE_LSI_GB_CFG1_RXL0S_SMP_SHFT 8
470#define CE_LSI_GB_CFG1_RXL0S_SMP_MASK (0xfULL << 8);
471#define CE_LSI_GB_CFG1_RXL0S_ADJ_SHFT 12
472#define CE_LSI_GB_CFG1_RXL0S_ADJ_MASK (0x7ULL << 12)
473#define CE_LSI_GB_CFG1_RXL0S_FLT_SHFT 15
474#define CE_LSI_GB_CFG1_RXL0S_FLT_MASK (0x1ULL << 15)
475#define CE_LSI_GB_CFG1_LPBK_SEL_SHFT 16
476#define CE_LSI_GB_CFG1_LPBK_SEL_MASK (0x3ULL << 16)
477#define CE_LSI_GB_CFG1_LPBK_EN_SHFT 18
478#define CE_LSI_GB_CFG1_LPBK_EN_MASK (0x1ULL << 18)
479#define CE_LSI_GB_CFG1_RVRS_LB_SHFT 19
480#define CE_LSI_GB_CFG1_RVRS_LB_MASK (0x1ULL << 19)
481#define CE_LSI_GB_CFG1_RVRS_CLK_SHFT 20
482#define CE_LSI_GB_CFG1_RVRS_CLK_MASK (0x3ULL << 20)
483#define CE_LSI_GB_CFG1_SLF_TS_SHFT 24
484#define CE_LSI_GB_CFG1_SLF_TS_MASK (0xfULL << 24)
485
486/* ce_adm_int_mask/ce_adm_int_status register bit defines */
487#define CE_ADM_INT_CE_ERROR_SHFT 0
488#define CE_ADM_INT_LSI1_IP_ERROR_SHFT 1
489#define CE_ADM_INT_LSI2_IP_ERROR_SHFT 2
490#define CE_ADM_INT_PCIE_ERROR_SHFT 3
491#define CE_ADM_INT_PORT1_HOTPLUG_EVENT_SHFT 4
492#define CE_ADM_INT_PORT2_HOTPLUG_EVENT_SHFT 5
493#define CE_ADM_INT_PCIE_PORT1_DEV_A_SHFT 6
494#define CE_ADM_INT_PCIE_PORT1_DEV_B_SHFT 7
495#define CE_ADM_INT_PCIE_PORT1_DEV_C_SHFT 8
496#define CE_ADM_INT_PCIE_PORT1_DEV_D_SHFT 9
497#define CE_ADM_INT_PCIE_PORT2_DEV_A_SHFT 10
498#define CE_ADM_INT_PCIE_PORT2_DEV_B_SHFT 11
499#define CE_ADM_INT_PCIE_PORT2_DEV_C_SHFT 12
500#define CE_ADM_INT_PCIE_PORT2_DEV_D_SHFT 13
501#define CE_ADM_INT_PCIE_MSG_SHFT 14 /*see int_dest_14*/
502#define CE_ADM_INT_PCIE_MSG_SLOT_0_SHFT 14
503#define CE_ADM_INT_PCIE_MSG_SLOT_1_SHFT 15
504#define CE_ADM_INT_PCIE_MSG_SLOT_2_SHFT 16
505#define CE_ADM_INT_PCIE_MSG_SLOT_3_SHFT 17
506#define CE_ADM_INT_PORT1_PM_PME_MSG_SHFT 22
507#define CE_ADM_INT_PORT2_PM_PME_MSG_SHFT 23
508
509/* ce_adm_force_int register bit defines */
510#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_A_SHFT 0
511#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_B_SHFT 1
512#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_C_SHFT 2
513#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_D_SHFT 3
514#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_A_SHFT 4
515#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_B_SHFT 5
516#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_C_SHFT 6
517#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_D_SHFT 7
518#define CE_ADM_FORCE_INT_ALWAYS_SHFT 8
519
520/* ce_adm_int_dest register bit masks & shifts */
521#define INTR_VECTOR_SHFT 56
522
523/* ce_adm_error_mask and ce_adm_error_summary register bit masks */
524#define CE_ADM_ERR_CRM_SSP_REQ_INVALID (0x1ULL << 0)
525#define CE_ADM_ERR_SSP_REQ_HEADER (0x1ULL << 1)
526#define CE_ADM_ERR_SSP_RSP_HEADER (0x1ULL << 2)
527#define CE_ADM_ERR_SSP_PROTOCOL_ERROR (0x1ULL << 3)
528#define CE_ADM_ERR_SSP_SBE (0x1ULL << 4)
529#define CE_ADM_ERR_SSP_MBE (0x1ULL << 5)
530#define CE_ADM_ERR_CXM_CREDIT_OFLOW (0x1ULL << 6)
531#define CE_ADM_ERR_DRE_SSP_REQ_INVAL (0x1ULL << 7)
532#define CE_ADM_ERR_SSP_REQ_LONG (0x1ULL << 8)
533#define CE_ADM_ERR_SSP_REQ_OFLOW (0x1ULL << 9)
534#define CE_ADM_ERR_SSP_REQ_SHORT (0x1ULL << 10)
535#define CE_ADM_ERR_SSP_REQ_SIDEBAND (0x1ULL << 11)
536#define CE_ADM_ERR_SSP_REQ_ADDR_ERR (0x1ULL << 12)
537#define CE_ADM_ERR_SSP_REQ_BAD_BE (0x1ULL << 13)
538#define CE_ADM_ERR_PCIE_COMPL_TIMEOUT (0x1ULL << 14)
539#define CE_ADM_ERR_PCIE_UNEXP_COMPL (0x1ULL << 15)
540#define CE_ADM_ERR_PCIE_ERR_COMPL (0x1ULL << 16)
541#define CE_ADM_ERR_DRE_CREDIT_OFLOW (0x1ULL << 17)
542#define CE_ADM_ERR_DRE_SRAM_PE (0x1ULL << 18)
543#define CE_ADM_ERR_SSP_RSP_INVALID (0x1ULL << 19)
544#define CE_ADM_ERR_SSP_RSP_LONG (0x1ULL << 20)
545#define CE_ADM_ERR_SSP_RSP_SHORT (0x1ULL << 21)
546#define CE_ADM_ERR_SSP_RSP_SIDEBAND (0x1ULL << 22)
547#define CE_ADM_ERR_URE_SSP_RSP_UNEXP (0x1ULL << 23)
548#define CE_ADM_ERR_URE_SSP_WR_REQ_TIMEOUT (0x1ULL << 24)
549#define CE_ADM_ERR_URE_SSP_RD_REQ_TIMEOUT (0x1ULL << 25)
550#define CE_ADM_ERR_URE_ATE3240_PAGE_FAULT (0x1ULL << 26)
551#define CE_ADM_ERR_URE_ATE40_PAGE_FAULT (0x1ULL << 27)
552#define CE_ADM_ERR_URE_CREDIT_OFLOW (0x1ULL << 28)
553#define CE_ADM_ERR_URE_SRAM_PE (0x1ULL << 29)
554#define CE_ADM_ERR_ADM_SSP_RSP_UNEXP (0x1ULL << 30)
555#define CE_ADM_ERR_ADM_SSP_REQ_TIMEOUT (0x1ULL << 31)
556#define CE_ADM_ERR_MMR_ACCESS_ERROR (0x1ULL << 32)
557#define CE_ADM_ERR_MMR_ADDR_ERROR (0x1ULL << 33)
558#define CE_ADM_ERR_ADM_CREDIT_OFLOW (0x1ULL << 34)
559#define CE_ADM_ERR_ADM_SRAM_PE (0x1ULL << 35)
560#define CE_ADM_ERR_DTL1_MIN_PDATA_CREDIT_ERR (0x1ULL << 36)
561#define CE_ADM_ERR_DTL1_INF_COMPL_CRED_UPDT_ERR (0x1ULL << 37)
562#define CE_ADM_ERR_DTL1_INF_POSTED_CRED_UPDT_ERR (0x1ULL << 38)
563#define CE_ADM_ERR_DTL1_INF_NPOSTED_CRED_UPDT_ERR (0x1ULL << 39)
564#define CE_ADM_ERR_DTL1_COMP_HD_CRED_MAX_ERR (0x1ULL << 40)
565#define CE_ADM_ERR_DTL1_COMP_D_CRED_MAX_ERR (0x1ULL << 41)
566#define CE_ADM_ERR_DTL1_NPOSTED_HD_CRED_MAX_ERR (0x1ULL << 42)
567#define CE_ADM_ERR_DTL1_NPOSTED_D_CRED_MAX_ERR (0x1ULL << 43)
568#define CE_ADM_ERR_DTL1_POSTED_HD_CRED_MAX_ERR (0x1ULL << 44)
569#define CE_ADM_ERR_DTL1_POSTED_D_CRED_MAX_ERR (0x1ULL << 45)
570#define CE_ADM_ERR_DTL2_MIN_PDATA_CREDIT_ERR (0x1ULL << 46)
571#define CE_ADM_ERR_DTL2_INF_COMPL_CRED_UPDT_ERR (0x1ULL << 47)
572#define CE_ADM_ERR_DTL2_INF_POSTED_CRED_UPDT_ERR (0x1ULL << 48)
573#define CE_ADM_ERR_DTL2_INF_NPOSTED_CRED_UPDT_ERR (0x1ULL << 49)
574#define CE_ADM_ERR_DTL2_COMP_HD_CRED_MAX_ERR (0x1ULL << 50)
575#define CE_ADM_ERR_DTL2_COMP_D_CRED_MAX_ERR (0x1ULL << 51)
576#define CE_ADM_ERR_DTL2_NPOSTED_HD_CRED_MAX_ERR (0x1ULL << 52)
577#define CE_ADM_ERR_DTL2_NPOSTED_D_CRED_MAX_ERR (0x1ULL << 53)
578#define CE_ADM_ERR_DTL2_POSTED_HD_CRED_MAX_ERR (0x1ULL << 54)
579#define CE_ADM_ERR_DTL2_POSTED_D_CRED_MAX_ERR (0x1ULL << 55)
580#define CE_ADM_ERR_PORT1_PCIE_COR_ERR (0x1ULL << 56)
581#define CE_ADM_ERR_PORT1_PCIE_NFAT_ERR (0x1ULL << 57)
582#define CE_ADM_ERR_PORT1_PCIE_FAT_ERR (0x1ULL << 58)
583#define CE_ADM_ERR_PORT2_PCIE_COR_ERR (0x1ULL << 59)
584#define CE_ADM_ERR_PORT2_PCIE_NFAT_ERR (0x1ULL << 60)
585#define CE_ADM_ERR_PORT2_PCIE_FAT_ERR (0x1ULL << 61)
586
587/* ce_adm_ure_ups_buf_barrier_flush register bit masks and shifts */
588#define FLUSH_SEL_PORT1_PIPE0_SHFT 0
589#define FLUSH_SEL_PORT1_PIPE1_SHFT 4
590#define FLUSH_SEL_PORT1_PIPE2_SHFT 8
591#define FLUSH_SEL_PORT1_PIPE3_SHFT 12
592#define FLUSH_SEL_PORT2_PIPE0_SHFT 16
593#define FLUSH_SEL_PORT2_PIPE1_SHFT 20
594#define FLUSH_SEL_PORT2_PIPE2_SHFT 24
595#define FLUSH_SEL_PORT2_PIPE3_SHFT 28
596
597/* ce_dre_config1 register bit masks and shifts */
598#define CE_DRE_RO_ENABLE (0x1ULL << 0)
599#define CE_DRE_DYN_RO_ENABLE (0x1ULL << 1)
600#define CE_DRE_SUP_CONFIG_COMP_ERROR (0x1ULL << 2)
601#define CE_DRE_SUP_IO_COMP_ERROR (0x1ULL << 3)
602#define CE_DRE_ADDR_MODE_SHFT 4
603
604/* ce_dre_config_req_status register bit masks */
605#define CE_DRE_LAST_CONFIG_COMPLETION (0x7ULL << 0)
606#define CE_DRE_DOWNSTREAM_CONFIG_ERROR (0x1ULL << 3)
607#define CE_DRE_CONFIG_COMPLETION_VALID (0x1ULL << 4)
608#define CE_DRE_CONFIG_REQUEST_ACTIVE (0x1ULL << 5)
609
610/* ce_ure_control register bit masks & shifts */
611#define CE_URE_RD_MRG_ENABLE (0x1ULL << 0)
612#define CE_URE_WRT_MRG_ENABLE1 (0x1ULL << 4)
613#define CE_URE_WRT_MRG_ENABLE2 (0x1ULL << 5)
614#define CE_URE_WRT_MRG_TIMER_SHFT 12
615#define CE_URE_WRT_MRG_TIMER_MASK (0x7FFULL << CE_URE_WRT_MRG_TIMER_SHFT)
616#define CE_URE_WRT_MRG_TIMER(x) (((u64)(x) << \
617 CE_URE_WRT_MRG_TIMER_SHFT) & \
618 CE_URE_WRT_MRG_TIMER_MASK)
619#define CE_URE_RSPQ_BYPASS_DISABLE (0x1ULL << 24)
620#define CE_URE_UPS_DAT1_PAR_DISABLE (0x1ULL << 32)
621#define CE_URE_UPS_HDR1_PAR_DISABLE (0x1ULL << 33)
622#define CE_URE_UPS_DAT2_PAR_DISABLE (0x1ULL << 34)
623#define CE_URE_UPS_HDR2_PAR_DISABLE (0x1ULL << 35)
624#define CE_URE_ATE_PAR_DISABLE (0x1ULL << 36)
625#define CE_URE_RCI_PAR_DISABLE (0x1ULL << 37)
626#define CE_URE_RSPQ_PAR_DISABLE (0x1ULL << 38)
627#define CE_URE_DNS_DAT_PAR_DISABLE (0x1ULL << 39)
628#define CE_URE_DNS_HDR_PAR_DISABLE (0x1ULL << 40)
629#define CE_URE_MALFORM_DISABLE (0x1ULL << 44)
630#define CE_URE_UNSUP_DISABLE (0x1ULL << 45)
631
632/* ce_ure_page_map register bit masks & shifts */
633#define CE_URE_ATE3240_ENABLE (0x1ULL << 0)
634#define CE_URE_ATE40_ENABLE (0x1ULL << 1)
635#define CE_URE_PAGESIZE_SHFT 4
636#define CE_URE_PAGESIZE_MASK (0x7ULL << CE_URE_PAGESIZE_SHFT)
637#define CE_URE_4K_PAGESIZE (0x0ULL << CE_URE_PAGESIZE_SHFT)
638#define CE_URE_16K_PAGESIZE (0x1ULL << CE_URE_PAGESIZE_SHFT)
639#define CE_URE_64K_PAGESIZE (0x2ULL << CE_URE_PAGESIZE_SHFT)
640#define CE_URE_128K_PAGESIZE (0x3ULL << CE_URE_PAGESIZE_SHFT)
641#define CE_URE_256K_PAGESIZE (0x4ULL << CE_URE_PAGESIZE_SHFT)
642
643/* ce_ure_pipe_sel register bit masks & shifts */
644#define PKT_TRAFIC_SHRT 16
645#define BUS_SRC_ID_SHFT 8
646#define DEV_SRC_ID_SHFT 3
647#define FNC_SRC_ID_SHFT 0
648#define CE_URE_TC_MASK (0x07ULL << PKT_TRAFIC_SHRT)
649#define CE_URE_BUS_MASK (0xFFULL << BUS_SRC_ID_SHFT)
650#define CE_URE_DEV_MASK (0x1FULL << DEV_SRC_ID_SHFT)
651#define CE_URE_FNC_MASK (0x07ULL << FNC_SRC_ID_SHFT)
652#define CE_URE_PIPE_BUS(b) (((u64)(b) << BUS_SRC_ID_SHFT) & \
653 CE_URE_BUS_MASK)
654#define CE_URE_PIPE_DEV(d) (((u64)(d) << DEV_SRC_ID_SHFT) & \
655 CE_URE_DEV_MASK)
656#define CE_URE_PIPE_FNC(f) (((u64)(f) << FNC_SRC_ID_SHFT) & \
657 CE_URE_FNC_MASK)
658
659#define CE_URE_SEL1_SHFT 0
660#define CE_URE_SEL2_SHFT 20
661#define CE_URE_SEL3_SHFT 40
662#define CE_URE_SEL1_MASK (0x7FFFFULL << CE_URE_SEL1_SHFT)
663#define CE_URE_SEL2_MASK (0x7FFFFULL << CE_URE_SEL2_SHFT)
664#define CE_URE_SEL3_MASK (0x7FFFFULL << CE_URE_SEL3_SHFT)
665
666
667/* ce_ure_pipe_mask register bit masks & shifts */
668#define CE_URE_MASK1_SHFT 0
669#define CE_URE_MASK2_SHFT 20
670#define CE_URE_MASK3_SHFT 40
671#define CE_URE_MASK1_MASK (0x7FFFFULL << CE_URE_MASK1_SHFT)
672#define CE_URE_MASK2_MASK (0x7FFFFULL << CE_URE_MASK2_SHFT)
673#define CE_URE_MASK3_MASK (0x7FFFFULL << CE_URE_MASK3_SHFT)
674
675
676/* ce_ure_pcie_control1 register bit masks & shifts */
677#define CE_URE_SI (0x1ULL << 0)
678#define CE_URE_ELAL_SHFT 4
679#define CE_URE_ELAL_MASK (0x7ULL << CE_URE_ELAL_SHFT)
680#define CE_URE_ELAL_SET(n) (((u64)(n) << CE_URE_ELAL_SHFT) & \
681 CE_URE_ELAL_MASK)
682#define CE_URE_ELAL1_SHFT 8
683#define CE_URE_ELAL1_MASK (0x7ULL << CE_URE_ELAL1_SHFT)
684#define CE_URE_ELAL1_SET(n) (((u64)(n) << CE_URE_ELAL1_SHFT) & \
685 CE_URE_ELAL1_MASK)
686#define CE_URE_SCC (0x1ULL << 12)
687#define CE_URE_PN1_SHFT 16
688#define CE_URE_PN1_MASK (0xFFULL << CE_URE_PN1_SHFT)
689#define CE_URE_PN2_SHFT 24
690#define CE_URE_PN2_MASK (0xFFULL << CE_URE_PN2_SHFT)
691#define CE_URE_PN1_SET(n) (((u64)(n) << CE_URE_PN1_SHFT) & \
692 CE_URE_PN1_MASK)
693#define CE_URE_PN2_SET(n) (((u64)(n) << CE_URE_PN2_SHFT) & \
694 CE_URE_PN2_MASK)
695
696/* ce_ure_pcie_control2 register bit masks & shifts */
697#define CE_URE_ABP (0x1ULL << 0)
698#define CE_URE_PCP (0x1ULL << 1)
699#define CE_URE_MSP (0x1ULL << 2)
700#define CE_URE_AIP (0x1ULL << 3)
701#define CE_URE_PIP (0x1ULL << 4)
702#define CE_URE_HPS (0x1ULL << 5)
703#define CE_URE_HPC (0x1ULL << 6)
704#define CE_URE_SPLV_SHFT 7
705#define CE_URE_SPLV_MASK (0xFFULL << CE_URE_SPLV_SHFT)
706#define CE_URE_SPLV_SET(n) (((u64)(n) << CE_URE_SPLV_SHFT) & \
707 CE_URE_SPLV_MASK)
708#define CE_URE_SPLS_SHFT 15
709#define CE_URE_SPLS_MASK (0x3ULL << CE_URE_SPLS_SHFT)
710#define CE_URE_SPLS_SET(n) (((u64)(n) << CE_URE_SPLS_SHFT) & \
711 CE_URE_SPLS_MASK)
712#define CE_URE_PSN1_SHFT 19
713#define CE_URE_PSN1_MASK (0x1FFFULL << CE_URE_PSN1_SHFT)
714#define CE_URE_PSN2_SHFT 32
715#define CE_URE_PSN2_MASK (0x1FFFULL << CE_URE_PSN2_SHFT)
716#define CE_URE_PSN1_SET(n) (((u64)(n) << CE_URE_PSN1_SHFT) & \
717 CE_URE_PSN1_MASK)
718#define CE_URE_PSN2_SET(n) (((u64)(n) << CE_URE_PSN2_SHFT) & \
719 CE_URE_PSN2_MASK)
720
721/*
722 * PIO address space ranges for CE
723 */
724
725/* Local CE Registers Space */
726#define CE_PIO_MMR 0x00000000
727#define CE_PIO_MMR_LEN 0x04000000
728
729/* PCI Compatible Config Space */
730#define CE_PIO_CONFIG_SPACE 0x04000000
731#define CE_PIO_CONFIG_SPACE_LEN 0x04000000
732
733/* PCI I/O Space Alias */
734#define CE_PIO_IO_SPACE_ALIAS 0x08000000
735#define CE_PIO_IO_SPACE_ALIAS_LEN 0x08000000
736
737/* PCI Enhanced Config Space */
738#define CE_PIO_E_CONFIG_SPACE 0x10000000
739#define CE_PIO_E_CONFIG_SPACE_LEN 0x10000000
740
741/* PCI I/O Space */
742#define CE_PIO_IO_SPACE 0x100000000
743#define CE_PIO_IO_SPACE_LEN 0x100000000
744
745/* PCI MEM Space */
746#define CE_PIO_MEM_SPACE 0x200000000
747#define CE_PIO_MEM_SPACE_LEN TIO_HWIN_SIZE
748
749
750/*
751 * CE PCI Enhanced Config Space shifts & masks
752 */
753#define CE_E_CONFIG_BUS_SHFT 20
754#define CE_E_CONFIG_BUS_MASK (0xFF << CE_E_CONFIG_BUS_SHFT)
755#define CE_E_CONFIG_DEVICE_SHFT 15
756#define CE_E_CONFIG_DEVICE_MASK (0x1F << CE_E_CONFIG_DEVICE_SHFT)
757#define CE_E_CONFIG_FUNC_SHFT 12
758#define CE_E_CONFIG_FUNC_MASK (0x7 << CE_E_CONFIG_FUNC_SHFT)
759
760#endif /* __ASM_IA64_SN_TIOCE_H__ */
diff --git a/include/asm-ia64/sn/tioce_provider.h b/include/asm-ia64/sn/tioce_provider.h
deleted file mode 100644
index 32c32f30b09..00000000000
--- a/include/asm-ia64/sn/tioce_provider.h
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved.
7 */
8
9#ifndef _ASM_IA64_SN_CE_PROVIDER_H
10#define _ASM_IA64_SN_CE_PROVIDER_H
11
12#include <asm/sn/pcibus_provider_defs.h>
13#include <asm/sn/tioce.h>
14
15/*
16 * Common TIOCE structure shared between the prom and kernel
17 *
18 * DO NOT CHANGE THIS STRUCT WITHOUT MAKING CORRESPONDING CHANGES TO THE
19 * PROM VERSION.
20 */
21struct tioce_common {
22 struct pcibus_bussoft ce_pcibus; /* common pciio header */
23
24 u32 ce_rev;
25 u64 ce_kernel_private;
26 u64 ce_prom_private;
27};
28
29struct tioce_kernel {
30 struct tioce_common *ce_common;
31 spinlock_t ce_lock;
32 struct list_head ce_dmamap_list;
33
34 u64 ce_ate40_shadow[TIOCE_NUM_M40_ATES];
35 u64 ce_ate3240_shadow[TIOCE_NUM_M3240_ATES];
36 u32 ce_ate3240_pagesize;
37
38 u8 ce_port1_secondary;
39
40 /* per-port resources */
41 struct {
42 int dirmap_refcnt;
43 u64 dirmap_shadow;
44 } ce_port[TIOCE_NUM_PORTS];
45};
46
47struct tioce_dmamap {
48 struct list_head ce_dmamap_list; /* headed by tioce_kernel */
49 u32 refcnt;
50
51 u64 nbytes; /* # bytes mapped */
52
53 u64 ct_start; /* coretalk start address */
54 u64 pci_start; /* bus start address */
55
56 u64 __iomem *ate_hw;/* hw ptr of first ate in map */
57 u64 *ate_shadow; /* shadow ptr of firat ate */
58 u16 ate_count; /* # ate's in the map */
59};
60
61extern int tioce_init_provider(void);
62
63#endif /* __ASM_IA64_SN_CE_PROVIDER_H */
diff --git a/include/asm-ia64/sn/tiocp.h b/include/asm-ia64/sn/tiocp.h
deleted file mode 100644
index e8ad0bb5b6c..00000000000
--- a/include/asm-ia64/sn/tiocp.h
+++ /dev/null
@@ -1,257 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003-2005 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_PCI_TIOCP_H
9#define _ASM_IA64_SN_PCI_TIOCP_H
10
11#define TIOCP_HOST_INTR_ADDR 0x003FFFFFFFFFFFFFUL
12#define TIOCP_PCI64_CMDTYPE_MEM (0x1ull << 60)
13#define TIOCP_PCI64_CMDTYPE_MSI (0x3ull << 60)
14
15
16/*****************************************************************************
17 *********************** TIOCP MMR structure mapping ***************************
18 *****************************************************************************/
19
20struct tiocp{
21
22 /* 0x000000-0x00FFFF -- Local Registers */
23
24 /* 0x000000-0x000057 -- (Legacy Widget Space) Configuration */
25 u64 cp_id; /* 0x000000 */
26 u64 cp_stat; /* 0x000008 */
27 u64 cp_err_upper; /* 0x000010 */
28 u64 cp_err_lower; /* 0x000018 */
29 #define cp_err cp_err_lower
30 u64 cp_control; /* 0x000020 */
31 u64 cp_req_timeout; /* 0x000028 */
32 u64 cp_intr_upper; /* 0x000030 */
33 u64 cp_intr_lower; /* 0x000038 */
34 #define cp_intr cp_intr_lower
35 u64 cp_err_cmdword; /* 0x000040 */
36 u64 _pad_000048; /* 0x000048 */
37 u64 cp_tflush; /* 0x000050 */
38
39 /* 0x000058-0x00007F -- Bridge-specific Configuration */
40 u64 cp_aux_err; /* 0x000058 */
41 u64 cp_resp_upper; /* 0x000060 */
42 u64 cp_resp_lower; /* 0x000068 */
43 #define cp_resp cp_resp_lower
44 u64 cp_tst_pin_ctrl; /* 0x000070 */
45 u64 cp_addr_lkerr; /* 0x000078 */
46
47 /* 0x000080-0x00008F -- PMU & MAP */
48 u64 cp_dir_map; /* 0x000080 */
49 u64 _pad_000088; /* 0x000088 */
50
51 /* 0x000090-0x00009F -- SSRAM */
52 u64 cp_map_fault; /* 0x000090 */
53 u64 _pad_000098; /* 0x000098 */
54
55 /* 0x0000A0-0x0000AF -- Arbitration */
56 u64 cp_arb; /* 0x0000A0 */
57 u64 _pad_0000A8; /* 0x0000A8 */
58
59 /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
60 u64 cp_ate_parity_err; /* 0x0000B0 */
61 u64 _pad_0000B8; /* 0x0000B8 */
62
63 /* 0x0000C0-0x0000FF -- PCI/GIO */
64 u64 cp_bus_timeout; /* 0x0000C0 */
65 u64 cp_pci_cfg; /* 0x0000C8 */
66 u64 cp_pci_err_upper; /* 0x0000D0 */
67 u64 cp_pci_err_lower; /* 0x0000D8 */
68 #define cp_pci_err cp_pci_err_lower
69 u64 _pad_0000E0[4]; /* 0x0000{E0..F8} */
70
71 /* 0x000100-0x0001FF -- Interrupt */
72 u64 cp_int_status; /* 0x000100 */
73 u64 cp_int_enable; /* 0x000108 */
74 u64 cp_int_rst_stat; /* 0x000110 */
75 u64 cp_int_mode; /* 0x000118 */
76 u64 cp_int_device; /* 0x000120 */
77 u64 cp_int_host_err; /* 0x000128 */
78 u64 cp_int_addr[8]; /* 0x0001{30,,,68} */
79 u64 cp_err_int_view; /* 0x000170 */
80 u64 cp_mult_int; /* 0x000178 */
81 u64 cp_force_always[8]; /* 0x0001{80,,,B8} */
82 u64 cp_force_pin[8]; /* 0x0001{C0,,,F8} */
83
84 /* 0x000200-0x000298 -- Device */
85 u64 cp_device[4]; /* 0x0002{00,,,18} */
86 u64 _pad_000220[4]; /* 0x0002{20,,,38} */
87 u64 cp_wr_req_buf[4]; /* 0x0002{40,,,58} */
88 u64 _pad_000260[4]; /* 0x0002{60,,,78} */
89 u64 cp_rrb_map[2]; /* 0x0002{80,,,88} */
90 #define cp_even_resp cp_rrb_map[0] /* 0x000280 */
91 #define cp_odd_resp cp_rrb_map[1] /* 0x000288 */
92 u64 cp_resp_status; /* 0x000290 */
93 u64 cp_resp_clear; /* 0x000298 */
94
95 u64 _pad_0002A0[12]; /* 0x0002{A0..F8} */
96
97 /* 0x000300-0x0003F8 -- Buffer Address Match Registers */
98 struct {
99 u64 upper; /* 0x0003{00,,,F0} */
100 u64 lower; /* 0x0003{08,,,F8} */
101 } cp_buf_addr_match[16];
102
103 /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
104 struct {
105 u64 flush_w_touch; /* 0x000{400,,,5C0} */
106 u64 flush_wo_touch; /* 0x000{408,,,5C8} */
107 u64 inflight; /* 0x000{410,,,5D0} */
108 u64 prefetch; /* 0x000{418,,,5D8} */
109 u64 total_pci_retry; /* 0x000{420,,,5E0} */
110 u64 max_pci_retry; /* 0x000{428,,,5E8} */
111 u64 max_latency; /* 0x000{430,,,5F0} */
112 u64 clear_all; /* 0x000{438,,,5F8} */
113 } cp_buf_count[8];
114
115
116 /* 0x000600-0x0009FF -- PCI/X registers */
117 u64 cp_pcix_bus_err_addr; /* 0x000600 */
118 u64 cp_pcix_bus_err_attr; /* 0x000608 */
119 u64 cp_pcix_bus_err_data; /* 0x000610 */
120 u64 cp_pcix_pio_split_addr; /* 0x000618 */
121 u64 cp_pcix_pio_split_attr; /* 0x000620 */
122 u64 cp_pcix_dma_req_err_attr; /* 0x000628 */
123 u64 cp_pcix_dma_req_err_addr; /* 0x000630 */
124 u64 cp_pcix_timeout; /* 0x000638 */
125
126 u64 _pad_000640[24]; /* 0x000{640,,,6F8} */
127
128 /* 0x000700-0x000737 -- Debug Registers */
129 u64 cp_ct_debug_ctl; /* 0x000700 */
130 u64 cp_br_debug_ctl; /* 0x000708 */
131 u64 cp_mux3_debug_ctl; /* 0x000710 */
132 u64 cp_mux4_debug_ctl; /* 0x000718 */
133 u64 cp_mux5_debug_ctl; /* 0x000720 */
134 u64 cp_mux6_debug_ctl; /* 0x000728 */
135 u64 cp_mux7_debug_ctl; /* 0x000730 */
136
137 u64 _pad_000738[89]; /* 0x000{738,,,9F8} */
138
139 /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
140 struct {
141 u64 cp_buf_addr; /* 0x000{A00,,,AF0} */
142 u64 cp_buf_attr; /* 0X000{A08,,,AF8} */
143 } cp_pcix_read_buf_64[16];
144
145 struct {
146 u64 cp_buf_addr; /* 0x000{B00,,,BE0} */
147 u64 cp_buf_attr; /* 0x000{B08,,,BE8} */
148 u64 cp_buf_valid; /* 0x000{B10,,,BF0} */
149 u64 __pad1; /* 0x000{B18,,,BF8} */
150 } cp_pcix_write_buf_64[8];
151
152 /* End of Local Registers -- Start of Address Map space */
153
154 char _pad_000c00[0x010000 - 0x000c00];
155
156 /* 0x010000-0x011FF8 -- Internal ATE RAM (Auto Parity Generation) */
157 u64 cp_int_ate_ram[1024]; /* 0x010000-0x011FF8 */
158
159 char _pad_012000[0x14000 - 0x012000];
160
161 /* 0x014000-0x015FF8 -- Internal ATE RAM (Manual Parity Generation) */
162 u64 cp_int_ate_ram_mp[1024]; /* 0x014000-0x015FF8 */
163
164 char _pad_016000[0x18000 - 0x016000];
165
166 /* 0x18000-0x197F8 -- TIOCP Write Request Ram */
167 u64 cp_wr_req_lower[256]; /* 0x18000 - 0x187F8 */
168 u64 cp_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */
169 u64 cp_wr_req_parity[256]; /* 0x19000 - 0x197F8 */
170
171 char _pad_019800[0x1C000 - 0x019800];
172
173 /* 0x1C000-0x1EFF8 -- TIOCP Read Response Ram */
174 u64 cp_rd_resp_lower[512]; /* 0x1C000 - 0x1CFF8 */
175 u64 cp_rd_resp_upper[512]; /* 0x1D000 - 0x1DFF8 */
176 u64 cp_rd_resp_parity[512]; /* 0x1E000 - 0x1EFF8 */
177
178 char _pad_01F000[0x20000 - 0x01F000];
179
180 /* 0x020000-0x021FFF -- Host Device (CP) Configuration Space (not used) */
181 char _pad_020000[0x021000 - 0x20000];
182
183 /* 0x021000-0x027FFF -- PCI Device Configuration Spaces */
184 union {
185 u8 c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */
186 u16 s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */
187 u32 l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */
188 u64 d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */
189 union {
190 u8 c[0x100 / 1];
191 u16 s[0x100 / 2];
192 u32 l[0x100 / 4];
193 u64 d[0x100 / 8];
194 } f[8];
195 } cp_type0_cfg_dev[7]; /* 0x02{1000,,,7FFF} */
196
197 /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
198 union {
199 u8 c[0x1000 / 1]; /* 0x028000-0x029000 */
200 u16 s[0x1000 / 2]; /* 0x028000-0x029000 */
201 u32 l[0x1000 / 4]; /* 0x028000-0x029000 */
202 u64 d[0x1000 / 8]; /* 0x028000-0x029000 */
203 union {
204 u8 c[0x100 / 1];
205 u16 s[0x100 / 2];
206 u32 l[0x100 / 4];
207 u64 d[0x100 / 8];
208 } f[8];
209 } cp_type1_cfg; /* 0x028000-0x029000 */
210
211 char _pad_029000[0x030000-0x029000];
212
213 /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
214 union {
215 u8 c[8 / 1];
216 u16 s[8 / 2];
217 u32 l[8 / 4];
218 u64 d[8 / 8];
219 } cp_pci_iack; /* 0x030000-0x030007 */
220
221 char _pad_030007[0x040000-0x030008];
222
223 /* 0x040000-0x040007 -- PCIX Special Cycle */
224 union {
225 u8 c[8 / 1];
226 u16 s[8 / 2];
227 u32 l[8 / 4];
228 u64 d[8 / 8];
229 } cp_pcix_cycle; /* 0x040000-0x040007 */
230
231 char _pad_040007[0x200000-0x040008];
232
233 /* 0x200000-0x7FFFFF -- PCI/GIO Device Spaces */
234 union {
235 u8 c[0x100000 / 1];
236 u16 s[0x100000 / 2];
237 u32 l[0x100000 / 4];
238 u64 d[0x100000 / 8];
239 } cp_devio_raw[6]; /* 0x200000-0x7FFFFF */
240
241 #define cp_devio(n) cp_devio_raw[((n)<2)?(n*2):(n+2)]
242
243 char _pad_800000[0xA00000-0x800000];
244
245 /* 0xA00000-0xBFFFFF -- PCI/GIO Device Spaces w/flush */
246 union {
247 u8 c[0x100000 / 1];
248 u16 s[0x100000 / 2];
249 u32 l[0x100000 / 4];
250 u64 d[0x100000 / 8];
251 } cp_devio_raw_flush[6]; /* 0xA00000-0xBFFFFF */
252
253 #define cp_devio_flush(n) cp_devio_raw_flush[((n)<2)?(n*2):(n+2)]
254
255};
256
257#endif /* _ASM_IA64_SN_PCI_TIOCP_H */
diff --git a/include/asm-ia64/sn/tiocx.h b/include/asm-ia64/sn/tiocx.h
deleted file mode 100644
index d29728492f3..00000000000
--- a/include/asm-ia64/sn/tiocx.h
+++ /dev/null
@@ -1,72 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (c) 2005 Silicon Graphics, Inc. All rights reserved.
7 */
8
9#ifndef _ASM_IA64_SN_TIO_TIOCX_H
10#define _ASM_IA64_SN_TIO_TIOCX_H
11
12#ifdef __KERNEL__
13
14struct cx_id_s {
15 unsigned int part_num;
16 unsigned int mfg_num;
17 int nasid;
18};
19
20struct cx_dev {
21 struct cx_id_s cx_id;
22 int bt; /* board/blade type */
23 void *soft; /* driver specific */
24 struct hubdev_info *hubdev;
25 struct device dev;
26 struct cx_drv *driver;
27};
28
29struct cx_device_id {
30 unsigned int part_num;
31 unsigned int mfg_num;
32};
33
34struct cx_drv {
35 char *name;
36 const struct cx_device_id *id_table;
37 struct device_driver driver;
38 int (*probe) (struct cx_dev * dev, const struct cx_device_id * id);
39 int (*remove) (struct cx_dev * dev);
40};
41
42/* create DMA address by stripping AS bits */
43#define TIOCX_DMA_ADDR(a) (u64)((u64)(a) & 0xffffcfffffffffUL)
44
45#define TIOCX_TO_TIOCX_DMA_ADDR(a) (u64)(((u64)(a) & 0xfffffffff) | \
46 ((((u64)(a)) & 0xffffc000000000UL) <<2))
47
48#define TIO_CE_ASIC_PARTNUM 0xce00
49#define TIOCX_CORELET 3
50
51/* These are taken from tio_mmr_as.h */
52#define TIO_ICE_FRZ_CFG TIO_MMR_ADDR_MOD(0x00000000b0008100UL)
53#define TIO_ICE_PMI_TX_CFG TIO_MMR_ADDR_MOD(0x00000000b000b100UL)
54#define TIO_ICE_PMI_TX_DYN_CREDIT_STAT_CB3 TIO_MMR_ADDR_MOD(0x00000000b000be18UL)
55#define TIO_ICE_PMI_TX_DYN_CREDIT_STAT_CB3_CREDIT_CNT_MASK 0x000000000000000fUL
56
57#define to_cx_dev(n) container_of(n, struct cx_dev, dev)
58#define to_cx_driver(drv) container_of(drv, struct cx_drv, driver)
59
60extern struct sn_irq_info *tiocx_irq_alloc(nasid_t, int, int, nasid_t, int);
61extern void tiocx_irq_free(struct sn_irq_info *);
62extern int cx_device_unregister(struct cx_dev *);
63extern int cx_device_register(nasid_t, int, int, struct hubdev_info *, int);
64extern int cx_driver_unregister(struct cx_drv *);
65extern int cx_driver_register(struct cx_drv *);
66extern u64 tiocx_dma_addr(u64 addr);
67extern u64 tiocx_swin_base(int nasid);
68extern void tiocx_mmr_store(int nasid, u64 offset, u64 value);
69extern u64 tiocx_mmr_load(int nasid, u64 offset);
70
71#endif // __KERNEL__
72#endif // _ASM_IA64_SN_TIO_TIOCX__
diff --git a/include/asm-ia64/sn/types.h b/include/asm-ia64/sn/types.h
deleted file mode 100644
index 8e04ee211e5..00000000000
--- a/include/asm-ia64/sn/types.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1999,2001-2003 Silicon Graphics, Inc. All Rights Reserved.
7 * Copyright (C) 1999 by Ralf Baechle
8 */
9#ifndef _ASM_IA64_SN_TYPES_H
10#define _ASM_IA64_SN_TYPES_H
11
12#include <linux/types.h>
13
14typedef unsigned long cpuid_t;
15typedef signed short nasid_t; /* node id in numa-as-id space */
16typedef signed char partid_t; /* partition ID type */
17typedef unsigned int moduleid_t; /* user-visible module number type */
18typedef unsigned int cmoduleid_t; /* kernel compact module id type */
19typedef unsigned char slotid_t; /* slot (blade) within module */
20typedef unsigned char slabid_t; /* slab (asic) within slot */
21typedef u64 nic_t;
22typedef unsigned long iopaddr_t;
23typedef unsigned long paddr_t;
24typedef short cnodeid_t;
25
26#endif /* _ASM_IA64_SN_TYPES_H */
diff --git a/include/asm-ia64/socket.h b/include/asm-ia64/socket.h
deleted file mode 100644
index d5ef0aa3e31..00000000000
--- a/include/asm-ia64/socket.h
+++ /dev/null
@@ -1,66 +0,0 @@
1#ifndef _ASM_IA64_SOCKET_H
2#define _ASM_IA64_SOCKET_H
3
4/*
5 * Socket related defines.
6 *
7 * Based on <asm-i386/socket.h>.
8 *
9 * Modified 1998-2000
10 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
11 */
12
13#include <asm/sockios.h>
14
15/* For setsockopt(2) */
16#define SOL_SOCKET 1
17
18#define SO_DEBUG 1
19#define SO_REUSEADDR 2
20#define SO_TYPE 3
21#define SO_ERROR 4
22#define SO_DONTROUTE 5
23#define SO_BROADCAST 6
24#define SO_SNDBUF 7
25#define SO_RCVBUF 8
26#define SO_SNDBUFFORCE 32
27#define SO_RCVBUFFORCE 33
28#define SO_KEEPALIVE 9
29#define SO_OOBINLINE 10
30#define SO_NO_CHECK 11
31#define SO_PRIORITY 12
32#define SO_LINGER 13
33#define SO_BSDCOMPAT 14
34/* To add :#define SO_REUSEPORT 15 */
35#define SO_PASSCRED 16
36#define SO_PEERCRED 17
37#define SO_RCVLOWAT 18
38#define SO_SNDLOWAT 19
39#define SO_RCVTIMEO 20
40#define SO_SNDTIMEO 21
41
42/* Security levels - as per NRL IPv6 - don't actually do anything */
43#define SO_SECURITY_AUTHENTICATION 22
44#define SO_SECURITY_ENCRYPTION_TRANSPORT 23
45#define SO_SECURITY_ENCRYPTION_NETWORK 24
46
47#define SO_BINDTODEVICE 25
48
49/* Socket filtering */
50#define SO_ATTACH_FILTER 26
51#define SO_DETACH_FILTER 27
52
53#define SO_PEERNAME 28
54#define SO_TIMESTAMP 29
55#define SCM_TIMESTAMP SO_TIMESTAMP
56
57#define SO_ACCEPTCONN 30
58
59#define SO_PEERSEC 31
60#define SO_PASSSEC 34
61#define SO_TIMESTAMPNS 35
62#define SCM_TIMESTAMPNS SO_TIMESTAMPNS
63
64#define SO_MARK 36
65
66#endif /* _ASM_IA64_SOCKET_H */
diff --git a/include/asm-ia64/sockios.h b/include/asm-ia64/sockios.h
deleted file mode 100644
index 15c92468ad3..00000000000
--- a/include/asm-ia64/sockios.h
+++ /dev/null
@@ -1,20 +0,0 @@
1#ifndef _ASM_IA64_SOCKIOS_H
2#define _ASM_IA64_SOCKIOS_H
3
4/*
5 * Socket-level I/O control calls.
6 *
7 * Based on <asm-i386/sockios.h>.
8 *
9 * Modified 1998, 1999
10 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
11 */
12#define FIOSETOWN 0x8901
13#define SIOCSPGRP 0x8902
14#define FIOGETOWN 0x8903
15#define SIOCGPGRP 0x8904
16#define SIOCATMARK 0x8905
17#define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */
18#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */
19
20#endif /* _ASM_IA64_SOCKIOS_H */
diff --git a/include/asm-ia64/sparsemem.h b/include/asm-ia64/sparsemem.h
deleted file mode 100644
index 67a7c40ec27..00000000000
--- a/include/asm-ia64/sparsemem.h
+++ /dev/null
@@ -1,20 +0,0 @@
1#ifndef _ASM_IA64_SPARSEMEM_H
2#define _ASM_IA64_SPARSEMEM_H
3
4#ifdef CONFIG_SPARSEMEM
5/*
6 * SECTION_SIZE_BITS 2^N: how big each section will be
7 * MAX_PHYSMEM_BITS 2^N: how much memory we can have in that space
8 */
9
10#define SECTION_SIZE_BITS (30)
11#define MAX_PHYSMEM_BITS (50)
12#ifdef CONFIG_FORCE_MAX_ZONEORDER
13#if ((CONFIG_FORCE_MAX_ZONEORDER - 1 + PAGE_SHIFT) > SECTION_SIZE_BITS)
14#undef SECTION_SIZE_BITS
15#define SECTION_SIZE_BITS (CONFIG_FORCE_MAX_ZONEORDER - 1 + PAGE_SHIFT)
16#endif
17#endif
18
19#endif /* CONFIG_SPARSEMEM */
20#endif /* _ASM_IA64_SPARSEMEM_H */
diff --git a/include/asm-ia64/spinlock.h b/include/asm-ia64/spinlock.h
deleted file mode 100644
index 0229fb95fb3..00000000000
--- a/include/asm-ia64/spinlock.h
+++ /dev/null
@@ -1,220 +0,0 @@
1#ifndef _ASM_IA64_SPINLOCK_H
2#define _ASM_IA64_SPINLOCK_H
3
4/*
5 * Copyright (C) 1998-2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
8 *
9 * This file is used for SMP configurations only.
10 */
11
12#include <linux/compiler.h>
13#include <linux/kernel.h>
14#include <linux/bitops.h>
15
16#include <asm/atomic.h>
17#include <asm/intrinsics.h>
18#include <asm/system.h>
19
20#define __raw_spin_lock_init(x) ((x)->lock = 0)
21
22#ifdef ASM_SUPPORTED
23/*
24 * Try to get the lock. If we fail to get the lock, make a non-standard call to
25 * ia64_spinlock_contention(). We do not use a normal call because that would force all
26 * callers of __raw_spin_lock() to be non-leaf routines. Instead, ia64_spinlock_contention() is
27 * carefully coded to touch only those registers that __raw_spin_lock() marks "clobbered".
28 */
29
30#define IA64_SPINLOCK_CLOBBERS "ar.ccv", "ar.pfs", "p14", "p15", "r27", "r28", "r29", "r30", "b6", "memory"
31
32static inline void
33__raw_spin_lock_flags (raw_spinlock_t *lock, unsigned long flags)
34{
35 register volatile unsigned int *ptr asm ("r31") = &lock->lock;
36
37#if (__GNUC__ == 3 && __GNUC_MINOR__ < 3)
38# ifdef CONFIG_ITANIUM
39 /* don't use brl on Itanium... */
40 asm volatile ("{\n\t"
41 " mov ar.ccv = r0\n\t"
42 " mov r28 = ip\n\t"
43 " mov r30 = 1;;\n\t"
44 "}\n\t"
45 "cmpxchg4.acq r30 = [%1], r30, ar.ccv\n\t"
46 "movl r29 = ia64_spinlock_contention_pre3_4;;\n\t"
47 "cmp4.ne p14, p0 = r30, r0\n\t"
48 "mov b6 = r29;;\n\t"
49 "mov r27=%2\n\t"
50 "(p14) br.cond.spnt.many b6"
51 : "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
52# else
53 asm volatile ("{\n\t"
54 " mov ar.ccv = r0\n\t"
55 " mov r28 = ip\n\t"
56 " mov r30 = 1;;\n\t"
57 "}\n\t"
58 "cmpxchg4.acq r30 = [%1], r30, ar.ccv;;\n\t"
59 "cmp4.ne p14, p0 = r30, r0\n\t"
60 "mov r27=%2\n\t"
61 "(p14) brl.cond.spnt.many ia64_spinlock_contention_pre3_4;;"
62 : "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
63# endif /* CONFIG_MCKINLEY */
64#else
65# ifdef CONFIG_ITANIUM
66 /* don't use brl on Itanium... */
67 /* mis-declare, so we get the entry-point, not it's function descriptor: */
68 asm volatile ("mov r30 = 1\n\t"
69 "mov r27=%2\n\t"
70 "mov ar.ccv = r0;;\n\t"
71 "cmpxchg4.acq r30 = [%0], r30, ar.ccv\n\t"
72 "movl r29 = ia64_spinlock_contention;;\n\t"
73 "cmp4.ne p14, p0 = r30, r0\n\t"
74 "mov b6 = r29;;\n\t"
75 "(p14) br.call.spnt.many b6 = b6"
76 : "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
77# else
78 asm volatile ("mov r30 = 1\n\t"
79 "mov r27=%2\n\t"
80 "mov ar.ccv = r0;;\n\t"
81 "cmpxchg4.acq r30 = [%0], r30, ar.ccv;;\n\t"
82 "cmp4.ne p14, p0 = r30, r0\n\t"
83 "(p14) brl.call.spnt.many b6=ia64_spinlock_contention;;"
84 : "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
85# endif /* CONFIG_MCKINLEY */
86#endif
87}
88
89#define __raw_spin_lock(lock) __raw_spin_lock_flags(lock, 0)
90
91/* Unlock by doing an ordered store and releasing the cacheline with nta */
92static inline void __raw_spin_unlock(raw_spinlock_t *x) {
93 barrier();
94 asm volatile ("st4.rel.nta [%0] = r0\n\t" :: "r"(x));
95}
96
97#else /* !ASM_SUPPORTED */
98#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
99# define __raw_spin_lock(x) \
100do { \
101 __u32 *ia64_spinlock_ptr = (__u32 *) (x); \
102 __u64 ia64_spinlock_val; \
103 ia64_spinlock_val = ia64_cmpxchg4_acq(ia64_spinlock_ptr, 1, 0); \
104 if (unlikely(ia64_spinlock_val)) { \
105 do { \
106 while (*ia64_spinlock_ptr) \
107 ia64_barrier(); \
108 ia64_spinlock_val = ia64_cmpxchg4_acq(ia64_spinlock_ptr, 1, 0); \
109 } while (ia64_spinlock_val); \
110 } \
111} while (0)
112#define __raw_spin_unlock(x) do { barrier(); ((raw_spinlock_t *) x)->lock = 0; } while (0)
113#endif /* !ASM_SUPPORTED */
114
115#define __raw_spin_is_locked(x) ((x)->lock != 0)
116#define __raw_spin_trylock(x) (cmpxchg_acq(&(x)->lock, 0, 1) == 0)
117#define __raw_spin_unlock_wait(lock) \
118 do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
119
120#define __raw_read_can_lock(rw) (*(volatile int *)(rw) >= 0)
121#define __raw_write_can_lock(rw) (*(volatile int *)(rw) == 0)
122
123#define __raw_read_lock(rw) \
124do { \
125 raw_rwlock_t *__read_lock_ptr = (rw); \
126 \
127 while (unlikely(ia64_fetchadd(1, (int *) __read_lock_ptr, acq) < 0)) { \
128 ia64_fetchadd(-1, (int *) __read_lock_ptr, rel); \
129 while (*(volatile int *)__read_lock_ptr < 0) \
130 cpu_relax(); \
131 } \
132} while (0)
133
134#define __raw_read_unlock(rw) \
135do { \
136 raw_rwlock_t *__read_lock_ptr = (rw); \
137 ia64_fetchadd(-1, (int *) __read_lock_ptr, rel); \
138} while (0)
139
140#ifdef ASM_SUPPORTED
141#define __raw_write_lock(rw) \
142do { \
143 __asm__ __volatile__ ( \
144 "mov ar.ccv = r0\n" \
145 "dep r29 = -1, r0, 31, 1;;\n" \
146 "1:\n" \
147 "ld4 r2 = [%0];;\n" \
148 "cmp4.eq p0,p7 = r0,r2\n" \
149 "(p7) br.cond.spnt.few 1b \n" \
150 "cmpxchg4.acq r2 = [%0], r29, ar.ccv;;\n" \
151 "cmp4.eq p0,p7 = r0, r2\n" \
152 "(p7) br.cond.spnt.few 1b;;\n" \
153 :: "r"(rw) : "ar.ccv", "p7", "r2", "r29", "memory"); \
154} while(0)
155
156#define __raw_write_trylock(rw) \
157({ \
158 register long result; \
159 \
160 __asm__ __volatile__ ( \
161 "mov ar.ccv = r0\n" \
162 "dep r29 = -1, r0, 31, 1;;\n" \
163 "cmpxchg4.acq %0 = [%1], r29, ar.ccv\n" \
164 : "=r"(result) : "r"(rw) : "ar.ccv", "r29", "memory"); \
165 (result == 0); \
166})
167
168static inline void __raw_write_unlock(raw_rwlock_t *x)
169{
170 u8 *y = (u8 *)x;
171 barrier();
172 asm volatile ("st1.rel.nta [%0] = r0\n\t" :: "r"(y+3) : "memory" );
173}
174
175#else /* !ASM_SUPPORTED */
176
177#define __raw_write_lock(l) \
178({ \
179 __u64 ia64_val, ia64_set_val = ia64_dep_mi(-1, 0, 31, 1); \
180 __u32 *ia64_write_lock_ptr = (__u32 *) (l); \
181 do { \
182 while (*ia64_write_lock_ptr) \
183 ia64_barrier(); \
184 ia64_val = ia64_cmpxchg4_acq(ia64_write_lock_ptr, ia64_set_val, 0); \
185 } while (ia64_val); \
186})
187
188#define __raw_write_trylock(rw) \
189({ \
190 __u64 ia64_val; \
191 __u64 ia64_set_val = ia64_dep_mi(-1, 0, 31,1); \
192 ia64_val = ia64_cmpxchg4_acq((__u32 *)(rw), ia64_set_val, 0); \
193 (ia64_val == 0); \
194})
195
196static inline void __raw_write_unlock(raw_rwlock_t *x)
197{
198 barrier();
199 x->write_lock = 0;
200}
201
202#endif /* !ASM_SUPPORTED */
203
204static inline int __raw_read_trylock(raw_rwlock_t *x)
205{
206 union {
207 raw_rwlock_t lock;
208 __u32 word;
209 } old, new;
210 old.lock = new.lock = *x;
211 old.lock.write_lock = new.lock.write_lock = 0;
212 ++new.lock.read_counter;
213 return (u32)ia64_cmpxchg4_acq((__u32 *)(x), new.word, old.word) == old.word;
214}
215
216#define _raw_spin_relax(lock) cpu_relax()
217#define _raw_read_relax(lock) cpu_relax()
218#define _raw_write_relax(lock) cpu_relax()
219
220#endif /* _ASM_IA64_SPINLOCK_H */
diff --git a/include/asm-ia64/spinlock_types.h b/include/asm-ia64/spinlock_types.h
deleted file mode 100644
index 474e46f1ab4..00000000000
--- a/include/asm-ia64/spinlock_types.h
+++ /dev/null
@@ -1,21 +0,0 @@
1#ifndef _ASM_IA64_SPINLOCK_TYPES_H
2#define _ASM_IA64_SPINLOCK_TYPES_H
3
4#ifndef __LINUX_SPINLOCK_TYPES_H
5# error "please don't include this file directly"
6#endif
7
8typedef struct {
9 volatile unsigned int lock;
10} raw_spinlock_t;
11
12#define __RAW_SPIN_LOCK_UNLOCKED { 0 }
13
14typedef struct {
15 volatile unsigned int read_counter : 31;
16 volatile unsigned int write_lock : 1;
17} raw_rwlock_t;
18
19#define __RAW_RW_LOCK_UNLOCKED { 0, 0 }
20
21#endif
diff --git a/include/asm-ia64/stat.h b/include/asm-ia64/stat.h
deleted file mode 100644
index 367bb90cdff..00000000000
--- a/include/asm-ia64/stat.h
+++ /dev/null
@@ -1,51 +0,0 @@
1#ifndef _ASM_IA64_STAT_H
2#define _ASM_IA64_STAT_H
3
4/*
5 * Modified 1998, 1999
6 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
7 */
8
9struct stat {
10 unsigned long st_dev;
11 unsigned long st_ino;
12 unsigned long st_nlink;
13 unsigned int st_mode;
14 unsigned int st_uid;
15 unsigned int st_gid;
16 unsigned int __pad0;
17 unsigned long st_rdev;
18 unsigned long st_size;
19 unsigned long st_atime;
20 unsigned long st_atime_nsec;
21 unsigned long st_mtime;
22 unsigned long st_mtime_nsec;
23 unsigned long st_ctime;
24 unsigned long st_ctime_nsec;
25 unsigned long st_blksize;
26 long st_blocks;
27 unsigned long __unused[3];
28};
29
30#define STAT_HAVE_NSEC 1
31
32struct ia64_oldstat {
33 unsigned int st_dev;
34 unsigned int st_ino;
35 unsigned int st_mode;
36 unsigned int st_nlink;
37 unsigned int st_uid;
38 unsigned int st_gid;
39 unsigned int st_rdev;
40 unsigned int __pad1;
41 unsigned long st_size;
42 unsigned long st_atime;
43 unsigned long st_mtime;
44 unsigned long st_ctime;
45 unsigned int st_blksize;
46 int st_blocks;
47 unsigned int __unused1;
48 unsigned int __unused2;
49};
50
51#endif /* _ASM_IA64_STAT_H */
diff --git a/include/asm-ia64/statfs.h b/include/asm-ia64/statfs.h
deleted file mode 100644
index 811097974f3..00000000000
--- a/include/asm-ia64/statfs.h
+++ /dev/null
@@ -1,62 +0,0 @@
1#ifndef _ASM_IA64_STATFS_H
2#define _ASM_IA64_STATFS_H
3
4/*
5 * Based on <asm-i386/statfs.h>.
6 *
7 * Modified 1998, 1999, 2003
8 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
9 */
10
11#ifndef __KERNEL_STRICT_NAMES
12# include <linux/types.h>
13typedef __kernel_fsid_t fsid_t;
14#endif
15
16/*
17 * This is ugly --- we're already 64-bit, so just duplicate the definitions
18 */
19struct statfs {
20 long f_type;
21 long f_bsize;
22 long f_blocks;
23 long f_bfree;
24 long f_bavail;
25 long f_files;
26 long f_ffree;
27 __kernel_fsid_t f_fsid;
28 long f_namelen;
29 long f_frsize;
30 long f_spare[5];
31};
32
33
34struct statfs64 {
35 long f_type;
36 long f_bsize;
37 long f_blocks;
38 long f_bfree;
39 long f_bavail;
40 long f_files;
41 long f_ffree;
42 __kernel_fsid_t f_fsid;
43 long f_namelen;
44 long f_frsize;
45 long f_spare[5];
46};
47
48struct compat_statfs64 {
49 __u32 f_type;
50 __u32 f_bsize;
51 __u64 f_blocks;
52 __u64 f_bfree;
53 __u64 f_bavail;
54 __u64 f_files;
55 __u64 f_ffree;
56 __kernel_fsid_t f_fsid;
57 __u32 f_namelen;
58 __u32 f_frsize;
59 __u32 f_spare[5];
60} __attribute__((packed));
61
62#endif /* _ASM_IA64_STATFS_H */
diff --git a/include/asm-ia64/string.h b/include/asm-ia64/string.h
deleted file mode 100644
index 85fd65c52a8..00000000000
--- a/include/asm-ia64/string.h
+++ /dev/null
@@ -1,21 +0,0 @@
1#ifndef _ASM_IA64_STRING_H
2#define _ASM_IA64_STRING_H
3
4/*
5 * Here is where we want to put optimized versions of the string
6 * routines.
7 *
8 * Copyright (C) 1998-2000, 2002 Hewlett-Packard Co
9 * David Mosberger-Tang <davidm@hpl.hp.com>
10 */
11
12
13#define __HAVE_ARCH_STRLEN 1 /* see arch/ia64/lib/strlen.S */
14#define __HAVE_ARCH_MEMSET 1 /* see arch/ia64/lib/memset.S */
15#define __HAVE_ARCH_MEMCPY 1 /* see arch/ia64/lib/memcpy.S */
16
17extern __kernel_size_t strlen (const char *);
18extern void *memcpy (void *, const void *, __kernel_size_t);
19extern void *memset (void *, int, __kernel_size_t);
20
21#endif /* _ASM_IA64_STRING_H */
diff --git a/include/asm-ia64/suspend.h b/include/asm-ia64/suspend.h
deleted file mode 100644
index b05bbb6074e..00000000000
--- a/include/asm-ia64/suspend.h
+++ /dev/null
@@ -1 +0,0 @@
1/* dummy (must be non-empty to prevent prejudicial removal...) */
diff --git a/include/asm-ia64/system.h b/include/asm-ia64/system.h
deleted file mode 100644
index 927a381c20c..00000000000
--- a/include/asm-ia64/system.h
+++ /dev/null
@@ -1,292 +0,0 @@
1#ifndef _ASM_IA64_SYSTEM_H
2#define _ASM_IA64_SYSTEM_H
3
4/*
5 * System defines. Note that this is included both from .c and .S
6 * files, so it does only defines, not any C code. This is based
7 * on information published in the Processor Abstraction Layer
8 * and the System Abstraction Layer manual.
9 *
10 * Copyright (C) 1998-2003 Hewlett-Packard Co
11 * David Mosberger-Tang <davidm@hpl.hp.com>
12 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
13 * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
14 */
15
16#include <asm/kregs.h>
17#include <asm/page.h>
18#include <asm/pal.h>
19#include <asm/percpu.h>
20
21#define GATE_ADDR RGN_BASE(RGN_GATE)
22
23/*
24 * 0xa000000000000000+2*PERCPU_PAGE_SIZE
25 * - 0xa000000000000000+3*PERCPU_PAGE_SIZE remain unmapped (guard page)
26 */
27#define KERNEL_START (GATE_ADDR+__IA64_UL_CONST(0x100000000))
28#define PERCPU_ADDR (-PERCPU_PAGE_SIZE)
29#define LOAD_OFFSET (KERNEL_START - KERNEL_TR_PAGE_SIZE)
30
31#ifndef __ASSEMBLY__
32
33#include <linux/kernel.h>
34#include <linux/types.h>
35
36#define AT_VECTOR_SIZE_ARCH 2 /* entries in ARCH_DLINFO */
37
38struct pci_vector_struct {
39 __u16 segment; /* PCI Segment number */
40 __u16 bus; /* PCI Bus number */
41 __u32 pci_id; /* ACPI split 16 bits device, 16 bits function (see section 6.1.1) */
42 __u8 pin; /* PCI PIN (0 = A, 1 = B, 2 = C, 3 = D) */
43 __u32 irq; /* IRQ assigned */
44};
45
46extern struct ia64_boot_param {
47 __u64 command_line; /* physical address of command line arguments */
48 __u64 efi_systab; /* physical address of EFI system table */
49 __u64 efi_memmap; /* physical address of EFI memory map */
50 __u64 efi_memmap_size; /* size of EFI memory map */
51 __u64 efi_memdesc_size; /* size of an EFI memory map descriptor */
52 __u32 efi_memdesc_version; /* memory descriptor version */
53 struct {
54 __u16 num_cols; /* number of columns on console output device */
55 __u16 num_rows; /* number of rows on console output device */
56 __u16 orig_x; /* cursor's x position */
57 __u16 orig_y; /* cursor's y position */
58 } console_info;
59 __u64 fpswa; /* physical address of the fpswa interface */
60 __u64 initrd_start;
61 __u64 initrd_size;
62} *ia64_boot_param;
63
64/*
65 * Macros to force memory ordering. In these descriptions, "previous"
66 * and "subsequent" refer to program order; "visible" means that all
67 * architecturally visible effects of a memory access have occurred
68 * (at a minimum, this means the memory has been read or written).
69 *
70 * wmb(): Guarantees that all preceding stores to memory-
71 * like regions are visible before any subsequent
72 * stores and that all following stores will be
73 * visible only after all previous stores.
74 * rmb(): Like wmb(), but for reads.
75 * mb(): wmb()/rmb() combo, i.e., all previous memory
76 * accesses are visible before all subsequent
77 * accesses and vice versa. This is also known as
78 * a "fence."
79 *
80 * Note: "mb()" and its variants cannot be used as a fence to order
81 * accesses to memory mapped I/O registers. For that, mf.a needs to
82 * be used. However, we don't want to always use mf.a because (a)
83 * it's (presumably) much slower than mf and (b) mf.a is supported for
84 * sequential memory pages only.
85 */
86#define mb() ia64_mf()
87#define rmb() mb()
88#define wmb() mb()
89#define read_barrier_depends() do { } while(0)
90
91#ifdef CONFIG_SMP
92# define smp_mb() mb()
93# define smp_rmb() rmb()
94# define smp_wmb() wmb()
95# define smp_read_barrier_depends() read_barrier_depends()
96#else
97# define smp_mb() barrier()
98# define smp_rmb() barrier()
99# define smp_wmb() barrier()
100# define smp_read_barrier_depends() do { } while(0)
101#endif
102
103/*
104 * XXX check on this ---I suspect what Linus really wants here is
105 * acquire vs release semantics but we can't discuss this stuff with
106 * Linus just yet. Grrr...
107 */
108#define set_mb(var, value) do { (var) = (value); mb(); } while (0)
109
110#define safe_halt() ia64_pal_halt_light() /* PAL_HALT_LIGHT */
111
112/*
113 * The group barrier in front of the rsm & ssm are necessary to ensure
114 * that none of the previous instructions in the same group are
115 * affected by the rsm/ssm.
116 */
117/* For spinlocks etc */
118
119/*
120 * - clearing psr.i is implicitly serialized (visible by next insn)
121 * - setting psr.i requires data serialization
122 * - we need a stop-bit before reading PSR because we sometimes
123 * write a floating-point register right before reading the PSR
124 * and that writes to PSR.mfl
125 */
126#ifdef CONFIG_PARAVIRT
127#define __local_save_flags() ia64_get_psr_i()
128#else
129#define __local_save_flags() ia64_getreg(_IA64_REG_PSR)
130#endif
131
132#define __local_irq_save(x) \
133do { \
134 ia64_stop(); \
135 (x) = __local_save_flags(); \
136 ia64_stop(); \
137 ia64_rsm(IA64_PSR_I); \
138} while (0)
139
140#define __local_irq_disable() \
141do { \
142 ia64_stop(); \
143 ia64_rsm(IA64_PSR_I); \
144} while (0)
145
146#define __local_irq_restore(x) ia64_intrin_local_irq_restore((x) & IA64_PSR_I)
147
148#ifdef CONFIG_IA64_DEBUG_IRQ
149
150 extern unsigned long last_cli_ip;
151
152# define __save_ip() last_cli_ip = ia64_getreg(_IA64_REG_IP)
153
154# define local_irq_save(x) \
155do { \
156 unsigned long __psr; \
157 \
158 __local_irq_save(__psr); \
159 if (__psr & IA64_PSR_I) \
160 __save_ip(); \
161 (x) = __psr; \
162} while (0)
163
164# define local_irq_disable() do { unsigned long __x; local_irq_save(__x); } while (0)
165
166# define local_irq_restore(x) \
167do { \
168 unsigned long __old_psr, __psr = (x); \
169 \
170 local_save_flags(__old_psr); \
171 __local_irq_restore(__psr); \
172 if ((__old_psr & IA64_PSR_I) && !(__psr & IA64_PSR_I)) \
173 __save_ip(); \
174} while (0)
175
176#else /* !CONFIG_IA64_DEBUG_IRQ */
177# define local_irq_save(x) __local_irq_save(x)
178# define local_irq_disable() __local_irq_disable()
179# define local_irq_restore(x) __local_irq_restore(x)
180#endif /* !CONFIG_IA64_DEBUG_IRQ */
181
182#define local_irq_enable() ({ ia64_stop(); ia64_ssm(IA64_PSR_I); ia64_srlz_d(); })
183#define local_save_flags(flags) ({ ia64_stop(); (flags) = __local_save_flags(); })
184
185#define irqs_disabled() \
186({ \
187 unsigned long __ia64_id_flags; \
188 local_save_flags(__ia64_id_flags); \
189 (__ia64_id_flags & IA64_PSR_I) == 0; \
190})
191
192#ifdef __KERNEL__
193
194#ifdef CONFIG_IA32_SUPPORT
195# define IS_IA32_PROCESS(regs) (ia64_psr(regs)->is != 0)
196#else
197# define IS_IA32_PROCESS(regs) 0
198struct task_struct;
199static inline void ia32_save_state(struct task_struct *t __attribute__((unused))){}
200static inline void ia32_load_state(struct task_struct *t __attribute__((unused))){}
201#endif
202
203/*
204 * Context switch from one thread to another. If the two threads have
205 * different address spaces, schedule() has already taken care of
206 * switching to the new address space by calling switch_mm().
207 *
208 * Disabling access to the fph partition and the debug-register
209 * context switch MUST be done before calling ia64_switch_to() since a
210 * newly created thread returns directly to
211 * ia64_ret_from_syscall_clear_r8.
212 */
213extern struct task_struct *ia64_switch_to (void *next_task);
214
215struct task_struct;
216
217extern void ia64_save_extra (struct task_struct *task);
218extern void ia64_load_extra (struct task_struct *task);
219
220#ifdef CONFIG_VIRT_CPU_ACCOUNTING
221extern void ia64_account_on_switch (struct task_struct *prev, struct task_struct *next);
222# define IA64_ACCOUNT_ON_SWITCH(p,n) ia64_account_on_switch(p,n)
223#else
224# define IA64_ACCOUNT_ON_SWITCH(p,n)
225#endif
226
227#ifdef CONFIG_PERFMON
228 DECLARE_PER_CPU(unsigned long, pfm_syst_info);
229# define PERFMON_IS_SYSWIDE() (__get_cpu_var(pfm_syst_info) & 0x1)
230#else
231# define PERFMON_IS_SYSWIDE() (0)
232#endif
233
234#define IA64_HAS_EXTRA_STATE(t) \
235 ((t)->thread.flags & (IA64_THREAD_DBG_VALID|IA64_THREAD_PM_VALID) \
236 || IS_IA32_PROCESS(task_pt_regs(t)) || PERFMON_IS_SYSWIDE())
237
238#define __switch_to(prev,next,last) do { \
239 IA64_ACCOUNT_ON_SWITCH(prev, next); \
240 if (IA64_HAS_EXTRA_STATE(prev)) \
241 ia64_save_extra(prev); \
242 if (IA64_HAS_EXTRA_STATE(next)) \
243 ia64_load_extra(next); \
244 ia64_psr(task_pt_regs(next))->dfh = !ia64_is_local_fpu_owner(next); \
245 (last) = ia64_switch_to((next)); \
246} while (0)
247
248#ifdef CONFIG_SMP
249/*
250 * In the SMP case, we save the fph state when context-switching away from a thread that
251 * modified fph. This way, when the thread gets scheduled on another CPU, the CPU can
252 * pick up the state from task->thread.fph, avoiding the complication of having to fetch
253 * the latest fph state from another CPU. In other words: eager save, lazy restore.
254 */
255# define switch_to(prev,next,last) do { \
256 if (ia64_psr(task_pt_regs(prev))->mfh && ia64_is_local_fpu_owner(prev)) { \
257 ia64_psr(task_pt_regs(prev))->mfh = 0; \
258 (prev)->thread.flags |= IA64_THREAD_FPH_VALID; \
259 __ia64_save_fpu((prev)->thread.fph); \
260 } \
261 __switch_to(prev, next, last); \
262 /* "next" in old context is "current" in new context */ \
263 if (unlikely((current->thread.flags & IA64_THREAD_MIGRATION) && \
264 (task_cpu(current) != \
265 task_thread_info(current)->last_cpu))) { \
266 platform_migrate(current); \
267 task_thread_info(current)->last_cpu = task_cpu(current); \
268 } \
269} while (0)
270#else
271# define switch_to(prev,next,last) __switch_to(prev, next, last)
272#endif
273
274#define __ARCH_WANT_UNLOCKED_CTXSW
275#define ARCH_HAS_PREFETCH_SWITCH_STACK
276#define ia64_platform_is(x) (strcmp(x, platform_name) == 0)
277
278void cpu_idle_wait(void);
279
280#define arch_align_stack(x) (x)
281
282void default_idle(void);
283
284#ifdef CONFIG_VIRT_CPU_ACCOUNTING
285extern void account_system_vtime(struct task_struct *);
286#endif
287
288#endif /* __KERNEL__ */
289
290#endif /* __ASSEMBLY__ */
291
292#endif /* _ASM_IA64_SYSTEM_H */
diff --git a/include/asm-ia64/termbits.h b/include/asm-ia64/termbits.h
deleted file mode 100644
index 9f162e0089a..00000000000
--- a/include/asm-ia64/termbits.h
+++ /dev/null
@@ -1,207 +0,0 @@
1#ifndef _ASM_IA64_TERMBITS_H
2#define _ASM_IA64_TERMBITS_H
3
4/*
5 * Based on <asm-i386/termbits.h>.
6 *
7 * Modified 1999
8 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
9 *
10 * 99/01/28 Added new baudrates
11 */
12
13#include <linux/posix_types.h>
14
15typedef unsigned char cc_t;
16typedef unsigned int speed_t;
17typedef unsigned int tcflag_t;
18
19#define NCCS 19
20struct termios {
21 tcflag_t c_iflag; /* input mode flags */
22 tcflag_t c_oflag; /* output mode flags */
23 tcflag_t c_cflag; /* control mode flags */
24 tcflag_t c_lflag; /* local mode flags */
25 cc_t c_line; /* line discipline */
26 cc_t c_cc[NCCS]; /* control characters */
27};
28
29struct termios2 {
30 tcflag_t c_iflag; /* input mode flags */
31 tcflag_t c_oflag; /* output mode flags */
32 tcflag_t c_cflag; /* control mode flags */
33 tcflag_t c_lflag; /* local mode flags */
34 cc_t c_line; /* line discipline */
35 cc_t c_cc[NCCS]; /* control characters */
36 speed_t c_ispeed; /* input speed */
37 speed_t c_ospeed; /* output speed */
38};
39
40struct ktermios {
41 tcflag_t c_iflag; /* input mode flags */
42 tcflag_t c_oflag; /* output mode flags */
43 tcflag_t c_cflag; /* control mode flags */
44 tcflag_t c_lflag; /* local mode flags */
45 cc_t c_line; /* line discipline */
46 cc_t c_cc[NCCS]; /* control characters */
47 speed_t c_ispeed; /* input speed */
48 speed_t c_ospeed; /* output speed */
49};
50
51/* c_cc characters */
52#define VINTR 0
53#define VQUIT 1
54#define VERASE 2
55#define VKILL 3
56#define VEOF 4
57#define VTIME 5
58#define VMIN 6
59#define VSWTC 7
60#define VSTART 8
61#define VSTOP 9
62#define VSUSP 10
63#define VEOL 11
64#define VREPRINT 12
65#define VDISCARD 13
66#define VWERASE 14
67#define VLNEXT 15
68#define VEOL2 16
69
70/* c_iflag bits */
71#define IGNBRK 0000001
72#define BRKINT 0000002
73#define IGNPAR 0000004
74#define PARMRK 0000010
75#define INPCK 0000020
76#define ISTRIP 0000040
77#define INLCR 0000100
78#define IGNCR 0000200
79#define ICRNL 0000400
80#define IUCLC 0001000
81#define IXON 0002000
82#define IXANY 0004000
83#define IXOFF 0010000
84#define IMAXBEL 0020000
85#define IUTF8 0040000
86
87/* c_oflag bits */
88#define OPOST 0000001
89#define OLCUC 0000002
90#define ONLCR 0000004
91#define OCRNL 0000010
92#define ONOCR 0000020
93#define ONLRET 0000040
94#define OFILL 0000100
95#define OFDEL 0000200
96#define NLDLY 0000400
97#define NL0 0000000
98#define NL1 0000400
99#define CRDLY 0003000
100#define CR0 0000000
101#define CR1 0001000
102#define CR2 0002000
103#define CR3 0003000
104#define TABDLY 0014000
105#define TAB0 0000000
106#define TAB1 0004000
107#define TAB2 0010000
108#define TAB3 0014000
109#define XTABS 0014000
110#define BSDLY 0020000
111#define BS0 0000000
112#define BS1 0020000
113#define VTDLY 0040000
114#define VT0 0000000
115#define VT1 0040000
116#define FFDLY 0100000
117#define FF0 0000000
118#define FF1 0100000
119
120/* c_cflag bit meaning */
121#define CBAUD 0010017
122#define B0 0000000 /* hang up */
123#define B50 0000001
124#define B75 0000002
125#define B110 0000003
126#define B134 0000004
127#define B150 0000005
128#define B200 0000006
129#define B300 0000007
130#define B600 0000010
131#define B1200 0000011
132#define B1800 0000012
133#define B2400 0000013
134#define B4800 0000014
135#define B9600 0000015
136#define B19200 0000016
137#define B38400 0000017
138#define EXTA B19200
139#define EXTB B38400
140#define CSIZE 0000060
141#define CS5 0000000
142#define CS6 0000020
143#define CS7 0000040
144#define CS8 0000060
145#define CSTOPB 0000100
146#define CREAD 0000200
147#define PARENB 0000400
148#define PARODD 0001000
149#define HUPCL 0002000
150#define CLOCAL 0004000
151#define CBAUDEX 0010000
152#define BOTHER 0010000
153#define B57600 0010001
154#define B115200 0010002
155#define B230400 0010003
156#define B460800 0010004
157#define B500000 0010005
158#define B576000 0010006
159#define B921600 0010007
160#define B1000000 0010010
161#define B1152000 0010011
162#define B1500000 0010012
163#define B2000000 0010013
164#define B2500000 0010014
165#define B3000000 0010015
166#define B3500000 0010016
167#define B4000000 0010017
168#define CIBAUD 002003600000 /* input baud rate */
169#define CMSPAR 010000000000 /* mark or space (stick) parity */
170#define CRTSCTS 020000000000 /* flow control */
171
172#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
173
174/* c_lflag bits */
175#define ISIG 0000001
176#define ICANON 0000002
177#define XCASE 0000004
178#define ECHO 0000010
179#define ECHOE 0000020
180#define ECHOK 0000040
181#define ECHONL 0000100
182#define NOFLSH 0000200
183#define TOSTOP 0000400
184#define ECHOCTL 0001000
185#define ECHOPRT 0002000
186#define ECHOKE 0004000
187#define FLUSHO 0010000
188#define PENDIN 0040000
189#define IEXTEN 0100000
190
191/* tcflow() and TCXONC use these */
192#define TCOOFF 0
193#define TCOON 1
194#define TCIOFF 2
195#define TCION 3
196
197/* tcflush() and TCFLSH use these */
198#define TCIFLUSH 0
199#define TCOFLUSH 1
200#define TCIOFLUSH 2
201
202/* tcsetattr uses these */
203#define TCSANOW 0
204#define TCSADRAIN 1
205#define TCSAFLUSH 2
206
207#endif /* _ASM_IA64_TERMBITS_H */
diff --git a/include/asm-ia64/termios.h b/include/asm-ia64/termios.h
deleted file mode 100644
index 689d218c0c2..00000000000
--- a/include/asm-ia64/termios.h
+++ /dev/null
@@ -1,97 +0,0 @@
1#ifndef _ASM_IA64_TERMIOS_H
2#define _ASM_IA64_TERMIOS_H
3
4/*
5 * Modified 1999
6 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
7 *
8 * 99/01/28 Added N_IRDA and N_SMSBLOCK
9 */
10
11#include <asm/termbits.h>
12#include <asm/ioctls.h>
13
14struct winsize {
15 unsigned short ws_row;
16 unsigned short ws_col;
17 unsigned short ws_xpixel;
18 unsigned short ws_ypixel;
19};
20
21#define NCC 8
22struct termio {
23 unsigned short c_iflag; /* input mode flags */
24 unsigned short c_oflag; /* output mode flags */
25 unsigned short c_cflag; /* control mode flags */
26 unsigned short c_lflag; /* local mode flags */
27 unsigned char c_line; /* line discipline */
28 unsigned char c_cc[NCC]; /* control characters */
29};
30
31/* modem lines */
32#define TIOCM_LE 0x001
33#define TIOCM_DTR 0x002
34#define TIOCM_RTS 0x004
35#define TIOCM_ST 0x008
36#define TIOCM_SR 0x010
37#define TIOCM_CTS 0x020
38#define TIOCM_CAR 0x040
39#define TIOCM_RNG 0x080
40#define TIOCM_DSR 0x100
41#define TIOCM_CD TIOCM_CAR
42#define TIOCM_RI TIOCM_RNG
43#define TIOCM_OUT1 0x2000
44#define TIOCM_OUT2 0x4000
45#define TIOCM_LOOP 0x8000
46
47/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
48
49# ifdef __KERNEL__
50
51/* intr=^C quit=^\ erase=del kill=^U
52 eof=^D vtime=\0 vmin=\1 sxtc=\0
53 start=^Q stop=^S susp=^Z eol=\0
54 reprint=^R discard=^U werase=^W lnext=^V
55 eol2=\0
56*/
57#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
58
59/*
60 * Translate a "termio" structure into a "termios". Ugh.
61 */
62#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \
63 unsigned short __tmp; \
64 get_user(__tmp,&(termio)->x); \
65 *(unsigned short *) &(termios)->x = __tmp; \
66}
67
68#define user_termio_to_kernel_termios(termios, termio) \
69({ \
70 SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \
71 SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \
72 SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \
73 SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \
74 copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
75})
76
77/*
78 * Translate a "termios" structure into a "termio". Ugh.
79 */
80#define kernel_termios_to_user_termio(termio, termios) \
81({ \
82 put_user((termios)->c_iflag, &(termio)->c_iflag); \
83 put_user((termios)->c_oflag, &(termio)->c_oflag); \
84 put_user((termios)->c_cflag, &(termio)->c_cflag); \
85 put_user((termios)->c_lflag, &(termio)->c_lflag); \
86 put_user((termios)->c_line, &(termio)->c_line); \
87 copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
88})
89
90#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2))
91#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2))
92#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios))
93#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios))
94
95# endif /* __KERNEL__ */
96
97#endif /* _ASM_IA64_TERMIOS_H */
diff --git a/include/asm-ia64/thread_info.h b/include/asm-ia64/thread_info.h
deleted file mode 100644
index 7c60fcdd2ef..00000000000
--- a/include/asm-ia64/thread_info.h
+++ /dev/null
@@ -1,148 +0,0 @@
1/*
2 * Copyright (C) 2002-2003 Hewlett-Packard Co
3 * David Mosberger-Tang <davidm@hpl.hp.com>
4 */
5#ifndef _ASM_IA64_THREAD_INFO_H
6#define _ASM_IA64_THREAD_INFO_H
7
8#ifndef ASM_OFFSETS_C
9#include <asm/asm-offsets.h>
10#endif
11#include <asm/processor.h>
12#include <asm/ptrace.h>
13
14#define PREEMPT_ACTIVE_BIT 30
15#define PREEMPT_ACTIVE (1 << PREEMPT_ACTIVE_BIT)
16
17#ifndef __ASSEMBLY__
18
19/*
20 * On IA-64, we want to keep the task structure and kernel stack together, so they can be
21 * mapped by a single TLB entry and so they can be addressed by the "current" pointer
22 * without having to do pointer masking.
23 */
24struct thread_info {
25 struct task_struct *task; /* XXX not really needed, except for dup_task_struct() */
26 struct exec_domain *exec_domain;/* execution domain */
27 __u32 flags; /* thread_info flags (see TIF_*) */
28 __u32 cpu; /* current CPU */
29 __u32 last_cpu; /* Last CPU thread ran on */
30 __u32 status; /* Thread synchronous flags */
31 mm_segment_t addr_limit; /* user-level address space limit */
32 int preempt_count; /* 0=premptable, <0=BUG; will also serve as bh-counter */
33 struct restart_block restart_block;
34#ifdef CONFIG_VIRT_CPU_ACCOUNTING
35 __u64 ac_stamp;
36 __u64 ac_leave;
37 __u64 ac_stime;
38 __u64 ac_utime;
39#endif
40};
41
42#define THREAD_SIZE KERNEL_STACK_SIZE
43
44#define INIT_THREAD_INFO(tsk) \
45{ \
46 .task = &tsk, \
47 .exec_domain = &default_exec_domain, \
48 .flags = 0, \
49 .cpu = 0, \
50 .addr_limit = KERNEL_DS, \
51 .preempt_count = 0, \
52 .restart_block = { \
53 .fn = do_no_restart_syscall, \
54 }, \
55}
56
57#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
58
59#ifndef ASM_OFFSETS_C
60/* how to get the thread information struct from C */
61#define current_thread_info() ((struct thread_info *) ((char *) current + IA64_TASK_SIZE))
62#define alloc_thread_info(tsk) ((struct thread_info *) ((char *) (tsk) + IA64_TASK_SIZE))
63#define task_thread_info(tsk) ((struct thread_info *) ((char *) (tsk) + IA64_TASK_SIZE))
64#else
65#define current_thread_info() ((struct thread_info *) 0)
66#define alloc_thread_info(tsk) ((struct thread_info *) 0)
67#define task_thread_info(tsk) ((struct thread_info *) 0)
68#endif
69#define free_thread_info(ti) /* nothing */
70#define task_stack_page(tsk) ((void *)(tsk))
71
72#define __HAVE_THREAD_FUNCTIONS
73#ifdef CONFIG_VIRT_CPU_ACCOUNTING
74#define setup_thread_stack(p, org) \
75 *task_thread_info(p) = *task_thread_info(org); \
76 task_thread_info(p)->ac_stime = 0; \
77 task_thread_info(p)->ac_utime = 0; \
78 task_thread_info(p)->task = (p);
79#else
80#define setup_thread_stack(p, org) \
81 *task_thread_info(p) = *task_thread_info(org); \
82 task_thread_info(p)->task = (p);
83#endif
84#define end_of_stack(p) (unsigned long *)((void *)(p) + IA64_RBS_OFFSET)
85
86#define __HAVE_ARCH_TASK_STRUCT_ALLOCATOR
87#define alloc_task_struct() ((struct task_struct *)__get_free_pages(GFP_KERNEL | __GFP_COMP, KERNEL_STACK_SIZE_ORDER))
88#define free_task_struct(tsk) free_pages((unsigned long) (tsk), KERNEL_STACK_SIZE_ORDER)
89
90#define tsk_set_notify_resume(tsk) \
91 set_ti_thread_flag(task_thread_info(tsk), TIF_NOTIFY_RESUME)
92extern void tsk_clear_notify_resume(struct task_struct *tsk);
93#endif /* !__ASSEMBLY */
94
95/*
96 * thread information flags
97 * - these are process state flags that various assembly files may need to access
98 * - pending work-to-be-done flags are in least-significant 16 bits, other flags
99 * in top 16 bits
100 */
101#define TIF_SIGPENDING 0 /* signal pending */
102#define TIF_NEED_RESCHED 1 /* rescheduling necessary */
103#define TIF_SYSCALL_TRACE 2 /* syscall trace active */
104#define TIF_SYSCALL_AUDIT 3 /* syscall auditing active */
105#define TIF_SINGLESTEP 4 /* restore singlestep on return to user mode */
106#define TIF_NOTIFY_RESUME 6 /* resumption notification requested */
107#define TIF_POLLING_NRFLAG 16 /* true if poll_idle() is polling TIF_NEED_RESCHED */
108#define TIF_MEMDIE 17
109#define TIF_MCA_INIT 18 /* this task is processing MCA or INIT */
110#define TIF_DB_DISABLED 19 /* debug trap disabled for fsyscall */
111#define TIF_FREEZE 20 /* is freezing for suspend */
112#define TIF_RESTORE_RSE 21 /* user RBS is newer than kernel RBS */
113
114#define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE)
115#define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT)
116#define _TIF_SINGLESTEP (1 << TIF_SINGLESTEP)
117#define _TIF_SYSCALL_TRACEAUDIT (_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SINGLESTEP)
118#define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME)
119#define _TIF_SIGPENDING (1 << TIF_SIGPENDING)
120#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED)
121#define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG)
122#define _TIF_MCA_INIT (1 << TIF_MCA_INIT)
123#define _TIF_DB_DISABLED (1 << TIF_DB_DISABLED)
124#define _TIF_FREEZE (1 << TIF_FREEZE)
125#define _TIF_RESTORE_RSE (1 << TIF_RESTORE_RSE)
126
127/* "work to do on user-return" bits */
128#define TIF_ALLWORK_MASK (_TIF_SIGPENDING|_TIF_NOTIFY_RESUME|_TIF_SYSCALL_AUDIT|\
129 _TIF_NEED_RESCHED|_TIF_SYSCALL_TRACE)
130/* like TIF_ALLWORK_BITS but sans TIF_SYSCALL_TRACE or TIF_SYSCALL_AUDIT */
131#define TIF_WORK_MASK (TIF_ALLWORK_MASK&~(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT))
132
133#define TS_POLLING 1 /* true if in idle loop and not sleeping */
134#define TS_RESTORE_SIGMASK 2 /* restore signal mask in do_signal() */
135
136#define tsk_is_polling(t) (task_thread_info(t)->status & TS_POLLING)
137
138#ifndef __ASSEMBLY__
139#define HAVE_SET_RESTORE_SIGMASK 1
140static inline void set_restore_sigmask(void)
141{
142 struct thread_info *ti = current_thread_info();
143 ti->status |= TS_RESTORE_SIGMASK;
144 set_bit(TIF_SIGPENDING, &ti->flags);
145}
146#endif /* !__ASSEMBLY__ */
147
148#endif /* _ASM_IA64_THREAD_INFO_H */
diff --git a/include/asm-ia64/timex.h b/include/asm-ia64/timex.h
deleted file mode 100644
index 05a6baf8a47..00000000000
--- a/include/asm-ia64/timex.h
+++ /dev/null
@@ -1,42 +0,0 @@
1#ifndef _ASM_IA64_TIMEX_H
2#define _ASM_IA64_TIMEX_H
3
4/*
5 * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 */
8/*
9 * 2001/01/18 davidm Removed CLOCK_TICK_RATE. It makes no sense on IA-64.
10 * Also removed cacheflush_time as it's entirely unused.
11 */
12
13#include <asm/intrinsics.h>
14#include <asm/processor.h>
15
16typedef unsigned long cycles_t;
17
18extern void (*ia64_udelay)(unsigned long usecs);
19
20/*
21 * For performance reasons, we don't want to define CLOCK_TICK_TRATE as
22 * local_cpu_data->itc_rate. Fortunately, we don't have to, either: according to George
23 * Anzinger, 1/CLOCK_TICK_RATE is taken as the resolution of the timer clock. The time
24 * calculation assumes that you will use enough of these so that your tick size <= 1/HZ.
25 * If the calculation shows that your CLOCK_TICK_RATE can not supply exactly 1/HZ ticks,
26 * the actual value is calculated and used to update the wall clock each jiffie. Setting
27 * the CLOCK_TICK_RATE to x*HZ insures that the calculation will find no errors. Hence we
28 * pick a multiple of HZ which gives us a (totally virtual) CLOCK_TICK_RATE of about
29 * 100MHz.
30 */
31#define CLOCK_TICK_RATE (HZ * 100000UL)
32
33static inline cycles_t
34get_cycles (void)
35{
36 cycles_t ret;
37
38 ret = ia64_getreg(_IA64_REG_AR_ITC);
39 return ret;
40}
41
42#endif /* _ASM_IA64_TIMEX_H */
diff --git a/include/asm-ia64/tlb.h b/include/asm-ia64/tlb.h
deleted file mode 100644
index 20d8a39680c..00000000000
--- a/include/asm-ia64/tlb.h
+++ /dev/null
@@ -1,257 +0,0 @@
1#ifndef _ASM_IA64_TLB_H
2#define _ASM_IA64_TLB_H
3/*
4 * Based on <asm-generic/tlb.h>.
5 *
6 * Copyright (C) 2002-2003 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
8 */
9/*
10 * Removing a translation from a page table (including TLB-shootdown) is a four-step
11 * procedure:
12 *
13 * (1) Flush (virtual) caches --- ensures virtual memory is coherent with kernel memory
14 * (this is a no-op on ia64).
15 * (2) Clear the relevant portions of the page-table
16 * (3) Flush the TLBs --- ensures that stale content is gone from CPU TLBs
17 * (4) Release the pages that were freed up in step (2).
18 *
19 * Note that the ordering of these steps is crucial to avoid races on MP machines.
20 *
21 * The Linux kernel defines several platform-specific hooks for TLB-shootdown. When
22 * unmapping a portion of the virtual address space, these hooks are called according to
23 * the following template:
24 *
25 * tlb <- tlb_gather_mmu(mm, full_mm_flush); // start unmap for address space MM
26 * {
27 * for each vma that needs a shootdown do {
28 * tlb_start_vma(tlb, vma);
29 * for each page-table-entry PTE that needs to be removed do {
30 * tlb_remove_tlb_entry(tlb, pte, address);
31 * if (pte refers to a normal page) {
32 * tlb_remove_page(tlb, page);
33 * }
34 * }
35 * tlb_end_vma(tlb, vma);
36 * }
37 * }
38 * tlb_finish_mmu(tlb, start, end); // finish unmap for address space MM
39 */
40#include <linux/mm.h>
41#include <linux/pagemap.h>
42#include <linux/swap.h>
43
44#include <asm/pgalloc.h>
45#include <asm/processor.h>
46#include <asm/tlbflush.h>
47#include <asm/machvec.h>
48
49#ifdef CONFIG_SMP
50# define FREE_PTE_NR 2048
51# define tlb_fast_mode(tlb) ((tlb)->nr == ~0U)
52#else
53# define FREE_PTE_NR 0
54# define tlb_fast_mode(tlb) (1)
55#endif
56
57struct mmu_gather {
58 struct mm_struct *mm;
59 unsigned int nr; /* == ~0U => fast mode */
60 unsigned char fullmm; /* non-zero means full mm flush */
61 unsigned char need_flush; /* really unmapped some PTEs? */
62 unsigned long start_addr;
63 unsigned long end_addr;
64 struct page *pages[FREE_PTE_NR];
65};
66
67struct ia64_tr_entry {
68 u64 ifa;
69 u64 itir;
70 u64 pte;
71 u64 rr;
72}; /*Record for tr entry!*/
73
74extern int ia64_itr_entry(u64 target_mask, u64 va, u64 pte, u64 log_size);
75extern void ia64_ptr_entry(u64 target_mask, int slot);
76
77extern struct ia64_tr_entry __per_cpu_idtrs[NR_CPUS][2][IA64_TR_ALLOC_MAX];
78
79/*
80 region register macros
81*/
82#define RR_TO_VE(val) (((val) >> 0) & 0x0000000000000001)
83#define RR_VE(val) (((val) & 0x0000000000000001) << 0)
84#define RR_VE_MASK 0x0000000000000001L
85#define RR_VE_SHIFT 0
86#define RR_TO_PS(val) (((val) >> 2) & 0x000000000000003f)
87#define RR_PS(val) (((val) & 0x000000000000003f) << 2)
88#define RR_PS_MASK 0x00000000000000fcL
89#define RR_PS_SHIFT 2
90#define RR_RID_MASK 0x00000000ffffff00L
91#define RR_TO_RID(val) ((val >> 8) & 0xffffff)
92
93/* Users of the generic TLB shootdown code must declare this storage space. */
94DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
95
96/*
97 * Flush the TLB for address range START to END and, if not in fast mode, release the
98 * freed pages that where gathered up to this point.
99 */
100static inline void
101ia64_tlb_flush_mmu (struct mmu_gather *tlb, unsigned long start, unsigned long end)
102{
103 unsigned int nr;
104
105 if (!tlb->need_flush)
106 return;
107 tlb->need_flush = 0;
108
109 if (tlb->fullmm) {
110 /*
111 * Tearing down the entire address space. This happens both as a result
112 * of exit() and execve(). The latter case necessitates the call to
113 * flush_tlb_mm() here.
114 */
115 flush_tlb_mm(tlb->mm);
116 } else if (unlikely (end - start >= 1024*1024*1024*1024UL
117 || REGION_NUMBER(start) != REGION_NUMBER(end - 1)))
118 {
119 /*
120 * If we flush more than a tera-byte or across regions, we're probably
121 * better off just flushing the entire TLB(s). This should be very rare
122 * and is not worth optimizing for.
123 */
124 flush_tlb_all();
125 } else {
126 /*
127 * XXX fix me: flush_tlb_range() should take an mm pointer instead of a
128 * vma pointer.
129 */
130 struct vm_area_struct vma;
131
132 vma.vm_mm = tlb->mm;
133 /* flush the address range from the tlb: */
134 flush_tlb_range(&vma, start, end);
135 /* now flush the virt. page-table area mapping the address range: */
136 flush_tlb_range(&vma, ia64_thash(start), ia64_thash(end));
137 }
138
139 /* lastly, release the freed pages */
140 nr = tlb->nr;
141 if (!tlb_fast_mode(tlb)) {
142 unsigned long i;
143 tlb->nr = 0;
144 tlb->start_addr = ~0UL;
145 for (i = 0; i < nr; ++i)
146 free_page_and_swap_cache(tlb->pages[i]);
147 }
148}
149
150/*
151 * Return a pointer to an initialized struct mmu_gather.
152 */
153static inline struct mmu_gather *
154tlb_gather_mmu (struct mm_struct *mm, unsigned int full_mm_flush)
155{
156 struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
157
158 tlb->mm = mm;
159 /*
160 * Use fast mode if only 1 CPU is online.
161 *
162 * It would be tempting to turn on fast-mode for full_mm_flush as well. But this
163 * doesn't work because of speculative accesses and software prefetching: the page
164 * table of "mm" may (and usually is) the currently active page table and even
165 * though the kernel won't do any user-space accesses during the TLB shoot down, a
166 * compiler might use speculation or lfetch.fault on what happens to be a valid
167 * user-space address. This in turn could trigger a TLB miss fault (or a VHPT
168 * walk) and re-insert a TLB entry we just removed. Slow mode avoids such
169 * problems. (We could make fast-mode work by switching the current task to a
170 * different "mm" during the shootdown.) --davidm 08/02/2002
171 */
172 tlb->nr = (num_online_cpus() == 1) ? ~0U : 0;
173 tlb->fullmm = full_mm_flush;
174 tlb->start_addr = ~0UL;
175 return tlb;
176}
177
178/*
179 * Called at the end of the shootdown operation to free up any resources that were
180 * collected.
181 */
182static inline void
183tlb_finish_mmu (struct mmu_gather *tlb, unsigned long start, unsigned long end)
184{
185 /*
186 * Note: tlb->nr may be 0 at this point, so we can't rely on tlb->start_addr and
187 * tlb->end_addr.
188 */
189 ia64_tlb_flush_mmu(tlb, start, end);
190
191 /* keep the page table cache within bounds */
192 check_pgt_cache();
193
194 put_cpu_var(mmu_gathers);
195}
196
197/*
198 * Logically, this routine frees PAGE. On MP machines, the actual freeing of the page
199 * must be delayed until after the TLB has been flushed (see comments at the beginning of
200 * this file).
201 */
202static inline void
203tlb_remove_page (struct mmu_gather *tlb, struct page *page)
204{
205 tlb->need_flush = 1;
206
207 if (tlb_fast_mode(tlb)) {
208 free_page_and_swap_cache(page);
209 return;
210 }
211 tlb->pages[tlb->nr++] = page;
212 if (tlb->nr >= FREE_PTE_NR)
213 ia64_tlb_flush_mmu(tlb, tlb->start_addr, tlb->end_addr);
214}
215
216/*
217 * Remove TLB entry for PTE mapped at virtual address ADDRESS. This is called for any
218 * PTE, not just those pointing to (normal) physical memory.
219 */
220static inline void
221__tlb_remove_tlb_entry (struct mmu_gather *tlb, pte_t *ptep, unsigned long address)
222{
223 if (tlb->start_addr == ~0UL)
224 tlb->start_addr = address;
225 tlb->end_addr = address + PAGE_SIZE;
226}
227
228#define tlb_migrate_finish(mm) platform_tlb_migrate_finish(mm)
229
230#define tlb_start_vma(tlb, vma) do { } while (0)
231#define tlb_end_vma(tlb, vma) do { } while (0)
232
233#define tlb_remove_tlb_entry(tlb, ptep, addr) \
234do { \
235 tlb->need_flush = 1; \
236 __tlb_remove_tlb_entry(tlb, ptep, addr); \
237} while (0)
238
239#define pte_free_tlb(tlb, ptep) \
240do { \
241 tlb->need_flush = 1; \
242 __pte_free_tlb(tlb, ptep); \
243} while (0)
244
245#define pmd_free_tlb(tlb, ptep) \
246do { \
247 tlb->need_flush = 1; \
248 __pmd_free_tlb(tlb, ptep); \
249} while (0)
250
251#define pud_free_tlb(tlb, pudp) \
252do { \
253 tlb->need_flush = 1; \
254 __pud_free_tlb(tlb, pudp); \
255} while (0)
256
257#endif /* _ASM_IA64_TLB_H */
diff --git a/include/asm-ia64/tlbflush.h b/include/asm-ia64/tlbflush.h
deleted file mode 100644
index 3be25dfed16..00000000000
--- a/include/asm-ia64/tlbflush.h
+++ /dev/null
@@ -1,102 +0,0 @@
1#ifndef _ASM_IA64_TLBFLUSH_H
2#define _ASM_IA64_TLBFLUSH_H
3
4/*
5 * Copyright (C) 2002 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 */
8
9
10#include <linux/mm.h>
11
12#include <asm/intrinsics.h>
13#include <asm/mmu_context.h>
14#include <asm/page.h>
15
16/*
17 * Now for some TLB flushing routines. This is the kind of stuff that
18 * can be very expensive, so try to avoid them whenever possible.
19 */
20extern void setup_ptcg_sem(int max_purges, int from_palo);
21
22/*
23 * Flush everything (kernel mapping may also have changed due to
24 * vmalloc/vfree).
25 */
26extern void local_flush_tlb_all (void);
27
28#ifdef CONFIG_SMP
29 extern void smp_flush_tlb_all (void);
30 extern void smp_flush_tlb_mm (struct mm_struct *mm);
31 extern void smp_flush_tlb_cpumask (cpumask_t xcpumask);
32# define flush_tlb_all() smp_flush_tlb_all()
33#else
34# define flush_tlb_all() local_flush_tlb_all()
35# define smp_flush_tlb_cpumask(m) local_flush_tlb_all()
36#endif
37
38static inline void
39local_finish_flush_tlb_mm (struct mm_struct *mm)
40{
41 if (mm == current->active_mm)
42 activate_context(mm);
43}
44
45/*
46 * Flush a specified user mapping. This is called, e.g., as a result of fork() and
47 * exit(). fork() ends up here because the copy-on-write mechanism needs to write-protect
48 * the PTEs of the parent task.
49 */
50static inline void
51flush_tlb_mm (struct mm_struct *mm)
52{
53 if (!mm)
54 return;
55
56 set_bit(mm->context, ia64_ctx.flushmap);
57 mm->context = 0;
58
59 if (atomic_read(&mm->mm_users) == 0)
60 return; /* happens as a result of exit_mmap() */
61
62#ifdef CONFIG_SMP
63 smp_flush_tlb_mm(mm);
64#else
65 local_finish_flush_tlb_mm(mm);
66#endif
67}
68
69extern void flush_tlb_range (struct vm_area_struct *vma, unsigned long start, unsigned long end);
70
71/*
72 * Page-granular tlb flush.
73 */
74static inline void
75flush_tlb_page (struct vm_area_struct *vma, unsigned long addr)
76{
77#ifdef CONFIG_SMP
78 flush_tlb_range(vma, (addr & PAGE_MASK), (addr & PAGE_MASK) + PAGE_SIZE);
79#else
80 if (vma->vm_mm == current->active_mm)
81 ia64_ptcl(addr, (PAGE_SHIFT << 2));
82 else
83 vma->vm_mm->context = 0;
84#endif
85}
86
87/*
88 * Flush the local TLB. Invoked from another cpu using an IPI.
89 */
90#ifdef CONFIG_SMP
91void smp_local_flush_tlb(void);
92#else
93#define smp_local_flush_tlb()
94#endif
95
96static inline void flush_tlb_kernel_range(unsigned long start,
97 unsigned long end)
98{
99 flush_tlb_all(); /* XXX fix me */
100}
101
102#endif /* _ASM_IA64_TLBFLUSH_H */
diff --git a/include/asm-ia64/topology.h b/include/asm-ia64/topology.h
deleted file mode 100644
index 32863b3bb1d..00000000000
--- a/include/asm-ia64/topology.h
+++ /dev/null
@@ -1,128 +0,0 @@
1/*
2 * linux/include/asm-ia64/topology.h
3 *
4 * Copyright (C) 2002, Erich Focht, NEC
5 *
6 * All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13#ifndef _ASM_IA64_TOPOLOGY_H
14#define _ASM_IA64_TOPOLOGY_H
15
16#include <asm/acpi.h>
17#include <asm/numa.h>
18#include <asm/smp.h>
19
20#ifdef CONFIG_NUMA
21
22/* Nodes w/o CPUs are preferred for memory allocations, see build_zonelists */
23#define PENALTY_FOR_NODE_WITH_CPUS 255
24
25/*
26 * Distance above which we begin to use zone reclaim
27 */
28#define RECLAIM_DISTANCE 15
29
30/*
31 * Returns the number of the node containing CPU 'cpu'
32 */
33#define cpu_to_node(cpu) (int)(cpu_to_node_map[cpu])
34
35/*
36 * Returns a bitmask of CPUs on Node 'node'.
37 */
38#define node_to_cpumask(node) (node_to_cpu_mask[node])
39
40/*
41 * Returns the number of the node containing Node 'nid'.
42 * Not implemented here. Multi-level hierarchies detected with
43 * the help of node_distance().
44 */
45#define parent_node(nid) (nid)
46
47/*
48 * Returns the number of the first CPU on Node 'node'.
49 */
50#define node_to_first_cpu(node) (first_cpu(node_to_cpumask(node)))
51
52/*
53 * Determines the node for a given pci bus
54 */
55#define pcibus_to_node(bus) PCI_CONTROLLER(bus)->node
56
57void build_cpu_to_node_map(void);
58
59#define SD_CPU_INIT (struct sched_domain) { \
60 .span = CPU_MASK_NONE, \
61 .parent = NULL, \
62 .child = NULL, \
63 .groups = NULL, \
64 .min_interval = 1, \
65 .max_interval = 4, \
66 .busy_factor = 64, \
67 .imbalance_pct = 125, \
68 .cache_nice_tries = 2, \
69 .busy_idx = 2, \
70 .idle_idx = 1, \
71 .newidle_idx = 2, \
72 .wake_idx = 1, \
73 .forkexec_idx = 1, \
74 .flags = SD_LOAD_BALANCE \
75 | SD_BALANCE_NEWIDLE \
76 | SD_BALANCE_EXEC \
77 | SD_WAKE_AFFINE, \
78 .last_balance = jiffies, \
79 .balance_interval = 1, \
80 .nr_balance_failed = 0, \
81}
82
83/* sched_domains SD_NODE_INIT for IA64 NUMA machines */
84#define SD_NODE_INIT (struct sched_domain) { \
85 .span = CPU_MASK_NONE, \
86 .parent = NULL, \
87 .child = NULL, \
88 .groups = NULL, \
89 .min_interval = 8, \
90 .max_interval = 8*(min(num_online_cpus(), 32)), \
91 .busy_factor = 64, \
92 .imbalance_pct = 125, \
93 .cache_nice_tries = 2, \
94 .busy_idx = 3, \
95 .idle_idx = 2, \
96 .newidle_idx = 2, \
97 .wake_idx = 1, \
98 .forkexec_idx = 1, \
99 .flags = SD_LOAD_BALANCE \
100 | SD_BALANCE_EXEC \
101 | SD_BALANCE_FORK \
102 | SD_SERIALIZE \
103 | SD_WAKE_BALANCE, \
104 .last_balance = jiffies, \
105 .balance_interval = 64, \
106 .nr_balance_failed = 0, \
107}
108
109#endif /* CONFIG_NUMA */
110
111#ifdef CONFIG_SMP
112#define topology_physical_package_id(cpu) (cpu_data(cpu)->socket_id)
113#define topology_core_id(cpu) (cpu_data(cpu)->core_id)
114#define topology_core_siblings(cpu) (cpu_core_map[cpu])
115#define topology_thread_siblings(cpu) (per_cpu(cpu_sibling_map, cpu))
116#define smt_capable() (smp_num_siblings > 1)
117#endif
118
119extern void arch_fix_phys_package_id(int num, u32 slot);
120
121#define pcibus_to_cpumask(bus) (pcibus_to_node(bus) == -1 ? \
122 CPU_MASK_ALL : \
123 node_to_cpumask(pcibus_to_node(bus)) \
124 )
125
126#include <asm-generic/topology.h>
127
128#endif /* _ASM_IA64_TOPOLOGY_H */
diff --git a/include/asm-ia64/types.h b/include/asm-ia64/types.h
deleted file mode 100644
index e36b3716e71..00000000000
--- a/include/asm-ia64/types.h
+++ /dev/null
@@ -1,46 +0,0 @@
1#ifndef _ASM_IA64_TYPES_H
2#define _ASM_IA64_TYPES_H
3
4/*
5 * This file is never included by application software unless explicitly requested (e.g.,
6 * via linux/types.h) in which case the application is Linux specific so (user-) name
7 * space pollution is not a major issue. However, for interoperability, libraries still
8 * need to be careful to avoid a name clashes.
9 *
10 * Based on <asm-alpha/types.h>.
11 *
12 * Modified 1998-2000, 2002
13 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
14 */
15
16#include <asm-generic/int-l64.h>
17
18#ifdef __ASSEMBLY__
19# define __IA64_UL(x) (x)
20# define __IA64_UL_CONST(x) x
21
22# ifdef __KERNEL__
23# define BITS_PER_LONG 64
24# endif
25
26#else
27# define __IA64_UL(x) ((unsigned long)(x))
28# define __IA64_UL_CONST(x) x##UL
29
30typedef unsigned int umode_t;
31
32/*
33 * These aren't exported outside the kernel to avoid name space clashes
34 */
35# ifdef __KERNEL__
36
37#define BITS_PER_LONG 64
38
39/* DMA addresses are 64-bits wide, in general. */
40
41typedef u64 dma_addr_t;
42
43# endif /* __KERNEL__ */
44#endif /* !__ASSEMBLY__ */
45
46#endif /* _ASM_IA64_TYPES_H */
diff --git a/include/asm-ia64/uaccess.h b/include/asm-ia64/uaccess.h
deleted file mode 100644
index 449c8c0fa2b..00000000000
--- a/include/asm-ia64/uaccess.h
+++ /dev/null
@@ -1,401 +0,0 @@
1#ifndef _ASM_IA64_UACCESS_H
2#define _ASM_IA64_UACCESS_H
3
4/*
5 * This file defines various macros to transfer memory areas across
6 * the user/kernel boundary. This needs to be done carefully because
7 * this code is executed in kernel mode and uses user-specified
8 * addresses. Thus, we need to be careful not to let the user to
9 * trick us into accessing kernel memory that would normally be
10 * inaccessible. This code is also fairly performance sensitive,
11 * so we want to spend as little time doing safety checks as
12 * possible.
13 *
14 * To make matters a bit more interesting, these macros sometimes also
15 * called from within the kernel itself, in which case the address
16 * validity check must be skipped. The get_fs() macro tells us what
17 * to do: if get_fs()==USER_DS, checking is performed, if
18 * get_fs()==KERNEL_DS, checking is bypassed.
19 *
20 * Note that even if the memory area specified by the user is in a
21 * valid address range, it is still possible that we'll get a page
22 * fault while accessing it. This is handled by filling out an
23 * exception handler fixup entry for each instruction that has the
24 * potential to fault. When such a fault occurs, the page fault
25 * handler checks to see whether the faulting instruction has a fixup
26 * associated and, if so, sets r8 to -EFAULT and clears r9 to 0 and
27 * then resumes execution at the continuation point.
28 *
29 * Based on <asm-alpha/uaccess.h>.
30 *
31 * Copyright (C) 1998, 1999, 2001-2004 Hewlett-Packard Co
32 * David Mosberger-Tang <davidm@hpl.hp.com>
33 */
34
35#include <linux/compiler.h>
36#include <linux/errno.h>
37#include <linux/sched.h>
38#include <linux/page-flags.h>
39#include <linux/mm.h>
40
41#include <asm/intrinsics.h>
42#include <asm/pgtable.h>
43#include <asm/io.h>
44
45/*
46 * For historical reasons, the following macros are grossly misnamed:
47 */
48#define KERNEL_DS ((mm_segment_t) { ~0UL }) /* cf. access_ok() */
49#define USER_DS ((mm_segment_t) { TASK_SIZE-1 }) /* cf. access_ok() */
50
51#define VERIFY_READ 0
52#define VERIFY_WRITE 1
53
54#define get_ds() (KERNEL_DS)
55#define get_fs() (current_thread_info()->addr_limit)
56#define set_fs(x) (current_thread_info()->addr_limit = (x))
57
58#define segment_eq(a, b) ((a).seg == (b).seg)
59
60/*
61 * When accessing user memory, we need to make sure the entire area really is in
62 * user-level space. In order to do this efficiently, we make sure that the page at
63 * address TASK_SIZE is never valid. We also need to make sure that the address doesn't
64 * point inside the virtually mapped linear page table.
65 */
66#define __access_ok(addr, size, segment) \
67({ \
68 __chk_user_ptr(addr); \
69 (likely((unsigned long) (addr) <= (segment).seg) \
70 && ((segment).seg == KERNEL_DS.seg \
71 || likely(REGION_OFFSET((unsigned long) (addr)) < RGN_MAP_LIMIT))); \
72})
73#define access_ok(type, addr, size) __access_ok((addr), (size), get_fs())
74
75/*
76 * These are the main single-value transfer routines. They automatically
77 * use the right size if we just have the right pointer type.
78 *
79 * Careful to not
80 * (a) re-use the arguments for side effects (sizeof/typeof is ok)
81 * (b) require any knowledge of processes at this stage
82 */
83#define put_user(x, ptr) __put_user_check((__typeof__(*(ptr))) (x), (ptr), sizeof(*(ptr)), get_fs())
84#define get_user(x, ptr) __get_user_check((x), (ptr), sizeof(*(ptr)), get_fs())
85
86/*
87 * The "__xxx" versions do not do address space checking, useful when
88 * doing multiple accesses to the same area (the programmer has to do the
89 * checks by hand with "access_ok()")
90 */
91#define __put_user(x, ptr) __put_user_nocheck((__typeof__(*(ptr))) (x), (ptr), sizeof(*(ptr)))
92#define __get_user(x, ptr) __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
93
94extern long __put_user_unaligned_unknown (void);
95
96#define __put_user_unaligned(x, ptr) \
97({ \
98 long __ret; \
99 switch (sizeof(*(ptr))) { \
100 case 1: __ret = __put_user((x), (ptr)); break; \
101 case 2: __ret = (__put_user((x), (u8 __user *)(ptr))) \
102 | (__put_user((x) >> 8, ((u8 __user *)(ptr) + 1))); break; \
103 case 4: __ret = (__put_user((x), (u16 __user *)(ptr))) \
104 | (__put_user((x) >> 16, ((u16 __user *)(ptr) + 1))); break; \
105 case 8: __ret = (__put_user((x), (u32 __user *)(ptr))) \
106 | (__put_user((x) >> 32, ((u32 __user *)(ptr) + 1))); break; \
107 default: __ret = __put_user_unaligned_unknown(); \
108 } \
109 __ret; \
110})
111
112extern long __get_user_unaligned_unknown (void);
113
114#define __get_user_unaligned(x, ptr) \
115({ \
116 long __ret; \
117 switch (sizeof(*(ptr))) { \
118 case 1: __ret = __get_user((x), (ptr)); break; \
119 case 2: __ret = (__get_user((x), (u8 __user *)(ptr))) \
120 | (__get_user((x) >> 8, ((u8 __user *)(ptr) + 1))); break; \
121 case 4: __ret = (__get_user((x), (u16 __user *)(ptr))) \
122 | (__get_user((x) >> 16, ((u16 __user *)(ptr) + 1))); break; \
123 case 8: __ret = (__get_user((x), (u32 __user *)(ptr))) \
124 | (__get_user((x) >> 32, ((u32 __user *)(ptr) + 1))); break; \
125 default: __ret = __get_user_unaligned_unknown(); \
126 } \
127 __ret; \
128})
129
130#ifdef ASM_SUPPORTED
131 struct __large_struct { unsigned long buf[100]; };
132# define __m(x) (*(struct __large_struct __user *)(x))
133
134/* We need to declare the __ex_table section before we can use it in .xdata. */
135asm (".section \"__ex_table\", \"a\"\n\t.previous");
136
137# define __get_user_size(val, addr, n, err) \
138do { \
139 register long __gu_r8 asm ("r8") = 0; \
140 register long __gu_r9 asm ("r9"); \
141 asm ("\n[1:]\tld"#n" %0=%2%P2\t// %0 and %1 get overwritten by exception handler\n" \
142 "\t.xdata4 \"__ex_table\", 1b-., 1f-.+4\n" \
143 "[1:]" \
144 : "=r"(__gu_r9), "=r"(__gu_r8) : "m"(__m(addr)), "1"(__gu_r8)); \
145 (err) = __gu_r8; \
146 (val) = __gu_r9; \
147} while (0)
148
149/*
150 * The "__put_user_size()" macro tells gcc it reads from memory instead of writing it. This
151 * is because they do not write to any memory gcc knows about, so there are no aliasing
152 * issues.
153 */
154# define __put_user_size(val, addr, n, err) \
155do { \
156 register long __pu_r8 asm ("r8") = 0; \
157 asm volatile ("\n[1:]\tst"#n" %1=%r2%P1\t// %0 gets overwritten by exception handler\n" \
158 "\t.xdata4 \"__ex_table\", 1b-., 1f-.\n" \
159 "[1:]" \
160 : "=r"(__pu_r8) : "m"(__m(addr)), "rO"(val), "0"(__pu_r8)); \
161 (err) = __pu_r8; \
162} while (0)
163
164#else /* !ASM_SUPPORTED */
165# define RELOC_TYPE 2 /* ip-rel */
166# define __get_user_size(val, addr, n, err) \
167do { \
168 __ld_user("__ex_table", (unsigned long) addr, n, RELOC_TYPE); \
169 (err) = ia64_getreg(_IA64_REG_R8); \
170 (val) = ia64_getreg(_IA64_REG_R9); \
171} while (0)
172# define __put_user_size(val, addr, n, err) \
173do { \
174 __st_user("__ex_table", (unsigned long) addr, n, RELOC_TYPE, (unsigned long) (val)); \
175 (err) = ia64_getreg(_IA64_REG_R8); \
176} while (0)
177#endif /* !ASM_SUPPORTED */
178
179extern void __get_user_unknown (void);
180
181/*
182 * Evaluating arguments X, PTR, SIZE, and SEGMENT may involve subroutine-calls, which
183 * could clobber r8 and r9 (among others). Thus, be careful not to evaluate it while
184 * using r8/r9.
185 */
186#define __do_get_user(check, x, ptr, size, segment) \
187({ \
188 const __typeof__(*(ptr)) __user *__gu_ptr = (ptr); \
189 __typeof__ (size) __gu_size = (size); \
190 long __gu_err = -EFAULT; \
191 unsigned long __gu_val = 0; \
192 if (!check || __access_ok(__gu_ptr, size, segment)) \
193 switch (__gu_size) { \
194 case 1: __get_user_size(__gu_val, __gu_ptr, 1, __gu_err); break; \
195 case 2: __get_user_size(__gu_val, __gu_ptr, 2, __gu_err); break; \
196 case 4: __get_user_size(__gu_val, __gu_ptr, 4, __gu_err); break; \
197 case 8: __get_user_size(__gu_val, __gu_ptr, 8, __gu_err); break; \
198 default: __get_user_unknown(); break; \
199 } \
200 (x) = (__typeof__(*(__gu_ptr))) __gu_val; \
201 __gu_err; \
202})
203
204#define __get_user_nocheck(x, ptr, size) __do_get_user(0, x, ptr, size, KERNEL_DS)
205#define __get_user_check(x, ptr, size, segment) __do_get_user(1, x, ptr, size, segment)
206
207extern void __put_user_unknown (void);
208
209/*
210 * Evaluating arguments X, PTR, SIZE, and SEGMENT may involve subroutine-calls, which
211 * could clobber r8 (among others). Thus, be careful not to evaluate them while using r8.
212 */
213#define __do_put_user(check, x, ptr, size, segment) \
214({ \
215 __typeof__ (x) __pu_x = (x); \
216 __typeof__ (*(ptr)) __user *__pu_ptr = (ptr); \
217 __typeof__ (size) __pu_size = (size); \
218 long __pu_err = -EFAULT; \
219 \
220 if (!check || __access_ok(__pu_ptr, __pu_size, segment)) \
221 switch (__pu_size) { \
222 case 1: __put_user_size(__pu_x, __pu_ptr, 1, __pu_err); break; \
223 case 2: __put_user_size(__pu_x, __pu_ptr, 2, __pu_err); break; \
224 case 4: __put_user_size(__pu_x, __pu_ptr, 4, __pu_err); break; \
225 case 8: __put_user_size(__pu_x, __pu_ptr, 8, __pu_err); break; \
226 default: __put_user_unknown(); break; \
227 } \
228 __pu_err; \
229})
230
231#define __put_user_nocheck(x, ptr, size) __do_put_user(0, x, ptr, size, KERNEL_DS)
232#define __put_user_check(x, ptr, size, segment) __do_put_user(1, x, ptr, size, segment)
233
234/*
235 * Complex access routines
236 */
237extern unsigned long __must_check __copy_user (void __user *to, const void __user *from,
238 unsigned long count);
239
240static inline unsigned long
241__copy_to_user (void __user *to, const void *from, unsigned long count)
242{
243 return __copy_user(to, (__force void __user *) from, count);
244}
245
246static inline unsigned long
247__copy_from_user (void *to, const void __user *from, unsigned long count)
248{
249 return __copy_user((__force void __user *) to, from, count);
250}
251
252#define __copy_to_user_inatomic __copy_to_user
253#define __copy_from_user_inatomic __copy_from_user
254#define copy_to_user(to, from, n) \
255({ \
256 void __user *__cu_to = (to); \
257 const void *__cu_from = (from); \
258 long __cu_len = (n); \
259 \
260 if (__access_ok(__cu_to, __cu_len, get_fs())) \
261 __cu_len = __copy_user(__cu_to, (__force void __user *) __cu_from, __cu_len); \
262 __cu_len; \
263})
264
265#define copy_from_user(to, from, n) \
266({ \
267 void *__cu_to = (to); \
268 const void __user *__cu_from = (from); \
269 long __cu_len = (n); \
270 \
271 __chk_user_ptr(__cu_from); \
272 if (__access_ok(__cu_from, __cu_len, get_fs())) \
273 __cu_len = __copy_user((__force void __user *) __cu_to, __cu_from, __cu_len); \
274 __cu_len; \
275})
276
277#define __copy_in_user(to, from, size) __copy_user((to), (from), (size))
278
279static inline unsigned long
280copy_in_user (void __user *to, const void __user *from, unsigned long n)
281{
282 if (likely(access_ok(VERIFY_READ, from, n) && access_ok(VERIFY_WRITE, to, n)))
283 n = __copy_user(to, from, n);
284 return n;
285}
286
287extern unsigned long __do_clear_user (void __user *, unsigned long);
288
289#define __clear_user(to, n) __do_clear_user(to, n)
290
291#define clear_user(to, n) \
292({ \
293 unsigned long __cu_len = (n); \
294 if (__access_ok(to, __cu_len, get_fs())) \
295 __cu_len = __do_clear_user(to, __cu_len); \
296 __cu_len; \
297})
298
299
300/*
301 * Returns: -EFAULT if exception before terminator, N if the entire buffer filled, else
302 * strlen.
303 */
304extern long __must_check __strncpy_from_user (char *to, const char __user *from, long to_len);
305
306#define strncpy_from_user(to, from, n) \
307({ \
308 const char __user * __sfu_from = (from); \
309 long __sfu_ret = -EFAULT; \
310 if (__access_ok(__sfu_from, 0, get_fs())) \
311 __sfu_ret = __strncpy_from_user((to), __sfu_from, (n)); \
312 __sfu_ret; \
313})
314
315/* Returns: 0 if bad, string length+1 (memory size) of string if ok */
316extern unsigned long __strlen_user (const char __user *);
317
318#define strlen_user(str) \
319({ \
320 const char __user *__su_str = (str); \
321 unsigned long __su_ret = 0; \
322 if (__access_ok(__su_str, 0, get_fs())) \
323 __su_ret = __strlen_user(__su_str); \
324 __su_ret; \
325})
326
327/*
328 * Returns: 0 if exception before NUL or reaching the supplied limit
329 * (N), a value greater than N if the limit would be exceeded, else
330 * strlen.
331 */
332extern unsigned long __strnlen_user (const char __user *, long);
333
334#define strnlen_user(str, len) \
335({ \
336 const char __user *__su_str = (str); \
337 unsigned long __su_ret = 0; \
338 if (__access_ok(__su_str, 0, get_fs())) \
339 __su_ret = __strnlen_user(__su_str, len); \
340 __su_ret; \
341})
342
343/* Generic code can't deal with the location-relative format that we use for compactness. */
344#define ARCH_HAS_SORT_EXTABLE
345#define ARCH_HAS_SEARCH_EXTABLE
346
347struct exception_table_entry {
348 int addr; /* location-relative address of insn this fixup is for */
349 int cont; /* location-relative continuation addr.; if bit 2 is set, r9 is set to 0 */
350};
351
352extern void ia64_handle_exception (struct pt_regs *regs, const struct exception_table_entry *e);
353extern const struct exception_table_entry *search_exception_tables (unsigned long addr);
354
355static inline int
356ia64_done_with_exception (struct pt_regs *regs)
357{
358 const struct exception_table_entry *e;
359 e = search_exception_tables(regs->cr_iip + ia64_psr(regs)->ri);
360 if (e) {
361 ia64_handle_exception(regs, e);
362 return 1;
363 }
364 return 0;
365}
366
367#define ARCH_HAS_TRANSLATE_MEM_PTR 1
368static __inline__ char *
369xlate_dev_mem_ptr (unsigned long p)
370{
371 struct page *page;
372 char * ptr;
373
374 page = pfn_to_page(p >> PAGE_SHIFT);
375 if (PageUncached(page))
376 ptr = (char *)p + __IA64_UNCACHED_OFFSET;
377 else
378 ptr = __va(p);
379
380 return ptr;
381}
382
383/*
384 * Convert a virtual cached kernel memory pointer to an uncached pointer
385 */
386static __inline__ char *
387xlate_dev_kmem_ptr (char * p)
388{
389 struct page *page;
390 char * ptr;
391
392 page = virt_to_page((unsigned long)p);
393 if (PageUncached(page))
394 ptr = (char *)__pa(p) + __IA64_UNCACHED_OFFSET;
395 else
396 ptr = p;
397
398 return ptr;
399}
400
401#endif /* _ASM_IA64_UACCESS_H */
diff --git a/include/asm-ia64/ucontext.h b/include/asm-ia64/ucontext.h
deleted file mode 100644
index bf573dc8ca6..00000000000
--- a/include/asm-ia64/ucontext.h
+++ /dev/null
@@ -1,12 +0,0 @@
1#ifndef _ASM_IA64_UCONTEXT_H
2#define _ASM_IA64_UCONTEXT_H
3
4struct ucontext {
5 struct sigcontext uc_mcontext;
6};
7
8#define uc_link uc_mcontext.sc_gr[0] /* wrong type; nobody cares */
9#define uc_sigmask uc_mcontext.sc_sigmask
10#define uc_stack uc_mcontext.sc_stack
11
12#endif /* _ASM_IA64_UCONTEXT_H */
diff --git a/include/asm-ia64/unaligned.h b/include/asm-ia64/unaligned.h
deleted file mode 100644
index 7bddc7f5858..00000000000
--- a/include/asm-ia64/unaligned.h
+++ /dev/null
@@ -1,11 +0,0 @@
1#ifndef _ASM_IA64_UNALIGNED_H
2#define _ASM_IA64_UNALIGNED_H
3
4#include <linux/unaligned/le_struct.h>
5#include <linux/unaligned/be_byteshift.h>
6#include <linux/unaligned/generic.h>
7
8#define get_unaligned __get_unaligned_le
9#define put_unaligned __put_unaligned_le
10
11#endif /* _ASM_IA64_UNALIGNED_H */
diff --git a/include/asm-ia64/uncached.h b/include/asm-ia64/uncached.h
deleted file mode 100644
index 13d7e65ca3c..00000000000
--- a/include/asm-ia64/uncached.h
+++ /dev/null
@@ -1,12 +0,0 @@
1/*
2 * Copyright (C) 2001-2008 Silicon Graphics, Inc. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 *
8 * Prototypes for the uncached page allocator
9 */
10
11extern unsigned long uncached_alloc_page(int starting_nid, int n_pages);
12extern void uncached_free_page(unsigned long uc_addr, int n_pages);
diff --git a/include/asm-ia64/unistd.h b/include/asm-ia64/unistd.h
deleted file mode 100644
index d535833aab5..00000000000
--- a/include/asm-ia64/unistd.h
+++ /dev/null
@@ -1,384 +0,0 @@
1#ifndef _ASM_IA64_UNISTD_H
2#define _ASM_IA64_UNISTD_H
3
4/*
5 * IA-64 Linux syscall numbers and inline-functions.
6 *
7 * Copyright (C) 1998-2005 Hewlett-Packard Co
8 * David Mosberger-Tang <davidm@hpl.hp.com>
9 */
10
11#include <asm/break.h>
12
13#define __BREAK_SYSCALL __IA64_BREAK_SYSCALL
14
15#define __NR_ni_syscall 1024
16#define __NR_exit 1025
17#define __NR_read 1026
18#define __NR_write 1027
19#define __NR_open 1028
20#define __NR_close 1029
21#define __NR_creat 1030
22#define __NR_link 1031
23#define __NR_unlink 1032
24#define __NR_execve 1033
25#define __NR_chdir 1034
26#define __NR_fchdir 1035
27#define __NR_utimes 1036
28#define __NR_mknod 1037
29#define __NR_chmod 1038
30#define __NR_chown 1039
31#define __NR_lseek 1040
32#define __NR_getpid 1041
33#define __NR_getppid 1042
34#define __NR_mount 1043
35#define __NR_umount 1044
36#define __NR_setuid 1045
37#define __NR_getuid 1046
38#define __NR_geteuid 1047
39#define __NR_ptrace 1048
40#define __NR_access 1049
41#define __NR_sync 1050
42#define __NR_fsync 1051
43#define __NR_fdatasync 1052
44#define __NR_kill 1053
45#define __NR_rename 1054
46#define __NR_mkdir 1055
47#define __NR_rmdir 1056
48#define __NR_dup 1057
49#define __NR_pipe 1058
50#define __NR_times 1059
51#define __NR_brk 1060
52#define __NR_setgid 1061
53#define __NR_getgid 1062
54#define __NR_getegid 1063
55#define __NR_acct 1064
56#define __NR_ioctl 1065
57#define __NR_fcntl 1066
58#define __NR_umask 1067
59#define __NR_chroot 1068
60#define __NR_ustat 1069
61#define __NR_dup2 1070
62#define __NR_setreuid 1071
63#define __NR_setregid 1072
64#define __NR_getresuid 1073
65#define __NR_setresuid 1074
66#define __NR_getresgid 1075
67#define __NR_setresgid 1076
68#define __NR_getgroups 1077
69#define __NR_setgroups 1078
70#define __NR_getpgid 1079
71#define __NR_setpgid 1080
72#define __NR_setsid 1081
73#define __NR_getsid 1082
74#define __NR_sethostname 1083
75#define __NR_setrlimit 1084
76#define __NR_getrlimit 1085
77#define __NR_getrusage 1086
78#define __NR_gettimeofday 1087
79#define __NR_settimeofday 1088
80#define __NR_select 1089
81#define __NR_poll 1090
82#define __NR_symlink 1091
83#define __NR_readlink 1092
84#define __NR_uselib 1093
85#define __NR_swapon 1094
86#define __NR_swapoff 1095
87#define __NR_reboot 1096
88#define __NR_truncate 1097
89#define __NR_ftruncate 1098
90#define __NR_fchmod 1099
91#define __NR_fchown 1100
92#define __NR_getpriority 1101
93#define __NR_setpriority 1102
94#define __NR_statfs 1103
95#define __NR_fstatfs 1104
96#define __NR_gettid 1105
97#define __NR_semget 1106
98#define __NR_semop 1107
99#define __NR_semctl 1108
100#define __NR_msgget 1109
101#define __NR_msgsnd 1110
102#define __NR_msgrcv 1111
103#define __NR_msgctl 1112
104#define __NR_shmget 1113
105#define __NR_shmat 1114
106#define __NR_shmdt 1115
107#define __NR_shmctl 1116
108/* also known as klogctl() in GNU libc: */
109#define __NR_syslog 1117
110#define __NR_setitimer 1118
111#define __NR_getitimer 1119
112/* 1120 was __NR_old_stat */
113/* 1121 was __NR_old_lstat */
114/* 1122 was __NR_old_fstat */
115#define __NR_vhangup 1123
116#define __NR_lchown 1124
117#define __NR_remap_file_pages 1125
118#define __NR_wait4 1126
119#define __NR_sysinfo 1127
120#define __NR_clone 1128
121#define __NR_setdomainname 1129
122#define __NR_uname 1130
123#define __NR_adjtimex 1131
124/* 1132 was __NR_create_module */
125#define __NR_init_module 1133
126#define __NR_delete_module 1134
127/* 1135 was __NR_get_kernel_syms */
128/* 1136 was __NR_query_module */
129#define __NR_quotactl 1137
130#define __NR_bdflush 1138
131#define __NR_sysfs 1139
132#define __NR_personality 1140
133#define __NR_afs_syscall 1141
134#define __NR_setfsuid 1142
135#define __NR_setfsgid 1143
136#define __NR_getdents 1144
137#define __NR_flock 1145
138#define __NR_readv 1146
139#define __NR_writev 1147
140#define __NR_pread64 1148
141#define __NR_pwrite64 1149
142#define __NR__sysctl 1150
143#define __NR_mmap 1151
144#define __NR_munmap 1152
145#define __NR_mlock 1153
146#define __NR_mlockall 1154
147#define __NR_mprotect 1155
148#define __NR_mremap 1156
149#define __NR_msync 1157
150#define __NR_munlock 1158
151#define __NR_munlockall 1159
152#define __NR_sched_getparam 1160
153#define __NR_sched_setparam 1161
154#define __NR_sched_getscheduler 1162
155#define __NR_sched_setscheduler 1163
156#define __NR_sched_yield 1164
157#define __NR_sched_get_priority_max 1165
158#define __NR_sched_get_priority_min 1166
159#define __NR_sched_rr_get_interval 1167
160#define __NR_nanosleep 1168
161#define __NR_nfsservctl 1169
162#define __NR_prctl 1170
163/* 1171 is reserved for backwards compatibility with old __NR_getpagesize */
164#define __NR_mmap2 1172
165#define __NR_pciconfig_read 1173
166#define __NR_pciconfig_write 1174
167#define __NR_perfmonctl 1175
168#define __NR_sigaltstack 1176
169#define __NR_rt_sigaction 1177
170#define __NR_rt_sigpending 1178
171#define __NR_rt_sigprocmask 1179
172#define __NR_rt_sigqueueinfo 1180
173#define __NR_rt_sigreturn 1181
174#define __NR_rt_sigsuspend 1182
175#define __NR_rt_sigtimedwait 1183
176#define __NR_getcwd 1184
177#define __NR_capget 1185
178#define __NR_capset 1186
179#define __NR_sendfile 1187
180#define __NR_getpmsg 1188
181#define __NR_putpmsg 1189
182#define __NR_socket 1190
183#define __NR_bind 1191
184#define __NR_connect 1192
185#define __NR_listen 1193
186#define __NR_accept 1194
187#define __NR_getsockname 1195
188#define __NR_getpeername 1196
189#define __NR_socketpair 1197
190#define __NR_send 1198
191#define __NR_sendto 1199
192#define __NR_recv 1200
193#define __NR_recvfrom 1201
194#define __NR_shutdown 1202
195#define __NR_setsockopt 1203
196#define __NR_getsockopt 1204
197#define __NR_sendmsg 1205
198#define __NR_recvmsg 1206
199#define __NR_pivot_root 1207
200#define __NR_mincore 1208
201#define __NR_madvise 1209
202#define __NR_stat 1210
203#define __NR_lstat 1211
204#define __NR_fstat 1212
205#define __NR_clone2 1213
206#define __NR_getdents64 1214
207#define __NR_getunwind 1215
208#define __NR_readahead 1216
209#define __NR_setxattr 1217
210#define __NR_lsetxattr 1218
211#define __NR_fsetxattr 1219
212#define __NR_getxattr 1220
213#define __NR_lgetxattr 1221
214#define __NR_fgetxattr 1222
215#define __NR_listxattr 1223
216#define __NR_llistxattr 1224
217#define __NR_flistxattr 1225
218#define __NR_removexattr 1226
219#define __NR_lremovexattr 1227
220#define __NR_fremovexattr 1228
221#define __NR_tkill 1229
222#define __NR_futex 1230
223#define __NR_sched_setaffinity 1231
224#define __NR_sched_getaffinity 1232
225#define __NR_set_tid_address 1233
226#define __NR_fadvise64 1234
227#define __NR_tgkill 1235
228#define __NR_exit_group 1236
229#define __NR_lookup_dcookie 1237
230#define __NR_io_setup 1238
231#define __NR_io_destroy 1239
232#define __NR_io_getevents 1240
233#define __NR_io_submit 1241
234#define __NR_io_cancel 1242
235#define __NR_epoll_create 1243
236#define __NR_epoll_ctl 1244
237#define __NR_epoll_wait 1245
238#define __NR_restart_syscall 1246
239#define __NR_semtimedop 1247
240#define __NR_timer_create 1248
241#define __NR_timer_settime 1249
242#define __NR_timer_gettime 1250
243#define __NR_timer_getoverrun 1251
244#define __NR_timer_delete 1252
245#define __NR_clock_settime 1253
246#define __NR_clock_gettime 1254
247#define __NR_clock_getres 1255
248#define __NR_clock_nanosleep 1256
249#define __NR_fstatfs64 1257
250#define __NR_statfs64 1258
251#define __NR_mbind 1259
252#define __NR_get_mempolicy 1260
253#define __NR_set_mempolicy 1261
254#define __NR_mq_open 1262
255#define __NR_mq_unlink 1263
256#define __NR_mq_timedsend 1264
257#define __NR_mq_timedreceive 1265
258#define __NR_mq_notify 1266
259#define __NR_mq_getsetattr 1267
260#define __NR_kexec_load 1268
261#define __NR_vserver 1269
262#define __NR_waitid 1270
263#define __NR_add_key 1271
264#define __NR_request_key 1272
265#define __NR_keyctl 1273
266#define __NR_ioprio_set 1274
267#define __NR_ioprio_get 1275
268#define __NR_move_pages 1276
269#define __NR_inotify_init 1277
270#define __NR_inotify_add_watch 1278
271#define __NR_inotify_rm_watch 1279
272#define __NR_migrate_pages 1280
273#define __NR_openat 1281
274#define __NR_mkdirat 1282
275#define __NR_mknodat 1283
276#define __NR_fchownat 1284
277#define __NR_futimesat 1285
278#define __NR_newfstatat 1286
279#define __NR_unlinkat 1287
280#define __NR_renameat 1288
281#define __NR_linkat 1289
282#define __NR_symlinkat 1290
283#define __NR_readlinkat 1291
284#define __NR_fchmodat 1292
285#define __NR_faccessat 1293
286#define __NR_pselect6 1294
287#define __NR_ppoll 1295
288#define __NR_unshare 1296
289#define __NR_splice 1297
290#define __NR_set_robust_list 1298
291#define __NR_get_robust_list 1299
292#define __NR_sync_file_range 1300
293#define __NR_tee 1301
294#define __NR_vmsplice 1302
295#define __NR_fallocate 1303
296#define __NR_getcpu 1304
297#define __NR_epoll_pwait 1305
298#define __NR_utimensat 1306
299#define __NR_signalfd 1307
300#define __NR_timerfd 1308
301#define __NR_eventfd 1309
302#define __NR_timerfd_create 1310
303#define __NR_timerfd_settime 1311
304#define __NR_timerfd_gettime 1312
305#define __NR_signalfd4 1313
306#define __NR_eventfd2 1314
307#define __NR_epoll_create1 1315
308#define __NR_dup3 1316
309#define __NR_pipe2 1317
310#define __NR_inotify_init1 1318
311
312#ifdef __KERNEL__
313
314
315#define NR_syscalls 295 /* length of syscall table */
316
317/*
318 * The following defines stop scripts/checksyscalls.sh from complaining about
319 * unimplemented system calls. Glibc provides for each of these by using
320 * more modern equivalent system calls.
321 */
322#define __IGNORE_fork /* clone() */
323#define __IGNORE_time /* gettimeofday() */
324#define __IGNORE_alarm /* setitimer(ITIMER_REAL, ... */
325#define __IGNORE_pause /* rt_sigprocmask(), rt_sigsuspend() */
326#define __IGNORE_utime /* utimes() */
327#define __IGNORE_getpgrp /* getpgid() */
328#define __IGNORE_vfork /* clone() */
329
330#define __ARCH_WANT_SYS_RT_SIGACTION
331#define __ARCH_WANT_SYS_RT_SIGSUSPEND
332
333#ifdef CONFIG_IA32_SUPPORT
334# define __ARCH_WANT_SYS_FADVISE64
335# define __ARCH_WANT_SYS_GETPGRP
336# define __ARCH_WANT_SYS_LLSEEK
337# define __ARCH_WANT_SYS_NICE
338# define __ARCH_WANT_SYS_OLD_GETRLIMIT
339# define __ARCH_WANT_SYS_OLDUMOUNT
340# define __ARCH_WANT_SYS_SIGPENDING
341# define __ARCH_WANT_SYS_SIGPROCMASK
342# define __ARCH_WANT_COMPAT_SYS_RT_SIGSUSPEND
343# define __ARCH_WANT_COMPAT_SYS_TIME
344#endif
345
346#if !defined(__ASSEMBLY__) && !defined(ASSEMBLER)
347
348#include <linux/types.h>
349#include <linux/linkage.h>
350#include <linux/compiler.h>
351
352extern long __ia64_syscall (long a0, long a1, long a2, long a3, long a4, long nr);
353
354asmlinkage unsigned long sys_mmap(
355 unsigned long addr, unsigned long len,
356 int prot, int flags,
357 int fd, long off);
358asmlinkage unsigned long sys_mmap2(
359 unsigned long addr, unsigned long len,
360 int prot, int flags,
361 int fd, long pgoff);
362struct pt_regs;
363struct sigaction;
364long sys_execve(char __user *filename, char __user * __user *argv,
365 char __user * __user *envp, struct pt_regs *regs);
366asmlinkage long sys_pipe(void);
367asmlinkage long sys_rt_sigaction(int sig,
368 const struct sigaction __user *act,
369 struct sigaction __user *oact,
370 size_t sigsetsize);
371
372/*
373 * "Conditional" syscalls
374 *
375 * Note, this macro can only be used in the file which defines sys_ni_syscall, i.e., in
376 * kernel/sys_ni.c. This version causes warnings because the declaration isn't a
377 * proper prototype, but we can't use __typeof__ either, because not all cond_syscall()
378 * declarations have prototypes at the moment.
379 */
380#define cond_syscall(x) asmlinkage long x (void) __attribute__((weak,alias("sys_ni_syscall")))
381
382#endif /* !__ASSEMBLY__ */
383#endif /* __KERNEL__ */
384#endif /* _ASM_IA64_UNISTD_H */
diff --git a/include/asm-ia64/unwind.h b/include/asm-ia64/unwind.h
deleted file mode 100644
index 1af3875f1a5..00000000000
--- a/include/asm-ia64/unwind.h
+++ /dev/null
@@ -1,233 +0,0 @@
1#ifndef _ASM_IA64_UNWIND_H
2#define _ASM_IA64_UNWIND_H
3
4/*
5 * Copyright (C) 1999-2000, 2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 *
8 * A simple API for unwinding kernel stacks. This is used for
9 * debugging and error reporting purposes. The kernel doesn't need
10 * full-blown stack unwinding with all the bells and whitles, so there
11 * is not much point in implementing the full IA-64 unwind API (though
12 * it would of course be possible to implement the kernel API on top
13 * of it).
14 */
15
16struct task_struct; /* forward declaration */
17struct switch_stack; /* forward declaration */
18
19enum unw_application_register {
20 UNW_AR_BSP,
21 UNW_AR_BSPSTORE,
22 UNW_AR_PFS,
23 UNW_AR_RNAT,
24 UNW_AR_UNAT,
25 UNW_AR_LC,
26 UNW_AR_EC,
27 UNW_AR_FPSR,
28 UNW_AR_RSC,
29 UNW_AR_CCV,
30 UNW_AR_CSD,
31 UNW_AR_SSD
32};
33
34/*
35 * The following declarations are private to the unwind
36 * implementation:
37 */
38
39struct unw_stack {
40 unsigned long limit;
41 unsigned long top;
42};
43
44#define UNW_FLAG_INTERRUPT_FRAME (1UL << 0)
45
46/*
47 * No user of this module should every access this structure directly
48 * as it is subject to change. It is declared here solely so we can
49 * use automatic variables.
50 */
51struct unw_frame_info {
52 struct unw_stack regstk;
53 struct unw_stack memstk;
54 unsigned int flags;
55 short hint;
56 short prev_script;
57
58 /* current frame info: */
59 unsigned long bsp; /* backing store pointer value */
60 unsigned long sp; /* stack pointer value */
61 unsigned long psp; /* previous sp value */
62 unsigned long ip; /* instruction pointer value */
63 unsigned long pr; /* current predicate values */
64 unsigned long *cfm_loc; /* cfm save location (or NULL) */
65 unsigned long pt; /* struct pt_regs location */
66
67 struct task_struct *task;
68 struct switch_stack *sw;
69
70 /* preserved state: */
71 unsigned long *bsp_loc; /* previous bsp save location */
72 unsigned long *bspstore_loc;
73 unsigned long *pfs_loc;
74 unsigned long *rnat_loc;
75 unsigned long *rp_loc;
76 unsigned long *pri_unat_loc;
77 unsigned long *unat_loc;
78 unsigned long *pr_loc;
79 unsigned long *lc_loc;
80 unsigned long *fpsr_loc;
81 struct unw_ireg {
82 unsigned long *loc;
83 struct unw_ireg_nat {
84 unsigned long type : 3; /* enum unw_nat_type */
85 signed long off : 61; /* NaT word is at loc+nat.off */
86 } nat;
87 } r4, r5, r6, r7;
88 unsigned long *b1_loc, *b2_loc, *b3_loc, *b4_loc, *b5_loc;
89 struct ia64_fpreg *f2_loc, *f3_loc, *f4_loc, *f5_loc, *fr_loc[16];
90};
91
92/*
93 * The official API follows below:
94 */
95
96struct unw_table_entry {
97 u64 start_offset;
98 u64 end_offset;
99 u64 info_offset;
100};
101
102/*
103 * Initialize unwind support.
104 */
105extern void unw_init (void);
106
107extern void *unw_add_unwind_table (const char *name, unsigned long segment_base, unsigned long gp,
108 const void *table_start, const void *table_end);
109
110extern void unw_remove_unwind_table (void *handle);
111
112/*
113 * Prepare to unwind blocked task t.
114 */
115extern void unw_init_from_blocked_task (struct unw_frame_info *info, struct task_struct *t);
116
117extern void unw_init_frame_info (struct unw_frame_info *info, struct task_struct *t,
118 struct switch_stack *sw);
119
120/*
121 * Prepare to unwind the currently running thread.
122 */
123extern void unw_init_running (void (*callback)(struct unw_frame_info *info, void *arg), void *arg);
124
125/*
126 * Unwind to previous to frame. Returns 0 if successful, negative
127 * number in case of an error.
128 */
129extern int unw_unwind (struct unw_frame_info *info);
130
131/*
132 * Unwind until the return pointer is in user-land (or until an error
133 * occurs). Returns 0 if successful, negative number in case of
134 * error.
135 */
136extern int unw_unwind_to_user (struct unw_frame_info *info);
137
138#define unw_is_intr_frame(info) (((info)->flags & UNW_FLAG_INTERRUPT_FRAME) != 0)
139
140static inline int
141unw_get_ip (struct unw_frame_info *info, unsigned long *valp)
142{
143 *valp = (info)->ip;
144 return 0;
145}
146
147static inline int
148unw_get_sp (struct unw_frame_info *info, unsigned long *valp)
149{
150 *valp = (info)->sp;
151 return 0;
152}
153
154static inline int
155unw_get_psp (struct unw_frame_info *info, unsigned long *valp)
156{
157 *valp = (info)->psp;
158 return 0;
159}
160
161static inline int
162unw_get_bsp (struct unw_frame_info *info, unsigned long *valp)
163{
164 *valp = (info)->bsp;
165 return 0;
166}
167
168static inline int
169unw_get_cfm (struct unw_frame_info *info, unsigned long *valp)
170{
171 *valp = *(info)->cfm_loc;
172 return 0;
173}
174
175static inline int
176unw_set_cfm (struct unw_frame_info *info, unsigned long val)
177{
178 *(info)->cfm_loc = val;
179 return 0;
180}
181
182static inline int
183unw_get_rp (struct unw_frame_info *info, unsigned long *val)
184{
185 if (!info->rp_loc)
186 return -1;
187 *val = *info->rp_loc;
188 return 0;
189}
190
191extern int unw_access_gr (struct unw_frame_info *, int, unsigned long *, char *, int);
192extern int unw_access_br (struct unw_frame_info *, int, unsigned long *, int);
193extern int unw_access_fr (struct unw_frame_info *, int, struct ia64_fpreg *, int);
194extern int unw_access_ar (struct unw_frame_info *, int, unsigned long *, int);
195extern int unw_access_pr (struct unw_frame_info *, unsigned long *, int);
196
197static inline int
198unw_set_gr (struct unw_frame_info *i, int n, unsigned long v, char nat)
199{
200 return unw_access_gr(i, n, &v, &nat, 1);
201}
202
203static inline int
204unw_set_br (struct unw_frame_info *i, int n, unsigned long v)
205{
206 return unw_access_br(i, n, &v, 1);
207}
208
209static inline int
210unw_set_fr (struct unw_frame_info *i, int n, struct ia64_fpreg v)
211{
212 return unw_access_fr(i, n, &v, 1);
213}
214
215static inline int
216unw_set_ar (struct unw_frame_info *i, int n, unsigned long v)
217{
218 return unw_access_ar(i, n, &v, 1);
219}
220
221static inline int
222unw_set_pr (struct unw_frame_info *i, unsigned long v)
223{
224 return unw_access_pr(i, &v, 1);
225}
226
227#define unw_get_gr(i,n,v,nat) unw_access_gr(i,n,v,nat,0)
228#define unw_get_br(i,n,v) unw_access_br(i,n,v,0)
229#define unw_get_fr(i,n,v) unw_access_fr(i,n,v,0)
230#define unw_get_ar(i,n,v) unw_access_ar(i,n,v,0)
231#define unw_get_pr(i,v) unw_access_pr(i,v,0)
232
233#endif /* _ASM_UNWIND_H */
diff --git a/include/asm-ia64/user.h b/include/asm-ia64/user.h
deleted file mode 100644
index 8b982111034..00000000000
--- a/include/asm-ia64/user.h
+++ /dev/null
@@ -1,58 +0,0 @@
1#ifndef _ASM_IA64_USER_H
2#define _ASM_IA64_USER_H
3
4/*
5 * Core file format: The core file is written in such a way that gdb
6 * can understand it and provide useful information to the user (under
7 * linux we use the `trad-core' bfd). The file contents are as
8 * follows:
9 *
10 * upage: 1 page consisting of a user struct that tells gdb
11 * what is present in the file. Directly after this is a
12 * copy of the task_struct, which is currently not used by gdb,
13 * but it may come in handy at some point. All of the registers
14 * are stored as part of the upage. The upage should always be
15 * only one page long.
16 * data: The data segment follows next. We use current->end_text to
17 * current->brk to pick up all of the user variables, plus any memory
18 * that may have been sbrk'ed. No attempt is made to determine if a
19 * page is demand-zero or if a page is totally unused, we just cover
20 * the entire range. All of the addresses are rounded in such a way
21 * that an integral number of pages is written.
22 * stack: We need the stack information in order to get a meaningful
23 * backtrace. We need to write the data from usp to
24 * current->start_stack, so we round each of these in order to be able
25 * to write an integer number of pages.
26 *
27 * Modified 1998, 1999, 2001
28 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
29 */
30
31#include <linux/ptrace.h>
32#include <linux/types.h>
33
34#include <asm/page.h>
35
36#define EF_SIZE 3072 /* XXX fix me */
37
38struct user {
39 unsigned long regs[EF_SIZE/8+32]; /* integer and fp regs */
40 size_t u_tsize; /* text size (pages) */
41 size_t u_dsize; /* data size (pages) */
42 size_t u_ssize; /* stack size (pages) */
43 unsigned long start_code; /* text starting address */
44 unsigned long start_data; /* data starting address */
45 unsigned long start_stack; /* stack starting address */
46 long int signal; /* signal causing core dump */
47 unsigned long u_ar0; /* help gdb find registers */
48 unsigned long magic; /* identifies a core file */
49 char u_comm[32]; /* user command name */
50};
51
52#define NBPG PAGE_SIZE
53#define UPAGES 1
54#define HOST_TEXT_START_ADDR (u.start_code)
55#define HOST_DATA_START_ADDR (u.start_data)
56#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
57
58#endif /* _ASM_IA64_USER_H */
diff --git a/include/asm-ia64/ustack.h b/include/asm-ia64/ustack.h
deleted file mode 100644
index 504167c35b8..00000000000
--- a/include/asm-ia64/ustack.h
+++ /dev/null
@@ -1,20 +0,0 @@
1#ifndef _ASM_IA64_USTACK_H
2#define _ASM_IA64_USTACK_H
3
4/*
5 * Constants for the user stack size
6 */
7
8#ifdef __KERNEL__
9#include <asm/page.h>
10
11/* The absolute hard limit for stack size is 1/2 of the mappable space in the region */
12#define MAX_USER_STACK_SIZE (RGN_MAP_LIMIT/2)
13#define STACK_TOP (0x6000000000000000UL + RGN_MAP_LIMIT)
14#define STACK_TOP_MAX STACK_TOP
15#endif
16
17/* Make a default stack size of 2GiB */
18#define DEFAULT_USER_STACK_SIZE (1UL << 31)
19
20#endif /* _ASM_IA64_USTACK_H */
diff --git a/include/asm-ia64/uv/uv_hub.h b/include/asm-ia64/uv/uv_hub.h
deleted file mode 100644
index f607018af4a..00000000000
--- a/include/asm-ia64/uv/uv_hub.h
+++ /dev/null
@@ -1,309 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV architectural definitions
7 *
8 * Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved.
9 */
10
11#ifndef __ASM_IA64_UV_HUB_H__
12#define __ASM_IA64_UV_HUB_H__
13
14#include <linux/numa.h>
15#include <linux/percpu.h>
16#include <asm/types.h>
17#include <asm/percpu.h>
18
19
20/*
21 * Addressing Terminology
22 *
23 * M - The low M bits of a physical address represent the offset
24 * into the blade local memory. RAM memory on a blade is physically
25 * contiguous (although various IO spaces may punch holes in
26 * it)..
27 *
28 * N - Number of bits in the node portion of a socket physical
29 * address.
30 *
31 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
32 * routers always have low bit of 1, C/MBricks have low bit
33 * equal to 0. Most addressing macros that target UV hub chips
34 * right shift the NASID by 1 to exclude the always-zero bit.
35 * NASIDs contain up to 15 bits.
36 *
37 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
38 * of nasids.
39 *
40 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
41 * of the nasid for socket usage.
42 *
43 *
44 * NumaLink Global Physical Address Format:
45 * +--------------------------------+---------------------+
46 * |00..000| GNODE | NodeOffset |
47 * +--------------------------------+---------------------+
48 * |<-------53 - M bits --->|<--------M bits ----->
49 *
50 * M - number of node offset bits (35 .. 40)
51 *
52 *
53 * Memory/UV-HUB Processor Socket Address Format:
54 * +----------------+---------------+---------------------+
55 * |00..000000000000| PNODE | NodeOffset |
56 * +----------------+---------------+---------------------+
57 * <--- N bits --->|<--------M bits ----->
58 *
59 * M - number of node offset bits (35 .. 40)
60 * N - number of PNODE bits (0 .. 10)
61 *
62 * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).
63 * The actual values are configuration dependent and are set at
64 * boot time. M & N values are set by the hardware/BIOS at boot.
65 */
66
67
68/*
69 * Maximum number of bricks in all partitions and in all coherency domains.
70 * This is the total number of bricks accessible in the numalink fabric. It
71 * includes all C & M bricks. Routers are NOT included.
72 *
73 * This value is also the value of the maximum number of non-router NASIDs
74 * in the numalink fabric.
75 *
76 * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused.
77 */
78#define UV_MAX_NUMALINK_BLADES 16384
79
80/*
81 * Maximum number of C/Mbricks within a software SSI (hardware may support
82 * more).
83 */
84#define UV_MAX_SSI_BLADES 1
85
86/*
87 * The largest possible NASID of a C or M brick (+ 2)
88 */
89#define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_NODES * 2)
90
91/*
92 * The following defines attributes of the HUB chip. These attributes are
93 * frequently referenced and are kept in the per-cpu data areas of each cpu.
94 * They are kept together in a struct to minimize cache misses.
95 */
96struct uv_hub_info_s {
97 unsigned long global_mmr_base;
98 unsigned long gpa_mask;
99 unsigned long gnode_upper;
100 unsigned long lowmem_remap_top;
101 unsigned long lowmem_remap_base;
102 unsigned short pnode;
103 unsigned short pnode_mask;
104 unsigned short coherency_domain_number;
105 unsigned short numa_blade_id;
106 unsigned char blade_processor_id;
107 unsigned char m_val;
108 unsigned char n_val;
109};
110DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
111#define uv_hub_info (&__get_cpu_var(__uv_hub_info))
112#define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu))
113
114/*
115 * Local & Global MMR space macros.
116 * Note: macros are intended to be used ONLY by inline functions
117 * in this file - not by other kernel code.
118 * n - NASID (full 15-bit global nasid)
119 * g - GNODE (full 15-bit global nasid, right shifted 1)
120 * p - PNODE (local part of nsids, right shifted 1)
121 */
122#define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask)
123#define UV_PNODE_TO_NASID(p) (((p) << 1) | uv_hub_info->gnode_upper)
124
125#define UV_LOCAL_MMR_BASE 0xf4000000UL
126#define UV_GLOBAL_MMR32_BASE 0xf8000000UL
127#define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base)
128
129#define UV_GLOBAL_MMR32_PNODE_SHIFT 15
130#define UV_GLOBAL_MMR64_PNODE_SHIFT 26
131
132#define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))
133
134#define UV_GLOBAL_MMR64_PNODE_BITS(p) \
135 ((unsigned long)(p) << UV_GLOBAL_MMR64_PNODE_SHIFT)
136
137/*
138 * Macros for converting between kernel virtual addresses, socket local physical
139 * addresses, and UV global physical addresses.
140 * Note: use the standard __pa() & __va() macros for converting
141 * between socket virtual and socket physical addresses.
142 */
143
144/* socket phys RAM --> UV global physical address */
145static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
146{
147 if (paddr < uv_hub_info->lowmem_remap_top)
148 paddr += uv_hub_info->lowmem_remap_base;
149 return paddr | uv_hub_info->gnode_upper;
150}
151
152
153/* socket virtual --> UV global physical address */
154static inline unsigned long uv_gpa(void *v)
155{
156 return __pa(v) | uv_hub_info->gnode_upper;
157}
158
159/* socket virtual --> UV global physical address */
160static inline void *uv_vgpa(void *v)
161{
162 return (void *)uv_gpa(v);
163}
164
165/* UV global physical address --> socket virtual */
166static inline void *uv_va(unsigned long gpa)
167{
168 return __va(gpa & uv_hub_info->gpa_mask);
169}
170
171/* pnode, offset --> socket virtual */
172static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
173{
174 return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset);
175}
176
177
178/*
179 * Access global MMRs using the low memory MMR32 space. This region supports
180 * faster MMR access but not all MMRs are accessible in this space.
181 */
182static inline unsigned long *uv_global_mmr32_address(int pnode,
183 unsigned long offset)
184{
185 return __va(UV_GLOBAL_MMR32_BASE |
186 UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset);
187}
188
189static inline void uv_write_global_mmr32(int pnode, unsigned long offset,
190 unsigned long val)
191{
192 *uv_global_mmr32_address(pnode, offset) = val;
193}
194
195static inline unsigned long uv_read_global_mmr32(int pnode,
196 unsigned long offset)
197{
198 return *uv_global_mmr32_address(pnode, offset);
199}
200
201/*
202 * Access Global MMR space using the MMR space located at the top of physical
203 * memory.
204 */
205static inline unsigned long *uv_global_mmr64_address(int pnode,
206 unsigned long offset)
207{
208 return __va(UV_GLOBAL_MMR64_BASE |
209 UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset);
210}
211
212static inline void uv_write_global_mmr64(int pnode, unsigned long offset,
213 unsigned long val)
214{
215 *uv_global_mmr64_address(pnode, offset) = val;
216}
217
218static inline unsigned long uv_read_global_mmr64(int pnode,
219 unsigned long offset)
220{
221 return *uv_global_mmr64_address(pnode, offset);
222}
223
224/*
225 * Access hub local MMRs. Faster than using global space but only local MMRs
226 * are accessible.
227 */
228static inline unsigned long *uv_local_mmr_address(unsigned long offset)
229{
230 return __va(UV_LOCAL_MMR_BASE | offset);
231}
232
233static inline unsigned long uv_read_local_mmr(unsigned long offset)
234{
235 return *uv_local_mmr_address(offset);
236}
237
238static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
239{
240 *uv_local_mmr_address(offset) = val;
241}
242
243/*
244 * Structures and definitions for converting between cpu, node, pnode, and blade
245 * numbers.
246 */
247
248/* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */
249static inline int uv_blade_processor_id(void)
250{
251 return smp_processor_id();
252}
253
254/* Blade number of current cpu. Numnbered 0 .. <#blades -1> */
255static inline int uv_numa_blade_id(void)
256{
257 return 0;
258}
259
260/* Convert a cpu number to the the UV blade number */
261static inline int uv_cpu_to_blade_id(int cpu)
262{
263 return 0;
264}
265
266/* Convert linux node number to the UV blade number */
267static inline int uv_node_to_blade_id(int nid)
268{
269 return 0;
270}
271
272/* Convert a blade id to the PNODE of the blade */
273static inline int uv_blade_to_pnode(int bid)
274{
275 return 0;
276}
277
278/* Determine the number of possible cpus on a blade */
279static inline int uv_blade_nr_possible_cpus(int bid)
280{
281 return num_possible_cpus();
282}
283
284/* Determine the number of online cpus on a blade */
285static inline int uv_blade_nr_online_cpus(int bid)
286{
287 return num_online_cpus();
288}
289
290/* Convert a cpu id to the PNODE of the blade containing the cpu */
291static inline int uv_cpu_to_pnode(int cpu)
292{
293 return 0;
294}
295
296/* Convert a linux node number to the PNODE of the blade */
297static inline int uv_node_to_pnode(int nid)
298{
299 return 0;
300}
301
302/* Maximum possible number of blades */
303static inline int uv_num_possible_blades(void)
304{
305 return 1;
306}
307
308#endif /* __ASM_IA64_UV_HUB__ */
309
diff --git a/include/asm-ia64/uv/uv_mmrs.h b/include/asm-ia64/uv/uv_mmrs.h
deleted file mode 100644
index c149ef08543..00000000000
--- a/include/asm-ia64/uv/uv_mmrs.h
+++ /dev/null
@@ -1,673 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV MMR definitions
7 *
8 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
9 */
10
11#ifndef __ASM_IA64_UV_MMRS__
12#define __ASM_IA64_UV_MMRS__
13
14#define UV_MMR_ENABLE (1UL << 63)
15
16/* ========================================================================= */
17/* UVH_BAU_DATA_CONFIG */
18/* ========================================================================= */
19#define UVH_BAU_DATA_CONFIG 0x61680UL
20#define UVH_BAU_DATA_CONFIG_32 0x0438
21
22#define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0
23#define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL
24#define UVH_BAU_DATA_CONFIG_DM_SHFT 8
25#define UVH_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL
26#define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT 11
27#define UVH_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL
28#define UVH_BAU_DATA_CONFIG_STATUS_SHFT 12
29#define UVH_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL
30#define UVH_BAU_DATA_CONFIG_P_SHFT 13
31#define UVH_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL
32#define UVH_BAU_DATA_CONFIG_T_SHFT 15
33#define UVH_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL
34#define UVH_BAU_DATA_CONFIG_M_SHFT 16
35#define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL
36#define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT 32
37#define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
38
39union uvh_bau_data_config_u {
40 unsigned long v;
41 struct uvh_bau_data_config_s {
42 unsigned long vector_ : 8; /* RW */
43 unsigned long dm : 3; /* RW */
44 unsigned long destmode : 1; /* RW */
45 unsigned long status : 1; /* RO */
46 unsigned long p : 1; /* RO */
47 unsigned long rsvd_14 : 1; /* */
48 unsigned long t : 1; /* RO */
49 unsigned long m : 1; /* RW */
50 unsigned long rsvd_17_31: 15; /* */
51 unsigned long apic_id : 32; /* RW */
52 } s;
53};
54
55/* ========================================================================= */
56/* UVH_EVENT_OCCURRED0 */
57/* ========================================================================= */
58#define UVH_EVENT_OCCURRED0 0x70000UL
59#define UVH_EVENT_OCCURRED0_32 0x005e8
60
61#define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT 0
62#define UVH_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
63#define UVH_EVENT_OCCURRED0_GR0_HCERR_SHFT 1
64#define UVH_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL
65#define UVH_EVENT_OCCURRED0_GR1_HCERR_SHFT 2
66#define UVH_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL
67#define UVH_EVENT_OCCURRED0_LH_HCERR_SHFT 3
68#define UVH_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL
69#define UVH_EVENT_OCCURRED0_RH_HCERR_SHFT 4
70#define UVH_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL
71#define UVH_EVENT_OCCURRED0_XN_HCERR_SHFT 5
72#define UVH_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL
73#define UVH_EVENT_OCCURRED0_SI_HCERR_SHFT 6
74#define UVH_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL
75#define UVH_EVENT_OCCURRED0_LB_AOERR0_SHFT 7
76#define UVH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL
77#define UVH_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8
78#define UVH_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL
79#define UVH_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9
80#define UVH_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL
81#define UVH_EVENT_OCCURRED0_LH_AOERR0_SHFT 10
82#define UVH_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL
83#define UVH_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
84#define UVH_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
85#define UVH_EVENT_OCCURRED0_XN_AOERR0_SHFT 12
86#define UVH_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL
87#define UVH_EVENT_OCCURRED0_SI_AOERR0_SHFT 13
88#define UVH_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL
89#define UVH_EVENT_OCCURRED0_LB_AOERR1_SHFT 14
90#define UVH_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL
91#define UVH_EVENT_OCCURRED0_GR0_AOERR1_SHFT 15
92#define UVH_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL
93#define UVH_EVENT_OCCURRED0_GR1_AOERR1_SHFT 16
94#define UVH_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL
95#define UVH_EVENT_OCCURRED0_LH_AOERR1_SHFT 17
96#define UVH_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL
97#define UVH_EVENT_OCCURRED0_RH_AOERR1_SHFT 18
98#define UVH_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL
99#define UVH_EVENT_OCCURRED0_XN_AOERR1_SHFT 19
100#define UVH_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL
101#define UVH_EVENT_OCCURRED0_SI_AOERR1_SHFT 20
102#define UVH_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL
103#define UVH_EVENT_OCCURRED0_RH_VPI_INT_SHFT 21
104#define UVH_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL
105#define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 22
106#define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL
107#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 23
108#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL
109#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 24
110#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL
111#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 25
112#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL
113#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 26
114#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL
115#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 27
116#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL
117#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 28
118#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL
119#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 29
120#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL
121#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 30
122#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL
123#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 31
124#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL
125#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 32
126#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL
127#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 33
128#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL
129#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 34
130#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL
131#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 35
132#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL
133#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 36
134#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL
135#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 37
136#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL
137#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 38
138#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL
139#define UVH_EVENT_OCCURRED0_L1_NMI_INT_SHFT 39
140#define UVH_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL
141#define UVH_EVENT_OCCURRED0_STOP_CLOCK_SHFT 40
142#define UVH_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL
143#define UVH_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 41
144#define UVH_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL
145#define UVH_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 42
146#define UVH_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL
147#define UVH_EVENT_OCCURRED0_LTC_INT_SHFT 43
148#define UVH_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL
149#define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 44
150#define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL
151#define UVH_EVENT_OCCURRED0_IPI_INT_SHFT 45
152#define UVH_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL
153#define UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT 46
154#define UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL
155#define UVH_EVENT_OCCURRED0_EXTIO_INT1_SHFT 47
156#define UVH_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL
157#define UVH_EVENT_OCCURRED0_EXTIO_INT2_SHFT 48
158#define UVH_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL
159#define UVH_EVENT_OCCURRED0_EXTIO_INT3_SHFT 49
160#define UVH_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL
161#define UVH_EVENT_OCCURRED0_PROFILE_INT_SHFT 50
162#define UVH_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL
163#define UVH_EVENT_OCCURRED0_RTC0_SHFT 51
164#define UVH_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL
165#define UVH_EVENT_OCCURRED0_RTC1_SHFT 52
166#define UVH_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL
167#define UVH_EVENT_OCCURRED0_RTC2_SHFT 53
168#define UVH_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL
169#define UVH_EVENT_OCCURRED0_RTC3_SHFT 54
170#define UVH_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL
171#define UVH_EVENT_OCCURRED0_BAU_DATA_SHFT 55
172#define UVH_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL
173#define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56
174#define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL
175union uvh_event_occurred0_u {
176 unsigned long v;
177 struct uvh_event_occurred0_s {
178 unsigned long lb_hcerr : 1; /* RW, W1C */
179 unsigned long gr0_hcerr : 1; /* RW, W1C */
180 unsigned long gr1_hcerr : 1; /* RW, W1C */
181 unsigned long lh_hcerr : 1; /* RW, W1C */
182 unsigned long rh_hcerr : 1; /* RW, W1C */
183 unsigned long xn_hcerr : 1; /* RW, W1C */
184 unsigned long si_hcerr : 1; /* RW, W1C */
185 unsigned long lb_aoerr0 : 1; /* RW, W1C */
186 unsigned long gr0_aoerr0 : 1; /* RW, W1C */
187 unsigned long gr1_aoerr0 : 1; /* RW, W1C */
188 unsigned long lh_aoerr0 : 1; /* RW, W1C */
189 unsigned long rh_aoerr0 : 1; /* RW, W1C */
190 unsigned long xn_aoerr0 : 1; /* RW, W1C */
191 unsigned long si_aoerr0 : 1; /* RW, W1C */
192 unsigned long lb_aoerr1 : 1; /* RW, W1C */
193 unsigned long gr0_aoerr1 : 1; /* RW, W1C */
194 unsigned long gr1_aoerr1 : 1; /* RW, W1C */
195 unsigned long lh_aoerr1 : 1; /* RW, W1C */
196 unsigned long rh_aoerr1 : 1; /* RW, W1C */
197 unsigned long xn_aoerr1 : 1; /* RW, W1C */
198 unsigned long si_aoerr1 : 1; /* RW, W1C */
199 unsigned long rh_vpi_int : 1; /* RW, W1C */
200 unsigned long system_shutdown_int : 1; /* RW, W1C */
201 unsigned long lb_irq_int_0 : 1; /* RW, W1C */
202 unsigned long lb_irq_int_1 : 1; /* RW, W1C */
203 unsigned long lb_irq_int_2 : 1; /* RW, W1C */
204 unsigned long lb_irq_int_3 : 1; /* RW, W1C */
205 unsigned long lb_irq_int_4 : 1; /* RW, W1C */
206 unsigned long lb_irq_int_5 : 1; /* RW, W1C */
207 unsigned long lb_irq_int_6 : 1; /* RW, W1C */
208 unsigned long lb_irq_int_7 : 1; /* RW, W1C */
209 unsigned long lb_irq_int_8 : 1; /* RW, W1C */
210 unsigned long lb_irq_int_9 : 1; /* RW, W1C */
211 unsigned long lb_irq_int_10 : 1; /* RW, W1C */
212 unsigned long lb_irq_int_11 : 1; /* RW, W1C */
213 unsigned long lb_irq_int_12 : 1; /* RW, W1C */
214 unsigned long lb_irq_int_13 : 1; /* RW, W1C */
215 unsigned long lb_irq_int_14 : 1; /* RW, W1C */
216 unsigned long lb_irq_int_15 : 1; /* RW, W1C */
217 unsigned long l1_nmi_int : 1; /* RW, W1C */
218 unsigned long stop_clock : 1; /* RW, W1C */
219 unsigned long asic_to_l1 : 1; /* RW, W1C */
220 unsigned long l1_to_asic : 1; /* RW, W1C */
221 unsigned long ltc_int : 1; /* RW, W1C */
222 unsigned long la_seq_trigger : 1; /* RW, W1C */
223 unsigned long ipi_int : 1; /* RW, W1C */
224 unsigned long extio_int0 : 1; /* RW, W1C */
225 unsigned long extio_int1 : 1; /* RW, W1C */
226 unsigned long extio_int2 : 1; /* RW, W1C */
227 unsigned long extio_int3 : 1; /* RW, W1C */
228 unsigned long profile_int : 1; /* RW, W1C */
229 unsigned long rtc0 : 1; /* RW, W1C */
230 unsigned long rtc1 : 1; /* RW, W1C */
231 unsigned long rtc2 : 1; /* RW, W1C */
232 unsigned long rtc3 : 1; /* RW, W1C */
233 unsigned long bau_data : 1; /* RW, W1C */
234 unsigned long power_management_req : 1; /* RW, W1C */
235 unsigned long rsvd_57_63 : 7; /* */
236 } s;
237};
238
239/* ========================================================================= */
240/* UVH_EVENT_OCCURRED0_ALIAS */
241/* ========================================================================= */
242#define UVH_EVENT_OCCURRED0_ALIAS 0x0000000000070008UL
243#define UVH_EVENT_OCCURRED0_ALIAS_32 0x005f0
244
245/* ========================================================================= */
246/* UVH_INT_CMPB */
247/* ========================================================================= */
248#define UVH_INT_CMPB 0x22080UL
249
250#define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0
251#define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL
252
253union uvh_int_cmpb_u {
254 unsigned long v;
255 struct uvh_int_cmpb_s {
256 unsigned long real_time_cmpb : 56; /* RW */
257 unsigned long rsvd_56_63 : 8; /* */
258 } s;
259};
260
261/* ========================================================================= */
262/* UVH_INT_CMPC */
263/* ========================================================================= */
264#define UVH_INT_CMPC 0x22100UL
265
266#define UVH_INT_CMPC_REAL_TIME_CMPC_SHFT 0
267#define UVH_INT_CMPC_REAL_TIME_CMPC_MASK 0x00ffffffffffffffUL
268
269union uvh_int_cmpc_u {
270 unsigned long v;
271 struct uvh_int_cmpc_s {
272 unsigned long real_time_cmpc : 56; /* RW */
273 unsigned long rsvd_56_63 : 8; /* */
274 } s;
275};
276
277/* ========================================================================= */
278/* UVH_INT_CMPD */
279/* ========================================================================= */
280#define UVH_INT_CMPD 0x22180UL
281
282#define UVH_INT_CMPD_REAL_TIME_CMPD_SHFT 0
283#define UVH_INT_CMPD_REAL_TIME_CMPD_MASK 0x00ffffffffffffffUL
284
285union uvh_int_cmpd_u {
286 unsigned long v;
287 struct uvh_int_cmpd_s {
288 unsigned long real_time_cmpd : 56; /* RW */
289 unsigned long rsvd_56_63 : 8; /* */
290 } s;
291};
292
293/* ========================================================================= */
294/* UVH_NODE_ID */
295/* ========================================================================= */
296#define UVH_NODE_ID 0x0UL
297
298#define UVH_NODE_ID_FORCE1_SHFT 0
299#define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL
300#define UVH_NODE_ID_MANUFACTURER_SHFT 1
301#define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
302#define UVH_NODE_ID_PART_NUMBER_SHFT 12
303#define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
304#define UVH_NODE_ID_REVISION_SHFT 28
305#define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL
306#define UVH_NODE_ID_NODE_ID_SHFT 32
307#define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
308#define UVH_NODE_ID_NODES_PER_BIT_SHFT 48
309#define UVH_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL
310#define UVH_NODE_ID_NI_PORT_SHFT 56
311#define UVH_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL
312
313union uvh_node_id_u {
314 unsigned long v;
315 struct uvh_node_id_s {
316 unsigned long force1 : 1; /* RO */
317 unsigned long manufacturer : 11; /* RO */
318 unsigned long part_number : 16; /* RO */
319 unsigned long revision : 4; /* RO */
320 unsigned long node_id : 15; /* RW */
321 unsigned long rsvd_47 : 1; /* */
322 unsigned long nodes_per_bit : 7; /* RW */
323 unsigned long rsvd_55 : 1; /* */
324 unsigned long ni_port : 4; /* RO */
325 unsigned long rsvd_60_63 : 4; /* */
326 } s;
327};
328
329/* ========================================================================= */
330/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */
331/* ========================================================================= */
332#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
333
334#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
335#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
336
337union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
338 unsigned long v;
339 struct uvh_rh_gam_alias210_redirect_config_0_mmr_s {
340 unsigned long rsvd_0_23 : 24; /* */
341 unsigned long dest_base : 22; /* RW */
342 unsigned long rsvd_46_63: 18; /* */
343 } s;
344};
345
346/* ========================================================================= */
347/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */
348/* ========================================================================= */
349#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
350
351#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
352#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
353
354union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
355 unsigned long v;
356 struct uvh_rh_gam_alias210_redirect_config_1_mmr_s {
357 unsigned long rsvd_0_23 : 24; /* */
358 unsigned long dest_base : 22; /* RW */
359 unsigned long rsvd_46_63: 18; /* */
360 } s;
361};
362
363/* ========================================================================= */
364/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */
365/* ========================================================================= */
366#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
367
368#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
369#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
370
371union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
372 unsigned long v;
373 struct uvh_rh_gam_alias210_redirect_config_2_mmr_s {
374 unsigned long rsvd_0_23 : 24; /* */
375 unsigned long dest_base : 22; /* RW */
376 unsigned long rsvd_46_63: 18; /* */
377 } s;
378};
379
380/* ========================================================================= */
381/* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */
382/* ========================================================================= */
383#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
384
385#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
386#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
387#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48
388#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL
389#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
390#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
391#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
392#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
393
394union uvh_rh_gam_gru_overlay_config_mmr_u {
395 unsigned long v;
396 struct uvh_rh_gam_gru_overlay_config_mmr_s {
397 unsigned long rsvd_0_27: 28; /* */
398 unsigned long base : 18; /* RW */
399 unsigned long rsvd_46_47: 2; /* */
400 unsigned long gr4 : 1; /* RW */
401 unsigned long rsvd_49_51: 3; /* */
402 unsigned long n_gru : 4; /* RW */
403 unsigned long rsvd_56_62: 7; /* */
404 unsigned long enable : 1; /* RW */
405 } s;
406};
407
408/* ========================================================================= */
409/* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */
410/* ========================================================================= */
411#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
412
413#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
414#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
415#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46
416#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL
417#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
418#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
419
420union uvh_rh_gam_mmr_overlay_config_mmr_u {
421 unsigned long v;
422 struct uvh_rh_gam_mmr_overlay_config_mmr_s {
423 unsigned long rsvd_0_25: 26; /* */
424 unsigned long base : 20; /* RW */
425 unsigned long dual_hub : 1; /* RW */
426 unsigned long rsvd_47_62: 16; /* */
427 unsigned long enable : 1; /* RW */
428 } s;
429};
430
431/* ========================================================================= */
432/* UVH_RTC */
433/* ========================================================================= */
434#define UVH_RTC 0x340000UL
435
436#define UVH_RTC_REAL_TIME_CLOCK_SHFT 0
437#define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL
438
439union uvh_rtc_u {
440 unsigned long v;
441 struct uvh_rtc_s {
442 unsigned long real_time_clock : 56; /* RW */
443 unsigned long rsvd_56_63 : 8; /* */
444 } s;
445};
446
447/* ========================================================================= */
448/* UVH_RTC1_INT_CONFIG */
449/* ========================================================================= */
450#define UVH_RTC1_INT_CONFIG 0x615c0UL
451
452#define UVH_RTC1_INT_CONFIG_VECTOR_SHFT 0
453#define UVH_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
454#define UVH_RTC1_INT_CONFIG_DM_SHFT 8
455#define UVH_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL
456#define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT 11
457#define UVH_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
458#define UVH_RTC1_INT_CONFIG_STATUS_SHFT 12
459#define UVH_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
460#define UVH_RTC1_INT_CONFIG_P_SHFT 13
461#define UVH_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL
462#define UVH_RTC1_INT_CONFIG_T_SHFT 15
463#define UVH_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL
464#define UVH_RTC1_INT_CONFIG_M_SHFT 16
465#define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL
466#define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT 32
467#define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
468
469union uvh_rtc1_int_config_u {
470 unsigned long v;
471 struct uvh_rtc1_int_config_s {
472 unsigned long vector_ : 8; /* RW */
473 unsigned long dm : 3; /* RW */
474 unsigned long destmode : 1; /* RW */
475 unsigned long status : 1; /* RO */
476 unsigned long p : 1; /* RO */
477 unsigned long rsvd_14 : 1; /* */
478 unsigned long t : 1; /* RO */
479 unsigned long m : 1; /* RW */
480 unsigned long rsvd_17_31: 15; /* */
481 unsigned long apic_id : 32; /* RW */
482 } s;
483};
484
485/* ========================================================================= */
486/* UVH_RTC2_INT_CONFIG */
487/* ========================================================================= */
488#define UVH_RTC2_INT_CONFIG 0x61600UL
489
490#define UVH_RTC2_INT_CONFIG_VECTOR_SHFT 0
491#define UVH_RTC2_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
492#define UVH_RTC2_INT_CONFIG_DM_SHFT 8
493#define UVH_RTC2_INT_CONFIG_DM_MASK 0x0000000000000700UL
494#define UVH_RTC2_INT_CONFIG_DESTMODE_SHFT 11
495#define UVH_RTC2_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
496#define UVH_RTC2_INT_CONFIG_STATUS_SHFT 12
497#define UVH_RTC2_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
498#define UVH_RTC2_INT_CONFIG_P_SHFT 13
499#define UVH_RTC2_INT_CONFIG_P_MASK 0x0000000000002000UL
500#define UVH_RTC2_INT_CONFIG_T_SHFT 15
501#define UVH_RTC2_INT_CONFIG_T_MASK 0x0000000000008000UL
502#define UVH_RTC2_INT_CONFIG_M_SHFT 16
503#define UVH_RTC2_INT_CONFIG_M_MASK 0x0000000000010000UL
504#define UVH_RTC2_INT_CONFIG_APIC_ID_SHFT 32
505#define UVH_RTC2_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
506
507union uvh_rtc2_int_config_u {
508 unsigned long v;
509 struct uvh_rtc2_int_config_s {
510 unsigned long vector_ : 8; /* RW */
511 unsigned long dm : 3; /* RW */
512 unsigned long destmode : 1; /* RW */
513 unsigned long status : 1; /* RO */
514 unsigned long p : 1; /* RO */
515 unsigned long rsvd_14 : 1; /* */
516 unsigned long t : 1; /* RO */
517 unsigned long m : 1; /* RW */
518 unsigned long rsvd_17_31: 15; /* */
519 unsigned long apic_id : 32; /* RW */
520 } s;
521};
522
523/* ========================================================================= */
524/* UVH_RTC3_INT_CONFIG */
525/* ========================================================================= */
526#define UVH_RTC3_INT_CONFIG 0x61640UL
527
528#define UVH_RTC3_INT_CONFIG_VECTOR_SHFT 0
529#define UVH_RTC3_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
530#define UVH_RTC3_INT_CONFIG_DM_SHFT 8
531#define UVH_RTC3_INT_CONFIG_DM_MASK 0x0000000000000700UL
532#define UVH_RTC3_INT_CONFIG_DESTMODE_SHFT 11
533#define UVH_RTC3_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
534#define UVH_RTC3_INT_CONFIG_STATUS_SHFT 12
535#define UVH_RTC3_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
536#define UVH_RTC3_INT_CONFIG_P_SHFT 13
537#define UVH_RTC3_INT_CONFIG_P_MASK 0x0000000000002000UL
538#define UVH_RTC3_INT_CONFIG_T_SHFT 15
539#define UVH_RTC3_INT_CONFIG_T_MASK 0x0000000000008000UL
540#define UVH_RTC3_INT_CONFIG_M_SHFT 16
541#define UVH_RTC3_INT_CONFIG_M_MASK 0x0000000000010000UL
542#define UVH_RTC3_INT_CONFIG_APIC_ID_SHFT 32
543#define UVH_RTC3_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
544
545union uvh_rtc3_int_config_u {
546 unsigned long v;
547 struct uvh_rtc3_int_config_s {
548 unsigned long vector_ : 8; /* RW */
549 unsigned long dm : 3; /* RW */
550 unsigned long destmode : 1; /* RW */
551 unsigned long status : 1; /* RO */
552 unsigned long p : 1; /* RO */
553 unsigned long rsvd_14 : 1; /* */
554 unsigned long t : 1; /* RO */
555 unsigned long m : 1; /* RW */
556 unsigned long rsvd_17_31: 15; /* */
557 unsigned long apic_id : 32; /* RW */
558 } s;
559};
560
561/* ========================================================================= */
562/* UVH_RTC_INC_RATIO */
563/* ========================================================================= */
564#define UVH_RTC_INC_RATIO 0x350000UL
565
566#define UVH_RTC_INC_RATIO_FRACTION_SHFT 0
567#define UVH_RTC_INC_RATIO_FRACTION_MASK 0x00000000000fffffUL
568#define UVH_RTC_INC_RATIO_RATIO_SHFT 20
569#define UVH_RTC_INC_RATIO_RATIO_MASK 0x0000000000700000UL
570
571union uvh_rtc_inc_ratio_u {
572 unsigned long v;
573 struct uvh_rtc_inc_ratio_s {
574 unsigned long fraction : 20; /* RW */
575 unsigned long ratio : 3; /* RW */
576 unsigned long rsvd_23_63: 41; /* */
577 } s;
578};
579
580/* ========================================================================= */
581/* UVH_SI_ADDR_MAP_CONFIG */
582/* ========================================================================= */
583#define UVH_SI_ADDR_MAP_CONFIG 0xc80000UL
584
585#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_SHFT 0
586#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_MASK 0x000000000000003fUL
587#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_SHFT 8
588#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_MASK 0x0000000000000f00UL
589
590union uvh_si_addr_map_config_u {
591 unsigned long v;
592 struct uvh_si_addr_map_config_s {
593 unsigned long m_skt : 6; /* RW */
594 unsigned long rsvd_6_7: 2; /* */
595 unsigned long n_skt : 4; /* RW */
596 unsigned long rsvd_12_63: 52; /* */
597 } s;
598};
599
600/* ========================================================================= */
601/* UVH_SI_ALIAS0_OVERLAY_CONFIG */
602/* ========================================================================= */
603#define UVH_SI_ALIAS0_OVERLAY_CONFIG 0xc80008UL
604
605#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_SHFT 24
606#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
607#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_SHFT 48
608#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
609#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_SHFT 63
610#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
611
612union uvh_si_alias0_overlay_config_u {
613 unsigned long v;
614 struct uvh_si_alias0_overlay_config_s {
615 unsigned long rsvd_0_23: 24; /* */
616 unsigned long base : 8; /* RW */
617 unsigned long rsvd_32_47: 16; /* */
618 unsigned long m_alias : 5; /* RW */
619 unsigned long rsvd_53_62: 10; /* */
620 unsigned long enable : 1; /* RW */
621 } s;
622};
623
624/* ========================================================================= */
625/* UVH_SI_ALIAS1_OVERLAY_CONFIG */
626/* ========================================================================= */
627#define UVH_SI_ALIAS1_OVERLAY_CONFIG 0xc80010UL
628
629#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_SHFT 24
630#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
631#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_SHFT 48
632#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
633#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_SHFT 63
634#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
635
636union uvh_si_alias1_overlay_config_u {
637 unsigned long v;
638 struct uvh_si_alias1_overlay_config_s {
639 unsigned long rsvd_0_23: 24; /* */
640 unsigned long base : 8; /* RW */
641 unsigned long rsvd_32_47: 16; /* */
642 unsigned long m_alias : 5; /* RW */
643 unsigned long rsvd_53_62: 10; /* */
644 unsigned long enable : 1; /* RW */
645 } s;
646};
647
648/* ========================================================================= */
649/* UVH_SI_ALIAS2_OVERLAY_CONFIG */
650/* ========================================================================= */
651#define UVH_SI_ALIAS2_OVERLAY_CONFIG 0xc80018UL
652
653#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_SHFT 24
654#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
655#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_SHFT 48
656#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
657#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_SHFT 63
658#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
659
660union uvh_si_alias2_overlay_config_u {
661 unsigned long v;
662 struct uvh_si_alias2_overlay_config_s {
663 unsigned long rsvd_0_23: 24; /* */
664 unsigned long base : 8; /* RW */
665 unsigned long rsvd_32_47: 16; /* */
666 unsigned long m_alias : 5; /* RW */
667 unsigned long rsvd_53_62: 10; /* */
668 unsigned long enable : 1; /* RW */
669 } s;
670};
671
672
673#endif /* __ASM_IA64_UV_MMRS__ */
diff --git a/include/asm-ia64/vga.h b/include/asm-ia64/vga.h
deleted file mode 100644
index 02184ecd820..00000000000
--- a/include/asm-ia64/vga.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * Access to VGA videoram
3 *
4 * (c) 1998 Martin Mares <mj@ucw.cz>
5 * (c) 1999 Asit Mallick <asit.k.mallick@intel.com>
6 * (c) 1999 Don Dugger <don.dugger@intel.com>
7 */
8
9#ifndef __ASM_IA64_VGA_H_
10#define __ASM_IA64_VGA_H_
11
12/*
13 * On the PC, we can just recalculate addresses and then access the
14 * videoram directly without any black magic.
15 */
16
17extern unsigned long vga_console_iobase;
18extern unsigned long vga_console_membase;
19
20#define VGA_MAP_MEM(x,s) ((unsigned long) ioremap_nocache(vga_console_membase + (x), s))
21
22#define vga_readb(x) (*(x))
23#define vga_writeb(x,y) (*(y) = (x))
24
25#endif /* __ASM_IA64_VGA_H_ */
diff --git a/include/asm-ia64/xor.h b/include/asm-ia64/xor.h
deleted file mode 100644
index 41fb8744d17..00000000000
--- a/include/asm-ia64/xor.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * include/asm-ia64/xor.h
3 *
4 * Optimized RAID-5 checksumming functions for IA-64.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2, or (at your option)
9 * any later version.
10 *
11 * You should have received a copy of the GNU General Public License
12 * (for example /usr/src/linux/COPYING); if not, write to the Free
13 * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
14 */
15
16
17extern void xor_ia64_2(unsigned long, unsigned long *, unsigned long *);
18extern void xor_ia64_3(unsigned long, unsigned long *, unsigned long *,
19 unsigned long *);
20extern void xor_ia64_4(unsigned long, unsigned long *, unsigned long *,
21 unsigned long *, unsigned long *);
22extern void xor_ia64_5(unsigned long, unsigned long *, unsigned long *,
23 unsigned long *, unsigned long *, unsigned long *);
24
25static struct xor_block_template xor_block_ia64 = {
26 .name = "ia64",
27 .do_2 = xor_ia64_2,
28 .do_3 = xor_ia64_3,
29 .do_4 = xor_ia64_4,
30 .do_5 = xor_ia64_5,
31};
32
33#define XOR_TRY_TEMPLATES xor_speed(&xor_block_ia64)
diff --git a/include/asm-m68k/contregs.h b/include/asm-m68k/contregs.h
index 1e233e7d191..d1ea750bddf 100644
--- a/include/asm-m68k/contregs.h
+++ b/include/asm-m68k/contregs.h
@@ -1,4 +1,53 @@
1#ifndef _M68K_CONTREGS_H 1#ifndef _M68K_CONTREGS_H
2#define _M68K_CONTREGS_H 2#define _M68K_CONTREGS_H
3#include <asm-sparc/contregs.h> 3
4/* contregs.h: Addresses of registers in the ASI_CONTROL alternate address
5 * space. These are for the mmu's context register, etc.
6 *
7 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
8 */
9
10/* 3=sun3
11 4=sun4 (as in sun4 sysmaint student book)
12 c=sun4c (according to davem) */
13
14#define AC_IDPROM 0x00000000 /* 34 ID PROM, R/O, byte, 32 bytes */
15#define AC_PAGEMAP 0x10000000 /* 3 Pagemap R/W, long */
16#define AC_SEGMAP 0x20000000 /* 3 Segment map, byte */
17#define AC_CONTEXT 0x30000000 /* 34c current mmu-context */
18#define AC_SENABLE 0x40000000 /* 34c system dvma/cache/reset enable reg*/
19#define AC_UDVMA_ENB 0x50000000 /* 34 Not used on Sun boards, byte */
20#define AC_BUS_ERROR 0x60000000 /* 34 Not cleared on read, byte. */
21#define AC_SYNC_ERR 0x60000000 /* c fault type */
22#define AC_SYNC_VA 0x60000004 /* c fault virtual address */
23#define AC_ASYNC_ERR 0x60000008 /* c asynchronous fault type */
24#define AC_ASYNC_VA 0x6000000c /* c async fault virtual address */
25#define AC_LEDS 0x70000000 /* 34 Zero turns on LEDs, byte */
26#define AC_CACHETAGS 0x80000000 /* 34c direct access to the VAC tags */
27#define AC_CACHEDDATA 0x90000000 /* 3 c direct access to the VAC data */
28#define AC_UDVMA_MAP 0xD0000000 /* 4 Not used on Sun boards, byte */
29#define AC_VME_VECTOR 0xE0000000 /* 4 For non-Autovector VME, byte */
30#define AC_BOOT_SCC 0xF0000000 /* 34 bypass to access Zilog 8530. byte.*/
31
32/* s=Swift, h=Ross_HyperSPARC, v=TI_Viking, t=Tsunami, r=Ross_Cypress */
33#define AC_M_PCR 0x0000 /* shv Processor Control Reg */
34#define AC_M_CTPR 0x0100 /* shv Context Table Pointer Reg */
35#define AC_M_CXR 0x0200 /* shv Context Register */
36#define AC_M_SFSR 0x0300 /* shv Synchronous Fault Status Reg */
37#define AC_M_SFAR 0x0400 /* shv Synchronous Fault Address Reg */
38#define AC_M_AFSR 0x0500 /* hv Asynchronous Fault Status Reg */
39#define AC_M_AFAR 0x0600 /* hv Asynchronous Fault Address Reg */
40#define AC_M_RESET 0x0700 /* hv Reset Reg */
41#define AC_M_RPR 0x1000 /* hv Root Pointer Reg */
42#define AC_M_TSUTRCR 0x1000 /* s TLB Replacement Ctrl Reg */
43#define AC_M_IAPTP 0x1100 /* hv Instruction Access PTP */
44#define AC_M_DAPTP 0x1200 /* hv Data Access PTP */
45#define AC_M_ITR 0x1300 /* hv Index Tag Register */
46#define AC_M_TRCR 0x1400 /* hv TLB Replacement Control Reg */
47#define AC_M_SFSRX 0x1300 /* s Synch Fault Status Reg prim */
48#define AC_M_SFARX 0x1400 /* s Synch Fault Address Reg prim */
49#define AC_M_RPR1 0x1500 /* h Root Pointer Reg (entry 2) */
50#define AC_M_IAPTP1 0x1600 /* h Instruction Access PTP (entry 2) */
51#define AC_M_DAPTP1 0x1700 /* h Data Access PTP (entry 2) */
52
4#endif /* _M68K_CONTREGS_H */ 53#endif /* _M68K_CONTREGS_H */
diff --git a/include/asm-m68k/fbio.h b/include/asm-m68k/fbio.h
index c17edf8c7bc..b9215a0907d 100644
--- a/include/asm-m68k/fbio.h
+++ b/include/asm-m68k/fbio.h
@@ -1 +1,330 @@
1#include <asm-sparc/fbio.h> 1#ifndef __LINUX_FBIO_H
2#define __LINUX_FBIO_H
3
4#include <linux/compiler.h>
5#include <linux/types.h>
6
7/* Constants used for fbio SunOS compatibility */
8/* (C) 1996 Miguel de Icaza */
9
10/* Frame buffer types */
11#define FBTYPE_NOTYPE -1
12#define FBTYPE_SUN1BW 0 /* mono */
13#define FBTYPE_SUN1COLOR 1
14#define FBTYPE_SUN2BW 2
15#define FBTYPE_SUN2COLOR 3
16#define FBTYPE_SUN2GP 4
17#define FBTYPE_SUN5COLOR 5
18#define FBTYPE_SUN3COLOR 6
19#define FBTYPE_MEMCOLOR 7
20#define FBTYPE_SUN4COLOR 8
21
22#define FBTYPE_NOTSUN1 9
23#define FBTYPE_NOTSUN2 10
24#define FBTYPE_NOTSUN3 11
25
26#define FBTYPE_SUNFAST_COLOR 12 /* cg6 */
27#define FBTYPE_SUNROP_COLOR 13
28#define FBTYPE_SUNFB_VIDEO 14
29#define FBTYPE_SUNGIFB 15
30#define FBTYPE_SUNGPLAS 16
31#define FBTYPE_SUNGP3 17
32#define FBTYPE_SUNGT 18
33#define FBTYPE_SUNLEO 19 /* zx Leo card */
34#define FBTYPE_MDICOLOR 20 /* cg14 */
35#define FBTYPE_TCXCOLOR 21 /* SUNW,tcx card */
36
37#define FBTYPE_LASTPLUSONE 21 /* This is not last + 1 in fact... */
38
39/* Does not seem to be listed in the Sun file either */
40#define FBTYPE_CREATOR 22
41#define FBTYPE_PCI_IGA1682 23
42#define FBTYPE_P9100COLOR 24
43
44#define FBTYPE_PCI_GENERIC 1000
45#define FBTYPE_PCI_MACH64 1001
46
47/* fbio ioctls */
48/* Returned by FBIOGTYPE */
49struct fbtype {
50 int fb_type; /* fb type, see above */
51 int fb_height; /* pixels */
52 int fb_width; /* pixels */
53 int fb_depth;
54 int fb_cmsize; /* color map entries */
55 int fb_size; /* fb size in bytes */
56};
57#define FBIOGTYPE _IOR('F', 0, struct fbtype)
58
59struct fbcmap {
60 int index; /* first element (0 origin) */
61 int count;
62 unsigned char __user *red;
63 unsigned char __user *green;
64 unsigned char __user *blue;
65};
66
67#ifdef __KERNEL__
68#define FBIOPUTCMAP_SPARC _IOW('F', 3, struct fbcmap)
69#define FBIOGETCMAP_SPARC _IOW('F', 4, struct fbcmap)
70#else
71#define FBIOPUTCMAP _IOW('F', 3, struct fbcmap)
72#define FBIOGETCMAP _IOW('F', 4, struct fbcmap)
73#endif
74
75/* # of device specific values */
76#define FB_ATTR_NDEVSPECIFIC 8
77/* # of possible emulations */
78#define FB_ATTR_NEMUTYPES 4
79
80struct fbsattr {
81 int flags;
82 int emu_type; /* -1 if none */
83 int dev_specific[FB_ATTR_NDEVSPECIFIC];
84};
85
86struct fbgattr {
87 int real_type; /* real frame buffer type */
88 int owner; /* unknown */
89 struct fbtype fbtype; /* real frame buffer fbtype */
90 struct fbsattr sattr;
91 int emu_types[FB_ATTR_NEMUTYPES]; /* supported emulations */
92};
93#define FBIOSATTR _IOW('F', 5, struct fbgattr) /* Unsupported: */
94#define FBIOGATTR _IOR('F', 6, struct fbgattr) /* supported */
95
96#define FBIOSVIDEO _IOW('F', 7, int)
97#define FBIOGVIDEO _IOR('F', 8, int)
98
99struct fbcursor {
100 short set; /* what to set, choose from the list above */
101 short enable; /* cursor on/off */
102 struct fbcurpos pos; /* cursor position */
103 struct fbcurpos hot; /* cursor hot spot */
104 struct fbcmap cmap; /* color map info */
105 struct fbcurpos size; /* cursor bit map size */
106 char __user *image; /* cursor image bits */
107 char __user *mask; /* cursor mask bits */
108};
109
110/* set/get cursor attributes/shape */
111#define FBIOSCURSOR _IOW('F', 24, struct fbcursor)
112#define FBIOGCURSOR _IOWR('F', 25, struct fbcursor)
113
114/* set/get cursor position */
115#define FBIOSCURPOS _IOW('F', 26, struct fbcurpos)
116#define FBIOGCURPOS _IOW('F', 27, struct fbcurpos)
117
118/* get max cursor size */
119#define FBIOGCURMAX _IOR('F', 28, struct fbcurpos)
120
121/* wid manipulation */
122struct fb_wid_alloc {
123#define FB_WID_SHARED_8 0
124#define FB_WID_SHARED_24 1
125#define FB_WID_DBL_8 2
126#define FB_WID_DBL_24 3
127 __u32 wa_type;
128 __s32 wa_index; /* Set on return */
129 __u32 wa_count;
130};
131struct fb_wid_item {
132 __u32 wi_type;
133 __s32 wi_index;
134 __u32 wi_attrs;
135 __u32 wi_values[32];
136};
137struct fb_wid_list {
138 __u32 wl_flags;
139 __u32 wl_count;
140 struct fb_wid_item *wl_list;
141};
142
143#define FBIO_WID_ALLOC _IOWR('F', 30, struct fb_wid_alloc)
144#define FBIO_WID_FREE _IOW('F', 31, struct fb_wid_alloc)
145#define FBIO_WID_PUT _IOW('F', 32, struct fb_wid_list)
146#define FBIO_WID_GET _IOWR('F', 33, struct fb_wid_list)
147
148/* Creator ioctls */
149#define FFB_IOCTL ('F'<<8)
150#define FFB_SYS_INFO (FFB_IOCTL|80)
151#define FFB_CLUTREAD (FFB_IOCTL|81)
152#define FFB_CLUTPOST (FFB_IOCTL|82)
153#define FFB_SETDIAGMODE (FFB_IOCTL|83)
154#define FFB_GETMONITORID (FFB_IOCTL|84)
155#define FFB_GETVIDEOMODE (FFB_IOCTL|85)
156#define FFB_SETVIDEOMODE (FFB_IOCTL|86)
157#define FFB_SETSERVER (FFB_IOCTL|87)
158#define FFB_SETOVCTL (FFB_IOCTL|88)
159#define FFB_GETOVCTL (FFB_IOCTL|89)
160#define FFB_GETSAXNUM (FFB_IOCTL|90)
161#define FFB_FBDEBUG (FFB_IOCTL|91)
162
163/* Cg14 ioctls */
164#define MDI_IOCTL ('M'<<8)
165#define MDI_RESET (MDI_IOCTL|1)
166#define MDI_GET_CFGINFO (MDI_IOCTL|2)
167#define MDI_SET_PIXELMODE (MDI_IOCTL|3)
168# define MDI_32_PIX 32
169# define MDI_16_PIX 16
170# define MDI_8_PIX 8
171
172struct mdi_cfginfo {
173 int mdi_ncluts; /* Number of implemented CLUTs in this MDI */
174 int mdi_type; /* FBTYPE name */
175 int mdi_height; /* height */
176 int mdi_width; /* widht */
177 int mdi_size; /* available ram */
178 int mdi_mode; /* 8bpp, 16bpp or 32bpp */
179 int mdi_pixfreq; /* pixel clock (from PROM) */
180};
181
182/* SparcLinux specific ioctl for the MDI, should be replaced for
183 * the SET_XLUT/SET_CLUTn ioctls instead
184 */
185#define MDI_CLEAR_XLUT (MDI_IOCTL|9)
186
187/* leo & ffb ioctls */
188struct fb_clut_alloc {
189 __u32 clutid; /* Set on return */
190 __u32 flag;
191 __u32 index;
192};
193
194struct fb_clut {
195#define FB_CLUT_WAIT 0x00000001 /* Not yet implemented */
196 __u32 flag;
197 __u32 clutid;
198 __u32 offset;
199 __u32 count;
200 char * red;
201 char * green;
202 char * blue;
203};
204
205struct fb_clut32 {
206 __u32 flag;
207 __u32 clutid;
208 __u32 offset;
209 __u32 count;
210 __u32 red;
211 __u32 green;
212 __u32 blue;
213};
214
215#define LEO_CLUTALLOC _IOWR('L', 53, struct fb_clut_alloc)
216#define LEO_CLUTFREE _IOW('L', 54, struct fb_clut_alloc)
217#define LEO_CLUTREAD _IOW('L', 55, struct fb_clut)
218#define LEO_CLUTPOST _IOW('L', 56, struct fb_clut)
219#define LEO_SETGAMMA _IOW('L', 68, int) /* Not yet implemented */
220#define LEO_GETGAMMA _IOR('L', 69, int) /* Not yet implemented */
221
222#ifdef __KERNEL__
223/* Addresses on the fd of a cgsix that are mappable */
224#define CG6_FBC 0x70000000
225#define CG6_TEC 0x70001000
226#define CG6_BTREGS 0x70002000
227#define CG6_FHC 0x70004000
228#define CG6_THC 0x70005000
229#define CG6_ROM 0x70006000
230#define CG6_RAM 0x70016000
231#define CG6_DHC 0x80000000
232
233#define CG3_MMAP_OFFSET 0x4000000
234
235/* Addresses on the fd of a tcx that are mappable */
236#define TCX_RAM8BIT 0x00000000
237#define TCX_RAM24BIT 0x01000000
238#define TCX_UNK3 0x10000000
239#define TCX_UNK4 0x20000000
240#define TCX_CONTROLPLANE 0x28000000
241#define TCX_UNK6 0x30000000
242#define TCX_UNK7 0x38000000
243#define TCX_TEC 0x70000000
244#define TCX_BTREGS 0x70002000
245#define TCX_THC 0x70004000
246#define TCX_DHC 0x70008000
247#define TCX_ALT 0x7000a000
248#define TCX_SYNC 0x7000e000
249#define TCX_UNK2 0x70010000
250
251/* CG14 definitions */
252
253/* Offsets into the OBIO space: */
254#define CG14_REGS 0 /* registers */
255#define CG14_CURSORREGS 0x1000 /* cursor registers */
256#define CG14_DACREGS 0x2000 /* DAC registers */
257#define CG14_XLUT 0x3000 /* X Look Up Table -- ??? */
258#define CG14_CLUT1 0x4000 /* Color Look Up Table */
259#define CG14_CLUT2 0x5000 /* Color Look Up Table */
260#define CG14_CLUT3 0x6000 /* Color Look Up Table */
261#define CG14_AUTO 0xf000
262
263#endif /* KERNEL */
264
265/* These are exported to userland for applications to use */
266/* Mappable offsets for the cg14: control registers */
267#define MDI_DIRECT_MAP 0x10000000
268#define MDI_CTLREG_MAP 0x20000000
269#define MDI_CURSOR_MAP 0x30000000
270#define MDI_SHDW_VRT_MAP 0x40000000
271
272/* Mappable offsets for the cg14: frame buffer resolutions */
273/* 32 bits */
274#define MDI_CHUNKY_XBGR_MAP 0x50000000
275#define MDI_CHUNKY_BGR_MAP 0x60000000
276
277/* 16 bits */
278#define MDI_PLANAR_X16_MAP 0x70000000
279#define MDI_PLANAR_C16_MAP 0x80000000
280
281/* 8 bit is done as CG3 MMAP offset */
282/* 32 bits, planar */
283#define MDI_PLANAR_X32_MAP 0x90000000
284#define MDI_PLANAR_B32_MAP 0xa0000000
285#define MDI_PLANAR_G32_MAP 0xb0000000
286#define MDI_PLANAR_R32_MAP 0xc0000000
287
288/* Mappable offsets on leo */
289#define LEO_SS0_MAP 0x00000000
290#define LEO_LC_SS0_USR_MAP 0x00800000
291#define LEO_LD_SS0_MAP 0x00801000
292#define LEO_LX_CURSOR_MAP 0x00802000
293#define LEO_SS1_MAP 0x00803000
294#define LEO_LC_SS1_USR_MAP 0x01003000
295#define LEO_LD_SS1_MAP 0x01004000
296#define LEO_UNK_MAP 0x01005000
297#define LEO_LX_KRN_MAP 0x01006000
298#define LEO_LC_SS0_KRN_MAP 0x01007000
299#define LEO_LC_SS1_KRN_MAP 0x01008000
300#define LEO_LD_GBL_MAP 0x01009000
301#define LEO_UNK2_MAP 0x0100a000
302
303#ifdef __KERNEL__
304struct fbcmap32 {
305 int index; /* first element (0 origin) */
306 int count;
307 u32 red;
308 u32 green;
309 u32 blue;
310};
311
312#define FBIOPUTCMAP32 _IOW('F', 3, struct fbcmap32)
313#define FBIOGETCMAP32 _IOW('F', 4, struct fbcmap32)
314
315struct fbcursor32 {
316 short set; /* what to set, choose from the list above */
317 short enable; /* cursor on/off */
318 struct fbcurpos pos; /* cursor position */
319 struct fbcurpos hot; /* cursor hot spot */
320 struct fbcmap32 cmap; /* color map info */
321 struct fbcurpos size; /* cursor bit map size */
322 u32 image; /* cursor image bits */
323 u32 mask; /* cursor mask bits */
324};
325
326#define FBIOSCURSOR32 _IOW('F', 24, struct fbcursor32)
327#define FBIOGCURSOR32 _IOW('F', 25, struct fbcursor32)
328#endif
329
330#endif /* __LINUX_FBIO_H */
diff --git a/include/asm-m68k/idprom.h b/include/asm-m68k/idprom.h
index 4349eaf3cfe..160616a89e0 100644
--- a/include/asm-m68k/idprom.h
+++ b/include/asm-m68k/idprom.h
@@ -1,6 +1,25 @@
1#ifndef _M68K_IDPROM_H 1#ifndef _M68K_IDPROM_H
2#define _M68K_IDPROM_H 2#define _M68K_IDPROM_H
3#include <asm-sparc/idprom.h> 3/*
4 * idprom.h: Macros and defines for idprom routines
5 *
6 * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
7 */
8
9#include <linux/types.h>
10
11struct idprom {
12 u8 id_format; /* Format identifier (always 0x01) */
13 u8 id_machtype; /* Machine type */
14 u8 id_ethaddr[6]; /* Hardware ethernet address */
15 s32 id_date; /* Date of manufacture */
16 u32 id_sernum:24; /* Unique serial number */
17 u8 id_cksum; /* Checksum - xor of the data bytes */
18 u8 reserved[16];
19};
20
21extern struct idprom *idprom;
22extern void idprom_init(void);
4 23
5/* Sun3: in control space */ 24/* Sun3: in control space */
6#define SUN3_IDPROM_BASE 0x00000000 25#define SUN3_IDPROM_BASE 0x00000000
diff --git a/include/asm-mips/gdb-stub.h b/include/asm-mips/gdb-stub.h
deleted file mode 100644
index 22f67d4a71a..00000000000
--- a/include/asm-mips/gdb-stub.h
+++ /dev/null
@@ -1,215 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1995 Andreas Busse
7 * Copyright (C) 2003 Ralf Baechle
8 */
9#ifndef _ASM_GDB_STUB_H
10#define _ASM_GDB_STUB_H
11
12
13/*
14 * important register numbers
15 */
16
17#define REG_EPC 37
18#define REG_FP 72
19#define REG_SP 29
20
21/*
22 * Stack layout for the GDB exception handler
23 * Derived from the stack layout described in asm-mips/stackframe.h
24 *
25 * The first PTRSIZE*6 bytes are argument save space for C subroutines.
26 */
27#define NUMREGS 90
28
29#define GDB_FR_REG0 (PTRSIZE*6) /* 0 */
30#define GDB_FR_REG1 ((GDB_FR_REG0) + LONGSIZE) /* 1 */
31#define GDB_FR_REG2 ((GDB_FR_REG1) + LONGSIZE) /* 2 */
32#define GDB_FR_REG3 ((GDB_FR_REG2) + LONGSIZE) /* 3 */
33#define GDB_FR_REG4 ((GDB_FR_REG3) + LONGSIZE) /* 4 */
34#define GDB_FR_REG5 ((GDB_FR_REG4) + LONGSIZE) /* 5 */
35#define GDB_FR_REG6 ((GDB_FR_REG5) + LONGSIZE) /* 6 */
36#define GDB_FR_REG7 ((GDB_FR_REG6) + LONGSIZE) /* 7 */
37#define GDB_FR_REG8 ((GDB_FR_REG7) + LONGSIZE) /* 8 */
38#define GDB_FR_REG9 ((GDB_FR_REG8) + LONGSIZE) /* 9 */
39#define GDB_FR_REG10 ((GDB_FR_REG9) + LONGSIZE) /* 10 */
40#define GDB_FR_REG11 ((GDB_FR_REG10) + LONGSIZE) /* 11 */
41#define GDB_FR_REG12 ((GDB_FR_REG11) + LONGSIZE) /* 12 */
42#define GDB_FR_REG13 ((GDB_FR_REG12) + LONGSIZE) /* 13 */
43#define GDB_FR_REG14 ((GDB_FR_REG13) + LONGSIZE) /* 14 */
44#define GDB_FR_REG15 ((GDB_FR_REG14) + LONGSIZE) /* 15 */
45#define GDB_FR_REG16 ((GDB_FR_REG15) + LONGSIZE) /* 16 */
46#define GDB_FR_REG17 ((GDB_FR_REG16) + LONGSIZE) /* 17 */
47#define GDB_FR_REG18 ((GDB_FR_REG17) + LONGSIZE) /* 18 */
48#define GDB_FR_REG19 ((GDB_FR_REG18) + LONGSIZE) /* 19 */
49#define GDB_FR_REG20 ((GDB_FR_REG19) + LONGSIZE) /* 20 */
50#define GDB_FR_REG21 ((GDB_FR_REG20) + LONGSIZE) /* 21 */
51#define GDB_FR_REG22 ((GDB_FR_REG21) + LONGSIZE) /* 22 */
52#define GDB_FR_REG23 ((GDB_FR_REG22) + LONGSIZE) /* 23 */
53#define GDB_FR_REG24 ((GDB_FR_REG23) + LONGSIZE) /* 24 */
54#define GDB_FR_REG25 ((GDB_FR_REG24) + LONGSIZE) /* 25 */
55#define GDB_FR_REG26 ((GDB_FR_REG25) + LONGSIZE) /* 26 */
56#define GDB_FR_REG27 ((GDB_FR_REG26) + LONGSIZE) /* 27 */
57#define GDB_FR_REG28 ((GDB_FR_REG27) + LONGSIZE) /* 28 */
58#define GDB_FR_REG29 ((GDB_FR_REG28) + LONGSIZE) /* 29 */
59#define GDB_FR_REG30 ((GDB_FR_REG29) + LONGSIZE) /* 30 */
60#define GDB_FR_REG31 ((GDB_FR_REG30) + LONGSIZE) /* 31 */
61
62/*
63 * Saved special registers
64 */
65#define GDB_FR_STATUS ((GDB_FR_REG31) + LONGSIZE) /* 32 */
66#define GDB_FR_LO ((GDB_FR_STATUS) + LONGSIZE) /* 33 */
67#define GDB_FR_HI ((GDB_FR_LO) + LONGSIZE) /* 34 */
68#define GDB_FR_BADVADDR ((GDB_FR_HI) + LONGSIZE) /* 35 */
69#define GDB_FR_CAUSE ((GDB_FR_BADVADDR) + LONGSIZE) /* 36 */
70#define GDB_FR_EPC ((GDB_FR_CAUSE) + LONGSIZE) /* 37 */
71
72/*
73 * Saved floating point registers
74 */
75#define GDB_FR_FPR0 ((GDB_FR_EPC) + LONGSIZE) /* 38 */
76#define GDB_FR_FPR1 ((GDB_FR_FPR0) + LONGSIZE) /* 39 */
77#define GDB_FR_FPR2 ((GDB_FR_FPR1) + LONGSIZE) /* 40 */
78#define GDB_FR_FPR3 ((GDB_FR_FPR2) + LONGSIZE) /* 41 */
79#define GDB_FR_FPR4 ((GDB_FR_FPR3) + LONGSIZE) /* 42 */
80#define GDB_FR_FPR5 ((GDB_FR_FPR4) + LONGSIZE) /* 43 */
81#define GDB_FR_FPR6 ((GDB_FR_FPR5) + LONGSIZE) /* 44 */
82#define GDB_FR_FPR7 ((GDB_FR_FPR6) + LONGSIZE) /* 45 */
83#define GDB_FR_FPR8 ((GDB_FR_FPR7) + LONGSIZE) /* 46 */
84#define GDB_FR_FPR9 ((GDB_FR_FPR8) + LONGSIZE) /* 47 */
85#define GDB_FR_FPR10 ((GDB_FR_FPR9) + LONGSIZE) /* 48 */
86#define GDB_FR_FPR11 ((GDB_FR_FPR10) + LONGSIZE) /* 49 */
87#define GDB_FR_FPR12 ((GDB_FR_FPR11) + LONGSIZE) /* 50 */
88#define GDB_FR_FPR13 ((GDB_FR_FPR12) + LONGSIZE) /* 51 */
89#define GDB_FR_FPR14 ((GDB_FR_FPR13) + LONGSIZE) /* 52 */
90#define GDB_FR_FPR15 ((GDB_FR_FPR14) + LONGSIZE) /* 53 */
91#define GDB_FR_FPR16 ((GDB_FR_FPR15) + LONGSIZE) /* 54 */
92#define GDB_FR_FPR17 ((GDB_FR_FPR16) + LONGSIZE) /* 55 */
93#define GDB_FR_FPR18 ((GDB_FR_FPR17) + LONGSIZE) /* 56 */
94#define GDB_FR_FPR19 ((GDB_FR_FPR18) + LONGSIZE) /* 57 */
95#define GDB_FR_FPR20 ((GDB_FR_FPR19) + LONGSIZE) /* 58 */
96#define GDB_FR_FPR21 ((GDB_FR_FPR20) + LONGSIZE) /* 59 */
97#define GDB_FR_FPR22 ((GDB_FR_FPR21) + LONGSIZE) /* 60 */
98#define GDB_FR_FPR23 ((GDB_FR_FPR22) + LONGSIZE) /* 61 */
99#define GDB_FR_FPR24 ((GDB_FR_FPR23) + LONGSIZE) /* 62 */
100#define GDB_FR_FPR25 ((GDB_FR_FPR24) + LONGSIZE) /* 63 */
101#define GDB_FR_FPR26 ((GDB_FR_FPR25) + LONGSIZE) /* 64 */
102#define GDB_FR_FPR27 ((GDB_FR_FPR26) + LONGSIZE) /* 65 */
103#define GDB_FR_FPR28 ((GDB_FR_FPR27) + LONGSIZE) /* 66 */
104#define GDB_FR_FPR29 ((GDB_FR_FPR28) + LONGSIZE) /* 67 */
105#define GDB_FR_FPR30 ((GDB_FR_FPR29) + LONGSIZE) /* 68 */
106#define GDB_FR_FPR31 ((GDB_FR_FPR30) + LONGSIZE) /* 69 */
107
108#define GDB_FR_FSR ((GDB_FR_FPR31) + LONGSIZE) /* 70 */
109#define GDB_FR_FIR ((GDB_FR_FSR) + LONGSIZE) /* 71 */
110#define GDB_FR_FRP ((GDB_FR_FIR) + LONGSIZE) /* 72 */
111
112#define GDB_FR_DUMMY ((GDB_FR_FRP) + LONGSIZE) /* 73, unused ??? */
113
114/*
115 * Again, CP0 registers
116 */
117#define GDB_FR_CP0_INDEX ((GDB_FR_DUMMY) + LONGSIZE) /* 74 */
118#define GDB_FR_CP0_RANDOM ((GDB_FR_CP0_INDEX) + LONGSIZE) /* 75 */
119#define GDB_FR_CP0_ENTRYLO0 ((GDB_FR_CP0_RANDOM) + LONGSIZE)/* 76 */
120#define GDB_FR_CP0_ENTRYLO1 ((GDB_FR_CP0_ENTRYLO0) + LONGSIZE)/* 77 */
121#define GDB_FR_CP0_CONTEXT ((GDB_FR_CP0_ENTRYLO1) + LONGSIZE)/* 78 */
122#define GDB_FR_CP0_PAGEMASK ((GDB_FR_CP0_CONTEXT) + LONGSIZE)/* 79 */
123#define GDB_FR_CP0_WIRED ((GDB_FR_CP0_PAGEMASK) + LONGSIZE)/* 80 */
124#define GDB_FR_CP0_REG7 ((GDB_FR_CP0_WIRED) + LONGSIZE) /* 81 */
125#define GDB_FR_CP0_REG8 ((GDB_FR_CP0_REG7) + LONGSIZE) /* 82 */
126#define GDB_FR_CP0_REG9 ((GDB_FR_CP0_REG8) + LONGSIZE) /* 83 */
127#define GDB_FR_CP0_ENTRYHI ((GDB_FR_CP0_REG9) + LONGSIZE) /* 84 */
128#define GDB_FR_CP0_REG11 ((GDB_FR_CP0_ENTRYHI) + LONGSIZE)/* 85 */
129#define GDB_FR_CP0_REG12 ((GDB_FR_CP0_REG11) + LONGSIZE) /* 86 */
130#define GDB_FR_CP0_REG13 ((GDB_FR_CP0_REG12) + LONGSIZE) /* 87 */
131#define GDB_FR_CP0_REG14 ((GDB_FR_CP0_REG13) + LONGSIZE) /* 88 */
132#define GDB_FR_CP0_PRID ((GDB_FR_CP0_REG14) + LONGSIZE) /* 89 */
133
134#define GDB_FR_SIZE ((((GDB_FR_CP0_PRID) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1))
135
136#ifndef __ASSEMBLY__
137
138/*
139 * This is the same as above, but for the high-level
140 * part of the GDB stub.
141 */
142
143struct gdb_regs {
144 /*
145 * Pad bytes for argument save space on the stack
146 * 24/48 Bytes for 32/64 bit code
147 */
148 unsigned long pad0[6];
149
150 /*
151 * saved main processor registers
152 */
153 long reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7;
154 long reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15;
155 long reg16, reg17, reg18, reg19, reg20, reg21, reg22, reg23;
156 long reg24, reg25, reg26, reg27, reg28, reg29, reg30, reg31;
157
158 /*
159 * Saved special registers
160 */
161 long cp0_status;
162 long lo;
163 long hi;
164 long cp0_badvaddr;
165 long cp0_cause;
166 long cp0_epc;
167
168 /*
169 * Saved floating point registers
170 */
171 long fpr0, fpr1, fpr2, fpr3, fpr4, fpr5, fpr6, fpr7;
172 long fpr8, fpr9, fpr10, fpr11, fpr12, fpr13, fpr14, fpr15;
173 long fpr16, fpr17, fpr18, fpr19, fpr20, fpr21, fpr22, fpr23;
174 long fpr24, fpr25, fpr26, fpr27, fpr28, fpr29, fpr30, fpr31;
175
176 long cp1_fsr;
177 long cp1_fir;
178
179 /*
180 * Frame pointer
181 */
182 long frame_ptr;
183 long dummy; /* unused */
184
185 /*
186 * saved cp0 registers
187 */
188 long cp0_index;
189 long cp0_random;
190 long cp0_entrylo0;
191 long cp0_entrylo1;
192 long cp0_context;
193 long cp0_pagemask;
194 long cp0_wired;
195 long cp0_reg7;
196 long cp0_reg8;
197 long cp0_reg9;
198 long cp0_entryhi;
199 long cp0_reg11;
200 long cp0_reg12;
201 long cp0_reg13;
202 long cp0_reg14;
203 long cp0_prid;
204};
205
206/*
207 * Prototypes
208 */
209
210extern int kgdb_enabled;
211void set_debug_traps(void);
212void set_async_breakpoint(unsigned long *epc);
213
214#endif /* !__ASSEMBLY__ */
215#endif /* _ASM_GDB_STUB_H */
diff --git a/include/asm-mips/kdebug.h b/include/asm-mips/kdebug.h
index 6ece1b03766..5bf62aafc89 100644
--- a/include/asm-mips/kdebug.h
+++ b/include/asm-mips/kdebug.h
@@ -1 +1,13 @@
1#include <asm-generic/kdebug.h> 1#ifndef _ASM_MIPS_KDEBUG_H
2#define _ASM_MIPS_KDEBUG_H
3
4#include <linux/notifier.h>
5
6enum die_val {
7 DIE_OOPS = 1,
8 DIE_FP,
9 DIE_TRAP,
10 DIE_RI,
11};
12
13#endif /* _ASM_MIPS_KDEBUG_H */
diff --git a/include/asm-mips/kgdb.h b/include/asm-mips/kgdb.h
new file mode 100644
index 00000000000..48223b09396
--- /dev/null
+++ b/include/asm-mips/kgdb.h
@@ -0,0 +1,44 @@
1#ifndef __ASM_KGDB_H_
2#define __ASM_KGDB_H_
3
4#ifdef __KERNEL__
5
6#include <asm/sgidefs.h>
7
8#if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \
9 (_MIPS_ISA == _MIPS_ISA_MIPS32)
10
11#define KGDB_GDB_REG_SIZE 32
12
13#elif (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
14 (_MIPS_ISA == _MIPS_ISA_MIPS64)
15
16#ifdef CONFIG_32BIT
17#define KGDB_GDB_REG_SIZE 32
18#else /* CONFIG_CPU_32BIT */
19#define KGDB_GDB_REG_SIZE 64
20#endif
21#else
22#error "Need to set KGDB_GDB_REG_SIZE for MIPS ISA"
23#endif /* _MIPS_ISA */
24
25#define BUFMAX 2048
26#if (KGDB_GDB_REG_SIZE == 32)
27#define NUMREGBYTES (90*sizeof(u32))
28#define NUMCRITREGBYTES (12*sizeof(u32))
29#else
30#define NUMREGBYTES (90*sizeof(u64))
31#define NUMCRITREGBYTES (12*sizeof(u64))
32#endif
33#define BREAK_INSTR_SIZE 4
34#define CACHE_FLUSH_IS_SAFE 0
35
36extern void arch_kgdb_breakpoint(void);
37extern int kgdb_early_setup;
38extern void *saved_vectors[32];
39extern void handle_exception(struct pt_regs *regs);
40extern void breakinst(void);
41
42#endif /* __KERNEL__ */
43
44#endif /* __ASM_KGDB_H_ */
diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h
index c205875d7f3..5510c53b7fe 100644
--- a/include/asm-mips/pci.h
+++ b/include/asm-mips/pci.h
@@ -174,4 +174,6 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
174 174
175extern int pci_probe_only; 175extern int pci_probe_only;
176 176
177extern char * (*pcibios_plat_setup)(char *str);
178
177#endif /* _ASM_PCI_H */ 179#endif /* _ASM_PCI_H */
diff --git a/include/asm-mips/txx9/generic.h b/include/asm-mips/txx9/generic.h
index cbae37ec3d8..5b1ccf901c6 100644
--- a/include/asm-mips/txx9/generic.h
+++ b/include/asm-mips/txx9/generic.h
@@ -44,5 +44,19 @@ extern struct txx9_board_vec *txx9_board_vec;
44extern int (*txx9_irq_dispatch)(int pending); 44extern int (*txx9_irq_dispatch)(int pending);
45void prom_init_cmdline(void); 45void prom_init_cmdline(void);
46char *prom_getcmdline(void); 46char *prom_getcmdline(void);
47void txx9_wdt_init(unsigned long base);
48void txx9_spi_init(int busid, unsigned long base, int irq);
49void txx9_ethaddr_init(unsigned int id, unsigned char *ethaddr);
50void txx9_sio_init(unsigned long baseaddr, int irq,
51 unsigned int line, unsigned int sclk, int nocts);
52void prom_putchar(char c);
53#ifdef CONFIG_EARLY_PRINTK
54extern void (*txx9_prom_putchar)(char c);
55void txx9_sio_putchar_init(unsigned long baseaddr);
56#else
57static inline void txx9_sio_putchar_init(unsigned long baseaddr)
58{
59}
60#endif
47 61
48#endif /* __ASM_TXX9_GENERIC_H */ 62#endif /* __ASM_TXX9_GENERIC_H */
diff --git a/include/asm-mips/txx9/jmr3927.h b/include/asm-mips/txx9/jmr3927.h
index d6eb1b6a54e..a409c446bf1 100644
--- a/include/asm-mips/txx9/jmr3927.h
+++ b/include/asm-mips/txx9/jmr3927.h
@@ -149,8 +149,6 @@
149 149
150/* Clocks */ 150/* Clocks */
151#define JMR3927_CORECLK 132710400 /* 132.7MHz */ 151#define JMR3927_CORECLK 132710400 /* 132.7MHz */
152#define JMR3927_GBUSCLK (JMR3927_CORECLK / 2) /* 66.35MHz */
153#define JMR3927_IMCLK (JMR3927_CORECLK / 4) /* 33.17MHz */
154 152
155/* 153/*
156 * TX3927 Pin Configuration: 154 * TX3927 Pin Configuration:
diff --git a/include/asm-mips/txx9/pci.h b/include/asm-mips/txx9/pci.h
index d89a45091e2..3d32529060a 100644
--- a/include/asm-mips/txx9/pci.h
+++ b/include/asm-mips/txx9/pci.h
@@ -33,4 +33,7 @@ enum txx9_pci_err_action {
33}; 33};
34extern enum txx9_pci_err_action txx9_pci_err_action; 34extern enum txx9_pci_err_action txx9_pci_err_action;
35 35
36extern char * (*txx9_board_pcibios_setup)(char *str);
37char *txx9_pcibios_setup(char *str);
38
36#endif /* __ASM_TXX9_PCI_H */ 39#endif /* __ASM_TXX9_PCI_H */
diff --git a/include/asm-mips/txx9/smsc_fdc37m81x.h b/include/asm-mips/txx9/smsc_fdc37m81x.h
index 9375e4fc228..02e161d0755 100644
--- a/include/asm-mips/txx9/smsc_fdc37m81x.h
+++ b/include/asm-mips/txx9/smsc_fdc37m81x.h
@@ -56,7 +56,7 @@
56#define SMSC_FDC37M81X_CONFIG_EXIT 0xaa 56#define SMSC_FDC37M81X_CONFIG_EXIT 0xaa
57#define SMSC_FDC37M81X_CHIP_ID 0x4d 57#define SMSC_FDC37M81X_CHIP_ID 0x4d
58 58
59unsigned long __init smsc_fdc37m81x_init(unsigned long port); 59unsigned long smsc_fdc37m81x_init(unsigned long port);
60 60
61void smsc_fdc37m81x_config_beg(void); 61void smsc_fdc37m81x_config_beg(void);
62 62
diff --git a/include/asm-mips/txx9/tx3927.h b/include/asm-mips/txx9/tx3927.h
index ea79e1b16e7..587deb9592d 100644
--- a/include/asm-mips/txx9/tx3927.h
+++ b/include/asm-mips/txx9/tx3927.h
@@ -8,9 +8,8 @@
8#ifndef __ASM_TXX9_TX3927_H 8#ifndef __ASM_TXX9_TX3927_H
9#define __ASM_TXX9_TX3927_H 9#define __ASM_TXX9_TX3927_H
10 10
11#include <asm/txx9/txx927.h>
12
13#define TX3927_REG_BASE 0xfffe0000UL 11#define TX3927_REG_BASE 0xfffe0000UL
12#define TX3927_REG_SIZE 0x00010000
14#define TX3927_SDRAMC_REG (TX3927_REG_BASE + 0x8000) 13#define TX3927_SDRAMC_REG (TX3927_REG_BASE + 0x8000)
15#define TX3927_ROMC_REG (TX3927_REG_BASE + 0x9000) 14#define TX3927_ROMC_REG (TX3927_REG_BASE + 0x9000)
16#define TX3927_DMA_REG (TX3927_REG_BASE + 0xb000) 15#define TX3927_DMA_REG (TX3927_REG_BASE + 0xb000)
@@ -236,11 +235,17 @@ struct tx3927_ccfg_reg {
236/* see PCI_STATUS_XXX in linux/pci.h */ 235/* see PCI_STATUS_XXX in linux/pci.h */
237#define PCI_STATUS_NEW_CAP 0x0010 236#define PCI_STATUS_NEW_CAP 0x0010
238 237
238/* bits for ISTAT/IIM */
239#define TX3927_PCIC_IIM_ALL 0x00001600
240
239/* bits for TC */ 241/* bits for TC */
240#define TX3927_PCIC_TC_OF16E 0x00000020 242#define TX3927_PCIC_TC_OF16E 0x00000020
241#define TX3927_PCIC_TC_IF8E 0x00000010 243#define TX3927_PCIC_TC_IF8E 0x00000010
242#define TX3927_PCIC_TC_OF8E 0x00000008 244#define TX3927_PCIC_TC_OF8E 0x00000008
243 245
246/* bits for TSTAT/TIM */
247#define TX3927_PCIC_TIM_ALL 0x0003ffff
248
244/* bits for IOBA/MBA */ 249/* bits for IOBA/MBA */
245/* see PCI_BASE_ADDRESS_XXX in linux/pci.h */ 250/* see PCI_BASE_ADDRESS_XXX in linux/pci.h */
246 251
@@ -313,12 +318,22 @@ struct tx3927_ccfg_reg {
313#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG) 318#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG)
314#define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG) 319#define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG)
315#define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG) 320#define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG)
316#define tx3927_tmrptr(ch) ((struct txx927_tmr_reg *)TX3927_TMR_REG(ch))
317#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch)) 321#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch))
318#define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG) 322#define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG)
319 323
324#define TX3927_REV_PCODE() (tx3927_ccfgptr->crir >> 16)
325#define TX3927_ROMC_BA(ch) (tx3927_romcptr->cr[(ch)] & 0xfff00000)
326#define TX3927_ROMC_SIZE(ch) \
327 (0x00100000 << ((tx3927_romcptr->cr[(ch)] >> 8) & 0xf))
328
329void tx3927_wdt_init(void);
330void tx3927_setup(void);
331void tx3927_time_init(unsigned int evt_tmrnr, unsigned int src_tmrnr);
332void tx3927_sio_init(unsigned int sclk, unsigned int cts_mask);
320struct pci_controller; 333struct pci_controller;
321void __init tx3927_pcic_setup(struct pci_controller *channel, 334void tx3927_pcic_setup(struct pci_controller *channel,
322 unsigned long sdram_size, int extarb); 335 unsigned long sdram_size, int extarb);
336void tx3927_setup_pcierr_irq(void);
337void tx3927_irq_init(void);
323 338
324#endif /* __ASM_TXX9_TX3927_H */ 339#endif /* __ASM_TXX9_TX3927_H */
diff --git a/include/asm-mips/txx9/tx4927.h b/include/asm-mips/txx9/tx4927.h
index ceb4b79ff4e..195f6515db9 100644
--- a/include/asm-mips/txx9/tx4927.h
+++ b/include/asm-mips/txx9/tx4927.h
@@ -243,12 +243,13 @@ static inline void tx4927_ccfg_change(__u64 change, __u64 new)
243} 243}
244 244
245unsigned int tx4927_get_mem_size(void); 245unsigned int tx4927_get_mem_size(void);
246void tx4927_wdr_init(void); 246void tx4927_wdt_init(void);
247void tx4927_setup(void); 247void tx4927_setup(void);
248void tx4927_time_init(unsigned int tmrnr); 248void tx4927_time_init(unsigned int tmrnr);
249void tx4927_setup_serial(void); 249void tx4927_sio_init(unsigned int sclk, unsigned int cts_mask);
250int tx4927_report_pciclk(void); 250int tx4927_report_pciclk(void);
251int tx4927_pciclk66_setup(void); 251int tx4927_pciclk66_setup(void);
252void tx4927_setup_pcierr_irq(void);
252void tx4927_irq_init(void); 253void tx4927_irq_init(void);
253 254
254#endif /* __ASM_TXX9_TX4927_H */ 255#endif /* __ASM_TXX9_TX4927_H */
diff --git a/include/asm-mips/txx9/tx4927pcic.h b/include/asm-mips/txx9/tx4927pcic.h
index d61c3d09c4a..c470b8a5fe5 100644
--- a/include/asm-mips/txx9/tx4927pcic.h
+++ b/include/asm-mips/txx9/tx4927pcic.h
@@ -10,6 +10,7 @@
10#define __ASM_TXX9_TX4927PCIC_H 10#define __ASM_TXX9_TX4927PCIC_H
11 11
12#include <linux/pci.h> 12#include <linux/pci.h>
13#include <linux/irqreturn.h>
13 14
14struct tx4927_pcic_reg { 15struct tx4927_pcic_reg {
15 u32 pciid; 16 u32 pciid;
@@ -192,8 +193,11 @@ struct tx4927_pcic_reg {
192 193
193struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr( 194struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr(
194 struct pci_controller *channel); 195 struct pci_controller *channel);
195void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr, 196void tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr,
196 struct pci_controller *channel, int extarb); 197 struct pci_controller *channel, int extarb);
197void tx4927_report_pcic_status(void); 198void tx4927_report_pcic_status(void);
199char *tx4927_pcibios_setup(char *str);
200void tx4927_dump_pcic_settings(void);
201irqreturn_t tx4927_pcierr_interrupt(int irq, void *dev_id);
198 202
199#endif /* __ASM_TXX9_TX4927PCIC_H */ 203#endif /* __ASM_TXX9_TX4927PCIC_H */
diff --git a/include/asm-mips/txx9/tx4938.h b/include/asm-mips/txx9/tx4938.h
index 1ed969d381d..8175d4ccbc3 100644
--- a/include/asm-mips/txx9/tx4938.h
+++ b/include/asm-mips/txx9/tx4938.h
@@ -276,15 +276,18 @@ struct tx4938_ccfg_reg {
276#define TX4938_EBUSC_SIZE(ch) TX4927_EBUSC_SIZE(ch) 276#define TX4938_EBUSC_SIZE(ch) TX4927_EBUSC_SIZE(ch)
277 277
278#define tx4938_get_mem_size() tx4927_get_mem_size() 278#define tx4938_get_mem_size() tx4927_get_mem_size()
279void tx4938_wdr_init(void); 279void tx4938_wdt_init(void);
280void tx4938_setup(void); 280void tx4938_setup(void);
281void tx4938_time_init(unsigned int tmrnr); 281void tx4938_time_init(unsigned int tmrnr);
282void tx4938_setup_serial(void); 282void tx4938_sio_init(unsigned int sclk, unsigned int cts_mask);
283void tx4938_spi_init(int busid);
284void tx4938_ethaddr_init(unsigned char *addr0, unsigned char *addr1);
283int tx4938_report_pciclk(void); 285int tx4938_report_pciclk(void);
284void tx4938_report_pci1clk(void); 286void tx4938_report_pci1clk(void);
285int tx4938_pciclk66_setup(void); 287int tx4938_pciclk66_setup(void);
286struct pci_dev; 288struct pci_dev;
287int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot); 289int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot);
290void tx4938_setup_pcierr_irq(void);
288void tx4938_irq_init(void); 291void tx4938_irq_init(void);
289 292
290#endif 293#endif
diff --git a/include/asm-mips/txx9/txx927.h b/include/asm-mips/txx9/txx927.h
deleted file mode 100644
index 97dd7ad1a89..00000000000
--- a/include/asm-mips/txx9/txx927.h
+++ /dev/null
@@ -1,121 +0,0 @@
1/*
2 * Common definitions for TX3927/TX4927
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2000 Toshiba Corporation
9 */
10#ifndef __ASM_TXX9_TXX927_H
11#define __ASM_TXX9_TXX927_H
12
13struct txx927_sio_reg {
14 volatile unsigned long lcr;
15 volatile unsigned long dicr;
16 volatile unsigned long disr;
17 volatile unsigned long cisr;
18 volatile unsigned long fcr;
19 volatile unsigned long flcr;
20 volatile unsigned long bgr;
21 volatile unsigned long tfifo;
22 volatile unsigned long rfifo;
23};
24
25/*
26 * SIO
27 */
28/* SILCR : Line Control */
29#define TXx927_SILCR_SCS_MASK 0x00000060
30#define TXx927_SILCR_SCS_IMCLK 0x00000000
31#define TXx927_SILCR_SCS_IMCLK_BG 0x00000020
32#define TXx927_SILCR_SCS_SCLK 0x00000040
33#define TXx927_SILCR_SCS_SCLK_BG 0x00000060
34#define TXx927_SILCR_UEPS 0x00000010
35#define TXx927_SILCR_UPEN 0x00000008
36#define TXx927_SILCR_USBL_MASK 0x00000004
37#define TXx927_SILCR_USBL_1BIT 0x00000004
38#define TXx927_SILCR_USBL_2BIT 0x00000000
39#define TXx927_SILCR_UMODE_MASK 0x00000003
40#define TXx927_SILCR_UMODE_8BIT 0x00000000
41#define TXx927_SILCR_UMODE_7BIT 0x00000001
42
43/* SIDICR : DMA/Int. Control */
44#define TXx927_SIDICR_TDE 0x00008000
45#define TXx927_SIDICR_RDE 0x00004000
46#define TXx927_SIDICR_TIE 0x00002000
47#define TXx927_SIDICR_RIE 0x00001000
48#define TXx927_SIDICR_SPIE 0x00000800
49#define TXx927_SIDICR_CTSAC 0x00000600
50#define TXx927_SIDICR_STIE_MASK 0x0000003f
51#define TXx927_SIDICR_STIE_OERS 0x00000020
52#define TXx927_SIDICR_STIE_CTSS 0x00000010
53#define TXx927_SIDICR_STIE_RBRKD 0x00000008
54#define TXx927_SIDICR_STIE_TRDY 0x00000004
55#define TXx927_SIDICR_STIE_TXALS 0x00000002
56#define TXx927_SIDICR_STIE_UBRKD 0x00000001
57
58/* SIDISR : DMA/Int. Status */
59#define TXx927_SIDISR_UBRK 0x00008000
60#define TXx927_SIDISR_UVALID 0x00004000
61#define TXx927_SIDISR_UFER 0x00002000
62#define TXx927_SIDISR_UPER 0x00001000
63#define TXx927_SIDISR_UOER 0x00000800
64#define TXx927_SIDISR_ERI 0x00000400
65#define TXx927_SIDISR_TOUT 0x00000200
66#define TXx927_SIDISR_TDIS 0x00000100
67#define TXx927_SIDISR_RDIS 0x00000080
68#define TXx927_SIDISR_STIS 0x00000040
69#define TXx927_SIDISR_RFDN_MASK 0x0000001f
70
71/* SICISR : Change Int. Status */
72#define TXx927_SICISR_OERS 0x00000020
73#define TXx927_SICISR_CTSS 0x00000010
74#define TXx927_SICISR_RBRKD 0x00000008
75#define TXx927_SICISR_TRDY 0x00000004
76#define TXx927_SICISR_TXALS 0x00000002
77#define TXx927_SICISR_UBRKD 0x00000001
78
79/* SIFCR : FIFO Control */
80#define TXx927_SIFCR_SWRST 0x00008000
81#define TXx927_SIFCR_RDIL_MASK 0x00000180
82#define TXx927_SIFCR_RDIL_1 0x00000000
83#define TXx927_SIFCR_RDIL_4 0x00000080
84#define TXx927_SIFCR_RDIL_8 0x00000100
85#define TXx927_SIFCR_RDIL_12 0x00000180
86#define TXx927_SIFCR_RDIL_MAX 0x00000180
87#define TXx927_SIFCR_TDIL_MASK 0x00000018
88#define TXx927_SIFCR_TDIL_MASK 0x00000018
89#define TXx927_SIFCR_TDIL_1 0x00000000
90#define TXx927_SIFCR_TDIL_4 0x00000001
91#define TXx927_SIFCR_TDIL_8 0x00000010
92#define TXx927_SIFCR_TDIL_MAX 0x00000010
93#define TXx927_SIFCR_TFRST 0x00000004
94#define TXx927_SIFCR_RFRST 0x00000002
95#define TXx927_SIFCR_FRSTE 0x00000001
96#define TXx927_SIO_TX_FIFO 8
97#define TXx927_SIO_RX_FIFO 16
98
99/* SIFLCR : Flow Control */
100#define TXx927_SIFLCR_RCS 0x00001000
101#define TXx927_SIFLCR_TES 0x00000800
102#define TXx927_SIFLCR_RTSSC 0x00000200
103#define TXx927_SIFLCR_RSDE 0x00000100
104#define TXx927_SIFLCR_TSDE 0x00000080
105#define TXx927_SIFLCR_RTSTL_MASK 0x0000001e
106#define TXx927_SIFLCR_RTSTL_MAX 0x0000001e
107#define TXx927_SIFLCR_TBRK 0x00000001
108
109/* SIBGR : Baudrate Control */
110#define TXx927_SIBGR_BCLK_MASK 0x00000300
111#define TXx927_SIBGR_BCLK_T0 0x00000000
112#define TXx927_SIBGR_BCLK_T2 0x00000100
113#define TXx927_SIBGR_BCLK_T4 0x00000200
114#define TXx927_SIBGR_BCLK_T6 0x00000300
115#define TXx927_SIBGR_BRD_MASK 0x000000ff
116
117/*
118 * PIO
119 */
120
121#endif /* __ASM_TXX9_TXX927_H */
diff --git a/include/asm-mips/txx9irq.h b/include/asm-mips/txx9irq.h
index 1c439e51b87..5620879be37 100644
--- a/include/asm-mips/txx9irq.h
+++ b/include/asm-mips/txx9irq.h
@@ -14,8 +14,12 @@
14#ifdef CONFIG_IRQ_CPU 14#ifdef CONFIG_IRQ_CPU
15#define TXX9_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) 15#define TXX9_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
16#else 16#else
17#ifdef CONFIG_I8259
18#define TXX9_IRQ_BASE (I8259A_IRQ_BASE + 16)
19#else
17#define TXX9_IRQ_BASE 0 20#define TXX9_IRQ_BASE 0
18#endif 21#endif
22#endif
19 23
20#ifdef CONFIG_CPU_TX39XX 24#ifdef CONFIG_CPU_TX39XX
21#define TXx9_MAX_IR 16 25#define TXx9_MAX_IR 16
diff --git a/include/asm-mn10300/unistd.h b/include/asm-mn10300/unistd.h
index 3721aa9e195..543a4f98695 100644
--- a/include/asm-mn10300/unistd.h
+++ b/include/asm-mn10300/unistd.h
@@ -338,6 +338,12 @@
338#define __NR_fallocate 325 338#define __NR_fallocate 325
339#define __NR_timerfd_settime 326 339#define __NR_timerfd_settime 326
340#define __NR_timerfd_gettime 327 340#define __NR_timerfd_gettime 327
341#define __NR_signalfd4 328
342#define __NR_eventfd2 329
343#define __NR_epoll_create1 330
344#define __NR_dup3 331
345#define __NR_pipe2 332
346#define __NR_inotify_init1 333
341 347
342#ifdef __KERNEL__ 348#ifdef __KERNEL__
343 349
diff --git a/include/asm-powerpc/8253pit.h b/include/asm-powerpc/8253pit.h
deleted file mode 100644
index b70d6e53b30..00000000000
--- a/include/asm-powerpc/8253pit.h
+++ /dev/null
@@ -1,10 +0,0 @@
1#ifndef _ASM_POWERPC_8253PIT_H
2#define _ASM_POWERPC_8253PIT_H
3
4/*
5 * 8253/8254 Programmable Interval Timer
6 */
7
8#define PIT_TICK_RATE 1193182UL
9
10#endif /* _ASM_POWERPC_8253PIT_H */
diff --git a/include/asm-powerpc/8xx_immap.h b/include/asm-powerpc/8xx_immap.h
deleted file mode 100644
index 4b0e1520600..00000000000
--- a/include/asm-powerpc/8xx_immap.h
+++ /dev/null
@@ -1,564 +0,0 @@
1/*
2 * MPC8xx Internal Memory Map
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * The I/O on the MPC860 is comprised of blocks of special registers
6 * and the dual port ram for the Communication Processor Module.
7 * Within this space are functional units such as the SIU, memory
8 * controller, system timers, and other control functions. It is
9 * a combination that I found difficult to separate into logical
10 * functional files.....but anyone else is welcome to try. -- Dan
11 */
12#ifdef __KERNEL__
13#ifndef __IMMAP_8XX__
14#define __IMMAP_8XX__
15
16/* System configuration registers.
17*/
18typedef struct sys_conf {
19 uint sc_siumcr;
20 uint sc_sypcr;
21 uint sc_swt;
22 char res1[2];
23 ushort sc_swsr;
24 uint sc_sipend;
25 uint sc_simask;
26 uint sc_siel;
27 uint sc_sivec;
28 uint sc_tesr;
29 char res2[0xc];
30 uint sc_sdcr;
31 char res3[0x4c];
32} sysconf8xx_t;
33
34/* PCMCIA configuration registers.
35*/
36typedef struct pcmcia_conf {
37 uint pcmc_pbr0;
38 uint pcmc_por0;
39 uint pcmc_pbr1;
40 uint pcmc_por1;
41 uint pcmc_pbr2;
42 uint pcmc_por2;
43 uint pcmc_pbr3;
44 uint pcmc_por3;
45 uint pcmc_pbr4;
46 uint pcmc_por4;
47 uint pcmc_pbr5;
48 uint pcmc_por5;
49 uint pcmc_pbr6;
50 uint pcmc_por6;
51 uint pcmc_pbr7;
52 uint pcmc_por7;
53 char res1[0x20];
54 uint pcmc_pgcra;
55 uint pcmc_pgcrb;
56 uint pcmc_pscr;
57 char res2[4];
58 uint pcmc_pipr;
59 char res3[4];
60 uint pcmc_per;
61 char res4[4];
62} pcmconf8xx_t;
63
64/* Memory controller registers.
65*/
66typedef struct mem_ctlr {
67 uint memc_br0;
68 uint memc_or0;
69 uint memc_br1;
70 uint memc_or1;
71 uint memc_br2;
72 uint memc_or2;
73 uint memc_br3;
74 uint memc_or3;
75 uint memc_br4;
76 uint memc_or4;
77 uint memc_br5;
78 uint memc_or5;
79 uint memc_br6;
80 uint memc_or6;
81 uint memc_br7;
82 uint memc_or7;
83 char res1[0x24];
84 uint memc_mar;
85 uint memc_mcr;
86 char res2[4];
87 uint memc_mamr;
88 uint memc_mbmr;
89 ushort memc_mstat;
90 ushort memc_mptpr;
91 uint memc_mdr;
92 char res3[0x80];
93} memctl8xx_t;
94
95/*-----------------------------------------------------------------------
96 * BR - Memory Controler: Base Register 16-9
97 */
98#define BR_BA_MSK 0xffff8000 /* Base Address Mask */
99#define BR_AT_MSK 0x00007000 /* Address Type Mask */
100#define BR_PS_MSK 0x00000c00 /* Port Size Mask */
101#define BR_PS_32 0x00000000 /* 32 bit port size */
102#define BR_PS_16 0x00000800 /* 16 bit port size */
103#define BR_PS_8 0x00000400 /* 8 bit port size */
104#define BR_PARE 0x00000200 /* Parity Enable */
105#define BR_WP 0x00000100 /* Write Protect */
106#define BR_MS_MSK 0x000000c0 /* Machine Select Mask */
107#define BR_MS_GPCM 0x00000000 /* G.P.C.M. Machine Select */
108#define BR_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */
109#define BR_MS_UPMB 0x000000c0 /* U.P.M.B Machine Select */
110#define BR_V 0x00000001 /* Bank Valid */
111
112/*-----------------------------------------------------------------------
113 * OR - Memory Controler: Option Register 16-11
114 */
115#define OR_AM_MSK 0xffff8000 /* Address Mask Mask */
116#define OR_ATM_MSK 0x00007000 /* Address Type Mask Mask */
117#define OR_CSNT_SAM 0x00000800 /* Chip Select Negation Time/ Start */
118 /* Address Multiplex */
119#define OR_ACS_MSK 0x00000600 /* Address to Chip Select Setup mask */
120#define OR_ACS_DIV1 0x00000000 /* CS is output at the same time */
121#define OR_ACS_DIV4 0x00000400 /* CS is output 1/4 a clock later */
122#define OR_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later */
123#define OR_G5LA 0x00000400 /* Output #GPL5 on #GPL_A5 */
124#define OR_G5LS 0x00000200 /* Drive #GPL high on falling edge of...*/
125#define OR_BI 0x00000100 /* Burst inhibit */
126#define OR_SCY_MSK 0x000000f0 /* Cycle Length in Clocks */
127#define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */
128#define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */
129#define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */
130#define OR_SCY_3_CLK 0x00000030 /* 3 clock cycles wait states */
131#define OR_SCY_4_CLK 0x00000040 /* 4 clock cycles wait states */
132#define OR_SCY_5_CLK 0x00000050 /* 5 clock cycles wait states */
133#define OR_SCY_6_CLK 0x00000060 /* 6 clock cycles wait states */
134#define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */
135#define OR_SCY_8_CLK 0x00000080 /* 8 clock cycles wait states */
136#define OR_SCY_9_CLK 0x00000090 /* 9 clock cycles wait states */
137#define OR_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */
138#define OR_SCY_11_CLK 0x000000b0 /* 11 clock cycles wait states */
139#define OR_SCY_12_CLK 0x000000c0 /* 12 clock cycles wait states */
140#define OR_SCY_13_CLK 0x000000d0 /* 13 clock cycles wait states */
141#define OR_SCY_14_CLK 0x000000e0 /* 14 clock cycles wait states */
142#define OR_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */
143#define OR_SETA 0x00000008 /* External Transfer Acknowledge */
144#define OR_TRLX 0x00000004 /* Timing Relaxed */
145#define OR_EHTR 0x00000002 /* Extended Hold Time on Read */
146
147/* System Integration Timers.
148*/
149typedef struct sys_int_timers {
150 ushort sit_tbscr;
151 char res0[0x02];
152 uint sit_tbreff0;
153 uint sit_tbreff1;
154 char res1[0x14];
155 ushort sit_rtcsc;
156 char res2[0x02];
157 uint sit_rtc;
158 uint sit_rtsec;
159 uint sit_rtcal;
160 char res3[0x10];
161 ushort sit_piscr;
162 char res4[2];
163 uint sit_pitc;
164 uint sit_pitr;
165 char res5[0x34];
166} sit8xx_t;
167
168#define TBSCR_TBIRQ_MASK ((ushort)0xff00)
169#define TBSCR_REFA ((ushort)0x0080)
170#define TBSCR_REFB ((ushort)0x0040)
171#define TBSCR_REFAE ((ushort)0x0008)
172#define TBSCR_REFBE ((ushort)0x0004)
173#define TBSCR_TBF ((ushort)0x0002)
174#define TBSCR_TBE ((ushort)0x0001)
175
176#define RTCSC_RTCIRQ_MASK ((ushort)0xff00)
177#define RTCSC_SEC ((ushort)0x0080)
178#define RTCSC_ALR ((ushort)0x0040)
179#define RTCSC_38K ((ushort)0x0010)
180#define RTCSC_SIE ((ushort)0x0008)
181#define RTCSC_ALE ((ushort)0x0004)
182#define RTCSC_RTF ((ushort)0x0002)
183#define RTCSC_RTE ((ushort)0x0001)
184
185#define PISCR_PIRQ_MASK ((ushort)0xff00)
186#define PISCR_PS ((ushort)0x0080)
187#define PISCR_PIE ((ushort)0x0004)
188#define PISCR_PTF ((ushort)0x0002)
189#define PISCR_PTE ((ushort)0x0001)
190
191/* Clocks and Reset.
192*/
193typedef struct clk_and_reset {
194 uint car_sccr;
195 uint car_plprcr;
196 uint car_rsr;
197 char res[0x74]; /* Reserved area */
198} car8xx_t;
199
200/* System Integration Timers keys.
201*/
202typedef struct sitk {
203 uint sitk_tbscrk;
204 uint sitk_tbreff0k;
205 uint sitk_tbreff1k;
206 uint sitk_tbk;
207 char res1[0x10];
208 uint sitk_rtcsck;
209 uint sitk_rtck;
210 uint sitk_rtseck;
211 uint sitk_rtcalk;
212 char res2[0x10];
213 uint sitk_piscrk;
214 uint sitk_pitck;
215 char res3[0x38];
216} sitk8xx_t;
217
218/* Clocks and reset keys.
219*/
220typedef struct cark {
221 uint cark_sccrk;
222 uint cark_plprcrk;
223 uint cark_rsrk;
224 char res[0x474];
225} cark8xx_t;
226
227/* The key to unlock registers maintained by keep-alive power.
228*/
229#define KAPWR_KEY ((unsigned int)0x55ccaa33)
230
231/* Video interface. MPC823 Only.
232*/
233typedef struct vid823 {
234 ushort vid_vccr;
235 ushort res1;
236 u_char vid_vsr;
237 u_char res2;
238 u_char vid_vcmr;
239 u_char res3;
240 uint vid_vbcb;
241 uint res4;
242 uint vid_vfcr0;
243 uint vid_vfaa0;
244 uint vid_vfba0;
245 uint vid_vfcr1;
246 uint vid_vfaa1;
247 uint vid_vfba1;
248 u_char res5[0x18];
249} vid823_t;
250
251/* LCD interface. 823 Only.
252*/
253typedef struct lcd {
254 uint lcd_lccr;
255 uint lcd_lchcr;
256 uint lcd_lcvcr;
257 char res1[4];
258 uint lcd_lcfaa;
259 uint lcd_lcfba;
260 char lcd_lcsr;
261 char res2[0x7];
262} lcd823_t;
263
264/* I2C
265*/
266typedef struct i2c {
267 u_char i2c_i2mod;
268 char res1[3];
269 u_char i2c_i2add;
270 char res2[3];
271 u_char i2c_i2brg;
272 char res3[3];
273 u_char i2c_i2com;
274 char res4[3];
275 u_char i2c_i2cer;
276 char res5[3];
277 u_char i2c_i2cmr;
278 char res6[0x8b];
279} i2c8xx_t;
280
281/* DMA control/status registers.
282*/
283typedef struct sdma_csr {
284 char res1[4];
285 uint sdma_sdar;
286 u_char sdma_sdsr;
287 char res3[3];
288 u_char sdma_sdmr;
289 char res4[3];
290 u_char sdma_idsr1;
291 char res5[3];
292 u_char sdma_idmr1;
293 char res6[3];
294 u_char sdma_idsr2;
295 char res7[3];
296 u_char sdma_idmr2;
297 char res8[0x13];
298} sdma8xx_t;
299
300/* Communication Processor Module Interrupt Controller.
301*/
302typedef struct cpm_ic {
303 ushort cpic_civr;
304 char res[0xe];
305 uint cpic_cicr;
306 uint cpic_cipr;
307 uint cpic_cimr;
308 uint cpic_cisr;
309} cpic8xx_t;
310
311/* Input/Output Port control/status registers.
312*/
313typedef struct io_port {
314 ushort iop_padir;
315 ushort iop_papar;
316 ushort iop_paodr;
317 ushort iop_padat;
318 char res1[8];
319 ushort iop_pcdir;
320 ushort iop_pcpar;
321 ushort iop_pcso;
322 ushort iop_pcdat;
323 ushort iop_pcint;
324 char res2[6];
325 ushort iop_pddir;
326 ushort iop_pdpar;
327 char res3[2];
328 ushort iop_pddat;
329 uint utmode;
330 char res4[4];
331} iop8xx_t;
332
333/* Communication Processor Module Timers
334*/
335typedef struct cpm_timers {
336 ushort cpmt_tgcr;
337 char res1[0xe];
338 ushort cpmt_tmr1;
339 ushort cpmt_tmr2;
340 ushort cpmt_trr1;
341 ushort cpmt_trr2;
342 ushort cpmt_tcr1;
343 ushort cpmt_tcr2;
344 ushort cpmt_tcn1;
345 ushort cpmt_tcn2;
346 ushort cpmt_tmr3;
347 ushort cpmt_tmr4;
348 ushort cpmt_trr3;
349 ushort cpmt_trr4;
350 ushort cpmt_tcr3;
351 ushort cpmt_tcr4;
352 ushort cpmt_tcn3;
353 ushort cpmt_tcn4;
354 ushort cpmt_ter1;
355 ushort cpmt_ter2;
356 ushort cpmt_ter3;
357 ushort cpmt_ter4;
358 char res2[8];
359} cpmtimer8xx_t;
360
361/* Finally, the Communication Processor stuff.....
362*/
363typedef struct scc { /* Serial communication channels */
364 uint scc_gsmrl;
365 uint scc_gsmrh;
366 ushort scc_psmr;
367 char res1[2];
368 ushort scc_todr;
369 ushort scc_dsr;
370 ushort scc_scce;
371 char res2[2];
372 ushort scc_sccm;
373 char res3;
374 u_char scc_sccs;
375 char res4[8];
376} scc_t;
377
378typedef struct smc { /* Serial management channels */
379 char res1[2];
380 ushort smc_smcmr;
381 char res2[2];
382 u_char smc_smce;
383 char res3[3];
384 u_char smc_smcm;
385 char res4[5];
386} smc_t;
387
388/* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but
389 * it fits within the address space.
390 */
391
392typedef struct fec {
393 uint fec_addr_low; /* lower 32 bits of station address */
394 ushort fec_addr_high; /* upper 16 bits of station address */
395 ushort res1; /* reserved */
396 uint fec_hash_table_high; /* upper 32-bits of hash table */
397 uint fec_hash_table_low; /* lower 32-bits of hash table */
398 uint fec_r_des_start; /* beginning of Rx descriptor ring */
399 uint fec_x_des_start; /* beginning of Tx descriptor ring */
400 uint fec_r_buff_size; /* Rx buffer size */
401 uint res2[9]; /* reserved */
402 uint fec_ecntrl; /* ethernet control register */
403 uint fec_ievent; /* interrupt event register */
404 uint fec_imask; /* interrupt mask register */
405 uint fec_ivec; /* interrupt level and vector status */
406 uint fec_r_des_active; /* Rx ring updated flag */
407 uint fec_x_des_active; /* Tx ring updated flag */
408 uint res3[10]; /* reserved */
409 uint fec_mii_data; /* MII data register */
410 uint fec_mii_speed; /* MII speed control register */
411 uint res4[17]; /* reserved */
412 uint fec_r_bound; /* end of RAM (read-only) */
413 uint fec_r_fstart; /* Rx FIFO start address */
414 uint res5[6]; /* reserved */
415 uint fec_x_fstart; /* Tx FIFO start address */
416 uint res6[17]; /* reserved */
417 uint fec_fun_code; /* fec SDMA function code */
418 uint res7[3]; /* reserved */
419 uint fec_r_cntrl; /* Rx control register */
420 uint fec_r_hash; /* Rx hash register */
421 uint res8[14]; /* reserved */
422 uint fec_x_cntrl; /* Tx control register */
423 uint res9[0x1e]; /* reserved */
424} fec_t;
425
426/* The FEC and LCD color map share the same address space....
427 * I guess we will never see an 823T :-).
428 */
429union fec_lcd {
430 fec_t fl_un_fec;
431 u_char fl_un_cmap[0x200];
432};
433
434typedef struct comm_proc {
435 /* General control and status registers.
436 */
437 ushort cp_cpcr;
438 u_char res1[2];
439 ushort cp_rccr;
440 u_char res2;
441 u_char cp_rmds;
442 u_char res3[4];
443 ushort cp_cpmcr1;
444 ushort cp_cpmcr2;
445 ushort cp_cpmcr3;
446 ushort cp_cpmcr4;
447 u_char res4[2];
448 ushort cp_rter;
449 u_char res5[2];
450 ushort cp_rtmr;
451 u_char res6[0x14];
452
453 /* Baud rate generators.
454 */
455 uint cp_brgc1;
456 uint cp_brgc2;
457 uint cp_brgc3;
458 uint cp_brgc4;
459
460 /* Serial Communication Channels.
461 */
462 scc_t cp_scc[4];
463
464 /* Serial Management Channels.
465 */
466 smc_t cp_smc[2];
467
468 /* Serial Peripheral Interface.
469 */
470 ushort cp_spmode;
471 u_char res7[4];
472 u_char cp_spie;
473 u_char res8[3];
474 u_char cp_spim;
475 u_char res9[2];
476 u_char cp_spcom;
477 u_char res10[2];
478
479 /* Parallel Interface Port.
480 */
481 u_char res11[2];
482 ushort cp_pipc;
483 u_char res12[2];
484 ushort cp_ptpr;
485 uint cp_pbdir;
486 uint cp_pbpar;
487 u_char res13[2];
488 ushort cp_pbodr;
489 uint cp_pbdat;
490
491 /* Port E - MPC87x/88x only.
492 */
493 uint cp_pedir;
494 uint cp_pepar;
495 uint cp_peso;
496 uint cp_peodr;
497 uint cp_pedat;
498
499 /* Communications Processor Timing Register -
500 Contains RMII Timing for the FECs on MPC87x/88x only.
501 */
502 uint cp_cptr;
503
504 /* Serial Interface and Time Slot Assignment.
505 */
506 uint cp_simode;
507 u_char cp_sigmr;
508 u_char res15;
509 u_char cp_sistr;
510 u_char cp_sicmr;
511 u_char res16[4];
512 uint cp_sicr;
513 uint cp_sirp;
514 u_char res17[0xc];
515
516 /* 256 bytes of MPC823 video controller RAM array.
517 */
518 u_char cp_vcram[0x100];
519 u_char cp_siram[0x200];
520
521 /* The fast ethernet controller is not really part of the CPM,
522 * but it resides in the address space.
523 * The LCD color map is also here.
524 */
525 union fec_lcd fl_un;
526#define cp_fec fl_un.fl_un_fec
527#define lcd_cmap fl_un.fl_un_cmap
528 char res18[0xE00];
529
530 /* The DUET family has a second FEC here */
531 fec_t cp_fec2;
532#define cp_fec1 cp_fec /* consistency macro */
533
534 /* Dual Ported RAM follows.
535 * There are many different formats for this memory area
536 * depending upon the devices used and options chosen.
537 * Some processors don't have all of it populated.
538 */
539 u_char cp_dpmem[0x1C00]; /* BD / Data / ucode */
540 u_char cp_dparam[0x400]; /* Parameter RAM */
541} cpm8xx_t;
542
543/* Internal memory map.
544*/
545typedef struct immap {
546 sysconf8xx_t im_siu_conf; /* SIU Configuration */
547 pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */
548 memctl8xx_t im_memctl; /* Memory Controller */
549 sit8xx_t im_sit; /* System integration timers */
550 car8xx_t im_clkrst; /* Clocks and reset */
551 sitk8xx_t im_sitk; /* Sys int timer keys */
552 cark8xx_t im_clkrstk; /* Clocks and reset keys */
553 vid823_t im_vid; /* Video (823 only) */
554 lcd823_t im_lcd; /* LCD (823 only) */
555 i2c8xx_t im_i2c; /* I2C control/status */
556 sdma8xx_t im_sdma; /* SDMA control/status */
557 cpic8xx_t im_cpic; /* CPM Interrupt Controller */
558 iop8xx_t im_ioport; /* IO Port control/status */
559 cpmtimer8xx_t im_cpmtimer; /* CPM timers */
560 cpm8xx_t im_cpm; /* Communication processor */
561} immap_t;
562
563#endif /* __IMMAP_8XX__ */
564#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/Kbuild b/include/asm-powerpc/Kbuild
deleted file mode 100644
index 5ab7d7fe198..00000000000
--- a/include/asm-powerpc/Kbuild
+++ /dev/null
@@ -1,37 +0,0 @@
1include include/asm-generic/Kbuild.asm
2
3header-y += auxvec.h
4header-y += ioctls.h
5header-y += sembuf.h
6header-y += siginfo.h
7header-y += stat.h
8header-y += errno.h
9header-y += ipcbuf.h
10header-y += msgbuf.h
11header-y += shmbuf.h
12header-y += socket.h
13header-y += termbits.h
14header-y += fcntl.h
15header-y += poll.h
16header-y += sockios.h
17header-y += ucontext.h
18header-y += ioctl.h
19header-y += linkage.h
20header-y += resource.h
21header-y += sigcontext.h
22header-y += statfs.h
23header-y += ps3fb.h
24
25unifdef-y += bootx.h
26unifdef-y += byteorder.h
27unifdef-y += cputable.h
28unifdef-y += elf.h
29unifdef-y += nvram.h
30unifdef-y += param.h
31unifdef-y += posix_types.h
32unifdef-y += seccomp.h
33unifdef-y += signal.h
34unifdef-y += spu_info.h
35unifdef-y += termios.h
36unifdef-y += types.h
37unifdef-y += unistd.h
diff --git a/include/asm-powerpc/a.out.h b/include/asm-powerpc/a.out.h
deleted file mode 100644
index 89cead6b176..00000000000
--- a/include/asm-powerpc/a.out.h
+++ /dev/null
@@ -1,20 +0,0 @@
1#ifndef _ASM_POWERPC_A_OUT_H
2#define _ASM_POWERPC_A_OUT_H
3
4struct exec
5{
6 unsigned long a_info; /* Use macros N_MAGIC, etc for access */
7 unsigned a_text; /* length of text, in bytes */
8 unsigned a_data; /* length of data, in bytes */
9 unsigned a_bss; /* length of uninitialized data area for file, in bytes */
10 unsigned a_syms; /* length of symbol table data in file, in bytes */
11 unsigned a_entry; /* start address */
12 unsigned a_trsize; /* length of relocation info for text, in bytes */
13 unsigned a_drsize; /* length of relocation info for data, in bytes */
14};
15
16#define N_TRSIZE(a) ((a).a_trsize)
17#define N_DRSIZE(a) ((a).a_drsize)
18#define N_SYMSIZE(a) ((a).a_syms)
19
20#endif /* _ASM_POWERPC_A_OUT_H */
diff --git a/include/asm-powerpc/abs_addr.h b/include/asm-powerpc/abs_addr.h
deleted file mode 100644
index 98324c5a828..00000000000
--- a/include/asm-powerpc/abs_addr.h
+++ /dev/null
@@ -1,75 +0,0 @@
1#ifndef _ASM_POWERPC_ABS_ADDR_H
2#define _ASM_POWERPC_ABS_ADDR_H
3#ifdef __KERNEL__
4
5
6/*
7 * c 2001 PPC 64 Team, IBM Corp
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14
15#include <linux/lmb.h>
16
17#include <asm/types.h>
18#include <asm/page.h>
19#include <asm/prom.h>
20#include <asm/firmware.h>
21
22struct mschunks_map {
23 unsigned long num_chunks;
24 unsigned long chunk_size;
25 unsigned long chunk_shift;
26 unsigned long chunk_mask;
27 u32 *mapping;
28};
29
30extern struct mschunks_map mschunks_map;
31
32/* Chunks are 256 KB */
33#define MSCHUNKS_CHUNK_SHIFT (18)
34#define MSCHUNKS_CHUNK_SIZE (1UL << MSCHUNKS_CHUNK_SHIFT)
35#define MSCHUNKS_OFFSET_MASK (MSCHUNKS_CHUNK_SIZE - 1)
36
37static inline unsigned long chunk_to_addr(unsigned long chunk)
38{
39 return chunk << MSCHUNKS_CHUNK_SHIFT;
40}
41
42static inline unsigned long addr_to_chunk(unsigned long addr)
43{
44 return addr >> MSCHUNKS_CHUNK_SHIFT;
45}
46
47static inline unsigned long phys_to_abs(unsigned long pa)
48{
49 unsigned long chunk;
50
51 /* This is a no-op on non-iSeries */
52 if (!firmware_has_feature(FW_FEATURE_ISERIES))
53 return pa;
54
55 chunk = addr_to_chunk(pa);
56
57 if (chunk < mschunks_map.num_chunks)
58 chunk = mschunks_map.mapping[chunk];
59
60 return chunk_to_addr(chunk) + (pa & MSCHUNKS_OFFSET_MASK);
61}
62
63/* Convenience macros */
64#define virt_to_abs(va) phys_to_abs(__pa(va))
65#define abs_to_virt(aa) __va(aa)
66
67/*
68 * Converts Virtual Address to Real Address for
69 * Legacy iSeries Hypervisor calls
70 */
71#define iseries_hv_addr(virtaddr) \
72 (0x8000000000000000 | virt_to_abs(virtaddr))
73
74#endif /* __KERNEL__ */
75#endif /* _ASM_POWERPC_ABS_ADDR_H */
diff --git a/include/asm-powerpc/agp.h b/include/asm-powerpc/agp.h
deleted file mode 100644
index 86455c4c31e..00000000000
--- a/include/asm-powerpc/agp.h
+++ /dev/null
@@ -1,22 +0,0 @@
1#ifndef _ASM_POWERPC_AGP_H
2#define _ASM_POWERPC_AGP_H
3#ifdef __KERNEL__
4
5#include <asm/io.h>
6
7#define map_page_into_agp(page)
8#define unmap_page_from_agp(page)
9#define flush_agp_cache() mb()
10
11/* Convert a physical address to an address suitable for the GART. */
12#define phys_to_gart(x) (x)
13#define gart_to_phys(x) (x)
14
15/* GATT allocation. Returns/accepts GATT kernel virtual address. */
16#define alloc_gatt_pages(order) \
17 ((char *)__get_free_pages(GFP_KERNEL, (order)))
18#define free_gatt_pages(table, order) \
19 free_pages((unsigned long)(table), (order))
20
21#endif /* __KERNEL__ */
22#endif /* _ASM_POWERPC_AGP_H */
diff --git a/include/asm-powerpc/asm-compat.h b/include/asm-powerpc/asm-compat.h
deleted file mode 100644
index 8f0fe797194..00000000000
--- a/include/asm-powerpc/asm-compat.h
+++ /dev/null
@@ -1,69 +0,0 @@
1#ifndef _ASM_POWERPC_ASM_COMPAT_H
2#define _ASM_POWERPC_ASM_COMPAT_H
3
4#include <asm/types.h>
5
6#ifdef __ASSEMBLY__
7# define stringify_in_c(...) __VA_ARGS__
8# define ASM_CONST(x) x
9#else
10/* This version of stringify will deal with commas... */
11# define __stringify_in_c(...) #__VA_ARGS__
12# define stringify_in_c(...) __stringify_in_c(__VA_ARGS__) " "
13# define __ASM_CONST(x) x##UL
14# define ASM_CONST(x) __ASM_CONST(x)
15#endif
16
17
18#ifdef __powerpc64__
19
20/* operations for longs and pointers */
21#define PPC_LL stringify_in_c(ld)
22#define PPC_STL stringify_in_c(std)
23#define PPC_LCMPI stringify_in_c(cmpdi)
24#define PPC_LONG stringify_in_c(.llong)
25#define PPC_LONG_ALIGN stringify_in_c(.balign 8)
26#define PPC_TLNEI stringify_in_c(tdnei)
27#define PPC_LLARX stringify_in_c(ldarx)
28#define PPC_STLCX stringify_in_c(stdcx.)
29#define PPC_CNTLZL stringify_in_c(cntlzd)
30
31/* Move to CR, single-entry optimized version. Only available
32 * on POWER4 and later.
33 */
34#ifdef CONFIG_POWER4_ONLY
35#define PPC_MTOCRF stringify_in_c(mtocrf)
36#else
37#define PPC_MTOCRF stringify_in_c(mtcrf)
38#endif
39
40#else /* 32-bit */
41
42/* operations for longs and pointers */
43#define PPC_LL stringify_in_c(lwz)
44#define PPC_STL stringify_in_c(stw)
45#define PPC_LCMPI stringify_in_c(cmpwi)
46#define PPC_LONG stringify_in_c(.long)
47#define PPC_LONG_ALIGN stringify_in_c(.balign 4)
48#define PPC_TLNEI stringify_in_c(twnei)
49#define PPC_LLARX stringify_in_c(lwarx)
50#define PPC_STLCX stringify_in_c(stwcx.)
51#define PPC_CNTLZL stringify_in_c(cntlzw)
52#define PPC_MTOCRF stringify_in_c(mtcrf)
53
54#endif
55
56#ifdef __KERNEL__
57#ifdef CONFIG_IBM405_ERR77
58/* Erratum #77 on the 405 means we need a sync or dcbt before every
59 * stwcx. The old ATOMIC_SYNC_FIX covered some but not all of this.
60 */
61#define PPC405_ERR77(ra,rb) stringify_in_c(dcbt ra, rb;)
62#define PPC405_ERR77_SYNC stringify_in_c(sync;)
63#else
64#define PPC405_ERR77(ra,rb)
65#define PPC405_ERR77_SYNC
66#endif
67#endif
68
69#endif /* _ASM_POWERPC_ASM_COMPAT_H */
diff --git a/include/asm-powerpc/atomic.h b/include/asm-powerpc/atomic.h
deleted file mode 100644
index f3fc733758f..00000000000
--- a/include/asm-powerpc/atomic.h
+++ /dev/null
@@ -1,479 +0,0 @@
1#ifndef _ASM_POWERPC_ATOMIC_H_
2#define _ASM_POWERPC_ATOMIC_H_
3
4/*
5 * PowerPC atomic operations
6 */
7
8typedef struct { int counter; } atomic_t;
9
10#ifdef __KERNEL__
11#include <linux/compiler.h>
12#include <asm/synch.h>
13#include <asm/asm-compat.h>
14#include <asm/system.h>
15
16#define ATOMIC_INIT(i) { (i) }
17
18static __inline__ int atomic_read(const atomic_t *v)
19{
20 int t;
21
22 __asm__ __volatile__("lwz%U1%X1 %0,%1" : "=r"(t) : "m"(v->counter));
23
24 return t;
25}
26
27static __inline__ void atomic_set(atomic_t *v, int i)
28{
29 __asm__ __volatile__("stw%U0%X0 %1,%0" : "=m"(v->counter) : "r"(i));
30}
31
32static __inline__ void atomic_add(int a, atomic_t *v)
33{
34 int t;
35
36 __asm__ __volatile__(
37"1: lwarx %0,0,%3 # atomic_add\n\
38 add %0,%2,%0\n"
39 PPC405_ERR77(0,%3)
40" stwcx. %0,0,%3 \n\
41 bne- 1b"
42 : "=&r" (t), "+m" (v->counter)
43 : "r" (a), "r" (&v->counter)
44 : "cc");
45}
46
47static __inline__ int atomic_add_return(int a, atomic_t *v)
48{
49 int t;
50
51 __asm__ __volatile__(
52 LWSYNC_ON_SMP
53"1: lwarx %0,0,%2 # atomic_add_return\n\
54 add %0,%1,%0\n"
55 PPC405_ERR77(0,%2)
56" stwcx. %0,0,%2 \n\
57 bne- 1b"
58 ISYNC_ON_SMP
59 : "=&r" (t)
60 : "r" (a), "r" (&v->counter)
61 : "cc", "memory");
62
63 return t;
64}
65
66#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
67
68static __inline__ void atomic_sub(int a, atomic_t *v)
69{
70 int t;
71
72 __asm__ __volatile__(
73"1: lwarx %0,0,%3 # atomic_sub\n\
74 subf %0,%2,%0\n"
75 PPC405_ERR77(0,%3)
76" stwcx. %0,0,%3 \n\
77 bne- 1b"
78 : "=&r" (t), "+m" (v->counter)
79 : "r" (a), "r" (&v->counter)
80 : "cc");
81}
82
83static __inline__ int atomic_sub_return(int a, atomic_t *v)
84{
85 int t;
86
87 __asm__ __volatile__(
88 LWSYNC_ON_SMP
89"1: lwarx %0,0,%2 # atomic_sub_return\n\
90 subf %0,%1,%0\n"
91 PPC405_ERR77(0,%2)
92" stwcx. %0,0,%2 \n\
93 bne- 1b"
94 ISYNC_ON_SMP
95 : "=&r" (t)
96 : "r" (a), "r" (&v->counter)
97 : "cc", "memory");
98
99 return t;
100}
101
102static __inline__ void atomic_inc(atomic_t *v)
103{
104 int t;
105
106 __asm__ __volatile__(
107"1: lwarx %0,0,%2 # atomic_inc\n\
108 addic %0,%0,1\n"
109 PPC405_ERR77(0,%2)
110" stwcx. %0,0,%2 \n\
111 bne- 1b"
112 : "=&r" (t), "+m" (v->counter)
113 : "r" (&v->counter)
114 : "cc");
115}
116
117static __inline__ int atomic_inc_return(atomic_t *v)
118{
119 int t;
120
121 __asm__ __volatile__(
122 LWSYNC_ON_SMP
123"1: lwarx %0,0,%1 # atomic_inc_return\n\
124 addic %0,%0,1\n"
125 PPC405_ERR77(0,%1)
126" stwcx. %0,0,%1 \n\
127 bne- 1b"
128 ISYNC_ON_SMP
129 : "=&r" (t)
130 : "r" (&v->counter)
131 : "cc", "memory");
132
133 return t;
134}
135
136/*
137 * atomic_inc_and_test - increment and test
138 * @v: pointer of type atomic_t
139 *
140 * Atomically increments @v by 1
141 * and returns true if the result is zero, or false for all
142 * other cases.
143 */
144#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
145
146static __inline__ void atomic_dec(atomic_t *v)
147{
148 int t;
149
150 __asm__ __volatile__(
151"1: lwarx %0,0,%2 # atomic_dec\n\
152 addic %0,%0,-1\n"
153 PPC405_ERR77(0,%2)\
154" stwcx. %0,0,%2\n\
155 bne- 1b"
156 : "=&r" (t), "+m" (v->counter)
157 : "r" (&v->counter)
158 : "cc");
159}
160
161static __inline__ int atomic_dec_return(atomic_t *v)
162{
163 int t;
164
165 __asm__ __volatile__(
166 LWSYNC_ON_SMP
167"1: lwarx %0,0,%1 # atomic_dec_return\n\
168 addic %0,%0,-1\n"
169 PPC405_ERR77(0,%1)
170" stwcx. %0,0,%1\n\
171 bne- 1b"
172 ISYNC_ON_SMP
173 : "=&r" (t)
174 : "r" (&v->counter)
175 : "cc", "memory");
176
177 return t;
178}
179
180#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
181#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
182
183/**
184 * atomic_add_unless - add unless the number is a given value
185 * @v: pointer of type atomic_t
186 * @a: the amount to add to v...
187 * @u: ...unless v is equal to u.
188 *
189 * Atomically adds @a to @v, so long as it was not @u.
190 * Returns non-zero if @v was not @u, and zero otherwise.
191 */
192static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
193{
194 int t;
195
196 __asm__ __volatile__ (
197 LWSYNC_ON_SMP
198"1: lwarx %0,0,%1 # atomic_add_unless\n\
199 cmpw 0,%0,%3 \n\
200 beq- 2f \n\
201 add %0,%2,%0 \n"
202 PPC405_ERR77(0,%2)
203" stwcx. %0,0,%1 \n\
204 bne- 1b \n"
205 ISYNC_ON_SMP
206" subf %0,%2,%0 \n\
2072:"
208 : "=&r" (t)
209 : "r" (&v->counter), "r" (a), "r" (u)
210 : "cc", "memory");
211
212 return t != u;
213}
214
215#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
216
217#define atomic_sub_and_test(a, v) (atomic_sub_return((a), (v)) == 0)
218#define atomic_dec_and_test(v) (atomic_dec_return((v)) == 0)
219
220/*
221 * Atomically test *v and decrement if it is greater than 0.
222 * The function returns the old value of *v minus 1, even if
223 * the atomic variable, v, was not decremented.
224 */
225static __inline__ int atomic_dec_if_positive(atomic_t *v)
226{
227 int t;
228
229 __asm__ __volatile__(
230 LWSYNC_ON_SMP
231"1: lwarx %0,0,%1 # atomic_dec_if_positive\n\
232 cmpwi %0,1\n\
233 addi %0,%0,-1\n\
234 blt- 2f\n"
235 PPC405_ERR77(0,%1)
236" stwcx. %0,0,%1\n\
237 bne- 1b"
238 ISYNC_ON_SMP
239 "\n\
2402:" : "=&b" (t)
241 : "r" (&v->counter)
242 : "cc", "memory");
243
244 return t;
245}
246
247#define smp_mb__before_atomic_dec() smp_mb()
248#define smp_mb__after_atomic_dec() smp_mb()
249#define smp_mb__before_atomic_inc() smp_mb()
250#define smp_mb__after_atomic_inc() smp_mb()
251
252#ifdef __powerpc64__
253
254typedef struct { long counter; } atomic64_t;
255
256#define ATOMIC64_INIT(i) { (i) }
257
258static __inline__ long atomic64_read(const atomic64_t *v)
259{
260 long t;
261
262 __asm__ __volatile__("ld%U1%X1 %0,%1" : "=r"(t) : "m"(v->counter));
263
264 return t;
265}
266
267static __inline__ void atomic64_set(atomic64_t *v, long i)
268{
269 __asm__ __volatile__("std%U0%X0 %1,%0" : "=m"(v->counter) : "r"(i));
270}
271
272static __inline__ void atomic64_add(long a, atomic64_t *v)
273{
274 long t;
275
276 __asm__ __volatile__(
277"1: ldarx %0,0,%3 # atomic64_add\n\
278 add %0,%2,%0\n\
279 stdcx. %0,0,%3 \n\
280 bne- 1b"
281 : "=&r" (t), "+m" (v->counter)
282 : "r" (a), "r" (&v->counter)
283 : "cc");
284}
285
286static __inline__ long atomic64_add_return(long a, atomic64_t *v)
287{
288 long t;
289
290 __asm__ __volatile__(
291 LWSYNC_ON_SMP
292"1: ldarx %0,0,%2 # atomic64_add_return\n\
293 add %0,%1,%0\n\
294 stdcx. %0,0,%2 \n\
295 bne- 1b"
296 ISYNC_ON_SMP
297 : "=&r" (t)
298 : "r" (a), "r" (&v->counter)
299 : "cc", "memory");
300
301 return t;
302}
303
304#define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0)
305
306static __inline__ void atomic64_sub(long a, atomic64_t *v)
307{
308 long t;
309
310 __asm__ __volatile__(
311"1: ldarx %0,0,%3 # atomic64_sub\n\
312 subf %0,%2,%0\n\
313 stdcx. %0,0,%3 \n\
314 bne- 1b"
315 : "=&r" (t), "+m" (v->counter)
316 : "r" (a), "r" (&v->counter)
317 : "cc");
318}
319
320static __inline__ long atomic64_sub_return(long a, atomic64_t *v)
321{
322 long t;
323
324 __asm__ __volatile__(
325 LWSYNC_ON_SMP
326"1: ldarx %0,0,%2 # atomic64_sub_return\n\
327 subf %0,%1,%0\n\
328 stdcx. %0,0,%2 \n\
329 bne- 1b"
330 ISYNC_ON_SMP
331 : "=&r" (t)
332 : "r" (a), "r" (&v->counter)
333 : "cc", "memory");
334
335 return t;
336}
337
338static __inline__ void atomic64_inc(atomic64_t *v)
339{
340 long t;
341
342 __asm__ __volatile__(
343"1: ldarx %0,0,%2 # atomic64_inc\n\
344 addic %0,%0,1\n\
345 stdcx. %0,0,%2 \n\
346 bne- 1b"
347 : "=&r" (t), "+m" (v->counter)
348 : "r" (&v->counter)
349 : "cc");
350}
351
352static __inline__ long atomic64_inc_return(atomic64_t *v)
353{
354 long t;
355
356 __asm__ __volatile__(
357 LWSYNC_ON_SMP
358"1: ldarx %0,0,%1 # atomic64_inc_return\n\
359 addic %0,%0,1\n\
360 stdcx. %0,0,%1 \n\
361 bne- 1b"
362 ISYNC_ON_SMP
363 : "=&r" (t)
364 : "r" (&v->counter)
365 : "cc", "memory");
366
367 return t;
368}
369
370/*
371 * atomic64_inc_and_test - increment and test
372 * @v: pointer of type atomic64_t
373 *
374 * Atomically increments @v by 1
375 * and returns true if the result is zero, or false for all
376 * other cases.
377 */
378#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
379
380static __inline__ void atomic64_dec(atomic64_t *v)
381{
382 long t;
383
384 __asm__ __volatile__(
385"1: ldarx %0,0,%2 # atomic64_dec\n\
386 addic %0,%0,-1\n\
387 stdcx. %0,0,%2\n\
388 bne- 1b"
389 : "=&r" (t), "+m" (v->counter)
390 : "r" (&v->counter)
391 : "cc");
392}
393
394static __inline__ long atomic64_dec_return(atomic64_t *v)
395{
396 long t;
397
398 __asm__ __volatile__(
399 LWSYNC_ON_SMP
400"1: ldarx %0,0,%1 # atomic64_dec_return\n\
401 addic %0,%0,-1\n\
402 stdcx. %0,0,%1\n\
403 bne- 1b"
404 ISYNC_ON_SMP
405 : "=&r" (t)
406 : "r" (&v->counter)
407 : "cc", "memory");
408
409 return t;
410}
411
412#define atomic64_sub_and_test(a, v) (atomic64_sub_return((a), (v)) == 0)
413#define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0)
414
415/*
416 * Atomically test *v and decrement if it is greater than 0.
417 * The function returns the old value of *v minus 1.
418 */
419static __inline__ long atomic64_dec_if_positive(atomic64_t *v)
420{
421 long t;
422
423 __asm__ __volatile__(
424 LWSYNC_ON_SMP
425"1: ldarx %0,0,%1 # atomic64_dec_if_positive\n\
426 addic. %0,%0,-1\n\
427 blt- 2f\n\
428 stdcx. %0,0,%1\n\
429 bne- 1b"
430 ISYNC_ON_SMP
431 "\n\
4322:" : "=&r" (t)
433 : "r" (&v->counter)
434 : "cc", "memory");
435
436 return t;
437}
438
439#define atomic64_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
440#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
441
442/**
443 * atomic64_add_unless - add unless the number is a given value
444 * @v: pointer of type atomic64_t
445 * @a: the amount to add to v...
446 * @u: ...unless v is equal to u.
447 *
448 * Atomically adds @a to @v, so long as it was not @u.
449 * Returns non-zero if @v was not @u, and zero otherwise.
450 */
451static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
452{
453 long t;
454
455 __asm__ __volatile__ (
456 LWSYNC_ON_SMP
457"1: ldarx %0,0,%1 # atomic_add_unless\n\
458 cmpd 0,%0,%3 \n\
459 beq- 2f \n\
460 add %0,%2,%0 \n"
461" stdcx. %0,0,%1 \n\
462 bne- 1b \n"
463 ISYNC_ON_SMP
464" subf %0,%2,%0 \n\
4652:"
466 : "=&r" (t)
467 : "r" (&v->counter), "r" (a), "r" (u)
468 : "cc", "memory");
469
470 return t != u;
471}
472
473#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
474
475#endif /* __powerpc64__ */
476
477#include <asm-generic/atomic.h>
478#endif /* __KERNEL__ */
479#endif /* _ASM_POWERPC_ATOMIC_H_ */
diff --git a/include/asm-powerpc/auxvec.h b/include/asm-powerpc/auxvec.h
deleted file mode 100644
index 19a099b62cd..00000000000
--- a/include/asm-powerpc/auxvec.h
+++ /dev/null
@@ -1,19 +0,0 @@
1#ifndef _ASM_POWERPC_AUXVEC_H
2#define _ASM_POWERPC_AUXVEC_H
3
4/*
5 * We need to put in some extra aux table entries to tell glibc what
6 * the cache block size is, so it can use the dcbz instruction safely.
7 */
8#define AT_DCACHEBSIZE 19
9#define AT_ICACHEBSIZE 20
10#define AT_UCACHEBSIZE 21
11/* A special ignored type value for PPC, for glibc compatibility. */
12#define AT_IGNOREPPC 22
13
14/* The vDSO location. We have to use the same value as x86 for glibc's
15 * sake :-)
16 */
17#define AT_SYSINFO_EHDR 33
18
19#endif
diff --git a/include/asm-powerpc/backlight.h b/include/asm-powerpc/backlight.h
deleted file mode 100644
index 8cf5c37c381..00000000000
--- a/include/asm-powerpc/backlight.h
+++ /dev/null
@@ -1,41 +0,0 @@
1/*
2 * Routines for handling backlight control on PowerBooks
3 *
4 * For now, implementation resides in
5 * arch/powerpc/platforms/powermac/backlight.c
6 *
7 */
8#ifndef __ASM_POWERPC_BACKLIGHT_H
9#define __ASM_POWERPC_BACKLIGHT_H
10#ifdef __KERNEL__
11
12#include <linux/fb.h>
13#include <linux/mutex.h>
14
15/* For locking instructions, see the implementation file */
16extern struct backlight_device *pmac_backlight;
17extern struct mutex pmac_backlight_mutex;
18
19extern int pmac_backlight_curve_lookup(struct fb_info *info, int value);
20
21extern int pmac_has_backlight_type(const char *type);
22
23extern void pmac_backlight_key(int direction);
24static inline void pmac_backlight_key_up(void)
25{
26 pmac_backlight_key(0);
27}
28static inline void pmac_backlight_key_down(void)
29{
30 pmac_backlight_key(1);
31}
32
33extern void pmac_backlight_set_legacy_brightness_pmu(int brightness);
34extern int pmac_backlight_set_legacy_brightness(int brightness);
35extern int pmac_backlight_get_legacy_brightness(void);
36
37extern void pmac_backlight_enable(void);
38extern void pmac_backlight_disable(void);
39
40#endif /* __KERNEL__ */
41#endif
diff --git a/include/asm-powerpc/bitops.h b/include/asm-powerpc/bitops.h
deleted file mode 100644
index 897eade3afb..00000000000
--- a/include/asm-powerpc/bitops.h
+++ /dev/null
@@ -1,410 +0,0 @@
1/*
2 * PowerPC atomic bit operations.
3 *
4 * Merged version by David Gibson <david@gibson.dropbear.id.au>.
5 * Based on ppc64 versions by: Dave Engebretsen, Todd Inglett, Don
6 * Reed, Pat McCarthy, Peter Bergner, Anton Blanchard. They
7 * originally took it from the ppc32 code.
8 *
9 * Within a word, bits are numbered LSB first. Lot's of places make
10 * this assumption by directly testing bits with (val & (1<<nr)).
11 * This can cause confusion for large (> 1 word) bitmaps on a
12 * big-endian system because, unlike little endian, the number of each
13 * bit depends on the word size.
14 *
15 * The bitop functions are defined to work on unsigned longs, so for a
16 * ppc64 system the bits end up numbered:
17 * |63..............0|127............64|191...........128|255...........196|
18 * and on ppc32:
19 * |31.....0|63....31|95....64|127...96|159..128|191..160|223..192|255..224|
20 *
21 * There are a few little-endian macros used mostly for filesystem
22 * bitmaps, these work on similar bit arrays layouts, but
23 * byte-oriented:
24 * |7...0|15...8|23...16|31...24|39...32|47...40|55...48|63...56|
25 *
26 * The main difference is that bit 3-5 (64b) or 3-4 (32b) in the bit
27 * number field needs to be reversed compared to the big-endian bit
28 * fields. This can be achieved by XOR with 0x38 (64b) or 0x18 (32b).
29 *
30 * This program is free software; you can redistribute it and/or
31 * modify it under the terms of the GNU General Public License
32 * as published by the Free Software Foundation; either version
33 * 2 of the License, or (at your option) any later version.
34 */
35
36#ifndef _ASM_POWERPC_BITOPS_H
37#define _ASM_POWERPC_BITOPS_H
38
39#ifdef __KERNEL__
40
41#ifndef _LINUX_BITOPS_H
42#error only <linux/bitops.h> can be included directly
43#endif
44
45#include <linux/compiler.h>
46#include <asm/asm-compat.h>
47#include <asm/synch.h>
48
49/*
50 * clear_bit doesn't imply a memory barrier
51 */
52#define smp_mb__before_clear_bit() smp_mb()
53#define smp_mb__after_clear_bit() smp_mb()
54
55#define BITOP_MASK(nr) (1UL << ((nr) % BITS_PER_LONG))
56#define BITOP_WORD(nr) ((nr) / BITS_PER_LONG)
57#define BITOP_LE_SWIZZLE ((BITS_PER_LONG-1) & ~0x7)
58
59static __inline__ void set_bit(int nr, volatile unsigned long *addr)
60{
61 unsigned long old;
62 unsigned long mask = BITOP_MASK(nr);
63 unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
64
65 __asm__ __volatile__(
66"1:" PPC_LLARX "%0,0,%3 # set_bit\n"
67 "or %0,%0,%2\n"
68 PPC405_ERR77(0,%3)
69 PPC_STLCX "%0,0,%3\n"
70 "bne- 1b"
71 : "=&r" (old), "+m" (*p)
72 : "r" (mask), "r" (p)
73 : "cc" );
74}
75
76static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
77{
78 unsigned long old;
79 unsigned long mask = BITOP_MASK(nr);
80 unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
81
82 __asm__ __volatile__(
83"1:" PPC_LLARX "%0,0,%3 # clear_bit\n"
84 "andc %0,%0,%2\n"
85 PPC405_ERR77(0,%3)
86 PPC_STLCX "%0,0,%3\n"
87 "bne- 1b"
88 : "=&r" (old), "+m" (*p)
89 : "r" (mask), "r" (p)
90 : "cc" );
91}
92
93static __inline__ void clear_bit_unlock(int nr, volatile unsigned long *addr)
94{
95 unsigned long old;
96 unsigned long mask = BITOP_MASK(nr);
97 unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
98
99 __asm__ __volatile__(
100 LWSYNC_ON_SMP
101"1:" PPC_LLARX "%0,0,%3 # clear_bit_unlock\n"
102 "andc %0,%0,%2\n"
103 PPC405_ERR77(0,%3)
104 PPC_STLCX "%0,0,%3\n"
105 "bne- 1b"
106 : "=&r" (old), "+m" (*p)
107 : "r" (mask), "r" (p)
108 : "cc", "memory");
109}
110
111static __inline__ void change_bit(int nr, volatile unsigned long *addr)
112{
113 unsigned long old;
114 unsigned long mask = BITOP_MASK(nr);
115 unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
116
117 __asm__ __volatile__(
118"1:" PPC_LLARX "%0,0,%3 # change_bit\n"
119 "xor %0,%0,%2\n"
120 PPC405_ERR77(0,%3)
121 PPC_STLCX "%0,0,%3\n"
122 "bne- 1b"
123 : "=&r" (old), "+m" (*p)
124 : "r" (mask), "r" (p)
125 : "cc" );
126}
127
128static __inline__ int test_and_set_bit(unsigned long nr,
129 volatile unsigned long *addr)
130{
131 unsigned long old, t;
132 unsigned long mask = BITOP_MASK(nr);
133 unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
134
135 __asm__ __volatile__(
136 LWSYNC_ON_SMP
137"1:" PPC_LLARX "%0,0,%3 # test_and_set_bit\n"
138 "or %1,%0,%2 \n"
139 PPC405_ERR77(0,%3)
140 PPC_STLCX "%1,0,%3 \n"
141 "bne- 1b"
142 ISYNC_ON_SMP
143 : "=&r" (old), "=&r" (t)
144 : "r" (mask), "r" (p)
145 : "cc", "memory");
146
147 return (old & mask) != 0;
148}
149
150static __inline__ int test_and_set_bit_lock(unsigned long nr,
151 volatile unsigned long *addr)
152{
153 unsigned long old, t;
154 unsigned long mask = BITOP_MASK(nr);
155 unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
156
157 __asm__ __volatile__(
158"1:" PPC_LLARX "%0,0,%3 # test_and_set_bit_lock\n"
159 "or %1,%0,%2 \n"
160 PPC405_ERR77(0,%3)
161 PPC_STLCX "%1,0,%3 \n"
162 "bne- 1b"
163 ISYNC_ON_SMP
164 : "=&r" (old), "=&r" (t)
165 : "r" (mask), "r" (p)
166 : "cc", "memory");
167
168 return (old & mask) != 0;
169}
170
171static __inline__ int test_and_clear_bit(unsigned long nr,
172 volatile unsigned long *addr)
173{
174 unsigned long old, t;
175 unsigned long mask = BITOP_MASK(nr);
176 unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
177
178 __asm__ __volatile__(
179 LWSYNC_ON_SMP
180"1:" PPC_LLARX "%0,0,%3 # test_and_clear_bit\n"
181 "andc %1,%0,%2 \n"
182 PPC405_ERR77(0,%3)
183 PPC_STLCX "%1,0,%3 \n"
184 "bne- 1b"
185 ISYNC_ON_SMP
186 : "=&r" (old), "=&r" (t)
187 : "r" (mask), "r" (p)
188 : "cc", "memory");
189
190 return (old & mask) != 0;
191}
192
193static __inline__ int test_and_change_bit(unsigned long nr,
194 volatile unsigned long *addr)
195{
196 unsigned long old, t;
197 unsigned long mask = BITOP_MASK(nr);
198 unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
199
200 __asm__ __volatile__(
201 LWSYNC_ON_SMP
202"1:" PPC_LLARX "%0,0,%3 # test_and_change_bit\n"
203 "xor %1,%0,%2 \n"
204 PPC405_ERR77(0,%3)
205 PPC_STLCX "%1,0,%3 \n"
206 "bne- 1b"
207 ISYNC_ON_SMP
208 : "=&r" (old), "=&r" (t)
209 : "r" (mask), "r" (p)
210 : "cc", "memory");
211
212 return (old & mask) != 0;
213}
214
215static __inline__ void set_bits(unsigned long mask, unsigned long *addr)
216{
217 unsigned long old;
218
219 __asm__ __volatile__(
220"1:" PPC_LLARX "%0,0,%3 # set_bits\n"
221 "or %0,%0,%2\n"
222 PPC_STLCX "%0,0,%3\n"
223 "bne- 1b"
224 : "=&r" (old), "+m" (*addr)
225 : "r" (mask), "r" (addr)
226 : "cc");
227}
228
229#include <asm-generic/bitops/non-atomic.h>
230
231static __inline__ void __clear_bit_unlock(int nr, volatile unsigned long *addr)
232{
233 __asm__ __volatile__(LWSYNC_ON_SMP "" ::: "memory");
234 __clear_bit(nr, addr);
235}
236
237/*
238 * Return the zero-based bit position (LE, not IBM bit numbering) of
239 * the most significant 1-bit in a double word.
240 */
241static __inline__ __attribute__((const))
242int __ilog2(unsigned long x)
243{
244 int lz;
245
246 asm (PPC_CNTLZL "%0,%1" : "=r" (lz) : "r" (x));
247 return BITS_PER_LONG - 1 - lz;
248}
249
250static inline __attribute__((const))
251int __ilog2_u32(u32 n)
252{
253 int bit;
254 asm ("cntlzw %0,%1" : "=r" (bit) : "r" (n));
255 return 31 - bit;
256}
257
258#ifdef __powerpc64__
259static inline __attribute__((const))
260int __ilog2_u64(u64 n)
261{
262 int bit;
263 asm ("cntlzd %0,%1" : "=r" (bit) : "r" (n));
264 return 63 - bit;
265}
266#endif
267
268/*
269 * Determines the bit position of the least significant 0 bit in the
270 * specified double word. The returned bit position will be
271 * zero-based, starting from the right side (63/31 - 0).
272 */
273static __inline__ unsigned long ffz(unsigned long x)
274{
275 /* no zero exists anywhere in the 8 byte area. */
276 if ((x = ~x) == 0)
277 return BITS_PER_LONG;
278
279 /*
280 * Calculate the bit position of the least signficant '1' bit in x
281 * (since x has been changed this will actually be the least signficant
282 * '0' bit in * the original x). Note: (x & -x) gives us a mask that
283 * is the least significant * (RIGHT-most) 1-bit of the value in x.
284 */
285 return __ilog2(x & -x);
286}
287
288static __inline__ int __ffs(unsigned long x)
289{
290 return __ilog2(x & -x);
291}
292
293/*
294 * ffs: find first bit set. This is defined the same way as
295 * the libc and compiler builtin ffs routines, therefore
296 * differs in spirit from the above ffz (man ffs).
297 */
298static __inline__ int ffs(int x)
299{
300 unsigned long i = (unsigned long)x;
301 return __ilog2(i & -i) + 1;
302}
303
304/*
305 * fls: find last (most-significant) bit set.
306 * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
307 */
308static __inline__ int fls(unsigned int x)
309{
310 int lz;
311
312 asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x));
313 return 32 - lz;
314}
315
316static __inline__ unsigned long __fls(unsigned long x)
317{
318 return __ilog2(x);
319}
320
321/*
322 * 64-bit can do this using one cntlzd (count leading zeroes doubleword)
323 * instruction; for 32-bit we use the generic version, which does two
324 * 32-bit fls calls.
325 */
326#ifdef __powerpc64__
327static __inline__ int fls64(__u64 x)
328{
329 int lz;
330
331 asm ("cntlzd %0,%1" : "=r" (lz) : "r" (x));
332 return 64 - lz;
333}
334#else
335#include <asm-generic/bitops/fls64.h>
336#endif /* __powerpc64__ */
337
338#include <asm-generic/bitops/hweight.h>
339#include <asm-generic/bitops/find.h>
340
341/* Little-endian versions */
342
343static __inline__ int test_le_bit(unsigned long nr,
344 __const__ unsigned long *addr)
345{
346 __const__ unsigned char *tmp = (__const__ unsigned char *) addr;
347 return (tmp[nr >> 3] >> (nr & 7)) & 1;
348}
349
350#define __set_le_bit(nr, addr) \
351 __set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
352#define __clear_le_bit(nr, addr) \
353 __clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
354
355#define test_and_set_le_bit(nr, addr) \
356 test_and_set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
357#define test_and_clear_le_bit(nr, addr) \
358 test_and_clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
359
360#define __test_and_set_le_bit(nr, addr) \
361 __test_and_set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
362#define __test_and_clear_le_bit(nr, addr) \
363 __test_and_clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
364
365#define find_first_zero_le_bit(addr, size) generic_find_next_zero_le_bit((addr), (size), 0)
366unsigned long generic_find_next_zero_le_bit(const unsigned long *addr,
367 unsigned long size, unsigned long offset);
368
369unsigned long generic_find_next_le_bit(const unsigned long *addr,
370 unsigned long size, unsigned long offset);
371/* Bitmap functions for the ext2 filesystem */
372
373#define ext2_set_bit(nr,addr) \
374 __test_and_set_le_bit((nr), (unsigned long*)addr)
375#define ext2_clear_bit(nr, addr) \
376 __test_and_clear_le_bit((nr), (unsigned long*)addr)
377
378#define ext2_set_bit_atomic(lock, nr, addr) \
379 test_and_set_le_bit((nr), (unsigned long*)addr)
380#define ext2_clear_bit_atomic(lock, nr, addr) \
381 test_and_clear_le_bit((nr), (unsigned long*)addr)
382
383#define ext2_test_bit(nr, addr) test_le_bit((nr),(unsigned long*)addr)
384
385#define ext2_find_first_zero_bit(addr, size) \
386 find_first_zero_le_bit((unsigned long*)addr, size)
387#define ext2_find_next_zero_bit(addr, size, off) \
388 generic_find_next_zero_le_bit((unsigned long*)addr, size, off)
389
390#define ext2_find_next_bit(addr, size, off) \
391 generic_find_next_le_bit((unsigned long *)addr, size, off)
392/* Bitmap functions for the minix filesystem. */
393
394#define minix_test_and_set_bit(nr,addr) \
395 __test_and_set_le_bit(nr, (unsigned long *)addr)
396#define minix_set_bit(nr,addr) \
397 __set_le_bit(nr, (unsigned long *)addr)
398#define minix_test_and_clear_bit(nr,addr) \
399 __test_and_clear_le_bit(nr, (unsigned long *)addr)
400#define minix_test_bit(nr,addr) \
401 test_le_bit(nr, (unsigned long *)addr)
402
403#define minix_find_first_zero_bit(addr,size) \
404 find_first_zero_le_bit((unsigned long *)addr, size)
405
406#include <asm-generic/bitops/sched.h>
407
408#endif /* __KERNEL__ */
409
410#endif /* _ASM_POWERPC_BITOPS_H */
diff --git a/include/asm-powerpc/bootx.h b/include/asm-powerpc/bootx.h
deleted file mode 100644
index 57b82e3f89c..00000000000
--- a/include/asm-powerpc/bootx.h
+++ /dev/null
@@ -1,171 +0,0 @@
1/*
2 * This file describes the structure passed from the BootX application
3 * (for MacOS) when it is used to boot Linux.
4 *
5 * Written by Benjamin Herrenschmidt.
6 */
7
8
9#ifndef __ASM_BOOTX_H__
10#define __ASM_BOOTX_H__
11
12#include <asm/types.h>
13
14#ifdef macintosh
15#include <Types.h>
16#include "linux_type_defs.h"
17#endif
18
19#ifdef macintosh
20/* All this requires PowerPC alignment */
21#pragma options align=power
22#endif
23
24/* On kernel entry:
25 *
26 * r3 = 0x426f6f58 ('BooX')
27 * r4 = pointer to boot_infos
28 * r5 = NULL
29 *
30 * Data and instruction translation disabled, interrupts
31 * disabled, kernel loaded at physical 0x00000000 on PCI
32 * machines (will be different on NuBus).
33 */
34
35#define BOOT_INFO_VERSION 5
36#define BOOT_INFO_COMPATIBLE_VERSION 1
37
38/* Bit in the architecture flag mask. More to be defined in
39 future versions. Note that either BOOT_ARCH_PCI or
40 BOOT_ARCH_NUBUS is set. The other BOOT_ARCH_NUBUS_xxx are
41 set additionally when BOOT_ARCH_NUBUS is set.
42 */
43#define BOOT_ARCH_PCI 0x00000001UL
44#define BOOT_ARCH_NUBUS 0x00000002UL
45#define BOOT_ARCH_NUBUS_PDM 0x00000010UL
46#define BOOT_ARCH_NUBUS_PERFORMA 0x00000020UL
47#define BOOT_ARCH_NUBUS_POWERBOOK 0x00000040UL
48
49/* Maximum number of ranges in phys memory map */
50#define MAX_MEM_MAP_SIZE 26
51
52/* This is the format of an element in the physical memory map. Note that
53 the map is optional and current BootX will only build it for pre-PCI
54 machines */
55typedef struct boot_info_map_entry
56{
57 __u32 physAddr; /* Physical starting address */
58 __u32 size; /* Size in bytes */
59} boot_info_map_entry_t;
60
61
62/* Here are the boot informations that are passed to the bootstrap
63 * Note that the kernel arguments and the device tree are appended
64 * at the end of this structure. */
65typedef struct boot_infos
66{
67 /* Version of this structure */
68 __u32 version;
69 /* backward compatible down to version: */
70 __u32 compatible_version;
71
72 /* NEW (vers. 2) this holds the current _logical_ base addr of
73 the frame buffer (for use by early boot message) */
74 __u8* logicalDisplayBase;
75
76 /* NEW (vers. 4) Apple's machine identification */
77 __u32 machineID;
78
79 /* NEW (vers. 4) Detected hw architecture */
80 __u32 architecture;
81
82 /* The device tree (internal addresses relative to the beginning of the tree,
83 * device tree offset relative to the beginning of this structure).
84 * On pre-PCI macintosh (BOOT_ARCH_PCI bit set to 0 in architecture), this
85 * field is 0.
86 */
87 __u32 deviceTreeOffset; /* Device tree offset */
88 __u32 deviceTreeSize; /* Size of the device tree */
89
90 /* Some infos about the current MacOS display */
91 __u32 dispDeviceRect[4]; /* left,top,right,bottom */
92 __u32 dispDeviceDepth; /* (8, 16 or 32) */
93 __u8* dispDeviceBase; /* base address (physical) */
94 __u32 dispDeviceRowBytes; /* rowbytes (in bytes) */
95 __u32 dispDeviceColorsOffset; /* Colormap (8 bits only) or 0 (*) */
96 /* Optional offset in the registry to the current
97 * MacOS display. (Can be 0 when not detected) */
98 __u32 dispDeviceRegEntryOffset;
99
100 /* Optional pointer to boot ramdisk (offset from this structure) */
101 __u32 ramDisk;
102 __u32 ramDiskSize; /* size of ramdisk image */
103
104 /* Kernel command line arguments (offset from this structure) */
105 __u32 kernelParamsOffset;
106
107 /* ALL BELOW NEW (vers. 4) */
108
109 /* This defines the physical memory. Valid with BOOT_ARCH_NUBUS flag
110 (non-PCI) only. On PCI, memory is contiguous and it's size is in the
111 device-tree. */
112 boot_info_map_entry_t
113 physMemoryMap[MAX_MEM_MAP_SIZE]; /* Where the phys memory is */
114 __u32 physMemoryMapSize; /* How many entries in map */
115
116
117 /* The framebuffer size (optional, currently 0) */
118 __u32 frameBufferSize; /* Represents a max size, can be 0. */
119
120 /* NEW (vers. 5) */
121
122 /* Total params size (args + colormap + device tree + ramdisk) */
123 __u32 totalParamsSize;
124
125} boot_infos_t;
126
127#ifdef __KERNEL__
128/* (*) The format of the colormap is 256 * 3 * 2 bytes. Each color index
129 * is represented by 3 short words containing a 16 bits (unsigned) color
130 * component. Later versions may contain the gamma table for direct-color
131 * devices here.
132 */
133#define BOOTX_COLORTABLE_SIZE (256UL*3UL*2UL)
134
135/* BootX passes the device-tree using a format that comes from earlier
136 * ppc32 kernels. This used to match what is in prom.h, but not anymore
137 * so we now define it here
138 */
139struct bootx_dt_prop {
140 u32 name;
141 int length;
142 u32 value;
143 u32 next;
144};
145
146struct bootx_dt_node {
147 u32 unused0;
148 u32 unused1;
149 u32 phandle; /* not really available */
150 u32 unused2;
151 u32 unused3;
152 u32 unused4;
153 u32 unused5;
154 u32 full_name;
155 u32 properties;
156 u32 parent;
157 u32 child;
158 u32 sibling;
159 u32 next;
160 u32 allnext;
161};
162
163extern void bootx_init(unsigned long r4, unsigned long phys);
164
165#endif /* __KERNEL__ */
166
167#ifdef macintosh
168#pragma options align=reset
169#endif
170
171#endif
diff --git a/include/asm-powerpc/btext.h b/include/asm-powerpc/btext.h
deleted file mode 100644
index 906f46e3100..00000000000
--- a/include/asm-powerpc/btext.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * Definitions for using the procedures in btext.c.
3 *
4 * Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 */
6#ifndef __PPC_BTEXT_H
7#define __PPC_BTEXT_H
8#ifdef __KERNEL__
9
10extern int btext_find_display(int allow_nonstdout);
11extern void btext_update_display(unsigned long phys, int width, int height,
12 int depth, int pitch);
13extern void btext_setup_display(int width, int height, int depth, int pitch,
14 unsigned long address);
15extern void btext_prepare_BAT(void);
16extern void btext_unmap(void);
17
18extern void btext_drawchar(char c);
19extern void btext_drawstring(const char *str);
20extern void btext_drawhex(unsigned long v);
21extern void btext_drawtext(const char *c, unsigned int len);
22
23extern void btext_clearscreen(void);
24extern void btext_flushscreen(void);
25extern void btext_flushline(void);
26
27#endif /* __KERNEL__ */
28#endif /* __PPC_BTEXT_H */
diff --git a/include/asm-powerpc/bug.h b/include/asm-powerpc/bug.h
deleted file mode 100644
index e55d1f66b86..00000000000
--- a/include/asm-powerpc/bug.h
+++ /dev/null
@@ -1,121 +0,0 @@
1#ifndef _ASM_POWERPC_BUG_H
2#define _ASM_POWERPC_BUG_H
3#ifdef __KERNEL__
4
5#include <asm/asm-compat.h>
6/*
7 * Define an illegal instr to trap on the bug.
8 * We don't use 0 because that marks the end of a function
9 * in the ELF ABI. That's "Boo Boo" in case you wonder...
10 */
11#define BUG_OPCODE .long 0x00b00b00 /* For asm */
12#define BUG_ILLEGAL_INSTR "0x00b00b00" /* For BUG macro */
13
14#ifdef CONFIG_BUG
15
16#ifdef __ASSEMBLY__
17#ifdef CONFIG_DEBUG_BUGVERBOSE
18.macro EMIT_BUG_ENTRY addr,file,line,flags
19 .section __bug_table,"a"
205001: PPC_LONG \addr, 5002f
21 .short \line, \flags
22 .org 5001b+BUG_ENTRY_SIZE
23 .previous
24 .section .rodata,"a"
255002: .asciz "\file"
26 .previous
27.endm
28#else
29 .macro EMIT_BUG_ENTRY addr,file,line,flags
30 .section __bug_table,"a"
315001: PPC_LONG \addr
32 .short \flags
33 .org 5001b+BUG_ENTRY_SIZE
34 .previous
35.endm
36#endif /* verbose */
37
38#else /* !__ASSEMBLY__ */
39/* _EMIT_BUG_ENTRY expects args %0,%1,%2,%3 to be FILE, LINE, flags and
40 sizeof(struct bug_entry), respectively */
41#ifdef CONFIG_DEBUG_BUGVERBOSE
42#define _EMIT_BUG_ENTRY \
43 ".section __bug_table,\"a\"\n" \
44 "2:\t" PPC_LONG "1b, %0\n" \
45 "\t.short %1, %2\n" \
46 ".org 2b+%3\n" \
47 ".previous\n"
48#else
49#define _EMIT_BUG_ENTRY \
50 ".section __bug_table,\"a\"\n" \
51 "2:\t" PPC_LONG "1b\n" \
52 "\t.short %2\n" \
53 ".org 2b+%3\n" \
54 ".previous\n"
55#endif
56
57/*
58 * BUG_ON() and WARN_ON() do their best to cooperate with compile-time
59 * optimisations. However depending on the complexity of the condition
60 * some compiler versions may not produce optimal results.
61 */
62
63#define BUG() do { \
64 __asm__ __volatile__( \
65 "1: twi 31,0,0\n" \
66 _EMIT_BUG_ENTRY \
67 : : "i" (__FILE__), "i" (__LINE__), \
68 "i" (0), "i" (sizeof(struct bug_entry))); \
69 for(;;) ; \
70} while (0)
71
72#define BUG_ON(x) do { \
73 if (__builtin_constant_p(x)) { \
74 if (x) \
75 BUG(); \
76 } else { \
77 __asm__ __volatile__( \
78 "1: "PPC_TLNEI" %4,0\n" \
79 _EMIT_BUG_ENTRY \
80 : : "i" (__FILE__), "i" (__LINE__), "i" (0), \
81 "i" (sizeof(struct bug_entry)), \
82 "r" ((__force long)(x))); \
83 } \
84} while (0)
85
86#define __WARN() do { \
87 __asm__ __volatile__( \
88 "1: twi 31,0,0\n" \
89 _EMIT_BUG_ENTRY \
90 : : "i" (__FILE__), "i" (__LINE__), \
91 "i" (BUGFLAG_WARNING), \
92 "i" (sizeof(struct bug_entry))); \
93} while (0)
94
95#define WARN_ON(x) ({ \
96 int __ret_warn_on = !!(x); \
97 if (__builtin_constant_p(__ret_warn_on)) { \
98 if (__ret_warn_on) \
99 __WARN(); \
100 } else { \
101 __asm__ __volatile__( \
102 "1: "PPC_TLNEI" %4,0\n" \
103 _EMIT_BUG_ENTRY \
104 : : "i" (__FILE__), "i" (__LINE__), \
105 "i" (BUGFLAG_WARNING), \
106 "i" (sizeof(struct bug_entry)), \
107 "r" (__ret_warn_on)); \
108 } \
109 unlikely(__ret_warn_on); \
110})
111
112#define HAVE_ARCH_BUG
113#define HAVE_ARCH_BUG_ON
114#define HAVE_ARCH_WARN_ON
115#endif /* __ASSEMBLY __ */
116#endif /* CONFIG_BUG */
117
118#include <asm-generic/bug.h>
119
120#endif /* __KERNEL__ */
121#endif /* _ASM_POWERPC_BUG_H */
diff --git a/include/asm-powerpc/bugs.h b/include/asm-powerpc/bugs.h
deleted file mode 100644
index 42fdb73e306..00000000000
--- a/include/asm-powerpc/bugs.h
+++ /dev/null
@@ -1,18 +0,0 @@
1#ifndef _ASM_POWERPC_BUGS_H
2#define _ASM_POWERPC_BUGS_H
3
4/*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10
11/*
12 * This file is included by 'init/main.c' to check for
13 * architecture-dependent bugs.
14 */
15
16static inline void check_bugs(void) { }
17
18#endif /* _ASM_POWERPC_BUGS_H */
diff --git a/include/asm-powerpc/byteorder.h b/include/asm-powerpc/byteorder.h
deleted file mode 100644
index b37752214a1..00000000000
--- a/include/asm-powerpc/byteorder.h
+++ /dev/null
@@ -1,89 +0,0 @@
1#ifndef _ASM_POWERPC_BYTEORDER_H
2#define _ASM_POWERPC_BYTEORDER_H
3
4/*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10
11#include <asm/types.h>
12#include <linux/compiler.h>
13
14#ifdef __GNUC__
15#ifdef __KERNEL__
16
17static __inline__ __u16 ld_le16(const volatile __u16 *addr)
18{
19 __u16 val;
20
21 __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
22 return val;
23}
24
25static __inline__ void st_le16(volatile __u16 *addr, const __u16 val)
26{
27 __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
28}
29
30static __inline__ __u32 ld_le32(const volatile __u32 *addr)
31{
32 __u32 val;
33
34 __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
35 return val;
36}
37
38static __inline__ void st_le32(volatile __u32 *addr, const __u32 val)
39{
40 __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
41}
42
43static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 value)
44{
45 __u16 result;
46
47 __asm__("rlwimi %0,%1,8,16,23"
48 : "=r" (result)
49 : "r" (value), "0" (value >> 8));
50 return result;
51}
52
53static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 value)
54{
55 __u32 result;
56
57 __asm__("rlwimi %0,%1,24,16,23\n\t"
58 "rlwimi %0,%1,8,8,15\n\t"
59 "rlwimi %0,%1,24,0,7"
60 : "=r" (result)
61 : "r" (value), "0" (value >> 24));
62 return result;
63}
64
65#define __arch__swab16(x) ___arch__swab16(x)
66#define __arch__swab32(x) ___arch__swab32(x)
67
68/* The same, but returns converted value from the location pointer by addr. */
69#define __arch__swab16p(addr) ld_le16(addr)
70#define __arch__swab32p(addr) ld_le32(addr)
71
72/* The same, but do the conversion in situ, ie. put the value back to addr. */
73#define __arch__swab16s(addr) st_le16(addr,*addr)
74#define __arch__swab32s(addr) st_le32(addr,*addr)
75
76#endif /* __KERNEL__ */
77
78#ifndef __STRICT_ANSI__
79#define __BYTEORDER_HAS_U64__
80#ifndef __powerpc64__
81#define __SWAB_64_THRU_32__
82#endif /* __powerpc64__ */
83#endif /* __STRICT_ANSI__ */
84
85#endif /* __GNUC__ */
86
87#include <linux/byteorder/big_endian.h>
88
89#endif /* _ASM_POWERPC_BYTEORDER_H */
diff --git a/include/asm-powerpc/cache.h b/include/asm-powerpc/cache.h
deleted file mode 100644
index 81de6eb3455..00000000000
--- a/include/asm-powerpc/cache.h
+++ /dev/null
@@ -1,45 +0,0 @@
1#ifndef _ASM_POWERPC_CACHE_H
2#define _ASM_POWERPC_CACHE_H
3
4#ifdef __KERNEL__
5
6
7/* bytes per L1 cache line */
8#if defined(CONFIG_8xx) || defined(CONFIG_403GCX)
9#define L1_CACHE_SHIFT 4
10#define MAX_COPY_PREFETCH 1
11#elif defined(CONFIG_PPC_E500MC)
12#define L1_CACHE_SHIFT 6
13#define MAX_COPY_PREFETCH 4
14#elif defined(CONFIG_PPC32)
15#define L1_CACHE_SHIFT 5
16#define MAX_COPY_PREFETCH 4
17#else /* CONFIG_PPC64 */
18#define L1_CACHE_SHIFT 7
19#endif
20
21#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
22
23#define SMP_CACHE_BYTES L1_CACHE_BYTES
24
25#if defined(__powerpc64__) && !defined(__ASSEMBLY__)
26struct ppc64_caches {
27 u32 dsize; /* L1 d-cache size */
28 u32 dline_size; /* L1 d-cache line size */
29 u32 log_dline_size;
30 u32 dlines_per_page;
31 u32 isize; /* L1 i-cache size */
32 u32 iline_size; /* L1 i-cache line size */
33 u32 log_iline_size;
34 u32 ilines_per_page;
35};
36
37extern struct ppc64_caches ppc64_caches;
38#endif /* __powerpc64__ && ! __ASSEMBLY__ */
39
40#if !defined(__ASSEMBLY__)
41#define __read_mostly __attribute__((__section__(".data.read_mostly")))
42#endif
43
44#endif /* __KERNEL__ */
45#endif /* _ASM_POWERPC_CACHE_H */
diff --git a/include/asm-powerpc/cacheflush.h b/include/asm-powerpc/cacheflush.h
deleted file mode 100644
index ba667a383b8..00000000000
--- a/include/asm-powerpc/cacheflush.h
+++ /dev/null
@@ -1,75 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version
5 * 2 of the License, or (at your option) any later version.
6 */
7#ifndef _ASM_POWERPC_CACHEFLUSH_H
8#define _ASM_POWERPC_CACHEFLUSH_H
9
10#ifdef __KERNEL__
11
12#include <linux/mm.h>
13#include <asm/cputable.h>
14
15/*
16 * No cache flushing is required when address mappings are changed,
17 * because the caches on PowerPCs are physically addressed.
18 */
19#define flush_cache_all() do { } while (0)
20#define flush_cache_mm(mm) do { } while (0)
21#define flush_cache_dup_mm(mm) do { } while (0)
22#define flush_cache_range(vma, start, end) do { } while (0)
23#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
24#define flush_icache_page(vma, page) do { } while (0)
25#define flush_cache_vmap(start, end) do { } while (0)
26#define flush_cache_vunmap(start, end) do { } while (0)
27
28extern void flush_dcache_page(struct page *page);
29#define flush_dcache_mmap_lock(mapping) do { } while (0)
30#define flush_dcache_mmap_unlock(mapping) do { } while (0)
31
32extern void __flush_icache_range(unsigned long, unsigned long);
33static inline void flush_icache_range(unsigned long start, unsigned long stop)
34{
35 if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
36 __flush_icache_range(start, stop);
37}
38
39extern void flush_icache_user_range(struct vm_area_struct *vma,
40 struct page *page, unsigned long addr,
41 int len);
42extern void __flush_dcache_icache(void *page_va);
43extern void flush_dcache_icache_page(struct page *page);
44#if defined(CONFIG_PPC32) && !defined(CONFIG_BOOKE)
45extern void __flush_dcache_icache_phys(unsigned long physaddr);
46#endif /* CONFIG_PPC32 && !CONFIG_BOOKE */
47
48extern void flush_dcache_range(unsigned long start, unsigned long stop);
49#ifdef CONFIG_PPC32
50extern void clean_dcache_range(unsigned long start, unsigned long stop);
51extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
52#endif /* CONFIG_PPC32 */
53#ifdef CONFIG_PPC64
54extern void flush_inval_dcache_range(unsigned long start, unsigned long stop);
55extern void flush_dcache_phys_range(unsigned long start, unsigned long stop);
56#endif
57
58#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
59 do { \
60 memcpy(dst, src, len); \
61 flush_icache_user_range(vma, page, vaddr, len); \
62 } while (0)
63#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
64 memcpy(dst, src, len)
65
66
67
68#ifdef CONFIG_DEBUG_PAGEALLOC
69/* internal debugging function */
70void kernel_map_pages(struct page *page, int numpages, int enable);
71#endif
72
73#endif /* __KERNEL__ */
74
75#endif /* _ASM_POWERPC_CACHEFLUSH_H */
diff --git a/include/asm-powerpc/cell-pmu.h b/include/asm-powerpc/cell-pmu.h
deleted file mode 100644
index 8066eede3a0..00000000000
--- a/include/asm-powerpc/cell-pmu.h
+++ /dev/null
@@ -1,105 +0,0 @@
1/*
2 * Cell Broadband Engine Performance Monitor
3 *
4 * (C) Copyright IBM Corporation 2006
5 *
6 * Author:
7 * David Erb (djerb@us.ibm.com)
8 * Kevin Corry (kevcorry@us.ibm.com)
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
13 * any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25#ifndef __ASM_CELL_PMU_H__
26#define __ASM_CELL_PMU_H__
27
28/* The Cell PMU has four hardware performance counters, which can be
29 * configured as four 32-bit counters or eight 16-bit counters.
30 */
31#define NR_PHYS_CTRS 4
32#define NR_CTRS (NR_PHYS_CTRS * 2)
33
34/* Macros for the pm_control register. */
35#define CBE_PM_16BIT_CTR(ctr) (1 << (24 - ((ctr) & (NR_PHYS_CTRS - 1))))
36#define CBE_PM_ENABLE_PERF_MON 0x80000000
37#define CBE_PM_STOP_AT_MAX 0x40000000
38#define CBE_PM_TRACE_MODE_GET(pm_control) (((pm_control) >> 28) & 0x3)
39#define CBE_PM_TRACE_MODE_SET(mode) (((mode) & 0x3) << 28)
40#define CBE_PM_COUNT_MODE_SET(count) (((count) & 0x3) << 18)
41#define CBE_PM_FREEZE_ALL_CTRS 0x00100000
42#define CBE_PM_ENABLE_EXT_TRACE 0x00008000
43
44/* Macros for the trace_address register. */
45#define CBE_PM_TRACE_BUF_FULL 0x00000800
46#define CBE_PM_TRACE_BUF_EMPTY 0x00000400
47#define CBE_PM_TRACE_BUF_DATA_COUNT(ta) ((ta) & 0x3ff)
48#define CBE_PM_TRACE_BUF_MAX_COUNT 0x400
49
50/* Macros for the pm07_control registers. */
51#define CBE_PM_CTR_INPUT_MUX(pm07_control) (((pm07_control) >> 26) & 0x3f)
52#define CBE_PM_CTR_INPUT_CONTROL 0x02000000
53#define CBE_PM_CTR_POLARITY 0x01000000
54#define CBE_PM_CTR_COUNT_CYCLES 0x00800000
55#define CBE_PM_CTR_ENABLE 0x00400000
56#define PM07_CTR_INPUT_MUX(x) (((x) & 0x3F) << 26)
57#define PM07_CTR_INPUT_CONTROL(x) (((x) & 1) << 25)
58#define PM07_CTR_POLARITY(x) (((x) & 1) << 24)
59#define PM07_CTR_COUNT_CYCLES(x) (((x) & 1) << 23)
60#define PM07_CTR_ENABLE(x) (((x) & 1) << 22)
61
62/* Macros for the pm_status register. */
63#define CBE_PM_CTR_OVERFLOW_INTR(ctr) (1 << (31 - ((ctr) & 7)))
64
65enum pm_reg_name {
66 group_control,
67 debug_bus_control,
68 trace_address,
69 ext_tr_timer,
70 pm_status,
71 pm_control,
72 pm_interval,
73 pm_start_stop,
74};
75
76/* Routines for reading/writing the PMU registers. */
77extern u32 cbe_read_phys_ctr(u32 cpu, u32 phys_ctr);
78extern void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val);
79extern u32 cbe_read_ctr(u32 cpu, u32 ctr);
80extern void cbe_write_ctr(u32 cpu, u32 ctr, u32 val);
81
82extern u32 cbe_read_pm07_control(u32 cpu, u32 ctr);
83extern void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val);
84extern u32 cbe_read_pm(u32 cpu, enum pm_reg_name reg);
85extern void cbe_write_pm(u32 cpu, enum pm_reg_name reg, u32 val);
86
87extern u32 cbe_get_ctr_size(u32 cpu, u32 phys_ctr);
88extern void cbe_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size);
89
90extern void cbe_enable_pm(u32 cpu);
91extern void cbe_disable_pm(u32 cpu);
92
93extern void cbe_read_trace_buffer(u32 cpu, u64 *buf);
94
95extern void cbe_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask);
96extern void cbe_disable_pm_interrupts(u32 cpu);
97extern u32 cbe_get_and_clear_pm_interrupts(u32 cpu);
98extern void cbe_sync_irq(int node);
99
100#define CBE_COUNT_SUPERVISOR_MODE 0
101#define CBE_COUNT_HYPERVISOR_MODE 1
102#define CBE_COUNT_PROBLEM_MODE 2
103#define CBE_COUNT_ALL_MODES 3
104
105#endif /* __ASM_CELL_PMU_H__ */
diff --git a/include/asm-powerpc/cell-regs.h b/include/asm-powerpc/cell-regs.h
deleted file mode 100644
index fd6fd00434e..00000000000
--- a/include/asm-powerpc/cell-regs.h
+++ /dev/null
@@ -1,315 +0,0 @@
1/*
2 * cbe_regs.h
3 *
4 * This file is intended to hold the various register definitions for CBE
5 * on-chip system devices (memory controller, IO controller, etc...)
6 *
7 * (C) Copyright IBM Corporation 2001,2006
8 *
9 * Authors: Maximino Aguilar (maguilar@us.ibm.com)
10 * David J. Erb (djerb@us.ibm.com)
11 *
12 * (c) 2006 Benjamin Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
13 */
14
15#ifndef CBE_REGS_H
16#define CBE_REGS_H
17
18#include <asm/cell-pmu.h>
19
20/*
21 *
22 * Some HID register definitions
23 *
24 */
25
26/* CBE specific HID0 bits */
27#define HID0_CBE_THERM_WAKEUP 0x0000020000000000ul
28#define HID0_CBE_SYSERR_WAKEUP 0x0000008000000000ul
29#define HID0_CBE_THERM_INT_EN 0x0000000400000000ul
30#define HID0_CBE_SYSERR_INT_EN 0x0000000200000000ul
31
32#define MAX_CBE 2
33
34/*
35 *
36 * Pervasive unit register definitions
37 *
38 */
39
40union spe_reg {
41 u64 val;
42 u8 spe[8];
43};
44
45union ppe_spe_reg {
46 u64 val;
47 struct {
48 u32 ppe;
49 u32 spe;
50 };
51};
52
53
54struct cbe_pmd_regs {
55 /* Debug Bus Control */
56 u64 pad_0x0000; /* 0x0000 */
57
58 u64 group_control; /* 0x0008 */
59
60 u8 pad_0x0010_0x00a8 [0x00a8 - 0x0010]; /* 0x0010 */
61
62 u64 debug_bus_control; /* 0x00a8 */
63
64 u8 pad_0x00b0_0x0100 [0x0100 - 0x00b0]; /* 0x00b0 */
65
66 u64 trace_aux_data; /* 0x0100 */
67 u64 trace_buffer_0_63; /* 0x0108 */
68 u64 trace_buffer_64_127; /* 0x0110 */
69 u64 trace_address; /* 0x0118 */
70 u64 ext_tr_timer; /* 0x0120 */
71
72 u8 pad_0x0128_0x0400 [0x0400 - 0x0128]; /* 0x0128 */
73
74 /* Performance Monitor */
75 u64 pm_status; /* 0x0400 */
76 u64 pm_control; /* 0x0408 */
77 u64 pm_interval; /* 0x0410 */
78 u64 pm_ctr[4]; /* 0x0418 */
79 u64 pm_start_stop; /* 0x0438 */
80 u64 pm07_control[8]; /* 0x0440 */
81
82 u8 pad_0x0480_0x0800 [0x0800 - 0x0480]; /* 0x0480 */
83
84 /* Thermal Sensor Registers */
85 union spe_reg ts_ctsr1; /* 0x0800 */
86 u64 ts_ctsr2; /* 0x0808 */
87 union spe_reg ts_mtsr1; /* 0x0810 */
88 u64 ts_mtsr2; /* 0x0818 */
89 union spe_reg ts_itr1; /* 0x0820 */
90 u64 ts_itr2; /* 0x0828 */
91 u64 ts_gitr; /* 0x0830 */
92 u64 ts_isr; /* 0x0838 */
93 u64 ts_imr; /* 0x0840 */
94 union spe_reg tm_cr1; /* 0x0848 */
95 u64 tm_cr2; /* 0x0850 */
96 u64 tm_simr; /* 0x0858 */
97 union ppe_spe_reg tm_tpr; /* 0x0860 */
98 union spe_reg tm_str1; /* 0x0868 */
99 u64 tm_str2; /* 0x0870 */
100 union ppe_spe_reg tm_tsr; /* 0x0878 */
101
102 /* Power Management */
103 u64 pmcr; /* 0x0880 */
104#define CBE_PMD_PAUSE_ZERO_CONTROL 0x10000
105 u64 pmsr; /* 0x0888 */
106
107 /* Time Base Register */
108 u64 tbr; /* 0x0890 */
109
110 u8 pad_0x0898_0x0c00 [0x0c00 - 0x0898]; /* 0x0898 */
111
112 /* Fault Isolation Registers */
113 u64 checkstop_fir; /* 0x0c00 */
114 u64 recoverable_fir; /* 0x0c08 */
115 u64 spec_att_mchk_fir; /* 0x0c10 */
116 u32 fir_mode_reg; /* 0x0c18 */
117 u8 pad_0x0c1c_0x0c20 [4]; /* 0x0c1c */
118#define CBE_PMD_FIR_MODE_M8 0x00800
119 u64 fir_enable_mask; /* 0x0c20 */
120
121 u8 pad_0x0c28_0x0ca8 [0x0ca8 - 0x0c28]; /* 0x0c28 */
122 u64 ras_esc_0; /* 0x0ca8 */
123 u8 pad_0x0cb0_0x1000 [0x1000 - 0x0cb0]; /* 0x0cb0 */
124};
125
126extern struct cbe_pmd_regs __iomem *cbe_get_pmd_regs(struct device_node *np);
127extern struct cbe_pmd_regs __iomem *cbe_get_cpu_pmd_regs(int cpu);
128
129/*
130 * PMU shadow registers
131 *
132 * Many of the registers in the performance monitoring unit are write-only,
133 * so we need to save a copy of what we write to those registers.
134 *
135 * The actual data counters are read/write. However, writing to the counters
136 * only takes effect if the PMU is enabled. Otherwise the value is stored in
137 * a hardware latch until the next time the PMU is enabled. So we save a copy
138 * of the counter values if we need to read them back while the PMU is
139 * disabled. The counter_value_in_latch field is a bitmap indicating which
140 * counters currently have a value waiting to be written.
141 */
142
143struct cbe_pmd_shadow_regs {
144 u32 group_control;
145 u32 debug_bus_control;
146 u32 trace_address;
147 u32 ext_tr_timer;
148 u32 pm_status;
149 u32 pm_control;
150 u32 pm_interval;
151 u32 pm_start_stop;
152 u32 pm07_control[NR_CTRS];
153
154 u32 pm_ctr[NR_PHYS_CTRS];
155 u32 counter_value_in_latch;
156};
157
158extern struct cbe_pmd_shadow_regs *cbe_get_pmd_shadow_regs(struct device_node *np);
159extern struct cbe_pmd_shadow_regs *cbe_get_cpu_pmd_shadow_regs(int cpu);
160
161/*
162 *
163 * IIC unit register definitions
164 *
165 */
166
167struct cbe_iic_pending_bits {
168 u32 data;
169 u8 flags;
170 u8 class;
171 u8 source;
172 u8 prio;
173};
174
175#define CBE_IIC_IRQ_VALID 0x80
176#define CBE_IIC_IRQ_IPI 0x40
177
178struct cbe_iic_thread_regs {
179 struct cbe_iic_pending_bits pending;
180 struct cbe_iic_pending_bits pending_destr;
181 u64 generate;
182 u64 prio;
183};
184
185struct cbe_iic_regs {
186 u8 pad_0x0000_0x0400[0x0400 - 0x0000]; /* 0x0000 */
187
188 /* IIC interrupt registers */
189 struct cbe_iic_thread_regs thread[2]; /* 0x0400 */
190
191 u64 iic_ir; /* 0x0440 */
192#define CBE_IIC_IR_PRIO(x) (((x) & 0xf) << 12)
193#define CBE_IIC_IR_DEST_NODE(x) (((x) & 0xf) << 4)
194#define CBE_IIC_IR_DEST_UNIT(x) ((x) & 0xf)
195#define CBE_IIC_IR_IOC_0 0x0
196#define CBE_IIC_IR_IOC_1S 0xb
197#define CBE_IIC_IR_PT_0 0xe
198#define CBE_IIC_IR_PT_1 0xf
199
200 u64 iic_is; /* 0x0448 */
201#define CBE_IIC_IS_PMI 0x2
202
203 u8 pad_0x0450_0x0500[0x0500 - 0x0450]; /* 0x0450 */
204
205 /* IOC FIR */
206 u64 ioc_fir_reset; /* 0x0500 */
207 u64 ioc_fir_set; /* 0x0508 */
208 u64 ioc_checkstop_enable; /* 0x0510 */
209 u64 ioc_fir_error_mask; /* 0x0518 */
210 u64 ioc_syserr_enable; /* 0x0520 */
211 u64 ioc_fir; /* 0x0528 */
212
213 u8 pad_0x0530_0x1000[0x1000 - 0x0530]; /* 0x0530 */
214};
215
216extern struct cbe_iic_regs __iomem *cbe_get_iic_regs(struct device_node *np);
217extern struct cbe_iic_regs __iomem *cbe_get_cpu_iic_regs(int cpu);
218
219
220struct cbe_mic_tm_regs {
221 u8 pad_0x0000_0x0040[0x0040 - 0x0000]; /* 0x0000 */
222
223 u64 mic_ctl_cnfg2; /* 0x0040 */
224#define CBE_MIC_ENABLE_AUX_TRC 0x8000000000000000LL
225#define CBE_MIC_DISABLE_PWR_SAV_2 0x0200000000000000LL
226#define CBE_MIC_DISABLE_AUX_TRC_WRAP 0x0100000000000000LL
227#define CBE_MIC_ENABLE_AUX_TRC_INT 0x0080000000000000LL
228
229 u64 pad_0x0048; /* 0x0048 */
230
231 u64 mic_aux_trc_base; /* 0x0050 */
232 u64 mic_aux_trc_max_addr; /* 0x0058 */
233 u64 mic_aux_trc_cur_addr; /* 0x0060 */
234 u64 mic_aux_trc_grf_addr; /* 0x0068 */
235 u64 mic_aux_trc_grf_data; /* 0x0070 */
236
237 u64 pad_0x0078; /* 0x0078 */
238
239 u64 mic_ctl_cnfg_0; /* 0x0080 */
240#define CBE_MIC_DISABLE_PWR_SAV_0 0x8000000000000000LL
241
242 u64 pad_0x0088; /* 0x0088 */
243
244 u64 slow_fast_timer_0; /* 0x0090 */
245 u64 slow_next_timer_0; /* 0x0098 */
246
247 u8 pad_0x00a0_0x00f8[0x00f8 - 0x00a0]; /* 0x00a0 */
248 u64 mic_df_ecc_address_0; /* 0x00f8 */
249
250 u8 pad_0x0100_0x01b8[0x01b8 - 0x0100]; /* 0x0100 */
251 u64 mic_df_ecc_address_1; /* 0x01b8 */
252
253 u64 mic_ctl_cnfg_1; /* 0x01c0 */
254#define CBE_MIC_DISABLE_PWR_SAV_1 0x8000000000000000LL
255
256 u64 pad_0x01c8; /* 0x01c8 */
257
258 u64 slow_fast_timer_1; /* 0x01d0 */
259 u64 slow_next_timer_1; /* 0x01d8 */
260
261 u8 pad_0x01e0_0x0208[0x0208 - 0x01e0]; /* 0x01e0 */
262 u64 mic_exc; /* 0x0208 */
263#define CBE_MIC_EXC_BLOCK_SCRUB 0x0800000000000000ULL
264#define CBE_MIC_EXC_FAST_SCRUB 0x0100000000000000ULL
265
266 u64 mic_mnt_cfg; /* 0x0210 */
267#define CBE_MIC_MNT_CFG_CHAN_0_POP 0x0002000000000000ULL
268#define CBE_MIC_MNT_CFG_CHAN_1_POP 0x0004000000000000ULL
269
270 u64 mic_df_config; /* 0x0218 */
271#define CBE_MIC_ECC_DISABLE_0 0x4000000000000000ULL
272#define CBE_MIC_ECC_REP_SINGLE_0 0x2000000000000000ULL
273#define CBE_MIC_ECC_DISABLE_1 0x0080000000000000ULL
274#define CBE_MIC_ECC_REP_SINGLE_1 0x0040000000000000ULL
275
276 u8 pad_0x0220_0x0230[0x0230 - 0x0220]; /* 0x0220 */
277 u64 mic_fir; /* 0x0230 */
278#define CBE_MIC_FIR_ECC_SINGLE_0_ERR 0x0200000000000000ULL
279#define CBE_MIC_FIR_ECC_MULTI_0_ERR 0x0100000000000000ULL
280#define CBE_MIC_FIR_ECC_SINGLE_1_ERR 0x0080000000000000ULL
281#define CBE_MIC_FIR_ECC_MULTI_1_ERR 0x0040000000000000ULL
282#define CBE_MIC_FIR_ECC_ERR_MASK 0xffff000000000000ULL
283#define CBE_MIC_FIR_ECC_SINGLE_0_CTE 0x0000020000000000ULL
284#define CBE_MIC_FIR_ECC_MULTI_0_CTE 0x0000010000000000ULL
285#define CBE_MIC_FIR_ECC_SINGLE_1_CTE 0x0000008000000000ULL
286#define CBE_MIC_FIR_ECC_MULTI_1_CTE 0x0000004000000000ULL
287#define CBE_MIC_FIR_ECC_CTE_MASK 0x0000ffff00000000ULL
288#define CBE_MIC_FIR_ECC_SINGLE_0_RESET 0x0000000002000000ULL
289#define CBE_MIC_FIR_ECC_MULTI_0_RESET 0x0000000001000000ULL
290#define CBE_MIC_FIR_ECC_SINGLE_1_RESET 0x0000000000800000ULL
291#define CBE_MIC_FIR_ECC_MULTI_1_RESET 0x0000000000400000ULL
292#define CBE_MIC_FIR_ECC_RESET_MASK 0x00000000ffff0000ULL
293#define CBE_MIC_FIR_ECC_SINGLE_0_SET 0x0000000000000200ULL
294#define CBE_MIC_FIR_ECC_MULTI_0_SET 0x0000000000000100ULL
295#define CBE_MIC_FIR_ECC_SINGLE_1_SET 0x0000000000000080ULL
296#define CBE_MIC_FIR_ECC_MULTI_1_SET 0x0000000000000040ULL
297#define CBE_MIC_FIR_ECC_SET_MASK 0x000000000000ffffULL
298 u64 mic_fir_debug; /* 0x0238 */
299
300 u8 pad_0x0240_0x1000[0x1000 - 0x0240]; /* 0x0240 */
301};
302
303extern struct cbe_mic_tm_regs __iomem *cbe_get_mic_tm_regs(struct device_node *np);
304extern struct cbe_mic_tm_regs __iomem *cbe_get_cpu_mic_tm_regs(int cpu);
305
306/* some utility functions to deal with SMT */
307extern u32 cbe_get_hw_thread_id(int cpu);
308extern u32 cbe_cpu_to_node(int cpu);
309extern u32 cbe_node_to_cpu(int node);
310
311/* Init this module early */
312extern void cbe_regs_init(void);
313
314
315#endif /* CBE_REGS_H */
diff --git a/include/asm-powerpc/checksum.h b/include/asm-powerpc/checksum.h
deleted file mode 100644
index 7cdf358337c..00000000000
--- a/include/asm-powerpc/checksum.h
+++ /dev/null
@@ -1,117 +0,0 @@
1#ifndef _ASM_POWERPC_CHECKSUM_H
2#define _ASM_POWERPC_CHECKSUM_H
3#ifdef __KERNEL__
4
5/*
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12/*
13 * This is a version of ip_compute_csum() optimized for IP headers,
14 * which always checksum on 4 octet boundaries. ihl is the number
15 * of 32-bit words and is always >= 5.
16 */
17extern __sum16 ip_fast_csum(const void *iph, unsigned int ihl);
18
19/*
20 * computes the checksum of the TCP/UDP pseudo-header
21 * returns a 16-bit checksum, already complemented
22 */
23extern __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
24 unsigned short len,
25 unsigned short proto,
26 __wsum sum);
27
28/*
29 * computes the checksum of a memory block at buff, length len,
30 * and adds in "sum" (32-bit)
31 *
32 * returns a 32-bit number suitable for feeding into itself
33 * or csum_tcpudp_magic
34 *
35 * this function must be called with even lengths, except
36 * for the last fragment, which may be odd
37 *
38 * it's best to have buff aligned on a 32-bit boundary
39 */
40extern __wsum csum_partial(const void *buff, int len, __wsum sum);
41
42/*
43 * Computes the checksum of a memory block at src, length len,
44 * and adds in "sum" (32-bit), while copying the block to dst.
45 * If an access exception occurs on src or dst, it stores -EFAULT
46 * to *src_err or *dst_err respectively (if that pointer is not
47 * NULL), and, for an error on src, zeroes the rest of dst.
48 *
49 * Like csum_partial, this must be called with even lengths,
50 * except for the last fragment.
51 */
52extern __wsum csum_partial_copy_generic(const void *src, void *dst,
53 int len, __wsum sum,
54 int *src_err, int *dst_err);
55/*
56 * the same as csum_partial, but copies from src to dst while it
57 * checksums.
58 */
59#define csum_partial_copy_from_user(src, dst, len, sum, errp) \
60 csum_partial_copy_generic((__force const void *)(src), (dst), (len), (sum), (errp), NULL)
61
62#define csum_partial_copy_nocheck(src, dst, len, sum) \
63 csum_partial_copy_generic((src), (dst), (len), (sum), NULL, NULL)
64
65
66/*
67 * turns a 32-bit partial checksum (e.g. from csum_partial) into a
68 * 1's complement 16-bit checksum.
69 */
70static inline __sum16 csum_fold(__wsum sum)
71{
72 unsigned int tmp;
73
74 /* swap the two 16-bit halves of sum */
75 __asm__("rlwinm %0,%1,16,0,31" : "=r" (tmp) : "r" (sum));
76 /* if there is a carry from adding the two 16-bit halves,
77 it will carry from the lower half into the upper half,
78 giving us the correct sum in the upper half. */
79 return (__force __sum16)(~((__force u32)sum + tmp) >> 16);
80}
81
82/*
83 * this routine is used for miscellaneous IP-like checksums, mainly
84 * in icmp.c
85 */
86static inline __sum16 ip_compute_csum(const void *buff, int len)
87{
88 return csum_fold(csum_partial(buff, len, 0));
89}
90
91static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
92 unsigned short len,
93 unsigned short proto,
94 __wsum sum)
95{
96#ifdef __powerpc64__
97 unsigned long s = (__force u32)sum;
98
99 s += (__force u32)saddr;
100 s += (__force u32)daddr;
101 s += proto + len;
102 s += (s >> 32);
103 return (__force __wsum) s;
104#else
105 __asm__("\n\
106 addc %0,%0,%1 \n\
107 adde %0,%0,%2 \n\
108 adde %0,%0,%3 \n\
109 addze %0,%0 \n\
110 "
111 : "=r" (sum)
112 : "r" (daddr), "r"(saddr), "r"(proto + len), "0"(sum));
113 return sum;
114#endif
115}
116#endif /* __KERNEL__ */
117#endif
diff --git a/include/asm-powerpc/clk_interface.h b/include/asm-powerpc/clk_interface.h
deleted file mode 100644
index ab1882c1e17..00000000000
--- a/include/asm-powerpc/clk_interface.h
+++ /dev/null
@@ -1,20 +0,0 @@
1#ifndef __ASM_POWERPC_CLK_INTERFACE_H
2#define __ASM_POWERPC_CLK_INTERFACE_H
3
4#include <linux/clk.h>
5
6struct clk_interface {
7 struct clk* (*clk_get) (struct device *dev, const char *id);
8 int (*clk_enable) (struct clk *clk);
9 void (*clk_disable) (struct clk *clk);
10 unsigned long (*clk_get_rate) (struct clk *clk);
11 void (*clk_put) (struct clk *clk);
12 long (*clk_round_rate) (struct clk *clk, unsigned long rate);
13 int (*clk_set_rate) (struct clk *clk, unsigned long rate);
14 int (*clk_set_parent) (struct clk *clk, struct clk *parent);
15 struct clk* (*clk_get_parent) (struct clk *clk);
16};
17
18extern struct clk_interface clk_functions;
19
20#endif /* __ASM_POWERPC_CLK_INTERFACE_H */
diff --git a/include/asm-powerpc/code-patching.h b/include/asm-powerpc/code-patching.h
deleted file mode 100644
index 107d9b915e3..00000000000
--- a/include/asm-powerpc/code-patching.h
+++ /dev/null
@@ -1,54 +0,0 @@
1#ifndef _ASM_POWERPC_CODE_PATCHING_H
2#define _ASM_POWERPC_CODE_PATCHING_H
3
4/*
5 * Copyright 2008, Michael Ellerman, IBM Corporation.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#include <asm/types.h>
14
15#define PPC_NOP_INSTR 0x60000000
16#define PPC_LWSYNC_INSTR 0x7c2004ac
17
18/* Flags for create_branch:
19 * "b" == create_branch(addr, target, 0);
20 * "ba" == create_branch(addr, target, BRANCH_ABSOLUTE);
21 * "bl" == create_branch(addr, target, BRANCH_SET_LINK);
22 * "bla" == create_branch(addr, target, BRANCH_ABSOLUTE | BRANCH_SET_LINK);
23 */
24#define BRANCH_SET_LINK 0x1
25#define BRANCH_ABSOLUTE 0x2
26
27unsigned int create_branch(const unsigned int *addr,
28 unsigned long target, int flags);
29unsigned int create_cond_branch(const unsigned int *addr,
30 unsigned long target, int flags);
31void patch_branch(unsigned int *addr, unsigned long target, int flags);
32void patch_instruction(unsigned int *addr, unsigned int instr);
33
34int instr_is_relative_branch(unsigned int instr);
35int instr_is_branch_to_addr(const unsigned int *instr, unsigned long addr);
36unsigned long branch_target(const unsigned int *instr);
37unsigned int translate_branch(const unsigned int *dest,
38 const unsigned int *src);
39
40static inline unsigned long ppc_function_entry(void *func)
41{
42#ifdef CONFIG_PPC64
43 /*
44 * On PPC64 the function pointer actually points to the function's
45 * descriptor. The first entry in the descriptor is the address
46 * of the function text.
47 */
48 return ((func_descr_t *)func)->entry;
49#else
50 return (unsigned long)func;
51#endif
52}
53
54#endif /* _ASM_POWERPC_CODE_PATCHING_H */
diff --git a/include/asm-powerpc/compat.h b/include/asm-powerpc/compat.h
deleted file mode 100644
index d811a8cd7b5..00000000000
--- a/include/asm-powerpc/compat.h
+++ /dev/null
@@ -1,214 +0,0 @@
1#ifndef _ASM_POWERPC_COMPAT_H
2#define _ASM_POWERPC_COMPAT_H
3#ifdef __KERNEL__
4/*
5 * Architecture specific compatibility types
6 */
7#include <linux/types.h>
8#include <linux/sched.h>
9
10#define COMPAT_USER_HZ 100
11
12typedef u32 compat_size_t;
13typedef s32 compat_ssize_t;
14typedef s32 compat_time_t;
15typedef s32 compat_clock_t;
16typedef s32 compat_pid_t;
17typedef u32 __compat_uid_t;
18typedef u32 __compat_gid_t;
19typedef u32 __compat_uid32_t;
20typedef u32 __compat_gid32_t;
21typedef u32 compat_mode_t;
22typedef u32 compat_ino_t;
23typedef u32 compat_dev_t;
24typedef s32 compat_off_t;
25typedef s64 compat_loff_t;
26typedef s16 compat_nlink_t;
27typedef u16 compat_ipc_pid_t;
28typedef s32 compat_daddr_t;
29typedef u32 compat_caddr_t;
30typedef __kernel_fsid_t compat_fsid_t;
31typedef s32 compat_key_t;
32typedef s32 compat_timer_t;
33
34typedef s32 compat_int_t;
35typedef s32 compat_long_t;
36typedef s64 compat_s64;
37typedef u32 compat_uint_t;
38typedef u32 compat_ulong_t;
39typedef u64 compat_u64;
40
41struct compat_timespec {
42 compat_time_t tv_sec;
43 s32 tv_nsec;
44};
45
46struct compat_timeval {
47 compat_time_t tv_sec;
48 s32 tv_usec;
49};
50
51struct compat_stat {
52 compat_dev_t st_dev;
53 compat_ino_t st_ino;
54 compat_mode_t st_mode;
55 compat_nlink_t st_nlink;
56 __compat_uid32_t st_uid;
57 __compat_gid32_t st_gid;
58 compat_dev_t st_rdev;
59 compat_off_t st_size;
60 compat_off_t st_blksize;
61 compat_off_t st_blocks;
62 compat_time_t st_atime;
63 u32 st_atime_nsec;
64 compat_time_t st_mtime;
65 u32 st_mtime_nsec;
66 compat_time_t st_ctime;
67 u32 st_ctime_nsec;
68 u32 __unused4[2];
69};
70
71struct compat_flock {
72 short l_type;
73 short l_whence;
74 compat_off_t l_start;
75 compat_off_t l_len;
76 compat_pid_t l_pid;
77};
78
79#define F_GETLK64 12 /* using 'struct flock64' */
80#define F_SETLK64 13
81#define F_SETLKW64 14
82
83struct compat_flock64 {
84 short l_type;
85 short l_whence;
86 compat_loff_t l_start;
87 compat_loff_t l_len;
88 compat_pid_t l_pid;
89};
90
91struct compat_statfs {
92 int f_type;
93 int f_bsize;
94 int f_blocks;
95 int f_bfree;
96 int f_bavail;
97 int f_files;
98 int f_ffree;
99 compat_fsid_t f_fsid;
100 int f_namelen; /* SunOS ignores this field. */
101 int f_frsize;
102 int f_spare[5];
103};
104
105#define COMPAT_RLIM_OLD_INFINITY 0x7fffffff
106#define COMPAT_RLIM_INFINITY 0xffffffff
107
108typedef u32 compat_old_sigset_t;
109
110#define _COMPAT_NSIG 64
111#define _COMPAT_NSIG_BPW 32
112
113typedef u32 compat_sigset_word;
114
115#define COMPAT_OFF_T_MAX 0x7fffffff
116#define COMPAT_LOFF_T_MAX 0x7fffffffffffffffL
117
118/*
119 * A pointer passed in from user mode. This should not
120 * be used for syscall parameters, just declare them
121 * as pointers because the syscall entry code will have
122 * appropriately converted them already.
123 */
124typedef u32 compat_uptr_t;
125
126static inline void __user *compat_ptr(compat_uptr_t uptr)
127{
128 return (void __user *)(unsigned long)uptr;
129}
130
131static inline compat_uptr_t ptr_to_compat(void __user *uptr)
132{
133 return (u32)(unsigned long)uptr;
134}
135
136static inline void __user *compat_alloc_user_space(long len)
137{
138 struct pt_regs *regs = current->thread.regs;
139 unsigned long usp = regs->gpr[1];
140
141 /*
142 * We cant access below the stack pointer in the 32bit ABI and
143 * can access 288 bytes in the 64bit ABI
144 */
145 if (!(test_thread_flag(TIF_32BIT)))
146 usp -= 288;
147
148 return (void __user *) (usp - len);
149}
150
151/*
152 * ipc64_perm is actually 32/64bit clean but since the compat layer refers to
153 * it we may as well define it.
154 */
155struct compat_ipc64_perm {
156 compat_key_t key;
157 __compat_uid_t uid;
158 __compat_gid_t gid;
159 __compat_uid_t cuid;
160 __compat_gid_t cgid;
161 compat_mode_t mode;
162 unsigned int seq;
163 unsigned int __pad2;
164 unsigned long __unused1; /* yes they really are 64bit pads */
165 unsigned long __unused2;
166};
167
168struct compat_semid64_ds {
169 struct compat_ipc64_perm sem_perm;
170 unsigned int __unused1;
171 compat_time_t sem_otime;
172 unsigned int __unused2;
173 compat_time_t sem_ctime;
174 compat_ulong_t sem_nsems;
175 compat_ulong_t __unused3;
176 compat_ulong_t __unused4;
177};
178
179struct compat_msqid64_ds {
180 struct compat_ipc64_perm msg_perm;
181 unsigned int __unused1;
182 compat_time_t msg_stime;
183 unsigned int __unused2;
184 compat_time_t msg_rtime;
185 unsigned int __unused3;
186 compat_time_t msg_ctime;
187 compat_ulong_t msg_cbytes;
188 compat_ulong_t msg_qnum;
189 compat_ulong_t msg_qbytes;
190 compat_pid_t msg_lspid;
191 compat_pid_t msg_lrpid;
192 compat_ulong_t __unused4;
193 compat_ulong_t __unused5;
194};
195
196struct compat_shmid64_ds {
197 struct compat_ipc64_perm shm_perm;
198 unsigned int __unused1;
199 compat_time_t shm_atime;
200 unsigned int __unused2;
201 compat_time_t shm_dtime;
202 unsigned int __unused3;
203 compat_time_t shm_ctime;
204 unsigned int __unused4;
205 compat_size_t shm_segsz;
206 compat_pid_t shm_cpid;
207 compat_pid_t shm_lpid;
208 compat_ulong_t shm_nattch;
209 compat_ulong_t __unused5;
210 compat_ulong_t __unused6;
211};
212
213#endif /* __KERNEL__ */
214#endif /* _ASM_POWERPC_COMPAT_H */
diff --git a/include/asm-powerpc/cpm.h b/include/asm-powerpc/cpm.h
deleted file mode 100644
index 63a55337c2d..00000000000
--- a/include/asm-powerpc/cpm.h
+++ /dev/null
@@ -1,103 +0,0 @@
1#ifndef __CPM_H
2#define __CPM_H
3
4#include <linux/compiler.h>
5#include <linux/types.h>
6
7/* Opcodes common to CPM1 and CPM2
8*/
9#define CPM_CR_INIT_TRX ((ushort)0x0000)
10#define CPM_CR_INIT_RX ((ushort)0x0001)
11#define CPM_CR_INIT_TX ((ushort)0x0002)
12#define CPM_CR_HUNT_MODE ((ushort)0x0003)
13#define CPM_CR_STOP_TX ((ushort)0x0004)
14#define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
15#define CPM_CR_RESTART_TX ((ushort)0x0006)
16#define CPM_CR_CLOSE_RX_BD ((ushort)0x0007)
17#define CPM_CR_SET_GADDR ((ushort)0x0008)
18#define CPM_CR_SET_TIMER ((ushort)0x0008)
19#define CPM_CR_STOP_IDMA ((ushort)0x000b)
20
21/* Buffer descriptors used by many of the CPM protocols. */
22typedef struct cpm_buf_desc {
23 ushort cbd_sc; /* Status and Control */
24 ushort cbd_datlen; /* Data length in buffer */
25 uint cbd_bufaddr; /* Buffer address in host memory */
26} cbd_t;
27
28/* Buffer descriptor control/status used by serial
29 */
30
31#define BD_SC_EMPTY (0x8000) /* Receive is empty */
32#define BD_SC_READY (0x8000) /* Transmit is ready */
33#define BD_SC_WRAP (0x2000) /* Last buffer descriptor */
34#define BD_SC_INTRPT (0x1000) /* Interrupt on change */
35#define BD_SC_LAST (0x0800) /* Last buffer in frame */
36#define BD_SC_TC (0x0400) /* Transmit CRC */
37#define BD_SC_CM (0x0200) /* Continous mode */
38#define BD_SC_ID (0x0100) /* Rec'd too many idles */
39#define BD_SC_P (0x0100) /* xmt preamble */
40#define BD_SC_BR (0x0020) /* Break received */
41#define BD_SC_FR (0x0010) /* Framing error */
42#define BD_SC_PR (0x0008) /* Parity error */
43#define BD_SC_NAK (0x0004) /* NAK - did not respond */
44#define BD_SC_OV (0x0002) /* Overrun */
45#define BD_SC_UN (0x0002) /* Underrun */
46#define BD_SC_CD (0x0001) /* */
47#define BD_SC_CL (0x0001) /* Collision */
48
49/* Buffer descriptor control/status used by Ethernet receive.
50 * Common to SCC and FCC.
51 */
52#define BD_ENET_RX_EMPTY (0x8000)
53#define BD_ENET_RX_WRAP (0x2000)
54#define BD_ENET_RX_INTR (0x1000)
55#define BD_ENET_RX_LAST (0x0800)
56#define BD_ENET_RX_FIRST (0x0400)
57#define BD_ENET_RX_MISS (0x0100)
58#define BD_ENET_RX_BC (0x0080) /* FCC Only */
59#define BD_ENET_RX_MC (0x0040) /* FCC Only */
60#define BD_ENET_RX_LG (0x0020)
61#define BD_ENET_RX_NO (0x0010)
62#define BD_ENET_RX_SH (0x0008)
63#define BD_ENET_RX_CR (0x0004)
64#define BD_ENET_RX_OV (0x0002)
65#define BD_ENET_RX_CL (0x0001)
66#define BD_ENET_RX_STATS (0x01ff) /* All status bits */
67
68/* Buffer descriptor control/status used by Ethernet transmit.
69 * Common to SCC and FCC.
70 */
71#define BD_ENET_TX_READY (0x8000)
72#define BD_ENET_TX_PAD (0x4000)
73#define BD_ENET_TX_WRAP (0x2000)
74#define BD_ENET_TX_INTR (0x1000)
75#define BD_ENET_TX_LAST (0x0800)
76#define BD_ENET_TX_TC (0x0400)
77#define BD_ENET_TX_DEF (0x0200)
78#define BD_ENET_TX_HB (0x0100)
79#define BD_ENET_TX_LC (0x0080)
80#define BD_ENET_TX_RL (0x0040)
81#define BD_ENET_TX_RCMASK (0x003c)
82#define BD_ENET_TX_UN (0x0002)
83#define BD_ENET_TX_CSL (0x0001)
84#define BD_ENET_TX_STATS (0x03ff) /* All status bits */
85
86/* Buffer descriptor control/status used by Transparent mode SCC.
87 */
88#define BD_SCC_TX_LAST (0x0800)
89
90/* Buffer descriptor control/status used by I2C.
91 */
92#define BD_I2C_START (0x0400)
93
94int cpm_muram_init(void);
95unsigned long cpm_muram_alloc(unsigned long size, unsigned long align);
96int cpm_muram_free(unsigned long offset);
97unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size);
98void __iomem *cpm_muram_addr(unsigned long offset);
99unsigned long cpm_muram_offset(void __iomem *addr);
100dma_addr_t cpm_muram_dma(void __iomem *addr);
101int cpm_command(u32 command, u8 opcode);
102
103#endif
diff --git a/include/asm-powerpc/cpm1.h b/include/asm-powerpc/cpm1.h
deleted file mode 100644
index 2ff798744c1..00000000000
--- a/include/asm-powerpc/cpm1.h
+++ /dev/null
@@ -1,652 +0,0 @@
1/*
2 * MPC8xx Communication Processor Module.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * This file contains structures and information for the communication
6 * processor channels. Some CPM control and status is available
7 * throught the MPC8xx internal memory map. See immap.h for details.
8 * This file only contains what I need for the moment, not the total
9 * CPM capabilities. I (or someone else) will add definitions as they
10 * are needed. -- Dan
11 *
12 * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
13 * bytes of the DP RAM and relocates the I2C parameter area to the
14 * IDMA1 space. The remaining DP RAM is available for buffer descriptors
15 * or other use.
16 */
17#ifndef __CPM1__
18#define __CPM1__
19
20#include <asm/8xx_immap.h>
21#include <asm/ptrace.h>
22#include <asm/cpm.h>
23
24/* CPM Command register.
25*/
26#define CPM_CR_RST ((ushort)0x8000)
27#define CPM_CR_OPCODE ((ushort)0x0f00)
28#define CPM_CR_CHAN ((ushort)0x00f0)
29#define CPM_CR_FLG ((ushort)0x0001)
30
31/* Channel numbers.
32*/
33#define CPM_CR_CH_SCC1 ((ushort)0x0000)
34#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */
35#define CPM_CR_CH_SCC2 ((ushort)0x0004)
36#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / IDMA2 / Timers */
37#define CPM_CR_CH_TIMER CPM_CR_CH_SPI
38#define CPM_CR_CH_SCC3 ((ushort)0x0008)
39#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */
40#define CPM_CR_CH_SCC4 ((ushort)0x000c)
41#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */
42
43#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4))
44
45/* Export the base address of the communication processor registers
46 * and dual port ram.
47 */
48extern cpm8xx_t __iomem *cpmp; /* Pointer to comm processor */
49
50#define cpm_dpalloc cpm_muram_alloc
51#define cpm_dpfree cpm_muram_free
52#define cpm_dpram_addr cpm_muram_addr
53#define cpm_dpram_phys cpm_muram_dma
54
55extern void cpm_setbrg(uint brg, uint rate);
56
57extern void cpm_load_patch(cpm8xx_t *cp);
58
59extern void cpm_reset(void);
60
61/* Parameter RAM offsets.
62*/
63#define PROFF_SCC1 ((uint)0x0000)
64#define PROFF_IIC ((uint)0x0080)
65#define PROFF_SCC2 ((uint)0x0100)
66#define PROFF_SPI ((uint)0x0180)
67#define PROFF_SCC3 ((uint)0x0200)
68#define PROFF_SMC1 ((uint)0x0280)
69#define PROFF_SCC4 ((uint)0x0300)
70#define PROFF_SMC2 ((uint)0x0380)
71
72/* Define enough so I can at least use the serial port as a UART.
73 * The MBX uses SMC1 as the host serial port.
74 */
75typedef struct smc_uart {
76 ushort smc_rbase; /* Rx Buffer descriptor base address */
77 ushort smc_tbase; /* Tx Buffer descriptor base address */
78 u_char smc_rfcr; /* Rx function code */
79 u_char smc_tfcr; /* Tx function code */
80 ushort smc_mrblr; /* Max receive buffer length */
81 uint smc_rstate; /* Internal */
82 uint smc_idp; /* Internal */
83 ushort smc_rbptr; /* Internal */
84 ushort smc_ibc; /* Internal */
85 uint smc_rxtmp; /* Internal */
86 uint smc_tstate; /* Internal */
87 uint smc_tdp; /* Internal */
88 ushort smc_tbptr; /* Internal */
89 ushort smc_tbc; /* Internal */
90 uint smc_txtmp; /* Internal */
91 ushort smc_maxidl; /* Maximum idle characters */
92 ushort smc_tmpidl; /* Temporary idle counter */
93 ushort smc_brklen; /* Last received break length */
94 ushort smc_brkec; /* rcv'd break condition counter */
95 ushort smc_brkcr; /* xmt break count register */
96 ushort smc_rmask; /* Temporary bit mask */
97 char res1[8]; /* Reserved */
98 ushort smc_rpbase; /* Relocation pointer */
99} smc_uart_t;
100
101/* Function code bits.
102*/
103#define SMC_EB ((u_char)0x10) /* Set big endian byte order */
104
105/* SMC uart mode register.
106*/
107#define SMCMR_REN ((ushort)0x0001)
108#define SMCMR_TEN ((ushort)0x0002)
109#define SMCMR_DM ((ushort)0x000c)
110#define SMCMR_SM_GCI ((ushort)0x0000)
111#define SMCMR_SM_UART ((ushort)0x0020)
112#define SMCMR_SM_TRANS ((ushort)0x0030)
113#define SMCMR_SM_MASK ((ushort)0x0030)
114#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
115#define SMCMR_REVD SMCMR_PM_EVEN
116#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
117#define SMCMR_BS SMCMR_PEN
118#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
119#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
120#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
121
122/* SMC2 as Centronics parallel printer. It is half duplex, in that
123 * it can only receive or transmit. The parameter ram values for
124 * each direction are either unique or properly overlap, so we can
125 * include them in one structure.
126 */
127typedef struct smc_centronics {
128 ushort scent_rbase;
129 ushort scent_tbase;
130 u_char scent_cfcr;
131 u_char scent_smask;
132 ushort scent_mrblr;
133 uint scent_rstate;
134 uint scent_r_ptr;
135 ushort scent_rbptr;
136 ushort scent_r_cnt;
137 uint scent_rtemp;
138 uint scent_tstate;
139 uint scent_t_ptr;
140 ushort scent_tbptr;
141 ushort scent_t_cnt;
142 uint scent_ttemp;
143 ushort scent_max_sl;
144 ushort scent_sl_cnt;
145 ushort scent_character1;
146 ushort scent_character2;
147 ushort scent_character3;
148 ushort scent_character4;
149 ushort scent_character5;
150 ushort scent_character6;
151 ushort scent_character7;
152 ushort scent_character8;
153 ushort scent_rccm;
154 ushort scent_rccr;
155} smc_cent_t;
156
157/* Centronics Status Mask Register.
158*/
159#define SMC_CENT_F ((u_char)0x08)
160#define SMC_CENT_PE ((u_char)0x04)
161#define SMC_CENT_S ((u_char)0x02)
162
163/* SMC Event and Mask register.
164*/
165#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
166#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
167#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */
168#define SMCM_BSY ((unsigned char)0x04)
169#define SMCM_TX ((unsigned char)0x02)
170#define SMCM_RX ((unsigned char)0x01)
171
172/* Baud rate generators.
173*/
174#define CPM_BRG_RST ((uint)0x00020000)
175#define CPM_BRG_EN ((uint)0x00010000)
176#define CPM_BRG_EXTC_INT ((uint)0x00000000)
177#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000)
178#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000)
179#define CPM_BRG_ATB ((uint)0x00002000)
180#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
181#define CPM_BRG_DIV16 ((uint)0x00000001)
182
183/* SI Clock Route Register
184*/
185#define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000)
186#define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000)
187#define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800)
188#define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100)
189#define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000)
190#define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000)
191#define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000)
192#define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000)
193
194/* SCCs.
195*/
196#define SCC_GSMRH_IRP ((uint)0x00040000)
197#define SCC_GSMRH_GDE ((uint)0x00010000)
198#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
199#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
200#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
201#define SCC_GSMRH_REVD ((uint)0x00002000)
202#define SCC_GSMRH_TRX ((uint)0x00001000)
203#define SCC_GSMRH_TTX ((uint)0x00000800)
204#define SCC_GSMRH_CDP ((uint)0x00000400)
205#define SCC_GSMRH_CTSP ((uint)0x00000200)
206#define SCC_GSMRH_CDS ((uint)0x00000100)
207#define SCC_GSMRH_CTSS ((uint)0x00000080)
208#define SCC_GSMRH_TFL ((uint)0x00000040)
209#define SCC_GSMRH_RFW ((uint)0x00000020)
210#define SCC_GSMRH_TXSY ((uint)0x00000010)
211#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
212#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
213#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
214#define SCC_GSMRH_RTSM ((uint)0x00000002)
215#define SCC_GSMRH_RSYN ((uint)0x00000001)
216
217#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
218#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
219#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
220#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
221#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
222#define SCC_GSMRL_TCI ((uint)0x10000000)
223#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
224#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
225#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
226#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
227#define SCC_GSMRL_RINV ((uint)0x02000000)
228#define SCC_GSMRL_TINV ((uint)0x01000000)
229#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
230#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
231#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
232#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
233#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
234#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
235#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
236#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
237#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
238#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
239#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
240#define SCC_GSMRL_TEND ((uint)0x00040000)
241#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
242#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
243#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
244#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
245#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
246#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
247#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
248#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
249#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
250#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
251#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
252#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
253#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
254#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
255#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
256#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
257#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
258#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
259#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
260#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
261#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
262#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
263#define SCC_GSMRL_ENR ((uint)0x00000020)
264#define SCC_GSMRL_ENT ((uint)0x00000010)
265#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
266#define SCC_GSMRL_MODE_QMC ((uint)0x0000000a)
267#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
268#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
269#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
270#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
271#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
272#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
273#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
274#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
275#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
276
277#define SCC_TODR_TOD ((ushort)0x8000)
278
279/* SCC Event and Mask register.
280*/
281#define SCCM_TXE ((unsigned char)0x10)
282#define SCCM_BSY ((unsigned char)0x04)
283#define SCCM_TX ((unsigned char)0x02)
284#define SCCM_RX ((unsigned char)0x01)
285
286typedef struct scc_param {
287 ushort scc_rbase; /* Rx Buffer descriptor base address */
288 ushort scc_tbase; /* Tx Buffer descriptor base address */
289 u_char scc_rfcr; /* Rx function code */
290 u_char scc_tfcr; /* Tx function code */
291 ushort scc_mrblr; /* Max receive buffer length */
292 uint scc_rstate; /* Internal */
293 uint scc_idp; /* Internal */
294 ushort scc_rbptr; /* Internal */
295 ushort scc_ibc; /* Internal */
296 uint scc_rxtmp; /* Internal */
297 uint scc_tstate; /* Internal */
298 uint scc_tdp; /* Internal */
299 ushort scc_tbptr; /* Internal */
300 ushort scc_tbc; /* Internal */
301 uint scc_txtmp; /* Internal */
302 uint scc_rcrc; /* Internal */
303 uint scc_tcrc; /* Internal */
304} sccp_t;
305
306/* Function code bits.
307*/
308#define SCC_EB ((u_char)0x10) /* Set big endian byte order */
309
310/* CPM Ethernet through SCCx.
311 */
312typedef struct scc_enet {
313 sccp_t sen_genscc;
314 uint sen_cpres; /* Preset CRC */
315 uint sen_cmask; /* Constant mask for CRC */
316 uint sen_crcec; /* CRC Error counter */
317 uint sen_alec; /* alignment error counter */
318 uint sen_disfc; /* discard frame counter */
319 ushort sen_pads; /* Tx short frame pad character */
320 ushort sen_retlim; /* Retry limit threshold */
321 ushort sen_retcnt; /* Retry limit counter */
322 ushort sen_maxflr; /* maximum frame length register */
323 ushort sen_minflr; /* minimum frame length register */
324 ushort sen_maxd1; /* maximum DMA1 length */
325 ushort sen_maxd2; /* maximum DMA2 length */
326 ushort sen_maxd; /* Rx max DMA */
327 ushort sen_dmacnt; /* Rx DMA counter */
328 ushort sen_maxb; /* Max BD byte count */
329 ushort sen_gaddr1; /* Group address filter */
330 ushort sen_gaddr2;
331 ushort sen_gaddr3;
332 ushort sen_gaddr4;
333 uint sen_tbuf0data0; /* Save area 0 - current frame */
334 uint sen_tbuf0data1; /* Save area 1 - current frame */
335 uint sen_tbuf0rba; /* Internal */
336 uint sen_tbuf0crc; /* Internal */
337 ushort sen_tbuf0bcnt; /* Internal */
338 ushort sen_paddrh; /* physical address (MSB) */
339 ushort sen_paddrm;
340 ushort sen_paddrl; /* physical address (LSB) */
341 ushort sen_pper; /* persistence */
342 ushort sen_rfbdptr; /* Rx first BD pointer */
343 ushort sen_tfbdptr; /* Tx first BD pointer */
344 ushort sen_tlbdptr; /* Tx last BD pointer */
345 uint sen_tbuf1data0; /* Save area 0 - current frame */
346 uint sen_tbuf1data1; /* Save area 1 - current frame */
347 uint sen_tbuf1rba; /* Internal */
348 uint sen_tbuf1crc; /* Internal */
349 ushort sen_tbuf1bcnt; /* Internal */
350 ushort sen_txlen; /* Tx Frame length counter */
351 ushort sen_iaddr1; /* Individual address filter */
352 ushort sen_iaddr2;
353 ushort sen_iaddr3;
354 ushort sen_iaddr4;
355 ushort sen_boffcnt; /* Backoff counter */
356
357 /* NOTE: Some versions of the manual have the following items
358 * incorrectly documented. Below is the proper order.
359 */
360 ushort sen_taddrh; /* temp address (MSB) */
361 ushort sen_taddrm;
362 ushort sen_taddrl; /* temp address (LSB) */
363} scc_enet_t;
364
365/* SCC Event register as used by Ethernet.
366*/
367#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
368#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
369#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
370#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
371#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
372#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
373
374/* SCC Mode Register (PMSR) as used by Ethernet.
375*/
376#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
377#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
378#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
379#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
380#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
381#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
382#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
383#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
384#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
385#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
386#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
387#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
388#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
389
390/* SCC as UART
391*/
392typedef struct scc_uart {
393 sccp_t scc_genscc;
394 char res1[8]; /* Reserved */
395 ushort scc_maxidl; /* Maximum idle chars */
396 ushort scc_idlc; /* temp idle counter */
397 ushort scc_brkcr; /* Break count register */
398 ushort scc_parec; /* receive parity error counter */
399 ushort scc_frmec; /* receive framing error counter */
400 ushort scc_nosec; /* receive noise counter */
401 ushort scc_brkec; /* receive break condition counter */
402 ushort scc_brkln; /* last received break length */
403 ushort scc_uaddr1; /* UART address character 1 */
404 ushort scc_uaddr2; /* UART address character 2 */
405 ushort scc_rtemp; /* Temp storage */
406 ushort scc_toseq; /* Transmit out of sequence char */
407 ushort scc_char1; /* control character 1 */
408 ushort scc_char2; /* control character 2 */
409 ushort scc_char3; /* control character 3 */
410 ushort scc_char4; /* control character 4 */
411 ushort scc_char5; /* control character 5 */
412 ushort scc_char6; /* control character 6 */
413 ushort scc_char7; /* control character 7 */
414 ushort scc_char8; /* control character 8 */
415 ushort scc_rccm; /* receive control character mask */
416 ushort scc_rccr; /* receive control character register */
417 ushort scc_rlbc; /* receive last break character */
418} scc_uart_t;
419
420/* SCC Event and Mask registers when it is used as a UART.
421*/
422#define UART_SCCM_GLR ((ushort)0x1000)
423#define UART_SCCM_GLT ((ushort)0x0800)
424#define UART_SCCM_AB ((ushort)0x0200)
425#define UART_SCCM_IDL ((ushort)0x0100)
426#define UART_SCCM_GRA ((ushort)0x0080)
427#define UART_SCCM_BRKE ((ushort)0x0040)
428#define UART_SCCM_BRKS ((ushort)0x0020)
429#define UART_SCCM_CCR ((ushort)0x0008)
430#define UART_SCCM_BSY ((ushort)0x0004)
431#define UART_SCCM_TX ((ushort)0x0002)
432#define UART_SCCM_RX ((ushort)0x0001)
433
434/* The SCC PMSR when used as a UART.
435*/
436#define SCU_PSMR_FLC ((ushort)0x8000)
437#define SCU_PSMR_SL ((ushort)0x4000)
438#define SCU_PSMR_CL ((ushort)0x3000)
439#define SCU_PSMR_UM ((ushort)0x0c00)
440#define SCU_PSMR_FRZ ((ushort)0x0200)
441#define SCU_PSMR_RZS ((ushort)0x0100)
442#define SCU_PSMR_SYN ((ushort)0x0080)
443#define SCU_PSMR_DRT ((ushort)0x0040)
444#define SCU_PSMR_PEN ((ushort)0x0010)
445#define SCU_PSMR_RPM ((ushort)0x000c)
446#define SCU_PSMR_REVP ((ushort)0x0008)
447#define SCU_PSMR_TPM ((ushort)0x0003)
448#define SCU_PSMR_TEVP ((ushort)0x0002)
449
450/* CPM Transparent mode SCC.
451 */
452typedef struct scc_trans {
453 sccp_t st_genscc;
454 uint st_cpres; /* Preset CRC */
455 uint st_cmask; /* Constant mask for CRC */
456} scc_trans_t;
457
458/* IIC parameter RAM.
459*/
460typedef struct iic {
461 ushort iic_rbase; /* Rx Buffer descriptor base address */
462 ushort iic_tbase; /* Tx Buffer descriptor base address */
463 u_char iic_rfcr; /* Rx function code */
464 u_char iic_tfcr; /* Tx function code */
465 ushort iic_mrblr; /* Max receive buffer length */
466 uint iic_rstate; /* Internal */
467 uint iic_rdp; /* Internal */
468 ushort iic_rbptr; /* Internal */
469 ushort iic_rbc; /* Internal */
470 uint iic_rxtmp; /* Internal */
471 uint iic_tstate; /* Internal */
472 uint iic_tdp; /* Internal */
473 ushort iic_tbptr; /* Internal */
474 ushort iic_tbc; /* Internal */
475 uint iic_txtmp; /* Internal */
476 char res1[4]; /* Reserved */
477 ushort iic_rpbase; /* Relocation pointer */
478 char res2[2]; /* Reserved */
479} iic_t;
480
481/* SPI parameter RAM.
482*/
483typedef struct spi {
484 ushort spi_rbase; /* Rx Buffer descriptor base address */
485 ushort spi_tbase; /* Tx Buffer descriptor base address */
486 u_char spi_rfcr; /* Rx function code */
487 u_char spi_tfcr; /* Tx function code */
488 ushort spi_mrblr; /* Max receive buffer length */
489 uint spi_rstate; /* Internal */
490 uint spi_rdp; /* Internal */
491 ushort spi_rbptr; /* Internal */
492 ushort spi_rbc; /* Internal */
493 uint spi_rxtmp; /* Internal */
494 uint spi_tstate; /* Internal */
495 uint spi_tdp; /* Internal */
496 ushort spi_tbptr; /* Internal */
497 ushort spi_tbc; /* Internal */
498 uint spi_txtmp; /* Internal */
499 uint spi_res;
500 ushort spi_rpbase; /* Relocation pointer */
501 ushort spi_res2;
502} spi_t;
503
504/* SPI Mode register.
505*/
506#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
507#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
508#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
509#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
510#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
511#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
512#define SPMODE_EN ((ushort)0x0100) /* Enable */
513#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
514#define SPMODE_LEN4 ((ushort)0x0030) /* 4 bits per char */
515#define SPMODE_LEN8 ((ushort)0x0070) /* 8 bits per char */
516#define SPMODE_LEN16 ((ushort)0x00f0) /* 16 bits per char */
517#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
518
519/* SPIE fields */
520#define SPIE_MME 0x20
521#define SPIE_TXE 0x10
522#define SPIE_BSY 0x04
523#define SPIE_TXB 0x02
524#define SPIE_RXB 0x01
525
526/*
527 * RISC Controller Configuration Register definitons
528 */
529#define RCCR_TIME 0x8000 /* RISC Timer Enable */
530#define RCCR_TIMEP(t) (((t) & 0x3F)<<8) /* RISC Timer Period */
531#define RCCR_TIME_MASK 0x00FF /* not RISC Timer related bits */
532
533/* RISC Timer Parameter RAM offset */
534#define PROFF_RTMR ((uint)0x01B0)
535
536typedef struct risc_timer_pram {
537 unsigned short tm_base; /* RISC Timer Table Base Address */
538 unsigned short tm_ptr; /* RISC Timer Table Pointer (internal) */
539 unsigned short r_tmr; /* RISC Timer Mode Register */
540 unsigned short r_tmv; /* RISC Timer Valid Register */
541 unsigned long tm_cmd; /* RISC Timer Command Register */
542 unsigned long tm_cnt; /* RISC Timer Internal Count */
543} rt_pram_t;
544
545/* Bits in RISC Timer Command Register */
546#define TM_CMD_VALID 0x80000000 /* Valid - Enables the timer */
547#define TM_CMD_RESTART 0x40000000 /* Restart - for automatic restart */
548#define TM_CMD_PWM 0x20000000 /* Run in Pulse Width Modulation Mode */
549#define TM_CMD_NUM(n) (((n)&0xF)<<16) /* Timer Number */
550#define TM_CMD_PERIOD(p) ((p)&0xFFFF) /* Timer Period */
551
552/* CPM interrupts. There are nearly 32 interrupts generated by CPM
553 * channels or devices. All of these are presented to the PPC core
554 * as a single interrupt. The CPM interrupt handler dispatches its
555 * own handlers, in a similar fashion to the PPC core handler. We
556 * use the table as defined in the manuals (i.e. no special high
557 * priority and SCC1 == SCCa, etc...).
558 */
559#define CPMVEC_NR 32
560#define CPMVEC_PIO_PC15 ((ushort)0x1f)
561#define CPMVEC_SCC1 ((ushort)0x1e)
562#define CPMVEC_SCC2 ((ushort)0x1d)
563#define CPMVEC_SCC3 ((ushort)0x1c)
564#define CPMVEC_SCC4 ((ushort)0x1b)
565#define CPMVEC_PIO_PC14 ((ushort)0x1a)
566#define CPMVEC_TIMER1 ((ushort)0x19)
567#define CPMVEC_PIO_PC13 ((ushort)0x18)
568#define CPMVEC_PIO_PC12 ((ushort)0x17)
569#define CPMVEC_SDMA_CB_ERR ((ushort)0x16)
570#define CPMVEC_IDMA1 ((ushort)0x15)
571#define CPMVEC_IDMA2 ((ushort)0x14)
572#define CPMVEC_TIMER2 ((ushort)0x12)
573#define CPMVEC_RISCTIMER ((ushort)0x11)
574#define CPMVEC_I2C ((ushort)0x10)
575#define CPMVEC_PIO_PC11 ((ushort)0x0f)
576#define CPMVEC_PIO_PC10 ((ushort)0x0e)
577#define CPMVEC_TIMER3 ((ushort)0x0c)
578#define CPMVEC_PIO_PC9 ((ushort)0x0b)
579#define CPMVEC_PIO_PC8 ((ushort)0x0a)
580#define CPMVEC_PIO_PC7 ((ushort)0x09)
581#define CPMVEC_TIMER4 ((ushort)0x07)
582#define CPMVEC_PIO_PC6 ((ushort)0x06)
583#define CPMVEC_SPI ((ushort)0x05)
584#define CPMVEC_SMC1 ((ushort)0x04)
585#define CPMVEC_SMC2 ((ushort)0x03)
586#define CPMVEC_PIO_PC5 ((ushort)0x02)
587#define CPMVEC_PIO_PC4 ((ushort)0x01)
588#define CPMVEC_ERROR ((ushort)0x00)
589
590/* CPM interrupt configuration vector.
591*/
592#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
593#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
594#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
595#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
596#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */
597#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
598#define CICR_IEN ((uint)0x00000080) /* Int. enable */
599#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
600
601#define IMAP_ADDR (get_immrbase())
602
603#define CPM_PIN_INPUT 0
604#define CPM_PIN_OUTPUT 1
605#define CPM_PIN_PRIMARY 0
606#define CPM_PIN_SECONDARY 2
607#define CPM_PIN_GPIO 4
608#define CPM_PIN_OPENDRAIN 8
609
610enum cpm_port {
611 CPM_PORTA,
612 CPM_PORTB,
613 CPM_PORTC,
614 CPM_PORTD,
615 CPM_PORTE,
616};
617
618void cpm1_set_pin(enum cpm_port port, int pin, int flags);
619
620enum cpm_clk_dir {
621 CPM_CLK_RX,
622 CPM_CLK_TX,
623 CPM_CLK_RTX
624};
625
626enum cpm_clk_target {
627 CPM_CLK_SCC1,
628 CPM_CLK_SCC2,
629 CPM_CLK_SCC3,
630 CPM_CLK_SCC4,
631 CPM_CLK_SMC1,
632 CPM_CLK_SMC2,
633};
634
635enum cpm_clk {
636 CPM_BRG1, /* Baud Rate Generator 1 */
637 CPM_BRG2, /* Baud Rate Generator 2 */
638 CPM_BRG3, /* Baud Rate Generator 3 */
639 CPM_BRG4, /* Baud Rate Generator 4 */
640 CPM_CLK1, /* Clock 1 */
641 CPM_CLK2, /* Clock 2 */
642 CPM_CLK3, /* Clock 3 */
643 CPM_CLK4, /* Clock 4 */
644 CPM_CLK5, /* Clock 5 */
645 CPM_CLK6, /* Clock 6 */
646 CPM_CLK7, /* Clock 7 */
647 CPM_CLK8, /* Clock 8 */
648};
649
650int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode);
651
652#endif /* __CPM1__ */
diff --git a/include/asm-powerpc/cpm2.h b/include/asm-powerpc/cpm2.h
deleted file mode 100644
index 2c7fd9cee29..00000000000
--- a/include/asm-powerpc/cpm2.h
+++ /dev/null
@@ -1,1175 +0,0 @@
1/*
2 * Communication Processor Module v2.
3 *
4 * This file contains structures and information for the communication
5 * processor channels found in the dual port RAM or parameter RAM.
6 * All CPM control and status is available through the CPM2 internal
7 * memory map. See immap_cpm2.h for details.
8 */
9#ifdef __KERNEL__
10#ifndef __CPM2__
11#define __CPM2__
12
13#include <asm/immap_cpm2.h>
14#include <asm/cpm.h>
15
16#ifdef CONFIG_PPC_85xx
17#define CPM_MAP_ADDR (get_immrbase() + 0x80000)
18#endif
19
20/* CPM Command register.
21*/
22#define CPM_CR_RST ((uint)0x80000000)
23#define CPM_CR_PAGE ((uint)0x7c000000)
24#define CPM_CR_SBLOCK ((uint)0x03e00000)
25#define CPM_CR_FLG ((uint)0x00010000)
26#define CPM_CR_MCN ((uint)0x00003fc0)
27#define CPM_CR_OPCODE ((uint)0x0000000f)
28
29/* Device sub-block and page codes.
30*/
31#define CPM_CR_SCC1_SBLOCK (0x04)
32#define CPM_CR_SCC2_SBLOCK (0x05)
33#define CPM_CR_SCC3_SBLOCK (0x06)
34#define CPM_CR_SCC4_SBLOCK (0x07)
35#define CPM_CR_SMC1_SBLOCK (0x08)
36#define CPM_CR_SMC2_SBLOCK (0x09)
37#define CPM_CR_SPI_SBLOCK (0x0a)
38#define CPM_CR_I2C_SBLOCK (0x0b)
39#define CPM_CR_TIMER_SBLOCK (0x0f)
40#define CPM_CR_RAND_SBLOCK (0x0e)
41#define CPM_CR_FCC1_SBLOCK (0x10)
42#define CPM_CR_FCC2_SBLOCK (0x11)
43#define CPM_CR_FCC3_SBLOCK (0x12)
44#define CPM_CR_IDMA1_SBLOCK (0x14)
45#define CPM_CR_IDMA2_SBLOCK (0x15)
46#define CPM_CR_IDMA3_SBLOCK (0x16)
47#define CPM_CR_IDMA4_SBLOCK (0x17)
48#define CPM_CR_MCC1_SBLOCK (0x1c)
49
50#define CPM_CR_FCC_SBLOCK(x) (x + 0x10)
51
52#define CPM_CR_SCC1_PAGE (0x00)
53#define CPM_CR_SCC2_PAGE (0x01)
54#define CPM_CR_SCC3_PAGE (0x02)
55#define CPM_CR_SCC4_PAGE (0x03)
56#define CPM_CR_SMC1_PAGE (0x07)
57#define CPM_CR_SMC2_PAGE (0x08)
58#define CPM_CR_SPI_PAGE (0x09)
59#define CPM_CR_I2C_PAGE (0x0a)
60#define CPM_CR_TIMER_PAGE (0x0a)
61#define CPM_CR_RAND_PAGE (0x0a)
62#define CPM_CR_FCC1_PAGE (0x04)
63#define CPM_CR_FCC2_PAGE (0x05)
64#define CPM_CR_FCC3_PAGE (0x06)
65#define CPM_CR_IDMA1_PAGE (0x07)
66#define CPM_CR_IDMA2_PAGE (0x08)
67#define CPM_CR_IDMA3_PAGE (0x09)
68#define CPM_CR_IDMA4_PAGE (0x0a)
69#define CPM_CR_MCC1_PAGE (0x07)
70#define CPM_CR_MCC2_PAGE (0x08)
71
72#define CPM_CR_FCC_PAGE(x) (x + 0x04)
73
74/* CPM2-specific opcodes (see cpm.h for common opcodes)
75*/
76#define CPM_CR_START_IDMA ((ushort)0x0009)
77
78#define mk_cr_cmd(PG, SBC, MCN, OP) \
79 ((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
80
81/* The number of pages of host memory we allocate for CPM. This is
82 * done early in kernel initialization to get physically contiguous
83 * pages.
84 */
85#define NUM_CPM_HOST_PAGES 2
86
87/* Export the base address of the communication processor registers
88 * and dual port ram.
89 */
90extern cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor */
91
92#define cpm_dpalloc cpm_muram_alloc
93#define cpm_dpfree cpm_muram_free
94#define cpm_dpram_addr cpm_muram_addr
95
96extern void cpm_setbrg(uint brg, uint rate);
97extern void cpm2_fastbrg(uint brg, uint rate, int div16);
98extern void cpm2_reset(void);
99
100/* Function code bits, usually generic to devices.
101*/
102#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
103#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */
104#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */
105#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
106#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
107
108/* Parameter RAM offsets from the base.
109*/
110#define PROFF_SCC1 ((uint)0x8000)
111#define PROFF_SCC2 ((uint)0x8100)
112#define PROFF_SCC3 ((uint)0x8200)
113#define PROFF_SCC4 ((uint)0x8300)
114#define PROFF_FCC1 ((uint)0x8400)
115#define PROFF_FCC2 ((uint)0x8500)
116#define PROFF_FCC3 ((uint)0x8600)
117#define PROFF_MCC1 ((uint)0x8700)
118#define PROFF_SMC1_BASE ((uint)0x87fc)
119#define PROFF_IDMA1_BASE ((uint)0x87fe)
120#define PROFF_MCC2 ((uint)0x8800)
121#define PROFF_SMC2_BASE ((uint)0x88fc)
122#define PROFF_IDMA2_BASE ((uint)0x88fe)
123#define PROFF_SPI_BASE ((uint)0x89fc)
124#define PROFF_IDMA3_BASE ((uint)0x89fe)
125#define PROFF_TIMERS ((uint)0x8ae0)
126#define PROFF_REVNUM ((uint)0x8af0)
127#define PROFF_RAND ((uint)0x8af8)
128#define PROFF_I2C_BASE ((uint)0x8afc)
129#define PROFF_IDMA4_BASE ((uint)0x8afe)
130
131#define PROFF_SCC_SIZE ((uint)0x100)
132#define PROFF_FCC_SIZE ((uint)0x100)
133#define PROFF_SMC_SIZE ((uint)64)
134
135/* The SMCs are relocated to any of the first eight DPRAM pages.
136 * We will fix these at the first locations of DPRAM, until we
137 * get some microcode patches :-).
138 * The parameter ram space for the SMCs is fifty-some bytes, and
139 * they are required to start on a 64 byte boundary.
140 */
141#define PROFF_SMC1 (0)
142#define PROFF_SMC2 (64)
143
144
145/* Define enough so I can at least use the serial port as a UART.
146 */
147typedef struct smc_uart {
148 ushort smc_rbase; /* Rx Buffer descriptor base address */
149 ushort smc_tbase; /* Tx Buffer descriptor base address */
150 u_char smc_rfcr; /* Rx function code */
151 u_char smc_tfcr; /* Tx function code */
152 ushort smc_mrblr; /* Max receive buffer length */
153 uint smc_rstate; /* Internal */
154 uint smc_idp; /* Internal */
155 ushort smc_rbptr; /* Internal */
156 ushort smc_ibc; /* Internal */
157 uint smc_rxtmp; /* Internal */
158 uint smc_tstate; /* Internal */
159 uint smc_tdp; /* Internal */
160 ushort smc_tbptr; /* Internal */
161 ushort smc_tbc; /* Internal */
162 uint smc_txtmp; /* Internal */
163 ushort smc_maxidl; /* Maximum idle characters */
164 ushort smc_tmpidl; /* Temporary idle counter */
165 ushort smc_brklen; /* Last received break length */
166 ushort smc_brkec; /* rcv'd break condition counter */
167 ushort smc_brkcr; /* xmt break count register */
168 ushort smc_rmask; /* Temporary bit mask */
169 uint smc_stmp; /* SDMA Temp */
170} smc_uart_t;
171
172/* SMC uart mode register (Internal memory map).
173*/
174#define SMCMR_REN ((ushort)0x0001)
175#define SMCMR_TEN ((ushort)0x0002)
176#define SMCMR_DM ((ushort)0x000c)
177#define SMCMR_SM_GCI ((ushort)0x0000)
178#define SMCMR_SM_UART ((ushort)0x0020)
179#define SMCMR_SM_TRANS ((ushort)0x0030)
180#define SMCMR_SM_MASK ((ushort)0x0030)
181#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
182#define SMCMR_REVD SMCMR_PM_EVEN
183#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
184#define SMCMR_BS SMCMR_PEN
185#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
186#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
187#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
188
189/* SMC Event and Mask register.
190*/
191#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
192#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
193#define SMCM_TXE ((unsigned char)0x10)
194#define SMCM_BSY ((unsigned char)0x04)
195#define SMCM_TX ((unsigned char)0x02)
196#define SMCM_RX ((unsigned char)0x01)
197
198/* Baud rate generators.
199*/
200#define CPM_BRG_RST ((uint)0x00020000)
201#define CPM_BRG_EN ((uint)0x00010000)
202#define CPM_BRG_EXTC_INT ((uint)0x00000000)
203#define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000)
204#define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000)
205#define CPM_BRG_ATB ((uint)0x00002000)
206#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
207#define CPM_BRG_DIV16 ((uint)0x00000001)
208
209/* SCCs.
210*/
211#define SCC_GSMRH_IRP ((uint)0x00040000)
212#define SCC_GSMRH_GDE ((uint)0x00010000)
213#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
214#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
215#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
216#define SCC_GSMRH_REVD ((uint)0x00002000)
217#define SCC_GSMRH_TRX ((uint)0x00001000)
218#define SCC_GSMRH_TTX ((uint)0x00000800)
219#define SCC_GSMRH_CDP ((uint)0x00000400)
220#define SCC_GSMRH_CTSP ((uint)0x00000200)
221#define SCC_GSMRH_CDS ((uint)0x00000100)
222#define SCC_GSMRH_CTSS ((uint)0x00000080)
223#define SCC_GSMRH_TFL ((uint)0x00000040)
224#define SCC_GSMRH_RFW ((uint)0x00000020)
225#define SCC_GSMRH_TXSY ((uint)0x00000010)
226#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
227#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
228#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
229#define SCC_GSMRH_RTSM ((uint)0x00000002)
230#define SCC_GSMRH_RSYN ((uint)0x00000001)
231
232#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
233#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
234#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
235#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
236#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
237#define SCC_GSMRL_TCI ((uint)0x10000000)
238#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
239#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
240#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
241#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
242#define SCC_GSMRL_RINV ((uint)0x02000000)
243#define SCC_GSMRL_TINV ((uint)0x01000000)
244#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
245#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
246#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
247#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
248#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
249#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
250#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
251#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
252#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
253#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
254#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
255#define SCC_GSMRL_TEND ((uint)0x00040000)
256#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
257#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
258#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
259#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
260#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
261#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
262#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
263#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
264#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
265#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
266#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
267#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
268#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
269#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
270#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
271#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
272#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
273#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
274#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
275#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
276#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
277#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
278#define SCC_GSMRL_ENR ((uint)0x00000020)
279#define SCC_GSMRL_ENT ((uint)0x00000010)
280#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
281#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
282#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
283#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
284#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
285#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
286#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
287#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
288#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
289#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
290
291#define SCC_TODR_TOD ((ushort)0x8000)
292
293/* SCC Event and Mask register.
294*/
295#define SCCM_TXE ((unsigned char)0x10)
296#define SCCM_BSY ((unsigned char)0x04)
297#define SCCM_TX ((unsigned char)0x02)
298#define SCCM_RX ((unsigned char)0x01)
299
300typedef struct scc_param {
301 ushort scc_rbase; /* Rx Buffer descriptor base address */
302 ushort scc_tbase; /* Tx Buffer descriptor base address */
303 u_char scc_rfcr; /* Rx function code */
304 u_char scc_tfcr; /* Tx function code */
305 ushort scc_mrblr; /* Max receive buffer length */
306 uint scc_rstate; /* Internal */
307 uint scc_idp; /* Internal */
308 ushort scc_rbptr; /* Internal */
309 ushort scc_ibc; /* Internal */
310 uint scc_rxtmp; /* Internal */
311 uint scc_tstate; /* Internal */
312 uint scc_tdp; /* Internal */
313 ushort scc_tbptr; /* Internal */
314 ushort scc_tbc; /* Internal */
315 uint scc_txtmp; /* Internal */
316 uint scc_rcrc; /* Internal */
317 uint scc_tcrc; /* Internal */
318} sccp_t;
319
320/* CPM Ethernet through SCC1.
321 */
322typedef struct scc_enet {
323 sccp_t sen_genscc;
324 uint sen_cpres; /* Preset CRC */
325 uint sen_cmask; /* Constant mask for CRC */
326 uint sen_crcec; /* CRC Error counter */
327 uint sen_alec; /* alignment error counter */
328 uint sen_disfc; /* discard frame counter */
329 ushort sen_pads; /* Tx short frame pad character */
330 ushort sen_retlim; /* Retry limit threshold */
331 ushort sen_retcnt; /* Retry limit counter */
332 ushort sen_maxflr; /* maximum frame length register */
333 ushort sen_minflr; /* minimum frame length register */
334 ushort sen_maxd1; /* maximum DMA1 length */
335 ushort sen_maxd2; /* maximum DMA2 length */
336 ushort sen_maxd; /* Rx max DMA */
337 ushort sen_dmacnt; /* Rx DMA counter */
338 ushort sen_maxb; /* Max BD byte count */
339 ushort sen_gaddr1; /* Group address filter */
340 ushort sen_gaddr2;
341 ushort sen_gaddr3;
342 ushort sen_gaddr4;
343 uint sen_tbuf0data0; /* Save area 0 - current frame */
344 uint sen_tbuf0data1; /* Save area 1 - current frame */
345 uint sen_tbuf0rba; /* Internal */
346 uint sen_tbuf0crc; /* Internal */
347 ushort sen_tbuf0bcnt; /* Internal */
348 ushort sen_paddrh; /* physical address (MSB) */
349 ushort sen_paddrm;
350 ushort sen_paddrl; /* physical address (LSB) */
351 ushort sen_pper; /* persistence */
352 ushort sen_rfbdptr; /* Rx first BD pointer */
353 ushort sen_tfbdptr; /* Tx first BD pointer */
354 ushort sen_tlbdptr; /* Tx last BD pointer */
355 uint sen_tbuf1data0; /* Save area 0 - current frame */
356 uint sen_tbuf1data1; /* Save area 1 - current frame */
357 uint sen_tbuf1rba; /* Internal */
358 uint sen_tbuf1crc; /* Internal */
359 ushort sen_tbuf1bcnt; /* Internal */
360 ushort sen_txlen; /* Tx Frame length counter */
361 ushort sen_iaddr1; /* Individual address filter */
362 ushort sen_iaddr2;
363 ushort sen_iaddr3;
364 ushort sen_iaddr4;
365 ushort sen_boffcnt; /* Backoff counter */
366
367 /* NOTE: Some versions of the manual have the following items
368 * incorrectly documented. Below is the proper order.
369 */
370 ushort sen_taddrh; /* temp address (MSB) */
371 ushort sen_taddrm;
372 ushort sen_taddrl; /* temp address (LSB) */
373} scc_enet_t;
374
375
376/* SCC Event register as used by Ethernet.
377*/
378#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
379#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
380#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
381#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
382#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
383#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
384
385/* SCC Mode Register (PSMR) as used by Ethernet.
386*/
387#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
388#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
389#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
390#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
391#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
392#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
393#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
394#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
395#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
396#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
397#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
398#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
399#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
400
401/* SCC as UART
402*/
403typedef struct scc_uart {
404 sccp_t scc_genscc;
405 uint scc_res1; /* Reserved */
406 uint scc_res2; /* Reserved */
407 ushort scc_maxidl; /* Maximum idle chars */
408 ushort scc_idlc; /* temp idle counter */
409 ushort scc_brkcr; /* Break count register */
410 ushort scc_parec; /* receive parity error counter */
411 ushort scc_frmec; /* receive framing error counter */
412 ushort scc_nosec; /* receive noise counter */
413 ushort scc_brkec; /* receive break condition counter */
414 ushort scc_brkln; /* last received break length */
415 ushort scc_uaddr1; /* UART address character 1 */
416 ushort scc_uaddr2; /* UART address character 2 */
417 ushort scc_rtemp; /* Temp storage */
418 ushort scc_toseq; /* Transmit out of sequence char */
419 ushort scc_char1; /* control character 1 */
420 ushort scc_char2; /* control character 2 */
421 ushort scc_char3; /* control character 3 */
422 ushort scc_char4; /* control character 4 */
423 ushort scc_char5; /* control character 5 */
424 ushort scc_char6; /* control character 6 */
425 ushort scc_char7; /* control character 7 */
426 ushort scc_char8; /* control character 8 */
427 ushort scc_rccm; /* receive control character mask */
428 ushort scc_rccr; /* receive control character register */
429 ushort scc_rlbc; /* receive last break character */
430} scc_uart_t;
431
432/* SCC Event and Mask registers when it is used as a UART.
433*/
434#define UART_SCCM_GLR ((ushort)0x1000)
435#define UART_SCCM_GLT ((ushort)0x0800)
436#define UART_SCCM_AB ((ushort)0x0200)
437#define UART_SCCM_IDL ((ushort)0x0100)
438#define UART_SCCM_GRA ((ushort)0x0080)
439#define UART_SCCM_BRKE ((ushort)0x0040)
440#define UART_SCCM_BRKS ((ushort)0x0020)
441#define UART_SCCM_CCR ((ushort)0x0008)
442#define UART_SCCM_BSY ((ushort)0x0004)
443#define UART_SCCM_TX ((ushort)0x0002)
444#define UART_SCCM_RX ((ushort)0x0001)
445
446/* The SCC PSMR when used as a UART.
447*/
448#define SCU_PSMR_FLC ((ushort)0x8000)
449#define SCU_PSMR_SL ((ushort)0x4000)
450#define SCU_PSMR_CL ((ushort)0x3000)
451#define SCU_PSMR_UM ((ushort)0x0c00)
452#define SCU_PSMR_FRZ ((ushort)0x0200)
453#define SCU_PSMR_RZS ((ushort)0x0100)
454#define SCU_PSMR_SYN ((ushort)0x0080)
455#define SCU_PSMR_DRT ((ushort)0x0040)
456#define SCU_PSMR_PEN ((ushort)0x0010)
457#define SCU_PSMR_RPM ((ushort)0x000c)
458#define SCU_PSMR_REVP ((ushort)0x0008)
459#define SCU_PSMR_TPM ((ushort)0x0003)
460#define SCU_PSMR_TEVP ((ushort)0x0002)
461
462/* CPM Transparent mode SCC.
463 */
464typedef struct scc_trans {
465 sccp_t st_genscc;
466 uint st_cpres; /* Preset CRC */
467 uint st_cmask; /* Constant mask for CRC */
468} scc_trans_t;
469
470/* How about some FCCs.....
471*/
472#define FCC_GFMR_DIAG_NORM ((uint)0x00000000)
473#define FCC_GFMR_DIAG_LE ((uint)0x40000000)
474#define FCC_GFMR_DIAG_AE ((uint)0x80000000)
475#define FCC_GFMR_DIAG_ALE ((uint)0xc0000000)
476#define FCC_GFMR_TCI ((uint)0x20000000)
477#define FCC_GFMR_TRX ((uint)0x10000000)
478#define FCC_GFMR_TTX ((uint)0x08000000)
479#define FCC_GFMR_TTX ((uint)0x08000000)
480#define FCC_GFMR_CDP ((uint)0x04000000)
481#define FCC_GFMR_CTSP ((uint)0x02000000)
482#define FCC_GFMR_CDS ((uint)0x01000000)
483#define FCC_GFMR_CTSS ((uint)0x00800000)
484#define FCC_GFMR_SYNL_NONE ((uint)0x00000000)
485#define FCC_GFMR_SYNL_AUTO ((uint)0x00004000)
486#define FCC_GFMR_SYNL_8 ((uint)0x00008000)
487#define FCC_GFMR_SYNL_16 ((uint)0x0000c000)
488#define FCC_GFMR_RTSM ((uint)0x00002000)
489#define FCC_GFMR_RENC_NRZ ((uint)0x00000000)
490#define FCC_GFMR_RENC_NRZI ((uint)0x00000800)
491#define FCC_GFMR_REVD ((uint)0x00000400)
492#define FCC_GFMR_TENC_NRZ ((uint)0x00000000)
493#define FCC_GFMR_TENC_NRZI ((uint)0x00000100)
494#define FCC_GFMR_TCRC_16 ((uint)0x00000000)
495#define FCC_GFMR_TCRC_32 ((uint)0x00000080)
496#define FCC_GFMR_ENR ((uint)0x00000020)
497#define FCC_GFMR_ENT ((uint)0x00000010)
498#define FCC_GFMR_MODE_ENET ((uint)0x0000000c)
499#define FCC_GFMR_MODE_ATM ((uint)0x0000000a)
500#define FCC_GFMR_MODE_HDLC ((uint)0x00000000)
501
502/* Generic FCC parameter ram.
503*/
504typedef struct fcc_param {
505 ushort fcc_riptr; /* Rx Internal temp pointer */
506 ushort fcc_tiptr; /* Tx Internal temp pointer */
507 ushort fcc_res1;
508 ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */
509 uint fcc_rstate; /* Upper byte is Func code, must be set */
510 uint fcc_rbase; /* Receive BD base */
511 ushort fcc_rbdstat; /* RxBD status */
512 ushort fcc_rbdlen; /* RxBD down counter */
513 uint fcc_rdptr; /* RxBD internal data pointer */
514 uint fcc_tstate; /* Upper byte is Func code, must be set */
515 uint fcc_tbase; /* Transmit BD base */
516 ushort fcc_tbdstat; /* TxBD status */
517 ushort fcc_tbdlen; /* TxBD down counter */
518 uint fcc_tdptr; /* TxBD internal data pointer */
519 uint fcc_rbptr; /* Rx BD Internal buf pointer */
520 uint fcc_tbptr; /* Tx BD Internal buf pointer */
521 uint fcc_rcrc; /* Rx temp CRC */
522 uint fcc_res2;
523 uint fcc_tcrc; /* Tx temp CRC */
524} fccp_t;
525
526
527/* Ethernet controller through FCC.
528*/
529typedef struct fcc_enet {
530 fccp_t fen_genfcc;
531 uint fen_statbuf; /* Internal status buffer */
532 uint fen_camptr; /* CAM address */
533 uint fen_cmask; /* Constant mask for CRC */
534 uint fen_cpres; /* Preset CRC */
535 uint fen_crcec; /* CRC Error counter */
536 uint fen_alec; /* alignment error counter */
537 uint fen_disfc; /* discard frame counter */
538 ushort fen_retlim; /* Retry limit */
539 ushort fen_retcnt; /* Retry counter */
540 ushort fen_pper; /* Persistence */
541 ushort fen_boffcnt; /* backoff counter */
542 uint fen_gaddrh; /* Group address filter, high 32-bits */
543 uint fen_gaddrl; /* Group address filter, low 32-bits */
544 ushort fen_tfcstat; /* out of sequence TxBD */
545 ushort fen_tfclen;
546 uint fen_tfcptr;
547 ushort fen_mflr; /* Maximum frame length (1518) */
548 ushort fen_paddrh; /* MAC address */
549 ushort fen_paddrm;
550 ushort fen_paddrl;
551 ushort fen_ibdcount; /* Internal BD counter */
552 ushort fen_ibdstart; /* Internal BD start pointer */
553 ushort fen_ibdend; /* Internal BD end pointer */
554 ushort fen_txlen; /* Internal Tx frame length counter */
555 uint fen_ibdbase[8]; /* Internal use */
556 uint fen_iaddrh; /* Individual address filter */
557 uint fen_iaddrl;
558 ushort fen_minflr; /* Minimum frame length (64) */
559 ushort fen_taddrh; /* Filter transfer MAC address */
560 ushort fen_taddrm;
561 ushort fen_taddrl;
562 ushort fen_padptr; /* Pointer to pad byte buffer */
563 ushort fen_cftype; /* control frame type */
564 ushort fen_cfrange; /* control frame range */
565 ushort fen_maxb; /* maximum BD count */
566 ushort fen_maxd1; /* Max DMA1 length (1520) */
567 ushort fen_maxd2; /* Max DMA2 length (1520) */
568 ushort fen_maxd; /* internal max DMA count */
569 ushort fen_dmacnt; /* internal DMA counter */
570 uint fen_octc; /* Total octect counter */
571 uint fen_colc; /* Total collision counter */
572 uint fen_broc; /* Total broadcast packet counter */
573 uint fen_mulc; /* Total multicast packet count */
574 uint fen_uspc; /* Total packets < 64 bytes */
575 uint fen_frgc; /* Total packets < 64 bytes with errors */
576 uint fen_ospc; /* Total packets > 1518 */
577 uint fen_jbrc; /* Total packets > 1518 with errors */
578 uint fen_p64c; /* Total packets == 64 bytes */
579 uint fen_p65c; /* Total packets 64 < bytes <= 127 */
580 uint fen_p128c; /* Total packets 127 < bytes <= 255 */
581 uint fen_p256c; /* Total packets 256 < bytes <= 511 */
582 uint fen_p512c; /* Total packets 512 < bytes <= 1023 */
583 uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */
584 uint fen_cambuf; /* Internal CAM buffer poiner */
585 ushort fen_rfthr; /* Received frames threshold */
586 ushort fen_rfcnt; /* Received frames count */
587} fcc_enet_t;
588
589/* FCC Event/Mask register as used by Ethernet.
590*/
591#define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
592#define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */
593#define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */
594#define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */
595#define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */
596#define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */
597#define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
598#define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */
599
600/* FCC Mode Register (FPSMR) as used by Ethernet.
601*/
602#define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */
603#define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */
604#define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */
605#define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */
606#define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */
607#define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */
608#define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */
609#define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */
610#define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */
611#define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */
612#define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */
613#define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */
614#define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */
615
616/* IIC parameter RAM.
617*/
618typedef struct iic {
619 ushort iic_rbase; /* Rx Buffer descriptor base address */
620 ushort iic_tbase; /* Tx Buffer descriptor base address */
621 u_char iic_rfcr; /* Rx function code */
622 u_char iic_tfcr; /* Tx function code */
623 ushort iic_mrblr; /* Max receive buffer length */
624 uint iic_rstate; /* Internal */
625 uint iic_rdp; /* Internal */
626 ushort iic_rbptr; /* Internal */
627 ushort iic_rbc; /* Internal */
628 uint iic_rxtmp; /* Internal */
629 uint iic_tstate; /* Internal */
630 uint iic_tdp; /* Internal */
631 ushort iic_tbptr; /* Internal */
632 ushort iic_tbc; /* Internal */
633 uint iic_txtmp; /* Internal */
634} iic_t;
635
636/* SPI parameter RAM.
637*/
638typedef struct spi {
639 ushort spi_rbase; /* Rx Buffer descriptor base address */
640 ushort spi_tbase; /* Tx Buffer descriptor base address */
641 u_char spi_rfcr; /* Rx function code */
642 u_char spi_tfcr; /* Tx function code */
643 ushort spi_mrblr; /* Max receive buffer length */
644 uint spi_rstate; /* Internal */
645 uint spi_rdp; /* Internal */
646 ushort spi_rbptr; /* Internal */
647 ushort spi_rbc; /* Internal */
648 uint spi_rxtmp; /* Internal */
649 uint spi_tstate; /* Internal */
650 uint spi_tdp; /* Internal */
651 ushort spi_tbptr; /* Internal */
652 ushort spi_tbc; /* Internal */
653 uint spi_txtmp; /* Internal */
654 uint spi_res; /* Tx temp. */
655 uint spi_res1[4]; /* SDMA temp. */
656} spi_t;
657
658/* SPI Mode register.
659*/
660#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
661#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
662#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
663#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
664#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
665#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
666#define SPMODE_EN ((ushort)0x0100) /* Enable */
667#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
668#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
669
670#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
671#define SPMODE_PM(x) ((x) &0xF)
672
673#define SPI_EB ((u_char)0x10) /* big endian byte order */
674
675/* IDMA parameter RAM
676*/
677typedef struct idma {
678 ushort ibase; /* IDMA buffer descriptor table base address */
679 ushort dcm; /* DMA channel mode */
680 ushort ibdptr; /* IDMA current buffer descriptor pointer */
681 ushort dpr_buf; /* IDMA transfer buffer base address */
682 ushort buf_inv; /* internal buffer inventory */
683 ushort ss_max; /* steady-state maximum transfer size */
684 ushort dpr_in_ptr; /* write pointer inside the internal buffer */
685 ushort sts; /* source transfer size */
686 ushort dpr_out_ptr; /* read pointer inside the internal buffer */
687 ushort seob; /* source end of burst */
688 ushort deob; /* destination end of burst */
689 ushort dts; /* destination transfer size */
690 ushort ret_add; /* return address when working in ERM=1 mode */
691 ushort res0; /* reserved */
692 uint bd_cnt; /* internal byte count */
693 uint s_ptr; /* source internal data pointer */
694 uint d_ptr; /* destination internal data pointer */
695 uint istate; /* internal state */
696 u_char res1[20]; /* pad to 64-byte length */
697} idma_t;
698
699/* DMA channel mode bit fields
700*/
701#define IDMA_DCM_FB ((ushort)0x8000) /* fly-by mode */
702#define IDMA_DCM_LP ((ushort)0x4000) /* low priority */
703#define IDMA_DCM_TC2 ((ushort)0x0400) /* value driven on TC[2] */
704#define IDMA_DCM_DMA_WRAP_MASK ((ushort)0x01c0) /* mask for DMA wrap */
705#define IDMA_DCM_DMA_WRAP_64 ((ushort)0x0000) /* 64-byte DMA xfer buffer */
706#define IDMA_DCM_DMA_WRAP_128 ((ushort)0x0040) /* 128-byte DMA xfer buffer */
707#define IDMA_DCM_DMA_WRAP_256 ((ushort)0x0080) /* 256-byte DMA xfer buffer */
708#define IDMA_DCM_DMA_WRAP_512 ((ushort)0x00c0) /* 512-byte DMA xfer buffer */
709#define IDMA_DCM_DMA_WRAP_1024 ((ushort)0x0100) /* 1024-byte DMA xfer buffer */
710#define IDMA_DCM_DMA_WRAP_2048 ((ushort)0x0140) /* 2048-byte DMA xfer buffer */
711#define IDMA_DCM_SINC ((ushort)0x0020) /* source inc addr */
712#define IDMA_DCM_DINC ((ushort)0x0010) /* destination inc addr */
713#define IDMA_DCM_ERM ((ushort)0x0008) /* external request mode */
714#define IDMA_DCM_DT ((ushort)0x0004) /* DONE treatment */
715#define IDMA_DCM_SD_MASK ((ushort)0x0003) /* mask for SD bit field */
716#define IDMA_DCM_SD_MEM2MEM ((ushort)0x0000) /* memory-to-memory xfer */
717#define IDMA_DCM_SD_PER2MEM ((ushort)0x0002) /* peripheral-to-memory xfer */
718#define IDMA_DCM_SD_MEM2PER ((ushort)0x0001) /* memory-to-peripheral xfer */
719
720/* IDMA Buffer Descriptors
721*/
722typedef struct idma_bd {
723 uint flags;
724 uint len; /* data length */
725 uint src; /* source data buffer pointer */
726 uint dst; /* destination data buffer pointer */
727} idma_bd_t;
728
729/* IDMA buffer descriptor flag bit fields
730*/
731#define IDMA_BD_V ((uint)0x80000000) /* valid */
732#define IDMA_BD_W ((uint)0x20000000) /* wrap */
733#define IDMA_BD_I ((uint)0x10000000) /* interrupt */
734#define IDMA_BD_L ((uint)0x08000000) /* last */
735#define IDMA_BD_CM ((uint)0x02000000) /* continuous mode */
736#define IDMA_BD_SDN ((uint)0x00400000) /* source done */
737#define IDMA_BD_DDN ((uint)0x00200000) /* destination done */
738#define IDMA_BD_DGBL ((uint)0x00100000) /* destination global */
739#define IDMA_BD_DBO_LE ((uint)0x00040000) /* little-end dest byte order */
740#define IDMA_BD_DBO_BE ((uint)0x00080000) /* big-end dest byte order */
741#define IDMA_BD_DDTB ((uint)0x00010000) /* destination data bus */
742#define IDMA_BD_SGBL ((uint)0x00002000) /* source global */
743#define IDMA_BD_SBO_LE ((uint)0x00000800) /* little-end src byte order */
744#define IDMA_BD_SBO_BE ((uint)0x00001000) /* big-end src byte order */
745#define IDMA_BD_SDTB ((uint)0x00000200) /* source data bus */
746
747/* per-channel IDMA registers
748*/
749typedef struct im_idma {
750 u_char idsr; /* IDMAn event status register */
751 u_char res0[3];
752 u_char idmr; /* IDMAn event mask register */
753 u_char res1[3];
754} im_idma_t;
755
756/* IDMA event register bit fields
757*/
758#define IDMA_EVENT_SC ((unsigned char)0x08) /* stop completed */
759#define IDMA_EVENT_OB ((unsigned char)0x04) /* out of buffers */
760#define IDMA_EVENT_EDN ((unsigned char)0x02) /* external DONE asserted */
761#define IDMA_EVENT_BC ((unsigned char)0x01) /* buffer descriptor complete */
762
763/* RISC Controller Configuration Register (RCCR) bit fields
764*/
765#define RCCR_TIME ((uint)0x80000000) /* timer enable */
766#define RCCR_TIMEP_MASK ((uint)0x3f000000) /* mask for timer period bit field */
767#define RCCR_DR0M ((uint)0x00800000) /* IDMA0 request mode */
768#define RCCR_DR1M ((uint)0x00400000) /* IDMA1 request mode */
769#define RCCR_DR2M ((uint)0x00000080) /* IDMA2 request mode */
770#define RCCR_DR3M ((uint)0x00000040) /* IDMA3 request mode */
771#define RCCR_DR0QP_MASK ((uint)0x00300000) /* mask for IDMA0 req priority */
772#define RCCR_DR0QP_HIGH ((uint)0x00000000) /* IDMA0 has high req priority */
773#define RCCR_DR0QP_MED ((uint)0x00100000) /* IDMA0 has medium req priority */
774#define RCCR_DR0QP_LOW ((uint)0x00200000) /* IDMA0 has low req priority */
775#define RCCR_DR1QP_MASK ((uint)0x00030000) /* mask for IDMA1 req priority */
776#define RCCR_DR1QP_HIGH ((uint)0x00000000) /* IDMA1 has high req priority */
777#define RCCR_DR1QP_MED ((uint)0x00010000) /* IDMA1 has medium req priority */
778#define RCCR_DR1QP_LOW ((uint)0x00020000) /* IDMA1 has low req priority */
779#define RCCR_DR2QP_MASK ((uint)0x00000030) /* mask for IDMA2 req priority */
780#define RCCR_DR2QP_HIGH ((uint)0x00000000) /* IDMA2 has high req priority */
781#define RCCR_DR2QP_MED ((uint)0x00000010) /* IDMA2 has medium req priority */
782#define RCCR_DR2QP_LOW ((uint)0x00000020) /* IDMA2 has low req priority */
783#define RCCR_DR3QP_MASK ((uint)0x00000003) /* mask for IDMA3 req priority */
784#define RCCR_DR3QP_HIGH ((uint)0x00000000) /* IDMA3 has high req priority */
785#define RCCR_DR3QP_MED ((uint)0x00000001) /* IDMA3 has medium req priority */
786#define RCCR_DR3QP_LOW ((uint)0x00000002) /* IDMA3 has low req priority */
787#define RCCR_EIE ((uint)0x00080000) /* external interrupt enable */
788#define RCCR_SCD ((uint)0x00040000) /* scheduler configuration */
789#define RCCR_ERAM_MASK ((uint)0x0000e000) /* mask for enable RAM microcode */
790#define RCCR_ERAM_0KB ((uint)0x00000000) /* use 0KB of dpram for microcode */
791#define RCCR_ERAM_2KB ((uint)0x00002000) /* use 2KB of dpram for microcode */
792#define RCCR_ERAM_4KB ((uint)0x00004000) /* use 4KB of dpram for microcode */
793#define RCCR_ERAM_6KB ((uint)0x00006000) /* use 6KB of dpram for microcode */
794#define RCCR_ERAM_8KB ((uint)0x00008000) /* use 8KB of dpram for microcode */
795#define RCCR_ERAM_10KB ((uint)0x0000a000) /* use 10KB of dpram for microcode */
796#define RCCR_ERAM_12KB ((uint)0x0000c000) /* use 12KB of dpram for microcode */
797#define RCCR_EDM0 ((uint)0x00000800) /* DREQ0 edge detect mode */
798#define RCCR_EDM1 ((uint)0x00000400) /* DREQ1 edge detect mode */
799#define RCCR_EDM2 ((uint)0x00000200) /* DREQ2 edge detect mode */
800#define RCCR_EDM3 ((uint)0x00000100) /* DREQ3 edge detect mode */
801#define RCCR_DEM01 ((uint)0x00000008) /* DONE0/DONE1 edge detect mode */
802#define RCCR_DEM23 ((uint)0x00000004) /* DONE2/DONE3 edge detect mode */
803
804/*-----------------------------------------------------------------------
805 * CMXFCR - CMX FCC Clock Route Register
806 */
807#define CMXFCR_FC1 0x40000000 /* FCC1 connection */
808#define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */
809#define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */
810#define CMXFCR_FC2 0x00400000 /* FCC2 connection */
811#define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */
812#define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */
813#define CMXFCR_FC3 0x00004000 /* FCC3 connection */
814#define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */
815#define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */
816
817#define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */
818#define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */
819#define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */
820#define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */
821#define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */
822#define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */
823#define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */
824#define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */
825
826#define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */
827#define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */
828#define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */
829#define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */
830#define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */
831#define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */
832#define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */
833#define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */
834
835#define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */
836#define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */
837#define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */
838#define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */
839#define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */
840#define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */
841#define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */
842#define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */
843
844#define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */
845#define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */
846#define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */
847#define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */
848#define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */
849#define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */
850#define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */
851#define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */
852
853#define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */
854#define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */
855#define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */
856#define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */
857#define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */
858#define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */
859#define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */
860#define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */
861
862#define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */
863#define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */
864#define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */
865#define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */
866#define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */
867#define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */
868#define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */
869#define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */
870
871/*-----------------------------------------------------------------------
872 * CMXSCR - CMX SCC Clock Route Register
873 */
874#define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */
875#define CMXSCR_SC1 0x40000000 /* SCC1 connection */
876#define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */
877#define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */
878#define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */
879#define CMXSCR_SC2 0x00400000 /* SCC2 connection */
880#define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */
881#define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */
882#define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */
883#define CMXSCR_SC3 0x00004000 /* SCC3 connection */
884#define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */
885#define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */
886#define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */
887#define CMXSCR_SC4 0x00000040 /* SCC4 connection */
888#define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */
889#define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */
890
891#define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */
892#define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */
893#define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */
894#define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */
895#define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */
896#define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */
897#define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */
898#define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */
899
900#define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */
901#define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */
902#define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */
903#define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */
904#define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */
905#define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */
906#define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */
907#define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */
908
909#define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */
910#define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */
911#define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */
912#define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */
913#define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */
914#define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */
915#define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */
916#define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */
917
918#define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */
919#define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */
920#define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */
921#define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */
922#define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */
923#define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */
924#define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */
925#define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */
926
927#define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */
928#define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */
929#define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */
930#define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */
931#define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */
932#define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */
933#define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */
934#define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */
935
936#define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */
937#define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */
938#define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */
939#define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */
940#define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */
941#define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */
942#define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */
943#define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */
944
945#define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */
946#define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */
947#define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */
948#define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */
949#define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */
950#define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */
951#define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */
952#define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */
953
954#define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */
955#define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */
956#define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */
957#define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */
958#define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */
959#define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */
960#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */
961#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */
962
963/*-----------------------------------------------------------------------
964 * SIUMCR - SIU Module Configuration Register 4-31
965 */
966#define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */
967#define SIUMCR_ESE 0x40000000 /* External Snoop Enable */
968#define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */
969#define SIUMCR_CDIS 0x10000000 /* Core Disable */
970#define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/
971#define SIUMCR_DPPC01 0x04000000 /* - " - */
972#define SIUMCR_DPPC10 0x08000000 /* - " - */
973#define SIUMCR_DPPC11 0x0c000000 /* - " - */
974#define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */
975#define SIUMCR_L2CPC01 0x01000000 /* - " - */
976#define SIUMCR_L2CPC10 0x02000000 /* - " - */
977#define SIUMCR_L2CPC11 0x03000000 /* - " - */
978#define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */
979#define SIUMCR_LBPC01 0x00400000 /* - " - */
980#define SIUMCR_LBPC10 0x00800000 /* - " - */
981#define SIUMCR_LBPC11 0x00c00000 /* - " - */
982#define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/
983#define SIUMCR_APPC01 0x00100000 /* - " - */
984#define SIUMCR_APPC10 0x00200000 /* - " - */
985#define SIUMCR_APPC11 0x00300000 /* - " - */
986#define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */
987#define SIUMCR_CS10PC01 0x00040000 /* - " - */
988#define SIUMCR_CS10PC10 0x00080000 /* - " - */
989#define SIUMCR_CS10PC11 0x000c0000 /* - " - */
990#define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */
991#define SIUMCR_BCTLC01 0x00010000 /* - " - */
992#define SIUMCR_BCTLC10 0x00020000 /* - " - */
993#define SIUMCR_BCTLC11 0x00030000 /* - " - */
994#define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */
995#define SIUMCR_MMR01 0x00004000 /* - " - */
996#define SIUMCR_MMR10 0x00008000 /* - " - */
997#define SIUMCR_MMR11 0x0000c000 /* - " - */
998#define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/
999
1000/*-----------------------------------------------------------------------
1001 * SCCR - System Clock Control Register 9-8
1002*/
1003#define SCCR_PCI_MODE 0x00000100 /* PCI Mode */
1004#define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */
1005#define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */
1006#define SCCR_PCIDF_SHIFT 3
1007
1008#ifndef CPM_IMMR_OFFSET
1009#define CPM_IMMR_OFFSET 0x101a8
1010#endif
1011
1012#define FCC_PSMR_RMII ((uint)0x00020000) /* Use RMII interface */
1013
1014/* FCC iop & clock configuration. BSP code is responsible to define Fx_RXCLK & Fx_TXCLK
1015 * in order to use clock-computing stuff below for the FCC x
1016 */
1017
1018/* Automatically generates register configurations */
1019#define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */
1020
1021#define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */
1022#define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */
1023#define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */
1024#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */
1025#define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */
1026#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */
1027
1028#define PC_F1RXCLK PC_CLK(F1_RXCLK)
1029#define PC_F1TXCLK PC_CLK(F1_TXCLK)
1030#define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK))
1031#define CMX1_CLK_MASK ((uint)0xff000000)
1032
1033#define PC_F2RXCLK PC_CLK(F2_RXCLK)
1034#define PC_F2TXCLK PC_CLK(F2_TXCLK)
1035#define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK))
1036#define CMX2_CLK_MASK ((uint)0x00ff0000)
1037
1038#define PC_F3RXCLK PC_CLK(F3_RXCLK)
1039#define PC_F3TXCLK PC_CLK(F3_TXCLK)
1040#define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK))
1041#define CMX3_CLK_MASK ((uint)0x0000ff00)
1042
1043#define CPMUX_CLK_MASK (CMX3_CLK_MASK | CMX2_CLK_MASK)
1044#define CPMUX_CLK_ROUTE (CMX3_CLK_ROUTE | CMX2_CLK_ROUTE)
1045
1046#define CLK_TRX (PC_F3TXCLK | PC_F3RXCLK | PC_F2TXCLK | PC_F2RXCLK)
1047
1048/* I/O Pin assignment for FCC1. I don't yet know the best way to do this,
1049 * but there is little variation among the choices.
1050 */
1051#define PA1_COL 0x00000001U
1052#define PA1_CRS 0x00000002U
1053#define PA1_TXER 0x00000004U
1054#define PA1_TXEN 0x00000008U
1055#define PA1_RXDV 0x00000010U
1056#define PA1_RXER 0x00000020U
1057#define PA1_TXDAT 0x00003c00U
1058#define PA1_RXDAT 0x0003c000U
1059#define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT)
1060#define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \
1061 PA1_RXDV | PA1_RXER)
1062#define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV)
1063#define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER)
1064
1065
1066/* I/O Pin assignment for FCC2. I don't yet know the best way to do this,
1067 * but there is little variation among the choices.
1068 */
1069#define PB2_TXER 0x00000001U
1070#define PB2_RXDV 0x00000002U
1071#define PB2_TXEN 0x00000004U
1072#define PB2_RXER 0x00000008U
1073#define PB2_COL 0x00000010U
1074#define PB2_CRS 0x00000020U
1075#define PB2_TXDAT 0x000003c0U
1076#define PB2_RXDAT 0x00003c00U
1077#define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
1078 PB2_RXER | PB2_RXDV | PB2_TXER)
1079#define PB2_PSORB1 (PB2_TXEN)
1080#define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
1081#define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER)
1082
1083
1084/* I/O Pin assignment for FCC3. I don't yet know the best way to do this,
1085 * but there is little variation among the choices.
1086 */
1087#define PB3_RXDV 0x00004000U
1088#define PB3_RXER 0x00008000U
1089#define PB3_TXER 0x00010000U
1090#define PB3_TXEN 0x00020000U
1091#define PB3_COL 0x00040000U
1092#define PB3_CRS 0x00080000U
1093#define PB3_TXDAT 0x0f000000U
1094#define PC3_TXDAT 0x00000010U
1095#define PB3_RXDAT 0x00f00000U
1096#define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
1097 PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
1098#define PB3_PSORB1 0
1099#define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
1100#define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER)
1101#define PC3_DIRC1 (PC3_TXDAT)
1102
1103/* Handy macro to specify mem for FCCs*/
1104#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128))
1105#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0)
1106#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1)
1107#define FCC3_MEM_OFFSET FCC_MEM_OFFSET(2)
1108
1109/* Clocks and GRG's */
1110
1111enum cpm_clk_dir {
1112 CPM_CLK_RX,
1113 CPM_CLK_TX,
1114 CPM_CLK_RTX
1115};
1116
1117enum cpm_clk_target {
1118 CPM_CLK_SCC1,
1119 CPM_CLK_SCC2,
1120 CPM_CLK_SCC3,
1121 CPM_CLK_SCC4,
1122 CPM_CLK_FCC1,
1123 CPM_CLK_FCC2,
1124 CPM_CLK_FCC3,
1125 CPM_CLK_SMC1,
1126 CPM_CLK_SMC2,
1127};
1128
1129enum cpm_clk {
1130 CPM_CLK_NONE = 0,
1131 CPM_BRG1, /* Baud Rate Generator 1 */
1132 CPM_BRG2, /* Baud Rate Generator 2 */
1133 CPM_BRG3, /* Baud Rate Generator 3 */
1134 CPM_BRG4, /* Baud Rate Generator 4 */
1135 CPM_BRG5, /* Baud Rate Generator 5 */
1136 CPM_BRG6, /* Baud Rate Generator 6 */
1137 CPM_BRG7, /* Baud Rate Generator 7 */
1138 CPM_BRG8, /* Baud Rate Generator 8 */
1139 CPM_CLK1, /* Clock 1 */
1140 CPM_CLK2, /* Clock 2 */
1141 CPM_CLK3, /* Clock 3 */
1142 CPM_CLK4, /* Clock 4 */
1143 CPM_CLK5, /* Clock 5 */
1144 CPM_CLK6, /* Clock 6 */
1145 CPM_CLK7, /* Clock 7 */
1146 CPM_CLK8, /* Clock 8 */
1147 CPM_CLK9, /* Clock 9 */
1148 CPM_CLK10, /* Clock 10 */
1149 CPM_CLK11, /* Clock 11 */
1150 CPM_CLK12, /* Clock 12 */
1151 CPM_CLK13, /* Clock 13 */
1152 CPM_CLK14, /* Clock 14 */
1153 CPM_CLK15, /* Clock 15 */
1154 CPM_CLK16, /* Clock 16 */
1155 CPM_CLK17, /* Clock 17 */
1156 CPM_CLK18, /* Clock 18 */
1157 CPM_CLK19, /* Clock 19 */
1158 CPM_CLK20, /* Clock 20 */
1159 CPM_CLK_DUMMY
1160};
1161
1162extern int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode);
1163extern int cpm2_smc_clk_setup(enum cpm_clk_target target, int clock);
1164
1165#define CPM_PIN_INPUT 0
1166#define CPM_PIN_OUTPUT 1
1167#define CPM_PIN_PRIMARY 0
1168#define CPM_PIN_SECONDARY 2
1169#define CPM_PIN_GPIO 4
1170#define CPM_PIN_OPENDRAIN 8
1171
1172void cpm2_set_pin(int port, int pin, int flags);
1173
1174#endif /* __CPM2__ */
1175#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h
deleted file mode 100644
index ef8a248dfd5..00000000000
--- a/include/asm-powerpc/cputable.h
+++ /dev/null
@@ -1,514 +0,0 @@
1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
4#define PPC_FEATURE_32 0x80000000
5#define PPC_FEATURE_64 0x40000000
6#define PPC_FEATURE_601_INSTR 0x20000000
7#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
8#define PPC_FEATURE_HAS_FPU 0x08000000
9#define PPC_FEATURE_HAS_MMU 0x04000000
10#define PPC_FEATURE_HAS_4xxMAC 0x02000000
11#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
12#define PPC_FEATURE_HAS_SPE 0x00800000
13#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
14#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
15#define PPC_FEATURE_NO_TB 0x00100000
16#define PPC_FEATURE_POWER4 0x00080000
17#define PPC_FEATURE_POWER5 0x00040000
18#define PPC_FEATURE_POWER5_PLUS 0x00020000
19#define PPC_FEATURE_CELL 0x00010000
20#define PPC_FEATURE_BOOKE 0x00008000
21#define PPC_FEATURE_SMT 0x00004000
22#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
23#define PPC_FEATURE_ARCH_2_05 0x00001000
24#define PPC_FEATURE_PA6T 0x00000800
25#define PPC_FEATURE_HAS_DFP 0x00000400
26#define PPC_FEATURE_POWER6_EXT 0x00000200
27#define PPC_FEATURE_ARCH_2_06 0x00000100
28#define PPC_FEATURE_HAS_VSX 0x00000080
29
30#define PPC_FEATURE_PSERIES_PERFMON_COMPAT \
31 0x00000040
32
33#define PPC_FEATURE_TRUE_LE 0x00000002
34#define PPC_FEATURE_PPC_LE 0x00000001
35
36#ifdef __KERNEL__
37
38#include <asm/asm-compat.h>
39#include <asm/feature-fixups.h>
40
41#ifndef __ASSEMBLY__
42
43/* This structure can grow, it's real size is used by head.S code
44 * via the mkdefs mechanism.
45 */
46struct cpu_spec;
47
48typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
49typedef void (*cpu_restore_t)(void);
50
51enum powerpc_oprofile_type {
52 PPC_OPROFILE_INVALID = 0,
53 PPC_OPROFILE_RS64 = 1,
54 PPC_OPROFILE_POWER4 = 2,
55 PPC_OPROFILE_G4 = 3,
56 PPC_OPROFILE_FSL_EMB = 4,
57 PPC_OPROFILE_CELL = 5,
58 PPC_OPROFILE_PA6T = 6,
59};
60
61enum powerpc_pmc_type {
62 PPC_PMC_DEFAULT = 0,
63 PPC_PMC_IBM = 1,
64 PPC_PMC_PA6T = 2,
65};
66
67struct pt_regs;
68
69extern int machine_check_generic(struct pt_regs *regs);
70extern int machine_check_4xx(struct pt_regs *regs);
71extern int machine_check_440A(struct pt_regs *regs);
72extern int machine_check_e500(struct pt_regs *regs);
73extern int machine_check_e200(struct pt_regs *regs);
74
75/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
76struct cpu_spec {
77 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
78 unsigned int pvr_mask;
79 unsigned int pvr_value;
80
81 char *cpu_name;
82 unsigned long cpu_features; /* Kernel features */
83 unsigned int cpu_user_features; /* Userland features */
84
85 /* cache line sizes */
86 unsigned int icache_bsize;
87 unsigned int dcache_bsize;
88
89 /* number of performance monitor counters */
90 unsigned int num_pmcs;
91 enum powerpc_pmc_type pmc_type;
92
93 /* this is called to initialize various CPU bits like L1 cache,
94 * BHT, SPD, etc... from head.S before branching to identify_machine
95 */
96 cpu_setup_t cpu_setup;
97 /* Used to restore cpu setup on secondary processors and at resume */
98 cpu_restore_t cpu_restore;
99
100 /* Used by oprofile userspace to select the right counters */
101 char *oprofile_cpu_type;
102
103 /* Processor specific oprofile operations */
104 enum powerpc_oprofile_type oprofile_type;
105
106 /* Bit locations inside the mmcra change */
107 unsigned long oprofile_mmcra_sihv;
108 unsigned long oprofile_mmcra_sipr;
109
110 /* Bits to clear during an oprofile exception */
111 unsigned long oprofile_mmcra_clear;
112
113 /* Name of processor class, for the ELF AT_PLATFORM entry */
114 char *platform;
115
116 /* Processor specific machine check handling. Return negative
117 * if the error is fatal, 1 if it was fully recovered and 0 to
118 * pass up (not CPU originated) */
119 int (*machine_check)(struct pt_regs *regs);
120};
121
122extern struct cpu_spec *cur_cpu_spec;
123
124extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
125
126extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
127extern void do_feature_fixups(unsigned long value, void *fixup_start,
128 void *fixup_end);
129
130extern const char *powerpc_base_platform;
131
132#endif /* __ASSEMBLY__ */
133
134/* CPU kernel features */
135
136/* Retain the 32b definitions all use bottom half of word */
137#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000000000000001)
138#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
139#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
140#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
141#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
142#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
143#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
144#define CPU_FTR_L2CSR ASM_CONST(0x0000000000000080)
145#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
146#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
147#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
148#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
149#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
150#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
151#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
152#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
153#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
154#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
155#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
156#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
157#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
158#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
159#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
160#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000)
161#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000)
162#define CPU_FTR_SPE ASM_CONST(0x0000000002000000)
163#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x0000000004000000)
164#define CPU_FTR_LWSYNC ASM_CONST(0x0000000008000000)
165
166/*
167 * Add the 64-bit processor unique features in the top half of the word;
168 * on 32-bit, make the names available but defined to be 0.
169 */
170#ifdef __powerpc64__
171#define LONG_ASM_CONST(x) ASM_CONST(x)
172#else
173#define LONG_ASM_CONST(x) 0
174#endif
175
176#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
177#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
178#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
179#define CPU_FTR_NOEXECUTE LONG_ASM_CONST(0x0000000800000000)
180#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
181#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
182#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
183#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
184#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
185#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
186#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
187#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
188#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
189#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
190#define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000)
191#define CPU_FTR_1T_SEGMENT LONG_ASM_CONST(0x0004000000000000)
192#define CPU_FTR_NO_SLBIE_B LONG_ASM_CONST(0x0008000000000000)
193#define CPU_FTR_VSX LONG_ASM_CONST(0x0010000000000000)
194#define CPU_FTR_SAO LONG_ASM_CONST(0x0020000000000000)
195
196#ifndef __ASSEMBLY__
197
198#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_SLB | \
199 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
200 CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
201
202/* We only set the altivec features if the kernel was compiled with altivec
203 * support
204 */
205#ifdef CONFIG_ALTIVEC
206#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
207#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
208#else
209#define CPU_FTR_ALTIVEC_COMP 0
210#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
211#endif
212
213/* We only set the VSX features if the kernel was compiled with VSX
214 * support
215 */
216#ifdef CONFIG_VSX
217#define CPU_FTR_VSX_COMP CPU_FTR_VSX
218#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
219#else
220#define CPU_FTR_VSX_COMP 0
221#define PPC_FEATURE_HAS_VSX_COMP 0
222#endif
223
224/* We only set the spe features if the kernel was compiled with spe
225 * support
226 */
227#ifdef CONFIG_SPE
228#define CPU_FTR_SPE_COMP CPU_FTR_SPE
229#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
230#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
231#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
232#else
233#define CPU_FTR_SPE_COMP 0
234#define PPC_FEATURE_HAS_SPE_COMP 0
235#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
236#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
237#endif
238
239/* We need to mark all pages as being coherent if we're SMP or we have a
240 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
241 * require it for PCI "streaming/prefetch" to work properly.
242 */
243#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
244 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260)
245#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
246#else
247#define CPU_FTR_COMMON 0
248#endif
249
250/* The powersave features NAP & DOZE seems to confuse BDI when
251 debugging. So if a BDI is used, disable theses
252 */
253#ifndef CONFIG_BDI_SWITCH
254#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
255#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
256#else
257#define CPU_FTR_MAYBE_CAN_DOZE 0
258#define CPU_FTR_MAYBE_CAN_NAP 0
259#endif
260
261#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
262 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
263 !defined(CONFIG_BOOKE))
264
265#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE | \
266 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
267#define CPU_FTRS_603 (CPU_FTR_COMMON | \
268 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
269 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
270#define CPU_FTRS_604 (CPU_FTR_COMMON | \
271 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_PPC_LE)
272#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
273 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
274 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
275#define CPU_FTRS_740 (CPU_FTR_COMMON | \
276 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
277 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
278 CPU_FTR_PPC_LE)
279#define CPU_FTRS_750 (CPU_FTR_COMMON | \
280 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
281 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
282 CPU_FTR_PPC_LE)
283#define CPU_FTRS_750CL (CPU_FTRS_750 | CPU_FTR_HAS_HIGH_BATS)
284#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
285#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
286#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | \
287 CPU_FTR_HAS_HIGH_BATS)
288#define CPU_FTRS_750GX (CPU_FTRS_750FX)
289#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
290 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
291 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
292 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
293#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
294 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
295 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
296 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
297#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
298 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
299 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
300 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
301#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
302 CPU_FTR_USE_TB | \
303 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
304 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
305 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
306 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
307#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
308 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
309 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
310 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
311 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
312#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
313 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
314 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
315 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
316 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
317#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
318 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
319 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
320 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
321 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
322 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
323#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
324 CPU_FTR_USE_TB | \
325 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
326 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
327 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
328 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
329#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
330 CPU_FTR_USE_TB | \
331 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
332 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
333 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
334 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
335 CPU_FTR_NEED_PAIRED_STWCX)
336#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
337 CPU_FTR_USE_TB | \
338 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
339 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
340 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
341 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
342#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
343 CPU_FTR_USE_TB | \
344 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
345 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
346 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
347 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
348#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
349 CPU_FTR_USE_TB | \
350 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
351 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
352 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
353 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
354#define CPU_FTRS_82XX (CPU_FTR_COMMON | \
355 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
356#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
357 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
358#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
359 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
360 CPU_FTR_COMMON)
361#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
362 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
363 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
364#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | \
365 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
366#define CPU_FTRS_8XX (CPU_FTR_USE_TB)
367#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
368#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
369#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
370 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
371 CPU_FTR_UNIFIED_ID_CACHE)
372#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
373 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN)
374#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
375 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | \
376 CPU_FTR_NODSISRALIGN)
377#define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
378 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN | \
379 CPU_FTR_L2CSR | CPU_FTR_LWSYNC)
380#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
381
382/* 64-bit CPUs */
383#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
384 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
385#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
386 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
387 CPU_FTR_MMCRA | CPU_FTR_CTRL)
388#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
389 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
390 CPU_FTR_MMCRA)
391#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
392 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
393 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
394#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
395 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
396 CPU_FTR_MMCRA | CPU_FTR_SMT | \
397 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
398 CPU_FTR_PURR)
399#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
400 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
401 CPU_FTR_MMCRA | CPU_FTR_SMT | \
402 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
403 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
404 CPU_FTR_DSCR)
405#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
406 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
407 CPU_FTR_MMCRA | CPU_FTR_SMT | \
408 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
409 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
410 CPU_FTR_DSCR | CPU_FTR_SAO)
411#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
412 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
413 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
414 CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG)
415#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
416 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
417 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
418 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
419#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | \
420 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
421
422#ifdef __powerpc64__
423#define CPU_FTRS_POSSIBLE \
424 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
425 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
426 CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
427 CPU_FTR_1T_SEGMENT | CPU_FTR_VSX)
428#else
429enum {
430 CPU_FTRS_POSSIBLE =
431#if CLASSIC_PPC
432 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
433 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
434 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
435 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
436 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
437 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
438 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
439 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
440 CPU_FTRS_CLASSIC32 |
441#else
442 CPU_FTRS_GENERIC_32 |
443#endif
444#ifdef CONFIG_8xx
445 CPU_FTRS_8XX |
446#endif
447#ifdef CONFIG_40x
448 CPU_FTRS_40X |
449#endif
450#ifdef CONFIG_44x
451 CPU_FTRS_44X |
452#endif
453#ifdef CONFIG_E200
454 CPU_FTRS_E200 |
455#endif
456#ifdef CONFIG_E500
457 CPU_FTRS_E500 | CPU_FTRS_E500_2 | CPU_FTRS_E500MC |
458#endif
459 0,
460};
461#endif /* __powerpc64__ */
462
463#ifdef __powerpc64__
464#define CPU_FTRS_ALWAYS \
465 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
466 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
467 CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
468#else
469enum {
470 CPU_FTRS_ALWAYS =
471#if CLASSIC_PPC
472 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
473 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
474 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
475 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
476 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
477 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
478 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
479 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
480 CPU_FTRS_CLASSIC32 &
481#else
482 CPU_FTRS_GENERIC_32 &
483#endif
484#ifdef CONFIG_8xx
485 CPU_FTRS_8XX &
486#endif
487#ifdef CONFIG_40x
488 CPU_FTRS_40X &
489#endif
490#ifdef CONFIG_44x
491 CPU_FTRS_44X &
492#endif
493#ifdef CONFIG_E200
494 CPU_FTRS_E200 &
495#endif
496#ifdef CONFIG_E500
497 CPU_FTRS_E500 & CPU_FTRS_E500_2 & CPU_FTRS_E500MC &
498#endif
499 CPU_FTRS_POSSIBLE,
500};
501#endif /* __powerpc64__ */
502
503static inline int cpu_has_feature(unsigned long feature)
504{
505 return (CPU_FTRS_ALWAYS & feature) ||
506 (CPU_FTRS_POSSIBLE
507 & cur_cpu_spec->cpu_features
508 & feature);
509}
510
511#endif /* !__ASSEMBLY__ */
512
513#endif /* __KERNEL__ */
514#endif /* __ASM_POWERPC_CPUTABLE_H */
diff --git a/include/asm-powerpc/cputhreads.h b/include/asm-powerpc/cputhreads.h
deleted file mode 100644
index fb11b0c459b..00000000000
--- a/include/asm-powerpc/cputhreads.h
+++ /dev/null
@@ -1,71 +0,0 @@
1#ifndef _ASM_POWERPC_CPUTHREADS_H
2#define _ASM_POWERPC_CPUTHREADS_H
3
4#include <linux/cpumask.h>
5
6/*
7 * Mapping of threads to cores
8 */
9
10#ifdef CONFIG_SMP
11extern int threads_per_core;
12extern int threads_shift;
13extern cpumask_t threads_core_mask;
14#else
15#define threads_per_core 1
16#define threads_shift 0
17#define threads_core_mask (CPU_MASK_CPU0)
18#endif
19
20/* cpu_thread_mask_to_cores - Return a cpumask of one per cores
21 * hit by the argument
22 *
23 * @threads: a cpumask of threads
24 *
25 * This function returns a cpumask which will have one "cpu" (or thread)
26 * bit set for each core that has at least one thread set in the argument.
27 *
28 * This can typically be used for things like IPI for tlb invalidations
29 * since those need to be done only once per core/TLB
30 */
31static inline cpumask_t cpu_thread_mask_to_cores(cpumask_t threads)
32{
33 cpumask_t tmp, res;
34 int i;
35
36 res = CPU_MASK_NONE;
37 for (i = 0; i < NR_CPUS; i += threads_per_core) {
38 cpus_shift_left(tmp, threads_core_mask, i);
39 if (cpus_intersects(threads, tmp))
40 cpu_set(i, res);
41 }
42 return res;
43}
44
45static inline int cpu_nr_cores(void)
46{
47 return NR_CPUS >> threads_shift;
48}
49
50static inline cpumask_t cpu_online_cores_map(void)
51{
52 return cpu_thread_mask_to_cores(cpu_online_map);
53}
54
55static inline int cpu_thread_to_core(int cpu)
56{
57 return cpu >> threads_shift;
58}
59
60static inline int cpu_thread_in_core(int cpu)
61{
62 return cpu & (threads_per_core - 1);
63}
64
65static inline int cpu_first_thread_in_core(int cpu)
66{
67 return cpu & ~(threads_per_core - 1);
68}
69
70#endif /* _ASM_POWERPC_CPUTHREADS_H */
71
diff --git a/include/asm-powerpc/cputime.h b/include/asm-powerpc/cputime.h
deleted file mode 100644
index f42e623030e..00000000000
--- a/include/asm-powerpc/cputime.h
+++ /dev/null
@@ -1,235 +0,0 @@
1/*
2 * Definitions for measuring cputime on powerpc machines.
3 *
4 * Copyright (C) 2006 Paul Mackerras, IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * If we have CONFIG_VIRT_CPU_ACCOUNTING, we measure cpu time in
12 * the same units as the timebase. Otherwise we measure cpu time
13 * in jiffies using the generic definitions.
14 */
15
16#ifndef __POWERPC_CPUTIME_H
17#define __POWERPC_CPUTIME_H
18
19#ifndef CONFIG_VIRT_CPU_ACCOUNTING
20#include <asm-generic/cputime.h>
21#else
22
23#include <linux/types.h>
24#include <linux/time.h>
25#include <asm/div64.h>
26#include <asm/time.h>
27#include <asm/param.h>
28
29typedef u64 cputime_t;
30typedef u64 cputime64_t;
31
32#define cputime_zero ((cputime_t)0)
33#define cputime_max ((~((cputime_t)0) >> 1) - 1)
34#define cputime_add(__a, __b) ((__a) + (__b))
35#define cputime_sub(__a, __b) ((__a) - (__b))
36#define cputime_div(__a, __n) ((__a) / (__n))
37#define cputime_halve(__a) ((__a) >> 1)
38#define cputime_eq(__a, __b) ((__a) == (__b))
39#define cputime_gt(__a, __b) ((__a) > (__b))
40#define cputime_ge(__a, __b) ((__a) >= (__b))
41#define cputime_lt(__a, __b) ((__a) < (__b))
42#define cputime_le(__a, __b) ((__a) <= (__b))
43
44#define cputime64_zero ((cputime64_t)0)
45#define cputime64_add(__a, __b) ((__a) + (__b))
46#define cputime64_sub(__a, __b) ((__a) - (__b))
47#define cputime_to_cputime64(__ct) (__ct)
48
49#ifdef __KERNEL__
50
51/*
52 * Convert cputime <-> jiffies
53 */
54extern u64 __cputime_jiffies_factor;
55DECLARE_PER_CPU(unsigned long, cputime_last_delta);
56DECLARE_PER_CPU(unsigned long, cputime_scaled_last_delta);
57
58static inline unsigned long cputime_to_jiffies(const cputime_t ct)
59{
60 return mulhdu(ct, __cputime_jiffies_factor);
61}
62
63/* Estimate the scaled cputime by scaling the real cputime based on
64 * the last scaled to real ratio */
65static inline cputime_t cputime_to_scaled(const cputime_t ct)
66{
67 if (cpu_has_feature(CPU_FTR_SPURR) &&
68 per_cpu(cputime_last_delta, smp_processor_id()))
69 return ct *
70 per_cpu(cputime_scaled_last_delta, smp_processor_id())/
71 per_cpu(cputime_last_delta, smp_processor_id());
72 return ct;
73}
74
75static inline cputime_t jiffies_to_cputime(const unsigned long jif)
76{
77 cputime_t ct;
78 unsigned long sec;
79
80 /* have to be a little careful about overflow */
81 ct = jif % HZ;
82 sec = jif / HZ;
83 if (ct) {
84 ct *= tb_ticks_per_sec;
85 do_div(ct, HZ);
86 }
87 if (sec)
88 ct += (cputime_t) sec * tb_ticks_per_sec;
89 return ct;
90}
91
92static inline cputime64_t jiffies64_to_cputime64(const u64 jif)
93{
94 cputime_t ct;
95 u64 sec;
96
97 /* have to be a little careful about overflow */
98 ct = jif % HZ;
99 sec = jif / HZ;
100 if (ct) {
101 ct *= tb_ticks_per_sec;
102 do_div(ct, HZ);
103 }
104 if (sec)
105 ct += (cputime_t) sec * tb_ticks_per_sec;
106 return ct;
107}
108
109static inline u64 cputime64_to_jiffies64(const cputime_t ct)
110{
111 return mulhdu(ct, __cputime_jiffies_factor);
112}
113
114/*
115 * Convert cputime <-> milliseconds
116 */
117extern u64 __cputime_msec_factor;
118
119static inline unsigned long cputime_to_msecs(const cputime_t ct)
120{
121 return mulhdu(ct, __cputime_msec_factor);
122}
123
124static inline cputime_t msecs_to_cputime(const unsigned long ms)
125{
126 cputime_t ct;
127 unsigned long sec;
128
129 /* have to be a little careful about overflow */
130 ct = ms % 1000;
131 sec = ms / 1000;
132 if (ct) {
133 ct *= tb_ticks_per_sec;
134 do_div(ct, 1000);
135 }
136 if (sec)
137 ct += (cputime_t) sec * tb_ticks_per_sec;
138 return ct;
139}
140
141/*
142 * Convert cputime <-> seconds
143 */
144extern u64 __cputime_sec_factor;
145
146static inline unsigned long cputime_to_secs(const cputime_t ct)
147{
148 return mulhdu(ct, __cputime_sec_factor);
149}
150
151static inline cputime_t secs_to_cputime(const unsigned long sec)
152{
153 return (cputime_t) sec * tb_ticks_per_sec;
154}
155
156/*
157 * Convert cputime <-> timespec
158 */
159static inline void cputime_to_timespec(const cputime_t ct, struct timespec *p)
160{
161 u64 x = ct;
162 unsigned int frac;
163
164 frac = do_div(x, tb_ticks_per_sec);
165 p->tv_sec = x;
166 x = (u64) frac * 1000000000;
167 do_div(x, tb_ticks_per_sec);
168 p->tv_nsec = x;
169}
170
171static inline cputime_t timespec_to_cputime(const struct timespec *p)
172{
173 cputime_t ct;
174
175 ct = (u64) p->tv_nsec * tb_ticks_per_sec;
176 do_div(ct, 1000000000);
177 return ct + (u64) p->tv_sec * tb_ticks_per_sec;
178}
179
180/*
181 * Convert cputime <-> timeval
182 */
183static inline void cputime_to_timeval(const cputime_t ct, struct timeval *p)
184{
185 u64 x = ct;
186 unsigned int frac;
187
188 frac = do_div(x, tb_ticks_per_sec);
189 p->tv_sec = x;
190 x = (u64) frac * 1000000;
191 do_div(x, tb_ticks_per_sec);
192 p->tv_usec = x;
193}
194
195static inline cputime_t timeval_to_cputime(const struct timeval *p)
196{
197 cputime_t ct;
198
199 ct = (u64) p->tv_usec * tb_ticks_per_sec;
200 do_div(ct, 1000000);
201 return ct + (u64) p->tv_sec * tb_ticks_per_sec;
202}
203
204/*
205 * Convert cputime <-> clock_t (units of 1/USER_HZ seconds)
206 */
207extern u64 __cputime_clockt_factor;
208
209static inline unsigned long cputime_to_clock_t(const cputime_t ct)
210{
211 return mulhdu(ct, __cputime_clockt_factor);
212}
213
214static inline cputime_t clock_t_to_cputime(const unsigned long clk)
215{
216 cputime_t ct;
217 unsigned long sec;
218
219 /* have to be a little careful about overflow */
220 ct = clk % USER_HZ;
221 sec = clk / USER_HZ;
222 if (ct) {
223 ct *= tb_ticks_per_sec;
224 do_div(ct, USER_HZ);
225 }
226 if (sec)
227 ct += (cputime_t) sec * tb_ticks_per_sec;
228 return ct;
229}
230
231#define cputime64_to_clock_t(ct) cputime_to_clock_t((cputime_t)(ct))
232
233#endif /* __KERNEL__ */
234#endif /* CONFIG_VIRT_CPU_ACCOUNTING */
235#endif /* __POWERPC_CPUTIME_H */
diff --git a/include/asm-powerpc/current.h b/include/asm-powerpc/current.h
deleted file mode 100644
index e2c7f06931e..00000000000
--- a/include/asm-powerpc/current.h
+++ /dev/null
@@ -1,40 +0,0 @@
1#ifndef _ASM_POWERPC_CURRENT_H
2#define _ASM_POWERPC_CURRENT_H
3#ifdef __KERNEL__
4
5/*
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12struct task_struct;
13
14#ifdef __powerpc64__
15#include <linux/stddef.h>
16#include <asm/paca.h>
17
18static inline struct task_struct *get_current(void)
19{
20 struct task_struct *task;
21
22 __asm__ __volatile__("ld %0,%1(13)"
23 : "=r" (task)
24 : "i" (offsetof(struct paca_struct, __current)));
25
26 return task;
27}
28#define current get_current()
29
30#else
31
32/*
33 * We keep `current' in r2 for speed.
34 */
35register struct task_struct *current asm ("r2");
36
37#endif
38
39#endif /* __KERNEL__ */
40#endif /* _ASM_POWERPC_CURRENT_H */
diff --git a/include/asm-powerpc/dbdma.h b/include/asm-powerpc/dbdma.h
deleted file mode 100644
index e23f07e73cb..00000000000
--- a/include/asm-powerpc/dbdma.h
+++ /dev/null
@@ -1,108 +0,0 @@
1/*
2 * Definitions for using the Apple Descriptor-Based DMA controller
3 * in Power Macintosh computers.
4 *
5 * Copyright (C) 1996 Paul Mackerras.
6 */
7
8#ifdef __KERNEL__
9#ifndef _ASM_DBDMA_H_
10#define _ASM_DBDMA_H_
11/*
12 * DBDMA control/status registers. All little-endian.
13 */
14struct dbdma_regs {
15 unsigned int control; /* lets you change bits in status */
16 unsigned int status; /* DMA and device status bits (see below) */
17 unsigned int cmdptr_hi; /* upper 32 bits of command address */
18 unsigned int cmdptr; /* (lower 32 bits of) command address (phys) */
19 unsigned int intr_sel; /* select interrupt condition bit */
20 unsigned int br_sel; /* select branch condition bit */
21 unsigned int wait_sel; /* select wait condition bit */
22 unsigned int xfer_mode;
23 unsigned int data2ptr_hi;
24 unsigned int data2ptr;
25 unsigned int res1;
26 unsigned int address_hi;
27 unsigned int br_addr_hi;
28 unsigned int res2[3];
29};
30
31/* Bits in control and status registers */
32#define RUN 0x8000
33#define PAUSE 0x4000
34#define FLUSH 0x2000
35#define WAKE 0x1000
36#define DEAD 0x0800
37#define ACTIVE 0x0400
38#define BT 0x0100
39#define DEVSTAT 0x00ff
40
41/*
42 * DBDMA command structure. These fields are all little-endian!
43 */
44struct dbdma_cmd {
45 unsigned short req_count; /* requested byte transfer count */
46 unsigned short command; /* command word (has bit-fields) */
47 unsigned int phy_addr; /* physical data address */
48 unsigned int cmd_dep; /* command-dependent field */
49 unsigned short res_count; /* residual count after completion */
50 unsigned short xfer_status; /* transfer status */
51};
52
53/* DBDMA command values in command field */
54#define OUTPUT_MORE 0 /* transfer memory data to stream */
55#define OUTPUT_LAST 0x1000 /* ditto followed by end marker */
56#define INPUT_MORE 0x2000 /* transfer stream data to memory */
57#define INPUT_LAST 0x3000 /* ditto, expect end marker */
58#define STORE_WORD 0x4000 /* write word (4 bytes) to device reg */
59#define LOAD_WORD 0x5000 /* read word (4 bytes) from device reg */
60#define DBDMA_NOP 0x6000 /* do nothing */
61#define DBDMA_STOP 0x7000 /* suspend processing */
62
63/* Key values in command field */
64#define KEY_STREAM0 0 /* usual data stream */
65#define KEY_STREAM1 0x100 /* control/status stream */
66#define KEY_STREAM2 0x200 /* device-dependent stream */
67#define KEY_STREAM3 0x300 /* device-dependent stream */
68#define KEY_REGS 0x500 /* device register space */
69#define KEY_SYSTEM 0x600 /* system memory-mapped space */
70#define KEY_DEVICE 0x700 /* device memory-mapped space */
71
72/* Interrupt control values in command field */
73#define INTR_NEVER 0 /* don't interrupt */
74#define INTR_IFSET 0x10 /* intr if condition bit is 1 */
75#define INTR_IFCLR 0x20 /* intr if condition bit is 0 */
76#define INTR_ALWAYS 0x30 /* always interrupt */
77
78/* Branch control values in command field */
79#define BR_NEVER 0 /* don't branch */
80#define BR_IFSET 0x4 /* branch if condition bit is 1 */
81#define BR_IFCLR 0x8 /* branch if condition bit is 0 */
82#define BR_ALWAYS 0xc /* always branch */
83
84/* Wait control values in command field */
85#define WAIT_NEVER 0 /* don't wait */
86#define WAIT_IFSET 1 /* wait if condition bit is 1 */
87#define WAIT_IFCLR 2 /* wait if condition bit is 0 */
88#define WAIT_ALWAYS 3 /* always wait */
89
90/* Align an address for a DBDMA command structure */
91#define DBDMA_ALIGN(x) (((unsigned long)(x) + sizeof(struct dbdma_cmd) - 1) \
92 & -sizeof(struct dbdma_cmd))
93
94/* Useful macros */
95#define DBDMA_DO_STOP(regs) do { \
96 out_le32(&((regs)->control), (RUN|FLUSH)<<16); \
97 while(in_le32(&((regs)->status)) & (ACTIVE|FLUSH)) \
98 ; \
99} while(0)
100
101#define DBDMA_DO_RESET(regs) do { \
102 out_le32(&((regs)->control), (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16);\
103 while(in_le32(&((regs)->status)) & (RUN)) \
104 ; \
105} while(0)
106
107#endif /* _ASM_DBDMA_H_ */
108#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/dcr-generic.h b/include/asm-powerpc/dcr-generic.h
deleted file mode 100644
index 35b71599ec4..00000000000
--- a/include/asm-powerpc/dcr-generic.h
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
3 * <benh@kernel.crashing.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
13 * the GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#ifndef _ASM_POWERPC_DCR_GENERIC_H
21#define _ASM_POWERPC_DCR_GENERIC_H
22#ifdef __KERNEL__
23#ifndef __ASSEMBLY__
24
25enum host_type_t {DCR_HOST_MMIO, DCR_HOST_NATIVE, DCR_HOST_INVALID};
26
27typedef struct {
28 enum host_type_t type;
29 union {
30 dcr_host_mmio_t mmio;
31 dcr_host_native_t native;
32 } host;
33} dcr_host_t;
34
35extern bool dcr_map_ok_generic(dcr_host_t host);
36
37extern dcr_host_t dcr_map_generic(struct device_node *dev, unsigned int dcr_n,
38 unsigned int dcr_c);
39extern void dcr_unmap_generic(dcr_host_t host, unsigned int dcr_c);
40
41extern u32 dcr_read_generic(dcr_host_t host, unsigned int dcr_n);
42
43extern void dcr_write_generic(dcr_host_t host, unsigned int dcr_n, u32 value);
44
45#endif /* __ASSEMBLY__ */
46#endif /* __KERNEL__ */
47#endif /* _ASM_POWERPC_DCR_GENERIC_H */
48
49
diff --git a/include/asm-powerpc/dcr-mmio.h b/include/asm-powerpc/dcr-mmio.h
deleted file mode 100644
index acd491dbd45..00000000000
--- a/include/asm-powerpc/dcr-mmio.h
+++ /dev/null
@@ -1,61 +0,0 @@
1/*
2 * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
3 * <benh@kernel.crashing.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
13 * the GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#ifndef _ASM_POWERPC_DCR_MMIO_H
21#define _ASM_POWERPC_DCR_MMIO_H
22#ifdef __KERNEL__
23
24#include <asm/io.h>
25
26typedef struct {
27 void __iomem *token;
28 unsigned int stride;
29 unsigned int base;
30} dcr_host_mmio_t;
31
32static inline bool dcr_map_ok_mmio(dcr_host_mmio_t host)
33{
34 return host.token != NULL;
35}
36
37extern dcr_host_mmio_t dcr_map_mmio(struct device_node *dev,
38 unsigned int dcr_n,
39 unsigned int dcr_c);
40extern void dcr_unmap_mmio(dcr_host_mmio_t host, unsigned int dcr_c);
41
42static inline u32 dcr_read_mmio(dcr_host_mmio_t host, unsigned int dcr_n)
43{
44 return in_be32(host.token + ((host.base + dcr_n) * host.stride));
45}
46
47static inline void dcr_write_mmio(dcr_host_mmio_t host,
48 unsigned int dcr_n,
49 u32 value)
50{
51 out_be32(host.token + ((host.base + dcr_n) * host.stride), value);
52}
53
54extern u64 of_translate_dcr_address(struct device_node *dev,
55 unsigned int dcr_n,
56 unsigned int *stride);
57
58#endif /* __KERNEL__ */
59#endif /* _ASM_POWERPC_DCR_MMIO_H */
60
61
diff --git a/include/asm-powerpc/dcr-native.h b/include/asm-powerpc/dcr-native.h
deleted file mode 100644
index 72d2b72c739..00000000000
--- a/include/asm-powerpc/dcr-native.h
+++ /dev/null
@@ -1,116 +0,0 @@
1/*
2 * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
3 * <benh@kernel.crashing.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
13 * the GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#ifndef _ASM_POWERPC_DCR_NATIVE_H
21#define _ASM_POWERPC_DCR_NATIVE_H
22#ifdef __KERNEL__
23#ifndef __ASSEMBLY__
24
25#include <linux/spinlock.h>
26
27typedef struct {
28 unsigned int base;
29} dcr_host_native_t;
30
31static inline bool dcr_map_ok_native(dcr_host_native_t host)
32{
33 return 1;
34}
35
36#define dcr_map_native(dev, dcr_n, dcr_c) \
37 ((dcr_host_native_t){ .base = (dcr_n) })
38#define dcr_unmap_native(host, dcr_c) do {} while (0)
39#define dcr_read_native(host, dcr_n) mfdcr(dcr_n + host.base)
40#define dcr_write_native(host, dcr_n, value) mtdcr(dcr_n + host.base, value)
41
42/* Device Control Registers */
43void __mtdcr(int reg, unsigned int val);
44unsigned int __mfdcr(int reg);
45#define mfdcr(rn) \
46 ({unsigned int rval; \
47 if (__builtin_constant_p(rn)) \
48 asm volatile("mfdcr %0," __stringify(rn) \
49 : "=r" (rval)); \
50 else \
51 rval = __mfdcr(rn); \
52 rval;})
53
54#define mtdcr(rn, v) \
55do { \
56 if (__builtin_constant_p(rn)) \
57 asm volatile("mtdcr " __stringify(rn) ",%0" \
58 : : "r" (v)); \
59 else \
60 __mtdcr(rn, v); \
61} while (0)
62
63/* R/W of indirect DCRs make use of standard naming conventions for DCRs */
64extern spinlock_t dcr_ind_lock;
65
66static inline unsigned __mfdcri(int base_addr, int base_data, int reg)
67{
68 unsigned long flags;
69 unsigned int val;
70
71 spin_lock_irqsave(&dcr_ind_lock, flags);
72 __mtdcr(base_addr, reg);
73 val = __mfdcr(base_data);
74 spin_unlock_irqrestore(&dcr_ind_lock, flags);
75 return val;
76}
77
78static inline void __mtdcri(int base_addr, int base_data, int reg,
79 unsigned val)
80{
81 unsigned long flags;
82
83 spin_lock_irqsave(&dcr_ind_lock, flags);
84 __mtdcr(base_addr, reg);
85 __mtdcr(base_data, val);
86 spin_unlock_irqrestore(&dcr_ind_lock, flags);
87}
88
89static inline void __dcri_clrset(int base_addr, int base_data, int reg,
90 unsigned clr, unsigned set)
91{
92 unsigned long flags;
93 unsigned int val;
94
95 spin_lock_irqsave(&dcr_ind_lock, flags);
96 __mtdcr(base_addr, reg);
97 val = (__mfdcr(base_data) & ~clr) | set;
98 __mtdcr(base_data, val);
99 spin_unlock_irqrestore(&dcr_ind_lock, flags);
100}
101
102#define mfdcri(base, reg) __mfdcri(DCRN_ ## base ## _CONFIG_ADDR, \
103 DCRN_ ## base ## _CONFIG_DATA, \
104 reg)
105
106#define mtdcri(base, reg, data) __mtdcri(DCRN_ ## base ## _CONFIG_ADDR, \
107 DCRN_ ## base ## _CONFIG_DATA, \
108 reg, data)
109
110#define dcri_clrset(base, reg, clr, set) __dcri_clrset(DCRN_ ## base ## _CONFIG_ADDR, \
111 DCRN_ ## base ## _CONFIG_DATA, \
112 reg, clr, set)
113
114#endif /* __ASSEMBLY__ */
115#endif /* __KERNEL__ */
116#endif /* _ASM_POWERPC_DCR_NATIVE_H */
diff --git a/include/asm-powerpc/dcr-regs.h b/include/asm-powerpc/dcr-regs.h
deleted file mode 100644
index 29b0ecef980..00000000000
--- a/include/asm-powerpc/dcr-regs.h
+++ /dev/null
@@ -1,149 +0,0 @@
1/*
2 * Common DCR / SDR / CPR register definitions used on various IBM/AMCC
3 * 4xx processors
4 *
5 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp
6 * <benh@kernel.crashing.org>
7 *
8 * Mostly lifted from asm-ppc/ibm4xx.h by
9 *
10 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
11 *
12 */
13
14#ifndef __DCR_REGS_H__
15#define __DCR_REGS_H__
16
17/*
18 * Most DCRs used for controlling devices such as the MAL, DMA engine,
19 * etc... are obtained for the device tree.
20 *
21 * The definitions in this files are fixed DCRs and indirect DCRs that
22 * are commonly used outside of specific drivers or refer to core
23 * common registers that may occasionally have to be tweaked outside
24 * of the driver main register set
25 */
26
27/* CPRs (440GX and 440SP/440SPe) */
28#define DCRN_CPR0_CONFIG_ADDR 0xc
29#define DCRN_CPR0_CONFIG_DATA 0xd
30
31/* SDRs (440GX and 440SP/440SPe) */
32#define DCRN_SDR0_CONFIG_ADDR 0xe
33#define DCRN_SDR0_CONFIG_DATA 0xf
34
35#define SDR0_PFC0 0x4100
36#define SDR0_PFC1 0x4101
37#define SDR0_PFC1_EPS 0x1c00000
38#define SDR0_PFC1_EPS_SHIFT 22
39#define SDR0_PFC1_RMII 0x02000000
40#define SDR0_MFR 0x4300
41#define SDR0_MFR_TAH0 0x80000000 /* TAHOE0 Enable */
42#define SDR0_MFR_TAH1 0x40000000 /* TAHOE1 Enable */
43#define SDR0_MFR_PCM 0x10000000 /* PPC440GP irq compat mode */
44#define SDR0_MFR_ECS 0x08000000 /* EMAC int clk */
45#define SDR0_MFR_T0TXFL 0x00080000
46#define SDR0_MFR_T0TXFH 0x00040000
47#define SDR0_MFR_T1TXFL 0x00020000
48#define SDR0_MFR_T1TXFH 0x00010000
49#define SDR0_MFR_E0TXFL 0x00008000
50#define SDR0_MFR_E0TXFH 0x00004000
51#define SDR0_MFR_E0RXFL 0x00002000
52#define SDR0_MFR_E0RXFH 0x00001000
53#define SDR0_MFR_E1TXFL 0x00000800
54#define SDR0_MFR_E1TXFH 0x00000400
55#define SDR0_MFR_E1RXFL 0x00000200
56#define SDR0_MFR_E1RXFH 0x00000100
57#define SDR0_MFR_E2TXFL 0x00000080
58#define SDR0_MFR_E2TXFH 0x00000040
59#define SDR0_MFR_E2RXFL 0x00000020
60#define SDR0_MFR_E2RXFH 0x00000010
61#define SDR0_MFR_E3TXFL 0x00000008
62#define SDR0_MFR_E3TXFH 0x00000004
63#define SDR0_MFR_E3RXFL 0x00000002
64#define SDR0_MFR_E3RXFH 0x00000001
65#define SDR0_UART0 0x0120
66#define SDR0_UART1 0x0121
67#define SDR0_UART2 0x0122
68#define SDR0_UART3 0x0123
69#define SDR0_CUST0 0x4000
70
71/*
72 * All those DCR register addresses are offsets from the base address
73 * for the SRAM0 controller (e.g. 0x20 on 440GX). The base address is
74 * excluded here and configured in the device tree.
75 */
76#define DCRN_SRAM0_SB0CR 0x00
77#define DCRN_SRAM0_SB1CR 0x01
78#define DCRN_SRAM0_SB2CR 0x02
79#define DCRN_SRAM0_SB3CR 0x03
80#define SRAM_SBCR_BU_MASK 0x00000180
81#define SRAM_SBCR_BS_64KB 0x00000800
82#define SRAM_SBCR_BU_RO 0x00000080
83#define SRAM_SBCR_BU_RW 0x00000180
84#define DCRN_SRAM0_BEAR 0x04
85#define DCRN_SRAM0_BESR0 0x05
86#define DCRN_SRAM0_BESR1 0x06
87#define DCRN_SRAM0_PMEG 0x07
88#define DCRN_SRAM0_CID 0x08
89#define DCRN_SRAM0_REVID 0x09
90#define DCRN_SRAM0_DPC 0x0a
91#define SRAM_DPC_ENABLE 0x80000000
92
93/*
94 * All those DCR register addresses are offsets from the base address
95 * for the SRAM0 controller (e.g. 0x30 on 440GX). The base address is
96 * excluded here and configured in the device tree.
97 */
98#define DCRN_L2C0_CFG 0x00
99#define L2C_CFG_L2M 0x80000000
100#define L2C_CFG_ICU 0x40000000
101#define L2C_CFG_DCU 0x20000000
102#define L2C_CFG_DCW_MASK 0x1e000000
103#define L2C_CFG_TPC 0x01000000
104#define L2C_CFG_CPC 0x00800000
105#define L2C_CFG_FRAN 0x00200000
106#define L2C_CFG_SS_MASK 0x00180000
107#define L2C_CFG_SS_256 0x00000000
108#define L2C_CFG_CPIM 0x00040000
109#define L2C_CFG_TPIM 0x00020000
110#define L2C_CFG_LIM 0x00010000
111#define L2C_CFG_PMUX_MASK 0x00007000
112#define L2C_CFG_PMUX_SNP 0x00000000
113#define L2C_CFG_PMUX_IF 0x00001000
114#define L2C_CFG_PMUX_DF 0x00002000
115#define L2C_CFG_PMUX_DS 0x00003000
116#define L2C_CFG_PMIM 0x00000800
117#define L2C_CFG_TPEI 0x00000400
118#define L2C_CFG_CPEI 0x00000200
119#define L2C_CFG_NAM 0x00000100
120#define L2C_CFG_SMCM 0x00000080
121#define L2C_CFG_NBRM 0x00000040
122#define L2C_CFG_RDBW 0x00000008 /* only 460EX/GT */
123#define DCRN_L2C0_CMD 0x01
124#define L2C_CMD_CLR 0x80000000
125#define L2C_CMD_DIAG 0x40000000
126#define L2C_CMD_INV 0x20000000
127#define L2C_CMD_CCP 0x10000000
128#define L2C_CMD_CTE 0x08000000
129#define L2C_CMD_STRC 0x04000000
130#define L2C_CMD_STPC 0x02000000
131#define L2C_CMD_RPMC 0x01000000
132#define L2C_CMD_HCC 0x00800000
133#define DCRN_L2C0_ADDR 0x02
134#define DCRN_L2C0_DATA 0x03
135#define DCRN_L2C0_SR 0x04
136#define L2C_SR_CC 0x80000000
137#define L2C_SR_CPE 0x40000000
138#define L2C_SR_TPE 0x20000000
139#define L2C_SR_LRU 0x10000000
140#define L2C_SR_PCS 0x08000000
141#define DCRN_L2C0_REVID 0x05
142#define DCRN_L2C0_SNP0 0x06
143#define DCRN_L2C0_SNP1 0x07
144#define L2C_SNP_BA_MASK 0xffff0000
145#define L2C_SNP_SSR_MASK 0x0000f000
146#define L2C_SNP_SSR_32G 0x0000f000
147#define L2C_SNP_ESR 0x00000800
148
149#endif /* __DCR_REGS_H__ */
diff --git a/include/asm-powerpc/dcr.h b/include/asm-powerpc/dcr.h
deleted file mode 100644
index 53b283050ab..00000000000
--- a/include/asm-powerpc/dcr.h
+++ /dev/null
@@ -1,82 +0,0 @@
1/*
2 * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
3 * <benh@kernel.crashing.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
13 * the GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#ifndef _ASM_POWERPC_DCR_H
21#define _ASM_POWERPC_DCR_H
22#ifdef __KERNEL__
23#ifndef __ASSEMBLY__
24#ifdef CONFIG_PPC_DCR
25
26#ifdef CONFIG_PPC_DCR_NATIVE
27#include <asm/dcr-native.h>
28#endif
29
30#ifdef CONFIG_PPC_DCR_MMIO
31#include <asm/dcr-mmio.h>
32#endif
33
34
35/* Indirection layer for providing both NATIVE and MMIO support. */
36
37#if defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO)
38
39#include <asm/dcr-generic.h>
40
41#define DCR_MAP_OK(host) dcr_map_ok_generic(host)
42#define dcr_map(dev, dcr_n, dcr_c) dcr_map_generic(dev, dcr_n, dcr_c)
43#define dcr_unmap(host, dcr_c) dcr_unmap_generic(host, dcr_c)
44#define dcr_read(host, dcr_n) dcr_read_generic(host, dcr_n)
45#define dcr_write(host, dcr_n, value) dcr_write_generic(host, dcr_n, value)
46
47#else
48
49#ifdef CONFIG_PPC_DCR_NATIVE
50typedef dcr_host_native_t dcr_host_t;
51#define DCR_MAP_OK(host) dcr_map_ok_native(host)
52#define dcr_map(dev, dcr_n, dcr_c) dcr_map_native(dev, dcr_n, dcr_c)
53#define dcr_unmap(host, dcr_c) dcr_unmap_native(host, dcr_c)
54#define dcr_read(host, dcr_n) dcr_read_native(host, dcr_n)
55#define dcr_write(host, dcr_n, value) dcr_write_native(host, dcr_n, value)
56#else
57typedef dcr_host_mmio_t dcr_host_t;
58#define DCR_MAP_OK(host) dcr_map_ok_mmio(host)
59#define dcr_map(dev, dcr_n, dcr_c) dcr_map_mmio(dev, dcr_n, dcr_c)
60#define dcr_unmap(host, dcr_c) dcr_unmap_mmio(host, dcr_c)
61#define dcr_read(host, dcr_n) dcr_read_mmio(host, dcr_n)
62#define dcr_write(host, dcr_n, value) dcr_write_mmio(host, dcr_n, value)
63#endif
64
65#endif /* defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO) */
66
67/*
68 * On CONFIG_PPC_MERGE, we have additional helpers to read the DCR
69 * base from the device-tree
70 */
71#ifdef CONFIG_PPC_MERGE
72struct device_node;
73extern unsigned int dcr_resource_start(struct device_node *np,
74 unsigned int index);
75extern unsigned int dcr_resource_len(struct device_node *np,
76 unsigned int index);
77#endif /* CONFIG_PPC_MERGE */
78
79#endif /* CONFIG_PPC_DCR */
80#endif /* __ASSEMBLY__ */
81#endif /* __KERNEL__ */
82#endif /* _ASM_POWERPC_DCR_H */
diff --git a/include/asm-powerpc/delay.h b/include/asm-powerpc/delay.h
deleted file mode 100644
index f9200a65c63..00000000000
--- a/include/asm-powerpc/delay.h
+++ /dev/null
@@ -1,34 +0,0 @@
1#ifndef _ASM_POWERPC_DELAY_H
2#define _ASM_POWERPC_DELAY_H
3#ifdef __KERNEL__
4
5/*
6 * Copyright 1996, Paul Mackerras.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 *
13 * PPC64 Support added by Dave Engebretsen, Todd Inglett, Mike Corrigan,
14 * Anton Blanchard.
15 */
16
17extern void __delay(unsigned long loops);
18extern void udelay(unsigned long usecs);
19
20/*
21 * On shared processor machines the generic implementation of mdelay can
22 * result in large errors. While each iteration of the loop inside mdelay
23 * is supposed to take 1ms, the hypervisor could sleep our partition for
24 * longer (eg 10ms). With the right timing these errors can add up.
25 *
26 * Since there is no 32bit overflow issue on 64bit kernels, just call
27 * udelay directly.
28 */
29#ifdef CONFIG_PPC64
30#define mdelay(n) udelay((n) * 1000)
31#endif
32
33#endif /* __KERNEL__ */
34#endif /* _ASM_POWERPC_DELAY_H */
diff --git a/include/asm-powerpc/device.h b/include/asm-powerpc/device.h
deleted file mode 100644
index 228ab2a315b..00000000000
--- a/include/asm-powerpc/device.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * Arch specific extensions to struct device
3 *
4 * This file is released under the GPLv2
5 */
6#ifndef _ASM_POWERPC_DEVICE_H
7#define _ASM_POWERPC_DEVICE_H
8
9struct dma_mapping_ops;
10struct device_node;
11
12struct dev_archdata {
13 /* Optional pointer to an OF device node */
14 struct device_node *of_node;
15
16 /* DMA operations on that device */
17 struct dma_mapping_ops *dma_ops;
18 void *dma_data;
19
20 /* NUMA node if applicable */
21 int numa_node;
22};
23
24#endif /* _ASM_POWERPC_DEVICE_H */
diff --git a/include/asm-powerpc/div64.h b/include/asm-powerpc/div64.h
deleted file mode 100644
index 6cd978cefb2..00000000000
--- a/include/asm-powerpc/div64.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/div64.h>
diff --git a/include/asm-powerpc/dma-mapping.h b/include/asm-powerpc/dma-mapping.h
deleted file mode 100644
index c7ca45f97dd..00000000000
--- a/include/asm-powerpc/dma-mapping.h
+++ /dev/null
@@ -1,474 +0,0 @@
1/*
2 * Copyright (C) 2004 IBM
3 *
4 * Implements the generic device dma API for powerpc.
5 * the pci and vio busses
6 */
7#ifndef _ASM_DMA_MAPPING_H
8#define _ASM_DMA_MAPPING_H
9#ifdef __KERNEL__
10
11#include <linux/types.h>
12#include <linux/cache.h>
13/* need struct page definitions */
14#include <linux/mm.h>
15#include <linux/scatterlist.h>
16#include <linux/dma-attrs.h>
17#include <asm/io.h>
18
19#define DMA_ERROR_CODE (~(dma_addr_t)0x0)
20
21#ifdef CONFIG_NOT_COHERENT_CACHE
22/*
23 * DMA-consistent mapping functions for PowerPCs that don't support
24 * cache snooping. These allocate/free a region of uncached mapped
25 * memory space for use with DMA devices. Alternatively, you could
26 * allocate the space "normally" and use the cache management functions
27 * to ensure it is consistent.
28 */
29extern void *__dma_alloc_coherent(size_t size, dma_addr_t *handle, gfp_t gfp);
30extern void __dma_free_coherent(size_t size, void *vaddr);
31extern void __dma_sync(void *vaddr, size_t size, int direction);
32extern void __dma_sync_page(struct page *page, unsigned long offset,
33 size_t size, int direction);
34
35#else /* ! CONFIG_NOT_COHERENT_CACHE */
36/*
37 * Cache coherent cores.
38 */
39
40#define __dma_alloc_coherent(gfp, size, handle) NULL
41#define __dma_free_coherent(size, addr) ((void)0)
42#define __dma_sync(addr, size, rw) ((void)0)
43#define __dma_sync_page(pg, off, sz, rw) ((void)0)
44
45#endif /* ! CONFIG_NOT_COHERENT_CACHE */
46
47#ifdef CONFIG_PPC64
48
49static inline unsigned long device_to_mask(struct device *dev)
50{
51 if (dev->dma_mask && *dev->dma_mask)
52 return *dev->dma_mask;
53 /* Assume devices without mask can take 32 bit addresses */
54 return 0xfffffffful;
55}
56
57/*
58 * DMA operations are abstracted for G5 vs. i/pSeries, PCI vs. VIO
59 */
60struct dma_mapping_ops {
61 void * (*alloc_coherent)(struct device *dev, size_t size,
62 dma_addr_t *dma_handle, gfp_t flag);
63 void (*free_coherent)(struct device *dev, size_t size,
64 void *vaddr, dma_addr_t dma_handle);
65 dma_addr_t (*map_single)(struct device *dev, void *ptr,
66 size_t size, enum dma_data_direction direction,
67 struct dma_attrs *attrs);
68 void (*unmap_single)(struct device *dev, dma_addr_t dma_addr,
69 size_t size, enum dma_data_direction direction,
70 struct dma_attrs *attrs);
71 int (*map_sg)(struct device *dev, struct scatterlist *sg,
72 int nents, enum dma_data_direction direction,
73 struct dma_attrs *attrs);
74 void (*unmap_sg)(struct device *dev, struct scatterlist *sg,
75 int nents, enum dma_data_direction direction,
76 struct dma_attrs *attrs);
77 int (*dma_supported)(struct device *dev, u64 mask);
78 int (*set_dma_mask)(struct device *dev, u64 dma_mask);
79};
80
81static inline struct dma_mapping_ops *get_dma_ops(struct device *dev)
82{
83 /* We don't handle the NULL dev case for ISA for now. We could
84 * do it via an out of line call but it is not needed for now. The
85 * only ISA DMA device we support is the floppy and we have a hack
86 * in the floppy driver directly to get a device for us.
87 */
88 if (unlikely(dev == NULL || dev->archdata.dma_ops == NULL))
89 return NULL;
90 return dev->archdata.dma_ops;
91}
92
93static inline void set_dma_ops(struct device *dev, struct dma_mapping_ops *ops)
94{
95 dev->archdata.dma_ops = ops;
96}
97
98static inline int dma_supported(struct device *dev, u64 mask)
99{
100 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
101
102 if (unlikely(dma_ops == NULL))
103 return 0;
104 if (dma_ops->dma_supported == NULL)
105 return 1;
106 return dma_ops->dma_supported(dev, mask);
107}
108
109/* We have our own implementation of pci_set_dma_mask() */
110#define HAVE_ARCH_PCI_SET_DMA_MASK
111
112static inline int dma_set_mask(struct device *dev, u64 dma_mask)
113{
114 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
115
116 if (unlikely(dma_ops == NULL))
117 return -EIO;
118 if (dma_ops->set_dma_mask != NULL)
119 return dma_ops->set_dma_mask(dev, dma_mask);
120 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
121 return -EIO;
122 *dev->dma_mask = dma_mask;
123 return 0;
124}
125
126static inline dma_addr_t dma_map_single_attrs(struct device *dev,
127 void *cpu_addr,
128 size_t size,
129 enum dma_data_direction direction,
130 struct dma_attrs *attrs)
131{
132 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
133
134 BUG_ON(!dma_ops);
135 return dma_ops->map_single(dev, cpu_addr, size, direction, attrs);
136}
137
138static inline void dma_unmap_single_attrs(struct device *dev,
139 dma_addr_t dma_addr,
140 size_t size,
141 enum dma_data_direction direction,
142 struct dma_attrs *attrs)
143{
144 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
145
146 BUG_ON(!dma_ops);
147 dma_ops->unmap_single(dev, dma_addr, size, direction, attrs);
148}
149
150static inline dma_addr_t dma_map_page_attrs(struct device *dev,
151 struct page *page,
152 unsigned long offset, size_t size,
153 enum dma_data_direction direction,
154 struct dma_attrs *attrs)
155{
156 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
157
158 BUG_ON(!dma_ops);
159 return dma_ops->map_single(dev, page_address(page) + offset, size,
160 direction, attrs);
161}
162
163static inline void dma_unmap_page_attrs(struct device *dev,
164 dma_addr_t dma_address,
165 size_t size,
166 enum dma_data_direction direction,
167 struct dma_attrs *attrs)
168{
169 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
170
171 BUG_ON(!dma_ops);
172 dma_ops->unmap_single(dev, dma_address, size, direction, attrs);
173}
174
175static inline int dma_map_sg_attrs(struct device *dev, struct scatterlist *sg,
176 int nents, enum dma_data_direction direction,
177 struct dma_attrs *attrs)
178{
179 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
180
181 BUG_ON(!dma_ops);
182 return dma_ops->map_sg(dev, sg, nents, direction, attrs);
183}
184
185static inline void dma_unmap_sg_attrs(struct device *dev,
186 struct scatterlist *sg,
187 int nhwentries,
188 enum dma_data_direction direction,
189 struct dma_attrs *attrs)
190{
191 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
192
193 BUG_ON(!dma_ops);
194 dma_ops->unmap_sg(dev, sg, nhwentries, direction, attrs);
195}
196
197static inline void *dma_alloc_coherent(struct device *dev, size_t size,
198 dma_addr_t *dma_handle, gfp_t flag)
199{
200 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
201
202 BUG_ON(!dma_ops);
203 return dma_ops->alloc_coherent(dev, size, dma_handle, flag);
204}
205
206static inline void dma_free_coherent(struct device *dev, size_t size,
207 void *cpu_addr, dma_addr_t dma_handle)
208{
209 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
210
211 BUG_ON(!dma_ops);
212 dma_ops->free_coherent(dev, size, cpu_addr, dma_handle);
213}
214
215static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
216 size_t size,
217 enum dma_data_direction direction)
218{
219 return dma_map_single_attrs(dev, cpu_addr, size, direction, NULL);
220}
221
222static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
223 size_t size,
224 enum dma_data_direction direction)
225{
226 dma_unmap_single_attrs(dev, dma_addr, size, direction, NULL);
227}
228
229static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
230 unsigned long offset, size_t size,
231 enum dma_data_direction direction)
232{
233 return dma_map_page_attrs(dev, page, offset, size, direction, NULL);
234}
235
236static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
237 size_t size,
238 enum dma_data_direction direction)
239{
240 dma_unmap_page_attrs(dev, dma_address, size, direction, NULL);
241}
242
243static inline int dma_map_sg(struct device *dev, struct scatterlist *sg,
244 int nents, enum dma_data_direction direction)
245{
246 return dma_map_sg_attrs(dev, sg, nents, direction, NULL);
247}
248
249static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
250 int nhwentries,
251 enum dma_data_direction direction)
252{
253 dma_unmap_sg_attrs(dev, sg, nhwentries, direction, NULL);
254}
255
256/*
257 * Available generic sets of operations
258 */
259extern struct dma_mapping_ops dma_iommu_ops;
260extern struct dma_mapping_ops dma_direct_ops;
261
262#else /* CONFIG_PPC64 */
263
264#define dma_supported(dev, mask) (1)
265
266static inline int dma_set_mask(struct device *dev, u64 dma_mask)
267{
268 if (!dev->dma_mask || !dma_supported(dev, mask))
269 return -EIO;
270
271 *dev->dma_mask = dma_mask;
272
273 return 0;
274}
275
276static inline void *dma_alloc_coherent(struct device *dev, size_t size,
277 dma_addr_t * dma_handle,
278 gfp_t gfp)
279{
280#ifdef CONFIG_NOT_COHERENT_CACHE
281 return __dma_alloc_coherent(size, dma_handle, gfp);
282#else
283 void *ret;
284 /* ignore region specifiers */
285 gfp &= ~(__GFP_DMA | __GFP_HIGHMEM);
286
287 if (dev == NULL || dev->coherent_dma_mask < 0xffffffff)
288 gfp |= GFP_DMA;
289
290 ret = (void *)__get_free_pages(gfp, get_order(size));
291
292 if (ret != NULL) {
293 memset(ret, 0, size);
294 *dma_handle = virt_to_bus(ret);
295 }
296
297 return ret;
298#endif
299}
300
301static inline void
302dma_free_coherent(struct device *dev, size_t size, void *vaddr,
303 dma_addr_t dma_handle)
304{
305#ifdef CONFIG_NOT_COHERENT_CACHE
306 __dma_free_coherent(size, vaddr);
307#else
308 free_pages((unsigned long)vaddr, get_order(size));
309#endif
310}
311
312static inline dma_addr_t
313dma_map_single(struct device *dev, void *ptr, size_t size,
314 enum dma_data_direction direction)
315{
316 BUG_ON(direction == DMA_NONE);
317
318 __dma_sync(ptr, size, direction);
319
320 return virt_to_bus(ptr);
321}
322
323static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
324 size_t size,
325 enum dma_data_direction direction)
326{
327 /* We do nothing. */
328}
329
330static inline dma_addr_t
331dma_map_page(struct device *dev, struct page *page,
332 unsigned long offset, size_t size,
333 enum dma_data_direction direction)
334{
335 BUG_ON(direction == DMA_NONE);
336
337 __dma_sync_page(page, offset, size, direction);
338
339 return page_to_bus(page) + offset;
340}
341
342static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
343 size_t size,
344 enum dma_data_direction direction)
345{
346 /* We do nothing. */
347}
348
349static inline int
350dma_map_sg(struct device *dev, struct scatterlist *sgl, int nents,
351 enum dma_data_direction direction)
352{
353 struct scatterlist *sg;
354 int i;
355
356 BUG_ON(direction == DMA_NONE);
357
358 for_each_sg(sgl, sg, nents, i) {
359 BUG_ON(!sg_page(sg));
360 __dma_sync_page(sg_page(sg), sg->offset, sg->length, direction);
361 sg->dma_address = page_to_bus(sg_page(sg)) + sg->offset;
362 }
363
364 return nents;
365}
366
367static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
368 int nhwentries,
369 enum dma_data_direction direction)
370{
371 /* We don't do anything here. */
372}
373
374#endif /* CONFIG_PPC64 */
375
376static inline void dma_sync_single_for_cpu(struct device *dev,
377 dma_addr_t dma_handle, size_t size,
378 enum dma_data_direction direction)
379{
380 BUG_ON(direction == DMA_NONE);
381 __dma_sync(bus_to_virt(dma_handle), size, direction);
382}
383
384static inline void dma_sync_single_for_device(struct device *dev,
385 dma_addr_t dma_handle, size_t size,
386 enum dma_data_direction direction)
387{
388 BUG_ON(direction == DMA_NONE);
389 __dma_sync(bus_to_virt(dma_handle), size, direction);
390}
391
392static inline void dma_sync_sg_for_cpu(struct device *dev,
393 struct scatterlist *sgl, int nents,
394 enum dma_data_direction direction)
395{
396 struct scatterlist *sg;
397 int i;
398
399 BUG_ON(direction == DMA_NONE);
400
401 for_each_sg(sgl, sg, nents, i)
402 __dma_sync_page(sg_page(sg), sg->offset, sg->length, direction);
403}
404
405static inline void dma_sync_sg_for_device(struct device *dev,
406 struct scatterlist *sgl, int nents,
407 enum dma_data_direction direction)
408{
409 struct scatterlist *sg;
410 int i;
411
412 BUG_ON(direction == DMA_NONE);
413
414 for_each_sg(sgl, sg, nents, i)
415 __dma_sync_page(sg_page(sg), sg->offset, sg->length, direction);
416}
417
418static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
419{
420#ifdef CONFIG_PPC64
421 return (dma_addr == DMA_ERROR_CODE);
422#else
423 return 0;
424#endif
425}
426
427#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
428#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
429#ifdef CONFIG_NOT_COHERENT_CACHE
430#define dma_is_consistent(d, h) (0)
431#else
432#define dma_is_consistent(d, h) (1)
433#endif
434
435static inline int dma_get_cache_alignment(void)
436{
437#ifdef CONFIG_PPC64
438 /* no easy way to get cache size on all processors, so return
439 * the maximum possible, to be safe */
440 return (1 << INTERNODE_CACHE_SHIFT);
441#else
442 /*
443 * Each processor family will define its own L1_CACHE_SHIFT,
444 * L1_CACHE_BYTES wraps to this, so this is always safe.
445 */
446 return L1_CACHE_BYTES;
447#endif
448}
449
450static inline void dma_sync_single_range_for_cpu(struct device *dev,
451 dma_addr_t dma_handle, unsigned long offset, size_t size,
452 enum dma_data_direction direction)
453{
454 /* just sync everything for now */
455 dma_sync_single_for_cpu(dev, dma_handle, offset + size, direction);
456}
457
458static inline void dma_sync_single_range_for_device(struct device *dev,
459 dma_addr_t dma_handle, unsigned long offset, size_t size,
460 enum dma_data_direction direction)
461{
462 /* just sync everything for now */
463 dma_sync_single_for_device(dev, dma_handle, offset + size, direction);
464}
465
466static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
467 enum dma_data_direction direction)
468{
469 BUG_ON(direction == DMA_NONE);
470 __dma_sync(vaddr, size, (int)direction);
471}
472
473#endif /* __KERNEL__ */
474#endif /* _ASM_DMA_MAPPING_H */
diff --git a/include/asm-powerpc/dma.h b/include/asm-powerpc/dma.h
deleted file mode 100644
index a7e06e25c70..00000000000
--- a/include/asm-powerpc/dma.h
+++ /dev/null
@@ -1,360 +0,0 @@
1#ifndef _ASM_POWERPC_DMA_H
2#define _ASM_POWERPC_DMA_H
3#ifdef __KERNEL__
4
5/*
6 * Defines for using and allocating dma channels.
7 * Written by Hennus Bergman, 1992.
8 * High DMA channel support & info by Hannu Savolainen
9 * and John Boyd, Nov. 1992.
10 * Changes for ppc sound by Christoph Nadig
11 */
12
13/*
14 * Note: Adapted for PowerPC by Gary Thomas
15 * Modified by Cort Dougan <cort@cs.nmt.edu>
16 *
17 * None of this really applies for Power Macintoshes. There is
18 * basically just enough here to get kernel/dma.c to compile.
19 *
20 * There may be some comments or restrictions made here which are
21 * not valid for the PReP platform. Take what you read
22 * with a grain of salt.
23 */
24
25#include <asm/io.h>
26#include <linux/spinlock.h>
27#include <asm/system.h>
28
29#ifndef MAX_DMA_CHANNELS
30#define MAX_DMA_CHANNELS 8
31#endif
32
33/* The maximum address that we can perform a DMA transfer to on this platform */
34/* Doesn't really apply... */
35#define MAX_DMA_ADDRESS (~0UL)
36
37#if !defined(CONFIG_PPC_ISERIES) || defined(CONFIG_PCI)
38
39#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
40#define dma_outb outb_p
41#else
42#define dma_outb outb
43#endif
44
45#define dma_inb inb
46
47/*
48 * NOTES about DMA transfers:
49 *
50 * controller 1: channels 0-3, byte operations, ports 00-1F
51 * controller 2: channels 4-7, word operations, ports C0-DF
52 *
53 * - ALL registers are 8 bits only, regardless of transfer size
54 * - channel 4 is not used - cascades 1 into 2.
55 * - channels 0-3 are byte - addresses/counts are for physical bytes
56 * - channels 5-7 are word - addresses/counts are for physical words
57 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
58 * - transfer count loaded to registers is 1 less than actual count
59 * - controller 2 offsets are all even (2x offsets for controller 1)
60 * - page registers for 5-7 don't use data bit 0, represent 128K pages
61 * - page registers for 0-3 use bit 0, represent 64K pages
62 *
63 * On PReP, DMA transfers are limited to the lower 16MB of _physical_ memory.
64 * On CHRP, the W83C553F (and VLSI Tollgate?) support full 32 bit addressing.
65 * Note that addresses loaded into registers must be _physical_ addresses,
66 * not logical addresses (which may differ if paging is active).
67 *
68 * Address mapping for channels 0-3:
69 *
70 * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
71 * | ... | | ... | | ... |
72 * | ... | | ... | | ... |
73 * | ... | | ... | | ... |
74 * P7 ... P0 A7 ... A0 A7 ... A0
75 * | Page | Addr MSB | Addr LSB | (DMA registers)
76 *
77 * Address mapping for channels 5-7:
78 *
79 * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
80 * | ... | \ \ ... \ \ \ ... \ \
81 * | ... | \ \ ... \ \ \ ... \ (not used)
82 * | ... | \ \ ... \ \ \ ... \
83 * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
84 * | Page | Addr MSB | Addr LSB | (DMA registers)
85 *
86 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
87 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
88 * the hardware level, so odd-byte transfers aren't possible).
89 *
90 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
91 * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
92 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
93 *
94 */
95
96/* 8237 DMA controllers */
97#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
98#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
99
100/* DMA controller registers */
101#define DMA1_CMD_REG 0x08 /* command register (w) */
102#define DMA1_STAT_REG 0x08 /* status register (r) */
103#define DMA1_REQ_REG 0x09 /* request register (w) */
104#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
105#define DMA1_MODE_REG 0x0B /* mode register (w) */
106#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
107#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
108#define DMA1_RESET_REG 0x0D /* Master Clear (w) */
109#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
110#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
111
112#define DMA2_CMD_REG 0xD0 /* command register (w) */
113#define DMA2_STAT_REG 0xD0 /* status register (r) */
114#define DMA2_REQ_REG 0xD2 /* request register (w) */
115#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
116#define DMA2_MODE_REG 0xD6 /* mode register (w) */
117#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
118#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
119#define DMA2_RESET_REG 0xDA /* Master Clear (w) */
120#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
121#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
122
123#define DMA_ADDR_0 0x00 /* DMA address registers */
124#define DMA_ADDR_1 0x02
125#define DMA_ADDR_2 0x04
126#define DMA_ADDR_3 0x06
127#define DMA_ADDR_4 0xC0
128#define DMA_ADDR_5 0xC4
129#define DMA_ADDR_6 0xC8
130#define DMA_ADDR_7 0xCC
131
132#define DMA_CNT_0 0x01 /* DMA count registers */
133#define DMA_CNT_1 0x03
134#define DMA_CNT_2 0x05
135#define DMA_CNT_3 0x07
136#define DMA_CNT_4 0xC2
137#define DMA_CNT_5 0xC6
138#define DMA_CNT_6 0xCA
139#define DMA_CNT_7 0xCE
140
141#define DMA_LO_PAGE_0 0x87 /* DMA page registers */
142#define DMA_LO_PAGE_1 0x83
143#define DMA_LO_PAGE_2 0x81
144#define DMA_LO_PAGE_3 0x82
145#define DMA_LO_PAGE_5 0x8B
146#define DMA_LO_PAGE_6 0x89
147#define DMA_LO_PAGE_7 0x8A
148
149#define DMA_HI_PAGE_0 0x487 /* DMA page registers */
150#define DMA_HI_PAGE_1 0x483
151#define DMA_HI_PAGE_2 0x481
152#define DMA_HI_PAGE_3 0x482
153#define DMA_HI_PAGE_5 0x48B
154#define DMA_HI_PAGE_6 0x489
155#define DMA_HI_PAGE_7 0x48A
156
157#define DMA1_EXT_REG 0x40B
158#define DMA2_EXT_REG 0x4D6
159
160#ifndef __powerpc64__
161 /* in arch/ppc/kernel/setup.c -- Cort */
162 extern unsigned int DMA_MODE_WRITE;
163 extern unsigned int DMA_MODE_READ;
164 extern unsigned long ISA_DMA_THRESHOLD;
165#else
166 #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
167 #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
168#endif
169
170#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
171
172#define DMA_AUTOINIT 0x10
173
174extern spinlock_t dma_spin_lock;
175
176static __inline__ unsigned long claim_dma_lock(void)
177{
178 unsigned long flags;
179 spin_lock_irqsave(&dma_spin_lock, flags);
180 return flags;
181}
182
183static __inline__ void release_dma_lock(unsigned long flags)
184{
185 spin_unlock_irqrestore(&dma_spin_lock, flags);
186}
187
188/* enable/disable a specific DMA channel */
189static __inline__ void enable_dma(unsigned int dmanr)
190{
191 unsigned char ucDmaCmd = 0x00;
192
193 if (dmanr != 4) {
194 dma_outb(0, DMA2_MASK_REG); /* This may not be enabled */
195 dma_outb(ucDmaCmd, DMA2_CMD_REG); /* Enable group */
196 }
197 if (dmanr <= 3) {
198 dma_outb(dmanr, DMA1_MASK_REG);
199 dma_outb(ucDmaCmd, DMA1_CMD_REG); /* Enable group */
200 } else {
201 dma_outb(dmanr & 3, DMA2_MASK_REG);
202 }
203}
204
205static __inline__ void disable_dma(unsigned int dmanr)
206{
207 if (dmanr <= 3)
208 dma_outb(dmanr | 4, DMA1_MASK_REG);
209 else
210 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
211}
212
213/* Clear the 'DMA Pointer Flip Flop'.
214 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
215 * Use this once to initialize the FF to a known state.
216 * After that, keep track of it. :-)
217 * --- In order to do that, the DMA routines below should ---
218 * --- only be used while interrupts are disabled! ---
219 */
220static __inline__ void clear_dma_ff(unsigned int dmanr)
221{
222 if (dmanr <= 3)
223 dma_outb(0, DMA1_CLEAR_FF_REG);
224 else
225 dma_outb(0, DMA2_CLEAR_FF_REG);
226}
227
228/* set mode (above) for a specific DMA channel */
229static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
230{
231 if (dmanr <= 3)
232 dma_outb(mode | dmanr, DMA1_MODE_REG);
233 else
234 dma_outb(mode | (dmanr & 3), DMA2_MODE_REG);
235}
236
237/* Set only the page register bits of the transfer address.
238 * This is used for successive transfers when we know the contents of
239 * the lower 16 bits of the DMA current address register, but a 64k boundary
240 * may have been crossed.
241 */
242static __inline__ void set_dma_page(unsigned int dmanr, int pagenr)
243{
244 switch (dmanr) {
245 case 0:
246 dma_outb(pagenr, DMA_LO_PAGE_0);
247 dma_outb(pagenr >> 8, DMA_HI_PAGE_0);
248 break;
249 case 1:
250 dma_outb(pagenr, DMA_LO_PAGE_1);
251 dma_outb(pagenr >> 8, DMA_HI_PAGE_1);
252 break;
253 case 2:
254 dma_outb(pagenr, DMA_LO_PAGE_2);
255 dma_outb(pagenr >> 8, DMA_HI_PAGE_2);
256 break;
257 case 3:
258 dma_outb(pagenr, DMA_LO_PAGE_3);
259 dma_outb(pagenr >> 8, DMA_HI_PAGE_3);
260 break;
261 case 5:
262 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5);
263 dma_outb(pagenr >> 8, DMA_HI_PAGE_5);
264 break;
265 case 6:
266 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6);
267 dma_outb(pagenr >> 8, DMA_HI_PAGE_6);
268 break;
269 case 7:
270 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7);
271 dma_outb(pagenr >> 8, DMA_HI_PAGE_7);
272 break;
273 }
274}
275
276/* Set transfer address & page bits for specific DMA channel.
277 * Assumes dma flipflop is clear.
278 */
279static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys)
280{
281 if (dmanr <= 3) {
282 dma_outb(phys & 0xff,
283 ((dmanr & 3) << 1) + IO_DMA1_BASE);
284 dma_outb((phys >> 8) & 0xff,
285 ((dmanr & 3) << 1) + IO_DMA1_BASE);
286 } else {
287 dma_outb((phys >> 1) & 0xff,
288 ((dmanr & 3) << 2) + IO_DMA2_BASE);
289 dma_outb((phys >> 9) & 0xff,
290 ((dmanr & 3) << 2) + IO_DMA2_BASE);
291 }
292 set_dma_page(dmanr, phys >> 16);
293}
294
295
296/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
297 * a specific DMA channel.
298 * You must ensure the parameters are valid.
299 * NOTE: from a manual: "the number of transfers is one more
300 * than the initial word count"! This is taken into account.
301 * Assumes dma flip-flop is clear.
302 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
303 */
304static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
305{
306 count--;
307 if (dmanr <= 3) {
308 dma_outb(count & 0xff,
309 ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
310 dma_outb((count >> 8) & 0xff,
311 ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
312 } else {
313 dma_outb((count >> 1) & 0xff,
314 ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
315 dma_outb((count >> 9) & 0xff,
316 ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
317 }
318}
319
320
321/* Get DMA residue count. After a DMA transfer, this
322 * should return zero. Reading this while a DMA transfer is
323 * still in progress will return unpredictable results.
324 * If called before the channel has been used, it may return 1.
325 * Otherwise, it returns the number of _bytes_ left to transfer.
326 *
327 * Assumes DMA flip-flop is clear.
328 */
329static __inline__ int get_dma_residue(unsigned int dmanr)
330{
331 unsigned int io_port = (dmanr <= 3)
332 ? ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
333 : ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE;
334
335 /* using short to get 16-bit wrap around */
336 unsigned short count;
337
338 count = 1 + dma_inb(io_port);
339 count += dma_inb(io_port) << 8;
340
341 return (dmanr <= 3) ? count : (count << 1);
342}
343
344/* These are in kernel/dma.c: */
345
346/* reserve a DMA channel */
347extern int request_dma(unsigned int dmanr, const char *device_id);
348/* release it again */
349extern void free_dma(unsigned int dmanr);
350
351#ifdef CONFIG_PCI
352extern int isa_dma_bridge_buggy;
353#else
354#define isa_dma_bridge_buggy (0)
355#endif
356
357#endif /* !defined(CONFIG_PPC_ISERIES) || defined(CONFIG_PCI) */
358
359#endif /* __KERNEL__ */
360#endif /* _ASM_POWERPC_DMA_H */
diff --git a/include/asm-powerpc/edac.h b/include/asm-powerpc/edac.h
deleted file mode 100644
index 6ead88bbfbb..00000000000
--- a/include/asm-powerpc/edac.h
+++ /dev/null
@@ -1,40 +0,0 @@
1/*
2 * PPC EDAC common defs
3 *
4 * Author: Dave Jiang <djiang@mvista.com>
5 *
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#ifndef ASM_EDAC_H
12#define ASM_EDAC_H
13/*
14 * ECC atomic, DMA, SMP and interrupt safe scrub function.
15 * Implements the per arch atomic_scrub() that EDAC use for software
16 * ECC scrubbing. It reads memory and then writes back the original
17 * value, allowing the hardware to detect and correct memory errors.
18 */
19static __inline__ void atomic_scrub(void *va, u32 size)
20{
21 unsigned int *virt_addr = va;
22 unsigned int temp;
23 unsigned int i;
24
25 for (i = 0; i < size / sizeof(*virt_addr); i++, virt_addr++) {
26 /* Very carefully read and write to memory atomically
27 * so we are interrupt, DMA and SMP safe.
28 */
29 __asm__ __volatile__ ("\n\
30 1: lwarx %0,0,%1\n\
31 stwcx. %0,0,%1\n\
32 bne- 1b\n\
33 isync"
34 : "=&r"(temp)
35 : "r"(virt_addr)
36 : "cr0", "memory");
37 }
38}
39
40#endif
diff --git a/include/asm-powerpc/eeh.h b/include/asm-powerpc/eeh.h
deleted file mode 100644
index b886bec6701..00000000000
--- a/include/asm-powerpc/eeh.h
+++ /dev/null
@@ -1,211 +0,0 @@
1/*
2 * eeh.h
3 * Copyright (C) 2001 Dave Engebretsen & Todd Inglett IBM Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#ifndef _PPC64_EEH_H
21#define _PPC64_EEH_H
22#ifdef __KERNEL__
23
24#include <linux/init.h>
25#include <linux/list.h>
26#include <linux/string.h>
27
28struct pci_dev;
29struct pci_bus;
30struct device_node;
31
32#ifdef CONFIG_EEH
33
34extern int eeh_subsystem_enabled;
35
36/* Values for eeh_mode bits in device_node */
37#define EEH_MODE_SUPPORTED (1<<0)
38#define EEH_MODE_NOCHECK (1<<1)
39#define EEH_MODE_ISOLATED (1<<2)
40#define EEH_MODE_RECOVERING (1<<3)
41#define EEH_MODE_IRQ_DISABLED (1<<4)
42
43/* Max number of EEH freezes allowed before we consider the device
44 * to be permanently disabled. */
45#define EEH_MAX_ALLOWED_FREEZES 5
46
47void __init eeh_init(void);
48unsigned long eeh_check_failure(const volatile void __iomem *token,
49 unsigned long val);
50int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev);
51void __init pci_addr_cache_build(void);
52
53/**
54 * eeh_add_device_early
55 * eeh_add_device_late
56 *
57 * Perform eeh initialization for devices added after boot.
58 * Call eeh_add_device_early before doing any i/o to the
59 * device (including config space i/o). Call eeh_add_device_late
60 * to finish the eeh setup for this device.
61 */
62void eeh_add_device_tree_early(struct device_node *);
63void eeh_add_device_tree_late(struct pci_bus *);
64
65/**
66 * eeh_remove_device_recursive - undo EEH for device & children.
67 * @dev: pci device to be removed
68 *
69 * As above, this removes the device; it also removes child
70 * pci devices as well.
71 */
72void eeh_remove_bus_device(struct pci_dev *);
73
74/**
75 * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
76 *
77 * If this macro yields TRUE, the caller relays to eeh_check_failure()
78 * which does further tests out of line.
79 */
80#define EEH_POSSIBLE_ERROR(val, type) ((val) == (type)~0 && eeh_subsystem_enabled)
81
82/*
83 * Reads from a device which has been isolated by EEH will return
84 * all 1s. This macro gives an all-1s value of the given size (in
85 * bytes: 1, 2, or 4) for comparing with the result of a read.
86 */
87#define EEH_IO_ERROR_VALUE(size) (~0U >> ((4 - (size)) * 8))
88
89#else /* !CONFIG_EEH */
90static inline void eeh_init(void) { }
91
92static inline unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val)
93{
94 return val;
95}
96
97static inline int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev)
98{
99 return 0;
100}
101
102static inline void pci_addr_cache_build(void) { }
103
104static inline void eeh_add_device_tree_early(struct device_node *dn) { }
105
106static inline void eeh_add_device_tree_late(struct pci_bus *bus) { }
107
108static inline void eeh_remove_bus_device(struct pci_dev *dev) { }
109#define EEH_POSSIBLE_ERROR(val, type) (0)
110#define EEH_IO_ERROR_VALUE(size) (-1UL)
111#endif /* CONFIG_EEH */
112
113/*
114 * MMIO read/write operations with EEH support.
115 */
116static inline u8 eeh_readb(const volatile void __iomem *addr)
117{
118 u8 val = in_8(addr);
119 if (EEH_POSSIBLE_ERROR(val, u8))
120 return eeh_check_failure(addr, val);
121 return val;
122}
123
124static inline u16 eeh_readw(const volatile void __iomem *addr)
125{
126 u16 val = in_le16(addr);
127 if (EEH_POSSIBLE_ERROR(val, u16))
128 return eeh_check_failure(addr, val);
129 return val;
130}
131
132static inline u32 eeh_readl(const volatile void __iomem *addr)
133{
134 u32 val = in_le32(addr);
135 if (EEH_POSSIBLE_ERROR(val, u32))
136 return eeh_check_failure(addr, val);
137 return val;
138}
139
140static inline u64 eeh_readq(const volatile void __iomem *addr)
141{
142 u64 val = in_le64(addr);
143 if (EEH_POSSIBLE_ERROR(val, u64))
144 return eeh_check_failure(addr, val);
145 return val;
146}
147
148static inline u16 eeh_readw_be(const volatile void __iomem *addr)
149{
150 u16 val = in_be16(addr);
151 if (EEH_POSSIBLE_ERROR(val, u16))
152 return eeh_check_failure(addr, val);
153 return val;
154}
155
156static inline u32 eeh_readl_be(const volatile void __iomem *addr)
157{
158 u32 val = in_be32(addr);
159 if (EEH_POSSIBLE_ERROR(val, u32))
160 return eeh_check_failure(addr, val);
161 return val;
162}
163
164static inline u64 eeh_readq_be(const volatile void __iomem *addr)
165{
166 u64 val = in_be64(addr);
167 if (EEH_POSSIBLE_ERROR(val, u64))
168 return eeh_check_failure(addr, val);
169 return val;
170}
171
172static inline void eeh_memcpy_fromio(void *dest, const
173 volatile void __iomem *src,
174 unsigned long n)
175{
176 _memcpy_fromio(dest, src, n);
177
178 /* Look for ffff's here at dest[n]. Assume that at least 4 bytes
179 * were copied. Check all four bytes.
180 */
181 if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32))
182 eeh_check_failure(src, *((u32 *)(dest + n - 4)));
183}
184
185/* in-string eeh macros */
186static inline void eeh_readsb(const volatile void __iomem *addr, void * buf,
187 int ns)
188{
189 _insb(addr, buf, ns);
190 if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8))
191 eeh_check_failure(addr, *(u8*)buf);
192}
193
194static inline void eeh_readsw(const volatile void __iomem *addr, void * buf,
195 int ns)
196{
197 _insw(addr, buf, ns);
198 if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16))
199 eeh_check_failure(addr, *(u16*)buf);
200}
201
202static inline void eeh_readsl(const volatile void __iomem *addr, void * buf,
203 int nl)
204{
205 _insl(addr, buf, nl);
206 if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32))
207 eeh_check_failure(addr, *(u32*)buf);
208}
209
210#endif /* __KERNEL__ */
211#endif /* _PPC64_EEH_H */
diff --git a/include/asm-powerpc/eeh_event.h b/include/asm-powerpc/eeh_event.h
deleted file mode 100644
index cc3cb04539a..00000000000
--- a/include/asm-powerpc/eeh_event.h
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * eeh_event.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 *
18 * Copyright (c) 2005 Linas Vepstas <linas@linas.org>
19 */
20
21#ifndef ASM_POWERPC_EEH_EVENT_H
22#define ASM_POWERPC_EEH_EVENT_H
23#ifdef __KERNEL__
24
25/** EEH event -- structure holding pci controller data that describes
26 * a change in the isolation status of a PCI slot. A pointer
27 * to this struct is passed as the data pointer in a notify callback.
28 */
29struct eeh_event {
30 struct list_head list;
31 struct device_node *dn; /* struct device node */
32 struct pci_dev *dev; /* affected device */
33};
34
35/**
36 * eeh_send_failure_event - generate a PCI error event
37 * @dev pci device
38 *
39 * This routine builds a PCI error event which will be delivered
40 * to all listeners on the eeh_notifier_chain.
41 *
42 * This routine can be called within an interrupt context;
43 * the actual event will be delivered in a normal context
44 * (from a workqueue).
45 */
46int eeh_send_failure_event (struct device_node *dn,
47 struct pci_dev *dev);
48
49/* Main recovery function */
50struct pci_dn * handle_eeh_events (struct eeh_event *);
51
52#endif /* __KERNEL__ */
53#endif /* ASM_POWERPC_EEH_EVENT_H */
diff --git a/include/asm-powerpc/elf.h b/include/asm-powerpc/elf.h
deleted file mode 100644
index 80d1f399ee5..00000000000
--- a/include/asm-powerpc/elf.h
+++ /dev/null
@@ -1,424 +0,0 @@
1#ifndef _ASM_POWERPC_ELF_H
2#define _ASM_POWERPC_ELF_H
3
4#ifdef __KERNEL__
5#include <linux/sched.h> /* for task_struct */
6#include <asm/page.h>
7#include <asm/string.h>
8#endif
9
10#include <asm/types.h>
11#include <asm/ptrace.h>
12#include <asm/cputable.h>
13#include <asm/auxvec.h>
14
15/* PowerPC relocations defined by the ABIs */
16#define R_PPC_NONE 0
17#define R_PPC_ADDR32 1 /* 32bit absolute address */
18#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */
19#define R_PPC_ADDR16 3 /* 16bit absolute address */
20#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */
21#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */
22#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */
23#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */
24#define R_PPC_ADDR14_BRTAKEN 8
25#define R_PPC_ADDR14_BRNTAKEN 9
26#define R_PPC_REL24 10 /* PC relative 26 bit */
27#define R_PPC_REL14 11 /* PC relative 16 bit */
28#define R_PPC_REL14_BRTAKEN 12
29#define R_PPC_REL14_BRNTAKEN 13
30#define R_PPC_GOT16 14
31#define R_PPC_GOT16_LO 15
32#define R_PPC_GOT16_HI 16
33#define R_PPC_GOT16_HA 17
34#define R_PPC_PLTREL24 18
35#define R_PPC_COPY 19
36#define R_PPC_GLOB_DAT 20
37#define R_PPC_JMP_SLOT 21
38#define R_PPC_RELATIVE 22
39#define R_PPC_LOCAL24PC 23
40#define R_PPC_UADDR32 24
41#define R_PPC_UADDR16 25
42#define R_PPC_REL32 26
43#define R_PPC_PLT32 27
44#define R_PPC_PLTREL32 28
45#define R_PPC_PLT16_LO 29
46#define R_PPC_PLT16_HI 30
47#define R_PPC_PLT16_HA 31
48#define R_PPC_SDAREL16 32
49#define R_PPC_SECTOFF 33
50#define R_PPC_SECTOFF_LO 34
51#define R_PPC_SECTOFF_HI 35
52#define R_PPC_SECTOFF_HA 36
53
54/* PowerPC relocations defined for the TLS access ABI. */
55#define R_PPC_TLS 67 /* none (sym+add)@tls */
56#define R_PPC_DTPMOD32 68 /* word32 (sym+add)@dtpmod */
57#define R_PPC_TPREL16 69 /* half16* (sym+add)@tprel */
58#define R_PPC_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */
59#define R_PPC_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */
60#define R_PPC_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */
61#define R_PPC_TPREL32 73 /* word32 (sym+add)@tprel */
62#define R_PPC_DTPREL16 74 /* half16* (sym+add)@dtprel */
63#define R_PPC_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */
64#define R_PPC_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */
65#define R_PPC_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */
66#define R_PPC_DTPREL32 78 /* word32 (sym+add)@dtprel */
67#define R_PPC_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */
68#define R_PPC_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */
69#define R_PPC_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */
70#define R_PPC_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */
71#define R_PPC_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */
72#define R_PPC_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */
73#define R_PPC_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */
74#define R_PPC_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */
75#define R_PPC_GOT_TPREL16 87 /* half16* (sym+add)@got@tprel */
76#define R_PPC_GOT_TPREL16_LO 88 /* half16 (sym+add)@got@tprel@l */
77#define R_PPC_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */
78#define R_PPC_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */
79#define R_PPC_GOT_DTPREL16 91 /* half16* (sym+add)@got@dtprel */
80#define R_PPC_GOT_DTPREL16_LO 92 /* half16* (sym+add)@got@dtprel@l */
81#define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */
82#define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */
83
84/* keep this the last entry. */
85#define R_PPC_NUM 95
86
87/*
88 * ELF register definitions..
89 *
90 * This program is free software; you can redistribute it and/or
91 * modify it under the terms of the GNU General Public License
92 * as published by the Free Software Foundation; either version
93 * 2 of the License, or (at your option) any later version.
94 */
95
96#define ELF_NGREG 48 /* includes nip, msr, lr, etc. */
97#define ELF_NFPREG 33 /* includes fpscr */
98
99typedef unsigned long elf_greg_t64;
100typedef elf_greg_t64 elf_gregset_t64[ELF_NGREG];
101
102typedef unsigned int elf_greg_t32;
103typedef elf_greg_t32 elf_gregset_t32[ELF_NGREG];
104typedef elf_gregset_t32 compat_elf_gregset_t;
105
106/*
107 * ELF_ARCH, CLASS, and DATA are used to set parameters in the core dumps.
108 */
109#ifdef __powerpc64__
110# define ELF_NVRREG32 33 /* includes vscr & vrsave stuffed together */
111# define ELF_NVRREG 34 /* includes vscr & vrsave in split vectors */
112# define ELF_NVSRHALFREG 32 /* Half the vsx registers */
113# define ELF_GREG_TYPE elf_greg_t64
114#else
115# define ELF_NEVRREG 34 /* includes acc (as 2) */
116# define ELF_NVRREG 33 /* includes vscr */
117# define ELF_GREG_TYPE elf_greg_t32
118# define ELF_ARCH EM_PPC
119# define ELF_CLASS ELFCLASS32
120# define ELF_DATA ELFDATA2MSB
121#endif /* __powerpc64__ */
122
123#ifndef ELF_ARCH
124# define ELF_ARCH EM_PPC64
125# define ELF_CLASS ELFCLASS64
126# define ELF_DATA ELFDATA2MSB
127 typedef elf_greg_t64 elf_greg_t;
128 typedef elf_gregset_t64 elf_gregset_t;
129#else
130 /* Assumption: ELF_ARCH == EM_PPC and ELF_CLASS == ELFCLASS32 */
131 typedef elf_greg_t32 elf_greg_t;
132 typedef elf_gregset_t32 elf_gregset_t;
133#endif /* ELF_ARCH */
134
135/* Floating point registers */
136typedef double elf_fpreg_t;
137typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
138
139/* Altivec registers */
140/*
141 * The entries with indexes 0-31 contain the corresponding vector registers.
142 * The entry with index 32 contains the vscr as the last word (offset 12)
143 * within the quadword. This allows the vscr to be stored as either a
144 * quadword (since it must be copied via a vector register to/from storage)
145 * or as a word.
146 *
147 * 64-bit kernel notes: The entry at index 33 contains the vrsave as the first
148 * word (offset 0) within the quadword.
149 *
150 * This definition of the VMX state is compatible with the current PPC32
151 * ptrace interface. This allows signal handling and ptrace to use the same
152 * structures. This also simplifies the implementation of a bi-arch
153 * (combined (32- and 64-bit) gdb.
154 *
155 * Note that it's _not_ compatible with 32 bits ucontext which stuffs the
156 * vrsave along with vscr and so only uses 33 vectors for the register set
157 */
158typedef __vector128 elf_vrreg_t;
159typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG];
160#ifdef __powerpc64__
161typedef elf_vrreg_t elf_vrregset_t32[ELF_NVRREG32];
162typedef elf_fpreg_t elf_vsrreghalf_t32[ELF_NVSRHALFREG];
163#endif
164
165#ifdef __KERNEL__
166/*
167 * This is used to ensure we don't load something for the wrong architecture.
168 */
169#define elf_check_arch(x) ((x)->e_machine == ELF_ARCH)
170#define compat_elf_check_arch(x) ((x)->e_machine == EM_PPC)
171
172#define USE_ELF_CORE_DUMP
173#define CORE_DUMP_USE_REGSET
174#define ELF_EXEC_PAGESIZE PAGE_SIZE
175
176/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
177 use of this is to invoke "./ld.so someprog" to test out a new version of
178 the loader. We need to make sure that it is out of the way of the program
179 that it will "exec", and that there is sufficient room for the brk. */
180
181#define ELF_ET_DYN_BASE (0x20000000)
182
183/*
184 * Our registers are always unsigned longs, whether we're a 32 bit
185 * process or 64 bit, on either a 64 bit or 32 bit kernel.
186 *
187 * This macro relies on elf_regs[i] having the right type to truncate to,
188 * either u32 or u64. It defines the body of the elf_core_copy_regs
189 * function, either the native one with elf_gregset_t elf_regs or
190 * the 32-bit one with elf_gregset_t32 elf_regs.
191 */
192#define PPC_ELF_CORE_COPY_REGS(elf_regs, regs) \
193 int i, nregs = min(sizeof(*regs) / sizeof(unsigned long), \
194 (size_t)ELF_NGREG); \
195 for (i = 0; i < nregs; i++) \
196 elf_regs[i] = ((unsigned long *) regs)[i]; \
197 memset(&elf_regs[i], 0, (ELF_NGREG - i) * sizeof(elf_regs[0]))
198
199/* Common routine for both 32-bit and 64-bit native processes */
200static inline void ppc_elf_core_copy_regs(elf_gregset_t elf_regs,
201 struct pt_regs *regs)
202{
203 PPC_ELF_CORE_COPY_REGS(elf_regs, regs);
204}
205#define ELF_CORE_COPY_REGS(gregs, regs) ppc_elf_core_copy_regs(gregs, regs);
206
207typedef elf_vrregset_t elf_fpxregset_t;
208
209/* ELF_HWCAP yields a mask that user programs can use to figure out what
210 instruction set this cpu supports. This could be done in userspace,
211 but it's not easy, and we've already done it here. */
212# define ELF_HWCAP (cur_cpu_spec->cpu_user_features)
213
214/* This yields a string that ld.so will use to load implementation
215 specific libraries for optimization. This is more specific in
216 intent than poking at uname or /proc/cpuinfo. */
217
218#define ELF_PLATFORM (cur_cpu_spec->platform)
219
220/* While ELF_PLATFORM indicates the ISA supported by the platform, it
221 * may not accurately reflect the underlying behavior of the hardware
222 * (as in the case of running in Power5+ compatibility mode on a
223 * Power6 machine). ELF_BASE_PLATFORM allows ld.so to load libraries
224 * that are tuned for the real hardware.
225 */
226#define ELF_BASE_PLATFORM (powerpc_base_platform)
227
228#ifdef __powerpc64__
229# define ELF_PLAT_INIT(_r, load_addr) do { \
230 _r->gpr[2] = load_addr; \
231} while (0)
232#endif /* __powerpc64__ */
233
234#ifdef __powerpc64__
235# define SET_PERSONALITY(ex, ibcs2) \
236do { \
237 unsigned long new_flags = 0; \
238 if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
239 new_flags = _TIF_32BIT; \
240 if ((current_thread_info()->flags & _TIF_32BIT) \
241 != new_flags) \
242 set_thread_flag(TIF_ABI_PENDING); \
243 else \
244 clear_thread_flag(TIF_ABI_PENDING); \
245 if (personality(current->personality) != PER_LINUX32) \
246 set_personality(PER_LINUX | \
247 (current->personality & (~PER_MASK))); \
248} while (0)
249/*
250 * An executable for which elf_read_implies_exec() returns TRUE will
251 * have the READ_IMPLIES_EXEC personality flag set automatically. This
252 * is only required to work around bugs in old 32bit toolchains. Since
253 * the 64bit ABI has never had these issues dont enable the workaround
254 * even if we have an executable stack.
255 */
256# define elf_read_implies_exec(ex, exec_stk) (test_thread_flag(TIF_32BIT) ? \
257 (exec_stk != EXSTACK_DISABLE_X) : 0)
258#else
259# define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
260#endif /* __powerpc64__ */
261
262extern int dcache_bsize;
263extern int icache_bsize;
264extern int ucache_bsize;
265
266/* vDSO has arch_setup_additional_pages */
267#define ARCH_HAS_SETUP_ADDITIONAL_PAGES
268struct linux_binprm;
269extern int arch_setup_additional_pages(struct linux_binprm *bprm,
270 int executable_stack);
271#define VDSO_AUX_ENT(a,b) NEW_AUX_ENT(a,b);
272
273#endif /* __KERNEL__ */
274
275/*
276 * The requirements here are:
277 * - keep the final alignment of sp (sp & 0xf)
278 * - make sure the 32-bit value at the first 16 byte aligned position of
279 * AUXV is greater than 16 for glibc compatibility.
280 * AT_IGNOREPPC is used for that.
281 * - for compatibility with glibc ARCH_DLINFO must always be defined on PPC,
282 * even if DLINFO_ARCH_ITEMS goes to zero or is undefined.
283 * update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes
284 */
285#define ARCH_DLINFO \
286do { \
287 /* Handle glibc compatibility. */ \
288 NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
289 NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
290 /* Cache size items */ \
291 NEW_AUX_ENT(AT_DCACHEBSIZE, dcache_bsize); \
292 NEW_AUX_ENT(AT_ICACHEBSIZE, icache_bsize); \
293 NEW_AUX_ENT(AT_UCACHEBSIZE, ucache_bsize); \
294 VDSO_AUX_ENT(AT_SYSINFO_EHDR, current->mm->context.vdso_base) \
295} while (0)
296
297/* PowerPC64 relocations defined by the ABIs */
298#define R_PPC64_NONE R_PPC_NONE
299#define R_PPC64_ADDR32 R_PPC_ADDR32 /* 32bit absolute address. */
300#define R_PPC64_ADDR24 R_PPC_ADDR24 /* 26bit address, word aligned. */
301#define R_PPC64_ADDR16 R_PPC_ADDR16 /* 16bit absolute address. */
302#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of abs. address. */
303#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of abs. address. */
304#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits. */
305#define R_PPC64_ADDR14 R_PPC_ADDR14 /* 16bit address, word aligned. */
306#define R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN
307#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN
308#define R_PPC64_REL24 R_PPC_REL24 /* PC relative 26 bit, word aligned. */
309#define R_PPC64_REL14 R_PPC_REL14 /* PC relative 16 bit. */
310#define R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN
311#define R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN
312#define R_PPC64_GOT16 R_PPC_GOT16
313#define R_PPC64_GOT16_LO R_PPC_GOT16_LO
314#define R_PPC64_GOT16_HI R_PPC_GOT16_HI
315#define R_PPC64_GOT16_HA R_PPC_GOT16_HA
316
317#define R_PPC64_COPY R_PPC_COPY
318#define R_PPC64_GLOB_DAT R_PPC_GLOB_DAT
319#define R_PPC64_JMP_SLOT R_PPC_JMP_SLOT
320#define R_PPC64_RELATIVE R_PPC_RELATIVE
321
322#define R_PPC64_UADDR32 R_PPC_UADDR32
323#define R_PPC64_UADDR16 R_PPC_UADDR16
324#define R_PPC64_REL32 R_PPC_REL32
325#define R_PPC64_PLT32 R_PPC_PLT32
326#define R_PPC64_PLTREL32 R_PPC_PLTREL32
327#define R_PPC64_PLT16_LO R_PPC_PLT16_LO
328#define R_PPC64_PLT16_HI R_PPC_PLT16_HI
329#define R_PPC64_PLT16_HA R_PPC_PLT16_HA
330
331#define R_PPC64_SECTOFF R_PPC_SECTOFF
332#define R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO
333#define R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI
334#define R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA
335#define R_PPC64_ADDR30 37 /* word30 (S + A - P) >> 2. */
336#define R_PPC64_ADDR64 38 /* doubleword64 S + A. */
337#define R_PPC64_ADDR16_HIGHER 39 /* half16 #higher(S + A). */
338#define R_PPC64_ADDR16_HIGHERA 40 /* half16 #highera(S + A). */
339#define R_PPC64_ADDR16_HIGHEST 41 /* half16 #highest(S + A). */
340#define R_PPC64_ADDR16_HIGHESTA 42 /* half16 #highesta(S + A). */
341#define R_PPC64_UADDR64 43 /* doubleword64 S + A. */
342#define R_PPC64_REL64 44 /* doubleword64 S + A - P. */
343#define R_PPC64_PLT64 45 /* doubleword64 L + A. */
344#define R_PPC64_PLTREL64 46 /* doubleword64 L + A - P. */
345#define R_PPC64_TOC16 47 /* half16* S + A - .TOC. */
346#define R_PPC64_TOC16_LO 48 /* half16 #lo(S + A - .TOC.). */
347#define R_PPC64_TOC16_HI 49 /* half16 #hi(S + A - .TOC.). */
348#define R_PPC64_TOC16_HA 50 /* half16 #ha(S + A - .TOC.). */
349#define R_PPC64_TOC 51 /* doubleword64 .TOC. */
350#define R_PPC64_PLTGOT16 52 /* half16* M + A. */
351#define R_PPC64_PLTGOT16_LO 53 /* half16 #lo(M + A). */
352#define R_PPC64_PLTGOT16_HI 54 /* half16 #hi(M + A). */
353#define R_PPC64_PLTGOT16_HA 55 /* half16 #ha(M + A). */
354
355#define R_PPC64_ADDR16_DS 56 /* half16ds* (S + A) >> 2. */
356#define R_PPC64_ADDR16_LO_DS 57 /* half16ds #lo(S + A) >> 2. */
357#define R_PPC64_GOT16_DS 58 /* half16ds* (G + A) >> 2. */
358#define R_PPC64_GOT16_LO_DS 59 /* half16ds #lo(G + A) >> 2. */
359#define R_PPC64_PLT16_LO_DS 60 /* half16ds #lo(L + A) >> 2. */
360#define R_PPC64_SECTOFF_DS 61 /* half16ds* (R + A) >> 2. */
361#define R_PPC64_SECTOFF_LO_DS 62 /* half16ds #lo(R + A) >> 2. */
362#define R_PPC64_TOC16_DS 63 /* half16ds* (S + A - .TOC.) >> 2. */
363#define R_PPC64_TOC16_LO_DS 64 /* half16ds #lo(S + A - .TOC.) >> 2. */
364#define R_PPC64_PLTGOT16_DS 65 /* half16ds* (M + A) >> 2. */
365#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds #lo(M + A) >> 2. */
366
367/* PowerPC64 relocations defined for the TLS access ABI. */
368#define R_PPC64_TLS 67 /* none (sym+add)@tls */
369#define R_PPC64_DTPMOD64 68 /* doubleword64 (sym+add)@dtpmod */
370#define R_PPC64_TPREL16 69 /* half16* (sym+add)@tprel */
371#define R_PPC64_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */
372#define R_PPC64_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */
373#define R_PPC64_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */
374#define R_PPC64_TPREL64 73 /* doubleword64 (sym+add)@tprel */
375#define R_PPC64_DTPREL16 74 /* half16* (sym+add)@dtprel */
376#define R_PPC64_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */
377#define R_PPC64_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */
378#define R_PPC64_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */
379#define R_PPC64_DTPREL64 78 /* doubleword64 (sym+add)@dtprel */
380#define R_PPC64_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */
381#define R_PPC64_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */
382#define R_PPC64_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */
383#define R_PPC64_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */
384#define R_PPC64_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */
385#define R_PPC64_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */
386#define R_PPC64_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */
387#define R_PPC64_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */
388#define R_PPC64_GOT_TPREL16_DS 87 /* half16ds* (sym+add)@got@tprel */
389#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */
390#define R_PPC64_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */
391#define R_PPC64_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */
392#define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */
393#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */
394#define R_PPC64_GOT_DTPREL16_HI 93 /* half16 (sym+add)@got@dtprel@h */
395#define R_PPC64_GOT_DTPREL16_HA 94 /* half16 (sym+add)@got@dtprel@ha */
396#define R_PPC64_TPREL16_DS 95 /* half16ds* (sym+add)@tprel */
397#define R_PPC64_TPREL16_LO_DS 96 /* half16ds (sym+add)@tprel@l */
398#define R_PPC64_TPREL16_HIGHER 97 /* half16 (sym+add)@tprel@higher */
399#define R_PPC64_TPREL16_HIGHERA 98 /* half16 (sym+add)@tprel@highera */
400#define R_PPC64_TPREL16_HIGHEST 99 /* half16 (sym+add)@tprel@highest */
401#define R_PPC64_TPREL16_HIGHESTA 100 /* half16 (sym+add)@tprel@highesta */
402#define R_PPC64_DTPREL16_DS 101 /* half16ds* (sym+add)@dtprel */
403#define R_PPC64_DTPREL16_LO_DS 102 /* half16ds (sym+add)@dtprel@l */
404#define R_PPC64_DTPREL16_HIGHER 103 /* half16 (sym+add)@dtprel@higher */
405#define R_PPC64_DTPREL16_HIGHERA 104 /* half16 (sym+add)@dtprel@highera */
406#define R_PPC64_DTPREL16_HIGHEST 105 /* half16 (sym+add)@dtprel@highest */
407#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */
408
409/* Keep this the last entry. */
410#define R_PPC64_NUM 107
411
412#ifdef __KERNEL__
413
414#ifdef CONFIG_SPU_BASE
415/* Notes used in ET_CORE. Note name is "SPU/<fd>/<filename>". */
416#define NT_SPU 1
417
418#define ARCH_HAVE_EXTRA_ELF_NOTES
419
420#endif /* CONFIG_SPU_BASE */
421
422#endif /* __KERNEL */
423
424#endif /* _ASM_POWERPC_ELF_H */
diff --git a/include/asm-powerpc/emergency-restart.h b/include/asm-powerpc/emergency-restart.h
deleted file mode 100644
index 3711bd9d50b..00000000000
--- a/include/asm-powerpc/emergency-restart.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/emergency-restart.h>
diff --git a/include/asm-powerpc/errno.h b/include/asm-powerpc/errno.h
deleted file mode 100644
index 8c145fd17d8..00000000000
--- a/include/asm-powerpc/errno.h
+++ /dev/null
@@ -1,11 +0,0 @@
1#ifndef _ASM_POWERPC_ERRNO_H
2#define _ASM_POWERPC_ERRNO_H
3
4#include <asm-generic/errno.h>
5
6#undef EDEADLOCK
7#define EDEADLOCK 58 /* File locking deadlock error */
8
9#define _LAST_ERRNO 516
10
11#endif /* _ASM_POWERPC_ERRNO_H */
diff --git a/include/asm-powerpc/exception.h b/include/asm-powerpc/exception.h
deleted file mode 100644
index 329148b5acc..00000000000
--- a/include/asm-powerpc/exception.h
+++ /dev/null
@@ -1,311 +0,0 @@
1#ifndef _ASM_POWERPC_EXCEPTION_H
2#define _ASM_POWERPC_EXCEPTION_H
3/*
4 * Extracted from head_64.S
5 *
6 * PowerPC version
7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
8 *
9 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
10 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
11 * Adapted for Power Macintosh by Paul Mackerras.
12 * Low-level exception handlers and MMU support
13 * rewritten by Paul Mackerras.
14 * Copyright (C) 1996 Paul Mackerras.
15 *
16 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
17 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
18 *
19 * This file contains the low-level support and setup for the
20 * PowerPC-64 platform, including trap and interrupt dispatch.
21 *
22 * This program is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU General Public License
24 * as published by the Free Software Foundation; either version
25 * 2 of the License, or (at your option) any later version.
26 */
27/*
28 * The following macros define the code that appears as
29 * the prologue to each of the exception handlers. They
30 * are split into two parts to allow a single kernel binary
31 * to be used for pSeries and iSeries.
32 *
33 * We make as much of the exception code common between native
34 * exception handlers (including pSeries LPAR) and iSeries LPAR
35 * implementations as possible.
36 */
37
38#define EX_R9 0
39#define EX_R10 8
40#define EX_R11 16
41#define EX_R12 24
42#define EX_R13 32
43#define EX_SRR0 40
44#define EX_DAR 48
45#define EX_DSISR 56
46#define EX_CCR 60
47#define EX_R3 64
48#define EX_LR 72
49
50/*
51 * We're short on space and time in the exception prolog, so we can't
52 * use the normal SET_REG_IMMEDIATE macro. Normally we just need the
53 * low halfword of the address, but for Kdump we need the whole low
54 * word.
55 */
56#ifdef CONFIG_CRASH_DUMP
57#define LOAD_HANDLER(reg, label) \
58 oris reg,reg,(label)@h; /* virt addr of handler ... */ \
59 ori reg,reg,(label)@l; /* .. and the rest */
60#else
61#define LOAD_HANDLER(reg, label) \
62 ori reg,reg,(label)@l; /* virt addr of handler ... */
63#endif
64
65#define EXCEPTION_PROLOG_1(area) \
66 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
67 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
68 std r10,area+EX_R10(r13); \
69 std r11,area+EX_R11(r13); \
70 std r12,area+EX_R12(r13); \
71 mfspr r9,SPRN_SPRG1; \
72 std r9,area+EX_R13(r13); \
73 mfcr r9
74
75/*
76 * Equal to EXCEPTION_PROLOG_PSERIES, except that it forces 64bit mode.
77 * The firmware calls the registered system_reset_fwnmi and
78 * machine_check_fwnmi handlers in 32bit mode if the cpu happens to run
79 * a 32bit application at the time of the event.
80 * This firmware bug is present on POWER4 and JS20.
81 */
82#define EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(area, label) \
83 EXCEPTION_PROLOG_1(area); \
84 clrrdi r12,r13,32; /* get high part of &label */ \
85 mfmsr r10; \
86 /* force 64bit mode */ \
87 li r11,5; /* MSR_SF_LG|MSR_ISF_LG */ \
88 rldimi r10,r11,61,0; /* insert into top 3 bits */ \
89 /* done 64bit mode */ \
90 mfspr r11,SPRN_SRR0; /* save SRR0 */ \
91 LOAD_HANDLER(r12,label) \
92 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
93 mtspr SPRN_SRR0,r12; \
94 mfspr r12,SPRN_SRR1; /* and SRR1 */ \
95 mtspr SPRN_SRR1,r10; \
96 rfid; \
97 b . /* prevent speculative execution */
98
99#define EXCEPTION_PROLOG_PSERIES(area, label) \
100 EXCEPTION_PROLOG_1(area); \
101 clrrdi r12,r13,32; /* get high part of &label */ \
102 mfmsr r10; \
103 mfspr r11,SPRN_SRR0; /* save SRR0 */ \
104 LOAD_HANDLER(r12,label) \
105 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
106 mtspr SPRN_SRR0,r12; \
107 mfspr r12,SPRN_SRR1; /* and SRR1 */ \
108 mtspr SPRN_SRR1,r10; \
109 rfid; \
110 b . /* prevent speculative execution */
111
112/*
113 * The common exception prolog is used for all except a few exceptions
114 * such as a segment miss on a kernel address. We have to be prepared
115 * to take another exception from the point where we first touch the
116 * kernel stack onwards.
117 *
118 * On entry r13 points to the paca, r9-r13 are saved in the paca,
119 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
120 * SRR1, and relocation is on.
121 */
122#define EXCEPTION_PROLOG_COMMON(n, area) \
123 andi. r10,r12,MSR_PR; /* See if coming from user */ \
124 mr r10,r1; /* Save r1 */ \
125 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
126 beq- 1f; \
127 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
1281: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \
129 bge- cr1,2f; /* abort if it is */ \
130 b 3f; \
1312: li r1,(n); /* will be reloaded later */ \
132 sth r1,PACA_TRAP_SAVE(r13); \
133 b bad_stack; \
1343: std r9,_CCR(r1); /* save CR in stackframe */ \
135 std r11,_NIP(r1); /* save SRR0 in stackframe */ \
136 std r12,_MSR(r1); /* save SRR1 in stackframe */ \
137 std r10,0(r1); /* make stack chain pointer */ \
138 std r0,GPR0(r1); /* save r0 in stackframe */ \
139 std r10,GPR1(r1); /* save r1 in stackframe */ \
140 ACCOUNT_CPU_USER_ENTRY(r9, r10); \
141 std r2,GPR2(r1); /* save r2 in stackframe */ \
142 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
143 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
144 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
145 ld r10,area+EX_R10(r13); \
146 std r9,GPR9(r1); \
147 std r10,GPR10(r1); \
148 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \
149 ld r10,area+EX_R12(r13); \
150 ld r11,area+EX_R13(r13); \
151 std r9,GPR11(r1); \
152 std r10,GPR12(r1); \
153 std r11,GPR13(r1); \
154 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
155 mflr r9; /* save LR in stackframe */ \
156 std r9,_LINK(r1); \
157 mfctr r10; /* save CTR in stackframe */ \
158 std r10,_CTR(r1); \
159 lbz r10,PACASOFTIRQEN(r13); \
160 mfspr r11,SPRN_XER; /* save XER in stackframe */ \
161 std r10,SOFTE(r1); \
162 std r11,_XER(r1); \
163 li r9,(n)+1; \
164 std r9,_TRAP(r1); /* set trap number */ \
165 li r10,0; \
166 ld r11,exception_marker@toc(r2); \
167 std r10,RESULT(r1); /* clear regs->result */ \
168 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
169
170/*
171 * Exception vectors.
172 */
173#define STD_EXCEPTION_PSERIES(n, label) \
174 . = n; \
175 .globl label##_pSeries; \
176label##_pSeries: \
177 HMT_MEDIUM; \
178 mtspr SPRN_SPRG1,r13; /* save r13 */ \
179 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
180
181#define HSTD_EXCEPTION_PSERIES(n, label) \
182 . = n; \
183 .globl label##_pSeries; \
184label##_pSeries: \
185 HMT_MEDIUM; \
186 mtspr SPRN_SPRG1,r20; /* save r20 */ \
187 mfspr r20,SPRN_HSRR0; /* copy HSRR0 to SRR0 */ \
188 mtspr SPRN_SRR0,r20; \
189 mfspr r20,SPRN_HSRR1; /* copy HSRR0 to SRR0 */ \
190 mtspr SPRN_SRR1,r20; \
191 mfspr r20,SPRN_SPRG1; /* restore r20 */ \
192 mtspr SPRN_SPRG1,r13; /* save r13 */ \
193 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
194
195
196#define MASKABLE_EXCEPTION_PSERIES(n, label) \
197 . = n; \
198 .globl label##_pSeries; \
199label##_pSeries: \
200 HMT_MEDIUM; \
201 mtspr SPRN_SPRG1,r13; /* save r13 */ \
202 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
203 std r9,PACA_EXGEN+EX_R9(r13); /* save r9, r10 */ \
204 std r10,PACA_EXGEN+EX_R10(r13); \
205 lbz r10,PACASOFTIRQEN(r13); \
206 mfcr r9; \
207 cmpwi r10,0; \
208 beq masked_interrupt; \
209 mfspr r10,SPRN_SPRG1; \
210 std r10,PACA_EXGEN+EX_R13(r13); \
211 std r11,PACA_EXGEN+EX_R11(r13); \
212 std r12,PACA_EXGEN+EX_R12(r13); \
213 clrrdi r12,r13,32; /* get high part of &label */ \
214 mfmsr r10; \
215 mfspr r11,SPRN_SRR0; /* save SRR0 */ \
216 LOAD_HANDLER(r12,label##_common) \
217 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
218 mtspr SPRN_SRR0,r12; \
219 mfspr r12,SPRN_SRR1; /* and SRR1 */ \
220 mtspr SPRN_SRR1,r10; \
221 rfid; \
222 b . /* prevent speculative execution */
223
224#ifdef CONFIG_PPC_ISERIES
225#define DISABLE_INTS \
226 li r11,0; \
227 stb r11,PACASOFTIRQEN(r13); \
228BEGIN_FW_FTR_SECTION; \
229 stb r11,PACAHARDIRQEN(r13); \
230END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES); \
231 TRACE_DISABLE_INTS; \
232BEGIN_FW_FTR_SECTION; \
233 mfmsr r10; \
234 ori r10,r10,MSR_EE; \
235 mtmsrd r10,1; \
236END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
237#else
238#define DISABLE_INTS \
239 li r11,0; \
240 stb r11,PACASOFTIRQEN(r13); \
241 stb r11,PACAHARDIRQEN(r13); \
242 TRACE_DISABLE_INTS
243#endif /* CONFIG_PPC_ISERIES */
244
245#define ENABLE_INTS \
246 ld r12,_MSR(r1); \
247 mfmsr r11; \
248 rlwimi r11,r12,0,MSR_EE; \
249 mtmsrd r11,1
250
251#define STD_EXCEPTION_COMMON(trap, label, hdlr) \
252 .align 7; \
253 .globl label##_common; \
254label##_common: \
255 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
256 DISABLE_INTS; \
257 bl .save_nvgprs; \
258 addi r3,r1,STACK_FRAME_OVERHEAD; \
259 bl hdlr; \
260 b .ret_from_except
261
262/*
263 * Like STD_EXCEPTION_COMMON, but for exceptions that can occur
264 * in the idle task and therefore need the special idle handling.
265 */
266#define STD_EXCEPTION_COMMON_IDLE(trap, label, hdlr) \
267 .align 7; \
268 .globl label##_common; \
269label##_common: \
270 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
271 FINISH_NAP; \
272 DISABLE_INTS; \
273 bl .save_nvgprs; \
274 addi r3,r1,STACK_FRAME_OVERHEAD; \
275 bl hdlr; \
276 b .ret_from_except
277
278#define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \
279 .align 7; \
280 .globl label##_common; \
281label##_common: \
282 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
283 FINISH_NAP; \
284 DISABLE_INTS; \
285BEGIN_FTR_SECTION \
286 bl .ppc64_runlatch_on; \
287END_FTR_SECTION_IFSET(CPU_FTR_CTRL) \
288 addi r3,r1,STACK_FRAME_OVERHEAD; \
289 bl hdlr; \
290 b .ret_from_except_lite
291
292/*
293 * When the idle code in power4_idle puts the CPU into NAP mode,
294 * it has to do so in a loop, and relies on the external interrupt
295 * and decrementer interrupt entry code to get it out of the loop.
296 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags
297 * to signal that it is in the loop and needs help to get out.
298 */
299#ifdef CONFIG_PPC_970_NAP
300#define FINISH_NAP \
301BEGIN_FTR_SECTION \
302 clrrdi r11,r1,THREAD_SHIFT; \
303 ld r9,TI_LOCAL_FLAGS(r11); \
304 andi. r10,r9,_TLF_NAPPING; \
305 bnel power4_fixup_nap; \
306END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
307#else
308#define FINISH_NAP
309#endif
310
311#endif /* _ASM_POWERPC_EXCEPTION_H */
diff --git a/include/asm-powerpc/fb.h b/include/asm-powerpc/fb.h
deleted file mode 100644
index 411af8d17a6..00000000000
--- a/include/asm-powerpc/fb.h
+++ /dev/null
@@ -1,21 +0,0 @@
1#ifndef _ASM_FB_H_
2#define _ASM_FB_H_
3
4#include <linux/fb.h>
5#include <linux/fs.h>
6#include <asm/page.h>
7
8static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
9 unsigned long off)
10{
11 vma->vm_page_prot = phys_mem_access_prot(file, off >> PAGE_SHIFT,
12 vma->vm_end - vma->vm_start,
13 vma->vm_page_prot);
14}
15
16static inline int fb_is_primary_device(struct fb_info *info)
17{
18 return 0;
19}
20
21#endif /* _ASM_FB_H_ */
diff --git a/include/asm-powerpc/fcntl.h b/include/asm-powerpc/fcntl.h
deleted file mode 100644
index ce5c4516d40..00000000000
--- a/include/asm-powerpc/fcntl.h
+++ /dev/null
@@ -1,11 +0,0 @@
1#ifndef _ASM_FCNTL_H
2#define _ASM_FCNTL_H
3
4#define O_DIRECTORY 040000 /* must be a directory */
5#define O_NOFOLLOW 0100000 /* don't follow links */
6#define O_LARGEFILE 0200000
7#define O_DIRECT 0400000 /* direct disk access hint */
8
9#include <asm-generic/fcntl.h>
10
11#endif /* _ASM_FCNTL_H */
diff --git a/include/asm-powerpc/feature-fixups.h b/include/asm-powerpc/feature-fixups.h
deleted file mode 100644
index a1029967620..00000000000
--- a/include/asm-powerpc/feature-fixups.h
+++ /dev/null
@@ -1,126 +0,0 @@
1#ifndef __ASM_POWERPC_FEATURE_FIXUPS_H
2#define __ASM_POWERPC_FEATURE_FIXUPS_H
3
4/*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10
11#ifdef __ASSEMBLY__
12
13/*
14 * Feature section common macros
15 *
16 * Note that the entries now contain offsets between the table entry
17 * and the code rather than absolute code pointers in order to be
18 * useable with the vdso shared library. There is also an assumption
19 * that values will be negative, that is, the fixup table has to be
20 * located after the code it fixes up.
21 */
22#if defined(CONFIG_PPC64) && !defined(__powerpc64__)
23/* 64 bits kernel, 32 bits code (ie. vdso32) */
24#define FTR_ENTRY_LONG .llong
25#define FTR_ENTRY_OFFSET .long 0xffffffff; .long
26#else
27/* 64 bit kernel 64 bit code, or 32 bit kernel 32 bit code */
28#define FTR_ENTRY_LONG PPC_LONG
29#define FTR_ENTRY_OFFSET PPC_LONG
30#endif
31
32#define START_FTR_SECTION(label) label##1:
33
34#define FTR_SECTION_ELSE_NESTED(label) \
35label##2: \
36 .pushsection __ftr_alt_##label,"a"; \
37 .align 2; \
38label##3:
39
40#define MAKE_FTR_SECTION_ENTRY(msk, val, label, sect) \
41label##4: \
42 .popsection; \
43 .pushsection sect,"a"; \
44 .align 3; \
45label##5: \
46 FTR_ENTRY_LONG msk; \
47 FTR_ENTRY_LONG val; \
48 FTR_ENTRY_OFFSET label##1b-label##5b; \
49 FTR_ENTRY_OFFSET label##2b-label##5b; \
50 FTR_ENTRY_OFFSET label##3b-label##5b; \
51 FTR_ENTRY_OFFSET label##4b-label##5b; \
52 .popsection;
53
54
55/* CPU feature dependent sections */
56#define BEGIN_FTR_SECTION_NESTED(label) START_FTR_SECTION(label)
57#define BEGIN_FTR_SECTION START_FTR_SECTION(97)
58
59#define END_FTR_SECTION_NESTED(msk, val, label) \
60 FTR_SECTION_ELSE_NESTED(label) \
61 MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup)
62
63#define END_FTR_SECTION(msk, val) \
64 END_FTR_SECTION_NESTED(msk, val, 97)
65
66#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
67#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
68
69/* CPU feature sections with alternatives, use BEGIN_FTR_SECTION to start */
70#define FTR_SECTION_ELSE FTR_SECTION_ELSE_NESTED(97)
71#define ALT_FTR_SECTION_END_NESTED(msk, val, label) \
72 MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup)
73#define ALT_FTR_SECTION_END_NESTED_IFSET(msk, label) \
74 ALT_FTR_SECTION_END_NESTED(msk, msk, label)
75#define ALT_FTR_SECTION_END_NESTED_IFCLR(msk, label) \
76 ALT_FTR_SECTION_END_NESTED(msk, 0, label)
77#define ALT_FTR_SECTION_END(msk, val) \
78 ALT_FTR_SECTION_END_NESTED(msk, val, 97)
79#define ALT_FTR_SECTION_END_IFSET(msk) \
80 ALT_FTR_SECTION_END_NESTED_IFSET(msk, 97)
81#define ALT_FTR_SECTION_END_IFCLR(msk) \
82 ALT_FTR_SECTION_END_NESTED_IFCLR(msk, 97)
83
84/* Firmware feature dependent sections */
85#define BEGIN_FW_FTR_SECTION_NESTED(label) START_FTR_SECTION(label)
86#define BEGIN_FW_FTR_SECTION START_FTR_SECTION(97)
87
88#define END_FW_FTR_SECTION_NESTED(msk, val, label) \
89 FTR_SECTION_ELSE_NESTED(label) \
90 MAKE_FTR_SECTION_ENTRY(msk, val, label, __fw_ftr_fixup)
91
92#define END_FW_FTR_SECTION(msk, val) \
93 END_FW_FTR_SECTION_NESTED(msk, val, 97)
94
95#define END_FW_FTR_SECTION_IFSET(msk) END_FW_FTR_SECTION((msk), (msk))
96#define END_FW_FTR_SECTION_IFCLR(msk) END_FW_FTR_SECTION((msk), 0)
97
98/* Firmware feature sections with alternatives */
99#define FW_FTR_SECTION_ELSE_NESTED(label) FTR_SECTION_ELSE_NESTED(label)
100#define FW_FTR_SECTION_ELSE FTR_SECTION_ELSE_NESTED(97)
101#define ALT_FW_FTR_SECTION_END_NESTED(msk, val, label) \
102 MAKE_FTR_SECTION_ENTRY(msk, val, label, __fw_ftr_fixup)
103#define ALT_FW_FTR_SECTION_END_NESTED_IFSET(msk, label) \
104 ALT_FW_FTR_SECTION_END_NESTED(msk, msk, label)
105#define ALT_FW_FTR_SECTION_END_NESTED_IFCLR(msk, label) \
106 ALT_FW_FTR_SECTION_END_NESTED(msk, 0, label)
107#define ALT_FW_FTR_SECTION_END(msk, val) \
108 ALT_FW_FTR_SECTION_END_NESTED(msk, val, 97)
109#define ALT_FW_FTR_SECTION_END_IFSET(msk) \
110 ALT_FW_FTR_SECTION_END_NESTED_IFSET(msk, 97)
111#define ALT_FW_FTR_SECTION_END_IFCLR(msk) \
112 ALT_FW_FTR_SECTION_END_NESTED_IFCLR(msk, 97)
113
114#endif /* __ASSEMBLY__ */
115
116/* LWSYNC feature sections */
117#define START_LWSYNC_SECTION(label) label##1:
118#define MAKE_LWSYNC_SECTION_ENTRY(label, sect) \
119label##2: \
120 .pushsection sect,"a"; \
121 .align 2; \
122label##3: \
123 .long label##1b-label##3b; \
124 .popsection;
125
126#endif /* __ASM_POWERPC_FEATURE_FIXUPS_H */
diff --git a/include/asm-powerpc/firmware.h b/include/asm-powerpc/firmware.h
deleted file mode 100644
index 3a179827528..00000000000
--- a/include/asm-powerpc/firmware.h
+++ /dev/null
@@ -1,132 +0,0 @@
1/*
2 * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
3 *
4 * Modifications for ppc64:
5 * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12#ifndef __ASM_POWERPC_FIRMWARE_H
13#define __ASM_POWERPC_FIRMWARE_H
14
15#ifdef __KERNEL__
16
17#include <asm/asm-compat.h>
18#include <asm/feature-fixups.h>
19
20/* firmware feature bitmask values */
21#define FIRMWARE_MAX_FEATURES 63
22
23#define FW_FEATURE_PFT ASM_CONST(0x0000000000000001)
24#define FW_FEATURE_TCE ASM_CONST(0x0000000000000002)
25#define FW_FEATURE_SPRG0 ASM_CONST(0x0000000000000004)
26#define FW_FEATURE_DABR ASM_CONST(0x0000000000000008)
27#define FW_FEATURE_COPY ASM_CONST(0x0000000000000010)
28#define FW_FEATURE_ASR ASM_CONST(0x0000000000000020)
29#define FW_FEATURE_DEBUG ASM_CONST(0x0000000000000040)
30#define FW_FEATURE_TERM ASM_CONST(0x0000000000000080)
31#define FW_FEATURE_PERF ASM_CONST(0x0000000000000100)
32#define FW_FEATURE_DUMP ASM_CONST(0x0000000000000200)
33#define FW_FEATURE_INTERRUPT ASM_CONST(0x0000000000000400)
34#define FW_FEATURE_MIGRATE ASM_CONST(0x0000000000000800)
35#define FW_FEATURE_PERFMON ASM_CONST(0x0000000000001000)
36#define FW_FEATURE_CRQ ASM_CONST(0x0000000000002000)
37#define FW_FEATURE_VIO ASM_CONST(0x0000000000004000)
38#define FW_FEATURE_RDMA ASM_CONST(0x0000000000008000)
39#define FW_FEATURE_LLAN ASM_CONST(0x0000000000010000)
40#define FW_FEATURE_BULK ASM_CONST(0x0000000000020000)
41#define FW_FEATURE_XDABR ASM_CONST(0x0000000000040000)
42#define FW_FEATURE_MULTITCE ASM_CONST(0x0000000000080000)
43#define FW_FEATURE_SPLPAR ASM_CONST(0x0000000000100000)
44#define FW_FEATURE_ISERIES ASM_CONST(0x0000000000200000)
45#define FW_FEATURE_LPAR ASM_CONST(0x0000000000400000)
46#define FW_FEATURE_PS3_LV1 ASM_CONST(0x0000000000800000)
47#define FW_FEATURE_BEAT ASM_CONST(0x0000000001000000)
48#define FW_FEATURE_BULK_REMOVE ASM_CONST(0x0000000002000000)
49#define FW_FEATURE_CMO ASM_CONST(0x0000000004000000)
50
51#ifndef __ASSEMBLY__
52
53enum {
54#ifdef CONFIG_PPC64
55 FW_FEATURE_PSERIES_POSSIBLE = FW_FEATURE_PFT | FW_FEATURE_TCE |
56 FW_FEATURE_SPRG0 | FW_FEATURE_DABR | FW_FEATURE_COPY |
57 FW_FEATURE_ASR | FW_FEATURE_DEBUG | FW_FEATURE_TERM |
58 FW_FEATURE_PERF | FW_FEATURE_DUMP | FW_FEATURE_INTERRUPT |
59 FW_FEATURE_MIGRATE | FW_FEATURE_PERFMON | FW_FEATURE_CRQ |
60 FW_FEATURE_VIO | FW_FEATURE_RDMA | FW_FEATURE_LLAN |
61 FW_FEATURE_BULK | FW_FEATURE_XDABR | FW_FEATURE_MULTITCE |
62 FW_FEATURE_SPLPAR | FW_FEATURE_LPAR | FW_FEATURE_CMO,
63 FW_FEATURE_PSERIES_ALWAYS = 0,
64 FW_FEATURE_ISERIES_POSSIBLE = FW_FEATURE_ISERIES | FW_FEATURE_LPAR,
65 FW_FEATURE_ISERIES_ALWAYS = FW_FEATURE_ISERIES | FW_FEATURE_LPAR,
66 FW_FEATURE_PS3_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1,
67 FW_FEATURE_PS3_ALWAYS = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1,
68 FW_FEATURE_CELLEB_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_BEAT,
69 FW_FEATURE_CELLEB_ALWAYS = 0,
70 FW_FEATURE_NATIVE_POSSIBLE = 0,
71 FW_FEATURE_NATIVE_ALWAYS = 0,
72 FW_FEATURE_POSSIBLE =
73#ifdef CONFIG_PPC_PSERIES
74 FW_FEATURE_PSERIES_POSSIBLE |
75#endif
76#ifdef CONFIG_PPC_ISERIES
77 FW_FEATURE_ISERIES_POSSIBLE |
78#endif
79#ifdef CONFIG_PPC_PS3
80 FW_FEATURE_PS3_POSSIBLE |
81#endif
82#ifdef CONFIG_PPC_CELLEB
83 FW_FEATURE_CELLEB_POSSIBLE |
84#endif
85#ifdef CONFIG_PPC_NATIVE
86 FW_FEATURE_NATIVE_ALWAYS |
87#endif
88 0,
89 FW_FEATURE_ALWAYS =
90#ifdef CONFIG_PPC_PSERIES
91 FW_FEATURE_PSERIES_ALWAYS &
92#endif
93#ifdef CONFIG_PPC_ISERIES
94 FW_FEATURE_ISERIES_ALWAYS &
95#endif
96#ifdef CONFIG_PPC_PS3
97 FW_FEATURE_PS3_ALWAYS &
98#endif
99#ifdef CONFIG_PPC_CELLEB
100 FW_FEATURE_CELLEB_ALWAYS &
101#endif
102#ifdef CONFIG_PPC_NATIVE
103 FW_FEATURE_NATIVE_ALWAYS &
104#endif
105 FW_FEATURE_POSSIBLE,
106
107#else /* CONFIG_PPC64 */
108 FW_FEATURE_POSSIBLE = 0,
109 FW_FEATURE_ALWAYS = 0,
110#endif
111};
112
113/* This is used to identify firmware features which are available
114 * to the kernel.
115 */
116extern unsigned long powerpc_firmware_features;
117
118#define firmware_has_feature(feature) \
119 ((FW_FEATURE_ALWAYS & (feature)) || \
120 (FW_FEATURE_POSSIBLE & powerpc_firmware_features & (feature)))
121
122extern void system_reset_fwnmi(void);
123extern void machine_check_fwnmi(void);
124
125/* This is true if we are using the firmware NMI handler (typically LPAR) */
126extern int fwnmi_active;
127
128extern unsigned int __start___fw_ftr_fixup, __stop___fw_ftr_fixup;
129
130#endif /* __ASSEMBLY__ */
131#endif /* __KERNEL__ */
132#endif /* __ASM_POWERPC_FIRMWARE_H */
diff --git a/include/asm-powerpc/fixmap.h b/include/asm-powerpc/fixmap.h
deleted file mode 100644
index 8428b38a3d3..00000000000
--- a/include/asm-powerpc/fixmap.h
+++ /dev/null
@@ -1,106 +0,0 @@
1/*
2 * fixmap.h: compile-time virtual memory allocation
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1998 Ingo Molnar
9 *
10 * Copyright 2008 Freescale Semiconductor Inc.
11 * Port to powerpc added by Kumar Gala
12 */
13
14#ifndef _ASM_FIXMAP_H
15#define _ASM_FIXMAP_H
16
17extern unsigned long FIXADDR_TOP;
18
19#ifndef __ASSEMBLY__
20#include <linux/kernel.h>
21#include <asm/page.h>
22#ifdef CONFIG_HIGHMEM
23#include <linux/threads.h>
24#include <asm/kmap_types.h>
25#endif
26
27/*
28 * Here we define all the compile-time 'special' virtual
29 * addresses. The point is to have a constant address at
30 * compile time, but to set the physical address only
31 * in the boot process. We allocate these special addresses
32 * from the end of virtual memory (0xfffff000) backwards.
33 * Also this lets us do fail-safe vmalloc(), we
34 * can guarantee that these special addresses and
35 * vmalloc()-ed addresses never overlap.
36 *
37 * these 'compile-time allocated' memory buffers are
38 * fixed-size 4k pages. (or larger if used with an increment
39 * highger than 1) use fixmap_set(idx,phys) to associate
40 * physical memory with fixmap indices.
41 *
42 * TLB entries of such buffers will not be flushed across
43 * task switches.
44 */
45enum fixed_addresses {
46 FIX_HOLE,
47#ifdef CONFIG_HIGHMEM
48 FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */
49 FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
50#endif
51 /* FIX_PCIE_MCFG, */
52 __end_of_fixed_addresses
53};
54
55extern void __set_fixmap (enum fixed_addresses idx,
56 phys_addr_t phys, pgprot_t flags);
57
58#define set_fixmap(idx, phys) \
59 __set_fixmap(idx, phys, PAGE_KERNEL)
60/*
61 * Some hardware wants to get fixmapped without caching.
62 */
63#define set_fixmap_nocache(idx, phys) \
64 __set_fixmap(idx, phys, PAGE_KERNEL_NOCACHE)
65
66#define clear_fixmap(idx) \
67 __set_fixmap(idx, 0, __pgprot(0))
68
69#define __FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT)
70#define FIXADDR_START (FIXADDR_TOP - __FIXADDR_SIZE)
71
72#define __fix_to_virt(x) (FIXADDR_TOP - ((x) << PAGE_SHIFT))
73#define __virt_to_fix(x) ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
74
75extern void __this_fixmap_does_not_exist(void);
76
77/*
78 * 'index to address' translation. If anyone tries to use the idx
79 * directly without tranlation, we catch the bug with a NULL-deference
80 * kernel oops. Illegal ranges of incoming indices are caught too.
81 */
82static __always_inline unsigned long fix_to_virt(const unsigned int idx)
83{
84 /*
85 * this branch gets completely eliminated after inlining,
86 * except when someone tries to use fixaddr indices in an
87 * illegal way. (such as mixing up address types or using
88 * out-of-range indices).
89 *
90 * If it doesn't get removed, the linker will complain
91 * loudly with a reasonably clear error message..
92 */
93 if (idx >= __end_of_fixed_addresses)
94 __this_fixmap_does_not_exist();
95
96 return __fix_to_virt(idx);
97}
98
99static inline unsigned long virt_to_fix(const unsigned long vaddr)
100{
101 BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
102 return __virt_to_fix(vaddr);
103}
104
105#endif /* !__ASSEMBLY__ */
106#endif
diff --git a/include/asm-powerpc/floppy.h b/include/asm-powerpc/floppy.h
deleted file mode 100644
index 24bd34c57e9..00000000000
--- a/include/asm-powerpc/floppy.h
+++ /dev/null
@@ -1,213 +0,0 @@
1/*
2 * Architecture specific parts of the Floppy driver
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1995
9 */
10#ifndef __ASM_POWERPC_FLOPPY_H
11#define __ASM_POWERPC_FLOPPY_H
12#ifdef __KERNEL__
13
14#include <asm/machdep.h>
15
16#define fd_inb(port) inb_p(port)
17#define fd_outb(value,port) outb_p(value,port)
18
19#define fd_enable_dma() enable_dma(FLOPPY_DMA)
20#define fd_disable_dma() fd_ops->_disable_dma(FLOPPY_DMA)
21#define fd_free_dma() fd_ops->_free_dma(FLOPPY_DMA)
22#define fd_clear_dma_ff() clear_dma_ff(FLOPPY_DMA)
23#define fd_set_dma_mode(mode) set_dma_mode(FLOPPY_DMA, mode)
24#define fd_set_dma_count(count) set_dma_count(FLOPPY_DMA, count)
25#define fd_get_dma_residue() fd_ops->_get_dma_residue(FLOPPY_DMA)
26#define fd_enable_irq() enable_irq(FLOPPY_IRQ)
27#define fd_disable_irq() disable_irq(FLOPPY_IRQ)
28#define fd_cacheflush(addr,size) /* nothing */
29#define fd_free_irq() free_irq(FLOPPY_IRQ, NULL);
30
31#include <linux/pci.h>
32#include <asm/ppc-pci.h> /* for isa_bridge_pcidev */
33
34#define fd_dma_setup(addr,size,mode,io) fd_ops->_dma_setup(addr,size,mode,io)
35
36static int fd_request_dma(void);
37
38struct fd_dma_ops {
39 void (*_disable_dma)(unsigned int dmanr);
40 void (*_free_dma)(unsigned int dmanr);
41 int (*_get_dma_residue)(unsigned int dummy);
42 int (*_dma_setup)(char *addr, unsigned long size, int mode, int io);
43};
44
45static int virtual_dma_count;
46static int virtual_dma_residue;
47static char *virtual_dma_addr;
48static int virtual_dma_mode;
49static int doing_vdma;
50static struct fd_dma_ops *fd_ops;
51
52static irqreturn_t floppy_hardint(int irq, void *dev_id)
53{
54 unsigned char st;
55 int lcount;
56 char *lptr;
57
58 if (!doing_vdma)
59 return floppy_interrupt(irq, dev_id);
60
61
62 st = 1;
63 for (lcount=virtual_dma_count, lptr=virtual_dma_addr;
64 lcount; lcount--, lptr++) {
65 st=inb(virtual_dma_port+4) & 0xa0 ;
66 if (st != 0xa0)
67 break;
68 if (virtual_dma_mode)
69 outb_p(*lptr, virtual_dma_port+5);
70 else
71 *lptr = inb_p(virtual_dma_port+5);
72 }
73 virtual_dma_count = lcount;
74 virtual_dma_addr = lptr;
75 st = inb(virtual_dma_port+4);
76
77 if (st == 0x20)
78 return IRQ_HANDLED;
79 if (!(st & 0x20)) {
80 virtual_dma_residue += virtual_dma_count;
81 virtual_dma_count=0;
82 doing_vdma = 0;
83 floppy_interrupt(irq, dev_id);
84 return IRQ_HANDLED;
85 }
86 return IRQ_HANDLED;
87}
88
89static void vdma_disable_dma(unsigned int dummy)
90{
91 doing_vdma = 0;
92 virtual_dma_residue += virtual_dma_count;
93 virtual_dma_count=0;
94}
95
96static void vdma_nop(unsigned int dummy)
97{
98}
99
100
101static int vdma_get_dma_residue(unsigned int dummy)
102{
103 return virtual_dma_count + virtual_dma_residue;
104}
105
106
107static int fd_request_irq(void)
108{
109 if (can_use_virtual_dma)
110 return request_irq(FLOPPY_IRQ, floppy_hardint,
111 IRQF_DISABLED, "floppy", NULL);
112 else
113 return request_irq(FLOPPY_IRQ, floppy_interrupt,
114 IRQF_DISABLED, "floppy", NULL);
115}
116
117static int vdma_dma_setup(char *addr, unsigned long size, int mode, int io)
118{
119 doing_vdma = 1;
120 virtual_dma_port = io;
121 virtual_dma_mode = (mode == DMA_MODE_WRITE);
122 virtual_dma_addr = addr;
123 virtual_dma_count = size;
124 virtual_dma_residue = 0;
125 return 0;
126}
127
128static int hard_dma_setup(char *addr, unsigned long size, int mode, int io)
129{
130 static unsigned long prev_size;
131 static dma_addr_t bus_addr = 0;
132 static char *prev_addr;
133 static int prev_dir;
134 int dir;
135
136 doing_vdma = 0;
137 dir = (mode == DMA_MODE_READ) ? PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE;
138
139 if (bus_addr
140 && (addr != prev_addr || size != prev_size || dir != prev_dir)) {
141 /* different from last time -- unmap prev */
142 pci_unmap_single(isa_bridge_pcidev, bus_addr, prev_size, prev_dir);
143 bus_addr = 0;
144 }
145
146 if (!bus_addr) /* need to map it */
147 bus_addr = pci_map_single(isa_bridge_pcidev, addr, size, dir);
148
149 /* remember this one as prev */
150 prev_addr = addr;
151 prev_size = size;
152 prev_dir = dir;
153
154 fd_clear_dma_ff();
155 fd_cacheflush(addr, size);
156 fd_set_dma_mode(mode);
157 set_dma_addr(FLOPPY_DMA, bus_addr);
158 fd_set_dma_count(size);
159 virtual_dma_port = io;
160 fd_enable_dma();
161
162 return 0;
163}
164
165static struct fd_dma_ops real_dma_ops =
166{
167 ._disable_dma = disable_dma,
168 ._free_dma = free_dma,
169 ._get_dma_residue = get_dma_residue,
170 ._dma_setup = hard_dma_setup
171};
172
173static struct fd_dma_ops virt_dma_ops =
174{
175 ._disable_dma = vdma_disable_dma,
176 ._free_dma = vdma_nop,
177 ._get_dma_residue = vdma_get_dma_residue,
178 ._dma_setup = vdma_dma_setup
179};
180
181static int fd_request_dma(void)
182{
183 if (can_use_virtual_dma & 1) {
184 fd_ops = &virt_dma_ops;
185 return 0;
186 }
187 else {
188 fd_ops = &real_dma_ops;
189 return request_dma(FLOPPY_DMA, "floppy");
190 }
191}
192
193static int FDC1 = 0x3f0;
194static int FDC2 = -1;
195
196/*
197 * Again, the CMOS information not available
198 */
199#define FLOPPY0_TYPE 6
200#define FLOPPY1_TYPE 0
201
202#define N_FDC 2 /* Don't change this! */
203#define N_DRIVE 8
204
205/*
206 * The PowerPC has no problems with floppy DMA crossing 64k borders.
207 */
208#define CROSS_64KB(a,s) (0)
209
210#define EXTRA_FLOPPY_PARAMS
211
212#endif /* __KERNEL__ */
213#endif /* __ASM_POWERPC_FLOPPY_H */
diff --git a/include/asm-powerpc/fs_pd.h b/include/asm-powerpc/fs_pd.h
deleted file mode 100644
index 9361cd5342c..00000000000
--- a/include/asm-powerpc/fs_pd.h
+++ /dev/null
@@ -1,50 +0,0 @@
1/*
2 * Platform information definitions.
3 *
4 * 2006 (c) MontaVista Software, Inc.
5 * Vitaly Bordug <vbordug@ru.mvista.com>
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12#ifndef FS_PD_H
13#define FS_PD_H
14#include <sysdev/fsl_soc.h>
15#include <asm/time.h>
16
17#ifdef CONFIG_CPM2
18#include <asm/cpm2.h>
19
20#if defined(CONFIG_8260)
21#include <asm/mpc8260.h>
22#endif
23
24#define cpm2_map(member) (&cpm2_immr->member)
25#define cpm2_map_size(member, size) (&cpm2_immr->member)
26#define cpm2_unmap(addr) do {} while(0)
27#endif
28
29#ifdef CONFIG_8xx
30#include <asm/8xx_immap.h>
31#include <asm/mpc8xx.h>
32
33extern immap_t __iomem *mpc8xx_immr;
34
35#define immr_map(member) (&mpc8xx_immr->member)
36#define immr_map_size(member, size) (&mpc8xx_immr->member)
37#define immr_unmap(addr) do {} while (0)
38#endif
39
40static inline int uart_baudrate(void)
41{
42 return get_baudrate();
43}
44
45static inline int uart_clock(void)
46{
47 return ppc_proc_freq;
48}
49
50#endif
diff --git a/include/asm-powerpc/fsl_gtm.h b/include/asm-powerpc/fsl_gtm.h
deleted file mode 100644
index 8e8c9b5032d..00000000000
--- a/include/asm-powerpc/fsl_gtm.h
+++ /dev/null
@@ -1,47 +0,0 @@
1/*
2 * Freescale General-purpose Timers Module
3 *
4 * Copyright (c) Freescale Semicondutor, Inc. 2006.
5 * Shlomi Gridish <gridish@freescale.com>
6 * Jerry Huang <Chang-Ming.Huang@freescale.com>
7 * Copyright (c) MontaVista Software, Inc. 2008.
8 * Anton Vorontsov <avorontsov@ru.mvista.com>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#ifndef __ASM_FSL_GTM_H
17#define __ASM_FSL_GTM_H
18
19#include <linux/types.h>
20
21struct gtm;
22
23struct gtm_timer {
24 unsigned int irq;
25
26 struct gtm *gtm;
27 bool requested;
28 u8 __iomem *gtcfr;
29 __be16 __iomem *gtmdr;
30 __be16 __iomem *gtpsr;
31 __be16 __iomem *gtcnr;
32 __be16 __iomem *gtrfr;
33 __be16 __iomem *gtevr;
34};
35
36extern struct gtm_timer *gtm_get_timer16(void);
37extern struct gtm_timer *gtm_get_specific_timer16(struct gtm *gtm,
38 unsigned int timer);
39extern void gtm_put_timer16(struct gtm_timer *tmr);
40extern int gtm_set_timer16(struct gtm_timer *tmr, unsigned long usec,
41 bool reload);
42extern int gtm_set_exact_timer16(struct gtm_timer *tmr, u16 usec,
43 bool reload);
44extern void gtm_stop_timer16(struct gtm_timer *tmr);
45extern void gtm_ack_timer16(struct gtm_timer *tmr, u16 events);
46
47#endif /* __ASM_FSL_GTM_H */
diff --git a/include/asm-powerpc/fsl_lbc.h b/include/asm-powerpc/fsl_lbc.h
deleted file mode 100644
index 303f5484c05..00000000000
--- a/include/asm-powerpc/fsl_lbc.h
+++ /dev/null
@@ -1,311 +0,0 @@
1/* Freescale Local Bus Controller
2 *
3 * Copyright (c) 2006-2007 Freescale Semiconductor
4 *
5 * Authors: Nick Spence <nick.spence@freescale.com>,
6 * Scott Wood <scottwood@freescale.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#ifndef __ASM_FSL_LBC_H
24#define __ASM_FSL_LBC_H
25
26#include <linux/types.h>
27#include <linux/spinlock.h>
28#include <asm/io.h>
29
30struct fsl_lbc_bank {
31 __be32 br; /**< Base Register */
32#define BR_BA 0xFFFF8000
33#define BR_BA_SHIFT 15
34#define BR_PS 0x00001800
35#define BR_PS_SHIFT 11
36#define BR_PS_8 0x00000800 /* Port Size 8 bit */
37#define BR_PS_16 0x00001000 /* Port Size 16 bit */
38#define BR_PS_32 0x00001800 /* Port Size 32 bit */
39#define BR_DECC 0x00000600
40#define BR_DECC_SHIFT 9
41#define BR_DECC_OFF 0x00000000 /* HW ECC checking and generation off */
42#define BR_DECC_CHK 0x00000200 /* HW ECC checking on, generation off */
43#define BR_DECC_CHK_GEN 0x00000400 /* HW ECC checking and generation on */
44#define BR_WP 0x00000100
45#define BR_WP_SHIFT 8
46#define BR_MSEL 0x000000E0
47#define BR_MSEL_SHIFT 5
48#define BR_MS_GPCM 0x00000000 /* GPCM */
49#define BR_MS_FCM 0x00000020 /* FCM */
50#define BR_MS_SDRAM 0x00000060 /* SDRAM */
51#define BR_MS_UPMA 0x00000080 /* UPMA */
52#define BR_MS_UPMB 0x000000A0 /* UPMB */
53#define BR_MS_UPMC 0x000000C0 /* UPMC */
54#define BR_V 0x00000001
55#define BR_V_SHIFT 0
56#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
57
58 __be32 or; /**< Base Register */
59#define OR0 0x5004
60#define OR1 0x500C
61#define OR2 0x5014
62#define OR3 0x501C
63#define OR4 0x5024
64#define OR5 0x502C
65#define OR6 0x5034
66#define OR7 0x503C
67
68#define OR_FCM_AM 0xFFFF8000
69#define OR_FCM_AM_SHIFT 15
70#define OR_FCM_BCTLD 0x00001000
71#define OR_FCM_BCTLD_SHIFT 12
72#define OR_FCM_PGS 0x00000400
73#define OR_FCM_PGS_SHIFT 10
74#define OR_FCM_CSCT 0x00000200
75#define OR_FCM_CSCT_SHIFT 9
76#define OR_FCM_CST 0x00000100
77#define OR_FCM_CST_SHIFT 8
78#define OR_FCM_CHT 0x00000080
79#define OR_FCM_CHT_SHIFT 7
80#define OR_FCM_SCY 0x00000070
81#define OR_FCM_SCY_SHIFT 4
82#define OR_FCM_SCY_1 0x00000010
83#define OR_FCM_SCY_2 0x00000020
84#define OR_FCM_SCY_3 0x00000030
85#define OR_FCM_SCY_4 0x00000040
86#define OR_FCM_SCY_5 0x00000050
87#define OR_FCM_SCY_6 0x00000060
88#define OR_FCM_SCY_7 0x00000070
89#define OR_FCM_RST 0x00000008
90#define OR_FCM_RST_SHIFT 3
91#define OR_FCM_TRLX 0x00000004
92#define OR_FCM_TRLX_SHIFT 2
93#define OR_FCM_EHTR 0x00000002
94#define OR_FCM_EHTR_SHIFT 1
95};
96
97struct fsl_lbc_regs {
98 struct fsl_lbc_bank bank[8];
99 u8 res0[0x28];
100 __be32 mar; /**< UPM Address Register */
101 u8 res1[0x4];
102 __be32 mamr; /**< UPMA Mode Register */
103#define MxMR_OP_NO (0 << 28) /**< normal operation */
104#define MxMR_OP_WA (1 << 28) /**< write array */
105#define MxMR_OP_RA (2 << 28) /**< read array */
106#define MxMR_OP_RP (3 << 28) /**< run pattern */
107#define MxMR_MAD 0x3f /**< machine address */
108 __be32 mbmr; /**< UPMB Mode Register */
109 __be32 mcmr; /**< UPMC Mode Register */
110 u8 res2[0x8];
111 __be32 mrtpr; /**< Memory Refresh Timer Prescaler Register */
112 __be32 mdr; /**< UPM Data Register */
113 u8 res3[0x4];
114 __be32 lsor; /**< Special Operation Initiation Register */
115 __be32 lsdmr; /**< SDRAM Mode Register */
116 u8 res4[0x8];
117 __be32 lurt; /**< UPM Refresh Timer */
118 __be32 lsrt; /**< SDRAM Refresh Timer */
119 u8 res5[0x8];
120 __be32 ltesr; /**< Transfer Error Status Register */
121#define LTESR_BM 0x80000000
122#define LTESR_FCT 0x40000000
123#define LTESR_PAR 0x20000000
124#define LTESR_WP 0x04000000
125#define LTESR_ATMW 0x00800000
126#define LTESR_ATMR 0x00400000
127#define LTESR_CS 0x00080000
128#define LTESR_CC 0x00000001
129#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
130 __be32 ltedr; /**< Transfer Error Disable Register */
131 __be32 lteir; /**< Transfer Error Interrupt Register */
132 __be32 lteatr; /**< Transfer Error Attributes Register */
133 __be32 ltear; /**< Transfer Error Address Register */
134 u8 res6[0xC];
135 __be32 lbcr; /**< Configuration Register */
136#define LBCR_LDIS 0x80000000
137#define LBCR_LDIS_SHIFT 31
138#define LBCR_BCTLC 0x00C00000
139#define LBCR_BCTLC_SHIFT 22
140#define LBCR_AHD 0x00200000
141#define LBCR_LPBSE 0x00020000
142#define LBCR_LPBSE_SHIFT 17
143#define LBCR_EPAR 0x00010000
144#define LBCR_EPAR_SHIFT 16
145#define LBCR_BMT 0x0000FF00
146#define LBCR_BMT_SHIFT 8
147#define LBCR_INIT 0x00040000
148 __be32 lcrr; /**< Clock Ratio Register */
149#define LCRR_DBYP 0x80000000
150#define LCRR_DBYP_SHIFT 31
151#define LCRR_BUFCMDC 0x30000000
152#define LCRR_BUFCMDC_SHIFT 28
153#define LCRR_ECL 0x03000000
154#define LCRR_ECL_SHIFT 24
155#define LCRR_EADC 0x00030000
156#define LCRR_EADC_SHIFT 16
157#define LCRR_CLKDIV 0x0000000F
158#define LCRR_CLKDIV_SHIFT 0
159 u8 res7[0x8];
160 __be32 fmr; /**< Flash Mode Register */
161#define FMR_CWTO 0x0000F000
162#define FMR_CWTO_SHIFT 12
163#define FMR_BOOT 0x00000800
164#define FMR_ECCM 0x00000100
165#define FMR_AL 0x00000030
166#define FMR_AL_SHIFT 4
167#define FMR_OP 0x00000003
168#define FMR_OP_SHIFT 0
169 __be32 fir; /**< Flash Instruction Register */
170#define FIR_OP0 0xF0000000
171#define FIR_OP0_SHIFT 28
172#define FIR_OP1 0x0F000000
173#define FIR_OP1_SHIFT 24
174#define FIR_OP2 0x00F00000
175#define FIR_OP2_SHIFT 20
176#define FIR_OP3 0x000F0000
177#define FIR_OP3_SHIFT 16
178#define FIR_OP4 0x0000F000
179#define FIR_OP4_SHIFT 12
180#define FIR_OP5 0x00000F00
181#define FIR_OP5_SHIFT 8
182#define FIR_OP6 0x000000F0
183#define FIR_OP6_SHIFT 4
184#define FIR_OP7 0x0000000F
185#define FIR_OP7_SHIFT 0
186#define FIR_OP_NOP 0x0 /* No operation and end of sequence */
187#define FIR_OP_CA 0x1 /* Issue current column address */
188#define FIR_OP_PA 0x2 /* Issue current block+page address */
189#define FIR_OP_UA 0x3 /* Issue user defined address */
190#define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */
191#define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */
192#define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */
193#define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */
194#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */
195#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */
196#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */
197#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */
198#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */
199#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */
200#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */
201#define FIR_OP_RSW 0xE /* Wait then read 1 or 2 bytes */
202 __be32 fcr; /**< Flash Command Register */
203#define FCR_CMD0 0xFF000000
204#define FCR_CMD0_SHIFT 24
205#define FCR_CMD1 0x00FF0000
206#define FCR_CMD1_SHIFT 16
207#define FCR_CMD2 0x0000FF00
208#define FCR_CMD2_SHIFT 8
209#define FCR_CMD3 0x000000FF
210#define FCR_CMD3_SHIFT 0
211 __be32 fbar; /**< Flash Block Address Register */
212#define FBAR_BLK 0x00FFFFFF
213 __be32 fpar; /**< Flash Page Address Register */
214#define FPAR_SP_PI 0x00007C00
215#define FPAR_SP_PI_SHIFT 10
216#define FPAR_SP_MS 0x00000200
217#define FPAR_SP_CI 0x000001FF
218#define FPAR_SP_CI_SHIFT 0
219#define FPAR_LP_PI 0x0003F000
220#define FPAR_LP_PI_SHIFT 12
221#define FPAR_LP_MS 0x00000800
222#define FPAR_LP_CI 0x000007FF
223#define FPAR_LP_CI_SHIFT 0
224 __be32 fbcr; /**< Flash Byte Count Register */
225#define FBCR_BC 0x00000FFF
226 u8 res11[0x8];
227 u8 res8[0xF00];
228};
229
230extern struct fsl_lbc_regs __iomem *fsl_lbc_regs;
231extern spinlock_t fsl_lbc_lock;
232
233/*
234 * FSL UPM routines
235 */
236struct fsl_upm {
237 __be32 __iomem *mxmr;
238 int width;
239};
240
241extern int fsl_lbc_find(phys_addr_t addr_base);
242extern int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm);
243
244/**
245 * fsl_upm_start_pattern - start UPM patterns execution
246 * @upm: pointer to the fsl_upm structure obtained via fsl_upm_find
247 * @pat_offset: UPM pattern offset for the command to be executed
248 *
249 * This routine programmes UPM so the next memory access that hits an UPM
250 * will trigger pattern execution, starting at pat_offset.
251 */
252static inline void fsl_upm_start_pattern(struct fsl_upm *upm, u8 pat_offset)
253{
254 clrsetbits_be32(upm->mxmr, MxMR_MAD, MxMR_OP_RP | pat_offset);
255}
256
257/**
258 * fsl_upm_end_pattern - end UPM patterns execution
259 * @upm: pointer to the fsl_upm structure obtained via fsl_upm_find
260 *
261 * This routine reverts UPM to normal operation mode.
262 */
263static inline void fsl_upm_end_pattern(struct fsl_upm *upm)
264{
265 clrbits32(upm->mxmr, MxMR_OP_RP);
266
267 while (in_be32(upm->mxmr) & MxMR_OP_RP)
268 cpu_relax();
269}
270
271/**
272 * fsl_upm_run_pattern - actually run an UPM pattern
273 * @upm: pointer to the fsl_upm structure obtained via fsl_upm_find
274 * @io_base: remapped pointer to where memory access should happen
275 * @mar: MAR register content during pattern execution
276 *
277 * This function triggers dummy write to the memory specified by the io_base,
278 * thus UPM pattern actually executed. Note that mar usage depends on the
279 * pre-programmed AMX bits in the UPM RAM.
280 */
281static inline int fsl_upm_run_pattern(struct fsl_upm *upm,
282 void __iomem *io_base, u32 mar)
283{
284 int ret = 0;
285 unsigned long flags;
286
287 spin_lock_irqsave(&fsl_lbc_lock, flags);
288
289 out_be32(&fsl_lbc_regs->mar, mar << (32 - upm->width));
290
291 switch (upm->width) {
292 case 8:
293 out_8(io_base, 0x0);
294 break;
295 case 16:
296 out_be16(io_base, 0x0);
297 break;
298 case 32:
299 out_be32(io_base, 0x0);
300 break;
301 default:
302 ret = -EINVAL;
303 break;
304 }
305
306 spin_unlock_irqrestore(&fsl_lbc_lock, flags);
307
308 return ret;
309}
310
311#endif /* __ASM_FSL_LBC_H */
diff --git a/include/asm-powerpc/ftrace.h b/include/asm-powerpc/ftrace.h
deleted file mode 100644
index de921326cca..00000000000
--- a/include/asm-powerpc/ftrace.h
+++ /dev/null
@@ -1,14 +0,0 @@
1#ifndef _ASM_POWERPC_FTRACE
2#define _ASM_POWERPC_FTRACE
3
4#ifdef CONFIG_FTRACE
5#define MCOUNT_ADDR ((long)(_mcount))
6#define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */
7
8#ifndef __ASSEMBLY__
9extern void _mcount(void);
10#endif
11
12#endif
13
14#endif /* _ASM_POWERPC_FTRACE */
diff --git a/include/asm-powerpc/futex.h b/include/asm-powerpc/futex.h
deleted file mode 100644
index 6d406c5c5de..00000000000
--- a/include/asm-powerpc/futex.h
+++ /dev/null
@@ -1,117 +0,0 @@
1#ifndef _ASM_POWERPC_FUTEX_H
2#define _ASM_POWERPC_FUTEX_H
3
4#ifdef __KERNEL__
5
6#include <linux/futex.h>
7#include <linux/uaccess.h>
8#include <asm/errno.h>
9#include <asm/synch.h>
10#include <asm/asm-compat.h>
11
12#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
13 __asm__ __volatile ( \
14 LWSYNC_ON_SMP \
15"1: lwarx %0,0,%2\n" \
16 insn \
17 PPC405_ERR77(0, %2) \
18"2: stwcx. %1,0,%2\n" \
19 "bne- 1b\n" \
20 "li %1,0\n" \
21"3: .section .fixup,\"ax\"\n" \
22"4: li %1,%3\n" \
23 "b 3b\n" \
24 ".previous\n" \
25 ".section __ex_table,\"a\"\n" \
26 ".align 3\n" \
27 PPC_LONG "1b,4b,2b,4b\n" \
28 ".previous" \
29 : "=&r" (oldval), "=&r" (ret) \
30 : "b" (uaddr), "i" (-EFAULT), "1" (oparg) \
31 : "cr0", "memory")
32
33static inline int futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
34{
35 int op = (encoded_op >> 28) & 7;
36 int cmp = (encoded_op >> 24) & 15;
37 int oparg = (encoded_op << 8) >> 20;
38 int cmparg = (encoded_op << 20) >> 20;
39 int oldval = 0, ret;
40 if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
41 oparg = 1 << oparg;
42
43 if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
44 return -EFAULT;
45
46 pagefault_disable();
47
48 switch (op) {
49 case FUTEX_OP_SET:
50 __futex_atomic_op("", ret, oldval, uaddr, oparg);
51 break;
52 case FUTEX_OP_ADD:
53 __futex_atomic_op("add %1,%0,%1\n", ret, oldval, uaddr, oparg);
54 break;
55 case FUTEX_OP_OR:
56 __futex_atomic_op("or %1,%0,%1\n", ret, oldval, uaddr, oparg);
57 break;
58 case FUTEX_OP_ANDN:
59 __futex_atomic_op("andc %1,%0,%1\n", ret, oldval, uaddr, oparg);
60 break;
61 case FUTEX_OP_XOR:
62 __futex_atomic_op("xor %1,%0,%1\n", ret, oldval, uaddr, oparg);
63 break;
64 default:
65 ret = -ENOSYS;
66 }
67
68 pagefault_enable();
69
70 if (!ret) {
71 switch (cmp) {
72 case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
73 case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
74 case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
75 case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
76 case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
77 case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
78 default: ret = -ENOSYS;
79 }
80 }
81 return ret;
82}
83
84static inline int
85futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
86{
87 int prev;
88
89 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
90 return -EFAULT;
91
92 __asm__ __volatile__ (
93 LWSYNC_ON_SMP
94"1: lwarx %0,0,%2 # futex_atomic_cmpxchg_inatomic\n\
95 cmpw 0,%0,%3\n\
96 bne- 3f\n"
97 PPC405_ERR77(0,%2)
98"2: stwcx. %4,0,%2\n\
99 bne- 1b\n"
100 ISYNC_ON_SMP
101"3: .section .fixup,\"ax\"\n\
1024: li %0,%5\n\
103 b 3b\n\
104 .previous\n\
105 .section __ex_table,\"a\"\n\
106 .align 3\n\
107 " PPC_LONG "1b,4b,2b,4b\n\
108 .previous" \
109 : "=&r" (prev), "+m" (*uaddr)
110 : "r" (uaddr), "r" (oldval), "r" (newval), "i" (-EFAULT)
111 : "cc", "memory");
112
113 return prev;
114}
115
116#endif /* __KERNEL__ */
117#endif /* _ASM_POWERPC_FUTEX_H */
diff --git a/include/asm-powerpc/gpio.h b/include/asm-powerpc/gpio.h
deleted file mode 100644
index ea04632399d..00000000000
--- a/include/asm-powerpc/gpio.h
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * Generic GPIO API implementation for PowerPC.
3 *
4 * Copyright (c) 2007-2008 MontaVista Software, Inc.
5 *
6 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#ifndef __ASM_POWERPC_GPIO_H
15#define __ASM_POWERPC_GPIO_H
16
17#include <linux/errno.h>
18#include <asm-generic/gpio.h>
19
20#ifdef CONFIG_GPIOLIB
21
22/*
23 * We don't (yet) implement inlined/rapid versions for on-chip gpios.
24 * Just call gpiolib.
25 */
26static inline int gpio_get_value(unsigned int gpio)
27{
28 return __gpio_get_value(gpio);
29}
30
31static inline void gpio_set_value(unsigned int gpio, int value)
32{
33 __gpio_set_value(gpio, value);
34}
35
36static inline int gpio_cansleep(unsigned int gpio)
37{
38 return __gpio_cansleep(gpio);
39}
40
41/*
42 * Not implemented, yet.
43 */
44static inline int gpio_to_irq(unsigned int gpio)
45{
46 return -ENOSYS;
47}
48
49static inline int irq_to_gpio(unsigned int irq)
50{
51 return -EINVAL;
52}
53
54#endif /* CONFIG_GPIOLIB */
55
56#endif /* __ASM_POWERPC_GPIO_H */
diff --git a/include/asm-powerpc/grackle.h b/include/asm-powerpc/grackle.h
deleted file mode 100644
index bd7812a519d..00000000000
--- a/include/asm-powerpc/grackle.h
+++ /dev/null
@@ -1,12 +0,0 @@
1#ifndef _ASM_POWERPC_GRACKLE_H
2#define _ASM_POWERPC_GRACKLE_H
3#ifdef __KERNEL__
4/*
5 * Functions for setting up and using a MPC106 northbridge
6 */
7
8#include <asm/pci-bridge.h>
9
10extern void setup_grackle(struct pci_controller *hose);
11#endif /* __KERNEL__ */
12#endif /* _ASM_POWERPC_GRACKLE_H */
diff --git a/include/asm-powerpc/hardirq.h b/include/asm-powerpc/hardirq.h
deleted file mode 100644
index 288e14d53b7..00000000000
--- a/include/asm-powerpc/hardirq.h
+++ /dev/null
@@ -1,29 +0,0 @@
1#ifndef _ASM_POWERPC_HARDIRQ_H
2#define _ASM_POWERPC_HARDIRQ_H
3#ifdef __KERNEL__
4
5#include <asm/irq.h>
6#include <asm/bug.h>
7
8/* The __last_jiffy_stamp field is needed to ensure that no decrementer
9 * interrupt is lost on SMP machines. Since on most CPUs it is in the same
10 * cache line as local_irq_count, it is cheap to access and is also used on UP
11 * for uniformity.
12 */
13typedef struct {
14 unsigned int __softirq_pending; /* set_bit is used on this */
15 unsigned int __last_jiffy_stamp;
16} ____cacheline_aligned irq_cpustat_t;
17
18#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
19
20#define last_jiffy_stamp(cpu) __IRQ_STAT((cpu), __last_jiffy_stamp)
21
22static inline void ack_bad_irq(int irq)
23{
24 printk(KERN_CRIT "illegal vector %d received!\n", irq);
25 BUG();
26}
27
28#endif /* __KERNEL__ */
29#endif /* _ASM_POWERPC_HARDIRQ_H */
diff --git a/include/asm-powerpc/heathrow.h b/include/asm-powerpc/heathrow.h
deleted file mode 100644
index 93f54958a9d..00000000000
--- a/include/asm-powerpc/heathrow.h
+++ /dev/null
@@ -1,67 +0,0 @@
1#ifndef _ASM_POWERPC_HEATHROW_H
2#define _ASM_POWERPC_HEATHROW_H
3#ifdef __KERNEL__
4/*
5 * heathrow.h: definitions for using the "Heathrow" I/O controller chip.
6 *
7 * Grabbed from Open Firmware definitions on a PowerBook G3 Series
8 *
9 * Copyright (C) 1997 Paul Mackerras.
10 */
11
12/* Front light color on Yikes/B&W G3. 32 bits */
13#define HEATHROW_FRONT_LIGHT 0x32 /* (set to 0 or 0xffffffff) */
14
15/* Brightness/contrast (gossamer iMac ?). 8 bits */
16#define HEATHROW_BRIGHTNESS_CNTL 0x32
17#define HEATHROW_CONTRAST_CNTL 0x33
18
19/* offset from ohare base for feature control register */
20#define HEATHROW_MBCR 0x34 /* Media bay control */
21#define HEATHROW_FCR 0x38 /* Feature control */
22#define HEATHROW_AUX_CNTL_REG 0x3c /* Aux control */
23
24/*
25 * Bits in feature control register.
26 * Bits postfixed with a _N are in inverse logic
27 */
28#define HRW_SCC_TRANS_EN_N 0x00000001 /* Also controls modem power */
29#define HRW_BAY_POWER_N 0x00000002
30#define HRW_BAY_PCI_ENABLE 0x00000004
31#define HRW_BAY_IDE_ENABLE 0x00000008
32#define HRW_BAY_FLOPPY_ENABLE 0x00000010
33#define HRW_IDE0_ENABLE 0x00000020
34#define HRW_IDE0_RESET_N 0x00000040
35#define HRW_BAY_DEV_MASK 0x0000001c
36#define HRW_BAY_RESET_N 0x00000080
37#define HRW_IOBUS_ENABLE 0x00000100 /* Internal IDE ? */
38#define HRW_SCC_ENABLE 0x00000200
39#define HRW_MESH_ENABLE 0x00000400
40#define HRW_SWIM_ENABLE 0x00000800
41#define HRW_SOUND_POWER_N 0x00001000
42#define HRW_SOUND_CLK_ENABLE 0x00002000
43#define HRW_SCCA_IO 0x00004000
44#define HRW_SCCB_IO 0x00008000
45#define HRW_PORT_OR_DESK_VIA_N 0x00010000 /* This one is 0 on PowerBook */
46#define HRW_PWM_MON_ID_N 0x00020000 /* ??? (0) */
47#define HRW_HOOK_MB_CNT_N 0x00040000 /* ??? (0) */
48#define HRW_SWIM_CLONE_FLOPPY 0x00080000 /* ??? (0) */
49#define HRW_AUD_RUN22 0x00100000 /* ??? (1) */
50#define HRW_SCSI_LINK_MODE 0x00200000 /* Read ??? (1) */
51#define HRW_ARB_BYPASS 0x00400000 /* Disable internal PCI arbitrer */
52#define HRW_IDE1_RESET_N 0x00800000 /* Media bay */
53#define HRW_SLOW_SCC_PCLK 0x01000000 /* ??? (0) */
54#define HRW_RESET_SCC 0x02000000
55#define HRW_MFDC_CELL_ENABLE 0x04000000 /* ??? (0) */
56#define HRW_USE_MFDC 0x08000000 /* ??? (0) */
57#define HRW_BMAC_IO_ENABLE 0x60000000 /* two bits, not documented in OF */
58#define HRW_BMAC_RESET 0x80000000 /* not documented in OF */
59
60/* We OR those features at boot on desktop G3s */
61#define HRW_DEFAULTS (HRW_SCCA_IO | HRW_SCCB_IO | HRW_SCC_ENABLE)
62
63/* Looks like Heathrow has some sort of GPIOs as well... */
64#define HRW_GPIO_MODEM_RESET 0x6d
65
66#endif /* __KERNEL__ */
67#endif /* _ASM_POWERPC_HEATHROW_H */
diff --git a/include/asm-powerpc/highmem.h b/include/asm-powerpc/highmem.h
deleted file mode 100644
index 5d99b6489d5..00000000000
--- a/include/asm-powerpc/highmem.h
+++ /dev/null
@@ -1,138 +0,0 @@
1/*
2 * highmem.h: virtual kernel memory mappings for high memory
3 *
4 * PowerPC version, stolen from the i386 version.
5 *
6 * Used in CONFIG_HIGHMEM systems for memory pages which
7 * are not addressable by direct kernel virtual addresses.
8 *
9 * Copyright (C) 1999 Gerhard Wichert, Siemens AG
10 * Gerhard.Wichert@pdb.siemens.de
11 *
12 *
13 * Redesigned the x86 32-bit VM architecture to deal with
14 * up to 16 Terrabyte physical memory. With current x86 CPUs
15 * we now support up to 64 Gigabytes physical RAM.
16 *
17 * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
18 */
19
20#ifndef _ASM_HIGHMEM_H
21#define _ASM_HIGHMEM_H
22
23#ifdef __KERNEL__
24
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <asm/kmap_types.h>
28#include <asm/tlbflush.h>
29#include <asm/page.h>
30#include <asm/fixmap.h>
31
32extern pte_t *kmap_pte;
33extern pgprot_t kmap_prot;
34extern pte_t *pkmap_page_table;
35
36/*
37 * Right now we initialize only a single pte table. It can be extended
38 * easily, subsequent pte tables have to be allocated in one physical
39 * chunk of RAM.
40 */
41#define LAST_PKMAP (1 << PTE_SHIFT)
42#define LAST_PKMAP_MASK (LAST_PKMAP-1)
43#define PKMAP_BASE ((FIXADDR_START - PAGE_SIZE*(LAST_PKMAP + 1)) & PMD_MASK)
44#define PKMAP_NR(virt) ((virt-PKMAP_BASE) >> PAGE_SHIFT)
45#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
46
47extern void *kmap_high(struct page *page);
48extern void kunmap_high(struct page *page);
49
50static inline void *kmap(struct page *page)
51{
52 might_sleep();
53 if (!PageHighMem(page))
54 return page_address(page);
55 return kmap_high(page);
56}
57
58static inline void kunmap(struct page *page)
59{
60 BUG_ON(in_interrupt());
61 if (!PageHighMem(page))
62 return;
63 kunmap_high(page);
64}
65
66/*
67 * The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap
68 * gives a more generic (and caching) interface. But kmap_atomic can
69 * be used in IRQ contexts, so in some (very limited) cases we need
70 * it.
71 */
72static inline void *kmap_atomic_prot(struct page *page, enum km_type type, pgprot_t prot)
73{
74 unsigned int idx;
75 unsigned long vaddr;
76
77 /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */
78 pagefault_disable();
79 if (!PageHighMem(page))
80 return page_address(page);
81
82 idx = type + KM_TYPE_NR*smp_processor_id();
83 vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
84#ifdef CONFIG_DEBUG_HIGHMEM
85 BUG_ON(!pte_none(*(kmap_pte-idx)));
86#endif
87 set_pte_at(&init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot));
88 flush_tlb_page(NULL, vaddr);
89
90 return (void*) vaddr;
91}
92
93static inline void *kmap_atomic(struct page *page, enum km_type type)
94{
95 return kmap_atomic_prot(page, type, kmap_prot);
96}
97
98static inline void kunmap_atomic(void *kvaddr, enum km_type type)
99{
100#ifdef CONFIG_DEBUG_HIGHMEM
101 unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK;
102 enum fixed_addresses idx = type + KM_TYPE_NR*smp_processor_id();
103
104 if (vaddr < __fix_to_virt(FIX_KMAP_END)) {
105 pagefault_enable();
106 return;
107 }
108
109 BUG_ON(vaddr != __fix_to_virt(FIX_KMAP_BEGIN + idx));
110
111 /*
112 * force other mappings to Oops if they'll try to access
113 * this pte without first remap it
114 */
115 pte_clear(&init_mm, vaddr, kmap_pte-idx);
116 flush_tlb_page(NULL, vaddr);
117#endif
118 pagefault_enable();
119}
120
121static inline struct page *kmap_atomic_to_page(void *ptr)
122{
123 unsigned long idx, vaddr = (unsigned long) ptr;
124 pte_t *pte;
125
126 if (vaddr < FIXADDR_START)
127 return virt_to_page(ptr);
128
129 idx = virt_to_fix(vaddr);
130 pte = kmap_pte - (idx - FIX_KMAP_BEGIN);
131 return pte_page(*pte);
132}
133
134#define flush_cache_kmaps() flush_cache_all()
135
136#endif /* __KERNEL__ */
137
138#endif /* _ASM_HIGHMEM_H */
diff --git a/include/asm-powerpc/hugetlb.h b/include/asm-powerpc/hugetlb.h
deleted file mode 100644
index 26f0d0ab27a..00000000000
--- a/include/asm-powerpc/hugetlb.h
+++ /dev/null
@@ -1,75 +0,0 @@
1#ifndef _ASM_POWERPC_HUGETLB_H
2#define _ASM_POWERPC_HUGETLB_H
3
4#include <asm/page.h>
5
6
7int is_hugepage_only_range(struct mm_struct *mm, unsigned long addr,
8 unsigned long len);
9
10void hugetlb_free_pgd_range(struct mmu_gather *tlb, unsigned long addr,
11 unsigned long end, unsigned long floor,
12 unsigned long ceiling);
13
14void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
15 pte_t *ptep, pte_t pte);
16
17pte_t huge_ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
18 pte_t *ptep);
19
20/*
21 * If the arch doesn't supply something else, assume that hugepage
22 * size aligned regions are ok without further preparation.
23 */
24static inline int prepare_hugepage_range(struct file *file,
25 unsigned long addr, unsigned long len)
26{
27 struct hstate *h = hstate_file(file);
28 if (len & ~huge_page_mask(h))
29 return -EINVAL;
30 if (addr & ~huge_page_mask(h))
31 return -EINVAL;
32 return 0;
33}
34
35static inline void hugetlb_prefault_arch_hook(struct mm_struct *mm)
36{
37}
38
39static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
40 unsigned long addr, pte_t *ptep)
41{
42}
43
44static inline int huge_pte_none(pte_t pte)
45{
46 return pte_none(pte);
47}
48
49static inline pte_t huge_pte_wrprotect(pte_t pte)
50{
51 return pte_wrprotect(pte);
52}
53
54static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
55 unsigned long addr, pte_t *ptep,
56 pte_t pte, int dirty)
57{
58 return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
59}
60
61static inline pte_t huge_ptep_get(pte_t *ptep)
62{
63 return *ptep;
64}
65
66static inline int arch_prepare_hugepage(struct page *page)
67{
68 return 0;
69}
70
71static inline void arch_release_hugepage(struct page *page)
72{
73}
74
75#endif /* _ASM_POWERPC_HUGETLB_H */
diff --git a/include/asm-powerpc/hvcall.h b/include/asm-powerpc/hvcall.h
deleted file mode 100644
index fbe2932fa9e..00000000000
--- a/include/asm-powerpc/hvcall.h
+++ /dev/null
@@ -1,296 +0,0 @@
1#ifndef _ASM_POWERPC_HVCALL_H
2#define _ASM_POWERPC_HVCALL_H
3#ifdef __KERNEL__
4
5#define HVSC .long 0x44000022
6
7#define H_SUCCESS 0
8#define H_BUSY 1 /* Hardware busy -- retry later */
9#define H_CLOSED 2 /* Resource closed */
10#define H_NOT_AVAILABLE 3
11#define H_CONSTRAINED 4 /* Resource request constrained to max allowed */
12#define H_PARTIAL 5
13#define H_IN_PROGRESS 14 /* Kind of like busy */
14#define H_PAGE_REGISTERED 15
15#define H_PARTIAL_STORE 16
16#define H_PENDING 17 /* returned from H_POLL_PENDING */
17#define H_CONTINUE 18 /* Returned from H_Join on success */
18#define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */
19#define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \
20 is a good time to retry */
21#define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \
22 is a good time to retry */
23#define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \
24 is a good time to retry */
25#define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \
26 is a good time to retry */
27#define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \
28 is a good time to retry */
29#define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \
30 is a good time to retry */
31#define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */
32#define H_HARDWARE -1 /* Hardware error */
33#define H_FUNCTION -2 /* Function not supported */
34#define H_PRIVILEGE -3 /* Caller not privileged */
35#define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */
36#define H_BAD_MODE -5 /* Illegal msr value */
37#define H_PTEG_FULL -6 /* PTEG is full */
38#define H_NOT_FOUND -7 /* PTE was not found" */
39#define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */
40#define H_NO_MEM -9
41#define H_AUTHORITY -10
42#define H_PERMISSION -11
43#define H_DROPPED -12
44#define H_SOURCE_PARM -13
45#define H_DEST_PARM -14
46#define H_REMOTE_PARM -15
47#define H_RESOURCE -16
48#define H_ADAPTER_PARM -17
49#define H_RH_PARM -18
50#define H_RCQ_PARM -19
51#define H_SCQ_PARM -20
52#define H_EQ_PARM -21
53#define H_RT_PARM -22
54#define H_ST_PARM -23
55#define H_SIGT_PARM -24
56#define H_TOKEN_PARM -25
57#define H_MLENGTH_PARM -27
58#define H_MEM_PARM -28
59#define H_MEM_ACCESS_PARM -29
60#define H_ATTR_PARM -30
61#define H_PORT_PARM -31
62#define H_MCG_PARM -32
63#define H_VL_PARM -33
64#define H_TSIZE_PARM -34
65#define H_TRACE_PARM -35
66
67#define H_MASK_PARM -37
68#define H_MCG_FULL -38
69#define H_ALIAS_EXIST -39
70#define H_P_COUNTER -40
71#define H_TABLE_FULL -41
72#define H_ALT_TABLE -42
73#define H_MR_CONDITION -43
74#define H_NOT_ENOUGH_RESOURCES -44
75#define H_R_STATE -45
76#define H_RESCINDEND -46
77
78
79/* Long Busy is a condition that can be returned by the firmware
80 * when a call cannot be completed now, but the identical call
81 * should be retried later. This prevents calls blocking in the
82 * firmware for long periods of time. Annoyingly the firmware can return
83 * a range of return codes, hinting at how long we should wait before
84 * retrying. If you don't care for the hint, the macro below is a good
85 * way to check for the long_busy return codes
86 */
87#define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \
88 && (x <= H_LONG_BUSY_END_RANGE))
89
90/* Flags */
91#define H_LARGE_PAGE (1UL<<(63-16))
92#define H_EXACT (1UL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */
93#define H_R_XLATE (1UL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */
94#define H_READ_4 (1UL<<(63-26)) /* Return 4 PTEs */
95#define H_PAGE_STATE_CHANGE (1UL<<(63-28))
96#define H_PAGE_UNUSED ((1UL<<(63-29)) | (1UL<<(63-30)))
97#define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED)
98#define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1UL<<(63-31)))
99#define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE
100#define H_AVPN (1UL<<(63-32)) /* An avpn is provided as a sanity test */
101#define H_ANDCOND (1UL<<(63-33))
102#define H_ICACHE_INVALIDATE (1UL<<(63-40)) /* icbi, etc. (ignored for IO pages) */
103#define H_ICACHE_SYNCHRONIZE (1UL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */
104#define H_ZERO_PAGE (1UL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */
105#define H_COPY_PAGE (1UL<<(63-49))
106#define H_N (1UL<<(63-61))
107#define H_PP1 (1UL<<(63-62))
108#define H_PP2 (1UL<<(63-63))
109
110/* VASI States */
111#define H_VASI_INVALID 0
112#define H_VASI_ENABLED 1
113#define H_VASI_ABORTED 2
114#define H_VASI_SUSPENDING 3
115#define H_VASI_SUSPENDED 4
116#define H_VASI_RESUMED 5
117#define H_VASI_COMPLETED 6
118
119/* DABRX flags */
120#define H_DABRX_HYPERVISOR (1UL<<(63-61))
121#define H_DABRX_KERNEL (1UL<<(63-62))
122#define H_DABRX_USER (1UL<<(63-63))
123
124/* Each control block has to be on a 4K bondary */
125#define H_CB_ALIGNMENT 4096
126
127/* pSeries hypervisor opcodes */
128#define H_REMOVE 0x04
129#define H_ENTER 0x08
130#define H_READ 0x0c
131#define H_CLEAR_MOD 0x10
132#define H_CLEAR_REF 0x14
133#define H_PROTECT 0x18
134#define H_GET_TCE 0x1c
135#define H_PUT_TCE 0x20
136#define H_SET_SPRG0 0x24
137#define H_SET_DABR 0x28
138#define H_PAGE_INIT 0x2c
139#define H_SET_ASR 0x30
140#define H_ASR_ON 0x34
141#define H_ASR_OFF 0x38
142#define H_LOGICAL_CI_LOAD 0x3c
143#define H_LOGICAL_CI_STORE 0x40
144#define H_LOGICAL_CACHE_LOAD 0x44
145#define H_LOGICAL_CACHE_STORE 0x48
146#define H_LOGICAL_ICBI 0x4c
147#define H_LOGICAL_DCBF 0x50
148#define H_GET_TERM_CHAR 0x54
149#define H_PUT_TERM_CHAR 0x58
150#define H_REAL_TO_LOGICAL 0x5c
151#define H_HYPERVISOR_DATA 0x60
152#define H_EOI 0x64
153#define H_CPPR 0x68
154#define H_IPI 0x6c
155#define H_IPOLL 0x70
156#define H_XIRR 0x74
157#define H_PERFMON 0x7c
158#define H_MIGRATE_DMA 0x78
159#define H_REGISTER_VPA 0xDC
160#define H_CEDE 0xE0
161#define H_CONFER 0xE4
162#define H_PROD 0xE8
163#define H_GET_PPP 0xEC
164#define H_SET_PPP 0xF0
165#define H_PURR 0xF4
166#define H_PIC 0xF8
167#define H_REG_CRQ 0xFC
168#define H_FREE_CRQ 0x100
169#define H_VIO_SIGNAL 0x104
170#define H_SEND_CRQ 0x108
171#define H_COPY_RDMA 0x110
172#define H_REGISTER_LOGICAL_LAN 0x114
173#define H_FREE_LOGICAL_LAN 0x118
174#define H_ADD_LOGICAL_LAN_BUFFER 0x11C
175#define H_SEND_LOGICAL_LAN 0x120
176#define H_BULK_REMOVE 0x124
177#define H_MULTICAST_CTRL 0x130
178#define H_SET_XDABR 0x134
179#define H_STUFF_TCE 0x138
180#define H_PUT_TCE_INDIRECT 0x13C
181#define H_CHANGE_LOGICAL_LAN_MAC 0x14C
182#define H_VTERM_PARTNER_INFO 0x150
183#define H_REGISTER_VTERM 0x154
184#define H_FREE_VTERM 0x158
185#define H_RESET_EVENTS 0x15C
186#define H_ALLOC_RESOURCE 0x160
187#define H_FREE_RESOURCE 0x164
188#define H_MODIFY_QP 0x168
189#define H_QUERY_QP 0x16C
190#define H_REREGISTER_PMR 0x170
191#define H_REGISTER_SMR 0x174
192#define H_QUERY_MR 0x178
193#define H_QUERY_MW 0x17C
194#define H_QUERY_HCA 0x180
195#define H_QUERY_PORT 0x184
196#define H_MODIFY_PORT 0x188
197#define H_DEFINE_AQP1 0x18C
198#define H_GET_TRACE_BUFFER 0x190
199#define H_DEFINE_AQP0 0x194
200#define H_RESIZE_MR 0x198
201#define H_ATTACH_MCQP 0x19C
202#define H_DETACH_MCQP 0x1A0
203#define H_CREATE_RPT 0x1A4
204#define H_REMOVE_RPT 0x1A8
205#define H_REGISTER_RPAGES 0x1AC
206#define H_DISABLE_AND_GETC 0x1B0
207#define H_ERROR_DATA 0x1B4
208#define H_GET_HCA_INFO 0x1B8
209#define H_GET_PERF_COUNT 0x1BC
210#define H_MANAGE_TRACE 0x1C0
211#define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
212#define H_QUERY_INT_STATE 0x1E4
213#define H_POLL_PENDING 0x1D8
214#define H_ILLAN_ATTRIBUTES 0x244
215#define H_JOIN 0x298
216#define H_VASI_STATE 0x2A4
217#define H_ENABLE_CRQ 0x2B0
218#define H_SET_MPP 0x2D0
219#define H_GET_MPP 0x2D4
220#define MAX_HCALL_OPCODE H_GET_MPP
221
222#ifndef __ASSEMBLY__
223
224/**
225 * plpar_hcall_norets: - Make a pseries hypervisor call with no return arguments
226 * @opcode: The hypervisor call to make.
227 *
228 * This call supports up to 7 arguments and only returns the status of
229 * the hcall. Use this version where possible, its slightly faster than
230 * the other plpar_hcalls.
231 */
232long plpar_hcall_norets(unsigned long opcode, ...);
233
234/**
235 * plpar_hcall: - Make a pseries hypervisor call
236 * @opcode: The hypervisor call to make.
237 * @retbuf: Buffer to store up to 4 return arguments in.
238 *
239 * This call supports up to 6 arguments and 4 return arguments. Use
240 * PLPAR_HCALL_BUFSIZE to size the return argument buffer.
241 *
242 * Used for all but the craziest of phyp interfaces (see plpar_hcall9)
243 */
244#define PLPAR_HCALL_BUFSIZE 4
245long plpar_hcall(unsigned long opcode, unsigned long *retbuf, ...);
246
247/**
248 * plpar_hcall_raw: - Make a hypervisor call without calculating hcall stats
249 * @opcode: The hypervisor call to make.
250 * @retbuf: Buffer to store up to 4 return arguments in.
251 *
252 * This call supports up to 6 arguments and 4 return arguments. Use
253 * PLPAR_HCALL_BUFSIZE to size the return argument buffer.
254 *
255 * Used when phyp interface needs to be called in real mode. Similar to
256 * plpar_hcall, but plpar_hcall_raw works in real mode and does not
257 * calculate hypervisor call statistics.
258 */
259long plpar_hcall_raw(unsigned long opcode, unsigned long *retbuf, ...);
260
261/**
262 * plpar_hcall9: - Make a pseries hypervisor call with up to 9 return arguments
263 * @opcode: The hypervisor call to make.
264 * @retbuf: Buffer to store up to 9 return arguments in.
265 *
266 * This call supports up to 9 arguments and 9 return arguments. Use
267 * PLPAR_HCALL9_BUFSIZE to size the return argument buffer.
268 */
269#define PLPAR_HCALL9_BUFSIZE 9
270long plpar_hcall9(unsigned long opcode, unsigned long *retbuf, ...);
271
272/* For hcall instrumentation. One structure per-hcall, per-CPU */
273struct hcall_stats {
274 unsigned long num_calls; /* number of calls (on this CPU) */
275 unsigned long tb_total; /* total wall time (mftb) of calls. */
276 unsigned long purr_total; /* total cpu time (PURR) of calls. */
277};
278#define HCALL_STAT_ARRAY_SIZE ((MAX_HCALL_OPCODE >> 2) + 1)
279
280struct hvcall_mpp_data {
281 unsigned long entitled_mem;
282 unsigned long mapped_mem;
283 unsigned short group_num;
284 unsigned short pool_num;
285 unsigned char mem_weight;
286 unsigned char unallocated_mem_weight;
287 unsigned long unallocated_entitlement; /* value in bytes */
288 unsigned long pool_size;
289 signed long loan_request;
290 unsigned long backing_mem;
291};
292
293int h_get_mpp(struct hvcall_mpp_data *);
294#endif /* __ASSEMBLY__ */
295#endif /* __KERNEL__ */
296#endif /* _ASM_POWERPC_HVCALL_H */
diff --git a/include/asm-powerpc/hvconsole.h b/include/asm-powerpc/hvconsole.h
deleted file mode 100644
index 35ea69e8121..00000000000
--- a/include/asm-powerpc/hvconsole.h
+++ /dev/null
@@ -1,41 +0,0 @@
1/*
2 * hvconsole.h
3 * Copyright (C) 2004 Ryan S Arnold, IBM Corporation
4 *
5 * LPAR console support.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#ifndef _PPC64_HVCONSOLE_H
23#define _PPC64_HVCONSOLE_H
24#ifdef __KERNEL__
25
26/*
27 * PSeries firmware will only send/recv up to 16 bytes of character data per
28 * hcall.
29 */
30#define MAX_VIO_PUT_CHARS 16
31#define SIZE_VIO_GET_CHARS 16
32
33/*
34 * Vio firmware always attempts to fetch MAX_VIO_GET_CHARS chars. The 'count'
35 * parm is included to conform to put_chars() function pointer template
36 */
37extern int hvc_get_chars(uint32_t vtermno, char *buf, int count);
38extern int hvc_put_chars(uint32_t vtermno, const char *buf, int count);
39
40#endif /* __KERNEL__ */
41#endif /* _PPC64_HVCONSOLE_H */
diff --git a/include/asm-powerpc/hvcserver.h b/include/asm-powerpc/hvcserver.h
deleted file mode 100644
index 67d7da3a4da..00000000000
--- a/include/asm-powerpc/hvcserver.h
+++ /dev/null
@@ -1,59 +0,0 @@
1/*
2 * hvcserver.h
3 * Copyright (C) 2004 Ryan S Arnold, IBM Corporation
4 *
5 * PPC64 virtual I/O console server support.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#ifndef _PPC64_HVCSERVER_H
23#define _PPC64_HVCSERVER_H
24#ifdef __KERNEL__
25
26#include <linux/list.h>
27
28/* Converged Location Code length */
29#define HVCS_CLC_LENGTH 79
30
31/**
32 * hvcs_partner_info - an element in a list of partner info
33 * @node: list_head denoting this partner_info struct's position in the list of
34 * partner info.
35 * @unit_address: The partner unit address of this entry.
36 * @partition_ID: The partner partition ID of this entry.
37 * @location_code: The converged location code of this entry + 1 char for the
38 * null-term.
39 *
40 * This structure outlines the format that partner info is presented to a caller
41 * of the hvcs partner info fetching functions. These are strung together into
42 * a list using linux kernel lists.
43 */
44struct hvcs_partner_info {
45 struct list_head node;
46 uint32_t unit_address;
47 uint32_t partition_ID;
48 char location_code[HVCS_CLC_LENGTH + 1]; /* CLC + 1 null-term char */
49};
50
51extern int hvcs_free_partner_info(struct list_head *head);
52extern int hvcs_get_partner_info(uint32_t unit_address,
53 struct list_head *head, unsigned long *pi_buff);
54extern int hvcs_register_connection(uint32_t unit_address,
55 uint32_t p_partition_ID, uint32_t p_unit_address);
56extern int hvcs_free_connection(uint32_t unit_address);
57
58#endif /* __KERNEL__ */
59#endif /* _PPC64_HVCSERVER_H */
diff --git a/include/asm-powerpc/hw_irq.h b/include/asm-powerpc/hw_irq.h
deleted file mode 100644
index f75a5fc64d2..00000000000
--- a/include/asm-powerpc/hw_irq.h
+++ /dev/null
@@ -1,135 +0,0 @@
1/*
2 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
3 */
4#ifndef _ASM_POWERPC_HW_IRQ_H
5#define _ASM_POWERPC_HW_IRQ_H
6
7#ifdef __KERNEL__
8
9#include <linux/errno.h>
10#include <linux/compiler.h>
11#include <asm/ptrace.h>
12#include <asm/processor.h>
13
14extern void timer_interrupt(struct pt_regs *);
15
16#ifdef CONFIG_PPC64
17#include <asm/paca.h>
18
19static inline unsigned long local_get_flags(void)
20{
21 unsigned long flags;
22
23 __asm__ __volatile__("lbz %0,%1(13)"
24 : "=r" (flags)
25 : "i" (offsetof(struct paca_struct, soft_enabled)));
26
27 return flags;
28}
29
30static inline unsigned long raw_local_irq_disable(void)
31{
32 unsigned long flags, zero;
33
34 __asm__ __volatile__("li %1,0; lbz %0,%2(13); stb %1,%2(13)"
35 : "=r" (flags), "=&r" (zero)
36 : "i" (offsetof(struct paca_struct, soft_enabled))
37 : "memory");
38
39 return flags;
40}
41
42extern void raw_local_irq_restore(unsigned long);
43extern void iseries_handle_interrupts(void);
44
45#define raw_local_irq_enable() raw_local_irq_restore(1)
46#define raw_local_save_flags(flags) ((flags) = local_get_flags())
47#define raw_local_irq_save(flags) ((flags) = raw_local_irq_disable())
48
49#define raw_irqs_disabled() (local_get_flags() == 0)
50#define raw_irqs_disabled_flags(flags) ((flags) == 0)
51
52#define __hard_irq_enable() __mtmsrd(mfmsr() | MSR_EE, 1)
53#define __hard_irq_disable() __mtmsrd(mfmsr() & ~MSR_EE, 1)
54
55#define hard_irq_disable() \
56 do { \
57 __hard_irq_disable(); \
58 get_paca()->soft_enabled = 0; \
59 get_paca()->hard_enabled = 0; \
60 } while(0)
61
62static inline int irqs_disabled_flags(unsigned long flags)
63{
64 return flags == 0;
65}
66
67#else
68
69#if defined(CONFIG_BOOKE)
70#define SET_MSR_EE(x) mtmsr(x)
71#define local_irq_restore(flags) __asm__ __volatile__("wrtee %0" : : "r" (flags) : "memory")
72#else
73#define SET_MSR_EE(x) mtmsr(x)
74#define local_irq_restore(flags) mtmsr(flags)
75#endif
76
77static inline void local_irq_disable(void)
78{
79#ifdef CONFIG_BOOKE
80 __asm__ __volatile__("wrteei 0": : :"memory");
81#else
82 unsigned long msr;
83 __asm__ __volatile__("": : :"memory");
84 msr = mfmsr();
85 SET_MSR_EE(msr & ~MSR_EE);
86#endif
87}
88
89static inline void local_irq_enable(void)
90{
91#ifdef CONFIG_BOOKE
92 __asm__ __volatile__("wrteei 1": : :"memory");
93#else
94 unsigned long msr;
95 __asm__ __volatile__("": : :"memory");
96 msr = mfmsr();
97 SET_MSR_EE(msr | MSR_EE);
98#endif
99}
100
101static inline void local_irq_save_ptr(unsigned long *flags)
102{
103 unsigned long msr;
104 msr = mfmsr();
105 *flags = msr;
106#ifdef CONFIG_BOOKE
107 __asm__ __volatile__("wrteei 0": : :"memory");
108#else
109 SET_MSR_EE(msr & ~MSR_EE);
110#endif
111 __asm__ __volatile__("": : :"memory");
112}
113
114#define local_save_flags(flags) ((flags) = mfmsr())
115#define local_irq_save(flags) local_irq_save_ptr(&flags)
116#define irqs_disabled() ((mfmsr() & MSR_EE) == 0)
117
118#define hard_irq_enable() local_irq_enable()
119#define hard_irq_disable() local_irq_disable()
120
121static inline int irqs_disabled_flags(unsigned long flags)
122{
123 return (flags & MSR_EE) == 0;
124}
125
126#endif /* CONFIG_PPC64 */
127
128/*
129 * interrupt-retrigger: should we handle this via lost interrupts and IPIs
130 * or should we not care like we do now ? --BenH.
131 */
132struct hw_interrupt_type;
133
134#endif /* __KERNEL__ */
135#endif /* _ASM_POWERPC_HW_IRQ_H */
diff --git a/include/asm-powerpc/hydra.h b/include/asm-powerpc/hydra.h
deleted file mode 100644
index 1ad4eed07fb..00000000000
--- a/include/asm-powerpc/hydra.h
+++ /dev/null
@@ -1,102 +0,0 @@
1/*
2 * include/asm-ppc/hydra.h -- Mac I/O `Hydra' definitions
3 *
4 * Copyright (C) 1997 Geert Uytterhoeven
5 *
6 * This file is based on the following documentation:
7 *
8 * Macintosh Technology in the Common Hardware Reference Platform
9 * Apple Computer, Inc.
10 *
11 * © Copyright 1995 Apple Computer, Inc. All rights reserved.
12 *
13 * It's available online from http://chrp.apple.com/MacTech.pdf.
14 * You can obtain paper copies of this book from computer bookstores or by
15 * writing Morgan Kaufmann Publishers, Inc., 340 Pine Street, Sixth Floor, San
16 * Francisco, CA 94104. Reference ISBN 1-55860-393-X.
17 *
18 * This file is subject to the terms and conditions of the GNU General Public
19 * License. See the file COPYING in the main directory of this archive
20 * for more details.
21 */
22
23#ifndef _ASMPPC_HYDRA_H
24#define _ASMPPC_HYDRA_H
25
26#ifdef __KERNEL__
27
28struct Hydra {
29 /* DBDMA Controller Register Space */
30 char Pad1[0x30];
31 u_int CachePD;
32 u_int IDs;
33 u_int Feature_Control;
34 char Pad2[0x7fc4];
35 /* DBDMA Channel Register Space */
36 char SCSI_DMA[0x100];
37 char Pad3[0x300];
38 char SCCA_Tx_DMA[0x100];
39 char SCCA_Rx_DMA[0x100];
40 char SCCB_Tx_DMA[0x100];
41 char SCCB_Rx_DMA[0x100];
42 char Pad4[0x7800];
43 /* Device Register Space */
44 char SCSI[0x1000];
45 char ADB[0x1000];
46 char SCC_Legacy[0x1000];
47 char SCC[0x1000];
48 char Pad9[0x2000];
49 char VIA[0x2000];
50 char Pad10[0x28000];
51 char OpenPIC[0x40000];
52};
53
54extern volatile struct Hydra __iomem *Hydra;
55
56
57 /*
58 * Feature Control Register
59 */
60
61#define HYDRA_FC_SCC_CELL_EN 0x00000001 /* Enable SCC Clock */
62#define HYDRA_FC_SCSI_CELL_EN 0x00000002 /* Enable SCSI Clock */
63#define HYDRA_FC_SCCA_ENABLE 0x00000004 /* Enable SCC A Lines */
64#define HYDRA_FC_SCCB_ENABLE 0x00000008 /* Enable SCC B Lines */
65#define HYDRA_FC_ARB_BYPASS 0x00000010 /* Bypass Internal Arbiter */
66#define HYDRA_FC_RESET_SCC 0x00000020 /* Reset SCC */
67#define HYDRA_FC_MPIC_ENABLE 0x00000040 /* Enable OpenPIC */
68#define HYDRA_FC_SLOW_SCC_PCLK 0x00000080 /* 1=15.6672, 0=25 MHz */
69#define HYDRA_FC_MPIC_IS_MASTER 0x00000100 /* OpenPIC Master Mode */
70
71
72 /*
73 * OpenPIC Interrupt Sources
74 */
75
76#define HYDRA_INT_SIO 0
77#define HYDRA_INT_SCSI_DMA 1
78#define HYDRA_INT_SCCA_TX_DMA 2
79#define HYDRA_INT_SCCA_RX_DMA 3
80#define HYDRA_INT_SCCB_TX_DMA 4
81#define HYDRA_INT_SCCB_RX_DMA 5
82#define HYDRA_INT_SCSI 6
83#define HYDRA_INT_SCCA 7
84#define HYDRA_INT_SCCB 8
85#define HYDRA_INT_VIA 9
86#define HYDRA_INT_ADB 10
87#define HYDRA_INT_ADB_NMI 11
88#define HYDRA_INT_EXT1 12 /* PCI IRQW */
89#define HYDRA_INT_EXT2 13 /* PCI IRQX */
90#define HYDRA_INT_EXT3 14 /* PCI IRQY */
91#define HYDRA_INT_EXT4 15 /* PCI IRQZ */
92#define HYDRA_INT_EXT5 16 /* IDE Primay/Secondary */
93#define HYDRA_INT_EXT6 17 /* IDE Secondary */
94#define HYDRA_INT_EXT7 18 /* Power Off Request */
95#define HYDRA_INT_SPARE 19
96
97extern int hydra_init(void);
98extern void macio_adb_init(void);
99
100#endif /* __KERNEL__ */
101
102#endif /* _ASMPPC_HYDRA_H */
diff --git a/include/asm-powerpc/i8259.h b/include/asm-powerpc/i8259.h
deleted file mode 100644
index db1362f8c60..00000000000
--- a/include/asm-powerpc/i8259.h
+++ /dev/null
@@ -1,17 +0,0 @@
1#ifndef _ASM_POWERPC_I8259_H
2#define _ASM_POWERPC_I8259_H
3#ifdef __KERNEL__
4
5#include <linux/irq.h>
6
7#ifdef CONFIG_PPC_MERGE
8extern void i8259_init(struct device_node *node, unsigned long intack_addr);
9extern unsigned int i8259_irq(void);
10extern struct irq_host *i8259_get_host(void);
11#else
12extern void i8259_init(unsigned long intack_addr, int offset);
13extern int i8259_irq(void);
14#endif
15
16#endif /* __KERNEL__ */
17#endif /* _ASM_POWERPC_I8259_H */
diff --git a/include/asm-powerpc/ibmebus.h b/include/asm-powerpc/ibmebus.h
deleted file mode 100644
index 1a9d9aea21f..00000000000
--- a/include/asm-powerpc/ibmebus.h
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 * IBM PowerPC eBus Infrastructure Support.
3 *
4 * Copyright (c) 2005 IBM Corporation
5 * Joachim Fenkes <fenkes@de.ibm.com>
6 * Heiko J Schick <schickhj@de.ibm.com>
7 *
8 * All rights reserved.
9 *
10 * This source code is distributed under a dual license of GPL v2.0 and OpenIB
11 * BSD.
12 *
13 * OpenIB BSD License
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are met:
17 *
18 * Redistributions of source code must retain the above copyright notice, this
19 * list of conditions and the following disclaimer.
20 *
21 * Redistributions in binary form must reproduce the above copyright notice,
22 * this list of conditions and the following disclaimer in the documentation
23 * and/or other materials
24 * provided with the distribution.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
27 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
30 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
33 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
34 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#ifndef _ASM_EBUS_H
40#define _ASM_EBUS_H
41#ifdef __KERNEL__
42
43#include <linux/device.h>
44#include <linux/interrupt.h>
45#include <linux/mod_devicetable.h>
46#include <linux/of_device.h>
47#include <linux/of_platform.h>
48
49extern struct bus_type ibmebus_bus_type;
50
51int ibmebus_register_driver(struct of_platform_driver *drv);
52void ibmebus_unregister_driver(struct of_platform_driver *drv);
53
54int ibmebus_request_irq(u32 ist, irq_handler_t handler,
55 unsigned long irq_flags, const char *devname,
56 void *dev_id);
57void ibmebus_free_irq(u32 ist, void *dev_id);
58
59#endif /* __KERNEL__ */
60#endif /* _ASM_IBMEBUS_H */
diff --git a/include/asm-powerpc/ide.h b/include/asm-powerpc/ide.h
deleted file mode 100644
index 1aaf27be874..00000000000
--- a/include/asm-powerpc/ide.h
+++ /dev/null
@@ -1,59 +0,0 @@
1/*
2 * Copyright (C) 1994-1996 Linus Torvalds & authors
3 *
4 * This file contains the powerpc architecture specific IDE code.
5 */
6#ifndef _ASM_POWERPC_IDE_H
7#define _ASM_POWERPC_IDE_H
8
9#ifdef __KERNEL__
10
11#ifndef __powerpc64__
12#include <linux/sched.h>
13#include <asm/mpc8xx.h>
14#endif
15#include <asm/io.h>
16
17#define __ide_mm_insw(p, a, c) readsw((void __iomem *)(p), (a), (c))
18#define __ide_mm_insl(p, a, c) readsl((void __iomem *)(p), (a), (c))
19#define __ide_mm_outsw(p, a, c) writesw((void __iomem *)(p), (a), (c))
20#define __ide_mm_outsl(p, a, c) writesl((void __iomem *)(p), (a), (c))
21
22#ifndef __powerpc64__
23#include <linux/hdreg.h>
24#include <linux/ioport.h>
25
26/* FIXME: use ide_platform host driver */
27static __inline__ int ide_default_irq(unsigned long base)
28{
29#ifdef CONFIG_PPLUS
30 switch (base) {
31 case 0x1f0: return 14;
32 case 0x170: return 15;
33 }
34#endif
35 return 0;
36}
37
38/* FIXME: use ide_platform host driver */
39static __inline__ unsigned long ide_default_io_base(int index)
40{
41#ifdef CONFIG_PPLUS
42 switch (index) {
43 case 0: return 0x1f0;
44 case 1: return 0x170;
45 }
46#endif
47 return 0;
48}
49
50#ifdef CONFIG_BLK_DEV_MPC8xx_IDE
51#define IDE_ARCH_ACK_INTR 1
52#define ide_ack_intr(hwif) ((hwif)->ack_intr ? (hwif)->ack_intr(hwif) : 1)
53#endif
54
55#endif /* __powerpc64__ */
56
57#endif /* __KERNEL__ */
58
59#endif /* _ASM_POWERPC_IDE_H */
diff --git a/include/asm-powerpc/immap_86xx.h b/include/asm-powerpc/immap_86xx.h
deleted file mode 100644
index 0f165e59c32..00000000000
--- a/include/asm-powerpc/immap_86xx.h
+++ /dev/null
@@ -1,156 +0,0 @@
1/**
2 * MPC86xx Internal Memory Map
3 *
4 * Authors: Jeff Brown
5 * Timur Tabi <timur@freescale.com>
6 *
7 * Copyright 2004,2007 Freescale Semiconductor, Inc
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * This header file defines structures for various 86xx SOC devices that are
15 * used by multiple source files.
16 */
17
18#ifndef __ASM_POWERPC_IMMAP_86XX_H__
19#define __ASM_POWERPC_IMMAP_86XX_H__
20#ifdef __KERNEL__
21
22/* Global Utility Registers */
23struct ccsr_guts {
24 __be32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
25 __be32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
26 __be32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */
27 __be32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
28 __be32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
29 u8 res1[0x20 - 0x14];
30 __be32 porcir; /* 0x.0020 - POR Configuration Information Register */
31 u8 res2[0x30 - 0x24];
32 __be32 gpiocr; /* 0x.0030 - GPIO Control Register */
33 u8 res3[0x40 - 0x34];
34 __be32 gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */
35 u8 res4[0x50 - 0x44];
36 __be32 gpindr; /* 0x.0050 - General-Purpose Input Data Register */
37 u8 res5[0x60 - 0x54];
38 __be32 pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */
39 u8 res6[0x70 - 0x64];
40 __be32 devdisr; /* 0x.0070 - Device Disable Control */
41 __be32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
42 u8 res7[0x80 - 0x78];
43 __be32 powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */
44 u8 res8[0x90 - 0x84];
45 __be32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */
46 __be32 rstrscr; /* 0x.0094 - Reset Request Status and Control Register */
47 u8 res9[0xA0 - 0x98];
48 __be32 pvr; /* 0x.00a0 - Processor Version Register */
49 __be32 svr; /* 0x.00a4 - System Version Register */
50 u8 res10[0xB0 - 0xA8];
51 __be32 rstcr; /* 0x.00b0 - Reset Control Register */
52 u8 res11[0xC0 - 0xB4];
53 __be32 elbcvselcr; /* 0x.00c0 - eLBC Voltage Select Ctrl Reg */
54 u8 res12[0x800 - 0xC4];
55 __be32 clkdvdr; /* 0x.0800 - Clock Divide Register */
56 u8 res13[0x900 - 0x804];
57 __be32 ircr; /* 0x.0900 - Infrared Control Register */
58 u8 res14[0x908 - 0x904];
59 __be32 dmacr; /* 0x.0908 - DMA Control Register */
60 u8 res15[0x914 - 0x90C];
61 __be32 elbccr; /* 0x.0914 - eLBC Control Register */
62 u8 res16[0xB20 - 0x918];
63 __be32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */
64 __be32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */
65 __be32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */
66 u8 res17[0xE00 - 0xB2C];
67 __be32 clkocr; /* 0x.0e00 - Clock Out Select Register */
68 u8 res18[0xE10 - 0xE04];
69 __be32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
70 u8 res19[0xE20 - 0xE14];
71 __be32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
72 u8 res20[0xF04 - 0xE24];
73 __be32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */
74 __be32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */
75 u8 res21[0xF40 - 0xF0C];
76 __be32 srds2cr0; /* 0x.0f40 - SerDes1 Control Register 0 */
77 __be32 srds2cr1; /* 0x.0f44 - SerDes1 Control Register 0 */
78} __attribute__ ((packed));
79
80#define CCSR_GUTS_DMACR_DEV_SSI 0 /* DMA controller/channel set to SSI */
81#define CCSR_GUTS_DMACR_DEV_IR 1 /* DMA controller/channel set to IR */
82
83/*
84 * Set the DMACR register in the GUTS
85 *
86 * The DMACR register determines the source of initiated transfers for each
87 * channel on each DMA controller. Rather than have a bunch of repetitive
88 * macros for the bit patterns, we just have a function that calculates
89 * them.
90 *
91 * guts: Pointer to GUTS structure
92 * co: The DMA controller (0 or 1)
93 * ch: The channel on the DMA controller (0, 1, 2, or 3)
94 * device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx)
95 */
96static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts,
97 unsigned int co, unsigned int ch, unsigned int device)
98{
99 unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch));
100
101 clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift);
102}
103
104#define CCSR_GUTS_PMUXCR_LDPSEL 0x00010000
105#define CCSR_GUTS_PMUXCR_SSI1_MASK 0x0000C000 /* Bitmask for SSI1 */
106#define CCSR_GUTS_PMUXCR_SSI1_LA 0x00000000 /* Latched address */
107#define CCSR_GUTS_PMUXCR_SSI1_HI 0x00004000 /* High impedance */
108#define CCSR_GUTS_PMUXCR_SSI1_SSI 0x00008000 /* Used for SSI1 */
109#define CCSR_GUTS_PMUXCR_SSI2_MASK 0x00003000 /* Bitmask for SSI2 */
110#define CCSR_GUTS_PMUXCR_SSI2_LA 0x00000000 /* Latched address */
111#define CCSR_GUTS_PMUXCR_SSI2_HI 0x00001000 /* High impedance */
112#define CCSR_GUTS_PMUXCR_SSI2_SSI 0x00002000 /* Used for SSI2 */
113#define CCSR_GUTS_PMUXCR_LA_22_25_LA 0x00000000 /* Latched Address */
114#define CCSR_GUTS_PMUXCR_LA_22_25_HI 0x00000400 /* High impedance */
115#define CCSR_GUTS_PMUXCR_DBGDRV 0x00000200 /* Signals not driven */
116#define CCSR_GUTS_PMUXCR_DMA2_0 0x00000008
117#define CCSR_GUTS_PMUXCR_DMA2_3 0x00000004
118#define CCSR_GUTS_PMUXCR_DMA1_0 0x00000002
119#define CCSR_GUTS_PMUXCR_DMA1_3 0x00000001
120
121/*
122 * Set the DMA external control bits in the GUTS
123 *
124 * The DMA external control bits in the PMUXCR are only meaningful for
125 * channels 0 and 3. Any other channels are ignored.
126 *
127 * guts: Pointer to GUTS structure
128 * co: The DMA controller (0 or 1)
129 * ch: The channel on the DMA controller (0, 1, 2, or 3)
130 * value: the new value for the bit (0 or 1)
131 */
132static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts,
133 unsigned int co, unsigned int ch, unsigned int value)
134{
135 if ((ch == 0) || (ch == 3)) {
136 unsigned int shift = 2 * (co + 1) - (ch & 1) - 1;
137
138 clrsetbits_be32(&guts->pmuxcr, 1 << shift, value << shift);
139 }
140}
141
142#define CCSR_GUTS_CLKDVDR_PXCKEN 0x80000000
143#define CCSR_GUTS_CLKDVDR_SSICKEN 0x20000000
144#define CCSR_GUTS_CLKDVDR_PXCKINV 0x10000000
145#define CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT 25
146#define CCSR_GUTS_CLKDVDR_PXCKDLY_MASK 0x06000000
147#define CCSR_GUTS_CLKDVDR_PXCKDLY(x) \
148 (((x) & 3) << CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT)
149#define CCSR_GUTS_CLKDVDR_PXCLK_SHIFT 16
150#define CCSR_GUTS_CLKDVDR_PXCLK_MASK 0x001F0000
151#define CCSR_GUTS_CLKDVDR_PXCLK(x) (((x) & 31) << CCSR_GUTS_CLKDVDR_PXCLK_SHIFT)
152#define CCSR_GUTS_CLKDVDR_SSICLK_MASK 0x000000FF
153#define CCSR_GUTS_CLKDVDR_SSICLK(x) ((x) & CCSR_GUTS_CLKDVDR_SSICLK_MASK)
154
155#endif /* __ASM_POWERPC_IMMAP_86XX_H__ */
156#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/immap_cpm2.h b/include/asm-powerpc/immap_cpm2.h
deleted file mode 100644
index 4080bab0468..00000000000
--- a/include/asm-powerpc/immap_cpm2.h
+++ /dev/null
@@ -1,650 +0,0 @@
1/*
2 * CPM2 Internal Memory Map
3 * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
4 *
5 * The Internal Memory Map for devices with CPM2 on them. This
6 * is the superset of all CPM2 devices (8260, 8266, 8280, 8272,
7 * 8560).
8 */
9#ifdef __KERNEL__
10#ifndef __IMMAP_CPM2__
11#define __IMMAP_CPM2__
12
13#include <linux/types.h>
14
15/* System configuration registers.
16*/
17typedef struct sys_82xx_conf {
18 u32 sc_siumcr;
19 u32 sc_sypcr;
20 u8 res1[6];
21 u16 sc_swsr;
22 u8 res2[20];
23 u32 sc_bcr;
24 u8 sc_ppc_acr;
25 u8 res3[3];
26 u32 sc_ppc_alrh;
27 u32 sc_ppc_alrl;
28 u8 sc_lcl_acr;
29 u8 res4[3];
30 u32 sc_lcl_alrh;
31 u32 sc_lcl_alrl;
32 u32 sc_tescr1;
33 u32 sc_tescr2;
34 u32 sc_ltescr1;
35 u32 sc_ltescr2;
36 u32 sc_pdtea;
37 u8 sc_pdtem;
38 u8 res5[3];
39 u32 sc_ldtea;
40 u8 sc_ldtem;
41 u8 res6[163];
42} sysconf_82xx_cpm2_t;
43
44typedef struct sys_85xx_conf {
45 u32 sc_cear;
46 u16 sc_ceer;
47 u16 sc_cemr;
48 u8 res1[70];
49 u32 sc_smaer;
50 u8 res2[4];
51 u32 sc_smevr;
52 u32 sc_smctr;
53 u32 sc_lmaer;
54 u8 res3[4];
55 u32 sc_lmevr;
56 u32 sc_lmctr;
57 u8 res4[144];
58} sysconf_85xx_cpm2_t;
59
60typedef union sys_conf {
61 sysconf_82xx_cpm2_t siu_82xx;
62 sysconf_85xx_cpm2_t siu_85xx;
63} sysconf_cpm2_t;
64
65
66
67/* Memory controller registers.
68*/
69typedef struct mem_ctlr {
70 u32 memc_br0;
71 u32 memc_or0;
72 u32 memc_br1;
73 u32 memc_or1;
74 u32 memc_br2;
75 u32 memc_or2;
76 u32 memc_br3;
77 u32 memc_or3;
78 u32 memc_br4;
79 u32 memc_or4;
80 u32 memc_br5;
81 u32 memc_or5;
82 u32 memc_br6;
83 u32 memc_or6;
84 u32 memc_br7;
85 u32 memc_or7;
86 u32 memc_br8;
87 u32 memc_or8;
88 u32 memc_br9;
89 u32 memc_or9;
90 u32 memc_br10;
91 u32 memc_or10;
92 u32 memc_br11;
93 u32 memc_or11;
94 u8 res1[8];
95 u32 memc_mar;
96 u8 res2[4];
97 u32 memc_mamr;
98 u32 memc_mbmr;
99 u32 memc_mcmr;
100 u8 res3[8];
101 u16 memc_mptpr;
102 u8 res4[2];
103 u32 memc_mdr;
104 u8 res5[4];
105 u32 memc_psdmr;
106 u32 memc_lsdmr;
107 u8 memc_purt;
108 u8 res6[3];
109 u8 memc_psrt;
110 u8 res7[3];
111 u8 memc_lurt;
112 u8 res8[3];
113 u8 memc_lsrt;
114 u8 res9[3];
115 u32 memc_immr;
116 u32 memc_pcibr0;
117 u32 memc_pcibr1;
118 u8 res10[16];
119 u32 memc_pcimsk0;
120 u32 memc_pcimsk1;
121 u8 res11[52];
122} memctl_cpm2_t;
123
124/* System Integration Timers.
125*/
126typedef struct sys_int_timers {
127 u8 res1[32];
128 u16 sit_tmcntsc;
129 u8 res2[2];
130 u32 sit_tmcnt;
131 u8 res3[4];
132 u32 sit_tmcntal;
133 u8 res4[16];
134 u16 sit_piscr;
135 u8 res5[2];
136 u32 sit_pitc;
137 u32 sit_pitr;
138 u8 res6[94];
139 u8 res7[390];
140} sit_cpm2_t;
141
142#define PISCR_PIRQ_MASK ((u16)0xff00)
143#define PISCR_PS ((u16)0x0080)
144#define PISCR_PIE ((u16)0x0004)
145#define PISCR_PTF ((u16)0x0002)
146#define PISCR_PTE ((u16)0x0001)
147
148/* PCI Controller.
149*/
150typedef struct pci_ctlr {
151 u32 pci_omisr;
152 u32 pci_omimr;
153 u8 res1[8];
154 u32 pci_ifqpr;
155 u32 pci_ofqpr;
156 u8 res2[8];
157 u32 pci_imr0;
158 u32 pci_imr1;
159 u32 pci_omr0;
160 u32 pci_omr1;
161 u32 pci_odr;
162 u8 res3[4];
163 u32 pci_idr;
164 u8 res4[20];
165 u32 pci_imisr;
166 u32 pci_imimr;
167 u8 res5[24];
168 u32 pci_ifhpr;
169 u8 res6[4];
170 u32 pci_iftpr;
171 u8 res7[4];
172 u32 pci_iphpr;
173 u8 res8[4];
174 u32 pci_iptpr;
175 u8 res9[4];
176 u32 pci_ofhpr;
177 u8 res10[4];
178 u32 pci_oftpr;
179 u8 res11[4];
180 u32 pci_ophpr;
181 u8 res12[4];
182 u32 pci_optpr;
183 u8 res13[8];
184 u32 pci_mucr;
185 u8 res14[8];
186 u32 pci_qbar;
187 u8 res15[12];
188 u32 pci_dmamr0;
189 u32 pci_dmasr0;
190 u32 pci_dmacdar0;
191 u8 res16[4];
192 u32 pci_dmasar0;
193 u8 res17[4];
194 u32 pci_dmadar0;
195 u8 res18[4];
196 u32 pci_dmabcr0;
197 u32 pci_dmandar0;
198 u8 res19[86];
199 u32 pci_dmamr1;
200 u32 pci_dmasr1;
201 u32 pci_dmacdar1;
202 u8 res20[4];
203 u32 pci_dmasar1;
204 u8 res21[4];
205 u32 pci_dmadar1;
206 u8 res22[4];
207 u32 pci_dmabcr1;
208 u32 pci_dmandar1;
209 u8 res23[88];
210 u32 pci_dmamr2;
211 u32 pci_dmasr2;
212 u32 pci_dmacdar2;
213 u8 res24[4];
214 u32 pci_dmasar2;
215 u8 res25[4];
216 u32 pci_dmadar2;
217 u8 res26[4];
218 u32 pci_dmabcr2;
219 u32 pci_dmandar2;
220 u8 res27[88];
221 u32 pci_dmamr3;
222 u32 pci_dmasr3;
223 u32 pci_dmacdar3;
224 u8 res28[4];
225 u32 pci_dmasar3;
226 u8 res29[4];
227 u32 pci_dmadar3;
228 u8 res30[4];
229 u32 pci_dmabcr3;
230 u32 pci_dmandar3;
231 u8 res31[344];
232 u32 pci_potar0;
233 u8 res32[4];
234 u32 pci_pobar0;
235 u8 res33[4];
236 u32 pci_pocmr0;
237 u8 res34[4];
238 u32 pci_potar1;
239 u8 res35[4];
240 u32 pci_pobar1;
241 u8 res36[4];
242 u32 pci_pocmr1;
243 u8 res37[4];
244 u32 pci_potar2;
245 u8 res38[4];
246 u32 pci_pobar2;
247 u8 res39[4];
248 u32 pci_pocmr2;
249 u8 res40[50];
250 u32 pci_ptcr;
251 u32 pci_gpcr;
252 u32 pci_gcr;
253 u32 pci_esr;
254 u32 pci_emr;
255 u32 pci_ecr;
256 u32 pci_eacr;
257 u8 res41[4];
258 u32 pci_edcr;
259 u8 res42[4];
260 u32 pci_eccr;
261 u8 res43[44];
262 u32 pci_pitar1;
263 u8 res44[4];
264 u32 pci_pibar1;
265 u8 res45[4];
266 u32 pci_picmr1;
267 u8 res46[4];
268 u32 pci_pitar0;
269 u8 res47[4];
270 u32 pci_pibar0;
271 u8 res48[4];
272 u32 pci_picmr0;
273 u8 res49[4];
274 u32 pci_cfg_addr;
275 u32 pci_cfg_data;
276 u32 pci_int_ack;
277 u8 res50[756];
278} pci_cpm2_t;
279
280/* Interrupt Controller.
281*/
282typedef struct interrupt_controller {
283 u16 ic_sicr;
284 u8 res1[2];
285 u32 ic_sivec;
286 u32 ic_sipnrh;
287 u32 ic_sipnrl;
288 u32 ic_siprr;
289 u32 ic_scprrh;
290 u32 ic_scprrl;
291 u32 ic_simrh;
292 u32 ic_simrl;
293 u32 ic_siexr;
294 u8 res2[88];
295} intctl_cpm2_t;
296
297/* Clocks and Reset.
298*/
299typedef struct clk_and_reset {
300 u32 car_sccr;
301 u8 res1[4];
302 u32 car_scmr;
303 u8 res2[4];
304 u32 car_rsr;
305 u32 car_rmr;
306 u8 res[104];
307} car_cpm2_t;
308
309/* Input/Output Port control/status registers.
310 * Names consistent with processor manual, although they are different
311 * from the original 8xx names.......
312 */
313typedef struct io_port {
314 u32 iop_pdira;
315 u32 iop_ppara;
316 u32 iop_psora;
317 u32 iop_podra;
318 u32 iop_pdata;
319 u8 res1[12];
320 u32 iop_pdirb;
321 u32 iop_pparb;
322 u32 iop_psorb;
323 u32 iop_podrb;
324 u32 iop_pdatb;
325 u8 res2[12];
326 u32 iop_pdirc;
327 u32 iop_pparc;
328 u32 iop_psorc;
329 u32 iop_podrc;
330 u32 iop_pdatc;
331 u8 res3[12];
332 u32 iop_pdird;
333 u32 iop_ppard;
334 u32 iop_psord;
335 u32 iop_podrd;
336 u32 iop_pdatd;
337 u8 res4[12];
338} iop_cpm2_t;
339
340/* Communication Processor Module Timers
341*/
342typedef struct cpm_timers {
343 u8 cpmt_tgcr1;
344 u8 res1[3];
345 u8 cpmt_tgcr2;
346 u8 res2[11];
347 u16 cpmt_tmr1;
348 u16 cpmt_tmr2;
349 u16 cpmt_trr1;
350 u16 cpmt_trr2;
351 u16 cpmt_tcr1;
352 u16 cpmt_tcr2;
353 u16 cpmt_tcn1;
354 u16 cpmt_tcn2;
355 u16 cpmt_tmr3;
356 u16 cpmt_tmr4;
357 u16 cpmt_trr3;
358 u16 cpmt_trr4;
359 u16 cpmt_tcr3;
360 u16 cpmt_tcr4;
361 u16 cpmt_tcn3;
362 u16 cpmt_tcn4;
363 u16 cpmt_ter1;
364 u16 cpmt_ter2;
365 u16 cpmt_ter3;
366 u16 cpmt_ter4;
367 u8 res3[584];
368} cpmtimer_cpm2_t;
369
370/* DMA control/status registers.
371*/
372typedef struct sdma_csr {
373 u8 res0[24];
374 u8 sdma_sdsr;
375 u8 res1[3];
376 u8 sdma_sdmr;
377 u8 res2[3];
378 u8 sdma_idsr1;
379 u8 res3[3];
380 u8 sdma_idmr1;
381 u8 res4[3];
382 u8 sdma_idsr2;
383 u8 res5[3];
384 u8 sdma_idmr2;
385 u8 res6[3];
386 u8 sdma_idsr3;
387 u8 res7[3];
388 u8 sdma_idmr3;
389 u8 res8[3];
390 u8 sdma_idsr4;
391 u8 res9[3];
392 u8 sdma_idmr4;
393 u8 res10[707];
394} sdma_cpm2_t;
395
396/* Fast controllers
397*/
398typedef struct fcc {
399 u32 fcc_gfmr;
400 u32 fcc_fpsmr;
401 u16 fcc_ftodr;
402 u8 res1[2];
403 u16 fcc_fdsr;
404 u8 res2[2];
405 u16 fcc_fcce;
406 u8 res3[2];
407 u16 fcc_fccm;
408 u8 res4[2];
409 u8 fcc_fccs;
410 u8 res5[3];
411 u8 fcc_ftirr_phy[4];
412} fcc_t;
413
414/* Fast controllers continued
415 */
416typedef struct fcc_c {
417 u32 fcc_firper;
418 u32 fcc_firer;
419 u32 fcc_firsr_hi;
420 u32 fcc_firsr_lo;
421 u8 fcc_gfemr;
422 u8 res1[15];
423} fcc_c_t;
424
425/* TC Layer
426 */
427typedef struct tclayer {
428 u16 tc_tcmode;
429 u16 tc_cdsmr;
430 u16 tc_tcer;
431 u16 tc_rcc;
432 u16 tc_tcmr;
433 u16 tc_fcc;
434 u16 tc_ccc;
435 u16 tc_icc;
436 u16 tc_tcc;
437 u16 tc_ecc;
438 u8 res1[12];
439} tclayer_t;
440
441
442/* I2C
443*/
444typedef struct i2c {
445 u8 i2c_i2mod;
446 u8 res1[3];
447 u8 i2c_i2add;
448 u8 res2[3];
449 u8 i2c_i2brg;
450 u8 res3[3];
451 u8 i2c_i2com;
452 u8 res4[3];
453 u8 i2c_i2cer;
454 u8 res5[3];
455 u8 i2c_i2cmr;
456 u8 res6[331];
457} i2c_cpm2_t;
458
459typedef struct scc { /* Serial communication channels */
460 u32 scc_gsmrl;
461 u32 scc_gsmrh;
462 u16 scc_psmr;
463 u8 res1[2];
464 u16 scc_todr;
465 u16 scc_dsr;
466 u16 scc_scce;
467 u8 res2[2];
468 u16 scc_sccm;
469 u8 res3;
470 u8 scc_sccs;
471 u8 res4[8];
472} scc_t;
473
474typedef struct smc { /* Serial management channels */
475 u8 res1[2];
476 u16 smc_smcmr;
477 u8 res2[2];
478 u8 smc_smce;
479 u8 res3[3];
480 u8 smc_smcm;
481 u8 res4[5];
482} smc_t;
483
484/* Serial Peripheral Interface.
485*/
486typedef struct spi_ctrl {
487 u16 spi_spmode;
488 u8 res1[4];
489 u8 spi_spie;
490 u8 res2[3];
491 u8 spi_spim;
492 u8 res3[2];
493 u8 spi_spcom;
494 u8 res4[82];
495} spictl_cpm2_t;
496
497/* CPM Mux.
498*/
499typedef struct cpmux {
500 u8 cmx_si1cr;
501 u8 res1;
502 u8 cmx_si2cr;
503 u8 res2;
504 u32 cmx_fcr;
505 u32 cmx_scr;
506 u8 cmx_smr;
507 u8 res3;
508 u16 cmx_uar;
509 u8 res4[16];
510} cpmux_t;
511
512/* SIRAM control
513*/
514typedef struct siram {
515 u16 si_amr;
516 u16 si_bmr;
517 u16 si_cmr;
518 u16 si_dmr;
519 u8 si_gmr;
520 u8 res1;
521 u8 si_cmdr;
522 u8 res2;
523 u8 si_str;
524 u8 res3;
525 u16 si_rsr;
526} siramctl_t;
527
528typedef struct mcc {
529 u16 mcc_mcce;
530 u8 res1[2];
531 u16 mcc_mccm;
532 u8 res2[2];
533 u8 mcc_mccf;
534 u8 res3[7];
535} mcc_t;
536
537typedef struct comm_proc {
538 u32 cp_cpcr;
539 u32 cp_rccr;
540 u8 res1[14];
541 u16 cp_rter;
542 u8 res2[2];
543 u16 cp_rtmr;
544 u16 cp_rtscr;
545 u8 res3[2];
546 u32 cp_rtsr;
547 u8 res4[12];
548} cpm_cpm2_t;
549
550/* USB Controller.
551*/
552typedef struct usb_ctlr {
553 u8 usb_usmod;
554 u8 usb_usadr;
555 u8 usb_uscom;
556 u8 res1[1];
557 u16 usb_usep1;
558 u16 usb_usep2;
559 u16 usb_usep3;
560 u16 usb_usep4;
561 u8 res2[4];
562 u16 usb_usber;
563 u8 res3[2];
564 u16 usb_usbmr;
565 u8 usb_usbs;
566 u8 res4[7];
567} usb_cpm2_t;
568
569/* ...and the whole thing wrapped up....
570*/
571
572typedef struct immap {
573 /* Some references are into the unique and known dpram spaces,
574 * others are from the generic base.
575 */
576#define im_dprambase im_dpram1
577 u8 im_dpram1[16*1024];
578 u8 res1[16*1024];
579 u8 im_dpram2[4*1024];
580 u8 res2[8*1024];
581 u8 im_dpram3[4*1024];
582 u8 res3[16*1024];
583
584 sysconf_cpm2_t im_siu_conf; /* SIU Configuration */
585 memctl_cpm2_t im_memctl; /* Memory Controller */
586 sit_cpm2_t im_sit; /* System Integration Timers */
587 pci_cpm2_t im_pci; /* PCI Controller */
588 intctl_cpm2_t im_intctl; /* Interrupt Controller */
589 car_cpm2_t im_clkrst; /* Clocks and reset */
590 iop_cpm2_t im_ioport; /* IO Port control/status */
591 cpmtimer_cpm2_t im_cpmtimer; /* CPM timers */
592 sdma_cpm2_t im_sdma; /* SDMA control/status */
593
594 fcc_t im_fcc[3]; /* Three FCCs */
595 u8 res4z[32];
596 fcc_c_t im_fcc_c[3]; /* Continued FCCs */
597
598 u8 res4[32];
599
600 tclayer_t im_tclayer[8]; /* Eight TCLayers */
601 u16 tc_tcgsr;
602 u16 tc_tcger;
603
604 /* First set of baud rate generators.
605 */
606 u8 res[236];
607 u32 im_brgc5;
608 u32 im_brgc6;
609 u32 im_brgc7;
610 u32 im_brgc8;
611
612 u8 res5[608];
613
614 i2c_cpm2_t im_i2c; /* I2C control/status */
615 cpm_cpm2_t im_cpm; /* Communication processor */
616
617 /* Second set of baud rate generators.
618 */
619 u32 im_brgc1;
620 u32 im_brgc2;
621 u32 im_brgc3;
622 u32 im_brgc4;
623
624 scc_t im_scc[4]; /* Four SCCs */
625 smc_t im_smc[2]; /* Couple of SMCs */
626 spictl_cpm2_t im_spi; /* A SPI */
627 cpmux_t im_cpmux; /* CPM clock route mux */
628 siramctl_t im_siramctl1; /* First SI RAM Control */
629 mcc_t im_mcc1; /* First MCC */
630 siramctl_t im_siramctl2; /* Second SI RAM Control */
631 mcc_t im_mcc2; /* Second MCC */
632 usb_cpm2_t im_usb; /* USB Controller */
633
634 u8 res6[1153];
635
636 u16 im_si1txram[256];
637 u8 res7[512];
638 u16 im_si1rxram[256];
639 u8 res8[512];
640 u16 im_si2txram[256];
641 u8 res9[512];
642 u16 im_si2rxram[256];
643 u8 res10[512];
644 u8 res11[4096];
645} cpm2_map_t;
646
647extern cpm2_map_t __iomem *cpm2_immr;
648
649#endif /* __IMMAP_CPM2__ */
650#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/immap_qe.h b/include/asm-powerpc/immap_qe.h
deleted file mode 100644
index 7b6f411db3e..00000000000
--- a/include/asm-powerpc/immap_qe.h
+++ /dev/null
@@ -1,485 +0,0 @@
1/*
2 * include/asm-powerpc/immap_qe.h
3 *
4 * QUICC Engine (QE) Internal Memory Map.
5 * The Internal Memory Map for devices with QE on them. This
6 * is the superset of all QE devices (8360, etc.).
7
8 * Copyright (C) 2006. Freescale Semicondutor, Inc. All rights reserved.
9 *
10 * Authors: Shlomi Gridish <gridish@freescale.com>
11 * Li Yang <leoli@freescale.com>
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18#ifndef _ASM_POWERPC_IMMAP_QE_H
19#define _ASM_POWERPC_IMMAP_QE_H
20#ifdef __KERNEL__
21
22#include <linux/kernel.h>
23#include <asm/io.h>
24
25#define QE_IMMAP_SIZE (1024 * 1024) /* 1MB from 1MB+IMMR */
26
27/* QE I-RAM */
28struct qe_iram {
29 __be32 iadd; /* I-RAM Address Register */
30 __be32 idata; /* I-RAM Data Register */
31 u8 res0[0x78];
32} __attribute__ ((packed));
33
34/* QE Interrupt Controller */
35struct qe_ic_regs {
36 __be32 qicr;
37 __be32 qivec;
38 __be32 qripnr;
39 __be32 qipnr;
40 __be32 qipxcc;
41 __be32 qipycc;
42 __be32 qipwcc;
43 __be32 qipzcc;
44 __be32 qimr;
45 __be32 qrimr;
46 __be32 qicnr;
47 u8 res0[0x4];
48 __be32 qiprta;
49 __be32 qiprtb;
50 u8 res1[0x4];
51 __be32 qricr;
52 u8 res2[0x20];
53 __be32 qhivec;
54 u8 res3[0x1C];
55} __attribute__ ((packed));
56
57/* Communications Processor */
58struct cp_qe {
59 __be32 cecr; /* QE command register */
60 __be32 ceccr; /* QE controller configuration register */
61 __be32 cecdr; /* QE command data register */
62 u8 res0[0xA];
63 __be16 ceter; /* QE timer event register */
64 u8 res1[0x2];
65 __be16 cetmr; /* QE timers mask register */
66 __be32 cetscr; /* QE time-stamp timer control register */
67 __be32 cetsr1; /* QE time-stamp register 1 */
68 __be32 cetsr2; /* QE time-stamp register 2 */
69 u8 res2[0x8];
70 __be32 cevter; /* QE virtual tasks event register */
71 __be32 cevtmr; /* QE virtual tasks mask register */
72 __be16 cercr; /* QE RAM control register */
73 u8 res3[0x2];
74 u8 res4[0x24];
75 __be16 ceexe1; /* QE external request 1 event register */
76 u8 res5[0x2];
77 __be16 ceexm1; /* QE external request 1 mask register */
78 u8 res6[0x2];
79 __be16 ceexe2; /* QE external request 2 event register */
80 u8 res7[0x2];
81 __be16 ceexm2; /* QE external request 2 mask register */
82 u8 res8[0x2];
83 __be16 ceexe3; /* QE external request 3 event register */
84 u8 res9[0x2];
85 __be16 ceexm3; /* QE external request 3 mask register */
86 u8 res10[0x2];
87 __be16 ceexe4; /* QE external request 4 event register */
88 u8 res11[0x2];
89 __be16 ceexm4; /* QE external request 4 mask register */
90 u8 res12[0x3A];
91 __be32 ceurnr; /* QE microcode revision number register */
92 u8 res13[0x244];
93} __attribute__ ((packed));
94
95/* QE Multiplexer */
96struct qe_mux {
97 __be32 cmxgcr; /* CMX general clock route register */
98 __be32 cmxsi1cr_l; /* CMX SI1 clock route low register */
99 __be32 cmxsi1cr_h; /* CMX SI1 clock route high register */
100 __be32 cmxsi1syr; /* CMX SI1 SYNC route register */
101 __be32 cmxucr[4]; /* CMX UCCx clock route registers */
102 __be32 cmxupcr; /* CMX UPC clock route register */
103 u8 res0[0x1C];
104} __attribute__ ((packed));
105
106/* QE Timers */
107struct qe_timers {
108 u8 gtcfr1; /* Timer 1 and Timer 2 global config register*/
109 u8 res0[0x3];
110 u8 gtcfr2; /* Timer 3 and timer 4 global config register*/
111 u8 res1[0xB];
112 __be16 gtmdr1; /* Timer 1 mode register */
113 __be16 gtmdr2; /* Timer 2 mode register */
114 __be16 gtrfr1; /* Timer 1 reference register */
115 __be16 gtrfr2; /* Timer 2 reference register */
116 __be16 gtcpr1; /* Timer 1 capture register */
117 __be16 gtcpr2; /* Timer 2 capture register */
118 __be16 gtcnr1; /* Timer 1 counter */
119 __be16 gtcnr2; /* Timer 2 counter */
120 __be16 gtmdr3; /* Timer 3 mode register */
121 __be16 gtmdr4; /* Timer 4 mode register */
122 __be16 gtrfr3; /* Timer 3 reference register */
123 __be16 gtrfr4; /* Timer 4 reference register */
124 __be16 gtcpr3; /* Timer 3 capture register */
125 __be16 gtcpr4; /* Timer 4 capture register */
126 __be16 gtcnr3; /* Timer 3 counter */
127 __be16 gtcnr4; /* Timer 4 counter */
128 __be16 gtevr1; /* Timer 1 event register */
129 __be16 gtevr2; /* Timer 2 event register */
130 __be16 gtevr3; /* Timer 3 event register */
131 __be16 gtevr4; /* Timer 4 event register */
132 __be16 gtps; /* Timer 1 prescale register */
133 u8 res2[0x46];
134} __attribute__ ((packed));
135
136/* BRG */
137struct qe_brg {
138 __be32 brgc[16]; /* BRG configuration registers */
139 u8 res0[0x40];
140} __attribute__ ((packed));
141
142/* SPI */
143struct spi {
144 u8 res0[0x20];
145 __be32 spmode; /* SPI mode register */
146 u8 res1[0x2];
147 u8 spie; /* SPI event register */
148 u8 res2[0x1];
149 u8 res3[0x2];
150 u8 spim; /* SPI mask register */
151 u8 res4[0x1];
152 u8 res5[0x1];
153 u8 spcom; /* SPI command register */
154 u8 res6[0x2];
155 __be32 spitd; /* SPI transmit data register (cpu mode) */
156 __be32 spird; /* SPI receive data register (cpu mode) */
157 u8 res7[0x8];
158} __attribute__ ((packed));
159
160/* SI */
161struct si1 {
162 __be16 siamr1; /* SI1 TDMA mode register */
163 __be16 sibmr1; /* SI1 TDMB mode register */
164 __be16 sicmr1; /* SI1 TDMC mode register */
165 __be16 sidmr1; /* SI1 TDMD mode register */
166 u8 siglmr1_h; /* SI1 global mode register high */
167 u8 res0[0x1];
168 u8 sicmdr1_h; /* SI1 command register high */
169 u8 res2[0x1];
170 u8 sistr1_h; /* SI1 status register high */
171 u8 res3[0x1];
172 __be16 sirsr1_h; /* SI1 RAM shadow address register high */
173 u8 sitarc1; /* SI1 RAM counter Tx TDMA */
174 u8 sitbrc1; /* SI1 RAM counter Tx TDMB */
175 u8 sitcrc1; /* SI1 RAM counter Tx TDMC */
176 u8 sitdrc1; /* SI1 RAM counter Tx TDMD */
177 u8 sirarc1; /* SI1 RAM counter Rx TDMA */
178 u8 sirbrc1; /* SI1 RAM counter Rx TDMB */
179 u8 sircrc1; /* SI1 RAM counter Rx TDMC */
180 u8 sirdrc1; /* SI1 RAM counter Rx TDMD */
181 u8 res4[0x8];
182 __be16 siemr1; /* SI1 TDME mode register 16 bits */
183 __be16 sifmr1; /* SI1 TDMF mode register 16 bits */
184 __be16 sigmr1; /* SI1 TDMG mode register 16 bits */
185 __be16 sihmr1; /* SI1 TDMH mode register 16 bits */
186 u8 siglmg1_l; /* SI1 global mode register low 8 bits */
187 u8 res5[0x1];
188 u8 sicmdr1_l; /* SI1 command register low 8 bits */
189 u8 res6[0x1];
190 u8 sistr1_l; /* SI1 status register low 8 bits */
191 u8 res7[0x1];
192 __be16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits*/
193 u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */
194 u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */
195 u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */
196 u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */
197 u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */
198 u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */
199 u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */
200 u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */
201 u8 res8[0x8];
202 __be32 siml1; /* SI1 multiframe limit register */
203 u8 siedm1; /* SI1 extended diagnostic mode register */
204 u8 res9[0xBB];
205} __attribute__ ((packed));
206
207/* SI Routing Tables */
208struct sir {
209 u8 tx[0x400];
210 u8 rx[0x400];
211 u8 res0[0x800];
212} __attribute__ ((packed));
213
214/* USB Controller */
215struct usb_ctlr {
216 u8 usb_usmod;
217 u8 usb_usadr;
218 u8 usb_uscom;
219 u8 res1[1];
220 __be16 usb_usep1;
221 __be16 usb_usep2;
222 __be16 usb_usep3;
223 __be16 usb_usep4;
224 u8 res2[4];
225 __be16 usb_usber;
226 u8 res3[2];
227 __be16 usb_usbmr;
228 u8 res4[1];
229 u8 usb_usbs;
230 __be16 usb_ussft;
231 u8 res5[2];
232 __be16 usb_usfrn;
233 u8 res6[0x22];
234} __attribute__ ((packed));
235
236/* MCC */
237struct mcc {
238 __be32 mcce; /* MCC event register */
239 __be32 mccm; /* MCC mask register */
240 __be32 mccf; /* MCC configuration register */
241 __be32 merl; /* MCC emergency request level register */
242 u8 res0[0xF0];
243} __attribute__ ((packed));
244
245/* QE UCC Slow */
246struct ucc_slow {
247 __be32 gumr_l; /* UCCx general mode register (low) */
248 __be32 gumr_h; /* UCCx general mode register (high) */
249 __be16 upsmr; /* UCCx protocol-specific mode register */
250 u8 res0[0x2];
251 __be16 utodr; /* UCCx transmit on demand register */
252 __be16 udsr; /* UCCx data synchronization register */
253 __be16 ucce; /* UCCx event register */
254 u8 res1[0x2];
255 __be16 uccm; /* UCCx mask register */
256 u8 res2[0x1];
257 u8 uccs; /* UCCx status register */
258 u8 res3[0x24];
259 __be16 utpt;
260 u8 res4[0x52];
261 u8 guemr; /* UCC general extended mode register */
262} __attribute__ ((packed));
263
264/* QE UCC Fast */
265struct ucc_fast {
266 __be32 gumr; /* UCCx general mode register */
267 __be32 upsmr; /* UCCx protocol-specific mode register */
268 __be16 utodr; /* UCCx transmit on demand register */
269 u8 res0[0x2];
270 __be16 udsr; /* UCCx data synchronization register */
271 u8 res1[0x2];
272 __be32 ucce; /* UCCx event register */
273 __be32 uccm; /* UCCx mask register */
274 u8 uccs; /* UCCx status register */
275 u8 res2[0x7];
276 __be32 urfb; /* UCC receive FIFO base */
277 __be16 urfs; /* UCC receive FIFO size */
278 u8 res3[0x2];
279 __be16 urfet; /* UCC receive FIFO emergency threshold */
280 __be16 urfset; /* UCC receive FIFO special emergency
281 threshold */
282 __be32 utfb; /* UCC transmit FIFO base */
283 __be16 utfs; /* UCC transmit FIFO size */
284 u8 res4[0x2];
285 __be16 utfet; /* UCC transmit FIFO emergency threshold */
286 u8 res5[0x2];
287 __be16 utftt; /* UCC transmit FIFO transmit threshold */
288 u8 res6[0x2];
289 __be16 utpt; /* UCC transmit polling timer */
290 u8 res7[0x2];
291 __be32 urtry; /* UCC retry counter register */
292 u8 res8[0x4C];
293 u8 guemr; /* UCC general extended mode register */
294} __attribute__ ((packed));
295
296struct ucc {
297 union {
298 struct ucc_slow slow;
299 struct ucc_fast fast;
300 u8 res[0x200]; /* UCC blocks are 512 bytes each */
301 };
302} __attribute__ ((packed));
303
304/* MultiPHY UTOPIA POS Controllers (UPC) */
305struct upc {
306 __be32 upgcr; /* UTOPIA/POS general configuration register */
307 __be32 uplpa; /* UTOPIA/POS last PHY address */
308 __be32 uphec; /* ATM HEC register */
309 __be32 upuc; /* UTOPIA/POS UCC configuration */
310 __be32 updc1; /* UTOPIA/POS device 1 configuration */
311 __be32 updc2; /* UTOPIA/POS device 2 configuration */
312 __be32 updc3; /* UTOPIA/POS device 3 configuration */
313 __be32 updc4; /* UTOPIA/POS device 4 configuration */
314 __be32 upstpa; /* UTOPIA/POS STPA threshold */
315 u8 res0[0xC];
316 __be32 updrs1_h; /* UTOPIA/POS device 1 rate select */
317 __be32 updrs1_l; /* UTOPIA/POS device 1 rate select */
318 __be32 updrs2_h; /* UTOPIA/POS device 2 rate select */
319 __be32 updrs2_l; /* UTOPIA/POS device 2 rate select */
320 __be32 updrs3_h; /* UTOPIA/POS device 3 rate select */
321 __be32 updrs3_l; /* UTOPIA/POS device 3 rate select */
322 __be32 updrs4_h; /* UTOPIA/POS device 4 rate select */
323 __be32 updrs4_l; /* UTOPIA/POS device 4 rate select */
324 __be32 updrp1; /* UTOPIA/POS device 1 receive priority low */
325 __be32 updrp2; /* UTOPIA/POS device 2 receive priority low */
326 __be32 updrp3; /* UTOPIA/POS device 3 receive priority low */
327 __be32 updrp4; /* UTOPIA/POS device 4 receive priority low */
328 __be32 upde1; /* UTOPIA/POS device 1 event */
329 __be32 upde2; /* UTOPIA/POS device 2 event */
330 __be32 upde3; /* UTOPIA/POS device 3 event */
331 __be32 upde4; /* UTOPIA/POS device 4 event */
332 __be16 uprp1;
333 __be16 uprp2;
334 __be16 uprp3;
335 __be16 uprp4;
336 u8 res1[0x8];
337 __be16 uptirr1_0; /* Device 1 transmit internal rate 0 */
338 __be16 uptirr1_1; /* Device 1 transmit internal rate 1 */
339 __be16 uptirr1_2; /* Device 1 transmit internal rate 2 */
340 __be16 uptirr1_3; /* Device 1 transmit internal rate 3 */
341 __be16 uptirr2_0; /* Device 2 transmit internal rate 0 */
342 __be16 uptirr2_1; /* Device 2 transmit internal rate 1 */
343 __be16 uptirr2_2; /* Device 2 transmit internal rate 2 */
344 __be16 uptirr2_3; /* Device 2 transmit internal rate 3 */
345 __be16 uptirr3_0; /* Device 3 transmit internal rate 0 */
346 __be16 uptirr3_1; /* Device 3 transmit internal rate 1 */
347 __be16 uptirr3_2; /* Device 3 transmit internal rate 2 */
348 __be16 uptirr3_3; /* Device 3 transmit internal rate 3 */
349 __be16 uptirr4_0; /* Device 4 transmit internal rate 0 */
350 __be16 uptirr4_1; /* Device 4 transmit internal rate 1 */
351 __be16 uptirr4_2; /* Device 4 transmit internal rate 2 */
352 __be16 uptirr4_3; /* Device 4 transmit internal rate 3 */
353 __be32 uper1; /* Device 1 port enable register */
354 __be32 uper2; /* Device 2 port enable register */
355 __be32 uper3; /* Device 3 port enable register */
356 __be32 uper4; /* Device 4 port enable register */
357 u8 res2[0x150];
358} __attribute__ ((packed));
359
360/* SDMA */
361struct sdma {
362 __be32 sdsr; /* Serial DMA status register */
363 __be32 sdmr; /* Serial DMA mode register */
364 __be32 sdtr1; /* SDMA system bus threshold register */
365 __be32 sdtr2; /* SDMA secondary bus threshold register */
366 __be32 sdhy1; /* SDMA system bus hysteresis register */
367 __be32 sdhy2; /* SDMA secondary bus hysteresis register */
368 __be32 sdta1; /* SDMA system bus address register */
369 __be32 sdta2; /* SDMA secondary bus address register */
370 __be32 sdtm1; /* SDMA system bus MSNUM register */
371 __be32 sdtm2; /* SDMA secondary bus MSNUM register */
372 u8 res0[0x10];
373 __be32 sdaqr; /* SDMA address bus qualify register */
374 __be32 sdaqmr; /* SDMA address bus qualify mask register */
375 u8 res1[0x4];
376 __be32 sdebcr; /* SDMA CAM entries base register */
377 u8 res2[0x38];
378} __attribute__ ((packed));
379
380/* Debug Space */
381struct dbg {
382 __be32 bpdcr; /* Breakpoint debug command register */
383 __be32 bpdsr; /* Breakpoint debug status register */
384 __be32 bpdmr; /* Breakpoint debug mask register */
385 __be32 bprmrr0; /* Breakpoint request mode risc register 0 */
386 __be32 bprmrr1; /* Breakpoint request mode risc register 1 */
387 u8 res0[0x8];
388 __be32 bprmtr0; /* Breakpoint request mode trb register 0 */
389 __be32 bprmtr1; /* Breakpoint request mode trb register 1 */
390 u8 res1[0x8];
391 __be32 bprmir; /* Breakpoint request mode immediate register */
392 __be32 bprmsr; /* Breakpoint request mode serial register */
393 __be32 bpemr; /* Breakpoint exit mode register */
394 u8 res2[0x48];
395} __attribute__ ((packed));
396
397/*
398 * RISC Special Registers (Trap and Breakpoint). These are described in
399 * the QE Developer's Handbook.
400 */
401struct rsp {
402 __be32 tibcr[16]; /* Trap/instruction breakpoint control regs */
403 u8 res0[64];
404 __be32 ibcr0;
405 __be32 ibs0;
406 __be32 ibcnr0;
407 u8 res1[4];
408 __be32 ibcr1;
409 __be32 ibs1;
410 __be32 ibcnr1;
411 __be32 npcr;
412 __be32 dbcr;
413 __be32 dbar;
414 __be32 dbamr;
415 __be32 dbsr;
416 __be32 dbcnr;
417 u8 res2[12];
418 __be32 dbdr_h;
419 __be32 dbdr_l;
420 __be32 dbdmr_h;
421 __be32 dbdmr_l;
422 __be32 bsr;
423 __be32 bor;
424 __be32 bior;
425 u8 res3[4];
426 __be32 iatr[4];
427 __be32 eccr; /* Exception control configuration register */
428 __be32 eicr;
429 u8 res4[0x100-0xf8];
430} __attribute__ ((packed));
431
432struct qe_immap {
433 struct qe_iram iram; /* I-RAM */
434 struct qe_ic_regs ic; /* Interrupt Controller */
435 struct cp_qe cp; /* Communications Processor */
436 struct qe_mux qmx; /* QE Multiplexer */
437 struct qe_timers qet; /* QE Timers */
438 struct spi spi[0x2]; /* spi */
439 struct mcc mcc; /* mcc */
440 struct qe_brg brg; /* brg */
441 struct usb_ctlr usb; /* USB */
442 struct si1 si1; /* SI */
443 u8 res11[0x800];
444 struct sir sir; /* SI Routing Tables */
445 struct ucc ucc1; /* ucc1 */
446 struct ucc ucc3; /* ucc3 */
447 struct ucc ucc5; /* ucc5 */
448 struct ucc ucc7; /* ucc7 */
449 u8 res12[0x600];
450 struct upc upc1; /* MultiPHY UTOPIA POS Ctrlr 1*/
451 struct ucc ucc2; /* ucc2 */
452 struct ucc ucc4; /* ucc4 */
453 struct ucc ucc6; /* ucc6 */
454 struct ucc ucc8; /* ucc8 */
455 u8 res13[0x600];
456 struct upc upc2; /* MultiPHY UTOPIA POS Ctrlr 2*/
457 struct sdma sdma; /* SDMA */
458 struct dbg dbg; /* 0x104080 - 0x1040FF
459 Debug Space */
460 struct rsp rsp[0x2]; /* 0x104100 - 0x1042FF
461 RISC Special Registers
462 (Trap and Breakpoint) */
463 u8 res14[0x300]; /* 0x104300 - 0x1045FF */
464 u8 res15[0x3A00]; /* 0x104600 - 0x107FFF */
465 u8 res16[0x8000]; /* 0x108000 - 0x110000 */
466 u8 muram[0xC000]; /* 0x110000 - 0x11C000
467 Multi-user RAM */
468 u8 res17[0x24000]; /* 0x11C000 - 0x140000 */
469 u8 res18[0xC0000]; /* 0x140000 - 0x200000 */
470} __attribute__ ((packed));
471
472extern struct qe_immap __iomem *qe_immr;
473extern phys_addr_t get_qe_base(void);
474
475static inline unsigned long immrbar_virt_to_phys(void *address)
476{
477 if ( ((u32)address >= (u32)qe_immr) &&
478 ((u32)address < ((u32)qe_immr + QE_IMMAP_SIZE)) )
479 return (unsigned long)(address - (u32)qe_immr +
480 (u32)get_qe_base());
481 return (unsigned long)virt_to_phys(address);
482}
483
484#endif /* __KERNEL__ */
485#endif /* _ASM_POWERPC_IMMAP_QE_H */
diff --git a/include/asm-powerpc/io-defs.h b/include/asm-powerpc/io-defs.h
deleted file mode 100644
index 44d7927aec6..00000000000
--- a/include/asm-powerpc/io-defs.h
+++ /dev/null
@@ -1,60 +0,0 @@
1/* This file is meant to be include multiple times by other headers */
2/* last 2 argments are used by platforms/cell/io-workarounds.[ch] */
3
4DEF_PCI_AC_RET(readb, u8, (const PCI_IO_ADDR addr), (addr), mem, addr)
5DEF_PCI_AC_RET(readw, u16, (const PCI_IO_ADDR addr), (addr), mem, addr)
6DEF_PCI_AC_RET(readl, u32, (const PCI_IO_ADDR addr), (addr), mem, addr)
7DEF_PCI_AC_RET(readw_be, u16, (const PCI_IO_ADDR addr), (addr), mem, addr)
8DEF_PCI_AC_RET(readl_be, u32, (const PCI_IO_ADDR addr), (addr), mem, addr)
9DEF_PCI_AC_NORET(writeb, (u8 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
10DEF_PCI_AC_NORET(writew, (u16 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
11DEF_PCI_AC_NORET(writel, (u32 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
12DEF_PCI_AC_NORET(writew_be, (u16 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
13DEF_PCI_AC_NORET(writel_be, (u32 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
14
15#ifdef __powerpc64__
16DEF_PCI_AC_RET(readq, u64, (const PCI_IO_ADDR addr), (addr), mem, addr)
17DEF_PCI_AC_RET(readq_be, u64, (const PCI_IO_ADDR addr), (addr), mem, addr)
18DEF_PCI_AC_NORET(writeq, (u64 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
19DEF_PCI_AC_NORET(writeq_be, (u64 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
20#endif /* __powerpc64__ */
21
22DEF_PCI_AC_RET(inb, u8, (unsigned long port), (port), pio, port)
23DEF_PCI_AC_RET(inw, u16, (unsigned long port), (port), pio, port)
24DEF_PCI_AC_RET(inl, u32, (unsigned long port), (port), pio, port)
25DEF_PCI_AC_NORET(outb, (u8 val, unsigned long port), (val, port), pio, port)
26DEF_PCI_AC_NORET(outw, (u16 val, unsigned long port), (val, port), pio, port)
27DEF_PCI_AC_NORET(outl, (u32 val, unsigned long port), (val, port), pio, port)
28
29DEF_PCI_AC_NORET(readsb, (const PCI_IO_ADDR a, void *b, unsigned long c),
30 (a, b, c), mem, a)
31DEF_PCI_AC_NORET(readsw, (const PCI_IO_ADDR a, void *b, unsigned long c),
32 (a, b, c), mem, a)
33DEF_PCI_AC_NORET(readsl, (const PCI_IO_ADDR a, void *b, unsigned long c),
34 (a, b, c), mem, a)
35DEF_PCI_AC_NORET(writesb, (PCI_IO_ADDR a, const void *b, unsigned long c),
36 (a, b, c), mem, a)
37DEF_PCI_AC_NORET(writesw, (PCI_IO_ADDR a, const void *b, unsigned long c),
38 (a, b, c), mem, a)
39DEF_PCI_AC_NORET(writesl, (PCI_IO_ADDR a, const void *b, unsigned long c),
40 (a, b, c), mem, a)
41
42DEF_PCI_AC_NORET(insb, (unsigned long p, void *b, unsigned long c),
43 (p, b, c), pio, p)
44DEF_PCI_AC_NORET(insw, (unsigned long p, void *b, unsigned long c),
45 (p, b, c), pio, p)
46DEF_PCI_AC_NORET(insl, (unsigned long p, void *b, unsigned long c),
47 (p, b, c), pio, p)
48DEF_PCI_AC_NORET(outsb, (unsigned long p, const void *b, unsigned long c),
49 (p, b, c), pio, p)
50DEF_PCI_AC_NORET(outsw, (unsigned long p, const void *b, unsigned long c),
51 (p, b, c), pio, p)
52DEF_PCI_AC_NORET(outsl, (unsigned long p, const void *b, unsigned long c),
53 (p, b, c), pio, p)
54
55DEF_PCI_AC_NORET(memset_io, (PCI_IO_ADDR a, int c, unsigned long n),
56 (a, c, n), mem, a)
57DEF_PCI_AC_NORET(memcpy_fromio, (void *d, const PCI_IO_ADDR s, unsigned long n),
58 (d, s, n), mem, s)
59DEF_PCI_AC_NORET(memcpy_toio, (PCI_IO_ADDR d, const void *s, unsigned long n),
60 (d, s, n), mem, d)
diff --git a/include/asm-powerpc/io.h b/include/asm-powerpc/io.h
deleted file mode 100644
index 77c7fa025e6..00000000000
--- a/include/asm-powerpc/io.h
+++ /dev/null
@@ -1,787 +0,0 @@
1#ifndef _ASM_POWERPC_IO_H
2#define _ASM_POWERPC_IO_H
3#ifdef __KERNEL__
4
5/*
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12/* Check of existence of legacy devices */
13extern int check_legacy_ioport(unsigned long base_port);
14#define I8042_DATA_REG 0x60
15#define FDC_BASE 0x3f0
16/* only relevant for PReP */
17#define _PIDXR 0x279
18#define _PNPWRP 0xa79
19#define PNPBIOS_BASE 0xf000
20
21#include <linux/device.h>
22#include <linux/io.h>
23
24#include <linux/compiler.h>
25#include <asm/page.h>
26#include <asm/byteorder.h>
27#include <asm/synch.h>
28#include <asm/delay.h>
29#include <asm/mmu.h>
30
31#include <asm-generic/iomap.h>
32
33#ifdef CONFIG_PPC64
34#include <asm/paca.h>
35#endif
36
37#define SIO_CONFIG_RA 0x398
38#define SIO_CONFIG_RD 0x399
39
40#define SLOW_DOWN_IO
41
42/* 32 bits uses slightly different variables for the various IO
43 * bases. Most of this file only uses _IO_BASE though which we
44 * define properly based on the platform
45 */
46#ifndef CONFIG_PCI
47#define _IO_BASE 0
48#define _ISA_MEM_BASE 0
49#define PCI_DRAM_OFFSET 0
50#elif defined(CONFIG_PPC32)
51#define _IO_BASE isa_io_base
52#define _ISA_MEM_BASE isa_mem_base
53#define PCI_DRAM_OFFSET pci_dram_offset
54#else
55#define _IO_BASE pci_io_base
56#define _ISA_MEM_BASE isa_mem_base
57#define PCI_DRAM_OFFSET 0
58#endif
59
60extern unsigned long isa_io_base;
61extern unsigned long pci_io_base;
62extern unsigned long pci_dram_offset;
63
64extern resource_size_t isa_mem_base;
65
66#if defined(CONFIG_PPC32) && defined(CONFIG_PPC_INDIRECT_IO)
67#error CONFIG_PPC_INDIRECT_IO is not yet supported on 32 bits
68#endif
69
70/*
71 *
72 * Low level MMIO accessors
73 *
74 * This provides the non-bus specific accessors to MMIO. Those are PowerPC
75 * specific and thus shouldn't be used in generic code. The accessors
76 * provided here are:
77 *
78 * in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64
79 * out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64
80 * _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns
81 *
82 * Those operate directly on a kernel virtual address. Note that the prototype
83 * for the out_* accessors has the arguments in opposite order from the usual
84 * linux PCI accessors. Unlike those, they take the address first and the value
85 * next.
86 *
87 * Note: I might drop the _ns suffix on the stream operations soon as it is
88 * simply normal for stream operations to not swap in the first place.
89 *
90 */
91
92#ifdef CONFIG_PPC64
93#define IO_SET_SYNC_FLAG() do { local_paca->io_sync = 1; } while(0)
94#else
95#define IO_SET_SYNC_FLAG()
96#endif
97
98/* gcc 4.0 and older doesn't have 'Z' constraint */
99#if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ == 0)
100#define DEF_MMIO_IN_LE(name, size, insn) \
101static inline u##size name(const volatile u##size __iomem *addr) \
102{ \
103 u##size ret; \
104 __asm__ __volatile__("sync;"#insn" %0,0,%1;twi 0,%0,0;isync" \
105 : "=r" (ret) : "r" (addr), "m" (*addr) : "memory"); \
106 return ret; \
107}
108
109#define DEF_MMIO_OUT_LE(name, size, insn) \
110static inline void name(volatile u##size __iomem *addr, u##size val) \
111{ \
112 __asm__ __volatile__("sync;"#insn" %1,0,%2" \
113 : "=m" (*addr) : "r" (val), "r" (addr) : "memory"); \
114 IO_SET_SYNC_FLAG(); \
115}
116#else /* newer gcc */
117#define DEF_MMIO_IN_LE(name, size, insn) \
118static inline u##size name(const volatile u##size __iomem *addr) \
119{ \
120 u##size ret; \
121 __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \
122 : "=r" (ret) : "Z" (*addr) : "memory"); \
123 return ret; \
124}
125
126#define DEF_MMIO_OUT_LE(name, size, insn) \
127static inline void name(volatile u##size __iomem *addr, u##size val) \
128{ \
129 __asm__ __volatile__("sync;"#insn" %1,%y0" \
130 : "=Z" (*addr) : "r" (val) : "memory"); \
131 IO_SET_SYNC_FLAG(); \
132}
133#endif
134
135#define DEF_MMIO_IN_BE(name, size, insn) \
136static inline u##size name(const volatile u##size __iomem *addr) \
137{ \
138 u##size ret; \
139 __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\
140 : "=r" (ret) : "m" (*addr) : "memory"); \
141 return ret; \
142}
143
144#define DEF_MMIO_OUT_BE(name, size, insn) \
145static inline void name(volatile u##size __iomem *addr, u##size val) \
146{ \
147 __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0" \
148 : "=m" (*addr) : "r" (val) : "memory"); \
149 IO_SET_SYNC_FLAG(); \
150}
151
152
153DEF_MMIO_IN_BE(in_8, 8, lbz);
154DEF_MMIO_IN_BE(in_be16, 16, lhz);
155DEF_MMIO_IN_BE(in_be32, 32, lwz);
156DEF_MMIO_IN_LE(in_le16, 16, lhbrx);
157DEF_MMIO_IN_LE(in_le32, 32, lwbrx);
158
159DEF_MMIO_OUT_BE(out_8, 8, stb);
160DEF_MMIO_OUT_BE(out_be16, 16, sth);
161DEF_MMIO_OUT_BE(out_be32, 32, stw);
162DEF_MMIO_OUT_LE(out_le16, 16, sthbrx);
163DEF_MMIO_OUT_LE(out_le32, 32, stwbrx);
164
165#ifdef __powerpc64__
166DEF_MMIO_OUT_BE(out_be64, 64, std);
167DEF_MMIO_IN_BE(in_be64, 64, ld);
168
169/* There is no asm instructions for 64 bits reverse loads and stores */
170static inline u64 in_le64(const volatile u64 __iomem *addr)
171{
172 return swab64(in_be64(addr));
173}
174
175static inline void out_le64(volatile u64 __iomem *addr, u64 val)
176{
177 out_be64(addr, swab64(val));
178}
179#endif /* __powerpc64__ */
180
181/*
182 * Low level IO stream instructions are defined out of line for now
183 */
184extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
185extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
186extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
187extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
188extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
189extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
190
191/* The _ns naming is historical and will be removed. For now, just #define
192 * the non _ns equivalent names
193 */
194#define _insw _insw_ns
195#define _insl _insl_ns
196#define _outsw _outsw_ns
197#define _outsl _outsl_ns
198
199
200/*
201 * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line
202 */
203
204extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n);
205extern void _memcpy_fromio(void *dest, const volatile void __iomem *src,
206 unsigned long n);
207extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
208 unsigned long n);
209
210/*
211 *
212 * PCI and standard ISA accessors
213 *
214 * Those are globally defined linux accessors for devices on PCI or ISA
215 * busses. They follow the Linux defined semantics. The current implementation
216 * for PowerPC is as close as possible to the x86 version of these, and thus
217 * provides fairly heavy weight barriers for the non-raw versions
218 *
219 * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_IO
220 * allowing the platform to provide its own implementation of some or all
221 * of the accessors.
222 */
223
224/*
225 * Include the EEH definitions when EEH is enabled only so they don't get
226 * in the way when building for 32 bits
227 */
228#ifdef CONFIG_EEH
229#include <asm/eeh.h>
230#endif
231
232/* Shortcut to the MMIO argument pointer */
233#define PCI_IO_ADDR volatile void __iomem *
234
235/* Indirect IO address tokens:
236 *
237 * When CONFIG_PPC_INDIRECT_IO is set, the platform can provide hooks
238 * on all IOs. (Note that this is all 64 bits only for now)
239 *
240 * To help platforms who may need to differenciate MMIO addresses in
241 * their hooks, a bitfield is reserved for use by the platform near the
242 * top of MMIO addresses (not PIO, those have to cope the hard way).
243 *
244 * This bit field is 12 bits and is at the top of the IO virtual
245 * addresses PCI_IO_INDIRECT_TOKEN_MASK.
246 *
247 * The kernel virtual space is thus:
248 *
249 * 0xD000000000000000 : vmalloc
250 * 0xD000080000000000 : PCI PHB IO space
251 * 0xD000080080000000 : ioremap
252 * 0xD0000fffffffffff : end of ioremap region
253 *
254 * Since the top 4 bits are reserved as the region ID, we use thus
255 * the next 12 bits and keep 4 bits available for the future if the
256 * virtual address space is ever to be extended.
257 *
258 * The direct IO mapping operations will then mask off those bits
259 * before doing the actual access, though that only happen when
260 * CONFIG_PPC_INDIRECT_IO is set, thus be careful when you use that
261 * mechanism
262 */
263
264#ifdef CONFIG_PPC_INDIRECT_IO
265#define PCI_IO_IND_TOKEN_MASK 0x0fff000000000000ul
266#define PCI_IO_IND_TOKEN_SHIFT 48
267#define PCI_FIX_ADDR(addr) \
268 ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
269#define PCI_GET_ADDR_TOKEN(addr) \
270 (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \
271 PCI_IO_IND_TOKEN_SHIFT)
272#define PCI_SET_ADDR_TOKEN(addr, token) \
273do { \
274 unsigned long __a = (unsigned long)(addr); \
275 __a &= ~PCI_IO_IND_TOKEN_MASK; \
276 __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT; \
277 (addr) = (void __iomem *)__a; \
278} while(0)
279#else
280#define PCI_FIX_ADDR(addr) (addr)
281#endif
282
283
284/*
285 * Non ordered and non-swapping "raw" accessors
286 */
287
288static inline unsigned char __raw_readb(const volatile void __iomem *addr)
289{
290 return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr);
291}
292static inline unsigned short __raw_readw(const volatile void __iomem *addr)
293{
294 return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr);
295}
296static inline unsigned int __raw_readl(const volatile void __iomem *addr)
297{
298 return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr);
299}
300static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
301{
302 *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v;
303}
304static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
305{
306 *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v;
307}
308static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
309{
310 *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v;
311}
312
313#ifdef __powerpc64__
314static inline unsigned long __raw_readq(const volatile void __iomem *addr)
315{
316 return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr);
317}
318static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
319{
320 *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v;
321}
322#endif /* __powerpc64__ */
323
324/*
325 *
326 * PCI PIO and MMIO accessors.
327 *
328 *
329 * On 32 bits, PIO operations have a recovery mechanism in case they trigger
330 * machine checks (which they occasionally do when probing non existing
331 * IO ports on some platforms, like PowerMac and 8xx).
332 * I always found it to be of dubious reliability and I am tempted to get
333 * rid of it one of these days. So if you think it's important to keep it,
334 * please voice up asap. We never had it for 64 bits and I do not intend
335 * to port it over
336 */
337
338#ifdef CONFIG_PPC32
339
340#define __do_in_asm(name, op) \
341static inline unsigned int name(unsigned int port) \
342{ \
343 unsigned int x; \
344 __asm__ __volatile__( \
345 "sync\n" \
346 "0:" op " %0,0,%1\n" \
347 "1: twi 0,%0,0\n" \
348 "2: isync\n" \
349 "3: nop\n" \
350 "4:\n" \
351 ".section .fixup,\"ax\"\n" \
352 "5: li %0,-1\n" \
353 " b 4b\n" \
354 ".previous\n" \
355 ".section __ex_table,\"a\"\n" \
356 " .align 2\n" \
357 " .long 0b,5b\n" \
358 " .long 1b,5b\n" \
359 " .long 2b,5b\n" \
360 " .long 3b,5b\n" \
361 ".previous" \
362 : "=&r" (x) \
363 : "r" (port + _IO_BASE) \
364 : "memory"); \
365 return x; \
366}
367
368#define __do_out_asm(name, op) \
369static inline void name(unsigned int val, unsigned int port) \
370{ \
371 __asm__ __volatile__( \
372 "sync\n" \
373 "0:" op " %0,0,%1\n" \
374 "1: sync\n" \
375 "2:\n" \
376 ".section __ex_table,\"a\"\n" \
377 " .align 2\n" \
378 " .long 0b,2b\n" \
379 " .long 1b,2b\n" \
380 ".previous" \
381 : : "r" (val), "r" (port + _IO_BASE) \
382 : "memory"); \
383}
384
385__do_in_asm(_rec_inb, "lbzx")
386__do_in_asm(_rec_inw, "lhbrx")
387__do_in_asm(_rec_inl, "lwbrx")
388__do_out_asm(_rec_outb, "stbx")
389__do_out_asm(_rec_outw, "sthbrx")
390__do_out_asm(_rec_outl, "stwbrx")
391
392#endif /* CONFIG_PPC32 */
393
394/* The "__do_*" operations below provide the actual "base" implementation
395 * for each of the defined acccessor. Some of them use the out_* functions
396 * directly, some of them still use EEH, though we might change that in the
397 * future. Those macros below provide the necessary argument swapping and
398 * handling of the IO base for PIO.
399 *
400 * They are themselves used by the macros that define the actual accessors
401 * and can be used by the hooks if any.
402 *
403 * Note that PIO operations are always defined in terms of their corresonding
404 * MMIO operations. That allows platforms like iSeries who want to modify the
405 * behaviour of both to only hook on the MMIO version and get both. It's also
406 * possible to hook directly at the toplevel PIO operation if they have to
407 * be handled differently
408 */
409#define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val)
410#define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val)
411#define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val)
412#define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val)
413#define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
414#define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
415#define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
416
417#ifdef CONFIG_EEH
418#define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr))
419#define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr))
420#define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr))
421#define __do_readq(addr) eeh_readq(PCI_FIX_ADDR(addr))
422#define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr))
423#define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr))
424#define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr))
425#else /* CONFIG_EEH */
426#define __do_readb(addr) in_8(PCI_FIX_ADDR(addr))
427#define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr))
428#define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr))
429#define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr))
430#define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr))
431#define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr))
432#define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr))
433#endif /* !defined(CONFIG_EEH) */
434
435#ifdef CONFIG_PPC32
436#define __do_outb(val, port) _rec_outb(val, port)
437#define __do_outw(val, port) _rec_outw(val, port)
438#define __do_outl(val, port) _rec_outl(val, port)
439#define __do_inb(port) _rec_inb(port)
440#define __do_inw(port) _rec_inw(port)
441#define __do_inl(port) _rec_inl(port)
442#else /* CONFIG_PPC32 */
443#define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
444#define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port);
445#define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port);
446#define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port);
447#define __do_inw(port) readw((PCI_IO_ADDR)_IO_BASE + port);
448#define __do_inl(port) readl((PCI_IO_ADDR)_IO_BASE + port);
449#endif /* !CONFIG_PPC32 */
450
451#ifdef CONFIG_EEH
452#define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
453#define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
454#define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
455#else /* CONFIG_EEH */
456#define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n))
457#define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n))
458#define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n))
459#endif /* !CONFIG_EEH */
460#define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n))
461#define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n))
462#define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n))
463
464#define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
465#define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
466#define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
467#define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
468#define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
469#define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
470
471#define __do_memset_io(addr, c, n) \
472 _memset_io(PCI_FIX_ADDR(addr), c, n)
473#define __do_memcpy_toio(dst, src, n) \
474 _memcpy_toio(PCI_FIX_ADDR(dst), src, n)
475
476#ifdef CONFIG_EEH
477#define __do_memcpy_fromio(dst, src, n) \
478 eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n)
479#else /* CONFIG_EEH */
480#define __do_memcpy_fromio(dst, src, n) \
481 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
482#endif /* !CONFIG_EEH */
483
484#ifdef CONFIG_PPC_INDIRECT_IO
485#define DEF_PCI_HOOK(x) x
486#else
487#define DEF_PCI_HOOK(x) NULL
488#endif
489
490/* Structure containing all the hooks */
491extern struct ppc_pci_io {
492
493#define DEF_PCI_AC_RET(name, ret, at, al, space, aa) ret (*name) at;
494#define DEF_PCI_AC_NORET(name, at, al, space, aa) void (*name) at;
495
496#include <asm/io-defs.h>
497
498#undef DEF_PCI_AC_RET
499#undef DEF_PCI_AC_NORET
500
501} ppc_pci_io;
502
503/* The inline wrappers */
504#define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \
505static inline ret name at \
506{ \
507 if (DEF_PCI_HOOK(ppc_pci_io.name) != NULL) \
508 return ppc_pci_io.name al; \
509 return __do_##name al; \
510}
511
512#define DEF_PCI_AC_NORET(name, at, al, space, aa) \
513static inline void name at \
514{ \
515 if (DEF_PCI_HOOK(ppc_pci_io.name) != NULL) \
516 ppc_pci_io.name al; \
517 else \
518 __do_##name al; \
519}
520
521#include <asm/io-defs.h>
522
523#undef DEF_PCI_AC_RET
524#undef DEF_PCI_AC_NORET
525
526/* Some drivers check for the presence of readq & writeq with
527 * a #ifdef, so we make them happy here.
528 */
529#ifdef __powerpc64__
530#define readq readq
531#define writeq writeq
532#endif
533
534/*
535 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
536 * access
537 */
538#define xlate_dev_mem_ptr(p) __va(p)
539
540/*
541 * Convert a virtual cached pointer to an uncached pointer
542 */
543#define xlate_dev_kmem_ptr(p) p
544
545/*
546 * We don't do relaxed operations yet, at least not with this semantic
547 */
548#define readb_relaxed(addr) readb(addr)
549#define readw_relaxed(addr) readw(addr)
550#define readl_relaxed(addr) readl(addr)
551#define readq_relaxed(addr) readq(addr)
552
553#ifdef CONFIG_PPC32
554#define mmiowb()
555#else
556/*
557 * Enforce synchronisation of stores vs. spin_unlock
558 * (this does it explicitly, though our implementation of spin_unlock
559 * does it implicitely too)
560 */
561static inline void mmiowb(void)
562{
563 unsigned long tmp;
564
565 __asm__ __volatile__("sync; li %0,0; stb %0,%1(13)"
566 : "=&r" (tmp) : "i" (offsetof(struct paca_struct, io_sync))
567 : "memory");
568}
569#endif /* !CONFIG_PPC32 */
570
571static inline void iosync(void)
572{
573 __asm__ __volatile__ ("sync" : : : "memory");
574}
575
576/* Enforce in-order execution of data I/O.
577 * No distinction between read/write on PPC; use eieio for all three.
578 * Those are fairly week though. They don't provide a barrier between
579 * MMIO and cacheable storage nor do they provide a barrier vs. locks,
580 * they only provide barriers between 2 __raw MMIO operations and
581 * possibly break write combining.
582 */
583#define iobarrier_rw() eieio()
584#define iobarrier_r() eieio()
585#define iobarrier_w() eieio()
586
587
588/*
589 * output pause versions need a delay at least for the
590 * w83c105 ide controller in a p610.
591 */
592#define inb_p(port) inb(port)
593#define outb_p(val, port) (udelay(1), outb((val), (port)))
594#define inw_p(port) inw(port)
595#define outw_p(val, port) (udelay(1), outw((val), (port)))
596#define inl_p(port) inl(port)
597#define outl_p(val, port) (udelay(1), outl((val), (port)))
598
599
600#define IO_SPACE_LIMIT ~(0UL)
601
602
603/**
604 * ioremap - map bus memory into CPU space
605 * @address: bus address of the memory
606 * @size: size of the resource to map
607 *
608 * ioremap performs a platform specific sequence of operations to
609 * make bus memory CPU accessible via the readb/readw/readl/writeb/
610 * writew/writel functions and the other mmio helpers. The returned
611 * address is not guaranteed to be usable directly as a virtual
612 * address.
613 *
614 * We provide a few variations of it:
615 *
616 * * ioremap is the standard one and provides non-cacheable guarded mappings
617 * and can be hooked by the platform via ppc_md
618 *
619 * * ioremap_flags allows to specify the page flags as an argument and can
620 * also be hooked by the platform via ppc_md. ioremap_prot is the exact
621 * same thing as ioremap_flags.
622 *
623 * * ioremap_nocache is identical to ioremap
624 *
625 * * iounmap undoes such a mapping and can be hooked
626 *
627 * * __ioremap_at (and the pending __iounmap_at) are low level functions to
628 * create hand-made mappings for use only by the PCI code and cannot
629 * currently be hooked. Must be page aligned.
630 *
631 * * __ioremap is the low level implementation used by ioremap and
632 * ioremap_flags and cannot be hooked (but can be used by a hook on one
633 * of the previous ones)
634 *
635 * * __iounmap, is the low level implementation used by iounmap and cannot
636 * be hooked (but can be used by a hook on iounmap)
637 *
638 */
639extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
640extern void __iomem *ioremap_flags(phys_addr_t address, unsigned long size,
641 unsigned long flags);
642#define ioremap_nocache(addr, size) ioremap((addr), (size))
643#define ioremap_prot(addr, size, prot) ioremap_flags((addr), (size), (prot))
644
645extern void iounmap(volatile void __iomem *addr);
646
647extern void __iomem *__ioremap(phys_addr_t, unsigned long size,
648 unsigned long flags);
649extern void __iounmap(volatile void __iomem *addr);
650
651extern void __iomem * __ioremap_at(phys_addr_t pa, void *ea,
652 unsigned long size, unsigned long flags);
653extern void __iounmap_at(void *ea, unsigned long size);
654
655/*
656 * When CONFIG_PPC_INDIRECT_IO is set, we use the generic iomap implementation
657 * which needs some additional definitions here. They basically allow PIO
658 * space overall to be 1GB. This will work as long as we never try to use
659 * iomap to map MMIO below 1GB which should be fine on ppc64
660 */
661#define HAVE_ARCH_PIO_SIZE 1
662#define PIO_OFFSET 0x00000000UL
663#define PIO_MASK (FULL_IO_SIZE - 1)
664#define PIO_RESERVED (FULL_IO_SIZE)
665
666#define mmio_read16be(addr) readw_be(addr)
667#define mmio_read32be(addr) readl_be(addr)
668#define mmio_write16be(val, addr) writew_be(val, addr)
669#define mmio_write32be(val, addr) writel_be(val, addr)
670#define mmio_insb(addr, dst, count) readsb(addr, dst, count)
671#define mmio_insw(addr, dst, count) readsw(addr, dst, count)
672#define mmio_insl(addr, dst, count) readsl(addr, dst, count)
673#define mmio_outsb(addr, src, count) writesb(addr, src, count)
674#define mmio_outsw(addr, src, count) writesw(addr, src, count)
675#define mmio_outsl(addr, src, count) writesl(addr, src, count)
676
677/**
678 * virt_to_phys - map virtual addresses to physical
679 * @address: address to remap
680 *
681 * The returned physical address is the physical (CPU) mapping for
682 * the memory address given. It is only valid to use this function on
683 * addresses directly mapped or allocated via kmalloc.
684 *
685 * This function does not give bus mappings for DMA transfers. In
686 * almost all conceivable cases a device driver should not be using
687 * this function
688 */
689static inline unsigned long virt_to_phys(volatile void * address)
690{
691 return __pa((unsigned long)address);
692}
693
694/**
695 * phys_to_virt - map physical address to virtual
696 * @address: address to remap
697 *
698 * The returned virtual address is a current CPU mapping for
699 * the memory address given. It is only valid to use this function on
700 * addresses that have a kernel mapping
701 *
702 * This function does not handle bus mappings for DMA transfers. In
703 * almost all conceivable cases a device driver should not be using
704 * this function
705 */
706static inline void * phys_to_virt(unsigned long address)
707{
708 return (void *)__va(address);
709}
710
711/*
712 * Change "struct page" to physical address.
713 */
714#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
715
716/* We do NOT want virtual merging, it would put too much pressure on
717 * our iommu allocator. Instead, we want drivers to be smart enough
718 * to coalesce sglists that happen to have been mapped in a contiguous
719 * way by the iommu
720 */
721#define BIO_VMERGE_BOUNDARY 0
722
723/*
724 * 32 bits still uses virt_to_bus() for it's implementation of DMA
725 * mappings se we have to keep it defined here. We also have some old
726 * drivers (shame shame shame) that use bus_to_virt() and haven't been
727 * fixed yet so I need to define it here.
728 */
729#ifdef CONFIG_PPC32
730
731static inline unsigned long virt_to_bus(volatile void * address)
732{
733 if (address == NULL)
734 return 0;
735 return __pa(address) + PCI_DRAM_OFFSET;
736}
737
738static inline void * bus_to_virt(unsigned long address)
739{
740 if (address == 0)
741 return NULL;
742 return __va(address - PCI_DRAM_OFFSET);
743}
744
745#define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET)
746
747#endif /* CONFIG_PPC32 */
748
749/* access ports */
750#define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
751#define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
752
753#define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v))
754#define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
755
756#define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v))
757#define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v))
758
759/* Clear and set bits in one shot. These macros can be used to clear and
760 * set multiple bits in a register using a single read-modify-write. These
761 * macros can also be used to set a multiple-bit bit pattern using a mask,
762 * by specifying the mask in the 'clear' parameter and the new bit pattern
763 * in the 'set' parameter.
764 */
765
766#define clrsetbits(type, addr, clear, set) \
767 out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
768
769#ifdef __powerpc64__
770#define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set)
771#define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set)
772#endif
773
774#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
775#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
776
777#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
778#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
779
780#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
781
782void __iomem *devm_ioremap_prot(struct device *dev, resource_size_t offset,
783 size_t size, unsigned long flags);
784
785#endif /* __KERNEL__ */
786
787#endif /* _ASM_POWERPC_IO_H */
diff --git a/include/asm-powerpc/ioctl.h b/include/asm-powerpc/ioctl.h
deleted file mode 100644
index 57d68304218..00000000000
--- a/include/asm-powerpc/ioctl.h
+++ /dev/null
@@ -1,13 +0,0 @@
1#ifndef _ASM_POWERPC_IOCTL_H
2#define _ASM_POWERPC_IOCTL_H
3
4#define _IOC_SIZEBITS 13
5#define _IOC_DIRBITS 3
6
7#define _IOC_NONE 1U
8#define _IOC_READ 2U
9#define _IOC_WRITE 4U
10
11#include <asm-generic/ioctl.h>
12
13#endif /* _ASM_POWERPC_IOCTL_H */
diff --git a/include/asm-powerpc/ioctls.h b/include/asm-powerpc/ioctls.h
deleted file mode 100644
index 279a6229584..00000000000
--- a/include/asm-powerpc/ioctls.h
+++ /dev/null
@@ -1,110 +0,0 @@
1#ifndef _ASM_POWERPC_IOCTLS_H
2#define _ASM_POWERPC_IOCTLS_H
3
4#include <asm/ioctl.h>
5
6#define FIOCLEX _IO('f', 1)
7#define FIONCLEX _IO('f', 2)
8#define FIOASYNC _IOW('f', 125, int)
9#define FIONBIO _IOW('f', 126, int)
10#define FIONREAD _IOR('f', 127, int)
11#define TIOCINQ FIONREAD
12#define FIOQSIZE _IOR('f', 128, loff_t)
13
14#define TIOCGETP _IOR('t', 8, struct sgttyb)
15#define TIOCSETP _IOW('t', 9, struct sgttyb)
16#define TIOCSETN _IOW('t', 10, struct sgttyb) /* TIOCSETP wo flush */
17
18#define TIOCSETC _IOW('t', 17, struct tchars)
19#define TIOCGETC _IOR('t', 18, struct tchars)
20#define TCGETS _IOR('t', 19, struct termios)
21#define TCSETS _IOW('t', 20, struct termios)
22#define TCSETSW _IOW('t', 21, struct termios)
23#define TCSETSF _IOW('t', 22, struct termios)
24
25#define TCGETA _IOR('t', 23, struct termio)
26#define TCSETA _IOW('t', 24, struct termio)
27#define TCSETAW _IOW('t', 25, struct termio)
28#define TCSETAF _IOW('t', 28, struct termio)
29
30#define TCSBRK _IO('t', 29)
31#define TCXONC _IO('t', 30)
32#define TCFLSH _IO('t', 31)
33
34#define TIOCSWINSZ _IOW('t', 103, struct winsize)
35#define TIOCGWINSZ _IOR('t', 104, struct winsize)
36#define TIOCSTART _IO('t', 110) /* start output, like ^Q */
37#define TIOCSTOP _IO('t', 111) /* stop output, like ^S */
38#define TIOCOUTQ _IOR('t', 115, int) /* output queue size */
39
40#define TIOCGLTC _IOR('t', 116, struct ltchars)
41#define TIOCSLTC _IOW('t', 117, struct ltchars)
42#define TIOCSPGRP _IOW('t', 118, int)
43#define TIOCGPGRP _IOR('t', 119, int)
44
45#define TIOCEXCL 0x540C
46#define TIOCNXCL 0x540D
47#define TIOCSCTTY 0x540E
48
49#define TIOCSTI 0x5412
50#define TIOCMGET 0x5415
51#define TIOCMBIS 0x5416
52#define TIOCMBIC 0x5417
53#define TIOCMSET 0x5418
54# define TIOCM_LE 0x001
55# define TIOCM_DTR 0x002
56# define TIOCM_RTS 0x004
57# define TIOCM_ST 0x008
58# define TIOCM_SR 0x010
59# define TIOCM_CTS 0x020
60# define TIOCM_CAR 0x040
61# define TIOCM_RNG 0x080
62# define TIOCM_DSR 0x100
63# define TIOCM_CD TIOCM_CAR
64# define TIOCM_RI TIOCM_RNG
65#define TIOCM_OUT1 0x2000
66#define TIOCM_OUT2 0x4000
67#define TIOCM_LOOP 0x8000
68
69#define TIOCGSOFTCAR 0x5419
70#define TIOCSSOFTCAR 0x541A
71#define TIOCLINUX 0x541C
72#define TIOCCONS 0x541D
73#define TIOCGSERIAL 0x541E
74#define TIOCSSERIAL 0x541F
75#define TIOCPKT 0x5420
76# define TIOCPKT_DATA 0
77# define TIOCPKT_FLUSHREAD 1
78# define TIOCPKT_FLUSHWRITE 2
79# define TIOCPKT_STOP 4
80# define TIOCPKT_START 8
81# define TIOCPKT_NOSTOP 16
82# define TIOCPKT_DOSTOP 32
83
84
85#define TIOCNOTTY 0x5422
86#define TIOCSETD 0x5423
87#define TIOCGETD 0x5424
88#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */
89#define TIOCSBRK 0x5427 /* BSD compatibility */
90#define TIOCCBRK 0x5428 /* BSD compatibility */
91#define TIOCGSID 0x5429 /* Return the session ID of FD */
92#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
93#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */
94
95#define TIOCSERCONFIG 0x5453
96#define TIOCSERGWILD 0x5454
97#define TIOCSERSWILD 0x5455
98#define TIOCGLCKTRMIOS 0x5456
99#define TIOCSLCKTRMIOS 0x5457
100#define TIOCSERGSTRUCT 0x5458 /* For debugging only */
101#define TIOCSERGETLSR 0x5459 /* Get line status register */
102 /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
103# define TIOCSER_TEMT 0x01 /* Transmitter physically empty */
104#define TIOCSERGETMULTI 0x545A /* Get multiport config */
105#define TIOCSERSETMULTI 0x545B /* Set multiport config */
106
107#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */
108#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */
109
110#endif /* _ASM_POWERPC_IOCTLS_H */
diff --git a/include/asm-powerpc/iommu.h b/include/asm-powerpc/iommu.h
deleted file mode 100644
index 51ecfef8d84..00000000000
--- a/include/asm-powerpc/iommu.h
+++ /dev/null
@@ -1,131 +0,0 @@
1/*
2 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
3 * Rewrite, cleanup:
4 * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef _ASM_IOMMU_H
22#define _ASM_IOMMU_H
23#ifdef __KERNEL__
24
25#include <linux/compiler.h>
26#include <linux/spinlock.h>
27#include <linux/device.h>
28#include <linux/dma-mapping.h>
29#include <linux/bitops.h>
30#include <asm/machdep.h>
31#include <asm/types.h>
32
33#define IOMMU_PAGE_SHIFT 12
34#define IOMMU_PAGE_SIZE (ASM_CONST(1) << IOMMU_PAGE_SHIFT)
35#define IOMMU_PAGE_MASK (~((1 << IOMMU_PAGE_SHIFT) - 1))
36#define IOMMU_PAGE_ALIGN(addr) _ALIGN_UP(addr, IOMMU_PAGE_SIZE)
37
38/* Boot time flags */
39extern int iommu_is_off;
40extern int iommu_force_on;
41
42/* Pure 2^n version of get_order */
43static __inline__ __attribute_const__ int get_iommu_order(unsigned long size)
44{
45 return __ilog2((size - 1) >> IOMMU_PAGE_SHIFT) + 1;
46}
47
48
49/*
50 * IOMAP_MAX_ORDER defines the largest contiguous block
51 * of dma space we can get. IOMAP_MAX_ORDER = 13
52 * allows up to 2**12 pages (4096 * 4096) = 16 MB
53 */
54#define IOMAP_MAX_ORDER 13
55
56struct iommu_table {
57 unsigned long it_busno; /* Bus number this table belongs to */
58 unsigned long it_size; /* Size of iommu table in entries */
59 unsigned long it_offset; /* Offset into global table */
60 unsigned long it_base; /* mapped address of tce table */
61 unsigned long it_index; /* which iommu table this is */
62 unsigned long it_type; /* type: PCI or Virtual Bus */
63 unsigned long it_blocksize; /* Entries in each block (cacheline) */
64 unsigned long it_hint; /* Hint for next alloc */
65 unsigned long it_largehint; /* Hint for large allocs */
66 unsigned long it_halfpoint; /* Breaking point for small/large allocs */
67 spinlock_t it_lock; /* Protects it_map */
68 unsigned long *it_map; /* A simple allocation bitmap for now */
69};
70
71struct scatterlist;
72
73/* Frees table for an individual device node */
74extern void iommu_free_table(struct iommu_table *tbl, const char *node_name);
75
76/* Initializes an iommu_table based in values set in the passed-in
77 * structure
78 */
79extern struct iommu_table *iommu_init_table(struct iommu_table * tbl,
80 int nid);
81
82extern int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
83 struct scatterlist *sglist, int nelems,
84 unsigned long mask, enum dma_data_direction direction,
85 struct dma_attrs *attrs);
86extern void iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist,
87 int nelems, enum dma_data_direction direction,
88 struct dma_attrs *attrs);
89
90extern void *iommu_alloc_coherent(struct device *dev, struct iommu_table *tbl,
91 size_t size, dma_addr_t *dma_handle,
92 unsigned long mask, gfp_t flag, int node);
93extern void iommu_free_coherent(struct iommu_table *tbl, size_t size,
94 void *vaddr, dma_addr_t dma_handle);
95extern dma_addr_t iommu_map_single(struct device *dev, struct iommu_table *tbl,
96 void *vaddr, size_t size, unsigned long mask,
97 enum dma_data_direction direction,
98 struct dma_attrs *attrs);
99extern void iommu_unmap_single(struct iommu_table *tbl, dma_addr_t dma_handle,
100 size_t size, enum dma_data_direction direction,
101 struct dma_attrs *attrs);
102
103extern void iommu_init_early_pSeries(void);
104extern void iommu_init_early_iSeries(void);
105extern void iommu_init_early_dart(void);
106extern void iommu_init_early_pasemi(void);
107
108#ifdef CONFIG_PCI
109extern void pci_iommu_init(void);
110extern void pci_direct_iommu_init(void);
111#else
112static inline void pci_iommu_init(void) { }
113#endif
114
115extern void alloc_dart_table(void);
116#if defined(CONFIG_PPC64) && defined(CONFIG_PM)
117static inline void iommu_save(void)
118{
119 if (ppc_md.iommu_save)
120 ppc_md.iommu_save();
121}
122
123static inline void iommu_restore(void)
124{
125 if (ppc_md.iommu_restore)
126 ppc_md.iommu_restore();
127}
128#endif
129
130#endif /* __KERNEL__ */
131#endif /* _ASM_IOMMU_H */
diff --git a/include/asm-powerpc/ipcbuf.h b/include/asm-powerpc/ipcbuf.h
deleted file mode 100644
index 2c3e1d94db1..00000000000
--- a/include/asm-powerpc/ipcbuf.h
+++ /dev/null
@@ -1,34 +0,0 @@
1#ifndef _ASM_POWERPC_IPCBUF_H
2#define _ASM_POWERPC_IPCBUF_H
3
4/*
5 * The ipc64_perm structure for the powerpc is identical to
6 * kern_ipc_perm as we have always had 32-bit UIDs and GIDs in the
7 * kernel. Note extra padding because this structure is passed back
8 * and forth between kernel and user space. Pad space is left for:
9 * - 1 32-bit value to fill up for 8-byte alignment
10 * - 2 miscellaneous 64-bit values
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version
15 * 2 of the License, or (at your option) any later version.
16 */
17
18#include <linux/types.h>
19
20struct ipc64_perm
21{
22 __kernel_key_t key;
23 __kernel_uid_t uid;
24 __kernel_gid_t gid;
25 __kernel_uid_t cuid;
26 __kernel_gid_t cgid;
27 __kernel_mode_t mode;
28 unsigned int seq;
29 unsigned int __pad1;
30 unsigned long long __unused1;
31 unsigned long long __unused2;
32};
33
34#endif /* _ASM_POWERPC_IPCBUF_H */
diff --git a/include/asm-powerpc/ipic.h b/include/asm-powerpc/ipic.h
deleted file mode 100644
index 8ff08be0014..00000000000
--- a/include/asm-powerpc/ipic.h
+++ /dev/null
@@ -1,93 +0,0 @@
1/*
2 * include/asm-powerpc/ipic.h
3 *
4 * IPIC external definitions and structure.
5 *
6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
7 *
8 * Copyright 2005 Freescale Semiconductor, Inc
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15#ifdef __KERNEL__
16#ifndef __ASM_IPIC_H__
17#define __ASM_IPIC_H__
18
19#include <linux/irq.h>
20
21/* Flags when we init the IPIC */
22#define IPIC_SPREADMODE_GRP_A 0x00000001
23#define IPIC_SPREADMODE_GRP_B 0x00000002
24#define IPIC_SPREADMODE_GRP_C 0x00000004
25#define IPIC_SPREADMODE_GRP_D 0x00000008
26#define IPIC_SPREADMODE_MIX_A 0x00000010
27#define IPIC_SPREADMODE_MIX_B 0x00000020
28#define IPIC_DISABLE_MCP_OUT 0x00000040
29#define IPIC_IRQ0_MCP 0x00000080
30
31/* IPIC registers offsets */
32#define IPIC_SICFR 0x00 /* System Global Interrupt Configuration Register */
33#define IPIC_SIVCR 0x04 /* System Global Interrupt Vector Register */
34#define IPIC_SIPNR_H 0x08 /* System Internal Interrupt Pending Register (HIGH) */
35#define IPIC_SIPNR_L 0x0C /* System Internal Interrupt Pending Register (LOW) */
36#define IPIC_SIPRR_A 0x10 /* System Internal Interrupt group A Priority Register */
37#define IPIC_SIPRR_B 0x14 /* System Internal Interrupt group B Priority Register */
38#define IPIC_SIPRR_C 0x18 /* System Internal Interrupt group C Priority Register */
39#define IPIC_SIPRR_D 0x1C /* System Internal Interrupt group D Priority Register */
40#define IPIC_SIMSR_H 0x20 /* System Internal Interrupt Mask Register (HIGH) */
41#define IPIC_SIMSR_L 0x24 /* System Internal Interrupt Mask Register (LOW) */
42#define IPIC_SICNR 0x28 /* System Internal Interrupt Control Register */
43#define IPIC_SEPNR 0x2C /* System External Interrupt Pending Register */
44#define IPIC_SMPRR_A 0x30 /* System Mixed Interrupt group A Priority Register */
45#define IPIC_SMPRR_B 0x34 /* System Mixed Interrupt group B Priority Register */
46#define IPIC_SEMSR 0x38 /* System External Interrupt Mask Register */
47#define IPIC_SECNR 0x3C /* System External Interrupt Control Register */
48#define IPIC_SERSR 0x40 /* System Error Status Register */
49#define IPIC_SERMR 0x44 /* System Error Mask Register */
50#define IPIC_SERCR 0x48 /* System Error Control Register */
51#define IPIC_SIFCR_H 0x50 /* System Internal Interrupt Force Register (HIGH) */
52#define IPIC_SIFCR_L 0x54 /* System Internal Interrupt Force Register (LOW) */
53#define IPIC_SEFCR 0x58 /* System External Interrupt Force Register */
54#define IPIC_SERFR 0x5C /* System Error Force Register */
55#define IPIC_SCVCR 0x60 /* System Critical Interrupt Vector Register */
56#define IPIC_SMVCR 0x64 /* System Management Interrupt Vector Register */
57
58enum ipic_prio_grp {
59 IPIC_INT_GRP_A = IPIC_SIPRR_A,
60 IPIC_INT_GRP_D = IPIC_SIPRR_D,
61 IPIC_MIX_GRP_A = IPIC_SMPRR_A,
62 IPIC_MIX_GRP_B = IPIC_SMPRR_B,
63};
64
65enum ipic_mcp_irq {
66 IPIC_MCP_IRQ0 = 0,
67 IPIC_MCP_WDT = 1,
68 IPIC_MCP_SBA = 2,
69 IPIC_MCP_PCI1 = 5,
70 IPIC_MCP_PCI2 = 6,
71 IPIC_MCP_MU = 7,
72};
73
74extern int ipic_set_priority(unsigned int irq, unsigned int priority);
75extern void ipic_set_highest_priority(unsigned int irq);
76extern void ipic_set_default_priority(void);
77extern void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq);
78extern void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq);
79extern u32 ipic_get_mcp_status(void);
80extern void ipic_clear_mcp_status(u32 mask);
81
82#ifdef CONFIG_PPC_MERGE
83extern struct ipic * ipic_init(struct device_node *node, unsigned int flags);
84extern unsigned int ipic_get_irq(void);
85#else
86extern void ipic_init(phys_addr_t phys_addr, unsigned int flags,
87 unsigned int irq_offset,
88 unsigned char *senses, unsigned int senses_count);
89extern int ipic_get_irq(void);
90#endif
91
92#endif /* __ASM_IPIC_H__ */
93#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/irq.h b/include/asm-powerpc/irq.h
deleted file mode 100644
index 1ef8e304e0e..00000000000
--- a/include/asm-powerpc/irq.h
+++ /dev/null
@@ -1,654 +0,0 @@
1#ifdef __KERNEL__
2#ifndef _ASM_POWERPC_IRQ_H
3#define _ASM_POWERPC_IRQ_H
4
5/*
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#include <linux/threads.h>
13#include <linux/list.h>
14#include <linux/radix-tree.h>
15
16#include <asm/types.h>
17#include <asm/atomic.h>
18
19
20#define get_irq_desc(irq) (&irq_desc[(irq)])
21
22/* Define a way to iterate across irqs. */
23#define for_each_irq(i) \
24 for ((i) = 0; (i) < NR_IRQS; ++(i))
25
26extern atomic_t ppc_n_lost_interrupts;
27
28#ifdef CONFIG_PPC_MERGE
29
30/* This number is used when no interrupt has been assigned */
31#define NO_IRQ (0)
32
33/* This is a special irq number to return from get_irq() to tell that
34 * no interrupt happened _and_ ignore it (don't count it as bad). Some
35 * platforms like iSeries rely on that.
36 */
37#define NO_IRQ_IGNORE ((unsigned int)-1)
38
39/* Total number of virq in the platform (make it a CONFIG_* option ? */
40#define NR_IRQS 512
41
42/* Number of irqs reserved for the legacy controller */
43#define NUM_ISA_INTERRUPTS 16
44
45/* This type is the placeholder for a hardware interrupt number. It has to
46 * be big enough to enclose whatever representation is used by a given
47 * platform.
48 */
49typedef unsigned long irq_hw_number_t;
50
51/* Interrupt controller "host" data structure. This could be defined as a
52 * irq domain controller. That is, it handles the mapping between hardware
53 * and virtual interrupt numbers for a given interrupt domain. The host
54 * structure is generally created by the PIC code for a given PIC instance
55 * (though a host can cover more than one PIC if they have a flat number
56 * model). It's the host callbacks that are responsible for setting the
57 * irq_chip on a given irq_desc after it's been mapped.
58 *
59 * The host code and data structures are fairly agnostic to the fact that
60 * we use an open firmware device-tree. We do have references to struct
61 * device_node in two places: in irq_find_host() to find the host matching
62 * a given interrupt controller node, and of course as an argument to its
63 * counterpart host->ops->match() callback. However, those are treated as
64 * generic pointers by the core and the fact that it's actually a device-node
65 * pointer is purely a convention between callers and implementation. This
66 * code could thus be used on other architectures by replacing those two
67 * by some sort of arch-specific void * "token" used to identify interrupt
68 * controllers.
69 */
70struct irq_host;
71struct radix_tree_root;
72
73/* Functions below are provided by the host and called whenever a new mapping
74 * is created or an old mapping is disposed. The host can then proceed to
75 * whatever internal data structures management is required. It also needs
76 * to setup the irq_desc when returning from map().
77 */
78struct irq_host_ops {
79 /* Match an interrupt controller device node to a host, returns
80 * 1 on a match
81 */
82 int (*match)(struct irq_host *h, struct device_node *node);
83
84 /* Create or update a mapping between a virtual irq number and a hw
85 * irq number. This is called only once for a given mapping.
86 */
87 int (*map)(struct irq_host *h, unsigned int virq, irq_hw_number_t hw);
88
89 /* Dispose of such a mapping */
90 void (*unmap)(struct irq_host *h, unsigned int virq);
91
92 /* Update of such a mapping */
93 void (*remap)(struct irq_host *h, unsigned int virq, irq_hw_number_t hw);
94
95 /* Translate device-tree interrupt specifier from raw format coming
96 * from the firmware to a irq_hw_number_t (interrupt line number) and
97 * type (sense) that can be passed to set_irq_type(). In the absence
98 * of this callback, irq_create_of_mapping() and irq_of_parse_and_map()
99 * will return the hw number in the first cell and IRQ_TYPE_NONE for
100 * the type (which amount to keeping whatever default value the
101 * interrupt controller has for that line)
102 */
103 int (*xlate)(struct irq_host *h, struct device_node *ctrler,
104 u32 *intspec, unsigned int intsize,
105 irq_hw_number_t *out_hwirq, unsigned int *out_type);
106};
107
108struct irq_host {
109 struct list_head link;
110
111 /* type of reverse mapping technique */
112 unsigned int revmap_type;
113#define IRQ_HOST_MAP_LEGACY 0 /* legacy 8259, gets irqs 1..15 */
114#define IRQ_HOST_MAP_NOMAP 1 /* no fast reverse mapping */
115#define IRQ_HOST_MAP_LINEAR 2 /* linear map of interrupts */
116#define IRQ_HOST_MAP_TREE 3 /* radix tree */
117 union {
118 struct {
119 unsigned int size;
120 unsigned int *revmap;
121 } linear;
122 struct radix_tree_root tree;
123 } revmap_data;
124 struct irq_host_ops *ops;
125 void *host_data;
126 irq_hw_number_t inval_irq;
127
128 /* Optional device node pointer */
129 struct device_node *of_node;
130};
131
132/* The main irq map itself is an array of NR_IRQ entries containing the
133 * associate host and irq number. An entry with a host of NULL is free.
134 * An entry can be allocated if it's free, the allocator always then sets
135 * hwirq first to the host's invalid irq number and then fills ops.
136 */
137struct irq_map_entry {
138 irq_hw_number_t hwirq;
139 struct irq_host *host;
140};
141
142extern struct irq_map_entry irq_map[NR_IRQS];
143
144extern irq_hw_number_t virq_to_hw(unsigned int virq);
145
146/**
147 * irq_alloc_host - Allocate a new irq_host data structure
148 * @of_node: optional device-tree node of the interrupt controller
149 * @revmap_type: type of reverse mapping to use
150 * @revmap_arg: for IRQ_HOST_MAP_LINEAR linear only: size of the map
151 * @ops: map/unmap host callbacks
152 * @inval_irq: provide a hw number in that host space that is always invalid
153 *
154 * Allocates and initialize and irq_host structure. Note that in the case of
155 * IRQ_HOST_MAP_LEGACY, the map() callback will be called before this returns
156 * for all legacy interrupts except 0 (which is always the invalid irq for
157 * a legacy controller). For a IRQ_HOST_MAP_LINEAR, the map is allocated by
158 * this call as well. For a IRQ_HOST_MAP_TREE, the radix tree will be allocated
159 * later during boot automatically (the reverse mapping will use the slow path
160 * until that happens).
161 */
162extern struct irq_host *irq_alloc_host(struct device_node *of_node,
163 unsigned int revmap_type,
164 unsigned int revmap_arg,
165 struct irq_host_ops *ops,
166 irq_hw_number_t inval_irq);
167
168
169/**
170 * irq_find_host - Locates a host for a given device node
171 * @node: device-tree node of the interrupt controller
172 */
173extern struct irq_host *irq_find_host(struct device_node *node);
174
175
176/**
177 * irq_set_default_host - Set a "default" host
178 * @host: default host pointer
179 *
180 * For convenience, it's possible to set a "default" host that will be used
181 * whenever NULL is passed to irq_create_mapping(). It makes life easier for
182 * platforms that want to manipulate a few hard coded interrupt numbers that
183 * aren't properly represented in the device-tree.
184 */
185extern void irq_set_default_host(struct irq_host *host);
186
187
188/**
189 * irq_set_virq_count - Set the maximum number of virt irqs
190 * @count: number of linux virtual irqs, capped with NR_IRQS
191 *
192 * This is mainly for use by platforms like iSeries who want to program
193 * the virtual irq number in the controller to avoid the reverse mapping
194 */
195extern void irq_set_virq_count(unsigned int count);
196
197
198/**
199 * irq_create_mapping - Map a hardware interrupt into linux virq space
200 * @host: host owning this hardware interrupt or NULL for default host
201 * @hwirq: hardware irq number in that host space
202 *
203 * Only one mapping per hardware interrupt is permitted. Returns a linux
204 * virq number.
205 * If the sense/trigger is to be specified, set_irq_type() should be called
206 * on the number returned from that call.
207 */
208extern unsigned int irq_create_mapping(struct irq_host *host,
209 irq_hw_number_t hwirq);
210
211
212/**
213 * irq_dispose_mapping - Unmap an interrupt
214 * @virq: linux virq number of the interrupt to unmap
215 */
216extern void irq_dispose_mapping(unsigned int virq);
217
218/**
219 * irq_find_mapping - Find a linux virq from an hw irq number.
220 * @host: host owning this hardware interrupt
221 * @hwirq: hardware irq number in that host space
222 *
223 * This is a slow path, for use by generic code. It's expected that an
224 * irq controller implementation directly calls the appropriate low level
225 * mapping function.
226 */
227extern unsigned int irq_find_mapping(struct irq_host *host,
228 irq_hw_number_t hwirq);
229
230/**
231 * irq_create_direct_mapping - Allocate a virq for direct mapping
232 * @host: host to allocate the virq for or NULL for default host
233 *
234 * This routine is used for irq controllers which can choose the hardware
235 * interrupt numbers they generate. In such a case it's simplest to use
236 * the linux virq as the hardware interrupt number.
237 */
238extern unsigned int irq_create_direct_mapping(struct irq_host *host);
239
240/**
241 * irq_radix_revmap - Find a linux virq from a hw irq number.
242 * @host: host owning this hardware interrupt
243 * @hwirq: hardware irq number in that host space
244 *
245 * This is a fast path, for use by irq controller code that uses radix tree
246 * revmaps
247 */
248extern unsigned int irq_radix_revmap(struct irq_host *host,
249 irq_hw_number_t hwirq);
250
251/**
252 * irq_linear_revmap - Find a linux virq from a hw irq number.
253 * @host: host owning this hardware interrupt
254 * @hwirq: hardware irq number in that host space
255 *
256 * This is a fast path, for use by irq controller code that uses linear
257 * revmaps. It does fallback to the slow path if the revmap doesn't exist
258 * yet and will create the revmap entry with appropriate locking
259 */
260
261extern unsigned int irq_linear_revmap(struct irq_host *host,
262 irq_hw_number_t hwirq);
263
264
265
266/**
267 * irq_alloc_virt - Allocate virtual irq numbers
268 * @host: host owning these new virtual irqs
269 * @count: number of consecutive numbers to allocate
270 * @hint: pass a hint number, the allocator will try to use a 1:1 mapping
271 *
272 * This is a low level function that is used internally by irq_create_mapping()
273 * and that can be used by some irq controllers implementations for things
274 * like allocating ranges of numbers for MSIs. The revmaps are left untouched.
275 */
276extern unsigned int irq_alloc_virt(struct irq_host *host,
277 unsigned int count,
278 unsigned int hint);
279
280/**
281 * irq_free_virt - Free virtual irq numbers
282 * @virq: virtual irq number of the first interrupt to free
283 * @count: number of interrupts to free
284 *
285 * This function is the opposite of irq_alloc_virt. It will not clear reverse
286 * maps, this should be done previously by unmap'ing the interrupt. In fact,
287 * all interrupts covered by the range being freed should have been unmapped
288 * prior to calling this.
289 */
290extern void irq_free_virt(unsigned int virq, unsigned int count);
291
292
293/* -- OF helpers -- */
294
295/* irq_create_of_mapping - Map a hardware interrupt into linux virq space
296 * @controller: Device node of the interrupt controller
297 * @inspec: Interrupt specifier from the device-tree
298 * @intsize: Size of the interrupt specifier from the device-tree
299 *
300 * This function is identical to irq_create_mapping except that it takes
301 * as input informations straight from the device-tree (typically the results
302 * of the of_irq_map_*() functions.
303 */
304extern unsigned int irq_create_of_mapping(struct device_node *controller,
305 u32 *intspec, unsigned int intsize);
306
307
308/* irq_of_parse_and_map - Parse nad Map an interrupt into linux virq space
309 * @device: Device node of the device whose interrupt is to be mapped
310 * @index: Index of the interrupt to map
311 *
312 * This function is a wrapper that chains of_irq_map_one() and
313 * irq_create_of_mapping() to make things easier to callers
314 */
315extern unsigned int irq_of_parse_and_map(struct device_node *dev, int index);
316
317/* -- End OF helpers -- */
318
319/**
320 * irq_early_init - Init irq remapping subsystem
321 */
322extern void irq_early_init(void);
323
324static __inline__ int irq_canonicalize(int irq)
325{
326 return irq;
327}
328
329
330#else /* CONFIG_PPC_MERGE */
331
332/* This number is used when no interrupt has been assigned */
333#define NO_IRQ (-1)
334#define NO_IRQ_IGNORE (-2)
335
336
337/*
338 * These constants are used for passing information about interrupt
339 * signal polarity and level/edge sensing to the low-level PIC chip
340 * drivers.
341 */
342#define IRQ_SENSE_MASK 0x1
343#define IRQ_SENSE_LEVEL 0x1 /* interrupt on active level */
344#define IRQ_SENSE_EDGE 0x0 /* interrupt triggered by edge */
345
346#define IRQ_POLARITY_MASK 0x2
347#define IRQ_POLARITY_POSITIVE 0x2 /* high level or low->high edge */
348#define IRQ_POLARITY_NEGATIVE 0x0 /* low level or high->low edge */
349
350
351#if defined(CONFIG_40x)
352#include <asm/ibm4xx.h>
353
354#ifndef NR_BOARD_IRQS
355#define NR_BOARD_IRQS 0
356#endif
357
358#ifndef UIC_WIDTH /* Number of interrupts per device */
359#define UIC_WIDTH 32
360#endif
361
362#ifndef NR_UICS /* number of UIC devices */
363#define NR_UICS 1
364#endif
365
366#if defined (CONFIG_403)
367/*
368 * The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has
369 * 32 possible interrupts, a majority of which are not implemented on
370 * all cores. There are six configurable, external interrupt pins and
371 * there are eight internal interrupts for the on-chip serial port
372 * (SPU), DMA controller, and JTAG controller.
373 *
374 */
375
376#define NR_AIC_IRQS 32
377#define NR_IRQS (NR_AIC_IRQS + NR_BOARD_IRQS)
378
379#elif !defined (CONFIG_403)
380
381/*
382 * The PowerPC 405 cores' Universal Interrupt Controller (UIC) has 32
383 * possible interrupts as well. There are seven, configurable external
384 * interrupt pins and there are 17 internal interrupts for the on-chip
385 * serial port, DMA controller, on-chip Ethernet controller, PCI, etc.
386 *
387 */
388
389
390#define NR_UIC_IRQS UIC_WIDTH
391#define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
392#endif
393
394#elif defined(CONFIG_44x)
395#include <asm/ibm44x.h>
396
397#define NR_UIC_IRQS 32
398#define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
399
400#elif defined(CONFIG_8xx)
401
402/* Now include the board configuration specific associations.
403*/
404#include <asm/mpc8xx.h>
405
406/* The MPC8xx cores have 16 possible interrupts. There are eight
407 * possible level sensitive interrupts assigned and generated internally
408 * from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer.
409 * There are eight external interrupts (IRQs) that can be configured
410 * as either level or edge sensitive.
411 *
412 * On some implementations, there is also the possibility of an 8259
413 * through the PCI and PCI-ISA bridges.
414 *
415 * We are "flattening" the interrupt vectors of the cascaded CPM
416 * and 8259 interrupt controllers so that we can uniquely identify
417 * any interrupt source with a single integer.
418 */
419#define NR_SIU_INTS 16
420#define NR_CPM_INTS 32
421#ifndef NR_8259_INTS
422#define NR_8259_INTS 0
423#endif
424
425#define SIU_IRQ_OFFSET 0
426#define CPM_IRQ_OFFSET (SIU_IRQ_OFFSET + NR_SIU_INTS)
427#define I8259_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS)
428
429#define NR_IRQS (NR_SIU_INTS + NR_CPM_INTS + NR_8259_INTS)
430
431/* These values must be zero-based and map 1:1 with the SIU configuration.
432 * They are used throughout the 8xx I/O subsystem to generate
433 * interrupt masks, flags, and other control patterns. This is why the
434 * current kernel assumption of the 8259 as the base controller is such
435 * a pain in the butt.
436 */
437#define SIU_IRQ0 (0) /* Highest priority */
438#define SIU_LEVEL0 (1)
439#define SIU_IRQ1 (2)
440#define SIU_LEVEL1 (3)
441#define SIU_IRQ2 (4)
442#define SIU_LEVEL2 (5)
443#define SIU_IRQ3 (6)
444#define SIU_LEVEL3 (7)
445#define SIU_IRQ4 (8)
446#define SIU_LEVEL4 (9)
447#define SIU_IRQ5 (10)
448#define SIU_LEVEL5 (11)
449#define SIU_IRQ6 (12)
450#define SIU_LEVEL6 (13)
451#define SIU_IRQ7 (14)
452#define SIU_LEVEL7 (15)
453
454#define MPC8xx_INT_FEC1 SIU_LEVEL1
455#define MPC8xx_INT_FEC2 SIU_LEVEL3
456
457#define MPC8xx_INT_SCC1 (CPM_IRQ_OFFSET + CPMVEC_SCC1)
458#define MPC8xx_INT_SCC2 (CPM_IRQ_OFFSET + CPMVEC_SCC2)
459#define MPC8xx_INT_SCC3 (CPM_IRQ_OFFSET + CPMVEC_SCC3)
460#define MPC8xx_INT_SCC4 (CPM_IRQ_OFFSET + CPMVEC_SCC4)
461#define MPC8xx_INT_SMC1 (CPM_IRQ_OFFSET + CPMVEC_SMC1)
462#define MPC8xx_INT_SMC2 (CPM_IRQ_OFFSET + CPMVEC_SMC2)
463
464/* The internal interrupts we can configure as we see fit.
465 * My personal preference is CPM at level 2, which puts it above the
466 * MBX PCI/ISA/IDE interrupts.
467 */
468#ifndef PIT_INTERRUPT
469#define PIT_INTERRUPT SIU_LEVEL0
470#endif
471#ifndef CPM_INTERRUPT
472#define CPM_INTERRUPT SIU_LEVEL2
473#endif
474#ifndef PCMCIA_INTERRUPT
475#define PCMCIA_INTERRUPT SIU_LEVEL6
476#endif
477#ifndef DEC_INTERRUPT
478#define DEC_INTERRUPT SIU_LEVEL7
479#endif
480
481/* Some internal interrupt registers use an 8-bit mask for the interrupt
482 * level instead of a number.
483 */
484#define mk_int_int_mask(IL) (1 << (7 - (IL/2)))
485
486#else /* CONFIG_40x + CONFIG_8xx */
487/*
488 * this is the # irq's for all ppc arch's (pmac/chrp/prep)
489 * so it is the max of them all
490 */
491#define NR_IRQS 256
492#define __DO_IRQ_CANON 1
493
494#ifndef CONFIG_8260
495
496#define NUM_8259_INTERRUPTS 16
497
498#else /* CONFIG_8260 */
499
500/* The 8260 has an internal interrupt controller with a maximum of
501 * 64 IRQs. We will use NR_IRQs from above since it is large enough.
502 * Don't be confused by the 8260 documentation where they list an
503 * "interrupt number" and "interrupt vector". We are only interested
504 * in the interrupt vector. There are "reserved" holes where the
505 * vector number increases, but the interrupt number in the table does not.
506 * (Document errata updates have fixed this...make sure you have up to
507 * date processor documentation -- Dan).
508 */
509
510#ifndef CPM_IRQ_OFFSET
511#define CPM_IRQ_OFFSET 0
512#endif
513
514#define NR_CPM_INTS 64
515
516#define SIU_INT_ERROR ((uint)0x00 + CPM_IRQ_OFFSET)
517#define SIU_INT_I2C ((uint)0x01 + CPM_IRQ_OFFSET)
518#define SIU_INT_SPI ((uint)0x02 + CPM_IRQ_OFFSET)
519#define SIU_INT_RISC ((uint)0x03 + CPM_IRQ_OFFSET)
520#define SIU_INT_SMC1 ((uint)0x04 + CPM_IRQ_OFFSET)
521#define SIU_INT_SMC2 ((uint)0x05 + CPM_IRQ_OFFSET)
522#define SIU_INT_IDMA1 ((uint)0x06 + CPM_IRQ_OFFSET)
523#define SIU_INT_IDMA2 ((uint)0x07 + CPM_IRQ_OFFSET)
524#define SIU_INT_IDMA3 ((uint)0x08 + CPM_IRQ_OFFSET)
525#define SIU_INT_IDMA4 ((uint)0x09 + CPM_IRQ_OFFSET)
526#define SIU_INT_SDMA ((uint)0x0a + CPM_IRQ_OFFSET)
527#define SIU_INT_USB ((uint)0x0b + CPM_IRQ_OFFSET)
528#define SIU_INT_TIMER1 ((uint)0x0c + CPM_IRQ_OFFSET)
529#define SIU_INT_TIMER2 ((uint)0x0d + CPM_IRQ_OFFSET)
530#define SIU_INT_TIMER3 ((uint)0x0e + CPM_IRQ_OFFSET)
531#define SIU_INT_TIMER4 ((uint)0x0f + CPM_IRQ_OFFSET)
532#define SIU_INT_TMCNT ((uint)0x10 + CPM_IRQ_OFFSET)
533#define SIU_INT_PIT ((uint)0x11 + CPM_IRQ_OFFSET)
534#define SIU_INT_PCI ((uint)0x12 + CPM_IRQ_OFFSET)
535#define SIU_INT_IRQ1 ((uint)0x13 + CPM_IRQ_OFFSET)
536#define SIU_INT_IRQ2 ((uint)0x14 + CPM_IRQ_OFFSET)
537#define SIU_INT_IRQ3 ((uint)0x15 + CPM_IRQ_OFFSET)
538#define SIU_INT_IRQ4 ((uint)0x16 + CPM_IRQ_OFFSET)
539#define SIU_INT_IRQ5 ((uint)0x17 + CPM_IRQ_OFFSET)
540#define SIU_INT_IRQ6 ((uint)0x18 + CPM_IRQ_OFFSET)
541#define SIU_INT_IRQ7 ((uint)0x19 + CPM_IRQ_OFFSET)
542#define SIU_INT_FCC1 ((uint)0x20 + CPM_IRQ_OFFSET)
543#define SIU_INT_FCC2 ((uint)0x21 + CPM_IRQ_OFFSET)
544#define SIU_INT_FCC3 ((uint)0x22 + CPM_IRQ_OFFSET)
545#define SIU_INT_MCC1 ((uint)0x24 + CPM_IRQ_OFFSET)
546#define SIU_INT_MCC2 ((uint)0x25 + CPM_IRQ_OFFSET)
547#define SIU_INT_SCC1 ((uint)0x28 + CPM_IRQ_OFFSET)
548#define SIU_INT_SCC2 ((uint)0x29 + CPM_IRQ_OFFSET)
549#define SIU_INT_SCC3 ((uint)0x2a + CPM_IRQ_OFFSET)
550#define SIU_INT_SCC4 ((uint)0x2b + CPM_IRQ_OFFSET)
551#define SIU_INT_PC15 ((uint)0x30 + CPM_IRQ_OFFSET)
552#define SIU_INT_PC14 ((uint)0x31 + CPM_IRQ_OFFSET)
553#define SIU_INT_PC13 ((uint)0x32 + CPM_IRQ_OFFSET)
554#define SIU_INT_PC12 ((uint)0x33 + CPM_IRQ_OFFSET)
555#define SIU_INT_PC11 ((uint)0x34 + CPM_IRQ_OFFSET)
556#define SIU_INT_PC10 ((uint)0x35 + CPM_IRQ_OFFSET)
557#define SIU_INT_PC9 ((uint)0x36 + CPM_IRQ_OFFSET)
558#define SIU_INT_PC8 ((uint)0x37 + CPM_IRQ_OFFSET)
559#define SIU_INT_PC7 ((uint)0x38 + CPM_IRQ_OFFSET)
560#define SIU_INT_PC6 ((uint)0x39 + CPM_IRQ_OFFSET)
561#define SIU_INT_PC5 ((uint)0x3a + CPM_IRQ_OFFSET)
562#define SIU_INT_PC4 ((uint)0x3b + CPM_IRQ_OFFSET)
563#define SIU_INT_PC3 ((uint)0x3c + CPM_IRQ_OFFSET)
564#define SIU_INT_PC2 ((uint)0x3d + CPM_IRQ_OFFSET)
565#define SIU_INT_PC1 ((uint)0x3e + CPM_IRQ_OFFSET)
566#define SIU_INT_PC0 ((uint)0x3f + CPM_IRQ_OFFSET)
567
568#endif /* CONFIG_8260 */
569
570#endif /* Whatever way too big #ifdef */
571
572#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
573/* pedantic: these are long because they are used with set_bit --RR */
574extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
575
576/*
577 * Because many systems have two overlapping names spaces for
578 * interrupts (ISA and XICS for example), and the ISA interrupts
579 * have historically not been easy to renumber, we allow ISA
580 * interrupts to take values 0 - 15, and shift up the remaining
581 * interrupts by 0x10.
582 */
583#define NUM_ISA_INTERRUPTS 0x10
584extern int __irq_offset_value;
585
586static inline int irq_offset_up(int irq)
587{
588 return(irq + __irq_offset_value);
589}
590
591static inline int irq_offset_down(int irq)
592{
593 return(irq - __irq_offset_value);
594}
595
596static inline int irq_offset_value(void)
597{
598 return __irq_offset_value;
599}
600
601#ifdef __DO_IRQ_CANON
602extern int ppc_do_canonicalize_irqs;
603#else
604#define ppc_do_canonicalize_irqs 0
605#endif
606
607static __inline__ int irq_canonicalize(int irq)
608{
609 if (ppc_do_canonicalize_irqs && irq == 2)
610 irq = 9;
611 return irq;
612}
613#endif /* CONFIG_PPC_MERGE */
614
615extern int distribute_irqs;
616
617struct irqaction;
618struct pt_regs;
619
620#define __ARCH_HAS_DO_SOFTIRQ
621
622#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
623/*
624 * Per-cpu stacks for handling critical, debug and machine check
625 * level interrupts.
626 */
627extern struct thread_info *critirq_ctx[NR_CPUS];
628extern struct thread_info *dbgirq_ctx[NR_CPUS];
629extern struct thread_info *mcheckirq_ctx[NR_CPUS];
630extern void exc_lvl_ctx_init(void);
631#else
632#define exc_lvl_ctx_init()
633#endif
634
635#ifdef CONFIG_IRQSTACKS
636/*
637 * Per-cpu stacks for handling hard and soft interrupts.
638 */
639extern struct thread_info *hardirq_ctx[NR_CPUS];
640extern struct thread_info *softirq_ctx[NR_CPUS];
641
642extern void irq_ctx_init(void);
643extern void call_do_softirq(struct thread_info *tp);
644extern int call_handle_irq(int irq, void *p1,
645 struct thread_info *tp, void *func);
646#else
647#define irq_ctx_init()
648
649#endif /* CONFIG_IRQSTACKS */
650
651extern void do_IRQ(struct pt_regs *regs);
652
653#endif /* _ASM_IRQ_H */
654#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/irq_regs.h b/include/asm-powerpc/irq_regs.h
deleted file mode 100644
index ba94b51a0a7..00000000000
--- a/include/asm-powerpc/irq_regs.h
+++ /dev/null
@@ -1,2 +0,0 @@
1#include <asm-generic/irq_regs.h>
2
diff --git a/include/asm-powerpc/irqflags.h b/include/asm-powerpc/irqflags.h
deleted file mode 100644
index cc6fdba3366..00000000000
--- a/include/asm-powerpc/irqflags.h
+++ /dev/null
@@ -1,44 +0,0 @@
1/*
2 * include/asm-powerpc/irqflags.h
3 *
4 * IRQ flags handling
5 */
6#ifndef _ASM_IRQFLAGS_H
7#define _ASM_IRQFLAGS_H
8
9#ifndef __ASSEMBLY__
10/*
11 * Get definitions for raw_local_save_flags(x), etc.
12 */
13#include <asm-powerpc/hw_irq.h>
14
15#else
16#ifdef CONFIG_TRACE_IRQFLAGS
17/*
18 * Most of the CPU's IRQ-state tracing is done from assembly code; we
19 * have to call a C function so call a wrapper that saves all the
20 * C-clobbered registers.
21 */
22#define TRACE_ENABLE_INTS bl .trace_hardirqs_on
23#define TRACE_DISABLE_INTS bl .trace_hardirqs_off
24#define TRACE_AND_RESTORE_IRQ_PARTIAL(en,skip) \
25 cmpdi en, 0; \
26 bne 95f; \
27 stb en,PACASOFTIRQEN(r13); \
28 bl .trace_hardirqs_off; \
29 b skip; \
3095: bl .trace_hardirqs_on; \
31 li en,1;
32#define TRACE_AND_RESTORE_IRQ(en) \
33 TRACE_AND_RESTORE_IRQ_PARTIAL(en,96f); \
3496: stb en,PACASOFTIRQEN(r13)
35#else
36#define TRACE_ENABLE_INTS
37#define TRACE_DISABLE_INTS
38#define TRACE_AND_RESTORE_IRQ_PARTIAL(en,skip)
39#define TRACE_AND_RESTORE_IRQ(en) \
40 stb en,PACASOFTIRQEN(r13)
41#endif
42#endif
43
44#endif
diff --git a/include/asm-powerpc/iseries/alpaca.h b/include/asm-powerpc/iseries/alpaca.h
deleted file mode 100644
index c0cce6727a6..00000000000
--- a/include/asm-powerpc/iseries/alpaca.h
+++ /dev/null
@@ -1,31 +0,0 @@
1/*
2 * Copyright © 2008 Stephen Rothwell IBM Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18#ifndef _ASM_POWERPC_ISERIES_ALPACA_H
19#define _ASM_POWERPC_ISERIES_ALPACA_H
20
21/*
22 * This is the part of the paca that the iSeries hypervisor
23 * needs to be statically initialised. Immediately after boot
24 * we switch to the normal Linux paca.
25 */
26struct alpaca {
27 struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */
28 const void *reg_save_ptr; /* Pointer to LpRegSave for PLIC */
29};
30
31#endif /* _ASM_POWERPC_ISERIES_ALPACA_H */
diff --git a/include/asm-powerpc/iseries/hv_call.h b/include/asm-powerpc/iseries/hv_call.h
deleted file mode 100644
index 162d653ad51..00000000000
--- a/include/asm-powerpc/iseries/hv_call.h
+++ /dev/null
@@ -1,111 +0,0 @@
1/*
2 * Copyright (C) 2001 Mike Corrigan IBM Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 *
18 * This file contains the "hypervisor call" interface which is used to
19 * drive the hypervisor from the OS.
20 */
21#ifndef _ASM_POWERPC_ISERIES_HV_CALL_H
22#define _ASM_POWERPC_ISERIES_HV_CALL_H
23
24#include <asm/iseries/hv_call_sc.h>
25#include <asm/iseries/hv_types.h>
26#include <asm/paca.h>
27
28/* Type of yield for HvCallBaseYieldProcessor */
29#define HvCall_YieldTimed 0 /* Yield until specified time (tb) */
30#define HvCall_YieldToActive 1 /* Yield until all active procs have run */
31#define HvCall_YieldToProc 2 /* Yield until the specified processor has run */
32
33/* interrupt masks for setEnabledInterrupts */
34#define HvCall_MaskIPI 0x00000001
35#define HvCall_MaskLpEvent 0x00000002
36#define HvCall_MaskLpProd 0x00000004
37#define HvCall_MaskTimeout 0x00000008
38
39/* Log buffer formats */
40#define HvCall_LogBuffer_ASCII 0
41#define HvCall_LogBuffer_EBCDIC 1
42
43#define HvCallBaseAckDeferredInts HvCallBase + 0
44#define HvCallBaseCpmPowerOff HvCallBase + 1
45#define HvCallBaseGetHwPatch HvCallBase + 2
46#define HvCallBaseReIplSpAttn HvCallBase + 3
47#define HvCallBaseSetASR HvCallBase + 4
48#define HvCallBaseSetASRAndRfi HvCallBase + 5
49#define HvCallBaseSetIMR HvCallBase + 6
50#define HvCallBaseSendIPI HvCallBase + 7
51#define HvCallBaseTerminateMachine HvCallBase + 8
52#define HvCallBaseTerminateMachineSrc HvCallBase + 9
53#define HvCallBaseProcessPlicInterrupts HvCallBase + 10
54#define HvCallBaseIsPrimaryCpmOrMsdIpl HvCallBase + 11
55#define HvCallBaseSetVirtualSIT HvCallBase + 12
56#define HvCallBaseVaryOffThisProcessor HvCallBase + 13
57#define HvCallBaseVaryOffMemoryChunk HvCallBase + 14
58#define HvCallBaseVaryOffInteractivePercentage HvCallBase + 15
59#define HvCallBaseSendLpProd HvCallBase + 16
60#define HvCallBaseSetEnabledInterrupts HvCallBase + 17
61#define HvCallBaseYieldProcessor HvCallBase + 18
62#define HvCallBaseVaryOffSharedProcUnits HvCallBase + 19
63#define HvCallBaseSetVirtualDecr HvCallBase + 20
64#define HvCallBaseClearLogBuffer HvCallBase + 21
65#define HvCallBaseGetLogBufferCodePage HvCallBase + 22
66#define HvCallBaseGetLogBufferFormat HvCallBase + 23
67#define HvCallBaseGetLogBufferLength HvCallBase + 24
68#define HvCallBaseReadLogBuffer HvCallBase + 25
69#define HvCallBaseSetLogBufferFormatAndCodePage HvCallBase + 26
70#define HvCallBaseWriteLogBuffer HvCallBase + 27
71#define HvCallBaseRouter28 HvCallBase + 28
72#define HvCallBaseRouter29 HvCallBase + 29
73#define HvCallBaseRouter30 HvCallBase + 30
74#define HvCallBaseSetDebugBus HvCallBase + 31
75
76#define HvCallCcSetDABR HvCallCc + 7
77
78static inline void HvCall_setVirtualDecr(void)
79{
80 /*
81 * Ignore any error return codes - most likely means that the
82 * target value for the LP has been increased and this vary off
83 * would bring us below the new target.
84 */
85 HvCall0(HvCallBaseSetVirtualDecr);
86}
87
88static inline void HvCall_yieldProcessor(unsigned typeOfYield, u64 yieldParm)
89{
90 HvCall2(HvCallBaseYieldProcessor, typeOfYield, yieldParm);
91}
92
93static inline void HvCall_setEnabledInterrupts(u64 enabledInterrupts)
94{
95 HvCall1(HvCallBaseSetEnabledInterrupts, enabledInterrupts);
96}
97
98static inline void HvCall_setLogBufferFormatAndCodepage(int format,
99 u32 codePage)
100{
101 HvCall2(HvCallBaseSetLogBufferFormatAndCodePage, format, codePage);
102}
103
104extern void HvCall_writeLogBuffer(const void *buffer, u64 bufLen);
105
106static inline void HvCall_sendIPI(struct paca_struct *targetPaca)
107{
108 HvCall1(HvCallBaseSendIPI, targetPaca->paca_index);
109}
110
111#endif /* _ASM_POWERPC_ISERIES_HV_CALL_H */
diff --git a/include/asm-powerpc/iseries/hv_call_event.h b/include/asm-powerpc/iseries/hv_call_event.h
deleted file mode 100644
index cc029d388e1..00000000000
--- a/include/asm-powerpc/iseries/hv_call_event.h
+++ /dev/null
@@ -1,201 +0,0 @@
1/*
2 * Copyright (C) 2001 Mike Corrigan IBM Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 *
18 * This file contains the "hypervisor call" interface which is used to
19 * drive the hypervisor from the OS.
20 */
21#ifndef _ASM_POWERPC_ISERIES_HV_CALL_EVENT_H
22#define _ASM_POWERPC_ISERIES_HV_CALL_EVENT_H
23
24#include <linux/types.h>
25#include <linux/dma-mapping.h>
26
27#include <asm/iseries/hv_call_sc.h>
28#include <asm/iseries/hv_types.h>
29#include <asm/abs_addr.h>
30
31struct HvLpEvent;
32
33typedef u8 HvLpEvent_Type;
34typedef u8 HvLpEvent_AckInd;
35typedef u8 HvLpEvent_AckType;
36
37typedef u8 HvLpDma_Direction;
38typedef u8 HvLpDma_AddressType;
39
40typedef u64 HvLpEvent_Rc;
41typedef u64 HvLpDma_Rc;
42
43#define HvCallEventAckLpEvent HvCallEvent + 0
44#define HvCallEventCancelLpEvent HvCallEvent + 1
45#define HvCallEventCloseLpEventPath HvCallEvent + 2
46#define HvCallEventDmaBufList HvCallEvent + 3
47#define HvCallEventDmaSingle HvCallEvent + 4
48#define HvCallEventDmaToSp HvCallEvent + 5
49#define HvCallEventGetOverflowLpEvents HvCallEvent + 6
50#define HvCallEventGetSourceLpInstanceId HvCallEvent + 7
51#define HvCallEventGetTargetLpInstanceId HvCallEvent + 8
52#define HvCallEventOpenLpEventPath HvCallEvent + 9
53#define HvCallEventSetLpEventStack HvCallEvent + 10
54#define HvCallEventSignalLpEvent HvCallEvent + 11
55#define HvCallEventSignalLpEventParms HvCallEvent + 12
56#define HvCallEventSetInterLpQueueIndex HvCallEvent + 13
57#define HvCallEventSetLpEventQueueInterruptProc HvCallEvent + 14
58#define HvCallEventRouter15 HvCallEvent + 15
59
60static inline void HvCallEvent_getOverflowLpEvents(u8 queueIndex)
61{
62 HvCall1(HvCallEventGetOverflowLpEvents, queueIndex);
63}
64
65static inline void HvCallEvent_setInterLpQueueIndex(u8 queueIndex)
66{
67 HvCall1(HvCallEventSetInterLpQueueIndex, queueIndex);
68}
69
70static inline void HvCallEvent_setLpEventStack(u8 queueIndex,
71 char *eventStackAddr, u32 eventStackSize)
72{
73 HvCall3(HvCallEventSetLpEventStack, queueIndex,
74 virt_to_abs(eventStackAddr), eventStackSize);
75}
76
77static inline void HvCallEvent_setLpEventQueueInterruptProc(u8 queueIndex,
78 u16 lpLogicalProcIndex)
79{
80 HvCall2(HvCallEventSetLpEventQueueInterruptProc, queueIndex,
81 lpLogicalProcIndex);
82}
83
84static inline HvLpEvent_Rc HvCallEvent_signalLpEvent(struct HvLpEvent *event)
85{
86 return HvCall1(HvCallEventSignalLpEvent, virt_to_abs(event));
87}
88
89static inline HvLpEvent_Rc HvCallEvent_signalLpEventFast(HvLpIndex targetLp,
90 HvLpEvent_Type type, u16 subtype, HvLpEvent_AckInd ackInd,
91 HvLpEvent_AckType ackType, HvLpInstanceId sourceInstanceId,
92 HvLpInstanceId targetInstanceId, u64 correlationToken,
93 u64 eventData1, u64 eventData2, u64 eventData3,
94 u64 eventData4, u64 eventData5)
95{
96 /* Pack the misc bits into a single Dword to pass to PLIC */
97 union {
98 struct {
99 u8 ack_and_target;
100 u8 type;
101 u16 subtype;
102 HvLpInstanceId src_inst;
103 HvLpInstanceId target_inst;
104 } parms;
105 u64 dword;
106 } packed;
107
108 packed.parms.ack_and_target = (ackType << 7) | (ackInd << 6) | targetLp;
109 packed.parms.type = type;
110 packed.parms.subtype = subtype;
111 packed.parms.src_inst = sourceInstanceId;
112 packed.parms.target_inst = targetInstanceId;
113
114 return HvCall7(HvCallEventSignalLpEventParms, packed.dword,
115 correlationToken, eventData1, eventData2,
116 eventData3, eventData4, eventData5);
117}
118
119extern void *iseries_hv_alloc(size_t size, dma_addr_t *dma_handle, gfp_t flag);
120extern void iseries_hv_free(size_t size, void *vaddr, dma_addr_t dma_handle);
121extern dma_addr_t iseries_hv_map(void *vaddr, size_t size,
122 enum dma_data_direction direction);
123extern void iseries_hv_unmap(dma_addr_t dma_handle, size_t size,
124 enum dma_data_direction direction);
125
126static inline HvLpEvent_Rc HvCallEvent_ackLpEvent(struct HvLpEvent *event)
127{
128 return HvCall1(HvCallEventAckLpEvent, virt_to_abs(event));
129}
130
131static inline HvLpEvent_Rc HvCallEvent_cancelLpEvent(struct HvLpEvent *event)
132{
133 return HvCall1(HvCallEventCancelLpEvent, virt_to_abs(event));
134}
135
136static inline HvLpInstanceId HvCallEvent_getSourceLpInstanceId(
137 HvLpIndex targetLp, HvLpEvent_Type type)
138{
139 return HvCall2(HvCallEventGetSourceLpInstanceId, targetLp, type);
140}
141
142static inline HvLpInstanceId HvCallEvent_getTargetLpInstanceId(
143 HvLpIndex targetLp, HvLpEvent_Type type)
144{
145 return HvCall2(HvCallEventGetTargetLpInstanceId, targetLp, type);
146}
147
148static inline void HvCallEvent_openLpEventPath(HvLpIndex targetLp,
149 HvLpEvent_Type type)
150{
151 HvCall2(HvCallEventOpenLpEventPath, targetLp, type);
152}
153
154static inline void HvCallEvent_closeLpEventPath(HvLpIndex targetLp,
155 HvLpEvent_Type type)
156{
157 HvCall2(HvCallEventCloseLpEventPath, targetLp, type);
158}
159
160static inline HvLpDma_Rc HvCallEvent_dmaBufList(HvLpEvent_Type type,
161 HvLpIndex remoteLp, HvLpDma_Direction direction,
162 HvLpInstanceId localInstanceId,
163 HvLpInstanceId remoteInstanceId,
164 HvLpDma_AddressType localAddressType,
165 HvLpDma_AddressType remoteAddressType,
166 /* Do these need to be converted to absolute addresses? */
167 u64 localBufList, u64 remoteBufList, u32 transferLength)
168{
169 /* Pack the misc bits into a single Dword to pass to PLIC */
170 union {
171 struct {
172 u8 flags;
173 HvLpIndex remote;
174 u8 type;
175 u8 reserved;
176 HvLpInstanceId local_inst;
177 HvLpInstanceId remote_inst;
178 } parms;
179 u64 dword;
180 } packed;
181
182 packed.parms.flags = (direction << 7) |
183 (localAddressType << 6) | (remoteAddressType << 5);
184 packed.parms.remote = remoteLp;
185 packed.parms.type = type;
186 packed.parms.reserved = 0;
187 packed.parms.local_inst = localInstanceId;
188 packed.parms.remote_inst = remoteInstanceId;
189
190 return HvCall4(HvCallEventDmaBufList, packed.dword, localBufList,
191 remoteBufList, transferLength);
192}
193
194static inline HvLpDma_Rc HvCallEvent_dmaToSp(void *local, u32 remote,
195 u32 length, HvLpDma_Direction dir)
196{
197 return HvCall4(HvCallEventDmaToSp, virt_to_abs(local), remote,
198 length, dir);
199}
200
201#endif /* _ASM_POWERPC_ISERIES_HV_CALL_EVENT_H */
diff --git a/include/asm-powerpc/iseries/hv_call_sc.h b/include/asm-powerpc/iseries/hv_call_sc.h
deleted file mode 100644
index f5d21095925..00000000000
--- a/include/asm-powerpc/iseries/hv_call_sc.h
+++ /dev/null
@@ -1,50 +0,0 @@
1/*
2 * Copyright (C) 2001 Mike Corrigan IBM Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18#ifndef _ASM_POWERPC_ISERIES_HV_CALL_SC_H
19#define _ASM_POWERPC_ISERIES_HV_CALL_SC_H
20
21#include <linux/types.h>
22
23#define HvCallBase 0x8000000000000000ul
24#define HvCallCc 0x8001000000000000ul
25#define HvCallCfg 0x8002000000000000ul
26#define HvCallEvent 0x8003000000000000ul
27#define HvCallHpt 0x8004000000000000ul
28#define HvCallPci 0x8005000000000000ul
29#define HvCallSm 0x8007000000000000ul
30#define HvCallXm 0x8009000000000000ul
31
32extern u64 HvCall0(u64);
33extern u64 HvCall1(u64, u64);
34extern u64 HvCall2(u64, u64, u64);
35extern u64 HvCall3(u64, u64, u64, u64);
36extern u64 HvCall4(u64, u64, u64, u64, u64);
37extern u64 HvCall5(u64, u64, u64, u64, u64, u64);
38extern u64 HvCall6(u64, u64, u64, u64, u64, u64, u64);
39extern u64 HvCall7(u64, u64, u64, u64, u64, u64, u64, u64);
40
41extern u64 HvCall0Ret16(u64, void *);
42extern u64 HvCall1Ret16(u64, void *, u64);
43extern u64 HvCall2Ret16(u64, void *, u64, u64);
44extern u64 HvCall3Ret16(u64, void *, u64, u64, u64);
45extern u64 HvCall4Ret16(u64, void *, u64, u64, u64, u64);
46extern u64 HvCall5Ret16(u64, void *, u64, u64, u64, u64, u64);
47extern u64 HvCall6Ret16(u64, void *, u64, u64, u64, u64, u64, u64);
48extern u64 HvCall7Ret16(u64, void *, u64, u64 ,u64 ,u64 ,u64 ,u64 ,u64);
49
50#endif /* _ASM_POWERPC_ISERIES_HV_CALL_SC_H */
diff --git a/include/asm-powerpc/iseries/hv_call_xm.h b/include/asm-powerpc/iseries/hv_call_xm.h
deleted file mode 100644
index 392ac3f54df..00000000000
--- a/include/asm-powerpc/iseries/hv_call_xm.h
+++ /dev/null
@@ -1,61 +0,0 @@
1/*
2 * This file contains the "hypervisor call" interface which is used to
3 * drive the hypervisor from SLIC.
4 */
5#ifndef _ASM_POWERPC_ISERIES_HV_CALL_XM_H
6#define _ASM_POWERPC_ISERIES_HV_CALL_XM_H
7
8#include <asm/iseries/hv_call_sc.h>
9#include <asm/iseries/hv_types.h>
10
11#define HvCallXmGetTceTableParms HvCallXm + 0
12#define HvCallXmTestBus HvCallXm + 1
13#define HvCallXmConnectBusUnit HvCallXm + 2
14#define HvCallXmLoadTod HvCallXm + 8
15#define HvCallXmTestBusUnit HvCallXm + 9
16#define HvCallXmSetTce HvCallXm + 11
17#define HvCallXmSetTces HvCallXm + 13
18
19static inline void HvCallXm_getTceTableParms(u64 cb)
20{
21 HvCall1(HvCallXmGetTceTableParms, cb);
22}
23
24static inline u64 HvCallXm_setTce(u64 tceTableToken, u64 tceOffset, u64 tce)
25{
26 return HvCall3(HvCallXmSetTce, tceTableToken, tceOffset, tce);
27}
28
29static inline u64 HvCallXm_setTces(u64 tceTableToken, u64 tceOffset,
30 u64 numTces, u64 tce1, u64 tce2, u64 tce3, u64 tce4)
31{
32 return HvCall7(HvCallXmSetTces, tceTableToken, tceOffset, numTces,
33 tce1, tce2, tce3, tce4);
34}
35
36static inline u64 HvCallXm_testBus(u16 busNumber)
37{
38 return HvCall1(HvCallXmTestBus, busNumber);
39}
40
41static inline u64 HvCallXm_testBusUnit(u16 busNumber, u8 subBusNumber,
42 u8 deviceId)
43{
44 return HvCall2(HvCallXmTestBusUnit, busNumber,
45 (subBusNumber << 8) | deviceId);
46}
47
48static inline u64 HvCallXm_connectBusUnit(u16 busNumber, u8 subBusNumber,
49 u8 deviceId, u64 interruptToken)
50{
51 return HvCall5(HvCallXmConnectBusUnit, busNumber,
52 (subBusNumber << 8) | deviceId, interruptToken, 0,
53 0 /* HvLpConfig::mapDsaToQueueIndex(HvLpDSA(busNumber, xBoard, xCard)) */);
54}
55
56static inline u64 HvCallXm_loadTod(void)
57{
58 return HvCall0(HvCallXmLoadTod);
59}
60
61#endif /* _ASM_POWERPC_ISERIES_HV_CALL_XM_H */
diff --git a/include/asm-powerpc/iseries/hv_lp_config.h b/include/asm-powerpc/iseries/hv_lp_config.h
deleted file mode 100644
index a006fd1e4a2..00000000000
--- a/include/asm-powerpc/iseries/hv_lp_config.h
+++ /dev/null
@@ -1,128 +0,0 @@
1/*
2 * Copyright (C) 2001 Mike Corrigan IBM Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18#ifndef _ASM_POWERPC_ISERIES_HV_LP_CONFIG_H
19#define _ASM_POWERPC_ISERIES_HV_LP_CONFIG_H
20
21/*
22 * This file contains the interface to the LPAR configuration data
23 * to determine which resources should be allocated to each partition.
24 */
25
26#include <asm/iseries/hv_call_sc.h>
27#include <asm/iseries/hv_types.h>
28
29enum {
30 HvCallCfg_Cur = 0,
31 HvCallCfg_Init = 1,
32 HvCallCfg_Max = 2,
33 HvCallCfg_Min = 3
34};
35
36#define HvCallCfgGetSystemPhysicalProcessors HvCallCfg + 6
37#define HvCallCfgGetPhysicalProcessors HvCallCfg + 7
38#define HvCallCfgGetMsChunks HvCallCfg + 9
39#define HvCallCfgGetSharedPoolIndex HvCallCfg + 20
40#define HvCallCfgGetSharedProcUnits HvCallCfg + 21
41#define HvCallCfgGetNumProcsInSharedPool HvCallCfg + 22
42#define HvCallCfgGetVirtualLanIndexMap HvCallCfg + 30
43#define HvCallCfgGetHostingLpIndex HvCallCfg + 32
44
45extern HvLpIndex HvLpConfig_getLpIndex_outline(void);
46extern HvLpIndex HvLpConfig_getLpIndex(void);
47extern HvLpIndex HvLpConfig_getPrimaryLpIndex(void);
48
49static inline u64 HvLpConfig_getMsChunks(void)
50{
51 return HvCall2(HvCallCfgGetMsChunks, HvLpConfig_getLpIndex(),
52 HvCallCfg_Cur);
53}
54
55static inline u64 HvLpConfig_getSystemPhysicalProcessors(void)
56{
57 return HvCall0(HvCallCfgGetSystemPhysicalProcessors);
58}
59
60static inline u64 HvLpConfig_getNumProcsInSharedPool(HvLpSharedPoolIndex sPI)
61{
62 return (u16)HvCall1(HvCallCfgGetNumProcsInSharedPool, sPI);
63}
64
65static inline u64 HvLpConfig_getPhysicalProcessors(void)
66{
67 return HvCall2(HvCallCfgGetPhysicalProcessors, HvLpConfig_getLpIndex(),
68 HvCallCfg_Cur);
69}
70
71static inline HvLpSharedPoolIndex HvLpConfig_getSharedPoolIndex(void)
72{
73 return HvCall1(HvCallCfgGetSharedPoolIndex, HvLpConfig_getLpIndex());
74}
75
76static inline u64 HvLpConfig_getSharedProcUnits(void)
77{
78 return HvCall2(HvCallCfgGetSharedProcUnits, HvLpConfig_getLpIndex(),
79 HvCallCfg_Cur);
80}
81
82static inline u64 HvLpConfig_getMaxSharedProcUnits(void)
83{
84 return HvCall2(HvCallCfgGetSharedProcUnits, HvLpConfig_getLpIndex(),
85 HvCallCfg_Max);
86}
87
88static inline u64 HvLpConfig_getMaxPhysicalProcessors(void)
89{
90 return HvCall2(HvCallCfgGetPhysicalProcessors, HvLpConfig_getLpIndex(),
91 HvCallCfg_Max);
92}
93
94static inline HvLpVirtualLanIndexMap HvLpConfig_getVirtualLanIndexMapForLp(
95 HvLpIndex lp)
96{
97 /*
98 * This is a new function in V5R1 so calls to this on older
99 * hypervisors will return -1
100 */
101 u64 retVal = HvCall1(HvCallCfgGetVirtualLanIndexMap, lp);
102 if (retVal == -1)
103 retVal = 0;
104 return retVal;
105}
106
107static inline HvLpVirtualLanIndexMap HvLpConfig_getVirtualLanIndexMap(void)
108{
109 return HvLpConfig_getVirtualLanIndexMapForLp(
110 HvLpConfig_getLpIndex_outline());
111}
112
113static inline int HvLpConfig_doLpsCommunicateOnVirtualLan(HvLpIndex lp1,
114 HvLpIndex lp2)
115{
116 HvLpVirtualLanIndexMap virtualLanIndexMap1 =
117 HvLpConfig_getVirtualLanIndexMapForLp(lp1);
118 HvLpVirtualLanIndexMap virtualLanIndexMap2 =
119 HvLpConfig_getVirtualLanIndexMapForLp(lp2);
120 return ((virtualLanIndexMap1 & virtualLanIndexMap2) != 0);
121}
122
123static inline HvLpIndex HvLpConfig_getHostingLpIndex(HvLpIndex lp)
124{
125 return HvCall1(HvCallCfgGetHostingLpIndex, lp);
126}
127
128#endif /* _ASM_POWERPC_ISERIES_HV_LP_CONFIG_H */
diff --git a/include/asm-powerpc/iseries/hv_lp_event.h b/include/asm-powerpc/iseries/hv_lp_event.h
deleted file mode 100644
index 8f5da7d7720..00000000000
--- a/include/asm-powerpc/iseries/hv_lp_event.h
+++ /dev/null
@@ -1,162 +0,0 @@
1/*
2 * Copyright (C) 2001 Mike Corrigan IBM Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19/* This file contains the class for HV events in the system. */
20
21#ifndef _ASM_POWERPC_ISERIES_HV_LP_EVENT_H
22#define _ASM_POWERPC_ISERIES_HV_LP_EVENT_H
23
24#include <asm/types.h>
25#include <asm/ptrace.h>
26#include <asm/iseries/hv_types.h>
27#include <asm/iseries/hv_call_event.h>
28
29/*
30 * HvLpEvent is the structure for Lp Event messages passed between
31 * partitions through PLIC.
32 */
33
34struct HvLpEvent {
35 u8 flags; /* Event flags x00-x00 */
36 u8 xType; /* Type of message x01-x01 */
37 u16 xSubtype; /* Subtype for event x02-x03 */
38 u8 xSourceLp; /* Source LP x04-x04 */
39 u8 xTargetLp; /* Target LP x05-x05 */
40 u8 xSizeMinus1; /* Size of Derived class - 1 x06-x06 */
41 u8 xRc; /* RC for Ack flows x07-x07 */
42 u16 xSourceInstanceId; /* Source sides instance id x08-x09 */
43 u16 xTargetInstanceId; /* Target sides instance id x0A-x0B */
44 union {
45 u32 xSubtypeData; /* Data usable by the subtype x0C-x0F */
46 u16 xSubtypeDataShort[2]; /* Data as 2 shorts */
47 u8 xSubtypeDataChar[4]; /* Data as 4 chars */
48 } x;
49
50 u64 xCorrelationToken; /* Unique value for source/type x10-x17 */
51};
52
53typedef void (*LpEventHandler)(struct HvLpEvent *);
54
55/* Register a handler for an event type - returns 0 on success */
56extern int HvLpEvent_registerHandler(HvLpEvent_Type eventType,
57 LpEventHandler hdlr);
58
59/*
60 * Unregister a handler for an event type
61 *
62 * This call will sleep until the handler being removed is guaranteed to
63 * be no longer executing on any CPU. Do not call with locks held.
64 *
65 * returns 0 on success
66 * Unregister will fail if there are any paths open for the type
67 */
68extern int HvLpEvent_unregisterHandler(HvLpEvent_Type eventType);
69
70/*
71 * Open an Lp Event Path for an event type
72 * returns 0 on success
73 * openPath will fail if there is no handler registered for the event type.
74 * The lpIndex specified is the partition index for the target partition
75 * (for VirtualIo, VirtualLan and SessionMgr) other types specify zero)
76 */
77extern int HvLpEvent_openPath(HvLpEvent_Type eventType, HvLpIndex lpIndex);
78
79/*
80 * Close an Lp Event Path for a type and partition
81 * returns 0 on success
82 */
83extern int HvLpEvent_closePath(HvLpEvent_Type eventType, HvLpIndex lpIndex);
84
85#define HvLpEvent_Type_Hypervisor 0
86#define HvLpEvent_Type_MachineFac 1
87#define HvLpEvent_Type_SessionMgr 2
88#define HvLpEvent_Type_SpdIo 3
89#define HvLpEvent_Type_VirtualBus 4
90#define HvLpEvent_Type_PciIo 5
91#define HvLpEvent_Type_RioIo 6
92#define HvLpEvent_Type_VirtualLan 7
93#define HvLpEvent_Type_VirtualIo 8
94#define HvLpEvent_Type_NumTypes 9
95
96#define HvLpEvent_Rc_Good 0
97#define HvLpEvent_Rc_BufferNotAvailable 1
98#define HvLpEvent_Rc_Cancelled 2
99#define HvLpEvent_Rc_GenericError 3
100#define HvLpEvent_Rc_InvalidAddress 4
101#define HvLpEvent_Rc_InvalidPartition 5
102#define HvLpEvent_Rc_InvalidSize 6
103#define HvLpEvent_Rc_InvalidSubtype 7
104#define HvLpEvent_Rc_InvalidSubtypeData 8
105#define HvLpEvent_Rc_InvalidType 9
106#define HvLpEvent_Rc_PartitionDead 10
107#define HvLpEvent_Rc_PathClosed 11
108#define HvLpEvent_Rc_SubtypeError 12
109
110#define HvLpEvent_Function_Ack 0
111#define HvLpEvent_Function_Int 1
112
113#define HvLpEvent_AckInd_NoAck 0
114#define HvLpEvent_AckInd_DoAck 1
115
116#define HvLpEvent_AckType_ImmediateAck 0
117#define HvLpEvent_AckType_DeferredAck 1
118
119#define HV_LP_EVENT_INT 0x01
120#define HV_LP_EVENT_DO_ACK 0x02
121#define HV_LP_EVENT_DEFERRED_ACK 0x04
122#define HV_LP_EVENT_VALID 0x80
123
124#define HvLpDma_Direction_LocalToRemote 0
125#define HvLpDma_Direction_RemoteToLocal 1
126
127#define HvLpDma_AddressType_TceIndex 0
128#define HvLpDma_AddressType_RealAddress 1
129
130#define HvLpDma_Rc_Good 0
131#define HvLpDma_Rc_Error 1
132#define HvLpDma_Rc_PartitionDead 2
133#define HvLpDma_Rc_PathClosed 3
134#define HvLpDma_Rc_InvalidAddress 4
135#define HvLpDma_Rc_InvalidLength 5
136
137static inline int hvlpevent_is_valid(struct HvLpEvent *h)
138{
139 return h->flags & HV_LP_EVENT_VALID;
140}
141
142static inline void hvlpevent_invalidate(struct HvLpEvent *h)
143{
144 h->flags &= ~ HV_LP_EVENT_VALID;
145}
146
147static inline int hvlpevent_is_int(struct HvLpEvent *h)
148{
149 return h->flags & HV_LP_EVENT_INT;
150}
151
152static inline int hvlpevent_is_ack(struct HvLpEvent *h)
153{
154 return !hvlpevent_is_int(h);
155}
156
157static inline int hvlpevent_need_ack(struct HvLpEvent *h)
158{
159 return h->flags & HV_LP_EVENT_DO_ACK;
160}
161
162#endif /* _ASM_POWERPC_ISERIES_HV_LP_EVENT_H */
diff --git a/include/asm-powerpc/iseries/hv_types.h b/include/asm-powerpc/iseries/hv_types.h
deleted file mode 100644
index c3e6d2a1d1c..00000000000
--- a/include/asm-powerpc/iseries/hv_types.h
+++ /dev/null
@@ -1,112 +0,0 @@
1/*
2 * Copyright (C) 2001 Mike Corrigan IBM Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18#ifndef _ASM_POWERPC_ISERIES_HV_TYPES_H
19#define _ASM_POWERPC_ISERIES_HV_TYPES_H
20
21/*
22 * General typedefs for the hypervisor.
23 */
24
25#include <asm/types.h>
26
27typedef u8 HvLpIndex;
28typedef u16 HvLpInstanceId;
29typedef u64 HvLpTOD;
30typedef u64 HvLpSystemSerialNum;
31typedef u8 HvLpDeviceSerialNum[12];
32typedef u16 HvLpSanHwSet;
33typedef u16 HvLpBus;
34typedef u16 HvLpBoard;
35typedef u16 HvLpCard;
36typedef u8 HvLpDeviceType[4];
37typedef u8 HvLpDeviceModel[3];
38typedef u64 HvIoToken;
39typedef u8 HvLpName[8];
40typedef u32 HvIoId;
41typedef u64 HvRealMemoryIndex;
42typedef u32 HvLpIndexMap; /* Must hold HVMAXARCHITECTEDLPS bits!!! */
43typedef u16 HvLpVrmIndex;
44typedef u32 HvXmGenerationId;
45typedef u8 HvLpBusPool;
46typedef u8 HvLpSharedPoolIndex;
47typedef u16 HvLpSharedProcUnitsX100;
48typedef u8 HvLpVirtualLanIndex;
49typedef u16 HvLpVirtualLanIndexMap; /* Must hold HVMAXARCHITECTEDVIRTUALLANS bits!!! */
50typedef u16 HvBusNumber; /* Hypervisor Bus Number */
51typedef u8 HvSubBusNumber; /* Hypervisor SubBus Number */
52typedef u8 HvAgentId; /* Hypervisor DevFn */
53
54
55#define HVMAXARCHITECTEDLPS 32
56#define HVMAXARCHITECTEDVIRTUALLANS 16
57#define HVMAXARCHITECTEDVIRTUALDISKS 32
58#define HVMAXARCHITECTEDVIRTUALCDROMS 8
59#define HVMAXARCHITECTEDVIRTUALTAPES 8
60#define HVCHUNKSIZE (256 * 1024)
61#define HVPAGESIZE (4 * 1024)
62#define HVLPMINMEGSPRIMARY 256
63#define HVLPMINMEGSSECONDARY 64
64#define HVCHUNKSPERMEG 4
65#define HVPAGESPERMEG 256
66#define HVPAGESPERCHUNK 64
67
68#define HvLpIndexInvalid ((HvLpIndex)0xff)
69
70/*
71 * Enums for the sub-components under PLIC
72 * Used in HvCall and HvPrimaryCall
73 */
74enum {
75 HvCallCompId = 0,
76 HvCallCpuCtlsCompId = 1,
77 HvCallCfgCompId = 2,
78 HvCallEventCompId = 3,
79 HvCallHptCompId = 4,
80 HvCallPciCompId = 5,
81 HvCallSlmCompId = 6,
82 HvCallSmCompId = 7,
83 HvCallSpdCompId = 8,
84 HvCallXmCompId = 9,
85 HvCallRioCompId = 10,
86 HvCallRsvd3CompId = 11,
87 HvCallRsvd2CompId = 12,
88 HvCallRsvd1CompId = 13,
89 HvCallMaxCompId = 14,
90 HvPrimaryCallCompId = 0,
91 HvPrimaryCallCfgCompId = 1,
92 HvPrimaryCallPciCompId = 2,
93 HvPrimaryCallSmCompId = 3,
94 HvPrimaryCallSpdCompId = 4,
95 HvPrimaryCallXmCompId = 5,
96 HvPrimaryCallRioCompId = 6,
97 HvPrimaryCallRsvd7CompId = 7,
98 HvPrimaryCallRsvd6CompId = 8,
99 HvPrimaryCallRsvd5CompId = 9,
100 HvPrimaryCallRsvd4CompId = 10,
101 HvPrimaryCallRsvd3CompId = 11,
102 HvPrimaryCallRsvd2CompId = 12,
103 HvPrimaryCallRsvd1CompId = 13,
104 HvPrimaryCallMaxCompId = HvCallMaxCompId
105};
106
107struct HvLpBufferList {
108 u64 addr;
109 u64 len;
110};
111
112#endif /* _ASM_POWERPC_ISERIES_HV_TYPES_H */
diff --git a/include/asm-powerpc/iseries/iommu.h b/include/asm-powerpc/iseries/iommu.h
deleted file mode 100644
index c59ee7e4bed..00000000000
--- a/include/asm-powerpc/iseries/iommu.h
+++ /dev/null
@@ -1,41 +0,0 @@
1#ifndef _ASM_POWERPC_ISERIES_IOMMU_H
2#define _ASM_POWERPC_ISERIES_IOMMU_H
3
4/*
5 * Copyright (C) 2005 Stephen Rothwell, IBM Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the:
19 * Free Software Foundation, Inc.,
20 * 59 Temple Place, Suite 330,
21 * Boston, MA 02111-1307 USA
22 */
23
24struct pci_dev;
25struct vio_dev;
26struct device_node;
27struct iommu_table;
28
29/* Creates table for an individual device node */
30extern void iommu_devnode_init_iSeries(struct pci_dev *pdev,
31 struct device_node *dn);
32
33/* Get table parameters from HV */
34extern void iommu_table_getparms_iSeries(unsigned long busno,
35 unsigned char slotno, unsigned char virtbus,
36 struct iommu_table *tbl);
37
38extern struct iommu_table *vio_build_iommu_table_iseries(struct vio_dev *dev);
39extern void iommu_vio_init(void);
40
41#endif /* _ASM_POWERPC_ISERIES_IOMMU_H */
diff --git a/include/asm-powerpc/iseries/it_lp_queue.h b/include/asm-powerpc/iseries/it_lp_queue.h
deleted file mode 100644
index 42827883882..00000000000
--- a/include/asm-powerpc/iseries/it_lp_queue.h
+++ /dev/null
@@ -1,78 +0,0 @@
1/*
2 * Copyright (C) 2001 Mike Corrigan IBM Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18#ifndef _ASM_POWERPC_ISERIES_IT_LP_QUEUE_H
19#define _ASM_POWERPC_ISERIES_IT_LP_QUEUE_H
20
21/*
22 * This control block defines the simple LP queue structure that is
23 * shared between the hypervisor (PLIC) and the OS in order to send
24 * events to an LP.
25 */
26
27#include <asm/types.h>
28#include <asm/ptrace.h>
29
30#define IT_LP_MAX_QUEUES 8
31
32#define IT_LP_NOT_USED 0 /* Queue will not be used by PLIC */
33#define IT_LP_DEDICATED_IO 1 /* Queue dedicated to IO processor specified */
34#define IT_LP_DEDICATED_LP 2 /* Queue dedicated to LP specified */
35#define IT_LP_SHARED 3 /* Queue shared for both IO and LP */
36
37#define IT_LP_EVENT_STACK_SIZE 4096
38#define IT_LP_EVENT_MAX_SIZE 256
39#define IT_LP_EVENT_ALIGN 64
40
41struct hvlpevent_queue {
42/*
43 * The hq_current_event is the pointer to the next event stack entry
44 * that will become valid. The OS must peek at this entry to determine
45 * if it is valid. PLIC will set the valid indicator as the very last
46 * store into that entry.
47 *
48 * When the OS has completed processing of the event then it will mark
49 * the event as invalid so that PLIC knows it can store into that event
50 * location again.
51 *
52 * If the event stack fills and there are overflow events, then PLIC
53 * will set the hq_overflow_pending flag in which case the OS will
54 * have to fetch the additional LP events once they have drained the
55 * event stack.
56 *
57 * The first 16-bytes are known by both the OS and PLIC. The remainder
58 * of the cache line is for use by the OS.
59 */
60 u8 hq_overflow_pending; /* 0x00 Overflow events are pending */
61 u8 hq_status; /* 0x01 DedicatedIo or DedicatedLp or NotUsed */
62 u16 hq_proc_index; /* 0x02 Logical Proc Index for correlation */
63 u8 hq_reserved1[12]; /* 0x04 */
64 char *hq_current_event; /* 0x10 */
65 char *hq_last_event; /* 0x18 */
66 char *hq_event_stack; /* 0x20 */
67 u8 hq_index; /* 0x28 unique sequential index. */
68 u8 hq_reserved2[3]; /* 0x29-2b */
69 spinlock_t hq_lock;
70};
71
72extern struct hvlpevent_queue hvlpevent_queue;
73
74extern int hvlpevent_is_pending(void);
75extern void process_hvlpevents(void);
76extern void setup_hvlpevent_queue(void);
77
78#endif /* _ASM_POWERPC_ISERIES_IT_LP_QUEUE_H */
diff --git a/include/asm-powerpc/iseries/lpar_map.h b/include/asm-powerpc/iseries/lpar_map.h
deleted file mode 100644
index 5e9f3e128ee..00000000000
--- a/include/asm-powerpc/iseries/lpar_map.h
+++ /dev/null
@@ -1,85 +0,0 @@
1/*
2 * Copyright (C) 2001 Mike Corrigan IBM Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18#ifndef _ASM_POWERPC_ISERIES_LPAR_MAP_H
19#define _ASM_POWERPC_ISERIES_LPAR_MAP_H
20
21#ifndef __ASSEMBLY__
22
23#include <asm/types.h>
24
25#endif
26
27/*
28 * The iSeries hypervisor will set up mapping for one or more
29 * ESID/VSID pairs (in SLB/segment registers) and will set up
30 * mappings of one or more ranges of pages to VAs.
31 * We will have the hypervisor set up the ESID->VSID mapping
32 * for the four kernel segments (C-F). With shared processors,
33 * the hypervisor will clear all segment registers and reload
34 * these four whenever the processor is switched from one
35 * partition to another.
36 */
37
38/* The Vsid and Esid identified below will be used by the hypervisor
39 * to set up a memory mapping for part of the load area before giving
40 * control to the Linux kernel. The load area is 64 MB, but this must
41 * not attempt to map the whole load area. The Hashed Page Table may
42 * need to be located within the load area (if the total partition size
43 * is 64 MB), but cannot be mapped. Typically, this should specify
44 * to map half (32 MB) of the load area.
45 *
46 * The hypervisor will set up page table entries for the number of
47 * pages specified.
48 *
49 * In 32-bit mode, the hypervisor will load all four of the
50 * segment registers (identified by the low-order four bits of the
51 * Esid field. In 64-bit mode, the hypervisor will load one SLB
52 * entry to map the Esid to the Vsid.
53*/
54
55#define HvEsidsToMap 2
56#define HvRangesToMap 1
57
58/* Hypervisor initially maps 32MB of the load area */
59#define HvPagesToMap 8192
60
61#ifndef __ASSEMBLY__
62struct LparMap {
63 u64 xNumberEsids; // Number of ESID/VSID pairs
64 u64 xNumberRanges; // Number of VA ranges to map
65 u64 xSegmentTableOffs; // Page number within load area of seg table
66 u64 xRsvd[5];
67 struct {
68 u64 xKernelEsid; // Esid used to map kernel load
69 u64 xKernelVsid; // Vsid used to map kernel load
70 } xEsids[HvEsidsToMap];
71 struct {
72 u64 xPages; // Number of pages to be mapped
73 u64 xOffset; // Offset from start of load area
74 u64 xVPN; // Virtual Page Number
75 } xRanges[HvRangesToMap];
76};
77
78extern const struct LparMap xLparMap;
79
80#endif /* __ASSEMBLY__ */
81
82/* the fixed address where the LparMap exists */
83#define LPARMAP_PHYS 0x7000
84
85#endif /* _ASM_POWERPC_ISERIES_LPAR_MAP_H */
diff --git a/include/asm-powerpc/iseries/mf.h b/include/asm-powerpc/iseries/mf.h
deleted file mode 100644
index eb851a9c9e5..00000000000
--- a/include/asm-powerpc/iseries/mf.h
+++ /dev/null
@@ -1,51 +0,0 @@
1/*
2 * Copyright (C) 2001 Troy D. Armstrong IBM Corporation
3 * Copyright (C) 2004 Stephen Rothwell IBM Corporation
4 *
5 * This modules exists as an interface between a Linux secondary partition
6 * running on an iSeries and the primary partition's Virtual Service
7 * Processor (VSP) object. The VSP has final authority over powering on/off
8 * all partitions in the iSeries. It also provides miscellaneous low-level
9 * machine facility type operations.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25#ifndef _ASM_POWERPC_ISERIES_MF_H
26#define _ASM_POWERPC_ISERIES_MF_H
27
28#include <linux/types.h>
29
30#include <asm/iseries/hv_types.h>
31#include <asm/iseries/hv_call_event.h>
32
33struct rtc_time;
34
35typedef void (*MFCompleteHandler)(void *clientToken, int returnCode);
36
37extern void mf_allocate_lp_events(HvLpIndex targetLp, HvLpEvent_Type type,
38 unsigned size, unsigned amount, MFCompleteHandler hdlr,
39 void *userToken);
40extern void mf_deallocate_lp_events(HvLpIndex targetLp, HvLpEvent_Type type,
41 unsigned count, MFCompleteHandler hdlr, void *userToken);
42
43extern void mf_power_off(void);
44extern void mf_reboot(char *cmd);
45
46extern void mf_display_src(u32 word);
47extern void mf_display_progress(u16 value);
48
49extern void mf_init(void);
50
51#endif /* _ASM_POWERPC_ISERIES_MF_H */
diff --git a/include/asm-powerpc/iseries/vio.h b/include/asm-powerpc/iseries/vio.h
deleted file mode 100644
index f9ac0d00b95..00000000000
--- a/include/asm-powerpc/iseries/vio.h
+++ /dev/null
@@ -1,265 +0,0 @@
1/* -*- linux-c -*-
2 *
3 * iSeries Virtual I/O Message Path header
4 *
5 * Authors: Dave Boutcher <boutcher@us.ibm.com>
6 * Ryan Arnold <ryanarn@us.ibm.com>
7 * Colin Devilbiss <devilbis@us.ibm.com>
8 *
9 * (C) Copyright 2000 IBM Corporation
10 *
11 * This header file is used by the iSeries virtual I/O device
12 * drivers. It defines the interfaces to the common functions
13 * (implemented in drivers/char/viopath.h) as well as defining
14 * common functions and structures. Currently (at the time I
15 * wrote this comment) the iSeries virtual I/O device drivers
16 * that use this are
17 * drivers/block/viodasd.c
18 * drivers/char/viocons.c
19 * drivers/char/viotape.c
20 * drivers/cdrom/viocd.c
21 *
22 * The iSeries virtual ethernet support (veth.c) uses a whole
23 * different set of functions.
24 *
25 * This program is free software; you can redistribute it and/or
26 * modify it under the terms of the GNU General Public License as
27 * published by the Free Software Foundation; either version 2 of the
28 * License, or (at your option) anyu later version.
29 *
30 * This program is distributed in the hope that it will be useful, but
31 * WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
33 * General Public License for more details.
34 *
35 * You should have received a copy of the GNU General Public License
36 * along with this program; if not, write to the Free Software Foundation,
37 * Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
38 *
39 */
40#ifndef _ASM_POWERPC_ISERIES_VIO_H
41#define _ASM_POWERPC_ISERIES_VIO_H
42
43#include <asm/iseries/hv_types.h>
44#include <asm/iseries/hv_lp_event.h>
45
46/*
47 * iSeries virtual I/O events use the subtype field in
48 * HvLpEvent to figure out what kind of vio event is coming
49 * in. We use a table to route these, and this defines
50 * the maximum number of distinct subtypes
51 */
52#define VIO_MAX_SUBTYPES 8
53
54#define VIOMAXBLOCKDMA 12
55
56struct open_data {
57 u64 disk_size;
58 u16 max_disk;
59 u16 cylinders;
60 u16 tracks;
61 u16 sectors;
62 u16 bytes_per_sector;
63};
64
65struct rw_data {
66 u64 offset;
67 struct {
68 u32 token;
69 u32 reserved;
70 u64 len;
71 } dma_info[VIOMAXBLOCKDMA];
72};
73
74struct vioblocklpevent {
75 struct HvLpEvent event;
76 u32 reserved;
77 u16 version;
78 u16 sub_result;
79 u16 disk;
80 u16 flags;
81 union {
82 struct open_data open_data;
83 struct rw_data rw_data;
84 u64 changed;
85 } u;
86};
87
88#define vioblockflags_ro 0x0001
89
90enum vioblocksubtype {
91 vioblockopen = 0x0001,
92 vioblockclose = 0x0002,
93 vioblockread = 0x0003,
94 vioblockwrite = 0x0004,
95 vioblockflush = 0x0005,
96 vioblockcheck = 0x0007
97};
98
99struct viocdlpevent {
100 struct HvLpEvent event;
101 u32 reserved;
102 u16 version;
103 u16 sub_result;
104 u16 disk;
105 u16 flags;
106 u32 token;
107 u64 offset; /* On open, max number of disks */
108 u64 len; /* On open, size of the disk */
109 u32 block_size; /* Only set on open */
110 u32 media_size; /* Only set on open */
111};
112
113enum viocdsubtype {
114 viocdopen = 0x0001,
115 viocdclose = 0x0002,
116 viocdread = 0x0003,
117 viocdwrite = 0x0004,
118 viocdlockdoor = 0x0005,
119 viocdgetinfo = 0x0006,
120 viocdcheck = 0x0007
121};
122
123struct viotapelpevent {
124 struct HvLpEvent event;
125 u32 reserved;
126 u16 version;
127 u16 sub_type_result;
128 u16 tape;
129 u16 flags;
130 u32 token;
131 u64 len;
132 union {
133 struct {
134 u32 tape_op;
135 u32 count;
136 } op;
137 struct {
138 u32 type;
139 u32 resid;
140 u32 dsreg;
141 u32 gstat;
142 u32 erreg;
143 u32 file_no;
144 u32 block_no;
145 } get_status;
146 struct {
147 u32 block_no;
148 } get_pos;
149 } u;
150};
151
152enum viotapesubtype {
153 viotapeopen = 0x0001,
154 viotapeclose = 0x0002,
155 viotaperead = 0x0003,
156 viotapewrite = 0x0004,
157 viotapegetinfo = 0x0005,
158 viotapeop = 0x0006,
159 viotapegetpos = 0x0007,
160 viotapesetpos = 0x0008,
161 viotapegetstatus = 0x0009
162};
163
164/*
165 * Each subtype can register a handler to process their events.
166 * The handler must have this interface.
167 */
168typedef void (vio_event_handler_t) (struct HvLpEvent * event);
169
170extern int viopath_open(HvLpIndex remoteLp, int subtype, int numReq);
171extern int viopath_close(HvLpIndex remoteLp, int subtype, int numReq);
172extern int vio_setHandler(int subtype, vio_event_handler_t * beh);
173extern int vio_clearHandler(int subtype);
174extern int viopath_isactive(HvLpIndex lp);
175extern HvLpInstanceId viopath_sourceinst(HvLpIndex lp);
176extern HvLpInstanceId viopath_targetinst(HvLpIndex lp);
177extern void vio_set_hostlp(void);
178extern void *vio_get_event_buffer(int subtype);
179extern void vio_free_event_buffer(int subtype, void *buffer);
180
181extern struct vio_dev *vio_create_viodasd(u32 unit);
182
183extern HvLpIndex viopath_hostLp;
184extern HvLpIndex viopath_ourLp;
185
186#define VIOCHAR_MAX_DATA 200
187
188#define VIOMAJOR_SUBTYPE_MASK 0xff00
189#define VIOMINOR_SUBTYPE_MASK 0x00ff
190#define VIOMAJOR_SUBTYPE_SHIFT 8
191
192#define VIOVERSION 0x0101
193
194/*
195 * This is the general structure for VIO errors; each module should have
196 * a table of them, and each table should be terminated by an entry of
197 * { 0, 0, NULL }. Then, to find a specific error message, a module
198 * should pass its local table and the return code.
199 */
200struct vio_error_entry {
201 u16 rc;
202 int errno;
203 const char *msg;
204};
205extern const struct vio_error_entry *vio_lookup_rc(
206 const struct vio_error_entry *local_table, u16 rc);
207
208enum viosubtypes {
209 viomajorsubtype_monitor = 0x0100,
210 viomajorsubtype_blockio = 0x0200,
211 viomajorsubtype_chario = 0x0300,
212 viomajorsubtype_config = 0x0400,
213 viomajorsubtype_cdio = 0x0500,
214 viomajorsubtype_tape = 0x0600,
215 viomajorsubtype_scsi = 0x0700
216};
217
218enum vioconfigsubtype {
219 vioconfigget = 0x0001,
220};
221
222enum viorc {
223 viorc_good = 0x0000,
224 viorc_noConnection = 0x0001,
225 viorc_noReceiver = 0x0002,
226 viorc_noBufferAvailable = 0x0003,
227 viorc_invalidMessageType = 0x0004,
228 viorc_invalidRange = 0x0201,
229 viorc_invalidToken = 0x0202,
230 viorc_DMAError = 0x0203,
231 viorc_useError = 0x0204,
232 viorc_releaseError = 0x0205,
233 viorc_invalidDisk = 0x0206,
234 viorc_openRejected = 0x0301
235};
236
237/*
238 * The structure of the events that flow between us and OS/400 for chario
239 * events. You can't mess with this unless the OS/400 side changes too.
240 */
241struct viocharlpevent {
242 struct HvLpEvent event;
243 u32 reserved;
244 u16 version;
245 u16 subtype_result_code;
246 u8 virtual_device;
247 u8 len;
248 u8 data[VIOCHAR_MAX_DATA];
249};
250
251#define VIOCHAR_WINDOW 10
252
253enum viocharsubtype {
254 viocharopen = 0x0001,
255 viocharclose = 0x0002,
256 viochardata = 0x0003,
257 viocharack = 0x0004,
258 viocharconfig = 0x0005
259};
260
261enum viochar_rc {
262 viochar_rc_ebusy = 1
263};
264
265#endif /* _ASM_POWERPC_ISERIES_VIO_H */
diff --git a/include/asm-powerpc/kdebug.h b/include/asm-powerpc/kdebug.h
deleted file mode 100644
index ae6d206728a..00000000000
--- a/include/asm-powerpc/kdebug.h
+++ /dev/null
@@ -1,15 +0,0 @@
1#ifndef _ASM_POWERPC_KDEBUG_H
2#define _ASM_POWERPC_KDEBUG_H
3#ifdef __KERNEL__
4
5/* Grossly misnamed. */
6enum die_val {
7 DIE_OOPS = 1,
8 DIE_IABR_MATCH,
9 DIE_DABR_MATCH,
10 DIE_BPT,
11 DIE_SSTEP,
12};
13
14#endif /* __KERNEL__ */
15#endif /* _ASM_POWERPC_KDEBUG_H */
diff --git a/include/asm-powerpc/kdump.h b/include/asm-powerpc/kdump.h
deleted file mode 100644
index f6c93c71689..00000000000
--- a/include/asm-powerpc/kdump.h
+++ /dev/null
@@ -1,35 +0,0 @@
1#ifndef _PPC64_KDUMP_H
2#define _PPC64_KDUMP_H
3
4/* Kdump kernel runs at 32 MB, change at your peril. */
5#define KDUMP_KERNELBASE 0x2000000
6
7/* How many bytes to reserve at zero for kdump. The reserve limit should
8 * be greater or equal to the trampoline's end address.
9 * Reserve to the end of the FWNMI area, see head_64.S */
10#define KDUMP_RESERVE_LIMIT 0x10000 /* 64K */
11
12#ifdef CONFIG_CRASH_DUMP
13
14#define KDUMP_TRAMPOLINE_START 0x0100
15#define KDUMP_TRAMPOLINE_END 0x3000
16
17#define KDUMP_MIN_TCE_ENTRIES 2048
18
19#endif /* CONFIG_CRASH_DUMP */
20
21#ifndef __ASSEMBLY__
22#ifdef CONFIG_CRASH_DUMP
23
24extern void reserve_kdump_trampoline(void);
25extern void setup_kdump_trampoline(void);
26
27#else /* !CONFIG_CRASH_DUMP */
28
29static inline void reserve_kdump_trampoline(void) { ; }
30static inline void setup_kdump_trampoline(void) { ; }
31
32#endif /* CONFIG_CRASH_DUMP */
33#endif /* __ASSEMBLY__ */
34
35#endif /* __PPC64_KDUMP_H */
diff --git a/include/asm-powerpc/kexec.h b/include/asm-powerpc/kexec.h
deleted file mode 100644
index acdcdc66f1b..00000000000
--- a/include/asm-powerpc/kexec.h
+++ /dev/null
@@ -1,160 +0,0 @@
1#ifndef _ASM_POWERPC_KEXEC_H
2#define _ASM_POWERPC_KEXEC_H
3#ifdef __KERNEL__
4
5/*
6 * Maximum page that is mapped directly into kernel memory.
7 * XXX: Since we copy virt we can use any page we allocate
8 */
9#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
10
11/*
12 * Maximum address we can reach in physical address mode.
13 * XXX: I want to allow initrd in highmem. Otherwise set to rmo on LPAR.
14 */
15#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
16
17/* Maximum address we can use for the control code buffer */
18#ifdef __powerpc64__
19#define KEXEC_CONTROL_MEMORY_LIMIT (-1UL)
20#else
21/* TASK_SIZE, probably left over from use_mm ?? */
22#define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE
23#endif
24
25#define KEXEC_CONTROL_CODE_SIZE 4096
26
27/* The native architecture */
28#ifdef __powerpc64__
29#define KEXEC_ARCH KEXEC_ARCH_PPC64
30#else
31#define KEXEC_ARCH KEXEC_ARCH_PPC
32#endif
33
34#ifndef __ASSEMBLY__
35#include <linux/cpumask.h>
36
37typedef void (*crash_shutdown_t)(void);
38
39#ifdef CONFIG_KEXEC
40
41#ifdef __powerpc64__
42/*
43 * This function is responsible for capturing register states if coming
44 * via panic or invoking dump using sysrq-trigger.
45 */
46static inline void crash_setup_regs(struct pt_regs *newregs,
47 struct pt_regs *oldregs)
48{
49 if (oldregs)
50 memcpy(newregs, oldregs, sizeof(*newregs));
51 else {
52 /* FIXME Merge this with xmon_save_regs ?? */
53 unsigned long tmp1, tmp2;
54 __asm__ __volatile__ (
55 "std 0,0(%2)\n"
56 "std 1,8(%2)\n"
57 "std 2,16(%2)\n"
58 "std 3,24(%2)\n"
59 "std 4,32(%2)\n"
60 "std 5,40(%2)\n"
61 "std 6,48(%2)\n"
62 "std 7,56(%2)\n"
63 "std 8,64(%2)\n"
64 "std 9,72(%2)\n"
65 "std 10,80(%2)\n"
66 "std 11,88(%2)\n"
67 "std 12,96(%2)\n"
68 "std 13,104(%2)\n"
69 "std 14,112(%2)\n"
70 "std 15,120(%2)\n"
71 "std 16,128(%2)\n"
72 "std 17,136(%2)\n"
73 "std 18,144(%2)\n"
74 "std 19,152(%2)\n"
75 "std 20,160(%2)\n"
76 "std 21,168(%2)\n"
77 "std 22,176(%2)\n"
78 "std 23,184(%2)\n"
79 "std 24,192(%2)\n"
80 "std 25,200(%2)\n"
81 "std 26,208(%2)\n"
82 "std 27,216(%2)\n"
83 "std 28,224(%2)\n"
84 "std 29,232(%2)\n"
85 "std 30,240(%2)\n"
86 "std 31,248(%2)\n"
87 "mfmsr %0\n"
88 "std %0, 264(%2)\n"
89 "mfctr %0\n"
90 "std %0, 280(%2)\n"
91 "mflr %0\n"
92 "std %0, 288(%2)\n"
93 "bl 1f\n"
94 "1: mflr %1\n"
95 "std %1, 256(%2)\n"
96 "mtlr %0\n"
97 "mfxer %0\n"
98 "std %0, 296(%2)\n"
99 : "=&r" (tmp1), "=&r" (tmp2)
100 : "b" (newregs)
101 : "memory");
102 }
103}
104#else
105/*
106 * Provide a dummy definition to avoid build failures. Will remain
107 * empty till crash dump support is enabled.
108 */
109static inline void crash_setup_regs(struct pt_regs *newregs,
110 struct pt_regs *oldregs) { }
111#endif /* !__powerpc64 __ */
112
113extern void kexec_smp_wait(void); /* get and clear naca physid, wait for
114 master to copy new code to 0 */
115extern int crashing_cpu;
116extern void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *));
117extern cpumask_t cpus_in_sr;
118static inline int kexec_sr_activated(int cpu)
119{
120 return cpu_isset(cpu,cpus_in_sr);
121}
122
123struct kimage;
124struct pt_regs;
125extern void default_machine_kexec(struct kimage *image);
126extern int default_machine_kexec_prepare(struct kimage *image);
127extern void default_machine_crash_shutdown(struct pt_regs *regs);
128extern int crash_shutdown_register(crash_shutdown_t handler);
129extern int crash_shutdown_unregister(crash_shutdown_t handler);
130
131extern void machine_kexec_simple(struct kimage *image);
132extern void crash_kexec_secondary(struct pt_regs *regs);
133extern int overlaps_crashkernel(unsigned long start, unsigned long size);
134extern void reserve_crashkernel(void);
135
136#else /* !CONFIG_KEXEC */
137static inline int kexec_sr_activated(int cpu) { return 0; }
138static inline void crash_kexec_secondary(struct pt_regs *regs) { }
139
140static inline int overlaps_crashkernel(unsigned long start, unsigned long size)
141{
142 return 0;
143}
144
145static inline void reserve_crashkernel(void) { ; }
146
147static inline int crash_shutdown_register(crash_shutdown_t handler)
148{
149 return 0;
150}
151
152static inline int crash_shutdown_unregister(crash_shutdown_t handler)
153{
154 return 0;
155}
156
157#endif /* CONFIG_KEXEC */
158#endif /* ! __ASSEMBLY__ */
159#endif /* __KERNEL__ */
160#endif /* _ASM_POWERPC_KEXEC_H */
diff --git a/include/asm-powerpc/keylargo.h b/include/asm-powerpc/keylargo.h
deleted file mode 100644
index d8520ef121f..00000000000
--- a/include/asm-powerpc/keylargo.h
+++ /dev/null
@@ -1,261 +0,0 @@
1#ifndef _ASM_POWERPC_KEYLARGO_H
2#define _ASM_POWERPC_KEYLARGO_H
3#ifdef __KERNEL__
4/*
5 * keylargo.h: definitions for using the "KeyLargo" I/O controller chip.
6 *
7 */
8
9/* "Pangea" chipset has keylargo device-id 0x25 while core99
10 * has device-id 0x22. The rev. of the pangea one is 0, so we
11 * fake an artificial rev. in keylargo_rev by oring 0x100
12 */
13#define KL_PANGEA_REV 0x100
14
15/* offset from base for feature control registers */
16#define KEYLARGO_MBCR 0x34 /* KL Only, Media bay control/status */
17#define KEYLARGO_FCR0 0x38
18#define KEYLARGO_FCR1 0x3c
19#define KEYLARGO_FCR2 0x40
20#define KEYLARGO_FCR3 0x44
21#define KEYLARGO_FCR4 0x48
22#define KEYLARGO_FCR5 0x4c /* Pangea only */
23
24/* K2 aditional FCRs */
25#define K2_FCR6 0x34
26#define K2_FCR7 0x30
27#define K2_FCR8 0x2c
28#define K2_FCR9 0x28
29#define K2_FCR10 0x24
30
31/* GPIO registers */
32#define KEYLARGO_GPIO_LEVELS0 0x50
33#define KEYLARGO_GPIO_LEVELS1 0x54
34#define KEYLARGO_GPIO_EXTINT_0 0x58
35#define KEYLARGO_GPIO_EXTINT_CNT 18
36#define KEYLARGO_GPIO_0 0x6A
37#define KEYLARGO_GPIO_CNT 17
38#define KEYLARGO_GPIO_EXTINT_DUAL_EDGE 0x80
39#define KEYLARGO_GPIO_OUTPUT_ENABLE 0x04
40#define KEYLARGO_GPIO_OUTOUT_DATA 0x01
41#define KEYLARGO_GPIO_INPUT_DATA 0x02
42
43/* K2 does only extint GPIOs and does 51 of them */
44#define K2_GPIO_EXTINT_0 0x58
45#define K2_GPIO_EXTINT_CNT 51
46
47/* Specific GPIO regs */
48
49#define KL_GPIO_MODEM_RESET (KEYLARGO_GPIO_0+0x03)
50#define KL_GPIO_MODEM_POWER (KEYLARGO_GPIO_0+0x02) /* Pangea */
51
52#define KL_GPIO_SOUND_POWER (KEYLARGO_GPIO_0+0x05)
53
54/* Hrm... this one is only to be used on Pismo. It seeem to also
55 * control the timebase enable on other machines. Still to be
56 * experimented... --BenH.
57 */
58#define KL_GPIO_FW_CABLE_POWER (KEYLARGO_GPIO_0+0x09)
59#define KL_GPIO_TB_ENABLE (KEYLARGO_GPIO_0+0x09)
60
61#define KL_GPIO_ETH_PHY_RESET (KEYLARGO_GPIO_0+0x10)
62
63#define KL_GPIO_EXTINT_CPU1 (KEYLARGO_GPIO_0+0x0a)
64#define KL_GPIO_EXTINT_CPU1_ASSERT 0x04
65#define KL_GPIO_EXTINT_CPU1_RELEASE 0x38
66
67#define KL_GPIO_RESET_CPU0 (KEYLARGO_GPIO_EXTINT_0+0x03)
68#define KL_GPIO_RESET_CPU1 (KEYLARGO_GPIO_EXTINT_0+0x04)
69#define KL_GPIO_RESET_CPU2 (KEYLARGO_GPIO_EXTINT_0+0x0f)
70#define KL_GPIO_RESET_CPU3 (KEYLARGO_GPIO_EXTINT_0+0x10)
71
72#define KL_GPIO_PMU_MESSAGE_IRQ (KEYLARGO_GPIO_EXTINT_0+0x09)
73#define KL_GPIO_PMU_MESSAGE_BIT KEYLARGO_GPIO_INPUT_DATA
74
75#define KL_GPIO_MEDIABAY_IRQ (KEYLARGO_GPIO_EXTINT_0+0x0e)
76
77#define KL_GPIO_AIRPORT_0 (KEYLARGO_GPIO_EXTINT_0+0x0a)
78#define KL_GPIO_AIRPORT_1 (KEYLARGO_GPIO_EXTINT_0+0x0d)
79#define KL_GPIO_AIRPORT_2 (KEYLARGO_GPIO_0+0x0d)
80#define KL_GPIO_AIRPORT_3 (KEYLARGO_GPIO_0+0x0e)
81#define KL_GPIO_AIRPORT_4 (KEYLARGO_GPIO_0+0x0f)
82
83/*
84 * Bits in feature control register. Those bits different for K2 are
85 * listed separately
86 */
87#define KL_MBCR_MB0_PCI_ENABLE 0x00000800 /* exist ? */
88#define KL_MBCR_MB0_IDE_ENABLE 0x00001000
89#define KL_MBCR_MB0_FLOPPY_ENABLE 0x00002000 /* exist ? */
90#define KL_MBCR_MB0_SOUND_ENABLE 0x00004000 /* hrm... */
91#define KL_MBCR_MB0_DEV_MASK 0x00007800
92#define KL_MBCR_MB0_DEV_POWER 0x00000400
93#define KL_MBCR_MB0_DEV_RESET 0x00000200
94#define KL_MBCR_MB0_ENABLE 0x00000100
95#define KL_MBCR_MB1_PCI_ENABLE 0x08000000 /* exist ? */
96#define KL_MBCR_MB1_IDE_ENABLE 0x10000000
97#define KL_MBCR_MB1_FLOPPY_ENABLE 0x20000000 /* exist ? */
98#define KL_MBCR_MB1_SOUND_ENABLE 0x40000000 /* hrm... */
99#define KL_MBCR_MB1_DEV_MASK 0x78000000
100#define KL_MBCR_MB1_DEV_POWER 0x04000000
101#define KL_MBCR_MB1_DEV_RESET 0x02000000
102#define KL_MBCR_MB1_ENABLE 0x01000000
103
104#define KL0_SCC_B_INTF_ENABLE 0x00000001 /* (KL Only) */
105#define KL0_SCC_A_INTF_ENABLE 0x00000002
106#define KL0_SCC_SLOWPCLK 0x00000004
107#define KL0_SCC_RESET 0x00000008
108#define KL0_SCCA_ENABLE 0x00000010
109#define KL0_SCCB_ENABLE 0x00000020
110#define KL0_SCC_CELL_ENABLE 0x00000040
111#define KL0_IRDA_HIGH_BAND 0x00000100 /* (KL Only) */
112#define KL0_IRDA_SOURCE2_SEL 0x00000200 /* (KL Only) */
113#define KL0_IRDA_SOURCE1_SEL 0x00000400 /* (KL Only) */
114#define KL0_PG_USB0_PMI_ENABLE 0x00000400 /* (Pangea/Intrepid Only) */
115#define KL0_IRDA_RESET 0x00000800 /* (KL Only) */
116#define KL0_PG_USB0_REF_SUSPEND_SEL 0x00000800 /* (Pangea/Intrepid Only) */
117#define KL0_IRDA_DEFAULT1 0x00001000 /* (KL Only) */
118#define KL0_PG_USB0_REF_SUSPEND 0x00001000 /* (Pangea/Intrepid Only) */
119#define KL0_IRDA_DEFAULT0 0x00002000 /* (KL Only) */
120#define KL0_PG_USB0_PAD_SUSPEND 0x00002000 /* (Pangea/Intrepid Only) */
121#define KL0_IRDA_FAST_CONNECT 0x00004000 /* (KL Only) */
122#define KL0_PG_USB1_PMI_ENABLE 0x00004000 /* (Pangea/Intrepid Only) */
123#define KL0_IRDA_ENABLE 0x00008000 /* (KL Only) */
124#define KL0_PG_USB1_REF_SUSPEND_SEL 0x00008000 /* (Pangea/Intrepid Only) */
125#define KL0_IRDA_CLK32_ENABLE 0x00010000 /* (KL Only) */
126#define KL0_PG_USB1_REF_SUSPEND 0x00010000 /* (Pangea/Intrepid Only) */
127#define KL0_IRDA_CLK19_ENABLE 0x00020000 /* (KL Only) */
128#define KL0_PG_USB1_PAD_SUSPEND 0x00020000 /* (Pangea/Intrepid Only) */
129#define KL0_USB0_PAD_SUSPEND0 0x00040000
130#define KL0_USB0_PAD_SUSPEND1 0x00080000
131#define KL0_USB0_CELL_ENABLE 0x00100000
132#define KL0_USB1_PAD_SUSPEND0 0x00400000
133#define KL0_USB1_PAD_SUSPEND1 0x00800000
134#define KL0_USB1_CELL_ENABLE 0x01000000
135#define KL0_USB_REF_SUSPEND 0x10000000 /* (KL Only) */
136
137#define KL0_SERIAL_ENABLE (KL0_SCC_B_INTF_ENABLE | \
138 KL0_SCC_SLOWPCLK | \
139 KL0_SCC_CELL_ENABLE | KL0_SCCA_ENABLE)
140
141#define KL1_USB2_PMI_ENABLE 0x00000001 /* Intrepid only */
142#define KL1_AUDIO_SEL_22MCLK 0x00000002 /* KL/Pangea only */
143#define KL1_USB2_REF_SUSPEND_SEL 0x00000002 /* Intrepid only */
144#define KL1_USB2_REF_SUSPEND 0x00000004 /* Intrepid only */
145#define KL1_AUDIO_CLK_ENABLE_BIT 0x00000008 /* KL/Pangea only */
146#define KL1_USB2_PAD_SUSPEND_SEL 0x00000008 /* Intrepid only */
147#define KL1_USB2_PAD_SUSPEND0 0x00000010 /* Intrepid only */
148#define KL1_AUDIO_CLK_OUT_ENABLE 0x00000020 /* KL/Pangea only */
149#define KL1_USB2_PAD_SUSPEND1 0x00000020 /* Intrepid only */
150#define KL1_AUDIO_CELL_ENABLE 0x00000040 /* KL/Pangea only */
151#define KL1_USB2_CELL_ENABLE 0x00000040 /* Intrepid only */
152#define KL1_AUDIO_CHOOSE 0x00000080 /* KL/Pangea only */
153#define KL1_I2S0_CHOOSE 0x00000200 /* KL Only */
154#define KL1_I2S0_CELL_ENABLE 0x00000400
155#define KL1_I2S0_CLK_ENABLE_BIT 0x00001000
156#define KL1_I2S0_ENABLE 0x00002000
157#define KL1_I2S1_CELL_ENABLE 0x00020000
158#define KL1_I2S1_CLK_ENABLE_BIT 0x00080000
159#define KL1_I2S1_ENABLE 0x00100000
160#define KL1_EIDE0_ENABLE 0x00800000 /* KL/Intrepid Only */
161#define KL1_EIDE0_RESET_N 0x01000000 /* KL/Intrepid Only */
162#define KL1_EIDE1_ENABLE 0x04000000 /* KL Only */
163#define KL1_EIDE1_RESET_N 0x08000000 /* KL Only */
164#define KL1_UIDE_ENABLE 0x20000000 /* KL/Pangea Only */
165#define KL1_UIDE_RESET_N 0x40000000 /* KL/Pangea Only */
166
167#define KL2_IOBUS_ENABLE 0x00000002
168#define KL2_SLEEP_STATE_BIT 0x00000100 /* KL Only */
169#define KL2_PG_STOP_ALL_CLOCKS 0x00000100 /* Pangea Only */
170#define KL2_MPIC_ENABLE 0x00020000
171#define KL2_CARDSLOT_RESET 0x00040000 /* Pangea/Intrepid Only */
172#define KL2_ALT_DATA_OUT 0x02000000 /* KL Only ??? */
173#define KL2_MEM_IS_BIG 0x04000000
174#define KL2_CARDSEL_16 0x08000000
175
176#define KL3_SHUTDOWN_PLL_TOTAL 0x00000001 /* KL/Pangea only */
177#define KL3_SHUTDOWN_PLLKW6 0x00000002 /* KL/Pangea only */
178#define KL3_IT_SHUTDOWN_PLL3 0x00000002 /* Intrepid only */
179#define KL3_SHUTDOWN_PLLKW4 0x00000004 /* KL/Pangea only */
180#define KL3_IT_SHUTDOWN_PLL2 0x00000004 /* Intrepid only */
181#define KL3_SHUTDOWN_PLLKW35 0x00000008 /* KL/Pangea only */
182#define KL3_IT_SHUTDOWN_PLL1 0x00000008 /* Intrepid only */
183#define KL3_SHUTDOWN_PLLKW12 0x00000010 /* KL Only */
184#define KL3_IT_ENABLE_PLL3_SHUTDOWN 0x00000010 /* Intrepid only */
185#define KL3_PLL_RESET 0x00000020 /* KL/Pangea only */
186#define KL3_IT_ENABLE_PLL2_SHUTDOWN 0x00000020 /* Intrepid only */
187#define KL3_IT_ENABLE_PLL1_SHUTDOWN 0x00000010 /* Intrepid only */
188#define KL3_SHUTDOWN_PLL2X 0x00000080 /* KL Only */
189#define KL3_CLK66_ENABLE 0x00000100 /* KL Only */
190#define KL3_CLK49_ENABLE 0x00000200
191#define KL3_CLK45_ENABLE 0x00000400
192#define KL3_CLK31_ENABLE 0x00000800 /* KL/Pangea only */
193#define KL3_TIMER_CLK18_ENABLE 0x00001000
194#define KL3_I2S1_CLK18_ENABLE 0x00002000
195#define KL3_I2S0_CLK18_ENABLE 0x00004000
196#define KL3_VIA_CLK16_ENABLE 0x00008000 /* KL/Pangea only */
197#define KL3_IT_VIA_CLK32_ENABLE 0x00008000 /* Intrepid only */
198#define KL3_STOPPING33_ENABLED 0x00080000 /* KL Only */
199#define KL3_PG_PLL_ENABLE_TEST 0x00080000 /* Pangea Only */
200
201/* Intrepid USB bus 2, port 0,1 */
202#define KL3_IT_PORT_WAKEUP_ENABLE(p) (0x00080000 << ((p)<<3))
203#define KL3_IT_PORT_RESUME_WAKE_EN(p) (0x00040000 << ((p)<<3))
204#define KL3_IT_PORT_CONNECT_WAKE_EN(p) (0x00020000 << ((p)<<3))
205#define KL3_IT_PORT_DISCONNECT_WAKE_EN(p) (0x00010000 << ((p)<<3))
206#define KL3_IT_PORT_RESUME_STAT(p) (0x00300000 << ((p)<<3))
207#define KL3_IT_PORT_CONNECT_STAT(p) (0x00200000 << ((p)<<3))
208#define KL3_IT_PORT_DISCONNECT_STAT(p) (0x00100000 << ((p)<<3))
209
210/* Port 0,1 : bus 0, port 2,3 : bus 1 */
211#define KL4_PORT_WAKEUP_ENABLE(p) (0x00000008 << ((p)<<3))
212#define KL4_PORT_RESUME_WAKE_EN(p) (0x00000004 << ((p)<<3))
213#define KL4_PORT_CONNECT_WAKE_EN(p) (0x00000002 << ((p)<<3))
214#define KL4_PORT_DISCONNECT_WAKE_EN(p) (0x00000001 << ((p)<<3))
215#define KL4_PORT_RESUME_STAT(p) (0x00000040 << ((p)<<3))
216#define KL4_PORT_CONNECT_STAT(p) (0x00000020 << ((p)<<3))
217#define KL4_PORT_DISCONNECT_STAT(p) (0x00000010 << ((p)<<3))
218
219/* Pangea and Intrepid only */
220#define KL5_VIA_USE_CLK31 0000000001 /* Pangea Only */
221#define KL5_SCC_USE_CLK31 0x00000002 /* Pangea Only */
222#define KL5_PWM_CLK32_EN 0x00000004
223#define KL5_CLK3_68_EN 0x00000010
224#define KL5_CLK32_EN 0x00000020
225
226
227/* K2 definitions */
228#define K2_FCR0_USB0_SWRESET 0x00200000
229#define K2_FCR0_USB1_SWRESET 0x02000000
230#define K2_FCR0_RING_PME_DISABLE 0x08000000
231
232#define K2_FCR1_PCI1_BUS_RESET_N 0x00000010
233#define K2_FCR1_PCI1_SLEEP_RESET_EN 0x00000020
234#define K2_FCR1_I2S0_CELL_ENABLE 0x00000400
235#define K2_FCR1_I2S0_RESET 0x00000800
236#define K2_FCR1_I2S0_CLK_ENABLE_BIT 0x00001000
237#define K2_FCR1_I2S0_ENABLE 0x00002000
238#define K2_FCR1_PCI1_CLK_ENABLE 0x00004000
239#define K2_FCR1_FW_CLK_ENABLE 0x00008000
240#define K2_FCR1_FW_RESET_N 0x00010000
241#define K2_FCR1_I2S1_CELL_ENABLE 0x00020000
242#define K2_FCR1_I2S1_CLK_ENABLE_BIT 0x00080000
243#define K2_FCR1_I2S1_ENABLE 0x00100000
244#define K2_FCR1_GMAC_CLK_ENABLE 0x00400000
245#define K2_FCR1_GMAC_POWER_DOWN 0x00800000
246#define K2_FCR1_GMAC_RESET_N 0x01000000
247#define K2_FCR1_SATA_CLK_ENABLE 0x02000000
248#define K2_FCR1_SATA_POWER_DOWN 0x04000000
249#define K2_FCR1_SATA_RESET_N 0x08000000
250#define K2_FCR1_UATA_CLK_ENABLE 0x10000000
251#define K2_FCR1_UATA_RESET_N 0x40000000
252#define K2_FCR1_UATA_CHOOSE_CLK66 0x80000000
253
254/* Shasta definitions */
255#define SH_FCR1_I2S2_CELL_ENABLE 0x00000010
256#define SH_FCR1_I2S2_CLK_ENABLE_BIT 0x00000040
257#define SH_FCR1_I2S2_ENABLE 0x00000080
258#define SH_FCR3_I2S2_CLK18_ENABLE 0x00008000
259
260#endif /* __KERNEL__ */
261#endif /* _ASM_POWERPC_KEYLARGO_H */
diff --git a/include/asm-powerpc/kgdb.h b/include/asm-powerpc/kgdb.h
deleted file mode 100644
index 1399caf719a..00000000000
--- a/include/asm-powerpc/kgdb.h
+++ /dev/null
@@ -1,65 +0,0 @@
1/*
2 * include/asm-powerpc/kgdb.h
3 *
4 * The PowerPC (32/64) specific defines / externs for KGDB. Based on
5 * the previous 32bit and 64bit specific files, which had the following
6 * copyrights:
7 *
8 * PPC64 Mods (C) 2005 Frank Rowand (frowand@mvista.com)
9 * PPC Mods (C) 2004 Tom Rini (trini@mvista.com)
10 * PPC Mods (C) 2003 John Whitney (john.whitney@timesys.com)
11 * PPC Mods (C) 1998 Michael Tesch (tesch@cs.wisc.edu)
12 *
13 *
14 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
15 * Author: Tom Rini <trini@kernel.crashing.org>
16 *
17 * 2006 (c) MontaVista Software, Inc. This file is licensed under
18 * the terms of the GNU General Public License version 2. This program
19 * is licensed "as is" without any warranty of any kind, whether express
20 * or implied.
21 */
22#ifdef __KERNEL__
23#ifndef __POWERPC_KGDB_H__
24#define __POWERPC_KGDB_H__
25
26#ifndef __ASSEMBLY__
27
28#define BREAK_INSTR_SIZE 4
29#define BUFMAX ((NUMREGBYTES * 2) + 512)
30#define OUTBUFMAX ((NUMREGBYTES * 2) + 512)
31static inline void arch_kgdb_breakpoint(void)
32{
33 asm(".long 0x7d821008"); /* twge r2, r2 */
34}
35#define CACHE_FLUSH_IS_SAFE 1
36
37/* The number bytes of registers we have to save depends on a few
38 * things. For 64bit we default to not including vector registers and
39 * vector state registers. */
40#ifdef CONFIG_PPC64
41/*
42 * 64 bit (8 byte) registers:
43 * 32 gpr, 32 fpr, nip, msr, link, ctr
44 * 32 bit (4 byte) registers:
45 * ccr, xer, fpscr
46 */
47#define NUMREGBYTES ((68 * 8) + (3 * 4))
48#define NUMCRITREGBYTES 184
49#else /* CONFIG_PPC32 */
50/* On non-E500 family PPC32 we determine the size by picking the last
51 * register we need, but on E500 we skip sections so we list what we
52 * need to store, and add it up. */
53#ifndef CONFIG_E500
54#define MAXREG (PT_FPSCR+1)
55#else
56/* 32 GPRs (8 bytes), nip, msr, ccr, link, ctr, xer, acc (8 bytes), spefscr*/
57#define MAXREG ((32*2)+6+2+1)
58#endif
59#define NUMREGBYTES (MAXREG * sizeof(int))
60/* CR/LR, R1, R2, R13-R31 inclusive. */
61#define NUMCRITREGBYTES (23 * sizeof(int))
62#endif /* 32/64 */
63#endif /* !(__ASSEMBLY__) */
64#endif /* !__POWERPC_KGDB_H__ */
65#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/kmap_types.h b/include/asm-powerpc/kmap_types.h
deleted file mode 100644
index b6bac6f61c1..00000000000
--- a/include/asm-powerpc/kmap_types.h
+++ /dev/null
@@ -1,33 +0,0 @@
1#ifndef _ASM_POWERPC_KMAP_TYPES_H
2#define _ASM_POWERPC_KMAP_TYPES_H
3
4#ifdef __KERNEL__
5
6/*
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13enum km_type {
14 KM_BOUNCE_READ,
15 KM_SKB_SUNRPC_DATA,
16 KM_SKB_DATA_SOFTIRQ,
17 KM_USER0,
18 KM_USER1,
19 KM_BIO_SRC_IRQ,
20 KM_BIO_DST_IRQ,
21 KM_PTE0,
22 KM_PTE1,
23 KM_IRQ0,
24 KM_IRQ1,
25 KM_SOFTIRQ0,
26 KM_SOFTIRQ1,
27 KM_PPC_SYNC_PAGE,
28 KM_PPC_SYNC_ICACHE,
29 KM_TYPE_NR
30};
31
32#endif /* __KERNEL__ */
33#endif /* _ASM_POWERPC_KMAP_TYPES_H */
diff --git a/include/asm-powerpc/kprobes.h b/include/asm-powerpc/kprobes.h
deleted file mode 100644
index d0e7701fa1f..00000000000
--- a/include/asm-powerpc/kprobes.h
+++ /dev/null
@@ -1,118 +0,0 @@
1#ifndef _ASM_POWERPC_KPROBES_H
2#define _ASM_POWERPC_KPROBES_H
3#ifdef __KERNEL__
4/*
5 * Kernel Probes (KProbes)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 *
21 * Copyright (C) IBM Corporation, 2002, 2004
22 *
23 * 2002-Oct Created by Vamsi Krishna S <vamsi_krishna@in.ibm.com> Kernel
24 * Probes initial implementation ( includes suggestions from
25 * Rusty Russell).
26 * 2004-Nov Modified for PPC64 by Ananth N Mavinakayanahalli
27 * <ananth@in.ibm.com>
28 */
29#include <linux/types.h>
30#include <linux/ptrace.h>
31#include <linux/percpu.h>
32
33#define __ARCH_WANT_KPROBES_INSN_SLOT
34
35struct pt_regs;
36struct kprobe;
37
38typedef unsigned int kprobe_opcode_t;
39#define BREAKPOINT_INSTRUCTION 0x7fe00008 /* trap */
40#define MAX_INSN_SIZE 1
41
42#define IS_TW(instr) (((instr) & 0xfc0007fe) == 0x7c000008)
43#define IS_TD(instr) (((instr) & 0xfc0007fe) == 0x7c000088)
44#define IS_TDI(instr) (((instr) & 0xfc000000) == 0x08000000)
45#define IS_TWI(instr) (((instr) & 0xfc000000) == 0x0c000000)
46
47#ifdef CONFIG_PPC64
48/*
49 * 64bit powerpc uses function descriptors.
50 * Handle cases where:
51 * - User passes a <.symbol> or <module:.symbol>
52 * - User passes a <symbol> or <module:symbol>
53 * - User passes a non-existant symbol, kallsyms_lookup_name
54 * returns 0. Don't deref the NULL pointer in that case
55 */
56#define kprobe_lookup_name(name, addr) \
57{ \
58 addr = (kprobe_opcode_t *)kallsyms_lookup_name(name); \
59 if (addr) { \
60 char *colon; \
61 if ((colon = strchr(name, ':')) != NULL) { \
62 colon++; \
63 if (*colon != '\0' && *colon != '.') \
64 addr = *(kprobe_opcode_t **)addr; \
65 } else if (name[0] != '.') \
66 addr = *(kprobe_opcode_t **)addr; \
67 } else { \
68 char dot_name[KSYM_NAME_LEN]; \
69 dot_name[0] = '.'; \
70 dot_name[1] = '\0'; \
71 strncat(dot_name, name, KSYM_NAME_LEN - 2); \
72 addr = (kprobe_opcode_t *)kallsyms_lookup_name(dot_name); \
73 } \
74}
75
76#define is_trap(instr) (IS_TW(instr) || IS_TD(instr) || \
77 IS_TWI(instr) || IS_TDI(instr))
78#else
79/* Use stock kprobe_lookup_name since ppc32 doesn't use function descriptors */
80#define is_trap(instr) (IS_TW(instr) || IS_TWI(instr))
81#endif
82
83#define flush_insn_slot(p) do { } while (0)
84#define kretprobe_blacklist_size 0
85
86void kretprobe_trampoline(void);
87extern void arch_remove_kprobe(struct kprobe *p);
88
89/* Architecture specific copy of original instruction */
90struct arch_specific_insn {
91 /* copy of original instruction */
92 kprobe_opcode_t *insn;
93 /*
94 * Set in kprobes code, initially to 0. If the instruction can be
95 * eumulated, this is set to 1, if not, to -1.
96 */
97 int boostable;
98};
99
100struct prev_kprobe {
101 struct kprobe *kp;
102 unsigned long status;
103 unsigned long saved_msr;
104};
105
106/* per-cpu kprobe control block */
107struct kprobe_ctlblk {
108 unsigned long kprobe_status;
109 unsigned long kprobe_saved_msr;
110 struct pt_regs jprobe_saved_regs;
111 struct prev_kprobe prev_kprobe;
112};
113
114extern int kprobe_exceptions_notify(struct notifier_block *self,
115 unsigned long val, void *data);
116extern int kprobe_fault_handler(struct pt_regs *regs, int trapnr);
117#endif /* __KERNEL__ */
118#endif /* _ASM_POWERPC_KPROBES_H */
diff --git a/include/asm-powerpc/kvm.h b/include/asm-powerpc/kvm.h
deleted file mode 100644
index f993e4198d5..00000000000
--- a/include/asm-powerpc/kvm.h
+++ /dev/null
@@ -1,55 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
14 *
15 * Copyright IBM Corp. 2007
16 *
17 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
18 */
19
20#ifndef __LINUX_KVM_POWERPC_H
21#define __LINUX_KVM_POWERPC_H
22
23#include <asm/types.h>
24
25struct kvm_regs {
26 __u64 pc;
27 __u64 cr;
28 __u64 ctr;
29 __u64 lr;
30 __u64 xer;
31 __u64 msr;
32 __u64 srr0;
33 __u64 srr1;
34 __u64 pid;
35
36 __u64 sprg0;
37 __u64 sprg1;
38 __u64 sprg2;
39 __u64 sprg3;
40 __u64 sprg4;
41 __u64 sprg5;
42 __u64 sprg6;
43 __u64 sprg7;
44
45 __u64 gpr[32];
46};
47
48struct kvm_sregs {
49};
50
51struct kvm_fpu {
52 __u64 fpr[32];
53};
54
55#endif /* __LINUX_KVM_POWERPC_H */
diff --git a/include/asm-powerpc/kvm_asm.h b/include/asm-powerpc/kvm_asm.h
deleted file mode 100644
index 2197764796d..00000000000
--- a/include/asm-powerpc/kvm_asm.h
+++ /dev/null
@@ -1,55 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
14 *
15 * Copyright IBM Corp. 2008
16 *
17 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
18 */
19
20#ifndef __POWERPC_KVM_ASM_H__
21#define __POWERPC_KVM_ASM_H__
22
23/* IVPR must be 64KiB-aligned. */
24#define VCPU_SIZE_ORDER 4
25#define VCPU_SIZE_LOG (VCPU_SIZE_ORDER + 12)
26#define VCPU_TLB_PGSZ PPC44x_TLB_64K
27#define VCPU_SIZE_BYTES (1<<VCPU_SIZE_LOG)
28
29#define BOOKE_INTERRUPT_CRITICAL 0
30#define BOOKE_INTERRUPT_MACHINE_CHECK 1
31#define BOOKE_INTERRUPT_DATA_STORAGE 2
32#define BOOKE_INTERRUPT_INST_STORAGE 3
33#define BOOKE_INTERRUPT_EXTERNAL 4
34#define BOOKE_INTERRUPT_ALIGNMENT 5
35#define BOOKE_INTERRUPT_PROGRAM 6
36#define BOOKE_INTERRUPT_FP_UNAVAIL 7
37#define BOOKE_INTERRUPT_SYSCALL 8
38#define BOOKE_INTERRUPT_AP_UNAVAIL 9
39#define BOOKE_INTERRUPT_DECREMENTER 10
40#define BOOKE_INTERRUPT_FIT 11
41#define BOOKE_INTERRUPT_WATCHDOG 12
42#define BOOKE_INTERRUPT_DTLB_MISS 13
43#define BOOKE_INTERRUPT_ITLB_MISS 14
44#define BOOKE_INTERRUPT_DEBUG 15
45#define BOOKE_MAX_INTERRUPT 15
46
47#define RESUME_FLAG_NV (1<<0) /* Reload guest nonvolatile state? */
48#define RESUME_FLAG_HOST (1<<1) /* Resume host? */
49
50#define RESUME_GUEST 0
51#define RESUME_GUEST_NV RESUME_FLAG_NV
52#define RESUME_HOST RESUME_FLAG_HOST
53#define RESUME_HOST_NV (RESUME_FLAG_HOST|RESUME_FLAG_NV)
54
55#endif /* __POWERPC_KVM_ASM_H__ */
diff --git a/include/asm-powerpc/kvm_host.h b/include/asm-powerpc/kvm_host.h
deleted file mode 100644
index 2655e2a4831..00000000000
--- a/include/asm-powerpc/kvm_host.h
+++ /dev/null
@@ -1,155 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
14 *
15 * Copyright IBM Corp. 2007
16 *
17 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
18 */
19
20#ifndef __POWERPC_KVM_HOST_H__
21#define __POWERPC_KVM_HOST_H__
22
23#include <linux/mutex.h>
24#include <linux/timer.h>
25#include <linux/types.h>
26#include <linux/kvm_types.h>
27#include <asm/kvm_asm.h>
28
29#define KVM_MAX_VCPUS 1
30#define KVM_MEMORY_SLOTS 32
31/* memory slots that does not exposed to userspace */
32#define KVM_PRIVATE_MEM_SLOTS 4
33
34#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
35
36/* We don't currently support large pages. */
37#define KVM_PAGES_PER_HPAGE (1<<31)
38
39struct kvm;
40struct kvm_run;
41struct kvm_vcpu;
42
43struct kvm_vm_stat {
44 u32 remote_tlb_flush;
45};
46
47struct kvm_vcpu_stat {
48 u32 sum_exits;
49 u32 mmio_exits;
50 u32 dcr_exits;
51 u32 signal_exits;
52 u32 light_exits;
53 /* Account for special types of light exits: */
54 u32 itlb_real_miss_exits;
55 u32 itlb_virt_miss_exits;
56 u32 dtlb_real_miss_exits;
57 u32 dtlb_virt_miss_exits;
58 u32 syscall_exits;
59 u32 isi_exits;
60 u32 dsi_exits;
61 u32 emulated_inst_exits;
62 u32 dec_exits;
63 u32 ext_intr_exits;
64 u32 halt_wakeup;
65};
66
67struct tlbe {
68 u32 tid; /* Only the low 8 bits are used. */
69 u32 word0;
70 u32 word1;
71 u32 word2;
72};
73
74struct kvm_arch {
75};
76
77struct kvm_vcpu_arch {
78 /* Unmodified copy of the guest's TLB. */
79 struct tlbe guest_tlb[PPC44x_TLB_SIZE];
80 /* TLB that's actually used when the guest is running. */
81 struct tlbe shadow_tlb[PPC44x_TLB_SIZE];
82 /* Pages which are referenced in the shadow TLB. */
83 struct page *shadow_pages[PPC44x_TLB_SIZE];
84 /* Copy of the host's TLB. */
85 struct tlbe host_tlb[PPC44x_TLB_SIZE];
86
87 u32 host_stack;
88 u32 host_pid;
89
90 u64 fpr[32];
91 u32 gpr[32];
92
93 u32 pc;
94 u32 cr;
95 u32 ctr;
96 u32 lr;
97 u32 xer;
98
99 u32 msr;
100 u32 mmucr;
101 u32 sprg0;
102 u32 sprg1;
103 u32 sprg2;
104 u32 sprg3;
105 u32 sprg4;
106 u32 sprg5;
107 u32 sprg6;
108 u32 sprg7;
109 u32 srr0;
110 u32 srr1;
111 u32 csrr0;
112 u32 csrr1;
113 u32 dsrr0;
114 u32 dsrr1;
115 u32 dear;
116 u32 esr;
117 u32 dec;
118 u32 decar;
119 u32 tbl;
120 u32 tbu;
121 u32 tcr;
122 u32 tsr;
123 u32 ivor[16];
124 u32 ivpr;
125 u32 pir;
126 u32 pid;
127 u32 pvr;
128 u32 ccr0;
129 u32 ccr1;
130 u32 dbcr0;
131 u32 dbcr1;
132
133 u32 last_inst;
134 u32 fault_dear;
135 u32 fault_esr;
136 gpa_t paddr_accessed;
137
138 u8 io_gpr; /* GPR used as IO source/target */
139 u8 mmio_is_bigendian;
140 u8 dcr_needed;
141 u8 dcr_is_write;
142
143 u32 cpr0_cfgaddr; /* holds the last set cpr0_cfgaddr */
144
145 struct timer_list dec_timer;
146 unsigned long pending_exceptions;
147};
148
149struct kvm_guest_debug {
150 int enabled;
151 unsigned long bp[4];
152 int singlestep;
153};
154
155#endif /* __POWERPC_KVM_HOST_H__ */
diff --git a/include/asm-powerpc/kvm_para.h b/include/asm-powerpc/kvm_para.h
deleted file mode 100644
index 2d48f6a63d0..00000000000
--- a/include/asm-powerpc/kvm_para.h
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
14 *
15 * Copyright IBM Corp. 2008
16 *
17 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
18 */
19
20#ifndef __POWERPC_KVM_PARA_H__
21#define __POWERPC_KVM_PARA_H__
22
23#ifdef __KERNEL__
24
25static inline int kvm_para_available(void)
26{
27 return 0;
28}
29
30static inline unsigned int kvm_arch_para_features(void)
31{
32 return 0;
33}
34
35#endif /* __KERNEL__ */
36
37#endif /* __POWERPC_KVM_PARA_H__ */
diff --git a/include/asm-powerpc/kvm_ppc.h b/include/asm-powerpc/kvm_ppc.h
deleted file mode 100644
index a8b06879226..00000000000
--- a/include/asm-powerpc/kvm_ppc.h
+++ /dev/null
@@ -1,95 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
14 *
15 * Copyright IBM Corp. 2008
16 *
17 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
18 */
19
20#ifndef __POWERPC_KVM_PPC_H__
21#define __POWERPC_KVM_PPC_H__
22
23/* This file exists just so we can dereference kvm_vcpu, avoiding nested header
24 * dependencies. */
25
26#include <linux/mutex.h>
27#include <linux/timer.h>
28#include <linux/types.h>
29#include <linux/kvm_types.h>
30#include <linux/kvm_host.h>
31
32struct kvm_tlb {
33 struct tlbe guest_tlb[PPC44x_TLB_SIZE];
34 struct tlbe shadow_tlb[PPC44x_TLB_SIZE];
35};
36
37enum emulation_result {
38 EMULATE_DONE, /* no further processing */
39 EMULATE_DO_MMIO, /* kvm_run filled with MMIO request */
40 EMULATE_DO_DCR, /* kvm_run filled with DCR request */
41 EMULATE_FAIL, /* can't emulate this instruction */
42};
43
44extern const unsigned char exception_priority[];
45extern const unsigned char priority_exception[];
46
47extern int __kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu);
48extern char kvmppc_handlers_start[];
49extern unsigned long kvmppc_handler_len;
50
51extern void kvmppc_dump_vcpu(struct kvm_vcpu *vcpu);
52extern int kvmppc_handle_load(struct kvm_run *run, struct kvm_vcpu *vcpu,
53 unsigned int rt, unsigned int bytes,
54 int is_bigendian);
55extern int kvmppc_handle_store(struct kvm_run *run, struct kvm_vcpu *vcpu,
56 u32 val, unsigned int bytes, int is_bigendian);
57
58extern int kvmppc_emulate_instruction(struct kvm_run *run,
59 struct kvm_vcpu *vcpu);
60extern int kvmppc_emulate_mmio(struct kvm_run *run, struct kvm_vcpu *vcpu);
61
62extern void kvmppc_mmu_map(struct kvm_vcpu *vcpu, u64 gvaddr, gfn_t gfn,
63 u64 asid, u32 flags);
64extern void kvmppc_mmu_invalidate(struct kvm_vcpu *vcpu, gva_t eaddr,
65 gva_t eend, u32 asid);
66extern void kvmppc_mmu_priv_switch(struct kvm_vcpu *vcpu, int usermode);
67
68extern void kvmppc_check_and_deliver_interrupts(struct kvm_vcpu *vcpu);
69
70static inline void kvmppc_queue_exception(struct kvm_vcpu *vcpu, int exception)
71{
72 unsigned int priority = exception_priority[exception];
73 set_bit(priority, &vcpu->arch.pending_exceptions);
74}
75
76static inline void kvmppc_clear_exception(struct kvm_vcpu *vcpu, int exception)
77{
78 unsigned int priority = exception_priority[exception];
79 clear_bit(priority, &vcpu->arch.pending_exceptions);
80}
81
82/* Helper function for "full" MSR writes. No need to call this if only EE is
83 * changing. */
84static inline void kvmppc_set_msr(struct kvm_vcpu *vcpu, u32 new_msr)
85{
86 if ((new_msr & MSR_PR) != (vcpu->arch.msr & MSR_PR))
87 kvmppc_mmu_priv_switch(vcpu, new_msr & MSR_PR);
88
89 vcpu->arch.msr = new_msr;
90
91 if (vcpu->arch.msr & MSR_WE)
92 kvm_vcpu_block(vcpu);
93}
94
95#endif /* __POWERPC_KVM_PPC_H__ */
diff --git a/include/asm-powerpc/libata-portmap.h b/include/asm-powerpc/libata-portmap.h
deleted file mode 100644
index 4d8518049f4..00000000000
--- a/include/asm-powerpc/libata-portmap.h
+++ /dev/null
@@ -1,12 +0,0 @@
1#ifndef __ASM_POWERPC_LIBATA_PORTMAP_H
2#define __ASM_POWERPC_LIBATA_PORTMAP_H
3
4#define ATA_PRIMARY_CMD 0x1F0
5#define ATA_PRIMARY_CTL 0x3F6
6#define ATA_PRIMARY_IRQ(dev) pci_get_legacy_ide_irq(dev, 0)
7
8#define ATA_SECONDARY_CMD 0x170
9#define ATA_SECONDARY_CTL 0x376
10#define ATA_SECONDARY_IRQ(dev) pci_get_legacy_ide_irq(dev, 1)
11
12#endif
diff --git a/include/asm-powerpc/linkage.h b/include/asm-powerpc/linkage.h
deleted file mode 100644
index e1c4ac1cc4b..00000000000
--- a/include/asm-powerpc/linkage.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _ASM_POWERPC_LINKAGE_H
2#define _ASM_POWERPC_LINKAGE_H
3
4/* Nothing to see here... */
5
6#endif /* _ASM_POWERPC_LINKAGE_H */
diff --git a/include/asm-powerpc/lmb.h b/include/asm-powerpc/lmb.h
deleted file mode 100644
index 6f5fdf0a19a..00000000000
--- a/include/asm-powerpc/lmb.h
+++ /dev/null
@@ -1,15 +0,0 @@
1#ifndef _ASM_POWERPC_LMB_H
2#define _ASM_POWERPC_LMB_H
3
4#include <asm/udbg.h>
5
6#define LMB_DBG(fmt...) udbg_printf(fmt)
7
8#ifdef CONFIG_PPC32
9extern phys_addr_t lowmem_end_addr;
10#define LMB_REAL_LIMIT lowmem_end_addr
11#else
12#define LMB_REAL_LIMIT 0
13#endif
14
15#endif /* _ASM_POWERPC_LMB_H */
diff --git a/include/asm-powerpc/local.h b/include/asm-powerpc/local.h
deleted file mode 100644
index 612d8327665..00000000000
--- a/include/asm-powerpc/local.h
+++ /dev/null
@@ -1,200 +0,0 @@
1#ifndef _ARCH_POWERPC_LOCAL_H
2#define _ARCH_POWERPC_LOCAL_H
3
4#include <linux/percpu.h>
5#include <asm/atomic.h>
6
7typedef struct
8{
9 atomic_long_t a;
10} local_t;
11
12#define LOCAL_INIT(i) { ATOMIC_LONG_INIT(i) }
13
14#define local_read(l) atomic_long_read(&(l)->a)
15#define local_set(l,i) atomic_long_set(&(l)->a, (i))
16
17#define local_add(i,l) atomic_long_add((i),(&(l)->a))
18#define local_sub(i,l) atomic_long_sub((i),(&(l)->a))
19#define local_inc(l) atomic_long_inc(&(l)->a)
20#define local_dec(l) atomic_long_dec(&(l)->a)
21
22static __inline__ long local_add_return(long a, local_t *l)
23{
24 long t;
25
26 __asm__ __volatile__(
27"1:" PPC_LLARX "%0,0,%2 # local_add_return\n\
28 add %0,%1,%0\n"
29 PPC405_ERR77(0,%2)
30 PPC_STLCX "%0,0,%2 \n\
31 bne- 1b"
32 : "=&r" (t)
33 : "r" (a), "r" (&(l->a.counter))
34 : "cc", "memory");
35
36 return t;
37}
38
39#define local_add_negative(a, l) (local_add_return((a), (l)) < 0)
40
41static __inline__ long local_sub_return(long a, local_t *l)
42{
43 long t;
44
45 __asm__ __volatile__(
46"1:" PPC_LLARX "%0,0,%2 # local_sub_return\n\
47 subf %0,%1,%0\n"
48 PPC405_ERR77(0,%2)
49 PPC_STLCX "%0,0,%2 \n\
50 bne- 1b"
51 : "=&r" (t)
52 : "r" (a), "r" (&(l->a.counter))
53 : "cc", "memory");
54
55 return t;
56}
57
58static __inline__ long local_inc_return(local_t *l)
59{
60 long t;
61
62 __asm__ __volatile__(
63"1:" PPC_LLARX "%0,0,%1 # local_inc_return\n\
64 addic %0,%0,1\n"
65 PPC405_ERR77(0,%1)
66 PPC_STLCX "%0,0,%1 \n\
67 bne- 1b"
68 : "=&r" (t)
69 : "r" (&(l->a.counter))
70 : "cc", "memory");
71
72 return t;
73}
74
75/*
76 * local_inc_and_test - increment and test
77 * @l: pointer of type local_t
78 *
79 * Atomically increments @l by 1
80 * and returns true if the result is zero, or false for all
81 * other cases.
82 */
83#define local_inc_and_test(l) (local_inc_return(l) == 0)
84
85static __inline__ long local_dec_return(local_t *l)
86{
87 long t;
88
89 __asm__ __volatile__(
90"1:" PPC_LLARX "%0,0,%1 # local_dec_return\n\
91 addic %0,%0,-1\n"
92 PPC405_ERR77(0,%1)
93 PPC_STLCX "%0,0,%1\n\
94 bne- 1b"
95 : "=&r" (t)
96 : "r" (&(l->a.counter))
97 : "cc", "memory");
98
99 return t;
100}
101
102#define local_cmpxchg(l, o, n) \
103 (cmpxchg_local(&((l)->a.counter), (o), (n)))
104#define local_xchg(l, n) (xchg_local(&((l)->a.counter), (n)))
105
106/**
107 * local_add_unless - add unless the number is a given value
108 * @l: pointer of type local_t
109 * @a: the amount to add to v...
110 * @u: ...unless v is equal to u.
111 *
112 * Atomically adds @a to @l, so long as it was not @u.
113 * Returns non-zero if @l was not @u, and zero otherwise.
114 */
115static __inline__ int local_add_unless(local_t *l, long a, long u)
116{
117 long t;
118
119 __asm__ __volatile__ (
120"1:" PPC_LLARX "%0,0,%1 # local_add_unless\n\
121 cmpw 0,%0,%3 \n\
122 beq- 2f \n\
123 add %0,%2,%0 \n"
124 PPC405_ERR77(0,%2)
125 PPC_STLCX "%0,0,%1 \n\
126 bne- 1b \n"
127" subf %0,%2,%0 \n\
1282:"
129 : "=&r" (t)
130 : "r" (&(l->a.counter)), "r" (a), "r" (u)
131 : "cc", "memory");
132
133 return t != u;
134}
135
136#define local_inc_not_zero(l) local_add_unless((l), 1, 0)
137
138#define local_sub_and_test(a, l) (local_sub_return((a), (l)) == 0)
139#define local_dec_and_test(l) (local_dec_return((l)) == 0)
140
141/*
142 * Atomically test *l and decrement if it is greater than 0.
143 * The function returns the old value of *l minus 1.
144 */
145static __inline__ long local_dec_if_positive(local_t *l)
146{
147 long t;
148
149 __asm__ __volatile__(
150"1:" PPC_LLARX "%0,0,%1 # local_dec_if_positive\n\
151 cmpwi %0,1\n\
152 addi %0,%0,-1\n\
153 blt- 2f\n"
154 PPC405_ERR77(0,%1)
155 PPC_STLCX "%0,0,%1\n\
156 bne- 1b"
157 "\n\
1582:" : "=&b" (t)
159 : "r" (&(l->a.counter))
160 : "cc", "memory");
161
162 return t;
163}
164
165/* Use these for per-cpu local_t variables: on some archs they are
166 * much more efficient than these naive implementations. Note they take
167 * a variable, not an address.
168 */
169
170#define __local_inc(l) ((l)->a.counter++)
171#define __local_dec(l) ((l)->a.counter++)
172#define __local_add(i,l) ((l)->a.counter+=(i))
173#define __local_sub(i,l) ((l)->a.counter-=(i))
174
175/* Need to disable preemption for the cpu local counters otherwise we could
176 still access a variable of a previous CPU in a non atomic way. */
177#define cpu_local_wrap_v(l) \
178 ({ local_t res__; \
179 preempt_disable(); \
180 res__ = (l); \
181 preempt_enable(); \
182 res__; })
183#define cpu_local_wrap(l) \
184 ({ preempt_disable(); \
185 l; \
186 preempt_enable(); }) \
187
188#define cpu_local_read(l) cpu_local_wrap_v(local_read(&__get_cpu_var(l)))
189#define cpu_local_set(l, i) cpu_local_wrap(local_set(&__get_cpu_var(l), (i)))
190#define cpu_local_inc(l) cpu_local_wrap(local_inc(&__get_cpu_var(l)))
191#define cpu_local_dec(l) cpu_local_wrap(local_dec(&__get_cpu_var(l)))
192#define cpu_local_add(i, l) cpu_local_wrap(local_add((i), &__get_cpu_var(l)))
193#define cpu_local_sub(i, l) cpu_local_wrap(local_sub((i), &__get_cpu_var(l)))
194
195#define __cpu_local_inc(l) cpu_local_inc(l)
196#define __cpu_local_dec(l) cpu_local_dec(l)
197#define __cpu_local_add(i, l) cpu_local_add((i), (l))
198#define __cpu_local_sub(i, l) cpu_local_sub((i), (l))
199
200#endif /* _ARCH_POWERPC_LOCAL_H */
diff --git a/include/asm-powerpc/lppaca.h b/include/asm-powerpc/lppaca.h
deleted file mode 100644
index 2fe268b1033..00000000000
--- a/include/asm-powerpc/lppaca.h
+++ /dev/null
@@ -1,159 +0,0 @@
1/*
2 * lppaca.h
3 * Copyright (C) 2001 Mike Corrigan IBM Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#ifndef _ASM_POWERPC_LPPACA_H
20#define _ASM_POWERPC_LPPACA_H
21#ifdef __KERNEL__
22
23//=============================================================================
24//
25// This control block contains the data that is shared between the
26// hypervisor (PLIC) and the OS.
27//
28//
29//----------------------------------------------------------------------------
30#include <linux/cache.h>
31#include <asm/types.h>
32#include <asm/mmu.h>
33
34/* The Hypervisor barfs if the lppaca crosses a page boundary. A 1k
35 * alignment is sufficient to prevent this */
36struct lppaca {
37//=============================================================================
38// CACHE_LINE_1 0x0000 - 0x007F Contains read-only data
39// NOTE: The xDynXyz fields are fields that will be dynamically changed by
40// PLIC when preparing to bring a processor online or when dispatching a
41// virtual processor!
42//=============================================================================
43 u32 desc; // Eye catcher 0xD397D781 x00-x03
44 u16 size; // Size of this struct x04-x05
45 u16 reserved1; // Reserved x06-x07
46 u16 reserved2:14; // Reserved x08-x09
47 u8 shared_proc:1; // Shared processor indicator ...
48 u8 secondary_thread:1; // Secondary thread indicator ...
49 volatile u8 dyn_proc_status:8; // Dynamic Status of this proc x0A-x0A
50 u8 secondary_thread_count; // Secondary thread count x0B-x0B
51 volatile u16 dyn_hv_phys_proc_index;// Dynamic HV Physical Proc Index0C-x0D
52 volatile u16 dyn_hv_log_proc_index;// Dynamic HV Logical Proc Indexx0E-x0F
53 u32 decr_val; // Value for Decr programming x10-x13
54 u32 pmc_val; // Value for PMC regs x14-x17
55 volatile u32 dyn_hw_node_id; // Dynamic Hardware Node id x18-x1B
56 volatile u32 dyn_hw_proc_id; // Dynamic Hardware Proc Id x1C-x1F
57 volatile u32 dyn_pir; // Dynamic ProcIdReg value x20-x23
58 u32 dsei_data; // DSEI data x24-x27
59 u64 sprg3; // SPRG3 value x28-x2F
60 u8 reserved3[80]; // Reserved x30-x7F
61
62//=============================================================================
63// CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data
64//=============================================================================
65 // This Dword contains a byte for each type of interrupt that can occur.
66 // The IPI is a count while the others are just a binary 1 or 0.
67 union {
68 u64 any_int;
69 struct {
70 u16 reserved; // Reserved - cleared by #mpasmbl
71 u8 xirr_int; // Indicates xXirrValue is valid or Immed IO
72 u8 ipi_cnt; // IPI Count
73 u8 decr_int; // DECR interrupt occurred
74 u8 pdc_int; // PDC interrupt occurred
75 u8 quantum_int; // Interrupt quantum reached
76 u8 old_plic_deferred_ext_int; // Old PLIC has a deferred XIRR pending
77 } fields;
78 } int_dword;
79
80 // Whenever any fields in this Dword are set then PLIC will defer the
81 // processing of external interrupts. Note that PLIC will store the
82 // XIRR directly into the xXirrValue field so that another XIRR will
83 // not be presented until this one clears. The layout of the low
84 // 4-bytes of this Dword is upto SLIC - PLIC just checks whether the
85 // entire Dword is zero or not. A non-zero value in the low order
86 // 2-bytes will result in SLIC being granted the highest thread
87 // priority upon return. A 0 will return to SLIC as medium priority.
88 u64 plic_defer_ints_area; // Entire Dword
89
90 // Used to pass the real SRR0/1 from PLIC to SLIC as well as to
91 // pass the target SRR0/1 from SLIC to PLIC on a SetAsrAndRfid.
92 u64 saved_srr0; // Saved SRR0 x10-x17
93 u64 saved_srr1; // Saved SRR1 x18-x1F
94
95 // Used to pass parms from the OS to PLIC for SetAsrAndRfid
96 u64 saved_gpr3; // Saved GPR3 x20-x27
97 u64 saved_gpr4; // Saved GPR4 x28-x2F
98 u64 saved_gpr5; // Saved GPR5 x30-x37
99
100 u8 reserved4; // Reserved x38-x38
101 u8 donate_dedicated_cpu; // Donate dedicated CPU cycles x39-x39
102 u8 fpregs_in_use; // FP regs in use x3A-x3A
103 u8 pmcregs_in_use; // PMC regs in use x3B-x3B
104 volatile u32 saved_decr; // Saved Decr Value x3C-x3F
105 volatile u64 emulated_time_base;// Emulated TB for this thread x40-x47
106 volatile u64 cur_plic_latency; // Unaccounted PLIC latency x48-x4F
107 u64 tot_plic_latency; // Accumulated PLIC latency x50-x57
108 u64 wait_state_cycles; // Wait cycles for this proc x58-x5F
109 u64 end_of_quantum; // TB at end of quantum x60-x67
110 u64 pdc_saved_sprg1; // Saved SPRG1 for PMC int x68-x6F
111 u64 pdc_saved_srr0; // Saved SRR0 for PMC int x70-x77
112 volatile u32 virtual_decr; // Virtual DECR for shared procsx78-x7B
113 u16 slb_count; // # of SLBs to maintain x7C-x7D
114 u8 idle; // Indicate OS is idle x7E
115 u8 vmxregs_in_use; // VMX registers in use x7F
116
117
118//=============================================================================
119// CACHE_LINE_3 0x0100 - 0x017F: This line is shared with other processors
120//=============================================================================
121 // This is the yield_count. An "odd" value (low bit on) means that
122 // the processor is yielded (either because of an OS yield or a PLIC
123 // preempt). An even value implies that the processor is currently
124 // executing.
125 // NOTE: This value will ALWAYS be zero for dedicated processors and
126 // will NEVER be zero for shared processors (ie, initialized to a 1).
127 volatile u32 yield_count; // PLIC increments each dispatchx00-x03
128 u32 reserved6;
129 volatile u64 cmo_faults; // CMO page fault count x08-x0F
130 volatile u64 cmo_fault_time; // CMO page fault time x10-x17
131 u8 reserved7[104]; // Reserved x18-x7F
132
133//=============================================================================
134// CACHE_LINE_4-5 0x0180 - 0x027F Contains PMC interrupt data
135//=============================================================================
136 u8 pmc_save_area[256]; // PMC interrupt Area x00-xFF
137} __attribute__((__aligned__(0x400)));
138
139extern struct lppaca lppaca[];
140
141/*
142 * SLB shadow buffer structure as defined in the PAPR. The save_area
143 * contains adjacent ESID and VSID pairs for each shadowed SLB. The
144 * ESID is stored in the lower 64bits, then the VSID.
145 */
146struct slb_shadow {
147 u32 persistent; // Number of persistent SLBs x00-x03
148 u32 buffer_length; // Total shadow buffer length x04-x07
149 u64 reserved; // Alignment x08-x0f
150 struct {
151 u64 esid;
152 u64 vsid;
153 } save_area[SLB_NUM_BOLTED]; // x10-x40
154} ____cacheline_aligned;
155
156extern struct slb_shadow slb_shadow[];
157
158#endif /* __KERNEL__ */
159#endif /* _ASM_POWERPC_LPPACA_H */
diff --git a/include/asm-powerpc/lv1call.h b/include/asm-powerpc/lv1call.h
deleted file mode 100644
index 81713acf752..00000000000
--- a/include/asm-powerpc/lv1call.h
+++ /dev/null
@@ -1,348 +0,0 @@
1/*
2 * PS3 hvcall interface.
3 *
4 * Copyright (C) 2006 Sony Computer Entertainment Inc.
5 * Copyright 2006 Sony Corp.
6 * Copyright 2003, 2004 (c) MontaVista Software, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#if !defined(_ASM_POWERPC_LV1CALL_H)
23#define _ASM_POWERPC_LV1CALL_H
24
25#if !defined(__ASSEMBLY__)
26
27#include <linux/types.h>
28
29/* lv1 call declaration macros */
30
31#define LV1_1_IN_ARG_DECL u64 in_1
32#define LV1_2_IN_ARG_DECL LV1_1_IN_ARG_DECL, u64 in_2
33#define LV1_3_IN_ARG_DECL LV1_2_IN_ARG_DECL, u64 in_3
34#define LV1_4_IN_ARG_DECL LV1_3_IN_ARG_DECL, u64 in_4
35#define LV1_5_IN_ARG_DECL LV1_4_IN_ARG_DECL, u64 in_5
36#define LV1_6_IN_ARG_DECL LV1_5_IN_ARG_DECL, u64 in_6
37#define LV1_7_IN_ARG_DECL LV1_6_IN_ARG_DECL, u64 in_7
38#define LV1_8_IN_ARG_DECL LV1_7_IN_ARG_DECL, u64 in_8
39#define LV1_1_OUT_ARG_DECL u64 *out_1
40#define LV1_2_OUT_ARG_DECL LV1_1_OUT_ARG_DECL, u64 *out_2
41#define LV1_3_OUT_ARG_DECL LV1_2_OUT_ARG_DECL, u64 *out_3
42#define LV1_4_OUT_ARG_DECL LV1_3_OUT_ARG_DECL, u64 *out_4
43#define LV1_5_OUT_ARG_DECL LV1_4_OUT_ARG_DECL, u64 *out_5
44#define LV1_6_OUT_ARG_DECL LV1_5_OUT_ARG_DECL, u64 *out_6
45#define LV1_7_OUT_ARG_DECL LV1_6_OUT_ARG_DECL, u64 *out_7
46
47#define LV1_0_IN_0_OUT_ARG_DECL void
48#define LV1_1_IN_0_OUT_ARG_DECL LV1_1_IN_ARG_DECL
49#define LV1_2_IN_0_OUT_ARG_DECL LV1_2_IN_ARG_DECL
50#define LV1_3_IN_0_OUT_ARG_DECL LV1_3_IN_ARG_DECL
51#define LV1_4_IN_0_OUT_ARG_DECL LV1_4_IN_ARG_DECL
52#define LV1_5_IN_0_OUT_ARG_DECL LV1_5_IN_ARG_DECL
53#define LV1_6_IN_0_OUT_ARG_DECL LV1_6_IN_ARG_DECL
54#define LV1_7_IN_0_OUT_ARG_DECL LV1_7_IN_ARG_DECL
55
56#define LV1_0_IN_1_OUT_ARG_DECL LV1_1_OUT_ARG_DECL
57#define LV1_1_IN_1_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
58#define LV1_2_IN_1_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
59#define LV1_3_IN_1_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
60#define LV1_4_IN_1_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
61#define LV1_5_IN_1_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
62#define LV1_6_IN_1_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
63#define LV1_7_IN_1_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
64#define LV1_8_IN_1_OUT_ARG_DECL LV1_8_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
65
66#define LV1_0_IN_2_OUT_ARG_DECL LV1_2_OUT_ARG_DECL
67#define LV1_1_IN_2_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
68#define LV1_2_IN_2_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
69#define LV1_3_IN_2_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
70#define LV1_4_IN_2_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
71#define LV1_5_IN_2_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
72#define LV1_6_IN_2_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
73#define LV1_7_IN_2_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
74
75#define LV1_0_IN_3_OUT_ARG_DECL LV1_3_OUT_ARG_DECL
76#define LV1_1_IN_3_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
77#define LV1_2_IN_3_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
78#define LV1_3_IN_3_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
79#define LV1_4_IN_3_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
80#define LV1_5_IN_3_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
81#define LV1_6_IN_3_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
82#define LV1_7_IN_3_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
83
84#define LV1_0_IN_4_OUT_ARG_DECL LV1_4_OUT_ARG_DECL
85#define LV1_1_IN_4_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
86#define LV1_2_IN_4_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
87#define LV1_3_IN_4_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
88#define LV1_4_IN_4_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
89#define LV1_5_IN_4_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
90#define LV1_6_IN_4_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
91#define LV1_7_IN_4_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
92
93#define LV1_0_IN_5_OUT_ARG_DECL LV1_5_OUT_ARG_DECL
94#define LV1_1_IN_5_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
95#define LV1_2_IN_5_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
96#define LV1_3_IN_5_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
97#define LV1_4_IN_5_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
98#define LV1_5_IN_5_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
99#define LV1_6_IN_5_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
100#define LV1_7_IN_5_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
101
102#define LV1_0_IN_6_OUT_ARG_DECL LV1_6_OUT_ARG_DECL
103#define LV1_1_IN_6_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
104#define LV1_2_IN_6_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
105#define LV1_3_IN_6_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
106#define LV1_4_IN_6_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
107#define LV1_5_IN_6_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
108#define LV1_6_IN_6_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
109#define LV1_7_IN_6_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
110
111#define LV1_0_IN_7_OUT_ARG_DECL LV1_7_OUT_ARG_DECL
112#define LV1_1_IN_7_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
113#define LV1_2_IN_7_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
114#define LV1_3_IN_7_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
115#define LV1_4_IN_7_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
116#define LV1_5_IN_7_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
117#define LV1_6_IN_7_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
118#define LV1_7_IN_7_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
119
120#define LV1_1_IN_ARGS in_1
121#define LV1_2_IN_ARGS LV1_1_IN_ARGS, in_2
122#define LV1_3_IN_ARGS LV1_2_IN_ARGS, in_3
123#define LV1_4_IN_ARGS LV1_3_IN_ARGS, in_4
124#define LV1_5_IN_ARGS LV1_4_IN_ARGS, in_5
125#define LV1_6_IN_ARGS LV1_5_IN_ARGS, in_6
126#define LV1_7_IN_ARGS LV1_6_IN_ARGS, in_7
127#define LV1_8_IN_ARGS LV1_7_IN_ARGS, in_8
128
129#define LV1_1_OUT_ARGS out_1
130#define LV1_2_OUT_ARGS LV1_1_OUT_ARGS, out_2
131#define LV1_3_OUT_ARGS LV1_2_OUT_ARGS, out_3
132#define LV1_4_OUT_ARGS LV1_3_OUT_ARGS, out_4
133#define LV1_5_OUT_ARGS LV1_4_OUT_ARGS, out_5
134#define LV1_6_OUT_ARGS LV1_5_OUT_ARGS, out_6
135#define LV1_7_OUT_ARGS LV1_6_OUT_ARGS, out_7
136
137#define LV1_0_IN_0_OUT_ARGS
138#define LV1_1_IN_0_OUT_ARGS LV1_1_IN_ARGS
139#define LV1_2_IN_0_OUT_ARGS LV1_2_IN_ARGS
140#define LV1_3_IN_0_OUT_ARGS LV1_3_IN_ARGS
141#define LV1_4_IN_0_OUT_ARGS LV1_4_IN_ARGS
142#define LV1_5_IN_0_OUT_ARGS LV1_5_IN_ARGS
143#define LV1_6_IN_0_OUT_ARGS LV1_6_IN_ARGS
144#define LV1_7_IN_0_OUT_ARGS LV1_7_IN_ARGS
145
146#define LV1_0_IN_1_OUT_ARGS LV1_1_OUT_ARGS
147#define LV1_1_IN_1_OUT_ARGS LV1_1_IN_ARGS, LV1_1_OUT_ARGS
148#define LV1_2_IN_1_OUT_ARGS LV1_2_IN_ARGS, LV1_1_OUT_ARGS
149#define LV1_3_IN_1_OUT_ARGS LV1_3_IN_ARGS, LV1_1_OUT_ARGS
150#define LV1_4_IN_1_OUT_ARGS LV1_4_IN_ARGS, LV1_1_OUT_ARGS
151#define LV1_5_IN_1_OUT_ARGS LV1_5_IN_ARGS, LV1_1_OUT_ARGS
152#define LV1_6_IN_1_OUT_ARGS LV1_6_IN_ARGS, LV1_1_OUT_ARGS
153#define LV1_7_IN_1_OUT_ARGS LV1_7_IN_ARGS, LV1_1_OUT_ARGS
154#define LV1_8_IN_1_OUT_ARGS LV1_8_IN_ARGS, LV1_1_OUT_ARGS
155
156#define LV1_0_IN_2_OUT_ARGS LV1_2_OUT_ARGS
157#define LV1_1_IN_2_OUT_ARGS LV1_1_IN_ARGS, LV1_2_OUT_ARGS
158#define LV1_2_IN_2_OUT_ARGS LV1_2_IN_ARGS, LV1_2_OUT_ARGS
159#define LV1_3_IN_2_OUT_ARGS LV1_3_IN_ARGS, LV1_2_OUT_ARGS
160#define LV1_4_IN_2_OUT_ARGS LV1_4_IN_ARGS, LV1_2_OUT_ARGS
161#define LV1_5_IN_2_OUT_ARGS LV1_5_IN_ARGS, LV1_2_OUT_ARGS
162#define LV1_6_IN_2_OUT_ARGS LV1_6_IN_ARGS, LV1_2_OUT_ARGS
163#define LV1_7_IN_2_OUT_ARGS LV1_7_IN_ARGS, LV1_2_OUT_ARGS
164
165#define LV1_0_IN_3_OUT_ARGS LV1_3_OUT_ARGS
166#define LV1_1_IN_3_OUT_ARGS LV1_1_IN_ARGS, LV1_3_OUT_ARGS
167#define LV1_2_IN_3_OUT_ARGS LV1_2_IN_ARGS, LV1_3_OUT_ARGS
168#define LV1_3_IN_3_OUT_ARGS LV1_3_IN_ARGS, LV1_3_OUT_ARGS
169#define LV1_4_IN_3_OUT_ARGS LV1_4_IN_ARGS, LV1_3_OUT_ARGS
170#define LV1_5_IN_3_OUT_ARGS LV1_5_IN_ARGS, LV1_3_OUT_ARGS
171#define LV1_6_IN_3_OUT_ARGS LV1_6_IN_ARGS, LV1_3_OUT_ARGS
172#define LV1_7_IN_3_OUT_ARGS LV1_7_IN_ARGS, LV1_3_OUT_ARGS
173
174#define LV1_0_IN_4_OUT_ARGS LV1_4_OUT_ARGS
175#define LV1_1_IN_4_OUT_ARGS LV1_1_IN_ARGS, LV1_4_OUT_ARGS
176#define LV1_2_IN_4_OUT_ARGS LV1_2_IN_ARGS, LV1_4_OUT_ARGS
177#define LV1_3_IN_4_OUT_ARGS LV1_3_IN_ARGS, LV1_4_OUT_ARGS
178#define LV1_4_IN_4_OUT_ARGS LV1_4_IN_ARGS, LV1_4_OUT_ARGS
179#define LV1_5_IN_4_OUT_ARGS LV1_5_IN_ARGS, LV1_4_OUT_ARGS
180#define LV1_6_IN_4_OUT_ARGS LV1_6_IN_ARGS, LV1_4_OUT_ARGS
181#define LV1_7_IN_4_OUT_ARGS LV1_7_IN_ARGS, LV1_4_OUT_ARGS
182
183#define LV1_0_IN_5_OUT_ARGS LV1_5_OUT_ARGS
184#define LV1_1_IN_5_OUT_ARGS LV1_1_IN_ARGS, LV1_5_OUT_ARGS
185#define LV1_2_IN_5_OUT_ARGS LV1_2_IN_ARGS, LV1_5_OUT_ARGS
186#define LV1_3_IN_5_OUT_ARGS LV1_3_IN_ARGS, LV1_5_OUT_ARGS
187#define LV1_4_IN_5_OUT_ARGS LV1_4_IN_ARGS, LV1_5_OUT_ARGS
188#define LV1_5_IN_5_OUT_ARGS LV1_5_IN_ARGS, LV1_5_OUT_ARGS
189#define LV1_6_IN_5_OUT_ARGS LV1_6_IN_ARGS, LV1_5_OUT_ARGS
190#define LV1_7_IN_5_OUT_ARGS LV1_7_IN_ARGS, LV1_5_OUT_ARGS
191
192#define LV1_0_IN_6_OUT_ARGS LV1_6_OUT_ARGS
193#define LV1_1_IN_6_OUT_ARGS LV1_1_IN_ARGS, LV1_6_OUT_ARGS
194#define LV1_2_IN_6_OUT_ARGS LV1_2_IN_ARGS, LV1_6_OUT_ARGS
195#define LV1_3_IN_6_OUT_ARGS LV1_3_IN_ARGS, LV1_6_OUT_ARGS
196#define LV1_4_IN_6_OUT_ARGS LV1_4_IN_ARGS, LV1_6_OUT_ARGS
197#define LV1_5_IN_6_OUT_ARGS LV1_5_IN_ARGS, LV1_6_OUT_ARGS
198#define LV1_6_IN_6_OUT_ARGS LV1_6_IN_ARGS, LV1_6_OUT_ARGS
199#define LV1_7_IN_6_OUT_ARGS LV1_7_IN_ARGS, LV1_6_OUT_ARGS
200
201#define LV1_0_IN_7_OUT_ARGS LV1_7_OUT_ARGS
202#define LV1_1_IN_7_OUT_ARGS LV1_1_IN_ARGS, LV1_7_OUT_ARGS
203#define LV1_2_IN_7_OUT_ARGS LV1_2_IN_ARGS, LV1_7_OUT_ARGS
204#define LV1_3_IN_7_OUT_ARGS LV1_3_IN_ARGS, LV1_7_OUT_ARGS
205#define LV1_4_IN_7_OUT_ARGS LV1_4_IN_ARGS, LV1_7_OUT_ARGS
206#define LV1_5_IN_7_OUT_ARGS LV1_5_IN_ARGS, LV1_7_OUT_ARGS
207#define LV1_6_IN_7_OUT_ARGS LV1_6_IN_ARGS, LV1_7_OUT_ARGS
208#define LV1_7_IN_7_OUT_ARGS LV1_7_IN_ARGS, LV1_7_OUT_ARGS
209
210/*
211 * This LV1_CALL() macro is for use by callers. It expands into an
212 * inline call wrapper and an underscored HV call declaration. The
213 * wrapper can be used to instrument the lv1 call interface. The
214 * file lv1call.S defines its own LV1_CALL() macro to expand into
215 * the actual underscored call definition.
216 */
217
218#if !defined(LV1_CALL)
219#define LV1_CALL(name, in, out, num) \
220 extern s64 _lv1_##name(LV1_##in##_IN_##out##_OUT_ARG_DECL); \
221 static inline int lv1_##name(LV1_##in##_IN_##out##_OUT_ARG_DECL) \
222 {return _lv1_##name(LV1_##in##_IN_##out##_OUT_ARGS);}
223#endif
224
225#endif /* !defined(__ASSEMBLY__) */
226
227/* lv1 call table */
228
229LV1_CALL(allocate_memory, 4, 2, 0 )
230LV1_CALL(write_htab_entry, 4, 0, 1 )
231LV1_CALL(construct_virtual_address_space, 3, 2, 2 )
232LV1_CALL(invalidate_htab_entries, 5, 0, 3 )
233LV1_CALL(get_virtual_address_space_id_of_ppe, 1, 1, 4 )
234LV1_CALL(query_logical_partition_address_region_info, 1, 5, 6 )
235LV1_CALL(select_virtual_address_space, 1, 0, 7 )
236LV1_CALL(pause, 1, 0, 9 )
237LV1_CALL(destruct_virtual_address_space, 1, 0, 10 )
238LV1_CALL(configure_irq_state_bitmap, 3, 0, 11 )
239LV1_CALL(connect_irq_plug_ext, 5, 0, 12 )
240LV1_CALL(release_memory, 1, 0, 13 )
241LV1_CALL(put_iopte, 5, 0, 15 )
242LV1_CALL(disconnect_irq_plug_ext, 3, 0, 17 )
243LV1_CALL(construct_event_receive_port, 0, 1, 18 )
244LV1_CALL(destruct_event_receive_port, 1, 0, 19 )
245LV1_CALL(send_event_locally, 1, 0, 24 )
246LV1_CALL(end_of_interrupt, 1, 0, 27 )
247LV1_CALL(connect_irq_plug, 2, 0, 28 )
248LV1_CALL(disconnect_irq_plug, 1, 0, 29 )
249LV1_CALL(end_of_interrupt_ext, 3, 0, 30 )
250LV1_CALL(did_update_interrupt_mask, 2, 0, 31 )
251LV1_CALL(shutdown_logical_partition, 1, 0, 44 )
252LV1_CALL(destruct_logical_spe, 1, 0, 54 )
253LV1_CALL(construct_logical_spe, 7, 6, 57 )
254LV1_CALL(set_spe_interrupt_mask, 3, 0, 61 )
255LV1_CALL(set_spe_transition_notifier, 3, 0, 64 )
256LV1_CALL(disable_logical_spe, 2, 0, 65 )
257LV1_CALL(clear_spe_interrupt_status, 4, 0, 66 )
258LV1_CALL(get_spe_interrupt_status, 2, 1, 67 )
259LV1_CALL(get_logical_ppe_id, 0, 1, 69 )
260LV1_CALL(set_interrupt_mask, 5, 0, 73 )
261LV1_CALL(get_logical_partition_id, 0, 1, 74 )
262LV1_CALL(configure_execution_time_variable, 1, 0, 77 )
263LV1_CALL(get_spe_irq_outlet, 2, 1, 78 )
264LV1_CALL(set_spe_privilege_state_area_1_register, 3, 0, 79 )
265LV1_CALL(create_repository_node, 6, 0, 90 )
266LV1_CALL(get_repository_node_value, 5, 2, 91 )
267LV1_CALL(modify_repository_node_value, 6, 0, 92 )
268LV1_CALL(remove_repository_node, 4, 0, 93 )
269LV1_CALL(read_htab_entries, 2, 5, 95 )
270LV1_CALL(set_dabr, 2, 0, 96 )
271LV1_CALL(get_total_execution_time, 2, 1, 103 )
272LV1_CALL(allocate_io_segment, 3, 1, 116 )
273LV1_CALL(release_io_segment, 2, 0, 117 )
274LV1_CALL(construct_io_irq_outlet, 1, 1, 120 )
275LV1_CALL(destruct_io_irq_outlet, 1, 0, 121 )
276LV1_CALL(map_htab, 1, 1, 122 )
277LV1_CALL(unmap_htab, 1, 0, 123 )
278LV1_CALL(get_version_info, 0, 1, 127 )
279LV1_CALL(insert_htab_entry, 6, 3, 158 )
280LV1_CALL(read_virtual_uart, 3, 1, 162 )
281LV1_CALL(write_virtual_uart, 3, 1, 163 )
282LV1_CALL(set_virtual_uart_param, 3, 0, 164 )
283LV1_CALL(get_virtual_uart_param, 2, 1, 165 )
284LV1_CALL(configure_virtual_uart_irq, 1, 1, 166 )
285LV1_CALL(open_device, 3, 0, 170 )
286LV1_CALL(close_device, 2, 0, 171 )
287LV1_CALL(map_device_mmio_region, 5, 1, 172 )
288LV1_CALL(unmap_device_mmio_region, 3, 0, 173 )
289LV1_CALL(allocate_device_dma_region, 5, 1, 174 )
290LV1_CALL(free_device_dma_region, 3, 0, 175 )
291LV1_CALL(map_device_dma_region, 6, 0, 176 )
292LV1_CALL(unmap_device_dma_region, 4, 0, 177 )
293LV1_CALL(net_add_multicast_address, 4, 0, 185 )
294LV1_CALL(net_remove_multicast_address, 4, 0, 186 )
295LV1_CALL(net_start_tx_dma, 4, 0, 187 )
296LV1_CALL(net_stop_tx_dma, 3, 0, 188 )
297LV1_CALL(net_start_rx_dma, 4, 0, 189 )
298LV1_CALL(net_stop_rx_dma, 3, 0, 190 )
299LV1_CALL(net_set_interrupt_status_indicator, 4, 0, 191 )
300LV1_CALL(net_set_interrupt_mask, 4, 0, 193 )
301LV1_CALL(net_control, 6, 2, 194 )
302LV1_CALL(connect_interrupt_event_receive_port, 4, 0, 197 )
303LV1_CALL(disconnect_interrupt_event_receive_port, 4, 0, 198 )
304LV1_CALL(get_spe_all_interrupt_statuses, 1, 1, 199 )
305LV1_CALL(deconfigure_virtual_uart_irq, 0, 0, 202 )
306LV1_CALL(enable_logical_spe, 2, 0, 207 )
307LV1_CALL(gpu_open, 1, 0, 210 )
308LV1_CALL(gpu_close, 0, 0, 211 )
309LV1_CALL(gpu_device_map, 1, 2, 212 )
310LV1_CALL(gpu_device_unmap, 1, 0, 213 )
311LV1_CALL(gpu_memory_allocate, 5, 2, 214 )
312LV1_CALL(gpu_memory_free, 1, 0, 216 )
313LV1_CALL(gpu_context_allocate, 2, 5, 217 )
314LV1_CALL(gpu_context_free, 1, 0, 218 )
315LV1_CALL(gpu_context_iomap, 5, 0, 221 )
316LV1_CALL(gpu_context_attribute, 6, 0, 225 )
317LV1_CALL(gpu_context_intr, 1, 1, 227 )
318LV1_CALL(gpu_attribute, 5, 0, 228 )
319LV1_CALL(get_rtc, 0, 2, 232 )
320LV1_CALL(set_ppe_periodic_tracer_frequency, 1, 0, 240 )
321LV1_CALL(start_ppe_periodic_tracer, 5, 0, 241 )
322LV1_CALL(stop_ppe_periodic_tracer, 1, 1, 242 )
323LV1_CALL(storage_read, 6, 1, 245 )
324LV1_CALL(storage_write, 6, 1, 246 )
325LV1_CALL(storage_send_device_command, 6, 1, 248 )
326LV1_CALL(storage_get_async_status, 1, 2, 249 )
327LV1_CALL(storage_check_async_status, 2, 1, 254 )
328LV1_CALL(panic, 1, 0, 255 )
329LV1_CALL(construct_lpm, 6, 3, 140 )
330LV1_CALL(destruct_lpm, 1, 0, 141 )
331LV1_CALL(start_lpm, 1, 0, 142 )
332LV1_CALL(stop_lpm, 1, 1, 143 )
333LV1_CALL(copy_lpm_trace_buffer, 3, 1, 144 )
334LV1_CALL(add_lpm_event_bookmark, 5, 0, 145 )
335LV1_CALL(delete_lpm_event_bookmark, 3, 0, 146 )
336LV1_CALL(set_lpm_interrupt_mask, 3, 1, 147 )
337LV1_CALL(get_lpm_interrupt_status, 1, 1, 148 )
338LV1_CALL(set_lpm_general_control, 5, 2, 149 )
339LV1_CALL(set_lpm_interval, 3, 1, 150 )
340LV1_CALL(set_lpm_trigger_control, 3, 1, 151 )
341LV1_CALL(set_lpm_counter_control, 4, 1, 152 )
342LV1_CALL(set_lpm_group_control, 3, 1, 153 )
343LV1_CALL(set_lpm_debug_bus_control, 3, 1, 154 )
344LV1_CALL(set_lpm_counter, 5, 2, 155 )
345LV1_CALL(set_lpm_signal, 7, 0, 156 )
346LV1_CALL(set_lpm_spr_trigger, 2, 0, 157 )
347
348#endif
diff --git a/include/asm-powerpc/machdep.h b/include/asm-powerpc/machdep.h
deleted file mode 100644
index 893aafd87fd..00000000000
--- a/include/asm-powerpc/machdep.h
+++ /dev/null
@@ -1,365 +0,0 @@
1#ifndef _ASM_POWERPC_MACHDEP_H
2#define _ASM_POWERPC_MACHDEP_H
3#ifdef __KERNEL__
4
5/*
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#include <linux/seq_file.h>
13#include <linux/init.h>
14#include <linux/dma-mapping.h>
15
16#include <asm/setup.h>
17
18/* We export this macro for external modules like Alsa to know if
19 * ppc_md.feature_call is implemented or not
20 */
21#define CONFIG_PPC_HAS_FEATURE_CALLS
22
23struct pt_regs;
24struct pci_bus;
25struct device_node;
26struct iommu_table;
27struct rtc_time;
28struct file;
29struct pci_controller;
30#ifdef CONFIG_KEXEC
31struct kimage;
32#endif
33
34#ifdef CONFIG_SMP
35struct smp_ops_t {
36 void (*message_pass)(int target, int msg);
37 int (*probe)(void);
38 void (*kick_cpu)(int nr);
39 void (*setup_cpu)(int nr);
40 void (*take_timebase)(void);
41 void (*give_timebase)(void);
42 int (*cpu_enable)(unsigned int nr);
43 int (*cpu_disable)(void);
44 void (*cpu_die)(unsigned int nr);
45 int (*cpu_bootable)(unsigned int nr);
46};
47#endif
48
49struct machdep_calls {
50 char *name;
51#ifdef CONFIG_PPC64
52 void (*hpte_invalidate)(unsigned long slot,
53 unsigned long va,
54 int psize, int ssize,
55 int local);
56 long (*hpte_updatepp)(unsigned long slot,
57 unsigned long newpp,
58 unsigned long va,
59 int psize, int ssize,
60 int local);
61 void (*hpte_updateboltedpp)(unsigned long newpp,
62 unsigned long ea,
63 int psize, int ssize);
64 long (*hpte_insert)(unsigned long hpte_group,
65 unsigned long va,
66 unsigned long prpn,
67 unsigned long rflags,
68 unsigned long vflags,
69 int psize, int ssize);
70 long (*hpte_remove)(unsigned long hpte_group);
71 void (*hpte_removebolted)(unsigned long ea,
72 int psize, int ssize);
73 void (*flush_hash_range)(unsigned long number, int local);
74
75 /* special for kexec, to be called in real mode, linar mapping is
76 * destroyed as well */
77 void (*hpte_clear_all)(void);
78
79 int (*tce_build)(struct iommu_table *tbl,
80 long index,
81 long npages,
82 unsigned long uaddr,
83 enum dma_data_direction direction,
84 struct dma_attrs *attrs);
85 void (*tce_free)(struct iommu_table *tbl,
86 long index,
87 long npages);
88 unsigned long (*tce_get)(struct iommu_table *tbl,
89 long index);
90 void (*tce_flush)(struct iommu_table *tbl);
91 void (*pci_dma_dev_setup)(struct pci_dev *dev);
92 void (*pci_dma_bus_setup)(struct pci_bus *bus);
93
94 void __iomem * (*ioremap)(phys_addr_t addr, unsigned long size,
95 unsigned long flags);
96 void (*iounmap)(volatile void __iomem *token);
97
98#ifdef CONFIG_PM
99 void (*iommu_save)(void);
100 void (*iommu_restore)(void);
101#endif
102#endif /* CONFIG_PPC64 */
103
104 int (*probe)(void);
105 void (*setup_arch)(void); /* Optional, may be NULL */
106 void (*init_early)(void);
107 /* Optional, may be NULL. */
108 void (*show_cpuinfo)(struct seq_file *m);
109 void (*show_percpuinfo)(struct seq_file *m, int i);
110
111 void (*init_IRQ)(void);
112 unsigned int (*get_irq)(void);
113#ifdef CONFIG_KEXEC
114 void (*kexec_cpu_down)(int crash_shutdown, int secondary);
115#endif
116
117 /* PCI stuff */
118 /* Called after scanning the bus, before allocating resources */
119 void (*pcibios_fixup)(void);
120 int (*pci_probe_mode)(struct pci_bus *);
121 void (*pci_irq_fixup)(struct pci_dev *dev);
122
123 /* To setup PHBs when using automatic OF platform driver for PCI */
124 int (*pci_setup_phb)(struct pci_controller *host);
125
126#ifdef CONFIG_PCI_MSI
127 int (*msi_check_device)(struct pci_dev* dev,
128 int nvec, int type);
129 int (*setup_msi_irqs)(struct pci_dev *dev,
130 int nvec, int type);
131 void (*teardown_msi_irqs)(struct pci_dev *dev);
132#endif
133
134 void (*restart)(char *cmd);
135 void (*power_off)(void);
136 void (*halt)(void);
137 void (*panic)(char *str);
138 void (*cpu_die)(void);
139
140 long (*time_init)(void); /* Optional, may be NULL */
141
142 int (*set_rtc_time)(struct rtc_time *);
143 void (*get_rtc_time)(struct rtc_time *);
144 unsigned long (*get_boot_time)(void);
145 unsigned char (*rtc_read_val)(int addr);
146 void (*rtc_write_val)(int addr, unsigned char val);
147
148 void (*calibrate_decr)(void);
149
150 void (*progress)(char *, unsigned short);
151
152 /* Interface for platform error logging */
153 void (*log_error)(char *buf, unsigned int err_type, int fatal);
154
155 unsigned char (*nvram_read_val)(int addr);
156 void (*nvram_write_val)(int addr, unsigned char val);
157 ssize_t (*nvram_write)(char *buf, size_t count, loff_t *index);
158 ssize_t (*nvram_read)(char *buf, size_t count, loff_t *index);
159 ssize_t (*nvram_size)(void);
160 void (*nvram_sync)(void);
161
162 /* Exception handlers */
163 int (*system_reset_exception)(struct pt_regs *regs);
164 int (*machine_check_exception)(struct pt_regs *regs);
165
166 /* Motherboard/chipset features. This is a kind of general purpose
167 * hook used to control some machine specific features (like reset
168 * lines, chip power control, etc...).
169 */
170 long (*feature_call)(unsigned int feature, ...);
171
172 /* Get legacy PCI/IDE interrupt mapping */
173 int (*pci_get_legacy_ide_irq)(struct pci_dev *dev, int channel);
174
175 /* Get access protection for /dev/mem */
176 pgprot_t (*phys_mem_access_prot)(struct file *file,
177 unsigned long pfn,
178 unsigned long size,
179 pgprot_t vma_prot);
180
181 /* Idle loop for this platform, leave empty for default idle loop */
182 void (*idle_loop)(void);
183
184 /*
185 * Function for waiting for work with reduced power in idle loop;
186 * called with interrupts disabled.
187 */
188 void (*power_save)(void);
189
190 /* Function to enable performance monitor counters for this
191 platform, called once per cpu. */
192 void (*enable_pmcs)(void);
193
194 /* Set DABR for this platform, leave empty for default implemenation */
195 int (*set_dabr)(unsigned long dabr);
196
197#ifdef CONFIG_PPC32 /* XXX for now */
198 /* A general init function, called by ppc_init in init/main.c.
199 May be NULL. */
200 void (*init)(void);
201
202 void (*kgdb_map_scc)(void);
203
204 /*
205 * optional PCI "hooks"
206 */
207 /* Called in indirect_* to avoid touching devices */
208 int (*pci_exclude_device)(struct pci_controller *, unsigned char, unsigned char);
209
210 /* Called at then very end of pcibios_init() */
211 void (*pcibios_after_init)(void);
212
213#endif /* CONFIG_PPC32 */
214
215 /* Called after PPC generic resource fixup to perform
216 machine specific fixups */
217 void (*pcibios_fixup_resources)(struct pci_dev *);
218
219 /* Called for each PCI bus in the system when it's probed */
220 void (*pcibios_fixup_bus)(struct pci_bus *);
221
222 /* Called when pci_enable_device() is called. Returns 0 to
223 * allow assignment/enabling of the device. */
224 int (*pcibios_enable_device_hook)(struct pci_dev *);
225
226 /* Called to shutdown machine specific hardware not already controlled
227 * by other drivers.
228 */
229 void (*machine_shutdown)(void);
230
231#ifdef CONFIG_KEXEC
232 /* Called to do the minimal shutdown needed to run a kexec'd kernel
233 * to run successfully.
234 * XXX Should we move this one out of kexec scope?
235 */
236 void (*machine_crash_shutdown)(struct pt_regs *regs);
237
238 /* Called to do what every setup is needed on image and the
239 * reboot code buffer. Returns 0 on success.
240 * Provide your own (maybe dummy) implementation if your platform
241 * claims to support kexec.
242 */
243 int (*machine_kexec_prepare)(struct kimage *image);
244
245 /* Called to handle any machine specific cleanup on image */
246 void (*machine_kexec_cleanup)(struct kimage *image);
247
248 /* Called to perform the _real_ kexec.
249 * Do NOT allocate memory or fail here. We are past the point of
250 * no return.
251 */
252 void (*machine_kexec)(struct kimage *image);
253#endif /* CONFIG_KEXEC */
254
255#ifdef CONFIG_SUSPEND
256 /* These are called to disable and enable, respectively, IRQs when
257 * entering a suspend state. If NULL, then the generic versions
258 * will be called. The generic versions disable/enable the
259 * decrementer along with interrupts.
260 */
261 void (*suspend_disable_irqs)(void);
262 void (*suspend_enable_irqs)(void);
263#endif
264};
265
266extern void e500_idle(void);
267extern void power4_idle(void);
268extern void power4_cpu_offline_powersave(void);
269extern void ppc6xx_idle(void);
270
271/*
272 * ppc_md contains a copy of the machine description structure for the
273 * current platform. machine_id contains the initial address where the
274 * description was found during boot.
275 */
276extern struct machdep_calls ppc_md;
277extern struct machdep_calls *machine_id;
278
279#define __machine_desc __attribute__ ((__section__ (".machine.desc")))
280
281#define define_machine(name) \
282 extern struct machdep_calls mach_##name; \
283 EXPORT_SYMBOL(mach_##name); \
284 struct machdep_calls mach_##name __machine_desc =
285
286#define machine_is(name) \
287 ({ \
288 extern struct machdep_calls mach_##name \
289 __attribute__((weak)); \
290 machine_id == &mach_##name; \
291 })
292
293extern void probe_machine(void);
294
295extern char cmd_line[COMMAND_LINE_SIZE];
296
297#ifdef CONFIG_PPC_PMAC
298/*
299 * Power macintoshes have either a CUDA, PMU or SMU controlling
300 * system reset, power, NVRAM, RTC.
301 */
302typedef enum sys_ctrler_kind {
303 SYS_CTRLER_UNKNOWN = 0,
304 SYS_CTRLER_CUDA = 1,
305 SYS_CTRLER_PMU = 2,
306 SYS_CTRLER_SMU = 3,
307} sys_ctrler_t;
308extern sys_ctrler_t sys_ctrler;
309
310#endif /* CONFIG_PPC_PMAC */
311
312extern void setup_pci_ptrs(void);
313
314#ifdef CONFIG_SMP
315/* Poor default implementations */
316extern void __devinit smp_generic_give_timebase(void);
317extern void __devinit smp_generic_take_timebase(void);
318#endif /* CONFIG_SMP */
319
320
321/* Functions to produce codes on the leds.
322 * The SRC code should be unique for the message category and should
323 * be limited to the lower 24 bits (the upper 8 are set by these funcs),
324 * and (for boot & dump) should be sorted numerically in the order
325 * the events occur.
326 */
327/* Print a boot progress message. */
328void ppc64_boot_msg(unsigned int src, const char *msg);
329/* Print a termination message (print only -- does not stop the kernel) */
330void ppc64_terminate_msg(unsigned int src, const char *msg);
331
332static inline void log_error(char *buf, unsigned int err_type, int fatal)
333{
334 if (ppc_md.log_error)
335 ppc_md.log_error(buf, err_type, fatal);
336}
337
338#define __define_machine_initcall(mach,level,fn,id) \
339 static int __init __machine_initcall_##mach##_##fn(void) { \
340 if (machine_is(mach)) return fn(); \
341 return 0; \
342 } \
343 __define_initcall(level,__machine_initcall_##mach##_##fn,id);
344
345#define machine_core_initcall(mach,fn) __define_machine_initcall(mach,"1",fn,1)
346#define machine_core_initcall_sync(mach,fn) __define_machine_initcall(mach,"1s",fn,1s)
347#define machine_postcore_initcall(mach,fn) __define_machine_initcall(mach,"2",fn,2)
348#define machine_postcore_initcall_sync(mach,fn) __define_machine_initcall(mach,"2s",fn,2s)
349#define machine_arch_initcall(mach,fn) __define_machine_initcall(mach,"3",fn,3)
350#define machine_arch_initcall_sync(mach,fn) __define_machine_initcall(mach,"3s",fn,3s)
351#define machine_subsys_initcall(mach,fn) __define_machine_initcall(mach,"4",fn,4)
352#define machine_subsys_initcall_sync(mach,fn) __define_machine_initcall(mach,"4s",fn,4s)
353#define machine_fs_initcall(mach,fn) __define_machine_initcall(mach,"5",fn,5)
354#define machine_fs_initcall_sync(mach,fn) __define_machine_initcall(mach,"5s",fn,5s)
355#define machine_rootfs_initcall(mach,fn) __define_machine_initcall(mach,"rootfs",fn,rootfs)
356#define machine_device_initcall(mach,fn) __define_machine_initcall(mach,"6",fn,6)
357#define machine_device_initcall_sync(mach,fn) __define_machine_initcall(mach,"6s",fn,6s)
358#define machine_late_initcall(mach,fn) __define_machine_initcall(mach,"7",fn,7)
359#define machine_late_initcall_sync(mach,fn) __define_machine_initcall(mach,"7s",fn,7s)
360
361void generic_suspend_disable_irqs(void);
362void generic_suspend_enable_irqs(void);
363
364#endif /* __KERNEL__ */
365#endif /* _ASM_POWERPC_MACHDEP_H */
diff --git a/include/asm-powerpc/macio.h b/include/asm-powerpc/macio.h
deleted file mode 100644
index 079c06eae44..00000000000
--- a/include/asm-powerpc/macio.h
+++ /dev/null
@@ -1,142 +0,0 @@
1#ifndef __MACIO_ASIC_H__
2#define __MACIO_ASIC_H__
3#ifdef __KERNEL__
4
5#include <linux/of_device.h>
6
7extern struct bus_type macio_bus_type;
8
9/* MacIO device driver is defined later */
10struct macio_driver;
11struct macio_chip;
12
13#define MACIO_DEV_COUNT_RESOURCES 8
14#define MACIO_DEV_COUNT_IRQS 8
15
16/*
17 * the macio_bus structure is used to describe a "virtual" bus
18 * within a MacIO ASIC. It's typically provided by a macio_pci_asic
19 * PCI device, but could be provided differently as well (nubus
20 * machines using a fake OF tree).
21 *
22 * The pdev field can be NULL on non-PCI machines
23 */
24struct macio_bus
25{
26 struct macio_chip *chip; /* macio_chip (private use) */
27 int index; /* macio chip index in system */
28#ifdef CONFIG_PCI
29 struct pci_dev *pdev; /* PCI device hosting this bus */
30#endif
31};
32
33/*
34 * the macio_dev structure is used to describe a device
35 * within an Apple MacIO ASIC.
36 */
37struct macio_dev
38{
39 struct macio_bus *bus; /* macio bus this device is on */
40 struct macio_dev *media_bay; /* Device is part of a media bay */
41 struct of_device ofdev;
42 int n_resources;
43 struct resource resource[MACIO_DEV_COUNT_RESOURCES];
44 int n_interrupts;
45 struct resource interrupt[MACIO_DEV_COUNT_IRQS];
46};
47#define to_macio_device(d) container_of(d, struct macio_dev, ofdev.dev)
48#define of_to_macio_device(d) container_of(d, struct macio_dev, ofdev)
49
50extern struct macio_dev *macio_dev_get(struct macio_dev *dev);
51extern void macio_dev_put(struct macio_dev *dev);
52
53/*
54 * Accessors to resources & interrupts and other device
55 * fields
56 */
57
58static inline int macio_resource_count(struct macio_dev *dev)
59{
60 return dev->n_resources;
61}
62
63static inline unsigned long macio_resource_start(struct macio_dev *dev, int resource_no)
64{
65 return dev->resource[resource_no].start;
66}
67
68static inline unsigned long macio_resource_end(struct macio_dev *dev, int resource_no)
69{
70 return dev->resource[resource_no].end;
71}
72
73static inline unsigned long macio_resource_len(struct macio_dev *dev, int resource_no)
74{
75 struct resource *res = &dev->resource[resource_no];
76 if (res->start == 0 || res->end == 0 || res->end < res->start)
77 return 0;
78 return res->end - res->start + 1;
79}
80
81extern int macio_request_resource(struct macio_dev *dev, int resource_no, const char *name);
82extern void macio_release_resource(struct macio_dev *dev, int resource_no);
83extern int macio_request_resources(struct macio_dev *dev, const char *name);
84extern void macio_release_resources(struct macio_dev *dev);
85
86static inline int macio_irq_count(struct macio_dev *dev)
87{
88 return dev->n_interrupts;
89}
90
91static inline int macio_irq(struct macio_dev *dev, int irq_no)
92{
93 return dev->interrupt[irq_no].start;
94}
95
96static inline void macio_set_drvdata(struct macio_dev *dev, void *data)
97{
98 dev_set_drvdata(&dev->ofdev.dev, data);
99}
100
101static inline void* macio_get_drvdata(struct macio_dev *dev)
102{
103 return dev_get_drvdata(&dev->ofdev.dev);
104}
105
106static inline struct device_node *macio_get_of_node(struct macio_dev *mdev)
107{
108 return mdev->ofdev.node;
109}
110
111#ifdef CONFIG_PCI
112static inline struct pci_dev *macio_get_pci_dev(struct macio_dev *mdev)
113{
114 return mdev->bus->pdev;
115}
116#endif
117
118/*
119 * A driver for a mac-io chip based device
120 */
121struct macio_driver
122{
123 char *name;
124 struct of_device_id *match_table;
125 struct module *owner;
126
127 int (*probe)(struct macio_dev* dev, const struct of_device_id *match);
128 int (*remove)(struct macio_dev* dev);
129
130 int (*suspend)(struct macio_dev* dev, pm_message_t state);
131 int (*resume)(struct macio_dev* dev);
132 int (*shutdown)(struct macio_dev* dev);
133
134 struct device_driver driver;
135};
136#define to_macio_driver(drv) container_of(drv,struct macio_driver, driver)
137
138extern int macio_register_driver(struct macio_driver *);
139extern void macio_unregister_driver(struct macio_driver *);
140
141#endif /* __KERNEL__ */
142#endif /* __MACIO_ASIC_H__ */
diff --git a/include/asm-powerpc/mc146818rtc.h b/include/asm-powerpc/mc146818rtc.h
deleted file mode 100644
index f2741c8b59a..00000000000
--- a/include/asm-powerpc/mc146818rtc.h
+++ /dev/null
@@ -1,36 +0,0 @@
1#ifndef _ASM_POWERPC_MC146818RTC_H
2#define _ASM_POWERPC_MC146818RTC_H
3
4/*
5 * Machine dependent access functions for RTC registers.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#ifdef __KERNEL__
14
15#include <asm/io.h>
16
17#ifndef RTC_PORT
18#define RTC_PORT(x) (0x70 + (x))
19#define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */
20#endif
21
22/*
23 * The yet supported machines all access the RTC index register via
24 * an ISA port access but the way to access the date register differs ...
25 */
26#define CMOS_READ(addr) ({ \
27outb_p((addr),RTC_PORT(0)); \
28inb_p(RTC_PORT(1)); \
29})
30#define CMOS_WRITE(val, addr) ({ \
31outb_p((addr),RTC_PORT(0)); \
32outb_p((val),RTC_PORT(1)); \
33})
34
35#endif /* __KERNEL__ */
36#endif /* _ASM_POWERPC_MC146818RTC_H */
diff --git a/include/asm-powerpc/mediabay.h b/include/asm-powerpc/mediabay.h
deleted file mode 100644
index b2efb332580..00000000000
--- a/include/asm-powerpc/mediabay.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * mediabay.h: definitions for using the media bay
3 * on PowerBook 3400 and similar computers.
4 *
5 * Copyright (C) 1997 Paul Mackerras.
6 */
7#ifndef _PPC_MEDIABAY_H
8#define _PPC_MEDIABAY_H
9
10#ifdef __KERNEL__
11
12#define MB_FD 0 /* media bay contains floppy drive (automatic eject ?) */
13#define MB_FD1 1 /* media bay contains floppy drive (manual eject ?) */
14#define MB_SOUND 2 /* sound device ? */
15#define MB_CD 3 /* media bay contains ATA drive such as CD or ZIP */
16#define MB_PCI 5 /* media bay contains a PCI device */
17#define MB_POWER 6 /* media bay contains a Power device (???) */
18#define MB_NO 7 /* media bay contains nothing */
19
20/* Number of bays in the machine or 0 */
21extern int media_bay_count;
22
23#ifdef CONFIG_BLK_DEV_IDE_PMAC
24#include <linux/ide.h>
25
26int check_media_bay_by_base(unsigned long base, int what);
27/* called by IDE PMAC host driver to register IDE controller for media bay */
28int media_bay_set_ide_infos(struct device_node *which_bay, unsigned long base,
29 int irq, ide_hwif_t *hwif);
30
31int check_media_bay(struct device_node *which_bay, int what);
32
33#else
34
35static inline int check_media_bay(struct device_node *which_bay, int what)
36{
37 return -ENODEV;
38}
39
40#endif
41
42#endif /* __KERNEL__ */
43#endif /* _PPC_MEDIABAY_H */
diff --git a/include/asm-powerpc/mman.h b/include/asm-powerpc/mman.h
deleted file mode 100644
index 9209f755763..00000000000
--- a/include/asm-powerpc/mman.h
+++ /dev/null
@@ -1,63 +0,0 @@
1#ifndef _ASM_POWERPC_MMAN_H
2#define _ASM_POWERPC_MMAN_H
3
4#include <asm-generic/mman.h>
5
6/*
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#define PROT_SAO 0x10 /* Strong Access Ordering */
14
15#define MAP_RENAME MAP_ANONYMOUS /* In SunOS terminology */
16#define MAP_NORESERVE 0x40 /* don't reserve swap pages */
17#define MAP_LOCKED 0x80
18
19#define MAP_GROWSDOWN 0x0100 /* stack-like segment */
20#define MAP_DENYWRITE 0x0800 /* ETXTBSY */
21#define MAP_EXECUTABLE 0x1000 /* mark it as an executable */
22
23#define MCL_CURRENT 0x2000 /* lock all currently mapped pages */
24#define MCL_FUTURE 0x4000 /* lock all additions to address space */
25
26#define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */
27#define MAP_NONBLOCK 0x10000 /* do not block on IO */
28
29#ifdef __KERNEL__
30#ifdef CONFIG_PPC64
31
32#include <asm/cputable.h>
33#include <linux/mm.h>
34
35/*
36 * This file is included by linux/mman.h, so we can't use cacl_vm_prot_bits()
37 * here. How important is the optimization?
38 */
39static inline unsigned long arch_calc_vm_prot_bits(unsigned long prot)
40{
41 return (prot & PROT_SAO) ? VM_SAO : 0;
42}
43#define arch_calc_vm_prot_bits(prot) arch_calc_vm_prot_bits(prot)
44
45static inline pgprot_t arch_vm_get_page_prot(unsigned long vm_flags)
46{
47 return (vm_flags & VM_SAO) ? __pgprot(_PAGE_SAO) : 0;
48}
49#define arch_vm_get_page_prot(vm_flags) arch_vm_get_page_prot(vm_flags)
50
51static inline int arch_validate_prot(unsigned long prot)
52{
53 if (prot & ~(PROT_READ | PROT_WRITE | PROT_EXEC | PROT_SEM | PROT_SAO))
54 return 0;
55 if ((prot & PROT_SAO) && !cpu_has_feature(CPU_FTR_SAO))
56 return 0;
57 return 1;
58}
59#define arch_validate_prot(prot) arch_validate_prot(prot)
60
61#endif /* CONFIG_PPC64 */
62#endif /* __KERNEL__ */
63#endif /* _ASM_POWERPC_MMAN_H */
diff --git a/include/asm-powerpc/mmu-40x.h b/include/asm-powerpc/mmu-40x.h
deleted file mode 100644
index 3d108676584..00000000000
--- a/include/asm-powerpc/mmu-40x.h
+++ /dev/null
@@ -1,63 +0,0 @@
1#ifndef _ASM_POWERPC_MMU_40X_H_
2#define _ASM_POWERPC_MMU_40X_H_
3
4/*
5 * PPC40x support
6 */
7
8#define PPC40X_TLB_SIZE 64
9
10/*
11 * TLB entries are defined by a "high" tag portion and a "low" data
12 * portion. On all architectures, the data portion is 32-bits.
13 *
14 * TLB entries are managed entirely under software control by reading,
15 * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
16 * instructions.
17 */
18
19#define TLB_LO 1
20#define TLB_HI 0
21
22#define TLB_DATA TLB_LO
23#define TLB_TAG TLB_HI
24
25/* Tag portion */
26
27#define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */
28#define TLB_PAGESZ_MASK 0x00000380
29#define TLB_PAGESZ(x) (((x) & 0x7) << 7)
30#define PAGESZ_1K 0
31#define PAGESZ_4K 1
32#define PAGESZ_16K 2
33#define PAGESZ_64K 3
34#define PAGESZ_256K 4
35#define PAGESZ_1M 5
36#define PAGESZ_4M 6
37#define PAGESZ_16M 7
38#define TLB_VALID 0x00000040 /* Entry is valid */
39
40/* Data portion */
41
42#define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */
43#define TLB_PERM_MASK 0x00000300
44#define TLB_EX 0x00000200 /* Instruction execution allowed */
45#define TLB_WR 0x00000100 /* Writes permitted */
46#define TLB_ZSEL_MASK 0x000000F0
47#define TLB_ZSEL(x) (((x) & 0xF) << 4)
48#define TLB_ATTR_MASK 0x0000000F
49#define TLB_W 0x00000008 /* Caching is write-through */
50#define TLB_I 0x00000004 /* Caching is inhibited */
51#define TLB_M 0x00000002 /* Memory is coherent */
52#define TLB_G 0x00000001 /* Memory is guarded from prefetch */
53
54#ifndef __ASSEMBLY__
55
56typedef struct {
57 unsigned long id;
58 unsigned long vdso_base;
59} mm_context_t;
60
61#endif /* !__ASSEMBLY__ */
62
63#endif /* _ASM_POWERPC_MMU_40X_H_ */
diff --git a/include/asm-powerpc/mmu-44x.h b/include/asm-powerpc/mmu-44x.h
deleted file mode 100644
index a825524c981..00000000000
--- a/include/asm-powerpc/mmu-44x.h
+++ /dev/null
@@ -1,76 +0,0 @@
1#ifndef _ASM_POWERPC_MMU_44X_H_
2#define _ASM_POWERPC_MMU_44X_H_
3/*
4 * PPC440 support
5 */
6
7#define PPC44x_MMUCR_TID 0x000000ff
8#define PPC44x_MMUCR_STS 0x00010000
9
10#define PPC44x_TLB_PAGEID 0
11#define PPC44x_TLB_XLAT 1
12#define PPC44x_TLB_ATTRIB 2
13
14/* Page identification fields */
15#define PPC44x_TLB_EPN_MASK 0xfffffc00 /* Effective Page Number */
16#define PPC44x_TLB_VALID 0x00000200 /* Valid flag */
17#define PPC44x_TLB_TS 0x00000100 /* Translation address space */
18#define PPC44x_TLB_1K 0x00000000 /* Page sizes */
19#define PPC44x_TLB_4K 0x00000010
20#define PPC44x_TLB_16K 0x00000020
21#define PPC44x_TLB_64K 0x00000030
22#define PPC44x_TLB_256K 0x00000040
23#define PPC44x_TLB_1M 0x00000050
24#define PPC44x_TLB_16M 0x00000070
25#define PPC44x_TLB_256M 0x00000090
26
27/* Translation fields */
28#define PPC44x_TLB_RPN_MASK 0xfffffc00 /* Real Page Number */
29#define PPC44x_TLB_ERPN_MASK 0x0000000f
30
31/* Storage attribute and access control fields */
32#define PPC44x_TLB_ATTR_MASK 0x0000ff80
33#define PPC44x_TLB_U0 0x00008000 /* User 0 */
34#define PPC44x_TLB_U1 0x00004000 /* User 1 */
35#define PPC44x_TLB_U2 0x00002000 /* User 2 */
36#define PPC44x_TLB_U3 0x00001000 /* User 3 */
37#define PPC44x_TLB_W 0x00000800 /* Caching is write-through */
38#define PPC44x_TLB_I 0x00000400 /* Caching is inhibited */
39#define PPC44x_TLB_M 0x00000200 /* Memory is coherent */
40#define PPC44x_TLB_G 0x00000100 /* Memory is guarded */
41#define PPC44x_TLB_E 0x00000080 /* Memory is guarded */
42
43#define PPC44x_TLB_PERM_MASK 0x0000003f
44#define PPC44x_TLB_UX 0x00000020 /* User execution */
45#define PPC44x_TLB_UW 0x00000010 /* User write */
46#define PPC44x_TLB_UR 0x00000008 /* User read */
47#define PPC44x_TLB_SX 0x00000004 /* Super execution */
48#define PPC44x_TLB_SW 0x00000002 /* Super write */
49#define PPC44x_TLB_SR 0x00000001 /* Super read */
50
51/* Number of TLB entries */
52#define PPC44x_TLB_SIZE 64
53
54#ifndef __ASSEMBLY__
55
56extern unsigned int tlb_44x_hwater;
57
58typedef struct {
59 unsigned long id;
60 unsigned long vdso_base;
61} mm_context_t;
62
63#endif /* !__ASSEMBLY__ */
64
65#ifndef CONFIG_PPC_EARLY_DEBUG_44x
66#define PPC44x_EARLY_TLBS 1
67#else
68#define PPC44x_EARLY_TLBS 2
69#define PPC44x_EARLY_DEBUG_VIRTADDR (ASM_CONST(0xf0000000) \
70 | (ASM_CONST(CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW) & 0xffff))
71#endif
72
73/* Size of the TLBs used for pinning in lowmem */
74#define PPC_PIN_SIZE (1 << 28) /* 256M */
75
76#endif /* _ASM_POWERPC_MMU_44X_H_ */
diff --git a/include/asm-powerpc/mmu-8xx.h b/include/asm-powerpc/mmu-8xx.h
deleted file mode 100644
index 9db877eb88d..00000000000
--- a/include/asm-powerpc/mmu-8xx.h
+++ /dev/null
@@ -1,145 +0,0 @@
1#ifndef _ASM_POWERPC_MMU_8XX_H_
2#define _ASM_POWERPC_MMU_8XX_H_
3/*
4 * PPC8xx support
5 */
6
7/* Control/status registers for the MPC8xx.
8 * A write operation to these registers causes serialized access.
9 * During software tablewalk, the registers used perform mask/shift-add
10 * operations when written/read. A TLB entry is created when the Mx_RPN
11 * is written, and the contents of several registers are used to
12 * create the entry.
13 */
14#define SPRN_MI_CTR 784 /* Instruction TLB control register */
15#define MI_GPM 0x80000000 /* Set domain manager mode */
16#define MI_PPM 0x40000000 /* Set subpage protection */
17#define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
18#define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */
19#define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
20#define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */
21#define MI_RESETVAL 0x00000000 /* Value of register at reset */
22
23/* These are the Ks and Kp from the PowerPC books. For proper operation,
24 * Ks = 0, Kp = 1.
25 */
26#define SPRN_MI_AP 786
27#define MI_Ks 0x80000000 /* Should not be set */
28#define MI_Kp 0x40000000 /* Should always be set */
29
30/* The effective page number register. When read, contains the information
31 * about the last instruction TLB miss. When MI_RPN is written, bits in
32 * this register are used to create the TLB entry.
33 */
34#define SPRN_MI_EPN 787
35#define MI_EPNMASK 0xfffff000 /* Effective page number for entry */
36#define MI_EVALID 0x00000200 /* Entry is valid */
37#define MI_ASIDMASK 0x0000000f /* ASID match value */
38 /* Reset value is undefined */
39
40/* A "level 1" or "segment" or whatever you want to call it register.
41 * For the instruction TLB, it contains bits that get loaded into the
42 * TLB entry when the MI_RPN is written.
43 */
44#define SPRN_MI_TWC 789
45#define MI_APG 0x000001e0 /* Access protection group (0) */
46#define MI_GUARDED 0x00000010 /* Guarded storage */
47#define MI_PSMASK 0x0000000c /* Mask of page size bits */
48#define MI_PS8MEG 0x0000000c /* 8M page size */
49#define MI_PS512K 0x00000004 /* 512K page size */
50#define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */
51#define MI_SVALID 0x00000001 /* Segment entry is valid */
52 /* Reset value is undefined */
53
54/* Real page number. Defined by the pte. Writing this register
55 * causes a TLB entry to be created for the instruction TLB, using
56 * additional information from the MI_EPN, and MI_TWC registers.
57 */
58#define SPRN_MI_RPN 790
59
60/* Define an RPN value for mapping kernel memory to large virtual
61 * pages for boot initialization. This has real page number of 0,
62 * large page size, shared page, cache enabled, and valid.
63 * Also mark all subpages valid and write access.
64 */
65#define MI_BOOTINIT 0x000001fd
66
67#define SPRN_MD_CTR 792 /* Data TLB control register */
68#define MD_GPM 0x80000000 /* Set domain manager mode */
69#define MD_PPM 0x40000000 /* Set subpage protection */
70#define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
71#define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */
72#define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */
73#define MD_TWAM 0x04000000 /* Use 4K page hardware assist */
74#define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
75#define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */
76#define MD_RESETVAL 0x04000000 /* Value of register at reset */
77
78#define SPRN_M_CASID 793 /* Address space ID (context) to match */
79#define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */
80
81
82/* These are the Ks and Kp from the PowerPC books. For proper operation,
83 * Ks = 0, Kp = 1.
84 */
85#define SPRN_MD_AP 794
86#define MD_Ks 0x80000000 /* Should not be set */
87#define MD_Kp 0x40000000 /* Should always be set */
88
89/* The effective page number register. When read, contains the information
90 * about the last instruction TLB miss. When MD_RPN is written, bits in
91 * this register are used to create the TLB entry.
92 */
93#define SPRN_MD_EPN 795
94#define MD_EPNMASK 0xfffff000 /* Effective page number for entry */
95#define MD_EVALID 0x00000200 /* Entry is valid */
96#define MD_ASIDMASK 0x0000000f /* ASID match value */
97 /* Reset value is undefined */
98
99/* The pointer to the base address of the first level page table.
100 * During a software tablewalk, reading this register provides the address
101 * of the entry associated with MD_EPN.
102 */
103#define SPRN_M_TWB 796
104#define M_L1TB 0xfffff000 /* Level 1 table base address */
105#define M_L1INDX 0x00000ffc /* Level 1 index, when read */
106 /* Reset value is undefined */
107
108/* A "level 1" or "segment" or whatever you want to call it register.
109 * For the data TLB, it contains bits that get loaded into the TLB entry
110 * when the MD_RPN is written. It is also provides the hardware assist
111 * for finding the PTE address during software tablewalk.
112 */
113#define SPRN_MD_TWC 797
114#define MD_L2TB 0xfffff000 /* Level 2 table base address */
115#define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */
116#define MD_APG 0x000001e0 /* Access protection group (0) */
117#define MD_GUARDED 0x00000010 /* Guarded storage */
118#define MD_PSMASK 0x0000000c /* Mask of page size bits */
119#define MD_PS8MEG 0x0000000c /* 8M page size */
120#define MD_PS512K 0x00000004 /* 512K page size */
121#define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */
122#define MD_WT 0x00000002 /* Use writethrough page attribute */
123#define MD_SVALID 0x00000001 /* Segment entry is valid */
124 /* Reset value is undefined */
125
126
127/* Real page number. Defined by the pte. Writing this register
128 * causes a TLB entry to be created for the data TLB, using
129 * additional information from the MD_EPN, and MD_TWC registers.
130 */
131#define SPRN_MD_RPN 798
132
133/* This is a temporary storage register that could be used to save
134 * a processor working register during a tablewalk.
135 */
136#define SPRN_M_TW 799
137
138#ifndef __ASSEMBLY__
139typedef struct {
140 unsigned long id;
141 unsigned long vdso_base;
142} mm_context_t;
143#endif /* !__ASSEMBLY__ */
144
145#endif /* _ASM_POWERPC_MMU_8XX_H_ */
diff --git a/include/asm-powerpc/mmu-fsl-booke.h b/include/asm-powerpc/mmu-fsl-booke.h
deleted file mode 100644
index 925d93cf64d..00000000000
--- a/include/asm-powerpc/mmu-fsl-booke.h
+++ /dev/null
@@ -1,82 +0,0 @@
1#ifndef _ASM_POWERPC_MMU_FSL_BOOKE_H_
2#define _ASM_POWERPC_MMU_FSL_BOOKE_H_
3/*
4 * Freescale Book-E MMU support
5 */
6
7/* Book-E defined page sizes */
8#define BOOKE_PAGESZ_1K 0
9#define BOOKE_PAGESZ_4K 1
10#define BOOKE_PAGESZ_16K 2
11#define BOOKE_PAGESZ_64K 3
12#define BOOKE_PAGESZ_256K 4
13#define BOOKE_PAGESZ_1M 5
14#define BOOKE_PAGESZ_4M 6
15#define BOOKE_PAGESZ_16M 7
16#define BOOKE_PAGESZ_64M 8
17#define BOOKE_PAGESZ_256M 9
18#define BOOKE_PAGESZ_1GB 10
19#define BOOKE_PAGESZ_4GB 11
20#define BOOKE_PAGESZ_16GB 12
21#define BOOKE_PAGESZ_64GB 13
22#define BOOKE_PAGESZ_256GB 14
23#define BOOKE_PAGESZ_1TB 15
24
25#define MAS0_TLBSEL(x) ((x << 28) & 0x30000000)
26#define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000)
27#define MAS0_NV(x) ((x) & 0x00000FFF)
28
29#define MAS1_VALID 0x80000000
30#define MAS1_IPROT 0x40000000
31#define MAS1_TID(x) ((x << 16) & 0x3FFF0000)
32#define MAS1_TS 0x00001000
33#define MAS1_TSIZE(x) ((x << 8) & 0x00000F00)
34
35#define MAS2_EPN 0xFFFFF000
36#define MAS2_X0 0x00000040
37#define MAS2_X1 0x00000020
38#define MAS2_W 0x00000010
39#define MAS2_I 0x00000008
40#define MAS2_M 0x00000004
41#define MAS2_G 0x00000002
42#define MAS2_E 0x00000001
43
44#define MAS3_RPN 0xFFFFF000
45#define MAS3_U0 0x00000200
46#define MAS3_U1 0x00000100
47#define MAS3_U2 0x00000080
48#define MAS3_U3 0x00000040
49#define MAS3_UX 0x00000020
50#define MAS3_SX 0x00000010
51#define MAS3_UW 0x00000008
52#define MAS3_SW 0x00000004
53#define MAS3_UR 0x00000002
54#define MAS3_SR 0x00000001
55
56#define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
57#define MAS4_TIDDSEL 0x000F0000
58#define MAS4_TSIZED(x) MAS1_TSIZE(x)
59#define MAS4_X0D 0x00000040
60#define MAS4_X1D 0x00000020
61#define MAS4_WD 0x00000010
62#define MAS4_ID 0x00000008
63#define MAS4_MD 0x00000004
64#define MAS4_GD 0x00000002
65#define MAS4_ED 0x00000001
66
67#define MAS6_SPID0 0x3FFF0000
68#define MAS6_SPID1 0x00007FFE
69#define MAS6_SAS 0x00000001
70#define MAS6_SPID MAS6_SPID0
71
72#define MAS7_RPN 0xFFFFFFFF
73
74#ifndef __ASSEMBLY__
75
76typedef struct {
77 unsigned long id;
78 unsigned long vdso_base;
79} mm_context_t;
80#endif /* !__ASSEMBLY__ */
81
82#endif /* _ASM_POWERPC_MMU_FSL_BOOKE_H_ */
diff --git a/include/asm-powerpc/mmu-hash32.h b/include/asm-powerpc/mmu-hash32.h
deleted file mode 100644
index 16b1a1e77e6..00000000000
--- a/include/asm-powerpc/mmu-hash32.h
+++ /dev/null
@@ -1,83 +0,0 @@
1#ifndef _ASM_POWERPC_MMU_HASH32_H_
2#define _ASM_POWERPC_MMU_HASH32_H_
3/*
4 * 32-bit hash table MMU support
5 */
6
7/*
8 * BATs
9 */
10
11/* Block size masks */
12#define BL_128K 0x000
13#define BL_256K 0x001
14#define BL_512K 0x003
15#define BL_1M 0x007
16#define BL_2M 0x00F
17#define BL_4M 0x01F
18#define BL_8M 0x03F
19#define BL_16M 0x07F
20#define BL_32M 0x0FF
21#define BL_64M 0x1FF
22#define BL_128M 0x3FF
23#define BL_256M 0x7FF
24
25/* BAT Access Protection */
26#define BPP_XX 0x00 /* No access */
27#define BPP_RX 0x01 /* Read only */
28#define BPP_RW 0x02 /* Read/write */
29
30#ifndef __ASSEMBLY__
31/* Contort a phys_addr_t into the right format/bits for a BAT */
32#ifdef CONFIG_PHYS_64BIT
33#define BAT_PHYS_ADDR(x) ((u32)((x & 0x00000000fffe0000ULL) | \
34 ((x & 0x0000000e00000000ULL) >> 24) | \
35 ((x & 0x0000000100000000ULL) >> 30)))
36#else
37#define BAT_PHYS_ADDR(x) (x)
38#endif
39
40struct ppc_bat {
41 u32 batu;
42 u32 batl;
43};
44#endif /* !__ASSEMBLY__ */
45
46/*
47 * Hash table
48 */
49
50/* Values for PP (assumes Ks=0, Kp=1) */
51#define PP_RWXX 0 /* Supervisor read/write, User none */
52#define PP_RWRX 1 /* Supervisor read/write, User read */
53#define PP_RWRW 2 /* Supervisor read/write, User read/write */
54#define PP_RXRX 3 /* Supervisor read, User read */
55
56#ifndef __ASSEMBLY__
57
58/* Hardware Page Table Entry */
59struct hash_pte {
60 unsigned long v:1; /* Entry is valid */
61 unsigned long vsid:24; /* Virtual segment identifier */
62 unsigned long h:1; /* Hash algorithm indicator */
63 unsigned long api:6; /* Abbreviated page index */
64 unsigned long rpn:20; /* Real (physical) page number */
65 unsigned long :3; /* Unused */
66 unsigned long r:1; /* Referenced */
67 unsigned long c:1; /* Changed */
68 unsigned long w:1; /* Write-thru cache mode */
69 unsigned long i:1; /* Cache inhibited */
70 unsigned long m:1; /* Memory coherence */
71 unsigned long g:1; /* Guarded */
72 unsigned long :1; /* Unused */
73 unsigned long pp:2; /* Page protection */
74};
75
76typedef struct {
77 unsigned long id;
78 unsigned long vdso_base;
79} mm_context_t;
80
81#endif /* !__ASSEMBLY__ */
82
83#endif /* _ASM_POWERPC_MMU_HASH32_H_ */
diff --git a/include/asm-powerpc/mmu-hash64.h b/include/asm-powerpc/mmu-hash64.h
deleted file mode 100644
index 19c7a940349..00000000000
--- a/include/asm-powerpc/mmu-hash64.h
+++ /dev/null
@@ -1,478 +0,0 @@
1#ifndef _ASM_POWERPC_MMU_HASH64_H_
2#define _ASM_POWERPC_MMU_HASH64_H_
3/*
4 * PowerPC64 memory management structures
5 *
6 * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
7 * PPC64 rework.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14
15#include <asm/asm-compat.h>
16#include <asm/page.h>
17
18/*
19 * Segment table
20 */
21
22#define STE_ESID_V 0x80
23#define STE_ESID_KS 0x20
24#define STE_ESID_KP 0x10
25#define STE_ESID_N 0x08
26
27#define STE_VSID_SHIFT 12
28
29/* Location of cpu0's segment table */
30#define STAB0_PAGE 0x6
31#define STAB0_OFFSET (STAB0_PAGE << 12)
32#define STAB0_PHYS_ADDR (STAB0_OFFSET + PHYSICAL_START)
33
34#ifndef __ASSEMBLY__
35extern char initial_stab[];
36#endif /* ! __ASSEMBLY */
37
38/*
39 * SLB
40 */
41
42#define SLB_NUM_BOLTED 3
43#define SLB_CACHE_ENTRIES 8
44
45/* Bits in the SLB ESID word */
46#define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */
47
48/* Bits in the SLB VSID word */
49#define SLB_VSID_SHIFT 12
50#define SLB_VSID_SHIFT_1T 24
51#define SLB_VSID_SSIZE_SHIFT 62
52#define SLB_VSID_B ASM_CONST(0xc000000000000000)
53#define SLB_VSID_B_256M ASM_CONST(0x0000000000000000)
54#define SLB_VSID_B_1T ASM_CONST(0x4000000000000000)
55#define SLB_VSID_KS ASM_CONST(0x0000000000000800)
56#define SLB_VSID_KP ASM_CONST(0x0000000000000400)
57#define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */
58#define SLB_VSID_L ASM_CONST(0x0000000000000100)
59#define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */
60#define SLB_VSID_LP ASM_CONST(0x0000000000000030)
61#define SLB_VSID_LP_00 ASM_CONST(0x0000000000000000)
62#define SLB_VSID_LP_01 ASM_CONST(0x0000000000000010)
63#define SLB_VSID_LP_10 ASM_CONST(0x0000000000000020)
64#define SLB_VSID_LP_11 ASM_CONST(0x0000000000000030)
65#define SLB_VSID_LLP (SLB_VSID_L|SLB_VSID_LP)
66
67#define SLB_VSID_KERNEL (SLB_VSID_KP)
68#define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)
69
70#define SLBIE_C (0x08000000)
71#define SLBIE_SSIZE_SHIFT 25
72
73/*
74 * Hash table
75 */
76
77#define HPTES_PER_GROUP 8
78
79#define HPTE_V_SSIZE_SHIFT 62
80#define HPTE_V_AVPN_SHIFT 7
81#define HPTE_V_AVPN ASM_CONST(0x3fffffffffffff80)
82#define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
83#define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & 0xffffffffffffff80UL))
84#define HPTE_V_BOLTED ASM_CONST(0x0000000000000010)
85#define HPTE_V_LOCK ASM_CONST(0x0000000000000008)
86#define HPTE_V_LARGE ASM_CONST(0x0000000000000004)
87#define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002)
88#define HPTE_V_VALID ASM_CONST(0x0000000000000001)
89
90#define HPTE_R_PP0 ASM_CONST(0x8000000000000000)
91#define HPTE_R_TS ASM_CONST(0x4000000000000000)
92#define HPTE_R_RPN_SHIFT 12
93#define HPTE_R_RPN ASM_CONST(0x3ffffffffffff000)
94#define HPTE_R_FLAGS ASM_CONST(0x00000000000003ff)
95#define HPTE_R_PP ASM_CONST(0x0000000000000003)
96#define HPTE_R_N ASM_CONST(0x0000000000000004)
97#define HPTE_R_C ASM_CONST(0x0000000000000080)
98#define HPTE_R_R ASM_CONST(0x0000000000000100)
99
100#define HPTE_V_1TB_SEG ASM_CONST(0x4000000000000000)
101#define HPTE_V_VRMA_MASK ASM_CONST(0x4001ffffff000000)
102
103/* Values for PP (assumes Ks=0, Kp=1) */
104/* pp0 will always be 0 for linux */
105#define PP_RWXX 0 /* Supervisor read/write, User none */
106#define PP_RWRX 1 /* Supervisor read/write, User read */
107#define PP_RWRW 2 /* Supervisor read/write, User read/write */
108#define PP_RXRX 3 /* Supervisor read, User read */
109
110#ifndef __ASSEMBLY__
111
112struct hash_pte {
113 unsigned long v;
114 unsigned long r;
115};
116
117extern struct hash_pte *htab_address;
118extern unsigned long htab_size_bytes;
119extern unsigned long htab_hash_mask;
120
121/*
122 * Page size definition
123 *
124 * shift : is the "PAGE_SHIFT" value for that page size
125 * sllp : is a bit mask with the value of SLB L || LP to be or'ed
126 * directly to a slbmte "vsid" value
127 * penc : is the HPTE encoding mask for the "LP" field:
128 *
129 */
130struct mmu_psize_def
131{
132 unsigned int shift; /* number of bits */
133 unsigned int penc; /* HPTE encoding */
134 unsigned int tlbiel; /* tlbiel supported for that page size */
135 unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */
136 unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */
137};
138
139#endif /* __ASSEMBLY__ */
140
141/*
142 * The kernel use the constants below to index in the page sizes array.
143 * The use of fixed constants for this purpose is better for performances
144 * of the low level hash refill handlers.
145 *
146 * A non supported page size has a "shift" field set to 0
147 *
148 * Any new page size being implemented can get a new entry in here. Whether
149 * the kernel will use it or not is a different matter though. The actual page
150 * size used by hugetlbfs is not defined here and may be made variable
151 */
152
153#define MMU_PAGE_4K 0 /* 4K */
154#define MMU_PAGE_64K 1 /* 64K */
155#define MMU_PAGE_64K_AP 2 /* 64K Admixed (in a 4K segment) */
156#define MMU_PAGE_1M 3 /* 1M */
157#define MMU_PAGE_16M 4 /* 16M */
158#define MMU_PAGE_16G 5 /* 16G */
159#define MMU_PAGE_COUNT 6
160
161/*
162 * Segment sizes.
163 * These are the values used by hardware in the B field of
164 * SLB entries and the first dword of MMU hashtable entries.
165 * The B field is 2 bits; the values 2 and 3 are unused and reserved.
166 */
167#define MMU_SEGSIZE_256M 0
168#define MMU_SEGSIZE_1T 1
169
170
171#ifndef __ASSEMBLY__
172
173/*
174 * The current system page and segment sizes
175 */
176extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
177extern int mmu_linear_psize;
178extern int mmu_virtual_psize;
179extern int mmu_vmalloc_psize;
180extern int mmu_vmemmap_psize;
181extern int mmu_io_psize;
182extern int mmu_kernel_ssize;
183extern int mmu_highuser_ssize;
184extern u16 mmu_slb_size;
185extern unsigned long tce_alloc_start, tce_alloc_end;
186
187/*
188 * If the processor supports 64k normal pages but not 64k cache
189 * inhibited pages, we have to be prepared to switch processes
190 * to use 4k pages when they create cache-inhibited mappings.
191 * If this is the case, mmu_ci_restrictions will be set to 1.
192 */
193extern int mmu_ci_restrictions;
194
195#ifdef CONFIG_HUGETLB_PAGE
196/*
197 * The page size indexes of the huge pages for use by hugetlbfs
198 */
199extern unsigned int mmu_huge_psizes[MMU_PAGE_COUNT];
200
201#endif /* CONFIG_HUGETLB_PAGE */
202
203/*
204 * This function sets the AVPN and L fields of the HPTE appropriately
205 * for the page size
206 */
207static inline unsigned long hpte_encode_v(unsigned long va, int psize,
208 int ssize)
209{
210 unsigned long v;
211 v = (va >> 23) & ~(mmu_psize_defs[psize].avpnm);
212 v <<= HPTE_V_AVPN_SHIFT;
213 if (psize != MMU_PAGE_4K)
214 v |= HPTE_V_LARGE;
215 v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
216 return v;
217}
218
219/*
220 * This function sets the ARPN, and LP fields of the HPTE appropriately
221 * for the page size. We assume the pa is already "clean" that is properly
222 * aligned for the requested page size
223 */
224static inline unsigned long hpte_encode_r(unsigned long pa, int psize)
225{
226 unsigned long r;
227
228 /* A 4K page needs no special encoding */
229 if (psize == MMU_PAGE_4K)
230 return pa & HPTE_R_RPN;
231 else {
232 unsigned int penc = mmu_psize_defs[psize].penc;
233 unsigned int shift = mmu_psize_defs[psize].shift;
234 return (pa & ~((1ul << shift) - 1)) | (penc << 12);
235 }
236 return r;
237}
238
239/*
240 * Build a VA given VSID, EA and segment size
241 */
242static inline unsigned long hpt_va(unsigned long ea, unsigned long vsid,
243 int ssize)
244{
245 if (ssize == MMU_SEGSIZE_256M)
246 return (vsid << 28) | (ea & 0xfffffffUL);
247 return (vsid << 40) | (ea & 0xffffffffffUL);
248}
249
250/*
251 * This hashes a virtual address
252 */
253
254static inline unsigned long hpt_hash(unsigned long va, unsigned int shift,
255 int ssize)
256{
257 unsigned long hash, vsid;
258
259 if (ssize == MMU_SEGSIZE_256M) {
260 hash = (va >> 28) ^ ((va & 0x0fffffffUL) >> shift);
261 } else {
262 vsid = va >> 40;
263 hash = vsid ^ (vsid << 25) ^ ((va & 0xffffffffffUL) >> shift);
264 }
265 return hash & 0x7fffffffffUL;
266}
267
268extern int __hash_page_4K(unsigned long ea, unsigned long access,
269 unsigned long vsid, pte_t *ptep, unsigned long trap,
270 unsigned int local, int ssize, int subpage_prot);
271extern int __hash_page_64K(unsigned long ea, unsigned long access,
272 unsigned long vsid, pte_t *ptep, unsigned long trap,
273 unsigned int local, int ssize);
274struct mm_struct;
275extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap);
276extern int hash_huge_page(struct mm_struct *mm, unsigned long access,
277 unsigned long ea, unsigned long vsid, int local,
278 unsigned long trap);
279
280extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
281 unsigned long pstart, unsigned long mode,
282 int psize, int ssize);
283extern void set_huge_psize(int psize);
284extern void add_gpage(unsigned long addr, unsigned long page_size,
285 unsigned long number_of_pages);
286extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr);
287
288extern void htab_initialize(void);
289extern void htab_initialize_secondary(void);
290extern void hpte_init_native(void);
291extern void hpte_init_lpar(void);
292extern void hpte_init_iSeries(void);
293extern void hpte_init_beat(void);
294extern void hpte_init_beat_v3(void);
295
296extern void stabs_alloc(void);
297extern void slb_initialize(void);
298extern void slb_flush_and_rebolt(void);
299extern void stab_initialize(unsigned long stab);
300
301extern void slb_vmalloc_update(void);
302#endif /* __ASSEMBLY__ */
303
304/*
305 * VSID allocation
306 *
307 * We first generate a 36-bit "proto-VSID". For kernel addresses this
308 * is equal to the ESID, for user addresses it is:
309 * (context << 15) | (esid & 0x7fff)
310 *
311 * The two forms are distinguishable because the top bit is 0 for user
312 * addresses, whereas the top two bits are 1 for kernel addresses.
313 * Proto-VSIDs with the top two bits equal to 0b10 are reserved for
314 * now.
315 *
316 * The proto-VSIDs are then scrambled into real VSIDs with the
317 * multiplicative hash:
318 *
319 * VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
320 * where VSID_MULTIPLIER = 268435399 = 0xFFFFFC7
321 * VSID_MODULUS = 2^36-1 = 0xFFFFFFFFF
322 *
323 * This scramble is only well defined for proto-VSIDs below
324 * 0xFFFFFFFFF, so both proto-VSID and actual VSID 0xFFFFFFFFF are
325 * reserved. VSID_MULTIPLIER is prime, so in particular it is
326 * co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
327 * Because the modulus is 2^n-1 we can compute it efficiently without
328 * a divide or extra multiply (see below).
329 *
330 * This scheme has several advantages over older methods:
331 *
332 * - We have VSIDs allocated for every kernel address
333 * (i.e. everything above 0xC000000000000000), except the very top
334 * segment, which simplifies several things.
335 *
336 * - We allow for 15 significant bits of ESID and 20 bits of
337 * context for user addresses. i.e. 8T (43 bits) of address space for
338 * up to 1M contexts (although the page table structure and context
339 * allocation will need changes to take advantage of this).
340 *
341 * - The scramble function gives robust scattering in the hash
342 * table (at least based on some initial results). The previous
343 * method was more susceptible to pathological cases giving excessive
344 * hash collisions.
345 */
346/*
347 * WARNING - If you change these you must make sure the asm
348 * implementations in slb_allocate (slb_low.S), do_stab_bolted
349 * (head.S) and ASM_VSID_SCRAMBLE (below) are changed accordingly.
350 *
351 * You'll also need to change the precomputed VSID values in head.S
352 * which are used by the iSeries firmware.
353 */
354
355#define VSID_MULTIPLIER_256M ASM_CONST(200730139) /* 28-bit prime */
356#define VSID_BITS_256M 36
357#define VSID_MODULUS_256M ((1UL<<VSID_BITS_256M)-1)
358
359#define VSID_MULTIPLIER_1T ASM_CONST(12538073) /* 24-bit prime */
360#define VSID_BITS_1T 24
361#define VSID_MODULUS_1T ((1UL<<VSID_BITS_1T)-1)
362
363#define CONTEXT_BITS 19
364#define USER_ESID_BITS 16
365#define USER_ESID_BITS_1T 4
366
367#define USER_VSID_RANGE (1UL << (USER_ESID_BITS + SID_SHIFT))
368
369/*
370 * This macro generates asm code to compute the VSID scramble
371 * function. Used in slb_allocate() and do_stab_bolted. The function
372 * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
373 *
374 * rt = register continaing the proto-VSID and into which the
375 * VSID will be stored
376 * rx = scratch register (clobbered)
377 *
378 * - rt and rx must be different registers
379 * - The answer will end up in the low VSID_BITS bits of rt. The higher
380 * bits may contain other garbage, so you may need to mask the
381 * result.
382 */
383#define ASM_VSID_SCRAMBLE(rt, rx, size) \
384 lis rx,VSID_MULTIPLIER_##size@h; \
385 ori rx,rx,VSID_MULTIPLIER_##size@l; \
386 mulld rt,rt,rx; /* rt = rt * MULTIPLIER */ \
387 \
388 srdi rx,rt,VSID_BITS_##size; \
389 clrldi rt,rt,(64-VSID_BITS_##size); \
390 add rt,rt,rx; /* add high and low bits */ \
391 /* Now, r3 == VSID (mod 2^36-1), and lies between 0 and \
392 * 2^36-1+2^28-1. That in particular means that if r3 >= \
393 * 2^36-1, then r3+1 has the 2^36 bit set. So, if r3+1 has \
394 * the bit clear, r3 already has the answer we want, if it \
395 * doesn't, the answer is the low 36 bits of r3+1. So in all \
396 * cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
397 addi rx,rt,1; \
398 srdi rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */ \
399 add rt,rt,rx
400
401
402#ifndef __ASSEMBLY__
403
404typedef unsigned long mm_context_id_t;
405
406typedef struct {
407 mm_context_id_t id;
408 u16 user_psize; /* page size index */
409
410#ifdef CONFIG_PPC_MM_SLICES
411 u64 low_slices_psize; /* SLB page size encodings */
412 u64 high_slices_psize; /* 4 bits per slice for now */
413#else
414 u16 sllp; /* SLB page size encoding */
415#endif
416 unsigned long vdso_base;
417} mm_context_t;
418
419
420#if 0
421/*
422 * The code below is equivalent to this function for arguments
423 * < 2^VSID_BITS, which is all this should ever be called
424 * with. However gcc is not clever enough to compute the
425 * modulus (2^n-1) without a second multiply.
426 */
427#define vsid_scrample(protovsid, size) \
428 ((((protovsid) * VSID_MULTIPLIER_##size) % VSID_MODULUS_##size))
429
430#else /* 1 */
431#define vsid_scramble(protovsid, size) \
432 ({ \
433 unsigned long x; \
434 x = (protovsid) * VSID_MULTIPLIER_##size; \
435 x = (x >> VSID_BITS_##size) + (x & VSID_MODULUS_##size); \
436 (x + ((x+1) >> VSID_BITS_##size)) & VSID_MODULUS_##size; \
437 })
438#endif /* 1 */
439
440/* This is only valid for addresses >= KERNELBASE */
441static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
442{
443 if (ssize == MMU_SEGSIZE_256M)
444 return vsid_scramble(ea >> SID_SHIFT, 256M);
445 return vsid_scramble(ea >> SID_SHIFT_1T, 1T);
446}
447
448/* Returns the segment size indicator for a user address */
449static inline int user_segment_size(unsigned long addr)
450{
451 /* Use 1T segments if possible for addresses >= 1T */
452 if (addr >= (1UL << SID_SHIFT_1T))
453 return mmu_highuser_ssize;
454 return MMU_SEGSIZE_256M;
455}
456
457/* This is only valid for user addresses (which are below 2^44) */
458static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
459 int ssize)
460{
461 if (ssize == MMU_SEGSIZE_256M)
462 return vsid_scramble((context << USER_ESID_BITS)
463 | (ea >> SID_SHIFT), 256M);
464 return vsid_scramble((context << USER_ESID_BITS_1T)
465 | (ea >> SID_SHIFT_1T), 1T);
466}
467
468/*
469 * This is only used on legacy iSeries in lparmap.c,
470 * hence the 256MB segment assumption.
471 */
472#define VSID_SCRAMBLE(pvsid) (((pvsid) * VSID_MULTIPLIER_256M) % \
473 VSID_MODULUS_256M)
474#define KERNEL_VSID(ea) VSID_SCRAMBLE(GET_ESID(ea))
475
476#endif /* __ASSEMBLY__ */
477
478#endif /* _ASM_POWERPC_MMU_HASH64_H_ */
diff --git a/include/asm-powerpc/mmu.h b/include/asm-powerpc/mmu.h
deleted file mode 100644
index 4c0e1b4f975..00000000000
--- a/include/asm-powerpc/mmu.h
+++ /dev/null
@@ -1,26 +0,0 @@
1#ifndef _ASM_POWERPC_MMU_H_
2#define _ASM_POWERPC_MMU_H_
3#ifdef __KERNEL__
4
5#ifdef CONFIG_PPC64
6/* 64-bit classic hash table MMU */
7# include <asm/mmu-hash64.h>
8#elif defined(CONFIG_PPC_STD_MMU)
9/* 32-bit classic hash table MMU */
10# include <asm/mmu-hash32.h>
11#elif defined(CONFIG_40x)
12/* 40x-style software loaded TLB */
13# include <asm/mmu-40x.h>
14#elif defined(CONFIG_44x)
15/* 44x-style software loaded TLB */
16# include <asm/mmu-44x.h>
17#elif defined(CONFIG_FSL_BOOKE)
18/* Freescale Book-E software loaded TLB */
19# include <asm/mmu-fsl-booke.h>
20#elif defined (CONFIG_PPC_8xx)
21/* Motorola/Freescale 8xx software loaded TLB */
22# include <asm/mmu-8xx.h>
23#endif
24
25#endif /* __KERNEL__ */
26#endif /* _ASM_POWERPC_MMU_H_ */
diff --git a/include/asm-powerpc/mmu_context.h b/include/asm-powerpc/mmu_context.h
deleted file mode 100644
index 9102b8bf0ea..00000000000
--- a/include/asm-powerpc/mmu_context.h
+++ /dev/null
@@ -1,280 +0,0 @@
1#ifndef __ASM_POWERPC_MMU_CONTEXT_H
2#define __ASM_POWERPC_MMU_CONTEXT_H
3#ifdef __KERNEL__
4
5#include <asm/mmu.h>
6#include <asm/cputable.h>
7#include <asm-generic/mm_hooks.h>
8
9#ifndef CONFIG_PPC64
10#include <asm/atomic.h>
11#include <linux/bitops.h>
12
13/*
14 * On 32-bit PowerPC 6xx/7xx/7xxx CPUs, we use a set of 16 VSIDs
15 * (virtual segment identifiers) for each context. Although the
16 * hardware supports 24-bit VSIDs, and thus >1 million contexts,
17 * we only use 32,768 of them. That is ample, since there can be
18 * at most around 30,000 tasks in the system anyway, and it means
19 * that we can use a bitmap to indicate which contexts are in use.
20 * Using a bitmap means that we entirely avoid all of the problems
21 * that we used to have when the context number overflowed,
22 * particularly on SMP systems.
23 * -- paulus.
24 */
25
26/*
27 * This function defines the mapping from contexts to VSIDs (virtual
28 * segment IDs). We use a skew on both the context and the high 4 bits
29 * of the 32-bit virtual address (the "effective segment ID") in order
30 * to spread out the entries in the MMU hash table. Note, if this
31 * function is changed then arch/ppc/mm/hashtable.S will have to be
32 * changed to correspond.
33 */
34#define CTX_TO_VSID(ctx, va) (((ctx) * (897 * 16) + ((va) >> 28) * 0x111) \
35 & 0xffffff)
36
37/*
38 The MPC8xx has only 16 contexts. We rotate through them on each
39 task switch. A better way would be to keep track of tasks that
40 own contexts, and implement an LRU usage. That way very active
41 tasks don't always have to pay the TLB reload overhead. The
42 kernel pages are mapped shared, so the kernel can run on behalf
43 of any task that makes a kernel entry. Shared does not mean they
44 are not protected, just that the ASID comparison is not performed.
45 -- Dan
46
47 The IBM4xx has 256 contexts, so we can just rotate through these
48 as a way of "switching" contexts. If the TID of the TLB is zero,
49 the PID/TID comparison is disabled, so we can use a TID of zero
50 to represent all kernel pages as shared among all contexts.
51 -- Dan
52 */
53
54static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
55{
56}
57
58#ifdef CONFIG_8xx
59#define NO_CONTEXT 16
60#define LAST_CONTEXT 15
61#define FIRST_CONTEXT 0
62
63#elif defined(CONFIG_4xx)
64#define NO_CONTEXT 256
65#define LAST_CONTEXT 255
66#define FIRST_CONTEXT 1
67
68#elif defined(CONFIG_E200) || defined(CONFIG_E500)
69#define NO_CONTEXT 256
70#define LAST_CONTEXT 255
71#define FIRST_CONTEXT 1
72
73#else
74
75/* PPC 6xx, 7xx CPUs */
76#define NO_CONTEXT ((unsigned long) -1)
77#define LAST_CONTEXT 32767
78#define FIRST_CONTEXT 1
79#endif
80
81/*
82 * Set the current MMU context.
83 * On 32-bit PowerPCs (other than the 8xx embedded chips), this is done by
84 * loading up the segment registers for the user part of the address space.
85 *
86 * Since the PGD is immediately available, it is much faster to simply
87 * pass this along as a second parameter, which is required for 8xx and
88 * can be used for debugging on all processors (if you happen to have
89 * an Abatron).
90 */
91extern void set_context(unsigned long contextid, pgd_t *pgd);
92
93/*
94 * Bitmap of contexts in use.
95 * The size of this bitmap is LAST_CONTEXT + 1 bits.
96 */
97extern unsigned long context_map[];
98
99/*
100 * This caches the next context number that we expect to be free.
101 * Its use is an optimization only, we can't rely on this context
102 * number to be free, but it usually will be.
103 */
104extern unsigned long next_mmu_context;
105
106/*
107 * If we don't have sufficient contexts to give one to every task
108 * that could be in the system, we need to be able to steal contexts.
109 * These variables support that.
110 */
111#if LAST_CONTEXT < 30000
112#define FEW_CONTEXTS 1
113extern atomic_t nr_free_contexts;
114extern struct mm_struct *context_mm[LAST_CONTEXT+1];
115extern void steal_context(void);
116#endif
117
118/*
119 * Get a new mmu context for the address space described by `mm'.
120 */
121static inline void get_mmu_context(struct mm_struct *mm)
122{
123 unsigned long ctx;
124
125 if (mm->context.id != NO_CONTEXT)
126 return;
127#ifdef FEW_CONTEXTS
128 while (atomic_dec_if_positive(&nr_free_contexts) < 0)
129 steal_context();
130#endif
131 ctx = next_mmu_context;
132 while (test_and_set_bit(ctx, context_map)) {
133 ctx = find_next_zero_bit(context_map, LAST_CONTEXT+1, ctx);
134 if (ctx > LAST_CONTEXT)
135 ctx = 0;
136 }
137 next_mmu_context = (ctx + 1) & LAST_CONTEXT;
138 mm->context.id = ctx;
139#ifdef FEW_CONTEXTS
140 context_mm[ctx] = mm;
141#endif
142}
143
144/*
145 * Set up the context for a new address space.
146 */
147static inline int init_new_context(struct task_struct *t, struct mm_struct *mm)
148{
149 mm->context.id = NO_CONTEXT;
150 mm->context.vdso_base = 0;
151 return 0;
152}
153
154/*
155 * We're finished using the context for an address space.
156 */
157static inline void destroy_context(struct mm_struct *mm)
158{
159 preempt_disable();
160 if (mm->context.id != NO_CONTEXT) {
161 clear_bit(mm->context.id, context_map);
162 mm->context.id = NO_CONTEXT;
163#ifdef FEW_CONTEXTS
164 atomic_inc(&nr_free_contexts);
165#endif
166 }
167 preempt_enable();
168}
169
170static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
171 struct task_struct *tsk)
172{
173#ifdef CONFIG_ALTIVEC
174 if (cpu_has_feature(CPU_FTR_ALTIVEC))
175 asm volatile ("dssall;\n"
176#ifndef CONFIG_POWER4
177 "sync;\n" /* G4 needs a sync here, G5 apparently not */
178#endif
179 : : );
180#endif /* CONFIG_ALTIVEC */
181
182 tsk->thread.pgdir = next->pgd;
183
184 /* No need to flush userspace segments if the mm doesnt change */
185 if (prev == next)
186 return;
187
188 /* Setup new userspace context */
189 get_mmu_context(next);
190 set_context(next->context.id, next->pgd);
191}
192
193#define deactivate_mm(tsk,mm) do { } while (0)
194
195/*
196 * After we have set current->mm to a new value, this activates
197 * the context for the new mm so we see the new mappings.
198 */
199#define activate_mm(active_mm, mm) switch_mm(active_mm, mm, current)
200
201extern void mmu_context_init(void);
202
203
204#else
205
206#include <linux/kernel.h>
207#include <linux/mm.h>
208#include <linux/sched.h>
209
210/*
211 * Copyright (C) 2001 PPC 64 Team, IBM Corp
212 *
213 * This program is free software; you can redistribute it and/or
214 * modify it under the terms of the GNU General Public License
215 * as published by the Free Software Foundation; either version
216 * 2 of the License, or (at your option) any later version.
217 */
218
219static inline void enter_lazy_tlb(struct mm_struct *mm,
220 struct task_struct *tsk)
221{
222}
223
224/*
225 * The proto-VSID space has 2^35 - 1 segments available for user mappings.
226 * Each segment contains 2^28 bytes. Each context maps 2^44 bytes,
227 * so we can support 2^19-1 contexts (19 == 35 + 28 - 44).
228 */
229#define NO_CONTEXT 0
230#define MAX_CONTEXT ((1UL << 19) - 1)
231
232extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
233extern void destroy_context(struct mm_struct *mm);
234
235extern void switch_stab(struct task_struct *tsk, struct mm_struct *mm);
236extern void switch_slb(struct task_struct *tsk, struct mm_struct *mm);
237
238/*
239 * switch_mm is the entry point called from the architecture independent
240 * code in kernel/sched.c
241 */
242static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
243 struct task_struct *tsk)
244{
245 if (!cpu_isset(smp_processor_id(), next->cpu_vm_mask))
246 cpu_set(smp_processor_id(), next->cpu_vm_mask);
247
248 /* No need to flush userspace segments if the mm doesnt change */
249 if (prev == next)
250 return;
251
252#ifdef CONFIG_ALTIVEC
253 if (cpu_has_feature(CPU_FTR_ALTIVEC))
254 asm volatile ("dssall");
255#endif /* CONFIG_ALTIVEC */
256
257 if (cpu_has_feature(CPU_FTR_SLB))
258 switch_slb(tsk, next);
259 else
260 switch_stab(tsk, next);
261}
262
263#define deactivate_mm(tsk,mm) do { } while (0)
264
265/*
266 * After we have set current->mm to a new value, this activates
267 * the context for the new mm so we see the new mappings.
268 */
269static inline void activate_mm(struct mm_struct *prev, struct mm_struct *next)
270{
271 unsigned long flags;
272
273 local_irq_save(flags);
274 switch_mm(prev, next, current);
275 local_irq_restore(flags);
276}
277
278#endif /* CONFIG_PPC64 */
279#endif /* __KERNEL__ */
280#endif /* __ASM_POWERPC_MMU_CONTEXT_H */
diff --git a/include/asm-powerpc/mmzone.h b/include/asm-powerpc/mmzone.h
deleted file mode 100644
index 19f299b7e25..00000000000
--- a/include/asm-powerpc/mmzone.h
+++ /dev/null
@@ -1,47 +0,0 @@
1/*
2 * Written by Kanoj Sarcar (kanoj@sgi.com) Aug 99
3 *
4 * PowerPC64 port:
5 * Copyright (C) 2002 Anton Blanchard, IBM Corp.
6 */
7#ifndef _ASM_MMZONE_H_
8#define _ASM_MMZONE_H_
9#ifdef __KERNEL__
10
11
12/*
13 * generic non-linear memory support:
14 *
15 * 1) we will not split memory into more chunks than will fit into the
16 * flags field of the struct page
17 */
18
19#ifdef CONFIG_NEED_MULTIPLE_NODES
20
21extern struct pglist_data *node_data[];
22/*
23 * Return a pointer to the node data for node n.
24 */
25#define NODE_DATA(nid) (node_data[nid])
26
27/*
28 * Following are specific to this numa platform.
29 */
30
31extern int numa_cpu_lookup_table[];
32extern cpumask_t numa_cpumask_lookup_table[];
33#ifdef CONFIG_MEMORY_HOTPLUG
34extern unsigned long max_pfn;
35#endif
36
37/*
38 * Following are macros that each numa implmentation must define.
39 */
40
41#define node_start_pfn(nid) (NODE_DATA(nid)->node_start_pfn)
42#define node_end_pfn(nid) (NODE_DATA(nid)->node_end_pfn)
43
44#endif /* CONFIG_NEED_MULTIPLE_NODES */
45
46#endif /* __KERNEL__ */
47#endif /* _ASM_MMZONE_H_ */
diff --git a/include/asm-powerpc/module.h b/include/asm-powerpc/module.h
deleted file mode 100644
index e5f14b13ccf..00000000000
--- a/include/asm-powerpc/module.h
+++ /dev/null
@@ -1,77 +0,0 @@
1#ifndef _ASM_POWERPC_MODULE_H
2#define _ASM_POWERPC_MODULE_H
3#ifdef __KERNEL__
4
5/*
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#include <linux/list.h>
13#include <asm/bug.h>
14
15
16#ifndef __powerpc64__
17/*
18 * Thanks to Paul M for explaining this.
19 *
20 * PPC can only do rel jumps += 32MB, and often the kernel and other
21 * modules are furthur away than this. So, we jump to a table of
22 * trampolines attached to the module (the Procedure Linkage Table)
23 * whenever that happens.
24 */
25
26struct ppc_plt_entry {
27 /* 16 byte jump instruction sequence (4 instructions) */
28 unsigned int jump[4];
29};
30#endif /* __powerpc64__ */
31
32
33struct mod_arch_specific {
34#ifdef __powerpc64__
35 unsigned int stubs_section; /* Index of stubs section in module */
36 unsigned int toc_section; /* What section is the TOC? */
37#else
38 /* Indices of PLT sections within module. */
39 unsigned int core_plt_section;
40 unsigned int init_plt_section;
41#endif
42
43 /* List of BUG addresses, source line numbers and filenames */
44 struct list_head bug_list;
45 struct bug_entry *bug_table;
46 unsigned int num_bugs;
47};
48
49/*
50 * Select ELF headers.
51 * Make empty section for module_frob_arch_sections to expand.
52 */
53
54#ifdef __powerpc64__
55# define Elf_Shdr Elf64_Shdr
56# define Elf_Sym Elf64_Sym
57# define Elf_Ehdr Elf64_Ehdr
58# ifdef MODULE
59 asm(".section .stubs,\"ax\",@nobits; .align 3; .previous");
60# endif
61#else
62# define Elf_Shdr Elf32_Shdr
63# define Elf_Sym Elf32_Sym
64# define Elf_Ehdr Elf32_Ehdr
65# ifdef MODULE
66 asm(".section .plt,\"ax\",@nobits; .align 3; .previous");
67 asm(".section .init.plt,\"ax\",@nobits; .align 3; .previous");
68# endif /* MODULE */
69#endif
70
71
72struct exception_table_entry;
73void sort_ex_table(struct exception_table_entry *start,
74 struct exception_table_entry *finish);
75
76#endif /* __KERNEL__ */
77#endif /* _ASM_POWERPC_MODULE_H */
diff --git a/include/asm-powerpc/mpc512x.h b/include/asm-powerpc/mpc512x.h
deleted file mode 100644
index c48a1658eea..00000000000
--- a/include/asm-powerpc/mpc512x.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
3 *
4 * Author: John Rigby, <jrigby@freescale.com>, Friday Apr 13 2007
5 *
6 * Description:
7 * MPC5121 Prototypes and definitions
8 *
9 * This is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 */
15
16#ifndef __ASM_POWERPC_MPC512x_H__
17#define __ASM_POWERPC_MPC512x_H__
18
19extern unsigned long mpc512x_find_ips_freq(struct device_node *node);
20
21#endif /* __ASM_POWERPC_MPC512x_H__ */
22
diff --git a/include/asm-powerpc/mpc52xx.h b/include/asm-powerpc/mpc52xx.h
deleted file mode 100644
index 81ef10b6b67..00000000000
--- a/include/asm-powerpc/mpc52xx.h
+++ /dev/null
@@ -1,295 +0,0 @@
1/*
2 * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips
3 * May need to be cleaned as the port goes on ...
4 *
5 * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
6 * Copyright (C) 2003 MontaVista, Software, Inc.
7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
13#ifndef __ASM_POWERPC_MPC52xx_H__
14#define __ASM_POWERPC_MPC52xx_H__
15
16#ifndef __ASSEMBLY__
17#include <asm/types.h>
18#include <asm/prom.h>
19#endif /* __ASSEMBLY__ */
20
21#include <linux/suspend.h>
22
23/* Variants of the 5200(B) */
24#define MPC5200_SVR 0x80110010
25#define MPC5200_SVR_MASK 0xfffffff0
26#define MPC5200B_SVR 0x80110020
27#define MPC5200B_SVR_MASK 0xfffffff0
28
29/* ======================================================================== */
30/* Structures mapping of some unit register set */
31/* ======================================================================== */
32
33#ifndef __ASSEMBLY__
34
35/* Memory Mapping Control */
36struct mpc52xx_mmap_ctl {
37 u32 mbar; /* MMAP_CTRL + 0x00 */
38
39 u32 cs0_start; /* MMAP_CTRL + 0x04 */
40 u32 cs0_stop; /* MMAP_CTRL + 0x08 */
41 u32 cs1_start; /* MMAP_CTRL + 0x0c */
42 u32 cs1_stop; /* MMAP_CTRL + 0x10 */
43 u32 cs2_start; /* MMAP_CTRL + 0x14 */
44 u32 cs2_stop; /* MMAP_CTRL + 0x18 */
45 u32 cs3_start; /* MMAP_CTRL + 0x1c */
46 u32 cs3_stop; /* MMAP_CTRL + 0x20 */
47 u32 cs4_start; /* MMAP_CTRL + 0x24 */
48 u32 cs4_stop; /* MMAP_CTRL + 0x28 */
49 u32 cs5_start; /* MMAP_CTRL + 0x2c */
50 u32 cs5_stop; /* MMAP_CTRL + 0x30 */
51
52 u32 sdram0; /* MMAP_CTRL + 0x34 */
53 u32 sdram1; /* MMAP_CTRL + 0X38 */
54
55 u32 reserved[4]; /* MMAP_CTRL + 0x3c .. 0x48 */
56
57 u32 boot_start; /* MMAP_CTRL + 0x4c */
58 u32 boot_stop; /* MMAP_CTRL + 0x50 */
59
60 u32 ipbi_ws_ctrl; /* MMAP_CTRL + 0x54 */
61
62 u32 cs6_start; /* MMAP_CTRL + 0x58 */
63 u32 cs6_stop; /* MMAP_CTRL + 0x5c */
64 u32 cs7_start; /* MMAP_CTRL + 0x60 */
65 u32 cs7_stop; /* MMAP_CTRL + 0x64 */
66};
67
68/* SDRAM control */
69struct mpc52xx_sdram {
70 u32 mode; /* SDRAM + 0x00 */
71 u32 ctrl; /* SDRAM + 0x04 */
72 u32 config1; /* SDRAM + 0x08 */
73 u32 config2; /* SDRAM + 0x0c */
74};
75
76/* SDMA */
77struct mpc52xx_sdma {
78 u32 taskBar; /* SDMA + 0x00 */
79 u32 currentPointer; /* SDMA + 0x04 */
80 u32 endPointer; /* SDMA + 0x08 */
81 u32 variablePointer; /* SDMA + 0x0c */
82
83 u8 IntVect1; /* SDMA + 0x10 */
84 u8 IntVect2; /* SDMA + 0x11 */
85 u16 PtdCntrl; /* SDMA + 0x12 */
86
87 u32 IntPend; /* SDMA + 0x14 */
88 u32 IntMask; /* SDMA + 0x18 */
89
90 u16 tcr[16]; /* SDMA + 0x1c .. 0x3a */
91
92 u8 ipr[32]; /* SDMA + 0x3c .. 0x5b */
93
94 u32 cReqSelect; /* SDMA + 0x5c */
95 u32 task_size0; /* SDMA + 0x60 */
96 u32 task_size1; /* SDMA + 0x64 */
97 u32 MDEDebug; /* SDMA + 0x68 */
98 u32 ADSDebug; /* SDMA + 0x6c */
99 u32 Value1; /* SDMA + 0x70 */
100 u32 Value2; /* SDMA + 0x74 */
101 u32 Control; /* SDMA + 0x78 */
102 u32 Status; /* SDMA + 0x7c */
103 u32 PTDDebug; /* SDMA + 0x80 */
104};
105
106/* GPT */
107struct mpc52xx_gpt {
108 u32 mode; /* GPTx + 0x00 */
109 u32 count; /* GPTx + 0x04 */
110 u32 pwm; /* GPTx + 0x08 */
111 u32 status; /* GPTx + 0X0c */
112};
113
114/* GPIO */
115struct mpc52xx_gpio {
116 u32 port_config; /* GPIO + 0x00 */
117 u32 simple_gpioe; /* GPIO + 0x04 */
118 u32 simple_ode; /* GPIO + 0x08 */
119 u32 simple_ddr; /* GPIO + 0x0c */
120 u32 simple_dvo; /* GPIO + 0x10 */
121 u32 simple_ival; /* GPIO + 0x14 */
122 u8 outo_gpioe; /* GPIO + 0x18 */
123 u8 reserved1[3]; /* GPIO + 0x19 */
124 u8 outo_dvo; /* GPIO + 0x1c */
125 u8 reserved2[3]; /* GPIO + 0x1d */
126 u8 sint_gpioe; /* GPIO + 0x20 */
127 u8 reserved3[3]; /* GPIO + 0x21 */
128 u8 sint_ode; /* GPIO + 0x24 */
129 u8 reserved4[3]; /* GPIO + 0x25 */
130 u8 sint_ddr; /* GPIO + 0x28 */
131 u8 reserved5[3]; /* GPIO + 0x29 */
132 u8 sint_dvo; /* GPIO + 0x2c */
133 u8 reserved6[3]; /* GPIO + 0x2d */
134 u8 sint_inten; /* GPIO + 0x30 */
135 u8 reserved7[3]; /* GPIO + 0x31 */
136 u16 sint_itype; /* GPIO + 0x34 */
137 u16 reserved8; /* GPIO + 0x36 */
138 u8 gpio_control; /* GPIO + 0x38 */
139 u8 reserved9[3]; /* GPIO + 0x39 */
140 u8 sint_istat; /* GPIO + 0x3c */
141 u8 sint_ival; /* GPIO + 0x3d */
142 u8 bus_errs; /* GPIO + 0x3e */
143 u8 reserved10; /* GPIO + 0x3f */
144};
145
146#define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD 4
147#define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD 5
148#define MPC52xx_GPIO_PCI_DIS (1<<15)
149
150/* GPIO with WakeUp*/
151struct mpc52xx_gpio_wkup {
152 u8 wkup_gpioe; /* GPIO_WKUP + 0x00 */
153 u8 reserved1[3]; /* GPIO_WKUP + 0x03 */
154 u8 wkup_ode; /* GPIO_WKUP + 0x04 */
155 u8 reserved2[3]; /* GPIO_WKUP + 0x05 */
156 u8 wkup_ddr; /* GPIO_WKUP + 0x08 */
157 u8 reserved3[3]; /* GPIO_WKUP + 0x09 */
158 u8 wkup_dvo; /* GPIO_WKUP + 0x0C */
159 u8 reserved4[3]; /* GPIO_WKUP + 0x0D */
160 u8 wkup_inten; /* GPIO_WKUP + 0x10 */
161 u8 reserved5[3]; /* GPIO_WKUP + 0x11 */
162 u8 wkup_iinten; /* GPIO_WKUP + 0x14 */
163 u8 reserved6[3]; /* GPIO_WKUP + 0x15 */
164 u16 wkup_itype; /* GPIO_WKUP + 0x18 */
165 u8 reserved7[2]; /* GPIO_WKUP + 0x1A */
166 u8 wkup_maste; /* GPIO_WKUP + 0x1C */
167 u8 reserved8[3]; /* GPIO_WKUP + 0x1D */
168 u8 wkup_ival; /* GPIO_WKUP + 0x20 */
169 u8 reserved9[3]; /* GPIO_WKUP + 0x21 */
170 u8 wkup_istat; /* GPIO_WKUP + 0x24 */
171 u8 reserved10[3]; /* GPIO_WKUP + 0x25 */
172};
173
174/* XLB Bus control */
175struct mpc52xx_xlb {
176 u8 reserved[0x40];
177 u32 config; /* XLB + 0x40 */
178 u32 version; /* XLB + 0x44 */
179 u32 status; /* XLB + 0x48 */
180 u32 int_enable; /* XLB + 0x4c */
181 u32 addr_capture; /* XLB + 0x50 */
182 u32 bus_sig_capture; /* XLB + 0x54 */
183 u32 addr_timeout; /* XLB + 0x58 */
184 u32 data_timeout; /* XLB + 0x5c */
185 u32 bus_act_timeout; /* XLB + 0x60 */
186 u32 master_pri_enable; /* XLB + 0x64 */
187 u32 master_priority; /* XLB + 0x68 */
188 u32 base_address; /* XLB + 0x6c */
189 u32 snoop_window; /* XLB + 0x70 */
190};
191
192#define MPC52xx_XLB_CFG_PLDIS (1 << 31)
193#define MPC52xx_XLB_CFG_SNOOP (1 << 15)
194
195/* Clock Distribution control */
196struct mpc52xx_cdm {
197 u32 jtag_id; /* CDM + 0x00 reg0 read only */
198 u32 rstcfg; /* CDM + 0x04 reg1 read only */
199 u32 breadcrumb; /* CDM + 0x08 reg2 */
200
201 u8 mem_clk_sel; /* CDM + 0x0c reg3 byte0 */
202 u8 xlb_clk_sel; /* CDM + 0x0d reg3 byte1 read only */
203 u8 ipb_clk_sel; /* CDM + 0x0e reg3 byte2 */
204 u8 pci_clk_sel; /* CDM + 0x0f reg3 byte3 */
205
206 u8 ext_48mhz_en; /* CDM + 0x10 reg4 byte0 */
207 u8 fd_enable; /* CDM + 0x11 reg4 byte1 */
208 u16 fd_counters; /* CDM + 0x12 reg4 byte2,3 */
209
210 u32 clk_enables; /* CDM + 0x14 reg5 */
211
212 u8 osc_disable; /* CDM + 0x18 reg6 byte0 */
213 u8 reserved0[3]; /* CDM + 0x19 reg6 byte1,2,3 */
214
215 u8 ccs_sleep_enable; /* CDM + 0x1c reg7 byte0 */
216 u8 osc_sleep_enable; /* CDM + 0x1d reg7 byte1 */
217 u8 reserved1; /* CDM + 0x1e reg7 byte2 */
218 u8 ccs_qreq_test; /* CDM + 0x1f reg7 byte3 */
219
220 u8 soft_reset; /* CDM + 0x20 u8 byte0 */
221 u8 no_ckstp; /* CDM + 0x21 u8 byte0 */
222 u8 reserved2[2]; /* CDM + 0x22 u8 byte1,2,3 */
223
224 u8 pll_lock; /* CDM + 0x24 reg9 byte0 */
225 u8 pll_looselock; /* CDM + 0x25 reg9 byte1 */
226 u8 pll_sm_lockwin; /* CDM + 0x26 reg9 byte2 */
227 u8 reserved3; /* CDM + 0x27 reg9 byte3 */
228
229 u16 reserved4; /* CDM + 0x28 reg10 byte0,1 */
230 u16 mclken_div_psc1; /* CDM + 0x2a reg10 byte2,3 */
231
232 u16 reserved5; /* CDM + 0x2c reg11 byte0,1 */
233 u16 mclken_div_psc2; /* CDM + 0x2e reg11 byte2,3 */
234
235 u16 reserved6; /* CDM + 0x30 reg12 byte0,1 */
236 u16 mclken_div_psc3; /* CDM + 0x32 reg12 byte2,3 */
237
238 u16 reserved7; /* CDM + 0x34 reg13 byte0,1 */
239 u16 mclken_div_psc6; /* CDM + 0x36 reg13 byte2,3 */
240};
241
242#endif /* __ASSEMBLY__ */
243
244
245/* ========================================================================= */
246/* Prototypes for MPC52xx sysdev */
247/* ========================================================================= */
248
249#ifndef __ASSEMBLY__
250
251/* mpc52xx_common.c */
252extern unsigned int mpc52xx_find_ipb_freq(struct device_node *node);
253extern void mpc5200_setup_xlb_arbiter(void);
254extern void mpc52xx_declare_of_platform_devices(void);
255extern void mpc52xx_map_common_devices(void);
256extern int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv);
257extern void mpc52xx_restart(char *cmd);
258
259/* mpc52xx_pic.c */
260extern void mpc52xx_init_irq(void);
261extern unsigned int mpc52xx_get_irq(void);
262
263/* mpc52xx_pci.c */
264#ifdef CONFIG_PCI
265extern int __init mpc52xx_add_bridge(struct device_node *node);
266extern void __init mpc52xx_setup_pci(void);
267#else
268static inline void mpc52xx_setup_pci(void) { }
269#endif
270
271#endif /* __ASSEMBLY__ */
272
273#ifdef CONFIG_PM
274struct mpc52xx_suspend {
275 void (*board_suspend_prepare)(void __iomem *mbar);
276 void (*board_resume_finish)(void __iomem *mbar);
277};
278
279extern struct mpc52xx_suspend mpc52xx_suspend;
280extern int __init mpc52xx_pm_init(void);
281extern int mpc52xx_set_wakeup_gpio(u8 pin, u8 level);
282
283#ifdef CONFIG_PPC_LITE5200
284extern int __init lite5200_pm_init(void);
285
286/* lite5200 calls mpc5200 suspend functions, so here they are */
287extern int mpc52xx_pm_prepare(void);
288extern int mpc52xx_pm_enter(suspend_state_t);
289extern void mpc52xx_pm_finish(void);
290extern char saved_sram[0x4000]; /* reuse buffer from mpc52xx suspend */
291#endif
292#endif /* CONFIG_PM */
293
294#endif /* __ASM_POWERPC_MPC52xx_H__ */
295
diff --git a/include/asm-powerpc/mpc52xx_psc.h b/include/asm-powerpc/mpc52xx_psc.h
deleted file mode 100644
index 8917ed63056..00000000000
--- a/include/asm-powerpc/mpc52xx_psc.h
+++ /dev/null
@@ -1,276 +0,0 @@
1/*
2 * include/asm-ppc/mpc52xx_psc.h
3 *
4 * Definitions of consts/structs to drive the Freescale MPC52xx OnChip
5 * PSCs. Theses are shared between multiple drivers since a PSC can be
6 * UART, AC97, IR, I2S, ... So this header is in asm-ppc.
7 *
8 *
9 * Maintainer : Sylvain Munaut <tnt@246tNt.com>
10 *
11 * Based/Extracted from some header of the 2.4 originally written by
12 * Dale Farnsworth <dfarnsworth@mvista.com>
13 *
14 * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
15 * Copyright (C) 2003 MontaVista, Software, Inc.
16 *
17 * This file is licensed under the terms of the GNU General Public License
18 * version 2. This program is licensed "as is" without any warranty of any
19 * kind, whether express or implied.
20 */
21
22#ifndef __ASM_MPC52xx_PSC_H__
23#define __ASM_MPC52xx_PSC_H__
24
25#include <asm/types.h>
26
27/* Max number of PSCs */
28#define MPC52xx_PSC_MAXNUM 6
29
30/* Programmable Serial Controller (PSC) status register bits */
31#define MPC52xx_PSC_SR_CDE 0x0080
32#define MPC52xx_PSC_SR_RXRDY 0x0100
33#define MPC52xx_PSC_SR_RXFULL 0x0200
34#define MPC52xx_PSC_SR_TXRDY 0x0400
35#define MPC52xx_PSC_SR_TXEMP 0x0800
36#define MPC52xx_PSC_SR_OE 0x1000
37#define MPC52xx_PSC_SR_PE 0x2000
38#define MPC52xx_PSC_SR_FE 0x4000
39#define MPC52xx_PSC_SR_RB 0x8000
40
41/* PSC Command values */
42#define MPC52xx_PSC_RX_ENABLE 0x0001
43#define MPC52xx_PSC_RX_DISABLE 0x0002
44#define MPC52xx_PSC_TX_ENABLE 0x0004
45#define MPC52xx_PSC_TX_DISABLE 0x0008
46#define MPC52xx_PSC_SEL_MODE_REG_1 0x0010
47#define MPC52xx_PSC_RST_RX 0x0020
48#define MPC52xx_PSC_RST_TX 0x0030
49#define MPC52xx_PSC_RST_ERR_STAT 0x0040
50#define MPC52xx_PSC_RST_BRK_CHG_INT 0x0050
51#define MPC52xx_PSC_START_BRK 0x0060
52#define MPC52xx_PSC_STOP_BRK 0x0070
53
54/* PSC TxRx FIFO status bits */
55#define MPC52xx_PSC_RXTX_FIFO_ERR 0x0040
56#define MPC52xx_PSC_RXTX_FIFO_UF 0x0020
57#define MPC52xx_PSC_RXTX_FIFO_OF 0x0010
58#define MPC52xx_PSC_RXTX_FIFO_FR 0x0008
59#define MPC52xx_PSC_RXTX_FIFO_FULL 0x0004
60#define MPC52xx_PSC_RXTX_FIFO_ALARM 0x0002
61#define MPC52xx_PSC_RXTX_FIFO_EMPTY 0x0001
62
63/* PSC interrupt status/mask bits */
64#define MPC52xx_PSC_IMR_TXRDY 0x0100
65#define MPC52xx_PSC_IMR_RXRDY 0x0200
66#define MPC52xx_PSC_IMR_DB 0x0400
67#define MPC52xx_PSC_IMR_TXEMP 0x0800
68#define MPC52xx_PSC_IMR_ORERR 0x1000
69#define MPC52xx_PSC_IMR_IPC 0x8000
70
71/* PSC input port change bit */
72#define MPC52xx_PSC_CTS 0x01
73#define MPC52xx_PSC_DCD 0x02
74#define MPC52xx_PSC_D_CTS 0x10
75#define MPC52xx_PSC_D_DCD 0x20
76
77/* PSC mode fields */
78#define MPC52xx_PSC_MODE_5_BITS 0x00
79#define MPC52xx_PSC_MODE_6_BITS 0x01
80#define MPC52xx_PSC_MODE_7_BITS 0x02
81#define MPC52xx_PSC_MODE_8_BITS 0x03
82#define MPC52xx_PSC_MODE_BITS_MASK 0x03
83#define MPC52xx_PSC_MODE_PAREVEN 0x00
84#define MPC52xx_PSC_MODE_PARODD 0x04
85#define MPC52xx_PSC_MODE_PARFORCE 0x08
86#define MPC52xx_PSC_MODE_PARNONE 0x10
87#define MPC52xx_PSC_MODE_ERR 0x20
88#define MPC52xx_PSC_MODE_FFULL 0x40
89#define MPC52xx_PSC_MODE_RXRTS 0x80
90
91#define MPC52xx_PSC_MODE_ONE_STOP_5_BITS 0x00
92#define MPC52xx_PSC_MODE_ONE_STOP 0x07
93#define MPC52xx_PSC_MODE_TWO_STOP 0x0f
94
95#define MPC52xx_PSC_RFNUM_MASK 0x01ff
96
97#define MPC52xx_PSC_SICR_DTS1 (1 << 29)
98#define MPC52xx_PSC_SICR_SHDR (1 << 28)
99#define MPC52xx_PSC_SICR_SIM_MASK (0xf << 24)
100#define MPC52xx_PSC_SICR_SIM_UART (0x0 << 24)
101#define MPC52xx_PSC_SICR_SIM_UART_DCD (0x8 << 24)
102#define MPC52xx_PSC_SICR_SIM_CODEC_8 (0x1 << 24)
103#define MPC52xx_PSC_SICR_SIM_CODEC_16 (0x2 << 24)
104#define MPC52xx_PSC_SICR_SIM_AC97 (0x3 << 24)
105#define MPC52xx_PSC_SICR_SIM_SIR (0x8 << 24)
106#define MPC52xx_PSC_SICR_SIM_SIR_DCD (0xc << 24)
107#define MPC52xx_PSC_SICR_SIM_MIR (0x5 << 24)
108#define MPC52xx_PSC_SICR_SIM_FIR (0x6 << 24)
109#define MPC52xx_PSC_SICR_SIM_CODEC_24 (0x7 << 24)
110#define MPC52xx_PSC_SICR_SIM_CODEC_32 (0xf << 24)
111#define MPC52xx_PSC_SICR_GENCLK (1 << 23)
112#define MPC52xx_PSC_SICR_I2S (1 << 22)
113#define MPC52xx_PSC_SICR_CLKPOL (1 << 21)
114#define MPC52xx_PSC_SICR_SYNCPOL (1 << 20)
115#define MPC52xx_PSC_SICR_CELLSLAVE (1 << 19)
116#define MPC52xx_PSC_SICR_CELL2XCLK (1 << 18)
117#define MPC52xx_PSC_SICR_ESAI (1 << 17)
118#define MPC52xx_PSC_SICR_ENAC97 (1 << 16)
119#define MPC52xx_PSC_SICR_SPI (1 << 15)
120#define MPC52xx_PSC_SICR_MSTR (1 << 14)
121#define MPC52xx_PSC_SICR_CPOL (1 << 13)
122#define MPC52xx_PSC_SICR_CPHA (1 << 12)
123#define MPC52xx_PSC_SICR_USEEOF (1 << 11)
124#define MPC52xx_PSC_SICR_DISABLEEOF (1 << 10)
125
126/* Structure of the hardware registers */
127struct mpc52xx_psc {
128 u8 mode; /* PSC + 0x00 */
129 u8 reserved0[3];
130 union { /* PSC + 0x04 */
131 u16 status;
132 u16 clock_select;
133 } sr_csr;
134#define mpc52xx_psc_status sr_csr.status
135#define mpc52xx_psc_clock_select sr_csr.clock_select
136 u16 reserved1;
137 u8 command; /* PSC + 0x08 */
138 u8 reserved2[3];
139 union { /* PSC + 0x0c */
140 u8 buffer_8;
141 u16 buffer_16;
142 u32 buffer_32;
143 } buffer;
144#define mpc52xx_psc_buffer_8 buffer.buffer_8
145#define mpc52xx_psc_buffer_16 buffer.buffer_16
146#define mpc52xx_psc_buffer_32 buffer.buffer_32
147 union { /* PSC + 0x10 */
148 u8 ipcr;
149 u8 acr;
150 } ipcr_acr;
151#define mpc52xx_psc_ipcr ipcr_acr.ipcr
152#define mpc52xx_psc_acr ipcr_acr.acr
153 u8 reserved3[3];
154 union { /* PSC + 0x14 */
155 u16 isr;
156 u16 imr;
157 } isr_imr;
158#define mpc52xx_psc_isr isr_imr.isr
159#define mpc52xx_psc_imr isr_imr.imr
160 u16 reserved4;
161 u8 ctur; /* PSC + 0x18 */
162 u8 reserved5[3];
163 u8 ctlr; /* PSC + 0x1c */
164 u8 reserved6[3];
165 /* BitClkDiv field of CCR is byte swapped in
166 * the hardware for mpc5200/b compatibility */
167 u32 ccr; /* PSC + 0x20 */
168 u32 ac97_slots; /* PSC + 0x24 */
169 u32 ac97_cmd; /* PSC + 0x28 */
170 u32 ac97_data; /* PSC + 0x2c */
171 u8 ivr; /* PSC + 0x30 */
172 u8 reserved8[3];
173 u8 ip; /* PSC + 0x34 */
174 u8 reserved9[3];
175 u8 op1; /* PSC + 0x38 */
176 u8 reserved10[3];
177 u8 op0; /* PSC + 0x3c */
178 u8 reserved11[3];
179 u32 sicr; /* PSC + 0x40 */
180 u8 ircr1; /* PSC + 0x44 */
181 u8 reserved13[3];
182 u8 ircr2; /* PSC + 0x44 */
183 u8 reserved14[3];
184 u8 irsdr; /* PSC + 0x4c */
185 u8 reserved15[3];
186 u8 irmdr; /* PSC + 0x50 */
187 u8 reserved16[3];
188 u8 irfdr; /* PSC + 0x54 */
189 u8 reserved17[3];
190};
191
192struct mpc52xx_psc_fifo {
193 u16 rfnum; /* PSC + 0x58 */
194 u16 reserved18;
195 u16 tfnum; /* PSC + 0x5c */
196 u16 reserved19;
197 u32 rfdata; /* PSC + 0x60 */
198 u16 rfstat; /* PSC + 0x64 */
199 u16 reserved20;
200 u8 rfcntl; /* PSC + 0x68 */
201 u8 reserved21[5];
202 u16 rfalarm; /* PSC + 0x6e */
203 u16 reserved22;
204 u16 rfrptr; /* PSC + 0x72 */
205 u16 reserved23;
206 u16 rfwptr; /* PSC + 0x76 */
207 u16 reserved24;
208 u16 rflrfptr; /* PSC + 0x7a */
209 u16 reserved25;
210 u16 rflwfptr; /* PSC + 0x7e */
211 u32 tfdata; /* PSC + 0x80 */
212 u16 tfstat; /* PSC + 0x84 */
213 u16 reserved26;
214 u8 tfcntl; /* PSC + 0x88 */
215 u8 reserved27[5];
216 u16 tfalarm; /* PSC + 0x8e */
217 u16 reserved28;
218 u16 tfrptr; /* PSC + 0x92 */
219 u16 reserved29;
220 u16 tfwptr; /* PSC + 0x96 */
221 u16 reserved30;
222 u16 tflrfptr; /* PSC + 0x9a */
223 u16 reserved31;
224 u16 tflwfptr; /* PSC + 0x9e */
225};
226
227#define MPC512x_PSC_FIFO_RESET_SLICE 0x80
228#define MPC512x_PSC_FIFO_ENABLE_SLICE 0x01
229#define MPC512x_PSC_FIFO_ENABLE_DMA 0x04
230
231#define MPC512x_PSC_FIFO_EMPTY 0x1
232#define MPC512x_PSC_FIFO_FULL 0x2
233#define MPC512x_PSC_FIFO_ALARM 0x4
234#define MPC512x_PSC_FIFO_URERR 0x8
235#define MPC512x_PSC_FIFO_ORERR 0x01
236#define MPC512x_PSC_FIFO_MEMERROR 0x02
237
238struct mpc512x_psc_fifo {
239 u32 reserved1[10];
240 u32 txcmd; /* PSC + 0x80 */
241 u32 txalarm; /* PSC + 0x84 */
242 u32 txsr; /* PSC + 0x88 */
243 u32 txisr; /* PSC + 0x8c */
244 u32 tximr; /* PSC + 0x90 */
245 u32 txcnt; /* PSC + 0x94 */
246 u32 txptr; /* PSC + 0x98 */
247 u32 txsz; /* PSC + 0x9c */
248 u32 reserved2[7];
249 union {
250 u8 txdata_8;
251 u16 txdata_16;
252 u32 txdata_32;
253 } txdata; /* PSC + 0xbc */
254#define txdata_8 txdata.txdata_8
255#define txdata_16 txdata.txdata_16
256#define txdata_32 txdata.txdata_32
257 u32 rxcmd; /* PSC + 0xc0 */
258 u32 rxalarm; /* PSC + 0xc4 */
259 u32 rxsr; /* PSC + 0xc8 */
260 u32 rxisr; /* PSC + 0xcc */
261 u32 rximr; /* PSC + 0xd0 */
262 u32 rxcnt; /* PSC + 0xd4 */
263 u32 rxptr; /* PSC + 0xd8 */
264 u32 rxsz; /* PSC + 0xdc */
265 u32 reserved3[7];
266 union {
267 u8 rxdata_8;
268 u16 rxdata_16;
269 u32 rxdata_32;
270 } rxdata; /* PSC + 0xfc */
271#define rxdata_8 rxdata.rxdata_8
272#define rxdata_16 rxdata.rxdata_16
273#define rxdata_32 rxdata.rxdata_32
274};
275
276#endif /* __ASM_MPC52xx_PSC_H__ */
diff --git a/include/asm-powerpc/mpc6xx.h b/include/asm-powerpc/mpc6xx.h
deleted file mode 100644
index effc2291beb..00000000000
--- a/include/asm-powerpc/mpc6xx.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef __ASM_POWERPC_MPC6xx_H
2#define __ASM_POWERPC_MPC6xx_H
3
4void mpc6xx_enter_standby(void);
5
6#endif
diff --git a/include/asm-powerpc/mpc8260.h b/include/asm-powerpc/mpc8260.h
deleted file mode 100644
index 03317e1e618..00000000000
--- a/include/asm-powerpc/mpc8260.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * Since there are many different boards and no standard configuration,
3 * we have a unique include file for each. Rather than change every
4 * file that has to include MPC8260 configuration, they all include
5 * this one and the configuration switching is done here.
6 */
7#ifdef __KERNEL__
8#ifndef __ASM_POWERPC_MPC8260_H__
9#define __ASM_POWERPC_MPC8260_H__
10
11#define MPC82XX_BCR_PLDP 0x00800000 /* Pipeline Maximum Depth */
12
13#ifdef CONFIG_8260
14
15#if defined(CONFIG_PQ2ADS) || defined (CONFIG_PQ2FADS)
16#include <platforms/82xx/pq2ads.h>
17#endif
18
19#ifdef CONFIG_PCI_8260
20#include <platforms/82xx/m82xx_pci.h>
21#endif
22
23#endif /* CONFIG_8260 */
24#endif /* !__ASM_POWERPC_MPC8260_H__ */
25#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/mpc86xx.h b/include/asm-powerpc/mpc86xx.h
deleted file mode 100644
index 15f650f987e..00000000000
--- a/include/asm-powerpc/mpc86xx.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * MPC86xx definitions
3 *
4 * Author: Jeff Brown
5 *
6 * Copyright 2004 Freescale Semiconductor, Inc
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#ifdef __KERNEL__
15#ifndef __ASM_POWERPC_MPC86xx_H__
16#define __ASM_POWERPC_MPC86xx_H__
17
18#include <asm/mmu.h>
19
20#ifdef CONFIG_PPC_86xx
21
22#define CPU0_BOOT_RELEASE 0x01000000
23#define CPU1_BOOT_RELEASE 0x02000000
24#define CPU_ALL_RELEASED (CPU0_BOOT_RELEASE | CPU1_BOOT_RELEASE)
25#define MCM_PORT_CONFIG_OFFSET 0x1010
26
27/* Offset from CCSRBAR */
28#define MPC86xx_MCM_OFFSET (0x00000)
29#define MPC86xx_MCM_SIZE (0x02000)
30
31#endif /* CONFIG_PPC_86xx */
32#endif /* __ASM_POWERPC_MPC86xx_H__ */
33#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/mpc8xx.h b/include/asm-powerpc/mpc8xx.h
deleted file mode 100644
index 98f3c4f1732..00000000000
--- a/include/asm-powerpc/mpc8xx.h
+++ /dev/null
@@ -1,12 +0,0 @@
1/* This is the single file included by all MPC8xx build options.
2 * Since there are many different boards and no standard configuration,
3 * we have a unique include file for each. Rather than change every
4 * file that has to include MPC8xx configuration, they all include
5 * this one and the configuration switching is done here.
6 */
7#ifndef __CONFIG_8xx_DEFS
8#define __CONFIG_8xx_DEFS
9
10extern struct mpc8xx_pcmcia_ops m8xx_pcmcia_ops;
11
12#endif /* __CONFIG_8xx_DEFS */
diff --git a/include/asm-powerpc/mpic.h b/include/asm-powerpc/mpic.h
deleted file mode 100644
index fe566a348a8..00000000000
--- a/include/asm-powerpc/mpic.h
+++ /dev/null
@@ -1,481 +0,0 @@
1#ifndef _ASM_POWERPC_MPIC_H
2#define _ASM_POWERPC_MPIC_H
3#ifdef __KERNEL__
4
5#include <linux/irq.h>
6#include <linux/sysdev.h>
7#include <asm/dcr.h>
8
9/*
10 * Global registers
11 */
12
13#define MPIC_GREG_BASE 0x01000
14
15#define MPIC_GREG_FEATURE_0 0x00000
16#define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000
17#define MPIC_GREG_FEATURE_LAST_SRC_SHIFT 16
18#define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00
19#define MPIC_GREG_FEATURE_LAST_CPU_SHIFT 8
20#define MPIC_GREG_FEATURE_VERSION_MASK 0xff
21#define MPIC_GREG_FEATURE_1 0x00010
22#define MPIC_GREG_GLOBAL_CONF_0 0x00020
23#define MPIC_GREG_GCONF_RESET 0x80000000
24#define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000
25#define MPIC_GREG_GCONF_NO_BIAS 0x10000000
26#define MPIC_GREG_GCONF_BASE_MASK 0x000fffff
27#define MPIC_GREG_GCONF_MCK 0x08000000
28#define MPIC_GREG_GLOBAL_CONF_1 0x00030
29#define MPIC_GREG_GLOBAL_CONF_1_SIE 0x08000000
30#define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK 0x70000000
31#define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(r) \
32 (((r) << 28) & MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK)
33#define MPIC_GREG_VENDOR_0 0x00040
34#define MPIC_GREG_VENDOR_1 0x00050
35#define MPIC_GREG_VENDOR_2 0x00060
36#define MPIC_GREG_VENDOR_3 0x00070
37#define MPIC_GREG_VENDOR_ID 0x00080
38#define MPIC_GREG_VENDOR_ID_STEPPING_MASK 0x00ff0000
39#define MPIC_GREG_VENDOR_ID_STEPPING_SHIFT 16
40#define MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK 0x0000ff00
41#define MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT 8
42#define MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK 0x000000ff
43#define MPIC_GREG_PROCESSOR_INIT 0x00090
44#define MPIC_GREG_IPI_VECTOR_PRI_0 0x000a0
45#define MPIC_GREG_IPI_VECTOR_PRI_1 0x000b0
46#define MPIC_GREG_IPI_VECTOR_PRI_2 0x000c0
47#define MPIC_GREG_IPI_VECTOR_PRI_3 0x000d0
48#define MPIC_GREG_IPI_STRIDE 0x10
49#define MPIC_GREG_SPURIOUS 0x000e0
50#define MPIC_GREG_TIMER_FREQ 0x000f0
51
52/*
53 *
54 * Timer registers
55 */
56#define MPIC_TIMER_BASE 0x01100
57#define MPIC_TIMER_STRIDE 0x40
58
59#define MPIC_TIMER_CURRENT_CNT 0x00000
60#define MPIC_TIMER_BASE_CNT 0x00010
61#define MPIC_TIMER_VECTOR_PRI 0x00020
62#define MPIC_TIMER_DESTINATION 0x00030
63
64/*
65 * Per-Processor registers
66 */
67
68#define MPIC_CPU_THISBASE 0x00000
69#define MPIC_CPU_BASE 0x20000
70#define MPIC_CPU_STRIDE 0x01000
71
72#define MPIC_CPU_IPI_DISPATCH_0 0x00040
73#define MPIC_CPU_IPI_DISPATCH_1 0x00050
74#define MPIC_CPU_IPI_DISPATCH_2 0x00060
75#define MPIC_CPU_IPI_DISPATCH_3 0x00070
76#define MPIC_CPU_IPI_DISPATCH_STRIDE 0x00010
77#define MPIC_CPU_CURRENT_TASK_PRI 0x00080
78#define MPIC_CPU_TASKPRI_MASK 0x0000000f
79#define MPIC_CPU_WHOAMI 0x00090
80#define MPIC_CPU_WHOAMI_MASK 0x0000001f
81#define MPIC_CPU_INTACK 0x000a0
82#define MPIC_CPU_EOI 0x000b0
83#define MPIC_CPU_MCACK 0x000c0
84
85/*
86 * Per-source registers
87 */
88
89#define MPIC_IRQ_BASE 0x10000
90#define MPIC_IRQ_STRIDE 0x00020
91#define MPIC_IRQ_VECTOR_PRI 0x00000
92#define MPIC_VECPRI_MASK 0x80000000
93#define MPIC_VECPRI_ACTIVITY 0x40000000 /* Read Only */
94#define MPIC_VECPRI_PRIORITY_MASK 0x000f0000
95#define MPIC_VECPRI_PRIORITY_SHIFT 16
96#define MPIC_VECPRI_VECTOR_MASK 0x000007ff
97#define MPIC_VECPRI_POLARITY_POSITIVE 0x00800000
98#define MPIC_VECPRI_POLARITY_NEGATIVE 0x00000000
99#define MPIC_VECPRI_POLARITY_MASK 0x00800000
100#define MPIC_VECPRI_SENSE_LEVEL 0x00400000
101#define MPIC_VECPRI_SENSE_EDGE 0x00000000
102#define MPIC_VECPRI_SENSE_MASK 0x00400000
103#define MPIC_IRQ_DESTINATION 0x00010
104
105#define MPIC_MAX_IRQ_SOURCES 2048
106#define MPIC_MAX_CPUS 32
107#define MPIC_MAX_ISU 32
108
109/*
110 * Tsi108 implementation of MPIC has many differences from the original one
111 */
112
113/*
114 * Global registers
115 */
116
117#define TSI108_GREG_BASE 0x00000
118#define TSI108_GREG_FEATURE_0 0x00000
119#define TSI108_GREG_GLOBAL_CONF_0 0x00004
120#define TSI108_GREG_VENDOR_ID 0x0000c
121#define TSI108_GREG_IPI_VECTOR_PRI_0 0x00204 /* Doorbell 0 */
122#define TSI108_GREG_IPI_STRIDE 0x0c
123#define TSI108_GREG_SPURIOUS 0x00010
124#define TSI108_GREG_TIMER_FREQ 0x00014
125
126/*
127 * Timer registers
128 */
129#define TSI108_TIMER_BASE 0x0030
130#define TSI108_TIMER_STRIDE 0x10
131#define TSI108_TIMER_CURRENT_CNT 0x00000
132#define TSI108_TIMER_BASE_CNT 0x00004
133#define TSI108_TIMER_VECTOR_PRI 0x00008
134#define TSI108_TIMER_DESTINATION 0x0000c
135
136/*
137 * Per-Processor registers
138 */
139#define TSI108_CPU_BASE 0x00300
140#define TSI108_CPU_STRIDE 0x00040
141#define TSI108_CPU_IPI_DISPATCH_0 0x00200
142#define TSI108_CPU_IPI_DISPATCH_STRIDE 0x00000
143#define TSI108_CPU_CURRENT_TASK_PRI 0x00000
144#define TSI108_CPU_WHOAMI 0xffffffff
145#define TSI108_CPU_INTACK 0x00004
146#define TSI108_CPU_EOI 0x00008
147#define TSI108_CPU_MCACK 0x00004 /* Doesn't really exist here */
148
149/*
150 * Per-source registers
151 */
152#define TSI108_IRQ_BASE 0x00100
153#define TSI108_IRQ_STRIDE 0x00008
154#define TSI108_IRQ_VECTOR_PRI 0x00000
155#define TSI108_VECPRI_VECTOR_MASK 0x000000ff
156#define TSI108_VECPRI_POLARITY_POSITIVE 0x01000000
157#define TSI108_VECPRI_POLARITY_NEGATIVE 0x00000000
158#define TSI108_VECPRI_SENSE_LEVEL 0x02000000
159#define TSI108_VECPRI_SENSE_EDGE 0x00000000
160#define TSI108_VECPRI_POLARITY_MASK 0x01000000
161#define TSI108_VECPRI_SENSE_MASK 0x02000000
162#define TSI108_IRQ_DESTINATION 0x00004
163
164/* weird mpic register indices and mask bits in the HW info array */
165enum {
166 MPIC_IDX_GREG_BASE = 0,
167 MPIC_IDX_GREG_FEATURE_0,
168 MPIC_IDX_GREG_GLOBAL_CONF_0,
169 MPIC_IDX_GREG_VENDOR_ID,
170 MPIC_IDX_GREG_IPI_VECTOR_PRI_0,
171 MPIC_IDX_GREG_IPI_STRIDE,
172 MPIC_IDX_GREG_SPURIOUS,
173 MPIC_IDX_GREG_TIMER_FREQ,
174
175 MPIC_IDX_TIMER_BASE,
176 MPIC_IDX_TIMER_STRIDE,
177 MPIC_IDX_TIMER_CURRENT_CNT,
178 MPIC_IDX_TIMER_BASE_CNT,
179 MPIC_IDX_TIMER_VECTOR_PRI,
180 MPIC_IDX_TIMER_DESTINATION,
181
182 MPIC_IDX_CPU_BASE,
183 MPIC_IDX_CPU_STRIDE,
184 MPIC_IDX_CPU_IPI_DISPATCH_0,
185 MPIC_IDX_CPU_IPI_DISPATCH_STRIDE,
186 MPIC_IDX_CPU_CURRENT_TASK_PRI,
187 MPIC_IDX_CPU_WHOAMI,
188 MPIC_IDX_CPU_INTACK,
189 MPIC_IDX_CPU_EOI,
190 MPIC_IDX_CPU_MCACK,
191
192 MPIC_IDX_IRQ_BASE,
193 MPIC_IDX_IRQ_STRIDE,
194 MPIC_IDX_IRQ_VECTOR_PRI,
195
196 MPIC_IDX_VECPRI_VECTOR_MASK,
197 MPIC_IDX_VECPRI_POLARITY_POSITIVE,
198 MPIC_IDX_VECPRI_POLARITY_NEGATIVE,
199 MPIC_IDX_VECPRI_SENSE_LEVEL,
200 MPIC_IDX_VECPRI_SENSE_EDGE,
201 MPIC_IDX_VECPRI_POLARITY_MASK,
202 MPIC_IDX_VECPRI_SENSE_MASK,
203 MPIC_IDX_IRQ_DESTINATION,
204 MPIC_IDX_END
205};
206
207
208#ifdef CONFIG_MPIC_U3_HT_IRQS
209/* Fixup table entry */
210struct mpic_irq_fixup
211{
212 u8 __iomem *base;
213 u8 __iomem *applebase;
214 u32 data;
215 unsigned int index;
216};
217#endif /* CONFIG_MPIC_U3_HT_IRQS */
218
219
220enum mpic_reg_type {
221 mpic_access_mmio_le,
222 mpic_access_mmio_be,
223#ifdef CONFIG_PPC_DCR
224 mpic_access_dcr
225#endif
226};
227
228struct mpic_reg_bank {
229 u32 __iomem *base;
230#ifdef CONFIG_PPC_DCR
231 dcr_host_t dhost;
232#endif /* CONFIG_PPC_DCR */
233};
234
235struct mpic_irq_save {
236 u32 vecprio,
237 dest;
238#ifdef CONFIG_MPIC_U3_HT_IRQS
239 u32 fixup_data;
240#endif
241};
242
243/* The instance data of a given MPIC */
244struct mpic
245{
246 /* The remapper for this MPIC */
247 struct irq_host *irqhost;
248
249 /* The "linux" controller struct */
250 struct irq_chip hc_irq;
251#ifdef CONFIG_MPIC_U3_HT_IRQS
252 struct irq_chip hc_ht_irq;
253#endif
254#ifdef CONFIG_SMP
255 struct irq_chip hc_ipi;
256#endif
257 const char *name;
258 /* Flags */
259 unsigned int flags;
260 /* How many irq sources in a given ISU */
261 unsigned int isu_size;
262 unsigned int isu_shift;
263 unsigned int isu_mask;
264 unsigned int irq_count;
265 /* Number of sources */
266 unsigned int num_sources;
267 /* Number of CPUs */
268 unsigned int num_cpus;
269 /* default senses array */
270 unsigned char *senses;
271 unsigned int senses_count;
272
273 /* vector numbers used for internal sources (ipi/timers) */
274 unsigned int ipi_vecs[4];
275 unsigned int timer_vecs[4];
276
277 /* Spurious vector to program into unused sources */
278 unsigned int spurious_vec;
279
280#ifdef CONFIG_MPIC_U3_HT_IRQS
281 /* The fixup table */
282 struct mpic_irq_fixup *fixups;
283 spinlock_t fixup_lock;
284#endif
285
286 /* Register access method */
287 enum mpic_reg_type reg_type;
288
289 /* The various ioremap'ed bases */
290 struct mpic_reg_bank gregs;
291 struct mpic_reg_bank tmregs;
292 struct mpic_reg_bank cpuregs[MPIC_MAX_CPUS];
293 struct mpic_reg_bank isus[MPIC_MAX_ISU];
294
295 /* Protected sources */
296 unsigned long *protected;
297
298#ifdef CONFIG_MPIC_WEIRD
299 /* Pointer to HW info array */
300 u32 *hw_set;
301#endif
302
303#ifdef CONFIG_PCI_MSI
304 spinlock_t bitmap_lock;
305 unsigned long *hwirq_bitmap;
306#endif
307
308#ifdef CONFIG_MPIC_BROKEN_REGREAD
309 u32 isu_reg0_shadow[MPIC_MAX_IRQ_SOURCES];
310#endif
311
312 /* link */
313 struct mpic *next;
314
315 struct sys_device sysdev;
316
317#ifdef CONFIG_PM
318 struct mpic_irq_save *save_data;
319#endif
320};
321
322/*
323 * MPIC flags (passed to mpic_alloc)
324 *
325 * The top 4 bits contain an MPIC bhw id that is used to index the
326 * register offsets and some masks when CONFIG_MPIC_WEIRD is set.
327 * Note setting any ID (leaving those bits to 0) means standard MPIC
328 */
329
330/* This is the primary controller, only that one has IPIs and
331 * has afinity control. A non-primary MPIC always uses CPU0
332 * registers only
333 */
334#define MPIC_PRIMARY 0x00000001
335
336/* Set this for a big-endian MPIC */
337#define MPIC_BIG_ENDIAN 0x00000002
338/* Broken U3 MPIC */
339#define MPIC_U3_HT_IRQS 0x00000004
340/* Broken IPI registers (autodetected) */
341#define MPIC_BROKEN_IPI 0x00000008
342/* MPIC wants a reset */
343#define MPIC_WANTS_RESET 0x00000010
344/* Spurious vector requires EOI */
345#define MPIC_SPV_EOI 0x00000020
346/* No passthrough disable */
347#define MPIC_NO_PTHROU_DIS 0x00000040
348/* DCR based MPIC */
349#define MPIC_USES_DCR 0x00000080
350/* MPIC has 11-bit vector fields (or larger) */
351#define MPIC_LARGE_VECTORS 0x00000100
352/* Enable delivery of prio 15 interrupts as MCK instead of EE */
353#define MPIC_ENABLE_MCK 0x00000200
354/* Disable bias among target selection, spread interrupts evenly */
355#define MPIC_NO_BIAS 0x00000400
356/* Ignore NIRQS as reported by FRR */
357#define MPIC_BROKEN_FRR_NIRQS 0x00000800
358
359/* MPIC HW modification ID */
360#define MPIC_REGSET_MASK 0xf0000000
361#define MPIC_REGSET(val) (((val) & 0xf ) << 28)
362#define MPIC_GET_REGSET(flags) (((flags) >> 28) & 0xf)
363
364#define MPIC_REGSET_STANDARD MPIC_REGSET(0) /* Original MPIC */
365#define MPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109 PIC */
366
367/* Allocate the controller structure and setup the linux irq descs
368 * for the range if interrupts passed in. No HW initialization is
369 * actually performed.
370 *
371 * @phys_addr: physial base address of the MPIC
372 * @flags: flags, see constants above
373 * @isu_size: number of interrupts in an ISU. Use 0 to use a
374 * standard ISU-less setup (aka powermac)
375 * @irq_offset: first irq number to assign to this mpic
376 * @irq_count: number of irqs to use with this mpic IRQ sources. Pass 0
377 * to match the number of sources
378 * @ipi_offset: first irq number to assign to this mpic IPI sources,
379 * used only on primary mpic
380 * @senses: array of sense values
381 * @senses_num: number of entries in the array
382 *
383 * Note about the sense array. If none is passed, all interrupts are
384 * setup to be level negative unless MPIC_U3_HT_IRQS is set in which
385 * case they are edge positive (and the array is ignored anyway).
386 * The values in the array start at the first source of the MPIC,
387 * that is senses[0] correspond to linux irq "irq_offset".
388 */
389extern struct mpic *mpic_alloc(struct device_node *node,
390 phys_addr_t phys_addr,
391 unsigned int flags,
392 unsigned int isu_size,
393 unsigned int irq_count,
394 const char *name);
395
396/* Assign ISUs, to call before mpic_init()
397 *
398 * @mpic: controller structure as returned by mpic_alloc()
399 * @isu_num: ISU number
400 * @phys_addr: physical address of the ISU
401 */
402extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
403 phys_addr_t phys_addr);
404
405/* Set default sense codes
406 *
407 * @mpic: controller
408 * @senses: array of sense codes
409 * @count: size of above array
410 *
411 * Optionally provide an array (indexed on hardware interrupt numbers
412 * for this MPIC) of default sense codes for the chip. Those are linux
413 * sense codes IRQ_TYPE_*
414 *
415 * The driver gets ownership of the pointer, don't dispose of it or
416 * anything like that. __init only.
417 */
418extern void mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count);
419
420
421/* Initialize the controller. After this has been called, none of the above
422 * should be called again for this mpic
423 */
424extern void mpic_init(struct mpic *mpic);
425
426/*
427 * All of the following functions must only be used after the
428 * ISUs have been assigned and the controller fully initialized
429 * with mpic_init()
430 */
431
432
433/* Change the priority of an interrupt. Default is 8 for irqs and
434 * 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the
435 * IPI number is then the offset'ed (linux irq number mapped to the IPI)
436 */
437extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri);
438
439/* Setup a non-boot CPU */
440extern void mpic_setup_this_cpu(void);
441
442/* Clean up for kexec (or cpu offline or ...) */
443extern void mpic_teardown_this_cpu(int secondary);
444
445/* Get the current cpu priority for this cpu (0..15) */
446extern int mpic_cpu_get_priority(void);
447
448/* Set the current cpu priority for this cpu */
449extern void mpic_cpu_set_priority(int prio);
450
451/* Request IPIs on primary mpic */
452extern void mpic_request_ipis(void);
453
454/* Send an IPI (non offseted number 0..3) */
455extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask);
456
457/* Send a message (IPI) to a given target (cpu number or MSG_*) */
458void smp_mpic_message_pass(int target, int msg);
459
460/* Unmask a specific virq */
461extern void mpic_unmask_irq(unsigned int irq);
462/* Mask a specific virq */
463extern void mpic_mask_irq(unsigned int irq);
464/* EOI a specific virq */
465extern void mpic_end_irq(unsigned int irq);
466
467/* Fetch interrupt from a given mpic */
468extern unsigned int mpic_get_one_irq(struct mpic *mpic);
469/* This one gets from the primary mpic */
470extern unsigned int mpic_get_irq(void);
471/* Fetch Machine Check interrupt from primary mpic */
472extern unsigned int mpic_get_mcirq(void);
473
474/* Set the EPIC clock ratio */
475void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio);
476
477/* Enable/Disable EPIC serial interrupt mode */
478void mpic_set_serial_int(struct mpic *mpic, int enable);
479
480#endif /* __KERNEL__ */
481#endif /* _ASM_POWERPC_MPIC_H */
diff --git a/include/asm-powerpc/msgbuf.h b/include/asm-powerpc/msgbuf.h
deleted file mode 100644
index dd76743c753..00000000000
--- a/include/asm-powerpc/msgbuf.h
+++ /dev/null
@@ -1,33 +0,0 @@
1#ifndef _ASM_POWERPC_MSGBUF_H
2#define _ASM_POWERPC_MSGBUF_H
3
4/*
5 * The msqid64_ds structure for the PowerPC architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 */
9
10struct msqid64_ds {
11 struct ipc64_perm msg_perm;
12#ifndef __powerpc64__
13 unsigned int __unused1;
14#endif
15 __kernel_time_t msg_stime; /* last msgsnd time */
16#ifndef __powerpc64__
17 unsigned int __unused2;
18#endif
19 __kernel_time_t msg_rtime; /* last msgrcv time */
20#ifndef __powerpc64__
21 unsigned int __unused3;
22#endif
23 __kernel_time_t msg_ctime; /* last change time */
24 unsigned long msg_cbytes; /* current number of bytes on queue */
25 unsigned long msg_qnum; /* number of messages in queue */
26 unsigned long msg_qbytes; /* max number of bytes on queue */
27 __kernel_pid_t msg_lspid; /* pid of last msgsnd */
28 __kernel_pid_t msg_lrpid; /* last receive pid */
29 unsigned long __unused4;
30 unsigned long __unused5;
31};
32
33#endif /* _ASM_POWERPC_MSGBUF_H */
diff --git a/include/asm-powerpc/mutex.h b/include/asm-powerpc/mutex.h
deleted file mode 100644
index 458c1f7fbc1..00000000000
--- a/include/asm-powerpc/mutex.h
+++ /dev/null
@@ -1,9 +0,0 @@
1/*
2 * Pull in the generic implementation for the mutex fastpath.
3 *
4 * TODO: implement optimized primitives instead, or leave the generic
5 * implementation in place, or pick the atomic_xchg() based generic
6 * implementation. (see asm-generic/mutex-xchg.h for details)
7 */
8
9#include <asm-generic/mutex-dec.h>
diff --git a/include/asm-powerpc/nvram.h b/include/asm-powerpc/nvram.h
deleted file mode 100644
index efde5ac82f7..00000000000
--- a/include/asm-powerpc/nvram.h
+++ /dev/null
@@ -1,139 +0,0 @@
1/*
2 * NVRAM definitions and access functions.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10#ifndef _ASM_POWERPC_NVRAM_H
11#define _ASM_POWERPC_NVRAM_H
12
13#include <linux/errno.h>
14
15#define NVRW_CNT 0x20
16#define NVRAM_HEADER_LEN 16 /* sizeof(struct nvram_header) */
17#define NVRAM_BLOCK_LEN 16
18#define NVRAM_MAX_REQ (2080/NVRAM_BLOCK_LEN)
19#define NVRAM_MIN_REQ (1056/NVRAM_BLOCK_LEN)
20
21#define NVRAM_AS0 0x74
22#define NVRAM_AS1 0x75
23#define NVRAM_DATA 0x77
24
25
26/* RTC Offsets */
27
28#define MOTO_RTC_SECONDS 0x1FF9
29#define MOTO_RTC_MINUTES 0x1FFA
30#define MOTO_RTC_HOURS 0x1FFB
31#define MOTO_RTC_DAY_OF_WEEK 0x1FFC
32#define MOTO_RTC_DAY_OF_MONTH 0x1FFD
33#define MOTO_RTC_MONTH 0x1FFE
34#define MOTO_RTC_YEAR 0x1FFF
35#define MOTO_RTC_CONTROLA 0x1FF8
36#define MOTO_RTC_CONTROLB 0x1FF9
37
38#define NVRAM_SIG_SP 0x02 /* support processor */
39#define NVRAM_SIG_OF 0x50 /* open firmware config */
40#define NVRAM_SIG_FW 0x51 /* general firmware */
41#define NVRAM_SIG_HW 0x52 /* hardware (VPD) */
42#define NVRAM_SIG_FLIP 0x5a /* Apple flip/flop header */
43#define NVRAM_SIG_APPL 0x5f /* Apple "system" (???) */
44#define NVRAM_SIG_SYS 0x70 /* system env vars */
45#define NVRAM_SIG_CFG 0x71 /* config data */
46#define NVRAM_SIG_ELOG 0x72 /* error log */
47#define NVRAM_SIG_VEND 0x7e /* vendor defined */
48#define NVRAM_SIG_FREE 0x7f /* Free space */
49#define NVRAM_SIG_OS 0xa0 /* OS defined */
50#define NVRAM_SIG_PANIC 0xa1 /* Apple OSX "panic" */
51
52/* If change this size, then change the size of NVNAME_LEN */
53struct nvram_header {
54 unsigned char signature;
55 unsigned char checksum;
56 unsigned short length;
57 char name[12];
58};
59
60#ifdef __KERNEL__
61
62#include <linux/list.h>
63
64struct nvram_partition {
65 struct list_head partition;
66 struct nvram_header header;
67 unsigned int index;
68};
69
70
71extern int nvram_write_error_log(char * buff, int length,
72 unsigned int err_type, unsigned int err_seq);
73extern int nvram_read_error_log(char * buff, int length,
74 unsigned int * err_type, unsigned int *err_seq);
75extern int nvram_clear_error_log(void);
76extern struct nvram_partition *nvram_find_partition(int sig, const char *name);
77
78extern int pSeries_nvram_init(void);
79
80#ifdef CONFIG_MMIO_NVRAM
81extern int mmio_nvram_init(void);
82#else
83static inline int mmio_nvram_init(void)
84{
85 return -ENODEV;
86}
87#endif
88
89#endif /* __KERNEL__ */
90
91/* PowerMac specific nvram stuffs */
92
93enum {
94 pmac_nvram_OF, /* Open Firmware partition */
95 pmac_nvram_XPRAM, /* MacOS XPRAM partition */
96 pmac_nvram_NR /* MacOS Name Registry partition */
97};
98
99#ifdef __KERNEL__
100/* Return partition offset in nvram */
101extern int pmac_get_partition(int partition);
102
103/* Direct access to XPRAM on PowerMacs */
104extern u8 pmac_xpram_read(int xpaddr);
105extern void pmac_xpram_write(int xpaddr, u8 data);
106
107/* Synchronize NVRAM */
108extern void nvram_sync(void);
109
110/* Normal access to NVRAM */
111extern unsigned char nvram_read_byte(int i);
112extern void nvram_write_byte(unsigned char c, int i);
113#endif
114
115/* Some offsets in XPRAM */
116#define PMAC_XPRAM_MACHINE_LOC 0xe4
117#define PMAC_XPRAM_SOUND_VOLUME 0x08
118
119/* Machine location structure in PowerMac XPRAM */
120struct pmac_machine_location {
121 unsigned int latitude; /* 2+30 bit Fractional number */
122 unsigned int longitude; /* 2+30 bit Fractional number */
123 unsigned int delta; /* mix of GMT delta and DLS */
124};
125
126/*
127 * /dev/nvram ioctls
128 *
129 * Note that PMAC_NVRAM_GET_OFFSET is still supported, but is
130 * definitely obsolete. Do not use it if you can avoid it
131 */
132
133#define OBSOLETE_PMAC_NVRAM_GET_OFFSET \
134 _IOWR('p', 0x40, int)
135
136#define IOC_NVRAM_GET_OFFSET _IOWR('p', 0x42, int) /* Get NVRAM partition offset */
137#define IOC_NVRAM_SYNC _IO('p', 0x43) /* Sync NVRAM image */
138
139#endif /* _ASM_POWERPC_NVRAM_H */
diff --git a/include/asm-powerpc/of_device.h b/include/asm-powerpc/of_device.h
deleted file mode 100644
index 3c123990ca2..00000000000
--- a/include/asm-powerpc/of_device.h
+++ /dev/null
@@ -1,31 +0,0 @@
1#ifndef _ASM_POWERPC_OF_DEVICE_H
2#define _ASM_POWERPC_OF_DEVICE_H
3#ifdef __KERNEL__
4
5#include <linux/device.h>
6#include <linux/of.h>
7
8/*
9 * The of_device is a kind of "base class" that is a superset of
10 * struct device for use by devices attached to an OF node and
11 * probed using OF properties.
12 */
13struct of_device
14{
15 struct device_node *node; /* to be obsoleted */
16 u64 dma_mask; /* DMA mask */
17 struct device dev; /* Generic device interface */
18};
19
20extern struct of_device *of_device_alloc(struct device_node *np,
21 const char *bus_id,
22 struct device *parent);
23
24extern int of_device_uevent(struct device *dev,
25 struct kobj_uevent_env *env);
26
27/* This is just here during the transition */
28#include <linux/of_device.h>
29
30#endif /* __KERNEL__ */
31#endif /* _ASM_POWERPC_OF_DEVICE_H */
diff --git a/include/asm-powerpc/of_platform.h b/include/asm-powerpc/of_platform.h
deleted file mode 100644
index 18659ef7213..00000000000
--- a/include/asm-powerpc/of_platform.h
+++ /dev/null
@@ -1,42 +0,0 @@
1#ifndef _ASM_POWERPC_OF_PLATFORM_H
2#define _ASM_POWERPC_OF_PLATFORM_H
3/*
4 * Copyright (C) 2006 Benjamin Herrenschmidt, IBM Corp.
5 * <benh@kernel.crashing.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 *
12 */
13
14/* This is just here during the transition */
15#include <linux/of_platform.h>
16
17/* Platform drivers register/unregister */
18static inline int of_register_platform_driver(struct of_platform_driver *drv)
19{
20 return of_register_driver(drv, &of_platform_bus_type);
21}
22static inline void of_unregister_platform_driver(struct of_platform_driver *drv)
23{
24 of_unregister_driver(drv);
25}
26
27/* Platform devices and busses creation */
28extern struct of_device *of_platform_device_create(struct device_node *np,
29 const char *bus_id,
30 struct device *parent);
31/* pseudo "matches" value to not do deep probe */
32#define OF_NO_DEEP_PROBE ((struct of_device_id *)-1)
33
34extern int of_platform_bus_probe(struct device_node *root,
35 const struct of_device_id *matches,
36 struct device *parent);
37
38extern struct of_device *of_find_device_by_phandle(phandle ph);
39
40extern void of_instantiate_rtc(void);
41
42#endif /* _ASM_POWERPC_OF_PLATFORM_H */
diff --git a/include/asm-powerpc/ohare.h b/include/asm-powerpc/ohare.h
deleted file mode 100644
index 0d030f9dea2..00000000000
--- a/include/asm-powerpc/ohare.h
+++ /dev/null
@@ -1,54 +0,0 @@
1#ifndef _ASM_POWERPC_OHARE_H
2#define _ASM_POWERPC_OHARE_H
3#ifdef __KERNEL__
4/*
5 * ohare.h: definitions for using the "O'Hare" I/O controller chip.
6 *
7 * Copyright (C) 1997 Paul Mackerras.
8 *
9 * BenH: Changed to match those of heathrow (but not all of them). Please
10 * check if I didn't break anything (especially the media bay).
11 */
12
13/* offset from ohare base for feature control register */
14#define OHARE_MBCR 0x34
15#define OHARE_FCR 0x38
16
17/*
18 * Bits in feature control register.
19 * These were mostly derived by experiment on a powerbook 3400
20 * and may differ for other machines.
21 */
22#define OH_SCC_RESET 1
23#define OH_BAY_POWER_N 2 /* a guess */
24#define OH_BAY_PCI_ENABLE 4 /* a guess */
25#define OH_BAY_IDE_ENABLE 8
26#define OH_BAY_FLOPPY_ENABLE 0x10
27#define OH_IDE0_ENABLE 0x20
28#define OH_IDE0_RESET_N 0x40 /* a guess */
29#define OH_BAY_DEV_MASK 0x1c
30#define OH_BAY_RESET_N 0x80
31#define OH_IOBUS_ENABLE 0x100 /* IOBUS seems to be IDE */
32#define OH_SCC_ENABLE 0x200
33#define OH_MESH_ENABLE 0x400
34#define OH_FLOPPY_ENABLE 0x800
35#define OH_SCCA_IO 0x4000
36#define OH_SCCB_IO 0x8000
37#define OH_VIA_ENABLE 0x10000 /* Is apparently wrong, to be verified */
38#define OH_IDE1_RESET_N 0x800000
39
40/*
41 * Bits to set in the feature control register on PowerBooks.
42 */
43#define PBOOK_FEATURES (OH_IDE_ENABLE | OH_SCC_ENABLE | \
44 OH_MESH_ENABLE | OH_SCCA_IO | OH_SCCB_IO)
45
46/*
47 * A magic value to put into the feature control register of the
48 * "ohare" I/O controller on Starmaxes to enable the IDE CD interface.
49 * Contributed by Harry Eaton.
50 */
51#define STARMAX_FEATURES 0xbeff7a
52
53#endif /* __KERNEL__ */
54#endif /* _ASM_POWERPC_OHARE_H */
diff --git a/include/asm-powerpc/oprofile_impl.h b/include/asm-powerpc/oprofile_impl.h
deleted file mode 100644
index 95035c602ba..00000000000
--- a/include/asm-powerpc/oprofile_impl.h
+++ /dev/null
@@ -1,134 +0,0 @@
1/*
2 * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
3 *
4 * Based on alpha version.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#ifndef _ASM_POWERPC_OPROFILE_IMPL_H
13#define _ASM_POWERPC_OPROFILE_IMPL_H
14#ifdef __KERNEL__
15
16#define OP_MAX_COUNTER 8
17
18/* Per-counter configuration as set via oprofilefs. */
19struct op_counter_config {
20 unsigned long enabled;
21 unsigned long event;
22 unsigned long count;
23 /* Classic doesn't support per-counter user/kernel selection */
24 unsigned long kernel;
25 unsigned long user;
26 unsigned long unit_mask;
27};
28
29/* System-wide configuration as set via oprofilefs. */
30struct op_system_config {
31#ifdef CONFIG_PPC64
32 unsigned long mmcr0;
33 unsigned long mmcr1;
34 unsigned long mmcra;
35#endif
36 unsigned long enable_kernel;
37 unsigned long enable_user;
38};
39
40/* Per-arch configuration */
41struct op_powerpc_model {
42 int (*reg_setup) (struct op_counter_config *,
43 struct op_system_config *,
44 int num_counters);
45 int (*cpu_setup) (struct op_counter_config *);
46 int (*start) (struct op_counter_config *);
47 int (*global_start) (struct op_counter_config *);
48 void (*stop) (void);
49 void (*global_stop) (void);
50 int (*sync_start)(void);
51 int (*sync_stop)(void);
52 void (*handle_interrupt) (struct pt_regs *,
53 struct op_counter_config *);
54 int num_counters;
55};
56
57extern struct op_powerpc_model op_model_fsl_emb;
58extern struct op_powerpc_model op_model_rs64;
59extern struct op_powerpc_model op_model_power4;
60extern struct op_powerpc_model op_model_7450;
61extern struct op_powerpc_model op_model_cell;
62extern struct op_powerpc_model op_model_pa6t;
63
64
65/* All the classic PPC parts use these */
66static inline unsigned int classic_ctr_read(unsigned int i)
67{
68 switch(i) {
69 case 0:
70 return mfspr(SPRN_PMC1);
71 case 1:
72 return mfspr(SPRN_PMC2);
73 case 2:
74 return mfspr(SPRN_PMC3);
75 case 3:
76 return mfspr(SPRN_PMC4);
77 case 4:
78 return mfspr(SPRN_PMC5);
79 case 5:
80 return mfspr(SPRN_PMC6);
81
82/* No PPC32 chip has more than 6 so far */
83#ifdef CONFIG_PPC64
84 case 6:
85 return mfspr(SPRN_PMC7);
86 case 7:
87 return mfspr(SPRN_PMC8);
88#endif
89 default:
90 return 0;
91 }
92}
93
94static inline void classic_ctr_write(unsigned int i, unsigned int val)
95{
96 switch(i) {
97 case 0:
98 mtspr(SPRN_PMC1, val);
99 break;
100 case 1:
101 mtspr(SPRN_PMC2, val);
102 break;
103 case 2:
104 mtspr(SPRN_PMC3, val);
105 break;
106 case 3:
107 mtspr(SPRN_PMC4, val);
108 break;
109 case 4:
110 mtspr(SPRN_PMC5, val);
111 break;
112 case 5:
113 mtspr(SPRN_PMC6, val);
114 break;
115
116/* No PPC32 chip has more than 6, yet */
117#ifdef CONFIG_PPC64
118 case 6:
119 mtspr(SPRN_PMC7, val);
120 break;
121 case 7:
122 mtspr(SPRN_PMC8, val);
123 break;
124#endif
125 default:
126 break;
127 }
128}
129
130
131extern void op_powerpc_backtrace(struct pt_regs * const regs, unsigned int depth);
132
133#endif /* __KERNEL__ */
134#endif /* _ASM_POWERPC_OPROFILE_IMPL_H */
diff --git a/include/asm-powerpc/pSeries_reconfig.h b/include/asm-powerpc/pSeries_reconfig.h
deleted file mode 100644
index e482e5352e6..00000000000
--- a/include/asm-powerpc/pSeries_reconfig.h
+++ /dev/null
@@ -1,29 +0,0 @@
1#ifndef _PPC64_PSERIES_RECONFIG_H
2#define _PPC64_PSERIES_RECONFIG_H
3#ifdef __KERNEL__
4
5#include <linux/notifier.h>
6
7/*
8 * Use this API if your code needs to know about OF device nodes being
9 * added or removed on pSeries systems.
10 */
11
12#define PSERIES_RECONFIG_ADD 0x0001
13#define PSERIES_RECONFIG_REMOVE 0x0002
14#define PSERIES_DRCONF_MEM_ADD 0x0003
15#define PSERIES_DRCONF_MEM_REMOVE 0x0004
16
17#ifdef CONFIG_PPC_PSERIES
18extern int pSeries_reconfig_notifier_register(struct notifier_block *);
19extern void pSeries_reconfig_notifier_unregister(struct notifier_block *);
20#else /* !CONFIG_PPC_PSERIES */
21static inline int pSeries_reconfig_notifier_register(struct notifier_block *nb)
22{
23 return 0;
24}
25static inline void pSeries_reconfig_notifier_unregister(struct notifier_block *nb) { }
26#endif /* CONFIG_PPC_PSERIES */
27
28#endif /* __KERNEL__ */
29#endif /* _PPC64_PSERIES_RECONFIG_H */
diff --git a/include/asm-powerpc/paca.h b/include/asm-powerpc/paca.h
deleted file mode 100644
index 7b564444ff6..00000000000
--- a/include/asm-powerpc/paca.h
+++ /dev/null
@@ -1,114 +0,0 @@
1/*
2 * include/asm-powerpc/paca.h
3 *
4 * This control block defines the PACA which defines the processor
5 * specific data for each logical processor on the system.
6 * There are some pointers defined that are utilized by PLIC.
7 *
8 * C 2001 PPC 64 Team, IBM Corp
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15#ifndef _ASM_POWERPC_PACA_H
16#define _ASM_POWERPC_PACA_H
17#ifdef __KERNEL__
18
19#include <asm/types.h>
20#include <asm/lppaca.h>
21#include <asm/mmu.h>
22
23register struct paca_struct *local_paca asm("r13");
24
25#if defined(CONFIG_DEBUG_PREEMPT) && defined(CONFIG_SMP)
26extern unsigned int debug_smp_processor_id(void); /* from linux/smp.h */
27/*
28 * Add standard checks that preemption cannot occur when using get_paca():
29 * otherwise the paca_struct it points to may be the wrong one just after.
30 */
31#define get_paca() ((void) debug_smp_processor_id(), local_paca)
32#else
33#define get_paca() local_paca
34#endif
35
36#define get_lppaca() (get_paca()->lppaca_ptr)
37#define get_slb_shadow() (get_paca()->slb_shadow_ptr)
38
39struct task_struct;
40
41/*
42 * Defines the layout of the paca.
43 *
44 * This structure is not directly accessed by firmware or the service
45 * processor.
46 */
47struct paca_struct {
48 /*
49 * Because hw_cpu_id, unlike other paca fields, is accessed
50 * routinely from other CPUs (from the IRQ code), we stick to
51 * read-only (after boot) fields in the first cacheline to
52 * avoid cacheline bouncing.
53 */
54
55 struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */
56
57 /*
58 * MAGIC: the spinlock functions in arch/powerpc/lib/locks.c
59 * load lock_token and paca_index with a single lwz
60 * instruction. They must travel together and be properly
61 * aligned.
62 */
63 u16 lock_token; /* Constant 0x8000, used in locks */
64 u16 paca_index; /* Logical processor number */
65
66 u64 kernel_toc; /* Kernel TOC address */
67 u64 stab_real; /* Absolute address of segment table */
68 u64 stab_addr; /* Virtual address of segment table */
69 void *emergency_sp; /* pointer to emergency stack */
70 u64 data_offset; /* per cpu data offset */
71 s16 hw_cpu_id; /* Physical processor number */
72 u8 cpu_start; /* At startup, processor spins until */
73 /* this becomes non-zero. */
74 struct slb_shadow *slb_shadow_ptr;
75
76 /*
77 * Now, starting in cacheline 2, the exception save areas
78 */
79 /* used for most interrupts/exceptions */
80 u64 exgen[10] __attribute__((aligned(0x80)));
81 u64 exmc[10]; /* used for machine checks */
82 u64 exslb[10]; /* used for SLB/segment table misses
83 * on the linear mapping */
84
85 mm_context_t context;
86 u16 vmalloc_sllp;
87 u16 slb_cache_ptr;
88 u16 slb_cache[SLB_CACHE_ENTRIES];
89
90 /*
91 * then miscellaneous read-write fields
92 */
93 struct task_struct *__current; /* Pointer to current */
94 u64 kstack; /* Saved Kernel stack addr */
95 u64 stab_rr; /* stab/slb round-robin counter */
96 u64 saved_r1; /* r1 save for RTAS calls */
97 u64 saved_msr; /* MSR saved here by enter_rtas */
98 u16 trap_save; /* Used when bad stack is encountered */
99 u8 soft_enabled; /* irq soft-enable flag */
100 u8 hard_enabled; /* set if irqs are enabled in MSR */
101 u8 io_sync; /* writel() needs spin_unlock sync */
102
103 /* Stuff for accurate time accounting */
104 u64 user_time; /* accumulated usermode TB ticks */
105 u64 system_time; /* accumulated system TB ticks */
106 u64 startpurr; /* PURR/TB value snapshot */
107 u64 startspurr; /* SPURR value snapshot */
108};
109
110extern struct paca_struct paca[];
111extern void initialise_pacas(void);
112
113#endif /* __KERNEL__ */
114#endif /* _ASM_POWERPC_PACA_H */
diff --git a/include/asm-powerpc/page.h b/include/asm-powerpc/page.h
deleted file mode 100644
index e088545cb3f..00000000000
--- a/include/asm-powerpc/page.h
+++ /dev/null
@@ -1,225 +0,0 @@
1#ifndef _ASM_POWERPC_PAGE_H
2#define _ASM_POWERPC_PAGE_H
3
4/*
5 * Copyright (C) 2001,2005 IBM Corporation.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#include <asm/asm-compat.h>
14#include <asm/kdump.h>
15#include <asm/types.h>
16
17/*
18 * On PPC32 page size is 4K. For PPC64 we support either 4K or 64K software
19 * page size. When using 64K pages however, whether we are really supporting
20 * 64K pages in HW or not is irrelevant to those definitions.
21 */
22#ifdef CONFIG_PPC_64K_PAGES
23#define PAGE_SHIFT 16
24#else
25#define PAGE_SHIFT 12
26#endif
27
28#define PAGE_SIZE (ASM_CONST(1) << PAGE_SHIFT)
29
30/* We do define AT_SYSINFO_EHDR but don't use the gate mechanism */
31#define __HAVE_ARCH_GATE_AREA 1
32
33/*
34 * Subtle: (1 << PAGE_SHIFT) is an int, not an unsigned long. So if we
35 * assign PAGE_MASK to a larger type it gets extended the way we want
36 * (i.e. with 1s in the high bits)
37 */
38#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1))
39
40/*
41 * KERNELBASE is the virtual address of the start of the kernel, it's often
42 * the same as PAGE_OFFSET, but _might not be_.
43 *
44 * The kdump dump kernel is one example where KERNELBASE != PAGE_OFFSET.
45 *
46 * PAGE_OFFSET is the virtual address of the start of lowmem.
47 *
48 * PHYSICAL_START is the physical address of the start of the kernel.
49 *
50 * MEMORY_START is the physical address of the start of lowmem.
51 *
52 * KERNELBASE, PAGE_OFFSET, and PHYSICAL_START are all configurable on
53 * ppc32 and based on how they are set we determine MEMORY_START.
54 *
55 * For the linear mapping the following equation should be true:
56 * KERNELBASE - PAGE_OFFSET = PHYSICAL_START - MEMORY_START
57 *
58 * Also, KERNELBASE >= PAGE_OFFSET and PHYSICAL_START >= MEMORY_START
59 *
60 * There are two was to determine a physical address from a virtual one:
61 * va = pa + PAGE_OFFSET - MEMORY_START
62 * va = pa + KERNELBASE - PHYSICAL_START
63 *
64 * If you want to know something's offset from the start of the kernel you
65 * should subtract KERNELBASE.
66 *
67 * If you want to test if something's a kernel address, use is_kernel_addr().
68 */
69
70#define KERNELBASE ASM_CONST(CONFIG_KERNEL_START)
71#define PAGE_OFFSET ASM_CONST(CONFIG_PAGE_OFFSET)
72#define LOAD_OFFSET ASM_CONST((CONFIG_KERNEL_START-CONFIG_PHYSICAL_START))
73
74#if defined(CONFIG_RELOCATABLE) && defined(CONFIG_FLATMEM)
75#ifndef __ASSEMBLY__
76extern phys_addr_t memstart_addr;
77extern phys_addr_t kernstart_addr;
78#endif
79#define PHYSICAL_START kernstart_addr
80#define MEMORY_START memstart_addr
81#else
82#define PHYSICAL_START ASM_CONST(CONFIG_PHYSICAL_START)
83#define MEMORY_START (PHYSICAL_START + PAGE_OFFSET - KERNELBASE)
84#endif
85
86#ifdef CONFIG_FLATMEM
87#define ARCH_PFN_OFFSET (MEMORY_START >> PAGE_SHIFT)
88#define pfn_valid(pfn) ((pfn) >= ARCH_PFN_OFFSET && (pfn) < (ARCH_PFN_OFFSET + max_mapnr))
89#endif
90
91#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
92#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
93#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
94
95#define __va(x) ((void *)((unsigned long)(x) - PHYSICAL_START + KERNELBASE))
96#define __pa(x) ((unsigned long)(x) + PHYSICAL_START - KERNELBASE)
97
98/*
99 * Unfortunately the PLT is in the BSS in the PPC32 ELF ABI,
100 * and needs to be executable. This means the whole heap ends
101 * up being executable.
102 */
103#define VM_DATA_DEFAULT_FLAGS32 (VM_READ | VM_WRITE | VM_EXEC | \
104 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
105
106#define VM_DATA_DEFAULT_FLAGS64 (VM_READ | VM_WRITE | \
107 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
108
109#ifdef __powerpc64__
110#include <asm/page_64.h>
111#else
112#include <asm/page_32.h>
113#endif
114
115/* align addr on a size boundary - adjust address up/down if needed */
116#define _ALIGN_UP(addr,size) (((addr)+((size)-1))&(~((size)-1)))
117#define _ALIGN_DOWN(addr,size) ((addr)&(~((size)-1)))
118
119/* align addr on a size boundary - adjust address up if needed */
120#define _ALIGN(addr,size) _ALIGN_UP(addr,size)
121
122/*
123 * Don't compare things with KERNELBASE or PAGE_OFFSET to test for
124 * "kernelness", use is_kernel_addr() - it should do what you want.
125 */
126#define is_kernel_addr(x) ((x) >= PAGE_OFFSET)
127
128#ifndef __ASSEMBLY__
129
130#undef STRICT_MM_TYPECHECKS
131
132#ifdef STRICT_MM_TYPECHECKS
133/* These are used to make use of C type-checking. */
134
135/* PTE level */
136typedef struct { pte_basic_t pte; } pte_t;
137#define pte_val(x) ((x).pte)
138#define __pte(x) ((pte_t) { (x) })
139
140/* 64k pages additionally define a bigger "real PTE" type that gathers
141 * the "second half" part of the PTE for pseudo 64k pages
142 */
143#ifdef CONFIG_PPC_64K_PAGES
144typedef struct { pte_t pte; unsigned long hidx; } real_pte_t;
145#else
146typedef struct { pte_t pte; } real_pte_t;
147#endif
148
149/* PMD level */
150#ifdef CONFIG_PPC64
151typedef struct { unsigned long pmd; } pmd_t;
152#define pmd_val(x) ((x).pmd)
153#define __pmd(x) ((pmd_t) { (x) })
154
155/* PUD level exusts only on 4k pages */
156#ifndef CONFIG_PPC_64K_PAGES
157typedef struct { unsigned long pud; } pud_t;
158#define pud_val(x) ((x).pud)
159#define __pud(x) ((pud_t) { (x) })
160#endif /* !CONFIG_PPC_64K_PAGES */
161#endif /* CONFIG_PPC64 */
162
163/* PGD level */
164typedef struct { unsigned long pgd; } pgd_t;
165#define pgd_val(x) ((x).pgd)
166#define __pgd(x) ((pgd_t) { (x) })
167
168/* Page protection bits */
169typedef struct { unsigned long pgprot; } pgprot_t;
170#define pgprot_val(x) ((x).pgprot)
171#define __pgprot(x) ((pgprot_t) { (x) })
172
173#else
174
175/*
176 * .. while these make it easier on the compiler
177 */
178
179typedef pte_basic_t pte_t;
180#define pte_val(x) (x)
181#define __pte(x) (x)
182
183#ifdef CONFIG_PPC_64K_PAGES
184typedef struct { pte_t pte; unsigned long hidx; } real_pte_t;
185#else
186typedef unsigned long real_pte_t;
187#endif
188
189
190#ifdef CONFIG_PPC64
191typedef unsigned long pmd_t;
192#define pmd_val(x) (x)
193#define __pmd(x) (x)
194
195#ifndef CONFIG_PPC_64K_PAGES
196typedef unsigned long pud_t;
197#define pud_val(x) (x)
198#define __pud(x) (x)
199#endif /* !CONFIG_PPC_64K_PAGES */
200#endif /* CONFIG_PPC64 */
201
202typedef unsigned long pgd_t;
203#define pgd_val(x) (x)
204#define pgprot_val(x) (x)
205
206typedef unsigned long pgprot_t;
207#define __pgd(x) (x)
208#define __pgprot(x) (x)
209
210#endif
211
212struct page;
213extern void clear_user_page(void *page, unsigned long vaddr, struct page *pg);
214extern void copy_user_page(void *to, void *from, unsigned long vaddr,
215 struct page *p);
216extern int page_is_ram(unsigned long pfn);
217
218struct vm_area_struct;
219
220typedef struct page *pgtable_t;
221
222#include <asm-generic/memory_model.h>
223#endif /* __ASSEMBLY__ */
224
225#endif /* _ASM_POWERPC_PAGE_H */
diff --git a/include/asm-powerpc/page_32.h b/include/asm-powerpc/page_32.h
deleted file mode 100644
index ebfae530a37..00000000000
--- a/include/asm-powerpc/page_32.h
+++ /dev/null
@@ -1,38 +0,0 @@
1#ifndef _ASM_POWERPC_PAGE_32_H
2#define _ASM_POWERPC_PAGE_32_H
3
4#if defined(CONFIG_PHYSICAL_ALIGN) && (CONFIG_PHYSICAL_START != 0)
5#if (CONFIG_PHYSICAL_START % CONFIG_PHYSICAL_ALIGN) != 0
6#error "CONFIG_PHYSICAL_START must be a multiple of CONFIG_PHYSICAL_ALIGN"
7#endif
8#endif
9
10#define VM_DATA_DEFAULT_FLAGS VM_DATA_DEFAULT_FLAGS32
11
12#ifdef CONFIG_NOT_COHERENT_CACHE
13#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES
14#endif
15
16#ifndef __ASSEMBLY__
17/*
18 * The basic type of a PTE - 64 bits for those CPUs with > 32 bit
19 * physical addressing. For now this just the IBM PPC440.
20 */
21#ifdef CONFIG_PTE_64BIT
22typedef unsigned long long pte_basic_t;
23#define PTE_SHIFT (PAGE_SHIFT - 3) /* 512 ptes per page */
24#else
25typedef unsigned long pte_basic_t;
26#define PTE_SHIFT (PAGE_SHIFT - 2) /* 1024 ptes per page */
27#endif
28
29struct page;
30extern void clear_pages(void *page, int order);
31static inline void clear_page(void *page) { clear_pages(page, 0); }
32extern void copy_page(void *to, void *from);
33
34#include <asm-generic/page.h>
35
36#endif /* __ASSEMBLY__ */
37
38#endif /* _ASM_POWERPC_PAGE_32_H */
diff --git a/include/asm-powerpc/page_64.h b/include/asm-powerpc/page_64.h
deleted file mode 100644
index 043bfdfe4f7..00000000000
--- a/include/asm-powerpc/page_64.h
+++ /dev/null
@@ -1,185 +0,0 @@
1#ifndef _ASM_POWERPC_PAGE_64_H
2#define _ASM_POWERPC_PAGE_64_H
3
4/*
5 * Copyright (C) 2001 PPC64 Team, IBM Corp
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13/*
14 * We always define HW_PAGE_SHIFT to 12 as use of 64K pages remains Linux
15 * specific, every notion of page number shared with the firmware, TCEs,
16 * iommu, etc... still uses a page size of 4K.
17 */
18#define HW_PAGE_SHIFT 12
19#define HW_PAGE_SIZE (ASM_CONST(1) << HW_PAGE_SHIFT)
20#define HW_PAGE_MASK (~(HW_PAGE_SIZE-1))
21
22/*
23 * PAGE_FACTOR is the number of bits factor between PAGE_SHIFT and
24 * HW_PAGE_SHIFT, that is 4K pages.
25 */
26#define PAGE_FACTOR (PAGE_SHIFT - HW_PAGE_SHIFT)
27
28/* Segment size; normal 256M segments */
29#define SID_SHIFT 28
30#define SID_MASK ASM_CONST(0xfffffffff)
31#define ESID_MASK 0xfffffffff0000000UL
32#define GET_ESID(x) (((x) >> SID_SHIFT) & SID_MASK)
33
34/* 1T segments */
35#define SID_SHIFT_1T 40
36#define SID_MASK_1T 0xffffffUL
37#define ESID_MASK_1T 0xffffff0000000000UL
38#define GET_ESID_1T(x) (((x) >> SID_SHIFT_1T) & SID_MASK_1T)
39
40#ifndef __ASSEMBLY__
41#include <asm/cache.h>
42
43typedef unsigned long pte_basic_t;
44
45static __inline__ void clear_page(void *addr)
46{
47 unsigned long lines, line_size;
48
49 line_size = ppc64_caches.dline_size;
50 lines = ppc64_caches.dlines_per_page;
51
52 __asm__ __volatile__(
53 "mtctr %1 # clear_page\n\
541: dcbz 0,%0\n\
55 add %0,%0,%3\n\
56 bdnz+ 1b"
57 : "=r" (addr)
58 : "r" (lines), "0" (addr), "r" (line_size)
59 : "ctr", "memory");
60}
61
62extern void copy_4K_page(void *to, void *from);
63
64#ifdef CONFIG_PPC_64K_PAGES
65static inline void copy_page(void *to, void *from)
66{
67 unsigned int i;
68 for (i=0; i < (1 << (PAGE_SHIFT - 12)); i++) {
69 copy_4K_page(to, from);
70 to += 4096;
71 from += 4096;
72 }
73}
74#else /* CONFIG_PPC_64K_PAGES */
75static inline void copy_page(void *to, void *from)
76{
77 copy_4K_page(to, from);
78}
79#endif /* CONFIG_PPC_64K_PAGES */
80
81/* Log 2 of page table size */
82extern u64 ppc64_pft_size;
83
84/* Large pages size */
85#ifdef CONFIG_HUGETLB_PAGE
86extern unsigned int HPAGE_SHIFT;
87#else
88#define HPAGE_SHIFT PAGE_SHIFT
89#endif
90#define HPAGE_SIZE ((1UL) << HPAGE_SHIFT)
91#define HPAGE_MASK (~(HPAGE_SIZE - 1))
92#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
93#define HUGE_MAX_HSTATE 3
94
95#endif /* __ASSEMBLY__ */
96
97#ifdef CONFIG_PPC_MM_SLICES
98
99#define SLICE_LOW_SHIFT 28
100#define SLICE_HIGH_SHIFT 40
101
102#define SLICE_LOW_TOP (0x100000000ul)
103#define SLICE_NUM_LOW (SLICE_LOW_TOP >> SLICE_LOW_SHIFT)
104#define SLICE_NUM_HIGH (PGTABLE_RANGE >> SLICE_HIGH_SHIFT)
105
106#define GET_LOW_SLICE_INDEX(addr) ((addr) >> SLICE_LOW_SHIFT)
107#define GET_HIGH_SLICE_INDEX(addr) ((addr) >> SLICE_HIGH_SHIFT)
108
109#ifndef __ASSEMBLY__
110
111struct slice_mask {
112 u16 low_slices;
113 u16 high_slices;
114};
115
116struct mm_struct;
117
118extern unsigned long slice_get_unmapped_area(unsigned long addr,
119 unsigned long len,
120 unsigned long flags,
121 unsigned int psize,
122 int topdown,
123 int use_cache);
124
125extern unsigned int get_slice_psize(struct mm_struct *mm,
126 unsigned long addr);
127
128extern void slice_init_context(struct mm_struct *mm, unsigned int psize);
129extern void slice_set_user_psize(struct mm_struct *mm, unsigned int psize);
130extern void slice_set_range_psize(struct mm_struct *mm, unsigned long start,
131 unsigned long len, unsigned int psize);
132
133#define slice_mm_new_context(mm) ((mm)->context.id == 0)
134
135#endif /* __ASSEMBLY__ */
136#else
137#define slice_init()
138#define get_slice_psize(mm, addr) ((mm)->context.user_psize)
139#define slice_set_user_psize(mm, psize) \
140do { \
141 (mm)->context.user_psize = (psize); \
142 (mm)->context.sllp = SLB_VSID_USER | mmu_psize_defs[(psize)].sllp; \
143} while (0)
144#define slice_set_range_psize(mm, start, len, psize) \
145 slice_set_user_psize((mm), (psize))
146#define slice_mm_new_context(mm) 1
147#endif /* CONFIG_PPC_MM_SLICES */
148
149#ifdef CONFIG_HUGETLB_PAGE
150
151#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
152
153#endif /* !CONFIG_HUGETLB_PAGE */
154
155#ifdef MODULE
156#define __page_aligned __attribute__((__aligned__(PAGE_SIZE)))
157#else
158#define __page_aligned \
159 __attribute__((__aligned__(PAGE_SIZE), \
160 __section__(".data.page_aligned")))
161#endif
162
163#define VM_DATA_DEFAULT_FLAGS \
164 (test_thread_flag(TIF_32BIT) ? \
165 VM_DATA_DEFAULT_FLAGS32 : VM_DATA_DEFAULT_FLAGS64)
166
167/*
168 * This is the default if a program doesn't have a PT_GNU_STACK
169 * program header entry. The PPC64 ELF ABI has a non executable stack
170 * stack by default, so in the absense of a PT_GNU_STACK program header
171 * we turn execute permission off.
172 */
173#define VM_STACK_DEFAULT_FLAGS32 (VM_READ | VM_WRITE | VM_EXEC | \
174 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
175
176#define VM_STACK_DEFAULT_FLAGS64 (VM_READ | VM_WRITE | \
177 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
178
179#define VM_STACK_DEFAULT_FLAGS \
180 (test_thread_flag(TIF_32BIT) ? \
181 VM_STACK_DEFAULT_FLAGS32 : VM_STACK_DEFAULT_FLAGS64)
182
183#include <asm-generic/page.h>
184
185#endif /* _ASM_POWERPC_PAGE_64_H */
diff --git a/include/asm-powerpc/param.h b/include/asm-powerpc/param.h
deleted file mode 100644
index 094f63d4d5c..00000000000
--- a/include/asm-powerpc/param.h
+++ /dev/null
@@ -1,22 +0,0 @@
1#ifndef _ASM_POWERPC_PARAM_H
2#define _ASM_POWERPC_PARAM_H
3
4#ifdef __KERNEL__
5#define HZ CONFIG_HZ /* internal kernel timer frequency */
6#define USER_HZ 100 /* for user interfaces in "ticks" */
7#define CLOCKS_PER_SEC (USER_HZ) /* frequency at which times() counts */
8#endif /* __KERNEL__ */
9
10#ifndef HZ
11#define HZ 100
12#endif
13
14#define EXEC_PAGESIZE 4096
15
16#ifndef NOGROUP
17#define NOGROUP (-1)
18#endif
19
20#define MAXHOSTNAMELEN 64 /* max length of hostname */
21
22#endif /* _ASM_POWERPC_PARAM_H */
diff --git a/include/asm-powerpc/parport.h b/include/asm-powerpc/parport.h
deleted file mode 100644
index 414c50e2e88..00000000000
--- a/include/asm-powerpc/parport.h
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * parport.h: platform-specific PC-style parport initialisation
3 *
4 * Copyright (C) 1999, 2000 Tim Waugh <tim@cyberelk.demon.co.uk>
5 *
6 * This file should only be included by drivers/parport/parport_pc.c.
7 */
8
9#ifndef _ASM_POWERPC_PARPORT_H
10#define _ASM_POWERPC_PARPORT_H
11#ifdef __KERNEL__
12
13#include <asm/prom.h>
14
15static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma)
16{
17 struct device_node *np;
18 const u32 *prop;
19 u32 io1, io2;
20 int propsize;
21 int count = 0;
22 for (np = NULL; (np = of_find_compatible_node(np,
23 "parallel",
24 "pnpPNP,400")) != NULL;) {
25 prop = of_get_property(np, "reg", &propsize);
26 if (!prop || propsize > 6*sizeof(u32))
27 continue;
28 io1 = prop[1]; io2 = prop[2];
29 prop = of_get_property(np, "interrupts", NULL);
30 if (!prop)
31 continue;
32 if (parport_pc_probe_port(io1, io2, prop[0], autodma, NULL) != NULL)
33 count++;
34 }
35 return count;
36}
37
38#endif /* __KERNEL__ */
39#endif /* !(_ASM_POWERPC_PARPORT_H) */
diff --git a/include/asm-powerpc/pasemi_dma.h b/include/asm-powerpc/pasemi_dma.h
deleted file mode 100644
index 19fd7933e2d..00000000000
--- a/include/asm-powerpc/pasemi_dma.h
+++ /dev/null
@@ -1,538 +0,0 @@
1/*
2 * Copyright (C) 2006-2008 PA Semi, Inc
3 *
4 * Hardware register layout and descriptor formats for the on-board
5 * DMA engine on PA Semi PWRficient. Used by ethernet, function and security
6 * drivers.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#ifndef ASM_PASEMI_DMA_H
23#define ASM_PASEMI_DMA_H
24
25/* status register layout in IOB region, at 0xfb800000 */
26struct pasdma_status {
27 u64 rx_sta[64]; /* RX channel status */
28 u64 tx_sta[20]; /* TX channel status */
29};
30
31
32/* All these registers live in the PCI configuration space for the DMA PCI
33 * device. Use the normal PCI config access functions for them.
34 */
35enum {
36 PAS_DMA_CAP_TXCH = 0x44, /* Transmit Channel Info */
37 PAS_DMA_CAP_RXCH = 0x48, /* Transmit Channel Info */
38 PAS_DMA_CAP_IFI = 0x4c, /* Interface Info */
39 PAS_DMA_COM_TXCMD = 0x100, /* Transmit Command Register */
40 PAS_DMA_COM_TXSTA = 0x104, /* Transmit Status Register */
41 PAS_DMA_COM_RXCMD = 0x108, /* Receive Command Register */
42 PAS_DMA_COM_RXSTA = 0x10c, /* Receive Status Register */
43 PAS_DMA_COM_CFG = 0x114, /* Common config reg */
44 PAS_DMA_TXF_SFLG0 = 0x140, /* Set flags */
45 PAS_DMA_TXF_SFLG1 = 0x144, /* Set flags */
46 PAS_DMA_TXF_CFLG0 = 0x148, /* Set flags */
47 PAS_DMA_TXF_CFLG1 = 0x14c, /* Set flags */
48};
49
50
51#define PAS_DMA_CAP_TXCH_TCHN_M 0x00ff0000 /* # of TX channels */
52#define PAS_DMA_CAP_TXCH_TCHN_S 16
53
54#define PAS_DMA_CAP_RXCH_RCHN_M 0x00ff0000 /* # of RX channels */
55#define PAS_DMA_CAP_RXCH_RCHN_S 16
56
57#define PAS_DMA_CAP_IFI_IOFF_M 0xff000000 /* Cfg reg for intf pointers */
58#define PAS_DMA_CAP_IFI_IOFF_S 24
59#define PAS_DMA_CAP_IFI_NIN_M 0x00ff0000 /* # of interfaces */
60#define PAS_DMA_CAP_IFI_NIN_S 16
61
62#define PAS_DMA_COM_TXCMD_EN 0x00000001 /* enable */
63#define PAS_DMA_COM_TXSTA_ACT 0x00000001 /* active */
64#define PAS_DMA_COM_RXCMD_EN 0x00000001 /* enable */
65#define PAS_DMA_COM_RXSTA_ACT 0x00000001 /* active */
66
67
68/* Per-interface and per-channel registers */
69#define _PAS_DMA_RXINT_STRIDE 0x20
70#define PAS_DMA_RXINT_RCMDSTA(i) (0x200+(i)*_PAS_DMA_RXINT_STRIDE)
71#define PAS_DMA_RXINT_RCMDSTA_EN 0x00000001
72#define PAS_DMA_RXINT_RCMDSTA_ST 0x00000002
73#define PAS_DMA_RXINT_RCMDSTA_MBT 0x00000008
74#define PAS_DMA_RXINT_RCMDSTA_MDR 0x00000010
75#define PAS_DMA_RXINT_RCMDSTA_MOO 0x00000020
76#define PAS_DMA_RXINT_RCMDSTA_MBP 0x00000040
77#define PAS_DMA_RXINT_RCMDSTA_BT 0x00000800
78#define PAS_DMA_RXINT_RCMDSTA_DR 0x00001000
79#define PAS_DMA_RXINT_RCMDSTA_OO 0x00002000
80#define PAS_DMA_RXINT_RCMDSTA_BP 0x00004000
81#define PAS_DMA_RXINT_RCMDSTA_TB 0x00008000
82#define PAS_DMA_RXINT_RCMDSTA_ACT 0x00010000
83#define PAS_DMA_RXINT_RCMDSTA_DROPS_M 0xfffe0000
84#define PAS_DMA_RXINT_RCMDSTA_DROPS_S 17
85#define PAS_DMA_RXINT_CFG(i) (0x204+(i)*_PAS_DMA_RXINT_STRIDE)
86#define PAS_DMA_RXINT_CFG_RBP 0x80000000
87#define PAS_DMA_RXINT_CFG_ITRR 0x40000000
88#define PAS_DMA_RXINT_CFG_DHL_M 0x07000000
89#define PAS_DMA_RXINT_CFG_DHL_S 24
90#define PAS_DMA_RXINT_CFG_DHL(x) (((x) << PAS_DMA_RXINT_CFG_DHL_S) & \
91 PAS_DMA_RXINT_CFG_DHL_M)
92#define PAS_DMA_RXINT_CFG_ITR 0x00400000
93#define PAS_DMA_RXINT_CFG_LW 0x00200000
94#define PAS_DMA_RXINT_CFG_L2 0x00100000
95#define PAS_DMA_RXINT_CFG_HEN 0x00080000
96#define PAS_DMA_RXINT_CFG_WIF 0x00000002
97#define PAS_DMA_RXINT_CFG_WIL 0x00000001
98
99#define PAS_DMA_RXINT_INCR(i) (0x210+(i)*_PAS_DMA_RXINT_STRIDE)
100#define PAS_DMA_RXINT_INCR_INCR_M 0x0000ffff
101#define PAS_DMA_RXINT_INCR_INCR_S 0
102#define PAS_DMA_RXINT_INCR_INCR(x) ((x) & 0x0000ffff)
103#define PAS_DMA_RXINT_BASEL(i) (0x218+(i)*_PAS_DMA_RXINT_STRIDE)
104#define PAS_DMA_RXINT_BASEL_BRBL(x) ((x) & ~0x3f)
105#define PAS_DMA_RXINT_BASEU(i) (0x21c+(i)*_PAS_DMA_RXINT_STRIDE)
106#define PAS_DMA_RXINT_BASEU_BRBH(x) ((x) & 0xfff)
107#define PAS_DMA_RXINT_BASEU_SIZ_M 0x3fff0000 /* # of cache lines worth of buffer ring */
108#define PAS_DMA_RXINT_BASEU_SIZ_S 16 /* 0 = 16K */
109#define PAS_DMA_RXINT_BASEU_SIZ(x) (((x) << PAS_DMA_RXINT_BASEU_SIZ_S) & \
110 PAS_DMA_RXINT_BASEU_SIZ_M)
111
112
113#define _PAS_DMA_TXCHAN_STRIDE 0x20 /* Size per channel */
114#define _PAS_DMA_TXCHAN_TCMDSTA 0x300 /* Command / Status */
115#define _PAS_DMA_TXCHAN_CFG 0x304 /* Configuration */
116#define _PAS_DMA_TXCHAN_DSCRBU 0x308 /* Descriptor BU Allocation */
117#define _PAS_DMA_TXCHAN_INCR 0x310 /* Descriptor increment */
118#define _PAS_DMA_TXCHAN_CNT 0x314 /* Descriptor count/offset */
119#define _PAS_DMA_TXCHAN_BASEL 0x318 /* Descriptor ring base (low) */
120#define _PAS_DMA_TXCHAN_BASEU 0x31c /* (high) */
121#define PAS_DMA_TXCHAN_TCMDSTA(c) (0x300+(c)*_PAS_DMA_TXCHAN_STRIDE)
122#define PAS_DMA_TXCHAN_TCMDSTA_EN 0x00000001 /* Enabled */
123#define PAS_DMA_TXCHAN_TCMDSTA_ST 0x00000002 /* Stop interface */
124#define PAS_DMA_TXCHAN_TCMDSTA_ACT 0x00010000 /* Active */
125#define PAS_DMA_TXCHAN_TCMDSTA_SZ 0x00000800
126#define PAS_DMA_TXCHAN_TCMDSTA_DB 0x00000400
127#define PAS_DMA_TXCHAN_TCMDSTA_DE 0x00000200
128#define PAS_DMA_TXCHAN_TCMDSTA_DA 0x00000100
129#define PAS_DMA_TXCHAN_CFG(c) (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE)
130#define PAS_DMA_TXCHAN_CFG_TY_IFACE 0x00000000 /* Type = interface */
131#define PAS_DMA_TXCHAN_CFG_TY_COPY 0x00000001 /* Type = copy only */
132#define PAS_DMA_TXCHAN_CFG_TY_FUNC 0x00000002 /* Type = function */
133#define PAS_DMA_TXCHAN_CFG_TY_XOR 0x00000003 /* Type = xor only */
134#define PAS_DMA_TXCHAN_CFG_TATTR_M 0x0000003c
135#define PAS_DMA_TXCHAN_CFG_TATTR_S 2
136#define PAS_DMA_TXCHAN_CFG_TATTR(x) (((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \
137 PAS_DMA_TXCHAN_CFG_TATTR_M)
138#define PAS_DMA_TXCHAN_CFG_LPDQ 0x00000800
139#define PAS_DMA_TXCHAN_CFG_LPSQ 0x00000400
140#define PAS_DMA_TXCHAN_CFG_WT_M 0x000003c0
141#define PAS_DMA_TXCHAN_CFG_WT_S 6
142#define PAS_DMA_TXCHAN_CFG_WT(x) (((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \
143 PAS_DMA_TXCHAN_CFG_WT_M)
144#define PAS_DMA_TXCHAN_CFG_TRD 0x00010000 /* translate data */
145#define PAS_DMA_TXCHAN_CFG_TRR 0x00008000 /* translate rings */
146#define PAS_DMA_TXCHAN_CFG_UP 0x00004000 /* update tx descr when sent */
147#define PAS_DMA_TXCHAN_CFG_CL 0x00002000 /* Clean last line */
148#define PAS_DMA_TXCHAN_CFG_CF 0x00001000 /* Clean first line */
149#define PAS_DMA_TXCHAN_INCR(c) (0x310+(c)*_PAS_DMA_TXCHAN_STRIDE)
150#define PAS_DMA_TXCHAN_BASEL(c) (0x318+(c)*_PAS_DMA_TXCHAN_STRIDE)
151#define PAS_DMA_TXCHAN_BASEL_BRBL_M 0xffffffc0
152#define PAS_DMA_TXCHAN_BASEL_BRBL_S 0
153#define PAS_DMA_TXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_TXCHAN_BASEL_BRBL_S) & \
154 PAS_DMA_TXCHAN_BASEL_BRBL_M)
155#define PAS_DMA_TXCHAN_BASEU(c) (0x31c+(c)*_PAS_DMA_TXCHAN_STRIDE)
156#define PAS_DMA_TXCHAN_BASEU_BRBH_M 0x00000fff
157#define PAS_DMA_TXCHAN_BASEU_BRBH_S 0
158#define PAS_DMA_TXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_TXCHAN_BASEU_BRBH_S) & \
159 PAS_DMA_TXCHAN_BASEU_BRBH_M)
160/* # of cache lines worth of buffer ring */
161#define PAS_DMA_TXCHAN_BASEU_SIZ_M 0x3fff0000
162#define PAS_DMA_TXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */
163#define PAS_DMA_TXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_TXCHAN_BASEU_SIZ_S) & \
164 PAS_DMA_TXCHAN_BASEU_SIZ_M)
165
166#define _PAS_DMA_RXCHAN_STRIDE 0x20 /* Size per channel */
167#define _PAS_DMA_RXCHAN_CCMDSTA 0x800 /* Command / Status */
168#define _PAS_DMA_RXCHAN_CFG 0x804 /* Configuration */
169#define _PAS_DMA_RXCHAN_INCR 0x810 /* Descriptor increment */
170#define _PAS_DMA_RXCHAN_CNT 0x814 /* Descriptor count/offset */
171#define _PAS_DMA_RXCHAN_BASEL 0x818 /* Descriptor ring base (low) */
172#define _PAS_DMA_RXCHAN_BASEU 0x81c /* (high) */
173#define PAS_DMA_RXCHAN_CCMDSTA(c) (0x800+(c)*_PAS_DMA_RXCHAN_STRIDE)
174#define PAS_DMA_RXCHAN_CCMDSTA_EN 0x00000001 /* Enabled */
175#define PAS_DMA_RXCHAN_CCMDSTA_ST 0x00000002 /* Stop interface */
176#define PAS_DMA_RXCHAN_CCMDSTA_ACT 0x00010000 /* Active */
177#define PAS_DMA_RXCHAN_CCMDSTA_DU 0x00020000
178#define PAS_DMA_RXCHAN_CCMDSTA_OD 0x00002000
179#define PAS_DMA_RXCHAN_CCMDSTA_FD 0x00001000
180#define PAS_DMA_RXCHAN_CCMDSTA_DT 0x00000800
181#define PAS_DMA_RXCHAN_CFG(c) (0x804+(c)*_PAS_DMA_RXCHAN_STRIDE)
182#define PAS_DMA_RXCHAN_CFG_CTR 0x00000400
183#define PAS_DMA_RXCHAN_CFG_HBU_M 0x00000380
184#define PAS_DMA_RXCHAN_CFG_HBU_S 7
185#define PAS_DMA_RXCHAN_CFG_HBU(x) (((x) << PAS_DMA_RXCHAN_CFG_HBU_S) & \
186 PAS_DMA_RXCHAN_CFG_HBU_M)
187#define PAS_DMA_RXCHAN_INCR(c) (0x810+(c)*_PAS_DMA_RXCHAN_STRIDE)
188#define PAS_DMA_RXCHAN_BASEL(c) (0x818+(c)*_PAS_DMA_RXCHAN_STRIDE)
189#define PAS_DMA_RXCHAN_BASEL_BRBL_M 0xffffffc0
190#define PAS_DMA_RXCHAN_BASEL_BRBL_S 0
191#define PAS_DMA_RXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_RXCHAN_BASEL_BRBL_S) & \
192 PAS_DMA_RXCHAN_BASEL_BRBL_M)
193#define PAS_DMA_RXCHAN_BASEU(c) (0x81c+(c)*_PAS_DMA_RXCHAN_STRIDE)
194#define PAS_DMA_RXCHAN_BASEU_BRBH_M 0x00000fff
195#define PAS_DMA_RXCHAN_BASEU_BRBH_S 0
196#define PAS_DMA_RXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_RXCHAN_BASEU_BRBH_S) & \
197 PAS_DMA_RXCHAN_BASEU_BRBH_M)
198/* # of cache lines worth of buffer ring */
199#define PAS_DMA_RXCHAN_BASEU_SIZ_M 0x3fff0000
200#define PAS_DMA_RXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */
201#define PAS_DMA_RXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_RXCHAN_BASEU_SIZ_S) & \
202 PAS_DMA_RXCHAN_BASEU_SIZ_M)
203
204#define PAS_STATUS_PCNT_M 0x000000000000ffffull
205#define PAS_STATUS_PCNT_S 0
206#define PAS_STATUS_DCNT_M 0x00000000ffff0000ull
207#define PAS_STATUS_DCNT_S 16
208#define PAS_STATUS_BPCNT_M 0x0000ffff00000000ull
209#define PAS_STATUS_BPCNT_S 32
210#define PAS_STATUS_CAUSE_M 0xf000000000000000ull
211#define PAS_STATUS_TIMER 0x1000000000000000ull
212#define PAS_STATUS_ERROR 0x2000000000000000ull
213#define PAS_STATUS_SOFT 0x4000000000000000ull
214#define PAS_STATUS_INT 0x8000000000000000ull
215
216#define PAS_IOB_COM_PKTHDRCNT 0x120
217#define PAS_IOB_COM_PKTHDRCNT_PKTHDR1_M 0x0fff0000
218#define PAS_IOB_COM_PKTHDRCNT_PKTHDR1_S 16
219#define PAS_IOB_COM_PKTHDRCNT_PKTHDR0_M 0x00000fff
220#define PAS_IOB_COM_PKTHDRCNT_PKTHDR0_S 0
221
222#define PAS_IOB_DMA_RXCH_CFG(i) (0x1100 + (i)*4)
223#define PAS_IOB_DMA_RXCH_CFG_CNTTH_M 0x00000fff
224#define PAS_IOB_DMA_RXCH_CFG_CNTTH_S 0
225#define PAS_IOB_DMA_RXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_RXCH_CFG_CNTTH_S) & \
226 PAS_IOB_DMA_RXCH_CFG_CNTTH_M)
227#define PAS_IOB_DMA_TXCH_CFG(i) (0x1200 + (i)*4)
228#define PAS_IOB_DMA_TXCH_CFG_CNTTH_M 0x00000fff
229#define PAS_IOB_DMA_TXCH_CFG_CNTTH_S 0
230#define PAS_IOB_DMA_TXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_TXCH_CFG_CNTTH_S) & \
231 PAS_IOB_DMA_TXCH_CFG_CNTTH_M)
232#define PAS_IOB_DMA_RXCH_STAT(i) (0x1300 + (i)*4)
233#define PAS_IOB_DMA_RXCH_STAT_INTGEN 0x00001000
234#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_M 0x00000fff
235#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_S 0
236#define PAS_IOB_DMA_RXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_RXCH_STAT_CNTDEL_S) &\
237 PAS_IOB_DMA_RXCH_STAT_CNTDEL_M)
238#define PAS_IOB_DMA_TXCH_STAT(i) (0x1400 + (i)*4)
239#define PAS_IOB_DMA_TXCH_STAT_INTGEN 0x00001000
240#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_M 0x00000fff
241#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_S 0
242#define PAS_IOB_DMA_TXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_TXCH_STAT_CNTDEL_S) &\
243 PAS_IOB_DMA_TXCH_STAT_CNTDEL_M)
244#define PAS_IOB_DMA_RXCH_RESET(i) (0x1500 + (i)*4)
245#define PAS_IOB_DMA_RXCH_RESET_PCNT_M 0xffff0000
246#define PAS_IOB_DMA_RXCH_RESET_PCNT_S 16
247#define PAS_IOB_DMA_RXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_RXCH_RESET_PCNT_S) & \
248 PAS_IOB_DMA_RXCH_RESET_PCNT_M)
249#define PAS_IOB_DMA_RXCH_RESET_PCNTRST 0x00000020
250#define PAS_IOB_DMA_RXCH_RESET_DCNTRST 0x00000010
251#define PAS_IOB_DMA_RXCH_RESET_TINTC 0x00000008
252#define PAS_IOB_DMA_RXCH_RESET_DINTC 0x00000004
253#define PAS_IOB_DMA_RXCH_RESET_SINTC 0x00000002
254#define PAS_IOB_DMA_RXCH_RESET_PINTC 0x00000001
255#define PAS_IOB_DMA_TXCH_RESET(i) (0x1600 + (i)*4)
256#define PAS_IOB_DMA_TXCH_RESET_PCNT_M 0xffff0000
257#define PAS_IOB_DMA_TXCH_RESET_PCNT_S 16
258#define PAS_IOB_DMA_TXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_TXCH_RESET_PCNT_S) & \
259 PAS_IOB_DMA_TXCH_RESET_PCNT_M)
260#define PAS_IOB_DMA_TXCH_RESET_PCNTRST 0x00000020
261#define PAS_IOB_DMA_TXCH_RESET_DCNTRST 0x00000010
262#define PAS_IOB_DMA_TXCH_RESET_TINTC 0x00000008
263#define PAS_IOB_DMA_TXCH_RESET_DINTC 0x00000004
264#define PAS_IOB_DMA_TXCH_RESET_SINTC 0x00000002
265#define PAS_IOB_DMA_TXCH_RESET_PINTC 0x00000001
266
267#define PAS_IOB_DMA_COM_TIMEOUTCFG 0x1700
268#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M 0x00ffffff
269#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S 0
270#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(x) (((x) << PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S) & \
271 PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M)
272
273/* Transmit descriptor fields */
274#define XCT_MACTX_T 0x8000000000000000ull
275#define XCT_MACTX_ST 0x4000000000000000ull
276#define XCT_MACTX_NORES 0x0000000000000000ull
277#define XCT_MACTX_8BRES 0x1000000000000000ull
278#define XCT_MACTX_24BRES 0x2000000000000000ull
279#define XCT_MACTX_40BRES 0x3000000000000000ull
280#define XCT_MACTX_I 0x0800000000000000ull
281#define XCT_MACTX_O 0x0400000000000000ull
282#define XCT_MACTX_E 0x0200000000000000ull
283#define XCT_MACTX_VLAN_M 0x0180000000000000ull
284#define XCT_MACTX_VLAN_NOP 0x0000000000000000ull
285#define XCT_MACTX_VLAN_REMOVE 0x0080000000000000ull
286#define XCT_MACTX_VLAN_INSERT 0x0100000000000000ull
287#define XCT_MACTX_VLAN_REPLACE 0x0180000000000000ull
288#define XCT_MACTX_CRC_M 0x0060000000000000ull
289#define XCT_MACTX_CRC_NOP 0x0000000000000000ull
290#define XCT_MACTX_CRC_INSERT 0x0020000000000000ull
291#define XCT_MACTX_CRC_PAD 0x0040000000000000ull
292#define XCT_MACTX_CRC_REPLACE 0x0060000000000000ull
293#define XCT_MACTX_SS 0x0010000000000000ull
294#define XCT_MACTX_LLEN_M 0x00007fff00000000ull
295#define XCT_MACTX_LLEN_S 32ull
296#define XCT_MACTX_LLEN(x) ((((long)(x)) << XCT_MACTX_LLEN_S) & \
297 XCT_MACTX_LLEN_M)
298#define XCT_MACTX_IPH_M 0x00000000f8000000ull
299#define XCT_MACTX_IPH_S 27ull
300#define XCT_MACTX_IPH(x) ((((long)(x)) << XCT_MACTX_IPH_S) & \
301 XCT_MACTX_IPH_M)
302#define XCT_MACTX_IPO_M 0x0000000007c00000ull
303#define XCT_MACTX_IPO_S 22ull
304#define XCT_MACTX_IPO(x) ((((long)(x)) << XCT_MACTX_IPO_S) & \
305 XCT_MACTX_IPO_M)
306#define XCT_MACTX_CSUM_M 0x0000000000000060ull
307#define XCT_MACTX_CSUM_NOP 0x0000000000000000ull
308#define XCT_MACTX_CSUM_TCP 0x0000000000000040ull
309#define XCT_MACTX_CSUM_UDP 0x0000000000000060ull
310#define XCT_MACTX_V6 0x0000000000000010ull
311#define XCT_MACTX_C 0x0000000000000004ull
312#define XCT_MACTX_AL2 0x0000000000000002ull
313
314/* Receive descriptor fields */
315#define XCT_MACRX_T 0x8000000000000000ull
316#define XCT_MACRX_ST 0x4000000000000000ull
317#define XCT_MACRX_RR_M 0x3000000000000000ull
318#define XCT_MACRX_RR_NORES 0x0000000000000000ull
319#define XCT_MACRX_RR_8BRES 0x1000000000000000ull
320#define XCT_MACRX_O 0x0400000000000000ull
321#define XCT_MACRX_E 0x0200000000000000ull
322#define XCT_MACRX_FF 0x0100000000000000ull
323#define XCT_MACRX_PF 0x0080000000000000ull
324#define XCT_MACRX_OB 0x0040000000000000ull
325#define XCT_MACRX_OD 0x0020000000000000ull
326#define XCT_MACRX_FS 0x0010000000000000ull
327#define XCT_MACRX_NB_M 0x000fc00000000000ull
328#define XCT_MACRX_NB_S 46ULL
329#define XCT_MACRX_NB(x) ((((long)(x)) << XCT_MACRX_NB_S) & \
330 XCT_MACRX_NB_M)
331#define XCT_MACRX_LLEN_M 0x00003fff00000000ull
332#define XCT_MACRX_LLEN_S 32ULL
333#define XCT_MACRX_LLEN(x) ((((long)(x)) << XCT_MACRX_LLEN_S) & \
334 XCT_MACRX_LLEN_M)
335#define XCT_MACRX_CRC 0x0000000080000000ull
336#define XCT_MACRX_LEN_M 0x0000000060000000ull
337#define XCT_MACRX_LEN_TOOSHORT 0x0000000020000000ull
338#define XCT_MACRX_LEN_BELOWMIN 0x0000000040000000ull
339#define XCT_MACRX_LEN_TRUNC 0x0000000060000000ull
340#define XCT_MACRX_CAST_M 0x0000000018000000ull
341#define XCT_MACRX_CAST_UNI 0x0000000000000000ull
342#define XCT_MACRX_CAST_MULTI 0x0000000008000000ull
343#define XCT_MACRX_CAST_BROAD 0x0000000010000000ull
344#define XCT_MACRX_CAST_PAUSE 0x0000000018000000ull
345#define XCT_MACRX_VLC_M 0x0000000006000000ull
346#define XCT_MACRX_FM 0x0000000001000000ull
347#define XCT_MACRX_HTY_M 0x0000000000c00000ull
348#define XCT_MACRX_HTY_IPV4_OK 0x0000000000000000ull
349#define XCT_MACRX_HTY_IPV6 0x0000000000400000ull
350#define XCT_MACRX_HTY_IPV4_BAD 0x0000000000800000ull
351#define XCT_MACRX_HTY_NONIP 0x0000000000c00000ull
352#define XCT_MACRX_IPP_M 0x00000000003f0000ull
353#define XCT_MACRX_IPP_S 16
354#define XCT_MACRX_CSUM_M 0x000000000000ffffull
355#define XCT_MACRX_CSUM_S 0
356
357#define XCT_PTR_T 0x8000000000000000ull
358#define XCT_PTR_LEN_M 0x7ffff00000000000ull
359#define XCT_PTR_LEN_S 44
360#define XCT_PTR_LEN(x) ((((long)(x)) << XCT_PTR_LEN_S) & \
361 XCT_PTR_LEN_M)
362#define XCT_PTR_ADDR_M 0x00000fffffffffffull
363#define XCT_PTR_ADDR_S 0
364#define XCT_PTR_ADDR(x) ((((long)(x)) << XCT_PTR_ADDR_S) & \
365 XCT_PTR_ADDR_M)
366
367/* Receive interface 8byte result fields */
368#define XCT_RXRES_8B_L4O_M 0xff00000000000000ull
369#define XCT_RXRES_8B_L4O_S 56
370#define XCT_RXRES_8B_RULE_M 0x00ffff0000000000ull
371#define XCT_RXRES_8B_RULE_S 40
372#define XCT_RXRES_8B_EVAL_M 0x000000ffff000000ull
373#define XCT_RXRES_8B_EVAL_S 24
374#define XCT_RXRES_8B_HTYPE_M 0x0000000000f00000ull
375#define XCT_RXRES_8B_HASH_M 0x00000000000fffffull
376#define XCT_RXRES_8B_HASH_S 0
377
378/* Receive interface buffer fields */
379#define XCT_RXB_LEN_M 0x0ffff00000000000ull
380#define XCT_RXB_LEN_S 44
381#define XCT_RXB_LEN(x) ((((long)(x)) << XCT_RXB_LEN_S) & \
382 XCT_RXB_LEN_M)
383#define XCT_RXB_ADDR_M 0x00000fffffffffffull
384#define XCT_RXB_ADDR_S 0
385#define XCT_RXB_ADDR(x) ((((long)(x)) << XCT_RXB_ADDR_S) & \
386 XCT_RXB_ADDR_M)
387
388/* Copy descriptor fields */
389#define XCT_COPY_T 0x8000000000000000ull
390#define XCT_COPY_ST 0x4000000000000000ull
391#define XCT_COPY_RR_M 0x3000000000000000ull
392#define XCT_COPY_RR_NORES 0x0000000000000000ull
393#define XCT_COPY_RR_8BRES 0x1000000000000000ull
394#define XCT_COPY_RR_24BRES 0x2000000000000000ull
395#define XCT_COPY_RR_40BRES 0x3000000000000000ull
396#define XCT_COPY_I 0x0800000000000000ull
397#define XCT_COPY_O 0x0400000000000000ull
398#define XCT_COPY_E 0x0200000000000000ull
399#define XCT_COPY_STY_ZERO 0x01c0000000000000ull
400#define XCT_COPY_DTY_PREF 0x0038000000000000ull
401#define XCT_COPY_LLEN_M 0x0007ffff00000000ull
402#define XCT_COPY_LLEN_S 32
403#define XCT_COPY_LLEN(x) ((((long)(x)) << XCT_COPY_LLEN_S) & \
404 XCT_COPY_LLEN_M)
405#define XCT_COPY_SE 0x0000000000000001ull
406
407/* Function descriptor fields */
408#define XCT_FUN_T 0x8000000000000000ull
409#define XCT_FUN_ST 0x4000000000000000ull
410#define XCT_FUN_RR_M 0x3000000000000000ull
411#define XCT_FUN_RR_NORES 0x0000000000000000ull
412#define XCT_FUN_RR_8BRES 0x1000000000000000ull
413#define XCT_FUN_RR_24BRES 0x2000000000000000ull
414#define XCT_FUN_RR_40BRES 0x3000000000000000ull
415#define XCT_FUN_I 0x0800000000000000ull
416#define XCT_FUN_O 0x0400000000000000ull
417#define XCT_FUN_E 0x0200000000000000ull
418#define XCT_FUN_FUN_M 0x01c0000000000000ull
419#define XCT_FUN_FUN_S 54
420#define XCT_FUN_FUN(x) ((((long)(x)) << XCT_FUN_FUN_S) & XCT_FUN_FUN_M)
421#define XCT_FUN_CRM_M 0x0038000000000000ull
422#define XCT_FUN_CRM_NOP 0x0000000000000000ull
423#define XCT_FUN_CRM_SIG 0x0008000000000000ull
424#define XCT_FUN_LLEN_M 0x0007ffff00000000ull
425#define XCT_FUN_LLEN_S 32
426#define XCT_FUN_LLEN(x) ((((long)(x)) << XCT_FUN_LLEN_S) & XCT_FUN_LLEN_M)
427#define XCT_FUN_SHL_M 0x00000000f8000000ull
428#define XCT_FUN_SHL_S 27
429#define XCT_FUN_SHL(x) ((((long)(x)) << XCT_FUN_SHL_S) & XCT_FUN_SHL_M)
430#define XCT_FUN_CHL_M 0x0000000007c00000ull
431#define XCT_FUN_HSZ_M 0x00000000003c0000ull
432#define XCT_FUN_ALG_M 0x0000000000038000ull
433#define XCT_FUN_HP 0x0000000000004000ull
434#define XCT_FUN_BCM_M 0x0000000000003800ull
435#define XCT_FUN_BCP_M 0x0000000000000600ull
436#define XCT_FUN_SIG_M 0x00000000000001f0ull
437#define XCT_FUN_SIG_TCP4 0x0000000000000140ull
438#define XCT_FUN_SIG_TCP6 0x0000000000000150ull
439#define XCT_FUN_SIG_UDP4 0x0000000000000160ull
440#define XCT_FUN_SIG_UDP6 0x0000000000000170ull
441#define XCT_FUN_A 0x0000000000000008ull
442#define XCT_FUN_C 0x0000000000000004ull
443#define XCT_FUN_AL2 0x0000000000000002ull
444#define XCT_FUN_SE 0x0000000000000001ull
445
446/* Function descriptor 8byte result fields */
447#define XCT_FUNRES_8B_CS_M 0x0000ffff00000000ull
448#define XCT_FUNRES_8B_CS_S 32
449#define XCT_FUNRES_8B_CRC_M 0x00000000ffffffffull
450#define XCT_FUNRES_8B_CRC_S 0
451
452/* Control descriptor fields */
453#define CTRL_CMD_T 0x8000000000000000ull
454#define CTRL_CMD_META_EVT 0x2000000000000000ull
455#define CTRL_CMD_O 0x0400000000000000ull
456#define CTRL_CMD_ETYPE_M 0x0038000000000000ull
457#define CTRL_CMD_ETYPE_EXT 0x0000000000000000ull
458#define CTRL_CMD_ETYPE_WSET 0x0020000000000000ull
459#define CTRL_CMD_ETYPE_WCLR 0x0028000000000000ull
460#define CTRL_CMD_ETYPE_SET 0x0030000000000000ull
461#define CTRL_CMD_ETYPE_CLR 0x0038000000000000ull
462#define CTRL_CMD_REG_M 0x000000000000007full
463#define CTRL_CMD_REG_S 0
464#define CTRL_CMD_REG(x) ((((long)(x)) << CTRL_CMD_REG_S) & \
465 CTRL_CMD_REG_M)
466
467
468
469/* Prototypes for the shared DMA functions in the platform code. */
470
471/* DMA TX Channel type. Right now only limitations used are event types 0/1,
472 * for event-triggered DMA transactions.
473 */
474
475enum pasemi_dmachan_type {
476 RXCHAN = 0, /* Any RX chan */
477 TXCHAN = 1, /* Any TX chan */
478 TXCHAN_EVT0 = 0x1001, /* TX chan in event class 0 (chan 0-9) */
479 TXCHAN_EVT1 = 0x2001, /* TX chan in event class 1 (chan 10-19) */
480};
481
482struct pasemi_dmachan {
483 int chno; /* Channel number */
484 enum pasemi_dmachan_type chan_type; /* TX / RX */
485 u64 *status; /* Ptr to cacheable status */
486 int irq; /* IRQ used by channel */
487 unsigned int ring_size; /* size of allocated ring */
488 dma_addr_t ring_dma; /* DMA address for ring */
489 u64 *ring_virt; /* Virt address for ring */
490 void *priv; /* Ptr to start of client struct */
491};
492
493/* Read/write the different registers in the I/O Bridge, Ethernet
494 * and DMA Controller
495 */
496extern unsigned int pasemi_read_iob_reg(unsigned int reg);
497extern void pasemi_write_iob_reg(unsigned int reg, unsigned int val);
498
499extern unsigned int pasemi_read_mac_reg(int intf, unsigned int reg);
500extern void pasemi_write_mac_reg(int intf, unsigned int reg, unsigned int val);
501
502extern unsigned int pasemi_read_dma_reg(unsigned int reg);
503extern void pasemi_write_dma_reg(unsigned int reg, unsigned int val);
504
505/* Channel management routines */
506
507extern void *pasemi_dma_alloc_chan(enum pasemi_dmachan_type type,
508 int total_size, int offset);
509extern void pasemi_dma_free_chan(struct pasemi_dmachan *chan);
510
511extern void pasemi_dma_start_chan(const struct pasemi_dmachan *chan,
512 const u32 cmdsta);
513extern int pasemi_dma_stop_chan(const struct pasemi_dmachan *chan);
514
515/* Common routines to allocate rings and buffers */
516
517extern int pasemi_dma_alloc_ring(struct pasemi_dmachan *chan, int ring_size);
518extern void pasemi_dma_free_ring(struct pasemi_dmachan *chan);
519
520extern void *pasemi_dma_alloc_buf(struct pasemi_dmachan *chan, int size,
521 dma_addr_t *handle);
522extern void pasemi_dma_free_buf(struct pasemi_dmachan *chan, int size,
523 dma_addr_t *handle);
524
525/* Routines to allocate flags (events) for channel syncronization */
526extern int pasemi_dma_alloc_flag(void);
527extern void pasemi_dma_free_flag(int flag);
528extern void pasemi_dma_set_flag(int flag);
529extern void pasemi_dma_clear_flag(int flag);
530
531/* Routines to allocate function engines */
532extern int pasemi_dma_alloc_fun(void);
533extern void pasemi_dma_free_fun(int fun);
534
535/* Initialize the library, must be called before any other functions */
536extern int pasemi_dma_init(void);
537
538#endif /* ASM_PASEMI_DMA_H */
diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h
deleted file mode 100644
index ae2ea803a0f..00000000000
--- a/include/asm-powerpc/pci-bridge.h
+++ /dev/null
@@ -1,302 +0,0 @@
1#ifndef _ASM_POWERPC_PCI_BRIDGE_H
2#define _ASM_POWERPC_PCI_BRIDGE_H
3#ifdef __KERNEL__
4/*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10#include <linux/pci.h>
11#include <linux/list.h>
12#include <linux/ioport.h>
13
14struct device_node;
15
16extern unsigned int ppc_pci_flags;
17enum {
18 /* Force re-assigning all resources (ignore firmware
19 * setup completely)
20 */
21 PPC_PCI_REASSIGN_ALL_RSRC = 0x00000001,
22
23 /* Re-assign all bus numbers */
24 PPC_PCI_REASSIGN_ALL_BUS = 0x00000002,
25
26 /* Do not try to assign, just use existing setup */
27 PPC_PCI_PROBE_ONLY = 0x00000004,
28
29 /* Don't bother with ISA alignment unless the bridge has
30 * ISA forwarding enabled
31 */
32 PPC_PCI_CAN_SKIP_ISA_ALIGN = 0x00000008,
33
34 /* Enable domain numbers in /proc */
35 PPC_PCI_ENABLE_PROC_DOMAINS = 0x00000010,
36 /* ... except for domain 0 */
37 PPC_PCI_COMPAT_DOMAIN_0 = 0x00000020,
38};
39
40
41/*
42 * Structure of a PCI controller (host bridge)
43 */
44struct pci_controller {
45 struct pci_bus *bus;
46 char is_dynamic;
47#ifdef CONFIG_PPC64
48 int node;
49#endif
50 struct device_node *dn;
51 struct list_head list_node;
52 struct device *parent;
53
54 int first_busno;
55 int last_busno;
56#ifndef CONFIG_PPC64
57 int self_busno;
58#endif
59
60 void __iomem *io_base_virt;
61#ifdef CONFIG_PPC64
62 void *io_base_alloc;
63#endif
64 resource_size_t io_base_phys;
65#ifndef CONFIG_PPC64
66 resource_size_t pci_io_size;
67#endif
68
69 /* Some machines (PReP) have a non 1:1 mapping of
70 * the PCI memory space in the CPU bus space
71 */
72 resource_size_t pci_mem_offset;
73#ifdef CONFIG_PPC64
74 unsigned long pci_io_size;
75#endif
76
77 struct pci_ops *ops;
78 unsigned int __iomem *cfg_addr;
79 void __iomem *cfg_data;
80
81#ifndef CONFIG_PPC64
82 /*
83 * Used for variants of PCI indirect handling and possible quirks:
84 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
85 * EXT_REG - provides access to PCI-e extended registers
86 * SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS
87 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
88 * to determine which bus number to match on when generating type0
89 * config cycles
90 * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
91 * hanging if we don't have link and try to do config cycles to
92 * anything but the PHB. Only allow talking to the PHB if this is
93 * set.
94 * BIG_ENDIAN - cfg_addr is a big endian register
95 * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
96 * the PLB4. Effectively disable MRM commands by setting this.
97 */
98#define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
99#define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
100#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
101#define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
102#define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
103#define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020
104 u32 indirect_type;
105#endif /* !CONFIG_PPC64 */
106 /* Currently, we limit ourselves to 1 IO range and 3 mem
107 * ranges since the common pci_bus structure can't handle more
108 */
109 struct resource io_resource;
110 struct resource mem_resources[3];
111 int global_number; /* PCI domain number */
112#ifdef CONFIG_PPC64
113 unsigned long buid;
114 unsigned long dma_window_base_cur;
115 unsigned long dma_window_size;
116
117 void *private_data;
118#endif /* CONFIG_PPC64 */
119};
120
121#ifndef CONFIG_PPC64
122
123static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
124{
125 return bus->sysdata;
126}
127
128static inline int isa_vaddr_is_ioport(void __iomem *address)
129{
130 /* No specific ISA handling on ppc32 at this stage, it
131 * all goes through PCI
132 */
133 return 0;
134}
135
136/* These are used for config access before all the PCI probing
137 has been done. */
138extern int early_read_config_byte(struct pci_controller *hose, int bus,
139 int dev_fn, int where, u8 *val);
140extern int early_read_config_word(struct pci_controller *hose, int bus,
141 int dev_fn, int where, u16 *val);
142extern int early_read_config_dword(struct pci_controller *hose, int bus,
143 int dev_fn, int where, u32 *val);
144extern int early_write_config_byte(struct pci_controller *hose, int bus,
145 int dev_fn, int where, u8 val);
146extern int early_write_config_word(struct pci_controller *hose, int bus,
147 int dev_fn, int where, u16 val);
148extern int early_write_config_dword(struct pci_controller *hose, int bus,
149 int dev_fn, int where, u32 val);
150
151extern int early_find_capability(struct pci_controller *hose, int bus,
152 int dev_fn, int cap);
153
154extern void setup_indirect_pci(struct pci_controller* hose,
155 resource_size_t cfg_addr,
156 resource_size_t cfg_data, u32 flags);
157extern void setup_grackle(struct pci_controller *hose);
158#else /* CONFIG_PPC64 */
159
160/*
161 * PCI stuff, for nodes representing PCI devices, pointed to
162 * by device_node->data.
163 */
164struct iommu_table;
165
166struct pci_dn {
167 int busno; /* pci bus number */
168 int devfn; /* pci device and function number */
169
170 struct pci_controller *phb; /* for pci devices */
171 struct iommu_table *iommu_table; /* for phb's or bridges */
172 struct device_node *node; /* back-pointer to the device_node */
173
174 int pci_ext_config_space; /* for pci devices */
175
176#ifdef CONFIG_EEH
177 struct pci_dev *pcidev; /* back-pointer to the pci device */
178 int class_code; /* pci device class */
179 int eeh_mode; /* See eeh.h for possible EEH_MODEs */
180 int eeh_config_addr;
181 int eeh_pe_config_addr; /* new-style partition endpoint address */
182 int eeh_check_count; /* # times driver ignored error */
183 int eeh_freeze_count; /* # times this device froze up. */
184 int eeh_false_positives; /* # times this device reported #ff's */
185 u32 config_space[16]; /* saved PCI config space */
186#endif
187};
188
189/* Get the pointer to a device_node's pci_dn */
190#define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
191
192extern struct device_node *fetch_dev_dn(struct pci_dev *dev);
193
194/* Get a device_node from a pci_dev. This code must be fast except
195 * in the case where the sysdata is incorrect and needs to be fixed
196 * up (this will only happen once).
197 * In this case the sysdata will have been inherited from a PCI host
198 * bridge or a PCI-PCI bridge further up the tree, so it will point
199 * to a valid struct pci_dn, just not the one we want.
200 */
201static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev)
202{
203 struct device_node *dn = dev->sysdata;
204 struct pci_dn *pdn = dn->data;
205
206 if (pdn && pdn->devfn == dev->devfn && pdn->busno == dev->bus->number)
207 return dn; /* fast path. sysdata is good */
208 return fetch_dev_dn(dev);
209}
210
211static inline int pci_device_from_OF_node(struct device_node *np,
212 u8 *bus, u8 *devfn)
213{
214 if (!PCI_DN(np))
215 return -ENODEV;
216 *bus = PCI_DN(np)->busno;
217 *devfn = PCI_DN(np)->devfn;
218 return 0;
219}
220
221static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
222{
223 if (bus->self)
224 return pci_device_to_OF_node(bus->self);
225 else
226 return bus->sysdata; /* Must be root bus (PHB) */
227}
228
229/** Find the bus corresponding to the indicated device node */
230extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);
231
232/** Remove all of the PCI devices under this bus */
233extern void pcibios_remove_pci_devices(struct pci_bus *bus);
234
235/** Discover new pci devices under this bus, and add them */
236extern void pcibios_add_pci_devices(struct pci_bus *bus);
237extern void pcibios_fixup_new_pci_devices(struct pci_bus *bus);
238
239extern int pcibios_remove_root_bus(struct pci_controller *phb);
240
241static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
242{
243 struct device_node *busdn = bus->sysdata;
244
245 BUG_ON(busdn == NULL);
246 return PCI_DN(busdn)->phb;
247}
248
249
250extern void isa_bridge_find_early(struct pci_controller *hose);
251
252static inline int isa_vaddr_is_ioport(void __iomem *address)
253{
254 /* Check if address hits the reserved legacy IO range */
255 unsigned long ea = (unsigned long)address;
256 return ea >= ISA_IO_BASE && ea < ISA_IO_END;
257}
258
259extern int pcibios_unmap_io_space(struct pci_bus *bus);
260extern int pcibios_map_io_space(struct pci_bus *bus);
261
262/* Return values for ppc_md.pci_probe_mode function */
263#define PCI_PROBE_NONE -1 /* Don't look at this bus at all */
264#define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */
265#define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */
266
267#ifdef CONFIG_NUMA
268#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
269#else
270#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
271#endif
272
273#endif /* CONFIG_PPC64 */
274
275/* Get the PCI host controller for an OF device */
276extern struct pci_controller *pci_find_hose_for_OF_device(
277 struct device_node* node);
278
279/* Fill up host controller resources from the OF node */
280extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
281 struct device_node *dev, int primary);
282
283/* Allocate & free a PCI host bridge structure */
284extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
285extern void pcibios_free_controller(struct pci_controller *phb);
286
287#ifdef CONFIG_PCI
288extern unsigned long pci_address_to_pio(phys_addr_t address);
289extern int pcibios_vaddr_is_ioport(void __iomem *address);
290#else
291static inline unsigned long pci_address_to_pio(phys_addr_t address)
292{
293 return (unsigned long)-1;
294}
295static inline int pcibios_vaddr_is_ioport(void __iomem *address)
296{
297 return 0;
298}
299#endif /* CONFIG_PCI */
300
301#endif /* __KERNEL__ */
302#endif /* _ASM_POWERPC_PCI_BRIDGE_H */
diff --git a/include/asm-powerpc/pci.h b/include/asm-powerpc/pci.h
deleted file mode 100644
index a05a942b1c2..00000000000
--- a/include/asm-powerpc/pci.h
+++ /dev/null
@@ -1,228 +0,0 @@
1#ifndef __ASM_POWERPC_PCI_H
2#define __ASM_POWERPC_PCI_H
3#ifdef __KERNEL__
4
5/*
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#include <linux/types.h>
13#include <linux/slab.h>
14#include <linux/string.h>
15#include <linux/dma-mapping.h>
16
17#include <asm/machdep.h>
18#include <asm/scatterlist.h>
19#include <asm/io.h>
20#include <asm/prom.h>
21#include <asm/pci-bridge.h>
22
23#include <asm-generic/pci-dma-compat.h>
24
25#define PCIBIOS_MIN_IO 0x1000
26#define PCIBIOS_MIN_MEM 0x10000000
27
28struct pci_dev;
29
30/* Values for the `which' argument to sys_pciconfig_iobase syscall. */
31#define IOBASE_BRIDGE_NUMBER 0
32#define IOBASE_MEMORY 1
33#define IOBASE_IO 2
34#define IOBASE_ISA_IO 3
35#define IOBASE_ISA_MEM 4
36
37/*
38 * Set this to 1 if you want the kernel to re-assign all PCI
39 * bus numbers (don't do that on ppc64 yet !)
40 */
41#define pcibios_assign_all_busses() (ppc_pci_flags & \
42 PPC_PCI_REASSIGN_ALL_BUS)
43#define pcibios_scan_all_fns(a, b) 0
44
45static inline void pcibios_set_master(struct pci_dev *dev)
46{
47 /* No special bus mastering setup handling */
48}
49
50static inline void pcibios_penalize_isa_irq(int irq, int active)
51{
52 /* We don't do dynamic PCI IRQ allocation */
53}
54
55#define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
56static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
57{
58 if (ppc_md.pci_get_legacy_ide_irq)
59 return ppc_md.pci_get_legacy_ide_irq(dev, channel);
60 return channel ? 15 : 14;
61}
62
63#ifdef CONFIG_PPC64
64
65/*
66 * We want to avoid touching the cacheline size or MWI bit.
67 * pSeries firmware sets the cacheline size (which is not the cpu cacheline
68 * size in all cases) and hardware treats MWI the same as memory write.
69 */
70#define PCI_DISABLE_MWI
71
72#ifdef CONFIG_PCI
73extern void set_pci_dma_ops(struct dma_mapping_ops *dma_ops);
74extern struct dma_mapping_ops *get_pci_dma_ops(void);
75
76static inline void pci_dma_burst_advice(struct pci_dev *pdev,
77 enum pci_dma_burst_strategy *strat,
78 unsigned long *strategy_parameter)
79{
80 unsigned long cacheline_size;
81 u8 byte;
82
83 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
84 if (byte == 0)
85 cacheline_size = 1024;
86 else
87 cacheline_size = (int) byte * 4;
88
89 *strat = PCI_DMA_BURST_MULTIPLE;
90 *strategy_parameter = cacheline_size;
91}
92#else /* CONFIG_PCI */
93#define set_pci_dma_ops(d)
94#define get_pci_dma_ops() NULL
95#endif
96
97#else /* 32-bit */
98
99#ifdef CONFIG_PCI
100static inline void pci_dma_burst_advice(struct pci_dev *pdev,
101 enum pci_dma_burst_strategy *strat,
102 unsigned long *strategy_parameter)
103{
104 *strat = PCI_DMA_BURST_INFINITY;
105 *strategy_parameter = ~0UL;
106}
107#endif
108#endif /* CONFIG_PPC64 */
109
110extern int pci_domain_nr(struct pci_bus *bus);
111
112/* Decide whether to display the domain number in /proc */
113extern int pci_proc_domain(struct pci_bus *bus);
114
115
116struct vm_area_struct;
117/* Map a range of PCI memory or I/O space for a device into user space */
118int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
119 enum pci_mmap_state mmap_state, int write_combine);
120
121/* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */
122#define HAVE_PCI_MMAP 1
123
124#if defined(CONFIG_PPC64) || defined(CONFIG_NOT_COHERENT_CACHE)
125/*
126 * For 64-bit kernels, pci_unmap_{single,page} is not a nop.
127 * For 32-bit non-coherent kernels, pci_dma_sync_single_for_cpu() and
128 * so on are not nops.
129 * and thus...
130 */
131#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
132 dma_addr_t ADDR_NAME;
133#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
134 __u32 LEN_NAME;
135#define pci_unmap_addr(PTR, ADDR_NAME) \
136 ((PTR)->ADDR_NAME)
137#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
138 (((PTR)->ADDR_NAME) = (VAL))
139#define pci_unmap_len(PTR, LEN_NAME) \
140 ((PTR)->LEN_NAME)
141#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
142 (((PTR)->LEN_NAME) = (VAL))
143
144#else /* 32-bit && coherent */
145
146/* pci_unmap_{page,single} is a nop so... */
147#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
148#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
149#define pci_unmap_addr(PTR, ADDR_NAME) (0)
150#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
151#define pci_unmap_len(PTR, LEN_NAME) (0)
152#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0)
153
154#endif /* CONFIG_PPC64 || CONFIG_NOT_COHERENT_CACHE */
155
156#ifdef CONFIG_PPC64
157
158/* The PCI address space does not equal the physical memory address
159 * space (we have an IOMMU). The IDE and SCSI device layers use
160 * this boolean for bounce buffer decisions.
161 */
162#define PCI_DMA_BUS_IS_PHYS (0)
163
164#else /* 32-bit */
165
166/* The PCI address space does equal the physical memory
167 * address space (no IOMMU). The IDE and SCSI device layers use
168 * this boolean for bounce buffer decisions.
169 */
170#define PCI_DMA_BUS_IS_PHYS (1)
171
172#endif /* CONFIG_PPC64 */
173
174extern void pcibios_resource_to_bus(struct pci_dev *dev,
175 struct pci_bus_region *region,
176 struct resource *res);
177
178extern void pcibios_bus_to_resource(struct pci_dev *dev,
179 struct resource *res,
180 struct pci_bus_region *region);
181
182static inline struct resource *pcibios_select_root(struct pci_dev *pdev,
183 struct resource *res)
184{
185 struct resource *root = NULL;
186
187 if (res->flags & IORESOURCE_IO)
188 root = &ioport_resource;
189 if (res->flags & IORESOURCE_MEM)
190 root = &iomem_resource;
191
192 return root;
193}
194
195extern void pcibios_setup_new_device(struct pci_dev *dev);
196
197extern void pcibios_claim_one_bus(struct pci_bus *b);
198
199extern void pcibios_resource_survey(void);
200
201extern struct pci_controller *init_phb_dynamic(struct device_node *dn);
202
203extern struct pci_dev *of_create_pci_dev(struct device_node *node,
204 struct pci_bus *bus, int devfn);
205
206extern void of_scan_pci_bridge(struct device_node *node,
207 struct pci_dev *dev);
208
209extern void of_scan_bus(struct device_node *node, struct pci_bus *bus);
210
211extern int pci_read_irq_line(struct pci_dev *dev);
212
213struct file;
214extern pgprot_t pci_phys_mem_access_prot(struct file *file,
215 unsigned long pfn,
216 unsigned long size,
217 pgprot_t prot);
218
219#define HAVE_ARCH_PCI_RESOURCE_TO_USER
220extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
221 const struct resource *rsrc,
222 resource_size_t *start, resource_size_t *end);
223
224extern void pcibios_do_bus_setup(struct pci_bus *bus);
225extern void pcibios_fixup_of_probed_bus(struct pci_bus *bus);
226
227#endif /* __KERNEL__ */
228#endif /* __ASM_POWERPC_PCI_H */
diff --git a/include/asm-powerpc/percpu.h b/include/asm-powerpc/percpu.h
deleted file mode 100644
index f879252b7ea..00000000000
--- a/include/asm-powerpc/percpu.h
+++ /dev/null
@@ -1,24 +0,0 @@
1#ifndef _ASM_POWERPC_PERCPU_H_
2#define _ASM_POWERPC_PERCPU_H_
3#ifdef __powerpc64__
4#include <linux/compiler.h>
5
6/*
7 * Same as asm-generic/percpu.h, except that we store the per cpu offset
8 * in the paca. Based on the x86-64 implementation.
9 */
10
11#ifdef CONFIG_SMP
12
13#include <asm/paca.h>
14
15#define __per_cpu_offset(cpu) (paca[cpu].data_offset)
16#define __my_cpu_offset local_paca->data_offset
17#define per_cpu_offset(x) (__per_cpu_offset(x))
18
19#endif /* CONFIG_SMP */
20#endif /* __powerpc64__ */
21
22#include <asm-generic/percpu.h>
23
24#endif /* _ASM_POWERPC_PERCPU_H_ */
diff --git a/include/asm-powerpc/pgalloc-32.h b/include/asm-powerpc/pgalloc-32.h
deleted file mode 100644
index 58c07147b3e..00000000000
--- a/include/asm-powerpc/pgalloc-32.h
+++ /dev/null
@@ -1,43 +0,0 @@
1#ifndef _ASM_POWERPC_PGALLOC_32_H
2#define _ASM_POWERPC_PGALLOC_32_H
3
4#include <linux/threads.h>
5
6extern void __bad_pte(pmd_t *pmd);
7
8extern pgd_t *pgd_alloc(struct mm_struct *mm);
9extern void pgd_free(struct mm_struct *mm, pgd_t *pgd);
10
11/*
12 * We don't have any real pmd's, and this code never triggers because
13 * the pgd will always be present..
14 */
15/* #define pmd_alloc_one(mm,address) ({ BUG(); ((pmd_t *)2); }) */
16#define pmd_free(mm, x) do { } while (0)
17#define __pmd_free_tlb(tlb,x) do { } while (0)
18/* #define pgd_populate(mm, pmd, pte) BUG() */
19
20#ifndef CONFIG_BOOKE
21#define pmd_populate_kernel(mm, pmd, pte) \
22 (pmd_val(*(pmd)) = __pa(pte) | _PMD_PRESENT)
23#define pmd_populate(mm, pmd, pte) \
24 (pmd_val(*(pmd)) = (page_to_pfn(pte) << PAGE_SHIFT) | _PMD_PRESENT)
25#define pmd_pgtable(pmd) pmd_page(pmd)
26#else
27#define pmd_populate_kernel(mm, pmd, pte) \
28 (pmd_val(*(pmd)) = (unsigned long)pte | _PMD_PRESENT)
29#define pmd_populate(mm, pmd, pte) \
30 (pmd_val(*(pmd)) = (unsigned long)lowmem_page_address(pte) | _PMD_PRESENT)
31#define pmd_pgtable(pmd) pmd_page(pmd)
32#endif
33
34extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr);
35extern pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long addr);
36extern void pte_free_kernel(struct mm_struct *mm, pte_t *pte);
37extern void pte_free(struct mm_struct *mm, pgtable_t pte);
38
39#define __pte_free_tlb(tlb, pte) pte_free((tlb)->mm, (pte))
40
41#define check_pgt_cache() do { } while (0)
42
43#endif /* _ASM_POWERPC_PGALLOC_32_H */
diff --git a/include/asm-powerpc/pgalloc-64.h b/include/asm-powerpc/pgalloc-64.h
deleted file mode 100644
index 812a1d8f35c..00000000000
--- a/include/asm-powerpc/pgalloc-64.h
+++ /dev/null
@@ -1,166 +0,0 @@
1#ifndef _ASM_POWERPC_PGALLOC_64_H
2#define _ASM_POWERPC_PGALLOC_64_H
3/*
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10#include <linux/mm.h>
11#include <linux/slab.h>
12#include <linux/cpumask.h>
13#include <linux/percpu.h>
14
15#ifndef CONFIG_PPC_SUBPAGE_PROT
16static inline void subpage_prot_free(pgd_t *pgd) {}
17#endif
18
19extern struct kmem_cache *pgtable_cache[];
20
21#define PGD_CACHE_NUM 0
22#define PUD_CACHE_NUM 1
23#define PMD_CACHE_NUM 1
24#define HUGEPTE_CACHE_NUM 2
25#define PTE_NONCACHE_NUM 7 /* from GFP rather than kmem_cache */
26
27static inline pgd_t *pgd_alloc(struct mm_struct *mm)
28{
29 return kmem_cache_alloc(pgtable_cache[PGD_CACHE_NUM], GFP_KERNEL);
30}
31
32static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
33{
34 subpage_prot_free(pgd);
35 kmem_cache_free(pgtable_cache[PGD_CACHE_NUM], pgd);
36}
37
38#ifndef CONFIG_PPC_64K_PAGES
39
40#define pgd_populate(MM, PGD, PUD) pgd_set(PGD, PUD)
41
42static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
43{
44 return kmem_cache_alloc(pgtable_cache[PUD_CACHE_NUM],
45 GFP_KERNEL|__GFP_REPEAT);
46}
47
48static inline void pud_free(struct mm_struct *mm, pud_t *pud)
49{
50 kmem_cache_free(pgtable_cache[PUD_CACHE_NUM], pud);
51}
52
53static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
54{
55 pud_set(pud, (unsigned long)pmd);
56}
57
58#define pmd_populate(mm, pmd, pte_page) \
59 pmd_populate_kernel(mm, pmd, page_address(pte_page))
60#define pmd_populate_kernel(mm, pmd, pte) pmd_set(pmd, (unsigned long)(pte))
61#define pmd_pgtable(pmd) pmd_page(pmd)
62
63
64#else /* CONFIG_PPC_64K_PAGES */
65
66#define pud_populate(mm, pud, pmd) pud_set(pud, (unsigned long)pmd)
67
68static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
69 pte_t *pte)
70{
71 pmd_set(pmd, (unsigned long)pte);
72}
73
74#define pmd_populate(mm, pmd, pte_page) \
75 pmd_populate_kernel(mm, pmd, page_address(pte_page))
76#define pmd_pgtable(pmd) pmd_page(pmd)
77
78#endif /* CONFIG_PPC_64K_PAGES */
79
80static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
81{
82 return kmem_cache_alloc(pgtable_cache[PMD_CACHE_NUM],
83 GFP_KERNEL|__GFP_REPEAT);
84}
85
86static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
87{
88 kmem_cache_free(pgtable_cache[PMD_CACHE_NUM], pmd);
89}
90
91static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
92 unsigned long address)
93{
94 return (pte_t *)__get_free_page(GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO);
95}
96
97static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
98 unsigned long address)
99{
100 struct page *page;
101 pte_t *pte;
102
103 pte = pte_alloc_one_kernel(mm, address);
104 if (!pte)
105 return NULL;
106 page = virt_to_page(pte);
107 pgtable_page_ctor(page);
108 return page;
109}
110
111static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
112{
113 free_page((unsigned long)pte);
114}
115
116static inline void pte_free(struct mm_struct *mm, pgtable_t ptepage)
117{
118 pgtable_page_dtor(ptepage);
119 __free_page(ptepage);
120}
121
122#define PGF_CACHENUM_MASK 0x7
123
124typedef struct pgtable_free {
125 unsigned long val;
126} pgtable_free_t;
127
128static inline pgtable_free_t pgtable_free_cache(void *p, int cachenum,
129 unsigned long mask)
130{
131 BUG_ON(cachenum > PGF_CACHENUM_MASK);
132
133 return (pgtable_free_t){.val = ((unsigned long) p & ~mask) | cachenum};
134}
135
136static inline void pgtable_free(pgtable_free_t pgf)
137{
138 void *p = (void *)(pgf.val & ~PGF_CACHENUM_MASK);
139 int cachenum = pgf.val & PGF_CACHENUM_MASK;
140
141 if (cachenum == PTE_NONCACHE_NUM)
142 free_page((unsigned long)p);
143 else
144 kmem_cache_free(pgtable_cache[cachenum], p);
145}
146
147extern void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf);
148
149#define __pte_free_tlb(tlb,ptepage) \
150do { \
151 pgtable_page_dtor(ptepage); \
152 pgtable_free_tlb(tlb, pgtable_free_cache(page_address(ptepage), \
153 PTE_NONCACHE_NUM, PTE_TABLE_SIZE-1)); \
154} while (0)
155#define __pmd_free_tlb(tlb, pmd) \
156 pgtable_free_tlb(tlb, pgtable_free_cache(pmd, \
157 PMD_CACHE_NUM, PMD_TABLE_SIZE-1))
158#ifndef CONFIG_PPC_64K_PAGES
159#define __pud_free_tlb(tlb, pud) \
160 pgtable_free_tlb(tlb, pgtable_free_cache(pud, \
161 PUD_CACHE_NUM, PUD_TABLE_SIZE-1))
162#endif /* CONFIG_PPC_64K_PAGES */
163
164#define check_pgt_cache() do { } while (0)
165
166#endif /* _ASM_POWERPC_PGALLOC_64_H */
diff --git a/include/asm-powerpc/pgalloc.h b/include/asm-powerpc/pgalloc.h
deleted file mode 100644
index b4505ed0f0f..00000000000
--- a/include/asm-powerpc/pgalloc.h
+++ /dev/null
@@ -1,12 +0,0 @@
1#ifndef _ASM_POWERPC_PGALLOC_H
2#define _ASM_POWERPC_PGALLOC_H
3#ifdef __KERNEL__
4
5#ifdef CONFIG_PPC64
6#include <asm/pgalloc-64.h>
7#else
8#include <asm/pgalloc-32.h>
9#endif
10
11#endif /* __KERNEL__ */
12#endif /* _ASM_POWERPC_PGALLOC_H */
diff --git a/include/asm-powerpc/pgtable-4k.h b/include/asm-powerpc/pgtable-4k.h
deleted file mode 100644
index c9601dfb4a1..00000000000
--- a/include/asm-powerpc/pgtable-4k.h
+++ /dev/null
@@ -1,115 +0,0 @@
1#ifndef _ASM_POWERPC_PGTABLE_4K_H
2#define _ASM_POWERPC_PGTABLE_4K_H
3/*
4 * Entries per page directory level. The PTE level must use a 64b record
5 * for each page table entry. The PMD and PGD level use a 32b record for
6 * each entry by assuming that each entry is page aligned.
7 */
8#define PTE_INDEX_SIZE 9
9#define PMD_INDEX_SIZE 7
10#define PUD_INDEX_SIZE 7
11#define PGD_INDEX_SIZE 9
12
13#ifndef __ASSEMBLY__
14#define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_INDEX_SIZE)
15#define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE)
16#define PUD_TABLE_SIZE (sizeof(pud_t) << PUD_INDEX_SIZE)
17#define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE)
18#endif /* __ASSEMBLY__ */
19
20#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
21#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
22#define PTRS_PER_PUD (1 << PMD_INDEX_SIZE)
23#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
24
25/* PMD_SHIFT determines what a second-level page table entry can map */
26#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
27#define PMD_SIZE (1UL << PMD_SHIFT)
28#define PMD_MASK (~(PMD_SIZE-1))
29
30/* With 4k base page size, hugepage PTEs go at the PMD level */
31#define MIN_HUGEPTE_SHIFT PMD_SHIFT
32
33/* PUD_SHIFT determines what a third-level page table entry can map */
34#define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
35#define PUD_SIZE (1UL << PUD_SHIFT)
36#define PUD_MASK (~(PUD_SIZE-1))
37
38/* PGDIR_SHIFT determines what a fourth-level page table entry can map */
39#define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE)
40#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
41#define PGDIR_MASK (~(PGDIR_SIZE-1))
42
43/* PTE bits */
44#define _PAGE_HASHPTE 0x0400 /* software: pte has an associated HPTE */
45#define _PAGE_SECONDARY 0x8000 /* software: HPTE is in secondary group */
46#define _PAGE_GROUP_IX 0x7000 /* software: HPTE index within group */
47#define _PAGE_F_SECOND _PAGE_SECONDARY
48#define _PAGE_F_GIX _PAGE_GROUP_IX
49
50/* PTE flags to conserve for HPTE identification */
51#define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | \
52 _PAGE_SECONDARY | _PAGE_GROUP_IX)
53
54/* There is no 4K PFN hack on 4K pages */
55#define _PAGE_4K_PFN 0
56
57/* PAGE_MASK gives the right answer below, but only by accident */
58/* It should be preserving the high 48 bits and then specifically */
59/* preserving _PAGE_SECONDARY | _PAGE_GROUP_IX */
60#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | \
61 _PAGE_HPTEFLAGS)
62
63/* Bits to mask out from a PMD to get to the PTE page */
64#define PMD_MASKED_BITS 0
65/* Bits to mask out from a PUD to get to the PMD page */
66#define PUD_MASKED_BITS 0
67/* Bits to mask out from a PGD to get to the PUD page */
68#define PGD_MASKED_BITS 0
69
70/* shift to put page number into pte */
71#define PTE_RPN_SHIFT (17)
72
73#ifdef STRICT_MM_TYPECHECKS
74#define __real_pte(e,p) ((real_pte_t){(e)})
75#define __rpte_to_pte(r) ((r).pte)
76#else
77#define __real_pte(e,p) (e)
78#define __rpte_to_pte(r) (__pte(r))
79#endif
80#define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> 12)
81
82#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
83 do { \
84 index = 0; \
85 shift = mmu_psize_defs[psize].shift; \
86
87#define pte_iterate_hashed_end() } while(0)
88
89#ifdef CONFIG_PPC_HAS_HASH_64K
90#define pte_pagesize_index(mm, addr, pte) get_slice_psize(mm, addr)
91#else
92#define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K
93#endif
94
95/*
96 * 4-level page tables related bits
97 */
98
99#define pgd_none(pgd) (!pgd_val(pgd))
100#define pgd_bad(pgd) (pgd_val(pgd) == 0)
101#define pgd_present(pgd) (pgd_val(pgd) != 0)
102#define pgd_clear(pgdp) (pgd_val(*(pgdp)) = 0)
103#define pgd_page_vaddr(pgd) (pgd_val(pgd) & ~PGD_MASKED_BITS)
104#define pgd_page(pgd) virt_to_page(pgd_page_vaddr(pgd))
105
106#define pud_offset(pgdp, addr) \
107 (((pud_t *) pgd_page_vaddr(*(pgdp))) + \
108 (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)))
109
110#define pud_ERROR(e) \
111 printk("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
112
113#define remap_4k_pfn(vma, addr, pfn, prot) \
114 remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot))
115#endif /* _ASM_POWERPC_PGTABLE_4K_H */
diff --git a/include/asm-powerpc/pgtable-64k.h b/include/asm-powerpc/pgtable-64k.h
deleted file mode 100644
index 7e54adb3559..00000000000
--- a/include/asm-powerpc/pgtable-64k.h
+++ /dev/null
@@ -1,153 +0,0 @@
1#ifndef _ASM_POWERPC_PGTABLE_64K_H
2#define _ASM_POWERPC_PGTABLE_64K_H
3
4#include <asm-generic/pgtable-nopud.h>
5
6
7#define PTE_INDEX_SIZE 12
8#define PMD_INDEX_SIZE 12
9#define PUD_INDEX_SIZE 0
10#define PGD_INDEX_SIZE 4
11
12#ifndef __ASSEMBLY__
13#define PTE_TABLE_SIZE (sizeof(real_pte_t) << PTE_INDEX_SIZE)
14#define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE)
15#define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE)
16
17#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
18#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
19#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
20
21#ifdef CONFIG_PPC_SUBPAGE_PROT
22/*
23 * For the sub-page protection option, we extend the PGD with one of
24 * these. Basically we have a 3-level tree, with the top level being
25 * the protptrs array. To optimize speed and memory consumption when
26 * only addresses < 4GB are being protected, pointers to the first
27 * four pages of sub-page protection words are stored in the low_prot
28 * array.
29 * Each page of sub-page protection words protects 1GB (4 bytes
30 * protects 64k). For the 3-level tree, each page of pointers then
31 * protects 8TB.
32 */
33struct subpage_prot_table {
34 unsigned long maxaddr; /* only addresses < this are protected */
35 unsigned int **protptrs[2];
36 unsigned int *low_prot[4];
37};
38
39#undef PGD_TABLE_SIZE
40#define PGD_TABLE_SIZE ((sizeof(pgd_t) << PGD_INDEX_SIZE) + \
41 sizeof(struct subpage_prot_table))
42
43#define SBP_L1_BITS (PAGE_SHIFT - 2)
44#define SBP_L2_BITS (PAGE_SHIFT - 3)
45#define SBP_L1_COUNT (1 << SBP_L1_BITS)
46#define SBP_L2_COUNT (1 << SBP_L2_BITS)
47#define SBP_L2_SHIFT (PAGE_SHIFT + SBP_L1_BITS)
48#define SBP_L3_SHIFT (SBP_L2_SHIFT + SBP_L2_BITS)
49
50extern void subpage_prot_free(pgd_t *pgd);
51
52static inline struct subpage_prot_table *pgd_subpage_prot(pgd_t *pgd)
53{
54 return (struct subpage_prot_table *)(pgd + PTRS_PER_PGD);
55}
56#endif /* CONFIG_PPC_SUBPAGE_PROT */
57#endif /* __ASSEMBLY__ */
58
59/* With 4k base page size, hugepage PTEs go at the PMD level */
60#define MIN_HUGEPTE_SHIFT PAGE_SHIFT
61
62/* PMD_SHIFT determines what a second-level page table entry can map */
63#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
64#define PMD_SIZE (1UL << PMD_SHIFT)
65#define PMD_MASK (~(PMD_SIZE-1))
66
67/* PGDIR_SHIFT determines what a third-level page table entry can map */
68#define PGDIR_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
69#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
70#define PGDIR_MASK (~(PGDIR_SIZE-1))
71
72/* Additional PTE bits (don't change without checking asm in hash_low.S) */
73#define _PAGE_HPTE_SUB 0x0ffff000 /* combo only: sub pages HPTE bits */
74#define _PAGE_HPTE_SUB0 0x08000000 /* combo only: first sub page */
75#define _PAGE_COMBO 0x10000000 /* this is a combo 4k page */
76#define _PAGE_4K_PFN 0x20000000 /* PFN is for a single 4k page */
77
78/* For 64K page, we don't have a separate _PAGE_HASHPTE bit. Instead,
79 * we set that to be the whole sub-bits mask. The C code will only
80 * test this, so a multi-bit mask will work. For combo pages, this
81 * is equivalent as effectively, the old _PAGE_HASHPTE was an OR of
82 * all the sub bits. For real 64k pages, we now have the assembly set
83 * _PAGE_HPTE_SUB0 in addition to setting the HIDX bits which overlap
84 * that mask. This is fine as long as the HIDX bits are never set on
85 * a PTE that isn't hashed, which is the case today.
86 *
87 * A little nit is for the huge page C code, which does the hashing
88 * in C, we need to provide which bit to use.
89 */
90#define _PAGE_HASHPTE _PAGE_HPTE_SUB
91
92/* Note the full page bits must be in the same location as for normal
93 * 4k pages as the same asssembly will be used to insert 64K pages
94 * wether the kernel has CONFIG_PPC_64K_PAGES or not
95 */
96#define _PAGE_F_SECOND 0x00008000 /* full page: hidx bits */
97#define _PAGE_F_GIX 0x00007000 /* full page: hidx bits */
98
99/* PTE flags to conserve for HPTE identification */
100#define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | _PAGE_COMBO)
101
102/* Shift to put page number into pte.
103 *
104 * That gives us a max RPN of 34 bits, which means a max of 50 bits
105 * of addressable physical space, or 46 bits for the special 4k PFNs.
106 */
107#define PTE_RPN_SHIFT (30)
108#define PTE_RPN_MAX (1UL << (64 - PTE_RPN_SHIFT))
109#define PTE_RPN_MASK (~((1UL<<PTE_RPN_SHIFT)-1))
110
111/* _PAGE_CHG_MASK masks of bits that are to be preserved accross
112 * pgprot changes
113 */
114#define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
115 _PAGE_ACCESSED)
116
117/* Bits to mask out from a PMD to get to the PTE page */
118#define PMD_MASKED_BITS 0x1ff
119/* Bits to mask out from a PGD/PUD to get to the PMD page */
120#define PUD_MASKED_BITS 0x1ff
121
122/* Manipulate "rpte" values */
123#define __real_pte(e,p) ((real_pte_t) { \
124 (e), pte_val(*((p) + PTRS_PER_PTE)) })
125#define __rpte_to_hidx(r,index) ((pte_val((r).pte) & _PAGE_COMBO) ? \
126 (((r).hidx >> ((index)<<2)) & 0xf) : ((pte_val((r).pte) >> 12) & 0xf))
127#define __rpte_to_pte(r) ((r).pte)
128#define __rpte_sub_valid(rpte, index) \
129 (pte_val(rpte.pte) & (_PAGE_HPTE_SUB0 >> (index)))
130
131
132/* Trick: we set __end to va + 64k, which happens works for
133 * a 16M page as well as we want only one iteration
134 */
135#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
136 do { \
137 unsigned long __end = va + PAGE_SIZE; \
138 unsigned __split = (psize == MMU_PAGE_4K || \
139 psize == MMU_PAGE_64K_AP); \
140 shift = mmu_psize_defs[psize].shift; \
141 for (index = 0; va < __end; index++, va += (1L << shift)) { \
142 if (!__split || __rpte_sub_valid(rpte, index)) do { \
143
144#define pte_iterate_hashed_end() } while(0); } } while(0)
145
146#define pte_pagesize_index(mm, addr, pte) \
147 (((pte) & _PAGE_COMBO)? MMU_PAGE_4K: MMU_PAGE_64K)
148
149#define remap_4k_pfn(vma, addr, pfn, prot) \
150 remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, \
151 __pgprot(pgprot_val((prot)) | _PAGE_4K_PFN))
152
153#endif /* _ASM_POWERPC_PGTABLE_64K_H */
diff --git a/include/asm-powerpc/pgtable-ppc32.h b/include/asm-powerpc/pgtable-ppc32.h
deleted file mode 100644
index bdbab72f3eb..00000000000
--- a/include/asm-powerpc/pgtable-ppc32.h
+++ /dev/null
@@ -1,799 +0,0 @@
1#ifndef _ASM_POWERPC_PGTABLE_PPC32_H
2#define _ASM_POWERPC_PGTABLE_PPC32_H
3
4#include <asm-generic/pgtable-nopmd.h>
5
6#ifndef __ASSEMBLY__
7#include <linux/sched.h>
8#include <linux/threads.h>
9#include <asm/io.h> /* For sub-arch specific PPC_PIN_SIZE */
10
11extern unsigned long va_to_phys(unsigned long address);
12extern pte_t *va_to_pte(unsigned long address);
13extern unsigned long ioremap_bot, ioremap_base;
14
15#ifdef CONFIG_44x
16extern int icache_44x_need_flush;
17#endif
18
19#endif /* __ASSEMBLY__ */
20
21/*
22 * The PowerPC MMU uses a hash table containing PTEs, together with
23 * a set of 16 segment registers (on 32-bit implementations), to define
24 * the virtual to physical address mapping.
25 *
26 * We use the hash table as an extended TLB, i.e. a cache of currently
27 * active mappings. We maintain a two-level page table tree, much
28 * like that used by the i386, for the sake of the Linux memory
29 * management code. Low-level assembler code in hashtable.S
30 * (procedure hash_page) is responsible for extracting ptes from the
31 * tree and putting them into the hash table when necessary, and
32 * updating the accessed and modified bits in the page table tree.
33 */
34
35/*
36 * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk.
37 * We also use the two level tables, but we can put the real bits in them
38 * needed for the TLB and tablewalk. These definitions require Mx_CTR.PPM = 0,
39 * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1. The level 2 descriptor has
40 * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit
41 * based upon user/super access. The TLB does not have accessed nor write
42 * protect. We assume that if the TLB get loaded with an entry it is
43 * accessed, and overload the changed bit for write protect. We use
44 * two bits in the software pte that are supposed to be set to zero in
45 * the TLB entry (24 and 25) for these indicators. Although the level 1
46 * descriptor contains the guarded and writethrough/copyback bits, we can
47 * set these at the page level since they get copied from the Mx_TWC
48 * register when the TLB entry is loaded. We will use bit 27 for guard, since
49 * that is where it exists in the MD_TWC, and bit 26 for writethrough.
50 * These will get masked from the level 2 descriptor at TLB load time, and
51 * copied to the MD_TWC before it gets loaded.
52 * Large page sizes added. We currently support two sizes, 4K and 8M.
53 * This also allows a TLB hander optimization because we can directly
54 * load the PMD into MD_TWC. The 8M pages are only used for kernel
55 * mapping of well known areas. The PMD (PGD) entries contain control
56 * flags in addition to the address, so care must be taken that the
57 * software no longer assumes these are only pointers.
58 */
59
60/*
61 * At present, all PowerPC 400-class processors share a similar TLB
62 * architecture. The instruction and data sides share a unified,
63 * 64-entry, fully-associative TLB which is maintained totally under
64 * software control. In addition, the instruction side has a
65 * hardware-managed, 4-entry, fully-associative TLB which serves as a
66 * first level to the shared TLB. These two TLBs are known as the UTLB
67 * and ITLB, respectively (see "mmu.h" for definitions).
68 */
69
70/*
71 * The normal case is that PTEs are 32-bits and we have a 1-page
72 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus
73 *
74 * For any >32-bit physical address platform, we can use the following
75 * two level page table layout where the pgdir is 8KB and the MS 13 bits
76 * are an index to the second level table. The combined pgdir/pmd first
77 * level has 2048 entries and the second level has 512 64-bit PTE entries.
78 * -Matt
79 */
80/* PGDIR_SHIFT determines what a top-level page table entry can map */
81#define PGDIR_SHIFT (PAGE_SHIFT + PTE_SHIFT)
82#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
83#define PGDIR_MASK (~(PGDIR_SIZE-1))
84
85/*
86 * entries per page directory level: our page-table tree is two-level, so
87 * we don't really have any PMD directory.
88 */
89#ifndef __ASSEMBLY__
90#define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_SHIFT)
91#define PGD_TABLE_SIZE (sizeof(pgd_t) << (32 - PGDIR_SHIFT))
92#endif /* __ASSEMBLY__ */
93
94#define PTRS_PER_PTE (1 << PTE_SHIFT)
95#define PTRS_PER_PMD 1
96#define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT))
97
98#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
99#define FIRST_USER_ADDRESS 0
100
101#define pte_ERROR(e) \
102 printk("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
103 (unsigned long long)pte_val(e))
104#define pgd_ERROR(e) \
105 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
106
107/*
108 * Just any arbitrary offset to the start of the vmalloc VM area: the
109 * current 64MB value just means that there will be a 64MB "hole" after the
110 * physical memory until the kernel virtual memory starts. That means that
111 * any out-of-bounds memory accesses will hopefully be caught.
112 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
113 * area for the same reason. ;)
114 *
115 * We no longer map larger than phys RAM with the BATs so we don't have
116 * to worry about the VMALLOC_OFFSET causing problems. We do have to worry
117 * about clashes between our early calls to ioremap() that start growing down
118 * from ioremap_base being run into the VM area allocations (growing upwards
119 * from VMALLOC_START). For this reason we have ioremap_bot to check when
120 * we actually run into our mappings setup in the early boot with the VM
121 * system. This really does become a problem for machines with good amounts
122 * of RAM. -- Cort
123 */
124#define VMALLOC_OFFSET (0x1000000) /* 16M */
125#ifdef PPC_PIN_SIZE
126#define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
127#else
128#define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
129#endif
130#define VMALLOC_END ioremap_bot
131
132/*
133 * Bits in a linux-style PTE. These match the bits in the
134 * (hardware-defined) PowerPC PTE as closely as possible.
135 */
136
137#if defined(CONFIG_40x)
138
139/* There are several potential gotchas here. The 40x hardware TLBLO
140 field looks like this:
141
142 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
143 RPN..................... 0 0 EX WR ZSEL....... W I M G
144
145 Where possible we make the Linux PTE bits match up with this
146
147 - bits 20 and 21 must be cleared, because we use 4k pages (40x can
148 support down to 1k pages), this is done in the TLBMiss exception
149 handler.
150 - We use only zones 0 (for kernel pages) and 1 (for user pages)
151 of the 16 available. Bit 24-26 of the TLB are cleared in the TLB
152 miss handler. Bit 27 is PAGE_USER, thus selecting the correct
153 zone.
154 - PRESENT *must* be in the bottom two bits because swap cache
155 entries use the top 30 bits. Because 40x doesn't support SMP
156 anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30
157 is cleared in the TLB miss handler before the TLB entry is loaded.
158 - All other bits of the PTE are loaded into TLBLO without
159 modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
160 software PTE bits. We actually use use bits 21, 24, 25, and
161 30 respectively for the software bits: ACCESSED, DIRTY, RW, and
162 PRESENT.
163*/
164
165/* Definitions for 40x embedded chips. */
166#define _PAGE_GUARDED 0x001 /* G: page is guarded from prefetch */
167#define _PAGE_FILE 0x001 /* when !present: nonlinear file mapping */
168#define _PAGE_PRESENT 0x002 /* software: PTE contains a translation */
169#define _PAGE_NO_CACHE 0x004 /* I: caching is inhibited */
170#define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */
171#define _PAGE_USER 0x010 /* matches one of the zone permission bits */
172#define _PAGE_RW 0x040 /* software: Writes permitted */
173#define _PAGE_DIRTY 0x080 /* software: dirty page */
174#define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */
175#define _PAGE_HWEXEC 0x200 /* hardware: EX permission */
176#define _PAGE_ACCESSED 0x400 /* software: R: page referenced */
177
178#define _PMD_PRESENT 0x400 /* PMD points to page of PTEs */
179#define _PMD_BAD 0x802
180#define _PMD_SIZE 0x0e0 /* size field, != 0 for large-page PMD entry */
181#define _PMD_SIZE_4M 0x0c0
182#define _PMD_SIZE_16M 0x0e0
183#define PMD_PAGE_SIZE(pmdval) (1024 << (((pmdval) & _PMD_SIZE) >> 4))
184
185/* Until my rework is finished, 40x still needs atomic PTE updates */
186#define PTE_ATOMIC_UPDATES 1
187
188#elif defined(CONFIG_44x)
189/*
190 * Definitions for PPC440
191 *
192 * Because of the 3 word TLB entries to support 36-bit addressing,
193 * the attribute are difficult to map in such a fashion that they
194 * are easily loaded during exception processing. I decided to
195 * organize the entry so the ERPN is the only portion in the
196 * upper word of the PTE and the attribute bits below are packed
197 * in as sensibly as they can be in the area below a 4KB page size
198 * oriented RPN. This at least makes it easy to load the RPN and
199 * ERPN fields in the TLB. -Matt
200 *
201 * Note that these bits preclude future use of a page size
202 * less than 4KB.
203 *
204 *
205 * PPC 440 core has following TLB attribute fields;
206 *
207 * TLB1:
208 * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
209 * RPN................................. - - - - - - ERPN.......
210 *
211 * TLB2:
212 * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
213 * - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR
214 *
215 * Newer 440 cores (440x6 as used on AMCC 460EX/460GT) have additional
216 * TLB2 storage attibute fields. Those are:
217 *
218 * TLB2:
219 * 0...10 11 12 13 14 15 16...31
220 * no change WL1 IL1I IL1D IL2I IL2D no change
221 *
222 * There are some constrains and options, to decide mapping software bits
223 * into TLB entry.
224 *
225 * - PRESENT *must* be in the bottom three bits because swap cache
226 * entries use the top 29 bits for TLB2.
227 *
228 * - FILE *must* be in the bottom three bits because swap cache
229 * entries use the top 29 bits for TLB2.
230 *
231 * - CACHE COHERENT bit (M) has no effect on PPC440 core, because it
232 * doesn't support SMP. So we can use this as software bit, like
233 * DIRTY.
234 *
235 * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used
236 * for memory protection related functions (see PTE structure in
237 * include/asm-ppc/mmu.h). The _PAGE_XXX definitions in this file map to the
238 * above bits. Note that the bit values are CPU specific, not architecture
239 * specific.
240 *
241 * The kernel PTE entry holds an arch-dependent swp_entry structure under
242 * certain situations. In other words, in such situations some portion of
243 * the PTE bits are used as a swp_entry. In the PPC implementation, the
244 * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still
245 * hold protection values. That means the three protection bits are
246 * reserved for both PTE and SWAP entry at the most significant three
247 * LSBs.
248 *
249 * There are three protection bits available for SWAP entry:
250 * _PAGE_PRESENT
251 * _PAGE_FILE
252 * _PAGE_HASHPTE (if HW has)
253 *
254 * So those three bits have to be inside of 0-2nd LSB of PTE.
255 *
256 */
257
258#define _PAGE_PRESENT 0x00000001 /* S: PTE valid */
259#define _PAGE_RW 0x00000002 /* S: Write permission */
260#define _PAGE_FILE 0x00000004 /* S: nonlinear file mapping */
261#define _PAGE_HWEXEC 0x00000004 /* H: Execute permission */
262#define _PAGE_ACCESSED 0x00000008 /* S: Page referenced */
263#define _PAGE_DIRTY 0x00000010 /* S: Page dirty */
264#define _PAGE_USER 0x00000040 /* S: User page */
265#define _PAGE_ENDIAN 0x00000080 /* H: E bit */
266#define _PAGE_GUARDED 0x00000100 /* H: G bit */
267#define _PAGE_COHERENT 0x00000200 /* H: M bit */
268#define _PAGE_NO_CACHE 0x00000400 /* H: I bit */
269#define _PAGE_WRITETHRU 0x00000800 /* H: W bit */
270
271/* TODO: Add large page lowmem mapping support */
272#define _PMD_PRESENT 0
273#define _PMD_PRESENT_MASK (PAGE_MASK)
274#define _PMD_BAD (~PAGE_MASK)
275
276/* ERPN in a PTE never gets cleared, ignore it */
277#define _PTE_NONE_MASK 0xffffffff00000000ULL
278
279
280#elif defined(CONFIG_FSL_BOOKE)
281/*
282 MMU Assist Register 3:
283
284 32 33 34 35 36 ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63
285 RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR
286
287 - PRESENT *must* be in the bottom three bits because swap cache
288 entries use the top 29 bits.
289
290 - FILE *must* be in the bottom three bits because swap cache
291 entries use the top 29 bits.
292*/
293
294/* Definitions for FSL Book-E Cores */
295#define _PAGE_PRESENT 0x00001 /* S: PTE contains a translation */
296#define _PAGE_USER 0x00002 /* S: User page (maps to UR) */
297#define _PAGE_FILE 0x00002 /* S: when !present: nonlinear file mapping */
298#define _PAGE_RW 0x00004 /* S: Write permission (SW) */
299#define _PAGE_DIRTY 0x00008 /* S: Page dirty */
300#define _PAGE_HWEXEC 0x00010 /* H: SX permission */
301#define _PAGE_ACCESSED 0x00020 /* S: Page referenced */
302
303#define _PAGE_ENDIAN 0x00040 /* H: E bit */
304#define _PAGE_GUARDED 0x00080 /* H: G bit */
305#define _PAGE_COHERENT 0x00100 /* H: M bit */
306#define _PAGE_NO_CACHE 0x00200 /* H: I bit */
307#define _PAGE_WRITETHRU 0x00400 /* H: W bit */
308
309#ifdef CONFIG_PTE_64BIT
310/* ERPN in a PTE never gets cleared, ignore it */
311#define _PTE_NONE_MASK 0xffffffffffff0000ULL
312#endif
313
314#define _PMD_PRESENT 0
315#define _PMD_PRESENT_MASK (PAGE_MASK)
316#define _PMD_BAD (~PAGE_MASK)
317
318#elif defined(CONFIG_8xx)
319/* Definitions for 8xx embedded chips. */
320#define _PAGE_PRESENT 0x0001 /* Page is valid */
321#define _PAGE_FILE 0x0002 /* when !present: nonlinear file mapping */
322#define _PAGE_NO_CACHE 0x0002 /* I: cache inhibit */
323#define _PAGE_SHARED 0x0004 /* No ASID (context) compare */
324
325/* These five software bits must be masked out when the entry is loaded
326 * into the TLB.
327 */
328#define _PAGE_EXEC 0x0008 /* software: i-cache coherency required */
329#define _PAGE_GUARDED 0x0010 /* software: guarded access */
330#define _PAGE_DIRTY 0x0020 /* software: page changed */
331#define _PAGE_RW 0x0040 /* software: user write access allowed */
332#define _PAGE_ACCESSED 0x0080 /* software: page referenced */
333
334/* Setting any bits in the nibble with the follow two controls will
335 * require a TLB exception handler change. It is assumed unused bits
336 * are always zero.
337 */
338#define _PAGE_HWWRITE 0x0100 /* h/w write enable: never set in Linux PTE */
339#define _PAGE_USER 0x0800 /* One of the PP bits, the other is USER&~RW */
340
341#define _PMD_PRESENT 0x0001
342#define _PMD_BAD 0x0ff0
343#define _PMD_PAGE_MASK 0x000c
344#define _PMD_PAGE_8M 0x000c
345
346#define _PTE_NONE_MASK _PAGE_ACCESSED
347
348/* Until my rework is finished, 8xx still needs atomic PTE updates */
349#define PTE_ATOMIC_UPDATES 1
350
351#else /* CONFIG_6xx */
352/* Definitions for 60x, 740/750, etc. */
353#define _PAGE_PRESENT 0x001 /* software: pte contains a translation */
354#define _PAGE_HASHPTE 0x002 /* hash_page has made an HPTE for this pte */
355#define _PAGE_FILE 0x004 /* when !present: nonlinear file mapping */
356#define _PAGE_USER 0x004 /* usermode access allowed */
357#define _PAGE_GUARDED 0x008 /* G: prohibit speculative access */
358#define _PAGE_COHERENT 0x010 /* M: enforce memory coherence (SMP systems) */
359#define _PAGE_NO_CACHE 0x020 /* I: cache inhibit */
360#define _PAGE_WRITETHRU 0x040 /* W: cache write-through */
361#define _PAGE_DIRTY 0x080 /* C: page changed */
362#define _PAGE_ACCESSED 0x100 /* R: page referenced */
363#define _PAGE_EXEC 0x200 /* software: i-cache coherency required */
364#define _PAGE_RW 0x400 /* software: user write access allowed */
365
366#define _PTE_NONE_MASK _PAGE_HASHPTE
367
368#define _PMD_PRESENT 0
369#define _PMD_PRESENT_MASK (PAGE_MASK)
370#define _PMD_BAD (~PAGE_MASK)
371
372/* Hash table based platforms need atomic updates of the linux PTE */
373#define PTE_ATOMIC_UPDATES 1
374
375#endif
376
377/*
378 * Some bits are only used on some cpu families...
379 */
380#ifndef _PAGE_HASHPTE
381#define _PAGE_HASHPTE 0
382#endif
383#ifndef _PTE_NONE_MASK
384#define _PTE_NONE_MASK 0
385#endif
386#ifndef _PAGE_SHARED
387#define _PAGE_SHARED 0
388#endif
389#ifndef _PAGE_HWWRITE
390#define _PAGE_HWWRITE 0
391#endif
392#ifndef _PAGE_HWEXEC
393#define _PAGE_HWEXEC 0
394#endif
395#ifndef _PAGE_EXEC
396#define _PAGE_EXEC 0
397#endif
398#ifndef _PAGE_ENDIAN
399#define _PAGE_ENDIAN 0
400#endif
401#ifndef _PAGE_COHERENT
402#define _PAGE_COHERENT 0
403#endif
404#ifndef _PMD_PRESENT_MASK
405#define _PMD_PRESENT_MASK _PMD_PRESENT
406#endif
407#ifndef _PMD_SIZE
408#define _PMD_SIZE 0
409#define PMD_PAGE_SIZE(pmd) bad_call_to_PMD_PAGE_SIZE()
410#endif
411
412#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
413
414
415#define PAGE_PROT_BITS __pgprot(_PAGE_GUARDED | _PAGE_COHERENT | _PAGE_NO_CACHE | \
416 _PAGE_WRITETHRU | _PAGE_ENDIAN | \
417 _PAGE_USER | _PAGE_ACCESSED | \
418 _PAGE_RW | _PAGE_HWWRITE | _PAGE_DIRTY | \
419 _PAGE_EXEC | _PAGE_HWEXEC)
420/*
421 * Note: the _PAGE_COHERENT bit automatically gets set in the hardware
422 * PTE if CONFIG_SMP is defined (hash_page does this); there is no need
423 * to have it in the Linux PTE, and in fact the bit could be reused for
424 * another purpose. -- paulus.
425 */
426
427#ifdef CONFIG_44x
428#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_GUARDED)
429#else
430#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED)
431#endif
432#define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE)
433#define _PAGE_KERNEL (_PAGE_BASE | _PAGE_SHARED | _PAGE_WRENABLE)
434
435#ifdef CONFIG_PPC_STD_MMU
436/* On standard PPC MMU, no user access implies kernel read/write access,
437 * so to write-protect kernel memory we must turn on user access */
438#define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED | _PAGE_USER)
439#else
440#define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED)
441#endif
442
443#define _PAGE_IO (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED)
444#define _PAGE_RAM (_PAGE_KERNEL | _PAGE_HWEXEC)
445
446#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) ||\
447 defined(CONFIG_KPROBES)
448/* We want the debuggers to be able to set breakpoints anywhere, so
449 * don't write protect the kernel text */
450#define _PAGE_RAM_TEXT _PAGE_RAM
451#else
452#define _PAGE_RAM_TEXT (_PAGE_KERNEL_RO | _PAGE_HWEXEC)
453#endif
454
455#define PAGE_NONE __pgprot(_PAGE_BASE)
456#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
457#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
458#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
459#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
460#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER)
461#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
462
463#define PAGE_KERNEL __pgprot(_PAGE_RAM)
464#define PAGE_KERNEL_NOCACHE __pgprot(_PAGE_IO)
465
466/*
467 * The PowerPC can only do execute protection on a segment (256MB) basis,
468 * not on a page basis. So we consider execute permission the same as read.
469 * Also, write permissions imply read permissions.
470 * This is the closest we can get..
471 */
472#define __P000 PAGE_NONE
473#define __P001 PAGE_READONLY_X
474#define __P010 PAGE_COPY
475#define __P011 PAGE_COPY_X
476#define __P100 PAGE_READONLY
477#define __P101 PAGE_READONLY_X
478#define __P110 PAGE_COPY
479#define __P111 PAGE_COPY_X
480
481#define __S000 PAGE_NONE
482#define __S001 PAGE_READONLY_X
483#define __S010 PAGE_SHARED
484#define __S011 PAGE_SHARED_X
485#define __S100 PAGE_READONLY
486#define __S101 PAGE_READONLY_X
487#define __S110 PAGE_SHARED
488#define __S111 PAGE_SHARED_X
489
490#ifndef __ASSEMBLY__
491/* Make sure we get a link error if PMD_PAGE_SIZE is ever called on a
492 * kernel without large page PMD support */
493extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
494
495/*
496 * Conversions between PTE values and page frame numbers.
497 */
498
499/* in some case we want to additionaly adjust where the pfn is in the pte to
500 * allow room for more flags */
501#if defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT)
502#define PFN_SHIFT_OFFSET (PAGE_SHIFT + 8)
503#else
504#define PFN_SHIFT_OFFSET (PAGE_SHIFT)
505#endif
506
507#define pte_pfn(x) (pte_val(x) >> PFN_SHIFT_OFFSET)
508#define pte_page(x) pfn_to_page(pte_pfn(x))
509
510#define pfn_pte(pfn, prot) __pte(((pte_basic_t)(pfn) << PFN_SHIFT_OFFSET) |\
511 pgprot_val(prot))
512#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
513#endif /* __ASSEMBLY__ */
514
515#define pte_none(pte) ((pte_val(pte) & ~_PTE_NONE_MASK) == 0)
516#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
517#define pte_clear(mm,addr,ptep) do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0)
518
519#define pmd_none(pmd) (!pmd_val(pmd))
520#define pmd_bad(pmd) (pmd_val(pmd) & _PMD_BAD)
521#define pmd_present(pmd) (pmd_val(pmd) & _PMD_PRESENT_MASK)
522#define pmd_clear(pmdp) do { pmd_val(*(pmdp)) = 0; } while (0)
523
524#ifndef __ASSEMBLY__
525/*
526 * The following only work if pte_present() is true.
527 * Undefined behaviour if not..
528 */
529static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; }
530static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
531static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
532static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; }
533static inline int pte_special(pte_t pte) { return 0; }
534
535static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; }
536static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; }
537
538static inline pte_t pte_wrprotect(pte_t pte) {
539 pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; }
540static inline pte_t pte_mkclean(pte_t pte) {
541 pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; }
542static inline pte_t pte_mkold(pte_t pte) {
543 pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
544
545static inline pte_t pte_mkwrite(pte_t pte) {
546 pte_val(pte) |= _PAGE_RW; return pte; }
547static inline pte_t pte_mkdirty(pte_t pte) {
548 pte_val(pte) |= _PAGE_DIRTY; return pte; }
549static inline pte_t pte_mkyoung(pte_t pte) {
550 pte_val(pte) |= _PAGE_ACCESSED; return pte; }
551static inline pte_t pte_mkspecial(pte_t pte) {
552 return pte; }
553static inline unsigned long pte_pgprot(pte_t pte)
554{
555 return __pgprot(pte_val(pte)) & PAGE_PROT_BITS;
556}
557
558static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
559{
560 pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
561 return pte;
562}
563
564/*
565 * When flushing the tlb entry for a page, we also need to flush the hash
566 * table entry. flush_hash_pages is assembler (for speed) in hashtable.S.
567 */
568extern int flush_hash_pages(unsigned context, unsigned long va,
569 unsigned long pmdval, int count);
570
571/* Add an HPTE to the hash table */
572extern void add_hash_page(unsigned context, unsigned long va,
573 unsigned long pmdval);
574
575/*
576 * Atomic PTE updates.
577 *
578 * pte_update clears and sets bit atomically, and returns
579 * the old pte value. In the 64-bit PTE case we lock around the
580 * low PTE word since we expect ALL flag bits to be there
581 */
582#ifndef CONFIG_PTE_64BIT
583static inline unsigned long pte_update(pte_t *p,
584 unsigned long clr,
585 unsigned long set)
586{
587#ifdef PTE_ATOMIC_UPDATES
588 unsigned long old, tmp;
589
590 __asm__ __volatile__("\
5911: lwarx %0,0,%3\n\
592 andc %1,%0,%4\n\
593 or %1,%1,%5\n"
594 PPC405_ERR77(0,%3)
595" stwcx. %1,0,%3\n\
596 bne- 1b"
597 : "=&r" (old), "=&r" (tmp), "=m" (*p)
598 : "r" (p), "r" (clr), "r" (set), "m" (*p)
599 : "cc" );
600#else /* PTE_ATOMIC_UPDATES */
601 unsigned long old = pte_val(*p);
602 *p = __pte((old & ~clr) | set);
603#endif /* !PTE_ATOMIC_UPDATES */
604
605#ifdef CONFIG_44x
606 if ((old & _PAGE_USER) && (old & _PAGE_HWEXEC))
607 icache_44x_need_flush = 1;
608#endif
609 return old;
610}
611#else /* CONFIG_PTE_64BIT */
612/* TODO: Change that to only modify the low word and move set_pte_at()
613 * out of line
614 */
615static inline unsigned long long pte_update(pte_t *p,
616 unsigned long clr,
617 unsigned long set)
618{
619#ifdef PTE_ATOMIC_UPDATES
620 unsigned long long old;
621 unsigned long tmp;
622
623 __asm__ __volatile__("\
6241: lwarx %L0,0,%4\n\
625 lwzx %0,0,%3\n\
626 andc %1,%L0,%5\n\
627 or %1,%1,%6\n"
628 PPC405_ERR77(0,%3)
629" stwcx. %1,0,%4\n\
630 bne- 1b"
631 : "=&r" (old), "=&r" (tmp), "=m" (*p)
632 : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
633 : "cc" );
634#else /* PTE_ATOMIC_UPDATES */
635 unsigned long long old = pte_val(*p);
636 *p = __pte((old & ~(unsigned long long)clr) | set);
637#endif /* !PTE_ATOMIC_UPDATES */
638
639#ifdef CONFIG_44x
640 if ((old & _PAGE_USER) && (old & _PAGE_HWEXEC))
641 icache_44x_need_flush = 1;
642#endif
643 return old;
644}
645#endif /* CONFIG_PTE_64BIT */
646
647/*
648 * set_pte stores a linux PTE into the linux page table.
649 * On machines which use an MMU hash table we avoid changing the
650 * _PAGE_HASHPTE bit.
651 */
652static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
653 pte_t *ptep, pte_t pte)
654{
655#if _PAGE_HASHPTE != 0
656 pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) & ~_PAGE_HASHPTE);
657#else
658 *ptep = pte;
659#endif
660}
661
662/*
663 * 2.6 calls this without flushing the TLB entry; this is wrong
664 * for our hash-based implementation, we fix that up here.
665 */
666#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
667static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep)
668{
669 unsigned long old;
670 old = pte_update(ptep, _PAGE_ACCESSED, 0);
671#if _PAGE_HASHPTE != 0
672 if (old & _PAGE_HASHPTE) {
673 unsigned long ptephys = __pa(ptep) & PAGE_MASK;
674 flush_hash_pages(context, addr, ptephys, 1);
675 }
676#endif
677 return (old & _PAGE_ACCESSED) != 0;
678}
679#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
680 __ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep)
681
682#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
683static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
684 pte_t *ptep)
685{
686 return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
687}
688
689#define __HAVE_ARCH_PTEP_SET_WRPROTECT
690static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
691 pte_t *ptep)
692{
693 pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0);
694}
695static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
696 unsigned long addr, pte_t *ptep)
697{
698 ptep_set_wrprotect(mm, addr, ptep);
699}
700
701
702#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
703static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
704{
705 unsigned long bits = pte_val(entry) &
706 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW);
707 pte_update(ptep, 0, bits);
708}
709
710#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
711({ \
712 int __changed = !pte_same(*(__ptep), __entry); \
713 if (__changed) { \
714 __ptep_set_access_flags(__ptep, __entry, __dirty); \
715 flush_tlb_page_nohash(__vma, __address); \
716 } \
717 __changed; \
718})
719
720/*
721 * Macro to mark a page protection value as "uncacheable".
722 */
723#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
724
725struct file;
726extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
727 unsigned long size, pgprot_t vma_prot);
728#define __HAVE_PHYS_MEM_ACCESS_PROT
729
730#define __HAVE_ARCH_PTE_SAME
731#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
732
733/*
734 * Note that on Book E processors, the pmd contains the kernel virtual
735 * (lowmem) address of the pte page. The physical address is less useful
736 * because everything runs with translation enabled (even the TLB miss
737 * handler). On everything else the pmd contains the physical address
738 * of the pte page. -- paulus
739 */
740#ifndef CONFIG_BOOKE
741#define pmd_page_vaddr(pmd) \
742 ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
743#define pmd_page(pmd) \
744 (mem_map + (pmd_val(pmd) >> PAGE_SHIFT))
745#else
746#define pmd_page_vaddr(pmd) \
747 ((unsigned long) (pmd_val(pmd) & PAGE_MASK))
748#define pmd_page(pmd) \
749 pfn_to_page((__pa(pmd_val(pmd)) >> PAGE_SHIFT))
750#endif
751
752/* to find an entry in a kernel page-table-directory */
753#define pgd_offset_k(address) pgd_offset(&init_mm, address)
754
755/* to find an entry in a page-table-directory */
756#define pgd_index(address) ((address) >> PGDIR_SHIFT)
757#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
758
759/* Find an entry in the third-level page table.. */
760#define pte_index(address) \
761 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
762#define pte_offset_kernel(dir, addr) \
763 ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr))
764#define pte_offset_map(dir, addr) \
765 ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE0) + pte_index(addr))
766#define pte_offset_map_nested(dir, addr) \
767 ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE1) + pte_index(addr))
768
769#define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0)
770#define pte_unmap_nested(pte) kunmap_atomic(pte, KM_PTE1)
771
772/*
773 * Encode and decode a swap entry.
774 * Note that the bits we use in a PTE for representing a swap entry
775 * must not include the _PAGE_PRESENT bit, the _PAGE_FILE bit, or the
776 *_PAGE_HASHPTE bit (if used). -- paulus
777 */
778#define __swp_type(entry) ((entry).val & 0x1f)
779#define __swp_offset(entry) ((entry).val >> 5)
780#define __swp_entry(type, offset) ((swp_entry_t) { (type) | ((offset) << 5) })
781#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 3 })
782#define __swp_entry_to_pte(x) ((pte_t) { (x).val << 3 })
783
784/* Encode and decode a nonlinear file mapping entry */
785#define PTE_FILE_MAX_BITS 29
786#define pte_to_pgoff(pte) (pte_val(pte) >> 3)
787#define pgoff_to_pte(off) ((pte_t) { ((off) << 3) | _PAGE_FILE })
788
789/*
790 * No page table caches to initialise
791 */
792#define pgtable_cache_init() do { } while (0)
793
794extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep,
795 pmd_t **pmdp);
796
797#endif /* !__ASSEMBLY__ */
798
799#endif /* _ASM_POWERPC_PGTABLE_PPC32_H */
diff --git a/include/asm-powerpc/pgtable-ppc64.h b/include/asm-powerpc/pgtable-ppc64.h
deleted file mode 100644
index ba8000352b9..00000000000
--- a/include/asm-powerpc/pgtable-ppc64.h
+++ /dev/null
@@ -1,466 +0,0 @@
1#ifndef _ASM_POWERPC_PGTABLE_PPC64_H_
2#define _ASM_POWERPC_PGTABLE_PPC64_H_
3/*
4 * This file contains the functions and defines necessary to modify and use
5 * the ppc64 hashed page table.
6 */
7
8#ifndef __ASSEMBLY__
9#include <linux/stddef.h>
10#include <asm/tlbflush.h>
11#endif /* __ASSEMBLY__ */
12
13#ifdef CONFIG_PPC_64K_PAGES
14#include <asm/pgtable-64k.h>
15#else
16#include <asm/pgtable-4k.h>
17#endif
18
19#define FIRST_USER_ADDRESS 0
20
21/*
22 * Size of EA range mapped by our pagetables.
23 */
24#define PGTABLE_EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \
25 PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT)
26#define PGTABLE_RANGE (ASM_CONST(1) << PGTABLE_EADDR_SIZE)
27
28#if TASK_SIZE_USER64 > PGTABLE_RANGE
29#error TASK_SIZE_USER64 exceeds pagetable range
30#endif
31
32#if TASK_SIZE_USER64 > (1UL << (USER_ESID_BITS + SID_SHIFT))
33#error TASK_SIZE_USER64 exceeds user VSID range
34#endif
35
36
37/*
38 * Define the address range of the vmalloc VM area.
39 */
40#define VMALLOC_START ASM_CONST(0xD000000000000000)
41#define VMALLOC_SIZE (PGTABLE_RANGE >> 1)
42#define VMALLOC_END (VMALLOC_START + VMALLOC_SIZE)
43
44/*
45 * Define the address ranges for MMIO and IO space :
46 *
47 * ISA_IO_BASE = VMALLOC_END, 64K reserved area
48 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
49 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
50 */
51#define FULL_IO_SIZE 0x80000000ul
52#define ISA_IO_BASE (VMALLOC_END)
53#define ISA_IO_END (VMALLOC_END + 0x10000ul)
54#define PHB_IO_BASE (ISA_IO_END)
55#define PHB_IO_END (VMALLOC_END + FULL_IO_SIZE)
56#define IOREMAP_BASE (PHB_IO_END)
57#define IOREMAP_END (VMALLOC_START + PGTABLE_RANGE)
58
59/*
60 * Region IDs
61 */
62#define REGION_SHIFT 60UL
63#define REGION_MASK (0xfUL << REGION_SHIFT)
64#define REGION_ID(ea) (((unsigned long)(ea)) >> REGION_SHIFT)
65
66#define VMALLOC_REGION_ID (REGION_ID(VMALLOC_START))
67#define KERNEL_REGION_ID (REGION_ID(PAGE_OFFSET))
68#define VMEMMAP_REGION_ID (0xfUL)
69#define USER_REGION_ID (0UL)
70
71/*
72 * Defines the address of the vmemap area, in its own region
73 */
74#define VMEMMAP_BASE (VMEMMAP_REGION_ID << REGION_SHIFT)
75#define vmemmap ((struct page *)VMEMMAP_BASE)
76
77
78/*
79 * Common bits in a linux-style PTE. These match the bits in the
80 * (hardware-defined) PowerPC PTE as closely as possible. Additional
81 * bits may be defined in pgtable-*.h
82 */
83#define _PAGE_PRESENT 0x0001 /* software: pte contains a translation */
84#define _PAGE_USER 0x0002 /* matches one of the PP bits */
85#define _PAGE_FILE 0x0002 /* (!present only) software: pte holds file offset */
86#define _PAGE_EXEC 0x0004 /* No execute on POWER4 and newer (we invert) */
87#define _PAGE_GUARDED 0x0008
88#define _PAGE_COHERENT 0x0010 /* M: enforce memory coherence (SMP systems) */
89#define _PAGE_NO_CACHE 0x0020 /* I: cache inhibit */
90#define _PAGE_WRITETHRU 0x0040 /* W: cache write-through */
91#define _PAGE_DIRTY 0x0080 /* C: page changed */
92#define _PAGE_ACCESSED 0x0100 /* R: page referenced */
93#define _PAGE_RW 0x0200 /* software: user write access allowed */
94#define _PAGE_BUSY 0x0800 /* software: PTE & hash are busy */
95
96/* Strong Access Ordering */
97#define _PAGE_SAO (_PAGE_WRITETHRU | _PAGE_NO_CACHE | _PAGE_COHERENT)
98
99#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_COHERENT)
100
101#define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY)
102
103/* __pgprot defined in asm-powerpc/page.h */
104#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
105
106#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER)
107#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER | _PAGE_EXEC)
108#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER)
109#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
110#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
111#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
112#define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_WRENABLE)
113#define PAGE_KERNEL_CI __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
114 _PAGE_WRENABLE | _PAGE_NO_CACHE | _PAGE_GUARDED)
115#define PAGE_KERNEL_EXEC __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_EXEC)
116
117#define PAGE_AGP __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_NO_CACHE)
118#define HAVE_PAGE_AGP
119
120#define PAGE_PROT_BITS __pgprot(_PAGE_GUARDED | _PAGE_COHERENT | \
121 _PAGE_NO_CACHE | _PAGE_WRITETHRU | \
122 _PAGE_4K_PFN | _PAGE_RW | _PAGE_USER | \
123 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_EXEC)
124/* PTEIDX nibble */
125#define _PTEIDX_SECONDARY 0x8
126#define _PTEIDX_GROUP_IX 0x7
127
128
129/*
130 * POWER4 and newer have per page execute protection, older chips can only
131 * do this on a segment (256MB) basis.
132 *
133 * Also, write permissions imply read permissions.
134 * This is the closest we can get..
135 *
136 * Note due to the way vm flags are laid out, the bits are XWR
137 */
138#define __P000 PAGE_NONE
139#define __P001 PAGE_READONLY
140#define __P010 PAGE_COPY
141#define __P011 PAGE_COPY
142#define __P100 PAGE_READONLY_X
143#define __P101 PAGE_READONLY_X
144#define __P110 PAGE_COPY_X
145#define __P111 PAGE_COPY_X
146
147#define __S000 PAGE_NONE
148#define __S001 PAGE_READONLY
149#define __S010 PAGE_SHARED
150#define __S011 PAGE_SHARED
151#define __S100 PAGE_READONLY_X
152#define __S101 PAGE_READONLY_X
153#define __S110 PAGE_SHARED_X
154#define __S111 PAGE_SHARED_X
155
156#ifdef CONFIG_HUGETLB_PAGE
157
158#define HAVE_ARCH_UNMAPPED_AREA
159#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
160
161#endif
162
163#ifndef __ASSEMBLY__
164
165/*
166 * Conversion functions: convert a page and protection to a page entry,
167 * and a page entry and page directory to the page they refer to.
168 *
169 * mk_pte takes a (struct page *) as input
170 */
171#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
172
173static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
174{
175 pte_t pte;
176
177
178 pte_val(pte) = (pfn << PTE_RPN_SHIFT) | pgprot_val(pgprot);
179 return pte;
180}
181
182#define pte_modify(_pte, newprot) \
183 (__pte((pte_val(_pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)))
184
185#define pte_none(pte) ((pte_val(pte) & ~_PAGE_HPTEFLAGS) == 0)
186#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
187
188/* pte_clear moved to later in this file */
189
190#define pte_pfn(x) ((unsigned long)((pte_val(x)>>PTE_RPN_SHIFT)))
191#define pte_page(x) pfn_to_page(pte_pfn(x))
192
193#define PMD_BAD_BITS (PTE_TABLE_SIZE-1)
194#define PUD_BAD_BITS (PMD_TABLE_SIZE-1)
195
196#define pmd_set(pmdp, pmdval) (pmd_val(*(pmdp)) = (pmdval))
197#define pmd_none(pmd) (!pmd_val(pmd))
198#define pmd_bad(pmd) (!is_kernel_addr(pmd_val(pmd)) \
199 || (pmd_val(pmd) & PMD_BAD_BITS))
200#define pmd_present(pmd) (pmd_val(pmd) != 0)
201#define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0)
202#define pmd_page_vaddr(pmd) (pmd_val(pmd) & ~PMD_MASKED_BITS)
203#define pmd_page(pmd) virt_to_page(pmd_page_vaddr(pmd))
204
205#define pud_set(pudp, pudval) (pud_val(*(pudp)) = (pudval))
206#define pud_none(pud) (!pud_val(pud))
207#define pud_bad(pud) (!is_kernel_addr(pud_val(pud)) \
208 || (pud_val(pud) & PUD_BAD_BITS))
209#define pud_present(pud) (pud_val(pud) != 0)
210#define pud_clear(pudp) (pud_val(*(pudp)) = 0)
211#define pud_page_vaddr(pud) (pud_val(pud) & ~PUD_MASKED_BITS)
212#define pud_page(pud) virt_to_page(pud_page_vaddr(pud))
213
214#define pgd_set(pgdp, pudp) ({pgd_val(*(pgdp)) = (unsigned long)(pudp);})
215
216/*
217 * Find an entry in a page-table-directory. We combine the address region
218 * (the high order N bits) and the pgd portion of the address.
219 */
220/* to avoid overflow in free_pgtables we don't use PTRS_PER_PGD here */
221#define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & 0x1ff)
222
223#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
224
225#define pmd_offset(pudp,addr) \
226 (((pmd_t *) pud_page_vaddr(*(pudp))) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
227
228#define pte_offset_kernel(dir,addr) \
229 (((pte_t *) pmd_page_vaddr(*(dir))) + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
230
231#define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
232#define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr))
233#define pte_unmap(pte) do { } while(0)
234#define pte_unmap_nested(pte) do { } while(0)
235
236/* to find an entry in a kernel page-table-directory */
237/* This now only contains the vmalloc pages */
238#define pgd_offset_k(address) pgd_offset(&init_mm, address)
239
240/*
241 * The following only work if pte_present() is true.
242 * Undefined behaviour if not..
243 */
244static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW;}
245static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY;}
246static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED;}
247static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE;}
248static inline int pte_special(pte_t pte) { return 0; }
249
250static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; }
251static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; }
252
253static inline pte_t pte_wrprotect(pte_t pte) {
254 pte_val(pte) &= ~(_PAGE_RW); return pte; }
255static inline pte_t pte_mkclean(pte_t pte) {
256 pte_val(pte) &= ~(_PAGE_DIRTY); return pte; }
257static inline pte_t pte_mkold(pte_t pte) {
258 pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
259static inline pte_t pte_mkwrite(pte_t pte) {
260 pte_val(pte) |= _PAGE_RW; return pte; }
261static inline pte_t pte_mkdirty(pte_t pte) {
262 pte_val(pte) |= _PAGE_DIRTY; return pte; }
263static inline pte_t pte_mkyoung(pte_t pte) {
264 pte_val(pte) |= _PAGE_ACCESSED; return pte; }
265static inline pte_t pte_mkhuge(pte_t pte) {
266 return pte; }
267static inline pte_t pte_mkspecial(pte_t pte) {
268 return pte; }
269static inline unsigned long pte_pgprot(pte_t pte)
270{
271 return __pgprot(pte_val(pte)) & PAGE_PROT_BITS;
272}
273
274/* Atomic PTE updates */
275static inline unsigned long pte_update(struct mm_struct *mm,
276 unsigned long addr,
277 pte_t *ptep, unsigned long clr,
278 int huge)
279{
280 unsigned long old, tmp;
281
282 __asm__ __volatile__(
283 "1: ldarx %0,0,%3 # pte_update\n\
284 andi. %1,%0,%6\n\
285 bne- 1b \n\
286 andc %1,%0,%4 \n\
287 stdcx. %1,0,%3 \n\
288 bne- 1b"
289 : "=&r" (old), "=&r" (tmp), "=m" (*ptep)
290 : "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY)
291 : "cc" );
292
293 if (old & _PAGE_HASHPTE)
294 hpte_need_flush(mm, addr, ptep, old, huge);
295 return old;
296}
297
298static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
299 unsigned long addr, pte_t *ptep)
300{
301 unsigned long old;
302
303 if ((pte_val(*ptep) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0)
304 return 0;
305 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0);
306 return (old & _PAGE_ACCESSED) != 0;
307}
308#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
309#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
310({ \
311 int __r; \
312 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
313 __r; \
314})
315
316#define __HAVE_ARCH_PTEP_SET_WRPROTECT
317static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
318 pte_t *ptep)
319{
320 unsigned long old;
321
322 if ((pte_val(*ptep) & _PAGE_RW) == 0)
323 return;
324 old = pte_update(mm, addr, ptep, _PAGE_RW, 0);
325}
326
327static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
328 unsigned long addr, pte_t *ptep)
329{
330 unsigned long old;
331
332 if ((pte_val(*ptep) & _PAGE_RW) == 0)
333 return;
334 old = pte_update(mm, addr, ptep, _PAGE_RW, 1);
335}
336
337/*
338 * We currently remove entries from the hashtable regardless of whether
339 * the entry was young or dirty. The generic routines only flush if the
340 * entry was young or dirty which is not good enough.
341 *
342 * We should be more intelligent about this but for the moment we override
343 * these functions and force a tlb flush unconditionally
344 */
345#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
346#define ptep_clear_flush_young(__vma, __address, __ptep) \
347({ \
348 int __young = __ptep_test_and_clear_young((__vma)->vm_mm, __address, \
349 __ptep); \
350 __young; \
351})
352
353#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
354static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
355 unsigned long addr, pte_t *ptep)
356{
357 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0);
358 return __pte(old);
359}
360
361static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
362 pte_t * ptep)
363{
364 pte_update(mm, addr, ptep, ~0UL, 0);
365}
366
367/*
368 * set_pte stores a linux PTE into the linux page table.
369 */
370static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
371 pte_t *ptep, pte_t pte)
372{
373 if (pte_present(*ptep))
374 pte_clear(mm, addr, ptep);
375 pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
376 *ptep = pte;
377}
378
379/* Set the dirty and/or accessed bits atomically in a linux PTE, this
380 * function doesn't need to flush the hash entry
381 */
382#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
383static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
384{
385 unsigned long bits = pte_val(entry) &
386 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
387 unsigned long old, tmp;
388
389 __asm__ __volatile__(
390 "1: ldarx %0,0,%4\n\
391 andi. %1,%0,%6\n\
392 bne- 1b \n\
393 or %0,%3,%0\n\
394 stdcx. %0,0,%4\n\
395 bne- 1b"
396 :"=&r" (old), "=&r" (tmp), "=m" (*ptep)
397 :"r" (bits), "r" (ptep), "m" (*ptep), "i" (_PAGE_BUSY)
398 :"cc");
399}
400#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
401({ \
402 int __changed = !pte_same(*(__ptep), __entry); \
403 if (__changed) { \
404 __ptep_set_access_flags(__ptep, __entry, __dirty); \
405 flush_tlb_page_nohash(__vma, __address); \
406 } \
407 __changed; \
408})
409
410/*
411 * Macro to mark a page protection value as "uncacheable".
412 */
413#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
414
415struct file;
416extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
417 unsigned long size, pgprot_t vma_prot);
418#define __HAVE_PHYS_MEM_ACCESS_PROT
419
420#define __HAVE_ARCH_PTE_SAME
421#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0)
422
423#define pte_ERROR(e) \
424 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
425#define pmd_ERROR(e) \
426 printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
427#define pgd_ERROR(e) \
428 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
429
430/* Encode and de-code a swap entry */
431#define __swp_type(entry) (((entry).val >> 1) & 0x3f)
432#define __swp_offset(entry) ((entry).val >> 8)
433#define __swp_entry(type, offset) ((swp_entry_t){((type)<< 1)|((offset)<<8)})
434#define __pte_to_swp_entry(pte) ((swp_entry_t){pte_val(pte) >> PTE_RPN_SHIFT})
435#define __swp_entry_to_pte(x) ((pte_t) { (x).val << PTE_RPN_SHIFT })
436#define pte_to_pgoff(pte) (pte_val(pte) >> PTE_RPN_SHIFT)
437#define pgoff_to_pte(off) ((pte_t) {((off) << PTE_RPN_SHIFT)|_PAGE_FILE})
438#define PTE_FILE_MAX_BITS (BITS_PER_LONG - PTE_RPN_SHIFT)
439
440void pgtable_cache_init(void);
441
442/*
443 * find_linux_pte returns the address of a linux pte for a given
444 * effective address and directory. If not found, it returns zero.
445 */static inline pte_t *find_linux_pte(pgd_t *pgdir, unsigned long ea)
446{
447 pgd_t *pg;
448 pud_t *pu;
449 pmd_t *pm;
450 pte_t *pt = NULL;
451
452 pg = pgdir + pgd_index(ea);
453 if (!pgd_none(*pg)) {
454 pu = pud_offset(pg, ea);
455 if (!pud_none(*pu)) {
456 pm = pmd_offset(pu, ea);
457 if (pmd_present(*pm))
458 pt = pte_offset_kernel(pm, ea);
459 }
460 }
461 return pt;
462}
463
464#endif /* __ASSEMBLY__ */
465
466#endif /* _ASM_POWERPC_PGTABLE_PPC64_H_ */
diff --git a/include/asm-powerpc/pgtable.h b/include/asm-powerpc/pgtable.h
deleted file mode 100644
index dbb8ca172e4..00000000000
--- a/include/asm-powerpc/pgtable.h
+++ /dev/null
@@ -1,57 +0,0 @@
1#ifndef _ASM_POWERPC_PGTABLE_H
2#define _ASM_POWERPC_PGTABLE_H
3#ifdef __KERNEL__
4
5#ifndef __ASSEMBLY__
6#include <asm/processor.h> /* For TASK_SIZE */
7#include <asm/mmu.h>
8#include <asm/page.h>
9struct mm_struct;
10#endif /* !__ASSEMBLY__ */
11
12#if defined(CONFIG_PPC64)
13# include <asm/pgtable-ppc64.h>
14#else
15# include <asm/pgtable-ppc32.h>
16#endif
17
18#ifndef __ASSEMBLY__
19/*
20 * ZERO_PAGE is a global shared page that is always zero: used
21 * for zero-mapped memory areas etc..
22 */
23extern unsigned long empty_zero_page[];
24#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
25
26extern pgd_t swapper_pg_dir[];
27
28extern void paging_init(void);
29
30/*
31 * kern_addr_valid is intended to indicate whether an address is a valid
32 * kernel address. Most 32-bit archs define it as always true (like this)
33 * but most 64-bit archs actually perform a test. What should we do here?
34 */
35#define kern_addr_valid(addr) (1)
36
37#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
38 remap_pfn_range(vma, vaddr, pfn, size, prot)
39
40#include <asm-generic/pgtable.h>
41
42
43/*
44 * This gets called at the end of handling a page fault, when
45 * the kernel has put a new PTE into the page table for the process.
46 * We use it to ensure coherency between the i-cache and d-cache
47 * for the page which has just been mapped in.
48 * On machines which use an MMU hash table, we use this to put a
49 * corresponding HPTE into the hash table ahead of time, instead of
50 * waiting for the inevitable extra hash-table miss exception.
51 */
52extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
53
54#endif /* __ASSEMBLY__ */
55
56#endif /* __KERNEL__ */
57#endif /* _ASM_POWERPC_PGTABLE_H */
diff --git a/include/asm-powerpc/phyp_dump.h b/include/asm-powerpc/phyp_dump.h
deleted file mode 100644
index fa74c6c3e10..00000000000
--- a/include/asm-powerpc/phyp_dump.h
+++ /dev/null
@@ -1,47 +0,0 @@
1/*
2 * Hypervisor-assisted dump
3 *
4 * Linas Vepstas, Manish Ahuja 2008
5 * Copyright 2008 IBM Corp.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#ifndef _PPC64_PHYP_DUMP_H
14#define _PPC64_PHYP_DUMP_H
15
16#ifdef CONFIG_PHYP_DUMP
17
18/* The RMR region will be saved for later dumping
19 * whenever the kernel crashes. Set this to 256MB. */
20#define PHYP_DUMP_RMR_START 0x0
21#define PHYP_DUMP_RMR_END (1UL<<28)
22
23struct phyp_dump {
24 /* Memory that is reserved during very early boot. */
25 unsigned long init_reserve_start;
26 unsigned long init_reserve_size;
27 /* cmd line options during boot */
28 unsigned long reserve_bootvar;
29 unsigned long phyp_dump_at_boot;
30 /* Check status during boot if dump supported, active & present*/
31 unsigned long phyp_dump_configured;
32 unsigned long phyp_dump_is_active;
33 /* store cpu & hpte size */
34 unsigned long cpu_state_size;
35 unsigned long hpte_region_size;
36 /* previous scratch area values */
37 unsigned long reserved_scratch_addr;
38 unsigned long reserved_scratch_size;
39};
40
41extern struct phyp_dump *phyp_dump_info;
42
43int early_init_dt_scan_phyp_dump(unsigned long node,
44 const char *uname, int depth, void *data);
45
46#endif /* CONFIG_PHYP_DUMP */
47#endif /* _PPC64_PHYP_DUMP_H */
diff --git a/include/asm-powerpc/pmac_feature.h b/include/asm-powerpc/pmac_feature.h
deleted file mode 100644
index 877c35a4356..00000000000
--- a/include/asm-powerpc/pmac_feature.h
+++ /dev/null
@@ -1,405 +0,0 @@
1/*
2 * Definition of platform feature hooks for PowerMacs
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1998 Paul Mackerras &
9 * Ben. Herrenschmidt.
10 *
11 *
12 * Note: I removed media-bay details from the feature stuff, I believe it's
13 * not worth it, the media-bay driver can directly use the mac-io
14 * ASIC registers.
15 *
16 * Implementation note: Currently, none of these functions will block.
17 * However, they may internally protect themselves with a spinlock
18 * for way too long. Be prepared for at least some of these to block
19 * in the future.
20 *
21 * Unless specifically defined, the result code is assumed to be an
22 * error when negative, 0 is the default success result. Some functions
23 * may return additional positive result values.
24 *
25 * To keep implementation simple, all feature calls are assumed to have
26 * the prototype parameters (struct device_node* node, int value).
27 * When either is not used, pass 0.
28 */
29
30#ifdef __KERNEL__
31#ifndef __ASM_POWERPC_PMAC_FEATURE_H
32#define __ASM_POWERPC_PMAC_FEATURE_H
33
34#include <asm/macio.h>
35#include <asm/machdep.h>
36
37/*
38 * Known Mac motherboard models
39 *
40 * Please, report any error here to benh@kernel.crashing.org, thanks !
41 *
42 * Note that I don't fully maintain this list for Core99 & MacRISC2
43 * and I'm considering removing all NewWorld entries from it and
44 * entirely rely on the model string.
45 */
46
47/* PowerSurge are the first generation of PCI Pmacs. This include
48 * all of the Grand-Central based machines. We currently don't
49 * differenciate most of them.
50 */
51#define PMAC_TYPE_PSURGE 0x10 /* PowerSurge */
52#define PMAC_TYPE_ANS 0x11 /* Apple Network Server */
53
54/* Here is the infamous serie of OHare based machines
55 */
56#define PMAC_TYPE_COMET 0x20 /* Beleived to be PowerBook 2400 */
57#define PMAC_TYPE_HOOPER 0x21 /* Beleived to be PowerBook 3400 */
58#define PMAC_TYPE_KANGA 0x22 /* PowerBook 3500 (first G3) */
59#define PMAC_TYPE_ALCHEMY 0x23 /* Alchemy motherboard base */
60#define PMAC_TYPE_GAZELLE 0x24 /* Spartacus, some 5xxx/6xxx */
61#define PMAC_TYPE_UNKNOWN_OHARE 0x2f /* Unknown, but OHare based */
62
63/* Here are the Heathrow based machines
64 * FIXME: Differenciate wallstreet,mainstreet,wallstreetII
65 */
66#define PMAC_TYPE_GOSSAMER 0x30 /* Gossamer motherboard */
67#define PMAC_TYPE_SILK 0x31 /* Desktop PowerMac G3 */
68#define PMAC_TYPE_WALLSTREET 0x32 /* Wallstreet/Mainstreet PowerBook*/
69#define PMAC_TYPE_UNKNOWN_HEATHROW 0x3f /* Unknown but heathrow based */
70
71/* Here are newworld machines based on Paddington (heathrow derivative)
72 */
73#define PMAC_TYPE_101_PBOOK 0x40 /* 101 PowerBook (aka Lombard) */
74#define PMAC_TYPE_ORIG_IMAC 0x41 /* First generation iMac */
75#define PMAC_TYPE_YOSEMITE 0x42 /* B&W G3 */
76#define PMAC_TYPE_YIKES 0x43 /* Yikes G4 (PCI graphics) */
77#define PMAC_TYPE_UNKNOWN_PADDINGTON 0x4f /* Unknown but paddington based */
78
79/* Core99 machines based on UniNorth 1.0 and 1.5
80 *
81 * Note: A single entry here may cover several actual models according
82 * to the device-tree. (Sawtooth is most tower G4s, FW_IMAC is most
83 * FireWire based iMacs, etc...). Those machines are too similar to be
84 * distinguished here, when they need to be differencied, use the
85 * device-tree "model" or "compatible" property.
86 */
87#define PMAC_TYPE_ORIG_IBOOK 0x40 /* First iBook model (no firewire) */
88#define PMAC_TYPE_SAWTOOTH 0x41 /* Desktop G4s */
89#define PMAC_TYPE_FW_IMAC 0x42 /* FireWire iMacs (except Pangea based) */
90#define PMAC_TYPE_FW_IBOOK 0x43 /* FireWire iBooks (except iBook2) */
91#define PMAC_TYPE_CUBE 0x44 /* Cube PowerMac */
92#define PMAC_TYPE_QUICKSILVER 0x45 /* QuickSilver G4s */
93#define PMAC_TYPE_PISMO 0x46 /* Pismo PowerBook */
94#define PMAC_TYPE_TITANIUM 0x47 /* Titanium PowerBook */
95#define PMAC_TYPE_TITANIUM2 0x48 /* Titanium II PowerBook (no L3, M6) */
96#define PMAC_TYPE_TITANIUM3 0x49 /* Titanium III PowerBook (with L3 & M7) */
97#define PMAC_TYPE_TITANIUM4 0x50 /* Titanium IV PowerBook (with L3 & M9) */
98#define PMAC_TYPE_EMAC 0x50 /* eMac */
99#define PMAC_TYPE_UNKNOWN_CORE99 0x5f
100
101/* MacRisc2 with UniNorth 2.0 */
102#define PMAC_TYPE_RACKMAC 0x80 /* XServe */
103#define PMAC_TYPE_WINDTUNNEL 0x81
104
105/* MacRISC2 machines based on the Pangea chipset
106 */
107#define PMAC_TYPE_PANGEA_IMAC 0x100 /* Flower Power iMac */
108#define PMAC_TYPE_IBOOK2 0x101 /* iBook2 (polycarbonate) */
109#define PMAC_TYPE_FLAT_PANEL_IMAC 0x102 /* Flat panel iMac */
110#define PMAC_TYPE_UNKNOWN_PANGEA 0x10f
111
112/* MacRISC2 machines based on the Intrepid chipset
113 */
114#define PMAC_TYPE_UNKNOWN_INTREPID 0x11f /* Generic */
115
116/* MacRISC4 / G5 machines. We don't have per-machine selection here anymore,
117 * but rather machine families
118 */
119#define PMAC_TYPE_POWERMAC_G5 0x150 /* U3 & U3H based */
120#define PMAC_TYPE_POWERMAC_G5_U3L 0x151 /* U3L based desktop */
121#define PMAC_TYPE_IMAC_G5 0x152 /* iMac G5 */
122#define PMAC_TYPE_XSERVE_G5 0x153 /* Xserve G5 */
123#define PMAC_TYPE_UNKNOWN_K2 0x19f /* Any other K2 based */
124#define PMAC_TYPE_UNKNOWN_SHASTA 0x19e /* Any other Shasta based */
125
126/*
127 * Motherboard flags
128 */
129
130#define PMAC_MB_CAN_SLEEP 0x00000001
131#define PMAC_MB_HAS_FW_POWER 0x00000002
132#define PMAC_MB_OLD_CORE99 0x00000004
133#define PMAC_MB_MOBILE 0x00000008
134#define PMAC_MB_MAY_SLEEP 0x00000010
135
136/*
137 * Feature calls supported on pmac
138 *
139 */
140
141/*
142 * Use this inline wrapper
143 */
144struct device_node;
145
146static inline long pmac_call_feature(int selector, struct device_node* node,
147 long param, long value)
148{
149 if (!ppc_md.feature_call || !machine_is(powermac))
150 return -ENODEV;
151 return ppc_md.feature_call(selector, node, param, value);
152}
153
154/* PMAC_FTR_SERIAL_ENABLE (struct device_node* node, int param, int value)
155 * enable/disable an SCC side. Pass the node corresponding to the
156 * channel side as a parameter.
157 * param is the type of port
158 * if param is ored with PMAC_SCC_FLAG_XMON, then the SCC is locked enabled
159 * for use by xmon.
160 */
161#define PMAC_FTR_SCC_ENABLE PMAC_FTR_DEF(0)
162 #define PMAC_SCC_ASYNC 0
163 #define PMAC_SCC_IRDA 1
164 #define PMAC_SCC_I2S1 2
165 #define PMAC_SCC_FLAG_XMON 0x00001000
166
167/* PMAC_FTR_MODEM_ENABLE (struct device_node* node, 0, int value)
168 * enable/disable the internal modem.
169 */
170#define PMAC_FTR_MODEM_ENABLE PMAC_FTR_DEF(1)
171
172/* PMAC_FTR_SWIM3_ENABLE (struct device_node* node, 0,int value)
173 * enable/disable the swim3 (floppy) cell of a mac-io ASIC
174 */
175#define PMAC_FTR_SWIM3_ENABLE PMAC_FTR_DEF(2)
176
177/* PMAC_FTR_MESH_ENABLE (struct device_node* node, 0, int value)
178 * enable/disable the mesh (scsi) cell of a mac-io ASIC
179 */
180#define PMAC_FTR_MESH_ENABLE PMAC_FTR_DEF(3)
181
182/* PMAC_FTR_IDE_ENABLE (struct device_node* node, int busID, int value)
183 * enable/disable an IDE port of a mac-io ASIC
184 * pass the busID parameter
185 */
186#define PMAC_FTR_IDE_ENABLE PMAC_FTR_DEF(4)
187
188/* PMAC_FTR_IDE_RESET (struct device_node* node, int busID, int value)
189 * assert(1)/release(0) an IDE reset line (mac-io IDE only)
190 */
191#define PMAC_FTR_IDE_RESET PMAC_FTR_DEF(5)
192
193/* PMAC_FTR_BMAC_ENABLE (struct device_node* node, 0, int value)
194 * enable/disable the bmac (ethernet) cell of a mac-io ASIC, also drive
195 * it's reset line
196 */
197#define PMAC_FTR_BMAC_ENABLE PMAC_FTR_DEF(6)
198
199/* PMAC_FTR_GMAC_ENABLE (struct device_node* node, 0, int value)
200 * enable/disable the gmac (ethernet) cell of an uninorth ASIC. This
201 * control the cell's clock.
202 */
203#define PMAC_FTR_GMAC_ENABLE PMAC_FTR_DEF(7)
204
205/* PMAC_FTR_GMAC_PHY_RESET (struct device_node* node, 0, 0)
206 * Perform a HW reset of the PHY connected to a gmac controller.
207 * Pass the gmac device node, not the PHY node.
208 */
209#define PMAC_FTR_GMAC_PHY_RESET PMAC_FTR_DEF(8)
210
211/* PMAC_FTR_SOUND_CHIP_ENABLE (struct device_node* node, 0, int value)
212 * enable/disable the sound chip, whatever it is and provided it can
213 * acually be controlled
214 */
215#define PMAC_FTR_SOUND_CHIP_ENABLE PMAC_FTR_DEF(9)
216
217/* -- add various tweaks related to sound routing -- */
218
219/* PMAC_FTR_AIRPORT_ENABLE (struct device_node* node, 0, int value)
220 * enable/disable the airport card
221 */
222#define PMAC_FTR_AIRPORT_ENABLE PMAC_FTR_DEF(10)
223
224/* PMAC_FTR_RESET_CPU (NULL, int cpu_nr, 0)
225 * toggle the reset line of a CPU on an uninorth-based SMP machine
226 */
227#define PMAC_FTR_RESET_CPU PMAC_FTR_DEF(11)
228
229/* PMAC_FTR_USB_ENABLE (struct device_node* node, 0, int value)
230 * enable/disable an USB cell, along with the power of the USB "pad"
231 * on keylargo based machines
232 */
233#define PMAC_FTR_USB_ENABLE PMAC_FTR_DEF(12)
234
235/* PMAC_FTR_1394_ENABLE (struct device_node* node, 0, int value)
236 * enable/disable the firewire cell of an uninorth ASIC.
237 */
238#define PMAC_FTR_1394_ENABLE PMAC_FTR_DEF(13)
239
240/* PMAC_FTR_1394_CABLE_POWER (struct device_node* node, 0, int value)
241 * enable/disable the firewire cable power supply of the uninorth
242 * firewire cell
243 */
244#define PMAC_FTR_1394_CABLE_POWER PMAC_FTR_DEF(14)
245
246/* PMAC_FTR_SLEEP_STATE (struct device_node* node, 0, int value)
247 * set the sleep state of the motherboard.
248 *
249 * Pass -1 as value to query for sleep capability
250 * Pass 1 to set IOs to sleep
251 * Pass 0 to set IOs to wake
252 */
253#define PMAC_FTR_SLEEP_STATE PMAC_FTR_DEF(15)
254
255/* PMAC_FTR_GET_MB_INFO (NULL, selector, 0)
256 *
257 * returns some motherboard infos.
258 * selector: 0 - model id
259 * 1 - model flags (capabilities)
260 * 2 - model name (cast to const char *)
261 */
262#define PMAC_FTR_GET_MB_INFO PMAC_FTR_DEF(16)
263#define PMAC_MB_INFO_MODEL 0
264#define PMAC_MB_INFO_FLAGS 1
265#define PMAC_MB_INFO_NAME 2
266
267/* PMAC_FTR_READ_GPIO (NULL, int index, 0)
268 *
269 * read a GPIO from a mac-io controller of type KeyLargo or Pangea.
270 * the value returned is a byte (positive), or a negative error code
271 */
272#define PMAC_FTR_READ_GPIO PMAC_FTR_DEF(17)
273
274/* PMAC_FTR_WRITE_GPIO (NULL, int index, int value)
275 *
276 * write a GPIO of a mac-io controller of type KeyLargo or Pangea.
277 */
278#define PMAC_FTR_WRITE_GPIO PMAC_FTR_DEF(18)
279
280/* PMAC_FTR_ENABLE_MPIC
281 *
282 * Enable the MPIC cell
283 */
284#define PMAC_FTR_ENABLE_MPIC PMAC_FTR_DEF(19)
285
286/* PMAC_FTR_AACK_DELAY_ENABLE (NULL, int enable, 0)
287 *
288 * Enable/disable the AACK delay on the northbridge for systems using DFS
289 */
290#define PMAC_FTR_AACK_DELAY_ENABLE PMAC_FTR_DEF(20)
291
292/* PMAC_FTR_DEVICE_CAN_WAKE
293 *
294 * Used by video drivers to inform system that they can actually perform
295 * wakeup from sleep
296 */
297#define PMAC_FTR_DEVICE_CAN_WAKE PMAC_FTR_DEF(22)
298
299
300/* Don't use those directly, they are for the sake of pmac_setup.c */
301extern long pmac_do_feature_call(unsigned int selector, ...);
302extern void pmac_feature_init(void);
303
304/* Video suspend tweak */
305extern void pmac_set_early_video_resume(void (*proc)(void *data), void *data);
306extern void pmac_call_early_video_resume(void);
307
308#define PMAC_FTR_DEF(x) ((0x6660000) | (x))
309
310/* The AGP driver registers itself here */
311extern void pmac_register_agp_pm(struct pci_dev *bridge,
312 int (*suspend)(struct pci_dev *bridge),
313 int (*resume)(struct pci_dev *bridge));
314
315/* Those are meant to be used by video drivers to deal with AGP
316 * suspend resume properly
317 */
318extern void pmac_suspend_agp_for_card(struct pci_dev *dev);
319extern void pmac_resume_agp_for_card(struct pci_dev *dev);
320
321/*
322 * The part below is for use by macio_asic.c only, do not rely
323 * on the data structures or constants below in a normal driver
324 *
325 */
326
327#define MAX_MACIO_CHIPS 2
328
329enum {
330 macio_unknown = 0,
331 macio_grand_central,
332 macio_ohare,
333 macio_ohareII,
334 macio_heathrow,
335 macio_gatwick,
336 macio_paddington,
337 macio_keylargo,
338 macio_pangea,
339 macio_intrepid,
340 macio_keylargo2,
341 macio_shasta,
342};
343
344struct macio_chip
345{
346 struct device_node *of_node;
347 int type;
348 const char *name;
349 int rev;
350 volatile u32 __iomem *base;
351 unsigned long flags;
352
353 /* For use by macio_asic PCI driver */
354 struct macio_bus lbus;
355};
356
357extern struct macio_chip macio_chips[MAX_MACIO_CHIPS];
358
359#define MACIO_FLAG_SCCA_ON 0x00000001
360#define MACIO_FLAG_SCCB_ON 0x00000002
361#define MACIO_FLAG_SCC_LOCKED 0x00000004
362#define MACIO_FLAG_AIRPORT_ON 0x00000010
363#define MACIO_FLAG_FW_SUPPORTED 0x00000020
364
365extern struct macio_chip* macio_find(struct device_node* child, int type);
366
367#define MACIO_FCR32(macio, r) ((macio)->base + ((r) >> 2))
368#define MACIO_FCR8(macio, r) (((volatile u8 __iomem *)((macio)->base)) + (r))
369
370#define MACIO_IN32(r) (in_le32(MACIO_FCR32(macio,r)))
371#define MACIO_OUT32(r,v) (out_le32(MACIO_FCR32(macio,r), (v)))
372#define MACIO_BIS(r,v) (MACIO_OUT32((r), MACIO_IN32(r) | (v)))
373#define MACIO_BIC(r,v) (MACIO_OUT32((r), MACIO_IN32(r) & ~(v)))
374#define MACIO_IN8(r) (in_8(MACIO_FCR8(macio,r)))
375#define MACIO_OUT8(r,v) (out_8(MACIO_FCR8(macio,r), (v)))
376
377/*
378 * Those are exported by pmac feature for internal use by arch code
379 * only like the platform function callbacks, do not use directly in drivers
380 */
381extern spinlock_t feature_lock;
382extern struct device_node *uninorth_node;
383extern u32 __iomem *uninorth_base;
384
385/*
386 * Uninorth reg. access. Note that Uni-N regs are big endian
387 */
388
389#define UN_REG(r) (uninorth_base + ((r) >> 2))
390#define UN_IN(r) (in_be32(UN_REG(r)))
391#define UN_OUT(r,v) (out_be32(UN_REG(r), (v)))
392#define UN_BIS(r,v) (UN_OUT((r), UN_IN(r) | (v)))
393#define UN_BIC(r,v) (UN_OUT((r), UN_IN(r) & ~(v)))
394
395/* Uninorth variant:
396 *
397 * 0 = not uninorth
398 * 1 = U1.x or U2.x
399 * 3 = U3
400 * 4 = U4
401 */
402extern int pmac_get_uninorth_variant(void);
403
404#endif /* __ASM_POWERPC_PMAC_FEATURE_H */
405#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/pmac_low_i2c.h b/include/asm-powerpc/pmac_low_i2c.h
deleted file mode 100644
index 131011bd7e7..00000000000
--- a/include/asm-powerpc/pmac_low_i2c.h
+++ /dev/null
@@ -1,107 +0,0 @@
1/*
2 * include/asm-ppc/pmac_low_i2c.h
3 *
4 * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 */
12#ifndef __PMAC_LOW_I2C_H__
13#define __PMAC_LOW_I2C_H__
14#ifdef __KERNEL__
15
16/* i2c mode (based on the platform functions format) */
17enum {
18 pmac_i2c_mode_dumb = 1,
19 pmac_i2c_mode_std = 2,
20 pmac_i2c_mode_stdsub = 3,
21 pmac_i2c_mode_combined = 4,
22};
23
24/* RW bit in address */
25enum {
26 pmac_i2c_read = 0x01,
27 pmac_i2c_write = 0x00
28};
29
30/* i2c bus type */
31enum {
32 pmac_i2c_bus_keywest = 0,
33 pmac_i2c_bus_pmu = 1,
34 pmac_i2c_bus_smu = 2,
35};
36
37/* i2c bus features */
38enum {
39 /* can_largesub : supports >1 byte subaddresses (SMU only) */
40 pmac_i2c_can_largesub = 0x00000001u,
41
42 /* multibus : device node holds multiple busses, bus number is
43 * encoded in bits 0xff00 of "reg" of a given device
44 */
45 pmac_i2c_multibus = 0x00000002u,
46};
47
48/* i2c busses in the system */
49struct pmac_i2c_bus;
50struct i2c_adapter;
51
52/* Init, called early during boot */
53extern int pmac_i2c_init(void);
54
55/* Lookup an i2c bus for a device-node. The node can be either the bus
56 * node itself or a device below it. In the case of a multibus, the bus
57 * node itself is the controller node, else, it's a child of the controller
58 * node
59 */
60extern struct pmac_i2c_bus *pmac_i2c_find_bus(struct device_node *node);
61
62/* Get the address for an i2c device. This strips the bus number if
63 * necessary. The 7 bits address is returned 1 bit right shifted so that the
64 * direction can be directly ored in
65 */
66extern u8 pmac_i2c_get_dev_addr(struct device_node *device);
67
68/* Get infos about a bus */
69extern struct device_node *pmac_i2c_get_controller(struct pmac_i2c_bus *bus);
70extern struct device_node *pmac_i2c_get_bus_node(struct pmac_i2c_bus *bus);
71extern int pmac_i2c_get_type(struct pmac_i2c_bus *bus);
72extern int pmac_i2c_get_flags(struct pmac_i2c_bus *bus);
73extern int pmac_i2c_get_channel(struct pmac_i2c_bus *bus);
74
75/* i2c layer adapter attach/detach */
76extern void pmac_i2c_attach_adapter(struct pmac_i2c_bus *bus,
77 struct i2c_adapter *adapter);
78extern void pmac_i2c_detach_adapter(struct pmac_i2c_bus *bus,
79 struct i2c_adapter *adapter);
80extern struct i2c_adapter *pmac_i2c_get_adapter(struct pmac_i2c_bus *bus);
81extern struct pmac_i2c_bus *pmac_i2c_adapter_to_bus(struct i2c_adapter *adapter);
82
83/* March a device or bus with an i2c adapter structure, to be used by drivers
84 * to match device-tree nodes with i2c adapters during adapter discovery
85 * callbacks
86 */
87extern int pmac_i2c_match_adapter(struct device_node *dev,
88 struct i2c_adapter *adapter);
89
90
91/* (legacy) Locking functions exposed to i2c-keywest */
92extern int pmac_low_i2c_lock(struct device_node *np);
93extern int pmac_low_i2c_unlock(struct device_node *np);
94
95/* Access functions for platform code */
96extern int pmac_i2c_open(struct pmac_i2c_bus *bus, int polled);
97extern void pmac_i2c_close(struct pmac_i2c_bus *bus);
98extern int pmac_i2c_setmode(struct pmac_i2c_bus *bus, int mode);
99extern int pmac_i2c_xfer(struct pmac_i2c_bus *bus, u8 addrdir, int subsize,
100 u32 subaddr, u8 *data, int len);
101
102/* Suspend/resume code called by via-pmu directly for now */
103extern void pmac_pfunc_i2c_suspend(void);
104extern void pmac_pfunc_i2c_resume(void);
105
106#endif /* __KERNEL__ */
107#endif /* __PMAC_LOW_I2C_H__ */
diff --git a/include/asm-powerpc/pmac_pfunc.h b/include/asm-powerpc/pmac_pfunc.h
deleted file mode 100644
index 1330d6a58c5..00000000000
--- a/include/asm-powerpc/pmac_pfunc.h
+++ /dev/null
@@ -1,252 +0,0 @@
1#ifndef __PMAC_PFUNC_H__
2#define __PMAC_PFUNC_H__
3
4#include <linux/types.h>
5#include <linux/list.h>
6
7/* Flags in command lists */
8#define PMF_FLAGS_ON_INIT 0x80000000u
9#define PMF_FLGAS_ON_TERM 0x40000000u
10#define PMF_FLAGS_ON_SLEEP 0x20000000u
11#define PMF_FLAGS_ON_WAKE 0x10000000u
12#define PMF_FLAGS_ON_DEMAND 0x08000000u
13#define PMF_FLAGS_INT_GEN 0x04000000u
14#define PMF_FLAGS_HIGH_SPEED 0x02000000u
15#define PMF_FLAGS_LOW_SPEED 0x01000000u
16#define PMF_FLAGS_SIDE_EFFECTS 0x00800000u
17
18/*
19 * Arguments to a platform function call.
20 *
21 * NOTE: By convention, pointer arguments point to an u32
22 */
23struct pmf_args {
24 union {
25 u32 v;
26 u32 *p;
27 } u[4];
28 unsigned int count;
29};
30
31/*
32 * A driver capable of interpreting commands provides a handlers
33 * structure filled with whatever handlers are implemented by this
34 * driver. Non implemented handlers are left NULL.
35 *
36 * PMF_STD_ARGS are the same arguments that are passed to the parser
37 * and that gets passed back to the various handlers.
38 *
39 * Interpreting a given function always start with a begin() call which
40 * returns an instance data to be passed around subsequent calls, and
41 * ends with an end() call. This allows the low level driver to implement
42 * locking policy or per-function instance data.
43 *
44 * For interrupt capable functions, irq_enable() is called when a client
45 * registers, and irq_disable() is called when the last client unregisters
46 * Note that irq_enable & irq_disable are called within a semaphore held
47 * by the core, thus you should not try to register yourself to some other
48 * pmf interrupt during those calls.
49 */
50
51#define PMF_STD_ARGS struct pmf_function *func, void *instdata, \
52 struct pmf_args *args
53
54struct pmf_function;
55
56struct pmf_handlers {
57 void * (*begin)(struct pmf_function *func, struct pmf_args *args);
58 void (*end)(struct pmf_function *func, void *instdata);
59
60 int (*irq_enable)(struct pmf_function *func);
61 int (*irq_disable)(struct pmf_function *func);
62
63 int (*write_gpio)(PMF_STD_ARGS, u8 value, u8 mask);
64 int (*read_gpio)(PMF_STD_ARGS, u8 mask, int rshift, u8 xor);
65
66 int (*write_reg32)(PMF_STD_ARGS, u32 offset, u32 value, u32 mask);
67 int (*read_reg32)(PMF_STD_ARGS, u32 offset);
68 int (*write_reg16)(PMF_STD_ARGS, u32 offset, u16 value, u16 mask);
69 int (*read_reg16)(PMF_STD_ARGS, u32 offset);
70 int (*write_reg8)(PMF_STD_ARGS, u32 offset, u8 value, u8 mask);
71 int (*read_reg8)(PMF_STD_ARGS, u32 offset);
72
73 int (*delay)(PMF_STD_ARGS, u32 duration);
74
75 int (*wait_reg32)(PMF_STD_ARGS, u32 offset, u32 value, u32 mask);
76 int (*wait_reg16)(PMF_STD_ARGS, u32 offset, u16 value, u16 mask);
77 int (*wait_reg8)(PMF_STD_ARGS, u32 offset, u8 value, u8 mask);
78
79 int (*read_i2c)(PMF_STD_ARGS, u32 len);
80 int (*write_i2c)(PMF_STD_ARGS, u32 len, const u8 *data);
81 int (*rmw_i2c)(PMF_STD_ARGS, u32 masklen, u32 valuelen, u32 totallen,
82 const u8 *maskdata, const u8 *valuedata);
83
84 int (*read_cfg)(PMF_STD_ARGS, u32 offset, u32 len);
85 int (*write_cfg)(PMF_STD_ARGS, u32 offset, u32 len, const u8 *data);
86 int (*rmw_cfg)(PMF_STD_ARGS, u32 offset, u32 masklen, u32 valuelen,
87 u32 totallen, const u8 *maskdata, const u8 *valuedata);
88
89 int (*read_i2c_sub)(PMF_STD_ARGS, u8 subaddr, u32 len);
90 int (*write_i2c_sub)(PMF_STD_ARGS, u8 subaddr, u32 len, const u8 *data);
91 int (*set_i2c_mode)(PMF_STD_ARGS, int mode);
92 int (*rmw_i2c_sub)(PMF_STD_ARGS, u8 subaddr, u32 masklen, u32 valuelen,
93 u32 totallen, const u8 *maskdata,
94 const u8 *valuedata);
95
96 int (*read_reg32_msrx)(PMF_STD_ARGS, u32 offset, u32 mask, u32 shift,
97 u32 xor);
98 int (*read_reg16_msrx)(PMF_STD_ARGS, u32 offset, u32 mask, u32 shift,
99 u32 xor);
100 int (*read_reg8_msrx)(PMF_STD_ARGS, u32 offset, u32 mask, u32 shift,
101 u32 xor);
102
103 int (*write_reg32_slm)(PMF_STD_ARGS, u32 offset, u32 shift, u32 mask);
104 int (*write_reg16_slm)(PMF_STD_ARGS, u32 offset, u32 shift, u32 mask);
105 int (*write_reg8_slm)(PMF_STD_ARGS, u32 offset, u32 shift, u32 mask);
106
107 int (*mask_and_compare)(PMF_STD_ARGS, u32 len, const u8 *maskdata,
108 const u8 *valuedata);
109
110 struct module *owner;
111};
112
113
114/*
115 * Drivers who expose platform functions register at init time, this
116 * causes the platform functions for that device node to be parsed in
117 * advance and associated with the device. The data structures are
118 * partially public so a driver can walk the list of platform functions
119 * and eventually inspect the flags
120 */
121struct pmf_device;
122
123struct pmf_function {
124 /* All functions for a given driver are linked */
125 struct list_head link;
126
127 /* Function node & driver data */
128 struct device_node *node;
129 void *driver_data;
130
131 /* For internal use by core */
132 struct pmf_device *dev;
133
134 /* The name is the "xxx" in "platform-do-xxx", this is how
135 * platform functions are identified by this code. Some functions
136 * only operate for a given target, in which case the phandle is
137 * here (or 0 if the filter doesn't apply)
138 */
139 const char *name;
140 u32 phandle;
141
142 /* The flags for that function. You can have several functions
143 * with the same name and different flag
144 */
145 u32 flags;
146
147 /* The actual tokenized function blob */
148 const void *data;
149 unsigned int length;
150
151 /* Interrupt clients */
152 struct list_head irq_clients;
153
154 /* Refcounting */
155 struct kref ref;
156};
157
158/*
159 * For platform functions that are interrupts, one can register
160 * irq_client structures. You canNOT use the same structure twice
161 * as it contains a link member. Also, the callback is called with
162 * a spinlock held, you must not call back into any of the pmf_* functions
163 * from within that callback
164 */
165struct pmf_irq_client {
166 void (*handler)(void *data);
167 void *data;
168 struct module *owner;
169 struct list_head link;
170 struct pmf_function *func;
171};
172
173
174/*
175 * Register/Unregister a function-capable driver and its handlers
176 */
177extern int pmf_register_driver(struct device_node *np,
178 struct pmf_handlers *handlers,
179 void *driverdata);
180
181extern void pmf_unregister_driver(struct device_node *np);
182
183
184/*
185 * Register/Unregister interrupt clients
186 */
187extern int pmf_register_irq_client(struct device_node *np,
188 const char *name,
189 struct pmf_irq_client *client);
190
191extern void pmf_unregister_irq_client(struct pmf_irq_client *client);
192
193/*
194 * Called by the handlers when an irq happens
195 */
196extern void pmf_do_irq(struct pmf_function *func);
197
198
199/*
200 * Low level call to platform functions.
201 *
202 * The phandle can filter on the target object for functions that have
203 * multiple targets, the flags allow you to restrict the call to a given
204 * combination of flags.
205 *
206 * The args array contains as many arguments as is required by the function,
207 * this is dependent on the function you are calling, unfortunately Apple
208 * mechanism provides no way to encode that so you have to get it right at
209 * the call site. Some functions require no args, in which case, you can
210 * pass NULL.
211 *
212 * You can also pass NULL to the name. This will match any function that has
213 * the appropriate combination of flags & phandle or you can pass 0 to the
214 * phandle to match any
215 */
216extern int pmf_do_functions(struct device_node *np, const char *name,
217 u32 phandle, u32 flags, struct pmf_args *args);
218
219
220
221/*
222 * High level call to a platform function.
223 *
224 * This one looks for the platform-xxx first so you should call it to the
225 * actual target if any. It will fallback to platform-do-xxx if it can't
226 * find one. It will also exclusively target functions that have
227 * the "OnDemand" flag.
228 */
229
230extern int pmf_call_function(struct device_node *target, const char *name,
231 struct pmf_args *args);
232
233
234/*
235 * For low latency interrupt usage, you can lookup for on-demand functions
236 * using the functions below
237 */
238
239extern struct pmf_function *pmf_find_function(struct device_node *target,
240 const char *name);
241
242extern struct pmf_function * pmf_get_function(struct pmf_function *func);
243extern void pmf_put_function(struct pmf_function *func);
244
245extern int pmf_call_one(struct pmf_function *func, struct pmf_args *args);
246
247
248/* Suspend/resume code called by via-pmu directly for now */
249extern void pmac_pfunc_base_suspend(void);
250extern void pmac_pfunc_base_resume(void);
251
252#endif /* __PMAC_PFUNC_H__ */
diff --git a/include/asm-powerpc/pmc.h b/include/asm-powerpc/pmc.h
deleted file mode 100644
index d6a616a1b3e..00000000000
--- a/include/asm-powerpc/pmc.h
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * pmc.h
3 * Copyright (C) 2004 David Gibson, IBM Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#ifndef _POWERPC_PMC_H
20#define _POWERPC_PMC_H
21#ifdef __KERNEL__
22
23#include <asm/ptrace.h>
24
25typedef void (*perf_irq_t)(struct pt_regs *);
26extern perf_irq_t perf_irq;
27
28int reserve_pmc_hardware(perf_irq_t new_perf_irq);
29void release_pmc_hardware(void);
30
31#ifdef CONFIG_PPC64
32void power4_enable_pmcs(void);
33void pasemi_enable_pmcs(void);
34#endif
35
36#endif /* __KERNEL__ */
37#endif /* _POWERPC_PMC_H */
diff --git a/include/asm-powerpc/pmi.h b/include/asm-powerpc/pmi.h
deleted file mode 100644
index b4e91fbf508..00000000000
--- a/include/asm-powerpc/pmi.h
+++ /dev/null
@@ -1,66 +0,0 @@
1#ifndef _POWERPC_PMI_H
2#define _POWERPC_PMI_H
3
4/*
5 * Definitions for talking with PMI device on PowerPC
6 *
7 * PMI (Platform Management Interrupt) is a way to communicate
8 * with the BMC (Baseboard Management Controller) via interrupts.
9 * Unlike IPMI it is bidirectional and has a low latency.
10 *
11 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
12 *
13 * Author: Christian Krafft <krafft@de.ibm.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30#ifdef __KERNEL__
31
32#define PMI_TYPE_FREQ_CHANGE 0x01
33#define PMI_TYPE_POWER_BUTTON 0x02
34#define PMI_READ_TYPE 0
35#define PMI_READ_DATA0 1
36#define PMI_READ_DATA1 2
37#define PMI_READ_DATA2 3
38#define PMI_WRITE_TYPE 4
39#define PMI_WRITE_DATA0 5
40#define PMI_WRITE_DATA1 6
41#define PMI_WRITE_DATA2 7
42
43#define PMI_ACK 0x80
44
45#define PMI_TIMEOUT 100
46
47typedef struct {
48 u8 type;
49 u8 data0;
50 u8 data1;
51 u8 data2;
52} pmi_message_t;
53
54struct pmi_handler {
55 struct list_head node;
56 u8 type;
57 void (*handle_pmi_message) (pmi_message_t);
58};
59
60int pmi_register_handler(struct pmi_handler *);
61void pmi_unregister_handler(struct pmi_handler *);
62
63int pmi_send_message(pmi_message_t);
64
65#endif /* __KERNEL__ */
66#endif /* _POWERPC_PMI_H */
diff --git a/include/asm-powerpc/poll.h b/include/asm-powerpc/poll.h
deleted file mode 100644
index c98509d3149..00000000000
--- a/include/asm-powerpc/poll.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/poll.h>
diff --git a/include/asm-powerpc/posix_types.h b/include/asm-powerpc/posix_types.h
deleted file mode 100644
index c4e396b540d..00000000000
--- a/include/asm-powerpc/posix_types.h
+++ /dev/null
@@ -1,128 +0,0 @@
1#ifndef _ASM_POWERPC_POSIX_TYPES_H
2#define _ASM_POWERPC_POSIX_TYPES_H
3
4/*
5 * This file is generally used by user-level software, so you need to
6 * be a little careful about namespace pollution etc. Also, we cannot
7 * assume GCC is being used.
8 */
9
10typedef unsigned long __kernel_ino_t;
11typedef unsigned int __kernel_mode_t;
12typedef long __kernel_off_t;
13typedef int __kernel_pid_t;
14typedef unsigned int __kernel_uid_t;
15typedef unsigned int __kernel_gid_t;
16typedef long __kernel_ptrdiff_t;
17typedef long __kernel_time_t;
18typedef long __kernel_clock_t;
19typedef int __kernel_timer_t;
20typedef int __kernel_clockid_t;
21typedef long __kernel_suseconds_t;
22typedef int __kernel_daddr_t;
23typedef char * __kernel_caddr_t;
24typedef unsigned short __kernel_uid16_t;
25typedef unsigned short __kernel_gid16_t;
26typedef unsigned int __kernel_uid32_t;
27typedef unsigned int __kernel_gid32_t;
28typedef unsigned int __kernel_old_uid_t;
29typedef unsigned int __kernel_old_gid_t;
30
31#ifdef __powerpc64__
32typedef unsigned long __kernel_nlink_t;
33typedef int __kernel_ipc_pid_t;
34typedef unsigned long __kernel_size_t;
35typedef long __kernel_ssize_t;
36typedef unsigned long __kernel_old_dev_t;
37#else
38typedef unsigned short __kernel_nlink_t;
39typedef short __kernel_ipc_pid_t;
40typedef unsigned int __kernel_size_t;
41typedef int __kernel_ssize_t;
42typedef unsigned int __kernel_old_dev_t;
43#endif
44
45#ifdef __powerpc64__
46typedef long long __kernel_loff_t;
47#else
48#ifdef __GNUC__
49typedef long long __kernel_loff_t;
50#endif
51#endif
52
53typedef struct {
54 int val[2];
55} __kernel_fsid_t;
56
57#ifndef __GNUC__
58
59#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
60#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
61#define __FD_ISSET(d, set) (((set)->fds_bits[__FDELT(d)] & __FDMASK(d)) != 0)
62#define __FD_ZERO(set) \
63 ((void) memset ((void *) (set), 0, sizeof (__kernel_fd_set)))
64
65#else /* __GNUC__ */
66
67#if defined(__KERNEL__)
68/* With GNU C, use inline functions instead so args are evaluated only once: */
69
70#undef __FD_SET
71static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
72{
73 unsigned long _tmp = fd / __NFDBITS;
74 unsigned long _rem = fd % __NFDBITS;
75 fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
76}
77
78#undef __FD_CLR
79static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
80{
81 unsigned long _tmp = fd / __NFDBITS;
82 unsigned long _rem = fd % __NFDBITS;
83 fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
84}
85
86#undef __FD_ISSET
87static __inline__ int __FD_ISSET(unsigned long fd, __kernel_fd_set *p)
88{
89 unsigned long _tmp = fd / __NFDBITS;
90 unsigned long _rem = fd % __NFDBITS;
91 return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
92}
93
94/*
95 * This will unroll the loop for the normal constant case (8 ints,
96 * for a 256-bit fd_set)
97 */
98#undef __FD_ZERO
99static __inline__ void __FD_ZERO(__kernel_fd_set *p)
100{
101 unsigned long *tmp = (unsigned long *)p->fds_bits;
102 int i;
103
104 if (__builtin_constant_p(__FDSET_LONGS)) {
105 switch (__FDSET_LONGS) {
106 case 16:
107 tmp[12] = 0; tmp[13] = 0; tmp[14] = 0; tmp[15] = 0;
108 tmp[ 8] = 0; tmp[ 9] = 0; tmp[10] = 0; tmp[11] = 0;
109
110 case 8:
111 tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
112
113 case 4:
114 tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
115 return;
116 }
117 }
118 i = __FDSET_LONGS;
119 while (i) {
120 i--;
121 *tmp = 0;
122 tmp++;
123 }
124}
125
126#endif /* defined(__KERNEL__) */
127#endif /* __GNUC__ */
128#endif /* _ASM_POWERPC_POSIX_TYPES_H */
diff --git a/include/asm-powerpc/ppc-pci.h b/include/asm-powerpc/ppc-pci.h
deleted file mode 100644
index 854ab713f56..00000000000
--- a/include/asm-powerpc/ppc-pci.h
+++ /dev/null
@@ -1,149 +0,0 @@
1/*
2 * c 2001 PPC 64 Team, IBM Corp
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9#ifndef _ASM_POWERPC_PPC_PCI_H
10#define _ASM_POWERPC_PPC_PCI_H
11#ifdef __KERNEL__
12
13#ifdef CONFIG_PCI
14
15#include <linux/pci.h>
16#include <asm/pci-bridge.h>
17
18extern unsigned long isa_io_base;
19
20extern void pci_setup_phb_io(struct pci_controller *hose, int primary);
21extern void pci_setup_phb_io_dynamic(struct pci_controller *hose, int primary);
22
23
24extern struct list_head hose_list;
25
26extern void find_and_init_phbs(void);
27
28extern struct pci_dev *isa_bridge_pcidev; /* may be NULL if no ISA bus */
29
30/** Bus Unit ID macros; get low and hi 32-bits of the 64-bit BUID */
31#define BUID_HI(buid) ((buid) >> 32)
32#define BUID_LO(buid) ((buid) & 0xffffffff)
33
34/* PCI device_node operations */
35struct device_node;
36typedef void *(*traverse_func)(struct device_node *me, void *data);
37void *traverse_pci_devices(struct device_node *start, traverse_func pre,
38 void *data);
39
40extern void pci_devs_phb_init(void);
41extern void pci_devs_phb_init_dynamic(struct pci_controller *phb);
42extern void scan_phb(struct pci_controller *hose);
43
44/* From rtas_pci.h */
45extern void init_pci_config_tokens (void);
46extern unsigned long get_phb_buid (struct device_node *);
47extern int rtas_setup_phb(struct pci_controller *phb);
48
49extern unsigned long pci_probe_only;
50
51/* ---- EEH internal-use-only related routines ---- */
52#ifdef CONFIG_EEH
53
54void pci_addr_cache_insert_device(struct pci_dev *dev);
55void pci_addr_cache_remove_device(struct pci_dev *dev);
56void pci_addr_cache_build(void);
57struct pci_dev *pci_get_device_by_addr(unsigned long addr);
58
59/**
60 * eeh_slot_error_detail -- record and EEH error condition to the log
61 * @pdn: pci device node
62 * @severity: EEH_LOG_TEMP_FAILURE or EEH_LOG_PERM_FAILURE
63 *
64 * Obtains the EEH error details from the RTAS subsystem,
65 * and then logs these details with the RTAS error log system.
66 */
67#define EEH_LOG_TEMP_FAILURE 1
68#define EEH_LOG_PERM_FAILURE 2
69void eeh_slot_error_detail (struct pci_dn *pdn, int severity);
70
71/**
72 * rtas_pci_enable - enable IO transfers for this slot
73 * @pdn: pci device node
74 * @function: either EEH_THAW_MMIO or EEH_THAW_DMA
75 *
76 * Enable I/O transfers to this slot
77 */
78#define EEH_THAW_MMIO 2
79#define EEH_THAW_DMA 3
80int rtas_pci_enable(struct pci_dn *pdn, int function);
81
82/**
83 * rtas_set_slot_reset -- unfreeze a frozen slot
84 * @pdn: pci device node
85 *
86 * Clear the EEH-frozen condition on a slot. This routine
87 * does this by asserting the PCI #RST line for 1/8th of
88 * a second; this routine will sleep while the adapter is
89 * being reset.
90 *
91 * Returns a non-zero value if the reset failed.
92 */
93int rtas_set_slot_reset (struct pci_dn *);
94int eeh_wait_for_slot_status(struct pci_dn *pdn, int max_wait_msecs);
95
96/**
97 * eeh_restore_bars - Restore device configuration info.
98 * @pdn: pci device node
99 *
100 * A reset of a PCI device will clear out its config space.
101 * This routines will restore the config space for this
102 * device, and is children, to values previously obtained
103 * from the firmware.
104 */
105void eeh_restore_bars(struct pci_dn *);
106
107/**
108 * rtas_configure_bridge -- firmware initialization of pci bridge
109 * @pdn: pci device node
110 *
111 * Ask the firmware to configure all PCI bridges devices
112 * located behind the indicated node. Required after a
113 * pci device reset. Does essentially the same hing as
114 * eeh_restore_bars, but for brdges, and lets firmware
115 * do the work.
116 */
117void rtas_configure_bridge(struct pci_dn *);
118
119int rtas_write_config(struct pci_dn *, int where, int size, u32 val);
120int rtas_read_config(struct pci_dn *, int where, int size, u32 *val);
121
122/**
123 * eeh_mark_slot -- set mode flags for pertition endpoint
124 * @pdn: pci device node
125 *
126 * mark and clear slots: find "partition endpoint" PE and set or
127 * clear the flags for each subnode of the PE.
128 */
129void eeh_mark_slot (struct device_node *dn, int mode_flag);
130void eeh_clear_slot (struct device_node *dn, int mode_flag);
131
132/**
133 * find_device_pe -- Find the associated "Partiationable Endpoint" PE
134 * @pdn: pci device node
135 */
136struct device_node * find_device_pe(struct device_node *dn);
137
138void eeh_sysfs_add_device(struct pci_dev *pdev);
139void eeh_sysfs_remove_device(struct pci_dev *pdev);
140
141#endif /* CONFIG_EEH */
142
143#else /* CONFIG_PCI */
144static inline void find_and_init_phbs(void) { }
145static inline void init_pci_config_tokens(void) { }
146#endif /* !CONFIG_PCI */
147
148#endif /* __KERNEL__ */
149#endif /* _ASM_POWERPC_PPC_PCI_H */
diff --git a/include/asm-powerpc/ppc4xx.h b/include/asm-powerpc/ppc4xx.h
deleted file mode 100644
index 033039a80c4..00000000000
--- a/include/asm-powerpc/ppc4xx.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/*
2 * PPC4xx Prototypes and definitions
3 *
4 * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 *
6 * This is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13#ifndef __ASM_POWERPC_PPC4xx_H__
14#define __ASM_POWERPC_PPC4xx_H__
15
16extern void ppc4xx_reset_system(char *cmd);
17
18#endif /* __ASM_POWERPC_PPC4xx_H__ */
diff --git a/include/asm-powerpc/ppc_asm.h b/include/asm-powerpc/ppc_asm.h
deleted file mode 100644
index 0966899d974..00000000000
--- a/include/asm-powerpc/ppc_asm.h
+++ /dev/null
@@ -1,689 +0,0 @@
1/*
2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
3 */
4#ifndef _ASM_POWERPC_PPC_ASM_H
5#define _ASM_POWERPC_PPC_ASM_H
6
7#include <linux/stringify.h>
8#include <asm/asm-compat.h>
9#include <asm/processor.h>
10
11#ifndef __ASSEMBLY__
12#error __FILE__ should only be used in assembler files
13#else
14
15#define SZL (BITS_PER_LONG/8)
16
17/*
18 * Stuff for accurate CPU time accounting.
19 * These macros handle transitions between user and system state
20 * in exception entry and exit and accumulate time to the
21 * user_time and system_time fields in the paca.
22 */
23
24#ifndef CONFIG_VIRT_CPU_ACCOUNTING
25#define ACCOUNT_CPU_USER_ENTRY(ra, rb)
26#define ACCOUNT_CPU_USER_EXIT(ra, rb)
27#else
28#define ACCOUNT_CPU_USER_ENTRY(ra, rb) \
29 beq 2f; /* if from kernel mode */ \
30BEGIN_FTR_SECTION; \
31 mfspr ra,SPRN_PURR; /* get processor util. reg */ \
32END_FTR_SECTION_IFSET(CPU_FTR_PURR); \
33BEGIN_FTR_SECTION; \
34 MFTB(ra); /* or get TB if no PURR */ \
35END_FTR_SECTION_IFCLR(CPU_FTR_PURR); \
36 ld rb,PACA_STARTPURR(r13); \
37 std ra,PACA_STARTPURR(r13); \
38 subf rb,rb,ra; /* subtract start value */ \
39 ld ra,PACA_USER_TIME(r13); \
40 add ra,ra,rb; /* add on to user time */ \
41 std ra,PACA_USER_TIME(r13); \
422:
43
44#define ACCOUNT_CPU_USER_EXIT(ra, rb) \
45BEGIN_FTR_SECTION; \
46 mfspr ra,SPRN_PURR; /* get processor util. reg */ \
47END_FTR_SECTION_IFSET(CPU_FTR_PURR); \
48BEGIN_FTR_SECTION; \
49 MFTB(ra); /* or get TB if no PURR */ \
50END_FTR_SECTION_IFCLR(CPU_FTR_PURR); \
51 ld rb,PACA_STARTPURR(r13); \
52 std ra,PACA_STARTPURR(r13); \
53 subf rb,rb,ra; /* subtract start value */ \
54 ld ra,PACA_SYSTEM_TIME(r13); \
55 add ra,ra,rb; /* add on to user time */ \
56 std ra,PACA_SYSTEM_TIME(r13);
57#endif
58
59/*
60 * Macros for storing registers into and loading registers from
61 * exception frames.
62 */
63#ifdef __powerpc64__
64#define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
65#define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
66#define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
67#define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
68#else
69#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
70#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
71#define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
72 SAVE_10GPRS(22, base)
73#define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \
74 REST_10GPRS(22, base)
75#endif
76
77/*
78 * Define what the VSX XX1 form instructions will look like, then add
79 * the 128 bit load store instructions based on that.
80 */
81#define VSX_XX1(xs, ra, rb) (((xs) & 0x1f) << 21 | ((ra) << 16) | \
82 ((rb) << 11) | (((xs) >> 5)))
83
84#define STXVD2X(xs, ra, rb) .long (0x7c000798 | VSX_XX1((xs), (ra), (rb)))
85#define LXVD2X(xs, ra, rb) .long (0x7c000698 | VSX_XX1((xs), (ra), (rb)))
86
87#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
88#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
89#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
90#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
91#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
92#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
93#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
94#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
95
96#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base)
97#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
98#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
99#define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
100#define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
101#define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
102#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base)
103#define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
104#define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
105#define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
106#define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
107#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
108
109#define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base
110#define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
111#define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
112#define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
113#define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
114#define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
115#define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base
116#define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
117#define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
118#define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
119#define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
120#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
121
122/* Save the lower 32 VSRs in the thread VSR region */
123#define SAVE_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); STXVD2X(n,b,base)
124#define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
125#define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
126#define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
127#define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
128#define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
129#define REST_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); LXVD2X(n,b,base)
130#define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base)
131#define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
132#define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
133#define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
134#define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
135/* Save the upper 32 VSRs (32-63) in the thread VSX region (0-31) */
136#define SAVE_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); STXVD2X(n+32,b,base)
137#define SAVE_2VSRSU(n,b,base) SAVE_VSRU(n,b,base); SAVE_VSRU(n+1,b,base)
138#define SAVE_4VSRSU(n,b,base) SAVE_2VSRSU(n,b,base); SAVE_2VSRSU(n+2,b,base)
139#define SAVE_8VSRSU(n,b,base) SAVE_4VSRSU(n,b,base); SAVE_4VSRSU(n+4,b,base)
140#define SAVE_16VSRSU(n,b,base) SAVE_8VSRSU(n,b,base); SAVE_8VSRSU(n+8,b,base)
141#define SAVE_32VSRSU(n,b,base) SAVE_16VSRSU(n,b,base); SAVE_16VSRSU(n+16,b,base)
142#define REST_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,b,base)
143#define REST_2VSRSU(n,b,base) REST_VSRU(n,b,base); REST_VSRU(n+1,b,base)
144#define REST_4VSRSU(n,b,base) REST_2VSRSU(n,b,base); REST_2VSRSU(n+2,b,base)
145#define REST_8VSRSU(n,b,base) REST_4VSRSU(n,b,base); REST_4VSRSU(n+4,b,base)
146#define REST_16VSRSU(n,b,base) REST_8VSRSU(n,b,base); REST_8VSRSU(n+8,b,base)
147#define REST_32VSRSU(n,b,base) REST_16VSRSU(n,b,base); REST_16VSRSU(n+16,b,base)
148
149#define SAVE_EVR(n,s,base) evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)
150#define SAVE_2EVRS(n,s,base) SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
151#define SAVE_4EVRS(n,s,base) SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base)
152#define SAVE_8EVRS(n,s,base) SAVE_4EVRS(n,s,base); SAVE_4EVRS(n+4,s,base)
153#define SAVE_16EVRS(n,s,base) SAVE_8EVRS(n,s,base); SAVE_8EVRS(n+8,s,base)
154#define SAVE_32EVRS(n,s,base) SAVE_16EVRS(n,s,base); SAVE_16EVRS(n+16,s,base)
155#define REST_EVR(n,s,base) lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n
156#define REST_2EVRS(n,s,base) REST_EVR(n,s,base); REST_EVR(n+1,s,base)
157#define REST_4EVRS(n,s,base) REST_2EVRS(n,s,base); REST_2EVRS(n+2,s,base)
158#define REST_8EVRS(n,s,base) REST_4EVRS(n,s,base); REST_4EVRS(n+4,s,base)
159#define REST_16EVRS(n,s,base) REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base)
160#define REST_32EVRS(n,s,base) REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base)
161
162/* Macros to adjust thread priority for hardware multithreading */
163#define HMT_VERY_LOW or 31,31,31 # very low priority
164#define HMT_LOW or 1,1,1
165#define HMT_MEDIUM_LOW or 6,6,6 # medium low priority
166#define HMT_MEDIUM or 2,2,2
167#define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority
168#define HMT_HIGH or 3,3,3
169
170/* handle instructions that older assemblers may not know */
171#define RFCI .long 0x4c000066 /* rfci instruction */
172#define RFDI .long 0x4c00004e /* rfdi instruction */
173#define RFMCI .long 0x4c00004c /* rfmci instruction */
174
175#ifdef __KERNEL__
176#ifdef CONFIG_PPC64
177
178#define XGLUE(a,b) a##b
179#define GLUE(a,b) XGLUE(a,b)
180
181#define _GLOBAL(name) \
182 .section ".text"; \
183 .align 2 ; \
184 .globl name; \
185 .globl GLUE(.,name); \
186 .section ".opd","aw"; \
187name: \
188 .quad GLUE(.,name); \
189 .quad .TOC.@tocbase; \
190 .quad 0; \
191 .previous; \
192 .type GLUE(.,name),@function; \
193GLUE(.,name):
194
195#define _INIT_GLOBAL(name) \
196 .section ".text.init.refok"; \
197 .align 2 ; \
198 .globl name; \
199 .globl GLUE(.,name); \
200 .section ".opd","aw"; \
201name: \
202 .quad GLUE(.,name); \
203 .quad .TOC.@tocbase; \
204 .quad 0; \
205 .previous; \
206 .type GLUE(.,name),@function; \
207GLUE(.,name):
208
209#define _KPROBE(name) \
210 .section ".kprobes.text","a"; \
211 .align 2 ; \
212 .globl name; \
213 .globl GLUE(.,name); \
214 .section ".opd","aw"; \
215name: \
216 .quad GLUE(.,name); \
217 .quad .TOC.@tocbase; \
218 .quad 0; \
219 .previous; \
220 .type GLUE(.,name),@function; \
221GLUE(.,name):
222
223#define _STATIC(name) \
224 .section ".text"; \
225 .align 2 ; \
226 .section ".opd","aw"; \
227name: \
228 .quad GLUE(.,name); \
229 .quad .TOC.@tocbase; \
230 .quad 0; \
231 .previous; \
232 .type GLUE(.,name),@function; \
233GLUE(.,name):
234
235#define _INIT_STATIC(name) \
236 .section ".text.init.refok"; \
237 .align 2 ; \
238 .section ".opd","aw"; \
239name: \
240 .quad GLUE(.,name); \
241 .quad .TOC.@tocbase; \
242 .quad 0; \
243 .previous; \
244 .type GLUE(.,name),@function; \
245GLUE(.,name):
246
247#else /* 32-bit */
248
249#define _ENTRY(n) \
250 .globl n; \
251n:
252
253#define _GLOBAL(n) \
254 .text; \
255 .stabs __stringify(n:F-1),N_FUN,0,0,n;\
256 .globl n; \
257n:
258
259#define _KPROBE(n) \
260 .section ".kprobes.text","a"; \
261 .globl n; \
262n:
263
264#endif
265
266/*
267 * LOAD_REG_IMMEDIATE(rn, expr)
268 * Loads the value of the constant expression 'expr' into register 'rn'
269 * using immediate instructions only. Use this when it's important not
270 * to reference other data (i.e. on ppc64 when the TOC pointer is not
271 * valid).
272 *
273 * LOAD_REG_ADDR(rn, name)
274 * Loads the address of label 'name' into register 'rn'. Use this when
275 * you don't particularly need immediate instructions only, but you need
276 * the whole address in one register (e.g. it's a structure address and
277 * you want to access various offsets within it). On ppc32 this is
278 * identical to LOAD_REG_IMMEDIATE.
279 *
280 * LOAD_REG_ADDRBASE(rn, name)
281 * ADDROFF(name)
282 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into
283 * register 'rn'. ADDROFF(name) returns the remainder of the address as
284 * a constant expression. ADDROFF(name) is a signed expression < 16 bits
285 * in size, so is suitable for use directly as an offset in load and store
286 * instructions. Use this when loading/storing a single word or less as:
287 * LOAD_REG_ADDRBASE(rX, name)
288 * ld rY,ADDROFF(name)(rX)
289 */
290#ifdef __powerpc64__
291#define LOAD_REG_IMMEDIATE(reg,expr) \
292 lis (reg),(expr)@highest; \
293 ori (reg),(reg),(expr)@higher; \
294 rldicr (reg),(reg),32,31; \
295 oris (reg),(reg),(expr)@h; \
296 ori (reg),(reg),(expr)@l;
297
298#define LOAD_REG_ADDR(reg,name) \
299 ld (reg),name@got(r2)
300
301#define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name)
302#define ADDROFF(name) 0
303
304/* offsets for stack frame layout */
305#define LRSAVE 16
306
307#else /* 32-bit */
308
309#define LOAD_REG_IMMEDIATE(reg,expr) \
310 lis (reg),(expr)@ha; \
311 addi (reg),(reg),(expr)@l;
312
313#define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE(reg, name)
314
315#define LOAD_REG_ADDRBASE(reg, name) lis (reg),name@ha
316#define ADDROFF(name) name@l
317
318/* offsets for stack frame layout */
319#define LRSAVE 4
320
321#endif
322
323/* various errata or part fixups */
324#ifdef CONFIG_PPC601_SYNC_FIX
325#define SYNC \
326BEGIN_FTR_SECTION \
327 sync; \
328 isync; \
329END_FTR_SECTION_IFSET(CPU_FTR_601)
330#define SYNC_601 \
331BEGIN_FTR_SECTION \
332 sync; \
333END_FTR_SECTION_IFSET(CPU_FTR_601)
334#define ISYNC_601 \
335BEGIN_FTR_SECTION \
336 isync; \
337END_FTR_SECTION_IFSET(CPU_FTR_601)
338#else
339#define SYNC
340#define SYNC_601
341#define ISYNC_601
342#endif
343
344#ifdef CONFIG_PPC_CELL
345#define MFTB(dest) \
34690: mftb dest; \
347BEGIN_FTR_SECTION_NESTED(96); \
348 cmpwi dest,0; \
349 beq- 90b; \
350END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
351#else
352#define MFTB(dest) mftb dest
353#endif
354
355#ifndef CONFIG_SMP
356#define TLBSYNC
357#else /* CONFIG_SMP */
358/* tlbsync is not implemented on 601 */
359#define TLBSYNC \
360BEGIN_FTR_SECTION \
361 tlbsync; \
362 sync; \
363END_FTR_SECTION_IFCLR(CPU_FTR_601)
364#endif
365
366
367/*
368 * This instruction is not implemented on the PPC 603 or 601; however, on
369 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
370 * All of these instructions exist in the 8xx, they have magical powers,
371 * and they must be used.
372 */
373
374#if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
375#define tlbia \
376 li r4,1024; \
377 mtctr r4; \
378 lis r4,KERNELBASE@h; \
3790: tlbie r4; \
380 addi r4,r4,0x1000; \
381 bdnz 0b
382#endif
383
384
385#ifdef CONFIG_IBM440EP_ERR42
386#define PPC440EP_ERR42 isync
387#else
388#define PPC440EP_ERR42
389#endif
390
391
392#if defined(CONFIG_BOOKE)
393#define toreal(rd)
394#define fromreal(rd)
395
396/*
397 * We use addis to ensure compatibility with the "classic" ppc versions of
398 * these macros, which use rs = 0 to get the tophys offset in rd, rather than
399 * converting the address in r0, and so this version has to do that too
400 * (i.e. set register rd to 0 when rs == 0).
401 */
402#define tophys(rd,rs) \
403 addis rd,rs,0
404
405#define tovirt(rd,rs) \
406 addis rd,rs,0
407
408#elif defined(CONFIG_PPC64)
409#define toreal(rd) /* we can access c000... in real mode */
410#define fromreal(rd)
411
412#define tophys(rd,rs) \
413 clrldi rd,rs,2
414
415#define tovirt(rd,rs) \
416 rotldi rd,rs,16; \
417 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\
418 rotldi rd,rd,48
419#else
420/*
421 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
422 * physical base address of RAM at compile time.
423 */
424#define toreal(rd) tophys(rd,rd)
425#define fromreal(rd) tovirt(rd,rd)
426
427#define tophys(rd,rs) \
4280: addis rd,rs,-KERNELBASE@h; \
429 .section ".vtop_fixup","aw"; \
430 .align 1; \
431 .long 0b; \
432 .previous
433
434#define tovirt(rd,rs) \
4350: addis rd,rs,KERNELBASE@h; \
436 .section ".ptov_fixup","aw"; \
437 .align 1; \
438 .long 0b; \
439 .previous
440#endif
441
442#ifdef CONFIG_PPC64
443#define RFI rfid
444#define MTMSRD(r) mtmsrd r
445
446#else
447#define FIX_SRR1(ra, rb)
448#ifndef CONFIG_40x
449#define RFI rfi
450#else
451#define RFI rfi; b . /* Prevent prefetch past rfi */
452#endif
453#define MTMSRD(r) mtmsr r
454#define CLR_TOP32(r)
455#endif
456
457#endif /* __KERNEL__ */
458
459/* The boring bits... */
460
461/* Condition Register Bit Fields */
462
463#define cr0 0
464#define cr1 1
465#define cr2 2
466#define cr3 3
467#define cr4 4
468#define cr5 5
469#define cr6 6
470#define cr7 7
471
472
473/* General Purpose Registers (GPRs) */
474
475#define r0 0
476#define r1 1
477#define r2 2
478#define r3 3
479#define r4 4
480#define r5 5
481#define r6 6
482#define r7 7
483#define r8 8
484#define r9 9
485#define r10 10
486#define r11 11
487#define r12 12
488#define r13 13
489#define r14 14
490#define r15 15
491#define r16 16
492#define r17 17
493#define r18 18
494#define r19 19
495#define r20 20
496#define r21 21
497#define r22 22
498#define r23 23
499#define r24 24
500#define r25 25
501#define r26 26
502#define r27 27
503#define r28 28
504#define r29 29
505#define r30 30
506#define r31 31
507
508
509/* Floating Point Registers (FPRs) */
510
511#define fr0 0
512#define fr1 1
513#define fr2 2
514#define fr3 3
515#define fr4 4
516#define fr5 5
517#define fr6 6
518#define fr7 7
519#define fr8 8
520#define fr9 9
521#define fr10 10
522#define fr11 11
523#define fr12 12
524#define fr13 13
525#define fr14 14
526#define fr15 15
527#define fr16 16
528#define fr17 17
529#define fr18 18
530#define fr19 19
531#define fr20 20
532#define fr21 21
533#define fr22 22
534#define fr23 23
535#define fr24 24
536#define fr25 25
537#define fr26 26
538#define fr27 27
539#define fr28 28
540#define fr29 29
541#define fr30 30
542#define fr31 31
543
544/* AltiVec Registers (VPRs) */
545
546#define vr0 0
547#define vr1 1
548#define vr2 2
549#define vr3 3
550#define vr4 4
551#define vr5 5
552#define vr6 6
553#define vr7 7
554#define vr8 8
555#define vr9 9
556#define vr10 10
557#define vr11 11
558#define vr12 12
559#define vr13 13
560#define vr14 14
561#define vr15 15
562#define vr16 16
563#define vr17 17
564#define vr18 18
565#define vr19 19
566#define vr20 20
567#define vr21 21
568#define vr22 22
569#define vr23 23
570#define vr24 24
571#define vr25 25
572#define vr26 26
573#define vr27 27
574#define vr28 28
575#define vr29 29
576#define vr30 30
577#define vr31 31
578
579/* VSX Registers (VSRs) */
580
581#define vsr0 0
582#define vsr1 1
583#define vsr2 2
584#define vsr3 3
585#define vsr4 4
586#define vsr5 5
587#define vsr6 6
588#define vsr7 7
589#define vsr8 8
590#define vsr9 9
591#define vsr10 10
592#define vsr11 11
593#define vsr12 12
594#define vsr13 13
595#define vsr14 14
596#define vsr15 15
597#define vsr16 16
598#define vsr17 17
599#define vsr18 18
600#define vsr19 19
601#define vsr20 20
602#define vsr21 21
603#define vsr22 22
604#define vsr23 23
605#define vsr24 24
606#define vsr25 25
607#define vsr26 26
608#define vsr27 27
609#define vsr28 28
610#define vsr29 29
611#define vsr30 30
612#define vsr31 31
613#define vsr32 32
614#define vsr33 33
615#define vsr34 34
616#define vsr35 35
617#define vsr36 36
618#define vsr37 37
619#define vsr38 38
620#define vsr39 39
621#define vsr40 40
622#define vsr41 41
623#define vsr42 42
624#define vsr43 43
625#define vsr44 44
626#define vsr45 45
627#define vsr46 46
628#define vsr47 47
629#define vsr48 48
630#define vsr49 49
631#define vsr50 50
632#define vsr51 51
633#define vsr52 52
634#define vsr53 53
635#define vsr54 54
636#define vsr55 55
637#define vsr56 56
638#define vsr57 57
639#define vsr58 58
640#define vsr59 59
641#define vsr60 60
642#define vsr61 61
643#define vsr62 62
644#define vsr63 63
645
646/* SPE Registers (EVPRs) */
647
648#define evr0 0
649#define evr1 1
650#define evr2 2
651#define evr3 3
652#define evr4 4
653#define evr5 5
654#define evr6 6
655#define evr7 7
656#define evr8 8
657#define evr9 9
658#define evr10 10
659#define evr11 11
660#define evr12 12
661#define evr13 13
662#define evr14 14
663#define evr15 15
664#define evr16 16
665#define evr17 17
666#define evr18 18
667#define evr19 19
668#define evr20 20
669#define evr21 21
670#define evr22 22
671#define evr23 23
672#define evr24 24
673#define evr25 25
674#define evr26 26
675#define evr27 27
676#define evr28 28
677#define evr29 29
678#define evr30 30
679#define evr31 31
680
681/* some stab codes */
682#define N_FUN 36
683#define N_RSYM 64
684#define N_SLINE 68
685#define N_SO 100
686
687#endif /* __ASSEMBLY__ */
688
689#endif /* _ASM_POWERPC_PPC_ASM_H */
diff --git a/include/asm-powerpc/processor.h b/include/asm-powerpc/processor.h
deleted file mode 100644
index 101ed87f7d8..00000000000
--- a/include/asm-powerpc/processor.h
+++ /dev/null
@@ -1,314 +0,0 @@
1#ifndef _ASM_POWERPC_PROCESSOR_H
2#define _ASM_POWERPC_PROCESSOR_H
3
4/*
5 * Copyright (C) 2001 PPC 64 Team, IBM Corp
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#include <asm/reg.h>
14
15#ifdef CONFIG_VSX
16#define TS_FPRWIDTH 2
17#else
18#define TS_FPRWIDTH 1
19#endif
20
21#ifndef __ASSEMBLY__
22#include <linux/compiler.h>
23#include <asm/ptrace.h>
24#include <asm/types.h>
25
26/* We do _not_ want to define new machine types at all, those must die
27 * in favor of using the device-tree
28 * -- BenH.
29 */
30
31/* PREP sub-platform types see residual.h for these */
32#define _PREP_Motorola 0x01 /* motorola prep */
33#define _PREP_Firm 0x02 /* firmworks prep */
34#define _PREP_IBM 0x00 /* ibm prep */
35#define _PREP_Bull 0x03 /* bull prep */
36
37/* CHRP sub-platform types. These are arbitrary */
38#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
39#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
40#define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */
41#define _CHRP_briq 0x07 /* TotalImpact's briQ */
42
43#if defined(__KERNEL__) && defined(CONFIG_PPC32)
44
45extern int _chrp_type;
46
47#ifdef CONFIG_PPC_PREP
48
49/* what kind of prep workstation we are */
50extern int _prep_type;
51
52#endif /* CONFIG_PPC_PREP */
53
54#endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
55
56/*
57 * Default implementation of macro that returns current
58 * instruction pointer ("program counter").
59 */
60#define current_text_addr() ({ __label__ _l; _l: &&_l;})
61
62/* Macros for adjusting thread priority (hardware multi-threading) */
63#define HMT_very_low() asm volatile("or 31,31,31 # very low priority")
64#define HMT_low() asm volatile("or 1,1,1 # low priority")
65#define HMT_medium_low() asm volatile("or 6,6,6 # medium low priority")
66#define HMT_medium() asm volatile("or 2,2,2 # medium priority")
67#define HMT_medium_high() asm volatile("or 5,5,5 # medium high priority")
68#define HMT_high() asm volatile("or 3,3,3 # high priority")
69
70#ifdef __KERNEL__
71
72extern int have_of;
73
74struct task_struct;
75void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
76void release_thread(struct task_struct *);
77
78/* Prepare to copy thread state - unlazy all lazy status */
79extern void prepare_to_copy(struct task_struct *tsk);
80
81/* Create a new kernel thread. */
82extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
83
84/* Lazy FPU handling on uni-processor */
85extern struct task_struct *last_task_used_math;
86extern struct task_struct *last_task_used_altivec;
87extern struct task_struct *last_task_used_vsx;
88extern struct task_struct *last_task_used_spe;
89
90#ifdef CONFIG_PPC32
91
92#if CONFIG_TASK_SIZE > CONFIG_KERNEL_START
93#error User TASK_SIZE overlaps with KERNEL_START address
94#endif
95#define TASK_SIZE (CONFIG_TASK_SIZE)
96
97/* This decides where the kernel will search for a free chunk of vm
98 * space during mmap's.
99 */
100#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3)
101#endif
102
103#ifdef CONFIG_PPC64
104/* 64-bit user address space is 44-bits (16TB user VM) */
105#define TASK_SIZE_USER64 (0x0000100000000000UL)
106
107/*
108 * 32-bit user address space is 4GB - 1 page
109 * (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT
110 */
111#define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))
112
113#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
114 TASK_SIZE_USER32 : TASK_SIZE_USER64)
115#define TASK_SIZE TASK_SIZE_OF(current)
116
117/* This decides where the kernel will search for a free chunk of vm
118 * space during mmap's.
119 */
120#define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4))
121#define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_USER64 / 4))
122
123#define TASK_UNMAPPED_BASE ((test_thread_flag(TIF_32BIT)) ? \
124 TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
125#endif
126
127#ifdef __KERNEL__
128#ifdef __powerpc64__
129
130#define STACK_TOP_USER64 TASK_SIZE_USER64
131#define STACK_TOP_USER32 TASK_SIZE_USER32
132
133#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
134 STACK_TOP_USER32 : STACK_TOP_USER64)
135
136#define STACK_TOP_MAX STACK_TOP_USER64
137
138#else /* __powerpc64__ */
139
140#define STACK_TOP TASK_SIZE
141#define STACK_TOP_MAX STACK_TOP
142
143#endif /* __powerpc64__ */
144#endif /* __KERNEL__ */
145
146typedef struct {
147 unsigned long seg;
148} mm_segment_t;
149
150#define TS_FPROFFSET 0
151#define TS_VSRLOWOFFSET 1
152#define TS_FPR(i) fpr[i][TS_FPROFFSET]
153
154struct thread_struct {
155 unsigned long ksp; /* Kernel stack pointer */
156 unsigned long ksp_limit; /* if ksp <= ksp_limit stack overflow */
157
158#ifdef CONFIG_PPC64
159 unsigned long ksp_vsid;
160#endif
161 struct pt_regs *regs; /* Pointer to saved register state */
162 mm_segment_t fs; /* for get_fs() validation */
163#ifdef CONFIG_PPC32
164 void *pgdir; /* root of page-table tree */
165#endif
166#if defined(CONFIG_4xx) || defined (CONFIG_BOOKE)
167 unsigned long dbcr0; /* debug control register values */
168 unsigned long dbcr1;
169#endif
170 /* FP and VSX 0-31 register set */
171 double fpr[32][TS_FPRWIDTH];
172 struct {
173
174 unsigned int pad;
175 unsigned int val; /* Floating point status */
176 } fpscr;
177 int fpexc_mode; /* floating-point exception mode */
178 unsigned int align_ctl; /* alignment handling control */
179#ifdef CONFIG_PPC64
180 unsigned long start_tb; /* Start purr when proc switched in */
181 unsigned long accum_tb; /* Total accumilated purr for process */
182#endif
183 unsigned long dabr; /* Data address breakpoint register */
184#ifdef CONFIG_ALTIVEC
185 /* Complete AltiVec register set */
186 vector128 vr[32] __attribute__((aligned(16)));
187 /* AltiVec status */
188 vector128 vscr __attribute__((aligned(16)));
189 unsigned long vrsave;
190 int used_vr; /* set if process has used altivec */
191#endif /* CONFIG_ALTIVEC */
192#ifdef CONFIG_VSX
193 /* VSR status */
194 int used_vsr; /* set if process has used altivec */
195#endif /* CONFIG_VSX */
196#ifdef CONFIG_SPE
197 unsigned long evr[32]; /* upper 32-bits of SPE regs */
198 u64 acc; /* Accumulator */
199 unsigned long spefscr; /* SPE & eFP status */
200 int used_spe; /* set if process has used spe */
201#endif /* CONFIG_SPE */
202};
203
204#define ARCH_MIN_TASKALIGN 16
205
206#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
207#define INIT_SP_LIMIT \
208 (_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack)
209
210
211#ifdef CONFIG_PPC32
212#define INIT_THREAD { \
213 .ksp = INIT_SP, \
214 .ksp_limit = INIT_SP_LIMIT, \
215 .fs = KERNEL_DS, \
216 .pgdir = swapper_pg_dir, \
217 .fpexc_mode = MSR_FE0 | MSR_FE1, \
218}
219#else
220#define INIT_THREAD { \
221 .ksp = INIT_SP, \
222 .ksp_limit = INIT_SP_LIMIT, \
223 .regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \
224 .fs = KERNEL_DS, \
225 .fpr = {{0}}, \
226 .fpscr = { .val = 0, }, \
227 .fpexc_mode = 0, \
228}
229#endif
230
231/*
232 * Return saved PC of a blocked thread. For now, this is the "user" PC
233 */
234#define thread_saved_pc(tsk) \
235 ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
236
237#define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.regs)
238
239unsigned long get_wchan(struct task_struct *p);
240
241#define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
242#define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
243
244/* Get/set floating-point exception mode */
245#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
246#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
247
248extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
249extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
250
251#define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
252#define SET_ENDIAN(tsk, val) set_endian((tsk), (val))
253
254extern int get_endian(struct task_struct *tsk, unsigned long adr);
255extern int set_endian(struct task_struct *tsk, unsigned int val);
256
257#define GET_UNALIGN_CTL(tsk, adr) get_unalign_ctl((tsk), (adr))
258#define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
259
260extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
261extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
262
263static inline unsigned int __unpack_fe01(unsigned long msr_bits)
264{
265 return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
266}
267
268static inline unsigned long __pack_fe01(unsigned int fpmode)
269{
270 return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
271}
272
273#ifdef CONFIG_PPC64
274#define cpu_relax() do { HMT_low(); HMT_medium(); barrier(); } while (0)
275#else
276#define cpu_relax() barrier()
277#endif
278
279/* Check that a certain kernel stack pointer is valid in task_struct p */
280int validate_sp(unsigned long sp, struct task_struct *p,
281 unsigned long nbytes);
282
283/*
284 * Prefetch macros.
285 */
286#define ARCH_HAS_PREFETCH
287#define ARCH_HAS_PREFETCHW
288#define ARCH_HAS_SPINLOCK_PREFETCH
289
290static inline void prefetch(const void *x)
291{
292 if (unlikely(!x))
293 return;
294
295 __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
296}
297
298static inline void prefetchw(const void *x)
299{
300 if (unlikely(!x))
301 return;
302
303 __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
304}
305
306#define spin_lock_prefetch(x) prefetchw(x)
307
308#ifdef CONFIG_PPC64
309#define HAVE_ARCH_PICK_MMAP_LAYOUT
310#endif
311
312#endif /* __KERNEL__ */
313#endif /* __ASSEMBLY__ */
314#endif /* _ASM_POWERPC_PROCESSOR_H */
diff --git a/include/asm-powerpc/prom.h b/include/asm-powerpc/prom.h
deleted file mode 100644
index eb3bd2e1c7f..00000000000
--- a/include/asm-powerpc/prom.h
+++ /dev/null
@@ -1,356 +0,0 @@
1#ifndef _POWERPC_PROM_H
2#define _POWERPC_PROM_H
3#ifdef __KERNEL__
4
5/*
6 * Definitions for talking to the Open Firmware PROM on
7 * Power Macintosh computers.
8 *
9 * Copyright (C) 1996-2005 Paul Mackerras.
10 *
11 * Updates for PPC64 by Peter Bergner & David Engebretsen, IBM Corp.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
17 */
18#include <linux/types.h>
19#include <linux/proc_fs.h>
20#include <linux/platform_device.h>
21#include <asm/irq.h>
22#include <asm/atomic.h>
23
24#define OF_ROOT_NODE_ADDR_CELLS_DEFAULT 1
25#define OF_ROOT_NODE_SIZE_CELLS_DEFAULT 1
26
27#define of_compat_cmp(s1, s2, l) strcasecmp((s1), (s2))
28#define of_prop_cmp(s1, s2) strcmp((s1), (s2))
29#define of_node_cmp(s1, s2) strcasecmp((s1), (s2))
30
31/* Definitions used by the flattened device tree */
32#define OF_DT_HEADER 0xd00dfeed /* marker */
33#define OF_DT_BEGIN_NODE 0x1 /* Start of node, full name */
34#define OF_DT_END_NODE 0x2 /* End node */
35#define OF_DT_PROP 0x3 /* Property: name off, size,
36 * content */
37#define OF_DT_NOP 0x4 /* nop */
38#define OF_DT_END 0x9
39
40#define OF_DT_VERSION 0x10
41
42/*
43 * This is what gets passed to the kernel by prom_init or kexec
44 *
45 * The dt struct contains the device tree structure, full pathes and
46 * property contents. The dt strings contain a separate block with just
47 * the strings for the property names, and is fully page aligned and
48 * self contained in a page, so that it can be kept around by the kernel,
49 * each property name appears only once in this page (cheap compression)
50 *
51 * the mem_rsvmap contains a map of reserved ranges of physical memory,
52 * passing it here instead of in the device-tree itself greatly simplifies
53 * the job of everybody. It's just a list of u64 pairs (base/size) that
54 * ends when size is 0
55 */
56struct boot_param_header
57{
58 u32 magic; /* magic word OF_DT_HEADER */
59 u32 totalsize; /* total size of DT block */
60 u32 off_dt_struct; /* offset to structure */
61 u32 off_dt_strings; /* offset to strings */
62 u32 off_mem_rsvmap; /* offset to memory reserve map */
63 u32 version; /* format version */
64 u32 last_comp_version; /* last compatible version */
65 /* version 2 fields below */
66 u32 boot_cpuid_phys; /* Physical CPU id we're booting on */
67 /* version 3 fields below */
68 u32 dt_strings_size; /* size of the DT strings block */
69 /* version 17 fields below */
70 u32 dt_struct_size; /* size of the DT structure block */
71};
72
73
74
75typedef u32 phandle;
76typedef u32 ihandle;
77
78struct property {
79 char *name;
80 int length;
81 void *value;
82 struct property *next;
83};
84
85struct device_node {
86 const char *name;
87 const char *type;
88 phandle node;
89 phandle linux_phandle;
90 char *full_name;
91
92 struct property *properties;
93 struct property *deadprops; /* removed properties */
94 struct device_node *parent;
95 struct device_node *child;
96 struct device_node *sibling;
97 struct device_node *next; /* next device of same type */
98 struct device_node *allnext; /* next in list of all nodes */
99 struct proc_dir_entry *pde; /* this node's proc directory */
100 struct kref kref;
101 unsigned long _flags;
102 void *data;
103};
104
105extern struct device_node *of_chosen;
106
107static inline int of_node_check_flag(struct device_node *n, unsigned long flag)
108{
109 return test_bit(flag, &n->_flags);
110}
111
112static inline void of_node_set_flag(struct device_node *n, unsigned long flag)
113{
114 set_bit(flag, &n->_flags);
115}
116
117
118#define HAVE_ARCH_DEVTREE_FIXUPS
119
120static inline void set_node_proc_entry(struct device_node *dn, struct proc_dir_entry *de)
121{
122 dn->pde = de;
123}
124
125
126extern struct device_node *of_find_all_nodes(struct device_node *prev);
127extern struct device_node *of_node_get(struct device_node *node);
128extern void of_node_put(struct device_node *node);
129
130/* For scanning the flat device-tree at boot time */
131extern int __init of_scan_flat_dt(int (*it)(unsigned long node,
132 const char *uname, int depth,
133 void *data),
134 void *data);
135extern void* __init of_get_flat_dt_prop(unsigned long node, const char *name,
136 unsigned long *size);
137extern int __init of_flat_dt_is_compatible(unsigned long node, const char *name);
138extern unsigned long __init of_get_flat_dt_root(void);
139
140/* For updating the device tree at runtime */
141extern void of_attach_node(struct device_node *);
142extern void of_detach_node(struct device_node *);
143
144/* Other Prototypes */
145extern void finish_device_tree(void);
146extern void unflatten_device_tree(void);
147extern void early_init_devtree(void *);
148extern int machine_is_compatible(const char *compat);
149extern void print_properties(struct device_node *node);
150extern int prom_n_intr_cells(struct device_node* np);
151extern void prom_get_irq_senses(unsigned char *senses, int off, int max);
152extern int prom_add_property(struct device_node* np, struct property* prop);
153extern int prom_remove_property(struct device_node *np, struct property *prop);
154extern int prom_update_property(struct device_node *np,
155 struct property *newprop,
156 struct property *oldprop);
157
158#ifdef CONFIG_PPC32
159/*
160 * PCI <-> OF matching functions
161 * (XXX should these be here?)
162 */
163struct pci_bus;
164struct pci_dev;
165extern int pci_device_from_OF_node(struct device_node *node,
166 u8* bus, u8* devfn);
167extern struct device_node* pci_busdev_to_OF_node(struct pci_bus *, int);
168extern struct device_node* pci_device_to_OF_node(struct pci_dev *);
169extern void pci_create_OF_bus_map(void);
170#endif
171
172extern struct resource *request_OF_resource(struct device_node* node,
173 int index, const char* name_postfix);
174extern int release_OF_resource(struct device_node* node, int index);
175
176
177/*
178 * OF address retreival & translation
179 */
180
181
182/* Helper to read a big number; size is in cells (not bytes) */
183static inline u64 of_read_number(const u32 *cell, int size)
184{
185 u64 r = 0;
186 while (size--)
187 r = (r << 32) | *(cell++);
188 return r;
189}
190
191/* Like of_read_number, but we want an unsigned long result */
192#ifdef CONFIG_PPC32
193static inline unsigned long of_read_ulong(const u32 *cell, int size)
194{
195 return cell[size-1];
196}
197#else
198#define of_read_ulong(cell, size) of_read_number(cell, size)
199#endif
200
201/* Translate an OF address block into a CPU physical address
202 */
203extern u64 of_translate_address(struct device_node *np, const u32 *addr);
204
205/* Translate a DMA address from device space to CPU space */
206extern u64 of_translate_dma_address(struct device_node *dev,
207 const u32 *in_addr);
208
209/* Extract an address from a device, returns the region size and
210 * the address space flags too. The PCI version uses a BAR number
211 * instead of an absolute index
212 */
213extern const u32 *of_get_address(struct device_node *dev, int index,
214 u64 *size, unsigned int *flags);
215#ifdef CONFIG_PCI
216extern const u32 *of_get_pci_address(struct device_node *dev, int bar_no,
217 u64 *size, unsigned int *flags);
218#else
219static inline const u32 *of_get_pci_address(struct device_node *dev,
220 int bar_no, u64 *size, unsigned int *flags)
221{
222 return NULL;
223}
224#endif /* CONFIG_PCI */
225
226/* Get an address as a resource. Note that if your address is
227 * a PIO address, the conversion will fail if the physical address
228 * can't be internally converted to an IO token with
229 * pci_address_to_pio(), that is because it's either called to early
230 * or it can't be matched to any host bridge IO space
231 */
232extern int of_address_to_resource(struct device_node *dev, int index,
233 struct resource *r);
234#ifdef CONFIG_PCI
235extern int of_pci_address_to_resource(struct device_node *dev, int bar,
236 struct resource *r);
237#else
238static inline int of_pci_address_to_resource(struct device_node *dev, int bar,
239 struct resource *r)
240{
241 return -ENOSYS;
242}
243#endif /* CONFIG_PCI */
244
245/* Parse the ibm,dma-window property of an OF node into the busno, phys and
246 * size parameters.
247 */
248void of_parse_dma_window(struct device_node *dn, const void *dma_window_prop,
249 unsigned long *busno, unsigned long *phys, unsigned long *size);
250
251extern void kdump_move_device_tree(void);
252
253/* CPU OF node matching */
254struct device_node *of_get_cpu_node(int cpu, unsigned int *thread);
255
256/* Get the MAC address */
257extern const void *of_get_mac_address(struct device_node *np);
258
259/*
260 * OF interrupt mapping
261 */
262
263/* This structure is returned when an interrupt is mapped. The controller
264 * field needs to be put() after use
265 */
266
267#define OF_MAX_IRQ_SPEC 4 /* We handle specifiers of at most 4 cells */
268
269struct of_irq {
270 struct device_node *controller; /* Interrupt controller node */
271 u32 size; /* Specifier size */
272 u32 specifier[OF_MAX_IRQ_SPEC]; /* Specifier copy */
273};
274
275/**
276 * of_irq_map_init - Initialize the irq remapper
277 * @flags: flags defining workarounds to enable
278 *
279 * Some machines have bugs in the device-tree which require certain workarounds
280 * to be applied. Call this before any interrupt mapping attempts to enable
281 * those workarounds.
282 */
283#define OF_IMAP_OLDWORLD_MAC 0x00000001
284#define OF_IMAP_NO_PHANDLE 0x00000002
285
286extern void of_irq_map_init(unsigned int flags);
287
288/**
289 * of_irq_map_raw - Low level interrupt tree parsing
290 * @parent: the device interrupt parent
291 * @intspec: interrupt specifier ("interrupts" property of the device)
292 * @ointsize: size of the passed in interrupt specifier
293 * @addr: address specifier (start of "reg" property of the device)
294 * @out_irq: structure of_irq filled by this function
295 *
296 * Returns 0 on success and a negative number on error
297 *
298 * This function is a low-level interrupt tree walking function. It
299 * can be used to do a partial walk with synthetized reg and interrupts
300 * properties, for example when resolving PCI interrupts when no device
301 * node exist for the parent.
302 *
303 */
304
305extern int of_irq_map_raw(struct device_node *parent, const u32 *intspec,
306 u32 ointsize, const u32 *addr,
307 struct of_irq *out_irq);
308
309
310/**
311 * of_irq_map_one - Resolve an interrupt for a device
312 * @device: the device whose interrupt is to be resolved
313 * @index: index of the interrupt to resolve
314 * @out_irq: structure of_irq filled by this function
315 *
316 * This function resolves an interrupt, walking the tree, for a given
317 * device-tree node. It's the high level pendant to of_irq_map_raw().
318 * It also implements the workarounds for OldWolrd Macs.
319 */
320extern int of_irq_map_one(struct device_node *device, int index,
321 struct of_irq *out_irq);
322
323/**
324 * of_irq_map_pci - Resolve the interrupt for a PCI device
325 * @pdev: the device whose interrupt is to be resolved
326 * @out_irq: structure of_irq filled by this function
327 *
328 * This function resolves the PCI interrupt for a given PCI device. If a
329 * device-node exists for a given pci_dev, it will use normal OF tree
330 * walking. If not, it will implement standard swizzling and walk up the
331 * PCI tree until an device-node is found, at which point it will finish
332 * resolving using the OF tree walking.
333 */
334struct pci_dev;
335extern int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq);
336
337extern int of_irq_to_resource(struct device_node *dev, int index,
338 struct resource *r);
339
340/**
341 * of_iomap - Maps the memory mapped IO for a given device_node
342 * @device: the device whose io range will be mapped
343 * @index: index of the io range
344 *
345 * Returns a pointer to the mapped memory
346 */
347extern void __iomem *of_iomap(struct device_node *device, int index);
348
349/*
350 * NB: This is here while we transition from using asm/prom.h
351 * to linux/of.h
352 */
353#include <linux/of.h>
354
355#endif /* __KERNEL__ */
356#endif /* _POWERPC_PROM_H */
diff --git a/include/asm-powerpc/ps3.h b/include/asm-powerpc/ps3.h
deleted file mode 100644
index f9e34c493cb..00000000000
--- a/include/asm-powerpc/ps3.h
+++ /dev/null
@@ -1,519 +0,0 @@
1/*
2 * PS3 platform declarations.
3 *
4 * Copyright (C) 2006 Sony Computer Entertainment Inc.
5 * Copyright 2006 Sony Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#if !defined(_ASM_POWERPC_PS3_H)
22#define _ASM_POWERPC_PS3_H
23
24#include <linux/init.h>
25#include <linux/types.h>
26#include <linux/device.h>
27#include "cell-pmu.h"
28
29union ps3_firmware_version {
30 u64 raw;
31 struct {
32 u16 pad;
33 u16 major;
34 u16 minor;
35 u16 rev;
36 };
37};
38
39void ps3_get_firmware_version(union ps3_firmware_version *v);
40int ps3_compare_firmware_version(u16 major, u16 minor, u16 rev);
41
42/* 'Other OS' area */
43
44enum ps3_param_av_multi_out {
45 PS3_PARAM_AV_MULTI_OUT_NTSC = 0,
46 PS3_PARAM_AV_MULTI_OUT_PAL_RGB = 1,
47 PS3_PARAM_AV_MULTI_OUT_PAL_YCBCR = 2,
48 PS3_PARAM_AV_MULTI_OUT_SECAM = 3,
49};
50
51enum ps3_param_av_multi_out ps3_os_area_get_av_multi_out(void);
52
53/* dma routines */
54
55enum ps3_dma_page_size {
56 PS3_DMA_4K = 12U,
57 PS3_DMA_64K = 16U,
58 PS3_DMA_1M = 20U,
59 PS3_DMA_16M = 24U,
60};
61
62enum ps3_dma_region_type {
63 PS3_DMA_OTHER = 0,
64 PS3_DMA_INTERNAL = 2,
65};
66
67struct ps3_dma_region_ops;
68
69/**
70 * struct ps3_dma_region - A per device dma state variables structure
71 * @did: The HV device id.
72 * @page_size: The ioc pagesize.
73 * @region_type: The HV region type.
74 * @bus_addr: The 'translated' bus address of the region.
75 * @len: The length in bytes of the region.
76 * @offset: The offset from the start of memory of the region.
77 * @ioid: The IOID of the device who owns this region
78 * @chunk_list: Opaque variable used by the ioc page manager.
79 * @region_ops: struct ps3_dma_region_ops - dma region operations
80 */
81
82struct ps3_dma_region {
83 struct ps3_system_bus_device *dev;
84 /* device variables */
85 const struct ps3_dma_region_ops *region_ops;
86 unsigned char ioid;
87 enum ps3_dma_page_size page_size;
88 enum ps3_dma_region_type region_type;
89 unsigned long len;
90 unsigned long offset;
91
92 /* driver variables (set by ps3_dma_region_create) */
93 unsigned long bus_addr;
94 struct {
95 spinlock_t lock;
96 struct list_head head;
97 } chunk_list;
98};
99
100struct ps3_dma_region_ops {
101 int (*create)(struct ps3_dma_region *);
102 int (*free)(struct ps3_dma_region *);
103 int (*map)(struct ps3_dma_region *,
104 unsigned long virt_addr,
105 unsigned long len,
106 unsigned long *bus_addr,
107 u64 iopte_pp);
108 int (*unmap)(struct ps3_dma_region *,
109 unsigned long bus_addr,
110 unsigned long len);
111};
112/**
113 * struct ps3_dma_region_init - Helper to initialize structure variables
114 *
115 * Helper to properly initialize variables prior to calling
116 * ps3_system_bus_device_register.
117 */
118
119struct ps3_system_bus_device;
120
121int ps3_dma_region_init(struct ps3_system_bus_device *dev,
122 struct ps3_dma_region *r, enum ps3_dma_page_size page_size,
123 enum ps3_dma_region_type region_type, void *addr, unsigned long len);
124int ps3_dma_region_create(struct ps3_dma_region *r);
125int ps3_dma_region_free(struct ps3_dma_region *r);
126int ps3_dma_map(struct ps3_dma_region *r, unsigned long virt_addr,
127 unsigned long len, unsigned long *bus_addr,
128 u64 iopte_pp);
129int ps3_dma_unmap(struct ps3_dma_region *r, unsigned long bus_addr,
130 unsigned long len);
131
132/* mmio routines */
133
134enum ps3_mmio_page_size {
135 PS3_MMIO_4K = 12U,
136 PS3_MMIO_64K = 16U
137};
138
139struct ps3_mmio_region_ops;
140/**
141 * struct ps3_mmio_region - a per device mmio state variables structure
142 *
143 * Current systems can be supported with a single region per device.
144 */
145
146struct ps3_mmio_region {
147 struct ps3_system_bus_device *dev;
148 const struct ps3_mmio_region_ops *mmio_ops;
149 unsigned long bus_addr;
150 unsigned long len;
151 enum ps3_mmio_page_size page_size;
152 unsigned long lpar_addr;
153};
154
155struct ps3_mmio_region_ops {
156 int (*create)(struct ps3_mmio_region *);
157 int (*free)(struct ps3_mmio_region *);
158};
159/**
160 * struct ps3_mmio_region_init - Helper to initialize structure variables
161 *
162 * Helper to properly initialize variables prior to calling
163 * ps3_system_bus_device_register.
164 */
165
166int ps3_mmio_region_init(struct ps3_system_bus_device *dev,
167 struct ps3_mmio_region *r, unsigned long bus_addr, unsigned long len,
168 enum ps3_mmio_page_size page_size);
169int ps3_mmio_region_create(struct ps3_mmio_region *r);
170int ps3_free_mmio_region(struct ps3_mmio_region *r);
171unsigned long ps3_mm_phys_to_lpar(unsigned long phys_addr);
172
173/* inrerrupt routines */
174
175enum ps3_cpu_binding {
176 PS3_BINDING_CPU_ANY = -1,
177 PS3_BINDING_CPU_0 = 0,
178 PS3_BINDING_CPU_1 = 1,
179};
180
181int ps3_irq_plug_setup(enum ps3_cpu_binding cpu, unsigned long outlet,
182 unsigned int *virq);
183int ps3_irq_plug_destroy(unsigned int virq);
184int ps3_event_receive_port_setup(enum ps3_cpu_binding cpu, unsigned int *virq);
185int ps3_event_receive_port_destroy(unsigned int virq);
186int ps3_send_event_locally(unsigned int virq);
187
188int ps3_io_irq_setup(enum ps3_cpu_binding cpu, unsigned int interrupt_id,
189 unsigned int *virq);
190int ps3_io_irq_destroy(unsigned int virq);
191int ps3_vuart_irq_setup(enum ps3_cpu_binding cpu, void* virt_addr_bmp,
192 unsigned int *virq);
193int ps3_vuart_irq_destroy(unsigned int virq);
194int ps3_spe_irq_setup(enum ps3_cpu_binding cpu, unsigned long spe_id,
195 unsigned int class, unsigned int *virq);
196int ps3_spe_irq_destroy(unsigned int virq);
197
198int ps3_sb_event_receive_port_setup(struct ps3_system_bus_device *dev,
199 enum ps3_cpu_binding cpu, unsigned int *virq);
200int ps3_sb_event_receive_port_destroy(struct ps3_system_bus_device *dev,
201 unsigned int virq);
202
203/* lv1 result codes */
204
205enum lv1_result {
206 LV1_SUCCESS = 0,
207 /* not used -1 */
208 LV1_RESOURCE_SHORTAGE = -2,
209 LV1_NO_PRIVILEGE = -3,
210 LV1_DENIED_BY_POLICY = -4,
211 LV1_ACCESS_VIOLATION = -5,
212 LV1_NO_ENTRY = -6,
213 LV1_DUPLICATE_ENTRY = -7,
214 LV1_TYPE_MISMATCH = -8,
215 LV1_BUSY = -9,
216 LV1_EMPTY = -10,
217 LV1_WRONG_STATE = -11,
218 /* not used -12 */
219 LV1_NO_MATCH = -13,
220 LV1_ALREADY_CONNECTED = -14,
221 LV1_UNSUPPORTED_PARAMETER_VALUE = -15,
222 LV1_CONDITION_NOT_SATISFIED = -16,
223 LV1_ILLEGAL_PARAMETER_VALUE = -17,
224 LV1_BAD_OPTION = -18,
225 LV1_IMPLEMENTATION_LIMITATION = -19,
226 LV1_NOT_IMPLEMENTED = -20,
227 LV1_INVALID_CLASS_ID = -21,
228 LV1_CONSTRAINT_NOT_SATISFIED = -22,
229 LV1_ALIGNMENT_ERROR = -23,
230 LV1_HARDWARE_ERROR = -24,
231 LV1_INVALID_DATA_FORMAT = -25,
232 LV1_INVALID_OPERATION = -26,
233 LV1_INTERNAL_ERROR = -32768,
234};
235
236static inline const char* ps3_result(int result)
237{
238#if defined(DEBUG)
239 switch (result) {
240 case LV1_SUCCESS:
241 return "LV1_SUCCESS (0)";
242 case -1:
243 return "** unknown result ** (-1)";
244 case LV1_RESOURCE_SHORTAGE:
245 return "LV1_RESOURCE_SHORTAGE (-2)";
246 case LV1_NO_PRIVILEGE:
247 return "LV1_NO_PRIVILEGE (-3)";
248 case LV1_DENIED_BY_POLICY:
249 return "LV1_DENIED_BY_POLICY (-4)";
250 case LV1_ACCESS_VIOLATION:
251 return "LV1_ACCESS_VIOLATION (-5)";
252 case LV1_NO_ENTRY:
253 return "LV1_NO_ENTRY (-6)";
254 case LV1_DUPLICATE_ENTRY:
255 return "LV1_DUPLICATE_ENTRY (-7)";
256 case LV1_TYPE_MISMATCH:
257 return "LV1_TYPE_MISMATCH (-8)";
258 case LV1_BUSY:
259 return "LV1_BUSY (-9)";
260 case LV1_EMPTY:
261 return "LV1_EMPTY (-10)";
262 case LV1_WRONG_STATE:
263 return "LV1_WRONG_STATE (-11)";
264 case -12:
265 return "** unknown result ** (-12)";
266 case LV1_NO_MATCH:
267 return "LV1_NO_MATCH (-13)";
268 case LV1_ALREADY_CONNECTED:
269 return "LV1_ALREADY_CONNECTED (-14)";
270 case LV1_UNSUPPORTED_PARAMETER_VALUE:
271 return "LV1_UNSUPPORTED_PARAMETER_VALUE (-15)";
272 case LV1_CONDITION_NOT_SATISFIED:
273 return "LV1_CONDITION_NOT_SATISFIED (-16)";
274 case LV1_ILLEGAL_PARAMETER_VALUE:
275 return "LV1_ILLEGAL_PARAMETER_VALUE (-17)";
276 case LV1_BAD_OPTION:
277 return "LV1_BAD_OPTION (-18)";
278 case LV1_IMPLEMENTATION_LIMITATION:
279 return "LV1_IMPLEMENTATION_LIMITATION (-19)";
280 case LV1_NOT_IMPLEMENTED:
281 return "LV1_NOT_IMPLEMENTED (-20)";
282 case LV1_INVALID_CLASS_ID:
283 return "LV1_INVALID_CLASS_ID (-21)";
284 case LV1_CONSTRAINT_NOT_SATISFIED:
285 return "LV1_CONSTRAINT_NOT_SATISFIED (-22)";
286 case LV1_ALIGNMENT_ERROR:
287 return "LV1_ALIGNMENT_ERROR (-23)";
288 case LV1_HARDWARE_ERROR:
289 return "LV1_HARDWARE_ERROR (-24)";
290 case LV1_INVALID_DATA_FORMAT:
291 return "LV1_INVALID_DATA_FORMAT (-25)";
292 case LV1_INVALID_OPERATION:
293 return "LV1_INVALID_OPERATION (-26)";
294 case LV1_INTERNAL_ERROR:
295 return "LV1_INTERNAL_ERROR (-32768)";
296 default:
297 BUG();
298 return "** unknown result **";
299 };
300#else
301 return "";
302#endif
303}
304
305/* system bus routines */
306
307enum ps3_match_id {
308 PS3_MATCH_ID_EHCI = 1,
309 PS3_MATCH_ID_OHCI = 2,
310 PS3_MATCH_ID_GELIC = 3,
311 PS3_MATCH_ID_AV_SETTINGS = 4,
312 PS3_MATCH_ID_SYSTEM_MANAGER = 5,
313 PS3_MATCH_ID_STOR_DISK = 6,
314 PS3_MATCH_ID_STOR_ROM = 7,
315 PS3_MATCH_ID_STOR_FLASH = 8,
316 PS3_MATCH_ID_SOUND = 9,
317 PS3_MATCH_ID_GRAPHICS = 10,
318 PS3_MATCH_ID_LPM = 11,
319};
320
321#define PS3_MODULE_ALIAS_EHCI "ps3:1"
322#define PS3_MODULE_ALIAS_OHCI "ps3:2"
323#define PS3_MODULE_ALIAS_GELIC "ps3:3"
324#define PS3_MODULE_ALIAS_AV_SETTINGS "ps3:4"
325#define PS3_MODULE_ALIAS_SYSTEM_MANAGER "ps3:5"
326#define PS3_MODULE_ALIAS_STOR_DISK "ps3:6"
327#define PS3_MODULE_ALIAS_STOR_ROM "ps3:7"
328#define PS3_MODULE_ALIAS_STOR_FLASH "ps3:8"
329#define PS3_MODULE_ALIAS_SOUND "ps3:9"
330#define PS3_MODULE_ALIAS_GRAPHICS "ps3:10"
331#define PS3_MODULE_ALIAS_LPM "ps3:11"
332
333enum ps3_system_bus_device_type {
334 PS3_DEVICE_TYPE_IOC0 = 1,
335 PS3_DEVICE_TYPE_SB,
336 PS3_DEVICE_TYPE_VUART,
337 PS3_DEVICE_TYPE_LPM,
338};
339
340enum ps3_match_sub_id {
341 /* for PS3_MATCH_ID_GRAPHICS */
342 PS3_MATCH_SUB_ID_FB = 1,
343};
344
345/**
346 * struct ps3_system_bus_device - a device on the system bus
347 */
348
349struct ps3_system_bus_device {
350 enum ps3_match_id match_id;
351 enum ps3_match_sub_id match_sub_id;
352 enum ps3_system_bus_device_type dev_type;
353
354 u64 bus_id; /* SB */
355 u64 dev_id; /* SB */
356 unsigned int interrupt_id; /* SB */
357 struct ps3_dma_region *d_region; /* SB, IOC0 */
358 struct ps3_mmio_region *m_region; /* SB, IOC0*/
359 unsigned int port_number; /* VUART */
360 struct { /* LPM */
361 u64 node_id;
362 u64 pu_id;
363 u64 rights;
364 } lpm;
365
366/* struct iommu_table *iommu_table; -- waiting for BenH's cleanups */
367 struct device core;
368 void *driver_priv; /* private driver variables */
369};
370
371int ps3_open_hv_device(struct ps3_system_bus_device *dev);
372int ps3_close_hv_device(struct ps3_system_bus_device *dev);
373
374/**
375 * struct ps3_system_bus_driver - a driver for a device on the system bus
376 */
377
378struct ps3_system_bus_driver {
379 enum ps3_match_id match_id;
380 enum ps3_match_sub_id match_sub_id;
381 struct device_driver core;
382 int (*probe)(struct ps3_system_bus_device *);
383 int (*remove)(struct ps3_system_bus_device *);
384 int (*shutdown)(struct ps3_system_bus_device *);
385/* int (*suspend)(struct ps3_system_bus_device *, pm_message_t); */
386/* int (*resume)(struct ps3_system_bus_device *); */
387};
388
389int ps3_system_bus_device_register(struct ps3_system_bus_device *dev);
390int ps3_system_bus_driver_register(struct ps3_system_bus_driver *drv);
391void ps3_system_bus_driver_unregister(struct ps3_system_bus_driver *drv);
392
393static inline struct ps3_system_bus_driver *ps3_drv_to_system_bus_drv(
394 struct device_driver *_drv)
395{
396 return container_of(_drv, struct ps3_system_bus_driver, core);
397}
398static inline struct ps3_system_bus_device *ps3_dev_to_system_bus_dev(
399 struct device *_dev)
400{
401 return container_of(_dev, struct ps3_system_bus_device, core);
402}
403static inline struct ps3_system_bus_driver *
404 ps3_system_bus_dev_to_system_bus_drv(struct ps3_system_bus_device *_dev)
405{
406 BUG_ON(!_dev);
407 BUG_ON(!_dev->core.driver);
408 return ps3_drv_to_system_bus_drv(_dev->core.driver);
409}
410
411/**
412 * ps3_system_bus_set_drvdata -
413 * @dev: device structure
414 * @data: Data to set
415 */
416
417static inline void ps3_system_bus_set_driver_data(
418 struct ps3_system_bus_device *dev, void *data)
419{
420 dev->core.driver_data = data;
421}
422static inline void *ps3_system_bus_get_driver_data(
423 struct ps3_system_bus_device *dev)
424{
425 return dev->core.driver_data;
426}
427
428/* These two need global scope for get_dma_ops(). */
429
430extern struct bus_type ps3_system_bus_type;
431
432/* system manager */
433
434struct ps3_sys_manager_ops {
435 struct ps3_system_bus_device *dev;
436 void (*power_off)(struct ps3_system_bus_device *dev);
437 void (*restart)(struct ps3_system_bus_device *dev);
438};
439
440void ps3_sys_manager_register_ops(const struct ps3_sys_manager_ops *ops);
441void __noreturn ps3_sys_manager_power_off(void);
442void __noreturn ps3_sys_manager_restart(void);
443void __noreturn ps3_sys_manager_halt(void);
444int ps3_sys_manager_get_wol(void);
445void ps3_sys_manager_set_wol(int state);
446
447struct ps3_prealloc {
448 const char *name;
449 void *address;
450 unsigned long size;
451 unsigned long align;
452};
453
454extern struct ps3_prealloc ps3fb_videomemory;
455extern struct ps3_prealloc ps3flash_bounce_buffer;
456
457/* logical performance monitor */
458
459/**
460 * enum ps3_lpm_rights - Rigths granted by the system policy module.
461 *
462 * @PS3_LPM_RIGHTS_USE_LPM: The right to use the lpm.
463 * @PS3_LPM_RIGHTS_USE_TB: The right to use the internal trace buffer.
464 */
465
466enum ps3_lpm_rights {
467 PS3_LPM_RIGHTS_USE_LPM = 0x001,
468 PS3_LPM_RIGHTS_USE_TB = 0x100,
469};
470
471/**
472 * enum ps3_lpm_tb_type - Type of trace buffer lv1 should use.
473 *
474 * @PS3_LPM_TB_TYPE_NONE: Do not use a trace buffer.
475 * @PS3_LPM_RIGHTS_USE_TB: Use the lv1 internal trace buffer. Must have
476 * rights @PS3_LPM_RIGHTS_USE_TB.
477 */
478
479enum ps3_lpm_tb_type {
480 PS3_LPM_TB_TYPE_NONE = 0,
481 PS3_LPM_TB_TYPE_INTERNAL = 1,
482};
483
484int ps3_lpm_open(enum ps3_lpm_tb_type tb_type, void *tb_cache,
485 u64 tb_cache_size);
486int ps3_lpm_close(void);
487int ps3_lpm_copy_tb(unsigned long offset, void *buf, unsigned long count,
488 unsigned long *bytes_copied);
489int ps3_lpm_copy_tb_to_user(unsigned long offset, void __user *buf,
490 unsigned long count, unsigned long *bytes_copied);
491void ps3_set_bookmark(u64 bookmark);
492void ps3_set_pm_bookmark(u64 tag, u64 incident, u64 th_id);
493int ps3_set_signal(u64 rtas_signal_group, u8 signal_bit, u16 sub_unit,
494 u8 bus_word);
495
496u32 ps3_read_phys_ctr(u32 cpu, u32 phys_ctr);
497void ps3_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val);
498u32 ps3_read_ctr(u32 cpu, u32 ctr);
499void ps3_write_ctr(u32 cpu, u32 ctr, u32 val);
500
501u32 ps3_read_pm07_control(u32 cpu, u32 ctr);
502void ps3_write_pm07_control(u32 cpu, u32 ctr, u32 val);
503u32 ps3_read_pm(u32 cpu, enum pm_reg_name reg);
504void ps3_write_pm(u32 cpu, enum pm_reg_name reg, u32 val);
505
506u32 ps3_get_ctr_size(u32 cpu, u32 phys_ctr);
507void ps3_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size);
508
509void ps3_enable_pm(u32 cpu);
510void ps3_disable_pm(u32 cpu);
511void ps3_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask);
512void ps3_disable_pm_interrupts(u32 cpu);
513
514u32 ps3_get_and_clear_pm_interrupts(u32 cpu);
515void ps3_sync_irq(int node);
516u32 ps3_get_hw_thread_id(int cpu);
517u64 ps3_get_spe_id(void *arg);
518
519#endif
diff --git a/include/asm-powerpc/ps3av.h b/include/asm-powerpc/ps3av.h
deleted file mode 100644
index fda98715cd3..00000000000
--- a/include/asm-powerpc/ps3av.h
+++ /dev/null
@@ -1,744 +0,0 @@
1/*
2 * PS3 AV backend support.
3 *
4 * Copyright (C) 2007 Sony Computer Entertainment Inc.
5 * Copyright 2007 Sony Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef _ASM_POWERPC_PS3AV_H_
22#define _ASM_POWERPC_PS3AV_H_
23
24/** command for ioctl() **/
25#define PS3AV_VERSION 0x205 /* version of ps3av command */
26
27#define PS3AV_CID_AV_INIT 0x00000001
28#define PS3AV_CID_AV_FIN 0x00000002
29#define PS3AV_CID_AV_GET_HW_CONF 0x00000003
30#define PS3AV_CID_AV_GET_MONITOR_INFO 0x00000004
31#define PS3AV_CID_AV_ENABLE_EVENT 0x00000006
32#define PS3AV_CID_AV_DISABLE_EVENT 0x00000007
33#define PS3AV_CID_AV_TV_MUTE 0x0000000a
34
35#define PS3AV_CID_AV_VIDEO_CS 0x00010001
36#define PS3AV_CID_AV_VIDEO_MUTE 0x00010002
37#define PS3AV_CID_AV_VIDEO_DISABLE_SIG 0x00010003
38#define PS3AV_CID_AV_AUDIO_PARAM 0x00020001
39#define PS3AV_CID_AV_AUDIO_MUTE 0x00020002
40#define PS3AV_CID_AV_HDMI_MODE 0x00040001
41
42#define PS3AV_CID_VIDEO_INIT 0x01000001
43#define PS3AV_CID_VIDEO_MODE 0x01000002
44#define PS3AV_CID_VIDEO_FORMAT 0x01000004
45#define PS3AV_CID_VIDEO_PITCH 0x01000005
46
47#define PS3AV_CID_AUDIO_INIT 0x02000001
48#define PS3AV_CID_AUDIO_MODE 0x02000002
49#define PS3AV_CID_AUDIO_MUTE 0x02000003
50#define PS3AV_CID_AUDIO_ACTIVE 0x02000004
51#define PS3AV_CID_AUDIO_INACTIVE 0x02000005
52#define PS3AV_CID_AUDIO_SPDIF_BIT 0x02000006
53#define PS3AV_CID_AUDIO_CTRL 0x02000007
54
55#define PS3AV_CID_EVENT_UNPLUGGED 0x10000001
56#define PS3AV_CID_EVENT_PLUGGED 0x10000002
57#define PS3AV_CID_EVENT_HDCP_DONE 0x10000003
58#define PS3AV_CID_EVENT_HDCP_FAIL 0x10000004
59#define PS3AV_CID_EVENT_HDCP_AUTH 0x10000005
60#define PS3AV_CID_EVENT_HDCP_ERROR 0x10000006
61
62#define PS3AV_CID_AVB_PARAM 0x04000001
63
64/* max backend ports */
65#define PS3AV_HDMI_MAX 2 /* HDMI_0 HDMI_1 */
66#define PS3AV_AVMULTI_MAX 1 /* AVMULTI_0 */
67#define PS3AV_AV_PORT_MAX (PS3AV_HDMI_MAX + PS3AV_AVMULTI_MAX)
68#define PS3AV_OPT_PORT_MAX 1 /* SPDIF0 */
69#define PS3AV_HEAD_MAX 2 /* HEAD_A HEAD_B */
70
71/* num of pkt for PS3AV_CID_AVB_PARAM */
72#define PS3AV_AVB_NUM_VIDEO PS3AV_HEAD_MAX
73#define PS3AV_AVB_NUM_AUDIO 0 /* not supported */
74#define PS3AV_AVB_NUM_AV_VIDEO PS3AV_AV_PORT_MAX
75#define PS3AV_AVB_NUM_AV_AUDIO PS3AV_HDMI_MAX
76
77#define PS3AV_MUTE_PORT_MAX 1 /* num of ports in mute pkt */
78
79/* event_bit */
80#define PS3AV_CMD_EVENT_BIT_UNPLUGGED (1 << 0)
81#define PS3AV_CMD_EVENT_BIT_PLUGGED (1 << 1)
82#define PS3AV_CMD_EVENT_BIT_HDCP_DONE (1 << 2)
83#define PS3AV_CMD_EVENT_BIT_HDCP_FAIL (1 << 3)
84#define PS3AV_CMD_EVENT_BIT_HDCP_REAUTH (1 << 4)
85#define PS3AV_CMD_EVENT_BIT_HDCP_TOPOLOGY (1 << 5)
86
87/* common params */
88/* mute */
89#define PS3AV_CMD_MUTE_OFF 0x0000
90#define PS3AV_CMD_MUTE_ON 0x0001
91/* avport */
92#define PS3AV_CMD_AVPORT_HDMI_0 0x0000
93#define PS3AV_CMD_AVPORT_HDMI_1 0x0001
94#define PS3AV_CMD_AVPORT_AVMULTI_0 0x0010
95#define PS3AV_CMD_AVPORT_SPDIF_0 0x0020
96#define PS3AV_CMD_AVPORT_SPDIF_1 0x0021
97
98/* for av backend */
99/* av_mclk */
100#define PS3AV_CMD_AV_MCLK_128 0x0000
101#define PS3AV_CMD_AV_MCLK_256 0x0001
102#define PS3AV_CMD_AV_MCLK_512 0x0003
103/* av_inputlen */
104#define PS3AV_CMD_AV_INPUTLEN_16 0x02
105#define PS3AV_CMD_AV_INPUTLEN_20 0x0a
106#define PS3AV_CMD_AV_INPUTLEN_24 0x0b
107/* alayout */
108#define PS3AV_CMD_AV_LAYOUT_32 (1 << 0)
109#define PS3AV_CMD_AV_LAYOUT_44 (1 << 1)
110#define PS3AV_CMD_AV_LAYOUT_48 (1 << 2)
111#define PS3AV_CMD_AV_LAYOUT_88 (1 << 3)
112#define PS3AV_CMD_AV_LAYOUT_96 (1 << 4)
113#define PS3AV_CMD_AV_LAYOUT_176 (1 << 5)
114#define PS3AV_CMD_AV_LAYOUT_192 (1 << 6)
115/* hdmi_mode */
116#define PS3AV_CMD_AV_HDMI_MODE_NORMAL 0xff
117#define PS3AV_CMD_AV_HDMI_HDCP_OFF 0x01
118#define PS3AV_CMD_AV_HDMI_EDID_PASS 0x80
119#define PS3AV_CMD_AV_HDMI_DVI 0x40
120
121/* for video module */
122/* video_head */
123#define PS3AV_CMD_VIDEO_HEAD_A 0x0000
124#define PS3AV_CMD_VIDEO_HEAD_B 0x0001
125/* video_cs_out video_cs_in */
126#define PS3AV_CMD_VIDEO_CS_NONE 0x0000
127#define PS3AV_CMD_VIDEO_CS_RGB_8 0x0001
128#define PS3AV_CMD_VIDEO_CS_YUV444_8 0x0002
129#define PS3AV_CMD_VIDEO_CS_YUV422_8 0x0003
130#define PS3AV_CMD_VIDEO_CS_XVYCC_8 0x0004
131#define PS3AV_CMD_VIDEO_CS_RGB_10 0x0005
132#define PS3AV_CMD_VIDEO_CS_YUV444_10 0x0006
133#define PS3AV_CMD_VIDEO_CS_YUV422_10 0x0007
134#define PS3AV_CMD_VIDEO_CS_XVYCC_10 0x0008
135#define PS3AV_CMD_VIDEO_CS_RGB_12 0x0009
136#define PS3AV_CMD_VIDEO_CS_YUV444_12 0x000a
137#define PS3AV_CMD_VIDEO_CS_YUV422_12 0x000b
138#define PS3AV_CMD_VIDEO_CS_XVYCC_12 0x000c
139/* video_vid */
140#define PS3AV_CMD_VIDEO_VID_NONE 0x0000
141#define PS3AV_CMD_VIDEO_VID_480I 0x0001
142#define PS3AV_CMD_VIDEO_VID_576I 0x0003
143#define PS3AV_CMD_VIDEO_VID_480P 0x0005
144#define PS3AV_CMD_VIDEO_VID_576P 0x0006
145#define PS3AV_CMD_VIDEO_VID_1080I_60HZ 0x0007
146#define PS3AV_CMD_VIDEO_VID_1080I_50HZ 0x0008
147#define PS3AV_CMD_VIDEO_VID_720P_60HZ 0x0009
148#define PS3AV_CMD_VIDEO_VID_720P_50HZ 0x000a
149#define PS3AV_CMD_VIDEO_VID_1080P_60HZ 0x000b
150#define PS3AV_CMD_VIDEO_VID_1080P_50HZ 0x000c
151#define PS3AV_CMD_VIDEO_VID_WXGA 0x000d
152#define PS3AV_CMD_VIDEO_VID_SXGA 0x000e
153#define PS3AV_CMD_VIDEO_VID_WUXGA 0x000f
154#define PS3AV_CMD_VIDEO_VID_480I_A 0x0010
155/* video_format */
156#define PS3AV_CMD_VIDEO_FORMAT_BLACK 0x0000
157#define PS3AV_CMD_VIDEO_FORMAT_ARGB_8BIT 0x0007
158/* video_order */
159#define PS3AV_CMD_VIDEO_ORDER_RGB 0x0000
160#define PS3AV_CMD_VIDEO_ORDER_BGR 0x0001
161/* video_fmt */
162#define PS3AV_CMD_VIDEO_FMT_X8R8G8B8 0x0000
163/* video_out_format */
164#define PS3AV_CMD_VIDEO_OUT_FORMAT_RGB_12BIT 0x0000
165/* video_cl_cnv */
166#define PS3AV_CMD_VIDEO_CL_CNV_ENABLE_LUT 0x0000
167#define PS3AV_CMD_VIDEO_CL_CNV_DISABLE_LUT 0x0010
168/* video_sync */
169#define PS3AV_CMD_VIDEO_SYNC_VSYNC 0x0001
170#define PS3AV_CMD_VIDEO_SYNC_CSYNC 0x0004
171#define PS3AV_CMD_VIDEO_SYNC_HSYNC 0x0010
172
173/* for audio module */
174/* num_of_ch */
175#define PS3AV_CMD_AUDIO_NUM_OF_CH_2 0x0000
176#define PS3AV_CMD_AUDIO_NUM_OF_CH_3 0x0001
177#define PS3AV_CMD_AUDIO_NUM_OF_CH_4 0x0002
178#define PS3AV_CMD_AUDIO_NUM_OF_CH_5 0x0003
179#define PS3AV_CMD_AUDIO_NUM_OF_CH_6 0x0004
180#define PS3AV_CMD_AUDIO_NUM_OF_CH_7 0x0005
181#define PS3AV_CMD_AUDIO_NUM_OF_CH_8 0x0006
182/* audio_fs */
183#define PS3AV_CMD_AUDIO_FS_32K 0x0001
184#define PS3AV_CMD_AUDIO_FS_44K 0x0002
185#define PS3AV_CMD_AUDIO_FS_48K 0x0003
186#define PS3AV_CMD_AUDIO_FS_88K 0x0004
187#define PS3AV_CMD_AUDIO_FS_96K 0x0005
188#define PS3AV_CMD_AUDIO_FS_176K 0x0006
189#define PS3AV_CMD_AUDIO_FS_192K 0x0007
190/* audio_word_bits */
191#define PS3AV_CMD_AUDIO_WORD_BITS_16 0x0001
192#define PS3AV_CMD_AUDIO_WORD_BITS_20 0x0002
193#define PS3AV_CMD_AUDIO_WORD_BITS_24 0x0003
194/* audio_format */
195#define PS3AV_CMD_AUDIO_FORMAT_PCM 0x0001
196#define PS3AV_CMD_AUDIO_FORMAT_BITSTREAM 0x00ff
197/* audio_source */
198#define PS3AV_CMD_AUDIO_SOURCE_SERIAL 0x0000
199#define PS3AV_CMD_AUDIO_SOURCE_SPDIF 0x0001
200/* audio_swap */
201#define PS3AV_CMD_AUDIO_SWAP_0 0x0000
202#define PS3AV_CMD_AUDIO_SWAP_1 0x0000
203/* audio_map */
204#define PS3AV_CMD_AUDIO_MAP_OUTPUT_0 0x0000
205#define PS3AV_CMD_AUDIO_MAP_OUTPUT_1 0x0001
206#define PS3AV_CMD_AUDIO_MAP_OUTPUT_2 0x0002
207#define PS3AV_CMD_AUDIO_MAP_OUTPUT_3 0x0003
208/* audio_layout */
209#define PS3AV_CMD_AUDIO_LAYOUT_2CH 0x0000
210#define PS3AV_CMD_AUDIO_LAYOUT_6CH 0x000b /* LREClr */
211#define PS3AV_CMD_AUDIO_LAYOUT_8CH 0x001f /* LREClrXY */
212/* audio_downmix */
213#define PS3AV_CMD_AUDIO_DOWNMIX_PERMITTED 0x0000
214#define PS3AV_CMD_AUDIO_DOWNMIX_PROHIBITED 0x0001
215
216/* audio_port */
217#define PS3AV_CMD_AUDIO_PORT_HDMI_0 ( 1 << 0 )
218#define PS3AV_CMD_AUDIO_PORT_HDMI_1 ( 1 << 1 )
219#define PS3AV_CMD_AUDIO_PORT_AVMULTI_0 ( 1 << 10 )
220#define PS3AV_CMD_AUDIO_PORT_SPDIF_0 ( 1 << 20 )
221#define PS3AV_CMD_AUDIO_PORT_SPDIF_1 ( 1 << 21 )
222
223/* audio_ctrl_id */
224#define PS3AV_CMD_AUDIO_CTRL_ID_DAC_RESET 0x0000
225#define PS3AV_CMD_AUDIO_CTRL_ID_DAC_DE_EMPHASIS 0x0001
226#define PS3AV_CMD_AUDIO_CTRL_ID_AVCLK 0x0002
227/* audio_ctrl_data[0] reset */
228#define PS3AV_CMD_AUDIO_CTRL_RESET_NEGATE 0x0000
229#define PS3AV_CMD_AUDIO_CTRL_RESET_ASSERT 0x0001
230/* audio_ctrl_data[0] de-emphasis */
231#define PS3AV_CMD_AUDIO_CTRL_DE_EMPHASIS_OFF 0x0000
232#define PS3AV_CMD_AUDIO_CTRL_DE_EMPHASIS_ON 0x0001
233/* audio_ctrl_data[0] avclk */
234#define PS3AV_CMD_AUDIO_CTRL_AVCLK_22 0x0000
235#define PS3AV_CMD_AUDIO_CTRL_AVCLK_18 0x0001
236
237/* av_vid */
238/* do not use these params directly, use vid_video2av */
239#define PS3AV_CMD_AV_VID_480I 0x0000
240#define PS3AV_CMD_AV_VID_480P 0x0001
241#define PS3AV_CMD_AV_VID_720P_60HZ 0x0002
242#define PS3AV_CMD_AV_VID_1080I_60HZ 0x0003
243#define PS3AV_CMD_AV_VID_1080P_60HZ 0x0004
244#define PS3AV_CMD_AV_VID_576I 0x0005
245#define PS3AV_CMD_AV_VID_576P 0x0006
246#define PS3AV_CMD_AV_VID_720P_50HZ 0x0007
247#define PS3AV_CMD_AV_VID_1080I_50HZ 0x0008
248#define PS3AV_CMD_AV_VID_1080P_50HZ 0x0009
249#define PS3AV_CMD_AV_VID_WXGA 0x000a
250#define PS3AV_CMD_AV_VID_SXGA 0x000b
251#define PS3AV_CMD_AV_VID_WUXGA 0x000c
252/* av_cs_out av_cs_in */
253/* use cs_video2av() */
254#define PS3AV_CMD_AV_CS_RGB_8 0x0000
255#define PS3AV_CMD_AV_CS_YUV444_8 0x0001
256#define PS3AV_CMD_AV_CS_YUV422_8 0x0002
257#define PS3AV_CMD_AV_CS_XVYCC_8 0x0003
258#define PS3AV_CMD_AV_CS_RGB_10 0x0004
259#define PS3AV_CMD_AV_CS_YUV444_10 0x0005
260#define PS3AV_CMD_AV_CS_YUV422_10 0x0006
261#define PS3AV_CMD_AV_CS_XVYCC_10 0x0007
262#define PS3AV_CMD_AV_CS_RGB_12 0x0008
263#define PS3AV_CMD_AV_CS_YUV444_12 0x0009
264#define PS3AV_CMD_AV_CS_YUV422_12 0x000a
265#define PS3AV_CMD_AV_CS_XVYCC_12 0x000b
266#define PS3AV_CMD_AV_CS_8 0x0000
267#define PS3AV_CMD_AV_CS_10 0x0001
268#define PS3AV_CMD_AV_CS_12 0x0002
269/* dither */
270#define PS3AV_CMD_AV_DITHER_OFF 0x0000
271#define PS3AV_CMD_AV_DITHER_ON 0x0001
272#define PS3AV_CMD_AV_DITHER_8BIT 0x0000
273#define PS3AV_CMD_AV_DITHER_10BIT 0x0002
274#define PS3AV_CMD_AV_DITHER_12BIT 0x0004
275/* super_white */
276#define PS3AV_CMD_AV_SUPER_WHITE_OFF 0x0000
277#define PS3AV_CMD_AV_SUPER_WHITE_ON 0x0001
278/* aspect */
279#define PS3AV_CMD_AV_ASPECT_16_9 0x0000
280#define PS3AV_CMD_AV_ASPECT_4_3 0x0001
281/* video_cs_cnv() */
282#define PS3AV_CMD_VIDEO_CS_RGB 0x0001
283#define PS3AV_CMD_VIDEO_CS_YUV422 0x0002
284#define PS3AV_CMD_VIDEO_CS_YUV444 0x0003
285
286/* for broadcast automode */
287#define PS3AV_RESBIT_720x480P 0x0003 /* 0x0001 | 0x0002 */
288#define PS3AV_RESBIT_720x576P 0x0003 /* 0x0001 | 0x0002 */
289#define PS3AV_RESBIT_1280x720P 0x0004
290#define PS3AV_RESBIT_1920x1080I 0x0008
291#define PS3AV_RESBIT_1920x1080P 0x4000
292#define PS3AV_RES_MASK_60 (PS3AV_RESBIT_720x480P \
293 | PS3AV_RESBIT_1280x720P \
294 | PS3AV_RESBIT_1920x1080I \
295 | PS3AV_RESBIT_1920x1080P)
296#define PS3AV_RES_MASK_50 (PS3AV_RESBIT_720x576P \
297 | PS3AV_RESBIT_1280x720P \
298 | PS3AV_RESBIT_1920x1080I \
299 | PS3AV_RESBIT_1920x1080P)
300
301/* for VESA automode */
302#define PS3AV_RESBIT_VGA 0x0001
303#define PS3AV_RESBIT_WXGA 0x0002
304#define PS3AV_RESBIT_SXGA 0x0004
305#define PS3AV_RESBIT_WUXGA 0x0008
306#define PS3AV_RES_MASK_VESA (PS3AV_RESBIT_WXGA |\
307 PS3AV_RESBIT_SXGA |\
308 PS3AV_RESBIT_WUXGA)
309
310#define PS3AV_MONITOR_TYPE_HDMI 1 /* HDMI */
311#define PS3AV_MONITOR_TYPE_DVI 2 /* DVI */
312
313
314/* for video mode */
315enum ps3av_mode_num {
316 PS3AV_MODE_AUTO = 0,
317 PS3AV_MODE_480I = 1,
318 PS3AV_MODE_480P = 2,
319 PS3AV_MODE_720P60 = 3,
320 PS3AV_MODE_1080I60 = 4,
321 PS3AV_MODE_1080P60 = 5,
322 PS3AV_MODE_576I = 6,
323 PS3AV_MODE_576P = 7,
324 PS3AV_MODE_720P50 = 8,
325 PS3AV_MODE_1080I50 = 9,
326 PS3AV_MODE_1080P50 = 10,
327 PS3AV_MODE_WXGA = 11,
328 PS3AV_MODE_SXGA = 12,
329 PS3AV_MODE_WUXGA = 13,
330};
331
332#define PS3AV_MODE_MASK 0x000F
333#define PS3AV_MODE_HDCP_OFF 0x1000 /* Retail PS3 product doesn't support this */
334#define PS3AV_MODE_DITHER 0x0800
335#define PS3AV_MODE_COLOR 0x0400
336#define PS3AV_MODE_WHITE 0x0200
337#define PS3AV_MODE_FULL 0x0080
338#define PS3AV_MODE_DVI 0x0040
339#define PS3AV_MODE_RGB 0x0020
340
341
342#define PS3AV_DEFAULT_HDMI_MODE_ID_REG_60 PS3AV_MODE_480P
343#define PS3AV_DEFAULT_AVMULTI_MODE_ID_REG_60 PS3AV_MODE_480I
344#define PS3AV_DEFAULT_HDMI_MODE_ID_REG_50 PS3AV_MODE_576P
345#define PS3AV_DEFAULT_AVMULTI_MODE_ID_REG_50 PS3AV_MODE_576I
346
347#define PS3AV_REGION_60 0x01
348#define PS3AV_REGION_50 0x02
349#define PS3AV_REGION_RGB 0x10
350
351#define get_status(buf) (((__u32 *)buf)[2])
352#define PS3AV_HDR_SIZE 4 /* version + size */
353
354
355/** command packet structure **/
356struct ps3av_send_hdr {
357 u16 version;
358 u16 size; /* size of command packet */
359 u32 cid; /* command id */
360};
361
362struct ps3av_reply_hdr {
363 u16 version;
364 u16 size;
365 u32 cid;
366 u32 status;
367};
368
369/* backend: initialization */
370struct ps3av_pkt_av_init {
371 struct ps3av_send_hdr send_hdr;
372 u32 event_bit;
373};
374
375/* backend: finalize */
376struct ps3av_pkt_av_fin {
377 struct ps3av_send_hdr send_hdr;
378 /* recv */
379 u32 reserved;
380};
381
382/* backend: get port */
383struct ps3av_pkt_av_get_hw_conf {
384 struct ps3av_send_hdr send_hdr;
385 /* recv */
386 u32 status;
387 u16 num_of_hdmi; /* out: number of hdmi */
388 u16 num_of_avmulti; /* out: number of avmulti */
389 u16 num_of_spdif; /* out: number of hdmi */
390 u16 reserved;
391};
392
393/* backend: get monitor info */
394struct ps3av_info_resolution {
395 u32 res_bits;
396 u32 native;
397};
398
399struct ps3av_info_cs {
400 u8 rgb;
401 u8 yuv444;
402 u8 yuv422;
403 u8 reserved;
404};
405
406struct ps3av_info_color {
407 u16 red_x;
408 u16 red_y;
409 u16 green_x;
410 u16 green_y;
411 u16 blue_x;
412 u16 blue_y;
413 u16 white_x;
414 u16 white_y;
415 u32 gamma;
416};
417
418struct ps3av_info_audio {
419 u8 type;
420 u8 max_num_of_ch;
421 u8 fs;
422 u8 sbit;
423};
424
425struct ps3av_info_monitor {
426 u8 avport;
427 u8 monitor_id[10];
428 u8 monitor_type;
429 u8 monitor_name[16];
430 struct ps3av_info_resolution res_60;
431 struct ps3av_info_resolution res_50;
432 struct ps3av_info_resolution res_other;
433 struct ps3av_info_resolution res_vesa;
434 struct ps3av_info_cs cs;
435 struct ps3av_info_color color;
436 u8 supported_ai;
437 u8 speaker_info;
438 u8 num_of_audio_block;
439 struct ps3av_info_audio audio[0]; /* 0 or more audio blocks */
440 u8 reserved[169];
441} __attribute__ ((packed));
442
443struct ps3av_pkt_av_get_monitor_info {
444 struct ps3av_send_hdr send_hdr;
445 u16 avport; /* in: avport */
446 u16 reserved;
447 /* recv */
448 struct ps3av_info_monitor info; /* out: monitor info */
449};
450
451/* backend: enable/disable event */
452struct ps3av_pkt_av_event {
453 struct ps3av_send_hdr send_hdr;
454 u32 event_bit; /* in */
455};
456
457/* backend: video cs param */
458struct ps3av_pkt_av_video_cs {
459 struct ps3av_send_hdr send_hdr;
460 u16 avport; /* in: avport */
461 u16 av_vid; /* in: video resolution */
462 u16 av_cs_out; /* in: output color space */
463 u16 av_cs_in; /* in: input color space */
464 u8 dither; /* in: dither bit length */
465 u8 bitlen_out; /* in: bit length */
466 u8 super_white; /* in: super white */
467 u8 aspect; /* in: aspect ratio */
468};
469
470/* backend: video mute */
471struct ps3av_av_mute {
472 u16 avport; /* in: avport */
473 u16 mute; /* in: mute on/off */
474};
475
476struct ps3av_pkt_av_video_mute {
477 struct ps3av_send_hdr send_hdr;
478 struct ps3av_av_mute mute[PS3AV_MUTE_PORT_MAX];
479};
480
481/* backend: video disable signal */
482struct ps3av_pkt_av_video_disable_sig {
483 struct ps3av_send_hdr send_hdr;
484 u16 avport; /* in: avport */
485 u16 reserved;
486};
487
488/* backend: audio param */
489struct ps3av_audio_info_frame {
490 struct pb1_bit {
491 u8 ct:4;
492 u8 rsv:1;
493 u8 cc:3;
494 } pb1;
495 struct pb2_bit {
496 u8 rsv:3;
497 u8 sf:3;
498 u8 ss:2;
499 } pb2;
500 u8 pb3;
501 u8 pb4;
502 struct pb5_bit {
503 u8 dm:1;
504 u8 lsv:4;
505 u8 rsv:3;
506 } pb5;
507};
508
509struct ps3av_pkt_av_audio_param {
510 struct ps3av_send_hdr send_hdr;
511 u16 avport; /* in: avport */
512 u16 reserved;
513 u8 mclk; /* in: audio mclk */
514 u8 ns[3]; /* in: audio ns val */
515 u8 enable; /* in: audio enable */
516 u8 swaplr; /* in: audio swap */
517 u8 fifomap; /* in: audio fifomap */
518 u8 inputctrl; /* in: audio input ctrl */
519 u8 inputlen; /* in: sample bit size */
520 u8 layout; /* in: speaker layout param */
521 struct ps3av_audio_info_frame info; /* in: info */
522 u8 chstat[5]; /* in: ch stat */
523};
524
525/* backend: audio_mute */
526struct ps3av_pkt_av_audio_mute {
527 struct ps3av_send_hdr send_hdr;
528 struct ps3av_av_mute mute[PS3AV_MUTE_PORT_MAX];
529};
530
531/* backend: hdmi_mode */
532struct ps3av_pkt_av_hdmi_mode {
533 struct ps3av_send_hdr send_hdr;
534 u8 mode; /* in: hdmi_mode */
535 u8 reserved0;
536 u8 reserved1;
537 u8 reserved2;
538};
539
540/* backend: tv_mute */
541struct ps3av_pkt_av_tv_mute {
542 struct ps3av_send_hdr send_hdr;
543 u16 avport; /* in: avport HDMI only */
544 u16 mute; /* in: mute */
545};
546
547/* video: initialize */
548struct ps3av_pkt_video_init {
549 struct ps3av_send_hdr send_hdr;
550 /* recv */
551 u32 reserved;
552};
553
554/* video: mode setting */
555struct ps3av_pkt_video_mode {
556 struct ps3av_send_hdr send_hdr;
557 u32 video_head; /* in: head */
558 u32 reserved;
559 u32 video_vid; /* in: video resolution */
560 u16 reserved1;
561 u16 width; /* in: width in pixel */
562 u16 reserved2;
563 u16 height; /* in: height in pixel */
564 u32 pitch; /* in: line size in byte */
565 u32 video_out_format; /* in: out format */
566 u32 video_format; /* in: input frame buffer format */
567 u8 reserved3;
568 u8 video_cl_cnv; /* in: color conversion */
569 u16 video_order; /* in: input RGB order */
570 u32 reserved4;
571};
572
573/* video: format */
574struct ps3av_pkt_video_format {
575 struct ps3av_send_hdr send_hdr;
576 u32 video_head; /* in: head */
577 u32 video_format; /* in: frame buffer format */
578 u8 reserved;
579 u8 video_cl_cnv; /* in: color conversion */
580 u16 video_order; /* in: input RGB order */
581};
582
583/* video: pitch */
584struct ps3av_pkt_video_pitch {
585 u16 version;
586 u16 size; /* size of command packet */
587 u32 cid; /* command id */
588 u32 video_head; /* in: head */
589 u32 pitch; /* in: line size in byte */
590};
591
592/* audio: initialize */
593struct ps3av_pkt_audio_init {
594 struct ps3av_send_hdr send_hdr;
595 /* recv */
596 u32 reserved;
597};
598
599/* audio: mode setting */
600struct ps3av_pkt_audio_mode {
601 struct ps3av_send_hdr send_hdr;
602 u8 avport; /* in: avport */
603 u8 reserved0[3];
604 u32 mask; /* in: mask */
605 u32 audio_num_of_ch; /* in: number of ch */
606 u32 audio_fs; /* in: sampling freq */
607 u32 audio_word_bits; /* in: sample bit size */
608 u32 audio_format; /* in: audio output format */
609 u32 audio_source; /* in: audio source */
610 u8 audio_enable[4]; /* in: audio enable */
611 u8 audio_swap[4]; /* in: audio swap */
612 u8 audio_map[4]; /* in: audio map */
613 u32 audio_layout; /* in: speaker layout */
614 u32 audio_downmix; /* in: audio downmix permission */
615 u32 audio_downmix_level;
616 u8 audio_cs_info[8]; /* in: IEC channel status */
617};
618
619/* audio: mute */
620struct ps3av_audio_mute {
621 u8 avport; /* in: opt_port optical */
622 u8 reserved[3];
623 u32 mute; /* in: mute */
624};
625
626struct ps3av_pkt_audio_mute {
627 struct ps3av_send_hdr send_hdr;
628 struct ps3av_audio_mute mute[PS3AV_OPT_PORT_MAX];
629};
630
631/* audio: active/inactive */
632struct ps3av_pkt_audio_active {
633 struct ps3av_send_hdr send_hdr;
634 u32 audio_port; /* in: audio active/inactive port */
635};
636
637/* audio: SPDIF user bit */
638struct ps3av_pkt_audio_spdif_bit {
639 u16 version;
640 u16 size; /* size of command packet */
641 u32 cid; /* command id */
642 u8 avport; /* in: avport SPDIF only */
643 u8 reserved[3];
644 u32 audio_port; /* in: SPDIF only */
645 u32 spdif_bit_data[12]; /* in: user bit data */
646};
647
648/* audio: audio control */
649struct ps3av_pkt_audio_ctrl {
650 u16 version;
651 u16 size; /* size of command packet */
652 u32 cid; /* command id */
653 u32 audio_ctrl_id; /* in: control id */
654 u32 audio_ctrl_data[4]; /* in: control data */
655};
656
657/* avb:param */
658#define PS3AV_PKT_AVB_PARAM_MAX_BUF_SIZE \
659 (PS3AV_AVB_NUM_VIDEO*sizeof(struct ps3av_pkt_video_mode) + \
660 PS3AV_AVB_NUM_AUDIO*sizeof(struct ps3av_pkt_audio_mode) + \
661 PS3AV_AVB_NUM_AV_VIDEO*sizeof(struct ps3av_pkt_av_video_cs) + \
662 PS3AV_AVB_NUM_AV_AUDIO*sizeof(struct ps3av_pkt_av_audio_param))
663
664struct ps3av_pkt_avb_param {
665 struct ps3av_send_hdr send_hdr;
666 u16 num_of_video_pkt;
667 u16 num_of_audio_pkt;
668 u16 num_of_av_video_pkt;
669 u16 num_of_av_audio_pkt;
670 /*
671 * The actual buffer layout depends on the fields above:
672 *
673 * struct ps3av_pkt_video_mode video[num_of_video_pkt];
674 * struct ps3av_pkt_audio_mode audio[num_of_audio_pkt];
675 * struct ps3av_pkt_av_video_cs av_video[num_of_av_video_pkt];
676 * struct ps3av_pkt_av_audio_param av_audio[num_of_av_audio_pkt];
677 */
678 u8 buf[PS3AV_PKT_AVB_PARAM_MAX_BUF_SIZE];
679};
680
681
682/** command status **/
683#define PS3AV_STATUS_SUCCESS 0x0000 /* success */
684#define PS3AV_STATUS_RECEIVE_VUART_ERROR 0x0001 /* receive vuart error */
685#define PS3AV_STATUS_SYSCON_COMMUNICATE_FAIL 0x0002 /* syscon communication error */
686#define PS3AV_STATUS_INVALID_COMMAND 0x0003 /* obsolete invalid CID */
687#define PS3AV_STATUS_INVALID_PORT 0x0004 /* invalid port number */
688#define PS3AV_STATUS_INVALID_VID 0x0005 /* invalid video format */
689#define PS3AV_STATUS_INVALID_COLOR_SPACE 0x0006 /* invalid video colose space */
690#define PS3AV_STATUS_INVALID_FS 0x0007 /* invalid audio sampling freq */
691#define PS3AV_STATUS_INVALID_AUDIO_CH 0x0008 /* invalid audio channel number */
692#define PS3AV_STATUS_UNSUPPORTED_VERSION 0x0009 /* version mismatch */
693#define PS3AV_STATUS_INVALID_SAMPLE_SIZE 0x000a /* invalid audio sample bit size */
694#define PS3AV_STATUS_FAILURE 0x000b /* other failures */
695#define PS3AV_STATUS_UNSUPPORTED_COMMAND 0x000c /* unsupported cid */
696#define PS3AV_STATUS_BUFFER_OVERFLOW 0x000d /* write buffer overflow */
697#define PS3AV_STATUS_INVALID_VIDEO_PARAM 0x000e /* invalid video param */
698#define PS3AV_STATUS_NO_SEL 0x000f /* not exist selector */
699#define PS3AV_STATUS_INVALID_AV_PARAM 0x0010 /* invalid backend param */
700#define PS3AV_STATUS_INVALID_AUDIO_PARAM 0x0011 /* invalid audio param */
701#define PS3AV_STATUS_UNSUPPORTED_HDMI_MODE 0x0012 /* unsupported hdmi mode */
702#define PS3AV_STATUS_NO_SYNC_HEAD 0x0013 /* sync head failed */
703
704extern void ps3av_set_hdr(u32, u16, struct ps3av_send_hdr *);
705extern int ps3av_do_pkt(u32, u16, size_t, struct ps3av_send_hdr *);
706
707extern int ps3av_cmd_init(void);
708extern int ps3av_cmd_fin(void);
709extern int ps3av_cmd_av_video_mute(int, u32 *, u32);
710extern int ps3av_cmd_av_video_disable_sig(u32);
711extern int ps3av_cmd_av_tv_mute(u32, u32);
712extern int ps3av_cmd_enable_event(void);
713extern int ps3av_cmd_av_hdmi_mode(u8);
714extern u32 ps3av_cmd_set_av_video_cs(void *, u32, int, int, int, u32);
715extern u32 ps3av_cmd_set_video_mode(void *, u32, int, int, u32);
716extern int ps3av_cmd_video_format_black(u32, u32, u32);
717extern int ps3av_cmd_av_audio_mute(int, u32 *, u32);
718extern u32 ps3av_cmd_set_av_audio_param(void *, u32,
719 const struct ps3av_pkt_audio_mode *,
720 u32);
721extern void ps3av_cmd_set_audio_mode(struct ps3av_pkt_audio_mode *, u32, u32,
722 u32, u32, u32, u32);
723extern int ps3av_cmd_audio_mode(struct ps3av_pkt_audio_mode *);
724extern int ps3av_cmd_audio_mute(int, u32 *, u32);
725extern int ps3av_cmd_audio_active(int, u32);
726extern int ps3av_cmd_avb_param(struct ps3av_pkt_avb_param *, u32);
727extern int ps3av_cmd_av_get_hw_conf(struct ps3av_pkt_av_get_hw_conf *);
728extern int ps3av_cmd_video_get_monitor_info(struct ps3av_pkt_av_get_monitor_info *,
729 u32);
730
731extern int ps3av_set_video_mode(u32);
732extern int ps3av_set_audio_mode(u32, u32, u32, u32, u32);
733extern int ps3av_get_auto_mode(void);
734extern int ps3av_get_mode(void);
735extern int ps3av_video_mode2res(u32, u32 *, u32 *);
736extern int ps3av_video_mute(int);
737extern int ps3av_audio_mute(int);
738extern int ps3av_dev_open(void);
739extern int ps3av_dev_close(void);
740extern void ps3av_register_flip_ctl(void (*flip_ctl)(int on, void *data),
741 void *flip_data);
742extern void ps3av_flip_ctl(int on);
743
744#endif /* _ASM_POWERPC_PS3AV_H_ */
diff --git a/include/asm-powerpc/ps3fb.h b/include/asm-powerpc/ps3fb.h
deleted file mode 100644
index 3f121fe4010..00000000000
--- a/include/asm-powerpc/ps3fb.h
+++ /dev/null
@@ -1,44 +0,0 @@
1/*
2 * Copyright (C) 2006 Sony Computer Entertainment Inc.
3 * Copyright 2006, 2007 Sony Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published
7 * by the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#ifndef _ASM_POWERPC_PS3FB_H_
20#define _ASM_POWERPC_PS3FB_H_
21
22#include <linux/ioctl.h>
23
24/* ioctl */
25#define PS3FB_IOCTL_SETMODE _IOW('r', 1, int) /* set video mode */
26#define PS3FB_IOCTL_GETMODE _IOR('r', 2, int) /* get video mode */
27#define PS3FB_IOCTL_SCREENINFO _IOR('r', 3, int) /* get screen info */
28#define PS3FB_IOCTL_ON _IO('r', 4) /* use IOCTL_FSEL */
29#define PS3FB_IOCTL_OFF _IO('r', 5) /* return to normal-flip */
30#define PS3FB_IOCTL_FSEL _IOW('r', 6, int) /* blit and flip request */
31
32#ifndef FBIO_WAITFORVSYNC
33#define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32) /* wait for vsync */
34#endif
35
36struct ps3fb_ioctl_res {
37 __u32 xres; /* frame buffer x_size */
38 __u32 yres; /* frame buffer y_size */
39 __u32 xoff; /* margine x */
40 __u32 yoff; /* margine y */
41 __u32 num_frames; /* num of frame buffers */
42};
43
44#endif /* _ASM_POWERPC_PS3FB_H_ */
diff --git a/include/asm-powerpc/ps3stor.h b/include/asm-powerpc/ps3stor.h
deleted file mode 100644
index 6fcaf714fa5..00000000000
--- a/include/asm-powerpc/ps3stor.h
+++ /dev/null
@@ -1,71 +0,0 @@
1/*
2 * PS3 Storage Devices
3 *
4 * Copyright (C) 2007 Sony Computer Entertainment Inc.
5 * Copyright 2007 Sony Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published
9 * by the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#ifndef _ASM_POWERPC_PS3STOR_H_
22#define _ASM_POWERPC_PS3STOR_H_
23
24#include <linux/interrupt.h>
25
26#include <asm/ps3.h>
27
28
29struct ps3_storage_region {
30 unsigned int id;
31 u64 start;
32 u64 size;
33};
34
35struct ps3_storage_device {
36 struct ps3_system_bus_device sbd;
37
38 struct ps3_dma_region dma_region;
39 unsigned int irq;
40 u64 blk_size;
41
42 u64 tag;
43 u64 lv1_status;
44 struct completion done;
45
46 unsigned long bounce_size;
47 void *bounce_buf;
48 u64 bounce_lpar;
49 dma_addr_t bounce_dma;
50
51 unsigned int num_regions;
52 unsigned long accessible_regions;
53 unsigned int region_idx; /* first accessible region */
54 struct ps3_storage_region regions[0]; /* Must be last */
55};
56
57static inline struct ps3_storage_device *to_ps3_storage_device(struct device *dev)
58{
59 return container_of(dev, struct ps3_storage_device, sbd.core);
60}
61
62extern int ps3stor_setup(struct ps3_storage_device *dev,
63 irq_handler_t handler);
64extern void ps3stor_teardown(struct ps3_storage_device *dev);
65extern u64 ps3stor_read_write_sectors(struct ps3_storage_device *dev, u64 lpar,
66 u64 start_sector, u64 sectors,
67 int write);
68extern u64 ps3stor_send_command(struct ps3_storage_device *dev, u64 cmd,
69 u64 arg1, u64 arg2, u64 arg3, u64 arg4);
70
71#endif /* _ASM_POWERPC_PS3STOR_H_ */
diff --git a/include/asm-powerpc/ptrace.h b/include/asm-powerpc/ptrace.h
deleted file mode 100644
index 3d6e31024e5..00000000000
--- a/include/asm-powerpc/ptrace.h
+++ /dev/null
@@ -1,292 +0,0 @@
1#ifndef _ASM_POWERPC_PTRACE_H
2#define _ASM_POWERPC_PTRACE_H
3
4/*
5 * Copyright (C) 2001 PPC64 Team, IBM Corp
6 *
7 * This struct defines the way the registers are stored on the
8 * kernel stack during a system call or other kernel entry.
9 *
10 * this should only contain volatile regs
11 * since we can keep non-volatile in the thread_struct
12 * should set this up when only volatiles are saved
13 * by intr code.
14 *
15 * Since this is going on the stack, *CARE MUST BE TAKEN* to insure
16 * that the overall structure is a multiple of 16 bytes in length.
17 *
18 * Note that the offsets of the fields in this struct correspond with
19 * the PT_* values below. This simplifies arch/powerpc/kernel/ptrace.c.
20 *
21 * This program is free software; you can redistribute it and/or
22 * modify it under the terms of the GNU General Public License
23 * as published by the Free Software Foundation; either version
24 * 2 of the License, or (at your option) any later version.
25 */
26
27#ifndef __ASSEMBLY__
28
29struct pt_regs {
30 unsigned long gpr[32];
31 unsigned long nip;
32 unsigned long msr;
33 unsigned long orig_gpr3; /* Used for restarting system calls */
34 unsigned long ctr;
35 unsigned long link;
36 unsigned long xer;
37 unsigned long ccr;
38#ifdef __powerpc64__
39 unsigned long softe; /* Soft enabled/disabled */
40#else
41 unsigned long mq; /* 601 only (not used at present) */
42 /* Used on APUS to hold IPL value. */
43#endif
44 unsigned long trap; /* Reason for being here */
45 /* N.B. for critical exceptions on 4xx, the dar and dsisr
46 fields are overloaded to hold srr0 and srr1. */
47 unsigned long dar; /* Fault registers */
48 unsigned long dsisr; /* on 4xx/Book-E used for ESR */
49 unsigned long result; /* Result of a system call */
50};
51
52#endif /* __ASSEMBLY__ */
53
54#ifdef __KERNEL__
55
56#ifdef __powerpc64__
57
58#define __ARCH_WANT_COMPAT_SYS_PTRACE
59
60#define STACK_FRAME_OVERHEAD 112 /* size of minimum stack frame */
61#define STACK_FRAME_LR_SAVE 2 /* Location of LR in stack frame */
62#define STACK_FRAME_REGS_MARKER ASM_CONST(0x7265677368657265)
63#define STACK_INT_FRAME_SIZE (sizeof(struct pt_regs) + \
64 STACK_FRAME_OVERHEAD + 288)
65#define STACK_FRAME_MARKER 12
66
67/* Size of dummy stack frame allocated when calling signal handler. */
68#define __SIGNAL_FRAMESIZE 128
69#define __SIGNAL_FRAMESIZE32 64
70
71#else /* __powerpc64__ */
72
73#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */
74#define STACK_FRAME_LR_SAVE 1 /* Location of LR in stack frame */
75#define STACK_FRAME_REGS_MARKER ASM_CONST(0x72656773)
76#define STACK_INT_FRAME_SIZE (sizeof(struct pt_regs) + STACK_FRAME_OVERHEAD)
77#define STACK_FRAME_MARKER 2
78
79/* Size of stack frame allocated when calling signal handler. */
80#define __SIGNAL_FRAMESIZE 64
81
82#endif /* __powerpc64__ */
83
84#ifndef __ASSEMBLY__
85
86#define instruction_pointer(regs) ((regs)->nip)
87#define regs_return_value(regs) ((regs)->gpr[3])
88
89#ifdef CONFIG_SMP
90extern unsigned long profile_pc(struct pt_regs *regs);
91#else
92#define profile_pc(regs) instruction_pointer(regs)
93#endif
94
95#ifdef __powerpc64__
96#define user_mode(regs) ((((regs)->msr) >> MSR_PR_LG) & 0x1)
97#else
98#define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
99#endif
100
101#define force_successful_syscall_return() \
102 do { \
103 set_thread_flag(TIF_NOERROR); \
104 } while(0)
105
106struct task_struct;
107extern unsigned long ptrace_get_reg(struct task_struct *task, int regno);
108extern int ptrace_put_reg(struct task_struct *task, int regno,
109 unsigned long data);
110
111/*
112 * We use the least-significant bit of the trap field to indicate
113 * whether we have saved the full set of registers, or only a
114 * partial set. A 1 there means the partial set.
115 * On 4xx we use the next bit to indicate whether the exception
116 * is a critical exception (1 means it is).
117 */
118#define FULL_REGS(regs) (((regs)->trap & 1) == 0)
119#ifndef __powerpc64__
120#define IS_CRITICAL_EXC(regs) (((regs)->trap & 2) != 0)
121#define IS_MCHECK_EXC(regs) (((regs)->trap & 4) != 0)
122#define IS_DEBUG_EXC(regs) (((regs)->trap & 8) != 0)
123#endif /* ! __powerpc64__ */
124#define TRAP(regs) ((regs)->trap & ~0xF)
125#ifdef __powerpc64__
126#define CHECK_FULL_REGS(regs) BUG_ON(regs->trap & 1)
127#else
128#define CHECK_FULL_REGS(regs) \
129do { \
130 if ((regs)->trap & 1) \
131 printk(KERN_CRIT "%s: partial register set\n", __FUNCTION__); \
132} while (0)
133#endif /* __powerpc64__ */
134
135/*
136 * These are defined as per linux/ptrace.h, which see.
137 */
138#define arch_has_single_step() (1)
139extern void user_enable_single_step(struct task_struct *);
140extern void user_disable_single_step(struct task_struct *);
141
142#endif /* __ASSEMBLY__ */
143
144#endif /* __KERNEL__ */
145
146/*
147 * Offsets used by 'ptrace' system call interface.
148 * These can't be changed without breaking binary compatibility
149 * with MkLinux, etc.
150 */
151#define PT_R0 0
152#define PT_R1 1
153#define PT_R2 2
154#define PT_R3 3
155#define PT_R4 4
156#define PT_R5 5
157#define PT_R6 6
158#define PT_R7 7
159#define PT_R8 8
160#define PT_R9 9
161#define PT_R10 10
162#define PT_R11 11
163#define PT_R12 12
164#define PT_R13 13
165#define PT_R14 14
166#define PT_R15 15
167#define PT_R16 16
168#define PT_R17 17
169#define PT_R18 18
170#define PT_R19 19
171#define PT_R20 20
172#define PT_R21 21
173#define PT_R22 22
174#define PT_R23 23
175#define PT_R24 24
176#define PT_R25 25
177#define PT_R26 26
178#define PT_R27 27
179#define PT_R28 28
180#define PT_R29 29
181#define PT_R30 30
182#define PT_R31 31
183
184#define PT_NIP 32
185#define PT_MSR 33
186#define PT_ORIG_R3 34
187#define PT_CTR 35
188#define PT_LNK 36
189#define PT_XER 37
190#define PT_CCR 38
191#ifndef __powerpc64__
192#define PT_MQ 39
193#else
194#define PT_SOFTE 39
195#endif
196#define PT_TRAP 40
197#define PT_DAR 41
198#define PT_DSISR 42
199#define PT_RESULT 43
200#define PT_REGS_COUNT 44
201
202#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */
203
204#ifndef __powerpc64__
205
206#define PT_FPR31 (PT_FPR0 + 2*31)
207#define PT_FPSCR (PT_FPR0 + 2*32 + 1)
208
209#else /* __powerpc64__ */
210
211#define PT_FPSCR (PT_FPR0 + 32) /* each FP reg occupies 1 slot in 64-bit space */
212
213#ifdef __KERNEL__
214#define PT_FPSCR32 (PT_FPR0 + 2*32 + 1) /* each FP reg occupies 2 32-bit userspace slots */
215#endif
216
217#define PT_VR0 82 /* each Vector reg occupies 2 slots in 64-bit */
218#define PT_VSCR (PT_VR0 + 32*2 + 1)
219#define PT_VRSAVE (PT_VR0 + 33*2)
220
221#ifdef __KERNEL__
222#define PT_VR0_32 164 /* each Vector reg occupies 4 slots in 32-bit */
223#define PT_VSCR_32 (PT_VR0 + 32*4 + 3)
224#define PT_VRSAVE_32 (PT_VR0 + 33*4)
225#endif
226
227/*
228 * Only store first 32 VSRs here. The second 32 VSRs in VR0-31
229 */
230#define PT_VSR0 150 /* each VSR reg occupies 2 slots in 64-bit */
231#define PT_VSR31 (PT_VSR0 + 2*31)
232#ifdef __KERNEL__
233#define PT_VSR0_32 300 /* each VSR reg occupies 4 slots in 32-bit */
234#endif
235#endif /* __powerpc64__ */
236
237/*
238 * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
239 * The transfer totals 34 quadword. Quadwords 0-31 contain the
240 * corresponding vector registers. Quadword 32 contains the vscr as the
241 * last word (offset 12) within that quadword. Quadword 33 contains the
242 * vrsave as the first word (offset 0) within the quadword.
243 *
244 * This definition of the VMX state is compatible with the current PPC32
245 * ptrace interface. This allows signal handling and ptrace to use the same
246 * structures. This also simplifies the implementation of a bi-arch
247 * (combined (32- and 64-bit) gdb.
248 */
249#define PTRACE_GETVRREGS 18
250#define PTRACE_SETVRREGS 19
251
252/* Get/set all the upper 32-bits of the SPE registers, accumulator, and
253 * spefscr, in one go */
254#define PTRACE_GETEVRREGS 20
255#define PTRACE_SETEVRREGS 21
256
257/* Get the first 32 128bit VSX registers */
258#define PTRACE_GETVSRREGS 27
259#define PTRACE_SETVSRREGS 28
260
261/*
262 * Get or set a debug register. The first 16 are DABR registers and the
263 * second 16 are IABR registers.
264 */
265#define PTRACE_GET_DEBUGREG 25
266#define PTRACE_SET_DEBUGREG 26
267
268/* (new) PTRACE requests using the same numbers as x86 and the same
269 * argument ordering. Additionally, they support more registers too
270 */
271#define PTRACE_GETREGS 12
272#define PTRACE_SETREGS 13
273#define PTRACE_GETFPREGS 14
274#define PTRACE_SETFPREGS 15
275#define PTRACE_GETREGS64 22
276#define PTRACE_SETREGS64 23
277
278/* (old) PTRACE requests with inverted arguments */
279#define PPC_PTRACE_GETREGS 0x99 /* Get GPRs 0 - 31 */
280#define PPC_PTRACE_SETREGS 0x98 /* Set GPRs 0 - 31 */
281#define PPC_PTRACE_GETFPREGS 0x97 /* Get FPRs 0 - 31 */
282#define PPC_PTRACE_SETFPREGS 0x96 /* Set FPRs 0 - 31 */
283
284/* Calls to trace a 64bit program from a 32bit program */
285#define PPC_PTRACE_PEEKTEXT_3264 0x95
286#define PPC_PTRACE_PEEKDATA_3264 0x94
287#define PPC_PTRACE_POKETEXT_3264 0x93
288#define PPC_PTRACE_POKEDATA_3264 0x92
289#define PPC_PTRACE_PEEKUSR_3264 0x91
290#define PPC_PTRACE_POKEUSR_3264 0x90
291
292#endif /* _ASM_POWERPC_PTRACE_H */
diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h
deleted file mode 100644
index edee15d269e..00000000000
--- a/include/asm-powerpc/qe.h
+++ /dev/null
@@ -1,642 +0,0 @@
1/*
2 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
3 *
4 * Authors: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
6 *
7 * Description:
8 * QUICC Engine (QE) external definitions and structure.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15#ifndef _ASM_POWERPC_QE_H
16#define _ASM_POWERPC_QE_H
17#ifdef __KERNEL__
18
19#include <linux/spinlock.h>
20#include <asm/cpm.h>
21#include <asm/immap_qe.h>
22
23#define QE_NUM_OF_SNUM 28
24#define QE_NUM_OF_BRGS 16
25#define QE_NUM_OF_PORTS 1024
26
27/* Memory partitions
28*/
29#define MEM_PART_SYSTEM 0
30#define MEM_PART_SECONDARY 1
31#define MEM_PART_MURAM 2
32
33/* Clocks and BRGs */
34enum qe_clock {
35 QE_CLK_NONE = 0,
36 QE_BRG1, /* Baud Rate Generator 1 */
37 QE_BRG2, /* Baud Rate Generator 2 */
38 QE_BRG3, /* Baud Rate Generator 3 */
39 QE_BRG4, /* Baud Rate Generator 4 */
40 QE_BRG5, /* Baud Rate Generator 5 */
41 QE_BRG6, /* Baud Rate Generator 6 */
42 QE_BRG7, /* Baud Rate Generator 7 */
43 QE_BRG8, /* Baud Rate Generator 8 */
44 QE_BRG9, /* Baud Rate Generator 9 */
45 QE_BRG10, /* Baud Rate Generator 10 */
46 QE_BRG11, /* Baud Rate Generator 11 */
47 QE_BRG12, /* Baud Rate Generator 12 */
48 QE_BRG13, /* Baud Rate Generator 13 */
49 QE_BRG14, /* Baud Rate Generator 14 */
50 QE_BRG15, /* Baud Rate Generator 15 */
51 QE_BRG16, /* Baud Rate Generator 16 */
52 QE_CLK1, /* Clock 1 */
53 QE_CLK2, /* Clock 2 */
54 QE_CLK3, /* Clock 3 */
55 QE_CLK4, /* Clock 4 */
56 QE_CLK5, /* Clock 5 */
57 QE_CLK6, /* Clock 6 */
58 QE_CLK7, /* Clock 7 */
59 QE_CLK8, /* Clock 8 */
60 QE_CLK9, /* Clock 9 */
61 QE_CLK10, /* Clock 10 */
62 QE_CLK11, /* Clock 11 */
63 QE_CLK12, /* Clock 12 */
64 QE_CLK13, /* Clock 13 */
65 QE_CLK14, /* Clock 14 */
66 QE_CLK15, /* Clock 15 */
67 QE_CLK16, /* Clock 16 */
68 QE_CLK17, /* Clock 17 */
69 QE_CLK18, /* Clock 18 */
70 QE_CLK19, /* Clock 19 */
71 QE_CLK20, /* Clock 20 */
72 QE_CLK21, /* Clock 21 */
73 QE_CLK22, /* Clock 22 */
74 QE_CLK23, /* Clock 23 */
75 QE_CLK24, /* Clock 24 */
76 QE_CLK_DUMMY
77};
78
79static inline bool qe_clock_is_brg(enum qe_clock clk)
80{
81 return clk >= QE_BRG1 && clk <= QE_BRG16;
82}
83
84extern spinlock_t cmxgcr_lock;
85
86/* Export QE common operations */
87extern void __init qe_reset(void);
88
89/* QE PIO */
90#define QE_PIO_PINS 32
91
92struct qe_pio_regs {
93 __be32 cpodr; /* Open drain register */
94 __be32 cpdata; /* Data register */
95 __be32 cpdir1; /* Direction register */
96 __be32 cpdir2; /* Direction register */
97 __be32 cppar1; /* Pin assignment register */
98 __be32 cppar2; /* Pin assignment register */
99#ifdef CONFIG_PPC_85xx
100 u8 pad[8];
101#endif
102};
103
104extern int par_io_init(struct device_node *np);
105extern int par_io_of_config(struct device_node *np);
106#define QE_PIO_DIR_IN 2
107#define QE_PIO_DIR_OUT 1
108extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin,
109 int dir, int open_drain, int assignment,
110 int has_irq);
111extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
112 int assignment, int has_irq);
113extern int par_io_data_set(u8 port, u8 pin, u8 val);
114
115/* QE internal API */
116int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
117enum qe_clock qe_clock_source(const char *source);
118unsigned int qe_get_brg_clk(void);
119int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
120int qe_get_snum(void);
121void qe_put_snum(u8 snum);
122/* we actually use cpm_muram implementation, define this for convenience */
123#define qe_muram_init cpm_muram_init
124#define qe_muram_alloc cpm_muram_alloc
125#define qe_muram_alloc_fixed cpm_muram_alloc_fixed
126#define qe_muram_free cpm_muram_free
127#define qe_muram_addr cpm_muram_addr
128#define qe_muram_offset cpm_muram_offset
129
130/* Structure that defines QE firmware binary files.
131 *
132 * See Documentation/powerpc/qe-firmware.txt for a description of these
133 * fields.
134 */
135struct qe_firmware {
136 struct qe_header {
137 __be32 length; /* Length of the entire structure, in bytes */
138 u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */
139 u8 version; /* Version of this layout. First ver is '1' */
140 } header;
141 u8 id[62]; /* Null-terminated identifier string */
142 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
143 u8 count; /* Number of microcode[] structures */
144 struct {
145 __be16 model; /* The SOC model */
146 u8 major; /* The SOC revision major */
147 u8 minor; /* The SOC revision minor */
148 } __attribute__ ((packed)) soc;
149 u8 padding[4]; /* Reserved, for alignment */
150 __be64 extended_modes; /* Extended modes */
151 __be32 vtraps[8]; /* Virtual trap addresses */
152 u8 reserved[4]; /* Reserved, for future expansion */
153 struct qe_microcode {
154 u8 id[32]; /* Null-terminated identifier */
155 __be32 traps[16]; /* Trap addresses, 0 == ignore */
156 __be32 eccr; /* The value for the ECCR register */
157 __be32 iram_offset; /* Offset into I-RAM for the code */
158 __be32 count; /* Number of 32-bit words of the code */
159 __be32 code_offset; /* Offset of the actual microcode */
160 u8 major; /* The microcode version major */
161 u8 minor; /* The microcode version minor */
162 u8 revision; /* The microcode version revision */
163 u8 padding; /* Reserved, for alignment */
164 u8 reserved[4]; /* Reserved, for future expansion */
165 } __attribute__ ((packed)) microcode[1];
166 /* All microcode binaries should be located here */
167 /* CRC32 should be located here, after the microcode binaries */
168} __attribute__ ((packed));
169
170struct qe_firmware_info {
171 char id[64]; /* Firmware name */
172 u32 vtraps[8]; /* Virtual trap addresses */
173 u64 extended_modes; /* Extended modes */
174};
175
176/* Upload a firmware to the QE */
177int qe_upload_firmware(const struct qe_firmware *firmware);
178
179/* Obtain information on the uploaded firmware */
180struct qe_firmware_info *qe_get_firmware_info(void);
181
182/* QE USB */
183int qe_usb_clock_set(enum qe_clock clk, int rate);
184
185/* Buffer descriptors */
186struct qe_bd {
187 __be16 status;
188 __be16 length;
189 __be32 buf;
190} __attribute__ ((packed));
191
192#define BD_STATUS_MASK 0xffff0000
193#define BD_LENGTH_MASK 0x0000ffff
194
195/* Alignment */
196#define QE_INTR_TABLE_ALIGN 16 /* ??? */
197#define QE_ALIGNMENT_OF_BD 8
198#define QE_ALIGNMENT_OF_PRAM 64
199
200/* RISC allocation */
201enum qe_risc_allocation {
202 QE_RISC_ALLOCATION_RISC1 = 1, /* RISC 1 */
203 QE_RISC_ALLOCATION_RISC2 = 2, /* RISC 2 */
204 QE_RISC_ALLOCATION_RISC1_AND_RISC2 = 3 /* Dynamically choose
205 RISC 1 or RISC 2 */
206};
207
208/* QE extended filtering Table Lookup Key Size */
209enum qe_fltr_tbl_lookup_key_size {
210 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
211 = 0x3f, /* LookupKey parsed by the Generate LookupKey
212 CMD is truncated to 8 bytes */
213 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
214 = 0x5f, /* LookupKey parsed by the Generate LookupKey
215 CMD is truncated to 16 bytes */
216};
217
218/* QE FLTR extended filtering Largest External Table Lookup Key Size */
219enum qe_fltr_largest_external_tbl_lookup_key_size {
220 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
221 = 0x0,/* not used */
222 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
223 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES, /* 8 bytes */
224 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
225 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES, /* 16 bytes */
226};
227
228/* structure representing QE parameter RAM */
229struct qe_timer_tables {
230 u16 tm_base; /* QE timer table base adr */
231 u16 tm_ptr; /* QE timer table pointer */
232 u16 r_tmr; /* QE timer mode register */
233 u16 r_tmv; /* QE timer valid register */
234 u32 tm_cmd; /* QE timer cmd register */
235 u32 tm_cnt; /* QE timer internal cnt */
236} __attribute__ ((packed));
237
238#define QE_FLTR_TAD_SIZE 8
239
240/* QE extended filtering Termination Action Descriptor (TAD) */
241struct qe_fltr_tad {
242 u8 serialized[QE_FLTR_TAD_SIZE];
243} __attribute__ ((packed));
244
245/* Communication Direction */
246enum comm_dir {
247 COMM_DIR_NONE = 0,
248 COMM_DIR_RX = 1,
249 COMM_DIR_TX = 2,
250 COMM_DIR_RX_AND_TX = 3
251};
252
253/* QE CMXUCR Registers.
254 * There are two UCCs represented in each of the four CMXUCR registers.
255 * These values are for the UCC in the LSBs
256 */
257#define QE_CMXUCR_MII_ENET_MNG 0x00007000
258#define QE_CMXUCR_MII_ENET_MNG_SHIFT 12
259#define QE_CMXUCR_GRANT 0x00008000
260#define QE_CMXUCR_TSA 0x00004000
261#define QE_CMXUCR_BKPT 0x00000100
262#define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F
263
264/* QE CMXGCR Registers.
265*/
266#define QE_CMXGCR_MII_ENET_MNG 0x00007000
267#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12
268#define QE_CMXGCR_USBCS 0x0000000f
269#define QE_CMXGCR_USBCS_CLK3 0x1
270#define QE_CMXGCR_USBCS_CLK5 0x2
271#define QE_CMXGCR_USBCS_CLK7 0x3
272#define QE_CMXGCR_USBCS_CLK9 0x4
273#define QE_CMXGCR_USBCS_CLK13 0x5
274#define QE_CMXGCR_USBCS_CLK17 0x6
275#define QE_CMXGCR_USBCS_CLK19 0x7
276#define QE_CMXGCR_USBCS_CLK21 0x8
277#define QE_CMXGCR_USBCS_BRG9 0x9
278#define QE_CMXGCR_USBCS_BRG10 0xa
279
280/* QE CECR Commands.
281*/
282#define QE_CR_FLG 0x00010000
283#define QE_RESET 0x80000000
284#define QE_INIT_TX_RX 0x00000000
285#define QE_INIT_RX 0x00000001
286#define QE_INIT_TX 0x00000002
287#define QE_ENTER_HUNT_MODE 0x00000003
288#define QE_STOP_TX 0x00000004
289#define QE_GRACEFUL_STOP_TX 0x00000005
290#define QE_RESTART_TX 0x00000006
291#define QE_CLOSE_RX_BD 0x00000007
292#define QE_SWITCH_COMMAND 0x00000007
293#define QE_SET_GROUP_ADDRESS 0x00000008
294#define QE_START_IDMA 0x00000009
295#define QE_MCC_STOP_RX 0x00000009
296#define QE_ATM_TRANSMIT 0x0000000a
297#define QE_HPAC_CLEAR_ALL 0x0000000b
298#define QE_GRACEFUL_STOP_RX 0x0000001a
299#define QE_RESTART_RX 0x0000001b
300#define QE_HPAC_SET_PRIORITY 0x0000010b
301#define QE_HPAC_STOP_TX 0x0000020b
302#define QE_HPAC_STOP_RX 0x0000030b
303#define QE_HPAC_GRACEFUL_STOP_TX 0x0000040b
304#define QE_HPAC_GRACEFUL_STOP_RX 0x0000050b
305#define QE_HPAC_START_TX 0x0000060b
306#define QE_HPAC_START_RX 0x0000070b
307#define QE_USB_STOP_TX 0x0000000a
308#define QE_USB_RESTART_TX 0x0000000c
309#define QE_QMC_STOP_TX 0x0000000c
310#define QE_QMC_STOP_RX 0x0000000d
311#define QE_SS7_SU_FIL_RESET 0x0000000e
312/* jonathbr added from here down for 83xx */
313#define QE_RESET_BCS 0x0000000a
314#define QE_MCC_INIT_TX_RX_16 0x00000003
315#define QE_MCC_STOP_TX 0x00000004
316#define QE_MCC_INIT_TX_1 0x00000005
317#define QE_MCC_INIT_RX_1 0x00000006
318#define QE_MCC_RESET 0x00000007
319#define QE_SET_TIMER 0x00000008
320#define QE_RANDOM_NUMBER 0x0000000c
321#define QE_ATM_MULTI_THREAD_INIT 0x00000011
322#define QE_ASSIGN_PAGE 0x00000012
323#define QE_ADD_REMOVE_HASH_ENTRY 0x00000013
324#define QE_START_FLOW_CONTROL 0x00000014
325#define QE_STOP_FLOW_CONTROL 0x00000015
326#define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016
327
328#define QE_ASSIGN_RISC 0x00000010
329#define QE_CR_MCN_NORMAL_SHIFT 6
330#define QE_CR_MCN_USB_SHIFT 4
331#define QE_CR_MCN_RISC_ASSIGN_SHIFT 8
332#define QE_CR_SNUM_SHIFT 17
333
334/* QE CECR Sub Block - sub block of QE command.
335*/
336#define QE_CR_SUBBLOCK_INVALID 0x00000000
337#define QE_CR_SUBBLOCK_USB 0x03200000
338#define QE_CR_SUBBLOCK_UCCFAST1 0x02000000
339#define QE_CR_SUBBLOCK_UCCFAST2 0x02200000
340#define QE_CR_SUBBLOCK_UCCFAST3 0x02400000
341#define QE_CR_SUBBLOCK_UCCFAST4 0x02600000
342#define QE_CR_SUBBLOCK_UCCFAST5 0x02800000
343#define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000
344#define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000
345#define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000
346#define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000
347#define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000
348#define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000
349#define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000
350#define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000
351#define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000
352#define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000
353#define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000
354#define QE_CR_SUBBLOCK_MCC1 0x03800000
355#define QE_CR_SUBBLOCK_MCC2 0x03a00000
356#define QE_CR_SUBBLOCK_MCC3 0x03000000
357#define QE_CR_SUBBLOCK_IDMA1 0x02800000
358#define QE_CR_SUBBLOCK_IDMA2 0x02a00000
359#define QE_CR_SUBBLOCK_IDMA3 0x02c00000
360#define QE_CR_SUBBLOCK_IDMA4 0x02e00000
361#define QE_CR_SUBBLOCK_HPAC 0x01e00000
362#define QE_CR_SUBBLOCK_SPI1 0x01400000
363#define QE_CR_SUBBLOCK_SPI2 0x01600000
364#define QE_CR_SUBBLOCK_RAND 0x01c00000
365#define QE_CR_SUBBLOCK_TIMER 0x01e00000
366#define QE_CR_SUBBLOCK_GENERAL 0x03c00000
367
368/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */
369#define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */
370#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
371#define QE_CR_PROTOCOL_QMC 0x02
372#define QE_CR_PROTOCOL_UART 0x04
373#define QE_CR_PROTOCOL_ATM_POS 0x0A
374#define QE_CR_PROTOCOL_ETHERNET 0x0C
375#define QE_CR_PROTOCOL_L2_SWITCH 0x0D
376
377/* BRG configuration register */
378#define QE_BRGC_ENABLE 0x00010000
379#define QE_BRGC_DIVISOR_SHIFT 1
380#define QE_BRGC_DIVISOR_MAX 0xFFF
381#define QE_BRGC_DIV16 1
382
383/* QE Timers registers */
384#define QE_GTCFR1_PCAS 0x80
385#define QE_GTCFR1_STP2 0x20
386#define QE_GTCFR1_RST2 0x10
387#define QE_GTCFR1_GM2 0x08
388#define QE_GTCFR1_GM1 0x04
389#define QE_GTCFR1_STP1 0x02
390#define QE_GTCFR1_RST1 0x01
391
392/* SDMA registers */
393#define QE_SDSR_BER1 0x02000000
394#define QE_SDSR_BER2 0x01000000
395
396#define QE_SDMR_GLB_1_MSK 0x80000000
397#define QE_SDMR_ADR_SEL 0x20000000
398#define QE_SDMR_BER1_MSK 0x02000000
399#define QE_SDMR_BER2_MSK 0x01000000
400#define QE_SDMR_EB1_MSK 0x00800000
401#define QE_SDMR_ER1_MSK 0x00080000
402#define QE_SDMR_ER2_MSK 0x00040000
403#define QE_SDMR_CEN_MASK 0x0000E000
404#define QE_SDMR_SBER_1 0x00000200
405#define QE_SDMR_SBER_2 0x00000200
406#define QE_SDMR_EB1_PR_MASK 0x000000C0
407#define QE_SDMR_ER1_PR 0x00000008
408
409#define QE_SDMR_CEN_SHIFT 13
410#define QE_SDMR_EB1_PR_SHIFT 6
411
412#define QE_SDTM_MSNUM_SHIFT 24
413
414#define QE_SDEBCR_BA_MASK 0x01FFFFFF
415
416/* Communication Processor */
417#define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */
418#define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */
419#define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */
420
421/* I-RAM */
422#define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */
423#define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */
424
425/* UPC */
426#define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */
427#define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */
428#define UPGCR_RMS 0x20000000 /* Receive master/slave mode */
429#define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */
430#define UPGCR_DIAG 0x01000000 /* Diagnostic mode */
431
432/* UCC GUEMR register */
433#define UCC_GUEMR_MODE_MASK_RX 0x02
434#define UCC_GUEMR_MODE_FAST_RX 0x02
435#define UCC_GUEMR_MODE_SLOW_RX 0x00
436#define UCC_GUEMR_MODE_MASK_TX 0x01
437#define UCC_GUEMR_MODE_FAST_TX 0x01
438#define UCC_GUEMR_MODE_SLOW_TX 0x00
439#define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX)
440#define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but
441 must be set 1 */
442
443/* structure representing UCC SLOW parameter RAM */
444struct ucc_slow_pram {
445 __be16 rbase; /* RX BD base address */
446 __be16 tbase; /* TX BD base address */
447 u8 rbmr; /* RX bus mode register (same as CPM's RFCR) */
448 u8 tbmr; /* TX bus mode register (same as CPM's TFCR) */
449 __be16 mrblr; /* Rx buffer length */
450 __be32 rstate; /* Rx internal state */
451 __be32 rptr; /* Rx internal data pointer */
452 __be16 rbptr; /* rb BD Pointer */
453 __be16 rcount; /* Rx internal byte count */
454 __be32 rtemp; /* Rx temp */
455 __be32 tstate; /* Tx internal state */
456 __be32 tptr; /* Tx internal data pointer */
457 __be16 tbptr; /* Tx BD pointer */
458 __be16 tcount; /* Tx byte count */
459 __be32 ttemp; /* Tx temp */
460 __be32 rcrc; /* temp receive CRC */
461 __be32 tcrc; /* temp transmit CRC */
462} __attribute__ ((packed));
463
464/* General UCC SLOW Mode Register (GUMRH & GUMRL) */
465#define UCC_SLOW_GUMR_H_SAM_QMC 0x00000000
466#define UCC_SLOW_GUMR_H_SAM_SATM 0x00008000
467#define UCC_SLOW_GUMR_H_REVD 0x00002000
468#define UCC_SLOW_GUMR_H_TRX 0x00001000
469#define UCC_SLOW_GUMR_H_TTX 0x00000800
470#define UCC_SLOW_GUMR_H_CDP 0x00000400
471#define UCC_SLOW_GUMR_H_CTSP 0x00000200
472#define UCC_SLOW_GUMR_H_CDS 0x00000100
473#define UCC_SLOW_GUMR_H_CTSS 0x00000080
474#define UCC_SLOW_GUMR_H_TFL 0x00000040
475#define UCC_SLOW_GUMR_H_RFW 0x00000020
476#define UCC_SLOW_GUMR_H_TXSY 0x00000010
477#define UCC_SLOW_GUMR_H_4SYNC 0x00000004
478#define UCC_SLOW_GUMR_H_8SYNC 0x00000008
479#define UCC_SLOW_GUMR_H_16SYNC 0x0000000c
480#define UCC_SLOW_GUMR_H_RTSM 0x00000002
481#define UCC_SLOW_GUMR_H_RSYN 0x00000001
482
483#define UCC_SLOW_GUMR_L_TCI 0x10000000
484#define UCC_SLOW_GUMR_L_RINV 0x02000000
485#define UCC_SLOW_GUMR_L_TINV 0x01000000
486#define UCC_SLOW_GUMR_L_TEND 0x00040000
487#define UCC_SLOW_GUMR_L_TDCR_MASK 0x00030000
488#define UCC_SLOW_GUMR_L_TDCR_32 0x00030000
489#define UCC_SLOW_GUMR_L_TDCR_16 0x00020000
490#define UCC_SLOW_GUMR_L_TDCR_8 0x00010000
491#define UCC_SLOW_GUMR_L_TDCR_1 0x00000000
492#define UCC_SLOW_GUMR_L_RDCR_MASK 0x0000c000
493#define UCC_SLOW_GUMR_L_RDCR_32 0x0000c000
494#define UCC_SLOW_GUMR_L_RDCR_16 0x00008000
495#define UCC_SLOW_GUMR_L_RDCR_8 0x00004000
496#define UCC_SLOW_GUMR_L_RDCR_1 0x00000000
497#define UCC_SLOW_GUMR_L_RENC_NRZI 0x00000800
498#define UCC_SLOW_GUMR_L_RENC_NRZ 0x00000000
499#define UCC_SLOW_GUMR_L_TENC_NRZI 0x00000100
500#define UCC_SLOW_GUMR_L_TENC_NRZ 0x00000000
501#define UCC_SLOW_GUMR_L_DIAG_MASK 0x000000c0
502#define UCC_SLOW_GUMR_L_DIAG_LE 0x000000c0
503#define UCC_SLOW_GUMR_L_DIAG_ECHO 0x00000080
504#define UCC_SLOW_GUMR_L_DIAG_LOOP 0x00000040
505#define UCC_SLOW_GUMR_L_DIAG_NORM 0x00000000
506#define UCC_SLOW_GUMR_L_ENR 0x00000020
507#define UCC_SLOW_GUMR_L_ENT 0x00000010
508#define UCC_SLOW_GUMR_L_MODE_MASK 0x0000000F
509#define UCC_SLOW_GUMR_L_MODE_BISYNC 0x00000008
510#define UCC_SLOW_GUMR_L_MODE_AHDLC 0x00000006
511#define UCC_SLOW_GUMR_L_MODE_UART 0x00000004
512#define UCC_SLOW_GUMR_L_MODE_QMC 0x00000002
513
514/* General UCC FAST Mode Register */
515#define UCC_FAST_GUMR_TCI 0x20000000
516#define UCC_FAST_GUMR_TRX 0x10000000
517#define UCC_FAST_GUMR_TTX 0x08000000
518#define UCC_FAST_GUMR_CDP 0x04000000
519#define UCC_FAST_GUMR_CTSP 0x02000000
520#define UCC_FAST_GUMR_CDS 0x01000000
521#define UCC_FAST_GUMR_CTSS 0x00800000
522#define UCC_FAST_GUMR_TXSY 0x00020000
523#define UCC_FAST_GUMR_RSYN 0x00010000
524#define UCC_FAST_GUMR_RTSM 0x00002000
525#define UCC_FAST_GUMR_REVD 0x00000400
526#define UCC_FAST_GUMR_ENR 0x00000020
527#define UCC_FAST_GUMR_ENT 0x00000010
528
529/* UART Slow UCC Event Register (UCCE) */
530#define UCC_UART_UCCE_AB 0x0200
531#define UCC_UART_UCCE_IDLE 0x0100
532#define UCC_UART_UCCE_GRA 0x0080
533#define UCC_UART_UCCE_BRKE 0x0040
534#define UCC_UART_UCCE_BRKS 0x0020
535#define UCC_UART_UCCE_CCR 0x0008
536#define UCC_UART_UCCE_BSY 0x0004
537#define UCC_UART_UCCE_TX 0x0002
538#define UCC_UART_UCCE_RX 0x0001
539
540/* HDLC Slow UCC Event Register (UCCE) */
541#define UCC_HDLC_UCCE_GLR 0x1000
542#define UCC_HDLC_UCCE_GLT 0x0800
543#define UCC_HDLC_UCCE_IDLE 0x0100
544#define UCC_HDLC_UCCE_BRKE 0x0040
545#define UCC_HDLC_UCCE_BRKS 0x0020
546#define UCC_HDLC_UCCE_TXE 0x0010
547#define UCC_HDLC_UCCE_RXF 0x0008
548#define UCC_HDLC_UCCE_BSY 0x0004
549#define UCC_HDLC_UCCE_TXB 0x0002
550#define UCC_HDLC_UCCE_RXB 0x0001
551
552/* BISYNC Slow UCC Event Register (UCCE) */
553#define UCC_BISYNC_UCCE_GRA 0x0080
554#define UCC_BISYNC_UCCE_TXE 0x0010
555#define UCC_BISYNC_UCCE_RCH 0x0008
556#define UCC_BISYNC_UCCE_BSY 0x0004
557#define UCC_BISYNC_UCCE_TXB 0x0002
558#define UCC_BISYNC_UCCE_RXB 0x0001
559
560/* Gigabit Ethernet Fast UCC Event Register (UCCE) */
561#define UCC_GETH_UCCE_MPD 0x80000000
562#define UCC_GETH_UCCE_SCAR 0x40000000
563#define UCC_GETH_UCCE_GRA 0x20000000
564#define UCC_GETH_UCCE_CBPR 0x10000000
565#define UCC_GETH_UCCE_BSY 0x08000000
566#define UCC_GETH_UCCE_RXC 0x04000000
567#define UCC_GETH_UCCE_TXC 0x02000000
568#define UCC_GETH_UCCE_TXE 0x01000000
569#define UCC_GETH_UCCE_TXB7 0x00800000
570#define UCC_GETH_UCCE_TXB6 0x00400000
571#define UCC_GETH_UCCE_TXB5 0x00200000
572#define UCC_GETH_UCCE_TXB4 0x00100000
573#define UCC_GETH_UCCE_TXB3 0x00080000
574#define UCC_GETH_UCCE_TXB2 0x00040000
575#define UCC_GETH_UCCE_TXB1 0x00020000
576#define UCC_GETH_UCCE_TXB0 0x00010000
577#define UCC_GETH_UCCE_RXB7 0x00008000
578#define UCC_GETH_UCCE_RXB6 0x00004000
579#define UCC_GETH_UCCE_RXB5 0x00002000
580#define UCC_GETH_UCCE_RXB4 0x00001000
581#define UCC_GETH_UCCE_RXB3 0x00000800
582#define UCC_GETH_UCCE_RXB2 0x00000400
583#define UCC_GETH_UCCE_RXB1 0x00000200
584#define UCC_GETH_UCCE_RXB0 0x00000100
585#define UCC_GETH_UCCE_RXF7 0x00000080
586#define UCC_GETH_UCCE_RXF6 0x00000040
587#define UCC_GETH_UCCE_RXF5 0x00000020
588#define UCC_GETH_UCCE_RXF4 0x00000010
589#define UCC_GETH_UCCE_RXF3 0x00000008
590#define UCC_GETH_UCCE_RXF2 0x00000004
591#define UCC_GETH_UCCE_RXF1 0x00000002
592#define UCC_GETH_UCCE_RXF0 0x00000001
593
594/* UPSMR, when used as a UART */
595#define UCC_UART_UPSMR_FLC 0x8000
596#define UCC_UART_UPSMR_SL 0x4000
597#define UCC_UART_UPSMR_CL_MASK 0x3000
598#define UCC_UART_UPSMR_CL_8 0x3000
599#define UCC_UART_UPSMR_CL_7 0x2000
600#define UCC_UART_UPSMR_CL_6 0x1000
601#define UCC_UART_UPSMR_CL_5 0x0000
602#define UCC_UART_UPSMR_UM_MASK 0x0c00
603#define UCC_UART_UPSMR_UM_NORMAL 0x0000
604#define UCC_UART_UPSMR_UM_MAN_MULTI 0x0400
605#define UCC_UART_UPSMR_UM_AUTO_MULTI 0x0c00
606#define UCC_UART_UPSMR_FRZ 0x0200
607#define UCC_UART_UPSMR_RZS 0x0100
608#define UCC_UART_UPSMR_SYN 0x0080
609#define UCC_UART_UPSMR_DRT 0x0040
610#define UCC_UART_UPSMR_PEN 0x0010
611#define UCC_UART_UPSMR_RPM_MASK 0x000c
612#define UCC_UART_UPSMR_RPM_ODD 0x0000
613#define UCC_UART_UPSMR_RPM_LOW 0x0004
614#define UCC_UART_UPSMR_RPM_EVEN 0x0008
615#define UCC_UART_UPSMR_RPM_HIGH 0x000C
616#define UCC_UART_UPSMR_TPM_MASK 0x0003
617#define UCC_UART_UPSMR_TPM_ODD 0x0000
618#define UCC_UART_UPSMR_TPM_LOW 0x0001
619#define UCC_UART_UPSMR_TPM_EVEN 0x0002
620#define UCC_UART_UPSMR_TPM_HIGH 0x0003
621
622/* UCC Transmit On Demand Register (UTODR) */
623#define UCC_SLOW_TOD 0x8000
624#define UCC_FAST_TOD 0x8000
625
626/* UCC Bus Mode Register masks */
627/* Not to be confused with the Bundle Mode Register */
628#define UCC_BMR_GBL 0x20
629#define UCC_BMR_BO_BE 0x10
630#define UCC_BMR_CETM 0x04
631#define UCC_BMR_DTB 0x02
632#define UCC_BMR_BDB 0x01
633
634/* Function code masks */
635#define FC_GBL 0x20
636#define FC_DTB_LCL 0x02
637#define UCC_FAST_FUNCTION_CODE_GBL 0x20
638#define UCC_FAST_FUNCTION_CODE_DTB_LCL 0x02
639#define UCC_FAST_FUNCTION_CODE_BDB_LCL 0x01
640
641#endif /* __KERNEL__ */
642#endif /* _ASM_POWERPC_QE_H */
diff --git a/include/asm-powerpc/qe_ic.h b/include/asm-powerpc/qe_ic.h
deleted file mode 100644
index a779b2c9eaf..00000000000
--- a/include/asm-powerpc/qe_ic.h
+++ /dev/null
@@ -1,130 +0,0 @@
1/*
2 * include/asm-powerpc/qe_ic.h
3 *
4 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
5 *
6 * Authors: Shlomi Gridish <gridish@freescale.com>
7 * Li Yang <leoli@freescale.com>
8 *
9 * Description:
10 * QE IC external definitions and structure.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17#ifndef _ASM_POWERPC_QE_IC_H
18#define _ASM_POWERPC_QE_IC_H
19
20#include <linux/irq.h>
21
22#define NUM_OF_QE_IC_GROUPS 6
23
24/* Flags when we init the QE IC */
25#define QE_IC_SPREADMODE_GRP_W 0x00000001
26#define QE_IC_SPREADMODE_GRP_X 0x00000002
27#define QE_IC_SPREADMODE_GRP_Y 0x00000004
28#define QE_IC_SPREADMODE_GRP_Z 0x00000008
29#define QE_IC_SPREADMODE_GRP_RISCA 0x00000010
30#define QE_IC_SPREADMODE_GRP_RISCB 0x00000020
31
32#define QE_IC_LOW_SIGNAL 0x00000100
33#define QE_IC_HIGH_SIGNAL 0x00000200
34
35#define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH 0x00001000
36#define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH 0x00002000
37#define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH 0x00004000
38#define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH 0x00008000
39#define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH 0x00010000
40#define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH 0x00020000
41#define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH 0x00040000
42#define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH 0x00080000
43#define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH 0x00100000
44#define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH 0x00200000
45#define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH 0x00400000
46#define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH 0x00800000
47#define QE_IC_GRP_W_DEST_SIGNAL_SHIFT (12)
48
49/* QE interrupt sources groups */
50enum qe_ic_grp_id {
51 QE_IC_GRP_W = 0, /* QE interrupt controller group W */
52 QE_IC_GRP_X, /* QE interrupt controller group X */
53 QE_IC_GRP_Y, /* QE interrupt controller group Y */
54 QE_IC_GRP_Z, /* QE interrupt controller group Z */
55 QE_IC_GRP_RISCA, /* QE interrupt controller RISC group A */
56 QE_IC_GRP_RISCB /* QE interrupt controller RISC group B */
57};
58
59void qe_ic_init(struct device_node *node, unsigned int flags,
60 void (*low_handler)(unsigned int irq, struct irq_desc *desc),
61 void (*high_handler)(unsigned int irq, struct irq_desc *desc));
62void qe_ic_set_highest_priority(unsigned int virq, int high);
63int qe_ic_set_priority(unsigned int virq, unsigned int priority);
64int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);
65
66struct qe_ic;
67unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic);
68unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic);
69
70static inline void qe_ic_cascade_low_ipic(unsigned int irq,
71 struct irq_desc *desc)
72{
73 struct qe_ic *qe_ic = desc->handler_data;
74 unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
75
76 if (cascade_irq != NO_IRQ)
77 generic_handle_irq(cascade_irq);
78}
79
80static inline void qe_ic_cascade_high_ipic(unsigned int irq,
81 struct irq_desc *desc)
82{
83 struct qe_ic *qe_ic = desc->handler_data;
84 unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
85
86 if (cascade_irq != NO_IRQ)
87 generic_handle_irq(cascade_irq);
88}
89
90static inline void qe_ic_cascade_low_mpic(unsigned int irq,
91 struct irq_desc *desc)
92{
93 struct qe_ic *qe_ic = desc->handler_data;
94 unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
95
96 if (cascade_irq != NO_IRQ)
97 generic_handle_irq(cascade_irq);
98
99 desc->chip->eoi(irq);
100}
101
102static inline void qe_ic_cascade_high_mpic(unsigned int irq,
103 struct irq_desc *desc)
104{
105 struct qe_ic *qe_ic = desc->handler_data;
106 unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
107
108 if (cascade_irq != NO_IRQ)
109 generic_handle_irq(cascade_irq);
110
111 desc->chip->eoi(irq);
112}
113
114static inline void qe_ic_cascade_muxed_mpic(unsigned int irq,
115 struct irq_desc *desc)
116{
117 struct qe_ic *qe_ic = desc->handler_data;
118 unsigned int cascade_irq;
119
120 cascade_irq = qe_ic_get_high_irq(qe_ic);
121 if (cascade_irq == NO_IRQ)
122 cascade_irq = qe_ic_get_low_irq(qe_ic);
123
124 if (cascade_irq != NO_IRQ)
125 generic_handle_irq(cascade_irq);
126
127 desc->chip->eoi(irq);
128}
129
130#endif /* _ASM_POWERPC_QE_IC_H */
diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h
deleted file mode 100644
index c6d1ab65077..00000000000
--- a/include/asm-powerpc/reg.h
+++ /dev/null
@@ -1,788 +0,0 @@
1/*
2 * Contains the definition of registers common to all PowerPC variants.
3 * If a register definition has been changed in a different PowerPC
4 * variant, we will case it in #ifndef XXX ... #endif, and have the
5 * number used in the Programming Environments Manual For 32-Bit
6 * Implementations of the PowerPC Architecture (a.k.a. Green Book) here.
7 */
8
9#ifndef _ASM_POWERPC_REG_H
10#define _ASM_POWERPC_REG_H
11#ifdef __KERNEL__
12
13#include <linux/stringify.h>
14#include <asm/cputable.h>
15
16/* Pickup Book E specific registers. */
17#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
18#include <asm/reg_booke.h>
19#endif /* CONFIG_BOOKE || CONFIG_40x */
20
21#ifdef CONFIG_FSL_EMB_PERFMON
22#include <asm/reg_fsl_emb.h>
23#endif
24
25#ifdef CONFIG_8xx
26#include <asm/reg_8xx.h>
27#endif /* CONFIG_8xx */
28
29#define MSR_SF_LG 63 /* Enable 64 bit mode */
30#define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */
31#define MSR_HV_LG 60 /* Hypervisor state */
32#define MSR_VEC_LG 25 /* Enable AltiVec */
33#define MSR_VSX_LG 23 /* Enable VSX */
34#define MSR_POW_LG 18 /* Enable Power Management */
35#define MSR_WE_LG 18 /* Wait State Enable */
36#define MSR_TGPR_LG 17 /* TLB Update registers in use */
37#define MSR_CE_LG 17 /* Critical Interrupt Enable */
38#define MSR_ILE_LG 16 /* Interrupt Little Endian */
39#define MSR_EE_LG 15 /* External Interrupt Enable */
40#define MSR_PR_LG 14 /* Problem State / Privilege Level */
41#define MSR_FP_LG 13 /* Floating Point enable */
42#define MSR_ME_LG 12 /* Machine Check Enable */
43#define MSR_FE0_LG 11 /* Floating Exception mode 0 */
44#define MSR_SE_LG 10 /* Single Step */
45#define MSR_BE_LG 9 /* Branch Trace */
46#define MSR_DE_LG 9 /* Debug Exception Enable */
47#define MSR_FE1_LG 8 /* Floating Exception mode 1 */
48#define MSR_IP_LG 6 /* Exception prefix 0x000/0xFFF */
49#define MSR_IR_LG 5 /* Instruction Relocate */
50#define MSR_DR_LG 4 /* Data Relocate */
51#define MSR_PE_LG 3 /* Protection Enable */
52#define MSR_PX_LG 2 /* Protection Exclusive Mode */
53#define MSR_PMM_LG 2 /* Performance monitor */
54#define MSR_RI_LG 1 /* Recoverable Exception */
55#define MSR_LE_LG 0 /* Little Endian */
56
57#ifdef __ASSEMBLY__
58#define __MASK(X) (1<<(X))
59#else
60#define __MASK(X) (1UL<<(X))
61#endif
62
63#ifdef CONFIG_PPC64
64#define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */
65#define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 */
66#define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */
67#else
68/* so tests for these bits fail on 32-bit */
69#define MSR_SF 0
70#define MSR_ISF 0
71#define MSR_HV 0
72#endif
73
74#define MSR_VEC __MASK(MSR_VEC_LG) /* Enable AltiVec */
75#define MSR_VSX __MASK(MSR_VSX_LG) /* Enable VSX */
76#define MSR_POW __MASK(MSR_POW_LG) /* Enable Power Management */
77#define MSR_WE __MASK(MSR_WE_LG) /* Wait State Enable */
78#define MSR_TGPR __MASK(MSR_TGPR_LG) /* TLB Update registers in use */
79#define MSR_CE __MASK(MSR_CE_LG) /* Critical Interrupt Enable */
80#define MSR_ILE __MASK(MSR_ILE_LG) /* Interrupt Little Endian */
81#define MSR_EE __MASK(MSR_EE_LG) /* External Interrupt Enable */
82#define MSR_PR __MASK(MSR_PR_LG) /* Problem State / Privilege Level */
83#define MSR_FP __MASK(MSR_FP_LG) /* Floating Point enable */
84#define MSR_ME __MASK(MSR_ME_LG) /* Machine Check Enable */
85#define MSR_FE0 __MASK(MSR_FE0_LG) /* Floating Exception mode 0 */
86#define MSR_SE __MASK(MSR_SE_LG) /* Single Step */
87#define MSR_BE __MASK(MSR_BE_LG) /* Branch Trace */
88#define MSR_DE __MASK(MSR_DE_LG) /* Debug Exception Enable */
89#define MSR_FE1 __MASK(MSR_FE1_LG) /* Floating Exception mode 1 */
90#define MSR_IP __MASK(MSR_IP_LG) /* Exception prefix 0x000/0xFFF */
91#define MSR_IR __MASK(MSR_IR_LG) /* Instruction Relocate */
92#define MSR_DR __MASK(MSR_DR_LG) /* Data Relocate */
93#define MSR_PE __MASK(MSR_PE_LG) /* Protection Enable */
94#define MSR_PX __MASK(MSR_PX_LG) /* Protection Exclusive Mode */
95#ifndef MSR_PMM
96#define MSR_PMM __MASK(MSR_PMM_LG) /* Performance monitor */
97#endif
98#define MSR_RI __MASK(MSR_RI_LG) /* Recoverable Exception */
99#define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */
100
101#ifdef CONFIG_PPC64
102#define MSR_ MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV
103#define MSR_KERNEL MSR_ | MSR_SF
104
105#define MSR_USER32 MSR_ | MSR_PR | MSR_EE
106#define MSR_USER64 MSR_USER32 | MSR_SF
107
108#else /* 32-bit */
109/* Default MSR for kernel mode. */
110#ifndef MSR_KERNEL /* reg_booke.h also defines this */
111#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR)
112#endif
113
114#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE)
115#endif
116
117/* Floating Point Status and Control Register (FPSCR) Fields */
118#define FPSCR_FX 0x80000000 /* FPU exception summary */
119#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
120#define FPSCR_VX 0x20000000 /* Invalid operation summary */
121#define FPSCR_OX 0x10000000 /* Overflow exception summary */
122#define FPSCR_UX 0x08000000 /* Underflow exception summary */
123#define FPSCR_ZX 0x04000000 /* Zero-divide exception summary */
124#define FPSCR_XX 0x02000000 /* Inexact exception summary */
125#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */
126#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
127#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */
128#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */
129#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */
130#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */
131#define FPSCR_FR 0x00040000 /* Fraction rounded */
132#define FPSCR_FI 0x00020000 /* Fraction inexact */
133#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */
134#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */
135#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */
136#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */
137#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */
138#define FPSCR_VE 0x00000080 /* Invalid op exception enable */
139#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */
140#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */
141#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */
142#define FPSCR_XE 0x00000008 /* FP inexact exception enable */
143#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
144#define FPSCR_RN 0x00000003 /* FPU rounding control */
145
146/* Special Purpose Registers (SPRNs)*/
147#define SPRN_CTR 0x009 /* Count Register */
148#define SPRN_DSCR 0x11
149#define SPRN_CTRLF 0x088
150#define SPRN_CTRLT 0x098
151#define CTRL_CT 0xc0000000 /* current thread */
152#define CTRL_CT0 0x80000000 /* thread 0 */
153#define CTRL_CT1 0x40000000 /* thread 1 */
154#define CTRL_TE 0x00c00000 /* thread enable */
155#define CTRL_RUNLATCH 0x1
156#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
157#define DABR_TRANSLATION (1UL << 2)
158#define SPRN_DABR2 0x13D /* e300 */
159#define SPRN_DABRX 0x3F7 /* Data Address Breakpoint Register Extension */
160#define DABRX_USER (1UL << 0)
161#define DABRX_KERNEL (1UL << 1)
162#define SPRN_DAR 0x013 /* Data Address Register */
163#define SPRN_DBCR 0x136 /* e300 Data Breakpoint Control Reg */
164#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
165#define DSISR_NOHPTE 0x40000000 /* no translation found */
166#define DSISR_PROTFAULT 0x08000000 /* protection fault */
167#define DSISR_ISSTORE 0x02000000 /* access was a store */
168#define DSISR_DABRMATCH 0x00400000 /* hit data breakpoint */
169#define DSISR_NOSEGMENT 0x00200000 /* STAB/SLB miss */
170#define SPRN_TBRL 0x10C /* Time Base Read Lower Register (user, R/O) */
171#define SPRN_TBRU 0x10D /* Time Base Read Upper Register (user, R/O) */
172#define SPRN_TBWL 0x11C /* Time Base Lower Register (super, R/W) */
173#define SPRN_TBWU 0x11D /* Time Base Upper Register (super, R/W) */
174#define SPRN_SPURR 0x134 /* Scaled PURR */
175#define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */
176#define SPRN_LPCR 0x13E /* LPAR Control Register */
177#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
178#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
179#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */
180#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */
181#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */
182#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */
183#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */
184#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */
185#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */
186#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */
187#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */
188#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */
189#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */
190#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */
191#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */
192#define SPRN_DBAT7U 0x23E /* Data BAT 7 Upper Register */
193
194#define SPRN_DEC 0x016 /* Decrement Register */
195#define SPRN_DER 0x095 /* Debug Enable Regsiter */
196#define DER_RSTE 0x40000000 /* Reset Interrupt */
197#define DER_CHSTPE 0x20000000 /* Check Stop */
198#define DER_MCIE 0x10000000 /* Machine Check Interrupt */
199#define DER_EXTIE 0x02000000 /* External Interrupt */
200#define DER_ALIE 0x01000000 /* Alignment Interrupt */
201#define DER_PRIE 0x00800000 /* Program Interrupt */
202#define DER_FPUVIE 0x00400000 /* FP Unavailable Interrupt */
203#define DER_DECIE 0x00200000 /* Decrementer Interrupt */
204#define DER_SYSIE 0x00040000 /* System Call Interrupt */
205#define DER_TRE 0x00020000 /* Trace Interrupt */
206#define DER_SEIE 0x00004000 /* FP SW Emulation Interrupt */
207#define DER_ITLBMSE 0x00002000 /* Imp. Spec. Instruction TLB Miss */
208#define DER_ITLBERE 0x00001000 /* Imp. Spec. Instruction TLB Error */
209#define DER_DTLBMSE 0x00000800 /* Imp. Spec. Data TLB Miss */
210#define DER_DTLBERE 0x00000400 /* Imp. Spec. Data TLB Error */
211#define DER_LBRKE 0x00000008 /* Load/Store Breakpoint Interrupt */
212#define DER_IBRKE 0x00000004 /* Instruction Breakpoint Interrupt */
213#define DER_EBRKE 0x00000002 /* External Breakpoint Interrupt */
214#define DER_DPIE 0x00000001 /* Dev. Port Nonmaskable Request */
215#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
216#define SPRN_EAR 0x11A /* External Address Register */
217#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */
218#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */
219#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */
220#define HID0_EMCP (1<<31) /* Enable Machine Check pin */
221#define HID0_EBA (1<<29) /* Enable Bus Address Parity */
222#define HID0_EBD (1<<28) /* Enable Bus Data Parity */
223#define HID0_SBCLK (1<<27)
224#define HID0_EICE (1<<26)
225#define HID0_TBEN (1<<26) /* Timebase enable - 745x */
226#define HID0_ECLK (1<<25)
227#define HID0_PAR (1<<24)
228#define HID0_STEN (1<<24) /* Software table search enable - 745x */
229#define HID0_HIGH_BAT (1<<23) /* Enable high BATs - 7455 */
230#define HID0_DOZE (1<<23)
231#define HID0_NAP (1<<22)
232#define HID0_SLEEP (1<<21)
233#define HID0_DPM (1<<20)
234#define HID0_BHTCLR (1<<18) /* Clear branch history table - 7450 */
235#define HID0_XAEN (1<<17) /* Extended addressing enable - 7450 */
236#define HID0_NHR (1<<16) /* Not hard reset (software bit-7450)*/
237#define HID0_ICE (1<<15) /* Instruction Cache Enable */
238#define HID0_DCE (1<<14) /* Data Cache Enable */
239#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
240#define HID0_DLOCK (1<<12) /* Data Cache Lock */
241#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
242#define HID0_DCI (1<<10) /* Data Cache Invalidate */
243#define HID0_SPD (1<<9) /* Speculative disable */
244#define HID0_DAPUEN (1<<8) /* Debug APU enable */
245#define HID0_SGE (1<<7) /* Store Gathering Enable */
246#define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */
247#define HID0_DCFA (1<<6) /* Data Cache Flush Assist */
248#define HID0_LRSTK (1<<4) /* Link register stack - 745x */
249#define HID0_BTIC (1<<5) /* Branch Target Instr Cache Enable */
250#define HID0_ABE (1<<3) /* Address Broadcast Enable */
251#define HID0_FOLD (1<<3) /* Branch Folding enable - 745x */
252#define HID0_BHTE (1<<2) /* Branch History Table Enable */
253#define HID0_BTCD (1<<1) /* Branch target cache disable */
254#define HID0_NOPDST (1<<1) /* No-op dst, dstt, etc. instr. */
255#define HID0_NOPTI (1<<0) /* No-op dcbt and dcbst instr. */
256
257#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
258#define HID1_EMCP (1<<31) /* 7450 Machine Check Pin Enable */
259#define HID1_DFS (1<<22) /* 7447A Dynamic Frequency Scaling */
260#define HID1_PC0 (1<<16) /* 7450 PLL_CFG[0] */
261#define HID1_PC1 (1<<15) /* 7450 PLL_CFG[1] */
262#define HID1_PC2 (1<<14) /* 7450 PLL_CFG[2] */
263#define HID1_PC3 (1<<13) /* 7450 PLL_CFG[3] */
264#define HID1_SYNCBE (1<<11) /* 7450 ABE for sync, eieio */
265#define HID1_ABE (1<<10) /* 7450 Address Broadcast Enable */
266#define HID1_PS (1<<16) /* 750FX PLL selection */
267#define SPRN_HID2 0x3F8 /* Hardware Implementation Register 2 */
268#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
269#define SPRN_IABR2 0x3FA /* 83xx */
270#define SPRN_IBCR 0x135 /* 83xx Insn Breakpoint Control Reg */
271#define SPRN_HID4 0x3F4 /* 970 HID4 */
272#define SPRN_HID5 0x3F6 /* 970 HID5 */
273#define SPRN_HID6 0x3F9 /* BE HID 6 */
274#define HID6_LB (0x0F<<12) /* Concurrent Large Page Modes */
275#define HID6_DLP (1<<20) /* Disable all large page modes (4K only) */
276#define SPRN_TSC_CELL 0x399 /* Thread switch control on Cell */
277#define TSC_CELL_DEC_ENABLE_0 0x400000 /* Decrementer Interrupt */
278#define TSC_CELL_DEC_ENABLE_1 0x200000 /* Decrementer Interrupt */
279#define TSC_CELL_EE_ENABLE 0x100000 /* External Interrupt */
280#define TSC_CELL_EE_BOOST 0x080000 /* External Interrupt Boost */
281#define SPRN_TSC 0x3FD /* Thread switch control on others */
282#define SPRN_TST 0x3FC /* Thread switch timeout on others */
283#if !defined(SPRN_IAC1) && !defined(SPRN_IAC2)
284#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
285#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */
286#endif
287#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */
288#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */
289#define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */
290#define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */
291#define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */
292#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */
293#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */
294#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */
295#define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */
296#define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */
297#define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */
298#define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */
299#define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */
300#define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */
301#define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */
302#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */
303#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
304#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
305#define SPRN_ICTRL 0x3F3 /* 1011 7450 icache and interrupt ctrl */
306#define ICTRL_EICE 0x08000000 /* enable icache parity errs */
307#define ICTRL_EDC 0x04000000 /* enable dcache parity errs */
308#define ICTRL_EICP 0x00000100 /* enable icache par. check */
309#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
310#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
311#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
312#define SPRN_L2CR2 0x3f8
313#define L2CR_L2E 0x80000000 /* L2 enable */
314#define L2CR_L2PE 0x40000000 /* L2 parity enable */
315#define L2CR_L2SIZ_MASK 0x30000000 /* L2 size mask */
316#define L2CR_L2SIZ_256KB 0x10000000 /* L2 size 256KB */
317#define L2CR_L2SIZ_512KB 0x20000000 /* L2 size 512KB */
318#define L2CR_L2SIZ_1MB 0x30000000 /* L2 size 1MB */
319#define L2CR_L2CLK_MASK 0x0e000000 /* L2 clock mask */
320#define L2CR_L2CLK_DISABLED 0x00000000 /* L2 clock disabled */
321#define L2CR_L2CLK_DIV1 0x02000000 /* L2 clock / 1 */
322#define L2CR_L2CLK_DIV1_5 0x04000000 /* L2 clock / 1.5 */
323#define L2CR_L2CLK_DIV2 0x08000000 /* L2 clock / 2 */
324#define L2CR_L2CLK_DIV2_5 0x0a000000 /* L2 clock / 2.5 */
325#define L2CR_L2CLK_DIV3 0x0c000000 /* L2 clock / 3 */
326#define L2CR_L2RAM_MASK 0x01800000 /* L2 RAM type mask */
327#define L2CR_L2RAM_FLOW 0x00000000 /* L2 RAM flow through */
328#define L2CR_L2RAM_PIPE 0x01000000 /* L2 RAM pipelined */
329#define L2CR_L2RAM_PIPE_LW 0x01800000 /* L2 RAM pipelined latewr */
330#define L2CR_L2DO 0x00400000 /* L2 data only */
331#define L2CR_L2I 0x00200000 /* L2 global invalidate */
332#define L2CR_L2CTL 0x00100000 /* L2 RAM control */
333#define L2CR_L2WT 0x00080000 /* L2 write-through */
334#define L2CR_L2TS 0x00040000 /* L2 test support */
335#define L2CR_L2OH_MASK 0x00030000 /* L2 output hold mask */
336#define L2CR_L2OH_0_5 0x00000000 /* L2 output hold 0.5 ns */
337#define L2CR_L2OH_1_0 0x00010000 /* L2 output hold 1.0 ns */
338#define L2CR_L2SL 0x00008000 /* L2 DLL slow */
339#define L2CR_L2DF 0x00004000 /* L2 differential clock */
340#define L2CR_L2BYP 0x00002000 /* L2 DLL bypass */
341#define L2CR_L2IP 0x00000001 /* L2 GI in progress */
342#define L2CR_L2IO_745x 0x00100000 /* L2 instr. only (745x) */
343#define L2CR_L2DO_745x 0x00010000 /* L2 data only (745x) */
344#define L2CR_L2REP_745x 0x00001000 /* L2 repl. algorithm (745x) */
345#define L2CR_L2HWF_745x 0x00000800 /* L2 hardware flush (745x) */
346#define SPRN_L3CR 0x3FA /* Level 3 Cache Control Regsiter */
347#define L3CR_L3E 0x80000000 /* L3 enable */
348#define L3CR_L3PE 0x40000000 /* L3 data parity enable */
349#define L3CR_L3APE 0x20000000 /* L3 addr parity enable */
350#define L3CR_L3SIZ 0x10000000 /* L3 size */
351#define L3CR_L3CLKEN 0x08000000 /* L3 clock enable */
352#define L3CR_L3RES 0x04000000 /* L3 special reserved bit */
353#define L3CR_L3CLKDIV 0x03800000 /* L3 clock divisor */
354#define L3CR_L3IO 0x00400000 /* L3 instruction only */
355#define L3CR_L3SPO 0x00040000 /* L3 sample point override */
356#define L3CR_L3CKSP 0x00030000 /* L3 clock sample point */
357#define L3CR_L3PSP 0x0000e000 /* L3 P-clock sample point */
358#define L3CR_L3REP 0x00001000 /* L3 replacement algorithm */
359#define L3CR_L3HWF 0x00000800 /* L3 hardware flush */
360#define L3CR_L3I 0x00000400 /* L3 global invalidate */
361#define L3CR_L3RT 0x00000300 /* L3 SRAM type */
362#define L3CR_L3NIRCA 0x00000080 /* L3 non-integer ratio clock adj. */
363#define L3CR_L3DO 0x00000040 /* L3 data only mode */
364#define L3CR_PMEN 0x00000004 /* L3 private memory enable */
365#define L3CR_PMSIZ 0x00000001 /* L3 private memory size */
366
367#define SPRN_MSSCR0 0x3f6 /* Memory Subsystem Control Register 0 */
368#define SPRN_MSSSR0 0x3f7 /* Memory Subsystem Status Register 1 */
369#define SPRN_LDSTCR 0x3f8 /* Load/Store control register */
370#define SPRN_LDSTDB 0x3f4 /* */
371#define SPRN_LR 0x008 /* Link Register */
372#ifndef SPRN_PIR
373#define SPRN_PIR 0x3FF /* Processor Identification Register */
374#endif
375#define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */
376#define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */
377#define SPRN_PURR 0x135 /* Processor Utilization of Resources Reg */
378#define SPRN_PVR 0x11F /* Processor Version Register */
379#define SPRN_RPA 0x3D6 /* Required Physical Address Register */
380#define SPRN_SDA 0x3BF /* Sampled Data Address Register */
381#define SPRN_SDR1 0x019 /* MMU Hash Base Register */
382#define SPRN_ASR 0x118 /* Address Space Register */
383#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
384#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
385#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
386#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
387#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
388#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */
389#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */
390#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */
391#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */
392#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
393#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
394#define SRR1_WAKEMASK 0x00380000 /* reason for wakeup */
395#define SRR1_WAKERESET 0x00380000 /* System reset */
396#define SRR1_WAKESYSERR 0x00300000 /* System error */
397#define SRR1_WAKEEE 0x00200000 /* External interrupt */
398#define SRR1_WAKEMT 0x00280000 /* mtctrl */
399#define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */
400#define SRR1_WAKETHERM 0x00100000 /* Thermal management interrupt */
401#define SPRN_HSRR0 0x13A /* Save/Restore Register 0 */
402#define SPRN_HSRR1 0x13B /* Save/Restore Register 1 */
403
404#define SPRN_TBCTL 0x35f /* PA6T Timebase control register */
405#define TBCTL_FREEZE 0x0000000000000000ull /* Freeze all tbs */
406#define TBCTL_RESTART 0x0000000100000000ull /* Restart all tbs */
407#define TBCTL_UPDATE_UPPER 0x0000000200000000ull /* Set upper 32 bits */
408#define TBCTL_UPDATE_LOWER 0x0000000300000000ull /* Set lower 32 bits */
409
410#ifndef SPRN_SVR
411#define SPRN_SVR 0x11E /* System Version Register */
412#endif
413#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */
414/* these bits were defined in inverted endian sense originally, ugh, confusing */
415#define THRM1_TIN (1 << 31)
416#define THRM1_TIV (1 << 30)
417#define THRM1_THRES(x) ((x&0x7f)<<23)
418#define THRM3_SITV(x) ((x&0x3fff)<<1)
419#define THRM1_TID (1<<2)
420#define THRM1_TIE (1<<1)
421#define THRM1_V (1<<0)
422#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */
423#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
424#define THRM3_E (1<<0)
425#define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */
426#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
427#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
428#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */
429#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */
430#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */
431#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */
432#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
433#define SPRN_VRSAVE 0x100 /* Vector Register Save Register */
434#define SPRN_XER 0x001 /* Fixed Point Exception Register */
435
436#define SPRN_SCOMC 0x114 /* SCOM Access Control */
437#define SPRN_SCOMD 0x115 /* SCOM Access DATA */
438
439/* Performance monitor SPRs */
440#ifdef CONFIG_PPC64
441#define SPRN_MMCR0 795
442#define MMCR0_FC 0x80000000UL /* freeze counters */
443#define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */
444#define MMCR0_KERNEL_DISABLE MMCR0_FCS
445#define MMCR0_FCP 0x20000000UL /* freeze in problem state */
446#define MMCR0_PROBLEM_DISABLE MMCR0_FCP
447#define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */
448#define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */
449#define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */
450#define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */
451#define MMCR0_TBEE 0x00400000UL /* time base exception enable */
452#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
453#define MMCR0_PMCjCE 0x00004000UL /* PMCj count enable*/
454#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
455#define MMCR0_PMAO 0x00000080UL /* performance monitor alert has occurred, set to 0 after handling exception */
456#define MMCR0_SHRFC 0x00000040UL /* SHRre freeze conditions between threads */
457#define MMCR0_FCTI 0x00000008UL /* freeze counters in tags inactive mode */
458#define MMCR0_FCTA 0x00000004UL /* freeze counters in tags active mode */
459#define MMCR0_FCWAIT 0x00000002UL /* freeze counter in WAIT state */
460#define MMCR0_FCHV 0x00000001UL /* freeze conditions in hypervisor mode */
461#define SPRN_MMCR1 798
462#define SPRN_MMCRA 0x312
463#define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */
464#define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */
465#define MMCRA_SLOT 0x07000000UL /* SLOT bits (37-39) */
466#define MMCRA_SLOT_SHIFT 24
467#define MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
468#define POWER6_MMCRA_SIHV 0x0000040000000000ULL
469#define POWER6_MMCRA_SIPR 0x0000020000000000ULL
470#define POWER6_MMCRA_THRM 0x00000020UL
471#define POWER6_MMCRA_OTHER 0x0000000EUL
472#define SPRN_PMC1 787
473#define SPRN_PMC2 788
474#define SPRN_PMC3 789
475#define SPRN_PMC4 790
476#define SPRN_PMC5 791
477#define SPRN_PMC6 792
478#define SPRN_PMC7 793
479#define SPRN_PMC8 794
480#define SPRN_SIAR 780
481#define SPRN_SDAR 781
482
483#define SPRN_PA6T_MMCR0 795
484#define PA6T_MMCR0_EN0 0x0000000000000001UL
485#define PA6T_MMCR0_EN1 0x0000000000000002UL
486#define PA6T_MMCR0_EN2 0x0000000000000004UL
487#define PA6T_MMCR0_EN3 0x0000000000000008UL
488#define PA6T_MMCR0_EN4 0x0000000000000010UL
489#define PA6T_MMCR0_EN5 0x0000000000000020UL
490#define PA6T_MMCR0_SUPEN 0x0000000000000040UL
491#define PA6T_MMCR0_PREN 0x0000000000000080UL
492#define PA6T_MMCR0_HYPEN 0x0000000000000100UL
493#define PA6T_MMCR0_FCM0 0x0000000000000200UL
494#define PA6T_MMCR0_FCM1 0x0000000000000400UL
495#define PA6T_MMCR0_INTGEN 0x0000000000000800UL
496#define PA6T_MMCR0_INTEN0 0x0000000000001000UL
497#define PA6T_MMCR0_INTEN1 0x0000000000002000UL
498#define PA6T_MMCR0_INTEN2 0x0000000000004000UL
499#define PA6T_MMCR0_INTEN3 0x0000000000008000UL
500#define PA6T_MMCR0_INTEN4 0x0000000000010000UL
501#define PA6T_MMCR0_INTEN5 0x0000000000020000UL
502#define PA6T_MMCR0_DISCNT 0x0000000000040000UL
503#define PA6T_MMCR0_UOP 0x0000000000080000UL
504#define PA6T_MMCR0_TRG 0x0000000000100000UL
505#define PA6T_MMCR0_TRGEN 0x0000000000200000UL
506#define PA6T_MMCR0_TRGREG 0x0000000001600000UL
507#define PA6T_MMCR0_SIARLOG 0x0000000002000000UL
508#define PA6T_MMCR0_SDARLOG 0x0000000004000000UL
509#define PA6T_MMCR0_PROEN 0x0000000008000000UL
510#define PA6T_MMCR0_PROLOG 0x0000000010000000UL
511#define PA6T_MMCR0_DAMEN2 0x0000000020000000UL
512#define PA6T_MMCR0_DAMEN3 0x0000000040000000UL
513#define PA6T_MMCR0_DAMEN4 0x0000000080000000UL
514#define PA6T_MMCR0_DAMEN5 0x0000000100000000UL
515#define PA6T_MMCR0_DAMSEL2 0x0000000200000000UL
516#define PA6T_MMCR0_DAMSEL3 0x0000000400000000UL
517#define PA6T_MMCR0_DAMSEL4 0x0000000800000000UL
518#define PA6T_MMCR0_DAMSEL5 0x0000001000000000UL
519#define PA6T_MMCR0_HANDDIS 0x0000002000000000UL
520#define PA6T_MMCR0_PCTEN 0x0000004000000000UL
521#define PA6T_MMCR0_SOCEN 0x0000008000000000UL
522#define PA6T_MMCR0_SOCMOD 0x0000010000000000UL
523
524#define SPRN_PA6T_MMCR1 798
525#define PA6T_MMCR1_ES2 0x00000000000000ffUL
526#define PA6T_MMCR1_ES3 0x000000000000ff00UL
527#define PA6T_MMCR1_ES4 0x0000000000ff0000UL
528#define PA6T_MMCR1_ES5 0x00000000ff000000UL
529
530#define SPRN_PA6T_UPMC0 771 /* User PerfMon Counter 0 */
531#define SPRN_PA6T_UPMC1 772 /* ... */
532#define SPRN_PA6T_UPMC2 773
533#define SPRN_PA6T_UPMC3 774
534#define SPRN_PA6T_UPMC4 775
535#define SPRN_PA6T_UPMC5 776
536#define SPRN_PA6T_UMMCR0 779 /* User Monitor Mode Control Register 0 */
537#define SPRN_PA6T_SIAR 780 /* Sampled Instruction Address */
538#define SPRN_PA6T_UMMCR1 782 /* User Monitor Mode Control Register 1 */
539#define SPRN_PA6T_SIER 785 /* Sampled Instruction Event Register */
540#define SPRN_PA6T_PMC0 787
541#define SPRN_PA6T_PMC1 788
542#define SPRN_PA6T_PMC2 789
543#define SPRN_PA6T_PMC3 790
544#define SPRN_PA6T_PMC4 791
545#define SPRN_PA6T_PMC5 792
546#define SPRN_PA6T_TSR0 793 /* Timestamp Register 0 */
547#define SPRN_PA6T_TSR1 794 /* Timestamp Register 1 */
548#define SPRN_PA6T_TSR2 799 /* Timestamp Register 2 */
549#define SPRN_PA6T_TSR3 784 /* Timestamp Register 3 */
550
551#define SPRN_PA6T_IER 981 /* Icache Error Register */
552#define SPRN_PA6T_DER 982 /* Dcache Error Register */
553#define SPRN_PA6T_BER 862 /* BIU Error Address Register */
554#define SPRN_PA6T_MER 849 /* MMU Error Register */
555
556#define SPRN_PA6T_IMA0 880 /* Instruction Match Array 0 */
557#define SPRN_PA6T_IMA1 881 /* ... */
558#define SPRN_PA6T_IMA2 882
559#define SPRN_PA6T_IMA3 883
560#define SPRN_PA6T_IMA4 884
561#define SPRN_PA6T_IMA5 885
562#define SPRN_PA6T_IMA6 886
563#define SPRN_PA6T_IMA7 887
564#define SPRN_PA6T_IMA8 888
565#define SPRN_PA6T_IMA9 889
566#define SPRN_PA6T_BTCR 978 /* Breakpoint and Tagging Control Register */
567#define SPRN_PA6T_IMAAT 979 /* Instruction Match Array Action Table */
568#define SPRN_PA6T_PCCR 1019 /* Power Counter Control Register */
569#define SPRN_BKMK 1020 /* Cell Bookmark Register */
570#define SPRN_PA6T_RPCCR 1021 /* Retire PC Trace Control Register */
571
572
573#else /* 32-bit */
574#define SPRN_MMCR0 952 /* Monitor Mode Control Register 0 */
575#define MMCR0_FC 0x80000000UL /* freeze counters */
576#define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */
577#define MMCR0_FCP 0x20000000UL /* freeze in problem state */
578#define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */
579#define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */
580#define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */
581#define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */
582#define MMCR0_TBEE 0x00400000UL /* time base exception enable */
583#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
584#define MMCR0_PMCnCE 0x00004000UL /* count enable for all but PMC 1*/
585#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
586#define MMCR0_PMC1SEL 0x00001fc0UL /* PMC 1 Event */
587#define MMCR0_PMC2SEL 0x0000003fUL /* PMC 2 Event */
588
589#define SPRN_MMCR1 956
590#define MMCR1_PMC3SEL 0xf8000000UL /* PMC 3 Event */
591#define MMCR1_PMC4SEL 0x07c00000UL /* PMC 4 Event */
592#define MMCR1_PMC5SEL 0x003e0000UL /* PMC 5 Event */
593#define MMCR1_PMC6SEL 0x0001f800UL /* PMC 6 Event */
594#define SPRN_MMCR2 944
595#define SPRN_PMC1 953 /* Performance Counter Register 1 */
596#define SPRN_PMC2 954 /* Performance Counter Register 2 */
597#define SPRN_PMC3 957 /* Performance Counter Register 3 */
598#define SPRN_PMC4 958 /* Performance Counter Register 4 */
599#define SPRN_PMC5 945 /* Performance Counter Register 5 */
600#define SPRN_PMC6 946 /* Performance Counter Register 6 */
601
602#define SPRN_SIAR 955 /* Sampled Instruction Address Register */
603
604/* Bit definitions for MMCR0 and PMC1 / PMC2. */
605#define MMCR0_PMC1_CYCLES (1 << 7)
606#define MMCR0_PMC1_ICACHEMISS (5 << 7)
607#define MMCR0_PMC1_DTLB (6 << 7)
608#define MMCR0_PMC2_DCACHEMISS 0x6
609#define MMCR0_PMC2_CYCLES 0x1
610#define MMCR0_PMC2_ITLB 0x7
611#define MMCR0_PMC2_LOADMISSTIME 0x5
612#endif
613
614/*
615 * An mtfsf instruction with the L bit set. On CPUs that support this a
616 * full 64bits of FPSCR is restored and on other CPUs the L bit is ignored.
617 *
618 * Until binutils gets the new form of mtfsf, hardwire the instruction.
619 */
620#ifdef CONFIG_PPC64
621#define MTFSF_L(REG) \
622 .long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25))
623#else
624#define MTFSF_L(REG) mtfsf 0xff, (REG)
625#endif
626
627/* Processor Version Register (PVR) field extraction */
628
629#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
630#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
631
632#define __is_processor(pv) (PVR_VER(mfspr(SPRN_PVR)) == (pv))
633
634/*
635 * IBM has further subdivided the standard PowerPC 16-bit version and
636 * revision subfields of the PVR for the PowerPC 403s into the following:
637 */
638
639#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */
640#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */
641#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */
642#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */
643#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
644#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
645
646/* Processor Version Numbers */
647
648#define PVR_403GA 0x00200000
649#define PVR_403GB 0x00200100
650#define PVR_403GC 0x00200200
651#define PVR_403GCX 0x00201400
652#define PVR_405GP 0x40110000
653#define PVR_STB03XXX 0x40310000
654#define PVR_NP405H 0x41410000
655#define PVR_NP405L 0x41610000
656#define PVR_601 0x00010000
657#define PVR_602 0x00050000
658#define PVR_603 0x00030000
659#define PVR_603e 0x00060000
660#define PVR_603ev 0x00070000
661#define PVR_603r 0x00071000
662#define PVR_604 0x00040000
663#define PVR_604e 0x00090000
664#define PVR_604r 0x000A0000
665#define PVR_620 0x00140000
666#define PVR_740 0x00080000
667#define PVR_750 PVR_740
668#define PVR_740P 0x10080000
669#define PVR_750P PVR_740P
670#define PVR_7400 0x000C0000
671#define PVR_7410 0x800C0000
672#define PVR_7450 0x80000000
673#define PVR_8540 0x80200000
674#define PVR_8560 0x80200000
675/*
676 * For the 8xx processors, all of them report the same PVR family for
677 * the PowerPC core. The various versions of these processors must be
678 * differentiated by the version number in the Communication Processor
679 * Module (CPM).
680 */
681#define PVR_821 0x00500000
682#define PVR_823 PVR_821
683#define PVR_850 PVR_821
684#define PVR_860 PVR_821
685#define PVR_8240 0x00810100
686#define PVR_8245 0x80811014
687#define PVR_8260 PVR_8240
688
689/* 64-bit processors */
690/* XXX the prefix should be PVR_, we'll do a global sweep to fix it one day */
691#define PV_NORTHSTAR 0x0033
692#define PV_PULSAR 0x0034
693#define PV_POWER4 0x0035
694#define PV_ICESTAR 0x0036
695#define PV_SSTAR 0x0037
696#define PV_POWER4p 0x0038
697#define PV_970 0x0039
698#define PV_POWER5 0x003A
699#define PV_POWER5p 0x003B
700#define PV_970FX 0x003C
701#define PV_630 0x0040
702#define PV_630p 0x0041
703#define PV_970MP 0x0044
704#define PV_970GX 0x0045
705#define PV_BE 0x0070
706#define PV_PA6T 0x0090
707
708/* Macros for setting and retrieving special purpose registers */
709#ifndef __ASSEMBLY__
710#define mfmsr() ({unsigned long rval; \
711 asm volatile("mfmsr %0" : "=r" (rval)); rval;})
712#ifdef CONFIG_PPC64
713#define __mtmsrd(v, l) asm volatile("mtmsrd %0," __stringify(l) \
714 : : "r" (v))
715#define mtmsrd(v) __mtmsrd((v), 0)
716#define mtmsr(v) mtmsrd(v)
717#else
718#define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v))
719#endif
720
721#define mfspr(rn) ({unsigned long rval; \
722 asm volatile("mfspr %0," __stringify(rn) \
723 : "=r" (rval)); rval;})
724#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v))
725
726#ifdef __powerpc64__
727#ifdef CONFIG_PPC_CELL
728#define mftb() ({unsigned long rval; \
729 asm volatile( \
730 "90: mftb %0;\n" \
731 "97: cmpwi %0,0;\n" \
732 " beq- 90b;\n" \
733 "99:\n" \
734 ".section __ftr_fixup,\"a\"\n" \
735 ".align 3\n" \
736 "98:\n" \
737 " .llong %1\n" \
738 " .llong %1\n" \
739 " .llong 97b-98b\n" \
740 " .llong 99b-98b\n" \
741 " .llong 0\n" \
742 " .llong 0\n" \
743 ".previous" \
744 : "=r" (rval) : "i" (CPU_FTR_CELL_TB_BUG)); rval;})
745#else
746#define mftb() ({unsigned long rval; \
747 asm volatile("mftb %0" : "=r" (rval)); rval;})
748#endif /* !CONFIG_PPC_CELL */
749
750#else /* __powerpc64__ */
751
752#define mftbl() ({unsigned long rval; \
753 asm volatile("mftbl %0" : "=r" (rval)); rval;})
754#define mftbu() ({unsigned long rval; \
755 asm volatile("mftbu %0" : "=r" (rval)); rval;})
756#endif /* !__powerpc64__ */
757
758#define mttbl(v) asm volatile("mttbl %0":: "r"(v))
759#define mttbu(v) asm volatile("mttbu %0":: "r"(v))
760
761#ifdef CONFIG_PPC32
762#define mfsrin(v) ({unsigned int rval; \
763 asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \
764 rval;})
765#endif
766
767#define proc_trap() asm volatile("trap")
768
769#ifdef CONFIG_PPC64
770
771extern void ppc64_runlatch_on(void);
772extern void ppc64_runlatch_off(void);
773
774extern unsigned long scom970_read(unsigned int address);
775extern void scom970_write(unsigned int address, unsigned long value);
776
777#else
778#define ppc64_runlatch_on()
779#define ppc64_runlatch_off()
780
781#endif /* CONFIG_PPC64 */
782
783#define __get_SP() ({unsigned long sp; \
784 asm volatile("mr %0,1": "=r" (sp)); sp;})
785
786#endif /* __ASSEMBLY__ */
787#endif /* __KERNEL__ */
788#endif /* _ASM_POWERPC_REG_H */
diff --git a/include/asm-powerpc/reg_8xx.h b/include/asm-powerpc/reg_8xx.h
deleted file mode 100644
index e8ea346b21d..00000000000
--- a/include/asm-powerpc/reg_8xx.h
+++ /dev/null
@@ -1,42 +0,0 @@
1/*
2 * Contains register definitions common to PowerPC 8xx CPUs. Notice
3 */
4#ifndef _ASM_POWERPC_REG_8xx_H
5#define _ASM_POWERPC_REG_8xx_H
6
7/* Cache control on the MPC8xx is provided through some additional
8 * special purpose registers.
9 */
10#define SPRN_IC_CST 560 /* Instruction cache control/status */
11#define SPRN_IC_ADR 561 /* Address needed for some commands */
12#define SPRN_IC_DAT 562 /* Read-only data register */
13#define SPRN_DC_CST 568 /* Data cache control/status */
14#define SPRN_DC_ADR 569 /* Address needed for some commands */
15#define SPRN_DC_DAT 570 /* Read-only data register */
16
17/* Commands. Only the first few are available to the instruction cache.
18*/
19#define IDC_ENABLE 0x02000000 /* Cache enable */
20#define IDC_DISABLE 0x04000000 /* Cache disable */
21#define IDC_LDLCK 0x06000000 /* Load and lock */
22#define IDC_UNLINE 0x08000000 /* Unlock line */
23#define IDC_UNALL 0x0a000000 /* Unlock all */
24#define IDC_INVALL 0x0c000000 /* Invalidate all */
25
26#define DC_FLINE 0x0e000000 /* Flush data cache line */
27#define DC_SFWT 0x01000000 /* Set forced writethrough mode */
28#define DC_CFWT 0x03000000 /* Clear forced writethrough mode */
29#define DC_SLES 0x05000000 /* Set little endian swap mode */
30#define DC_CLES 0x07000000 /* Clear little endian swap mode */
31
32/* Status.
33*/
34#define IDC_ENABLED 0x80000000 /* Cache is enabled */
35#define IDC_CERR1 0x00200000 /* Cache error 1 */
36#define IDC_CERR2 0x00100000 /* Cache error 2 */
37#define IDC_CERR3 0x00080000 /* Cache error 3 */
38
39#define DC_DFWT 0x40000000 /* Data cache is forced write through */
40#define DC_LES 0x20000000 /* Caches are little endian mode */
41
42#endif /* _ASM_POWERPC_REG_8xx_H */
diff --git a/include/asm-powerpc/reg_booke.h b/include/asm-powerpc/reg_booke.h
deleted file mode 100644
index be980f4ee49..00000000000
--- a/include/asm-powerpc/reg_booke.h
+++ /dev/null
@@ -1,501 +0,0 @@
1/*
2 * Contains register definitions common to the Book E PowerPC
3 * specification. Notice that while the IBM-40x series of CPUs
4 * are not true Book E PowerPCs, they borrowed a number of features
5 * before Book E was finalized, and are included here as well. Unfortunatly,
6 * they sometimes used different locations than true Book E CPUs did.
7 */
8#ifdef __KERNEL__
9#ifndef __ASM_POWERPC_REG_BOOKE_H__
10#define __ASM_POWERPC_REG_BOOKE_H__
11
12/* Machine State Register (MSR) Fields */
13#define MSR_UCLE (1<<26) /* User-mode cache lock enable */
14#define MSR_SPE (1<<25) /* Enable SPE */
15#define MSR_DWE (1<<10) /* Debug Wait Enable */
16#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */
17#define MSR_IS MSR_IR /* Instruction Space */
18#define MSR_DS MSR_DR /* Data Space */
19#define MSR_PMM (1<<2) /* Performance monitor mark bit */
20
21/* Default MSR for kernel mode. */
22#if defined (CONFIG_40x)
23#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE)
24#elif defined(CONFIG_BOOKE)
25#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_CE)
26#endif
27
28/* Special Purpose Registers (SPRNs)*/
29#define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
30#define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
31#define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
32#define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
33#define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
34#define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
35#define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
36#define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */
37#define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */
38#define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */
39#define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */
40#define SPRN_DBCR2 0x136 /* Debug Control Register 2 */
41#define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */
42#define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */
43#define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */
44#define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */
45#define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */
46#define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */
47#define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */
48#define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */
49#define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */
50#define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */
51#define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */
52#define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */
53#define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */
54#define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */
55#define SPRN_IVOR10 0x19A /* Interrupt Vector Offset Register 10 */
56#define SPRN_IVOR11 0x19B /* Interrupt Vector Offset Register 11 */
57#define SPRN_IVOR12 0x19C /* Interrupt Vector Offset Register 12 */
58#define SPRN_IVOR13 0x19D /* Interrupt Vector Offset Register 13 */
59#define SPRN_IVOR14 0x19E /* Interrupt Vector Offset Register 14 */
60#define SPRN_IVOR15 0x19F /* Interrupt Vector Offset Register 15 */
61#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
62#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
63#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
64#define SPRN_L1CFG0 0x203 /* L1 Cache Configure Register 0 */
65#define SPRN_L1CFG1 0x204 /* L1 Cache Configure Register 1 */
66#define SPRN_ATB 0x20E /* Alternate Time Base */
67#define SPRN_ATBL 0x20E /* Alternate Time Base Lower */
68#define SPRN_ATBU 0x20F /* Alternate Time Base Upper */
69#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
70#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
71#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */
72#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
73#define SPRN_IVOR36 0x214 /* Interrupt Vector Offset Register 36 */
74#define SPRN_IVOR37 0x215 /* Interrupt Vector Offset Register 37 */
75#define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */
76#define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */
77#define SPRN_MCSR 0x23C /* Machine Check Status Register */
78#define SPRN_MCAR 0x23D /* Machine Check Address Register */
79#define SPRN_DSRR0 0x23E /* Debug Save and Restore Register 0 */
80#define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */
81#define SPRN_SPRG8 0x25C /* Special Purpose Register General 8 */
82#define SPRN_SPRG9 0x25D /* Special Purpose Register General 9 */
83#define SPRN_L1CSR2 0x25E /* L1 Cache Control and Status Register 2 */
84#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
85#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
86#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
87#define SPRN_MAS3 0x273 /* MMU Assist Register 3 */
88#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
89#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */
90#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
91#define SPRN_PID1 0x279 /* Process ID Register 1 */
92#define SPRN_PID2 0x27A /* Process ID Register 2 */
93#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
94#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */
95#define SPRN_EPR 0x2BE /* External Proxy Register */
96#define SPRN_CCR1 0x378 /* Core Configuration Register 1 */
97#define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */
98#define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */
99#define SPRN_MMUCR 0x3B2 /* MMU Control Register */
100#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */
101#define SPRN_EPLC 0x3B3 /* External Process ID Load Context */
102#define SPRN_EPSC 0x3B4 /* External Process ID Store Context */
103#define SPRN_SGR 0x3B9 /* Storage Guarded Register */
104#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
105#define SPRN_SLER 0x3BB /* Little-endian real mode */
106#define SPRN_SU0R 0x3BC /* "User 0" real mode (40x) */
107#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
108#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */
109#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
110#define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */
111#define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */
112#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
113#define SPRN_BUCSR 0x3F5 /* Branch Unit Control and Status */
114#define SPRN_L2CSR0 0x3F9 /* L2 Data Cache Control and Status Register 0 */
115#define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status Register 1 */
116#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
117#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
118#define SPRN_SVR 0x3FF /* System Version Register */
119
120/*
121 * SPRs which have conflicting definitions on true Book E versus classic,
122 * or IBM 40x.
123 */
124#ifdef CONFIG_BOOKE
125#define SPRN_PID 0x030 /* Process ID */
126#define SPRN_PID0 SPRN_PID/* Process ID Register 0 */
127#define SPRN_CSRR0 0x03A /* Critical Save and Restore Register 0 */
128#define SPRN_CSRR1 0x03B /* Critical Save and Restore Register 1 */
129#define SPRN_DEAR 0x03D /* Data Error Address Register */
130#define SPRN_ESR 0x03E /* Exception Syndrome Register */
131#define SPRN_PIR 0x11E /* Processor Identification Register */
132#define SPRN_DBSR 0x130 /* Debug Status Register */
133#define SPRN_DBCR0 0x134 /* Debug Control Register 0 */
134#define SPRN_DBCR1 0x135 /* Debug Control Register 1 */
135#define SPRN_IAC1 0x138 /* Instruction Address Compare 1 */
136#define SPRN_IAC2 0x139 /* Instruction Address Compare 2 */
137#define SPRN_DAC1 0x13C /* Data Address Compare 1 */
138#define SPRN_DAC2 0x13D /* Data Address Compare 2 */
139#define SPRN_TSR 0x150 /* Timer Status Register */
140#define SPRN_TCR 0x154 /* Timer Control Register */
141#endif /* Book E */
142#ifdef CONFIG_40x
143#define SPRN_PID 0x3B1 /* Process ID */
144#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
145#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
146#define SPRN_DEAR 0x3D5 /* Data Error Address Register */
147#define SPRN_TSR 0x3D8 /* Timer Status Register */
148#define SPRN_TCR 0x3DA /* Timer Control Register */
149#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
150#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
151#define SPRN_DBSR 0x3F0 /* Debug Status Register */
152#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
153#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */
154#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
155#define SPRN_CSRR0 SPRN_SRR2 /* Critical Save and Restore Register 0 */
156#define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */
157#endif
158
159/* Bit definitions for CCR1. */
160#define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
161#define CCR1_TCS 0x00000080 /* Timer Clock Select */
162
163/* Bit definitions for the MCSR. */
164#define MCSR_MCS 0x80000000 /* Machine Check Summary */
165#define MCSR_IB 0x40000000 /* Instruction PLB Error */
166#define MCSR_DRB 0x20000000 /* Data Read PLB Error */
167#define MCSR_DWB 0x10000000 /* Data Write PLB Error */
168#define MCSR_TLBP 0x08000000 /* TLB Parity Error */
169#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
170#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
171#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
172#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
173
174#ifdef CONFIG_E500
175#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */
176#define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */
177#define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */
178#define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */
179#define MCSR_BUS_IAERR 0x00000080UL /* Instruction Address Error */
180#define MCSR_BUS_RAERR 0x00000040UL /* Read Address Error */
181#define MCSR_BUS_WAERR 0x00000020UL /* Write Address Error */
182#define MCSR_BUS_IBERR 0x00000010UL /* Instruction Data Error */
183#define MCSR_BUS_RBERR 0x00000008UL /* Read Data Bus Error */
184#define MCSR_BUS_WBERR 0x00000004UL /* Write Data Bus Error */
185#define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */
186#define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */
187
188/* e500 parts may set unused bits in MCSR; mask these off */
189#define MCSR_MASK (MCSR_MCP | MCSR_ICPERR | MCSR_DCP_PERR | \
190 MCSR_DCPERR | MCSR_BUS_IAERR | MCSR_BUS_RAERR | \
191 MCSR_BUS_WAERR | MCSR_BUS_IBERR | MCSR_BUS_RBERR | \
192 MCSR_BUS_WBERR | MCSR_BUS_IPERR | MCSR_BUS_RPERR)
193#endif
194#ifdef CONFIG_E200
195#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */
196#define MCSR_CP_PERR 0x20000000UL /* Cache Push Parity Error */
197#define MCSR_CPERR 0x10000000UL /* Cache Parity Error */
198#define MCSR_EXCP_ERR 0x08000000UL /* ISI, ITLB, or Bus Error on 1st insn
199 fetch for an exception handler */
200#define MCSR_BUS_IRERR 0x00000010UL /* Read Bus Error on instruction fetch*/
201#define MCSR_BUS_DRERR 0x00000008UL /* Read Bus Error on data load */
202#define MCSR_BUS_WRERR 0x00000004UL /* Write Bus Error on buffered
203 store or cache line push */
204
205/* e200 parts may set unused bits in MCSR; mask these off */
206#define MCSR_MASK (MCSR_MCP | MCSR_CP_PERR | MCSR_CPERR | \
207 MCSR_EXCP_ERR | MCSR_BUS_IRERR | MCSR_BUS_DRERR | \
208 MCSR_BUS_WRERR)
209#endif
210
211/* Bit definitions for the DBSR. */
212/*
213 * DBSR bits which have conflicting definitions on true Book E versus IBM 40x.
214 */
215#ifdef CONFIG_BOOKE
216#define DBSR_IC 0x08000000 /* Instruction Completion */
217#define DBSR_BT 0x04000000 /* Branch Taken */
218#define DBSR_IRPT 0x02000000 /* Exception Debug Event */
219#define DBSR_TIE 0x01000000 /* Trap Instruction Event */
220#define DBSR_IAC1 0x00800000 /* Instr Address Compare 1 Event */
221#define DBSR_IAC2 0x00400000 /* Instr Address Compare 2 Event */
222#define DBSR_IAC3 0x00200000 /* Instr Address Compare 3 Event */
223#define DBSR_IAC4 0x00100000 /* Instr Address Compare 4 Event */
224#define DBSR_DAC1R 0x00080000 /* Data Addr Compare 1 Read Event */
225#define DBSR_DAC1W 0x00040000 /* Data Addr Compare 1 Write Event */
226#define DBSR_DAC2R 0x00020000 /* Data Addr Compare 2 Read Event */
227#define DBSR_DAC2W 0x00010000 /* Data Addr Compare 2 Write Event */
228#define DBSR_RET 0x00008000 /* Return Debug Event */
229#define DBSR_CIRPT 0x00000040 /* Critical Interrupt Taken Event */
230#define DBSR_CRET 0x00000020 /* Critical Return Debug Event */
231#endif
232#ifdef CONFIG_40x
233#define DBSR_IC 0x80000000 /* Instruction Completion */
234#define DBSR_BT 0x40000000 /* Branch taken */
235#define DBSR_IRPT 0x20000000 /* Exception Debug Event */
236#define DBSR_TIE 0x10000000 /* Trap Instruction debug Event */
237#define DBSR_IAC1 0x04000000 /* Instruction Address Compare 1 Event */
238#define DBSR_IAC2 0x02000000 /* Instruction Address Compare 2 Event */
239#define DBSR_IAC3 0x00080000 /* Instruction Address Compare 3 Event */
240#define DBSR_IAC4 0x00040000 /* Instruction Address Compare 4 Event */
241#define DBSR_DAC1R 0x01000000 /* Data Address Compare 1 Read Event */
242#define DBSR_DAC1W 0x00800000 /* Data Address Compare 1 Write Event */
243#define DBSR_DAC2R 0x00400000 /* Data Address Compare 2 Read Event */
244#define DBSR_DAC2W 0x00200000 /* Data Address Compare 2 Write Event */
245#endif
246
247/* Bit definitions related to the ESR. */
248#define ESR_MCI 0x80000000 /* Machine Check - Instruction */
249#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
250#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
251#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
252#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
253#define ESR_PIL 0x08000000 /* Program Exception - Illegal */
254#define ESR_PPR 0x04000000 /* Program Exception - Privileged */
255#define ESR_PTR 0x02000000 /* Program Exception - Trap */
256#define ESR_FP 0x01000000 /* Floating Point Operation */
257#define ESR_DST 0x00800000 /* Storage Exception - Data miss */
258#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
259#define ESR_ST 0x00800000 /* Store Operation */
260#define ESR_DLK 0x00200000 /* Data Cache Locking */
261#define ESR_ILK 0x00100000 /* Instr. Cache Locking */
262#define ESR_PUO 0x00040000 /* Unimplemented Operation exception */
263#define ESR_BO 0x00020000 /* Byte Ordering */
264
265/* Bit definitions related to the DBCR0. */
266#if defined(CONFIG_40x)
267#define DBCR0_EDM 0x80000000 /* External Debug Mode */
268#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */
269#define DBCR0_RST 0x30000000 /* all the bits in the RST field */
270#define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */
271#define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */
272#define DBCR0_RST_CORE 0x10000000 /* Core Reset */
273#define DBCR0_RST_NONE 0x00000000 /* No Reset */
274#define DBCR0_IC 0x08000000 /* Instruction Completion */
275#define DBCR0_ICMP DBCR0_IC
276#define DBCR0_BT 0x04000000 /* Branch Taken */
277#define DBCR0_BRT DBCR0_BT
278#define DBCR0_EDE 0x02000000 /* Exception Debug Event */
279#define DBCR0_IRPT DBCR0_EDE
280#define DBCR0_TDE 0x01000000 /* TRAP Debug Event */
281#define DBCR0_IA1 0x00800000 /* Instr Addr compare 1 enable */
282#define DBCR0_IAC1 DBCR0_IA1
283#define DBCR0_IA2 0x00400000 /* Instr Addr compare 2 enable */
284#define DBCR0_IAC2 DBCR0_IA2
285#define DBCR0_IA12 0x00200000 /* Instr Addr 1-2 range enable */
286#define DBCR0_IA12X 0x00100000 /* Instr Addr 1-2 range eXclusive */
287#define DBCR0_IA3 0x00080000 /* Instr Addr compare 3 enable */
288#define DBCR0_IAC3 DBCR0_IA3
289#define DBCR0_IA4 0x00040000 /* Instr Addr compare 4 enable */
290#define DBCR0_IAC4 DBCR0_IA4
291#define DBCR0_IA34 0x00020000 /* Instr Addr 3-4 range Enable */
292#define DBCR0_IA34X 0x00010000 /* Instr Addr 3-4 range eXclusive */
293#define DBCR0_IA12T 0x00008000 /* Instr Addr 1-2 range Toggle */
294#define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */
295#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */
296#elif defined(CONFIG_BOOKE)
297#define DBCR0_EDM 0x80000000 /* External Debug Mode */
298#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */
299#define DBCR0_RST 0x30000000 /* all the bits in the RST field */
300/* DBCR0_RST_* is 44x specific and not followed in fsl booke */
301#define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */
302#define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */
303#define DBCR0_RST_CORE 0x10000000 /* Core Reset */
304#define DBCR0_RST_NONE 0x00000000 /* No Reset */
305#define DBCR0_ICMP 0x08000000 /* Instruction Completion */
306#define DBCR0_IC DBCR0_ICMP
307#define DBCR0_BRT 0x04000000 /* Branch Taken */
308#define DBCR0_BT DBCR0_BRT
309#define DBCR0_IRPT 0x02000000 /* Exception Debug Event */
310#define DBCR0_TDE 0x01000000 /* TRAP Debug Event */
311#define DBCR0_TIE DBCR0_TDE
312#define DBCR0_IAC1 0x00800000 /* Instr Addr compare 1 enable */
313#define DBCR0_IAC2 0x00400000 /* Instr Addr compare 2 enable */
314#define DBCR0_IAC3 0x00200000 /* Instr Addr compare 3 enable */
315#define DBCR0_IAC4 0x00100000 /* Instr Addr compare 4 enable */
316#define DBCR0_DAC1R 0x00080000 /* DAC 1 Read enable */
317#define DBCR0_DAC1W 0x00040000 /* DAC 1 Write enable */
318#define DBCR0_DAC2R 0x00020000 /* DAC 2 Read enable */
319#define DBCR0_DAC2W 0x00010000 /* DAC 2 Write enable */
320#define DBCR0_RET 0x00008000 /* Return Debug Event */
321#define DBCR0_CIRPT 0x00000040 /* Critical Interrupt Taken Event */
322#define DBCR0_CRET 0x00000020 /* Critical Return Debug Event */
323#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */
324
325/* Bit definitions related to the DBCR1. */
326#define DBCR1_IAC12M 0x00800000 /* Instr Addr 1-2 range enable */
327#define DBCR1_IAC12MX 0x00C00000 /* Instr Addr 1-2 range eXclusive */
328#define DBCR1_IAC12AT 0x00010000 /* Instr Addr 1-2 range Toggle */
329#define DBCR1_IAC34M 0x00000080 /* Instr Addr 3-4 range enable */
330#define DBCR1_IAC34MX 0x000000C0 /* Instr Addr 3-4 range eXclusive */
331#define DBCR1_IAC34AT 0x00000001 /* Instr Addr 3-4 range Toggle */
332
333/* Bit definitions related to the DBCR2. */
334#define DBCR2_DAC12M 0x00800000 /* DAC 1-2 range enable */
335#define DBCR2_DAC12MX 0x00C00000 /* DAC 1-2 range eXclusive */
336#define DBCR2_DAC12A 0x00200000 /* DAC 1-2 Asynchronous */
337#endif
338
339/* Bit definitions related to the TCR. */
340#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
341#define TCR_WP_MASK TCR_WP(3)
342#define WP_2_17 0 /* 2^17 clocks */
343#define WP_2_21 1 /* 2^21 clocks */
344#define WP_2_25 2 /* 2^25 clocks */
345#define WP_2_29 3 /* 2^29 clocks */
346#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */
347#define TCR_WRC_MASK TCR_WRC(3)
348#define WRC_NONE 0 /* No reset will occur */
349#define WRC_CORE 1 /* Core reset will occur */
350#define WRC_CHIP 2 /* Chip reset will occur */
351#define WRC_SYSTEM 3 /* System reset will occur */
352#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */
353#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
354#define TCR_DIE TCR_PIE /* DEC Interrupt Enable */
355#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */
356#define TCR_FP_MASK TCR_FP(3)
357#define FP_2_9 0 /* 2^9 clocks */
358#define FP_2_13 1 /* 2^13 clocks */
359#define FP_2_17 2 /* 2^17 clocks */
360#define FP_2_21 3 /* 2^21 clocks */
361#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
362#define TCR_ARE 0x00400000 /* Auto Reload Enable */
363
364/* Bit definitions for the TSR. */
365#define TSR_ENW 0x80000000 /* Enable Next Watchdog */
366#define TSR_WIS 0x40000000 /* WDT Interrupt Status */
367#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */
368#define WRS_NONE 0 /* No WDT reset occurred */
369#define WRS_CORE 1 /* WDT forced core reset */
370#define WRS_CHIP 2 /* WDT forced chip reset */
371#define WRS_SYSTEM 3 /* WDT forced system reset */
372#define TSR_PIS 0x08000000 /* PIT Interrupt Status */
373#define TSR_DIS TSR_PIS /* DEC Interrupt Status */
374#define TSR_FIS 0x04000000 /* FIT Interrupt Status */
375
376/* Bit definitions for the DCCR. */
377#define DCCR_NOCACHE 0 /* Noncacheable */
378#define DCCR_CACHE 1 /* Cacheable */
379
380/* Bit definitions for DCWR. */
381#define DCWR_COPY 0 /* Copy-back */
382#define DCWR_WRITE 1 /* Write-through */
383
384/* Bit definitions for ICCR. */
385#define ICCR_NOCACHE 0 /* Noncacheable */
386#define ICCR_CACHE 1 /* Cacheable */
387
388/* Bit definitions for L1CSR0. */
389#define L1CSR0_CLFC 0x00000100 /* Cache Lock Bits Flash Clear */
390#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
391#define L1CSR0_CFI 0x00000002 /* Cache Flash Invalidate */
392#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
393
394/* Bit definitions for L1CSR1. */
395#define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */
396#define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */
397#define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */
398
399/* Bit definitions for L2CSR0. */
400#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */
401#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */
402#define L2CSR0_L2WP 0x1c000000 /* L2 I/D Way Partioning */
403#define L2CSR0_L2CM 0x03000000 /* L2 Cache Coherency Mode */
404#define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */
405#define L2CSR0_L2IO 0x00100000 /* L2 Cache Instruction Only */
406#define L2CSR0_L2DO 0x00010000 /* L2 Cache Data Only */
407#define L2CSR0_L2REP 0x00003000 /* L2 Line Replacement Algo */
408#define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */
409#define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */
410#define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */
411#define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */
412
413/* Bit definitions for SGR. */
414#define SGR_NORMAL 0 /* Speculative fetching allowed. */
415#define SGR_GUARDED 1 /* Speculative fetching disallowed. */
416
417/* Bit definitions for SPEFSCR. */
418#define SPEFSCR_SOVH 0x80000000 /* Summary integer overflow high */
419#define SPEFSCR_OVH 0x40000000 /* Integer overflow high */
420#define SPEFSCR_FGH 0x20000000 /* Embedded FP guard bit high */
421#define SPEFSCR_FXH 0x10000000 /* Embedded FP sticky bit high */
422#define SPEFSCR_FINVH 0x08000000 /* Embedded FP invalid operation high */
423#define SPEFSCR_FDBZH 0x04000000 /* Embedded FP div by zero high */
424#define SPEFSCR_FUNFH 0x02000000 /* Embedded FP underflow high */
425#define SPEFSCR_FOVFH 0x01000000 /* Embedded FP overflow high */
426#define SPEFSCR_FINXS 0x00200000 /* Embedded FP inexact sticky */
427#define SPEFSCR_FINVS 0x00100000 /* Embedded FP invalid op. sticky */
428#define SPEFSCR_FDBZS 0x00080000 /* Embedded FP div by zero sticky */
429#define SPEFSCR_FUNFS 0x00040000 /* Embedded FP underflow sticky */
430#define SPEFSCR_FOVFS 0x00020000 /* Embedded FP overflow sticky */
431#define SPEFSCR_MODE 0x00010000 /* Embedded FP mode */
432#define SPEFSCR_SOV 0x00008000 /* Integer summary overflow */
433#define SPEFSCR_OV 0x00004000 /* Integer overflow */
434#define SPEFSCR_FG 0x00002000 /* Embedded FP guard bit */
435#define SPEFSCR_FX 0x00001000 /* Embedded FP sticky bit */
436#define SPEFSCR_FINV 0x00000800 /* Embedded FP invalid operation */
437#define SPEFSCR_FDBZ 0x00000400 /* Embedded FP div by zero */
438#define SPEFSCR_FUNF 0x00000200 /* Embedded FP underflow */
439#define SPEFSCR_FOVF 0x00000100 /* Embedded FP overflow */
440#define SPEFSCR_FINXE 0x00000040 /* Embedded FP inexact enable */
441#define SPEFSCR_FINVE 0x00000020 /* Embedded FP invalid op. enable */
442#define SPEFSCR_FDBZE 0x00000010 /* Embedded FP div by zero enable */
443#define SPEFSCR_FUNFE 0x00000008 /* Embedded FP underflow enable */
444#define SPEFSCR_FOVFE 0x00000004 /* Embedded FP overflow enable */
445#define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control */
446
447/*
448 * The IBM-403 is an even more odd special case, as it is much
449 * older than the IBM-405 series. We put these down here incase someone
450 * wishes to support these machines again.
451 */
452#ifdef CONFIG_403GCX
453/* Special Purpose Registers (SPRNs)*/
454#define SPRN_TBHU 0x3CC /* Time Base High User-mode */
455#define SPRN_TBLU 0x3CD /* Time Base Low User-mode */
456#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
457#define SPRN_TBHI 0x3DC /* Time Base High */
458#define SPRN_TBLO 0x3DD /* Time Base Low */
459#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
460#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */
461#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */
462#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */
463#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */
464
465
466/* Bit definitions for the DBCR. */
467#define DBCR_EDM DBCR0_EDM
468#define DBCR_IDM DBCR0_IDM
469#define DBCR_RST(x) (((x) & 0x3) << 28)
470#define DBCR_RST_NONE 0
471#define DBCR_RST_CORE 1
472#define DBCR_RST_CHIP 2
473#define DBCR_RST_SYSTEM 3
474#define DBCR_IC DBCR0_IC /* Instruction Completion Debug Evnt */
475#define DBCR_BT DBCR0_BT /* Branch Taken Debug Event */
476#define DBCR_EDE DBCR0_EDE /* Exception Debug Event */
477#define DBCR_TDE DBCR0_TDE /* TRAP Debug Event */
478#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */
479#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */
480#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */
481#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */
482#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */
483#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */
484#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */
485#define DAC_BYTE 0
486#define DAC_HALF 1
487#define DAC_WORD 2
488#define DAC_QUAD 3
489#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */
490#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */
491#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */
492#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */
493#define DBCR_SED 0x00000020 /* Second Exception Debug Event */
494#define DBCR_STD 0x00000010 /* Second Trap Debug Event */
495#define DBCR_SIA 0x00000008 /* Second IAC Enable */
496#define DBCR_SDA 0x00000004 /* Second DAC Enable */
497#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
498#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
499#endif /* 403GCX */
500#endif /* __ASM_POWERPC_REG_BOOKE_H__ */
501#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/reg_fsl_emb.h b/include/asm-powerpc/reg_fsl_emb.h
deleted file mode 100644
index 1e180a59458..00000000000
--- a/include/asm-powerpc/reg_fsl_emb.h
+++ /dev/null
@@ -1,72 +0,0 @@
1/*
2 * Contains register definitions for the Freescale Embedded Performance
3 * Monitor.
4 */
5#ifdef __KERNEL__
6#ifndef __ASM_POWERPC_REG_FSL_EMB_H__
7#define __ASM_POWERPC_REG_FSL_EMB_H__
8
9#ifndef __ASSEMBLY__
10/* Performance Monitor Registers */
11#define mfpmr(rn) ({unsigned int rval; \
12 asm volatile("mfpmr %0," __stringify(rn) \
13 : "=r" (rval)); rval;})
14#define mtpmr(rn, v) asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v))
15#endif /* __ASSEMBLY__ */
16
17/* Freescale Book E Performance Monitor APU Registers */
18#define PMRN_PMC0 0x010 /* Performance Monitor Counter 0 */
19#define PMRN_PMC1 0x011 /* Performance Monitor Counter 1 */
20#define PMRN_PMC2 0x012 /* Performance Monitor Counter 1 */
21#define PMRN_PMC3 0x013 /* Performance Monitor Counter 1 */
22#define PMRN_PMLCA0 0x090 /* PM Local Control A0 */
23#define PMRN_PMLCA1 0x091 /* PM Local Control A1 */
24#define PMRN_PMLCA2 0x092 /* PM Local Control A2 */
25#define PMRN_PMLCA3 0x093 /* PM Local Control A3 */
26
27#define PMLCA_FC 0x80000000 /* Freeze Counter */
28#define PMLCA_FCS 0x40000000 /* Freeze in Supervisor */
29#define PMLCA_FCU 0x20000000 /* Freeze in User */
30#define PMLCA_FCM1 0x10000000 /* Freeze when PMM==1 */
31#define PMLCA_FCM0 0x08000000 /* Freeze when PMM==0 */
32#define PMLCA_CE 0x04000000 /* Condition Enable */
33
34#define PMLCA_EVENT_MASK 0x007f0000 /* Event field */
35#define PMLCA_EVENT_SHIFT 16
36
37#define PMRN_PMLCB0 0x110 /* PM Local Control B0 */
38#define PMRN_PMLCB1 0x111 /* PM Local Control B1 */
39#define PMRN_PMLCB2 0x112 /* PM Local Control B2 */
40#define PMRN_PMLCB3 0x113 /* PM Local Control B3 */
41
42#define PMLCB_THRESHMUL_MASK 0x0700 /* Threshhold Multiple Field */
43#define PMLCB_THRESHMUL_SHIFT 8
44
45#define PMLCB_THRESHOLD_MASK 0x003f /* Threshold Field */
46#define PMLCB_THRESHOLD_SHIFT 0
47
48#define PMRN_PMGC0 0x190 /* PM Global Control 0 */
49
50#define PMGC0_FAC 0x80000000 /* Freeze all Counters */
51#define PMGC0_PMIE 0x40000000 /* Interrupt Enable */
52#define PMGC0_FCECE 0x20000000 /* Freeze countes on
53 Enabled Condition or
54 Event */
55
56#define PMRN_UPMC0 0x000 /* User Performance Monitor Counter 0 */
57#define PMRN_UPMC1 0x001 /* User Performance Monitor Counter 1 */
58#define PMRN_UPMC2 0x002 /* User Performance Monitor Counter 1 */
59#define PMRN_UPMC3 0x003 /* User Performance Monitor Counter 1 */
60#define PMRN_UPMLCA0 0x080 /* User PM Local Control A0 */
61#define PMRN_UPMLCA1 0x081 /* User PM Local Control A1 */
62#define PMRN_UPMLCA2 0x082 /* User PM Local Control A2 */
63#define PMRN_UPMLCA3 0x083 /* User PM Local Control A3 */
64#define PMRN_UPMLCB0 0x100 /* User PM Local Control B0 */
65#define PMRN_UPMLCB1 0x101 /* User PM Local Control B1 */
66#define PMRN_UPMLCB2 0x102 /* User PM Local Control B2 */
67#define PMRN_UPMLCB3 0x103 /* User PM Local Control B3 */
68#define PMRN_UPMGC0 0x180 /* User PM Global Control 0 */
69
70
71#endif /* __ASM_POWERPC_REG_FSL_EMB_H__ */
72#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/resource.h b/include/asm-powerpc/resource.h
deleted file mode 100644
index 04bc4db8921..00000000000
--- a/include/asm-powerpc/resource.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/resource.h>
diff --git a/include/asm-powerpc/rheap.h b/include/asm-powerpc/rheap.h
deleted file mode 100644
index 172381769cf..00000000000
--- a/include/asm-powerpc/rheap.h
+++ /dev/null
@@ -1,89 +0,0 @@
1/*
2 * include/asm-ppc/rheap.h
3 *
4 * Header file for the implementation of a remote heap.
5 *
6 * Author: Pantelis Antoniou <panto@intracom.gr>
7 *
8 * 2004 (c) INTRACOM S.A. Greece. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13
14#ifndef __ASM_PPC_RHEAP_H__
15#define __ASM_PPC_RHEAP_H__
16
17#include <linux/list.h>
18
19typedef struct _rh_block {
20 struct list_head list;
21 unsigned long start;
22 int size;
23 const char *owner;
24} rh_block_t;
25
26typedef struct _rh_info {
27 unsigned int alignment;
28 int max_blocks;
29 int empty_slots;
30 rh_block_t *block;
31 struct list_head empty_list;
32 struct list_head free_list;
33 struct list_head taken_list;
34 unsigned int flags;
35} rh_info_t;
36
37#define RHIF_STATIC_INFO 0x1
38#define RHIF_STATIC_BLOCK 0x2
39
40typedef struct _rh_stats {
41 unsigned long start;
42 int size;
43 const char *owner;
44} rh_stats_t;
45
46#define RHGS_FREE 0
47#define RHGS_TAKEN 1
48
49/* Create a remote heap dynamically */
50extern rh_info_t *rh_create(unsigned int alignment);
51
52/* Destroy a remote heap, created by rh_create() */
53extern void rh_destroy(rh_info_t * info);
54
55/* Initialize in place a remote info block */
56extern void rh_init(rh_info_t * info, unsigned int alignment, int max_blocks,
57 rh_block_t * block);
58
59/* Attach a free region to manage */
60extern int rh_attach_region(rh_info_t * info, unsigned long start, int size);
61
62/* Detach a free region */
63extern unsigned long rh_detach_region(rh_info_t * info, unsigned long start, int size);
64
65/* Allocate the given size from the remote heap (with alignment) */
66extern unsigned long rh_alloc_align(rh_info_t * info, int size, int alignment,
67 const char *owner);
68
69/* Allocate the given size from the remote heap */
70extern unsigned long rh_alloc(rh_info_t * info, int size, const char *owner);
71
72/* Allocate the given size from the given address */
73extern unsigned long rh_alloc_fixed(rh_info_t * info, unsigned long start, int size,
74 const char *owner);
75
76/* Free the allocated area */
77extern int rh_free(rh_info_t * info, unsigned long start);
78
79/* Get stats for debugging purposes */
80extern int rh_get_stats(rh_info_t * info, int what, int max_stats,
81 rh_stats_t * stats);
82
83/* Simple dump of remote heap info */
84extern void rh_dump(rh_info_t * info);
85
86/* Set owner of taken block */
87extern int rh_set_owner(rh_info_t * info, unsigned long start, const char *owner);
88
89#endif /* __ASM_PPC_RHEAP_H__ */
diff --git a/include/asm-powerpc/rio.h b/include/asm-powerpc/rio.h
deleted file mode 100644
index 0018bf80cb2..00000000000
--- a/include/asm-powerpc/rio.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/*
2 * RapidIO architecture support
3 *
4 * Copyright 2005 MontaVista Software, Inc.
5 * Matt Porter <mporter@kernel.crashing.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#ifndef ASM_PPC_RIO_H
14#define ASM_PPC_RIO_H
15
16extern void platform_rio_init(void);
17
18#endif /* ASM_PPC_RIO_H */
diff --git a/include/asm-powerpc/rtas.h b/include/asm-powerpc/rtas.h
deleted file mode 100644
index 8eaa7b28d9d..00000000000
--- a/include/asm-powerpc/rtas.h
+++ /dev/null
@@ -1,247 +0,0 @@
1#ifndef _POWERPC_RTAS_H
2#define _POWERPC_RTAS_H
3#ifdef __KERNEL__
4
5#include <linux/spinlock.h>
6#include <asm/page.h>
7
8/*
9 * Definitions for talking to the RTAS on CHRP machines.
10 *
11 * Copyright (C) 2001 Peter Bergner
12 * Copyright (C) 2001 PPC 64 Team, IBM Corp
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
18 */
19
20#define RTAS_UNKNOWN_SERVICE (-1)
21#define RTAS_INSTANTIATE_MAX (1UL<<30) /* Don't instantiate rtas at/above this value */
22
23/* Buffer size for ppc_rtas system call. */
24#define RTAS_RMOBUF_MAX (64 * 1024)
25
26/* RTAS return status codes */
27#define RTAS_NOT_SUSPENDABLE -9004
28#define RTAS_BUSY -2 /* RTAS Busy */
29#define RTAS_EXTENDED_DELAY_MIN 9900
30#define RTAS_EXTENDED_DELAY_MAX 9905
31
32/*
33 * In general to call RTAS use rtas_token("string") to lookup
34 * an RTAS token for the given string (e.g. "event-scan").
35 * To actually perform the call use
36 * ret = rtas_call(token, n_in, n_out, ...)
37 * Where n_in is the number of input parameters and
38 * n_out is the number of output parameters
39 *
40 * If the "string" is invalid on this system, RTAS_UNKNOWN_SERVICE
41 * will be returned as a token. rtas_call() does look for this
42 * token and error out gracefully so rtas_call(rtas_token("str"), ...)
43 * may be safely used for one-shot calls to RTAS.
44 *
45 */
46
47typedef u32 rtas_arg_t;
48
49struct rtas_args {
50 u32 token;
51 u32 nargs;
52 u32 nret;
53 rtas_arg_t args[16];
54 rtas_arg_t *rets; /* Pointer to return values in args[]. */
55};
56
57struct rtas_t {
58 unsigned long entry; /* physical address pointer */
59 unsigned long base; /* physical address pointer */
60 unsigned long size;
61 spinlock_t lock;
62 struct rtas_args args;
63 struct device_node *dev; /* virtual address pointer */
64};
65
66/* RTAS event classes */
67#define RTAS_INTERNAL_ERROR 0x80000000 /* set bit 0 */
68#define RTAS_EPOW_WARNING 0x40000000 /* set bit 1 */
69#define RTAS_POWERMGM_EVENTS 0x20000000 /* set bit 2 */
70#define RTAS_HOTPLUG_EVENTS 0x10000000 /* set bit 3 */
71#define RTAS_EVENT_SCAN_ALL_EVENTS 0xf0000000
72
73/* RTAS event severity */
74#define RTAS_SEVERITY_FATAL 0x5
75#define RTAS_SEVERITY_ERROR 0x4
76#define RTAS_SEVERITY_ERROR_SYNC 0x3
77#define RTAS_SEVERITY_WARNING 0x2
78#define RTAS_SEVERITY_EVENT 0x1
79#define RTAS_SEVERITY_NO_ERROR 0x0
80
81/* RTAS event disposition */
82#define RTAS_DISP_FULLY_RECOVERED 0x0
83#define RTAS_DISP_LIMITED_RECOVERY 0x1
84#define RTAS_DISP_NOT_RECOVERED 0x2
85
86/* RTAS event initiator */
87#define RTAS_INITIATOR_UNKNOWN 0x0
88#define RTAS_INITIATOR_CPU 0x1
89#define RTAS_INITIATOR_PCI 0x2
90#define RTAS_INITIATOR_ISA 0x3
91#define RTAS_INITIATOR_MEMORY 0x4
92#define RTAS_INITIATOR_POWERMGM 0x5
93
94/* RTAS event target */
95#define RTAS_TARGET_UNKNOWN 0x0
96#define RTAS_TARGET_CPU 0x1
97#define RTAS_TARGET_PCI 0x2
98#define RTAS_TARGET_ISA 0x3
99#define RTAS_TARGET_MEMORY 0x4
100#define RTAS_TARGET_POWERMGM 0x5
101
102/* RTAS event type */
103#define RTAS_TYPE_RETRY 0x01
104#define RTAS_TYPE_TCE_ERR 0x02
105#define RTAS_TYPE_INTERN_DEV_FAIL 0x03
106#define RTAS_TYPE_TIMEOUT 0x04
107#define RTAS_TYPE_DATA_PARITY 0x05
108#define RTAS_TYPE_ADDR_PARITY 0x06
109#define RTAS_TYPE_CACHE_PARITY 0x07
110#define RTAS_TYPE_ADDR_INVALID 0x08
111#define RTAS_TYPE_ECC_UNCORR 0x09
112#define RTAS_TYPE_ECC_CORR 0x0a
113#define RTAS_TYPE_EPOW 0x40
114#define RTAS_TYPE_PLATFORM 0xE0
115#define RTAS_TYPE_IO 0xE1
116#define RTAS_TYPE_INFO 0xE2
117#define RTAS_TYPE_DEALLOC 0xE3
118#define RTAS_TYPE_DUMP 0xE4
119/* I don't add PowerMGM events right now, this is a different topic */
120#define RTAS_TYPE_PMGM_POWER_SW_ON 0x60
121#define RTAS_TYPE_PMGM_POWER_SW_OFF 0x61
122#define RTAS_TYPE_PMGM_LID_OPEN 0x62
123#define RTAS_TYPE_PMGM_LID_CLOSE 0x63
124#define RTAS_TYPE_PMGM_SLEEP_BTN 0x64
125#define RTAS_TYPE_PMGM_WAKE_BTN 0x65
126#define RTAS_TYPE_PMGM_BATTERY_WARN 0x66
127#define RTAS_TYPE_PMGM_BATTERY_CRIT 0x67
128#define RTAS_TYPE_PMGM_SWITCH_TO_BAT 0x68
129#define RTAS_TYPE_PMGM_SWITCH_TO_AC 0x69
130#define RTAS_TYPE_PMGM_KBD_OR_MOUSE 0x6a
131#define RTAS_TYPE_PMGM_ENCLOS_OPEN 0x6b
132#define RTAS_TYPE_PMGM_ENCLOS_CLOSED 0x6c
133#define RTAS_TYPE_PMGM_RING_INDICATE 0x6d
134#define RTAS_TYPE_PMGM_LAN_ATTENTION 0x6e
135#define RTAS_TYPE_PMGM_TIME_ALARM 0x6f
136#define RTAS_TYPE_PMGM_CONFIG_CHANGE 0x70
137#define RTAS_TYPE_PMGM_SERVICE_PROC 0x71
138
139struct rtas_error_log {
140 unsigned long version:8; /* Architectural version */
141 unsigned long severity:3; /* Severity level of error */
142 unsigned long disposition:2; /* Degree of recovery */
143 unsigned long extended:1; /* extended log present? */
144 unsigned long /* reserved */ :2; /* Reserved for future use */
145 unsigned long initiator:4; /* Initiator of event */
146 unsigned long target:4; /* Target of failed operation */
147 unsigned long type:8; /* General event or error*/
148 unsigned long extended_log_length:32; /* length in bytes */
149 unsigned char buffer[1];
150};
151
152/*
153 * This can be set by the rtas_flash module so that it can get called
154 * as the absolutely last thing before the kernel terminates.
155 */
156extern void (*rtas_flash_term_hook)(int);
157
158extern struct rtas_t rtas;
159
160extern void enter_rtas(unsigned long);
161extern int rtas_token(const char *service);
162extern int rtas_service_present(const char *service);
163extern int rtas_call(int token, int, int, int *, ...);
164extern void rtas_restart(char *cmd);
165extern void rtas_power_off(void);
166extern void rtas_halt(void);
167extern void rtas_os_term(char *str);
168extern int rtas_get_sensor(int sensor, int index, int *state);
169extern int rtas_get_power_level(int powerdomain, int *level);
170extern int rtas_set_power_level(int powerdomain, int level, int *setlevel);
171extern int rtas_set_indicator(int indicator, int index, int new_value);
172extern int rtas_set_indicator_fast(int indicator, int index, int new_value);
173extern void rtas_progress(char *s, unsigned short hex);
174extern void rtas_initialize(void);
175
176struct rtc_time;
177extern unsigned long rtas_get_boot_time(void);
178extern void rtas_get_rtc_time(struct rtc_time *rtc_time);
179extern int rtas_set_rtc_time(struct rtc_time *rtc_time);
180
181extern unsigned int rtas_busy_delay_time(int status);
182extern unsigned int rtas_busy_delay(int status);
183
184extern int early_init_dt_scan_rtas(unsigned long node,
185 const char *uname, int depth, void *data);
186
187extern void pSeries_log_error(char *buf, unsigned int err_type, int fatal);
188
189/* Error types logged. */
190#define ERR_FLAG_ALREADY_LOGGED 0x0
191#define ERR_FLAG_BOOT 0x1 /* log was pulled from NVRAM on boot */
192#define ERR_TYPE_RTAS_LOG 0x2 /* from rtas event-scan */
193#define ERR_TYPE_KERNEL_PANIC 0x4 /* from panic() */
194
195/* All the types and not flags */
196#define ERR_TYPE_MASK (ERR_TYPE_RTAS_LOG | ERR_TYPE_KERNEL_PANIC)
197
198#define RTAS_DEBUG KERN_DEBUG "RTAS: "
199
200#define RTAS_ERROR_LOG_MAX 2048
201
202/*
203 * Return the firmware-specified size of the error log buffer
204 * for all rtas calls that require an error buffer argument.
205 * This includes 'check-exception' and 'rtas-last-error'.
206 */
207extern int rtas_get_error_log_max(void);
208
209/* Event Scan Parameters */
210#define EVENT_SCAN_ALL_EVENTS 0xf0000000
211#define SURVEILLANCE_TOKEN 9000
212#define LOG_NUMBER 64 /* must be a power of two */
213#define LOG_NUMBER_MASK (LOG_NUMBER-1)
214
215/* Some RTAS ops require a data buffer and that buffer must be < 4G.
216 * Rather than having a memory allocator, just use this buffer
217 * (get the lock first), make the RTAS call. Copy the data instead
218 * of holding the buffer for long.
219 */
220
221#define RTAS_DATA_BUF_SIZE 4096
222extern spinlock_t rtas_data_buf_lock;
223extern char rtas_data_buf[RTAS_DATA_BUF_SIZE];
224
225/* RMO buffer reserved for user-space RTAS use */
226extern unsigned long rtas_rmo_buf;
227
228#define GLOBAL_INTERRUPT_QUEUE 9005
229
230/**
231 * rtas_config_addr - Format a busno, devfn and reg for RTAS.
232 * @busno: The bus number.
233 * @devfn: The device and function number as encoded by PCI_DEVFN().
234 * @reg: The register number.
235 *
236 * This function encodes the given busno, devfn and register number as
237 * required for RTAS calls that take a "config_addr" parameter.
238 * See PAPR requirement 7.3.4-1 for more info.
239 */
240static inline u32 rtas_config_addr(int busno, int devfn, int reg)
241{
242 return ((reg & 0xf00) << 20) | ((busno & 0xff) << 16) |
243 (devfn << 8) | (reg & 0xff);
244}
245
246#endif /* __KERNEL__ */
247#endif /* _POWERPC_RTAS_H */
diff --git a/include/asm-powerpc/rtc.h b/include/asm-powerpc/rtc.h
deleted file mode 100644
index f5802926b6c..00000000000
--- a/include/asm-powerpc/rtc.h
+++ /dev/null
@@ -1,78 +0,0 @@
1/*
2 * Real-time clock definitions and interfaces
3 *
4 * Author: Tom Rini <trini@mvista.com>
5 *
6 * 2002 (c) MontaVista, Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 *
11 * Based on:
12 * include/asm-m68k/rtc.h
13 *
14 * Copyright Richard Zidlicky
15 * implementation details for genrtc/q40rtc driver
16 *
17 * And the old drivers/macintosh/rtc.c which was heavily based on:
18 * Linux/SPARC Real Time Clock Driver
19 * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
20 *
21 * With additional work by Paul Mackerras and Franz Sirl.
22 */
23
24#ifndef __ASM_POWERPC_RTC_H__
25#define __ASM_POWERPC_RTC_H__
26
27#ifdef __KERNEL__
28
29#include <linux/rtc.h>
30
31#include <asm/machdep.h>
32#include <asm/time.h>
33
34#define RTC_PIE 0x40 /* periodic interrupt enable */
35#define RTC_AIE 0x20 /* alarm interrupt enable */
36#define RTC_UIE 0x10 /* update-finished interrupt enable */
37
38/* some dummy definitions */
39#define RTC_BATT_BAD 0x100 /* battery bad */
40#define RTC_SQWE 0x08 /* enable square-wave output */
41#define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */
42#define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */
43#define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */
44
45static inline unsigned int get_rtc_time(struct rtc_time *time)
46{
47 if (ppc_md.get_rtc_time)
48 ppc_md.get_rtc_time(time);
49 return RTC_24H;
50}
51
52/* Set the current date and time in the real time clock. */
53static inline int set_rtc_time(struct rtc_time *time)
54{
55 if (ppc_md.set_rtc_time)
56 return ppc_md.set_rtc_time(time);
57 return -EINVAL;
58}
59
60static inline unsigned int get_rtc_ss(void)
61{
62 struct rtc_time h;
63
64 get_rtc_time(&h);
65 return h.tm_sec;
66}
67
68static inline int get_rtc_pll(struct rtc_pll_info *pll)
69{
70 return -EINVAL;
71}
72static inline int set_rtc_pll(struct rtc_pll_info *pll)
73{
74 return -EINVAL;
75}
76
77#endif /* __KERNEL__ */
78#endif /* __ASM_POWERPC_RTC_H__ */
diff --git a/include/asm-powerpc/rwsem.h b/include/asm-powerpc/rwsem.h
deleted file mode 100644
index a6cc93b78b9..00000000000
--- a/include/asm-powerpc/rwsem.h
+++ /dev/null
@@ -1,173 +0,0 @@
1#ifndef _ASM_POWERPC_RWSEM_H
2#define _ASM_POWERPC_RWSEM_H
3
4#ifndef _LINUX_RWSEM_H
5#error "Please don't include <asm/rwsem.h> directly, use <linux/rwsem.h> instead."
6#endif
7
8#ifdef __KERNEL__
9
10/*
11 * include/asm-powerpc/rwsem.h: R/W semaphores for PPC using the stuff
12 * in lib/rwsem.c. Adapted largely from include/asm-i386/rwsem.h
13 * by Paul Mackerras <paulus@samba.org>.
14 */
15
16#include <linux/list.h>
17#include <linux/spinlock.h>
18#include <asm/atomic.h>
19#include <asm/system.h>
20
21/*
22 * the semaphore definition
23 */
24struct rw_semaphore {
25 /* XXX this should be able to be an atomic_t -- paulus */
26 signed int count;
27#define RWSEM_UNLOCKED_VALUE 0x00000000
28#define RWSEM_ACTIVE_BIAS 0x00000001
29#define RWSEM_ACTIVE_MASK 0x0000ffff
30#define RWSEM_WAITING_BIAS (-0x00010000)
31#define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS
32#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
33 spinlock_t wait_lock;
34 struct list_head wait_list;
35#ifdef CONFIG_DEBUG_LOCK_ALLOC
36 struct lockdep_map dep_map;
37#endif
38};
39
40#ifdef CONFIG_DEBUG_LOCK_ALLOC
41# define __RWSEM_DEP_MAP_INIT(lockname) , .dep_map = { .name = #lockname }
42#else
43# define __RWSEM_DEP_MAP_INIT(lockname)
44#endif
45
46#define __RWSEM_INITIALIZER(name) \
47 { RWSEM_UNLOCKED_VALUE, __SPIN_LOCK_UNLOCKED((name).wait_lock), \
48 LIST_HEAD_INIT((name).wait_list) __RWSEM_DEP_MAP_INIT(name) }
49
50#define DECLARE_RWSEM(name) \
51 struct rw_semaphore name = __RWSEM_INITIALIZER(name)
52
53extern struct rw_semaphore *rwsem_down_read_failed(struct rw_semaphore *sem);
54extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem);
55extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem);
56extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem);
57
58extern void __init_rwsem(struct rw_semaphore *sem, const char *name,
59 struct lock_class_key *key);
60
61#define init_rwsem(sem) \
62 do { \
63 static struct lock_class_key __key; \
64 \
65 __init_rwsem((sem), #sem, &__key); \
66 } while (0)
67
68/*
69 * lock for reading
70 */
71static inline void __down_read(struct rw_semaphore *sem)
72{
73 if (unlikely(atomic_inc_return((atomic_t *)(&sem->count)) <= 0))
74 rwsem_down_read_failed(sem);
75}
76
77static inline int __down_read_trylock(struct rw_semaphore *sem)
78{
79 int tmp;
80
81 while ((tmp = sem->count) >= 0) {
82 if (tmp == cmpxchg(&sem->count, tmp,
83 tmp + RWSEM_ACTIVE_READ_BIAS)) {
84 return 1;
85 }
86 }
87 return 0;
88}
89
90/*
91 * lock for writing
92 */
93static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
94{
95 int tmp;
96
97 tmp = atomic_add_return(RWSEM_ACTIVE_WRITE_BIAS,
98 (atomic_t *)(&sem->count));
99 if (unlikely(tmp != RWSEM_ACTIVE_WRITE_BIAS))
100 rwsem_down_write_failed(sem);
101}
102
103static inline void __down_write(struct rw_semaphore *sem)
104{
105 __down_write_nested(sem, 0);
106}
107
108static inline int __down_write_trylock(struct rw_semaphore *sem)
109{
110 int tmp;
111
112 tmp = cmpxchg(&sem->count, RWSEM_UNLOCKED_VALUE,
113 RWSEM_ACTIVE_WRITE_BIAS);
114 return tmp == RWSEM_UNLOCKED_VALUE;
115}
116
117/*
118 * unlock after reading
119 */
120static inline void __up_read(struct rw_semaphore *sem)
121{
122 int tmp;
123
124 tmp = atomic_dec_return((atomic_t *)(&sem->count));
125 if (unlikely(tmp < -1 && (tmp & RWSEM_ACTIVE_MASK) == 0))
126 rwsem_wake(sem);
127}
128
129/*
130 * unlock after writing
131 */
132static inline void __up_write(struct rw_semaphore *sem)
133{
134 if (unlikely(atomic_sub_return(RWSEM_ACTIVE_WRITE_BIAS,
135 (atomic_t *)(&sem->count)) < 0))
136 rwsem_wake(sem);
137}
138
139/*
140 * implement atomic add functionality
141 */
142static inline void rwsem_atomic_add(int delta, struct rw_semaphore *sem)
143{
144 atomic_add(delta, (atomic_t *)(&sem->count));
145}
146
147/*
148 * downgrade write lock to read lock
149 */
150static inline void __downgrade_write(struct rw_semaphore *sem)
151{
152 int tmp;
153
154 tmp = atomic_add_return(-RWSEM_WAITING_BIAS, (atomic_t *)(&sem->count));
155 if (tmp < 0)
156 rwsem_downgrade_wake(sem);
157}
158
159/*
160 * implement exchange and add functionality
161 */
162static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
163{
164 return atomic_add_return(delta, (atomic_t *)(&sem->count));
165}
166
167static inline int rwsem_is_locked(struct rw_semaphore *sem)
168{
169 return (sem->count != 0);
170}
171
172#endif /* __KERNEL__ */
173#endif /* _ASM_POWERPC_RWSEM_H */
diff --git a/include/asm-powerpc/scatterlist.h b/include/asm-powerpc/scatterlist.h
deleted file mode 100644
index fcf7d55afe4..00000000000
--- a/include/asm-powerpc/scatterlist.h
+++ /dev/null
@@ -1,50 +0,0 @@
1#ifndef _ASM_POWERPC_SCATTERLIST_H
2#define _ASM_POWERPC_SCATTERLIST_H
3/*
4 * Copyright (C) 2001 PPC64 Team, IBM Corp
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#ifdef __KERNEL__
13#include <linux/types.h>
14#include <asm/dma.h>
15
16struct scatterlist {
17#ifdef CONFIG_DEBUG_SG
18 unsigned long sg_magic;
19#endif
20 unsigned long page_link;
21 unsigned int offset;
22 unsigned int length;
23
24 /* For TCE support */
25 dma_addr_t dma_address;
26 u32 dma_length;
27};
28
29/*
30 * These macros should be used after a dma_map_sg call has been done
31 * to get bus addresses of each of the SG entries and their lengths.
32 * You should only work with the number of sg entries pci_map_sg
33 * returns, or alternatively stop on the first sg_dma_len(sg) which
34 * is 0.
35 */
36#define sg_dma_address(sg) ((sg)->dma_address)
37#ifdef __powerpc64__
38#define sg_dma_len(sg) ((sg)->dma_length)
39#else
40#define sg_dma_len(sg) ((sg)->length)
41#endif
42
43#ifdef __powerpc64__
44#define ISA_DMA_THRESHOLD (~0UL)
45#endif
46
47#define ARCH_HAS_SG_CHAIN
48
49#endif /* __KERNEL__ */
50#endif /* _ASM_POWERPC_SCATTERLIST_H */
diff --git a/include/asm-powerpc/seccomp.h b/include/asm-powerpc/seccomp.h
deleted file mode 100644
index 853765eb1f6..00000000000
--- a/include/asm-powerpc/seccomp.h
+++ /dev/null
@@ -1,20 +0,0 @@
1#ifndef _ASM_POWERPC_SECCOMP_H
2#define _ASM_POWERPC_SECCOMP_H
3
4#ifdef __KERNEL__
5#include <linux/thread_info.h>
6#endif
7
8#include <linux/unistd.h>
9
10#define __NR_seccomp_read __NR_read
11#define __NR_seccomp_write __NR_write
12#define __NR_seccomp_exit __NR_exit
13#define __NR_seccomp_sigreturn __NR_rt_sigreturn
14
15#define __NR_seccomp_read_32 __NR_read
16#define __NR_seccomp_write_32 __NR_write
17#define __NR_seccomp_exit_32 __NR_exit
18#define __NR_seccomp_sigreturn_32 __NR_sigreturn
19
20#endif /* _ASM_POWERPC_SECCOMP_H */
diff --git a/include/asm-powerpc/sections.h b/include/asm-powerpc/sections.h
deleted file mode 100644
index 916018e425c..00000000000
--- a/include/asm-powerpc/sections.h
+++ /dev/null
@@ -1,22 +0,0 @@
1#ifndef _ASM_POWERPC_SECTIONS_H
2#define _ASM_POWERPC_SECTIONS_H
3#ifdef __KERNEL__
4
5#include <asm-generic/sections.h>
6
7#ifdef __powerpc64__
8
9extern char _end[];
10
11static inline int in_kernel_text(unsigned long addr)
12{
13 if (addr >= (unsigned long)_stext && addr < (unsigned long)__init_end)
14 return 1;
15
16 return 0;
17}
18
19#endif
20
21#endif /* __KERNEL__ */
22#endif /* _ASM_POWERPC_SECTIONS_H */
diff --git a/include/asm-powerpc/sembuf.h b/include/asm-powerpc/sembuf.h
deleted file mode 100644
index 99a41938ae3..00000000000
--- a/include/asm-powerpc/sembuf.h
+++ /dev/null
@@ -1,36 +0,0 @@
1#ifndef _ASM_POWERPC_SEMBUF_H
2#define _ASM_POWERPC_SEMBUF_H
3
4/*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10
11/*
12 * The semid64_ds structure for PPC architecture.
13 * Note extra padding because this structure is passed back and forth
14 * between kernel and user space.
15 *
16 * Pad space is left for:
17 * - 64-bit time_t to solve y2038 problem
18 * - 2 miscellaneous 32-bit values
19 */
20
21struct semid64_ds {
22 struct ipc64_perm sem_perm; /* permissions .. see ipc.h */
23#ifndef __powerpc64__
24 unsigned long __unused1;
25#endif
26 __kernel_time_t sem_otime; /* last semop time */
27#ifndef __powerpc64__
28 unsigned long __unused2;
29#endif
30 __kernel_time_t sem_ctime; /* last change time */
31 unsigned long sem_nsems; /* no. of semaphores in array */
32 unsigned long __unused3;
33 unsigned long __unused4;
34};
35
36#endif /* _ASM_POWERPC_SEMBUF_H */
diff --git a/include/asm-powerpc/serial.h b/include/asm-powerpc/serial.h
deleted file mode 100644
index 3e8589b43cb..00000000000
--- a/include/asm-powerpc/serial.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version
5 * 2 of the License, or (at your option) any later version.
6 */
7#ifndef _ASM_POWERPC_SERIAL_H
8#define _ASM_POWERPC_SERIAL_H
9
10/*
11 * Serial ports are not listed here, because they are discovered
12 * through the device tree.
13 */
14
15/* Default baud base if not found in device-tree */
16#define BASE_BAUD ( 1843200 / 16 )
17
18#ifdef CONFIG_PPC_UDBG_16550
19extern void find_legacy_serial_ports(void);
20#else
21#define find_legacy_serial_ports() do { } while (0)
22#endif
23
24#endif /* _PPC64_SERIAL_H */
diff --git a/include/asm-powerpc/setjmp.h b/include/asm-powerpc/setjmp.h
deleted file mode 100644
index 279d03a1eec..00000000000
--- a/include/asm-powerpc/setjmp.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/*
2 * Copyright © 2008 Michael Neuling IBM Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 */
10#ifndef _ASM_POWERPC_SETJMP_H
11#define _ASM_POWERPC_SETJMP_H
12
13#define JMP_BUF_LEN 23
14
15extern long setjmp(long *);
16extern void longjmp(long *, long);
17
18#endif /* _ASM_POWERPC_SETJMP_H */
diff --git a/include/asm-powerpc/setup.h b/include/asm-powerpc/setup.h
deleted file mode 100644
index 817fac0a071..00000000000
--- a/include/asm-powerpc/setup.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _ASM_POWERPC_SETUP_H
2#define _ASM_POWERPC_SETUP_H
3
4#define COMMAND_LINE_SIZE 512
5
6#endif /* _ASM_POWERPC_SETUP_H */
diff --git a/include/asm-powerpc/shmbuf.h b/include/asm-powerpc/shmbuf.h
deleted file mode 100644
index 8efa39698b6..00000000000
--- a/include/asm-powerpc/shmbuf.h
+++ /dev/null
@@ -1,59 +0,0 @@
1#ifndef _ASM_POWERPC_SHMBUF_H
2#define _ASM_POWERPC_SHMBUF_H
3
4/*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10
11/*
12 * The shmid64_ds structure for PPC architecture.
13 *
14 * Note extra padding because this structure is passed back and forth
15 * between kernel and user space.
16 *
17 * Pad space is left for:
18 * - 64-bit time_t to solve y2038 problem
19 * - 2 miscellaneous 32-bit values
20 */
21
22struct shmid64_ds {
23 struct ipc64_perm shm_perm; /* operation perms */
24#ifndef __powerpc64__
25 unsigned long __unused1;
26#endif
27 __kernel_time_t shm_atime; /* last attach time */
28#ifndef __powerpc64__
29 unsigned long __unused2;
30#endif
31 __kernel_time_t shm_dtime; /* last detach time */
32#ifndef __powerpc64__
33 unsigned long __unused3;
34#endif
35 __kernel_time_t shm_ctime; /* last change time */
36#ifndef __powerpc64__
37 unsigned long __unused4;
38#endif
39 size_t shm_segsz; /* size of segment (bytes) */
40 __kernel_pid_t shm_cpid; /* pid of creator */
41 __kernel_pid_t shm_lpid; /* pid of last operator */
42 unsigned long shm_nattch; /* no. of current attaches */
43 unsigned long __unused5;
44 unsigned long __unused6;
45};
46
47struct shminfo64 {
48 unsigned long shmmax;
49 unsigned long shmmin;
50 unsigned long shmmni;
51 unsigned long shmseg;
52 unsigned long shmall;
53 unsigned long __unused1;
54 unsigned long __unused2;
55 unsigned long __unused3;
56 unsigned long __unused4;
57};
58
59#endif /* _ASM_POWERPC_SHMBUF_H */
diff --git a/include/asm-powerpc/shmparam.h b/include/asm-powerpc/shmparam.h
deleted file mode 100644
index 5cda42a6d39..00000000000
--- a/include/asm-powerpc/shmparam.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _ASM_POWERPC_SHMPARAM_H
2#define _ASM_POWERPC_SHMPARAM_H
3
4#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */
5
6#endif /* _ASM_POWERPC_SHMPARAM_H */
diff --git a/include/asm-powerpc/sigcontext.h b/include/asm-powerpc/sigcontext.h
deleted file mode 100644
index 9c1f24fd5d1..00000000000
--- a/include/asm-powerpc/sigcontext.h
+++ /dev/null
@@ -1,87 +0,0 @@
1#ifndef _ASM_POWERPC_SIGCONTEXT_H
2#define _ASM_POWERPC_SIGCONTEXT_H
3
4/*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10#include <linux/compiler.h>
11#include <asm/ptrace.h>
12#ifdef __powerpc64__
13#include <asm/elf.h>
14#endif
15
16struct sigcontext {
17 unsigned long _unused[4];
18 int signal;
19#ifdef __powerpc64__
20 int _pad0;
21#endif
22 unsigned long handler;
23 unsigned long oldmask;
24 struct pt_regs __user *regs;
25#ifdef __powerpc64__
26 elf_gregset_t gp_regs;
27 elf_fpregset_t fp_regs;
28/*
29 * To maintain compatibility with current implementations the sigcontext is
30 * extended by appending a pointer (v_regs) to a quadword type (elf_vrreg_t)
31 * followed by an unstructured (vmx_reserve) field of 69 doublewords. This
32 * allows the array of vector registers to be quadword aligned independent of
33 * the alignment of the containing sigcontext or ucontext. It is the
34 * responsibility of the code setting the sigcontext to set this pointer to
35 * either NULL (if this processor does not support the VMX feature) or the
36 * address of the first quadword within the allocated (vmx_reserve) area.
37 *
38 * The pointer (v_regs) of vector type (elf_vrreg_t) is type compatible with
39 * an array of 34 quadword entries (elf_vrregset_t). The entries with
40 * indexes 0-31 contain the corresponding vector registers. The entry with
41 * index 32 contains the vscr as the last word (offset 12) within the
42 * quadword. This allows the vscr to be stored as either a quadword (since
43 * it must be copied via a vector register to/from storage) or as a word.
44 * The entry with index 33 contains the vrsave as the first word (offset 0)
45 * within the quadword.
46 *
47 * Part of the VSX data is stored here also by extending vmx_restore
48 * by an additional 32 double words. Architecturally the layout of
49 * the VSR registers and how they overlap on top of the legacy FPR and
50 * VR registers is shown below:
51 *
52 * VSR doubleword 0 VSR doubleword 1
53 * ----------------------------------------------------------------
54 * VSR[0] | FPR[0] | |
55 * ----------------------------------------------------------------
56 * VSR[1] | FPR[1] | |
57 * ----------------------------------------------------------------
58 * | ... | |
59 * | ... | |
60 * ----------------------------------------------------------------
61 * VSR[30] | FPR[30] | |
62 * ----------------------------------------------------------------
63 * VSR[31] | FPR[31] | |
64 * ----------------------------------------------------------------
65 * VSR[32] | VR[0] |
66 * ----------------------------------------------------------------
67 * VSR[33] | VR[1] |
68 * ----------------------------------------------------------------
69 * | ... |
70 * | ... |
71 * ----------------------------------------------------------------
72 * VSR[62] | VR[30] |
73 * ----------------------------------------------------------------
74 * VSR[63] | VR[31] |
75 * ----------------------------------------------------------------
76 *
77 * FPR/VSR 0-31 doubleword 0 is stored in fp_regs, and VMX/VSR 32-63
78 * is stored at the start of vmx_reserve. vmx_reserve is extended for
79 * backwards compatility to store VSR 0-31 doubleword 1 after the VMX
80 * registers and vscr/vrsave.
81 */
82 elf_vrreg_t __user *v_regs;
83 long vmx_reserve[ELF_NVRREG+ELF_NVRREG+32+1];
84#endif
85};
86
87#endif /* _ASM_POWERPC_SIGCONTEXT_H */
diff --git a/include/asm-powerpc/siginfo.h b/include/asm-powerpc/siginfo.h
deleted file mode 100644
index 12f1bce037b..00000000000
--- a/include/asm-powerpc/siginfo.h
+++ /dev/null
@@ -1,26 +0,0 @@
1#ifndef _ASM_POWERPC_SIGINFO_H
2#define _ASM_POWERPC_SIGINFO_H
3
4/*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10
11#ifdef __powerpc64__
12# define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
13# define SI_PAD_SIZE32 ((SI_MAX_SIZE/sizeof(int)) - 3)
14#endif
15
16#include <asm-generic/siginfo.h>
17
18/*
19 * SIGTRAP si_codes
20 */
21#define TRAP_BRANCH (__SI_FAULT|3) /* process taken branch trap */
22#define TRAP_HWBKPT (__SI_FAULT|4) /* hardware breakpoint or watchpoint */
23#undef NSIGTRAP
24#define NSIGTRAP 4
25
26#endif /* _ASM_POWERPC_SIGINFO_H */
diff --git a/include/asm-powerpc/signal.h b/include/asm-powerpc/signal.h
deleted file mode 100644
index a8c7babf495..00000000000
--- a/include/asm-powerpc/signal.h
+++ /dev/null
@@ -1,151 +0,0 @@
1#ifndef _ASM_POWERPC_SIGNAL_H
2#define _ASM_POWERPC_SIGNAL_H
3
4#include <linux/types.h>
5
6#define _NSIG 64
7#ifdef __powerpc64__
8#define _NSIG_BPW 64
9#else
10#define _NSIG_BPW 32
11#endif
12#define _NSIG_WORDS (_NSIG / _NSIG_BPW)
13
14typedef unsigned long old_sigset_t; /* at least 32 bits */
15
16typedef struct {
17 unsigned long sig[_NSIG_WORDS];
18} sigset_t;
19
20#define SIGHUP 1
21#define SIGINT 2
22#define SIGQUIT 3
23#define SIGILL 4
24#define SIGTRAP 5
25#define SIGABRT 6
26#define SIGIOT 6
27#define SIGBUS 7
28#define SIGFPE 8
29#define SIGKILL 9
30#define SIGUSR1 10
31#define SIGSEGV 11
32#define SIGUSR2 12
33#define SIGPIPE 13
34#define SIGALRM 14
35#define SIGTERM 15
36#define SIGSTKFLT 16
37#define SIGCHLD 17
38#define SIGCONT 18
39#define SIGSTOP 19
40#define SIGTSTP 20
41#define SIGTTIN 21
42#define SIGTTOU 22
43#define SIGURG 23
44#define SIGXCPU 24
45#define SIGXFSZ 25
46#define SIGVTALRM 26
47#define SIGPROF 27
48#define SIGWINCH 28
49#define SIGIO 29
50#define SIGPOLL SIGIO
51/*
52#define SIGLOST 29
53*/
54#define SIGPWR 30
55#define SIGSYS 31
56#define SIGUNUSED 31
57
58/* These should not be considered constants from userland. */
59#define SIGRTMIN 32
60#define SIGRTMAX _NSIG
61
62/*
63 * SA_FLAGS values:
64 *
65 * SA_ONSTACK is not currently supported, but will allow sigaltstack(2).
66 * SA_RESTART flag to get restarting signals (which were the default long ago)
67 * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
68 * SA_RESETHAND clears the handler when the signal is delivered.
69 * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
70 * SA_NODEFER prevents the current signal from being masked in the handler.
71 *
72 * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
73 * Unix names RESETHAND and NODEFER respectively.
74 */
75#define SA_NOCLDSTOP 0x00000001U
76#define SA_NOCLDWAIT 0x00000002U
77#define SA_SIGINFO 0x00000004U
78#define SA_ONSTACK 0x08000000U
79#define SA_RESTART 0x10000000U
80#define SA_NODEFER 0x40000000U
81#define SA_RESETHAND 0x80000000U
82
83#define SA_NOMASK SA_NODEFER
84#define SA_ONESHOT SA_RESETHAND
85
86#define SA_RESTORER 0x04000000U
87
88/*
89 * sigaltstack controls
90 */
91#define SS_ONSTACK 1
92#define SS_DISABLE 2
93
94#define MINSIGSTKSZ 2048
95#define SIGSTKSZ 8192
96
97#include <asm-generic/signal.h>
98
99struct old_sigaction {
100 __sighandler_t sa_handler;
101 old_sigset_t sa_mask;
102 unsigned long sa_flags;
103 __sigrestore_t sa_restorer;
104};
105
106struct sigaction {
107 __sighandler_t sa_handler;
108 unsigned long sa_flags;
109 __sigrestore_t sa_restorer;
110 sigset_t sa_mask; /* mask last for extensibility */
111};
112
113struct k_sigaction {
114 struct sigaction sa;
115};
116
117typedef struct sigaltstack {
118 void __user *ss_sp;
119 int ss_flags;
120 size_t ss_size;
121} stack_t;
122
123#ifdef __KERNEL__
124struct pt_regs;
125extern int do_signal(sigset_t *oldset, struct pt_regs *regs);
126extern int do_signal32(sigset_t *oldset, struct pt_regs *regs);
127#define ptrace_signal_deliver(regs, cookie) do { } while (0)
128#endif /* __KERNEL__ */
129
130#ifndef __powerpc64__
131/*
132 * These are parameters to dbg_sigreturn syscall. They enable or
133 * disable certain debugging things that can be done from signal
134 * handlers. The dbg_sigreturn syscall *must* be called from a
135 * SA_SIGINFO signal so the ucontext can be passed to it. It takes an
136 * array of struct sig_dbg_op, which has the debug operations to
137 * perform before returning from the signal.
138 */
139struct sig_dbg_op {
140 int dbg_type;
141 unsigned long dbg_value;
142};
143
144/* Enable or disable single-stepping. The value sets the state. */
145#define SIG_DBG_SINGLE_STEPPING 1
146
147/* Enable or disable branch tracing. The value sets the state. */
148#define SIG_DBG_BRANCH_TRACING 2
149#endif /* ! __powerpc64__ */
150
151#endif /* _ASM_POWERPC_SIGNAL_H */
diff --git a/include/asm-powerpc/smp.h b/include/asm-powerpc/smp.h
deleted file mode 100644
index 416d4c288ce..00000000000
--- a/include/asm-powerpc/smp.h
+++ /dev/null
@@ -1,125 +0,0 @@
1/*
2 * smp.h: PowerPC-specific SMP code.
3 *
4 * Original was a copy of sparc smp.h. Now heavily modified
5 * for PPC.
6 *
7 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
8 * Copyright (C) 1996-2001 Cort Dougan <cort@fsmlabs.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15
16#ifndef _ASM_POWERPC_SMP_H
17#define _ASM_POWERPC_SMP_H
18#ifdef __KERNEL__
19
20#include <linux/threads.h>
21#include <linux/cpumask.h>
22#include <linux/kernel.h>
23
24#ifndef __ASSEMBLY__
25
26#ifdef CONFIG_PPC64
27#include <asm/paca.h>
28#endif
29#include <asm/percpu.h>
30
31extern int boot_cpuid;
32
33extern void cpu_die(void);
34
35#ifdef CONFIG_SMP
36
37extern void smp_send_debugger_break(int cpu);
38extern void smp_message_recv(int);
39
40DECLARE_PER_CPU(unsigned int, pvr);
41
42#ifdef CONFIG_HOTPLUG_CPU
43extern void fixup_irqs(cpumask_t map);
44int generic_cpu_disable(void);
45int generic_cpu_enable(unsigned int cpu);
46void generic_cpu_die(unsigned int cpu);
47void generic_mach_cpu_die(void);
48#endif
49
50#ifdef CONFIG_PPC64
51#define raw_smp_processor_id() (local_paca->paca_index)
52#define hard_smp_processor_id() (get_paca()->hw_cpu_id)
53#else
54/* 32-bit */
55extern int smp_hw_index[];
56
57#define raw_smp_processor_id() (current_thread_info()->cpu)
58#define hard_smp_processor_id() (smp_hw_index[smp_processor_id()])
59#define get_hard_smp_processor_id(cpu) (smp_hw_index[(cpu)])
60#define set_hard_smp_processor_id(cpu, phys)\
61 (smp_hw_index[(cpu)] = (phys))
62#endif
63
64DECLARE_PER_CPU(cpumask_t, cpu_sibling_map);
65
66/* Since OpenPIC has only 4 IPIs, we use slightly different message numbers.
67 *
68 * Make sure this matches openpic_request_IPIs in open_pic.c, or what shows up
69 * in /proc/interrupts will be wrong!!! --Troy */
70#define PPC_MSG_CALL_FUNCTION 0
71#define PPC_MSG_RESCHEDULE 1
72#define PPC_MSG_CALL_FUNC_SINGLE 2
73#define PPC_MSG_DEBUGGER_BREAK 3
74
75void smp_init_iSeries(void);
76void smp_init_pSeries(void);
77void smp_init_cell(void);
78void smp_init_celleb(void);
79void smp_setup_cpu_maps(void);
80void smp_setup_cpu_sibling_map(void);
81
82extern int __cpu_disable(void);
83extern void __cpu_die(unsigned int cpu);
84
85#else
86/* for UP */
87#define hard_smp_processor_id() 0
88#define smp_setup_cpu_maps()
89
90#endif /* CONFIG_SMP */
91
92#ifdef CONFIG_PPC64
93#define get_hard_smp_processor_id(CPU) (paca[(CPU)].hw_cpu_id)
94#define set_hard_smp_processor_id(CPU, VAL) \
95 do { (paca[(CPU)].hw_cpu_id = (VAL)); } while (0)
96
97extern void smp_release_cpus(void);
98
99#else
100/* 32-bit */
101#ifndef CONFIG_SMP
102extern int boot_cpuid_phys;
103#define get_hard_smp_processor_id(cpu) boot_cpuid_phys
104#define set_hard_smp_processor_id(cpu, phys)
105#endif
106#endif
107
108extern int smt_enabled_at_boot;
109
110extern int smp_mpic_probe(void);
111extern void smp_mpic_setup_cpu(int cpu);
112extern void smp_generic_kick_cpu(int nr);
113
114extern void smp_generic_give_timebase(void);
115extern void smp_generic_take_timebase(void);
116
117extern struct smp_ops_t *smp_ops;
118
119extern void arch_send_call_function_single_ipi(int cpu);
120extern void arch_send_call_function_ipi(cpumask_t mask);
121
122#endif /* __ASSEMBLY__ */
123
124#endif /* __KERNEL__ */
125#endif /* _ASM_POWERPC_SMP_H) */
diff --git a/include/asm-powerpc/smu.h b/include/asm-powerpc/smu.h
deleted file mode 100644
index 7ae2753da56..00000000000
--- a/include/asm-powerpc/smu.h
+++ /dev/null
@@ -1,700 +0,0 @@
1#ifndef _SMU_H
2#define _SMU_H
3
4/*
5 * Definitions for talking to the SMU chip in newer G5 PowerMacs
6 */
7#ifdef __KERNEL__
8#include <linux/list.h>
9#endif
10#include <linux/types.h>
11
12/*
13 * Known SMU commands
14 *
15 * Most of what is below comes from looking at the Open Firmware driver,
16 * though this is still incomplete and could use better documentation here
17 * or there...
18 */
19
20
21/*
22 * Partition info commands
23 *
24 * These commands are used to retrieve the sdb-partition-XX datas from
25 * the SMU. The length is always 2. First byte is the subcommand code
26 * and second byte is the partition ID.
27 *
28 * The reply is 6 bytes:
29 *
30 * - 0..1 : partition address
31 * - 2 : a byte containing the partition ID
32 * - 3 : length (maybe other bits are rest of header ?)
33 *
34 * The data must then be obtained with calls to another command:
35 * SMU_CMD_MISC_ee_GET_DATABLOCK_REC (described below).
36 */
37#define SMU_CMD_PARTITION_COMMAND 0x3e
38#define SMU_CMD_PARTITION_LATEST 0x01
39#define SMU_CMD_PARTITION_BASE 0x02
40#define SMU_CMD_PARTITION_UPDATE 0x03
41
42
43/*
44 * Fan control
45 *
46 * This is a "mux" for fan control commands. The command seem to
47 * act differently based on the number of arguments. With 1 byte
48 * of argument, this seem to be queries for fans status, setpoint,
49 * etc..., while with 0xe arguments, we will set the fans speeds.
50 *
51 * Queries (1 byte arg):
52 * ---------------------
53 *
54 * arg=0x01: read RPM fans status
55 * arg=0x02: read RPM fans setpoint
56 * arg=0x11: read PWM fans status
57 * arg=0x12: read PWM fans setpoint
58 *
59 * the "status" queries return the current speed while the "setpoint" ones
60 * return the programmed/target speed. It _seems_ that the result is a bit
61 * mask in the first byte of active/available fans, followed by 6 words (16
62 * bits) containing the requested speed.
63 *
64 * Setpoint (14 bytes arg):
65 * ------------------------
66 *
67 * first arg byte is 0 for RPM fans and 0x10 for PWM. Second arg byte is the
68 * mask of fans affected by the command. Followed by 6 words containing the
69 * setpoint value for selected fans in the mask (or 0 if mask value is 0)
70 */
71#define SMU_CMD_FAN_COMMAND 0x4a
72
73
74/*
75 * Battery access
76 *
77 * Same command number as the PMU, could it be same syntax ?
78 */
79#define SMU_CMD_BATTERY_COMMAND 0x6f
80#define SMU_CMD_GET_BATTERY_INFO 0x00
81
82/*
83 * Real time clock control
84 *
85 * This is a "mux", first data byte contains the "sub" command.
86 * The "RTC" part of the SMU controls the date, time, powerup
87 * timer, but also a PRAM
88 *
89 * Dates are in BCD format on 7 bytes:
90 * [sec] [min] [hour] [weekday] [month day] [month] [year]
91 * with month being 1 based and year minus 100
92 */
93#define SMU_CMD_RTC_COMMAND 0x8e
94#define SMU_CMD_RTC_SET_PWRUP_TIMER 0x00 /* i: 7 bytes date */
95#define SMU_CMD_RTC_GET_PWRUP_TIMER 0x01 /* o: 7 bytes date */
96#define SMU_CMD_RTC_STOP_PWRUP_TIMER 0x02
97#define SMU_CMD_RTC_SET_PRAM_BYTE_ACC 0x20 /* i: 1 byte (address?) */
98#define SMU_CMD_RTC_SET_PRAM_AUTOINC 0x21 /* i: 1 byte (data?) */
99#define SMU_CMD_RTC_SET_PRAM_LO_BYTES 0x22 /* i: 10 bytes */
100#define SMU_CMD_RTC_SET_PRAM_HI_BYTES 0x23 /* i: 10 bytes */
101#define SMU_CMD_RTC_GET_PRAM_BYTE 0x28 /* i: 1 bytes (address?) */
102#define SMU_CMD_RTC_GET_PRAM_LO_BYTES 0x29 /* o: 10 bytes */
103#define SMU_CMD_RTC_GET_PRAM_HI_BYTES 0x2a /* o: 10 bytes */
104#define SMU_CMD_RTC_SET_DATETIME 0x80 /* i: 7 bytes date */
105#define SMU_CMD_RTC_GET_DATETIME 0x81 /* o: 7 bytes date */
106
107 /*
108 * i2c commands
109 *
110 * To issue an i2c command, first is to send a parameter block to the
111 * the SMU. This is a command of type 0x9a with 9 bytes of header
112 * eventually followed by data for a write:
113 *
114 * 0: bus number (from device-tree usually, SMU has lots of busses !)
115 * 1: transfer type/format (see below)
116 * 2: device address. For combined and combined4 type transfers, this
117 * is the "write" version of the address (bit 0x01 cleared)
118 * 3: subaddress length (0..3)
119 * 4: subaddress byte 0 (or only byte for subaddress length 1)
120 * 5: subaddress byte 1
121 * 6: subaddress byte 2
122 * 7: combined address (device address for combined mode data phase)
123 * 8: data length
124 *
125 * The transfer types are the same good old Apple ones it seems,
126 * that is:
127 * - 0x00: Simple transfer
128 * - 0x01: Subaddress transfer (addr write + data tx, no restart)
129 * - 0x02: Combined transfer (addr write + restart + data tx)
130 *
131 * This is then followed by actual data for a write.
132 *
133 * At this point, the OF driver seems to have a limitation on transfer
134 * sizes of 0xd bytes on reads and 0x5 bytes on writes. I do not know
135 * wether this is just an OF limit due to some temporary buffer size
136 * or if this is an SMU imposed limit. This driver has the same limitation
137 * for now as I use a 0x10 bytes temporary buffer as well
138 *
139 * Once that is completed, a response is expected from the SMU. This is
140 * obtained via a command of type 0x9a with a length of 1 byte containing
141 * 0 as the data byte. OF also fills the rest of the data buffer with 0xff's
142 * though I can't tell yet if this is actually necessary. Once this command
143 * is complete, at this point, all I can tell is what OF does. OF tests
144 * byte 0 of the reply:
145 * - on read, 0xfe or 0xfc : bus is busy, wait (see below) or nak ?
146 * - on read, 0x00 or 0x01 : reply is in buffer (after the byte 0)
147 * - on write, < 0 -> failure (immediate exit)
148 * - else, OF just exists (without error, weird)
149 *
150 * So on read, there is this wait-for-busy thing when getting a 0xfc or
151 * 0xfe result. OF does a loop of up to 64 retries, waiting 20ms and
152 * doing the above again until either the retries expire or the result
153 * is no longer 0xfe or 0xfc
154 *
155 * The Darwin I2C driver is less subtle though. On any non-success status
156 * from the response command, it waits 5ms and tries again up to 20 times,
157 * it doesn't differenciate between fatal errors or "busy" status.
158 *
159 * This driver provides an asynchronous paramblock based i2c command
160 * interface to be used either directly by low level code or by a higher
161 * level driver interfacing to the linux i2c layer. The current
162 * implementation of this relies on working timers & timer interrupts
163 * though, so be careful of calling context for now. This may be "fixed"
164 * in the future by adding a polling facility.
165 */
166#define SMU_CMD_I2C_COMMAND 0x9a
167 /* transfer types */
168#define SMU_I2C_TRANSFER_SIMPLE 0x00
169#define SMU_I2C_TRANSFER_STDSUB 0x01
170#define SMU_I2C_TRANSFER_COMBINED 0x02
171
172/*
173 * Power supply control
174 *
175 * The "sub" command is an ASCII string in the data, the
176 * data length is that of the string.
177 *
178 * The VSLEW command can be used to get or set the voltage slewing.
179 * - length 5 (only "VSLEW") : it returns "DONE" and 3 bytes of
180 * reply at data offset 6, 7 and 8.
181 * - length 8 ("VSLEWxyz") has 3 additional bytes appended, and is
182 * used to set the voltage slewing point. The SMU replies with "DONE"
183 * I yet have to figure out their exact meaning of those 3 bytes in
184 * both cases. They seem to be:
185 * x = processor mask
186 * y = op. point index
187 * z = processor freq. step index
188 * I haven't yet decyphered result codes
189 *
190 */
191#define SMU_CMD_POWER_COMMAND 0xaa
192#define SMU_CMD_POWER_RESTART "RESTART"
193#define SMU_CMD_POWER_SHUTDOWN "SHUTDOWN"
194#define SMU_CMD_POWER_VOLTAGE_SLEW "VSLEW"
195
196/*
197 * Read ADC sensors
198 *
199 * This command takes one byte of parameter: the sensor ID (or "reg"
200 * value in the device-tree) and returns a 16 bits value
201 */
202#define SMU_CMD_READ_ADC 0xd8
203
204
205/* Misc commands
206 *
207 * This command seem to be a grab bag of various things
208 *
209 * Parameters:
210 * 1: subcommand
211 */
212#define SMU_CMD_MISC_df_COMMAND 0xdf
213
214/*
215 * Sets "system ready" status
216 *
217 * I did not yet understand how it exactly works or what it does.
218 *
219 * Guessing from OF code, 0x02 activates the display backlight. Apple uses/used
220 * the same codebase for all OF versions. On PowerBooks, this command would
221 * enable the backlight. For the G5s, it only activates the front LED. However,
222 * don't take this for granted.
223 *
224 * Parameters:
225 * 2: status [0x00, 0x01 or 0x02]
226 */
227#define SMU_CMD_MISC_df_SET_DISPLAY_LIT 0x02
228
229/*
230 * Sets mode of power switch.
231 *
232 * What this actually does is not yet known. Maybe it enables some interrupt.
233 *
234 * Parameters:
235 * 2: enable power switch? [0x00 or 0x01]
236 * 3 (optional): enable nmi? [0x00 or 0x01]
237 *
238 * Returns:
239 * If parameter 2 is 0x00 and parameter 3 is not specified, returns wether
240 * NMI is enabled. Otherwise unknown.
241 */
242#define SMU_CMD_MISC_df_NMI_OPTION 0x04
243
244/* Sets LED dimm offset.
245 *
246 * The front LED dimms itself during sleep. Its brightness (or, well, the PWM
247 * frequency) depends on current time. Therefore, the SMU needs to know the
248 * timezone.
249 *
250 * Parameters:
251 * 2-8: unknown (BCD coding)
252 */
253#define SMU_CMD_MISC_df_DIMM_OFFSET 0x99
254
255
256/*
257 * Version info commands
258 *
259 * Parameters:
260 * 1 (optional): Specifies version part to retrieve
261 *
262 * Returns:
263 * Version value
264 */
265#define SMU_CMD_VERSION_COMMAND 0xea
266#define SMU_VERSION_RUNNING 0x00
267#define SMU_VERSION_BASE 0x01
268#define SMU_VERSION_UPDATE 0x02
269
270
271/*
272 * Switches
273 *
274 * These are switches whose status seems to be known to the SMU.
275 *
276 * Parameters:
277 * none
278 *
279 * Result:
280 * Switch bits (ORed, see below)
281 */
282#define SMU_CMD_SWITCHES 0xdc
283
284/* Switches bits */
285#define SMU_SWITCH_CASE_CLOSED 0x01
286#define SMU_SWITCH_AC_POWER 0x04
287#define SMU_SWITCH_POWER_SWITCH 0x08
288
289
290/*
291 * Misc commands
292 *
293 * This command seem to be a grab bag of various things
294 *
295 * SMU_CMD_MISC_ee_GET_DATABLOCK_REC is used, among others, to
296 * transfer blocks of data from the SMU. So far, I've decrypted it's
297 * usage to retrieve partition data. In order to do that, you have to
298 * break your transfer in "chunks" since that command cannot transfer
299 * more than a chunk at a time. The chunk size used by OF is 0xe bytes,
300 * but it seems that the darwin driver will let you do 0x1e bytes if
301 * your "PMU" version is >= 0x30. You can get the "PMU" version apparently
302 * either in the last 16 bits of property "smu-version-pmu" or as the 16
303 * bytes at offset 1 of "smu-version-info"
304 *
305 * For each chunk, the command takes 7 bytes of arguments:
306 * byte 0: subcommand code (0x02)
307 * byte 1: 0x04 (always, I don't know what it means, maybe the address
308 * space to use or some other nicety. It's hard coded in OF)
309 * byte 2..5: SMU address of the chunk (big endian 32 bits)
310 * byte 6: size to transfer (up to max chunk size)
311 *
312 * The data is returned directly
313 */
314#define SMU_CMD_MISC_ee_COMMAND 0xee
315#define SMU_CMD_MISC_ee_GET_DATABLOCK_REC 0x02
316
317/* Retrieves currently used watts.
318 *
319 * Parameters:
320 * 1: 0x03 (Meaning unknown)
321 */
322#define SMU_CMD_MISC_ee_GET_WATTS 0x03
323
324#define SMU_CMD_MISC_ee_LEDS_CTRL 0x04 /* i: 00 (00,01) [00] */
325#define SMU_CMD_MISC_ee_GET_DATA 0x05 /* i: 00 , o: ?? */
326
327
328/*
329 * Power related commands
330 *
331 * Parameters:
332 * 1: subcommand
333 */
334#define SMU_CMD_POWER_EVENTS_COMMAND 0x8f
335
336/* SMU_POWER_EVENTS subcommands */
337enum {
338 SMU_PWR_GET_POWERUP_EVENTS = 0x00,
339 SMU_PWR_SET_POWERUP_EVENTS = 0x01,
340 SMU_PWR_CLR_POWERUP_EVENTS = 0x02,
341 SMU_PWR_GET_WAKEUP_EVENTS = 0x03,
342 SMU_PWR_SET_WAKEUP_EVENTS = 0x04,
343 SMU_PWR_CLR_WAKEUP_EVENTS = 0x05,
344
345 /*
346 * Get last shutdown cause
347 *
348 * Returns:
349 * 1 byte (signed char): Last shutdown cause. Exact meaning unknown.
350 */
351 SMU_PWR_LAST_SHUTDOWN_CAUSE = 0x07,
352
353 /*
354 * Sets or gets server ID. Meaning or use is unknown.
355 *
356 * Parameters:
357 * 2 (optional): Set server ID (1 byte)
358 *
359 * Returns:
360 * 1 byte (server ID?)
361 */
362 SMU_PWR_SERVER_ID = 0x08,
363};
364
365/* Power events wakeup bits */
366enum {
367 SMU_PWR_WAKEUP_KEY = 0x01, /* Wake on key press */
368 SMU_PWR_WAKEUP_AC_INSERT = 0x02, /* Wake on AC adapter plug */
369 SMU_PWR_WAKEUP_AC_CHANGE = 0x04,
370 SMU_PWR_WAKEUP_LID_OPEN = 0x08,
371 SMU_PWR_WAKEUP_RING = 0x10,
372};
373
374
375/*
376 * - Kernel side interface -
377 */
378
379#ifdef __KERNEL__
380
381/*
382 * Asynchronous SMU commands
383 *
384 * Fill up this structure and submit it via smu_queue_command(),
385 * and get notified by the optional done() callback, or because
386 * status becomes != 1
387 */
388
389struct smu_cmd;
390
391struct smu_cmd
392{
393 /* public */
394 u8 cmd; /* command */
395 int data_len; /* data len */
396 int reply_len; /* reply len */
397 void *data_buf; /* data buffer */
398 void *reply_buf; /* reply buffer */
399 int status; /* command status */
400 void (*done)(struct smu_cmd *cmd, void *misc);
401 void *misc;
402
403 /* private */
404 struct list_head link;
405};
406
407/*
408 * Queues an SMU command, all fields have to be initialized
409 */
410extern int smu_queue_cmd(struct smu_cmd *cmd);
411
412/*
413 * Simple command wrapper. This structure embeds a small buffer
414 * to ease sending simple SMU commands from the stack
415 */
416struct smu_simple_cmd
417{
418 struct smu_cmd cmd;
419 u8 buffer[16];
420};
421
422/*
423 * Queues a simple command. All fields will be initialized by that
424 * function
425 */
426extern int smu_queue_simple(struct smu_simple_cmd *scmd, u8 command,
427 unsigned int data_len,
428 void (*done)(struct smu_cmd *cmd, void *misc),
429 void *misc,
430 ...);
431
432/*
433 * Completion helper. Pass it to smu_queue_simple or as 'done'
434 * member to smu_queue_cmd, it will call complete() on the struct
435 * completion passed in the "misc" argument
436 */
437extern void smu_done_complete(struct smu_cmd *cmd, void *misc);
438
439/*
440 * Synchronous helpers. Will spin-wait for completion of a command
441 */
442extern void smu_spinwait_cmd(struct smu_cmd *cmd);
443
444static inline void smu_spinwait_simple(struct smu_simple_cmd *scmd)
445{
446 smu_spinwait_cmd(&scmd->cmd);
447}
448
449/*
450 * Poll routine to call if blocked with irqs off
451 */
452extern void smu_poll(void);
453
454
455/*
456 * Init routine, presence check....
457 */
458extern int smu_init(void);
459extern int smu_present(void);
460struct of_device;
461extern struct of_device *smu_get_ofdev(void);
462
463
464/*
465 * Common command wrappers
466 */
467extern void smu_shutdown(void);
468extern void smu_restart(void);
469struct rtc_time;
470extern int smu_get_rtc_time(struct rtc_time *time, int spinwait);
471extern int smu_set_rtc_time(struct rtc_time *time, int spinwait);
472
473/*
474 * SMU command buffer absolute address, exported by pmac_setup,
475 * this is allocated very early during boot.
476 */
477extern unsigned long smu_cmdbuf_abs;
478
479
480/*
481 * Kenrel asynchronous i2c interface
482 */
483
484#define SMU_I2C_READ_MAX 0x1d
485#define SMU_I2C_WRITE_MAX 0x15
486
487/* SMU i2c header, exactly matches i2c header on wire */
488struct smu_i2c_param
489{
490 u8 bus; /* SMU bus ID (from device tree) */
491 u8 type; /* i2c transfer type */
492 u8 devaddr; /* device address (includes direction) */
493 u8 sublen; /* subaddress length */
494 u8 subaddr[3]; /* subaddress */
495 u8 caddr; /* combined address, filled by SMU driver */
496 u8 datalen; /* length of transfer */
497 u8 data[SMU_I2C_READ_MAX]; /* data */
498};
499
500struct smu_i2c_cmd
501{
502 /* public */
503 struct smu_i2c_param info;
504 void (*done)(struct smu_i2c_cmd *cmd, void *misc);
505 void *misc;
506 int status; /* 1 = pending, 0 = ok, <0 = fail */
507
508 /* private */
509 struct smu_cmd scmd;
510 int read;
511 int stage;
512 int retries;
513 u8 pdata[32];
514 struct list_head link;
515};
516
517/*
518 * Call this to queue an i2c command to the SMU. You must fill info,
519 * including info.data for a write, done and misc.
520 * For now, no polling interface is provided so you have to use completion
521 * callback.
522 */
523extern int smu_queue_i2c(struct smu_i2c_cmd *cmd);
524
525
526#endif /* __KERNEL__ */
527
528
529/*
530 * - SMU "sdb" partitions informations -
531 */
532
533
534/*
535 * Partition header format
536 */
537struct smu_sdbp_header {
538 __u8 id;
539 __u8 len;
540 __u8 version;
541 __u8 flags;
542};
543
544
545 /*
546 * demangle 16 and 32 bits integer in some SMU partitions
547 * (currently, afaik, this concerns only the FVT partition
548 * (0x12)
549 */
550#define SMU_U16_MIX(x) le16_to_cpu(x);
551#define SMU_U32_MIX(x) ((((x) & 0xff00ff00u) >> 8)|(((x) & 0x00ff00ffu) << 8))
552
553
554/* This is the definition of the SMU sdb-partition-0x12 table (called
555 * CPU F/V/T operating points in Darwin). The definition for all those
556 * SMU tables should be moved to some separate file
557 */
558#define SMU_SDB_FVT_ID 0x12
559
560struct smu_sdbp_fvt {
561 __u32 sysclk; /* Base SysClk frequency in Hz for
562 * this operating point. Value need to
563 * be unmixed with SMU_U32_MIX()
564 */
565 __u8 pad;
566 __u8 maxtemp; /* Max temp. supported by this
567 * operating point
568 */
569
570 __u16 volts[3]; /* CPU core voltage for the 3
571 * PowerTune modes, a mode with
572 * 0V = not supported. Value need
573 * to be unmixed with SMU_U16_MIX()
574 */
575};
576
577/* This partition contains voltage & current sensor calibration
578 * informations
579 */
580#define SMU_SDB_CPUVCP_ID 0x21
581
582struct smu_sdbp_cpuvcp {
583 __u16 volt_scale; /* u4.12 fixed point */
584 __s16 volt_offset; /* s4.12 fixed point */
585 __u16 curr_scale; /* u4.12 fixed point */
586 __s16 curr_offset; /* s4.12 fixed point */
587 __s32 power_quads[3]; /* s4.28 fixed point */
588};
589
590/* This partition contains CPU thermal diode calibration
591 */
592#define SMU_SDB_CPUDIODE_ID 0x18
593
594struct smu_sdbp_cpudiode {
595 __u16 m_value; /* u1.15 fixed point */
596 __s16 b_value; /* s10.6 fixed point */
597
598};
599
600/* This partition contains Slots power calibration
601 */
602#define SMU_SDB_SLOTSPOW_ID 0x78
603
604struct smu_sdbp_slotspow {
605 __u16 pow_scale; /* u4.12 fixed point */
606 __s16 pow_offset; /* s4.12 fixed point */
607};
608
609/* This partition contains machine specific version information about
610 * the sensor/control layout
611 */
612#define SMU_SDB_SENSORTREE_ID 0x25
613
614struct smu_sdbp_sensortree {
615 __u8 model_id;
616 __u8 unknown[3];
617};
618
619/* This partition contains CPU thermal control PID informations. So far
620 * only single CPU machines have been seen with an SMU, so we assume this
621 * carries only informations for those
622 */
623#define SMU_SDB_CPUPIDDATA_ID 0x17
624
625struct smu_sdbp_cpupiddata {
626 __u8 unknown1;
627 __u8 target_temp_delta;
628 __u8 unknown2;
629 __u8 history_len;
630 __s16 power_adj;
631 __u16 max_power;
632 __s32 gp,gr,gd;
633};
634
635
636/* Other partitions without known structures */
637#define SMU_SDB_DEBUG_SWITCHES_ID 0x05
638
639#ifdef __KERNEL__
640/*
641 * This returns the pointer to an SMU "sdb" partition data or NULL
642 * if not found. The data format is described below
643 */
644extern const struct smu_sdbp_header *smu_get_sdb_partition(int id,
645 unsigned int *size);
646
647/* Get "sdb" partition data from an SMU satellite */
648extern struct smu_sdbp_header *smu_sat_get_sdb_partition(unsigned int sat_id,
649 int id, unsigned int *size);
650
651
652#endif /* __KERNEL__ */
653
654
655/*
656 * - Userland interface -
657 */
658
659/*
660 * A given instance of the device can be configured for 2 different
661 * things at the moment:
662 *
663 * - sending SMU commands (default at open() time)
664 * - receiving SMU events (not yet implemented)
665 *
666 * Commands are written with write() of a command block. They can be
667 * "driver" commands (for example to switch to event reception mode)
668 * or real SMU commands. They are made of a header followed by command
669 * data if any.
670 *
671 * For SMU commands (not for driver commands), you can then read() back
672 * a reply. The reader will be blocked or not depending on how the device
673 * file is opened. poll() isn't implemented yet. The reply will consist
674 * of a header as well, followed by the reply data if any. You should
675 * always provide a buffer large enough for the maximum reply data, I
676 * recommand one page.
677 *
678 * It is illegal to send SMU commands through a file descriptor configured
679 * for events reception
680 *
681 */
682struct smu_user_cmd_hdr
683{
684 __u32 cmdtype;
685#define SMU_CMDTYPE_SMU 0 /* SMU command */
686#define SMU_CMDTYPE_WANTS_EVENTS 1 /* switch fd to events mode */
687#define SMU_CMDTYPE_GET_PARTITION 2 /* retrieve an sdb partition */
688
689 __u8 cmd; /* SMU command byte */
690 __u8 pad[3]; /* padding */
691 __u32 data_len; /* Length of data following */
692};
693
694struct smu_user_reply_hdr
695{
696 __u32 status; /* Command status */
697 __u32 reply_len; /* Length of data follwing */
698};
699
700#endif /* _SMU_H */
diff --git a/include/asm-powerpc/socket.h b/include/asm-powerpc/socket.h
deleted file mode 100644
index f5a4e168e49..00000000000
--- a/include/asm-powerpc/socket.h
+++ /dev/null
@@ -1,64 +0,0 @@
1#ifndef _ASM_POWERPC_SOCKET_H
2#define _ASM_POWERPC_SOCKET_H
3
4/*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10
11#include <asm/sockios.h>
12
13/* For setsockopt(2) */
14#define SOL_SOCKET 1
15
16#define SO_DEBUG 1
17#define SO_REUSEADDR 2
18#define SO_TYPE 3
19#define SO_ERROR 4
20#define SO_DONTROUTE 5
21#define SO_BROADCAST 6
22#define SO_SNDBUF 7
23#define SO_RCVBUF 8
24#define SO_SNDBUFFORCE 32
25#define SO_RCVBUFFORCE 33
26#define SO_KEEPALIVE 9
27#define SO_OOBINLINE 10
28#define SO_NO_CHECK 11
29#define SO_PRIORITY 12
30#define SO_LINGER 13
31#define SO_BSDCOMPAT 14
32/* To add :#define SO_REUSEPORT 15 */
33#define SO_RCVLOWAT 16
34#define SO_SNDLOWAT 17
35#define SO_RCVTIMEO 18
36#define SO_SNDTIMEO 19
37#define SO_PASSCRED 20
38#define SO_PEERCRED 21
39
40/* Security levels - as per NRL IPv6 - don't actually do anything */
41#define SO_SECURITY_AUTHENTICATION 22
42#define SO_SECURITY_ENCRYPTION_TRANSPORT 23
43#define SO_SECURITY_ENCRYPTION_NETWORK 24
44
45#define SO_BINDTODEVICE 25
46
47/* Socket filtering */
48#define SO_ATTACH_FILTER 26
49#define SO_DETACH_FILTER 27
50
51#define SO_PEERNAME 28
52#define SO_TIMESTAMP 29
53#define SCM_TIMESTAMP SO_TIMESTAMP
54
55#define SO_ACCEPTCONN 30
56
57#define SO_PEERSEC 31
58#define SO_PASSSEC 34
59#define SO_TIMESTAMPNS 35
60#define SCM_TIMESTAMPNS SO_TIMESTAMPNS
61
62#define SO_MARK 36
63
64#endif /* _ASM_POWERPC_SOCKET_H */
diff --git a/include/asm-powerpc/sockios.h b/include/asm-powerpc/sockios.h
deleted file mode 100644
index 55cef7675a3..00000000000
--- a/include/asm-powerpc/sockios.h
+++ /dev/null
@@ -1,20 +0,0 @@
1#ifndef _ASM_POWERPC_SOCKIOS_H
2#define _ASM_POWERPC_SOCKIOS_H
3
4/*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10
11/* Socket-level I/O control calls. */
12#define FIOSETOWN 0x8901
13#define SIOCSPGRP 0x8902
14#define FIOGETOWN 0x8903
15#define SIOCGPGRP 0x8904
16#define SIOCATMARK 0x8905
17#define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */
18#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */
19
20#endif /* _ASM_POWERPC_SOCKIOS_H */
diff --git a/include/asm-powerpc/sparsemem.h b/include/asm-powerpc/sparsemem.h
deleted file mode 100644
index 54a47ea2c3a..00000000000
--- a/include/asm-powerpc/sparsemem.h
+++ /dev/null
@@ -1,32 +0,0 @@
1#ifndef _ASM_POWERPC_SPARSEMEM_H
2#define _ASM_POWERPC_SPARSEMEM_H 1
3#ifdef __KERNEL__
4
5#ifdef CONFIG_SPARSEMEM
6/*
7 * SECTION_SIZE_BITS 2^N: how big each section will be
8 * MAX_PHYSADDR_BITS 2^N: how much physical address space we have
9 * MAX_PHYSMEM_BITS 2^N: how much memory we can have in that space
10 */
11#define SECTION_SIZE_BITS 24
12
13#define MAX_PHYSADDR_BITS 44
14#define MAX_PHYSMEM_BITS 44
15
16#endif /* CONFIG_SPARSEMEM */
17
18#ifdef CONFIG_MEMORY_HOTPLUG
19extern void create_section_mapping(unsigned long start, unsigned long end);
20extern int remove_section_mapping(unsigned long start, unsigned long end);
21#ifdef CONFIG_NUMA
22extern int hot_add_scn_to_nid(unsigned long scn_addr);
23#else
24static inline int hot_add_scn_to_nid(unsigned long scn_addr)
25{
26 return 0;
27}
28#endif /* CONFIG_NUMA */
29#endif /* CONFIG_MEMORY_HOTPLUG */
30
31#endif /* __KERNEL__ */
32#endif /* _ASM_POWERPC_SPARSEMEM_H */
diff --git a/include/asm-powerpc/spinlock.h b/include/asm-powerpc/spinlock.h
deleted file mode 100644
index f56a843f470..00000000000
--- a/include/asm-powerpc/spinlock.h
+++ /dev/null
@@ -1,295 +0,0 @@
1#ifndef __ASM_SPINLOCK_H
2#define __ASM_SPINLOCK_H
3#ifdef __KERNEL__
4
5/*
6 * Simple spin lock operations.
7 *
8 * Copyright (C) 2001-2004 Paul Mackerras <paulus@au.ibm.com>, IBM
9 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
10 * Copyright (C) 2002 Dave Engebretsen <engebret@us.ibm.com>, IBM
11 * Rework to support virtual processors
12 *
13 * Type of int is used as a full 64b word is not necessary.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 *
20 * (the type definitions are in asm/spinlock_types.h)
21 */
22#include <linux/irqflags.h>
23#ifdef CONFIG_PPC64
24#include <asm/paca.h>
25#include <asm/hvcall.h>
26#include <asm/iseries/hv_call.h>
27#endif
28#include <asm/asm-compat.h>
29#include <asm/synch.h>
30
31#define __raw_spin_is_locked(x) ((x)->slock != 0)
32
33#ifdef CONFIG_PPC64
34/* use 0x800000yy when locked, where yy == CPU number */
35#define LOCK_TOKEN (*(u32 *)(&get_paca()->lock_token))
36#else
37#define LOCK_TOKEN 1
38#endif
39
40#if defined(CONFIG_PPC64) && defined(CONFIG_SMP)
41#define CLEAR_IO_SYNC (get_paca()->io_sync = 0)
42#define SYNC_IO do { \
43 if (unlikely(get_paca()->io_sync)) { \
44 mb(); \
45 get_paca()->io_sync = 0; \
46 } \
47 } while (0)
48#else
49#define CLEAR_IO_SYNC
50#define SYNC_IO
51#endif
52
53/*
54 * This returns the old value in the lock, so we succeeded
55 * in getting the lock if the return value is 0.
56 */
57static inline unsigned long __spin_trylock(raw_spinlock_t *lock)
58{
59 unsigned long tmp, token;
60
61 token = LOCK_TOKEN;
62 __asm__ __volatile__(
63"1: lwarx %0,0,%2\n\
64 cmpwi 0,%0,0\n\
65 bne- 2f\n\
66 stwcx. %1,0,%2\n\
67 bne- 1b\n\
68 isync\n\
692:" : "=&r" (tmp)
70 : "r" (token), "r" (&lock->slock)
71 : "cr0", "memory");
72
73 return tmp;
74}
75
76static inline int __raw_spin_trylock(raw_spinlock_t *lock)
77{
78 CLEAR_IO_SYNC;
79 return __spin_trylock(lock) == 0;
80}
81
82/*
83 * On a system with shared processors (that is, where a physical
84 * processor is multiplexed between several virtual processors),
85 * there is no point spinning on a lock if the holder of the lock
86 * isn't currently scheduled on a physical processor. Instead
87 * we detect this situation and ask the hypervisor to give the
88 * rest of our timeslice to the lock holder.
89 *
90 * So that we can tell which virtual processor is holding a lock,
91 * we put 0x80000000 | smp_processor_id() in the lock when it is
92 * held. Conveniently, we have a word in the paca that holds this
93 * value.
94 */
95
96#if defined(CONFIG_PPC_SPLPAR) || defined(CONFIG_PPC_ISERIES)
97/* We only yield to the hypervisor if we are in shared processor mode */
98#define SHARED_PROCESSOR (get_lppaca()->shared_proc)
99extern void __spin_yield(raw_spinlock_t *lock);
100extern void __rw_yield(raw_rwlock_t *lock);
101#else /* SPLPAR || ISERIES */
102#define __spin_yield(x) barrier()
103#define __rw_yield(x) barrier()
104#define SHARED_PROCESSOR 0
105#endif
106
107static inline void __raw_spin_lock(raw_spinlock_t *lock)
108{
109 CLEAR_IO_SYNC;
110 while (1) {
111 if (likely(__spin_trylock(lock) == 0))
112 break;
113 do {
114 HMT_low();
115 if (SHARED_PROCESSOR)
116 __spin_yield(lock);
117 } while (unlikely(lock->slock != 0));
118 HMT_medium();
119 }
120}
121
122static inline
123void __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags)
124{
125 unsigned long flags_dis;
126
127 CLEAR_IO_SYNC;
128 while (1) {
129 if (likely(__spin_trylock(lock) == 0))
130 break;
131 local_save_flags(flags_dis);
132 local_irq_restore(flags);
133 do {
134 HMT_low();
135 if (SHARED_PROCESSOR)
136 __spin_yield(lock);
137 } while (unlikely(lock->slock != 0));
138 HMT_medium();
139 local_irq_restore(flags_dis);
140 }
141}
142
143static inline void __raw_spin_unlock(raw_spinlock_t *lock)
144{
145 SYNC_IO;
146 __asm__ __volatile__("# __raw_spin_unlock\n\t"
147 LWSYNC_ON_SMP: : :"memory");
148 lock->slock = 0;
149}
150
151#ifdef CONFIG_PPC64
152extern void __raw_spin_unlock_wait(raw_spinlock_t *lock);
153#else
154#define __raw_spin_unlock_wait(lock) \
155 do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
156#endif
157
158/*
159 * Read-write spinlocks, allowing multiple readers
160 * but only one writer.
161 *
162 * NOTE! it is quite common to have readers in interrupts
163 * but no interrupt writers. For those circumstances we
164 * can "mix" irq-safe locks - any writer needs to get a
165 * irq-safe write-lock, but readers can get non-irqsafe
166 * read-locks.
167 */
168
169#define __raw_read_can_lock(rw) ((rw)->lock >= 0)
170#define __raw_write_can_lock(rw) (!(rw)->lock)
171
172#ifdef CONFIG_PPC64
173#define __DO_SIGN_EXTEND "extsw %0,%0\n"
174#define WRLOCK_TOKEN LOCK_TOKEN /* it's negative */
175#else
176#define __DO_SIGN_EXTEND
177#define WRLOCK_TOKEN (-1)
178#endif
179
180/*
181 * This returns the old value in the lock + 1,
182 * so we got a read lock if the return value is > 0.
183 */
184static inline long __read_trylock(raw_rwlock_t *rw)
185{
186 long tmp;
187
188 __asm__ __volatile__(
189"1: lwarx %0,0,%1\n"
190 __DO_SIGN_EXTEND
191" addic. %0,%0,1\n\
192 ble- 2f\n"
193 PPC405_ERR77(0,%1)
194" stwcx. %0,0,%1\n\
195 bne- 1b\n\
196 isync\n\
1972:" : "=&r" (tmp)
198 : "r" (&rw->lock)
199 : "cr0", "xer", "memory");
200
201 return tmp;
202}
203
204/*
205 * This returns the old value in the lock,
206 * so we got the write lock if the return value is 0.
207 */
208static inline long __write_trylock(raw_rwlock_t *rw)
209{
210 long tmp, token;
211
212 token = WRLOCK_TOKEN;
213 __asm__ __volatile__(
214"1: lwarx %0,0,%2\n\
215 cmpwi 0,%0,0\n\
216 bne- 2f\n"
217 PPC405_ERR77(0,%1)
218" stwcx. %1,0,%2\n\
219 bne- 1b\n\
220 isync\n\
2212:" : "=&r" (tmp)
222 : "r" (token), "r" (&rw->lock)
223 : "cr0", "memory");
224
225 return tmp;
226}
227
228static inline void __raw_read_lock(raw_rwlock_t *rw)
229{
230 while (1) {
231 if (likely(__read_trylock(rw) > 0))
232 break;
233 do {
234 HMT_low();
235 if (SHARED_PROCESSOR)
236 __rw_yield(rw);
237 } while (unlikely(rw->lock < 0));
238 HMT_medium();
239 }
240}
241
242static inline void __raw_write_lock(raw_rwlock_t *rw)
243{
244 while (1) {
245 if (likely(__write_trylock(rw) == 0))
246 break;
247 do {
248 HMT_low();
249 if (SHARED_PROCESSOR)
250 __rw_yield(rw);
251 } while (unlikely(rw->lock != 0));
252 HMT_medium();
253 }
254}
255
256static inline int __raw_read_trylock(raw_rwlock_t *rw)
257{
258 return __read_trylock(rw) > 0;
259}
260
261static inline int __raw_write_trylock(raw_rwlock_t *rw)
262{
263 return __write_trylock(rw) == 0;
264}
265
266static inline void __raw_read_unlock(raw_rwlock_t *rw)
267{
268 long tmp;
269
270 __asm__ __volatile__(
271 "# read_unlock\n\t"
272 LWSYNC_ON_SMP
273"1: lwarx %0,0,%1\n\
274 addic %0,%0,-1\n"
275 PPC405_ERR77(0,%1)
276" stwcx. %0,0,%1\n\
277 bne- 1b"
278 : "=&r"(tmp)
279 : "r"(&rw->lock)
280 : "cr0", "memory");
281}
282
283static inline void __raw_write_unlock(raw_rwlock_t *rw)
284{
285 __asm__ __volatile__("# write_unlock\n\t"
286 LWSYNC_ON_SMP: : :"memory");
287 rw->lock = 0;
288}
289
290#define _raw_spin_relax(lock) __spin_yield(lock)
291#define _raw_read_relax(lock) __rw_yield(lock)
292#define _raw_write_relax(lock) __rw_yield(lock)
293
294#endif /* __KERNEL__ */
295#endif /* __ASM_SPINLOCK_H */
diff --git a/include/asm-powerpc/spinlock_types.h b/include/asm-powerpc/spinlock_types.h
deleted file mode 100644
index 74236c9f05b..00000000000
--- a/include/asm-powerpc/spinlock_types.h
+++ /dev/null
@@ -1,20 +0,0 @@
1#ifndef _ASM_POWERPC_SPINLOCK_TYPES_H
2#define _ASM_POWERPC_SPINLOCK_TYPES_H
3
4#ifndef __LINUX_SPINLOCK_TYPES_H
5# error "please don't include this file directly"
6#endif
7
8typedef struct {
9 volatile unsigned int slock;
10} raw_spinlock_t;
11
12#define __RAW_SPIN_LOCK_UNLOCKED { 0 }
13
14typedef struct {
15 volatile signed int lock;
16} raw_rwlock_t;
17
18#define __RAW_RW_LOCK_UNLOCKED { 0 }
19
20#endif
diff --git a/include/asm-powerpc/spu.h b/include/asm-powerpc/spu.h
deleted file mode 100644
index 8b2eb044270..00000000000
--- a/include/asm-powerpc/spu.h
+++ /dev/null
@@ -1,732 +0,0 @@
1/*
2 * SPU core / file system interface and HW structures
3 *
4 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
5 *
6 * Author: Arnd Bergmann <arndb@de.ibm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef _SPU_H
24#define _SPU_H
25#ifdef __KERNEL__
26
27#include <linux/workqueue.h>
28#include <linux/sysdev.h>
29
30#define LS_SIZE (256 * 1024)
31#define LS_ADDR_MASK (LS_SIZE - 1)
32
33#define MFC_PUT_CMD 0x20
34#define MFC_PUTS_CMD 0x28
35#define MFC_PUTR_CMD 0x30
36#define MFC_PUTF_CMD 0x22
37#define MFC_PUTB_CMD 0x21
38#define MFC_PUTFS_CMD 0x2A
39#define MFC_PUTBS_CMD 0x29
40#define MFC_PUTRF_CMD 0x32
41#define MFC_PUTRB_CMD 0x31
42#define MFC_PUTL_CMD 0x24
43#define MFC_PUTRL_CMD 0x34
44#define MFC_PUTLF_CMD 0x26
45#define MFC_PUTLB_CMD 0x25
46#define MFC_PUTRLF_CMD 0x36
47#define MFC_PUTRLB_CMD 0x35
48
49#define MFC_GET_CMD 0x40
50#define MFC_GETS_CMD 0x48
51#define MFC_GETF_CMD 0x42
52#define MFC_GETB_CMD 0x41
53#define MFC_GETFS_CMD 0x4A
54#define MFC_GETBS_CMD 0x49
55#define MFC_GETL_CMD 0x44
56#define MFC_GETLF_CMD 0x46
57#define MFC_GETLB_CMD 0x45
58
59#define MFC_SDCRT_CMD 0x80
60#define MFC_SDCRTST_CMD 0x81
61#define MFC_SDCRZ_CMD 0x89
62#define MFC_SDCRS_CMD 0x8D
63#define MFC_SDCRF_CMD 0x8F
64
65#define MFC_GETLLAR_CMD 0xD0
66#define MFC_PUTLLC_CMD 0xB4
67#define MFC_PUTLLUC_CMD 0xB0
68#define MFC_PUTQLLUC_CMD 0xB8
69#define MFC_SNDSIG_CMD 0xA0
70#define MFC_SNDSIGB_CMD 0xA1
71#define MFC_SNDSIGF_CMD 0xA2
72#define MFC_BARRIER_CMD 0xC0
73#define MFC_EIEIO_CMD 0xC8
74#define MFC_SYNC_CMD 0xCC
75
76#define MFC_MIN_DMA_SIZE_SHIFT 4 /* 16 bytes */
77#define MFC_MAX_DMA_SIZE_SHIFT 14 /* 16384 bytes */
78#define MFC_MIN_DMA_SIZE (1 << MFC_MIN_DMA_SIZE_SHIFT)
79#define MFC_MAX_DMA_SIZE (1 << MFC_MAX_DMA_SIZE_SHIFT)
80#define MFC_MIN_DMA_SIZE_MASK (MFC_MIN_DMA_SIZE - 1)
81#define MFC_MAX_DMA_SIZE_MASK (MFC_MAX_DMA_SIZE - 1)
82#define MFC_MIN_DMA_LIST_SIZE 0x0008 /* 8 bytes */
83#define MFC_MAX_DMA_LIST_SIZE 0x4000 /* 16K bytes */
84
85#define MFC_TAGID_TO_TAGMASK(tag_id) (1 << (tag_id & 0x1F))
86
87/* Events for Channels 0-2 */
88#define MFC_DMA_TAG_STATUS_UPDATE_EVENT 0x00000001
89#define MFC_DMA_TAG_CMD_STALL_NOTIFY_EVENT 0x00000002
90#define MFC_DMA_QUEUE_AVAILABLE_EVENT 0x00000008
91#define MFC_SPU_MAILBOX_WRITTEN_EVENT 0x00000010
92#define MFC_DECREMENTER_EVENT 0x00000020
93#define MFC_PU_INT_MAILBOX_AVAILABLE_EVENT 0x00000040
94#define MFC_PU_MAILBOX_AVAILABLE_EVENT 0x00000080
95#define MFC_SIGNAL_2_EVENT 0x00000100
96#define MFC_SIGNAL_1_EVENT 0x00000200
97#define MFC_LLR_LOST_EVENT 0x00000400
98#define MFC_PRIV_ATTN_EVENT 0x00000800
99#define MFC_MULTI_SRC_EVENT 0x00001000
100
101/* Flag indicating progress during context switch. */
102#define SPU_CONTEXT_SWITCH_PENDING 0UL
103#define SPU_CONTEXT_FAULT_PENDING 1UL
104
105struct spu_context;
106struct spu_runqueue;
107struct spu_lscsa;
108struct device_node;
109
110enum spu_utilization_state {
111 SPU_UTIL_USER,
112 SPU_UTIL_SYSTEM,
113 SPU_UTIL_IOWAIT,
114 SPU_UTIL_IDLE_LOADED,
115 SPU_UTIL_MAX
116};
117
118struct spu {
119 const char *name;
120 unsigned long local_store_phys;
121 u8 *local_store;
122 unsigned long problem_phys;
123 struct spu_problem __iomem *problem;
124 struct spu_priv2 __iomem *priv2;
125 struct list_head cbe_list;
126 struct list_head full_list;
127 enum { SPU_FREE, SPU_USED } alloc_state;
128 int number;
129 unsigned int irqs[3];
130 u32 node;
131 u64 flags;
132 u64 class_0_pending;
133 u64 class_0_dar;
134 u64 class_1_dar;
135 u64 class_1_dsisr;
136 size_t ls_size;
137 unsigned int slb_replace;
138 struct mm_struct *mm;
139 struct spu_context *ctx;
140 struct spu_runqueue *rq;
141 unsigned long long timestamp;
142 pid_t pid;
143 pid_t tgid;
144 spinlock_t register_lock;
145
146 void (* wbox_callback)(struct spu *spu);
147 void (* ibox_callback)(struct spu *spu);
148 void (* stop_callback)(struct spu *spu, int irq);
149 void (* mfc_callback)(struct spu *spu);
150
151 char irq_c0[8];
152 char irq_c1[8];
153 char irq_c2[8];
154
155 u64 spe_id;
156
157 void* pdata; /* platform private data */
158
159 /* of based platforms only */
160 struct device_node *devnode;
161
162 /* native only */
163 struct spu_priv1 __iomem *priv1;
164
165 /* beat only */
166 u64 shadow_int_mask_RW[3];
167
168 struct sys_device sysdev;
169
170 int has_mem_affinity;
171 struct list_head aff_list;
172
173 struct {
174 /* protected by interrupt reentrancy */
175 enum spu_utilization_state util_state;
176 unsigned long long tstamp;
177 unsigned long long times[SPU_UTIL_MAX];
178 unsigned long long vol_ctx_switch;
179 unsigned long long invol_ctx_switch;
180 unsigned long long min_flt;
181 unsigned long long maj_flt;
182 unsigned long long hash_flt;
183 unsigned long long slb_flt;
184 unsigned long long class2_intr;
185 unsigned long long libassist;
186 } stats;
187};
188
189struct cbe_spu_info {
190 struct mutex list_mutex;
191 struct list_head spus;
192 int n_spus;
193 int nr_active;
194 atomic_t busy_spus;
195 atomic_t reserved_spus;
196};
197
198extern struct cbe_spu_info cbe_spu_info[];
199
200void spu_init_channels(struct spu *spu);
201void spu_irq_setaffinity(struct spu *spu, int cpu);
202
203void spu_setup_kernel_slbs(struct spu *spu, struct spu_lscsa *lscsa,
204 void *code, int code_size);
205
206#ifdef CONFIG_KEXEC
207void crash_register_spus(struct list_head *list);
208#else
209static inline void crash_register_spus(struct list_head *list)
210{
211}
212#endif
213
214extern void spu_invalidate_slbs(struct spu *spu);
215extern void spu_associate_mm(struct spu *spu, struct mm_struct *mm);
216int spu_64k_pages_available(void);
217
218/* Calls from the memory management to the SPU */
219struct mm_struct;
220extern void spu_flush_all_slbs(struct mm_struct *mm);
221
222/* This interface allows a profiler (e.g., OProfile) to store a ref
223 * to spu context information that it creates. This caching technique
224 * avoids the need to recreate this information after a save/restore operation.
225 *
226 * Assumes the caller has already incremented the ref count to
227 * profile_info; then spu_context_destroy must call kref_put
228 * on prof_info_kref.
229 */
230void spu_set_profile_private_kref(struct spu_context *ctx,
231 struct kref *prof_info_kref,
232 void ( * prof_info_release) (struct kref *kref));
233
234void *spu_get_profile_private_kref(struct spu_context *ctx);
235
236/* system callbacks from the SPU */
237struct spu_syscall_block {
238 u64 nr_ret;
239 u64 parm[6];
240};
241extern long spu_sys_callback(struct spu_syscall_block *s);
242
243/* syscalls implemented in spufs */
244struct file;
245struct spufs_calls {
246 long (*create_thread)(const char __user *name,
247 unsigned int flags, mode_t mode,
248 struct file *neighbor);
249 long (*spu_run)(struct file *filp, __u32 __user *unpc,
250 __u32 __user *ustatus);
251 int (*coredump_extra_notes_size)(void);
252 int (*coredump_extra_notes_write)(struct file *file, loff_t *foffset);
253 void (*notify_spus_active)(void);
254 struct module *owner;
255};
256
257/* return status from spu_run, same as in libspe */
258#define SPE_EVENT_DMA_ALIGNMENT 0x0008 /*A DMA alignment error */
259#define SPE_EVENT_SPE_ERROR 0x0010 /*An illegal instruction error*/
260#define SPE_EVENT_SPE_DATA_SEGMENT 0x0020 /*A DMA segmentation error */
261#define SPE_EVENT_SPE_DATA_STORAGE 0x0040 /*A DMA storage error */
262#define SPE_EVENT_INVALID_DMA 0x0800 /* Invalid MFC DMA */
263
264/*
265 * Flags for sys_spu_create.
266 */
267#define SPU_CREATE_EVENTS_ENABLED 0x0001
268#define SPU_CREATE_GANG 0x0002
269#define SPU_CREATE_NOSCHED 0x0004
270#define SPU_CREATE_ISOLATE 0x0008
271#define SPU_CREATE_AFFINITY_SPU 0x0010
272#define SPU_CREATE_AFFINITY_MEM 0x0020
273
274#define SPU_CREATE_FLAG_ALL 0x003f /* mask of all valid flags */
275
276
277int register_spu_syscalls(struct spufs_calls *calls);
278void unregister_spu_syscalls(struct spufs_calls *calls);
279
280int spu_add_sysdev_attr(struct sysdev_attribute *attr);
281void spu_remove_sysdev_attr(struct sysdev_attribute *attr);
282
283int spu_add_sysdev_attr_group(struct attribute_group *attrs);
284void spu_remove_sysdev_attr_group(struct attribute_group *attrs);
285
286int spu_handle_mm_fault(struct mm_struct *mm, unsigned long ea,
287 unsigned long dsisr, unsigned *flt);
288
289/*
290 * Notifier blocks:
291 *
292 * oprofile can get notified when a context switch is performed
293 * on an spe. The notifer function that gets called is passed
294 * a pointer to the SPU structure as well as the object-id that
295 * identifies the binary running on that SPU now.
296 *
297 * For a context save, the object-id that is passed is zero,
298 * identifying that the kernel will run from that moment on.
299 *
300 * For a context restore, the object-id is the value written
301 * to object-id spufs file from user space and the notifer
302 * function can assume that spu->ctx is valid.
303 */
304struct notifier_block;
305int spu_switch_event_register(struct notifier_block * n);
306int spu_switch_event_unregister(struct notifier_block * n);
307
308extern void notify_spus_active(void);
309extern void do_notify_spus_active(void);
310
311/*
312 * This defines the Local Store, Problem Area and Privilege Area of an SPU.
313 */
314
315union mfc_tag_size_class_cmd {
316 struct {
317 u16 mfc_size;
318 u16 mfc_tag;
319 u8 pad;
320 u8 mfc_rclassid;
321 u16 mfc_cmd;
322 } u;
323 struct {
324 u32 mfc_size_tag32;
325 u32 mfc_class_cmd32;
326 } by32;
327 u64 all64;
328};
329
330struct mfc_cq_sr {
331 u64 mfc_cq_data0_RW;
332 u64 mfc_cq_data1_RW;
333 u64 mfc_cq_data2_RW;
334 u64 mfc_cq_data3_RW;
335};
336
337struct spu_problem {
338#define MS_SYNC_PENDING 1L
339 u64 spc_mssync_RW; /* 0x0000 */
340 u8 pad_0x0008_0x3000[0x3000 - 0x0008];
341
342 /* DMA Area */
343 u8 pad_0x3000_0x3004[0x4]; /* 0x3000 */
344 u32 mfc_lsa_W; /* 0x3004 */
345 u64 mfc_ea_W; /* 0x3008 */
346 union mfc_tag_size_class_cmd mfc_union_W; /* 0x3010 */
347 u8 pad_0x3018_0x3104[0xec]; /* 0x3018 */
348 u32 dma_qstatus_R; /* 0x3104 */
349 u8 pad_0x3108_0x3204[0xfc]; /* 0x3108 */
350 u32 dma_querytype_RW; /* 0x3204 */
351 u8 pad_0x3208_0x321c[0x14]; /* 0x3208 */
352 u32 dma_querymask_RW; /* 0x321c */
353 u8 pad_0x3220_0x322c[0xc]; /* 0x3220 */
354 u32 dma_tagstatus_R; /* 0x322c */
355#define DMA_TAGSTATUS_INTR_ANY 1u
356#define DMA_TAGSTATUS_INTR_ALL 2u
357 u8 pad_0x3230_0x4000[0x4000 - 0x3230]; /* 0x3230 */
358
359 /* SPU Control Area */
360 u8 pad_0x4000_0x4004[0x4]; /* 0x4000 */
361 u32 pu_mb_R; /* 0x4004 */
362 u8 pad_0x4008_0x400c[0x4]; /* 0x4008 */
363 u32 spu_mb_W; /* 0x400c */
364 u8 pad_0x4010_0x4014[0x4]; /* 0x4010 */
365 u32 mb_stat_R; /* 0x4014 */
366 u8 pad_0x4018_0x401c[0x4]; /* 0x4018 */
367 u32 spu_runcntl_RW; /* 0x401c */
368#define SPU_RUNCNTL_STOP 0L
369#define SPU_RUNCNTL_RUNNABLE 1L
370#define SPU_RUNCNTL_ISOLATE 2L
371 u8 pad_0x4020_0x4024[0x4]; /* 0x4020 */
372 u32 spu_status_R; /* 0x4024 */
373#define SPU_STOP_STATUS_SHIFT 16
374#define SPU_STATUS_STOPPED 0x0
375#define SPU_STATUS_RUNNING 0x1
376#define SPU_STATUS_STOPPED_BY_STOP 0x2
377#define SPU_STATUS_STOPPED_BY_HALT 0x4
378#define SPU_STATUS_WAITING_FOR_CHANNEL 0x8
379#define SPU_STATUS_SINGLE_STEP 0x10
380#define SPU_STATUS_INVALID_INSTR 0x20
381#define SPU_STATUS_INVALID_CH 0x40
382#define SPU_STATUS_ISOLATED_STATE 0x80
383#define SPU_STATUS_ISOLATED_LOAD_STATUS 0x200
384#define SPU_STATUS_ISOLATED_EXIT_STATUS 0x400
385 u8 pad_0x4028_0x402c[0x4]; /* 0x4028 */
386 u32 spu_spe_R; /* 0x402c */
387 u8 pad_0x4030_0x4034[0x4]; /* 0x4030 */
388 u32 spu_npc_RW; /* 0x4034 */
389 u8 pad_0x4038_0x14000[0x14000 - 0x4038]; /* 0x4038 */
390
391 /* Signal Notification Area */
392 u8 pad_0x14000_0x1400c[0xc]; /* 0x14000 */
393 u32 signal_notify1; /* 0x1400c */
394 u8 pad_0x14010_0x1c00c[0x7ffc]; /* 0x14010 */
395 u32 signal_notify2; /* 0x1c00c */
396} __attribute__ ((aligned(0x20000)));
397
398/* SPU Privilege 2 State Area */
399struct spu_priv2 {
400 /* MFC Registers */
401 u8 pad_0x0000_0x1100[0x1100 - 0x0000]; /* 0x0000 */
402
403 /* SLB Management Registers */
404 u8 pad_0x1100_0x1108[0x8]; /* 0x1100 */
405 u64 slb_index_W; /* 0x1108 */
406#define SLB_INDEX_MASK 0x7L
407 u64 slb_esid_RW; /* 0x1110 */
408 u64 slb_vsid_RW; /* 0x1118 */
409#define SLB_VSID_SUPERVISOR_STATE (0x1ull << 11)
410#define SLB_VSID_SUPERVISOR_STATE_MASK (0x1ull << 11)
411#define SLB_VSID_PROBLEM_STATE (0x1ull << 10)
412#define SLB_VSID_PROBLEM_STATE_MASK (0x1ull << 10)
413#define SLB_VSID_EXECUTE_SEGMENT (0x1ull << 9)
414#define SLB_VSID_NO_EXECUTE_SEGMENT (0x1ull << 9)
415#define SLB_VSID_EXECUTE_SEGMENT_MASK (0x1ull << 9)
416#define SLB_VSID_4K_PAGE (0x0 << 8)
417#define SLB_VSID_LARGE_PAGE (0x1ull << 8)
418#define SLB_VSID_PAGE_SIZE_MASK (0x1ull << 8)
419#define SLB_VSID_CLASS_MASK (0x1ull << 7)
420#define SLB_VSID_VIRTUAL_PAGE_SIZE_MASK (0x1ull << 6)
421 u64 slb_invalidate_entry_W; /* 0x1120 */
422 u64 slb_invalidate_all_W; /* 0x1128 */
423 u8 pad_0x1130_0x2000[0x2000 - 0x1130]; /* 0x1130 */
424
425 /* Context Save / Restore Area */
426 struct mfc_cq_sr spuq[16]; /* 0x2000 */
427 struct mfc_cq_sr puq[8]; /* 0x2200 */
428 u8 pad_0x2300_0x3000[0x3000 - 0x2300]; /* 0x2300 */
429
430 /* MFC Control */
431 u64 mfc_control_RW; /* 0x3000 */
432#define MFC_CNTL_RESUME_DMA_QUEUE (0ull << 0)
433#define MFC_CNTL_SUSPEND_DMA_QUEUE (1ull << 0)
434#define MFC_CNTL_SUSPEND_DMA_QUEUE_MASK (1ull << 0)
435#define MFC_CNTL_SUSPEND_MASK (1ull << 4)
436#define MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION (0ull << 8)
437#define MFC_CNTL_SUSPEND_IN_PROGRESS (1ull << 8)
438#define MFC_CNTL_SUSPEND_COMPLETE (3ull << 8)
439#define MFC_CNTL_SUSPEND_DMA_STATUS_MASK (3ull << 8)
440#define MFC_CNTL_DMA_QUEUES_EMPTY (1ull << 14)
441#define MFC_CNTL_DMA_QUEUES_EMPTY_MASK (1ull << 14)
442#define MFC_CNTL_PURGE_DMA_REQUEST (1ull << 15)
443#define MFC_CNTL_PURGE_DMA_IN_PROGRESS (1ull << 24)
444#define MFC_CNTL_PURGE_DMA_COMPLETE (3ull << 24)
445#define MFC_CNTL_PURGE_DMA_STATUS_MASK (3ull << 24)
446#define MFC_CNTL_RESTART_DMA_COMMAND (1ull << 32)
447#define MFC_CNTL_DMA_COMMAND_REISSUE_PENDING (1ull << 32)
448#define MFC_CNTL_DMA_COMMAND_REISSUE_STATUS_MASK (1ull << 32)
449#define MFC_CNTL_MFC_PRIVILEGE_STATE (2ull << 33)
450#define MFC_CNTL_MFC_PROBLEM_STATE (3ull << 33)
451#define MFC_CNTL_MFC_KEY_PROTECTION_STATE_MASK (3ull << 33)
452#define MFC_CNTL_DECREMENTER_HALTED (1ull << 35)
453#define MFC_CNTL_DECREMENTER_RUNNING (1ull << 40)
454#define MFC_CNTL_DECREMENTER_STATUS_MASK (1ull << 40)
455 u8 pad_0x3008_0x4000[0x4000 - 0x3008]; /* 0x3008 */
456
457 /* Interrupt Mailbox */
458 u64 puint_mb_R; /* 0x4000 */
459 u8 pad_0x4008_0x4040[0x4040 - 0x4008]; /* 0x4008 */
460
461 /* SPU Control */
462 u64 spu_privcntl_RW; /* 0x4040 */
463#define SPU_PRIVCNTL_MODE_NORMAL (0x0ull << 0)
464#define SPU_PRIVCNTL_MODE_SINGLE_STEP (0x1ull << 0)
465#define SPU_PRIVCNTL_MODE_MASK (0x1ull << 0)
466#define SPU_PRIVCNTL_NO_ATTENTION_EVENT (0x0ull << 1)
467#define SPU_PRIVCNTL_ATTENTION_EVENT (0x1ull << 1)
468#define SPU_PRIVCNTL_ATTENTION_EVENT_MASK (0x1ull << 1)
469#define SPU_PRIVCNT_LOAD_REQUEST_NORMAL (0x0ull << 2)
470#define SPU_PRIVCNT_LOAD_REQUEST_ENABLE_MASK (0x1ull << 2)
471 u8 pad_0x4048_0x4058[0x10]; /* 0x4048 */
472 u64 spu_lslr_RW; /* 0x4058 */
473 u64 spu_chnlcntptr_RW; /* 0x4060 */
474 u64 spu_chnlcnt_RW; /* 0x4068 */
475 u64 spu_chnldata_RW; /* 0x4070 */
476 u64 spu_cfg_RW; /* 0x4078 */
477 u8 pad_0x4080_0x5000[0x5000 - 0x4080]; /* 0x4080 */
478
479 /* PV2_ImplRegs: Implementation-specific privileged-state 2 regs */
480 u64 spu_pm_trace_tag_status_RW; /* 0x5000 */
481 u64 spu_tag_status_query_RW; /* 0x5008 */
482#define TAG_STATUS_QUERY_CONDITION_BITS (0x3ull << 32)
483#define TAG_STATUS_QUERY_MASK_BITS (0xffffffffull)
484 u64 spu_cmd_buf1_RW; /* 0x5010 */
485#define SPU_COMMAND_BUFFER_1_LSA_BITS (0x7ffffull << 32)
486#define SPU_COMMAND_BUFFER_1_EAH_BITS (0xffffffffull)
487 u64 spu_cmd_buf2_RW; /* 0x5018 */
488#define SPU_COMMAND_BUFFER_2_EAL_BITS ((0xffffffffull) << 32)
489#define SPU_COMMAND_BUFFER_2_TS_BITS (0xffffull << 16)
490#define SPU_COMMAND_BUFFER_2_TAG_BITS (0x3full)
491 u64 spu_atomic_status_RW; /* 0x5020 */
492} __attribute__ ((aligned(0x20000)));
493
494/* SPU Privilege 1 State Area */
495struct spu_priv1 {
496 /* Control and Configuration Area */
497 u64 mfc_sr1_RW; /* 0x000 */
498#define MFC_STATE1_LOCAL_STORAGE_DECODE_MASK 0x01ull
499#define MFC_STATE1_BUS_TLBIE_MASK 0x02ull
500#define MFC_STATE1_REAL_MODE_OFFSET_ENABLE_MASK 0x04ull
501#define MFC_STATE1_PROBLEM_STATE_MASK 0x08ull
502#define MFC_STATE1_RELOCATE_MASK 0x10ull
503#define MFC_STATE1_MASTER_RUN_CONTROL_MASK 0x20ull
504#define MFC_STATE1_TABLE_SEARCH_MASK 0x40ull
505 u64 mfc_lpid_RW; /* 0x008 */
506 u64 spu_idr_RW; /* 0x010 */
507 u64 mfc_vr_RO; /* 0x018 */
508#define MFC_VERSION_BITS (0xffff << 16)
509#define MFC_REVISION_BITS (0xffff)
510#define MFC_GET_VERSION_BITS(vr) (((vr) & MFC_VERSION_BITS) >> 16)
511#define MFC_GET_REVISION_BITS(vr) ((vr) & MFC_REVISION_BITS)
512 u64 spu_vr_RO; /* 0x020 */
513#define SPU_VERSION_BITS (0xffff << 16)
514#define SPU_REVISION_BITS (0xffff)
515#define SPU_GET_VERSION_BITS(vr) (vr & SPU_VERSION_BITS) >> 16
516#define SPU_GET_REVISION_BITS(vr) (vr & SPU_REVISION_BITS)
517 u8 pad_0x28_0x100[0x100 - 0x28]; /* 0x28 */
518
519 /* Interrupt Area */
520 u64 int_mask_RW[3]; /* 0x100 */
521#define CLASS0_ENABLE_DMA_ALIGNMENT_INTR 0x1L
522#define CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR 0x2L
523#define CLASS0_ENABLE_SPU_ERROR_INTR 0x4L
524#define CLASS0_ENABLE_MFC_FIR_INTR 0x8L
525#define CLASS1_ENABLE_SEGMENT_FAULT_INTR 0x1L
526#define CLASS1_ENABLE_STORAGE_FAULT_INTR 0x2L
527#define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_GET_INTR 0x4L
528#define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_PUT_INTR 0x8L
529#define CLASS2_ENABLE_MAILBOX_INTR 0x1L
530#define CLASS2_ENABLE_SPU_STOP_INTR 0x2L
531#define CLASS2_ENABLE_SPU_HALT_INTR 0x4L
532#define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L
533#define CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR 0x10L
534 u8 pad_0x118_0x140[0x28]; /* 0x118 */
535 u64 int_stat_RW[3]; /* 0x140 */
536#define CLASS0_DMA_ALIGNMENT_INTR 0x1L
537#define CLASS0_INVALID_DMA_COMMAND_INTR 0x2L
538#define CLASS0_SPU_ERROR_INTR 0x4L
539#define CLASS0_INTR_MASK 0x7L
540#define CLASS1_SEGMENT_FAULT_INTR 0x1L
541#define CLASS1_STORAGE_FAULT_INTR 0x2L
542#define CLASS1_LS_COMPARE_SUSPEND_ON_GET_INTR 0x4L
543#define CLASS1_LS_COMPARE_SUSPEND_ON_PUT_INTR 0x8L
544#define CLASS1_INTR_MASK 0xfL
545#define CLASS2_MAILBOX_INTR 0x1L
546#define CLASS2_SPU_STOP_INTR 0x2L
547#define CLASS2_SPU_HALT_INTR 0x4L
548#define CLASS2_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L
549#define CLASS2_MAILBOX_THRESHOLD_INTR 0x10L
550#define CLASS2_INTR_MASK 0x1fL
551 u8 pad_0x158_0x180[0x28]; /* 0x158 */
552 u64 int_route_RW; /* 0x180 */
553
554 /* Interrupt Routing */
555 u8 pad_0x188_0x200[0x200 - 0x188]; /* 0x188 */
556
557 /* Atomic Unit Control Area */
558 u64 mfc_atomic_flush_RW; /* 0x200 */
559#define mfc_atomic_flush_enable 0x1L
560 u8 pad_0x208_0x280[0x78]; /* 0x208 */
561 u64 resource_allocation_groupID_RW; /* 0x280 */
562 u64 resource_allocation_enable_RW; /* 0x288 */
563 u8 pad_0x290_0x3c8[0x3c8 - 0x290]; /* 0x290 */
564
565 /* SPU_Cache_ImplRegs: Implementation-dependent cache registers */
566
567 u64 smf_sbi_signal_sel; /* 0x3c8 */
568#define smf_sbi_mask_lsb 56
569#define smf_sbi_shift (63 - smf_sbi_mask_lsb)
570#define smf_sbi_mask (0x301LL << smf_sbi_shift)
571#define smf_sbi_bus0_bits (0x001LL << smf_sbi_shift)
572#define smf_sbi_bus2_bits (0x100LL << smf_sbi_shift)
573#define smf_sbi2_bus0_bits (0x201LL << smf_sbi_shift)
574#define smf_sbi2_bus2_bits (0x300LL << smf_sbi_shift)
575 u64 smf_ato_signal_sel; /* 0x3d0 */
576#define smf_ato_mask_lsb 35
577#define smf_ato_shift (63 - smf_ato_mask_lsb)
578#define smf_ato_mask (0x3LL << smf_ato_shift)
579#define smf_ato_bus0_bits (0x2LL << smf_ato_shift)
580#define smf_ato_bus2_bits (0x1LL << smf_ato_shift)
581 u8 pad_0x3d8_0x400[0x400 - 0x3d8]; /* 0x3d8 */
582
583 /* TLB Management Registers */
584 u64 mfc_sdr_RW; /* 0x400 */
585 u8 pad_0x408_0x500[0xf8]; /* 0x408 */
586 u64 tlb_index_hint_RO; /* 0x500 */
587 u64 tlb_index_W; /* 0x508 */
588 u64 tlb_vpn_RW; /* 0x510 */
589 u64 tlb_rpn_RW; /* 0x518 */
590 u8 pad_0x520_0x540[0x20]; /* 0x520 */
591 u64 tlb_invalidate_entry_W; /* 0x540 */
592 u64 tlb_invalidate_all_W; /* 0x548 */
593 u8 pad_0x550_0x580[0x580 - 0x550]; /* 0x550 */
594
595 /* SPU_MMU_ImplRegs: Implementation-dependent MMU registers */
596 u64 smm_hid; /* 0x580 */
597#define PAGE_SIZE_MASK 0xf000000000000000ull
598#define PAGE_SIZE_16MB_64KB 0x2000000000000000ull
599 u8 pad_0x588_0x600[0x600 - 0x588]; /* 0x588 */
600
601 /* MFC Status/Control Area */
602 u64 mfc_accr_RW; /* 0x600 */
603#define MFC_ACCR_EA_ACCESS_GET (1 << 0)
604#define MFC_ACCR_EA_ACCESS_PUT (1 << 1)
605#define MFC_ACCR_LS_ACCESS_GET (1 << 3)
606#define MFC_ACCR_LS_ACCESS_PUT (1 << 4)
607 u8 pad_0x608_0x610[0x8]; /* 0x608 */
608 u64 mfc_dsisr_RW; /* 0x610 */
609#define MFC_DSISR_PTE_NOT_FOUND (1 << 30)
610#define MFC_DSISR_ACCESS_DENIED (1 << 27)
611#define MFC_DSISR_ATOMIC (1 << 26)
612#define MFC_DSISR_ACCESS_PUT (1 << 25)
613#define MFC_DSISR_ADDR_MATCH (1 << 22)
614#define MFC_DSISR_LS (1 << 17)
615#define MFC_DSISR_L (1 << 16)
616#define MFC_DSISR_ADDRESS_OVERFLOW (1 << 0)
617 u8 pad_0x618_0x620[0x8]; /* 0x618 */
618 u64 mfc_dar_RW; /* 0x620 */
619 u8 pad_0x628_0x700[0x700 - 0x628]; /* 0x628 */
620
621 /* Replacement Management Table (RMT) Area */
622 u64 rmt_index_RW; /* 0x700 */
623 u8 pad_0x708_0x710[0x8]; /* 0x708 */
624 u64 rmt_data1_RW; /* 0x710 */
625 u8 pad_0x718_0x800[0x800 - 0x718]; /* 0x718 */
626
627 /* Control/Configuration Registers */
628 u64 mfc_dsir_R; /* 0x800 */
629#define MFC_DSIR_Q (1 << 31)
630#define MFC_DSIR_SPU_QUEUE MFC_DSIR_Q
631 u64 mfc_lsacr_RW; /* 0x808 */
632#define MFC_LSACR_COMPARE_MASK ((~0ull) << 32)
633#define MFC_LSACR_COMPARE_ADDR ((~0ull) >> 32)
634 u64 mfc_lscrr_R; /* 0x810 */
635#define MFC_LSCRR_Q (1 << 31)
636#define MFC_LSCRR_SPU_QUEUE MFC_LSCRR_Q
637#define MFC_LSCRR_QI_SHIFT 32
638#define MFC_LSCRR_QI_MASK ((~0ull) << MFC_LSCRR_QI_SHIFT)
639 u8 pad_0x818_0x820[0x8]; /* 0x818 */
640 u64 mfc_tclass_id_RW; /* 0x820 */
641#define MFC_TCLASS_ID_ENABLE (1L << 0L)
642#define MFC_TCLASS_SLOT2_ENABLE (1L << 5L)
643#define MFC_TCLASS_SLOT1_ENABLE (1L << 6L)
644#define MFC_TCLASS_SLOT0_ENABLE (1L << 7L)
645#define MFC_TCLASS_QUOTA_2_SHIFT 8L
646#define MFC_TCLASS_QUOTA_1_SHIFT 16L
647#define MFC_TCLASS_QUOTA_0_SHIFT 24L
648#define MFC_TCLASS_QUOTA_2_MASK (0x1FL << MFC_TCLASS_QUOTA_2_SHIFT)
649#define MFC_TCLASS_QUOTA_1_MASK (0x1FL << MFC_TCLASS_QUOTA_1_SHIFT)
650#define MFC_TCLASS_QUOTA_0_MASK (0x1FL << MFC_TCLASS_QUOTA_0_SHIFT)
651 u8 pad_0x828_0x900[0x900 - 0x828]; /* 0x828 */
652
653 /* Real Mode Support Registers */
654 u64 mfc_rm_boundary; /* 0x900 */
655 u8 pad_0x908_0x938[0x30]; /* 0x908 */
656 u64 smf_dma_signal_sel; /* 0x938 */
657#define mfc_dma1_mask_lsb 41
658#define mfc_dma1_shift (63 - mfc_dma1_mask_lsb)
659#define mfc_dma1_mask (0x3LL << mfc_dma1_shift)
660#define mfc_dma1_bits (0x1LL << mfc_dma1_shift)
661#define mfc_dma2_mask_lsb 43
662#define mfc_dma2_shift (63 - mfc_dma2_mask_lsb)
663#define mfc_dma2_mask (0x3LL << mfc_dma2_shift)
664#define mfc_dma2_bits (0x1LL << mfc_dma2_shift)
665 u8 pad_0x940_0xa38[0xf8]; /* 0x940 */
666 u64 smm_signal_sel; /* 0xa38 */
667#define smm_sig_mask_lsb 12
668#define smm_sig_shift (63 - smm_sig_mask_lsb)
669#define smm_sig_mask (0x3LL << smm_sig_shift)
670#define smm_sig_bus0_bits (0x2LL << smm_sig_shift)
671#define smm_sig_bus2_bits (0x1LL << smm_sig_shift)
672 u8 pad_0xa40_0xc00[0xc00 - 0xa40]; /* 0xa40 */
673
674 /* DMA Command Error Area */
675 u64 mfc_cer_R; /* 0xc00 */
676#define MFC_CER_Q (1 << 31)
677#define MFC_CER_SPU_QUEUE MFC_CER_Q
678 u8 pad_0xc08_0x1000[0x1000 - 0xc08]; /* 0xc08 */
679
680 /* PV1_ImplRegs: Implementation-dependent privileged-state 1 regs */
681 /* DMA Command Error Area */
682 u64 spu_ecc_cntl_RW; /* 0x1000 */
683#define SPU_ECC_CNTL_E (1ull << 0ull)
684#define SPU_ECC_CNTL_ENABLE SPU_ECC_CNTL_E
685#define SPU_ECC_CNTL_DISABLE (~SPU_ECC_CNTL_E & 1L)
686#define SPU_ECC_CNTL_S (1ull << 1ull)
687#define SPU_ECC_STOP_AFTER_ERROR SPU_ECC_CNTL_S
688#define SPU_ECC_CONTINUE_AFTER_ERROR (~SPU_ECC_CNTL_S & 2L)
689#define SPU_ECC_CNTL_B (1ull << 2ull)
690#define SPU_ECC_BACKGROUND_ENABLE SPU_ECC_CNTL_B
691#define SPU_ECC_BACKGROUND_DISABLE (~SPU_ECC_CNTL_B & 4L)
692#define SPU_ECC_CNTL_I_SHIFT 3ull
693#define SPU_ECC_CNTL_I_MASK (3ull << SPU_ECC_CNTL_I_SHIFT)
694#define SPU_ECC_WRITE_ALWAYS (~SPU_ECC_CNTL_I & 12L)
695#define SPU_ECC_WRITE_CORRECTABLE (1ull << SPU_ECC_CNTL_I_SHIFT)
696#define SPU_ECC_WRITE_UNCORRECTABLE (3ull << SPU_ECC_CNTL_I_SHIFT)
697#define SPU_ECC_CNTL_D (1ull << 5ull)
698#define SPU_ECC_DETECTION_ENABLE SPU_ECC_CNTL_D
699#define SPU_ECC_DETECTION_DISABLE (~SPU_ECC_CNTL_D & 32L)
700 u64 spu_ecc_stat_RW; /* 0x1008 */
701#define SPU_ECC_CORRECTED_ERROR (1ull << 0ul)
702#define SPU_ECC_UNCORRECTED_ERROR (1ull << 1ul)
703#define SPU_ECC_SCRUB_COMPLETE (1ull << 2ul)
704#define SPU_ECC_SCRUB_IN_PROGRESS (1ull << 3ul)
705#define SPU_ECC_INSTRUCTION_ERROR (1ull << 4ul)
706#define SPU_ECC_DATA_ERROR (1ull << 5ul)
707#define SPU_ECC_DMA_ERROR (1ull << 6ul)
708#define SPU_ECC_STATUS_CNT_MASK (256ull << 8)
709 u64 spu_ecc_addr_RW; /* 0x1010 */
710 u64 spu_err_mask_RW; /* 0x1018 */
711#define SPU_ERR_ILLEGAL_INSTR (1ull << 0ul)
712#define SPU_ERR_ILLEGAL_CHANNEL (1ull << 1ul)
713 u8 pad_0x1020_0x1028[0x1028 - 0x1020]; /* 0x1020 */
714
715 /* SPU Debug-Trace Bus (DTB) Selection Registers */
716 u64 spu_trig0_sel; /* 0x1028 */
717 u64 spu_trig1_sel; /* 0x1030 */
718 u64 spu_trig2_sel; /* 0x1038 */
719 u64 spu_trig3_sel; /* 0x1040 */
720 u64 spu_trace_sel; /* 0x1048 */
721#define spu_trace_sel_mask 0x1f1fLL
722#define spu_trace_sel_bus0_bits 0x1000LL
723#define spu_trace_sel_bus2_bits 0x0010LL
724 u64 spu_event0_sel; /* 0x1050 */
725 u64 spu_event1_sel; /* 0x1058 */
726 u64 spu_event2_sel; /* 0x1060 */
727 u64 spu_event3_sel; /* 0x1068 */
728 u64 spu_trace_cntl; /* 0x1070 */
729} __attribute__ ((aligned(0x2000)));
730
731#endif /* __KERNEL__ */
732#endif
diff --git a/include/asm-powerpc/spu_csa.h b/include/asm-powerpc/spu_csa.h
deleted file mode 100644
index a40fd491250..00000000000
--- a/include/asm-powerpc/spu_csa.h
+++ /dev/null
@@ -1,266 +0,0 @@
1/*
2 * spu_csa.h: Definitions for SPU context save area (CSA).
3 *
4 * (C) Copyright IBM 2005
5 *
6 * Author: Mark Nutter <mnutter@us.ibm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef _SPU_CSA_H_
24#define _SPU_CSA_H_
25#ifdef __KERNEL__
26
27/*
28 * Total number of 128-bit registers.
29 */
30#define NR_SPU_GPRS 128
31#define NR_SPU_SPRS 9
32#define NR_SPU_REGS_PAD 7
33#define NR_SPU_SPILL_REGS 144 /* GPRS + SPRS + PAD */
34#define SIZEOF_SPU_SPILL_REGS NR_SPU_SPILL_REGS * 16
35
36#define SPU_SAVE_COMPLETE 0x3FFB
37#define SPU_RESTORE_COMPLETE 0x3FFC
38
39/*
40 * Definitions for various 'stopped' status conditions,
41 * to be recreated during context restore.
42 */
43#define SPU_STOPPED_STATUS_P 1
44#define SPU_STOPPED_STATUS_I 2
45#define SPU_STOPPED_STATUS_H 3
46#define SPU_STOPPED_STATUS_S 4
47#define SPU_STOPPED_STATUS_S_I 5
48#define SPU_STOPPED_STATUS_S_P 6
49#define SPU_STOPPED_STATUS_P_H 7
50#define SPU_STOPPED_STATUS_P_I 8
51#define SPU_STOPPED_STATUS_R 9
52
53/*
54 * Definitions for software decrementer status flag.
55 */
56#define SPU_DECR_STATUS_RUNNING 0x1
57#define SPU_DECR_STATUS_WRAPPED 0x2
58
59#ifndef __ASSEMBLY__
60/**
61 * spu_reg128 - generic 128-bit register definition.
62 */
63struct spu_reg128 {
64 u32 slot[4];
65};
66
67/**
68 * struct spu_lscsa - Local Store Context Save Area.
69 * @gprs: Array of saved registers.
70 * @fpcr: Saved floating point status control register.
71 * @decr: Saved decrementer value.
72 * @decr_status: Indicates software decrementer status flags.
73 * @ppu_mb: Saved PPU mailbox data.
74 * @ppuint_mb: Saved PPU interrupting mailbox data.
75 * @tag_mask: Saved tag group mask.
76 * @event_mask: Saved event mask.
77 * @srr0: Saved SRR0.
78 * @stopped_status: Conditions to be recreated by restore.
79 * @ls: Saved contents of Local Storage Area.
80 *
81 * The LSCSA represents state that is primarily saved and
82 * restored by SPU-side code.
83 */
84struct spu_lscsa {
85 struct spu_reg128 gprs[128];
86 struct spu_reg128 fpcr;
87 struct spu_reg128 decr;
88 struct spu_reg128 decr_status;
89 struct spu_reg128 ppu_mb;
90 struct spu_reg128 ppuint_mb;
91 struct spu_reg128 tag_mask;
92 struct spu_reg128 event_mask;
93 struct spu_reg128 srr0;
94 struct spu_reg128 stopped_status;
95
96 /*
97 * 'ls' must be page-aligned on all configurations.
98 * Since we don't want to rely on having the spu-gcc
99 * installed to build the kernel and this structure
100 * is used in the SPU-side code, make it 64k-page
101 * aligned for now.
102 */
103 unsigned char ls[LS_SIZE] __attribute__((aligned(65536)));
104};
105
106#ifndef __SPU__
107/*
108 * struct spu_problem_collapsed - condensed problem state area, w/o pads.
109 */
110struct spu_problem_collapsed {
111 u64 spc_mssync_RW;
112 u32 mfc_lsa_W;
113 u32 unused_pad0;
114 u64 mfc_ea_W;
115 union mfc_tag_size_class_cmd mfc_union_W;
116 u32 dma_qstatus_R;
117 u32 dma_querytype_RW;
118 u32 dma_querymask_RW;
119 u32 dma_tagstatus_R;
120 u32 pu_mb_R;
121 u32 spu_mb_W;
122 u32 mb_stat_R;
123 u32 spu_runcntl_RW;
124 u32 spu_status_R;
125 u32 spu_spc_R;
126 u32 spu_npc_RW;
127 u32 signal_notify1;
128 u32 signal_notify2;
129 u32 unused_pad1;
130};
131
132/*
133 * struct spu_priv1_collapsed - condensed privileged 1 area, w/o pads.
134 */
135struct spu_priv1_collapsed {
136 u64 mfc_sr1_RW;
137 u64 mfc_lpid_RW;
138 u64 spu_idr_RW;
139 u64 mfc_vr_RO;
140 u64 spu_vr_RO;
141 u64 int_mask_class0_RW;
142 u64 int_mask_class1_RW;
143 u64 int_mask_class2_RW;
144 u64 int_stat_class0_RW;
145 u64 int_stat_class1_RW;
146 u64 int_stat_class2_RW;
147 u64 int_route_RW;
148 u64 mfc_atomic_flush_RW;
149 u64 resource_allocation_groupID_RW;
150 u64 resource_allocation_enable_RW;
151 u64 mfc_fir_R;
152 u64 mfc_fir_status_or_W;
153 u64 mfc_fir_status_and_W;
154 u64 mfc_fir_mask_R;
155 u64 mfc_fir_mask_or_W;
156 u64 mfc_fir_mask_and_W;
157 u64 mfc_fir_chkstp_enable_RW;
158 u64 smf_sbi_signal_sel;
159 u64 smf_ato_signal_sel;
160 u64 tlb_index_hint_RO;
161 u64 tlb_index_W;
162 u64 tlb_vpn_RW;
163 u64 tlb_rpn_RW;
164 u64 tlb_invalidate_entry_W;
165 u64 tlb_invalidate_all_W;
166 u64 smm_hid;
167 u64 mfc_accr_RW;
168 u64 mfc_dsisr_RW;
169 u64 mfc_dar_RW;
170 u64 rmt_index_RW;
171 u64 rmt_data1_RW;
172 u64 mfc_dsir_R;
173 u64 mfc_lsacr_RW;
174 u64 mfc_lscrr_R;
175 u64 mfc_tclass_id_RW;
176 u64 mfc_rm_boundary;
177 u64 smf_dma_signal_sel;
178 u64 smm_signal_sel;
179 u64 mfc_cer_R;
180 u64 pu_ecc_cntl_RW;
181 u64 pu_ecc_stat_RW;
182 u64 spu_ecc_addr_RW;
183 u64 spu_err_mask_RW;
184 u64 spu_trig0_sel;
185 u64 spu_trig1_sel;
186 u64 spu_trig2_sel;
187 u64 spu_trig3_sel;
188 u64 spu_trace_sel;
189 u64 spu_event0_sel;
190 u64 spu_event1_sel;
191 u64 spu_event2_sel;
192 u64 spu_event3_sel;
193 u64 spu_trace_cntl;
194};
195
196/*
197 * struct spu_priv2_collapsed - condensed privileged 2 area, w/o pads.
198 */
199struct spu_priv2_collapsed {
200 u64 slb_index_W;
201 u64 slb_esid_RW;
202 u64 slb_vsid_RW;
203 u64 slb_invalidate_entry_W;
204 u64 slb_invalidate_all_W;
205 struct mfc_cq_sr spuq[16];
206 struct mfc_cq_sr puq[8];
207 u64 mfc_control_RW;
208 u64 puint_mb_R;
209 u64 spu_privcntl_RW;
210 u64 spu_lslr_RW;
211 u64 spu_chnlcntptr_RW;
212 u64 spu_chnlcnt_RW;
213 u64 spu_chnldata_RW;
214 u64 spu_cfg_RW;
215 u64 spu_tag_status_query_RW;
216 u64 spu_cmd_buf1_RW;
217 u64 spu_cmd_buf2_RW;
218 u64 spu_atomic_status_RW;
219};
220
221/**
222 * struct spu_state
223 * @lscsa: Local Store Context Save Area.
224 * @prob: Collapsed Problem State Area, w/o pads.
225 * @priv1: Collapsed Privileged 1 Area, w/o pads.
226 * @priv2: Collapsed Privileged 2 Area, w/o pads.
227 * @spu_chnlcnt_RW: Array of saved channel counts.
228 * @spu_chnldata_RW: Array of saved channel data.
229 * @suspend_time: Time stamp when decrementer disabled.
230 *
231 * Structure representing the whole of the SPU
232 * context save area (CSA). This struct contains
233 * all of the state necessary to suspend and then
234 * later optionally resume execution of an SPU
235 * context.
236 *
237 * The @lscsa region is by far the largest, and is
238 * allocated separately so that it may either be
239 * pinned or mapped to/from application memory, as
240 * appropriate for the OS environment.
241 */
242struct spu_state {
243 struct spu_lscsa *lscsa;
244#ifdef CONFIG_SPU_FS_64K_LS
245 int use_big_pages;
246 /* One struct page per 64k page */
247#define SPU_LSCSA_NUM_BIG_PAGES (sizeof(struct spu_lscsa) / 0x10000)
248 struct page *lscsa_pages[SPU_LSCSA_NUM_BIG_PAGES];
249#endif
250 struct spu_problem_collapsed prob;
251 struct spu_priv1_collapsed priv1;
252 struct spu_priv2_collapsed priv2;
253 u64 spu_chnlcnt_RW[32];
254 u64 spu_chnldata_RW[32];
255 u32 spu_mailbox_data[4];
256 u32 pu_mailbox_data[1];
257 u64 class_0_dar, class_0_pending;
258 u64 class_1_dar, class_1_dsisr;
259 unsigned long suspend_time;
260 spinlock_t register_lock;
261};
262
263#endif /* !__SPU__ */
264#endif /* __KERNEL__ */
265#endif /* !__ASSEMBLY__ */
266#endif /* _SPU_CSA_H_ */
diff --git a/include/asm-powerpc/spu_info.h b/include/asm-powerpc/spu_info.h
deleted file mode 100644
index 3545efbf989..00000000000
--- a/include/asm-powerpc/spu_info.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * SPU info structures
3 *
4 * (C) Copyright 2006 IBM Corp.
5 *
6 * Author: Dwayne Grant McConnell <decimal@us.ibm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef _SPU_INFO_H
24#define _SPU_INFO_H
25
26#ifdef __KERNEL__
27#include <asm/spu.h>
28#include <linux/types.h>
29#else
30struct mfc_cq_sr {
31 __u64 mfc_cq_data0_RW;
32 __u64 mfc_cq_data1_RW;
33 __u64 mfc_cq_data2_RW;
34 __u64 mfc_cq_data3_RW;
35};
36#endif /* __KERNEL__ */
37
38struct spu_dma_info {
39 __u64 dma_info_type;
40 __u64 dma_info_mask;
41 __u64 dma_info_status;
42 __u64 dma_info_stall_and_notify;
43 __u64 dma_info_atomic_command_status;
44 struct mfc_cq_sr dma_info_command_data[16];
45};
46
47struct spu_proxydma_info {
48 __u64 proxydma_info_type;
49 __u64 proxydma_info_mask;
50 __u64 proxydma_info_status;
51 struct mfc_cq_sr proxydma_info_command_data[8];
52};
53
54#endif
diff --git a/include/asm-powerpc/spu_priv1.h b/include/asm-powerpc/spu_priv1.h
deleted file mode 100644
index 25020a34ce7..00000000000
--- a/include/asm-powerpc/spu_priv1.h
+++ /dev/null
@@ -1,236 +0,0 @@
1/*
2 * Defines an spu hypervisor abstraction layer.
3 *
4 * Copyright 2006 Sony Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#if !defined(_SPU_PRIV1_H)
21#define _SPU_PRIV1_H
22#if defined(__KERNEL__)
23
24#include <linux/types.h>
25
26struct spu;
27struct spu_context;
28
29/* access to priv1 registers */
30
31struct spu_priv1_ops {
32 void (*int_mask_and) (struct spu *spu, int class, u64 mask);
33 void (*int_mask_or) (struct spu *spu, int class, u64 mask);
34 void (*int_mask_set) (struct spu *spu, int class, u64 mask);
35 u64 (*int_mask_get) (struct spu *spu, int class);
36 void (*int_stat_clear) (struct spu *spu, int class, u64 stat);
37 u64 (*int_stat_get) (struct spu *spu, int class);
38 void (*cpu_affinity_set) (struct spu *spu, int cpu);
39 u64 (*mfc_dar_get) (struct spu *spu);
40 u64 (*mfc_dsisr_get) (struct spu *spu);
41 void (*mfc_dsisr_set) (struct spu *spu, u64 dsisr);
42 void (*mfc_sdr_setup) (struct spu *spu);
43 void (*mfc_sr1_set) (struct spu *spu, u64 sr1);
44 u64 (*mfc_sr1_get) (struct spu *spu);
45 void (*mfc_tclass_id_set) (struct spu *spu, u64 tclass_id);
46 u64 (*mfc_tclass_id_get) (struct spu *spu);
47 void (*tlb_invalidate) (struct spu *spu);
48 void (*resource_allocation_groupID_set) (struct spu *spu, u64 id);
49 u64 (*resource_allocation_groupID_get) (struct spu *spu);
50 void (*resource_allocation_enable_set) (struct spu *spu, u64 enable);
51 u64 (*resource_allocation_enable_get) (struct spu *spu);
52};
53
54extern const struct spu_priv1_ops* spu_priv1_ops;
55
56static inline void
57spu_int_mask_and (struct spu *spu, int class, u64 mask)
58{
59 spu_priv1_ops->int_mask_and(spu, class, mask);
60}
61
62static inline void
63spu_int_mask_or (struct spu *spu, int class, u64 mask)
64{
65 spu_priv1_ops->int_mask_or(spu, class, mask);
66}
67
68static inline void
69spu_int_mask_set (struct spu *spu, int class, u64 mask)
70{
71 spu_priv1_ops->int_mask_set(spu, class, mask);
72}
73
74static inline u64
75spu_int_mask_get (struct spu *spu, int class)
76{
77 return spu_priv1_ops->int_mask_get(spu, class);
78}
79
80static inline void
81spu_int_stat_clear (struct spu *spu, int class, u64 stat)
82{
83 spu_priv1_ops->int_stat_clear(spu, class, stat);
84}
85
86static inline u64
87spu_int_stat_get (struct spu *spu, int class)
88{
89 return spu_priv1_ops->int_stat_get (spu, class);
90}
91
92static inline void
93spu_cpu_affinity_set (struct spu *spu, int cpu)
94{
95 spu_priv1_ops->cpu_affinity_set(spu, cpu);
96}
97
98static inline u64
99spu_mfc_dar_get (struct spu *spu)
100{
101 return spu_priv1_ops->mfc_dar_get(spu);
102}
103
104static inline u64
105spu_mfc_dsisr_get (struct spu *spu)
106{
107 return spu_priv1_ops->mfc_dsisr_get(spu);
108}
109
110static inline void
111spu_mfc_dsisr_set (struct spu *spu, u64 dsisr)
112{
113 spu_priv1_ops->mfc_dsisr_set(spu, dsisr);
114}
115
116static inline void
117spu_mfc_sdr_setup (struct spu *spu)
118{
119 spu_priv1_ops->mfc_sdr_setup(spu);
120}
121
122static inline void
123spu_mfc_sr1_set (struct spu *spu, u64 sr1)
124{
125 spu_priv1_ops->mfc_sr1_set(spu, sr1);
126}
127
128static inline u64
129spu_mfc_sr1_get (struct spu *spu)
130{
131 return spu_priv1_ops->mfc_sr1_get(spu);
132}
133
134static inline void
135spu_mfc_tclass_id_set (struct spu *spu, u64 tclass_id)
136{
137 spu_priv1_ops->mfc_tclass_id_set(spu, tclass_id);
138}
139
140static inline u64
141spu_mfc_tclass_id_get (struct spu *spu)
142{
143 return spu_priv1_ops->mfc_tclass_id_get(spu);
144}
145
146static inline void
147spu_tlb_invalidate (struct spu *spu)
148{
149 spu_priv1_ops->tlb_invalidate(spu);
150}
151
152static inline void
153spu_resource_allocation_groupID_set (struct spu *spu, u64 id)
154{
155 spu_priv1_ops->resource_allocation_groupID_set(spu, id);
156}
157
158static inline u64
159spu_resource_allocation_groupID_get (struct spu *spu)
160{
161 return spu_priv1_ops->resource_allocation_groupID_get(spu);
162}
163
164static inline void
165spu_resource_allocation_enable_set (struct spu *spu, u64 enable)
166{
167 spu_priv1_ops->resource_allocation_enable_set(spu, enable);
168}
169
170static inline u64
171spu_resource_allocation_enable_get (struct spu *spu)
172{
173 return spu_priv1_ops->resource_allocation_enable_get(spu);
174}
175
176/* spu management abstraction */
177
178struct spu_management_ops {
179 int (*enumerate_spus)(int (*fn)(void *data));
180 int (*create_spu)(struct spu *spu, void *data);
181 int (*destroy_spu)(struct spu *spu);
182 void (*enable_spu)(struct spu_context *ctx);
183 void (*disable_spu)(struct spu_context *ctx);
184 int (*init_affinity)(void);
185};
186
187extern const struct spu_management_ops* spu_management_ops;
188
189static inline int
190spu_enumerate_spus (int (*fn)(void *data))
191{
192 return spu_management_ops->enumerate_spus(fn);
193}
194
195static inline int
196spu_create_spu (struct spu *spu, void *data)
197{
198 return spu_management_ops->create_spu(spu, data);
199}
200
201static inline int
202spu_destroy_spu (struct spu *spu)
203{
204 return spu_management_ops->destroy_spu(spu);
205}
206
207static inline int
208spu_init_affinity (void)
209{
210 return spu_management_ops->init_affinity();
211}
212
213static inline void
214spu_enable_spu (struct spu_context *ctx)
215{
216 spu_management_ops->enable_spu(ctx);
217}
218
219static inline void
220spu_disable_spu (struct spu_context *ctx)
221{
222 spu_management_ops->disable_spu(ctx);
223}
224
225/*
226 * The declarations folowing are put here for convenience
227 * and only intended to be used by the platform setup code.
228 */
229
230extern const struct spu_priv1_ops spu_priv1_mmio_ops;
231extern const struct spu_priv1_ops spu_priv1_beat_ops;
232
233extern const struct spu_management_ops spu_management_of_ops;
234
235#endif /* __KERNEL__ */
236#endif
diff --git a/include/asm-powerpc/sstep.h b/include/asm-powerpc/sstep.h
deleted file mode 100644
index f593b0f9b62..00000000000
--- a/include/asm-powerpc/sstep.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10struct pt_regs;
11
12/*
13 * We don't allow single-stepping an mtmsrd that would clear
14 * MSR_RI, since that would make the exception unrecoverable.
15 * Since we need to single-step to proceed from a breakpoint,
16 * we don't allow putting a breakpoint on an mtmsrd instruction.
17 * Similarly we don't allow breakpoints on rfid instructions.
18 * These macros tell us if an instruction is a mtmsrd or rfid.
19 * Note that IS_MTMSRD returns true for both an mtmsr (32-bit)
20 * and an mtmsrd (64-bit).
21 */
22#define IS_MTMSRD(instr) (((instr) & 0xfc0007be) == 0x7c000124)
23#define IS_RFID(instr) (((instr) & 0xfc0007fe) == 0x4c000024)
24#define IS_RFI(instr) (((instr) & 0xfc0007fe) == 0x4c000064)
25
26/* Emulate instructions that cause a transfer of control. */
27extern int emulate_step(struct pt_regs *regs, unsigned int instr);
diff --git a/include/asm-powerpc/stat.h b/include/asm-powerpc/stat.h
deleted file mode 100644
index e4edc510b53..00000000000
--- a/include/asm-powerpc/stat.h
+++ /dev/null
@@ -1,81 +0,0 @@
1#ifndef _ASM_POWERPC_STAT_H
2#define _ASM_POWERPC_STAT_H
3/*
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9#include <linux/types.h>
10
11#define STAT_HAVE_NSEC 1
12
13#ifndef __powerpc64__
14struct __old_kernel_stat {
15 unsigned short st_dev;
16 unsigned short st_ino;
17 unsigned short st_mode;
18 unsigned short st_nlink;
19 unsigned short st_uid;
20 unsigned short st_gid;
21 unsigned short st_rdev;
22 unsigned long st_size;
23 unsigned long st_atime;
24 unsigned long st_mtime;
25 unsigned long st_ctime;
26};
27#endif /* !__powerpc64__ */
28
29struct stat {
30 unsigned long st_dev;
31 ino_t st_ino;
32#ifdef __powerpc64__
33 nlink_t st_nlink;
34 mode_t st_mode;
35#else
36 mode_t st_mode;
37 nlink_t st_nlink;
38#endif
39 uid_t st_uid;
40 gid_t st_gid;
41 unsigned long st_rdev;
42 off_t st_size;
43 unsigned long st_blksize;
44 unsigned long st_blocks;
45 unsigned long st_atime;
46 unsigned long st_atime_nsec;
47 unsigned long st_mtime;
48 unsigned long st_mtime_nsec;
49 unsigned long st_ctime;
50 unsigned long st_ctime_nsec;
51 unsigned long __unused4;
52 unsigned long __unused5;
53#ifdef __powerpc64__
54 unsigned long __unused6;
55#endif
56};
57
58/* This matches struct stat64 in glibc2.1. Only used for 32 bit. */
59struct stat64 {
60 unsigned long long st_dev; /* Device. */
61 unsigned long long st_ino; /* File serial number. */
62 unsigned int st_mode; /* File mode. */
63 unsigned int st_nlink; /* Link count. */
64 unsigned int st_uid; /* User ID of the file's owner. */
65 unsigned int st_gid; /* Group ID of the file's group. */
66 unsigned long long st_rdev; /* Device number, if device. */
67 unsigned short __pad2;
68 long long st_size; /* Size of file, in bytes. */
69 int st_blksize; /* Optimal block size for I/O. */
70 long long st_blocks; /* Number 512-byte blocks allocated. */
71 int st_atime; /* Time of last access. */
72 unsigned int st_atime_nsec;
73 int st_mtime; /* Time of last modification. */
74 unsigned int st_mtime_nsec;
75 int st_ctime; /* Time of last status change. */
76 unsigned int st_ctime_nsec;
77 unsigned int __unused4;
78 unsigned int __unused5;
79};
80
81#endif /* _ASM_POWERPC_STAT_H */
diff --git a/include/asm-powerpc/statfs.h b/include/asm-powerpc/statfs.h
deleted file mode 100644
index 67024026c10..00000000000
--- a/include/asm-powerpc/statfs.h
+++ /dev/null
@@ -1,60 +0,0 @@
1#ifndef _ASM_POWERPC_STATFS_H
2#define _ASM_POWERPC_STATFS_H
3
4/* For ppc32 we just use the generic definitions, not so simple on ppc64 */
5
6#ifndef __powerpc64__
7#include <asm-generic/statfs.h>
8#else
9
10#ifndef __KERNEL_STRICT_NAMES
11#include <linux/types.h>
12typedef __kernel_fsid_t fsid_t;
13#endif
14
15/*
16 * We're already 64-bit, so duplicate the definition
17 */
18struct statfs {
19 long f_type;
20 long f_bsize;
21 long f_blocks;
22 long f_bfree;
23 long f_bavail;
24 long f_files;
25 long f_ffree;
26 __kernel_fsid_t f_fsid;
27 long f_namelen;
28 long f_frsize;
29 long f_spare[5];
30};
31
32struct statfs64 {
33 long f_type;
34 long f_bsize;
35 long f_blocks;
36 long f_bfree;
37 long f_bavail;
38 long f_files;
39 long f_ffree;
40 __kernel_fsid_t f_fsid;
41 long f_namelen;
42 long f_frsize;
43 long f_spare[5];
44};
45
46struct compat_statfs64 {
47 __u32 f_type;
48 __u32 f_bsize;
49 __u64 f_blocks;
50 __u64 f_bfree;
51 __u64 f_bavail;
52 __u64 f_files;
53 __u64 f_ffree;
54 __kernel_fsid_t f_fsid;
55 __u32 f_namelen;
56 __u32 f_frsize;
57 __u32 f_spare[5];
58};
59#endif /* ! __powerpc64__ */
60#endif
diff --git a/include/asm-powerpc/string.h b/include/asm-powerpc/string.h
deleted file mode 100644
index e40010abcaf..00000000000
--- a/include/asm-powerpc/string.h
+++ /dev/null
@@ -1,32 +0,0 @@
1#ifndef _ASM_POWERPC_STRING_H
2#define _ASM_POWERPC_STRING_H
3
4#ifdef __KERNEL__
5
6#define __HAVE_ARCH_STRCPY
7#define __HAVE_ARCH_STRNCPY
8#define __HAVE_ARCH_STRLEN
9#define __HAVE_ARCH_STRCMP
10#define __HAVE_ARCH_STRNCMP
11#define __HAVE_ARCH_STRCAT
12#define __HAVE_ARCH_MEMSET
13#define __HAVE_ARCH_MEMCPY
14#define __HAVE_ARCH_MEMMOVE
15#define __HAVE_ARCH_MEMCMP
16#define __HAVE_ARCH_MEMCHR
17
18extern char * strcpy(char *,const char *);
19extern char * strncpy(char *,const char *, __kernel_size_t);
20extern __kernel_size_t strlen(const char *);
21extern int strcmp(const char *,const char *);
22extern int strncmp(const char *, const char *, __kernel_size_t);
23extern char * strcat(char *, const char *);
24extern void * memset(void *,int,__kernel_size_t);
25extern void * memcpy(void *,const void *,__kernel_size_t);
26extern void * memmove(void *,const void *,__kernel_size_t);
27extern int memcmp(const void *,const void *,__kernel_size_t);
28extern void * memchr(const void *,int,__kernel_size_t);
29
30#endif /* __KERNEL__ */
31
32#endif /* _ASM_POWERPC_STRING_H */
diff --git a/include/asm-powerpc/suspend.h b/include/asm-powerpc/suspend.h
deleted file mode 100644
index cbf2c9404c3..00000000000
--- a/include/asm-powerpc/suspend.h
+++ /dev/null
@@ -1,9 +0,0 @@
1#ifndef __ASM_POWERPC_SUSPEND_H
2#define __ASM_POWERPC_SUSPEND_H
3
4static inline int arch_prepare_suspend(void) { return 0; }
5
6void save_processor_state(void);
7void restore_processor_state(void);
8
9#endif /* __ASM_POWERPC_SUSPEND_H */
diff --git a/include/asm-powerpc/synch.h b/include/asm-powerpc/synch.h
deleted file mode 100644
index 45963e80f55..00000000000
--- a/include/asm-powerpc/synch.h
+++ /dev/null
@@ -1,44 +0,0 @@
1#ifndef _ASM_POWERPC_SYNCH_H
2#define _ASM_POWERPC_SYNCH_H
3#ifdef __KERNEL__
4
5#include <linux/stringify.h>
6#include <asm/feature-fixups.h>
7
8#ifndef __ASSEMBLY__
9extern unsigned int __start___lwsync_fixup, __stop___lwsync_fixup;
10extern void do_lwsync_fixups(unsigned long value, void *fixup_start,
11 void *fixup_end);
12
13static inline void eieio(void)
14{
15 __asm__ __volatile__ ("eieio" : : : "memory");
16}
17
18static inline void isync(void)
19{
20 __asm__ __volatile__ ("isync" : : : "memory");
21}
22#endif /* __ASSEMBLY__ */
23
24#if defined(__powerpc64__)
25# define LWSYNC lwsync
26#elif defined(CONFIG_E500)
27# define LWSYNC \
28 START_LWSYNC_SECTION(96); \
29 sync; \
30 MAKE_LWSYNC_SECTION_ENTRY(96, __lwsync_fixup);
31#else
32# define LWSYNC sync
33#endif
34
35#ifdef CONFIG_SMP
36#define ISYNC_ON_SMP "\n\tisync\n"
37#define LWSYNC_ON_SMP stringify_in_c(LWSYNC) "\n"
38#else
39#define ISYNC_ON_SMP
40#define LWSYNC_ON_SMP
41#endif
42
43#endif /* __KERNEL__ */
44#endif /* _ASM_POWERPC_SYNCH_H */
diff --git a/include/asm-powerpc/syscalls.h b/include/asm-powerpc/syscalls.h
deleted file mode 100644
index eb8eb400c66..00000000000
--- a/include/asm-powerpc/syscalls.h
+++ /dev/null
@@ -1,52 +0,0 @@
1#ifndef __ASM_POWERPC_SYSCALLS_H
2#define __ASM_POWERPC_SYSCALLS_H
3#ifdef __KERNEL__
4
5#include <linux/compiler.h>
6#include <linux/linkage.h>
7#include <linux/types.h>
8#include <asm/signal.h>
9
10struct new_utsname;
11struct pt_regs;
12struct rtas_args;
13struct sigaction;
14
15asmlinkage unsigned long sys_mmap(unsigned long addr, size_t len,
16 unsigned long prot, unsigned long flags,
17 unsigned long fd, off_t offset);
18asmlinkage unsigned long sys_mmap2(unsigned long addr, size_t len,
19 unsigned long prot, unsigned long flags,
20 unsigned long fd, unsigned long pgoff);
21asmlinkage int sys_execve(unsigned long a0, unsigned long a1,
22 unsigned long a2, unsigned long a3, unsigned long a4,
23 unsigned long a5, struct pt_regs *regs);
24asmlinkage int sys_clone(unsigned long clone_flags, unsigned long usp,
25 int __user *parent_tidp, void __user *child_threadptr,
26 int __user *child_tidp, int p6, struct pt_regs *regs);
27asmlinkage int sys_fork(unsigned long p1, unsigned long p2,
28 unsigned long p3, unsigned long p4, unsigned long p5,
29 unsigned long p6, struct pt_regs *regs);
30asmlinkage int sys_vfork(unsigned long p1, unsigned long p2,
31 unsigned long p3, unsigned long p4, unsigned long p5,
32 unsigned long p6, struct pt_regs *regs);
33asmlinkage long sys_pipe(int __user *fildes);
34asmlinkage long sys_pipe2(int __user *fildes, int flags);
35asmlinkage long sys_rt_sigaction(int sig,
36 const struct sigaction __user *act,
37 struct sigaction __user *oact, size_t sigsetsize);
38asmlinkage int sys_ipc(uint call, int first, unsigned long second,
39 long third, void __user *ptr, long fifth);
40asmlinkage long ppc64_personality(unsigned long personality);
41asmlinkage int ppc_rtas(struct rtas_args __user *uargs);
42asmlinkage time_t sys64_time(time_t __user * tloc);
43asmlinkage long ppc_newuname(struct new_utsname __user * name);
44
45asmlinkage long sys_rt_sigsuspend(sigset_t __user *unewset,
46 size_t sigsetsize);
47asmlinkage long sys_sigaltstack(const stack_t __user *uss,
48 stack_t __user *uoss, unsigned long r5, unsigned long r6,
49 unsigned long r7, unsigned long r8, struct pt_regs *regs);
50
51#endif /* __KERNEL__ */
52#endif /* __ASM_POWERPC_SYSCALLS_H */
diff --git a/include/asm-powerpc/systbl.h b/include/asm-powerpc/systbl.h
deleted file mode 100644
index e084272ed1c..00000000000
--- a/include/asm-powerpc/systbl.h
+++ /dev/null
@@ -1,324 +0,0 @@
1/*
2 * List of powerpc syscalls. For the meaning of the _SPU suffix see
3 * arch/powerpc/platforms/cell/spu_callbacks.c
4 */
5
6SYSCALL(restart_syscall)
7SYSCALL(exit)
8PPC_SYS(fork)
9SYSCALL_SPU(read)
10SYSCALL_SPU(write)
11COMPAT_SYS_SPU(open)
12SYSCALL_SPU(close)
13COMPAT_SYS_SPU(waitpid)
14COMPAT_SYS_SPU(creat)
15SYSCALL_SPU(link)
16SYSCALL_SPU(unlink)
17COMPAT_SYS(execve)
18SYSCALL_SPU(chdir)
19COMPAT_SYS_SPU(time)
20SYSCALL_SPU(mknod)
21SYSCALL_SPU(chmod)
22SYSCALL_SPU(lchown)
23SYSCALL(ni_syscall)
24OLDSYS(stat)
25SYSX_SPU(sys_lseek,ppc32_lseek,sys_lseek)
26SYSCALL_SPU(getpid)
27COMPAT_SYS(mount)
28SYSX(sys_ni_syscall,sys_oldumount,sys_oldumount)
29SYSCALL_SPU(setuid)
30SYSCALL_SPU(getuid)
31COMPAT_SYS_SPU(stime)
32COMPAT_SYS(ptrace)
33SYSCALL_SPU(alarm)
34OLDSYS(fstat)
35COMPAT_SYS(pause)
36COMPAT_SYS(utime)
37SYSCALL(ni_syscall)
38SYSCALL(ni_syscall)
39COMPAT_SYS_SPU(access)
40COMPAT_SYS_SPU(nice)
41SYSCALL(ni_syscall)
42SYSCALL_SPU(sync)
43COMPAT_SYS_SPU(kill)
44SYSCALL_SPU(rename)
45COMPAT_SYS_SPU(mkdir)
46SYSCALL_SPU(rmdir)
47SYSCALL_SPU(dup)
48SYSCALL_SPU(pipe)
49COMPAT_SYS_SPU(times)
50SYSCALL(ni_syscall)
51SYSCALL_SPU(brk)
52SYSCALL_SPU(setgid)
53SYSCALL_SPU(getgid)
54SYSCALL(signal)
55SYSCALL_SPU(geteuid)
56SYSCALL_SPU(getegid)
57SYSCALL(acct)
58SYSCALL(umount)
59SYSCALL(ni_syscall)
60COMPAT_SYS_SPU(ioctl)
61COMPAT_SYS_SPU(fcntl)
62SYSCALL(ni_syscall)
63COMPAT_SYS_SPU(setpgid)
64SYSCALL(ni_syscall)
65SYSX(sys_ni_syscall,sys_olduname, sys_olduname)
66COMPAT_SYS_SPU(umask)
67SYSCALL_SPU(chroot)
68SYSCALL(ustat)
69SYSCALL_SPU(dup2)
70SYSCALL_SPU(getppid)
71SYSCALL_SPU(getpgrp)
72SYSCALL_SPU(setsid)
73SYS32ONLY(sigaction)
74SYSCALL_SPU(sgetmask)
75COMPAT_SYS_SPU(ssetmask)
76SYSCALL_SPU(setreuid)
77SYSCALL_SPU(setregid)
78SYS32ONLY(sigsuspend)
79COMPAT_SYS(sigpending)
80COMPAT_SYS_SPU(sethostname)
81COMPAT_SYS_SPU(setrlimit)
82COMPAT_SYS(old_getrlimit)
83COMPAT_SYS_SPU(getrusage)
84COMPAT_SYS_SPU(gettimeofday)
85COMPAT_SYS_SPU(settimeofday)
86COMPAT_SYS_SPU(getgroups)
87COMPAT_SYS_SPU(setgroups)
88SYSX(sys_ni_syscall,sys_ni_syscall,ppc_select)
89SYSCALL_SPU(symlink)
90OLDSYS(lstat)
91COMPAT_SYS_SPU(readlink)
92SYSCALL(uselib)
93SYSCALL(swapon)
94SYSCALL(reboot)
95SYSX(sys_ni_syscall,old32_readdir,old_readdir)
96SYSCALL_SPU(mmap)
97SYSCALL_SPU(munmap)
98SYSCALL_SPU(truncate)
99SYSCALL_SPU(ftruncate)
100SYSCALL_SPU(fchmod)
101SYSCALL_SPU(fchown)
102COMPAT_SYS_SPU(getpriority)
103COMPAT_SYS_SPU(setpriority)
104SYSCALL(ni_syscall)
105COMPAT_SYS(statfs)
106COMPAT_SYS(fstatfs)
107SYSCALL(ni_syscall)
108COMPAT_SYS_SPU(socketcall)
109COMPAT_SYS_SPU(syslog)
110COMPAT_SYS_SPU(setitimer)
111COMPAT_SYS_SPU(getitimer)
112COMPAT_SYS_SPU(newstat)
113COMPAT_SYS_SPU(newlstat)
114COMPAT_SYS_SPU(newfstat)
115SYSX(sys_ni_syscall,sys_uname,sys_uname)
116SYSCALL(ni_syscall)
117SYSCALL_SPU(vhangup)
118SYSCALL(ni_syscall)
119SYSCALL(ni_syscall)
120COMPAT_SYS_SPU(wait4)
121SYSCALL(swapoff)
122COMPAT_SYS_SPU(sysinfo)
123COMPAT_SYS(ipc)
124SYSCALL_SPU(fsync)
125SYS32ONLY(sigreturn)
126PPC_SYS(clone)
127COMPAT_SYS_SPU(setdomainname)
128PPC_SYS_SPU(newuname)
129SYSCALL(ni_syscall)
130COMPAT_SYS_SPU(adjtimex)
131SYSCALL_SPU(mprotect)
132SYSX(sys_ni_syscall,compat_sys_sigprocmask,sys_sigprocmask)
133SYSCALL(ni_syscall)
134SYSCALL(init_module)
135SYSCALL(delete_module)
136SYSCALL(ni_syscall)
137SYSCALL(quotactl)
138COMPAT_SYS_SPU(getpgid)
139SYSCALL_SPU(fchdir)
140SYSCALL_SPU(bdflush)
141COMPAT_SYS(sysfs)
142SYSX_SPU(ppc64_personality,ppc64_personality,sys_personality)
143SYSCALL(ni_syscall)
144SYSCALL_SPU(setfsuid)
145SYSCALL_SPU(setfsgid)
146SYSCALL_SPU(llseek)
147COMPAT_SYS_SPU(getdents)
148SYSX_SPU(sys_select,ppc32_select,ppc_select)
149SYSCALL_SPU(flock)
150SYSCALL_SPU(msync)
151COMPAT_SYS_SPU(readv)
152COMPAT_SYS_SPU(writev)
153COMPAT_SYS_SPU(getsid)
154SYSCALL_SPU(fdatasync)
155COMPAT_SYS(sysctl)
156SYSCALL_SPU(mlock)
157SYSCALL_SPU(munlock)
158SYSCALL_SPU(mlockall)
159SYSCALL_SPU(munlockall)
160COMPAT_SYS_SPU(sched_setparam)
161COMPAT_SYS_SPU(sched_getparam)
162COMPAT_SYS_SPU(sched_setscheduler)
163COMPAT_SYS_SPU(sched_getscheduler)
164SYSCALL_SPU(sched_yield)
165COMPAT_SYS_SPU(sched_get_priority_max)
166COMPAT_SYS_SPU(sched_get_priority_min)
167COMPAT_SYS_SPU(sched_rr_get_interval)
168COMPAT_SYS_SPU(nanosleep)
169SYSCALL_SPU(mremap)
170SYSCALL_SPU(setresuid)
171SYSCALL_SPU(getresuid)
172SYSCALL(ni_syscall)
173SYSCALL_SPU(poll)
174COMPAT_SYS(nfsservctl)
175SYSCALL_SPU(setresgid)
176SYSCALL_SPU(getresgid)
177COMPAT_SYS_SPU(prctl)
178COMPAT_SYS(rt_sigreturn)
179COMPAT_SYS(rt_sigaction)
180COMPAT_SYS(rt_sigprocmask)
181COMPAT_SYS(rt_sigpending)
182COMPAT_SYS(rt_sigtimedwait)
183COMPAT_SYS(rt_sigqueueinfo)
184COMPAT_SYS(rt_sigsuspend)
185COMPAT_SYS_SPU(pread64)
186COMPAT_SYS_SPU(pwrite64)
187SYSCALL_SPU(chown)
188SYSCALL_SPU(getcwd)
189SYSCALL_SPU(capget)
190SYSCALL_SPU(capset)
191COMPAT_SYS(sigaltstack)
192SYSX_SPU(sys_sendfile64,compat_sys_sendfile,sys_sendfile)
193SYSCALL(ni_syscall)
194SYSCALL(ni_syscall)
195PPC_SYS(vfork)
196COMPAT_SYS_SPU(getrlimit)
197COMPAT_SYS_SPU(readahead)
198SYS32ONLY(mmap2)
199SYS32ONLY(truncate64)
200SYS32ONLY(ftruncate64)
201SYSX(sys_ni_syscall,sys_stat64,sys_stat64)
202SYSX(sys_ni_syscall,sys_lstat64,sys_lstat64)
203SYSX(sys_ni_syscall,sys_fstat64,sys_fstat64)
204SYSCALL(pciconfig_read)
205SYSCALL(pciconfig_write)
206SYSCALL(pciconfig_iobase)
207SYSCALL(ni_syscall)
208SYSCALL_SPU(getdents64)
209SYSCALL_SPU(pivot_root)
210SYSX(sys_ni_syscall,compat_sys_fcntl64,sys_fcntl64)
211SYSCALL_SPU(madvise)
212SYSCALL_SPU(mincore)
213SYSCALL_SPU(gettid)
214SYSCALL_SPU(tkill)
215SYSCALL_SPU(setxattr)
216SYSCALL_SPU(lsetxattr)
217SYSCALL_SPU(fsetxattr)
218SYSCALL_SPU(getxattr)
219SYSCALL_SPU(lgetxattr)
220SYSCALL_SPU(fgetxattr)
221SYSCALL_SPU(listxattr)
222SYSCALL_SPU(llistxattr)
223SYSCALL_SPU(flistxattr)
224SYSCALL_SPU(removexattr)
225SYSCALL_SPU(lremovexattr)
226SYSCALL_SPU(fremovexattr)
227COMPAT_SYS_SPU(futex)
228COMPAT_SYS_SPU(sched_setaffinity)
229COMPAT_SYS_SPU(sched_getaffinity)
230SYSCALL(ni_syscall)
231SYSCALL(ni_syscall)
232SYS32ONLY(sendfile64)
233COMPAT_SYS_SPU(io_setup)
234SYSCALL_SPU(io_destroy)
235COMPAT_SYS_SPU(io_getevents)
236COMPAT_SYS_SPU(io_submit)
237SYSCALL_SPU(io_cancel)
238SYSCALL(set_tid_address)
239SYSX_SPU(sys_fadvise64,ppc32_fadvise64,sys_fadvise64)
240SYSCALL(exit_group)
241SYSX(sys_lookup_dcookie,ppc32_lookup_dcookie,sys_lookup_dcookie)
242SYSCALL_SPU(epoll_create)
243SYSCALL_SPU(epoll_ctl)
244SYSCALL_SPU(epoll_wait)
245SYSCALL_SPU(remap_file_pages)
246SYSX_SPU(sys_timer_create,compat_sys_timer_create,sys_timer_create)
247COMPAT_SYS_SPU(timer_settime)
248COMPAT_SYS_SPU(timer_gettime)
249SYSCALL_SPU(timer_getoverrun)
250SYSCALL_SPU(timer_delete)
251COMPAT_SYS_SPU(clock_settime)
252COMPAT_SYS_SPU(clock_gettime)
253COMPAT_SYS_SPU(clock_getres)
254COMPAT_SYS_SPU(clock_nanosleep)
255SYSX(ppc64_swapcontext,ppc32_swapcontext,ppc_swapcontext)
256COMPAT_SYS_SPU(tgkill)
257COMPAT_SYS_SPU(utimes)
258COMPAT_SYS_SPU(statfs64)
259COMPAT_SYS_SPU(fstatfs64)
260SYSX(sys_ni_syscall, ppc_fadvise64_64, ppc_fadvise64_64)
261PPC_SYS_SPU(rtas)
262OLDSYS(debug_setcontext)
263SYSCALL(ni_syscall)
264COMPAT_SYS(migrate_pages)
265COMPAT_SYS(mbind)
266COMPAT_SYS(get_mempolicy)
267COMPAT_SYS(set_mempolicy)
268COMPAT_SYS(mq_open)
269SYSCALL(mq_unlink)
270COMPAT_SYS(mq_timedsend)
271COMPAT_SYS(mq_timedreceive)
272COMPAT_SYS(mq_notify)
273COMPAT_SYS(mq_getsetattr)
274COMPAT_SYS(kexec_load)
275COMPAT_SYS(add_key)
276COMPAT_SYS(request_key)
277COMPAT_SYS(keyctl)
278COMPAT_SYS(waitid)
279COMPAT_SYS(ioprio_set)
280COMPAT_SYS(ioprio_get)
281SYSCALL(inotify_init)
282SYSCALL(inotify_add_watch)
283SYSCALL(inotify_rm_watch)
284SYSCALL(spu_run)
285SYSCALL(spu_create)
286COMPAT_SYS(pselect6)
287COMPAT_SYS(ppoll)
288SYSCALL_SPU(unshare)
289SYSCALL_SPU(splice)
290SYSCALL_SPU(tee)
291COMPAT_SYS_SPU(vmsplice)
292COMPAT_SYS_SPU(openat)
293SYSCALL_SPU(mkdirat)
294SYSCALL_SPU(mknodat)
295SYSCALL_SPU(fchownat)
296COMPAT_SYS_SPU(futimesat)
297SYSX_SPU(sys_newfstatat, sys_fstatat64, sys_fstatat64)
298SYSCALL_SPU(unlinkat)
299SYSCALL_SPU(renameat)
300SYSCALL_SPU(linkat)
301SYSCALL_SPU(symlinkat)
302SYSCALL_SPU(readlinkat)
303SYSCALL_SPU(fchmodat)
304SYSCALL_SPU(faccessat)
305COMPAT_SYS_SPU(get_robust_list)
306COMPAT_SYS_SPU(set_robust_list)
307COMPAT_SYS_SPU(move_pages)
308SYSCALL_SPU(getcpu)
309COMPAT_SYS(epoll_pwait)
310COMPAT_SYS_SPU(utimensat)
311COMPAT_SYS_SPU(signalfd)
312SYSCALL_SPU(timerfd_create)
313SYSCALL_SPU(eventfd)
314COMPAT_SYS_SPU(sync_file_range2)
315COMPAT_SYS(fallocate)
316SYSCALL(subpage_prot)
317COMPAT_SYS_SPU(timerfd_settime)
318COMPAT_SYS_SPU(timerfd_gettime)
319COMPAT_SYS_SPU(signalfd4)
320SYSCALL_SPU(eventfd2)
321SYSCALL_SPU(epoll_create1)
322SYSCALL_SPU(dup3)
323SYSCALL_SPU(pipe2)
324SYSCALL(inotify_init1)
diff --git a/include/asm-powerpc/system.h b/include/asm-powerpc/system.h
deleted file mode 100644
index d6648c14332..00000000000
--- a/include/asm-powerpc/system.h
+++ /dev/null
@@ -1,548 +0,0 @@
1/*
2 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
3 */
4#ifndef _ASM_POWERPC_SYSTEM_H
5#define _ASM_POWERPC_SYSTEM_H
6
7#include <linux/kernel.h>
8#include <linux/irqflags.h>
9
10#include <asm/hw_irq.h>
11
12/*
13 * Memory barrier.
14 * The sync instruction guarantees that all memory accesses initiated
15 * by this processor have been performed (with respect to all other
16 * mechanisms that access memory). The eieio instruction is a barrier
17 * providing an ordering (separately) for (a) cacheable stores and (b)
18 * loads and stores to non-cacheable memory (e.g. I/O devices).
19 *
20 * mb() prevents loads and stores being reordered across this point.
21 * rmb() prevents loads being reordered across this point.
22 * wmb() prevents stores being reordered across this point.
23 * read_barrier_depends() prevents data-dependent loads being reordered
24 * across this point (nop on PPC).
25 *
26 * We have to use the sync instructions for mb(), since lwsync doesn't
27 * order loads with respect to previous stores. Lwsync is fine for
28 * rmb(), though. Note that rmb() actually uses a sync on 32-bit
29 * architectures.
30 *
31 * For wmb(), we use sync since wmb is used in drivers to order
32 * stores to system memory with respect to writes to the device.
33 * However, smp_wmb() can be a lighter-weight lwsync or eieio barrier
34 * on SMP since it is only used to order updates to system memory.
35 */
36#define mb() __asm__ __volatile__ ("sync" : : : "memory")
37#define rmb() __asm__ __volatile__ ("sync" : : : "memory")
38#define wmb() __asm__ __volatile__ ("sync" : : : "memory")
39#define read_barrier_depends() do { } while(0)
40
41#define set_mb(var, value) do { var = value; mb(); } while (0)
42
43#ifdef __KERNEL__
44#define AT_VECTOR_SIZE_ARCH 6 /* entries in ARCH_DLINFO */
45#ifdef CONFIG_SMP
46
47#ifdef __SUBARCH_HAS_LWSYNC
48# define SMPWMB lwsync
49#else
50# define SMPWMB eieio
51#endif
52
53#define smp_mb() mb()
54#define smp_rmb() rmb()
55#define smp_wmb() __asm__ __volatile__ (__stringify(SMPWMB) : : :"memory")
56#define smp_read_barrier_depends() read_barrier_depends()
57#else
58#define smp_mb() barrier()
59#define smp_rmb() barrier()
60#define smp_wmb() barrier()
61#define smp_read_barrier_depends() do { } while(0)
62#endif /* CONFIG_SMP */
63
64/*
65 * This is a barrier which prevents following instructions from being
66 * started until the value of the argument x is known. For example, if
67 * x is a variable loaded from memory, this prevents following
68 * instructions from being executed until the load has been performed.
69 */
70#define data_barrier(x) \
71 asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory");
72
73struct task_struct;
74struct pt_regs;
75
76#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
77
78extern int (*__debugger)(struct pt_regs *regs);
79extern int (*__debugger_ipi)(struct pt_regs *regs);
80extern int (*__debugger_bpt)(struct pt_regs *regs);
81extern int (*__debugger_sstep)(struct pt_regs *regs);
82extern int (*__debugger_iabr_match)(struct pt_regs *regs);
83extern int (*__debugger_dabr_match)(struct pt_regs *regs);
84extern int (*__debugger_fault_handler)(struct pt_regs *regs);
85
86#define DEBUGGER_BOILERPLATE(__NAME) \
87static inline int __NAME(struct pt_regs *regs) \
88{ \
89 if (unlikely(__ ## __NAME)) \
90 return __ ## __NAME(regs); \
91 return 0; \
92}
93
94DEBUGGER_BOILERPLATE(debugger)
95DEBUGGER_BOILERPLATE(debugger_ipi)
96DEBUGGER_BOILERPLATE(debugger_bpt)
97DEBUGGER_BOILERPLATE(debugger_sstep)
98DEBUGGER_BOILERPLATE(debugger_iabr_match)
99DEBUGGER_BOILERPLATE(debugger_dabr_match)
100DEBUGGER_BOILERPLATE(debugger_fault_handler)
101
102#else
103static inline int debugger(struct pt_regs *regs) { return 0; }
104static inline int debugger_ipi(struct pt_regs *regs) { return 0; }
105static inline int debugger_bpt(struct pt_regs *regs) { return 0; }
106static inline int debugger_sstep(struct pt_regs *regs) { return 0; }
107static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; }
108static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; }
109static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
110#endif
111
112extern int set_dabr(unsigned long dabr);
113extern void do_dabr(struct pt_regs *regs, unsigned long address,
114 unsigned long error_code);
115extern void print_backtrace(unsigned long *);
116extern void show_regs(struct pt_regs * regs);
117extern void flush_instruction_cache(void);
118extern void hard_reset_now(void);
119extern void poweroff_now(void);
120
121#ifdef CONFIG_6xx
122extern long _get_L2CR(void);
123extern long _get_L3CR(void);
124extern void _set_L2CR(unsigned long);
125extern void _set_L3CR(unsigned long);
126#else
127#define _get_L2CR() 0L
128#define _get_L3CR() 0L
129#define _set_L2CR(val) do { } while(0)
130#define _set_L3CR(val) do { } while(0)
131#endif
132
133extern void via_cuda_init(void);
134extern void read_rtc_time(void);
135extern void pmac_find_display(void);
136extern void giveup_fpu(struct task_struct *);
137extern void disable_kernel_fp(void);
138extern void enable_kernel_fp(void);
139extern void flush_fp_to_thread(struct task_struct *);
140extern void enable_kernel_altivec(void);
141extern void giveup_altivec(struct task_struct *);
142extern void load_up_altivec(struct task_struct *);
143extern int emulate_altivec(struct pt_regs *);
144extern void __giveup_vsx(struct task_struct *);
145extern void giveup_vsx(struct task_struct *);
146extern void enable_kernel_spe(void);
147extern void giveup_spe(struct task_struct *);
148extern void load_up_spe(struct task_struct *);
149extern int fix_alignment(struct pt_regs *);
150extern void cvt_fd(float *from, double *to, struct thread_struct *thread);
151extern void cvt_df(double *from, float *to, struct thread_struct *thread);
152
153#ifndef CONFIG_SMP
154extern void discard_lazy_cpu_state(void);
155#else
156static inline void discard_lazy_cpu_state(void)
157{
158}
159#endif
160
161#ifdef CONFIG_ALTIVEC
162extern void flush_altivec_to_thread(struct task_struct *);
163#else
164static inline void flush_altivec_to_thread(struct task_struct *t)
165{
166}
167#endif
168
169#ifdef CONFIG_VSX
170extern void flush_vsx_to_thread(struct task_struct *);
171#else
172static inline void flush_vsx_to_thread(struct task_struct *t)
173{
174}
175#endif
176
177#ifdef CONFIG_SPE
178extern void flush_spe_to_thread(struct task_struct *);
179#else
180static inline void flush_spe_to_thread(struct task_struct *t)
181{
182}
183#endif
184
185extern int call_rtas(const char *, int, int, unsigned long *, ...);
186extern void cacheable_memzero(void *p, unsigned int nb);
187extern void *cacheable_memcpy(void *, const void *, unsigned int);
188extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
189extern void bad_page_fault(struct pt_regs *, unsigned long, int);
190extern int die(const char *, struct pt_regs *, long);
191extern void _exception(int, struct pt_regs *, int, unsigned long);
192extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
193
194#ifdef CONFIG_BOOKE_WDT
195extern u32 booke_wdt_enabled;
196extern u32 booke_wdt_period;
197#endif /* CONFIG_BOOKE_WDT */
198
199struct device_node;
200extern void note_scsi_host(struct device_node *, void *);
201
202extern struct task_struct *__switch_to(struct task_struct *,
203 struct task_struct *);
204#define switch_to(prev, next, last) ((last) = __switch_to((prev), (next)))
205
206struct thread_struct;
207extern struct task_struct *_switch(struct thread_struct *prev,
208 struct thread_struct *next);
209
210extern unsigned int rtas_data;
211extern int mem_init_done; /* set on boot once kmalloc can be called */
212extern int init_bootmem_done; /* set on !NUMA once bootmem is available */
213extern unsigned long memory_limit;
214extern unsigned long klimit;
215
216extern void *alloc_maybe_bootmem(size_t size, gfp_t mask);
217extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask);
218
219extern int powersave_nap; /* set if nap mode can be used in idle loop */
220
221/*
222 * Atomic exchange
223 *
224 * Changes the memory location '*ptr' to be val and returns
225 * the previous value stored there.
226 */
227static __always_inline unsigned long
228__xchg_u32(volatile void *p, unsigned long val)
229{
230 unsigned long prev;
231
232 __asm__ __volatile__(
233 LWSYNC_ON_SMP
234"1: lwarx %0,0,%2 \n"
235 PPC405_ERR77(0,%2)
236" stwcx. %3,0,%2 \n\
237 bne- 1b"
238 ISYNC_ON_SMP
239 : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
240 : "r" (p), "r" (val)
241 : "cc", "memory");
242
243 return prev;
244}
245
246/*
247 * Atomic exchange
248 *
249 * Changes the memory location '*ptr' to be val and returns
250 * the previous value stored there.
251 */
252static __always_inline unsigned long
253__xchg_u32_local(volatile void *p, unsigned long val)
254{
255 unsigned long prev;
256
257 __asm__ __volatile__(
258"1: lwarx %0,0,%2 \n"
259 PPC405_ERR77(0,%2)
260" stwcx. %3,0,%2 \n\
261 bne- 1b"
262 : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
263 : "r" (p), "r" (val)
264 : "cc", "memory");
265
266 return prev;
267}
268
269#ifdef CONFIG_PPC64
270static __always_inline unsigned long
271__xchg_u64(volatile void *p, unsigned long val)
272{
273 unsigned long prev;
274
275 __asm__ __volatile__(
276 LWSYNC_ON_SMP
277"1: ldarx %0,0,%2 \n"
278 PPC405_ERR77(0,%2)
279" stdcx. %3,0,%2 \n\
280 bne- 1b"
281 ISYNC_ON_SMP
282 : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
283 : "r" (p), "r" (val)
284 : "cc", "memory");
285
286 return prev;
287}
288
289static __always_inline unsigned long
290__xchg_u64_local(volatile void *p, unsigned long val)
291{
292 unsigned long prev;
293
294 __asm__ __volatile__(
295"1: ldarx %0,0,%2 \n"
296 PPC405_ERR77(0,%2)
297" stdcx. %3,0,%2 \n\
298 bne- 1b"
299 : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
300 : "r" (p), "r" (val)
301 : "cc", "memory");
302
303 return prev;
304}
305#endif
306
307/*
308 * This function doesn't exist, so you'll get a linker error
309 * if something tries to do an invalid xchg().
310 */
311extern void __xchg_called_with_bad_pointer(void);
312
313static __always_inline unsigned long
314__xchg(volatile void *ptr, unsigned long x, unsigned int size)
315{
316 switch (size) {
317 case 4:
318 return __xchg_u32(ptr, x);
319#ifdef CONFIG_PPC64
320 case 8:
321 return __xchg_u64(ptr, x);
322#endif
323 }
324 __xchg_called_with_bad_pointer();
325 return x;
326}
327
328static __always_inline unsigned long
329__xchg_local(volatile void *ptr, unsigned long x, unsigned int size)
330{
331 switch (size) {
332 case 4:
333 return __xchg_u32_local(ptr, x);
334#ifdef CONFIG_PPC64
335 case 8:
336 return __xchg_u64_local(ptr, x);
337#endif
338 }
339 __xchg_called_with_bad_pointer();
340 return x;
341}
342#define xchg(ptr,x) \
343 ({ \
344 __typeof__(*(ptr)) _x_ = (x); \
345 (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
346 })
347
348#define xchg_local(ptr,x) \
349 ({ \
350 __typeof__(*(ptr)) _x_ = (x); \
351 (__typeof__(*(ptr))) __xchg_local((ptr), \
352 (unsigned long)_x_, sizeof(*(ptr))); \
353 })
354
355/*
356 * Compare and exchange - if *p == old, set it to new,
357 * and return the old value of *p.
358 */
359#define __HAVE_ARCH_CMPXCHG 1
360
361static __always_inline unsigned long
362__cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
363{
364 unsigned int prev;
365
366 __asm__ __volatile__ (
367 LWSYNC_ON_SMP
368"1: lwarx %0,0,%2 # __cmpxchg_u32\n\
369 cmpw 0,%0,%3\n\
370 bne- 2f\n"
371 PPC405_ERR77(0,%2)
372" stwcx. %4,0,%2\n\
373 bne- 1b"
374 ISYNC_ON_SMP
375 "\n\
3762:"
377 : "=&r" (prev), "+m" (*p)
378 : "r" (p), "r" (old), "r" (new)
379 : "cc", "memory");
380
381 return prev;
382}
383
384static __always_inline unsigned long
385__cmpxchg_u32_local(volatile unsigned int *p, unsigned long old,
386 unsigned long new)
387{
388 unsigned int prev;
389
390 __asm__ __volatile__ (
391"1: lwarx %0,0,%2 # __cmpxchg_u32\n\
392 cmpw 0,%0,%3\n\
393 bne- 2f\n"
394 PPC405_ERR77(0,%2)
395" stwcx. %4,0,%2\n\
396 bne- 1b"
397 "\n\
3982:"
399 : "=&r" (prev), "+m" (*p)
400 : "r" (p), "r" (old), "r" (new)
401 : "cc", "memory");
402
403 return prev;
404}
405
406#ifdef CONFIG_PPC64
407static __always_inline unsigned long
408__cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new)
409{
410 unsigned long prev;
411
412 __asm__ __volatile__ (
413 LWSYNC_ON_SMP
414"1: ldarx %0,0,%2 # __cmpxchg_u64\n\
415 cmpd 0,%0,%3\n\
416 bne- 2f\n\
417 stdcx. %4,0,%2\n\
418 bne- 1b"
419 ISYNC_ON_SMP
420 "\n\
4212:"
422 : "=&r" (prev), "+m" (*p)
423 : "r" (p), "r" (old), "r" (new)
424 : "cc", "memory");
425
426 return prev;
427}
428
429static __always_inline unsigned long
430__cmpxchg_u64_local(volatile unsigned long *p, unsigned long old,
431 unsigned long new)
432{
433 unsigned long prev;
434
435 __asm__ __volatile__ (
436"1: ldarx %0,0,%2 # __cmpxchg_u64\n\
437 cmpd 0,%0,%3\n\
438 bne- 2f\n\
439 stdcx. %4,0,%2\n\
440 bne- 1b"
441 "\n\
4422:"
443 : "=&r" (prev), "+m" (*p)
444 : "r" (p), "r" (old), "r" (new)
445 : "cc", "memory");
446
447 return prev;
448}
449#endif
450
451/* This function doesn't exist, so you'll get a linker error
452 if something tries to do an invalid cmpxchg(). */
453extern void __cmpxchg_called_with_bad_pointer(void);
454
455static __always_inline unsigned long
456__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
457 unsigned int size)
458{
459 switch (size) {
460 case 4:
461 return __cmpxchg_u32(ptr, old, new);
462#ifdef CONFIG_PPC64
463 case 8:
464 return __cmpxchg_u64(ptr, old, new);
465#endif
466 }
467 __cmpxchg_called_with_bad_pointer();
468 return old;
469}
470
471static __always_inline unsigned long
472__cmpxchg_local(volatile void *ptr, unsigned long old, unsigned long new,
473 unsigned int size)
474{
475 switch (size) {
476 case 4:
477 return __cmpxchg_u32_local(ptr, old, new);
478#ifdef CONFIG_PPC64
479 case 8:
480 return __cmpxchg_u64_local(ptr, old, new);
481#endif
482 }
483 __cmpxchg_called_with_bad_pointer();
484 return old;
485}
486
487#define cmpxchg(ptr, o, n) \
488 ({ \
489 __typeof__(*(ptr)) _o_ = (o); \
490 __typeof__(*(ptr)) _n_ = (n); \
491 (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
492 (unsigned long)_n_, sizeof(*(ptr))); \
493 })
494
495
496#define cmpxchg_local(ptr, o, n) \
497 ({ \
498 __typeof__(*(ptr)) _o_ = (o); \
499 __typeof__(*(ptr)) _n_ = (n); \
500 (__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_, \
501 (unsigned long)_n_, sizeof(*(ptr))); \
502 })
503
504#ifdef CONFIG_PPC64
505/*
506 * We handle most unaligned accesses in hardware. On the other hand
507 * unaligned DMA can be very expensive on some ppc64 IO chips (it does
508 * powers of 2 writes until it reaches sufficient alignment).
509 *
510 * Based on this we disable the IP header alignment in network drivers.
511 * We also modify NET_SKB_PAD to be a cacheline in size, thus maintaining
512 * cacheline alignment of buffers.
513 */
514#define NET_IP_ALIGN 0
515#define NET_SKB_PAD L1_CACHE_BYTES
516
517#define cmpxchg64(ptr, o, n) \
518 ({ \
519 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
520 cmpxchg((ptr), (o), (n)); \
521 })
522#define cmpxchg64_local(ptr, o, n) \
523 ({ \
524 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
525 cmpxchg_local((ptr), (o), (n)); \
526 })
527#else
528#include <asm-generic/cmpxchg-local.h>
529#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
530#endif
531
532#define arch_align_stack(x) (x)
533
534/* Used in very early kernel initialization. */
535extern unsigned long reloc_offset(void);
536extern unsigned long add_reloc_offset(unsigned long);
537extern void reloc_got2(unsigned long);
538
539#define PTRRELOC(x) ((typeof(x)) add_reloc_offset((unsigned long)(x)))
540
541#ifdef CONFIG_VIRT_CPU_ACCOUNTING
542extern void account_system_vtime(struct task_struct *);
543#endif
544
545extern struct dentry *powerpc_debugfs_root;
546
547#endif /* __KERNEL__ */
548#endif /* _ASM_POWERPC_SYSTEM_H */
diff --git a/include/asm-powerpc/tce.h b/include/asm-powerpc/tce.h
deleted file mode 100644
index f663634cccc..00000000000
--- a/include/asm-powerpc/tce.h
+++ /dev/null
@@ -1,50 +0,0 @@
1/*
2 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
3 * Rewrite, cleanup:
4 * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef _ASM_POWERPC_TCE_H
22#define _ASM_POWERPC_TCE_H
23#ifdef __KERNEL__
24
25#include <asm/iommu.h>
26
27/*
28 * Tces come in two formats, one for the virtual bus and a different
29 * format for PCI
30 */
31#define TCE_VB 0
32#define TCE_PCI 1
33
34/* TCE page size is 4096 bytes (1 << 12) */
35
36#define TCE_SHIFT 12
37#define TCE_PAGE_SIZE (1 << TCE_SHIFT)
38
39#define TCE_ENTRY_SIZE 8 /* each TCE is 64 bits */
40
41#define TCE_RPN_MASK 0xfffffffffful /* 40-bit RPN (4K pages) */
42#define TCE_RPN_SHIFT 12
43#define TCE_VALID 0x800 /* TCE valid */
44#define TCE_ALLIO 0x400 /* TCE valid for all lpars */
45#define TCE_PCI_WRITE 0x2 /* write from PCI allowed */
46#define TCE_PCI_READ 0x1 /* read from PCI allowed */
47#define TCE_VB_WRITE 0x1 /* write from VB allowed */
48
49#endif /* __KERNEL__ */
50#endif /* _ASM_POWERPC_TCE_H */
diff --git a/include/asm-powerpc/termbits.h b/include/asm-powerpc/termbits.h
deleted file mode 100644
index 6698188ca55..00000000000
--- a/include/asm-powerpc/termbits.h
+++ /dev/null
@@ -1,209 +0,0 @@
1#ifndef _ASM_POWERPC_TERMBITS_H
2#define _ASM_POWERPC_TERMBITS_H
3
4/*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10
11typedef unsigned char cc_t;
12typedef unsigned int speed_t;
13typedef unsigned int tcflag_t;
14
15/*
16 * termios type and macro definitions. Be careful about adding stuff
17 * to this file since it's used in GNU libc and there are strict rules
18 * concerning namespace pollution.
19 */
20
21#define NCCS 19
22struct termios {
23 tcflag_t c_iflag; /* input mode flags */
24 tcflag_t c_oflag; /* output mode flags */
25 tcflag_t c_cflag; /* control mode flags */
26 tcflag_t c_lflag; /* local mode flags */
27 cc_t c_cc[NCCS]; /* control characters */
28 cc_t c_line; /* line discipline (== c_cc[19]) */
29 speed_t c_ispeed; /* input speed */
30 speed_t c_ospeed; /* output speed */
31};
32
33/* For PowerPC the termios and ktermios are the same */
34
35struct ktermios {
36 tcflag_t c_iflag; /* input mode flags */
37 tcflag_t c_oflag; /* output mode flags */
38 tcflag_t c_cflag; /* control mode flags */
39 tcflag_t c_lflag; /* local mode flags */
40 cc_t c_cc[NCCS]; /* control characters */
41 cc_t c_line; /* line discipline (== c_cc[19]) */
42 speed_t c_ispeed; /* input speed */
43 speed_t c_ospeed; /* output speed */
44};
45
46/* c_cc characters */
47#define VINTR 0
48#define VQUIT 1
49#define VERASE 2
50#define VKILL 3
51#define VEOF 4
52#define VMIN 5
53#define VEOL 6
54#define VTIME 7
55#define VEOL2 8
56#define VSWTC 9
57#define VWERASE 10
58#define VREPRINT 11
59#define VSUSP 12
60#define VSTART 13
61#define VSTOP 14
62#define VLNEXT 15
63#define VDISCARD 16
64
65/* c_iflag bits */
66#define IGNBRK 0000001
67#define BRKINT 0000002
68#define IGNPAR 0000004
69#define PARMRK 0000010
70#define INPCK 0000020
71#define ISTRIP 0000040
72#define INLCR 0000100
73#define IGNCR 0000200
74#define ICRNL 0000400
75#define IXON 0001000
76#define IXOFF 0002000
77#define IXANY 0004000
78#define IUCLC 0010000
79#define IMAXBEL 0020000
80#define IUTF8 0040000
81
82/* c_oflag bits */
83#define OPOST 0000001
84#define ONLCR 0000002
85#define OLCUC 0000004
86
87#define OCRNL 0000010
88#define ONOCR 0000020
89#define ONLRET 0000040
90
91#define OFILL 00000100
92#define OFDEL 00000200
93#define NLDLY 00001400
94#define NL0 00000000
95#define NL1 00000400
96#define NL2 00001000
97#define NL3 00001400
98#define TABDLY 00006000
99#define TAB0 00000000
100#define TAB1 00002000
101#define TAB2 00004000
102#define TAB3 00006000
103#define XTABS 00006000 /* required by POSIX to == TAB3 */
104#define CRDLY 00030000
105#define CR0 00000000
106#define CR1 00010000
107#define CR2 00020000
108#define CR3 00030000
109#define FFDLY 00040000
110#define FF0 00000000
111#define FF1 00040000
112#define BSDLY 00100000
113#define BS0 00000000
114#define BS1 00100000
115#define VTDLY 00200000
116#define VT0 00000000
117#define VT1 00200000
118
119/* c_cflag bit meaning */
120#define CBAUD 0000377
121#define B0 0000000 /* hang up */
122#define B50 0000001
123#define B75 0000002
124#define B110 0000003
125#define B134 0000004
126#define B150 0000005
127#define B200 0000006
128#define B300 0000007
129#define B600 0000010
130#define B1200 0000011
131#define B1800 0000012
132#define B2400 0000013
133#define B4800 0000014
134#define B9600 0000015
135#define B19200 0000016
136#define B38400 0000017
137#define EXTA B19200
138#define EXTB B38400
139#define CBAUDEX 0000000
140#define B57600 00020
141#define B115200 00021
142#define B230400 00022
143#define B460800 00023
144#define B500000 00024
145#define B576000 00025
146#define B921600 00026
147#define B1000000 00027
148#define B1152000 00030
149#define B1500000 00031
150#define B2000000 00032
151#define B2500000 00033
152#define B3000000 00034
153#define B3500000 00035
154#define B4000000 00036
155#define BOTHER 00037
156
157#define CIBAUD 077600000
158#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
159
160#define CSIZE 00001400
161#define CS5 00000000
162#define CS6 00000400
163#define CS7 00001000
164#define CS8 00001400
165
166#define CSTOPB 00002000
167#define CREAD 00004000
168#define PARENB 00010000
169#define PARODD 00020000
170#define HUPCL 00040000
171
172#define CLOCAL 00100000
173#define CMSPAR 010000000000 /* mark or space (stick) parity */
174#define CRTSCTS 020000000000 /* flow control */
175
176/* c_lflag bits */
177#define ISIG 0x00000080
178#define ICANON 0x00000100
179#define XCASE 0x00004000
180#define ECHO 0x00000008
181#define ECHOE 0x00000002
182#define ECHOK 0x00000004
183#define ECHONL 0x00000010
184#define NOFLSH 0x80000000
185#define TOSTOP 0x00400000
186#define ECHOCTL 0x00000040
187#define ECHOPRT 0x00000020
188#define ECHOKE 0x00000001
189#define FLUSHO 0x00800000
190#define PENDIN 0x20000000
191#define IEXTEN 0x00000400
192
193/* Values for the ACTION argument to `tcflow'. */
194#define TCOOFF 0
195#define TCOON 1
196#define TCIOFF 2
197#define TCION 3
198
199/* Values for the QUEUE_SELECTOR argument to `tcflush'. */
200#define TCIFLUSH 0
201#define TCOFLUSH 1
202#define TCIOFLUSH 2
203
204/* Values for the OPTIONAL_ACTIONS argument to `tcsetattr'. */
205#define TCSANOW 0
206#define TCSADRAIN 1
207#define TCSAFLUSH 2
208
209#endif /* _ASM_POWERPC_TERMBITS_H */
diff --git a/include/asm-powerpc/termios.h b/include/asm-powerpc/termios.h
deleted file mode 100644
index 2c14fea07c8..00000000000
--- a/include/asm-powerpc/termios.h
+++ /dev/null
@@ -1,85 +0,0 @@
1#ifndef _ASM_POWERPC_TERMIOS_H
2#define _ASM_POWERPC_TERMIOS_H
3
4/*
5 * Liberally adapted from alpha/termios.h. In particular, the c_cc[]
6 * fields have been reordered so that termio & termios share the
7 * common subset in the same order (for brain dead programs that don't
8 * know or care about the differences).
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15
16#include <asm/ioctls.h>
17#include <asm/termbits.h>
18
19struct sgttyb {
20 char sg_ispeed;
21 char sg_ospeed;
22 char sg_erase;
23 char sg_kill;
24 short sg_flags;
25};
26
27struct tchars {
28 char t_intrc;
29 char t_quitc;
30 char t_startc;
31 char t_stopc;
32 char t_eofc;
33 char t_brkc;
34};
35
36struct ltchars {
37 char t_suspc;
38 char t_dsuspc;
39 char t_rprntc;
40 char t_flushc;
41 char t_werasc;
42 char t_lnextc;
43};
44
45struct winsize {
46 unsigned short ws_row;
47 unsigned short ws_col;
48 unsigned short ws_xpixel;
49 unsigned short ws_ypixel;
50};
51
52#define NCC 10
53struct termio {
54 unsigned short c_iflag; /* input mode flags */
55 unsigned short c_oflag; /* output mode flags */
56 unsigned short c_cflag; /* control mode flags */
57 unsigned short c_lflag; /* local mode flags */
58 unsigned char c_line; /* line discipline */
59 unsigned char c_cc[NCC]; /* control characters */
60};
61
62/* c_cc characters */
63#define _VINTR 0
64#define _VQUIT 1
65#define _VERASE 2
66#define _VKILL 3
67#define _VEOF 4
68#define _VMIN 5
69#define _VEOL 6
70#define _VTIME 7
71#define _VEOL2 8
72#define _VSWTC 9
73
74#ifdef __KERNEL__
75/* ^C ^\ del ^U ^D 1 0 0 0 0 ^W ^R ^Z ^Q ^S ^V ^U */
76#define INIT_C_CC "\003\034\177\025\004\001\000\000\000\000\027\022\032\021\023\026\025"
77#endif
78
79#ifdef __KERNEL__
80
81#include <asm-generic/termios.h>
82
83#endif /* __KERNEL__ */
84
85#endif /* _ASM_POWERPC_TERMIOS_H */
diff --git a/include/asm-powerpc/thread_info.h b/include/asm-powerpc/thread_info.h
deleted file mode 100644
index a9db562df69..00000000000
--- a/include/asm-powerpc/thread_info.h
+++ /dev/null
@@ -1,158 +0,0 @@
1/* thread_info.h: PowerPC low-level thread information
2 * adapted from the i386 version by Paul Mackerras
3 *
4 * Copyright (C) 2002 David Howells (dhowells@redhat.com)
5 * - Incorporating suggestions made by Linus Torvalds and Dave Miller
6 */
7
8#ifndef _ASM_POWERPC_THREAD_INFO_H
9#define _ASM_POWERPC_THREAD_INFO_H
10
11#ifdef __KERNEL__
12
13/* We have 8k stacks on ppc32 and 16k on ppc64 */
14
15#ifdef CONFIG_PPC64
16#define THREAD_SHIFT 14
17#else
18#define THREAD_SHIFT 13
19#endif
20
21#define THREAD_SIZE (1 << THREAD_SHIFT)
22
23#ifndef __ASSEMBLY__
24#include <linux/cache.h>
25#include <asm/processor.h>
26#include <asm/page.h>
27#include <linux/stringify.h>
28
29/*
30 * low level task data.
31 */
32struct thread_info {
33 struct task_struct *task; /* main task structure */
34 struct exec_domain *exec_domain; /* execution domain */
35 int cpu; /* cpu we're on */
36 int preempt_count; /* 0 => preemptable,
37 <0 => BUG */
38 struct restart_block restart_block;
39 unsigned long local_flags; /* private flags for thread */
40
41 /* low level flags - has atomic operations done on it */
42 unsigned long flags ____cacheline_aligned_in_smp;
43};
44
45/*
46 * macros/functions for gaining access to the thread information structure
47 *
48 * preempt_count needs to be 1 initially, until the scheduler is functional.
49 */
50#define INIT_THREAD_INFO(tsk) \
51{ \
52 .task = &tsk, \
53 .exec_domain = &default_exec_domain, \
54 .cpu = 0, \
55 .preempt_count = 1, \
56 .restart_block = { \
57 .fn = do_no_restart_syscall, \
58 }, \
59 .flags = 0, \
60}
61
62#define init_thread_info (init_thread_union.thread_info)
63#define init_stack (init_thread_union.stack)
64
65/* thread information allocation */
66
67#if THREAD_SHIFT >= PAGE_SHIFT
68
69#define THREAD_SIZE_ORDER (THREAD_SHIFT - PAGE_SHIFT)
70
71#else /* THREAD_SHIFT < PAGE_SHIFT */
72
73#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
74
75extern struct thread_info *alloc_thread_info(struct task_struct *tsk);
76extern void free_thread_info(struct thread_info *ti);
77
78#endif /* THREAD_SHIFT < PAGE_SHIFT */
79
80/* how to get the thread information struct from C */
81static inline struct thread_info *current_thread_info(void)
82{
83 register unsigned long sp asm("r1");
84
85 /* gcc4, at least, is smart enough to turn this into a single
86 * rlwinm for ppc32 and clrrdi for ppc64 */
87 return (struct thread_info *)(sp & ~(THREAD_SIZE-1));
88}
89
90#endif /* __ASSEMBLY__ */
91
92#define PREEMPT_ACTIVE 0x10000000
93
94/*
95 * thread information flag bit numbers
96 */
97#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
98#define TIF_SIGPENDING 1 /* signal pending */
99#define TIF_NEED_RESCHED 2 /* rescheduling necessary */
100#define TIF_POLLING_NRFLAG 3 /* true if poll_idle() is polling
101 TIF_NEED_RESCHED */
102#define TIF_32BIT 4 /* 32 bit binary */
103#define TIF_PERFMON_WORK 5 /* work for pfm_handle_work() */
104#define TIF_PERFMON_CTXSW 6 /* perfmon needs ctxsw calls */
105#define TIF_SYSCALL_AUDIT 7 /* syscall auditing active */
106#define TIF_SINGLESTEP 8 /* singlestepping active */
107#define TIF_MEMDIE 9
108#define TIF_SECCOMP 10 /* secure computing */
109#define TIF_RESTOREALL 11 /* Restore all regs (implies NOERROR) */
110#define TIF_NOERROR 12 /* Force successful syscall return */
111#define TIF_FREEZE 14 /* Freezing for suspend */
112#define TIF_RUNLATCH 15 /* Is the runlatch enabled? */
113#define TIF_ABI_PENDING 16 /* 32/64 bit switch needed */
114
115/* as above, but as bit values */
116#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
117#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
118#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
119#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
120#define _TIF_32BIT (1<<TIF_32BIT)
121#define _TIF_PERFMON_WORK (1<<TIF_PERFMON_WORK)
122#define _TIF_PERFMON_CTXSW (1<<TIF_PERFMON_CTXSW)
123#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT)
124#define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP)
125#define _TIF_SECCOMP (1<<TIF_SECCOMP)
126#define _TIF_RESTOREALL (1<<TIF_RESTOREALL)
127#define _TIF_NOERROR (1<<TIF_NOERROR)
128#define _TIF_FREEZE (1<<TIF_FREEZE)
129#define _TIF_RUNLATCH (1<<TIF_RUNLATCH)
130#define _TIF_ABI_PENDING (1<<TIF_ABI_PENDING)
131#define _TIF_SYSCALL_T_OR_A (_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SECCOMP)
132
133#define _TIF_USER_WORK_MASK (_TIF_SIGPENDING | _TIF_NEED_RESCHED)
134#define _TIF_PERSYSCALL_MASK (_TIF_RESTOREALL|_TIF_NOERROR)
135
136/* Bits in local_flags */
137/* Don't move TLF_NAPPING without adjusting the code in entry_32.S */
138#define TLF_NAPPING 0 /* idle thread enabled NAP mode */
139#define TLF_SLEEPING 1 /* suspend code enabled SLEEP mode */
140#define TLF_RESTORE_SIGMASK 2 /* Restore signal mask in do_signal */
141
142#define _TLF_NAPPING (1 << TLF_NAPPING)
143#define _TLF_SLEEPING (1 << TLF_SLEEPING)
144#define _TLF_RESTORE_SIGMASK (1 << TLF_RESTORE_SIGMASK)
145
146#ifndef __ASSEMBLY__
147#define HAVE_SET_RESTORE_SIGMASK 1
148static inline void set_restore_sigmask(void)
149{
150 struct thread_info *ti = current_thread_info();
151 ti->local_flags |= _TLF_RESTORE_SIGMASK;
152 set_bit(TIF_SIGPENDING, &ti->flags);
153}
154#endif /* !__ASSEMBLY__ */
155
156#endif /* __KERNEL__ */
157
158#endif /* _ASM_POWERPC_THREAD_INFO_H */
diff --git a/include/asm-powerpc/time.h b/include/asm-powerpc/time.h
deleted file mode 100644
index febd581ec9b..00000000000
--- a/include/asm-powerpc/time.h
+++ /dev/null
@@ -1,255 +0,0 @@
1/*
2 * Common time prototypes and such for all ppc machines.
3 *
4 * Written by Cort Dougan (cort@cs.nmt.edu) to merge
5 * Paul Mackerras' version and mine for PReP and Pmac.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#ifndef __POWERPC_TIME_H
14#define __POWERPC_TIME_H
15
16#ifdef __KERNEL__
17#include <linux/types.h>
18#include <linux/percpu.h>
19
20#include <asm/processor.h>
21#ifdef CONFIG_PPC_ISERIES
22#include <asm/paca.h>
23#include <asm/firmware.h>
24#include <asm/iseries/hv_call.h>
25#endif
26
27/* time.c */
28extern unsigned long tb_ticks_per_jiffy;
29extern unsigned long tb_ticks_per_usec;
30extern unsigned long tb_ticks_per_sec;
31extern u64 tb_to_xs;
32extern unsigned tb_to_us;
33
34struct rtc_time;
35extern void to_tm(int tim, struct rtc_time * tm);
36extern void GregorianDay(struct rtc_time *tm);
37extern time_t last_rtc_update;
38
39extern void generic_calibrate_decr(void);
40extern void wakeup_decrementer(void);
41extern void snapshot_timebase(void);
42
43extern void set_dec_cpu6(unsigned int val);
44
45/* Some sane defaults: 125 MHz timebase, 1GHz processor */
46extern unsigned long ppc_proc_freq;
47#define DEFAULT_PROC_FREQ (DEFAULT_TB_FREQ * 8)
48extern unsigned long ppc_tb_freq;
49#define DEFAULT_TB_FREQ 125000000UL
50
51/*
52 * By putting all of this stuff into a single struct we
53 * reduce the number of cache lines touched by do_gettimeofday.
54 * Both by collecting all of the data in one cache line and
55 * by touching only one TOC entry on ppc64.
56 */
57struct gettimeofday_vars {
58 u64 tb_to_xs;
59 u64 stamp_xsec;
60 u64 tb_orig_stamp;
61};
62
63struct gettimeofday_struct {
64 unsigned long tb_ticks_per_sec;
65 struct gettimeofday_vars vars[2];
66 struct gettimeofday_vars * volatile varp;
67 unsigned var_idx;
68 unsigned tb_to_us;
69};
70
71struct div_result {
72 u64 result_high;
73 u64 result_low;
74};
75
76/* Accessor functions for the timebase (RTC on 601) registers. */
77/* If one day CONFIG_POWER is added just define __USE_RTC as 1 */
78#ifdef CONFIG_6xx
79#define __USE_RTC() (!cpu_has_feature(CPU_FTR_USE_TB))
80#else
81#define __USE_RTC() 0
82#endif
83
84#ifdef CONFIG_PPC64
85
86/* For compatibility, get_tbl() is defined as get_tb() on ppc64 */
87#define get_tbl get_tb
88
89#else
90
91static inline unsigned long get_tbl(void)
92{
93#if defined(CONFIG_403GCX)
94 unsigned long tbl;
95 asm volatile("mfspr %0, 0x3dd" : "=r" (tbl));
96 return tbl;
97#else
98 return mftbl();
99#endif
100}
101
102static inline unsigned int get_tbu(void)
103{
104#ifdef CONFIG_403GCX
105 unsigned int tbu;
106 asm volatile("mfspr %0, 0x3dc" : "=r" (tbu));
107 return tbu;
108#else
109 return mftbu();
110#endif
111}
112#endif /* !CONFIG_PPC64 */
113
114static inline unsigned int get_rtcl(void)
115{
116 unsigned int rtcl;
117
118 asm volatile("mfrtcl %0" : "=r" (rtcl));
119 return rtcl;
120}
121
122static inline u64 get_rtc(void)
123{
124 unsigned int hi, lo, hi2;
125
126 do {
127 asm volatile("mfrtcu %0; mfrtcl %1; mfrtcu %2"
128 : "=r" (hi), "=r" (lo), "=r" (hi2));
129 } while (hi2 != hi);
130 return (u64)hi * 1000000000 + lo;
131}
132
133#ifdef CONFIG_PPC64
134static inline u64 get_tb(void)
135{
136 return mftb();
137}
138#else /* CONFIG_PPC64 */
139static inline u64 get_tb(void)
140{
141 unsigned int tbhi, tblo, tbhi2;
142
143 do {
144 tbhi = get_tbu();
145 tblo = get_tbl();
146 tbhi2 = get_tbu();
147 } while (tbhi != tbhi2);
148
149 return ((u64)tbhi << 32) | tblo;
150}
151#endif /* !CONFIG_PPC64 */
152
153static inline u64 get_tb_or_rtc(void)
154{
155 return __USE_RTC() ? get_rtc() : get_tb();
156}
157
158static inline void set_tb(unsigned int upper, unsigned int lower)
159{
160 mtspr(SPRN_TBWL, 0);
161 mtspr(SPRN_TBWU, upper);
162 mtspr(SPRN_TBWL, lower);
163}
164
165/* Accessor functions for the decrementer register.
166 * The 4xx doesn't even have a decrementer. I tried to use the
167 * generic timer interrupt code, which seems OK, with the 4xx PIT
168 * in auto-reload mode. The problem is PIT stops counting when it
169 * hits zero. If it would wrap, we could use it just like a decrementer.
170 */
171static inline unsigned int get_dec(void)
172{
173#if defined(CONFIG_40x)
174 return (mfspr(SPRN_PIT));
175#else
176 return (mfspr(SPRN_DEC));
177#endif
178}
179
180/*
181 * Note: Book E and 4xx processors differ from other PowerPC processors
182 * in when the decrementer generates its interrupt: on the 1 to 0
183 * transition for Book E/4xx, but on the 0 to -1 transition for others.
184 */
185static inline void set_dec(int val)
186{
187#if defined(CONFIG_40x)
188 mtspr(SPRN_PIT, val);
189#elif defined(CONFIG_8xx_CPU6)
190 set_dec_cpu6(val - 1);
191#else
192#ifndef CONFIG_BOOKE
193 --val;
194#endif
195#ifdef CONFIG_PPC_ISERIES
196 if (firmware_has_feature(FW_FEATURE_ISERIES) &&
197 get_lppaca()->shared_proc) {
198 get_lppaca()->virtual_decr = val;
199 if (get_dec() > val)
200 HvCall_setVirtualDecr();
201 return;
202 }
203#endif
204 mtspr(SPRN_DEC, val);
205#endif /* not 40x or 8xx_CPU6 */
206}
207
208static inline unsigned long tb_ticks_since(unsigned long tstamp)
209{
210 if (__USE_RTC()) {
211 int delta = get_rtcl() - (unsigned int) tstamp;
212 return delta < 0 ? delta + 1000000000 : delta;
213 }
214 return get_tbl() - tstamp;
215}
216
217#define mulhwu(x,y) \
218({unsigned z; asm ("mulhwu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;})
219
220#ifdef CONFIG_PPC64
221#define mulhdu(x,y) \
222({unsigned long z; asm ("mulhdu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;})
223#else
224extern u64 mulhdu(u64, u64);
225#endif
226
227extern void smp_space_timers(unsigned int);
228
229extern unsigned mulhwu_scale_factor(unsigned, unsigned);
230extern void div128_by_32(u64 dividend_high, u64 dividend_low,
231 unsigned divisor, struct div_result *dr);
232
233/* Used to store Processor Utilization register (purr) values */
234
235struct cpu_usage {
236 u64 current_tb; /* Holds the current purr register values */
237};
238
239DECLARE_PER_CPU(struct cpu_usage, cpu_usage_array);
240
241#if defined(CONFIG_VIRT_CPU_ACCOUNTING)
242extern void calculate_steal_time(void);
243extern void snapshot_timebases(void);
244#define account_process_vtime(tsk) account_process_tick(tsk, 0)
245#else
246#define calculate_steal_time() do { } while (0)
247#define snapshot_timebases() do { } while (0)
248#define account_process_vtime(tsk) do { } while (0)
249#endif
250
251extern void secondary_cpu_time_init(void);
252extern void iSeries_time_init_early(void);
253
254#endif /* __KERNEL__ */
255#endif /* __POWERPC_TIME_H */
diff --git a/include/asm-powerpc/timex.h b/include/asm-powerpc/timex.h
deleted file mode 100644
index c55e14f7ef4..00000000000
--- a/include/asm-powerpc/timex.h
+++ /dev/null
@@ -1,50 +0,0 @@
1#ifndef _ASM_POWERPC_TIMEX_H
2#define _ASM_POWERPC_TIMEX_H
3
4#ifdef __KERNEL__
5
6/*
7 * PowerPC architecture timex specifications
8 */
9
10#include <asm/cputable.h>
11#include <asm/reg.h>
12
13#define CLOCK_TICK_RATE 1024000 /* Underlying HZ */
14
15typedef unsigned long cycles_t;
16
17static inline cycles_t get_cycles(void)
18{
19#ifdef __powerpc64__
20 return mftb();
21#else
22 cycles_t ret;
23
24 /*
25 * For the "cycle" counter we use the timebase lower half.
26 * Currently only used on SMP.
27 */
28
29 ret = 0;
30
31 __asm__ __volatile__(
32 "97: mftb %0\n"
33 "99:\n"
34 ".section __ftr_fixup,\"a\"\n"
35 ".align 2\n"
36 "98:\n"
37 " .long %1\n"
38 " .long 0\n"
39 " .long 97b-98b\n"
40 " .long 99b-98b\n"
41 " .long 0\n"
42 " .long 0\n"
43 ".previous"
44 : "=r" (ret) : "i" (CPU_FTR_601));
45 return ret;
46#endif
47}
48
49#endif /* __KERNEL__ */
50#endif /* _ASM_POWERPC_TIMEX_H */
diff --git a/include/asm-powerpc/tlb.h b/include/asm-powerpc/tlb.h
deleted file mode 100644
index e20ff7541f3..00000000000
--- a/include/asm-powerpc/tlb.h
+++ /dev/null
@@ -1,81 +0,0 @@
1/*
2 * TLB shootdown specifics for powerpc
3 *
4 * Copyright (C) 2002 Anton Blanchard, IBM Corp.
5 * Copyright (C) 2002 Paul Mackerras, IBM Corp.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12#ifndef _ASM_POWERPC_TLB_H
13#define _ASM_POWERPC_TLB_H
14#ifdef __KERNEL__
15
16#ifndef __powerpc64__
17#include <asm/pgtable.h>
18#endif
19#include <asm/pgalloc.h>
20#include <asm/tlbflush.h>
21#ifndef __powerpc64__
22#include <asm/page.h>
23#include <asm/mmu.h>
24#endif
25
26#include <linux/pagemap.h>
27
28struct mmu_gather;
29
30#define tlb_start_vma(tlb, vma) do { } while (0)
31#define tlb_end_vma(tlb, vma) do { } while (0)
32
33#if !defined(CONFIG_PPC_STD_MMU)
34
35#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
36
37#elif defined(__powerpc64__)
38
39extern void pte_free_finish(void);
40
41static inline void tlb_flush(struct mmu_gather *tlb)
42{
43 struct ppc64_tlb_batch *tlbbatch = &__get_cpu_var(ppc64_tlb_batch);
44
45 /* If there's a TLB batch pending, then we must flush it because the
46 * pages are going to be freed and we really don't want to have a CPU
47 * access a freed page because it has a stale TLB
48 */
49 if (tlbbatch->index)
50 __flush_tlb_pending(tlbbatch);
51
52 pte_free_finish();
53}
54
55#else
56
57extern void tlb_flush(struct mmu_gather *tlb);
58
59#endif
60
61/* Get the generic bits... */
62#include <asm-generic/tlb.h>
63
64#if !defined(CONFIG_PPC_STD_MMU) || defined(__powerpc64__)
65
66#define __tlb_remove_tlb_entry(tlb, pte, address) do { } while (0)
67
68#else
69extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep,
70 unsigned long address);
71
72static inline void __tlb_remove_tlb_entry(struct mmu_gather *tlb, pte_t *ptep,
73 unsigned long address)
74{
75 if (pte_val(*ptep) & _PAGE_HASHPTE)
76 flush_hash_entry(tlb->mm, ptep, address);
77}
78
79#endif
80#endif /* __KERNEL__ */
81#endif /* __ASM_POWERPC_TLB_H */
diff --git a/include/asm-powerpc/tlbflush.h b/include/asm-powerpc/tlbflush.h
deleted file mode 100644
index 361cd5c7a32..00000000000
--- a/include/asm-powerpc/tlbflush.h
+++ /dev/null
@@ -1,166 +0,0 @@
1#ifndef _ASM_POWERPC_TLBFLUSH_H
2#define _ASM_POWERPC_TLBFLUSH_H
3
4/*
5 * TLB flushing:
6 *
7 * - flush_tlb_mm(mm) flushes the specified mm context TLB's
8 * - flush_tlb_page(vma, vmaddr) flushes one page
9 * - flush_tlb_page_nohash(vma, vmaddr) flushes one page if SW loaded TLB
10 * - flush_tlb_range(vma, start, end) flushes a range of pages
11 * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
17 */
18#ifdef __KERNEL__
19
20#if defined(CONFIG_4xx) || defined(CONFIG_8xx) || defined(CONFIG_FSL_BOOKE)
21/*
22 * TLB flushing for software loaded TLB chips
23 *
24 * TODO: (CONFIG_FSL_BOOKE) determine if flush_tlb_range &
25 * flush_tlb_kernel_range are best implemented as tlbia vs
26 * specific tlbie's
27 */
28
29#include <linux/mm.h>
30
31extern void _tlbie(unsigned long address, unsigned int pid);
32
33#if defined(CONFIG_40x) || defined(CONFIG_8xx)
34#define _tlbia() asm volatile ("tlbia; sync" : : : "memory")
35#else /* CONFIG_44x || CONFIG_FSL_BOOKE */
36extern void _tlbia(void);
37#endif
38
39static inline void flush_tlb_mm(struct mm_struct *mm)
40{
41 _tlbia();
42}
43
44static inline void flush_tlb_page(struct vm_area_struct *vma,
45 unsigned long vmaddr)
46{
47 _tlbie(vmaddr, vma ? vma->vm_mm->context.id : 0);
48}
49
50static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,
51 unsigned long vmaddr)
52{
53 _tlbie(vmaddr, vma ? vma->vm_mm->context.id : 0);
54}
55
56static inline void flush_tlb_range(struct vm_area_struct *vma,
57 unsigned long start, unsigned long end)
58{
59 _tlbia();
60}
61
62static inline void flush_tlb_kernel_range(unsigned long start,
63 unsigned long end)
64{
65 _tlbia();
66}
67
68#elif defined(CONFIG_PPC32)
69/*
70 * TLB flushing for "classic" hash-MMMU 32-bit CPUs, 6xx, 7xx, 7xxx
71 */
72extern void _tlbie(unsigned long address);
73extern void _tlbia(void);
74
75extern void flush_tlb_mm(struct mm_struct *mm);
76extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
77extern void flush_tlb_page_nohash(struct vm_area_struct *vma, unsigned long addr);
78extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
79 unsigned long end);
80extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
81
82#else
83/*
84 * TLB flushing for 64-bit has-MMU CPUs
85 */
86
87#include <linux/percpu.h>
88#include <asm/page.h>
89
90#define PPC64_TLB_BATCH_NR 192
91
92struct ppc64_tlb_batch {
93 int active;
94 unsigned long index;
95 struct mm_struct *mm;
96 real_pte_t pte[PPC64_TLB_BATCH_NR];
97 unsigned long vaddr[PPC64_TLB_BATCH_NR];
98 unsigned int psize;
99 int ssize;
100};
101DECLARE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
102
103extern void __flush_tlb_pending(struct ppc64_tlb_batch *batch);
104
105extern void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
106 pte_t *ptep, unsigned long pte, int huge);
107
108#define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
109
110static inline void arch_enter_lazy_mmu_mode(void)
111{
112 struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
113
114 batch->active = 1;
115}
116
117static inline void arch_leave_lazy_mmu_mode(void)
118{
119 struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
120
121 if (batch->index)
122 __flush_tlb_pending(batch);
123 batch->active = 0;
124}
125
126#define arch_flush_lazy_mmu_mode() do {} while (0)
127
128
129extern void flush_hash_page(unsigned long va, real_pte_t pte, int psize,
130 int ssize, int local);
131extern void flush_hash_range(unsigned long number, int local);
132
133
134static inline void flush_tlb_mm(struct mm_struct *mm)
135{
136}
137
138static inline void flush_tlb_page(struct vm_area_struct *vma,
139 unsigned long vmaddr)
140{
141}
142
143static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,
144 unsigned long vmaddr)
145{
146}
147
148static inline void flush_tlb_range(struct vm_area_struct *vma,
149 unsigned long start, unsigned long end)
150{
151}
152
153static inline void flush_tlb_kernel_range(unsigned long start,
154 unsigned long end)
155{
156}
157
158/* Private function for use by PCI IO mapping code */
159extern void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
160 unsigned long end);
161
162
163#endif
164
165#endif /*__KERNEL__ */
166#endif /* _ASM_POWERPC_TLBFLUSH_H */
diff --git a/include/asm-powerpc/topology.h b/include/asm-powerpc/topology.h
deleted file mode 100644
index 100c6fbfc58..00000000000
--- a/include/asm-powerpc/topology.h
+++ /dev/null
@@ -1,115 +0,0 @@
1#ifndef _ASM_POWERPC_TOPOLOGY_H
2#define _ASM_POWERPC_TOPOLOGY_H
3#ifdef __KERNEL__
4
5
6struct sys_device;
7struct device_node;
8
9#ifdef CONFIG_NUMA
10
11#include <asm/mmzone.h>
12
13static inline int cpu_to_node(int cpu)
14{
15 return numa_cpu_lookup_table[cpu];
16}
17
18#define parent_node(node) (node)
19
20static inline cpumask_t node_to_cpumask(int node)
21{
22 return numa_cpumask_lookup_table[node];
23}
24
25static inline int node_to_first_cpu(int node)
26{
27 cpumask_t tmp;
28 tmp = node_to_cpumask(node);
29 return first_cpu(tmp);
30}
31
32int of_node_to_nid(struct device_node *device);
33
34struct pci_bus;
35#ifdef CONFIG_PCI
36extern int pcibus_to_node(struct pci_bus *bus);
37#else
38static inline int pcibus_to_node(struct pci_bus *bus)
39{
40 return -1;
41}
42#endif
43
44#define pcibus_to_cpumask(bus) (pcibus_to_node(bus) == -1 ? \
45 CPU_MASK_ALL : \
46 node_to_cpumask(pcibus_to_node(bus)) \
47 )
48
49/* sched_domains SD_NODE_INIT for PPC64 machines */
50#define SD_NODE_INIT (struct sched_domain) { \
51 .span = CPU_MASK_NONE, \
52 .parent = NULL, \
53 .child = NULL, \
54 .groups = NULL, \
55 .min_interval = 8, \
56 .max_interval = 32, \
57 .busy_factor = 32, \
58 .imbalance_pct = 125, \
59 .cache_nice_tries = 1, \
60 .busy_idx = 3, \
61 .idle_idx = 1, \
62 .newidle_idx = 2, \
63 .wake_idx = 1, \
64 .flags = SD_LOAD_BALANCE \
65 | SD_BALANCE_EXEC \
66 | SD_BALANCE_NEWIDLE \
67 | SD_WAKE_IDLE \
68 | SD_SERIALIZE \
69 | SD_WAKE_BALANCE, \
70 .last_balance = jiffies, \
71 .balance_interval = 1, \
72 .nr_balance_failed = 0, \
73}
74
75extern void __init dump_numa_cpu_topology(void);
76
77extern int sysfs_add_device_to_node(struct sys_device *dev, int nid);
78extern void sysfs_remove_device_from_node(struct sys_device *dev, int nid);
79
80#else
81
82static inline int of_node_to_nid(struct device_node *device)
83{
84 return 0;
85}
86
87static inline void dump_numa_cpu_topology(void) {}
88
89static inline int sysfs_add_device_to_node(struct sys_device *dev, int nid)
90{
91 return 0;
92}
93
94static inline void sysfs_remove_device_from_node(struct sys_device *dev,
95 int nid)
96{
97}
98
99#endif /* CONFIG_NUMA */
100
101#include <asm-generic/topology.h>
102
103#ifdef CONFIG_SMP
104#include <asm/cputable.h>
105#define smt_capable() (cpu_has_feature(CPU_FTR_SMT))
106
107#ifdef CONFIG_PPC64
108#include <asm/smp.h>
109
110#define topology_thread_siblings(cpu) (per_cpu(cpu_sibling_map, cpu))
111#endif
112#endif
113
114#endif /* __KERNEL__ */
115#endif /* _ASM_POWERPC_TOPOLOGY_H */
diff --git a/include/asm-powerpc/tsi108.h b/include/asm-powerpc/tsi108.h
deleted file mode 100644
index f8b60793b7a..00000000000
--- a/include/asm-powerpc/tsi108.h
+++ /dev/null
@@ -1,121 +0,0 @@
1/*
2 * common routine and memory layout for Tundra TSI108(Grendel) host bridge
3 * memory controller.
4 *
5 * Author: Jacob Pan (jacob.pan@freescale.com)
6 * Alex Bounine (alexandreb@tundra.com)
7 *
8 * Copyright 2004-2006 Freescale Semiconductor, Inc.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15
16#ifndef __PPC_KERNEL_TSI108_H
17#define __PPC_KERNEL_TSI108_H
18
19#include <asm/pci-bridge.h>
20
21/* Size of entire register space */
22#define TSI108_REG_SIZE (0x10000)
23
24/* Sizes of register spaces for individual blocks */
25#define TSI108_HLP_SIZE 0x1000
26#define TSI108_PCI_SIZE 0x1000
27#define TSI108_CLK_SIZE 0x1000
28#define TSI108_PB_SIZE 0x1000
29#define TSI108_SD_SIZE 0x1000
30#define TSI108_DMA_SIZE 0x1000
31#define TSI108_ETH_SIZE 0x1000
32#define TSI108_I2C_SIZE 0x400
33#define TSI108_MPIC_SIZE 0x400
34#define TSI108_UART0_SIZE 0x200
35#define TSI108_GPIO_SIZE 0x200
36#define TSI108_UART1_SIZE 0x200
37
38/* Offsets within Tsi108(A) CSR space for individual blocks */
39#define TSI108_HLP_OFFSET 0x0000
40#define TSI108_PCI_OFFSET 0x1000
41#define TSI108_CLK_OFFSET 0x2000
42#define TSI108_PB_OFFSET 0x3000
43#define TSI108_SD_OFFSET 0x4000
44#define TSI108_DMA_OFFSET 0x5000
45#define TSI108_ETH_OFFSET 0x6000
46#define TSI108_I2C_OFFSET 0x7000
47#define TSI108_MPIC_OFFSET 0x7400
48#define TSI108_UART0_OFFSET 0x7800
49#define TSI108_GPIO_OFFSET 0x7A00
50#define TSI108_UART1_OFFSET 0x7C00
51
52/* Tsi108 registers used by common code components */
53#define TSI108_PCI_CSR (0x004)
54#define TSI108_PCI_IRP_CFG_CTL (0x180)
55#define TSI108_PCI_IRP_STAT (0x184)
56#define TSI108_PCI_IRP_ENABLE (0x188)
57#define TSI108_PCI_IRP_INTAD (0x18C)
58
59#define TSI108_PCI_IRP_STAT_P_INT (0x00400000)
60#define TSI108_PCI_IRP_ENABLE_P_INT (0x00400000)
61
62#define TSI108_CG_PWRUP_STATUS (0x234)
63
64#define TSI108_PB_ISR (0x00C)
65#define TSI108_PB_ERRCS (0x404)
66#define TSI108_PB_AERR (0x408)
67
68#define TSI108_PB_ERRCS_ES (1 << 1)
69#define TSI108_PB_ISR_PBS_RD_ERR (1 << 8)
70
71#define TSI108_PCI_CFG_SIZE (0x01000000)
72
73/*
74 * PHY Configuration Options
75 *
76 * Specify "bcm54xx" in the compatible property of your device tree phy
77 * nodes if your board uses the Broadcom PHYs
78 */
79#define TSI108_PHY_MV88E 0 /* Marvel 88Exxxx PHY */
80#define TSI108_PHY_BCM54XX 1 /* Broardcom BCM54xx PHY */
81
82/* Global variables */
83
84extern u32 tsi108_pci_cfg_base;
85/* Exported functions */
86
87extern int tsi108_bridge_init(struct pci_controller *hose, uint phys_csr_base);
88extern unsigned long tsi108_get_mem_size(void);
89extern unsigned long tsi108_get_cpu_clk(void);
90extern unsigned long tsi108_get_sdc_clk(void);
91extern int tsi108_direct_write_config(struct pci_bus *bus, unsigned int devfn,
92 int offset, int len, u32 val);
93extern int tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn,
94 int offset, int len, u32 * val);
95extern void tsi108_clear_pci_error(u32 pci_cfg_base);
96
97extern phys_addr_t get_csrbase(void);
98
99typedef struct {
100 u32 regs; /* hw registers base address */
101 u32 phyregs; /* phy registers base address */
102 u16 phy; /* phy address */
103 u16 irq_num; /* irq number */
104 u8 mac_addr[6]; /* phy mac address */
105 u16 phy_type; /* type of phy on board */
106} hw_info;
107
108extern u32 get_vir_csrbase(void);
109extern u32 tsi108_csr_vir_base;
110
111static inline u32 tsi108_read_reg(u32 reg_offset)
112{
113 return in_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset));
114}
115
116static inline void tsi108_write_reg(u32 reg_offset, u32 val)
117{
118 out_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset), val);
119}
120
121#endif /* __PPC_KERNEL_TSI108_H */
diff --git a/include/asm-powerpc/tsi108_irq.h b/include/asm-powerpc/tsi108_irq.h
deleted file mode 100644
index 6ed93979fbe..00000000000
--- a/include/asm-powerpc/tsi108_irq.h
+++ /dev/null
@@ -1,124 +0,0 @@
1/*
2 * (C) Copyright 2005 Tundra Semiconductor Corp.
3 * Alex Bounine, <alexandreb at tundra.com).
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * definitions for interrupt controller initialization and external interrupt
26 * demultiplexing on TSI108EMU/SVB boards.
27 */
28
29#ifndef _ASM_POWERPC_TSI108_IRQ_H
30#define _ASM_POWERPC_TSI108_IRQ_H
31
32/*
33 * Tsi108 interrupts
34 */
35#ifndef TSI108_IRQ_REG_BASE
36#define TSI108_IRQ_REG_BASE 0
37#endif
38
39#define TSI108_IRQ(x) (TSI108_IRQ_REG_BASE + (x))
40
41#define TSI108_MAX_VECTORS (36 + 4) /* 36 sources + PCI INT demux */
42#define MAX_TASK_PRIO 0xF
43
44#define TSI108_IRQ_SPURIOUS (TSI108_MAX_VECTORS)
45
46#define DEFAULT_PRIO_LVL 10 /* initial priority level */
47
48/* Interrupt vectors assignment to external and internal
49 * sources of requests. */
50
51/* EXTERNAL INTERRUPT SOURCES */
52
53#define IRQ_TSI108_EXT_INT0 TSI108_IRQ(0) /* External Source at INT[0] */
54#define IRQ_TSI108_EXT_INT1 TSI108_IRQ(1) /* External Source at INT[1] */
55#define IRQ_TSI108_EXT_INT2 TSI108_IRQ(2) /* External Source at INT[2] */
56#define IRQ_TSI108_EXT_INT3 TSI108_IRQ(3) /* External Source at INT[3] */
57
58/* INTERNAL INTERRUPT SOURCES */
59
60#define IRQ_TSI108_RESERVED0 TSI108_IRQ(4) /* Reserved IRQ */
61#define IRQ_TSI108_RESERVED1 TSI108_IRQ(5) /* Reserved IRQ */
62#define IRQ_TSI108_RESERVED2 TSI108_IRQ(6) /* Reserved IRQ */
63#define IRQ_TSI108_RESERVED3 TSI108_IRQ(7) /* Reserved IRQ */
64#define IRQ_TSI108_DMA0 TSI108_IRQ(8) /* DMA0 */
65#define IRQ_TSI108_DMA1 TSI108_IRQ(9) /* DMA1 */
66#define IRQ_TSI108_DMA2 TSI108_IRQ(10) /* DMA2 */
67#define IRQ_TSI108_DMA3 TSI108_IRQ(11) /* DMA3 */
68#define IRQ_TSI108_UART0 TSI108_IRQ(12) /* UART0 */
69#define IRQ_TSI108_UART1 TSI108_IRQ(13) /* UART1 */
70#define IRQ_TSI108_I2C TSI108_IRQ(14) /* I2C */
71#define IRQ_TSI108_GPIO TSI108_IRQ(15) /* GPIO */
72#define IRQ_TSI108_GIGE0 TSI108_IRQ(16) /* GIGE0 */
73#define IRQ_TSI108_GIGE1 TSI108_IRQ(17) /* GIGE1 */
74#define IRQ_TSI108_RESERVED4 TSI108_IRQ(18) /* Reserved IRQ */
75#define IRQ_TSI108_HLP TSI108_IRQ(19) /* HLP */
76#define IRQ_TSI108_SDRAM TSI108_IRQ(20) /* SDC */
77#define IRQ_TSI108_PROC_IF TSI108_IRQ(21) /* Processor IF */
78#define IRQ_TSI108_RESERVED5 TSI108_IRQ(22) /* Reserved IRQ */
79#define IRQ_TSI108_PCI TSI108_IRQ(23) /* PCI/X block */
80
81#define IRQ_TSI108_MBOX0 TSI108_IRQ(24) /* Mailbox 0 register */
82#define IRQ_TSI108_MBOX1 TSI108_IRQ(25) /* Mailbox 1 register */
83#define IRQ_TSI108_MBOX2 TSI108_IRQ(26) /* Mailbox 2 register */
84#define IRQ_TSI108_MBOX3 TSI108_IRQ(27) /* Mailbox 3 register */
85
86#define IRQ_TSI108_DBELL0 TSI108_IRQ(28) /* Doorbell 0 */
87#define IRQ_TSI108_DBELL1 TSI108_IRQ(29) /* Doorbell 1 */
88#define IRQ_TSI108_DBELL2 TSI108_IRQ(30) /* Doorbell 2 */
89#define IRQ_TSI108_DBELL3 TSI108_IRQ(31) /* Doorbell 3 */
90
91#define IRQ_TSI108_TIMER0 TSI108_IRQ(32) /* Global Timer 0 */
92#define IRQ_TSI108_TIMER1 TSI108_IRQ(33) /* Global Timer 1 */
93#define IRQ_TSI108_TIMER2 TSI108_IRQ(34) /* Global Timer 2 */
94#define IRQ_TSI108_TIMER3 TSI108_IRQ(35) /* Global Timer 3 */
95
96/*
97 * PCI bus INTA# - INTD# lines demultiplexor
98 */
99#define IRQ_PCI_INTAD_BASE TSI108_IRQ(36)
100#define IRQ_PCI_INTA (IRQ_PCI_INTAD_BASE + 0)
101#define IRQ_PCI_INTB (IRQ_PCI_INTAD_BASE + 1)
102#define IRQ_PCI_INTC (IRQ_PCI_INTAD_BASE + 2)
103#define IRQ_PCI_INTD (IRQ_PCI_INTAD_BASE + 3)
104#define NUM_PCI_IRQS (4)
105
106/* number of entries in vector dispatch table */
107#define IRQ_TSI108_TAB_SIZE (TSI108_MAX_VECTORS + 1)
108
109/* Mapping of MPIC outputs to processors' interrupt pins */
110
111#define IDIR_INT_OUT0 0x1
112#define IDIR_INT_OUT1 0x2
113#define IDIR_INT_OUT2 0x4
114#define IDIR_INT_OUT3 0x8
115
116/*---------------------------------------------------------------
117 * IRQ line configuration parameters */
118
119/* Interrupt delivery modes */
120typedef enum {
121 TSI108_IRQ_DIRECTED,
122 TSI108_IRQ_DISTRIBUTED,
123} TSI108_IRQ_MODE;
124#endif /* _ASM_POWERPC_TSI108_IRQ_H */
diff --git a/include/asm-powerpc/tsi108_pci.h b/include/asm-powerpc/tsi108_pci.h
deleted file mode 100644
index 5653d7cc3e2..00000000000
--- a/include/asm-powerpc/tsi108_pci.h
+++ /dev/null
@@ -1,45 +0,0 @@
1/*
2 * Copyright 2007 IBM Corp
3 *
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21#ifndef _ASM_POWERPC_TSI108_PCI_H
22#define _ASM_POWERPC_TSI108_PCI_H
23
24#include <asm/tsi108.h>
25
26/* Register definitions */
27#define TSI108_PCI_P2O_BAR0 (TSI108_PCI_OFFSET + 0x10)
28#define TSI108_PCI_P2O_BAR0_UPPER (TSI108_PCI_OFFSET + 0x14)
29#define TSI108_PCI_P2O_BAR2 (TSI108_PCI_OFFSET + 0x18)
30#define TSI108_PCI_P2O_BAR2_UPPER (TSI108_PCI_OFFSET + 0x1c)
31#define TSI108_PCI_P2O_PAGE_SIZES (TSI108_PCI_OFFSET + 0x4c)
32#define TSI108_PCI_PFAB_BAR0 (TSI108_PCI_OFFSET + 0x204)
33#define TSI108_PCI_PFAB_BAR0_UPPER (TSI108_PCI_OFFSET + 0x208)
34#define TSI108_PCI_PFAB_IO (TSI108_PCI_OFFSET + 0x20c)
35#define TSI108_PCI_PFAB_IO_UPPER (TSI108_PCI_OFFSET + 0x210)
36#define TSI108_PCI_PFAB_MEM32 (TSI108_PCI_OFFSET + 0x214)
37#define TSI108_PCI_PFAB_PFM3 (TSI108_PCI_OFFSET + 0x220)
38#define TSI108_PCI_PFAB_PFM4 (TSI108_PCI_OFFSET + 0x230)
39
40extern int tsi108_setup_pci(struct device_node *dev, u32 cfg_phys, int primary);
41extern void tsi108_pci_int_init(struct device_node *node);
42extern void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc);
43extern void tsi108_clear_pci_cfg_error(void);
44
45#endif /* _ASM_POWERPC_TSI108_PCI_H */
diff --git a/include/asm-powerpc/types.h b/include/asm-powerpc/types.h
deleted file mode 100644
index d3374bc865b..00000000000
--- a/include/asm-powerpc/types.h
+++ /dev/null
@@ -1,75 +0,0 @@
1#ifndef _ASM_POWERPC_TYPES_H
2#define _ASM_POWERPC_TYPES_H
3
4#ifdef __powerpc64__
5# include <asm-generic/int-l64.h>
6#else
7# include <asm-generic/int-ll64.h>
8#endif
9
10#ifndef __ASSEMBLY__
11
12/*
13 * This file is never included by application software unless
14 * explicitly requested (e.g., via linux/types.h) in which case the
15 * application is Linux specific so (user-) name space pollution is
16 * not a major issue. However, for interoperability, libraries still
17 * need to be careful to avoid a name clashes.
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version
22 * 2 of the License, or (at your option) any later version.
23 */
24
25#ifdef __powerpc64__
26typedef unsigned int umode_t;
27#else
28typedef unsigned short umode_t;
29#endif
30
31typedef struct {
32 __u32 u[4];
33} __attribute__((aligned(16))) __vector128;
34
35#endif /* __ASSEMBLY__ */
36
37#ifdef __KERNEL__
38/*
39 * These aren't exported outside the kernel to avoid name space clashes
40 */
41#ifdef __powerpc64__
42#define BITS_PER_LONG 64
43#else
44#define BITS_PER_LONG 32
45#endif
46
47#ifndef __ASSEMBLY__
48
49typedef __vector128 vector128;
50
51/* Physical address used by some IO functions */
52#if defined(CONFIG_PPC64) || defined(CONFIG_PHYS_64BIT)
53typedef u64 phys_addr_t;
54#else
55typedef u32 phys_addr_t;
56#endif
57
58#ifdef __powerpc64__
59typedef u64 dma_addr_t;
60#else
61typedef u32 dma_addr_t;
62#endif
63typedef u64 dma64_addr_t;
64
65typedef struct {
66 unsigned long entry;
67 unsigned long toc;
68 unsigned long env;
69} func_descr_t;
70
71#endif /* __ASSEMBLY__ */
72
73#endif /* __KERNEL__ */
74
75#endif /* _ASM_POWERPC_TYPES_H */
diff --git a/include/asm-powerpc/uaccess.h b/include/asm-powerpc/uaccess.h
deleted file mode 100644
index bd0fb849515..00000000000
--- a/include/asm-powerpc/uaccess.h
+++ /dev/null
@@ -1,496 +0,0 @@
1#ifndef _ARCH_POWERPC_UACCESS_H
2#define _ARCH_POWERPC_UACCESS_H
3
4#ifdef __KERNEL__
5#ifndef __ASSEMBLY__
6
7#include <linux/sched.h>
8#include <linux/errno.h>
9#include <asm/asm-compat.h>
10#include <asm/processor.h>
11#include <asm/page.h>
12
13#define VERIFY_READ 0
14#define VERIFY_WRITE 1
15
16/*
17 * The fs value determines whether argument validity checking should be
18 * performed or not. If get_fs() == USER_DS, checking is performed, with
19 * get_fs() == KERNEL_DS, checking is bypassed.
20 *
21 * For historical reasons, these macros are grossly misnamed.
22 *
23 * The fs/ds values are now the highest legal address in the "segment".
24 * This simplifies the checking in the routines below.
25 */
26
27#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) })
28
29#define KERNEL_DS MAKE_MM_SEG(~0UL)
30#ifdef __powerpc64__
31/* We use TASK_SIZE_USER64 as TASK_SIZE is not constant */
32#define USER_DS MAKE_MM_SEG(TASK_SIZE_USER64 - 1)
33#else
34#define USER_DS MAKE_MM_SEG(TASK_SIZE - 1)
35#endif
36
37#define get_ds() (KERNEL_DS)
38#define get_fs() (current->thread.fs)
39#define set_fs(val) (current->thread.fs = (val))
40
41#define segment_eq(a, b) ((a).seg == (b).seg)
42
43#ifdef __powerpc64__
44/*
45 * This check is sufficient because there is a large enough
46 * gap between user addresses and the kernel addresses
47 */
48#define __access_ok(addr, size, segment) \
49 (((addr) <= (segment).seg) && ((size) <= (segment).seg))
50
51#else
52
53#define __access_ok(addr, size, segment) \
54 (((addr) <= (segment).seg) && \
55 (((size) == 0) || (((size) - 1) <= ((segment).seg - (addr)))))
56
57#endif
58
59#define access_ok(type, addr, size) \
60 (__chk_user_ptr(addr), \
61 __access_ok((__force unsigned long)(addr), (size), get_fs()))
62
63/*
64 * The exception table consists of pairs of addresses: the first is the
65 * address of an instruction that is allowed to fault, and the second is
66 * the address at which the program should continue. No registers are
67 * modified, so it is entirely up to the continuation code to figure out
68 * what to do.
69 *
70 * All the routines below use bits of fixup code that are out of line
71 * with the main instruction path. This means when everything is well,
72 * we don't even have to jump over them. Further, they do not intrude
73 * on our cache or tlb entries.
74 */
75
76struct exception_table_entry {
77 unsigned long insn;
78 unsigned long fixup;
79};
80
81/*
82 * These are the main single-value transfer routines. They automatically
83 * use the right size if we just have the right pointer type.
84 *
85 * This gets kind of ugly. We want to return _two_ values in "get_user()"
86 * and yet we don't want to do any pointers, because that is too much
87 * of a performance impact. Thus we have a few rather ugly macros here,
88 * and hide all the ugliness from the user.
89 *
90 * The "__xxx" versions of the user access functions are versions that
91 * do not verify the address space, that must have been done previously
92 * with a separate "access_ok()" call (this is used when we do multiple
93 * accesses to the same area of user memory).
94 *
95 * As we use the same address space for kernel and user data on the
96 * PowerPC, we can just do these as direct assignments. (Of course, the
97 * exception handling means that it's no longer "just"...)
98 *
99 * The "user64" versions of the user access functions are versions that
100 * allow access of 64-bit data. The "get_user" functions do not
101 * properly handle 64-bit data because the value gets down cast to a long.
102 * The "put_user" functions already handle 64-bit data properly but we add
103 * "user64" versions for completeness
104 */
105#define get_user(x, ptr) \
106 __get_user_check((x), (ptr), sizeof(*(ptr)))
107#define put_user(x, ptr) \
108 __put_user_check((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
109
110#define __get_user(x, ptr) \
111 __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
112#define __put_user(x, ptr) \
113 __put_user_nocheck((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
114
115#ifndef __powerpc64__
116#define __get_user64(x, ptr) \
117 __get_user64_nocheck((x), (ptr), sizeof(*(ptr)))
118#define __put_user64(x, ptr) __put_user(x, ptr)
119#endif
120
121#define __get_user_inatomic(x, ptr) \
122 __get_user_nosleep((x), (ptr), sizeof(*(ptr)))
123#define __put_user_inatomic(x, ptr) \
124 __put_user_nosleep((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
125
126#define __get_user_unaligned __get_user
127#define __put_user_unaligned __put_user
128
129extern long __put_user_bad(void);
130
131/*
132 * We don't tell gcc that we are accessing memory, but this is OK
133 * because we do not write to any memory gcc knows about, so there
134 * are no aliasing issues.
135 */
136#define __put_user_asm(x, addr, err, op) \
137 __asm__ __volatile__( \
138 "1: " op " %1,0(%2) # put_user\n" \
139 "2:\n" \
140 ".section .fixup,\"ax\"\n" \
141 "3: li %0,%3\n" \
142 " b 2b\n" \
143 ".previous\n" \
144 ".section __ex_table,\"a\"\n" \
145 PPC_LONG_ALIGN "\n" \
146 PPC_LONG "1b,3b\n" \
147 ".previous" \
148 : "=r" (err) \
149 : "r" (x), "b" (addr), "i" (-EFAULT), "0" (err))
150
151#ifdef __powerpc64__
152#define __put_user_asm2(x, ptr, retval) \
153 __put_user_asm(x, ptr, retval, "std")
154#else /* __powerpc64__ */
155#define __put_user_asm2(x, addr, err) \
156 __asm__ __volatile__( \
157 "1: stw %1,0(%2)\n" \
158 "2: stw %1+1,4(%2)\n" \
159 "3:\n" \
160 ".section .fixup,\"ax\"\n" \
161 "4: li %0,%3\n" \
162 " b 3b\n" \
163 ".previous\n" \
164 ".section __ex_table,\"a\"\n" \
165 PPC_LONG_ALIGN "\n" \
166 PPC_LONG "1b,4b\n" \
167 PPC_LONG "2b,4b\n" \
168 ".previous" \
169 : "=r" (err) \
170 : "r" (x), "b" (addr), "i" (-EFAULT), "0" (err))
171#endif /* __powerpc64__ */
172
173#define __put_user_size(x, ptr, size, retval) \
174do { \
175 retval = 0; \
176 switch (size) { \
177 case 1: __put_user_asm(x, ptr, retval, "stb"); break; \
178 case 2: __put_user_asm(x, ptr, retval, "sth"); break; \
179 case 4: __put_user_asm(x, ptr, retval, "stw"); break; \
180 case 8: __put_user_asm2(x, ptr, retval); break; \
181 default: __put_user_bad(); \
182 } \
183} while (0)
184
185#define __put_user_nocheck(x, ptr, size) \
186({ \
187 long __pu_err; \
188 __typeof__(*(ptr)) __user *__pu_addr = (ptr); \
189 if (!is_kernel_addr((unsigned long)__pu_addr)) \
190 might_sleep(); \
191 __chk_user_ptr(ptr); \
192 __put_user_size((x), __pu_addr, (size), __pu_err); \
193 __pu_err; \
194})
195
196#define __put_user_check(x, ptr, size) \
197({ \
198 long __pu_err = -EFAULT; \
199 __typeof__(*(ptr)) __user *__pu_addr = (ptr); \
200 might_sleep(); \
201 if (access_ok(VERIFY_WRITE, __pu_addr, size)) \
202 __put_user_size((x), __pu_addr, (size), __pu_err); \
203 __pu_err; \
204})
205
206#define __put_user_nosleep(x, ptr, size) \
207({ \
208 long __pu_err; \
209 __typeof__(*(ptr)) __user *__pu_addr = (ptr); \
210 __chk_user_ptr(ptr); \
211 __put_user_size((x), __pu_addr, (size), __pu_err); \
212 __pu_err; \
213})
214
215
216extern long __get_user_bad(void);
217
218#define __get_user_asm(x, addr, err, op) \
219 __asm__ __volatile__( \
220 "1: "op" %1,0(%2) # get_user\n" \
221 "2:\n" \
222 ".section .fixup,\"ax\"\n" \
223 "3: li %0,%3\n" \
224 " li %1,0\n" \
225 " b 2b\n" \
226 ".previous\n" \
227 ".section __ex_table,\"a\"\n" \
228 PPC_LONG_ALIGN "\n" \
229 PPC_LONG "1b,3b\n" \
230 ".previous" \
231 : "=r" (err), "=r" (x) \
232 : "b" (addr), "i" (-EFAULT), "0" (err))
233
234#ifdef __powerpc64__
235#define __get_user_asm2(x, addr, err) \
236 __get_user_asm(x, addr, err, "ld")
237#else /* __powerpc64__ */
238#define __get_user_asm2(x, addr, err) \
239 __asm__ __volatile__( \
240 "1: lwz %1,0(%2)\n" \
241 "2: lwz %1+1,4(%2)\n" \
242 "3:\n" \
243 ".section .fixup,\"ax\"\n" \
244 "4: li %0,%3\n" \
245 " li %1,0\n" \
246 " li %1+1,0\n" \
247 " b 3b\n" \
248 ".previous\n" \
249 ".section __ex_table,\"a\"\n" \
250 PPC_LONG_ALIGN "\n" \
251 PPC_LONG "1b,4b\n" \
252 PPC_LONG "2b,4b\n" \
253 ".previous" \
254 : "=r" (err), "=&r" (x) \
255 : "b" (addr), "i" (-EFAULT), "0" (err))
256#endif /* __powerpc64__ */
257
258#define __get_user_size(x, ptr, size, retval) \
259do { \
260 retval = 0; \
261 __chk_user_ptr(ptr); \
262 if (size > sizeof(x)) \
263 (x) = __get_user_bad(); \
264 switch (size) { \
265 case 1: __get_user_asm(x, ptr, retval, "lbz"); break; \
266 case 2: __get_user_asm(x, ptr, retval, "lhz"); break; \
267 case 4: __get_user_asm(x, ptr, retval, "lwz"); break; \
268 case 8: __get_user_asm2(x, ptr, retval); break; \
269 default: (x) = __get_user_bad(); \
270 } \
271} while (0)
272
273#define __get_user_nocheck(x, ptr, size) \
274({ \
275 long __gu_err; \
276 unsigned long __gu_val; \
277 const __typeof__(*(ptr)) __user *__gu_addr = (ptr); \
278 __chk_user_ptr(ptr); \
279 if (!is_kernel_addr((unsigned long)__gu_addr)) \
280 might_sleep(); \
281 __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
282 (x) = (__typeof__(*(ptr)))__gu_val; \
283 __gu_err; \
284})
285
286#ifndef __powerpc64__
287#define __get_user64_nocheck(x, ptr, size) \
288({ \
289 long __gu_err; \
290 long long __gu_val; \
291 const __typeof__(*(ptr)) __user *__gu_addr = (ptr); \
292 __chk_user_ptr(ptr); \
293 if (!is_kernel_addr((unsigned long)__gu_addr)) \
294 might_sleep(); \
295 __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
296 (x) = (__typeof__(*(ptr)))__gu_val; \
297 __gu_err; \
298})
299#endif /* __powerpc64__ */
300
301#define __get_user_check(x, ptr, size) \
302({ \
303 long __gu_err = -EFAULT; \
304 unsigned long __gu_val = 0; \
305 const __typeof__(*(ptr)) __user *__gu_addr = (ptr); \
306 might_sleep(); \
307 if (access_ok(VERIFY_READ, __gu_addr, (size))) \
308 __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
309 (x) = (__typeof__(*(ptr)))__gu_val; \
310 __gu_err; \
311})
312
313#define __get_user_nosleep(x, ptr, size) \
314({ \
315 long __gu_err; \
316 unsigned long __gu_val; \
317 const __typeof__(*(ptr)) __user *__gu_addr = (ptr); \
318 __chk_user_ptr(ptr); \
319 __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
320 (x) = (__typeof__(*(ptr)))__gu_val; \
321 __gu_err; \
322})
323
324
325/* more complex routines */
326
327extern unsigned long __copy_tofrom_user(void __user *to,
328 const void __user *from, unsigned long size);
329
330#ifndef __powerpc64__
331
332static inline unsigned long copy_from_user(void *to,
333 const void __user *from, unsigned long n)
334{
335 unsigned long over;
336
337 if (access_ok(VERIFY_READ, from, n))
338 return __copy_tofrom_user((__force void __user *)to, from, n);
339 if ((unsigned long)from < TASK_SIZE) {
340 over = (unsigned long)from + n - TASK_SIZE;
341 return __copy_tofrom_user((__force void __user *)to, from,
342 n - over) + over;
343 }
344 return n;
345}
346
347static inline unsigned long copy_to_user(void __user *to,
348 const void *from, unsigned long n)
349{
350 unsigned long over;
351
352 if (access_ok(VERIFY_WRITE, to, n))
353 return __copy_tofrom_user(to, (__force void __user *)from, n);
354 if ((unsigned long)to < TASK_SIZE) {
355 over = (unsigned long)to + n - TASK_SIZE;
356 return __copy_tofrom_user(to, (__force void __user *)from,
357 n - over) + over;
358 }
359 return n;
360}
361
362#else /* __powerpc64__ */
363
364#define __copy_in_user(to, from, size) \
365 __copy_tofrom_user((to), (from), (size))
366
367extern unsigned long copy_from_user(void *to, const void __user *from,
368 unsigned long n);
369extern unsigned long copy_to_user(void __user *to, const void *from,
370 unsigned long n);
371extern unsigned long copy_in_user(void __user *to, const void __user *from,
372 unsigned long n);
373
374#endif /* __powerpc64__ */
375
376static inline unsigned long __copy_from_user_inatomic(void *to,
377 const void __user *from, unsigned long n)
378{
379 if (__builtin_constant_p(n) && (n <= 8)) {
380 unsigned long ret = 1;
381
382 switch (n) {
383 case 1:
384 __get_user_size(*(u8 *)to, from, 1, ret);
385 break;
386 case 2:
387 __get_user_size(*(u16 *)to, from, 2, ret);
388 break;
389 case 4:
390 __get_user_size(*(u32 *)to, from, 4, ret);
391 break;
392 case 8:
393 __get_user_size(*(u64 *)to, from, 8, ret);
394 break;
395 }
396 if (ret == 0)
397 return 0;
398 }
399 return __copy_tofrom_user((__force void __user *)to, from, n);
400}
401
402static inline unsigned long __copy_to_user_inatomic(void __user *to,
403 const void *from, unsigned long n)
404{
405 if (__builtin_constant_p(n) && (n <= 8)) {
406 unsigned long ret = 1;
407
408 switch (n) {
409 case 1:
410 __put_user_size(*(u8 *)from, (u8 __user *)to, 1, ret);
411 break;
412 case 2:
413 __put_user_size(*(u16 *)from, (u16 __user *)to, 2, ret);
414 break;
415 case 4:
416 __put_user_size(*(u32 *)from, (u32 __user *)to, 4, ret);
417 break;
418 case 8:
419 __put_user_size(*(u64 *)from, (u64 __user *)to, 8, ret);
420 break;
421 }
422 if (ret == 0)
423 return 0;
424 }
425 return __copy_tofrom_user(to, (__force const void __user *)from, n);
426}
427
428static inline unsigned long __copy_from_user(void *to,
429 const void __user *from, unsigned long size)
430{
431 might_sleep();
432 return __copy_from_user_inatomic(to, from, size);
433}
434
435static inline unsigned long __copy_to_user(void __user *to,
436 const void *from, unsigned long size)
437{
438 might_sleep();
439 return __copy_to_user_inatomic(to, from, size);
440}
441
442extern unsigned long __clear_user(void __user *addr, unsigned long size);
443
444static inline unsigned long clear_user(void __user *addr, unsigned long size)
445{
446 might_sleep();
447 if (likely(access_ok(VERIFY_WRITE, addr, size)))
448 return __clear_user(addr, size);
449 if ((unsigned long)addr < TASK_SIZE) {
450 unsigned long over = (unsigned long)addr + size - TASK_SIZE;
451 return __clear_user(addr, size - over) + over;
452 }
453 return size;
454}
455
456extern int __strncpy_from_user(char *dst, const char __user *src, long count);
457
458static inline long strncpy_from_user(char *dst, const char __user *src,
459 long count)
460{
461 might_sleep();
462 if (likely(access_ok(VERIFY_READ, src, 1)))
463 return __strncpy_from_user(dst, src, count);
464 return -EFAULT;
465}
466
467/*
468 * Return the size of a string (including the ending 0)
469 *
470 * Return 0 for error
471 */
472extern int __strnlen_user(const char __user *str, long len, unsigned long top);
473
474/*
475 * Returns the length of the string at str (including the null byte),
476 * or 0 if we hit a page we can't access,
477 * or something > len if we didn't find a null byte.
478 *
479 * The `top' parameter to __strnlen_user is to make sure that
480 * we can never overflow from the user area into kernel space.
481 */
482static inline int strnlen_user(const char __user *str, long len)
483{
484 unsigned long top = current->thread.fs.seg;
485
486 if ((unsigned long)str > top)
487 return 0;
488 return __strnlen_user(str, len, top);
489}
490
491#define strlen_user(str) strnlen_user((str), 0x7ffffffe)
492
493#endif /* __ASSEMBLY__ */
494#endif /* __KERNEL__ */
495
496#endif /* _ARCH_POWERPC_UACCESS_H */
diff --git a/include/asm-powerpc/ucc.h b/include/asm-powerpc/ucc.h
deleted file mode 100644
index 46b09ba6bea..00000000000
--- a/include/asm-powerpc/ucc.h
+++ /dev/null
@@ -1,64 +0,0 @@
1/*
2 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
3 *
4 * Authors: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
6 *
7 * Description:
8 * Internal header file for UCC unit routines.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15#ifndef __UCC_H__
16#define __UCC_H__
17
18#include <asm/immap_qe.h>
19#include <asm/qe.h>
20
21#define STATISTICS
22
23#define UCC_MAX_NUM 8
24
25/* Slow or fast type for UCCs.
26*/
27enum ucc_speed_type {
28 UCC_SPEED_TYPE_FAST = UCC_GUEMR_MODE_FAST_RX | UCC_GUEMR_MODE_FAST_TX,
29 UCC_SPEED_TYPE_SLOW = UCC_GUEMR_MODE_SLOW_RX | UCC_GUEMR_MODE_SLOW_TX
30};
31
32/* ucc_set_type
33 * Sets UCC to slow or fast mode.
34 *
35 * ucc_num - (In) number of UCC (0-7).
36 * speed - (In) slow or fast mode for UCC.
37 */
38int ucc_set_type(unsigned int ucc_num, enum ucc_speed_type speed);
39
40int ucc_set_qe_mux_mii_mng(unsigned int ucc_num);
41
42int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock,
43 enum comm_dir mode);
44
45int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask);
46
47/* QE MUX clock routing for UCC
48*/
49static inline int ucc_set_qe_mux_grant(unsigned int ucc_num, int set)
50{
51 return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_GRANT);
52}
53
54static inline int ucc_set_qe_mux_tsa(unsigned int ucc_num, int set)
55{
56 return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_TSA);
57}
58
59static inline int ucc_set_qe_mux_bkpt(unsigned int ucc_num, int set)
60{
61 return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_BKPT);
62}
63
64#endif /* __UCC_H__ */
diff --git a/include/asm-powerpc/ucc_fast.h b/include/asm-powerpc/ucc_fast.h
deleted file mode 100644
index fce16abe7ee..00000000000
--- a/include/asm-powerpc/ucc_fast.h
+++ /dev/null
@@ -1,246 +0,0 @@
1/*
2 * include/asm-powerpc/ucc_fast.h
3 *
4 * Internal header file for UCC FAST unit routines.
5 *
6 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
7 *
8 * Authors: Shlomi Gridish <gridish@freescale.com>
9 * Li Yang <leoli@freescale.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16#ifndef __UCC_FAST_H__
17#define __UCC_FAST_H__
18
19#include <linux/kernel.h>
20
21#include <asm/immap_qe.h>
22#include <asm/qe.h>
23
24#include "ucc.h"
25
26/* Receive BD's status */
27#define R_E 0x80000000 /* buffer empty */
28#define R_W 0x20000000 /* wrap bit */
29#define R_I 0x10000000 /* interrupt on reception */
30#define R_L 0x08000000 /* last */
31#define R_F 0x04000000 /* first */
32
33/* transmit BD's status */
34#define T_R 0x80000000 /* ready bit */
35#define T_W 0x20000000 /* wrap bit */
36#define T_I 0x10000000 /* interrupt on completion */
37#define T_L 0x08000000 /* last */
38
39/* Rx Data buffer must be 4 bytes aligned in most cases */
40#define UCC_FAST_RX_ALIGN 4
41#define UCC_FAST_MRBLR_ALIGNMENT 4
42#define UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT 8
43
44/* Sizes */
45#define UCC_FAST_URFS_MIN_VAL 0x88
46#define UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR 8
47
48/* ucc_fast_channel_protocol_mode - UCC FAST mode */
49enum ucc_fast_channel_protocol_mode {
50 UCC_FAST_PROTOCOL_MODE_HDLC = 0x00000000,
51 UCC_FAST_PROTOCOL_MODE_RESERVED01 = 0x00000001,
52 UCC_FAST_PROTOCOL_MODE_RESERVED_QMC = 0x00000002,
53 UCC_FAST_PROTOCOL_MODE_RESERVED02 = 0x00000003,
54 UCC_FAST_PROTOCOL_MODE_RESERVED_UART = 0x00000004,
55 UCC_FAST_PROTOCOL_MODE_RESERVED03 = 0x00000005,
56 UCC_FAST_PROTOCOL_MODE_RESERVED_EX_MAC_1 = 0x00000006,
57 UCC_FAST_PROTOCOL_MODE_RESERVED_EX_MAC_2 = 0x00000007,
58 UCC_FAST_PROTOCOL_MODE_RESERVED_BISYNC = 0x00000008,
59 UCC_FAST_PROTOCOL_MODE_RESERVED04 = 0x00000009,
60 UCC_FAST_PROTOCOL_MODE_ATM = 0x0000000A,
61 UCC_FAST_PROTOCOL_MODE_RESERVED05 = 0x0000000B,
62 UCC_FAST_PROTOCOL_MODE_ETHERNET = 0x0000000C,
63 UCC_FAST_PROTOCOL_MODE_RESERVED06 = 0x0000000D,
64 UCC_FAST_PROTOCOL_MODE_POS = 0x0000000E,
65 UCC_FAST_PROTOCOL_MODE_RESERVED07 = 0x0000000F
66};
67
68/* ucc_fast_transparent_txrx - UCC Fast Transparent TX & RX */
69enum ucc_fast_transparent_txrx {
70 UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL = 0x00000000,
71 UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_TRANSPARENT = 0x18000000
72};
73
74/* UCC fast diagnostic mode */
75enum ucc_fast_diag_mode {
76 UCC_FAST_DIAGNOSTIC_NORMAL = 0x0,
77 UCC_FAST_DIAGNOSTIC_LOCAL_LOOP_BACK = 0x40000000,
78 UCC_FAST_DIAGNOSTIC_AUTO_ECHO = 0x80000000,
79 UCC_FAST_DIAGNOSTIC_LOOP_BACK_AND_ECHO = 0xC0000000
80};
81
82/* UCC fast Sync length (transparent mode only) */
83enum ucc_fast_sync_len {
84 UCC_FAST_SYNC_LEN_NOT_USED = 0x0,
85 UCC_FAST_SYNC_LEN_AUTOMATIC = 0x00004000,
86 UCC_FAST_SYNC_LEN_8_BIT = 0x00008000,
87 UCC_FAST_SYNC_LEN_16_BIT = 0x0000C000
88};
89
90/* UCC fast RTS mode */
91enum ucc_fast_ready_to_send {
92 UCC_FAST_SEND_IDLES_BETWEEN_FRAMES = 0x00000000,
93 UCC_FAST_SEND_FLAGS_BETWEEN_FRAMES = 0x00002000
94};
95
96/* UCC fast receiver decoding mode */
97enum ucc_fast_rx_decoding_method {
98 UCC_FAST_RX_ENCODING_NRZ = 0x00000000,
99 UCC_FAST_RX_ENCODING_NRZI = 0x00000800,
100 UCC_FAST_RX_ENCODING_RESERVED0 = 0x00001000,
101 UCC_FAST_RX_ENCODING_RESERVED1 = 0x00001800
102};
103
104/* UCC fast transmitter encoding mode */
105enum ucc_fast_tx_encoding_method {
106 UCC_FAST_TX_ENCODING_NRZ = 0x00000000,
107 UCC_FAST_TX_ENCODING_NRZI = 0x00000100,
108 UCC_FAST_TX_ENCODING_RESERVED0 = 0x00000200,
109 UCC_FAST_TX_ENCODING_RESERVED1 = 0x00000300
110};
111
112/* UCC fast CRC length */
113enum ucc_fast_transparent_tcrc {
114 UCC_FAST_16_BIT_CRC = 0x00000000,
115 UCC_FAST_CRC_RESERVED0 = 0x00000040,
116 UCC_FAST_32_BIT_CRC = 0x00000080,
117 UCC_FAST_CRC_RESERVED1 = 0x000000C0
118};
119
120/* Fast UCC initialization structure */
121struct ucc_fast_info {
122 int ucc_num;
123 enum qe_clock rx_clock;
124 enum qe_clock tx_clock;
125 u32 regs;
126 int irq;
127 u32 uccm_mask;
128 int bd_mem_part;
129 int brkpt_support;
130 int grant_support;
131 int tsa;
132 int cdp;
133 int cds;
134 int ctsp;
135 int ctss;
136 int tci;
137 int txsy;
138 int rtsm;
139 int revd;
140 int rsyn;
141 u16 max_rx_buf_length;
142 u16 urfs;
143 u16 urfet;
144 u16 urfset;
145 u16 utfs;
146 u16 utfet;
147 u16 utftt;
148 u16 ufpt;
149 enum ucc_fast_channel_protocol_mode mode;
150 enum ucc_fast_transparent_txrx ttx_trx;
151 enum ucc_fast_tx_encoding_method tenc;
152 enum ucc_fast_rx_decoding_method renc;
153 enum ucc_fast_transparent_tcrc tcrc;
154 enum ucc_fast_sync_len synl;
155};
156
157struct ucc_fast_private {
158 struct ucc_fast_info *uf_info;
159 struct ucc_fast __iomem *uf_regs; /* a pointer to the UCC regs. */
160 u32 __iomem *p_ucce; /* a pointer to the event register in memory. */
161 u32 __iomem *p_uccm; /* a pointer to the mask register in memory. */
162#ifdef CONFIG_UGETH_TX_ON_DEMAND
163 u16 __iomem *p_utodr; /* pointer to the transmit on demand register */
164#endif
165 int enabled_tx; /* Whether channel is enabled for Tx (ENT) */
166 int enabled_rx; /* Whether channel is enabled for Rx (ENR) */
167 int stopped_tx; /* Whether channel has been stopped for Tx
168 (STOP_TX, etc.) */
169 int stopped_rx; /* Whether channel has been stopped for Rx */
170 u32 ucc_fast_tx_virtual_fifo_base_offset;/* pointer to base of Tx
171 virtual fifo */
172 u32 ucc_fast_rx_virtual_fifo_base_offset;/* pointer to base of Rx
173 virtual fifo */
174#ifdef STATISTICS
175 u32 tx_frames; /* Transmitted frames counter. */
176 u32 rx_frames; /* Received frames counter (only frames
177 passed to application). */
178 u32 tx_discarded; /* Discarded tx frames counter (frames that
179 were discarded by the driver due to errors).
180 */
181 u32 rx_discarded; /* Discarded rx frames counter (frames that
182 were discarded by the driver due to errors).
183 */
184#endif /* STATISTICS */
185 u16 mrblr; /* maximum receive buffer length */
186};
187
188/* ucc_fast_init
189 * Initializes Fast UCC according to user provided parameters.
190 *
191 * uf_info - (In) pointer to the fast UCC info structure.
192 * uccf_ret - (Out) pointer to the fast UCC structure.
193 */
194int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** uccf_ret);
195
196/* ucc_fast_free
197 * Frees all resources for fast UCC.
198 *
199 * uccf - (In) pointer to the fast UCC structure.
200 */
201void ucc_fast_free(struct ucc_fast_private * uccf);
202
203/* ucc_fast_enable
204 * Enables a fast UCC port.
205 * This routine enables Tx and/or Rx through the General UCC Mode Register.
206 *
207 * uccf - (In) pointer to the fast UCC structure.
208 * mode - (In) TX, RX, or both.
209 */
210void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode);
211
212/* ucc_fast_disable
213 * Disables a fast UCC port.
214 * This routine disables Tx and/or Rx through the General UCC Mode Register.
215 *
216 * uccf - (In) pointer to the fast UCC structure.
217 * mode - (In) TX, RX, or both.
218 */
219void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode);
220
221/* ucc_fast_irq
222 * Handles interrupts on fast UCC.
223 * Called from the general interrupt routine to handle interrupts on fast UCC.
224 *
225 * uccf - (In) pointer to the fast UCC structure.
226 */
227void ucc_fast_irq(struct ucc_fast_private * uccf);
228
229/* ucc_fast_transmit_on_demand
230 * Immediately forces a poll of the transmitter for data to be sent.
231 * Typically, the hardware performs a periodic poll for data that the
232 * transmit routine has set up to be transmitted. In cases where
233 * this polling cycle is not soon enough, this optional routine can
234 * be invoked to force a poll right away, instead. Proper use for
235 * each transmission for which this functionality is desired is to
236 * call the transmit routine and then this routine right after.
237 *
238 * uccf - (In) pointer to the fast UCC structure.
239 */
240void ucc_fast_transmit_on_demand(struct ucc_fast_private * uccf);
241
242u32 ucc_fast_get_qe_cr_subblock(int uccf_num);
243
244void ucc_fast_dump_regs(struct ucc_fast_private * uccf);
245
246#endif /* __UCC_FAST_H__ */
diff --git a/include/asm-powerpc/ucc_slow.h b/include/asm-powerpc/ucc_slow.h
deleted file mode 100644
index 0980e6ad335..00000000000
--- a/include/asm-powerpc/ucc_slow.h
+++ /dev/null
@@ -1,290 +0,0 @@
1/*
2 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
3 *
4 * Authors: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
6 *
7 * Description:
8 * Internal header file for UCC SLOW unit routines.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15#ifndef __UCC_SLOW_H__
16#define __UCC_SLOW_H__
17
18#include <linux/kernel.h>
19
20#include <asm/immap_qe.h>
21#include <asm/qe.h>
22
23#include "ucc.h"
24
25/* transmit BD's status */
26#define T_R 0x80000000 /* ready bit */
27#define T_PAD 0x40000000 /* add pads to short frames */
28#define T_W 0x20000000 /* wrap bit */
29#define T_I 0x10000000 /* interrupt on completion */
30#define T_L 0x08000000 /* last */
31
32#define T_A 0x04000000 /* Address - the data transmitted as address
33 chars */
34#define T_TC 0x04000000 /* transmit CRC */
35#define T_CM 0x02000000 /* continuous mode */
36#define T_DEF 0x02000000 /* collision on previous attempt to transmit */
37#define T_P 0x01000000 /* Preamble - send Preamble sequence before
38 data */
39#define T_HB 0x01000000 /* heartbeat */
40#define T_NS 0x00800000 /* No Stop */
41#define T_LC 0x00800000 /* late collision */
42#define T_RL 0x00400000 /* retransmission limit */
43#define T_UN 0x00020000 /* underrun */
44#define T_CT 0x00010000 /* CTS lost */
45#define T_CSL 0x00010000 /* carrier sense lost */
46#define T_RC 0x003c0000 /* retry count */
47
48/* Receive BD's status */
49#define R_E 0x80000000 /* buffer empty */
50#define R_W 0x20000000 /* wrap bit */
51#define R_I 0x10000000 /* interrupt on reception */
52#define R_L 0x08000000 /* last */
53#define R_C 0x08000000 /* the last byte in this buffer is a cntl
54 char */
55#define R_F 0x04000000 /* first */
56#define R_A 0x04000000 /* the first byte in this buffer is address
57 byte */
58#define R_CM 0x02000000 /* continuous mode */
59#define R_ID 0x01000000 /* buffer close on reception of idles */
60#define R_M 0x01000000 /* Frame received because of promiscuous
61 mode */
62#define R_AM 0x00800000 /* Address match */
63#define R_DE 0x00800000 /* Address match */
64#define R_LG 0x00200000 /* Break received */
65#define R_BR 0x00200000 /* Frame length violation */
66#define R_NO 0x00100000 /* Rx Non Octet Aligned Packet */
67#define R_FR 0x00100000 /* Framing Error (no stop bit) character
68 received */
69#define R_PR 0x00080000 /* Parity Error character received */
70#define R_AB 0x00080000 /* Frame Aborted */
71#define R_SH 0x00080000 /* frame is too short */
72#define R_CR 0x00040000 /* CRC Error */
73#define R_OV 0x00020000 /* Overrun */
74#define R_CD 0x00010000 /* CD lost */
75#define R_CL 0x00010000 /* this frame is closed because of a
76 collision */
77
78/* Rx Data buffer must be 4 bytes aligned in most cases.*/
79#define UCC_SLOW_RX_ALIGN 4
80#define UCC_SLOW_MRBLR_ALIGNMENT 4
81#define UCC_SLOW_PRAM_SIZE 0x100
82#define ALIGNMENT_OF_UCC_SLOW_PRAM 64
83
84/* UCC Slow Channel Protocol Mode */
85enum ucc_slow_channel_protocol_mode {
86 UCC_SLOW_CHANNEL_PROTOCOL_MODE_QMC = 0x00000002,
87 UCC_SLOW_CHANNEL_PROTOCOL_MODE_UART = 0x00000004,
88 UCC_SLOW_CHANNEL_PROTOCOL_MODE_BISYNC = 0x00000008,
89};
90
91/* UCC Slow Transparent Transmit CRC (TCRC) */
92enum ucc_slow_transparent_tcrc {
93 /* 16-bit CCITT CRC (HDLC). (X16 + X12 + X5 + 1) */
94 UCC_SLOW_TRANSPARENT_TCRC_CCITT_CRC16 = 0x00000000,
95 /* CRC16 (BISYNC). (X16 + X15 + X2 + 1) */
96 UCC_SLOW_TRANSPARENT_TCRC_CRC16 = 0x00004000,
97 /* 32-bit CCITT CRC (Ethernet and HDLC) */
98 UCC_SLOW_TRANSPARENT_TCRC_CCITT_CRC32 = 0x00008000,
99};
100
101/* UCC Slow oversampling rate for transmitter (TDCR) */
102enum ucc_slow_tx_oversampling_rate {
103 /* 1x clock mode */
104 UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_1 = 0x00000000,
105 /* 8x clock mode */
106 UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_8 = 0x00010000,
107 /* 16x clock mode */
108 UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_16 = 0x00020000,
109 /* 32x clock mode */
110 UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_32 = 0x00030000,
111};
112
113/* UCC Slow Oversampling rate for receiver (RDCR)
114*/
115enum ucc_slow_rx_oversampling_rate {
116 /* 1x clock mode */
117 UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_1 = 0x00000000,
118 /* 8x clock mode */
119 UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_8 = 0x00004000,
120 /* 16x clock mode */
121 UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_16 = 0x00008000,
122 /* 32x clock mode */
123 UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_32 = 0x0000c000,
124};
125
126/* UCC Slow Transmitter encoding method (TENC)
127*/
128enum ucc_slow_tx_encoding_method {
129 UCC_SLOW_TRANSMITTER_ENCODING_METHOD_TENC_NRZ = 0x00000000,
130 UCC_SLOW_TRANSMITTER_ENCODING_METHOD_TENC_NRZI = 0x00000100
131};
132
133/* UCC Slow Receiver decoding method (RENC)
134*/
135enum ucc_slow_rx_decoding_method {
136 UCC_SLOW_RECEIVER_DECODING_METHOD_RENC_NRZ = 0x00000000,
137 UCC_SLOW_RECEIVER_DECODING_METHOD_RENC_NRZI = 0x00000800
138};
139
140/* UCC Slow Diagnostic mode (DIAG)
141*/
142enum ucc_slow_diag_mode {
143 UCC_SLOW_DIAG_MODE_NORMAL = 0x00000000,
144 UCC_SLOW_DIAG_MODE_LOOPBACK = 0x00000040,
145 UCC_SLOW_DIAG_MODE_ECHO = 0x00000080,
146 UCC_SLOW_DIAG_MODE_LOOPBACK_ECHO = 0x000000c0
147};
148
149struct ucc_slow_info {
150 int ucc_num;
151 int protocol; /* QE_CR_PROTOCOL_xxx */
152 enum qe_clock rx_clock;
153 enum qe_clock tx_clock;
154 phys_addr_t regs;
155 int irq;
156 u16 uccm_mask;
157 int data_mem_part;
158 int init_tx;
159 int init_rx;
160 u32 tx_bd_ring_len;
161 u32 rx_bd_ring_len;
162 int rx_interrupts;
163 int brkpt_support;
164 int grant_support;
165 int tsa;
166 int cdp;
167 int cds;
168 int ctsp;
169 int ctss;
170 int rinv;
171 int tinv;
172 int rtsm;
173 int rfw;
174 int tci;
175 int tend;
176 int tfl;
177 int txsy;
178 u16 max_rx_buf_length;
179 enum ucc_slow_transparent_tcrc tcrc;
180 enum ucc_slow_channel_protocol_mode mode;
181 enum ucc_slow_diag_mode diag;
182 enum ucc_slow_tx_oversampling_rate tdcr;
183 enum ucc_slow_rx_oversampling_rate rdcr;
184 enum ucc_slow_tx_encoding_method tenc;
185 enum ucc_slow_rx_decoding_method renc;
186};
187
188struct ucc_slow_private {
189 struct ucc_slow_info *us_info;
190 struct ucc_slow __iomem *us_regs; /* Ptr to memory map of UCC regs */
191 struct ucc_slow_pram *us_pram; /* a pointer to the parameter RAM */
192 u32 us_pram_offset;
193 int enabled_tx; /* Whether channel is enabled for Tx (ENT) */
194 int enabled_rx; /* Whether channel is enabled for Rx (ENR) */
195 int stopped_tx; /* Whether channel has been stopped for Tx
196 (STOP_TX, etc.) */
197 int stopped_rx; /* Whether channel has been stopped for Rx */
198 struct list_head confQ; /* frames passed to chip waiting for tx */
199 u32 first_tx_bd_mask; /* mask is used in Tx routine to save status
200 and length for first BD in a frame */
201 u32 tx_base_offset; /* first BD in Tx BD table offset (In MURAM) */
202 u32 rx_base_offset; /* first BD in Rx BD table offset (In MURAM) */
203 struct qe_bd *confBd; /* next BD for confirm after Tx */
204 struct qe_bd *tx_bd; /* next BD for new Tx request */
205 struct qe_bd *rx_bd; /* next BD to collect after Rx */
206 void *p_rx_frame; /* accumulating receive frame */
207 u16 *p_ucce; /* a pointer to the event register in memory.
208 */
209 u16 *p_uccm; /* a pointer to the mask register in memory */
210 u16 saved_uccm; /* a saved mask for the RX Interrupt bits */
211#ifdef STATISTICS
212 u32 tx_frames; /* Transmitted frames counters */
213 u32 rx_frames; /* Received frames counters (only frames
214 passed to application) */
215 u32 rx_discarded; /* Discarded frames counters (frames that
216 were discarded by the driver due to
217 errors) */
218#endif /* STATISTICS */
219};
220
221/* ucc_slow_init
222 * Initializes Slow UCC according to provided parameters.
223 *
224 * us_info - (In) pointer to the slow UCC info structure.
225 * uccs_ret - (Out) pointer to the slow UCC structure.
226 */
227int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** uccs_ret);
228
229/* ucc_slow_free
230 * Frees all resources for slow UCC.
231 *
232 * uccs - (In) pointer to the slow UCC structure.
233 */
234void ucc_slow_free(struct ucc_slow_private * uccs);
235
236/* ucc_slow_enable
237 * Enables a fast UCC port.
238 * This routine enables Tx and/or Rx through the General UCC Mode Register.
239 *
240 * uccs - (In) pointer to the slow UCC structure.
241 * mode - (In) TX, RX, or both.
242 */
243void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode);
244
245/* ucc_slow_disable
246 * Disables a fast UCC port.
247 * This routine disables Tx and/or Rx through the General UCC Mode Register.
248 *
249 * uccs - (In) pointer to the slow UCC structure.
250 * mode - (In) TX, RX, or both.
251 */
252void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode);
253
254/* ucc_slow_poll_transmitter_now
255 * Immediately forces a poll of the transmitter for data to be sent.
256 * Typically, the hardware performs a periodic poll for data that the
257 * transmit routine has set up to be transmitted. In cases where
258 * this polling cycle is not soon enough, this optional routine can
259 * be invoked to force a poll right away, instead. Proper use for
260 * each transmission for which this functionality is desired is to
261 * call the transmit routine and then this routine right after.
262 *
263 * uccs - (In) pointer to the slow UCC structure.
264 */
265void ucc_slow_poll_transmitter_now(struct ucc_slow_private * uccs);
266
267/* ucc_slow_graceful_stop_tx
268 * Smoothly stops transmission on a specified slow UCC.
269 *
270 * uccs - (In) pointer to the slow UCC structure.
271 */
272void ucc_slow_graceful_stop_tx(struct ucc_slow_private * uccs);
273
274/* ucc_slow_stop_tx
275 * Stops transmission on a specified slow UCC.
276 *
277 * uccs - (In) pointer to the slow UCC structure.
278 */
279void ucc_slow_stop_tx(struct ucc_slow_private * uccs);
280
281/* ucc_slow_restart_tx
282 * Restarts transmitting on a specified slow UCC.
283 *
284 * uccs - (In) pointer to the slow UCC structure.
285 */
286void ucc_slow_restart_tx(struct ucc_slow_private *uccs);
287
288u32 ucc_slow_get_qe_cr_subblock(int uccs_num);
289
290#endif /* __UCC_SLOW_H__ */
diff --git a/include/asm-powerpc/ucontext.h b/include/asm-powerpc/ucontext.h
deleted file mode 100644
index d9a4ddf0cc8..00000000000
--- a/include/asm-powerpc/ucontext.h
+++ /dev/null
@@ -1,40 +0,0 @@
1#ifndef _ASM_POWERPC_UCONTEXT_H
2#define _ASM_POWERPC_UCONTEXT_H
3
4#ifdef __powerpc64__
5#include <asm/sigcontext.h>
6#else
7#include <asm/elf.h>
8#endif
9#include <asm/signal.h>
10
11#ifndef __powerpc64__
12struct mcontext {
13 elf_gregset_t mc_gregs;
14 elf_fpregset_t mc_fregs;
15 unsigned long mc_pad[2];
16 elf_vrregset_t mc_vregs __attribute__((__aligned__(16)));
17};
18#endif
19
20struct ucontext {
21 unsigned long uc_flags;
22 struct ucontext __user *uc_link;
23 stack_t uc_stack;
24#ifndef __powerpc64__
25 int uc_pad[7];
26 struct mcontext __user *uc_regs;/* points to uc_mcontext field */
27#endif
28 sigset_t uc_sigmask;
29 /* glibc has 1024-bit signal masks, ours are 64-bit */
30#ifdef __powerpc64__
31 sigset_t __unused[15]; /* Allow for uc_sigmask growth */
32 struct sigcontext uc_mcontext; /* last for extensibility */
33#else
34 int uc_maskext[30];
35 int uc_pad2[3];
36 struct mcontext uc_mcontext;
37#endif
38};
39
40#endif /* _ASM_POWERPC_UCONTEXT_H */
diff --git a/include/asm-powerpc/udbg.h b/include/asm-powerpc/udbg.h
deleted file mode 100644
index 6418ceea44b..00000000000
--- a/include/asm-powerpc/udbg.h
+++ /dev/null
@@ -1,55 +0,0 @@
1/*
2 * (c) 2001, 2006 IBM Corporation.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10#ifndef _ASM_POWERPC_UDBG_H
11#define _ASM_POWERPC_UDBG_H
12#ifdef __KERNEL__
13
14#include <linux/compiler.h>
15#include <linux/init.h>
16
17extern void (*udbg_putc)(char c);
18extern int (*udbg_getc)(void);
19extern int (*udbg_getc_poll)(void);
20
21extern void udbg_puts(const char *s);
22extern int udbg_write(const char *s, int n);
23extern int udbg_read(char *buf, int buflen);
24
25extern void register_early_udbg_console(void);
26extern void udbg_printf(const char *fmt, ...)
27 __attribute__ ((format (printf, 1, 2)));
28extern void udbg_progress(char *s, unsigned short hex);
29
30extern void udbg_init_uart(void __iomem *comport, unsigned int speed,
31 unsigned int clock);
32extern unsigned int udbg_probe_uart_speed(void __iomem *comport,
33 unsigned int clock);
34
35struct device_node;
36extern void udbg_scc_init(int force_scc);
37extern int udbg_adb_init(int force_btext);
38extern void udbg_adb_init_early(void);
39
40extern void __init udbg_early_init(void);
41extern void __init udbg_init_debug_lpar(void);
42extern void __init udbg_init_pmac_realmode(void);
43extern void __init udbg_init_maple_realmode(void);
44extern void __init udbg_init_pas_realmode(void);
45extern void __init udbg_init_iseries(void);
46extern void __init udbg_init_rtas_panel(void);
47extern void __init udbg_init_rtas_console(void);
48extern void __init udbg_init_debug_beat(void);
49extern void __init udbg_init_btext(void);
50extern void __init udbg_init_44x_as1(void);
51extern void __init udbg_init_40x_realmode(void);
52extern void __init udbg_init_cpm(void);
53
54#endif /* __KERNEL__ */
55#endif /* _ASM_POWERPC_UDBG_H */
diff --git a/include/asm-powerpc/uic.h b/include/asm-powerpc/uic.h
deleted file mode 100644
index 970eb7e2186..00000000000
--- a/include/asm-powerpc/uic.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * include/asm-powerpc/uic.h
3 *
4 * IBM PPC4xx UIC external definitions and structure.
5 *
6 * Maintainer: David Gibson <dwg@au1.ibm.com>
7 * Copyright 2007 IBM Corporation.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14#ifndef _ASM_POWERPC_UIC_H
15#define _ASM_POWERPC_UIC_H
16
17#ifdef __KERNEL__
18
19extern void __init uic_init_tree(void);
20extern unsigned int uic_get_irq(void);
21
22#endif /* __KERNEL__ */
23#endif /* _ASM_POWERPC_UIC_H */
diff --git a/include/asm-powerpc/unaligned.h b/include/asm-powerpc/unaligned.h
deleted file mode 100644
index 5f1b1e3c213..00000000000
--- a/include/asm-powerpc/unaligned.h
+++ /dev/null
@@ -1,16 +0,0 @@
1#ifndef _ASM_POWERPC_UNALIGNED_H
2#define _ASM_POWERPC_UNALIGNED_H
3
4#ifdef __KERNEL__
5
6/*
7 * The PowerPC can do unaligned accesses itself in big endian mode.
8 */
9#include <linux/unaligned/access_ok.h>
10#include <linux/unaligned/generic.h>
11
12#define get_unaligned __get_unaligned_be
13#define put_unaligned __put_unaligned_be
14
15#endif /* __KERNEL__ */
16#endif /* _ASM_POWERPC_UNALIGNED_H */
diff --git a/include/asm-powerpc/uninorth.h b/include/asm-powerpc/uninorth.h
deleted file mode 100644
index f737732c386..00000000000
--- a/include/asm-powerpc/uninorth.h
+++ /dev/null
@@ -1,229 +0,0 @@
1/*
2 * uninorth.h: definitions for using the "UniNorth" host bridge chip
3 * from Apple. This chip is used on "Core99" machines
4 * This also includes U2 used on more recent MacRISC2/3
5 * machines and U3 (G5)
6 *
7 */
8#ifdef __KERNEL__
9#ifndef __ASM_UNINORTH_H__
10#define __ASM_UNINORTH_H__
11
12/*
13 * Uni-N and U3 config space reg. definitions
14 *
15 * (Little endian)
16 */
17
18/* Address ranges selection. This one should work with Bandit too */
19/* Not U3 */
20#define UNI_N_ADDR_SELECT 0x48
21#define UNI_N_ADDR_COARSE_MASK 0xffff0000 /* 256Mb regions at *0000000 */
22#define UNI_N_ADDR_FINE_MASK 0x0000ffff /* 16Mb regions at f*000000 */
23
24/* AGP registers */
25/* Not U3 */
26#define UNI_N_CFG_GART_BASE 0x8c
27#define UNI_N_CFG_AGP_BASE 0x90
28#define UNI_N_CFG_GART_CTRL 0x94
29#define UNI_N_CFG_INTERNAL_STATUS 0x98
30#define UNI_N_CFG_GART_DUMMY_PAGE 0xa4
31
32/* UNI_N_CFG_GART_CTRL bits definitions */
33#define UNI_N_CFG_GART_INVAL 0x00000001
34#define UNI_N_CFG_GART_ENABLE 0x00000100
35#define UNI_N_CFG_GART_2xRESET 0x00010000
36#define UNI_N_CFG_GART_DISSBADET 0x00020000
37/* The following seems to only be used only on U3 <j.glisse@gmail.com> */
38#define U3_N_CFG_GART_SYNCMODE 0x00040000
39#define U3_N_CFG_GART_PERFRD 0x00080000
40#define U3_N_CFG_GART_B2BGNT 0x00200000
41#define U3_N_CFG_GART_FASTDDR 0x00400000
42
43/* My understanding of UniNorth AGP as of UniNorth rev 1.0x,
44 * revision 1.5 (x4 AGP) may need further changes.
45 *
46 * AGP_BASE register contains the base address of the AGP aperture on
47 * the AGP bus. It doesn't seem to be visible to the CPU as of UniNorth 1.x,
48 * even if decoding of this address range is enabled in the address select
49 * register. Apparently, the only supported bases are 256Mb multiples
50 * (high 4 bits of that register).
51 *
52 * GART_BASE register appear to contain the physical address of the GART
53 * in system memory in the high address bits (page aligned), and the
54 * GART size in the low order bits (number of GART pages)
55 *
56 * The GART format itself is one 32bits word per physical memory page.
57 * This word contains, in little-endian format (!!!), the physical address
58 * of the page in the high bits, and what appears to be an "enable" bit
59 * in the LSB bit (0) that must be set to 1 when the entry is valid.
60 *
61 * Obviously, the GART is not cache coherent and so any change to it
62 * must be flushed to memory (or maybe just make the GART space non
63 * cachable). AGP memory itself doens't seem to be cache coherent neither.
64 *
65 * In order to invalidate the GART (which is probably necessary to inval
66 * the bridge internal TLBs), the following sequence has to be written,
67 * in order, to the GART_CTRL register:
68 *
69 * UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_INVAL
70 * UNI_N_CFG_GART_ENABLE
71 * UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_2xRESET
72 * UNI_N_CFG_GART_ENABLE
73 *
74 * As far as AGP "features" are concerned, it looks like fast write may
75 * not be supported but this has to be confirmed.
76 *
77 * Turning on AGP seem to require a double invalidate operation, one before
78 * setting the AGP command register, on after.
79 *
80 * Turning off AGP seems to require the following sequence: first wait
81 * for the AGP to be idle by reading the internal status register, then
82 * write in that order to the GART_CTRL register:
83 *
84 * UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_INVAL
85 * 0
86 * UNI_N_CFG_GART_2xRESET
87 * 0
88 */
89
90/*
91 * Uni-N memory mapped reg. definitions
92 *
93 * Those registers are Big-Endian !!
94 *
95 * Their meaning come from either Darwin and/or from experiments I made with
96 * the bootrom, I'm not sure about their exact meaning yet
97 *
98 */
99
100/* Version of the UniNorth chip */
101#define UNI_N_VERSION 0x0000 /* Known versions: 3,7 and 8 */
102
103#define UNI_N_VERSION_107 0x0003 /* 1.0.7 */
104#define UNI_N_VERSION_10A 0x0007 /* 1.0.10 */
105#define UNI_N_VERSION_150 0x0011 /* 1.5 */
106#define UNI_N_VERSION_200 0x0024 /* 2.0 */
107#define UNI_N_VERSION_PANGEA 0x00C0 /* Integrated U1 + K */
108#define UNI_N_VERSION_INTREPID 0x00D2 /* Integrated U2 + K */
109#define UNI_N_VERSION_300 0x0030 /* 3.0 (U3 on G5) */
110
111/* This register is used to enable/disable various clocks */
112#define UNI_N_CLOCK_CNTL 0x0020
113#define UNI_N_CLOCK_CNTL_PCI 0x00000001 /* PCI2 clock control */
114#define UNI_N_CLOCK_CNTL_GMAC 0x00000002 /* GMAC clock control */
115#define UNI_N_CLOCK_CNTL_FW 0x00000004 /* FireWire clock control */
116#define UNI_N_CLOCK_CNTL_ATA100 0x00000010 /* ATA-100 clock control (U2) */
117
118/* Power Management control */
119#define UNI_N_POWER_MGT 0x0030
120#define UNI_N_POWER_MGT_NORMAL 0x00
121#define UNI_N_POWER_MGT_IDLE2 0x01
122#define UNI_N_POWER_MGT_SLEEP 0x02
123
124/* This register is configured by Darwin depending on the UniN
125 * revision
126 */
127#define UNI_N_ARB_CTRL 0x0040
128#define UNI_N_ARB_CTRL_QACK_DELAY_SHIFT 15
129#define UNI_N_ARB_CTRL_QACK_DELAY_MASK 0x0e1f8000
130#define UNI_N_ARB_CTRL_QACK_DELAY 0x30
131#define UNI_N_ARB_CTRL_QACK_DELAY105 0x00
132
133/* This one _might_ return the CPU number of the CPU reading it;
134 * the bootROM decides whether to boot or to sleep/spinloop depending
135 * on this register beeing 0 or not
136 */
137#define UNI_N_CPU_NUMBER 0x0050
138
139/* This register appear to be read by the bootROM to decide what
140 * to do on a non-recoverable reset (powerup or wakeup)
141 */
142#define UNI_N_HWINIT_STATE 0x0070
143#define UNI_N_HWINIT_STATE_SLEEPING 0x01
144#define UNI_N_HWINIT_STATE_RUNNING 0x02
145/* This last bit appear to be used by the bootROM to know the second
146 * CPU has started and will enter it's sleep loop with IP=0
147 */
148#define UNI_N_HWINIT_STATE_CPU1_FLAG 0x10000000
149
150/* This register controls AACK delay, which is set when 2004 iBook/PowerBook
151 * is in low speed mode.
152 */
153#define UNI_N_AACK_DELAY 0x0100
154#define UNI_N_AACK_DELAY_ENABLE 0x00000001
155
156/* Clock status for Intrepid */
157#define UNI_N_CLOCK_STOP_STATUS0 0x0150
158#define UNI_N_CLOCK_STOPPED_EXTAGP 0x00200000
159#define UNI_N_CLOCK_STOPPED_AGPDEL 0x00100000
160#define UNI_N_CLOCK_STOPPED_I2S0_45_49 0x00080000
161#define UNI_N_CLOCK_STOPPED_I2S0_18 0x00040000
162#define UNI_N_CLOCK_STOPPED_I2S1_45_49 0x00020000
163#define UNI_N_CLOCK_STOPPED_I2S1_18 0x00010000
164#define UNI_N_CLOCK_STOPPED_TIMER 0x00008000
165#define UNI_N_CLOCK_STOPPED_SCC_RTCLK18 0x00004000
166#define UNI_N_CLOCK_STOPPED_SCC_RTCLK32 0x00002000
167#define UNI_N_CLOCK_STOPPED_SCC_VIA32 0x00001000
168#define UNI_N_CLOCK_STOPPED_SCC_SLOT0 0x00000800
169#define UNI_N_CLOCK_STOPPED_SCC_SLOT1 0x00000400
170#define UNI_N_CLOCK_STOPPED_SCC_SLOT2 0x00000200
171#define UNI_N_CLOCK_STOPPED_PCI_FBCLKO 0x00000100
172#define UNI_N_CLOCK_STOPPED_VEO0 0x00000080
173#define UNI_N_CLOCK_STOPPED_VEO1 0x00000040
174#define UNI_N_CLOCK_STOPPED_USB0 0x00000020
175#define UNI_N_CLOCK_STOPPED_USB1 0x00000010
176#define UNI_N_CLOCK_STOPPED_USB2 0x00000008
177#define UNI_N_CLOCK_STOPPED_32 0x00000004
178#define UNI_N_CLOCK_STOPPED_45 0x00000002
179#define UNI_N_CLOCK_STOPPED_49 0x00000001
180
181#define UNI_N_CLOCK_STOP_STATUS1 0x0160
182#define UNI_N_CLOCK_STOPPED_PLL4REF 0x00080000
183#define UNI_N_CLOCK_STOPPED_CPUDEL 0x00040000
184#define UNI_N_CLOCK_STOPPED_CPU 0x00020000
185#define UNI_N_CLOCK_STOPPED_BUF_REFCKO 0x00010000
186#define UNI_N_CLOCK_STOPPED_PCI2 0x00008000
187#define UNI_N_CLOCK_STOPPED_FW 0x00004000
188#define UNI_N_CLOCK_STOPPED_GB 0x00002000
189#define UNI_N_CLOCK_STOPPED_ATA66 0x00001000
190#define UNI_N_CLOCK_STOPPED_ATA100 0x00000800
191#define UNI_N_CLOCK_STOPPED_MAX 0x00000400
192#define UNI_N_CLOCK_STOPPED_PCI1 0x00000200
193#define UNI_N_CLOCK_STOPPED_KLPCI 0x00000100
194#define UNI_N_CLOCK_STOPPED_USB0PCI 0x00000080
195#define UNI_N_CLOCK_STOPPED_USB1PCI 0x00000040
196#define UNI_N_CLOCK_STOPPED_USB2PCI 0x00000020
197#define UNI_N_CLOCK_STOPPED_7PCI1 0x00000008
198#define UNI_N_CLOCK_STOPPED_AGP 0x00000004
199#define UNI_N_CLOCK_STOPPED_PCI0 0x00000002
200#define UNI_N_CLOCK_STOPPED_18 0x00000001
201
202/* Intrepid registe to OF do-platform-clockspreading */
203#define UNI_N_CLOCK_SPREADING 0x190
204
205/* Uninorth 1.5 rev. has additional perf. monitor registers at 0xf00-0xf50 */
206
207
208/*
209 * U3 specific registers
210 */
211
212
213/* U3 Toggle */
214#define U3_TOGGLE_REG 0x00e0
215#define U3_PMC_START_STOP 0x0001
216#define U3_MPIC_RESET 0x0002
217#define U3_MPIC_OUTPUT_ENABLE 0x0004
218
219/* U3 API PHY Config 1 */
220#define U3_API_PHY_CONFIG_1 0x23030
221
222/* U3 HyperTransport registers */
223#define U3_HT_CONFIG_BASE 0x70000
224#define U3_HT_LINK_COMMAND 0x100
225#define U3_HT_LINK_CONFIG 0x110
226#define U3_HT_LINK_FREQ 0x120
227
228#endif /* __ASM_UNINORTH_H__ */
229#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/unistd.h b/include/asm-powerpc/unistd.h
deleted file mode 100644
index e07d0c76ed7..00000000000
--- a/include/asm-powerpc/unistd.h
+++ /dev/null
@@ -1,398 +0,0 @@
1#ifndef _ASM_POWERPC_UNISTD_H_
2#define _ASM_POWERPC_UNISTD_H_
3
4/*
5 * This file contains the system call numbers.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#define __NR_restart_syscall 0
14#define __NR_exit 1
15#define __NR_fork 2
16#define __NR_read 3
17#define __NR_write 4
18#define __NR_open 5
19#define __NR_close 6
20#define __NR_waitpid 7
21#define __NR_creat 8
22#define __NR_link 9
23#define __NR_unlink 10
24#define __NR_execve 11
25#define __NR_chdir 12
26#define __NR_time 13
27#define __NR_mknod 14
28#define __NR_chmod 15
29#define __NR_lchown 16
30#define __NR_break 17
31#define __NR_oldstat 18
32#define __NR_lseek 19
33#define __NR_getpid 20
34#define __NR_mount 21
35#define __NR_umount 22
36#define __NR_setuid 23
37#define __NR_getuid 24
38#define __NR_stime 25
39#define __NR_ptrace 26
40#define __NR_alarm 27
41#define __NR_oldfstat 28
42#define __NR_pause 29
43#define __NR_utime 30
44#define __NR_stty 31
45#define __NR_gtty 32
46#define __NR_access 33
47#define __NR_nice 34
48#define __NR_ftime 35
49#define __NR_sync 36
50#define __NR_kill 37
51#define __NR_rename 38
52#define __NR_mkdir 39
53#define __NR_rmdir 40
54#define __NR_dup 41
55#define __NR_pipe 42
56#define __NR_times 43
57#define __NR_prof 44
58#define __NR_brk 45
59#define __NR_setgid 46
60#define __NR_getgid 47
61#define __NR_signal 48
62#define __NR_geteuid 49
63#define __NR_getegid 50
64#define __NR_acct 51
65#define __NR_umount2 52
66#define __NR_lock 53
67#define __NR_ioctl 54
68#define __NR_fcntl 55
69#define __NR_mpx 56
70#define __NR_setpgid 57
71#define __NR_ulimit 58
72#define __NR_oldolduname 59
73#define __NR_umask 60
74#define __NR_chroot 61
75#define __NR_ustat 62
76#define __NR_dup2 63
77#define __NR_getppid 64
78#define __NR_getpgrp 65
79#define __NR_setsid 66
80#define __NR_sigaction 67
81#define __NR_sgetmask 68
82#define __NR_ssetmask 69
83#define __NR_setreuid 70
84#define __NR_setregid 71
85#define __NR_sigsuspend 72
86#define __NR_sigpending 73
87#define __NR_sethostname 74
88#define __NR_setrlimit 75
89#define __NR_getrlimit 76
90#define __NR_getrusage 77
91#define __NR_gettimeofday 78
92#define __NR_settimeofday 79
93#define __NR_getgroups 80
94#define __NR_setgroups 81
95#define __NR_select 82
96#define __NR_symlink 83
97#define __NR_oldlstat 84
98#define __NR_readlink 85
99#define __NR_uselib 86
100#define __NR_swapon 87
101#define __NR_reboot 88
102#define __NR_readdir 89
103#define __NR_mmap 90
104#define __NR_munmap 91
105#define __NR_truncate 92
106#define __NR_ftruncate 93
107#define __NR_fchmod 94
108#define __NR_fchown 95
109#define __NR_getpriority 96
110#define __NR_setpriority 97
111#define __NR_profil 98
112#define __NR_statfs 99
113#define __NR_fstatfs 100
114#define __NR_ioperm 101
115#define __NR_socketcall 102
116#define __NR_syslog 103
117#define __NR_setitimer 104
118#define __NR_getitimer 105
119#define __NR_stat 106
120#define __NR_lstat 107
121#define __NR_fstat 108
122#define __NR_olduname 109
123#define __NR_iopl 110
124#define __NR_vhangup 111
125#define __NR_idle 112
126#define __NR_vm86 113
127#define __NR_wait4 114
128#define __NR_swapoff 115
129#define __NR_sysinfo 116
130#define __NR_ipc 117
131#define __NR_fsync 118
132#define __NR_sigreturn 119
133#define __NR_clone 120
134#define __NR_setdomainname 121
135#define __NR_uname 122
136#define __NR_modify_ldt 123
137#define __NR_adjtimex 124
138#define __NR_mprotect 125
139#define __NR_sigprocmask 126
140#define __NR_create_module 127
141#define __NR_init_module 128
142#define __NR_delete_module 129
143#define __NR_get_kernel_syms 130
144#define __NR_quotactl 131
145#define __NR_getpgid 132
146#define __NR_fchdir 133
147#define __NR_bdflush 134
148#define __NR_sysfs 135
149#define __NR_personality 136
150#define __NR_afs_syscall 137 /* Syscall for Andrew File System */
151#define __NR_setfsuid 138
152#define __NR_setfsgid 139
153#define __NR__llseek 140
154#define __NR_getdents 141
155#define __NR__newselect 142
156#define __NR_flock 143
157#define __NR_msync 144
158#define __NR_readv 145
159#define __NR_writev 146
160#define __NR_getsid 147
161#define __NR_fdatasync 148
162#define __NR__sysctl 149
163#define __NR_mlock 150
164#define __NR_munlock 151
165#define __NR_mlockall 152
166#define __NR_munlockall 153
167#define __NR_sched_setparam 154
168#define __NR_sched_getparam 155
169#define __NR_sched_setscheduler 156
170#define __NR_sched_getscheduler 157
171#define __NR_sched_yield 158
172#define __NR_sched_get_priority_max 159
173#define __NR_sched_get_priority_min 160
174#define __NR_sched_rr_get_interval 161
175#define __NR_nanosleep 162
176#define __NR_mremap 163
177#define __NR_setresuid 164
178#define __NR_getresuid 165
179#define __NR_query_module 166
180#define __NR_poll 167
181#define __NR_nfsservctl 168
182#define __NR_setresgid 169
183#define __NR_getresgid 170
184#define __NR_prctl 171
185#define __NR_rt_sigreturn 172
186#define __NR_rt_sigaction 173
187#define __NR_rt_sigprocmask 174
188#define __NR_rt_sigpending 175
189#define __NR_rt_sigtimedwait 176
190#define __NR_rt_sigqueueinfo 177
191#define __NR_rt_sigsuspend 178
192#define __NR_pread64 179
193#define __NR_pwrite64 180
194#define __NR_chown 181
195#define __NR_getcwd 182
196#define __NR_capget 183
197#define __NR_capset 184
198#define __NR_sigaltstack 185
199#define __NR_sendfile 186
200#define __NR_getpmsg 187 /* some people actually want streams */
201#define __NR_putpmsg 188 /* some people actually want streams */
202#define __NR_vfork 189
203#define __NR_ugetrlimit 190 /* SuS compliant getrlimit */
204#define __NR_readahead 191
205#ifndef __powerpc64__ /* these are 32-bit only */
206#define __NR_mmap2 192
207#define __NR_truncate64 193
208#define __NR_ftruncate64 194
209#define __NR_stat64 195
210#define __NR_lstat64 196
211#define __NR_fstat64 197
212#endif
213#define __NR_pciconfig_read 198
214#define __NR_pciconfig_write 199
215#define __NR_pciconfig_iobase 200
216#define __NR_multiplexer 201
217#define __NR_getdents64 202
218#define __NR_pivot_root 203
219#ifndef __powerpc64__
220#define __NR_fcntl64 204
221#endif
222#define __NR_madvise 205
223#define __NR_mincore 206
224#define __NR_gettid 207
225#define __NR_tkill 208
226#define __NR_setxattr 209
227#define __NR_lsetxattr 210
228#define __NR_fsetxattr 211
229#define __NR_getxattr 212
230#define __NR_lgetxattr 213
231#define __NR_fgetxattr 214
232#define __NR_listxattr 215
233#define __NR_llistxattr 216
234#define __NR_flistxattr 217
235#define __NR_removexattr 218
236#define __NR_lremovexattr 219
237#define __NR_fremovexattr 220
238#define __NR_futex 221
239#define __NR_sched_setaffinity 222
240#define __NR_sched_getaffinity 223
241/* 224 currently unused */
242#define __NR_tuxcall 225
243#ifndef __powerpc64__
244#define __NR_sendfile64 226
245#endif
246#define __NR_io_setup 227
247#define __NR_io_destroy 228
248#define __NR_io_getevents 229
249#define __NR_io_submit 230
250#define __NR_io_cancel 231
251#define __NR_set_tid_address 232
252#define __NR_fadvise64 233
253#define __NR_exit_group 234
254#define __NR_lookup_dcookie 235
255#define __NR_epoll_create 236
256#define __NR_epoll_ctl 237
257#define __NR_epoll_wait 238
258#define __NR_remap_file_pages 239
259#define __NR_timer_create 240
260#define __NR_timer_settime 241
261#define __NR_timer_gettime 242
262#define __NR_timer_getoverrun 243
263#define __NR_timer_delete 244
264#define __NR_clock_settime 245
265#define __NR_clock_gettime 246
266#define __NR_clock_getres 247
267#define __NR_clock_nanosleep 248
268#define __NR_swapcontext 249
269#define __NR_tgkill 250
270#define __NR_utimes 251
271#define __NR_statfs64 252
272#define __NR_fstatfs64 253
273#ifndef __powerpc64__
274#define __NR_fadvise64_64 254
275#endif
276#define __NR_rtas 255
277#define __NR_sys_debug_setcontext 256
278/* Number 257 is reserved for vserver */
279#define __NR_migrate_pages 258
280#define __NR_mbind 259
281#define __NR_get_mempolicy 260
282#define __NR_set_mempolicy 261
283#define __NR_mq_open 262
284#define __NR_mq_unlink 263
285#define __NR_mq_timedsend 264
286#define __NR_mq_timedreceive 265
287#define __NR_mq_notify 266
288#define __NR_mq_getsetattr 267
289#define __NR_kexec_load 268
290#define __NR_add_key 269
291#define __NR_request_key 270
292#define __NR_keyctl 271
293#define __NR_waitid 272
294#define __NR_ioprio_set 273
295#define __NR_ioprio_get 274
296#define __NR_inotify_init 275
297#define __NR_inotify_add_watch 276
298#define __NR_inotify_rm_watch 277
299#define __NR_spu_run 278
300#define __NR_spu_create 279
301#define __NR_pselect6 280
302#define __NR_ppoll 281
303#define __NR_unshare 282
304#define __NR_splice 283
305#define __NR_tee 284
306#define __NR_vmsplice 285
307#define __NR_openat 286
308#define __NR_mkdirat 287
309#define __NR_mknodat 288
310#define __NR_fchownat 289
311#define __NR_futimesat 290
312#ifdef __powerpc64__
313#define __NR_newfstatat 291
314#else
315#define __NR_fstatat64 291
316#endif
317#define __NR_unlinkat 292
318#define __NR_renameat 293
319#define __NR_linkat 294
320#define __NR_symlinkat 295
321#define __NR_readlinkat 296
322#define __NR_fchmodat 297
323#define __NR_faccessat 298
324#define __NR_get_robust_list 299
325#define __NR_set_robust_list 300
326#define __NR_move_pages 301
327#define __NR_getcpu 302
328#define __NR_epoll_pwait 303
329#define __NR_utimensat 304
330#define __NR_signalfd 305
331#define __NR_timerfd_create 306
332#define __NR_eventfd 307
333#define __NR_sync_file_range2 308
334#define __NR_fallocate 309
335#define __NR_subpage_prot 310
336#define __NR_timerfd_settime 311
337#define __NR_timerfd_gettime 312
338#define __NR_signalfd4 313
339#define __NR_eventfd2 314
340#define __NR_epoll_create1 315
341#define __NR_dup3 316
342#define __NR_pipe2 317
343#define __NR_inotify_init1 318
344
345#ifdef __KERNEL__
346
347#define __NR_syscalls 319
348
349#define __NR__exit __NR_exit
350#define NR_syscalls __NR_syscalls
351
352#ifndef __ASSEMBLY__
353
354#include <linux/types.h>
355#include <linux/compiler.h>
356#include <linux/linkage.h>
357
358#define __ARCH_WANT_IPC_PARSE_VERSION
359#define __ARCH_WANT_OLD_READDIR
360#define __ARCH_WANT_STAT64
361#define __ARCH_WANT_SYS_ALARM
362#define __ARCH_WANT_SYS_GETHOSTNAME
363#define __ARCH_WANT_SYS_PAUSE
364#define __ARCH_WANT_SYS_SGETMASK
365#define __ARCH_WANT_SYS_SIGNAL
366#define __ARCH_WANT_SYS_TIME
367#define __ARCH_WANT_SYS_UTIME
368#define __ARCH_WANT_SYS_WAITPID
369#define __ARCH_WANT_SYS_SOCKETCALL
370#define __ARCH_WANT_SYS_FADVISE64
371#define __ARCH_WANT_SYS_GETPGRP
372#define __ARCH_WANT_SYS_LLSEEK
373#define __ARCH_WANT_SYS_NICE
374#define __ARCH_WANT_SYS_OLD_GETRLIMIT
375#define __ARCH_WANT_SYS_OLDUMOUNT
376#define __ARCH_WANT_SYS_SIGPENDING
377#define __ARCH_WANT_SYS_SIGPROCMASK
378#define __ARCH_WANT_SYS_RT_SIGACTION
379#define __ARCH_WANT_SYS_RT_SIGSUSPEND
380#ifdef CONFIG_PPC32
381#define __ARCH_WANT_OLD_STAT
382#endif
383#ifdef CONFIG_PPC64
384#define __ARCH_WANT_COMPAT_SYS_TIME
385#define __ARCH_WANT_COMPAT_SYS_RT_SIGSUSPEND
386#define __ARCH_WANT_SYS_NEWFSTATAT
387#endif
388
389/*
390 * "Conditional" syscalls
391 */
392#define cond_syscall(x) \
393 asmlinkage long x (void) __attribute__((weak,alias("sys_ni_syscall")))
394
395#endif /* __ASSEMBLY__ */
396#endif /* __KERNEL__ */
397
398#endif /* _ASM_POWERPC_UNISTD_H_ */
diff --git a/include/asm-powerpc/user.h b/include/asm-powerpc/user.h
deleted file mode 100644
index 3fd4545dd74..00000000000
--- a/include/asm-powerpc/user.h
+++ /dev/null
@@ -1,51 +0,0 @@
1#ifndef _ASM_POWERPC_USER_H
2#define _ASM_POWERPC_USER_H
3
4#include <asm/ptrace.h>
5#include <asm/page.h>
6
7/*
8 * Adapted from <asm-alpha/user.h>
9 *
10 * Core file format: The core file is written in such a way that gdb
11 * can understand it and provide useful information to the user (under
12 * linux we use the `trad-core' bfd, NOT the osf-core). The file contents
13 * are as follows:
14 *
15 * upage: 1 page consisting of a user struct that tells gdb
16 * what is present in the file. Directly after this is a
17 * copy of the task_struct, which is currently not used by gdb,
18 * but it may come in handy at some point. All of the registers
19 * are stored as part of the upage. The upage should always be
20 * only one page long.
21 * data: The data segment follows next. We use current->end_text to
22 * current->brk to pick up all of the user variables, plus any memory
23 * that may have been sbrk'ed. No attempt is made to determine if a
24 * page is demand-zero or if a page is totally unused, we just cover
25 * the entire range. All of the addresses are rounded in such a way
26 * that an integral number of pages is written.
27 * stack: We need the stack information in order to get a meaningful
28 * backtrace. We need to write the data from usp to
29 * current->start_stack, so we round each of these in order to be able
30 * to write an integer number of pages.
31 */
32struct user {
33 struct pt_regs regs; /* entire machine state */
34 size_t u_tsize; /* text size (pages) */
35 size_t u_dsize; /* data size (pages) */
36 size_t u_ssize; /* stack size (pages) */
37 unsigned long start_code; /* text starting address */
38 unsigned long start_data; /* data starting address */
39 unsigned long start_stack; /* stack starting address */
40 long int signal; /* signal causing core dump */
41 unsigned long u_ar0; /* help gdb find registers */
42 unsigned long magic; /* identifies a core file */
43 char u_comm[32]; /* user command name */
44};
45
46#define NBPG PAGE_SIZE
47#define UPAGES 1
48#define HOST_TEXT_START_ADDR (u.start_code)
49#define HOST_DATA_START_ADDR (u.start_data)
50#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
51#endif /* _ASM_POWERPC_USER_H */
diff --git a/include/asm-powerpc/vdso.h b/include/asm-powerpc/vdso.h
deleted file mode 100644
index 26fc449bd98..00000000000
--- a/include/asm-powerpc/vdso.h
+++ /dev/null
@@ -1,78 +0,0 @@
1#ifndef __PPC64_VDSO_H__
2#define __PPC64_VDSO_H__
3
4#ifdef __KERNEL__
5
6/* Default link addresses for the vDSOs */
7#define VDSO32_LBASE 0x100000
8#define VDSO64_LBASE 0x100000
9
10/* Default map addresses */
11#define VDSO32_MBASE VDSO32_LBASE
12#define VDSO64_MBASE VDSO64_LBASE
13
14#define VDSO_VERSION_STRING LINUX_2.6.15
15
16/* Define if 64 bits VDSO has procedure descriptors */
17#undef VDS64_HAS_DESCRIPTORS
18
19#ifndef __ASSEMBLY__
20
21/* Offsets relative to thread->vdso_base */
22extern unsigned long vdso64_rt_sigtramp;
23extern unsigned long vdso32_sigtramp;
24extern unsigned long vdso32_rt_sigtramp;
25
26#else /* __ASSEMBLY__ */
27
28#ifdef __VDSO64__
29#ifdef VDS64_HAS_DESCRIPTORS
30#define V_FUNCTION_BEGIN(name) \
31 .globl name; \
32 .section ".opd","a"; \
33 .align 3; \
34 name: \
35 .quad .name,.TOC.@tocbase,0; \
36 .previous; \
37 .globl .name; \
38 .type .name,@function; \
39 .name: \
40
41#define V_FUNCTION_END(name) \
42 .size .name,.-.name;
43
44#define V_LOCAL_FUNC(name) (.name)
45
46#else /* VDS64_HAS_DESCRIPTORS */
47
48#define V_FUNCTION_BEGIN(name) \
49 .globl name; \
50 name: \
51
52#define V_FUNCTION_END(name) \
53 .size name,.-name;
54
55#define V_LOCAL_FUNC(name) (name)
56
57#endif /* VDS64_HAS_DESCRIPTORS */
58#endif /* __VDSO64__ */
59
60#ifdef __VDSO32__
61
62#define V_FUNCTION_BEGIN(name) \
63 .globl name; \
64 .type name,@function; \
65 name: \
66
67#define V_FUNCTION_END(name) \
68 .size name,.-name;
69
70#define V_LOCAL_FUNC(name) (name)
71
72#endif /* __VDSO32__ */
73
74#endif /* __ASSEMBLY__ */
75
76#endif /* __KERNEL__ */
77
78#endif /* __PPC64_VDSO_H__ */
diff --git a/include/asm-powerpc/vdso_datapage.h b/include/asm-powerpc/vdso_datapage.h
deleted file mode 100644
index f01393224b5..00000000000
--- a/include/asm-powerpc/vdso_datapage.h
+++ /dev/null
@@ -1,121 +0,0 @@
1#ifndef _VDSO_DATAPAGE_H
2#define _VDSO_DATAPAGE_H
3#ifdef __KERNEL__
4
5/*
6 * Copyright (C) 2002 Peter Bergner <bergner@vnet.ibm.com>, IBM
7 * Copyright (C) 2005 Benjamin Herrenschmidy <benh@kernel.crashing.org>,
8 * IBM Corp.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15
16
17/*
18 * Note about this structure:
19 *
20 * This structure was historically called systemcfg and exposed to
21 * userland via /proc/ppc64/systemcfg. Unfortunately, this became an
22 * ABI issue as some proprietary software started relying on being able
23 * to mmap() it, thus we have to keep the base layout at least for a
24 * few kernel versions.
25 *
26 * However, since ppc32 doesn't suffer from this backward handicap,
27 * a simpler version of the data structure is used there with only the
28 * fields actually used by the vDSO.
29 *
30 */
31
32/*
33 * If the major version changes we are incompatible.
34 * Minor version changes are a hint.
35 */
36#define SYSTEMCFG_MAJOR 1
37#define SYSTEMCFG_MINOR 1
38
39#ifndef __ASSEMBLY__
40
41#include <linux/unistd.h>
42
43#define SYSCALL_MAP_SIZE ((__NR_syscalls + 31) / 32)
44
45/*
46 * So here is the ppc64 backward compatible version
47 */
48
49#ifdef CONFIG_PPC64
50
51struct vdso_data {
52 __u8 eye_catcher[16]; /* Eyecatcher: SYSTEMCFG:PPC64 0x00 */
53 struct { /* Systemcfg version numbers */
54 __u32 major; /* Major number 0x10 */
55 __u32 minor; /* Minor number 0x14 */
56 } version;
57
58 /* Note about the platform flags: it now only contains the lpar
59 * bit. The actual platform number is dead and burried
60 */
61 __u32 platform; /* Platform flags 0x18 */
62 __u32 processor; /* Processor type 0x1C */
63 __u64 processorCount; /* # of physical processors 0x20 */
64 __u64 physicalMemorySize; /* Size of real memory(B) 0x28 */
65 __u64 tb_orig_stamp; /* Timebase at boot 0x30 */
66 __u64 tb_ticks_per_sec; /* Timebase tics / sec 0x38 */
67 __u64 tb_to_xs; /* Inverse of TB to 2^20 0x40 */
68 __u64 stamp_xsec; /* 0x48 */
69 __u64 tb_update_count; /* Timebase atomicity ctr 0x50 */
70 __u32 tz_minuteswest; /* Minutes west of Greenwich 0x58 */
71 __u32 tz_dsttime; /* Type of dst correction 0x5C */
72 __u32 dcache_size; /* L1 d-cache size 0x60 */
73 __u32 dcache_line_size; /* L1 d-cache line size 0x64 */
74 __u32 icache_size; /* L1 i-cache size 0x68 */
75 __u32 icache_line_size; /* L1 i-cache line size 0x6C */
76
77 /* those additional ones don't have to be located anywhere
78 * special as they were not part of the original systemcfg
79 */
80 __u32 dcache_block_size; /* L1 d-cache block size */
81 __u32 icache_block_size; /* L1 i-cache block size */
82 __u32 dcache_log_block_size; /* L1 d-cache log block size */
83 __u32 icache_log_block_size; /* L1 i-cache log block size */
84 __s32 wtom_clock_sec; /* Wall to monotonic clock */
85 __s32 wtom_clock_nsec;
86 __u32 syscall_map_64[SYSCALL_MAP_SIZE]; /* map of syscalls */
87 __u32 syscall_map_32[SYSCALL_MAP_SIZE]; /* map of syscalls */
88};
89
90#else /* CONFIG_PPC64 */
91
92/*
93 * And here is the simpler 32 bits version
94 */
95struct vdso_data {
96 __u64 tb_orig_stamp; /* Timebase at boot 0x30 */
97 __u64 tb_ticks_per_sec; /* Timebase tics / sec 0x38 */
98 __u64 tb_to_xs; /* Inverse of TB to 2^20 0x40 */
99 __u64 stamp_xsec; /* 0x48 */
100 __u32 tb_update_count; /* Timebase atomicity ctr 0x50 */
101 __u32 tz_minuteswest; /* Minutes west of Greenwich 0x58 */
102 __u32 tz_dsttime; /* Type of dst correction 0x5C */
103 __s32 wtom_clock_sec; /* Wall to monotonic clock */
104 __s32 wtom_clock_nsec;
105 __u32 syscall_map_32[SYSCALL_MAP_SIZE]; /* map of syscalls */
106 __u32 dcache_block_size; /* L1 d-cache block size */
107 __u32 icache_block_size; /* L1 i-cache block size */
108 __u32 dcache_log_block_size; /* L1 d-cache log block size */
109 __u32 icache_log_block_size; /* L1 i-cache log block size */
110};
111
112#endif /* CONFIG_PPC64 */
113
114#ifdef __KERNEL__
115extern struct vdso_data *vdso_data;
116#endif
117
118#endif /* __ASSEMBLY__ */
119
120#endif /* __KERNEL__ */
121#endif /* _SYSTEMCFG_H */
diff --git a/include/asm-powerpc/vga.h b/include/asm-powerpc/vga.h
deleted file mode 100644
index a2eac409c1e..00000000000
--- a/include/asm-powerpc/vga.h
+++ /dev/null
@@ -1,53 +0,0 @@
1#ifndef _ASM_POWERPC_VGA_H_
2#define _ASM_POWERPC_VGA_H_
3
4#ifdef __KERNEL__
5
6/*
7 * Access to VGA videoram
8 *
9 * (c) 1998 Martin Mares <mj@ucw.cz>
10 */
11
12
13#include <asm/io.h>
14
15
16#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_MDA_CONSOLE)
17
18#define VT_BUF_HAVE_RW
19/*
20 * These are only needed for supporting VGA or MDA text mode, which use little
21 * endian byte ordering.
22 * In other cases, we can optimize by using native byte ordering and
23 * <linux/vt_buffer.h> has already done the right job for us.
24 */
25
26static inline void scr_writew(u16 val, volatile u16 *addr)
27{
28 st_le16(addr, val);
29}
30
31static inline u16 scr_readw(volatile const u16 *addr)
32{
33 return ld_le16(addr);
34}
35
36#define VT_BUF_HAVE_MEMCPYW
37#define scr_memcpyw memcpy
38
39#endif /* !CONFIG_VGA_CONSOLE && !CONFIG_MDA_CONSOLE */
40
41extern unsigned long vgacon_remap_base;
42
43#ifdef __powerpc64__
44#define VGA_MAP_MEM(x,s) ((unsigned long) ioremap((x), s))
45#else
46#define VGA_MAP_MEM(x,s) (x + vgacon_remap_base)
47#endif
48
49#define vga_readb(x) (*(x))
50#define vga_writeb(x,y) (*(y) = (x))
51
52#endif /* __KERNEL__ */
53#endif /* _ASM_POWERPC_VGA_H_ */
diff --git a/include/asm-powerpc/vio.h b/include/asm-powerpc/vio.h
deleted file mode 100644
index 0a290a19594..00000000000
--- a/include/asm-powerpc/vio.h
+++ /dev/null
@@ -1,118 +0,0 @@
1/*
2 * IBM PowerPC Virtual I/O Infrastructure Support.
3 *
4 * Copyright (c) 2003 IBM Corp.
5 * Dave Engebretsen engebret@us.ibm.com
6 * Santiago Leon santil@us.ibm.com
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 */
13
14#ifndef _ASM_POWERPC_VIO_H
15#define _ASM_POWERPC_VIO_H
16#ifdef __KERNEL__
17
18#include <linux/init.h>
19#include <linux/errno.h>
20#include <linux/device.h>
21#include <linux/dma-mapping.h>
22#include <linux/mod_devicetable.h>
23
24#include <asm/hvcall.h>
25#include <asm/scatterlist.h>
26
27/*
28 * Architecture-specific constants for drivers to
29 * extract attributes of the device using vio_get_attribute()
30 */
31#define VETH_MAC_ADDR "local-mac-address"
32#define VETH_MCAST_FILTER_SIZE "ibm,mac-address-filters"
33
34/* End architecture-specific constants */
35
36#define h_vio_signal(ua, mode) \
37 plpar_hcall_norets(H_VIO_SIGNAL, ua, mode)
38
39#define VIO_IRQ_DISABLE 0UL
40#define VIO_IRQ_ENABLE 1UL
41
42/*
43 * VIO CMO minimum entitlement for all devices and spare entitlement
44 */
45#define VIO_CMO_MIN_ENT 1562624
46
47struct iommu_table;
48
49/**
50 * vio_dev - This structure is used to describe virtual I/O devices.
51 *
52 * @desired: set from return of driver's get_desired_dma() function
53 * @entitled: bytes of IO data that has been reserved for this device.
54 * @allocated: bytes of IO data currently in use by the device.
55 * @allocs_failed: number of DMA failures due to insufficient entitlement.
56 */
57struct vio_dev {
58 const char *name;
59 const char *type;
60 uint32_t unit_address;
61 unsigned int irq;
62 struct {
63 size_t desired;
64 size_t entitled;
65 size_t allocated;
66 atomic_t allocs_failed;
67 } cmo;
68 struct device dev;
69};
70
71struct vio_driver {
72 const struct vio_device_id *id_table;
73 int (*probe)(struct vio_dev *dev, const struct vio_device_id *id);
74 int (*remove)(struct vio_dev *dev);
75 /* A driver must have a get_desired_dma() function to
76 * be loaded in a CMO environment if it uses DMA.
77 */
78 unsigned long (*get_desired_dma)(struct vio_dev *dev);
79 struct device_driver driver;
80};
81
82extern int vio_register_driver(struct vio_driver *drv);
83extern void vio_unregister_driver(struct vio_driver *drv);
84
85extern int vio_cmo_entitlement_update(size_t);
86extern void vio_cmo_set_dev_desired(struct vio_dev *viodev, size_t desired);
87
88extern void __devinit vio_unregister_device(struct vio_dev *dev);
89
90struct device_node;
91
92extern struct vio_dev *vio_register_device_node(
93 struct device_node *node_vdev);
94extern const void *vio_get_attribute(struct vio_dev *vdev, char *which,
95 int *length);
96#ifdef CONFIG_PPC_PSERIES
97extern struct vio_dev *vio_find_node(struct device_node *vnode);
98extern int vio_enable_interrupts(struct vio_dev *dev);
99extern int vio_disable_interrupts(struct vio_dev *dev);
100#else
101static inline int vio_enable_interrupts(struct vio_dev *dev)
102{
103 return 0;
104}
105#endif
106
107static inline struct vio_driver *to_vio_driver(struct device_driver *drv)
108{
109 return container_of(drv, struct vio_driver, driver);
110}
111
112static inline struct vio_dev *to_vio_dev(struct device *dev)
113{
114 return container_of(dev, struct vio_dev, dev);
115}
116
117#endif /* __KERNEL__ */
118#endif /* _ASM_POWERPC_VIO_H */
diff --git a/include/asm-powerpc/xilinx_intc.h b/include/asm-powerpc/xilinx_intc.h
deleted file mode 100644
index 343612f8fec..00000000000
--- a/include/asm-powerpc/xilinx_intc.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * Xilinx intc external definitions
3 *
4 * Copyright 2007 Secret Lab Technologies Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11#ifndef _ASM_POWERPC_XILINX_INTC_H
12#define _ASM_POWERPC_XILINX_INTC_H
13
14#ifdef __KERNEL__
15
16extern void __init xilinx_intc_init_tree(void);
17extern unsigned int xilinx_intc_get_irq(void);
18
19#endif /* __KERNEL__ */
20#endif /* _ASM_POWERPC_XILINX_INTC_H */
diff --git a/include/asm-powerpc/xmon.h b/include/asm-powerpc/xmon.h
deleted file mode 100644
index 5eb8e599e5c..00000000000
--- a/include/asm-powerpc/xmon.h
+++ /dev/null
@@ -1,33 +0,0 @@
1#ifndef __ASM_POWERPC_XMON_H
2#define __ASM_POWERPC_XMON_H
3
4/*
5 * Copyrignt (C) 2006 IBM Corp
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#ifdef __KERNEL__
14
15#include <linux/irqreturn.h>
16
17#ifdef CONFIG_XMON
18extern void xmon_setup(void);
19extern void xmon_register_spus(struct list_head *list);
20struct pt_regs;
21extern int xmon(struct pt_regs *excp);
22extern irqreturn_t xmon_irq(int, void *);
23#else
24static inline void xmon_setup(void) { };
25static inline void xmon_register_spus(struct list_head *list) { };
26#endif
27
28#if defined(CONFIG_XMON) && defined(CONFIG_SMP)
29extern int cpus_are_in_xmon(void);
30#endif
31
32#endif /* __KERNEL __ */
33#endif /* __ASM_POWERPC_XMON_H */
diff --git a/include/asm-powerpc/xor.h b/include/asm-powerpc/xor.h
deleted file mode 100644
index c82eb12a5b1..00000000000
--- a/include/asm-powerpc/xor.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/xor.h>
diff --git a/include/asm-s390/Kbuild b/include/asm-s390/Kbuild
deleted file mode 100644
index 63a23415fba..00000000000
--- a/include/asm-s390/Kbuild
+++ /dev/null
@@ -1,15 +0,0 @@
1include include/asm-generic/Kbuild.asm
2
3header-y += dasd.h
4header-y += monwriter.h
5header-y += qeth.h
6header-y += tape390.h
7header-y += ucontext.h
8header-y += vtoc.h
9header-y += zcrypt.h
10header-y += chsc.h
11
12unifdef-y += cmb.h
13unifdef-y += debug.h
14unifdef-y += chpid.h
15unifdef-y += schid.h
diff --git a/include/asm-s390/airq.h b/include/asm-s390/airq.h
deleted file mode 100644
index 1ac80d6b058..00000000000
--- a/include/asm-s390/airq.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * include/asm-s390/airq.h
3 *
4 * Copyright IBM Corp. 2002,2007
5 * Author(s): Ingo Adlung <adlung@de.ibm.com>
6 * Cornelia Huck <cornelia.huck@de.ibm.com>
7 * Arnd Bergmann <arndb@de.ibm.com>
8 * Peter Oberparleiter <peter.oberparleiter@de.ibm.com>
9 */
10
11#ifndef _ASM_S390_AIRQ_H
12#define _ASM_S390_AIRQ_H
13
14typedef void (*adapter_int_handler_t)(void *, void *);
15
16void *s390_register_adapter_interrupt(adapter_int_handler_t, void *, u8);
17void s390_unregister_adapter_interrupt(void *, u8);
18
19#endif /* _ASM_S390_AIRQ_H */
diff --git a/include/asm-s390/appldata.h b/include/asm-s390/appldata.h
deleted file mode 100644
index 79283dac828..00000000000
--- a/include/asm-s390/appldata.h
+++ /dev/null
@@ -1,90 +0,0 @@
1/*
2 * include/asm-s390/appldata.h
3 *
4 * Copyright (C) IBM Corp. 2006
5 *
6 * Author(s): Melissa Howland <melissah@us.ibm.com>
7 */
8
9#ifndef _ASM_S390_APPLDATA_H
10#define _ASM_S390_APPLDATA_H
11
12#include <asm/io.h>
13
14#ifndef CONFIG_64BIT
15
16#define APPLDATA_START_INTERVAL_REC 0x00 /* Function codes for */
17#define APPLDATA_STOP_REC 0x01 /* DIAG 0xDC */
18#define APPLDATA_GEN_EVENT_REC 0x02
19#define APPLDATA_START_CONFIG_REC 0x03
20
21/*
22 * Parameter list for DIAGNOSE X'DC'
23 */
24struct appldata_parameter_list {
25 u16 diag; /* The DIAGNOSE code X'00DC' */
26 u8 function; /* The function code for the DIAGNOSE */
27 u8 parlist_length; /* Length of the parameter list */
28 u32 product_id_addr; /* Address of the 16-byte product ID */
29 u16 reserved;
30 u16 buffer_length; /* Length of the application data buffer */
31 u32 buffer_addr; /* Address of the application data buffer */
32} __attribute__ ((packed));
33
34#else /* CONFIG_64BIT */
35
36#define APPLDATA_START_INTERVAL_REC 0x80
37#define APPLDATA_STOP_REC 0x81
38#define APPLDATA_GEN_EVENT_REC 0x82
39#define APPLDATA_START_CONFIG_REC 0x83
40
41/*
42 * Parameter list for DIAGNOSE X'DC'
43 */
44struct appldata_parameter_list {
45 u16 diag;
46 u8 function;
47 u8 parlist_length;
48 u32 unused01;
49 u16 reserved;
50 u16 buffer_length;
51 u32 unused02;
52 u64 product_id_addr;
53 u64 buffer_addr;
54} __attribute__ ((packed));
55
56#endif /* CONFIG_64BIT */
57
58struct appldata_product_id {
59 char prod_nr[7]; /* product number */
60 u16 prod_fn; /* product function */
61 u8 record_nr; /* record number */
62 u16 version_nr; /* version */
63 u16 release_nr; /* release */
64 u16 mod_lvl; /* modification level */
65} __attribute__ ((packed));
66
67static inline int appldata_asm(struct appldata_product_id *id,
68 unsigned short fn, void *buffer,
69 unsigned short length)
70{
71 struct appldata_parameter_list parm_list;
72 int ry;
73
74 if (!MACHINE_IS_VM)
75 return -ENOSYS;
76 parm_list.diag = 0xdc;
77 parm_list.function = fn;
78 parm_list.parlist_length = sizeof(parm_list);
79 parm_list.buffer_length = length;
80 parm_list.product_id_addr = (unsigned long) id;
81 parm_list.buffer_addr = virt_to_phys(buffer);
82 asm volatile(
83 " diag %1,%0,0xdc"
84 : "=d" (ry)
85 : "d" (&parm_list), "m" (parm_list), "m" (*id)
86 : "cc");
87 return ry;
88}
89
90#endif /* _ASM_S390_APPLDATA_H */
diff --git a/include/asm-s390/atomic.h b/include/asm-s390/atomic.h
deleted file mode 100644
index 2d184655bc5..00000000000
--- a/include/asm-s390/atomic.h
+++ /dev/null
@@ -1,285 +0,0 @@
1#ifndef __ARCH_S390_ATOMIC__
2#define __ARCH_S390_ATOMIC__
3
4#include <linux/compiler.h>
5
6/*
7 * include/asm-s390/atomic.h
8 *
9 * S390 version
10 * Copyright (C) 1999-2005 IBM Deutschland Entwicklung GmbH, IBM Corporation
11 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
12 * Denis Joseph Barrow,
13 * Arnd Bergmann (arndb@de.ibm.com)
14 *
15 * Derived from "include/asm-i386/bitops.h"
16 * Copyright (C) 1992, Linus Torvalds
17 *
18 */
19
20/*
21 * Atomic operations that C can't guarantee us. Useful for
22 * resource counting etc..
23 * S390 uses 'Compare And Swap' for atomicity in SMP enviroment
24 */
25
26typedef struct {
27 int counter;
28} __attribute__ ((aligned (4))) atomic_t;
29#define ATOMIC_INIT(i) { (i) }
30
31#ifdef __KERNEL__
32
33#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
34
35#define __CS_LOOP(ptr, op_val, op_string) ({ \
36 typeof(ptr->counter) old_val, new_val; \
37 asm volatile( \
38 " l %0,%2\n" \
39 "0: lr %1,%0\n" \
40 op_string " %1,%3\n" \
41 " cs %0,%1,%2\n" \
42 " jl 0b" \
43 : "=&d" (old_val), "=&d" (new_val), \
44 "=Q" (((atomic_t *)(ptr))->counter) \
45 : "d" (op_val), "Q" (((atomic_t *)(ptr))->counter) \
46 : "cc", "memory"); \
47 new_val; \
48})
49
50#else /* __GNUC__ */
51
52#define __CS_LOOP(ptr, op_val, op_string) ({ \
53 typeof(ptr->counter) old_val, new_val; \
54 asm volatile( \
55 " l %0,0(%3)\n" \
56 "0: lr %1,%0\n" \
57 op_string " %1,%4\n" \
58 " cs %0,%1,0(%3)\n" \
59 " jl 0b" \
60 : "=&d" (old_val), "=&d" (new_val), \
61 "=m" (((atomic_t *)(ptr))->counter) \
62 : "a" (ptr), "d" (op_val), \
63 "m" (((atomic_t *)(ptr))->counter) \
64 : "cc", "memory"); \
65 new_val; \
66})
67
68#endif /* __GNUC__ */
69
70static inline int atomic_read(const atomic_t *v)
71{
72 barrier();
73 return v->counter;
74}
75
76static inline void atomic_set(atomic_t *v, int i)
77{
78 v->counter = i;
79 barrier();
80}
81
82static __inline__ int atomic_add_return(int i, atomic_t * v)
83{
84 return __CS_LOOP(v, i, "ar");
85}
86#define atomic_add(_i, _v) atomic_add_return(_i, _v)
87#define atomic_add_negative(_i, _v) (atomic_add_return(_i, _v) < 0)
88#define atomic_inc(_v) atomic_add_return(1, _v)
89#define atomic_inc_return(_v) atomic_add_return(1, _v)
90#define atomic_inc_and_test(_v) (atomic_add_return(1, _v) == 0)
91
92static __inline__ int atomic_sub_return(int i, atomic_t * v)
93{
94 return __CS_LOOP(v, i, "sr");
95}
96#define atomic_sub(_i, _v) atomic_sub_return(_i, _v)
97#define atomic_sub_and_test(_i, _v) (atomic_sub_return(_i, _v) == 0)
98#define atomic_dec(_v) atomic_sub_return(1, _v)
99#define atomic_dec_return(_v) atomic_sub_return(1, _v)
100#define atomic_dec_and_test(_v) (atomic_sub_return(1, _v) == 0)
101
102static __inline__ void atomic_clear_mask(unsigned long mask, atomic_t * v)
103{
104 __CS_LOOP(v, ~mask, "nr");
105}
106
107static __inline__ void atomic_set_mask(unsigned long mask, atomic_t * v)
108{
109 __CS_LOOP(v, mask, "or");
110}
111
112#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
113
114static __inline__ int atomic_cmpxchg(atomic_t *v, int old, int new)
115{
116#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
117 asm volatile(
118 " cs %0,%2,%1"
119 : "+d" (old), "=Q" (v->counter)
120 : "d" (new), "Q" (v->counter)
121 : "cc", "memory");
122#else /* __GNUC__ */
123 asm volatile(
124 " cs %0,%3,0(%2)"
125 : "+d" (old), "=m" (v->counter)
126 : "a" (v), "d" (new), "m" (v->counter)
127 : "cc", "memory");
128#endif /* __GNUC__ */
129 return old;
130}
131
132static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
133{
134 int c, old;
135 c = atomic_read(v);
136 for (;;) {
137 if (unlikely(c == u))
138 break;
139 old = atomic_cmpxchg(v, c, c + a);
140 if (likely(old == c))
141 break;
142 c = old;
143 }
144 return c != u;
145}
146
147#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
148
149#undef __CS_LOOP
150
151#ifdef __s390x__
152typedef struct {
153 long long counter;
154} __attribute__ ((aligned (8))) atomic64_t;
155#define ATOMIC64_INIT(i) { (i) }
156
157#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
158
159#define __CSG_LOOP(ptr, op_val, op_string) ({ \
160 typeof(ptr->counter) old_val, new_val; \
161 asm volatile( \
162 " lg %0,%2\n" \
163 "0: lgr %1,%0\n" \
164 op_string " %1,%3\n" \
165 " csg %0,%1,%2\n" \
166 " jl 0b" \
167 : "=&d" (old_val), "=&d" (new_val), \
168 "=Q" (((atomic_t *)(ptr))->counter) \
169 : "d" (op_val), "Q" (((atomic_t *)(ptr))->counter) \
170 : "cc", "memory" ); \
171 new_val; \
172})
173
174#else /* __GNUC__ */
175
176#define __CSG_LOOP(ptr, op_val, op_string) ({ \
177 typeof(ptr->counter) old_val, new_val; \
178 asm volatile( \
179 " lg %0,0(%3)\n" \
180 "0: lgr %1,%0\n" \
181 op_string " %1,%4\n" \
182 " csg %0,%1,0(%3)\n" \
183 " jl 0b" \
184 : "=&d" (old_val), "=&d" (new_val), \
185 "=m" (((atomic_t *)(ptr))->counter) \
186 : "a" (ptr), "d" (op_val), \
187 "m" (((atomic_t *)(ptr))->counter) \
188 : "cc", "memory" ); \
189 new_val; \
190})
191
192#endif /* __GNUC__ */
193
194static inline long long atomic64_read(const atomic64_t *v)
195{
196 barrier();
197 return v->counter;
198}
199
200static inline void atomic64_set(atomic64_t *v, long long i)
201{
202 v->counter = i;
203 barrier();
204}
205
206static __inline__ long long atomic64_add_return(long long i, atomic64_t * v)
207{
208 return __CSG_LOOP(v, i, "agr");
209}
210#define atomic64_add(_i, _v) atomic64_add_return(_i, _v)
211#define atomic64_add_negative(_i, _v) (atomic64_add_return(_i, _v) < 0)
212#define atomic64_inc(_v) atomic64_add_return(1, _v)
213#define atomic64_inc_return(_v) atomic64_add_return(1, _v)
214#define atomic64_inc_and_test(_v) (atomic64_add_return(1, _v) == 0)
215
216static __inline__ long long atomic64_sub_return(long long i, atomic64_t * v)
217{
218 return __CSG_LOOP(v, i, "sgr");
219}
220#define atomic64_sub(_i, _v) atomic64_sub_return(_i, _v)
221#define atomic64_sub_and_test(_i, _v) (atomic64_sub_return(_i, _v) == 0)
222#define atomic64_dec(_v) atomic64_sub_return(1, _v)
223#define atomic64_dec_return(_v) atomic64_sub_return(1, _v)
224#define atomic64_dec_and_test(_v) (atomic64_sub_return(1, _v) == 0)
225
226static __inline__ void atomic64_clear_mask(unsigned long mask, atomic64_t * v)
227{
228 __CSG_LOOP(v, ~mask, "ngr");
229}
230
231static __inline__ void atomic64_set_mask(unsigned long mask, atomic64_t * v)
232{
233 __CSG_LOOP(v, mask, "ogr");
234}
235
236#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
237
238static __inline__ long long atomic64_cmpxchg(atomic64_t *v,
239 long long old, long long new)
240{
241#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
242 asm volatile(
243 " csg %0,%2,%1"
244 : "+d" (old), "=Q" (v->counter)
245 : "d" (new), "Q" (v->counter)
246 : "cc", "memory");
247#else /* __GNUC__ */
248 asm volatile(
249 " csg %0,%3,0(%2)"
250 : "+d" (old), "=m" (v->counter)
251 : "a" (v), "d" (new), "m" (v->counter)
252 : "cc", "memory");
253#endif /* __GNUC__ */
254 return old;
255}
256
257static __inline__ int atomic64_add_unless(atomic64_t *v,
258 long long a, long long u)
259{
260 long long c, old;
261 c = atomic64_read(v);
262 for (;;) {
263 if (unlikely(c == u))
264 break;
265 old = atomic64_cmpxchg(v, c, c + a);
266 if (likely(old == c))
267 break;
268 c = old;
269 }
270 return c != u;
271}
272
273#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
274
275#undef __CSG_LOOP
276#endif
277
278#define smp_mb__before_atomic_dec() smp_mb()
279#define smp_mb__after_atomic_dec() smp_mb()
280#define smp_mb__before_atomic_inc() smp_mb()
281#define smp_mb__after_atomic_inc() smp_mb()
282
283#include <asm-generic/atomic.h>
284#endif /* __KERNEL__ */
285#endif /* __ARCH_S390_ATOMIC__ */
diff --git a/include/asm-s390/auxvec.h b/include/asm-s390/auxvec.h
deleted file mode 100644
index 0d340720fd9..00000000000
--- a/include/asm-s390/auxvec.h
+++ /dev/null
@@ -1,4 +0,0 @@
1#ifndef __ASMS390_AUXVEC_H
2#define __ASMS390_AUXVEC_H
3
4#endif
diff --git a/include/asm-s390/bitops.h b/include/asm-s390/bitops.h
deleted file mode 100644
index b4eb24ab5af..00000000000
--- a/include/asm-s390/bitops.h
+++ /dev/null
@@ -1,884 +0,0 @@
1#ifndef _S390_BITOPS_H
2#define _S390_BITOPS_H
3
4/*
5 * include/asm-s390/bitops.h
6 *
7 * S390 version
8 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
9 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
10 *
11 * Derived from "include/asm-i386/bitops.h"
12 * Copyright (C) 1992, Linus Torvalds
13 *
14 */
15
16#ifdef __KERNEL__
17
18#ifndef _LINUX_BITOPS_H
19#error only <linux/bitops.h> can be included directly
20#endif
21
22#include <linux/compiler.h>
23
24/*
25 * 32 bit bitops format:
26 * bit 0 is the LSB of *addr; bit 31 is the MSB of *addr;
27 * bit 32 is the LSB of *(addr+4). That combined with the
28 * big endian byte order on S390 give the following bit
29 * order in memory:
30 * 1f 1e 1d 1c 1b 1a 19 18 17 16 15 14 13 12 11 10 \
31 * 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00
32 * after that follows the next long with bit numbers
33 * 3f 3e 3d 3c 3b 3a 39 38 37 36 35 34 33 32 31 30
34 * 2f 2e 2d 2c 2b 2a 29 28 27 26 25 24 23 22 21 20
35 * The reason for this bit ordering is the fact that
36 * in the architecture independent code bits operations
37 * of the form "flags |= (1 << bitnr)" are used INTERMIXED
38 * with operation of the form "set_bit(bitnr, flags)".
39 *
40 * 64 bit bitops format:
41 * bit 0 is the LSB of *addr; bit 63 is the MSB of *addr;
42 * bit 64 is the LSB of *(addr+8). That combined with the
43 * big endian byte order on S390 give the following bit
44 * order in memory:
45 * 3f 3e 3d 3c 3b 3a 39 38 37 36 35 34 33 32 31 30
46 * 2f 2e 2d 2c 2b 2a 29 28 27 26 25 24 23 22 21 20
47 * 1f 1e 1d 1c 1b 1a 19 18 17 16 15 14 13 12 11 10
48 * 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00
49 * after that follows the next long with bit numbers
50 * 7f 7e 7d 7c 7b 7a 79 78 77 76 75 74 73 72 71 70
51 * 6f 6e 6d 6c 6b 6a 69 68 67 66 65 64 63 62 61 60
52 * 5f 5e 5d 5c 5b 5a 59 58 57 56 55 54 53 52 51 50
53 * 4f 4e 4d 4c 4b 4a 49 48 47 46 45 44 43 42 41 40
54 * The reason for this bit ordering is the fact that
55 * in the architecture independent code bits operations
56 * of the form "flags |= (1 << bitnr)" are used INTERMIXED
57 * with operation of the form "set_bit(bitnr, flags)".
58 */
59
60/* bitmap tables from arch/S390/kernel/bitmap.S */
61extern const char _oi_bitmap[];
62extern const char _ni_bitmap[];
63extern const char _zb_findmap[];
64extern const char _sb_findmap[];
65
66#ifndef __s390x__
67
68#define __BITOPS_ALIGN 3
69#define __BITOPS_WORDSIZE 32
70#define __BITOPS_OR "or"
71#define __BITOPS_AND "nr"
72#define __BITOPS_XOR "xr"
73
74#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
75
76#define __BITOPS_LOOP(__old, __new, __addr, __val, __op_string) \
77 asm volatile( \
78 " l %0,%2\n" \
79 "0: lr %1,%0\n" \
80 __op_string " %1,%3\n" \
81 " cs %0,%1,%2\n" \
82 " jl 0b" \
83 : "=&d" (__old), "=&d" (__new), \
84 "=Q" (*(unsigned long *) __addr) \
85 : "d" (__val), "Q" (*(unsigned long *) __addr) \
86 : "cc");
87
88#else /* __GNUC__ */
89
90#define __BITOPS_LOOP(__old, __new, __addr, __val, __op_string) \
91 asm volatile( \
92 " l %0,0(%4)\n" \
93 "0: lr %1,%0\n" \
94 __op_string " %1,%3\n" \
95 " cs %0,%1,0(%4)\n" \
96 " jl 0b" \
97 : "=&d" (__old), "=&d" (__new), \
98 "=m" (*(unsigned long *) __addr) \
99 : "d" (__val), "a" (__addr), \
100 "m" (*(unsigned long *) __addr) : "cc");
101
102#endif /* __GNUC__ */
103
104#else /* __s390x__ */
105
106#define __BITOPS_ALIGN 7
107#define __BITOPS_WORDSIZE 64
108#define __BITOPS_OR "ogr"
109#define __BITOPS_AND "ngr"
110#define __BITOPS_XOR "xgr"
111
112#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
113
114#define __BITOPS_LOOP(__old, __new, __addr, __val, __op_string) \
115 asm volatile( \
116 " lg %0,%2\n" \
117 "0: lgr %1,%0\n" \
118 __op_string " %1,%3\n" \
119 " csg %0,%1,%2\n" \
120 " jl 0b" \
121 : "=&d" (__old), "=&d" (__new), \
122 "=Q" (*(unsigned long *) __addr) \
123 : "d" (__val), "Q" (*(unsigned long *) __addr) \
124 : "cc");
125
126#else /* __GNUC__ */
127
128#define __BITOPS_LOOP(__old, __new, __addr, __val, __op_string) \
129 asm volatile( \
130 " lg %0,0(%4)\n" \
131 "0: lgr %1,%0\n" \
132 __op_string " %1,%3\n" \
133 " csg %0,%1,0(%4)\n" \
134 " jl 0b" \
135 : "=&d" (__old), "=&d" (__new), \
136 "=m" (*(unsigned long *) __addr) \
137 : "d" (__val), "a" (__addr), \
138 "m" (*(unsigned long *) __addr) : "cc");
139
140
141#endif /* __GNUC__ */
142
143#endif /* __s390x__ */
144
145#define __BITOPS_WORDS(bits) (((bits)+__BITOPS_WORDSIZE-1)/__BITOPS_WORDSIZE)
146#define __BITOPS_BARRIER() asm volatile("" : : : "memory")
147
148#ifdef CONFIG_SMP
149/*
150 * SMP safe set_bit routine based on compare and swap (CS)
151 */
152static inline void set_bit_cs(unsigned long nr, volatile unsigned long *ptr)
153{
154 unsigned long addr, old, new, mask;
155
156 addr = (unsigned long) ptr;
157 /* calculate address for CS */
158 addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
159 /* make OR mask */
160 mask = 1UL << (nr & (__BITOPS_WORDSIZE - 1));
161 /* Do the atomic update. */
162 __BITOPS_LOOP(old, new, addr, mask, __BITOPS_OR);
163}
164
165/*
166 * SMP safe clear_bit routine based on compare and swap (CS)
167 */
168static inline void clear_bit_cs(unsigned long nr, volatile unsigned long *ptr)
169{
170 unsigned long addr, old, new, mask;
171
172 addr = (unsigned long) ptr;
173 /* calculate address for CS */
174 addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
175 /* make AND mask */
176 mask = ~(1UL << (nr & (__BITOPS_WORDSIZE - 1)));
177 /* Do the atomic update. */
178 __BITOPS_LOOP(old, new, addr, mask, __BITOPS_AND);
179}
180
181/*
182 * SMP safe change_bit routine based on compare and swap (CS)
183 */
184static inline void change_bit_cs(unsigned long nr, volatile unsigned long *ptr)
185{
186 unsigned long addr, old, new, mask;
187
188 addr = (unsigned long) ptr;
189 /* calculate address for CS */
190 addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
191 /* make XOR mask */
192 mask = 1UL << (nr & (__BITOPS_WORDSIZE - 1));
193 /* Do the atomic update. */
194 __BITOPS_LOOP(old, new, addr, mask, __BITOPS_XOR);
195}
196
197/*
198 * SMP safe test_and_set_bit routine based on compare and swap (CS)
199 */
200static inline int
201test_and_set_bit_cs(unsigned long nr, volatile unsigned long *ptr)
202{
203 unsigned long addr, old, new, mask;
204
205 addr = (unsigned long) ptr;
206 /* calculate address for CS */
207 addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
208 /* make OR/test mask */
209 mask = 1UL << (nr & (__BITOPS_WORDSIZE - 1));
210 /* Do the atomic update. */
211 __BITOPS_LOOP(old, new, addr, mask, __BITOPS_OR);
212 __BITOPS_BARRIER();
213 return (old & mask) != 0;
214}
215
216/*
217 * SMP safe test_and_clear_bit routine based on compare and swap (CS)
218 */
219static inline int
220test_and_clear_bit_cs(unsigned long nr, volatile unsigned long *ptr)
221{
222 unsigned long addr, old, new, mask;
223
224 addr = (unsigned long) ptr;
225 /* calculate address for CS */
226 addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
227 /* make AND/test mask */
228 mask = ~(1UL << (nr & (__BITOPS_WORDSIZE - 1)));
229 /* Do the atomic update. */
230 __BITOPS_LOOP(old, new, addr, mask, __BITOPS_AND);
231 __BITOPS_BARRIER();
232 return (old ^ new) != 0;
233}
234
235/*
236 * SMP safe test_and_change_bit routine based on compare and swap (CS)
237 */
238static inline int
239test_and_change_bit_cs(unsigned long nr, volatile unsigned long *ptr)
240{
241 unsigned long addr, old, new, mask;
242
243 addr = (unsigned long) ptr;
244 /* calculate address for CS */
245 addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
246 /* make XOR/test mask */
247 mask = 1UL << (nr & (__BITOPS_WORDSIZE - 1));
248 /* Do the atomic update. */
249 __BITOPS_LOOP(old, new, addr, mask, __BITOPS_XOR);
250 __BITOPS_BARRIER();
251 return (old & mask) != 0;
252}
253#endif /* CONFIG_SMP */
254
255/*
256 * fast, non-SMP set_bit routine
257 */
258static inline void __set_bit(unsigned long nr, volatile unsigned long *ptr)
259{
260 unsigned long addr;
261
262 addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
263 asm volatile(
264 " oc 0(1,%1),0(%2)"
265 : "=m" (*(char *) addr) : "a" (addr),
266 "a" (_oi_bitmap + (nr & 7)), "m" (*(char *) addr) : "cc" );
267}
268
269static inline void
270__constant_set_bit(const unsigned long nr, volatile unsigned long *ptr)
271{
272 unsigned long addr;
273
274 addr = ((unsigned long) ptr) + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
275 *(unsigned char *) addr |= 1 << (nr & 7);
276}
277
278#define set_bit_simple(nr,addr) \
279(__builtin_constant_p((nr)) ? \
280 __constant_set_bit((nr),(addr)) : \
281 __set_bit((nr),(addr)) )
282
283/*
284 * fast, non-SMP clear_bit routine
285 */
286static inline void
287__clear_bit(unsigned long nr, volatile unsigned long *ptr)
288{
289 unsigned long addr;
290
291 addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
292 asm volatile(
293 " nc 0(1,%1),0(%2)"
294 : "=m" (*(char *) addr) : "a" (addr),
295 "a" (_ni_bitmap + (nr & 7)), "m" (*(char *) addr) : "cc");
296}
297
298static inline void
299__constant_clear_bit(const unsigned long nr, volatile unsigned long *ptr)
300{
301 unsigned long addr;
302
303 addr = ((unsigned long) ptr) + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
304 *(unsigned char *) addr &= ~(1 << (nr & 7));
305}
306
307#define clear_bit_simple(nr,addr) \
308(__builtin_constant_p((nr)) ? \
309 __constant_clear_bit((nr),(addr)) : \
310 __clear_bit((nr),(addr)) )
311
312/*
313 * fast, non-SMP change_bit routine
314 */
315static inline void __change_bit(unsigned long nr, volatile unsigned long *ptr)
316{
317 unsigned long addr;
318
319 addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
320 asm volatile(
321 " xc 0(1,%1),0(%2)"
322 : "=m" (*(char *) addr) : "a" (addr),
323 "a" (_oi_bitmap + (nr & 7)), "m" (*(char *) addr) : "cc" );
324}
325
326static inline void
327__constant_change_bit(const unsigned long nr, volatile unsigned long *ptr)
328{
329 unsigned long addr;
330
331 addr = ((unsigned long) ptr) + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
332 *(unsigned char *) addr ^= 1 << (nr & 7);
333}
334
335#define change_bit_simple(nr,addr) \
336(__builtin_constant_p((nr)) ? \
337 __constant_change_bit((nr),(addr)) : \
338 __change_bit((nr),(addr)) )
339
340/*
341 * fast, non-SMP test_and_set_bit routine
342 */
343static inline int
344test_and_set_bit_simple(unsigned long nr, volatile unsigned long *ptr)
345{
346 unsigned long addr;
347 unsigned char ch;
348
349 addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
350 ch = *(unsigned char *) addr;
351 asm volatile(
352 " oc 0(1,%1),0(%2)"
353 : "=m" (*(char *) addr)
354 : "a" (addr), "a" (_oi_bitmap + (nr & 7)),
355 "m" (*(char *) addr) : "cc", "memory");
356 return (ch >> (nr & 7)) & 1;
357}
358#define __test_and_set_bit(X,Y) test_and_set_bit_simple(X,Y)
359
360/*
361 * fast, non-SMP test_and_clear_bit routine
362 */
363static inline int
364test_and_clear_bit_simple(unsigned long nr, volatile unsigned long *ptr)
365{
366 unsigned long addr;
367 unsigned char ch;
368
369 addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
370 ch = *(unsigned char *) addr;
371 asm volatile(
372 " nc 0(1,%1),0(%2)"
373 : "=m" (*(char *) addr)
374 : "a" (addr), "a" (_ni_bitmap + (nr & 7)),
375 "m" (*(char *) addr) : "cc", "memory");
376 return (ch >> (nr & 7)) & 1;
377}
378#define __test_and_clear_bit(X,Y) test_and_clear_bit_simple(X,Y)
379
380/*
381 * fast, non-SMP test_and_change_bit routine
382 */
383static inline int
384test_and_change_bit_simple(unsigned long nr, volatile unsigned long *ptr)
385{
386 unsigned long addr;
387 unsigned char ch;
388
389 addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
390 ch = *(unsigned char *) addr;
391 asm volatile(
392 " xc 0(1,%1),0(%2)"
393 : "=m" (*(char *) addr)
394 : "a" (addr), "a" (_oi_bitmap + (nr & 7)),
395 "m" (*(char *) addr) : "cc", "memory");
396 return (ch >> (nr & 7)) & 1;
397}
398#define __test_and_change_bit(X,Y) test_and_change_bit_simple(X,Y)
399
400#ifdef CONFIG_SMP
401#define set_bit set_bit_cs
402#define clear_bit clear_bit_cs
403#define change_bit change_bit_cs
404#define test_and_set_bit test_and_set_bit_cs
405#define test_and_clear_bit test_and_clear_bit_cs
406#define test_and_change_bit test_and_change_bit_cs
407#else
408#define set_bit set_bit_simple
409#define clear_bit clear_bit_simple
410#define change_bit change_bit_simple
411#define test_and_set_bit test_and_set_bit_simple
412#define test_and_clear_bit test_and_clear_bit_simple
413#define test_and_change_bit test_and_change_bit_simple
414#endif
415
416
417/*
418 * This routine doesn't need to be atomic.
419 */
420
421static inline int __test_bit(unsigned long nr, const volatile unsigned long *ptr)
422{
423 unsigned long addr;
424 unsigned char ch;
425
426 addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
427 ch = *(volatile unsigned char *) addr;
428 return (ch >> (nr & 7)) & 1;
429}
430
431static inline int
432__constant_test_bit(unsigned long nr, const volatile unsigned long *addr) {
433 return (((volatile char *) addr)
434 [(nr^(__BITOPS_WORDSIZE-8))>>3] & (1<<(nr&7))) != 0;
435}
436
437#define test_bit(nr,addr) \
438(__builtin_constant_p((nr)) ? \
439 __constant_test_bit((nr),(addr)) : \
440 __test_bit((nr),(addr)) )
441
442/*
443 * Optimized find bit helper functions.
444 */
445
446/**
447 * __ffz_word_loop - find byte offset of first long != -1UL
448 * @addr: pointer to array of unsigned long
449 * @size: size of the array in bits
450 */
451static inline unsigned long __ffz_word_loop(const unsigned long *addr,
452 unsigned long size)
453{
454 typedef struct { long _[__BITOPS_WORDS(size)]; } addrtype;
455 unsigned long bytes = 0;
456
457 asm volatile(
458#ifndef __s390x__
459 " ahi %1,-1\n"
460 " sra %1,5\n"
461 " jz 1f\n"
462 "0: c %2,0(%0,%3)\n"
463 " jne 1f\n"
464 " la %0,4(%0)\n"
465 " brct %1,0b\n"
466 "1:\n"
467#else
468 " aghi %1,-1\n"
469 " srag %1,%1,6\n"
470 " jz 1f\n"
471 "0: cg %2,0(%0,%3)\n"
472 " jne 1f\n"
473 " la %0,8(%0)\n"
474 " brct %1,0b\n"
475 "1:\n"
476#endif
477 : "+&a" (bytes), "+&d" (size)
478 : "d" (-1UL), "a" (addr), "m" (*(addrtype *) addr)
479 : "cc" );
480 return bytes;
481}
482
483/**
484 * __ffs_word_loop - find byte offset of first long != 0UL
485 * @addr: pointer to array of unsigned long
486 * @size: size of the array in bits
487 */
488static inline unsigned long __ffs_word_loop(const unsigned long *addr,
489 unsigned long size)
490{
491 typedef struct { long _[__BITOPS_WORDS(size)]; } addrtype;
492 unsigned long bytes = 0;
493
494 asm volatile(
495#ifndef __s390x__
496 " ahi %1,-1\n"
497 " sra %1,5\n"
498 " jz 1f\n"
499 "0: c %2,0(%0,%3)\n"
500 " jne 1f\n"
501 " la %0,4(%0)\n"
502 " brct %1,0b\n"
503 "1:\n"
504#else
505 " aghi %1,-1\n"
506 " srag %1,%1,6\n"
507 " jz 1f\n"
508 "0: cg %2,0(%0,%3)\n"
509 " jne 1f\n"
510 " la %0,8(%0)\n"
511 " brct %1,0b\n"
512 "1:\n"
513#endif
514 : "+&a" (bytes), "+&a" (size)
515 : "d" (0UL), "a" (addr), "m" (*(addrtype *) addr)
516 : "cc" );
517 return bytes;
518}
519
520/**
521 * __ffz_word - add number of the first unset bit
522 * @nr: base value the bit number is added to
523 * @word: the word that is searched for unset bits
524 */
525static inline unsigned long __ffz_word(unsigned long nr, unsigned long word)
526{
527#ifdef __s390x__
528 if (likely((word & 0xffffffff) == 0xffffffff)) {
529 word >>= 32;
530 nr += 32;
531 }
532#endif
533 if (likely((word & 0xffff) == 0xffff)) {
534 word >>= 16;
535 nr += 16;
536 }
537 if (likely((word & 0xff) == 0xff)) {
538 word >>= 8;
539 nr += 8;
540 }
541 return nr + _zb_findmap[(unsigned char) word];
542}
543
544/**
545 * __ffs_word - add number of the first set bit
546 * @nr: base value the bit number is added to
547 * @word: the word that is searched for set bits
548 */
549static inline unsigned long __ffs_word(unsigned long nr, unsigned long word)
550{
551#ifdef __s390x__
552 if (likely((word & 0xffffffff) == 0)) {
553 word >>= 32;
554 nr += 32;
555 }
556#endif
557 if (likely((word & 0xffff) == 0)) {
558 word >>= 16;
559 nr += 16;
560 }
561 if (likely((word & 0xff) == 0)) {
562 word >>= 8;
563 nr += 8;
564 }
565 return nr + _sb_findmap[(unsigned char) word];
566}
567
568
569/**
570 * __load_ulong_be - load big endian unsigned long
571 * @p: pointer to array of unsigned long
572 * @offset: byte offset of source value in the array
573 */
574static inline unsigned long __load_ulong_be(const unsigned long *p,
575 unsigned long offset)
576{
577 p = (unsigned long *)((unsigned long) p + offset);
578 return *p;
579}
580
581/**
582 * __load_ulong_le - load little endian unsigned long
583 * @p: pointer to array of unsigned long
584 * @offset: byte offset of source value in the array
585 */
586static inline unsigned long __load_ulong_le(const unsigned long *p,
587 unsigned long offset)
588{
589 unsigned long word;
590
591 p = (unsigned long *)((unsigned long) p + offset);
592#ifndef __s390x__
593 asm volatile(
594 " ic %0,0(%1)\n"
595 " icm %0,2,1(%1)\n"
596 " icm %0,4,2(%1)\n"
597 " icm %0,8,3(%1)"
598 : "=&d" (word) : "a" (p), "m" (*p) : "cc");
599#else
600 asm volatile(
601 " lrvg %0,%1"
602 : "=d" (word) : "m" (*p) );
603#endif
604 return word;
605}
606
607/*
608 * The various find bit functions.
609 */
610
611/*
612 * ffz - find first zero in word.
613 * @word: The word to search
614 *
615 * Undefined if no zero exists, so code should check against ~0UL first.
616 */
617static inline unsigned long ffz(unsigned long word)
618{
619 return __ffz_word(0, word);
620}
621
622/**
623 * __ffs - find first bit in word.
624 * @word: The word to search
625 *
626 * Undefined if no bit exists, so code should check against 0 first.
627 */
628static inline unsigned long __ffs (unsigned long word)
629{
630 return __ffs_word(0, word);
631}
632
633/**
634 * ffs - find first bit set
635 * @x: the word to search
636 *
637 * This is defined the same way as
638 * the libc and compiler builtin ffs routines, therefore
639 * differs in spirit from the above ffz (man ffs).
640 */
641static inline int ffs(int x)
642{
643 if (!x)
644 return 0;
645 return __ffs_word(1, x);
646}
647
648/**
649 * find_first_zero_bit - find the first zero bit in a memory region
650 * @addr: The address to start the search at
651 * @size: The maximum size to search
652 *
653 * Returns the bit-number of the first zero bit, not the number of the byte
654 * containing a bit.
655 */
656static inline unsigned long find_first_zero_bit(const unsigned long *addr,
657 unsigned long size)
658{
659 unsigned long bytes, bits;
660
661 if (!size)
662 return 0;
663 bytes = __ffz_word_loop(addr, size);
664 bits = __ffz_word(bytes*8, __load_ulong_be(addr, bytes));
665 return (bits < size) ? bits : size;
666}
667
668/**
669 * find_first_bit - find the first set bit in a memory region
670 * @addr: The address to start the search at
671 * @size: The maximum size to search
672 *
673 * Returns the bit-number of the first set bit, not the number of the byte
674 * containing a bit.
675 */
676static inline unsigned long find_first_bit(const unsigned long * addr,
677 unsigned long size)
678{
679 unsigned long bytes, bits;
680
681 if (!size)
682 return 0;
683 bytes = __ffs_word_loop(addr, size);
684 bits = __ffs_word(bytes*8, __load_ulong_be(addr, bytes));
685 return (bits < size) ? bits : size;
686}
687
688/**
689 * find_next_zero_bit - find the first zero bit in a memory region
690 * @addr: The address to base the search on
691 * @offset: The bitnumber to start searching at
692 * @size: The maximum size to search
693 */
694static inline int find_next_zero_bit (const unsigned long * addr,
695 unsigned long size,
696 unsigned long offset)
697{
698 const unsigned long *p;
699 unsigned long bit, set;
700
701 if (offset >= size)
702 return size;
703 bit = offset & (__BITOPS_WORDSIZE - 1);
704 offset -= bit;
705 size -= offset;
706 p = addr + offset / __BITOPS_WORDSIZE;
707 if (bit) {
708 /*
709 * __ffz_word returns __BITOPS_WORDSIZE
710 * if no zero bit is present in the word.
711 */
712 set = __ffz_word(0, *p >> bit) + bit;
713 if (set >= size)
714 return size + offset;
715 if (set < __BITOPS_WORDSIZE)
716 return set + offset;
717 offset += __BITOPS_WORDSIZE;
718 size -= __BITOPS_WORDSIZE;
719 p++;
720 }
721 return offset + find_first_zero_bit(p, size);
722}
723
724/**
725 * find_next_bit - find the first set bit in a memory region
726 * @addr: The address to base the search on
727 * @offset: The bitnumber to start searching at
728 * @size: The maximum size to search
729 */
730static inline int find_next_bit (const unsigned long * addr,
731 unsigned long size,
732 unsigned long offset)
733{
734 const unsigned long *p;
735 unsigned long bit, set;
736
737 if (offset >= size)
738 return size;
739 bit = offset & (__BITOPS_WORDSIZE - 1);
740 offset -= bit;
741 size -= offset;
742 p = addr + offset / __BITOPS_WORDSIZE;
743 if (bit) {
744 /*
745 * __ffs_word returns __BITOPS_WORDSIZE
746 * if no one bit is present in the word.
747 */
748 set = __ffs_word(0, *p & (~0UL << bit));
749 if (set >= size)
750 return size + offset;
751 if (set < __BITOPS_WORDSIZE)
752 return set + offset;
753 offset += __BITOPS_WORDSIZE;
754 size -= __BITOPS_WORDSIZE;
755 p++;
756 }
757 return offset + find_first_bit(p, size);
758}
759
760/*
761 * Every architecture must define this function. It's the fastest
762 * way of searching a 140-bit bitmap where the first 100 bits are
763 * unlikely to be set. It's guaranteed that at least one of the 140
764 * bits is cleared.
765 */
766static inline int sched_find_first_bit(unsigned long *b)
767{
768 return find_first_bit(b, 140);
769}
770
771#include <asm-generic/bitops/fls.h>
772#include <asm-generic/bitops/__fls.h>
773#include <asm-generic/bitops/fls64.h>
774
775#include <asm-generic/bitops/hweight.h>
776#include <asm-generic/bitops/lock.h>
777
778/*
779 * ATTENTION: intel byte ordering convention for ext2 and minix !!
780 * bit 0 is the LSB of addr; bit 31 is the MSB of addr;
781 * bit 32 is the LSB of (addr+4).
782 * That combined with the little endian byte order of Intel gives the
783 * following bit order in memory:
784 * 07 06 05 04 03 02 01 00 15 14 13 12 11 10 09 08 \
785 * 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24
786 */
787
788#define ext2_set_bit(nr, addr) \
789 __test_and_set_bit((nr)^(__BITOPS_WORDSIZE - 8), (unsigned long *)addr)
790#define ext2_set_bit_atomic(lock, nr, addr) \
791 test_and_set_bit((nr)^(__BITOPS_WORDSIZE - 8), (unsigned long *)addr)
792#define ext2_clear_bit(nr, addr) \
793 __test_and_clear_bit((nr)^(__BITOPS_WORDSIZE - 8), (unsigned long *)addr)
794#define ext2_clear_bit_atomic(lock, nr, addr) \
795 test_and_clear_bit((nr)^(__BITOPS_WORDSIZE - 8), (unsigned long *)addr)
796#define ext2_test_bit(nr, addr) \
797 test_bit((nr)^(__BITOPS_WORDSIZE - 8), (unsigned long *)addr)
798
799static inline int ext2_find_first_zero_bit(void *vaddr, unsigned int size)
800{
801 unsigned long bytes, bits;
802
803 if (!size)
804 return 0;
805 bytes = __ffz_word_loop(vaddr, size);
806 bits = __ffz_word(bytes*8, __load_ulong_le(vaddr, bytes));
807 return (bits < size) ? bits : size;
808}
809
810static inline int ext2_find_next_zero_bit(void *vaddr, unsigned long size,
811 unsigned long offset)
812{
813 unsigned long *addr = vaddr, *p;
814 unsigned long bit, set;
815
816 if (offset >= size)
817 return size;
818 bit = offset & (__BITOPS_WORDSIZE - 1);
819 offset -= bit;
820 size -= offset;
821 p = addr + offset / __BITOPS_WORDSIZE;
822 if (bit) {
823 /*
824 * s390 version of ffz returns __BITOPS_WORDSIZE
825 * if no zero bit is present in the word.
826 */
827 set = ffz(__load_ulong_le(p, 0) >> bit) + bit;
828 if (set >= size)
829 return size + offset;
830 if (set < __BITOPS_WORDSIZE)
831 return set + offset;
832 offset += __BITOPS_WORDSIZE;
833 size -= __BITOPS_WORDSIZE;
834 p++;
835 }
836 return offset + ext2_find_first_zero_bit(p, size);
837}
838
839static inline unsigned long ext2_find_first_bit(void *vaddr,
840 unsigned long size)
841{
842 unsigned long bytes, bits;
843
844 if (!size)
845 return 0;
846 bytes = __ffs_word_loop(vaddr, size);
847 bits = __ffs_word(bytes*8, __load_ulong_le(vaddr, bytes));
848 return (bits < size) ? bits : size;
849}
850
851static inline int ext2_find_next_bit(void *vaddr, unsigned long size,
852 unsigned long offset)
853{
854 unsigned long *addr = vaddr, *p;
855 unsigned long bit, set;
856
857 if (offset >= size)
858 return size;
859 bit = offset & (__BITOPS_WORDSIZE - 1);
860 offset -= bit;
861 size -= offset;
862 p = addr + offset / __BITOPS_WORDSIZE;
863 if (bit) {
864 /*
865 * s390 version of ffz returns __BITOPS_WORDSIZE
866 * if no zero bit is present in the word.
867 */
868 set = ffs(__load_ulong_le(p, 0) >> bit) + bit;
869 if (set >= size)
870 return size + offset;
871 if (set < __BITOPS_WORDSIZE)
872 return set + offset;
873 offset += __BITOPS_WORDSIZE;
874 size -= __BITOPS_WORDSIZE;
875 p++;
876 }
877 return offset + ext2_find_first_bit(p, size);
878}
879
880#include <asm-generic/bitops/minix.h>
881
882#endif /* __KERNEL__ */
883
884#endif /* _S390_BITOPS_H */
diff --git a/include/asm-s390/bug.h b/include/asm-s390/bug.h
deleted file mode 100644
index 384e3621e34..00000000000
--- a/include/asm-s390/bug.h
+++ /dev/null
@@ -1,70 +0,0 @@
1#ifndef _ASM_S390_BUG_H
2#define _ASM_S390_BUG_H
3
4#include <linux/kernel.h>
5
6#ifdef CONFIG_BUG
7
8#ifdef CONFIG_64BIT
9#define S390_LONG ".quad"
10#else
11#define S390_LONG ".long"
12#endif
13
14#ifdef CONFIG_DEBUG_BUGVERBOSE
15
16#define __EMIT_BUG(x) do { \
17 asm volatile( \
18 "0: j 0b+2\n" \
19 "1:\n" \
20 ".section .rodata.str,\"aMS\",@progbits,1\n" \
21 "2: .asciz \""__FILE__"\"\n" \
22 ".previous\n" \
23 ".section __bug_table,\"a\"\n" \
24 "3:\t" S390_LONG "\t1b,2b\n" \
25 " .short %0,%1\n" \
26 " .org 3b+%2\n" \
27 ".previous\n" \
28 : : "i" (__LINE__), \
29 "i" (x), \
30 "i" (sizeof(struct bug_entry))); \
31} while (0)
32
33#else /* CONFIG_DEBUG_BUGVERBOSE */
34
35#define __EMIT_BUG(x) do { \
36 asm volatile( \
37 "0: j 0b+2\n" \
38 "1:\n" \
39 ".section __bug_table,\"a\"\n" \
40 "2:\t" S390_LONG "\t1b\n" \
41 " .short %0\n" \
42 " .org 2b+%1\n" \
43 ".previous\n" \
44 : : "i" (x), \
45 "i" (sizeof(struct bug_entry))); \
46} while (0)
47
48#endif /* CONFIG_DEBUG_BUGVERBOSE */
49
50#define BUG() __EMIT_BUG(0)
51
52#define WARN_ON(x) ({ \
53 int __ret_warn_on = !!(x); \
54 if (__builtin_constant_p(__ret_warn_on)) { \
55 if (__ret_warn_on) \
56 __EMIT_BUG(BUGFLAG_WARNING); \
57 } else { \
58 if (unlikely(__ret_warn_on)) \
59 __EMIT_BUG(BUGFLAG_WARNING); \
60 } \
61 unlikely(__ret_warn_on); \
62})
63
64#define HAVE_ARCH_BUG
65#define HAVE_ARCH_WARN_ON
66#endif /* CONFIG_BUG */
67
68#include <asm-generic/bug.h>
69
70#endif /* _ASM_S390_BUG_H */
diff --git a/include/asm-s390/bugs.h b/include/asm-s390/bugs.h
deleted file mode 100644
index 011f1e6a2a6..00000000000
--- a/include/asm-s390/bugs.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * include/asm-s390/bugs.h
3 *
4 * S390 version
5 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
7 *
8 * Derived from "include/asm-i386/bugs.h"
9 * Copyright (C) 1994 Linus Torvalds
10 */
11
12/*
13 * This is included by init/main.c to check for architecture-dependent bugs.
14 *
15 * Needs:
16 * void check_bugs(void);
17 */
18
19static inline void check_bugs(void)
20{
21 /* s390 has no bugs ... */
22}
diff --git a/include/asm-s390/byteorder.h b/include/asm-s390/byteorder.h
deleted file mode 100644
index 1fe2492baa8..00000000000
--- a/include/asm-s390/byteorder.h
+++ /dev/null
@@ -1,125 +0,0 @@
1#ifndef _S390_BYTEORDER_H
2#define _S390_BYTEORDER_H
3
4/*
5 * include/asm-s390/byteorder.h
6 *
7 * S390 version
8 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
9 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
10 */
11
12#include <asm/types.h>
13
14#ifdef __GNUC__
15
16#ifdef __s390x__
17static inline __u64 ___arch__swab64p(const __u64 *x)
18{
19 __u64 result;
20
21 asm volatile("lrvg %0,%1" : "=d" (result) : "m" (*x));
22 return result;
23}
24
25static inline __u64 ___arch__swab64(__u64 x)
26{
27 __u64 result;
28
29 asm volatile("lrvgr %0,%1" : "=d" (result) : "d" (x));
30 return result;
31}
32
33static inline void ___arch__swab64s(__u64 *x)
34{
35 *x = ___arch__swab64p(x);
36}
37#endif /* __s390x__ */
38
39static inline __u32 ___arch__swab32p(const __u32 *x)
40{
41 __u32 result;
42
43 asm volatile(
44#ifndef __s390x__
45 " icm %0,8,3(%1)\n"
46 " icm %0,4,2(%1)\n"
47 " icm %0,2,1(%1)\n"
48 " ic %0,0(%1)"
49 : "=&d" (result) : "a" (x), "m" (*x) : "cc");
50#else /* __s390x__ */
51 " lrv %0,%1"
52 : "=d" (result) : "m" (*x));
53#endif /* __s390x__ */
54 return result;
55}
56
57static inline __u32 ___arch__swab32(__u32 x)
58{
59#ifndef __s390x__
60 return ___arch__swab32p(&x);
61#else /* __s390x__ */
62 __u32 result;
63
64 asm volatile("lrvr %0,%1" : "=d" (result) : "d" (x));
65 return result;
66#endif /* __s390x__ */
67}
68
69static __inline__ void ___arch__swab32s(__u32 *x)
70{
71 *x = ___arch__swab32p(x);
72}
73
74static __inline__ __u16 ___arch__swab16p(const __u16 *x)
75{
76 __u16 result;
77
78 asm volatile(
79#ifndef __s390x__
80 " icm %0,2,1(%1)\n"
81 " ic %0,0(%1)\n"
82 : "=&d" (result) : "a" (x), "m" (*x) : "cc");
83#else /* __s390x__ */
84 " lrvh %0,%1"
85 : "=d" (result) : "m" (*x));
86#endif /* __s390x__ */
87 return result;
88}
89
90static __inline__ __u16 ___arch__swab16(__u16 x)
91{
92 return ___arch__swab16p(&x);
93}
94
95static __inline__ void ___arch__swab16s(__u16 *x)
96{
97 *x = ___arch__swab16p(x);
98}
99
100#ifdef __s390x__
101#define __arch__swab64(x) ___arch__swab64(x)
102#define __arch__swab64p(x) ___arch__swab64p(x)
103#define __arch__swab64s(x) ___arch__swab64s(x)
104#endif /* __s390x__ */
105#define __arch__swab32(x) ___arch__swab32(x)
106#define __arch__swab16(x) ___arch__swab16(x)
107#define __arch__swab32p(x) ___arch__swab32p(x)
108#define __arch__swab16p(x) ___arch__swab16p(x)
109#define __arch__swab32s(x) ___arch__swab32s(x)
110#define __arch__swab16s(x) ___arch__swab16s(x)
111
112#ifndef __s390x__
113#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
114# define __BYTEORDER_HAS_U64__
115# define __SWAB_64_THRU_32__
116#endif
117#else /* __s390x__ */
118#define __BYTEORDER_HAS_U64__
119#endif /* __s390x__ */
120
121#endif /* __GNUC__ */
122
123#include <linux/byteorder/big_endian.h>
124
125#endif /* _S390_BYTEORDER_H */
diff --git a/include/asm-s390/cache.h b/include/asm-s390/cache.h
deleted file mode 100644
index 9b866816863..00000000000
--- a/include/asm-s390/cache.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * include/asm-s390/cache.h
3 *
4 * S390 version
5 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 *
7 * Derived from "include/asm-i386/cache.h"
8 * Copyright (C) 1992, Linus Torvalds
9 */
10
11#ifndef __ARCH_S390_CACHE_H
12#define __ARCH_S390_CACHE_H
13
14#define L1_CACHE_BYTES 256
15#define L1_CACHE_SHIFT 8
16
17#define __read_mostly __attribute__((__section__(".data.read_mostly")))
18
19#endif
diff --git a/include/asm-s390/cacheflush.h b/include/asm-s390/cacheflush.h
deleted file mode 100644
index 49d5af916d0..00000000000
--- a/include/asm-s390/cacheflush.h
+++ /dev/null
@@ -1,31 +0,0 @@
1#ifndef _S390_CACHEFLUSH_H
2#define _S390_CACHEFLUSH_H
3
4/* Keep includes the same across arches. */
5#include <linux/mm.h>
6
7/* Caches aren't brain-dead on the s390. */
8#define flush_cache_all() do { } while (0)
9#define flush_cache_mm(mm) do { } while (0)
10#define flush_cache_dup_mm(mm) do { } while (0)
11#define flush_cache_range(vma, start, end) do { } while (0)
12#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
13#define flush_dcache_page(page) do { } while (0)
14#define flush_dcache_mmap_lock(mapping) do { } while (0)
15#define flush_dcache_mmap_unlock(mapping) do { } while (0)
16#define flush_icache_range(start, end) do { } while (0)
17#define flush_icache_page(vma,pg) do { } while (0)
18#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
19#define flush_cache_vmap(start, end) do { } while (0)
20#define flush_cache_vunmap(start, end) do { } while (0)
21
22#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
23 memcpy(dst, src, len)
24#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
25 memcpy(dst, src, len)
26
27#ifdef CONFIG_DEBUG_PAGEALLOC
28void kernel_map_pages(struct page *page, int numpages, int enable);
29#endif
30
31#endif /* _S390_CACHEFLUSH_H */
diff --git a/include/asm-s390/ccwdev.h b/include/asm-s390/ccwdev.h
deleted file mode 100644
index ba007d8df94..00000000000
--- a/include/asm-s390/ccwdev.h
+++ /dev/null
@@ -1,192 +0,0 @@
1/*
2 * include/asm-s390/ccwdev.h
3 * include/asm-s390x/ccwdev.h
4 *
5 * Copyright (C) 2002 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Arnd Bergmann <arndb@de.ibm.com>
7 *
8 * Interface for CCW device drivers
9 */
10#ifndef _S390_CCWDEV_H_
11#define _S390_CCWDEV_H_
12
13#include <linux/device.h>
14#include <linux/mod_devicetable.h>
15#include <asm/fcx.h>
16
17/* structs from asm/cio.h */
18struct irb;
19struct ccw1;
20struct ccw_dev_id;
21
22/* simplified initializers for struct ccw_device:
23 * CCW_DEVICE and CCW_DEVICE_DEVTYPE initialize one
24 * entry in your MODULE_DEVICE_TABLE and set the match_flag correctly */
25#define CCW_DEVICE(cu, cum) \
26 .cu_type=(cu), .cu_model=(cum), \
27 .match_flags=(CCW_DEVICE_ID_MATCH_CU_TYPE \
28 | (cum ? CCW_DEVICE_ID_MATCH_CU_MODEL : 0))
29
30#define CCW_DEVICE_DEVTYPE(cu, cum, dev, devm) \
31 .cu_type=(cu), .cu_model=(cum), .dev_type=(dev), .dev_model=(devm),\
32 .match_flags=CCW_DEVICE_ID_MATCH_CU_TYPE \
33 | ((cum) ? CCW_DEVICE_ID_MATCH_CU_MODEL : 0) \
34 | CCW_DEVICE_ID_MATCH_DEVICE_TYPE \
35 | ((devm) ? CCW_DEVICE_ID_MATCH_DEVICE_MODEL : 0)
36
37/* scan through an array of device ids and return the first
38 * entry that matches the device.
39 *
40 * the array must end with an entry containing zero match_flags
41 */
42static inline const struct ccw_device_id *
43ccw_device_id_match(const struct ccw_device_id *array,
44 const struct ccw_device_id *match)
45{
46 const struct ccw_device_id *id = array;
47
48 for (id = array; id->match_flags; id++) {
49 if ((id->match_flags & CCW_DEVICE_ID_MATCH_CU_TYPE)
50 && (id->cu_type != match->cu_type))
51 continue;
52
53 if ((id->match_flags & CCW_DEVICE_ID_MATCH_CU_MODEL)
54 && (id->cu_model != match->cu_model))
55 continue;
56
57 if ((id->match_flags & CCW_DEVICE_ID_MATCH_DEVICE_TYPE)
58 && (id->dev_type != match->dev_type))
59 continue;
60
61 if ((id->match_flags & CCW_DEVICE_ID_MATCH_DEVICE_MODEL)
62 && (id->dev_model != match->dev_model))
63 continue;
64
65 return id;
66 }
67
68 return NULL;
69}
70
71/**
72 * struct ccw_device - channel attached device
73 * @ccwlock: pointer to device lock
74 * @id: id of this device
75 * @drv: ccw driver for this device
76 * @dev: embedded device structure
77 * @online: online status of device
78 * @handler: interrupt handler
79 *
80 * @handler is a member of the device rather than the driver since a driver
81 * can have different interrupt handlers for different ccw devices
82 * (multi-subchannel drivers).
83 */
84struct ccw_device {
85 spinlock_t *ccwlock;
86/* private: */
87 struct ccw_device_private *private; /* cio private information */
88/* public: */
89 struct ccw_device_id id;
90 struct ccw_driver *drv;
91 struct device dev;
92 int online;
93 void (*handler) (struct ccw_device *, unsigned long, struct irb *);
94};
95
96
97/**
98 * struct ccw driver - device driver for channel attached devices
99 * @owner: owning module
100 * @ids: ids supported by this driver
101 * @probe: function called on probe
102 * @remove: function called on remove
103 * @set_online: called when setting device online
104 * @set_offline: called when setting device offline
105 * @notify: notify driver of device state changes
106 * @shutdown: called at device shutdown
107 * @driver: embedded device driver structure
108 * @name: device driver name
109 */
110struct ccw_driver {
111 struct module *owner;
112 struct ccw_device_id *ids;
113 int (*probe) (struct ccw_device *);
114 void (*remove) (struct ccw_device *);
115 int (*set_online) (struct ccw_device *);
116 int (*set_offline) (struct ccw_device *);
117 int (*notify) (struct ccw_device *, int);
118 void (*shutdown) (struct ccw_device *);
119 struct device_driver driver;
120 char *name;
121};
122
123extern struct ccw_device *get_ccwdev_by_busid(struct ccw_driver *cdrv,
124 const char *bus_id);
125
126/* devices drivers call these during module load and unload.
127 * When a driver is registered, its probe method is called
128 * when new devices for its type pop up */
129extern int ccw_driver_register (struct ccw_driver *driver);
130extern void ccw_driver_unregister (struct ccw_driver *driver);
131
132struct ccw1;
133
134extern int ccw_device_set_options_mask(struct ccw_device *, unsigned long);
135extern int ccw_device_set_options(struct ccw_device *, unsigned long);
136extern void ccw_device_clear_options(struct ccw_device *, unsigned long);
137
138/* Allow for i/o completion notification after primary interrupt status. */
139#define CCWDEV_EARLY_NOTIFICATION 0x0001
140/* Report all interrupt conditions. */
141#define CCWDEV_REPORT_ALL 0x0002
142/* Try to perform path grouping. */
143#define CCWDEV_DO_PATHGROUP 0x0004
144/* Allow forced onlining of boxed devices. */
145#define CCWDEV_ALLOW_FORCE 0x0008
146
147extern int ccw_device_start(struct ccw_device *, struct ccw1 *,
148 unsigned long, __u8, unsigned long);
149extern int ccw_device_start_timeout(struct ccw_device *, struct ccw1 *,
150 unsigned long, __u8, unsigned long, int);
151extern int ccw_device_start_key(struct ccw_device *, struct ccw1 *,
152 unsigned long, __u8, __u8, unsigned long);
153extern int ccw_device_start_timeout_key(struct ccw_device *, struct ccw1 *,
154 unsigned long, __u8, __u8,
155 unsigned long, int);
156
157
158extern int ccw_device_resume(struct ccw_device *);
159extern int ccw_device_halt(struct ccw_device *, unsigned long);
160extern int ccw_device_clear(struct ccw_device *, unsigned long);
161int ccw_device_tm_start_key(struct ccw_device *cdev, struct tcw *tcw,
162 unsigned long intparm, u8 lpm, u8 key);
163int ccw_device_tm_start_key(struct ccw_device *, struct tcw *,
164 unsigned long, u8, u8);
165int ccw_device_tm_start_timeout_key(struct ccw_device *, struct tcw *,
166 unsigned long, u8, u8, int);
167int ccw_device_tm_start(struct ccw_device *, struct tcw *,
168 unsigned long, u8);
169int ccw_device_tm_start_timeout(struct ccw_device *, struct tcw *,
170 unsigned long, u8, int);
171int ccw_device_tm_intrg(struct ccw_device *cdev);
172
173extern int ccw_device_set_online(struct ccw_device *cdev);
174extern int ccw_device_set_offline(struct ccw_device *cdev);
175
176
177extern struct ciw *ccw_device_get_ciw(struct ccw_device *, __u32 cmd);
178extern __u8 ccw_device_get_path_mask(struct ccw_device *);
179extern void ccw_device_get_id(struct ccw_device *, struct ccw_dev_id *);
180
181#define get_ccwdev_lock(x) (x)->ccwlock
182
183#define to_ccwdev(n) container_of(n, struct ccw_device, dev)
184#define to_ccwdrv(n) container_of(n, struct ccw_driver, driver)
185
186extern struct ccw_device *ccw_device_probe_console(void);
187
188// FIXME: these have to go
189extern int _ccw_device_get_subchannel_number(struct ccw_device *);
190
191extern void *ccw_device_get_chp_desc(struct ccw_device *, int);
192#endif /* _S390_CCWDEV_H_ */
diff --git a/include/asm-s390/ccwgroup.h b/include/asm-s390/ccwgroup.h
deleted file mode 100644
index a27f68985a7..00000000000
--- a/include/asm-s390/ccwgroup.h
+++ /dev/null
@@ -1,69 +0,0 @@
1#ifndef S390_CCWGROUP_H
2#define S390_CCWGROUP_H
3
4struct ccw_device;
5struct ccw_driver;
6
7/**
8 * struct ccwgroup_device - ccw group device
9 * @creator_id: unique number of the driver
10 * @state: online/offline state
11 * @count: number of attached slave devices
12 * @dev: embedded device structure
13 * @cdev: variable number of slave devices, allocated as needed
14 */
15struct ccwgroup_device {
16 unsigned long creator_id;
17 enum {
18 CCWGROUP_OFFLINE,
19 CCWGROUP_ONLINE,
20 } state;
21/* private: */
22 atomic_t onoff;
23 struct mutex reg_mutex;
24/* public: */
25 unsigned int count;
26 struct device dev;
27 struct ccw_device *cdev[0];
28};
29
30/**
31 * struct ccwgroup_driver - driver for ccw group devices
32 * @owner: driver owner
33 * @name: driver name
34 * @max_slaves: maximum number of slave devices
35 * @driver_id: unique id
36 * @probe: function called on probe
37 * @remove: function called on remove
38 * @set_online: function called when device is set online
39 * @set_offline: function called when device is set offline
40 * @shutdown: function called when device is shut down
41 * @driver: embedded driver structure
42 */
43struct ccwgroup_driver {
44 struct module *owner;
45 char *name;
46 int max_slaves;
47 unsigned long driver_id;
48
49 int (*probe) (struct ccwgroup_device *);
50 void (*remove) (struct ccwgroup_device *);
51 int (*set_online) (struct ccwgroup_device *);
52 int (*set_offline) (struct ccwgroup_device *);
53 void (*shutdown)(struct ccwgroup_device *);
54
55 struct device_driver driver;
56};
57
58extern int ccwgroup_driver_register (struct ccwgroup_driver *cdriver);
59extern void ccwgroup_driver_unregister (struct ccwgroup_driver *cdriver);
60int ccwgroup_create_from_string(struct device *root, unsigned int creator_id,
61 struct ccw_driver *cdrv, int num_devices,
62 const char *buf);
63
64extern int ccwgroup_probe_ccwdev(struct ccw_device *cdev);
65extern void ccwgroup_remove_ccwdev(struct ccw_device *cdev);
66
67#define to_ccwgroupdev(x) container_of((x), struct ccwgroup_device, dev)
68#define to_ccwgroupdrv(x) container_of((x), struct ccwgroup_driver, driver)
69#endif
diff --git a/include/asm-s390/checksum.h b/include/asm-s390/checksum.h
deleted file mode 100644
index d5a8e7c1477..00000000000
--- a/include/asm-s390/checksum.h
+++ /dev/null
@@ -1,166 +0,0 @@
1#ifndef _S390_CHECKSUM_H
2#define _S390_CHECKSUM_H
3
4/*
5 * include/asm-s390/checksum.h
6 * S390 fast network checksum routines
7 * see also arch/S390/lib/checksum.c
8 *
9 * S390 version
10 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
11 * Author(s): Ulrich Hild (first version)
12 * Martin Schwidefsky (heavily optimized CKSM version)
13 * D.J. Barrow (third attempt)
14 */
15
16#include <asm/uaccess.h>
17
18/*
19 * computes the checksum of a memory block at buff, length len,
20 * and adds in "sum" (32-bit)
21 *
22 * returns a 32-bit number suitable for feeding into itself
23 * or csum_tcpudp_magic
24 *
25 * this function must be called with even lengths, except
26 * for the last fragment, which may be odd
27 *
28 * it's best to have buff aligned on a 32-bit boundary
29 */
30static inline __wsum
31csum_partial(const void *buff, int len, __wsum sum)
32{
33 register unsigned long reg2 asm("2") = (unsigned long) buff;
34 register unsigned long reg3 asm("3") = (unsigned long) len;
35
36 asm volatile(
37 "0: cksm %0,%1\n" /* do checksum on longs */
38 " jo 0b\n"
39 : "+d" (sum), "+d" (reg2), "+d" (reg3) : : "cc", "memory");
40 return sum;
41}
42
43/*
44 * the same as csum_partial_copy, but copies from user space.
45 *
46 * here even more important to align src and dst on a 32-bit (or even
47 * better 64-bit) boundary
48 *
49 * Copy from userspace and compute checksum. If we catch an exception
50 * then zero the rest of the buffer.
51 */
52static inline __wsum
53csum_partial_copy_from_user(const void __user *src, void *dst,
54 int len, __wsum sum,
55 int *err_ptr)
56{
57 int missing;
58
59 missing = copy_from_user(dst, src, len);
60 if (missing) {
61 memset(dst + len - missing, 0, missing);
62 *err_ptr = -EFAULT;
63 }
64
65 return csum_partial(dst, len, sum);
66}
67
68
69static inline __wsum
70csum_partial_copy_nocheck (const void *src, void *dst, int len, __wsum sum)
71{
72 memcpy(dst,src,len);
73 return csum_partial(dst, len, sum);
74}
75
76/*
77 * Fold a partial checksum without adding pseudo headers
78 */
79static inline __sum16 csum_fold(__wsum sum)
80{
81#ifndef __s390x__
82 register_pair rp;
83
84 asm volatile(
85 " slr %N1,%N1\n" /* %0 = H L */
86 " lr %1,%0\n" /* %0 = H L, %1 = H L 0 0 */
87 " srdl %1,16\n" /* %0 = H L, %1 = 0 H L 0 */
88 " alr %1,%N1\n" /* %0 = H L, %1 = L H L 0 */
89 " alr %0,%1\n" /* %0 = H+L+C L+H */
90 " srl %0,16\n" /* %0 = H+L+C */
91 : "+&d" (sum), "=d" (rp) : : "cc");
92#else /* __s390x__ */
93 asm volatile(
94 " sr 3,3\n" /* %0 = H*65536 + L */
95 " lr 2,%0\n" /* %0 = H L, 2/3 = H L / 0 0 */
96 " srdl 2,16\n" /* %0 = H L, 2/3 = 0 H / L 0 */
97 " alr 2,3\n" /* %0 = H L, 2/3 = L H / L 0 */
98 " alr %0,2\n" /* %0 = H+L+C L+H */
99 " srl %0,16\n" /* %0 = H+L+C */
100 : "+&d" (sum) : : "cc", "2", "3");
101#endif /* __s390x__ */
102 return (__force __sum16) ~sum;
103}
104
105/*
106 * This is a version of ip_compute_csum() optimized for IP headers,
107 * which always checksum on 4 octet boundaries.
108 *
109 */
110static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
111{
112 return csum_fold(csum_partial(iph, ihl*4, 0));
113}
114
115/*
116 * computes the checksum of the TCP/UDP pseudo-header
117 * returns a 32-bit checksum
118 */
119static inline __wsum
120csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
121 unsigned short len, unsigned short proto,
122 __wsum sum)
123{
124 __u32 csum = (__force __u32)sum;
125
126 csum += (__force __u32)saddr;
127 if (csum < (__force __u32)saddr)
128 csum++;
129
130 csum += (__force __u32)daddr;
131 if (csum < (__force __u32)daddr)
132 csum++;
133
134 csum += len + proto;
135 if (csum < len + proto)
136 csum++;
137
138 return (__force __wsum)csum;
139}
140
141/*
142 * computes the checksum of the TCP/UDP pseudo-header
143 * returns a 16-bit checksum, already complemented
144 */
145
146static inline __sum16
147csum_tcpudp_magic(__be32 saddr, __be32 daddr,
148 unsigned short len, unsigned short proto,
149 __wsum sum)
150{
151 return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
152}
153
154/*
155 * this routine is used for miscellaneous IP-like checksums, mainly
156 * in icmp.c
157 */
158
159static inline __sum16 ip_compute_csum(const void *buff, int len)
160{
161 return csum_fold(csum_partial(buff, len, 0));
162}
163
164#endif /* _S390_CHECKSUM_H */
165
166
diff --git a/include/asm-s390/chpid.h b/include/asm-s390/chpid.h
deleted file mode 100644
index dfe3c7f3439..00000000000
--- a/include/asm-s390/chpid.h
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * drivers/s390/cio/chpid.h
3 *
4 * Copyright IBM Corp. 2007
5 * Author(s): Peter Oberparleiter <peter.oberparleiter@de.ibm.com>
6 */
7
8#ifndef _ASM_S390_CHPID_H
9#define _ASM_S390_CHPID_H _ASM_S390_CHPID_H
10
11#include <linux/string.h>
12#include <asm/types.h>
13
14#define __MAX_CHPID 255
15
16struct chp_id {
17 u8 reserved1;
18 u8 cssid;
19 u8 reserved2;
20 u8 id;
21} __attribute__((packed));
22
23#ifdef __KERNEL__
24#include <asm/cio.h>
25
26static inline void chp_id_init(struct chp_id *chpid)
27{
28 memset(chpid, 0, sizeof(struct chp_id));
29}
30
31static inline int chp_id_is_equal(struct chp_id *a, struct chp_id *b)
32{
33 return (a->id == b->id) && (a->cssid == b->cssid);
34}
35
36static inline void chp_id_next(struct chp_id *chpid)
37{
38 if (chpid->id < __MAX_CHPID)
39 chpid->id++;
40 else {
41 chpid->id = 0;
42 chpid->cssid++;
43 }
44}
45
46static inline int chp_id_is_valid(struct chp_id *chpid)
47{
48 return (chpid->cssid <= __MAX_CSSID);
49}
50
51
52#define chp_id_for_each(c) \
53 for (chp_id_init(c); chp_id_is_valid(c); chp_id_next(c))
54#endif /* __KERNEL */
55
56#endif /* _ASM_S390_CHPID_H */
diff --git a/include/asm-s390/chsc.h b/include/asm-s390/chsc.h
deleted file mode 100644
index d38d0cf62d4..00000000000
--- a/include/asm-s390/chsc.h
+++ /dev/null
@@ -1,127 +0,0 @@
1/*
2 * ioctl interface for /dev/chsc
3 *
4 * Copyright 2008 IBM Corp.
5 * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
6 */
7
8#ifndef _ASM_CHSC_H
9#define _ASM_CHSC_H
10
11#include <asm/chpid.h>
12#include <asm/schid.h>
13
14struct chsc_async_header {
15 __u16 length;
16 __u16 code;
17 __u32 cmd_dependend;
18 __u32 key : 4;
19 __u32 : 28;
20 struct subchannel_id sid;
21} __attribute__ ((packed));
22
23struct chsc_async_area {
24 struct chsc_async_header header;
25 __u8 data[PAGE_SIZE - 16 /* size of chsc_async_header */];
26} __attribute__ ((packed));
27
28
29struct chsc_response_struct {
30 __u16 length;
31 __u16 code;
32 __u32 parms;
33 __u8 data[PAGE_SIZE - 8];
34} __attribute__ ((packed));
35
36struct chsc_chp_cd {
37 struct chp_id chpid;
38 int m;
39 int fmt;
40 struct chsc_response_struct cpcb;
41};
42
43struct chsc_cu_cd {
44 __u16 cun;
45 __u8 cssid;
46 int m;
47 int fmt;
48 struct chsc_response_struct cucb;
49};
50
51struct chsc_sch_cud {
52 struct subchannel_id schid;
53 int fmt;
54 struct chsc_response_struct scub;
55};
56
57struct conf_id {
58 int m;
59 __u8 cssid;
60 __u8 ssid;
61};
62
63struct chsc_conf_info {
64 struct conf_id id;
65 int fmt;
66 struct chsc_response_struct scid;
67};
68
69struct ccl_parm_chpid {
70 int m;
71 struct chp_id chp;
72};
73
74struct ccl_parm_cssids {
75 __u8 f_cssid;
76 __u8 l_cssid;
77};
78
79struct chsc_comp_list {
80 struct {
81 enum {
82 CCL_CU_ON_CHP = 1,
83 CCL_CHP_TYPE_CAP = 2,
84 CCL_CSS_IMG = 4,
85 CCL_CSS_IMG_CONF_CHAR = 5,
86 CCL_IOP_CHP = 6,
87 } ctype;
88 int fmt;
89 struct ccl_parm_chpid chpid;
90 struct ccl_parm_cssids cssids;
91 } req;
92 struct chsc_response_struct sccl;
93};
94
95struct chsc_dcal {
96 struct {
97 enum {
98 DCAL_CSS_IID_PN = 4,
99 } atype;
100 __u32 list_parm[2];
101 int fmt;
102 } req;
103 struct chsc_response_struct sdcal;
104};
105
106struct chsc_cpd_info {
107 struct chp_id chpid;
108 int m;
109 int fmt;
110 int rfmt;
111 int c;
112 struct chsc_response_struct chpdb;
113};
114
115#define CHSC_IOCTL_MAGIC 'c'
116
117#define CHSC_START _IOWR(CHSC_IOCTL_MAGIC, 0x81, struct chsc_async_area)
118#define CHSC_INFO_CHANNEL_PATH _IOWR(CHSC_IOCTL_MAGIC, 0x82, \
119 struct chsc_chp_cd)
120#define CHSC_INFO_CU _IOWR(CHSC_IOCTL_MAGIC, 0x83, struct chsc_cu_cd)
121#define CHSC_INFO_SCH_CU _IOWR(CHSC_IOCTL_MAGIC, 0x84, struct chsc_sch_cud)
122#define CHSC_INFO_CI _IOWR(CHSC_IOCTL_MAGIC, 0x85, struct chsc_conf_info)
123#define CHSC_INFO_CCL _IOWR(CHSC_IOCTL_MAGIC, 0x86, struct chsc_comp_list)
124#define CHSC_INFO_CPD _IOWR(CHSC_IOCTL_MAGIC, 0x87, struct chsc_cpd_info)
125#define CHSC_INFO_DCAL _IOWR(CHSC_IOCTL_MAGIC, 0x88, struct chsc_dcal)
126
127#endif
diff --git a/include/asm-s390/cio.h b/include/asm-s390/cio.h
deleted file mode 100644
index 6dccb071aec..00000000000
--- a/include/asm-s390/cio.h
+++ /dev/null
@@ -1,514 +0,0 @@
1/*
2 * include/asm-s390/cio.h
3 * include/asm-s390x/cio.h
4 *
5 * Common interface for I/O on S/390
6 */
7#ifndef _ASM_S390_CIO_H_
8#define _ASM_S390_CIO_H_
9
10#include <linux/spinlock.h>
11#include <asm/types.h>
12
13#ifdef __KERNEL__
14
15#define LPM_ANYPATH 0xff
16#define __MAX_CSSID 0
17
18/**
19 * struct cmd_scsw - command-mode subchannel status word
20 * @key: subchannel key
21 * @sctl: suspend control
22 * @eswf: esw format
23 * @cc: deferred condition code
24 * @fmt: format
25 * @pfch: prefetch
26 * @isic: initial-status interruption control
27 * @alcc: address-limit checking control
28 * @ssi: suppress-suspended interruption
29 * @zcc: zero condition code
30 * @ectl: extended control
31 * @pno: path not operational
32 * @res: reserved
33 * @fctl: function control
34 * @actl: activity control
35 * @stctl: status control
36 * @cpa: channel program address
37 * @dstat: device status
38 * @cstat: subchannel status
39 * @count: residual count
40 */
41struct cmd_scsw {
42 __u32 key : 4;
43 __u32 sctl : 1;
44 __u32 eswf : 1;
45 __u32 cc : 2;
46 __u32 fmt : 1;
47 __u32 pfch : 1;
48 __u32 isic : 1;
49 __u32 alcc : 1;
50 __u32 ssi : 1;
51 __u32 zcc : 1;
52 __u32 ectl : 1;
53 __u32 pno : 1;
54 __u32 res : 1;
55 __u32 fctl : 3;
56 __u32 actl : 7;
57 __u32 stctl : 5;
58 __u32 cpa;
59 __u32 dstat : 8;
60 __u32 cstat : 8;
61 __u32 count : 16;
62} __attribute__ ((packed));
63
64/**
65 * struct tm_scsw - transport-mode subchannel status word
66 * @key: subchannel key
67 * @eswf: esw format
68 * @cc: deferred condition code
69 * @fmt: format
70 * @x: IRB-format control
71 * @q: interrogate-complete
72 * @ectl: extended control
73 * @pno: path not operational
74 * @fctl: function control
75 * @actl: activity control
76 * @stctl: status control
77 * @tcw: TCW address
78 * @dstat: device status
79 * @cstat: subchannel status
80 * @fcxs: FCX status
81 * @schxs: subchannel-extended status
82 */
83struct tm_scsw {
84 u32 key:4;
85 u32 :1;
86 u32 eswf:1;
87 u32 cc:2;
88 u32 fmt:3;
89 u32 x:1;
90 u32 q:1;
91 u32 :1;
92 u32 ectl:1;
93 u32 pno:1;
94 u32 :1;
95 u32 fctl:3;
96 u32 actl:7;
97 u32 stctl:5;
98 u32 tcw;
99 u32 dstat:8;
100 u32 cstat:8;
101 u32 fcxs:8;
102 u32 schxs:8;
103} __attribute__ ((packed));
104
105/**
106 * union scsw - subchannel status word
107 * @cmd: command-mode SCSW
108 * @tm: transport-mode SCSW
109 */
110union scsw {
111 struct cmd_scsw cmd;
112 struct tm_scsw tm;
113} __attribute__ ((packed));
114
115int scsw_is_tm(union scsw *scsw);
116u32 scsw_key(union scsw *scsw);
117u32 scsw_eswf(union scsw *scsw);
118u32 scsw_cc(union scsw *scsw);
119u32 scsw_ectl(union scsw *scsw);
120u32 scsw_pno(union scsw *scsw);
121u32 scsw_fctl(union scsw *scsw);
122u32 scsw_actl(union scsw *scsw);
123u32 scsw_stctl(union scsw *scsw);
124u32 scsw_dstat(union scsw *scsw);
125u32 scsw_cstat(union scsw *scsw);
126int scsw_is_solicited(union scsw *scsw);
127int scsw_is_valid_key(union scsw *scsw);
128int scsw_is_valid_eswf(union scsw *scsw);
129int scsw_is_valid_cc(union scsw *scsw);
130int scsw_is_valid_ectl(union scsw *scsw);
131int scsw_is_valid_pno(union scsw *scsw);
132int scsw_is_valid_fctl(union scsw *scsw);
133int scsw_is_valid_actl(union scsw *scsw);
134int scsw_is_valid_stctl(union scsw *scsw);
135int scsw_is_valid_dstat(union scsw *scsw);
136int scsw_is_valid_cstat(union scsw *scsw);
137int scsw_cmd_is_valid_key(union scsw *scsw);
138int scsw_cmd_is_valid_sctl(union scsw *scsw);
139int scsw_cmd_is_valid_eswf(union scsw *scsw);
140int scsw_cmd_is_valid_cc(union scsw *scsw);
141int scsw_cmd_is_valid_fmt(union scsw *scsw);
142int scsw_cmd_is_valid_pfch(union scsw *scsw);
143int scsw_cmd_is_valid_isic(union scsw *scsw);
144int scsw_cmd_is_valid_alcc(union scsw *scsw);
145int scsw_cmd_is_valid_ssi(union scsw *scsw);
146int scsw_cmd_is_valid_zcc(union scsw *scsw);
147int scsw_cmd_is_valid_ectl(union scsw *scsw);
148int scsw_cmd_is_valid_pno(union scsw *scsw);
149int scsw_cmd_is_valid_fctl(union scsw *scsw);
150int scsw_cmd_is_valid_actl(union scsw *scsw);
151int scsw_cmd_is_valid_stctl(union scsw *scsw);
152int scsw_cmd_is_valid_dstat(union scsw *scsw);
153int scsw_cmd_is_valid_cstat(union scsw *scsw);
154int scsw_cmd_is_solicited(union scsw *scsw);
155int scsw_tm_is_valid_key(union scsw *scsw);
156int scsw_tm_is_valid_eswf(union scsw *scsw);
157int scsw_tm_is_valid_cc(union scsw *scsw);
158int scsw_tm_is_valid_fmt(union scsw *scsw);
159int scsw_tm_is_valid_x(union scsw *scsw);
160int scsw_tm_is_valid_q(union scsw *scsw);
161int scsw_tm_is_valid_ectl(union scsw *scsw);
162int scsw_tm_is_valid_pno(union scsw *scsw);
163int scsw_tm_is_valid_fctl(union scsw *scsw);
164int scsw_tm_is_valid_actl(union scsw *scsw);
165int scsw_tm_is_valid_stctl(union scsw *scsw);
166int scsw_tm_is_valid_dstat(union scsw *scsw);
167int scsw_tm_is_valid_cstat(union scsw *scsw);
168int scsw_tm_is_valid_fcxs(union scsw *scsw);
169int scsw_tm_is_valid_schxs(union scsw *scsw);
170int scsw_tm_is_solicited(union scsw *scsw);
171
172#define SCSW_FCTL_CLEAR_FUNC 0x1
173#define SCSW_FCTL_HALT_FUNC 0x2
174#define SCSW_FCTL_START_FUNC 0x4
175
176#define SCSW_ACTL_SUSPENDED 0x1
177#define SCSW_ACTL_DEVACT 0x2
178#define SCSW_ACTL_SCHACT 0x4
179#define SCSW_ACTL_CLEAR_PEND 0x8
180#define SCSW_ACTL_HALT_PEND 0x10
181#define SCSW_ACTL_START_PEND 0x20
182#define SCSW_ACTL_RESUME_PEND 0x40
183
184#define SCSW_STCTL_STATUS_PEND 0x1
185#define SCSW_STCTL_SEC_STATUS 0x2
186#define SCSW_STCTL_PRIM_STATUS 0x4
187#define SCSW_STCTL_INTER_STATUS 0x8
188#define SCSW_STCTL_ALERT_STATUS 0x10
189
190#define DEV_STAT_ATTENTION 0x80
191#define DEV_STAT_STAT_MOD 0x40
192#define DEV_STAT_CU_END 0x20
193#define DEV_STAT_BUSY 0x10
194#define DEV_STAT_CHN_END 0x08
195#define DEV_STAT_DEV_END 0x04
196#define DEV_STAT_UNIT_CHECK 0x02
197#define DEV_STAT_UNIT_EXCEP 0x01
198
199#define SCHN_STAT_PCI 0x80
200#define SCHN_STAT_INCORR_LEN 0x40
201#define SCHN_STAT_PROG_CHECK 0x20
202#define SCHN_STAT_PROT_CHECK 0x10
203#define SCHN_STAT_CHN_DATA_CHK 0x08
204#define SCHN_STAT_CHN_CTRL_CHK 0x04
205#define SCHN_STAT_INTF_CTRL_CHK 0x02
206#define SCHN_STAT_CHAIN_CHECK 0x01
207
208/*
209 * architectured values for first sense byte
210 */
211#define SNS0_CMD_REJECT 0x80
212#define SNS_CMD_REJECT SNS0_CMD_REJEC
213#define SNS0_INTERVENTION_REQ 0x40
214#define SNS0_BUS_OUT_CHECK 0x20
215#define SNS0_EQUIPMENT_CHECK 0x10
216#define SNS0_DATA_CHECK 0x08
217#define SNS0_OVERRUN 0x04
218#define SNS0_INCOMPL_DOMAIN 0x01
219
220/*
221 * architectured values for second sense byte
222 */
223#define SNS1_PERM_ERR 0x80
224#define SNS1_INV_TRACK_FORMAT 0x40
225#define SNS1_EOC 0x20
226#define SNS1_MESSAGE_TO_OPER 0x10
227#define SNS1_NO_REC_FOUND 0x08
228#define SNS1_FILE_PROTECTED 0x04
229#define SNS1_WRITE_INHIBITED 0x02
230#define SNS1_INPRECISE_END 0x01
231
232/*
233 * architectured values for third sense byte
234 */
235#define SNS2_REQ_INH_WRITE 0x80
236#define SNS2_CORRECTABLE 0x40
237#define SNS2_FIRST_LOG_ERR 0x20
238#define SNS2_ENV_DATA_PRESENT 0x10
239#define SNS2_INPRECISE_END 0x04
240
241/**
242 * struct ccw1 - channel command word
243 * @cmd_code: command code
244 * @flags: flags, like IDA adressing, etc.
245 * @count: byte count
246 * @cda: data address
247 *
248 * The ccw is the basic structure to build channel programs that perform
249 * operations with the device or the control unit. Only Format-1 channel
250 * command words are supported.
251 */
252struct ccw1 {
253 __u8 cmd_code;
254 __u8 flags;
255 __u16 count;
256 __u32 cda;
257} __attribute__ ((packed,aligned(8)));
258
259#define CCW_FLAG_DC 0x80
260#define CCW_FLAG_CC 0x40
261#define CCW_FLAG_SLI 0x20
262#define CCW_FLAG_SKIP 0x10
263#define CCW_FLAG_PCI 0x08
264#define CCW_FLAG_IDA 0x04
265#define CCW_FLAG_SUSPEND 0x02
266
267#define CCW_CMD_READ_IPL 0x02
268#define CCW_CMD_NOOP 0x03
269#define CCW_CMD_BASIC_SENSE 0x04
270#define CCW_CMD_TIC 0x08
271#define CCW_CMD_STLCK 0x14
272#define CCW_CMD_SENSE_PGID 0x34
273#define CCW_CMD_SUSPEND_RECONN 0x5B
274#define CCW_CMD_RDC 0x64
275#define CCW_CMD_RELEASE 0x94
276#define CCW_CMD_SET_PGID 0xAF
277#define CCW_CMD_SENSE_ID 0xE4
278#define CCW_CMD_DCTL 0xF3
279
280#define SENSE_MAX_COUNT 0x20
281
282/**
283 * struct erw - extended report word
284 * @res0: reserved
285 * @auth: authorization check
286 * @pvrf: path-verification-required flag
287 * @cpt: channel-path timeout
288 * @fsavf: failing storage address validity flag
289 * @cons: concurrent sense
290 * @scavf: secondary ccw address validity flag
291 * @fsaf: failing storage address format
292 * @scnt: sense count, if @cons == %1
293 * @res16: reserved
294 */
295struct erw {
296 __u32 res0 : 3;
297 __u32 auth : 1;
298 __u32 pvrf : 1;
299 __u32 cpt : 1;
300 __u32 fsavf : 1;
301 __u32 cons : 1;
302 __u32 scavf : 1;
303 __u32 fsaf : 1;
304 __u32 scnt : 6;
305 __u32 res16 : 16;
306} __attribute__ ((packed));
307
308/**
309 * struct sublog - subchannel logout area
310 * @res0: reserved
311 * @esf: extended status flags
312 * @lpum: last path used mask
313 * @arep: ancillary report
314 * @fvf: field-validity flags
315 * @sacc: storage access code
316 * @termc: termination code
317 * @devsc: device-status check
318 * @serr: secondary error
319 * @ioerr: i/o-error alert
320 * @seqc: sequence code
321 */
322struct sublog {
323 __u32 res0 : 1;
324 __u32 esf : 7;
325 __u32 lpum : 8;
326 __u32 arep : 1;
327 __u32 fvf : 5;
328 __u32 sacc : 2;
329 __u32 termc : 2;
330 __u32 devsc : 1;
331 __u32 serr : 1;
332 __u32 ioerr : 1;
333 __u32 seqc : 3;
334} __attribute__ ((packed));
335
336/**
337 * struct esw0 - Format 0 Extended Status Word (ESW)
338 * @sublog: subchannel logout
339 * @erw: extended report word
340 * @faddr: failing storage address
341 * @saddr: secondary ccw address
342 */
343struct esw0 {
344 struct sublog sublog;
345 struct erw erw;
346 __u32 faddr[2];
347 __u32 saddr;
348} __attribute__ ((packed));
349
350/**
351 * struct esw1 - Format 1 Extended Status Word (ESW)
352 * @zero0: reserved zeros
353 * @lpum: last path used mask
354 * @zero16: reserved zeros
355 * @erw: extended report word
356 * @zeros: three fullwords of zeros
357 */
358struct esw1 {
359 __u8 zero0;
360 __u8 lpum;
361 __u16 zero16;
362 struct erw erw;
363 __u32 zeros[3];
364} __attribute__ ((packed));
365
366/**
367 * struct esw2 - Format 2 Extended Status Word (ESW)
368 * @zero0: reserved zeros
369 * @lpum: last path used mask
370 * @dcti: device-connect-time interval
371 * @erw: extended report word
372 * @zeros: three fullwords of zeros
373 */
374struct esw2 {
375 __u8 zero0;
376 __u8 lpum;
377 __u16 dcti;
378 struct erw erw;
379 __u32 zeros[3];
380} __attribute__ ((packed));
381
382/**
383 * struct esw3 - Format 3 Extended Status Word (ESW)
384 * @zero0: reserved zeros
385 * @lpum: last path used mask
386 * @res: reserved
387 * @erw: extended report word
388 * @zeros: three fullwords of zeros
389 */
390struct esw3 {
391 __u8 zero0;
392 __u8 lpum;
393 __u16 res;
394 struct erw erw;
395 __u32 zeros[3];
396} __attribute__ ((packed));
397
398/**
399 * struct irb - interruption response block
400 * @scsw: subchannel status word
401 * @esw: extened status word, 4 formats
402 * @ecw: extended control word
403 *
404 * The irb that is handed to the device driver when an interrupt occurs. For
405 * solicited interrupts, the common I/O layer already performs checks whether
406 * a field is valid; a field not being valid is always passed as %0.
407 * If a unit check occured, @ecw may contain sense data; this is retrieved
408 * by the common I/O layer itself if the device doesn't support concurrent
409 * sense (so that the device driver never needs to perform basic sene itself).
410 * For unsolicited interrupts, the irb is passed as-is (expect for sense data,
411 * if applicable).
412 */
413struct irb {
414 union scsw scsw;
415 union {
416 struct esw0 esw0;
417 struct esw1 esw1;
418 struct esw2 esw2;
419 struct esw3 esw3;
420 } esw;
421 __u8 ecw[32];
422} __attribute__ ((packed,aligned(4)));
423
424/**
425 * struct ciw - command information word (CIW) layout
426 * @et: entry type
427 * @reserved: reserved bits
428 * @ct: command type
429 * @cmd: command code
430 * @count: command count
431 */
432struct ciw {
433 __u32 et : 2;
434 __u32 reserved : 2;
435 __u32 ct : 4;
436 __u32 cmd : 8;
437 __u32 count : 16;
438} __attribute__ ((packed));
439
440#define CIW_TYPE_RCD 0x0 /* read configuration data */
441#define CIW_TYPE_SII 0x1 /* set interface identifier */
442#define CIW_TYPE_RNI 0x2 /* read node identifier */
443
444/*
445 * Flags used as input parameters for do_IO()
446 */
447#define DOIO_ALLOW_SUSPEND 0x0001 /* allow for channel prog. suspend */
448#define DOIO_DENY_PREFETCH 0x0002 /* don't allow for CCW prefetch */
449#define DOIO_SUPPRESS_INTER 0x0004 /* suppress intermediate inter. */
450 /* ... for suspended CCWs */
451/* Device or subchannel gone. */
452#define CIO_GONE 0x0001
453/* No path to device. */
454#define CIO_NO_PATH 0x0002
455/* Device has appeared. */
456#define CIO_OPER 0x0004
457/* Sick revalidation of device. */
458#define CIO_REVALIDATE 0x0008
459
460/**
461 * struct ccw_dev_id - unique identifier for ccw devices
462 * @ssid: subchannel set id
463 * @devno: device number
464 *
465 * This structure is not directly based on any hardware structure. The
466 * hardware identifies a device by its device number and its subchannel,
467 * which is in turn identified by its id. In order to get a unique identifier
468 * for ccw devices across subchannel sets, @struct ccw_dev_id has been
469 * introduced.
470 */
471struct ccw_dev_id {
472 u8 ssid;
473 u16 devno;
474};
475
476/**
477 * ccw_device_id_is_equal() - compare two ccw_dev_ids
478 * @dev_id1: a ccw_dev_id
479 * @dev_id2: another ccw_dev_id
480 * Returns:
481 * %1 if the two structures are equal field-by-field,
482 * %0 if not.
483 * Context:
484 * any
485 */
486static inline int ccw_dev_id_is_equal(struct ccw_dev_id *dev_id1,
487 struct ccw_dev_id *dev_id2)
488{
489 if ((dev_id1->ssid == dev_id2->ssid) &&
490 (dev_id1->devno == dev_id2->devno))
491 return 1;
492 return 0;
493}
494
495extern void wait_cons_dev(void);
496
497extern void css_schedule_reprobe(void);
498
499extern void reipl_ccw_dev(struct ccw_dev_id *id);
500
501struct cio_iplinfo {
502 u16 devno;
503 int is_qdio;
504};
505
506extern int cio_get_iplinfo(struct cio_iplinfo *iplinfo);
507
508/* Function from drivers/s390/cio/chsc.c */
509int chsc_sstpc(void *page, unsigned int op, u16 ctrl);
510int chsc_sstpi(void *page, void *result, size_t size);
511
512#endif
513
514#endif
diff --git a/include/asm-s390/cmb.h b/include/asm-s390/cmb.h
deleted file mode 100644
index 50196857d27..00000000000
--- a/include/asm-s390/cmb.h
+++ /dev/null
@@ -1,58 +0,0 @@
1#ifndef S390_CMB_H
2#define S390_CMB_H
3/**
4 * struct cmbdata - channel measurement block data for user space
5 * @size: size of the stored data
6 * @elapsed_time: time since last sampling
7 * @ssch_rsch_count: number of ssch and rsch
8 * @sample_count: number of samples
9 * @device_connect_time: time of device connect
10 * @function_pending_time: time of function pending
11 * @device_disconnect_time: time of device disconnect
12 * @control_unit_queuing_time: time of control unit queuing
13 * @device_active_only_time: time of device active only
14 * @device_busy_time: time of device busy (ext. format)
15 * @initial_command_response_time: initial command response time (ext. format)
16 *
17 * All values are stored as 64 bit for simplicity, especially
18 * in 32 bit emulation mode. All time values are normalized to
19 * nanoseconds.
20 * Currently, two formats are known, which differ by the size of
21 * this structure, i.e. the last two members are only set when
22 * the extended channel measurement facility (first shipped in
23 * z990 machines) is activated.
24 * Potentially, more fields could be added, which would result in a
25 * new ioctl number.
26 */
27struct cmbdata {
28 __u64 size;
29 __u64 elapsed_time;
30 /* basic and exended format: */
31 __u64 ssch_rsch_count;
32 __u64 sample_count;
33 __u64 device_connect_time;
34 __u64 function_pending_time;
35 __u64 device_disconnect_time;
36 __u64 control_unit_queuing_time;
37 __u64 device_active_only_time;
38 /* extended format only: */
39 __u64 device_busy_time;
40 __u64 initial_command_response_time;
41};
42
43/* enable channel measurement */
44#define BIODASDCMFENABLE _IO(DASD_IOCTL_LETTER, 32)
45/* enable channel measurement */
46#define BIODASDCMFDISABLE _IO(DASD_IOCTL_LETTER, 33)
47/* read channel measurement data */
48#define BIODASDREADALLCMB _IOWR(DASD_IOCTL_LETTER, 33, struct cmbdata)
49
50#ifdef __KERNEL__
51struct ccw_device;
52extern int enable_cmf(struct ccw_device *cdev);
53extern int disable_cmf(struct ccw_device *cdev);
54extern u64 cmf_read(struct ccw_device *cdev, int index);
55extern int cmf_readall(struct ccw_device *cdev, struct cmbdata *data);
56
57#endif /* __KERNEL__ */
58#endif /* S390_CMB_H */
diff --git a/include/asm-s390/compat.h b/include/asm-s390/compat.h
deleted file mode 100644
index de065b32381..00000000000
--- a/include/asm-s390/compat.h
+++ /dev/null
@@ -1,233 +0,0 @@
1#ifndef _ASM_S390X_COMPAT_H
2#define _ASM_S390X_COMPAT_H
3/*
4 * Architecture specific compatibility types
5 */
6#include <linux/types.h>
7#include <linux/sched.h>
8
9#define PSW32_MASK_PER 0x40000000UL
10#define PSW32_MASK_DAT 0x04000000UL
11#define PSW32_MASK_IO 0x02000000UL
12#define PSW32_MASK_EXT 0x01000000UL
13#define PSW32_MASK_KEY 0x00F00000UL
14#define PSW32_MASK_MCHECK 0x00040000UL
15#define PSW32_MASK_WAIT 0x00020000UL
16#define PSW32_MASK_PSTATE 0x00010000UL
17#define PSW32_MASK_ASC 0x0000C000UL
18#define PSW32_MASK_CC 0x00003000UL
19#define PSW32_MASK_PM 0x00000f00UL
20
21#define PSW32_ADDR_AMODE31 0x80000000UL
22#define PSW32_ADDR_INSN 0x7FFFFFFFUL
23
24#define PSW32_BASE_BITS 0x00080000UL
25
26#define PSW32_ASC_PRIMARY 0x00000000UL
27#define PSW32_ASC_ACCREG 0x00004000UL
28#define PSW32_ASC_SECONDARY 0x00008000UL
29#define PSW32_ASC_HOME 0x0000C000UL
30
31#define PSW32_MASK_MERGE(CURRENT,NEW) \
32 (((CURRENT) & ~(PSW32_MASK_CC|PSW32_MASK_PM)) | \
33 ((NEW) & (PSW32_MASK_CC|PSW32_MASK_PM)))
34
35extern long psw32_user_bits;
36
37#define COMPAT_USER_HZ 100
38
39typedef u32 compat_size_t;
40typedef s32 compat_ssize_t;
41typedef s32 compat_time_t;
42typedef s32 compat_clock_t;
43typedef s32 compat_pid_t;
44typedef u16 __compat_uid_t;
45typedef u16 __compat_gid_t;
46typedef u32 __compat_uid32_t;
47typedef u32 __compat_gid32_t;
48typedef u16 compat_mode_t;
49typedef u32 compat_ino_t;
50typedef u16 compat_dev_t;
51typedef s32 compat_off_t;
52typedef s64 compat_loff_t;
53typedef u16 compat_nlink_t;
54typedef u16 compat_ipc_pid_t;
55typedef s32 compat_daddr_t;
56typedef u32 compat_caddr_t;
57typedef __kernel_fsid_t compat_fsid_t;
58typedef s32 compat_key_t;
59typedef s32 compat_timer_t;
60
61typedef s32 compat_int_t;
62typedef s32 compat_long_t;
63typedef s64 compat_s64;
64typedef u32 compat_uint_t;
65typedef u32 compat_ulong_t;
66typedef u64 compat_u64;
67
68struct compat_timespec {
69 compat_time_t tv_sec;
70 s32 tv_nsec;
71};
72
73struct compat_timeval {
74 compat_time_t tv_sec;
75 s32 tv_usec;
76};
77
78struct compat_stat {
79 compat_dev_t st_dev;
80 u16 __pad1;
81 compat_ino_t st_ino;
82 compat_mode_t st_mode;
83 compat_nlink_t st_nlink;
84 __compat_uid_t st_uid;
85 __compat_gid_t st_gid;
86 compat_dev_t st_rdev;
87 u16 __pad2;
88 u32 st_size;
89 u32 st_blksize;
90 u32 st_blocks;
91 u32 st_atime;
92 u32 st_atime_nsec;
93 u32 st_mtime;
94 u32 st_mtime_nsec;
95 u32 st_ctime;
96 u32 st_ctime_nsec;
97 u32 __unused4;
98 u32 __unused5;
99};
100
101struct compat_flock {
102 short l_type;
103 short l_whence;
104 compat_off_t l_start;
105 compat_off_t l_len;
106 compat_pid_t l_pid;
107};
108
109#define F_GETLK64 12
110#define F_SETLK64 13
111#define F_SETLKW64 14
112
113struct compat_flock64 {
114 short l_type;
115 short l_whence;
116 compat_loff_t l_start;
117 compat_loff_t l_len;
118 compat_pid_t l_pid;
119};
120
121struct compat_statfs {
122 s32 f_type;
123 s32 f_bsize;
124 s32 f_blocks;
125 s32 f_bfree;
126 s32 f_bavail;
127 s32 f_files;
128 s32 f_ffree;
129 compat_fsid_t f_fsid;
130 s32 f_namelen;
131 s32 f_frsize;
132 s32 f_spare[6];
133};
134
135#define COMPAT_RLIM_OLD_INFINITY 0x7fffffff
136#define COMPAT_RLIM_INFINITY 0xffffffff
137
138typedef u32 compat_old_sigset_t; /* at least 32 bits */
139
140#define _COMPAT_NSIG 64
141#define _COMPAT_NSIG_BPW 32
142
143typedef u32 compat_sigset_word;
144
145#define COMPAT_OFF_T_MAX 0x7fffffff
146#define COMPAT_LOFF_T_MAX 0x7fffffffffffffffL
147
148/*
149 * A pointer passed in from user mode. This should not
150 * be used for syscall parameters, just declare them
151 * as pointers because the syscall entry code will have
152 * appropriately converted them already.
153 */
154typedef u32 compat_uptr_t;
155
156static inline void __user *compat_ptr(compat_uptr_t uptr)
157{
158 return (void __user *)(unsigned long)(uptr & 0x7fffffffUL);
159}
160
161static inline compat_uptr_t ptr_to_compat(void __user *uptr)
162{
163 return (u32)(unsigned long)uptr;
164}
165
166static inline void __user *compat_alloc_user_space(long len)
167{
168 unsigned long stack;
169
170 stack = KSTK_ESP(current);
171 if (test_thread_flag(TIF_31BIT))
172 stack &= 0x7fffffffUL;
173 return (void __user *) (stack - len);
174}
175
176struct compat_ipc64_perm {
177 compat_key_t key;
178 __compat_uid32_t uid;
179 __compat_gid32_t gid;
180 __compat_uid32_t cuid;
181 __compat_gid32_t cgid;
182 compat_mode_t mode;
183 unsigned short __pad1;
184 unsigned short seq;
185 unsigned short __pad2;
186 unsigned int __unused1;
187 unsigned int __unused2;
188};
189
190struct compat_semid64_ds {
191 struct compat_ipc64_perm sem_perm;
192 compat_time_t sem_otime;
193 compat_ulong_t __pad1;
194 compat_time_t sem_ctime;
195 compat_ulong_t __pad2;
196 compat_ulong_t sem_nsems;
197 compat_ulong_t __unused1;
198 compat_ulong_t __unused2;
199};
200
201struct compat_msqid64_ds {
202 struct compat_ipc64_perm msg_perm;
203 compat_time_t msg_stime;
204 compat_ulong_t __pad1;
205 compat_time_t msg_rtime;
206 compat_ulong_t __pad2;
207 compat_time_t msg_ctime;
208 compat_ulong_t __pad3;
209 compat_ulong_t msg_cbytes;
210 compat_ulong_t msg_qnum;
211 compat_ulong_t msg_qbytes;
212 compat_pid_t msg_lspid;
213 compat_pid_t msg_lrpid;
214 compat_ulong_t __unused1;
215 compat_ulong_t __unused2;
216};
217
218struct compat_shmid64_ds {
219 struct compat_ipc64_perm shm_perm;
220 compat_size_t shm_segsz;
221 compat_time_t shm_atime;
222 compat_ulong_t __pad1;
223 compat_time_t shm_dtime;
224 compat_ulong_t __pad2;
225 compat_time_t shm_ctime;
226 compat_ulong_t __pad3;
227 compat_pid_t shm_cpid;
228 compat_pid_t shm_lpid;
229 compat_ulong_t shm_nattch;
230 compat_ulong_t __unused1;
231 compat_ulong_t __unused2;
232};
233#endif /* _ASM_S390X_COMPAT_H */
diff --git a/include/asm-s390/cpcmd.h b/include/asm-s390/cpcmd.h
deleted file mode 100644
index 48a9eab1642..00000000000
--- a/include/asm-s390/cpcmd.h
+++ /dev/null
@@ -1,34 +0,0 @@
1/*
2 * arch/s390/kernel/cpcmd.h
3 *
4 * S390 version
5 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
7 * Christian Borntraeger (cborntra@de.ibm.com),
8 */
9
10#ifndef _ASM_S390_CPCMD_H
11#define _ASM_S390_CPCMD_H
12
13/*
14 * the lowlevel function for cpcmd
15 * the caller of __cpcmd has to ensure that the response buffer is below 2 GB
16 */
17extern int __cpcmd(const char *cmd, char *response, int rlen, int *response_code);
18
19/*
20 * cpcmd is the in-kernel interface for issuing CP commands
21 *
22 * cmd: null-terminated command string, max 240 characters
23 * response: response buffer for VM's textual response
24 * rlen: size of the response buffer, cpcmd will not exceed this size
25 * but will cap the output, if its too large. Everything that
26 * did not fit into the buffer will be silently dropped
27 * response_code: return pointer for VM's error code
28 * return value: the size of the response. The caller can check if the buffer
29 * was large enough by comparing the return value and rlen
30 * NOTE: If the response buffer is not below 2 GB, cpcmd can sleep
31 */
32extern int cpcmd(const char *cmd, char *response, int rlen, int *response_code);
33
34#endif /* _ASM_S390_CPCMD_H */
diff --git a/include/asm-s390/cpu.h b/include/asm-s390/cpu.h
deleted file mode 100644
index e5a6a9ba3ad..00000000000
--- a/include/asm-s390/cpu.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * include/asm-s390/cpu.h
3 *
4 * Copyright IBM Corp. 2007
5 * Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>
6 */
7
8#ifndef _ASM_S390_CPU_H_
9#define _ASM_S390_CPU_H_
10
11#include <linux/types.h>
12#include <linux/percpu.h>
13#include <linux/spinlock.h>
14
15struct s390_idle_data {
16 spinlock_t lock;
17 unsigned int in_idle;
18 unsigned long long idle_count;
19 unsigned long long idle_enter;
20 unsigned long long idle_time;
21};
22
23DECLARE_PER_CPU(struct s390_idle_data, s390_idle);
24
25void s390_idle_leave(void);
26
27static inline void s390_idle_check(void)
28{
29 if ((&__get_cpu_var(s390_idle))->in_idle)
30 s390_idle_leave();
31}
32
33#endif /* _ASM_S390_CPU_H_ */
diff --git a/include/asm-s390/cputime.h b/include/asm-s390/cputime.h
deleted file mode 100644
index 133ce054fc8..00000000000
--- a/include/asm-s390/cputime.h
+++ /dev/null
@@ -1,177 +0,0 @@
1/*
2 * include/asm-s390/cputime.h
3 *
4 * (C) Copyright IBM Corp. 2004
5 *
6 * Author: Martin Schwidefsky <schwidefsky@de.ibm.com>
7 */
8
9#ifndef _S390_CPUTIME_H
10#define _S390_CPUTIME_H
11
12#include <asm/div64.h>
13
14/* We want to use micro-second resolution. */
15
16typedef unsigned long long cputime_t;
17typedef unsigned long long cputime64_t;
18
19#ifndef __s390x__
20
21static inline unsigned int
22__div(unsigned long long n, unsigned int base)
23{
24 register_pair rp;
25
26 rp.pair = n >> 1;
27 asm ("dr %0,%1" : "+d" (rp) : "d" (base >> 1));
28 return rp.subreg.odd;
29}
30
31#else /* __s390x__ */
32
33static inline unsigned int
34__div(unsigned long long n, unsigned int base)
35{
36 return n / base;
37}
38
39#endif /* __s390x__ */
40
41#define cputime_zero (0ULL)
42#define cputime_max ((~0UL >> 1) - 1)
43#define cputime_add(__a, __b) ((__a) + (__b))
44#define cputime_sub(__a, __b) ((__a) - (__b))
45#define cputime_div(__a, __n) ({ \
46 unsigned long long __div = (__a); \
47 do_div(__div,__n); \
48 __div; \
49})
50#define cputime_halve(__a) ((__a) >> 1)
51#define cputime_eq(__a, __b) ((__a) == (__b))
52#define cputime_gt(__a, __b) ((__a) > (__b))
53#define cputime_ge(__a, __b) ((__a) >= (__b))
54#define cputime_lt(__a, __b) ((__a) < (__b))
55#define cputime_le(__a, __b) ((__a) <= (__b))
56#define cputime_to_jiffies(__ct) (__div((__ct), 1000000 / HZ))
57#define cputime_to_scaled(__ct) (__ct)
58#define jiffies_to_cputime(__hz) ((cputime_t)(__hz) * (1000000 / HZ))
59
60#define cputime64_zero (0ULL)
61#define cputime64_add(__a, __b) ((__a) + (__b))
62#define cputime_to_cputime64(__ct) (__ct)
63
64static inline u64
65cputime64_to_jiffies64(cputime64_t cputime)
66{
67 do_div(cputime, 1000000 / HZ);
68 return cputime;
69}
70
71/*
72 * Convert cputime to milliseconds and back.
73 */
74static inline unsigned int
75cputime_to_msecs(const cputime_t cputime)
76{
77 return __div(cputime, 1000);
78}
79
80static inline cputime_t
81msecs_to_cputime(const unsigned int m)
82{
83 return (cputime_t) m * 1000;
84}
85
86/*
87 * Convert cputime to milliseconds and back.
88 */
89static inline unsigned int
90cputime_to_secs(const cputime_t cputime)
91{
92 return __div(cputime, 1000000);
93}
94
95static inline cputime_t
96secs_to_cputime(const unsigned int s)
97{
98 return (cputime_t) s * 1000000;
99}
100
101/*
102 * Convert cputime to timespec and back.
103 */
104static inline cputime_t
105timespec_to_cputime(const struct timespec *value)
106{
107 return value->tv_nsec / 1000 + (u64) value->tv_sec * 1000000;
108}
109
110static inline void
111cputime_to_timespec(const cputime_t cputime, struct timespec *value)
112{
113#ifndef __s390x__
114 register_pair rp;
115
116 rp.pair = cputime >> 1;
117 asm ("dr %0,%1" : "+d" (rp) : "d" (1000000 >> 1));
118 value->tv_nsec = rp.subreg.even * 1000;
119 value->tv_sec = rp.subreg.odd;
120#else
121 value->tv_nsec = (cputime % 1000000) * 1000;
122 value->tv_sec = cputime / 1000000;
123#endif
124}
125
126/*
127 * Convert cputime to timeval and back.
128 * Since cputime and timeval have the same resolution (microseconds)
129 * this is easy.
130 */
131static inline cputime_t
132timeval_to_cputime(const struct timeval *value)
133{
134 return value->tv_usec + (u64) value->tv_sec * 1000000;
135}
136
137static inline void
138cputime_to_timeval(const cputime_t cputime, struct timeval *value)
139{
140#ifndef __s390x__
141 register_pair rp;
142
143 rp.pair = cputime >> 1;
144 asm ("dr %0,%1" : "+d" (rp) : "d" (1000000 >> 1));
145 value->tv_usec = rp.subreg.even;
146 value->tv_sec = rp.subreg.odd;
147#else
148 value->tv_usec = cputime % 1000000;
149 value->tv_sec = cputime / 1000000;
150#endif
151}
152
153/*
154 * Convert cputime to clock and back.
155 */
156static inline clock_t
157cputime_to_clock_t(cputime_t cputime)
158{
159 return __div(cputime, 1000000 / USER_HZ);
160}
161
162static inline cputime_t
163clock_t_to_cputime(unsigned long x)
164{
165 return (cputime_t) x * (1000000 / USER_HZ);
166}
167
168/*
169 * Convert cputime64 to clock.
170 */
171static inline clock_t
172cputime64_to_clock_t(cputime64_t cputime)
173{
174 return __div(cputime, 1000000 / USER_HZ);
175}
176
177#endif /* _S390_CPUTIME_H */
diff --git a/include/asm-s390/current.h b/include/asm-s390/current.h
deleted file mode 100644
index 83cf36cde2d..00000000000
--- a/include/asm-s390/current.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * include/asm-s390/current.h
3 *
4 * S390 version
5 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
7 *
8 * Derived from "include/asm-i386/current.h"
9 */
10
11#ifndef _S390_CURRENT_H
12#define _S390_CURRENT_H
13
14#ifdef __KERNEL__
15#include <asm/lowcore.h>
16
17struct task_struct;
18
19#define current ((struct task_struct *const)S390_lowcore.current_task)
20
21#endif
22
23#endif /* !(_S390_CURRENT_H) */
diff --git a/include/asm-s390/dasd.h b/include/asm-s390/dasd.h
deleted file mode 100644
index 3f002e13d02..00000000000
--- a/include/asm-s390/dasd.h
+++ /dev/null
@@ -1,270 +0,0 @@
1/*
2 * File...........: linux/drivers/s390/block/dasd.c
3 * Author(s)......: Holger Smolinski <Holger.Smolinski@de.ibm.com>
4 * Bugreports.to..: <Linux390@de.ibm.com>
5 * (C) IBM Corporation, IBM Deutschland Entwicklung GmbH, 1999,2000
6 *
7 * This file is the interface of the DASD device driver, which is exported to user space
8 * any future changes wrt the API will result in a change of the APIVERSION reported
9 * to userspace by the DASDAPIVER-ioctl
10 *
11 */
12
13#ifndef DASD_H
14#define DASD_H
15#include <linux/ioctl.h>
16
17#define DASD_IOCTL_LETTER 'D'
18
19#define DASD_API_VERSION 6
20
21/*
22 * struct dasd_information2_t
23 * represents any data about the device, which is visible to userspace.
24 * including foramt and featueres.
25 */
26typedef struct dasd_information2_t {
27 unsigned int devno; /* S/390 devno */
28 unsigned int real_devno; /* for aliases */
29 unsigned int schid; /* S/390 subchannel identifier */
30 unsigned int cu_type : 16; /* from SenseID */
31 unsigned int cu_model : 8; /* from SenseID */
32 unsigned int dev_type : 16; /* from SenseID */
33 unsigned int dev_model : 8; /* from SenseID */
34 unsigned int open_count;
35 unsigned int req_queue_len;
36 unsigned int chanq_len; /* length of chanq */
37 char type[4]; /* from discipline.name, 'none' for unknown */
38 unsigned int status; /* current device level */
39 unsigned int label_block; /* where to find the VOLSER */
40 unsigned int FBA_layout; /* fixed block size (like AIXVOL) */
41 unsigned int characteristics_size;
42 unsigned int confdata_size;
43 char characteristics[64]; /* from read_device_characteristics */
44 char configuration_data[256]; /* from read_configuration_data */
45 unsigned int format; /* format info like formatted/cdl/ldl/... */
46 unsigned int features; /* dasd features like 'ro',... */
47 unsigned int reserved0; /* reserved for further use ,... */
48 unsigned int reserved1; /* reserved for further use ,... */
49 unsigned int reserved2; /* reserved for further use ,... */
50 unsigned int reserved3; /* reserved for further use ,... */
51 unsigned int reserved4; /* reserved for further use ,... */
52 unsigned int reserved5; /* reserved for further use ,... */
53 unsigned int reserved6; /* reserved for further use ,... */
54 unsigned int reserved7; /* reserved for further use ,... */
55} dasd_information2_t;
56
57/*
58 * values to be used for dasd_information_t.format
59 * 0x00: NOT formatted
60 * 0x01: Linux disc layout
61 * 0x02: Common disc layout
62 */
63#define DASD_FORMAT_NONE 0
64#define DASD_FORMAT_LDL 1
65#define DASD_FORMAT_CDL 2
66/*
67 * values to be used for dasd_information_t.features
68 * 0x00: default features
69 * 0x01: readonly (ro)
70 * 0x02: use diag discipline (diag)
71 * 0x04: set the device initially online (internal use only)
72 * 0x08: enable ERP related logging
73 */
74#define DASD_FEATURE_DEFAULT 0x00
75#define DASD_FEATURE_READONLY 0x01
76#define DASD_FEATURE_USEDIAG 0x02
77#define DASD_FEATURE_INITIAL_ONLINE 0x04
78#define DASD_FEATURE_ERPLOG 0x08
79
80#define DASD_PARTN_BITS 2
81
82/*
83 * struct dasd_information_t
84 * represents any data about the data, which is visible to userspace
85 */
86typedef struct dasd_information_t {
87 unsigned int devno; /* S/390 devno */
88 unsigned int real_devno; /* for aliases */
89 unsigned int schid; /* S/390 subchannel identifier */
90 unsigned int cu_type : 16; /* from SenseID */
91 unsigned int cu_model : 8; /* from SenseID */
92 unsigned int dev_type : 16; /* from SenseID */
93 unsigned int dev_model : 8; /* from SenseID */
94 unsigned int open_count;
95 unsigned int req_queue_len;
96 unsigned int chanq_len; /* length of chanq */
97 char type[4]; /* from discipline.name, 'none' for unknown */
98 unsigned int status; /* current device level */
99 unsigned int label_block; /* where to find the VOLSER */
100 unsigned int FBA_layout; /* fixed block size (like AIXVOL) */
101 unsigned int characteristics_size;
102 unsigned int confdata_size;
103 char characteristics[64]; /* from read_device_characteristics */
104 char configuration_data[256]; /* from read_configuration_data */
105} dasd_information_t;
106
107/*
108 * Read Subsystem Data - Performance Statistics
109 */
110typedef struct dasd_rssd_perf_stats_t {
111 unsigned char invalid:1;
112 unsigned char format:3;
113 unsigned char data_format:4;
114 unsigned char unit_address;
115 unsigned short device_status;
116 unsigned int nr_read_normal;
117 unsigned int nr_read_normal_hits;
118 unsigned int nr_write_normal;
119 unsigned int nr_write_fast_normal_hits;
120 unsigned int nr_read_seq;
121 unsigned int nr_read_seq_hits;
122 unsigned int nr_write_seq;
123 unsigned int nr_write_fast_seq_hits;
124 unsigned int nr_read_cache;
125 unsigned int nr_read_cache_hits;
126 unsigned int nr_write_cache;
127 unsigned int nr_write_fast_cache_hits;
128 unsigned int nr_inhibit_cache;
129 unsigned int nr_bybass_cache;
130 unsigned int nr_seq_dasd_to_cache;
131 unsigned int nr_dasd_to_cache;
132 unsigned int nr_cache_to_dasd;
133 unsigned int nr_delayed_fast_write;
134 unsigned int nr_normal_fast_write;
135 unsigned int nr_seq_fast_write;
136 unsigned int nr_cache_miss;
137 unsigned char status2;
138 unsigned int nr_quick_write_promotes;
139 unsigned char reserved;
140 unsigned short ssid;
141 unsigned char reseved2[96];
142} __attribute__((packed)) dasd_rssd_perf_stats_t;
143
144/*
145 * struct profile_info_t
146 * holds the profinling information
147 */
148typedef struct dasd_profile_info_t {
149 unsigned int dasd_io_reqs; /* number of requests processed at all */
150 unsigned int dasd_io_sects; /* number of sectors processed at all */
151 unsigned int dasd_io_secs[32]; /* histogram of request's sizes */
152 unsigned int dasd_io_times[32]; /* histogram of requests's times */
153 unsigned int dasd_io_timps[32]; /* histogram of requests's times per sector */
154 unsigned int dasd_io_time1[32]; /* histogram of time from build to start */
155 unsigned int dasd_io_time2[32]; /* histogram of time from start to irq */
156 unsigned int dasd_io_time2ps[32]; /* histogram of time from start to irq */
157 unsigned int dasd_io_time3[32]; /* histogram of time from irq to end */
158 unsigned int dasd_io_nr_req[32]; /* histogram of # of requests in chanq */
159} dasd_profile_info_t;
160
161/*
162 * struct format_data_t
163 * represents all data necessary to format a dasd
164 */
165typedef struct format_data_t {
166 int start_unit; /* from track */
167 int stop_unit; /* to track */
168 int blksize; /* sectorsize */
169 int intensity;
170} format_data_t;
171
172/*
173 * values to be used for format_data_t.intensity
174 * 0/8: normal format
175 * 1/9: also write record zero
176 * 3/11: also write home address
177 * 4/12: invalidate track
178 */
179#define DASD_FMT_INT_FMT_R0 1 /* write record zero */
180#define DASD_FMT_INT_FMT_HA 2 /* write home address, also set FMT_R0 ! */
181#define DASD_FMT_INT_INVAL 4 /* invalidate tracks */
182#define DASD_FMT_INT_COMPAT 8 /* use OS/390 compatible disk layout */
183
184
185/*
186 * struct attrib_data_t
187 * represents the operation (cache) bits for the device.
188 * Used in DE to influence caching of the DASD.
189 */
190typedef struct attrib_data_t {
191 unsigned char operation:3; /* cache operation mode */
192 unsigned char reserved:5; /* cache operation mode */
193 __u16 nr_cyl; /* no of cyliners for read ahaed */
194 __u8 reserved2[29]; /* for future use */
195} __attribute__ ((packed)) attrib_data_t;
196
197/* definition of operation (cache) bits within attributes of DE */
198#define DASD_NORMAL_CACHE 0x0
199#define DASD_BYPASS_CACHE 0x1
200#define DASD_INHIBIT_LOAD 0x2
201#define DASD_SEQ_ACCESS 0x3
202#define DASD_SEQ_PRESTAGE 0x4
203#define DASD_REC_ACCESS 0x5
204
205
206/********************************************************************************
207 * SECTION: Definition of IOCTLs
208 *
209 * Here ist how the ioctl-nr should be used:
210 * 0 - 31 DASD driver itself
211 * 32 - 239 still open
212 * 240 - 255 reserved for EMC
213 *******************************************************************************/
214
215/* Disable the volume (for Linux) */
216#define BIODASDDISABLE _IO(DASD_IOCTL_LETTER,0)
217/* Enable the volume (for Linux) */
218#define BIODASDENABLE _IO(DASD_IOCTL_LETTER,1)
219/* Issue a reserve/release command, rsp. */
220#define BIODASDRSRV _IO(DASD_IOCTL_LETTER,2) /* reserve */
221#define BIODASDRLSE _IO(DASD_IOCTL_LETTER,3) /* release */
222#define BIODASDSLCK _IO(DASD_IOCTL_LETTER,4) /* steal lock */
223/* reset profiling information of a device */
224#define BIODASDPRRST _IO(DASD_IOCTL_LETTER,5)
225/* Quiesce IO on device */
226#define BIODASDQUIESCE _IO(DASD_IOCTL_LETTER,6)
227/* Resume IO on device */
228#define BIODASDRESUME _IO(DASD_IOCTL_LETTER,7)
229
230
231/* retrieve API version number */
232#define DASDAPIVER _IOR(DASD_IOCTL_LETTER,0,int)
233/* Get information on a dasd device */
234#define BIODASDINFO _IOR(DASD_IOCTL_LETTER,1,dasd_information_t)
235/* retrieve profiling information of a device */
236#define BIODASDPRRD _IOR(DASD_IOCTL_LETTER,2,dasd_profile_info_t)
237/* Get information on a dasd device (enhanced) */
238#define BIODASDINFO2 _IOR(DASD_IOCTL_LETTER,3,dasd_information2_t)
239/* Performance Statistics Read */
240#define BIODASDPSRD _IOR(DASD_IOCTL_LETTER,4,dasd_rssd_perf_stats_t)
241/* Get Attributes (cache operations) */
242#define BIODASDGATTR _IOR(DASD_IOCTL_LETTER,5,attrib_data_t)
243
244
245/* #define BIODASDFORMAT _IOW(IOCTL_LETTER,0,format_data_t) , deprecated */
246#define BIODASDFMT _IOW(DASD_IOCTL_LETTER,1,format_data_t)
247/* Set Attributes (cache operations) */
248#define BIODASDSATTR _IOW(DASD_IOCTL_LETTER,2,attrib_data_t)
249
250
251#endif /* DASD_H */
252
253/*
254 * Overrides for Emacs so that we follow Linus's tabbing style.
255 * Emacs will notice this stuff at the end of the file and automatically
256 * adjust the settings for this buffer only. This must remain at the end
257 * of the file.
258 * ---------------------------------------------------------------------------
259 * Local variables:
260 * c-indent-level: 4
261 * c-brace-imaginary-offset: 0
262 * c-brace-offset: -4
263 * c-argdecl-indent: 4
264 * c-label-offset: -4
265 * c-continued-statement-offset: 4
266 * c-continued-brace-offset: 0
267 * indent-tabs-mode: nil
268 * tab-width: 8
269 * End:
270 */
diff --git a/include/asm-s390/debug.h b/include/asm-s390/debug.h
deleted file mode 100644
index 9450ce6e32d..00000000000
--- a/include/asm-s390/debug.h
+++ /dev/null
@@ -1,261 +0,0 @@
1/*
2 * include/asm-s390/debug.h
3 * S/390 debug facility
4 *
5 * Copyright (C) 1999, 2000 IBM Deutschland Entwicklung GmbH,
6 * IBM Corporation
7 */
8
9#ifndef DEBUG_H
10#define DEBUG_H
11
12#include <linux/fs.h>
13
14/* Note:
15 * struct __debug_entry must be defined outside of #ifdef __KERNEL__
16 * in order to allow a user program to analyze the 'raw'-view.
17 */
18
19struct __debug_entry{
20 union {
21 struct {
22 unsigned long long clock:52;
23 unsigned long long exception:1;
24 unsigned long long level:3;
25 unsigned long long cpuid:8;
26 } fields;
27
28 unsigned long long stck;
29 } id;
30 void* caller;
31} __attribute__((packed));
32
33
34#define __DEBUG_FEATURE_VERSION 2 /* version of debug feature */
35
36#ifdef __KERNEL__
37#include <linux/string.h>
38#include <linux/spinlock.h>
39#include <linux/kernel.h>
40#include <linux/time.h>
41
42#define DEBUG_MAX_LEVEL 6 /* debug levels range from 0 to 6 */
43#define DEBUG_OFF_LEVEL -1 /* level where debug is switched off */
44#define DEBUG_FLUSH_ALL -1 /* parameter to flush all areas */
45#define DEBUG_MAX_VIEWS 10 /* max number of views in proc fs */
46#define DEBUG_MAX_NAME_LEN 64 /* max length for a debugfs file name */
47#define DEBUG_DEFAULT_LEVEL 3 /* initial debug level */
48
49#define DEBUG_DIR_ROOT "s390dbf" /* name of debug root directory in proc fs */
50
51#define DEBUG_DATA(entry) (char*)(entry + 1) /* data is stored behind */
52 /* the entry information */
53
54typedef struct __debug_entry debug_entry_t;
55
56struct debug_view;
57
58typedef struct debug_info {
59 struct debug_info* next;
60 struct debug_info* prev;
61 atomic_t ref_count;
62 spinlock_t lock;
63 int level;
64 int nr_areas;
65 int pages_per_area;
66 int buf_size;
67 int entry_size;
68 debug_entry_t*** areas;
69 int active_area;
70 int *active_pages;
71 int *active_entries;
72 struct dentry* debugfs_root_entry;
73 struct dentry* debugfs_entries[DEBUG_MAX_VIEWS];
74 struct debug_view* views[DEBUG_MAX_VIEWS];
75 char name[DEBUG_MAX_NAME_LEN];
76 mode_t mode;
77} debug_info_t;
78
79typedef int (debug_header_proc_t) (debug_info_t* id,
80 struct debug_view* view,
81 int area,
82 debug_entry_t* entry,
83 char* out_buf);
84
85typedef int (debug_format_proc_t) (debug_info_t* id,
86 struct debug_view* view, char* out_buf,
87 const char* in_buf);
88typedef int (debug_prolog_proc_t) (debug_info_t* id,
89 struct debug_view* view,
90 char* out_buf);
91typedef int (debug_input_proc_t) (debug_info_t* id,
92 struct debug_view* view,
93 struct file* file,
94 const char __user *user_buf,
95 size_t in_buf_size, loff_t* offset);
96
97int debug_dflt_header_fn(debug_info_t* id, struct debug_view* view,
98 int area, debug_entry_t* entry, char* out_buf);
99
100struct debug_view {
101 char name[DEBUG_MAX_NAME_LEN];
102 debug_prolog_proc_t* prolog_proc;
103 debug_header_proc_t* header_proc;
104 debug_format_proc_t* format_proc;
105 debug_input_proc_t* input_proc;
106 void* private_data;
107};
108
109extern struct debug_view debug_hex_ascii_view;
110extern struct debug_view debug_raw_view;
111extern struct debug_view debug_sprintf_view;
112
113/* do NOT use the _common functions */
114
115debug_entry_t* debug_event_common(debug_info_t* id, int level,
116 const void* data, int length);
117
118debug_entry_t* debug_exception_common(debug_info_t* id, int level,
119 const void* data, int length);
120
121/* Debug Feature API: */
122
123debug_info_t *debug_register(const char *name, int pages, int nr_areas,
124 int buf_size);
125
126debug_info_t *debug_register_mode(const char *name, int pages, int nr_areas,
127 int buf_size, mode_t mode, uid_t uid,
128 gid_t gid);
129
130void debug_unregister(debug_info_t* id);
131
132void debug_set_level(debug_info_t* id, int new_level);
133
134void debug_stop_all(void);
135
136static inline debug_entry_t*
137debug_event(debug_info_t* id, int level, void* data, int length)
138{
139 if ((!id) || (level > id->level) || (id->pages_per_area == 0))
140 return NULL;
141 return debug_event_common(id,level,data,length);
142}
143
144static inline debug_entry_t*
145debug_int_event(debug_info_t* id, int level, unsigned int tag)
146{
147 unsigned int t=tag;
148 if ((!id) || (level > id->level) || (id->pages_per_area == 0))
149 return NULL;
150 return debug_event_common(id,level,&t,sizeof(unsigned int));
151}
152
153static inline debug_entry_t *
154debug_long_event (debug_info_t* id, int level, unsigned long tag)
155{
156 unsigned long t=tag;
157 if ((!id) || (level > id->level) || (id->pages_per_area == 0))
158 return NULL;
159 return debug_event_common(id,level,&t,sizeof(unsigned long));
160}
161
162static inline debug_entry_t*
163debug_text_event(debug_info_t* id, int level, const char* txt)
164{
165 if ((!id) || (level > id->level) || (id->pages_per_area == 0))
166 return NULL;
167 return debug_event_common(id,level,txt,strlen(txt));
168}
169
170extern debug_entry_t *
171debug_sprintf_event(debug_info_t* id,int level,char *string,...)
172 __attribute__ ((format(printf, 3, 4)));
173
174
175static inline debug_entry_t*
176debug_exception(debug_info_t* id, int level, void* data, int length)
177{
178 if ((!id) || (level > id->level) || (id->pages_per_area == 0))
179 return NULL;
180 return debug_exception_common(id,level,data,length);
181}
182
183static inline debug_entry_t*
184debug_int_exception(debug_info_t* id, int level, unsigned int tag)
185{
186 unsigned int t=tag;
187 if ((!id) || (level > id->level) || (id->pages_per_area == 0))
188 return NULL;
189 return debug_exception_common(id,level,&t,sizeof(unsigned int));
190}
191
192static inline debug_entry_t *
193debug_long_exception (debug_info_t* id, int level, unsigned long tag)
194{
195 unsigned long t=tag;
196 if ((!id) || (level > id->level) || (id->pages_per_area == 0))
197 return NULL;
198 return debug_exception_common(id,level,&t,sizeof(unsigned long));
199}
200
201static inline debug_entry_t*
202debug_text_exception(debug_info_t* id, int level, const char* txt)
203{
204 if ((!id) || (level > id->level) || (id->pages_per_area == 0))
205 return NULL;
206 return debug_exception_common(id,level,txt,strlen(txt));
207}
208
209
210extern debug_entry_t *
211debug_sprintf_exception(debug_info_t* id,int level,char *string,...)
212 __attribute__ ((format(printf, 3, 4)));
213
214int debug_register_view(debug_info_t* id, struct debug_view* view);
215int debug_unregister_view(debug_info_t* id, struct debug_view* view);
216
217/*
218 define the debug levels:
219 - 0 No debugging output to console or syslog
220 - 1 Log internal errors to syslog, ignore check conditions
221 - 2 Log internal errors and check conditions to syslog
222 - 3 Log internal errors to console, log check conditions to syslog
223 - 4 Log internal errors and check conditions to console
224 - 5 panic on internal errors, log check conditions to console
225 - 6 panic on both, internal errors and check conditions
226 */
227
228#ifndef DEBUG_LEVEL
229#define DEBUG_LEVEL 4
230#endif
231
232#define INTERNAL_ERRMSG(x,y...) "E" __FILE__ "%d: " x, __LINE__, y
233#define INTERNAL_WRNMSG(x,y...) "W" __FILE__ "%d: " x, __LINE__, y
234#define INTERNAL_INFMSG(x,y...) "I" __FILE__ "%d: " x, __LINE__, y
235#define INTERNAL_DEBMSG(x,y...) "D" __FILE__ "%d: " x, __LINE__, y
236
237#if DEBUG_LEVEL > 0
238#define PRINT_DEBUG(x...) printk ( KERN_DEBUG PRINTK_HEADER x )
239#define PRINT_INFO(x...) printk ( KERN_INFO PRINTK_HEADER x )
240#define PRINT_WARN(x...) printk ( KERN_WARNING PRINTK_HEADER x )
241#define PRINT_ERR(x...) printk ( KERN_ERR PRINTK_HEADER x )
242#define PRINT_FATAL(x...) panic ( PRINTK_HEADER x )
243#else
244#define PRINT_DEBUG(x...) printk ( KERN_DEBUG PRINTK_HEADER x )
245#define PRINT_INFO(x...) printk ( KERN_DEBUG PRINTK_HEADER x )
246#define PRINT_WARN(x...) printk ( KERN_DEBUG PRINTK_HEADER x )
247#define PRINT_ERR(x...) printk ( KERN_DEBUG PRINTK_HEADER x )
248#define PRINT_FATAL(x...) printk ( KERN_DEBUG PRINTK_HEADER x )
249#endif /* DASD_DEBUG */
250
251#undef DEBUG_MALLOC
252#ifdef DEBUG_MALLOC
253void *b;
254#define kmalloc(x...) (PRINT_INFO(" kmalloc %p\n",b=kmalloc(x)),b)
255#define kfree(x) PRINT_INFO(" kfree %p\n",x);kfree(x)
256#define get_zeroed_page(x...) (PRINT_INFO(" gfp %p\n",b=get_zeroed_page(x)),b)
257#define __get_free_pages(x...) (PRINT_INFO(" gfps %p\n",b=__get_free_pages(x)),b)
258#endif /* DEBUG_MALLOC */
259
260#endif /* __KERNEL__ */
261#endif /* DEBUG_H */
diff --git a/include/asm-s390/delay.h b/include/asm-s390/delay.h
deleted file mode 100644
index 78357314c45..00000000000
--- a/include/asm-s390/delay.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * include/asm-s390/delay.h
3 *
4 * S390 version
5 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
7 *
8 * Derived from "include/asm-i386/delay.h"
9 * Copyright (C) 1993 Linus Torvalds
10 *
11 * Delay routines calling functions in arch/s390/lib/delay.c
12 */
13
14#ifndef _S390_DELAY_H
15#define _S390_DELAY_H
16
17extern void __udelay(unsigned long usecs);
18extern void __delay(unsigned long loops);
19
20#define udelay(n) __udelay(n)
21
22#endif /* defined(_S390_DELAY_H) */
diff --git a/include/asm-s390/device.h b/include/asm-s390/device.h
deleted file mode 100644
index d8f9872b0e2..00000000000
--- a/include/asm-s390/device.h
+++ /dev/null
@@ -1,7 +0,0 @@
1/*
2 * Arch specific extensions to struct device
3 *
4 * This file is released under the GPLv2
5 */
6#include <asm-generic/device.h>
7
diff --git a/include/asm-s390/diag.h b/include/asm-s390/diag.h
deleted file mode 100644
index 72b2e2f2d32..00000000000
--- a/include/asm-s390/diag.h
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * s390 diagnose functions
3 *
4 * Copyright IBM Corp. 2007
5 * Author(s): Michael Holzheu <holzheu@de.ibm.com>
6 */
7
8#ifndef _ASM_S390_DIAG_H
9#define _ASM_S390_DIAG_H
10
11/*
12 * Diagnose 10: Release pages
13 */
14extern void diag10(unsigned long addr);
15
16/*
17 * Diagnose 14: Input spool file manipulation
18 */
19extern int diag14(unsigned long rx, unsigned long ry1, unsigned long subcode);
20
21/*
22 * Diagnose 210: Get information about a virtual device
23 */
24struct diag210 {
25 u16 vrdcdvno; /* device number (input) */
26 u16 vrdclen; /* data block length (input) */
27 u8 vrdcvcla; /* virtual device class (output) */
28 u8 vrdcvtyp; /* virtual device type (output) */
29 u8 vrdcvsta; /* virtual device status (output) */
30 u8 vrdcvfla; /* virtual device flags (output) */
31 u8 vrdcrccl; /* real device class (output) */
32 u8 vrdccrty; /* real device type (output) */
33 u8 vrdccrmd; /* real device model (output) */
34 u8 vrdccrft; /* real device feature (output) */
35} __attribute__((packed, aligned(4)));
36
37extern int diag210(struct diag210 *addr);
38
39#endif /* _ASM_S390_DIAG_H */
diff --git a/include/asm-s390/div64.h b/include/asm-s390/div64.h
deleted file mode 100644
index 6cd978cefb2..00000000000
--- a/include/asm-s390/div64.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/div64.h>
diff --git a/include/asm-s390/dma.h b/include/asm-s390/dma.h
deleted file mode 100644
index 7425c6af6cd..00000000000
--- a/include/asm-s390/dma.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * include/asm-s390/dma.h
3 *
4 * S390 version
5 */
6
7#ifndef _ASM_DMA_H
8#define _ASM_DMA_H
9
10#include <asm/io.h> /* need byte IO */
11
12#define MAX_DMA_ADDRESS 0x80000000
13
14#define free_dma(x) do { } while (0)
15
16#endif /* _ASM_DMA_H */
diff --git a/include/asm-s390/ebcdic.h b/include/asm-s390/ebcdic.h
deleted file mode 100644
index 7f6f641d32f..00000000000
--- a/include/asm-s390/ebcdic.h
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * include/asm-s390/ebcdic.h
3 * EBCDIC -> ASCII, ASCII -> EBCDIC conversion routines.
4 *
5 * S390 version
6 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
7 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
8 */
9
10#ifndef _EBCDIC_H
11#define _EBCDIC_H
12
13#ifndef _S390_TYPES_H
14#include <types.h>
15#endif
16
17extern __u8 _ascebc_500[256]; /* ASCII -> EBCDIC 500 conversion table */
18extern __u8 _ebcasc_500[256]; /* EBCDIC 500 -> ASCII conversion table */
19extern __u8 _ascebc[256]; /* ASCII -> EBCDIC conversion table */
20extern __u8 _ebcasc[256]; /* EBCDIC -> ASCII conversion table */
21extern __u8 _ebc_tolower[256]; /* EBCDIC -> lowercase */
22extern __u8 _ebc_toupper[256]; /* EBCDIC -> uppercase */
23
24static inline void
25codepage_convert(const __u8 *codepage, volatile __u8 * addr, unsigned long nr)
26{
27 if (nr-- <= 0)
28 return;
29 asm volatile(
30 " bras 1,1f\n"
31 " tr 0(1,%0),0(%2)\n"
32 "0: tr 0(256,%0),0(%2)\n"
33 " la %0,256(%0)\n"
34 "1: ahi %1,-256\n"
35 " jnm 0b\n"
36 " ex %1,0(1)"
37 : "+&a" (addr), "+&a" (nr)
38 : "a" (codepage) : "cc", "memory", "1");
39}
40
41#define ASCEBC(addr,nr) codepage_convert(_ascebc, addr, nr)
42#define EBCASC(addr,nr) codepage_convert(_ebcasc, addr, nr)
43#define ASCEBC_500(addr,nr) codepage_convert(_ascebc_500, addr, nr)
44#define EBCASC_500(addr,nr) codepage_convert(_ebcasc_500, addr, nr)
45#define EBC_TOLOWER(addr,nr) codepage_convert(_ebc_tolower, addr, nr)
46#define EBC_TOUPPER(addr,nr) codepage_convert(_ebc_toupper, addr, nr)
47
48#endif
49
diff --git a/include/asm-s390/elf.h b/include/asm-s390/elf.h
deleted file mode 100644
index 3cad5692381..00000000000
--- a/include/asm-s390/elf.h
+++ /dev/null
@@ -1,196 +0,0 @@
1/*
2 * include/asm-s390/elf.h
3 *
4 * S390 version
5 *
6 * Derived from "include/asm-i386/elf.h"
7 */
8
9#ifndef __ASMS390_ELF_H
10#define __ASMS390_ELF_H
11
12/* s390 relocations defined by the ABIs */
13#define R_390_NONE 0 /* No reloc. */
14#define R_390_8 1 /* Direct 8 bit. */
15#define R_390_12 2 /* Direct 12 bit. */
16#define R_390_16 3 /* Direct 16 bit. */
17#define R_390_32 4 /* Direct 32 bit. */
18#define R_390_PC32 5 /* PC relative 32 bit. */
19#define R_390_GOT12 6 /* 12 bit GOT offset. */
20#define R_390_GOT32 7 /* 32 bit GOT offset. */
21#define R_390_PLT32 8 /* 32 bit PC relative PLT address. */
22#define R_390_COPY 9 /* Copy symbol at runtime. */
23#define R_390_GLOB_DAT 10 /* Create GOT entry. */
24#define R_390_JMP_SLOT 11 /* Create PLT entry. */
25#define R_390_RELATIVE 12 /* Adjust by program base. */
26#define R_390_GOTOFF32 13 /* 32 bit offset to GOT. */
27#define R_390_GOTPC 14 /* 32 bit PC rel. offset to GOT. */
28#define R_390_GOT16 15 /* 16 bit GOT offset. */
29#define R_390_PC16 16 /* PC relative 16 bit. */
30#define R_390_PC16DBL 17 /* PC relative 16 bit shifted by 1. */
31#define R_390_PLT16DBL 18 /* 16 bit PC rel. PLT shifted by 1. */
32#define R_390_PC32DBL 19 /* PC relative 32 bit shifted by 1. */
33#define R_390_PLT32DBL 20 /* 32 bit PC rel. PLT shifted by 1. */
34#define R_390_GOTPCDBL 21 /* 32 bit PC rel. GOT shifted by 1. */
35#define R_390_64 22 /* Direct 64 bit. */
36#define R_390_PC64 23 /* PC relative 64 bit. */
37#define R_390_GOT64 24 /* 64 bit GOT offset. */
38#define R_390_PLT64 25 /* 64 bit PC relative PLT address. */
39#define R_390_GOTENT 26 /* 32 bit PC rel. to GOT entry >> 1. */
40#define R_390_GOTOFF16 27 /* 16 bit offset to GOT. */
41#define R_390_GOTOFF64 28 /* 64 bit offset to GOT. */
42#define R_390_GOTPLT12 29 /* 12 bit offset to jump slot. */
43#define R_390_GOTPLT16 30 /* 16 bit offset to jump slot. */
44#define R_390_GOTPLT32 31 /* 32 bit offset to jump slot. */
45#define R_390_GOTPLT64 32 /* 64 bit offset to jump slot. */
46#define R_390_GOTPLTENT 33 /* 32 bit rel. offset to jump slot. */
47#define R_390_PLTOFF16 34 /* 16 bit offset from GOT to PLT. */
48#define R_390_PLTOFF32 35 /* 32 bit offset from GOT to PLT. */
49#define R_390_PLTOFF64 36 /* 16 bit offset from GOT to PLT. */
50#define R_390_TLS_LOAD 37 /* Tag for load insn in TLS code. */
51#define R_390_TLS_GDCALL 38 /* Tag for function call in general
52 dynamic TLS code. */
53#define R_390_TLS_LDCALL 39 /* Tag for function call in local
54 dynamic TLS code. */
55#define R_390_TLS_GD32 40 /* Direct 32 bit for general dynamic
56 thread local data. */
57#define R_390_TLS_GD64 41 /* Direct 64 bit for general dynamic
58 thread local data. */
59#define R_390_TLS_GOTIE12 42 /* 12 bit GOT offset for static TLS
60 block offset. */
61#define R_390_TLS_GOTIE32 43 /* 32 bit GOT offset for static TLS
62 block offset. */
63#define R_390_TLS_GOTIE64 44 /* 64 bit GOT offset for static TLS
64 block offset. */
65#define R_390_TLS_LDM32 45 /* Direct 32 bit for local dynamic
66 thread local data in LD code. */
67#define R_390_TLS_LDM64 46 /* Direct 64 bit for local dynamic
68 thread local data in LD code. */
69#define R_390_TLS_IE32 47 /* 32 bit address of GOT entry for
70 negated static TLS block offset. */
71#define R_390_TLS_IE64 48 /* 64 bit address of GOT entry for
72 negated static TLS block offset. */
73#define R_390_TLS_IEENT 49 /* 32 bit rel. offset to GOT entry for
74 negated static TLS block offset. */
75#define R_390_TLS_LE32 50 /* 32 bit negated offset relative to
76 static TLS block. */
77#define R_390_TLS_LE64 51 /* 64 bit negated offset relative to
78 static TLS block. */
79#define R_390_TLS_LDO32 52 /* 32 bit offset relative to TLS
80 block. */
81#define R_390_TLS_LDO64 53 /* 64 bit offset relative to TLS
82 block. */
83#define R_390_TLS_DTPMOD 54 /* ID of module containing symbol. */
84#define R_390_TLS_DTPOFF 55 /* Offset in TLS block. */
85#define R_390_TLS_TPOFF 56 /* Negate offset in static TLS
86 block. */
87#define R_390_20 57 /* Direct 20 bit. */
88#define R_390_GOT20 58 /* 20 bit GOT offset. */
89#define R_390_GOTPLT20 59 /* 20 bit offset to jump slot. */
90#define R_390_TLS_GOTIE20 60 /* 20 bit GOT offset for static TLS
91 block offset. */
92/* Keep this the last entry. */
93#define R_390_NUM 61
94
95/*
96 * These are used to set parameters in the core dumps.
97 */
98#ifndef __s390x__
99#define ELF_CLASS ELFCLASS32
100#else /* __s390x__ */
101#define ELF_CLASS ELFCLASS64
102#endif /* __s390x__ */
103#define ELF_DATA ELFDATA2MSB
104#define ELF_ARCH EM_S390
105
106/*
107 * ELF register definitions..
108 */
109
110#include <asm/ptrace.h>
111#include <asm/user.h>
112
113typedef s390_fp_regs elf_fpregset_t;
114typedef s390_regs elf_gregset_t;
115
116typedef s390_fp_regs compat_elf_fpregset_t;
117typedef s390_compat_regs compat_elf_gregset_t;
118
119#include <linux/sched.h> /* for task_struct */
120#include <asm/system.h> /* for save_access_regs */
121#include <asm/mmu_context.h>
122
123/*
124 * This is used to ensure we don't load something for the wrong architecture.
125 */
126#define elf_check_arch(x) \
127 (((x)->e_machine == EM_S390 || (x)->e_machine == EM_S390_OLD) \
128 && (x)->e_ident[EI_CLASS] == ELF_CLASS)
129#define compat_elf_check_arch(x) \
130 (((x)->e_machine == EM_S390 || (x)->e_machine == EM_S390_OLD) \
131 && (x)->e_ident[EI_CLASS] == ELF_CLASS)
132#define compat_start_thread start_thread31
133
134/* For SVR4/S390 the function pointer to be registered with `atexit` is
135 passed in R14. */
136#define ELF_PLAT_INIT(_r, load_addr) \
137 do { \
138 _r->gprs[14] = 0; \
139 } while (0)
140
141#define CORE_DUMP_USE_REGSET
142#define USE_ELF_CORE_DUMP
143#define ELF_EXEC_PAGESIZE 4096
144
145/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
146 use of this is to invoke "./ld.so someprog" to test out a new version of
147 the loader. We need to make sure that it is out of the way of the program
148 that it will "exec", and that there is sufficient room for the brk. */
149#define ELF_ET_DYN_BASE (STACK_TOP / 3 * 2)
150
151/* This yields a mask that user programs can use to figure out what
152 instruction set this CPU supports. */
153
154extern unsigned long elf_hwcap;
155#define ELF_HWCAP (elf_hwcap)
156
157/* This yields a string that ld.so will use to load implementation
158 specific libraries for optimization. This is more specific in
159 intent than poking at uname or /proc/cpuinfo.
160
161 For the moment, we have only optimizations for the Intel generations,
162 but that could change... */
163
164#define ELF_PLATFORM_SIZE 8
165extern char elf_platform[];
166#define ELF_PLATFORM (elf_platform)
167
168#ifndef __s390x__
169#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
170#else /* __s390x__ */
171#define SET_PERSONALITY(ex, ibcs2) \
172do { \
173 if (ibcs2) \
174 set_personality(PER_SVR4); \
175 else if (current->personality != PER_LINUX32) \
176 set_personality(PER_LINUX); \
177 if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
178 set_thread_flag(TIF_31BIT); \
179 else \
180 clear_thread_flag(TIF_31BIT); \
181} while (0)
182#endif /* __s390x__ */
183
184/*
185 * An executable for which elf_read_implies_exec() returns TRUE will
186 * have the READ_IMPLIES_EXEC personality flag set automatically.
187 */
188#define elf_read_implies_exec(ex, executable_stack) \
189({ \
190 if (current->mm->context.noexec && \
191 executable_stack != EXSTACK_DISABLE_X) \
192 disable_noexec(current->mm, current); \
193 current->mm->context.noexec == 0; \
194})
195
196#endif
diff --git a/include/asm-s390/emergency-restart.h b/include/asm-s390/emergency-restart.h
deleted file mode 100644
index 108d8c48e42..00000000000
--- a/include/asm-s390/emergency-restart.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _ASM_EMERGENCY_RESTART_H
2#define _ASM_EMERGENCY_RESTART_H
3
4#include <asm-generic/emergency-restart.h>
5
6#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-s390/errno.h b/include/asm-s390/errno.h
deleted file mode 100644
index e41d5b37c4d..00000000000
--- a/include/asm-s390/errno.h
+++ /dev/null
@@ -1,13 +0,0 @@
1/*
2 * include/asm-s390/errno.h
3 *
4 * S390 version
5 *
6 */
7
8#ifndef _S390_ERRNO_H
9#define _S390_ERRNO_H
10
11#include <asm-generic/errno.h>
12
13#endif
diff --git a/include/asm-s390/etr.h b/include/asm-s390/etr.h
deleted file mode 100644
index 80ef58c6197..00000000000
--- a/include/asm-s390/etr.h
+++ /dev/null
@@ -1,258 +0,0 @@
1/*
2 * include/asm-s390/etr.h
3 *
4 * Copyright IBM Corp. 2006
5 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
6 */
7#ifndef __S390_ETR_H
8#define __S390_ETR_H
9
10/* ETR attachment control register */
11struct etr_eacr {
12 unsigned int e0 : 1; /* port 0 stepping control */
13 unsigned int e1 : 1; /* port 1 stepping control */
14 unsigned int _pad0 : 5; /* must be 00100 */
15 unsigned int dp : 1; /* data port control */
16 unsigned int p0 : 1; /* port 0 change recognition control */
17 unsigned int p1 : 1; /* port 1 change recognition control */
18 unsigned int _pad1 : 3; /* must be 000 */
19 unsigned int ea : 1; /* ETR alert control */
20 unsigned int es : 1; /* ETR sync check control */
21 unsigned int sl : 1; /* switch to local control */
22} __attribute__ ((packed));
23
24/* Port state returned by steai */
25enum etr_psc {
26 etr_psc_operational = 0,
27 etr_psc_semi_operational = 1,
28 etr_psc_protocol_error = 4,
29 etr_psc_no_symbols = 8,
30 etr_psc_no_signal = 12,
31 etr_psc_pps_mode = 13
32};
33
34/* Logical port state returned by stetr */
35enum etr_lpsc {
36 etr_lpsc_operational_step = 0,
37 etr_lpsc_operational_alt = 1,
38 etr_lpsc_semi_operational = 2,
39 etr_lpsc_protocol_error = 4,
40 etr_lpsc_no_symbol_sync = 8,
41 etr_lpsc_no_signal = 12,
42 etr_lpsc_pps_mode = 13
43};
44
45/* ETR status words */
46struct etr_esw {
47 struct etr_eacr eacr; /* attachment control register */
48 unsigned int y : 1; /* stepping mode */
49 unsigned int _pad0 : 5; /* must be 00000 */
50 unsigned int p : 1; /* stepping port number */
51 unsigned int q : 1; /* data port number */
52 unsigned int psc0 : 4; /* port 0 state code */
53 unsigned int psc1 : 4; /* port 1 state code */
54} __attribute__ ((packed));
55
56/* Second level data register status word */
57struct etr_slsw {
58 unsigned int vv1 : 1; /* copy of validity bit data frame 1 */
59 unsigned int vv2 : 1; /* copy of validity bit data frame 2 */
60 unsigned int vv3 : 1; /* copy of validity bit data frame 3 */
61 unsigned int vv4 : 1; /* copy of validity bit data frame 4 */
62 unsigned int _pad0 : 19; /* must by all zeroes */
63 unsigned int n : 1; /* EAF port number */
64 unsigned int v1 : 1; /* validity bit ETR data frame 1 */
65 unsigned int v2 : 1; /* validity bit ETR data frame 2 */
66 unsigned int v3 : 1; /* validity bit ETR data frame 3 */
67 unsigned int v4 : 1; /* validity bit ETR data frame 4 */
68 unsigned int _pad1 : 4; /* must be 0000 */
69} __attribute__ ((packed));
70
71/* ETR data frames */
72struct etr_edf1 {
73 unsigned int u : 1; /* untuned bit */
74 unsigned int _pad0 : 1; /* must be 0 */
75 unsigned int r : 1; /* service request bit */
76 unsigned int _pad1 : 4; /* must be 0000 */
77 unsigned int a : 1; /* time adjustment bit */
78 unsigned int net_id : 8; /* ETR network id */
79 unsigned int etr_id : 8; /* id of ETR which sends data frames */
80 unsigned int etr_pn : 8; /* port number of ETR output port */
81} __attribute__ ((packed));
82
83struct etr_edf2 {
84 unsigned int etv : 32; /* Upper 32 bits of TOD. */
85} __attribute__ ((packed));
86
87struct etr_edf3 {
88 unsigned int rc : 8; /* failure reason code */
89 unsigned int _pad0 : 3; /* must be 000 */
90 unsigned int c : 1; /* ETR coupled bit */
91 unsigned int tc : 4; /* ETR type code */
92 unsigned int blto : 8; /* biased local time offset */
93 /* (blto - 128) * 15 = minutes */
94 unsigned int buo : 8; /* biased utc offset */
95 /* (buo - 128) = leap seconds */
96} __attribute__ ((packed));
97
98struct etr_edf4 {
99 unsigned int ed : 8; /* ETS device dependent data */
100 unsigned int _pad0 : 1; /* must be 0 */
101 unsigned int buc : 5; /* biased ut1 correction */
102 /* (buc - 16) * 0.1 seconds */
103 unsigned int em : 6; /* ETS error magnitude */
104 unsigned int dc : 6; /* ETS drift code */
105 unsigned int sc : 6; /* ETS steering code */
106} __attribute__ ((packed));
107
108/*
109 * ETR attachment information block, two formats
110 * format 1 has 4 reserved words with a size of 64 bytes
111 * format 2 has 16 reserved words with a size of 96 bytes
112 */
113struct etr_aib {
114 struct etr_esw esw;
115 struct etr_slsw slsw;
116 unsigned long long tsp;
117 struct etr_edf1 edf1;
118 struct etr_edf2 edf2;
119 struct etr_edf3 edf3;
120 struct etr_edf4 edf4;
121 unsigned int reserved[16];
122} __attribute__ ((packed,aligned(8)));
123
124/* ETR interruption parameter */
125struct etr_irq_parm {
126 unsigned int _pad0 : 8;
127 unsigned int pc0 : 1; /* port 0 state change */
128 unsigned int pc1 : 1; /* port 1 state change */
129 unsigned int _pad1 : 3;
130 unsigned int eai : 1; /* ETR alert indication */
131 unsigned int _pad2 : 18;
132} __attribute__ ((packed));
133
134/* Query TOD offset result */
135struct etr_ptff_qto {
136 unsigned long long physical_clock;
137 unsigned long long tod_offset;
138 unsigned long long logical_tod_offset;
139 unsigned long long tod_epoch_difference;
140} __attribute__ ((packed));
141
142/* Inline assembly helper functions */
143static inline int etr_setr(struct etr_eacr *ctrl)
144{
145 int rc = -ENOSYS;
146
147 asm volatile(
148 " .insn s,0xb2160000,0(%2)\n"
149 "0: la %0,0\n"
150 "1:\n"
151 EX_TABLE(0b,1b)
152 : "+d" (rc) : "m" (*ctrl), "a" (ctrl));
153 return rc;
154}
155
156/* Stores a format 1 aib with 64 bytes */
157static inline int etr_stetr(struct etr_aib *aib)
158{
159 int rc = -ENOSYS;
160
161 asm volatile(
162 " .insn s,0xb2170000,0(%2)\n"
163 "0: la %0,0\n"
164 "1:\n"
165 EX_TABLE(0b,1b)
166 : "+d" (rc) : "m" (*aib), "a" (aib));
167 return rc;
168}
169
170/* Stores a format 2 aib with 96 bytes for specified port */
171static inline int etr_steai(struct etr_aib *aib, unsigned int func)
172{
173 register unsigned int reg0 asm("0") = func;
174 int rc = -ENOSYS;
175
176 asm volatile(
177 " .insn s,0xb2b30000,0(%2)\n"
178 "0: la %0,0\n"
179 "1:\n"
180 EX_TABLE(0b,1b)
181 : "+d" (rc) : "m" (*aib), "a" (aib), "d" (reg0));
182 return rc;
183}
184
185/* Function codes for the steai instruction. */
186#define ETR_STEAI_STEPPING_PORT 0x10
187#define ETR_STEAI_ALTERNATE_PORT 0x11
188#define ETR_STEAI_PORT_0 0x12
189#define ETR_STEAI_PORT_1 0x13
190
191static inline int etr_ptff(void *ptff_block, unsigned int func)
192{
193 register unsigned int reg0 asm("0") = func;
194 register unsigned long reg1 asm("1") = (unsigned long) ptff_block;
195 int rc = -ENOSYS;
196
197 asm volatile(
198 " .word 0x0104\n"
199 " ipm %0\n"
200 " srl %0,28\n"
201 : "=d" (rc), "=m" (ptff_block)
202 : "d" (reg0), "d" (reg1), "m" (ptff_block) : "cc");
203 return rc;
204}
205
206/* Function codes for the ptff instruction. */
207#define ETR_PTFF_QAF 0x00 /* query available functions */
208#define ETR_PTFF_QTO 0x01 /* query tod offset */
209#define ETR_PTFF_QSI 0x02 /* query steering information */
210#define ETR_PTFF_ATO 0x40 /* adjust tod offset */
211#define ETR_PTFF_STO 0x41 /* set tod offset */
212#define ETR_PTFF_SFS 0x42 /* set fine steering rate */
213#define ETR_PTFF_SGS 0x43 /* set gross steering rate */
214
215/* Functions needed by the machine check handler */
216void etr_switch_to_local(void);
217void etr_sync_check(void);
218
219/* STP interruption parameter */
220struct stp_irq_parm {
221 unsigned int _pad0 : 14;
222 unsigned int tsc : 1; /* Timing status change */
223 unsigned int lac : 1; /* Link availability change */
224 unsigned int tcpc : 1; /* Time control parameter change */
225 unsigned int _pad2 : 15;
226} __attribute__ ((packed));
227
228#define STP_OP_SYNC 1
229#define STP_OP_CTRL 3
230
231struct stp_sstpi {
232 unsigned int rsvd0;
233 unsigned int rsvd1 : 8;
234 unsigned int stratum : 8;
235 unsigned int vbits : 16;
236 unsigned int leaps : 16;
237 unsigned int tmd : 4;
238 unsigned int ctn : 4;
239 unsigned int rsvd2 : 3;
240 unsigned int c : 1;
241 unsigned int tst : 4;
242 unsigned int tzo : 16;
243 unsigned int dsto : 16;
244 unsigned int ctrl : 16;
245 unsigned int rsvd3 : 16;
246 unsigned int tto;
247 unsigned int rsvd4;
248 unsigned int ctnid[3];
249 unsigned int rsvd5;
250 unsigned int todoff[4];
251 unsigned int rsvd6[48];
252} __attribute__ ((packed));
253
254/* Functions needed by the machine check handler */
255void stp_sync_check(void);
256void stp_island_check(void);
257
258#endif /* __S390_ETR_H */
diff --git a/include/asm-s390/extmem.h b/include/asm-s390/extmem.h
deleted file mode 100644
index 33837d75618..00000000000
--- a/include/asm-s390/extmem.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * include/asm-s390x/extmem.h
3 *
4 * definitions for external memory segment support
5 * Copyright (C) 2003 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 */
7
8#ifndef _ASM_S390X_DCSS_H
9#define _ASM_S390X_DCSS_H
10#ifndef __ASSEMBLY__
11
12/* possible values for segment type as returned by segment_info */
13#define SEG_TYPE_SW 0
14#define SEG_TYPE_EW 1
15#define SEG_TYPE_SR 2
16#define SEG_TYPE_ER 3
17#define SEG_TYPE_SN 4
18#define SEG_TYPE_EN 5
19#define SEG_TYPE_SC 6
20#define SEG_TYPE_EWEN 7
21
22#define SEGMENT_SHARED 0
23#define SEGMENT_EXCLUSIVE 1
24
25int segment_load (char *name, int segtype, unsigned long *addr, unsigned long *length);
26void segment_unload(char *name);
27void segment_save(char *name);
28int segment_type (char* name);
29int segment_modify_shared (char *name, int do_nonshared);
30void segment_warning(int rc, char *seg_name);
31
32#endif
33#endif
diff --git a/include/asm-s390/fb.h b/include/asm-s390/fb.h
deleted file mode 100644
index c7df3803099..00000000000
--- a/include/asm-s390/fb.h
+++ /dev/null
@@ -1,12 +0,0 @@
1#ifndef _ASM_FB_H_
2#define _ASM_FB_H_
3#include <linux/fb.h>
4
5#define fb_pgprotect(...) do {} while (0)
6
7static inline int fb_is_primary_device(struct fb_info *info)
8{
9 return 0;
10}
11
12#endif /* _ASM_FB_H_ */
diff --git a/include/asm-s390/fcntl.h b/include/asm-s390/fcntl.h
deleted file mode 100644
index 46ab12db573..00000000000
--- a/include/asm-s390/fcntl.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/fcntl.h>
diff --git a/include/asm-s390/fcx.h b/include/asm-s390/fcx.h
deleted file mode 100644
index 8be1f3a5804..00000000000
--- a/include/asm-s390/fcx.h
+++ /dev/null
@@ -1,311 +0,0 @@
1/*
2 * Functions for assembling fcx enabled I/O control blocks.
3 *
4 * Copyright IBM Corp. 2008
5 * Author(s): Peter Oberparleiter <peter.oberparleiter@de.ibm.com>
6 */
7
8#ifndef _ASM_S390_FCX_H
9#define _ASM_S390_FCX_H _ASM_S390_FCX_H
10
11#include <linux/types.h>
12
13#define TCW_FORMAT_DEFAULT 0
14#define TCW_TIDAW_FORMAT_DEFAULT 0
15#define TCW_FLAGS_INPUT_TIDA 1 << (23 - 5)
16#define TCW_FLAGS_TCCB_TIDA 1 << (23 - 6)
17#define TCW_FLAGS_OUTPUT_TIDA 1 << (23 - 7)
18#define TCW_FLAGS_TIDAW_FORMAT(x) ((x) & 3) << (23 - 9)
19#define TCW_FLAGS_GET_TIDAW_FORMAT(x) (((x) >> (23 - 9)) & 3)
20
21/**
22 * struct tcw - Transport Control Word (TCW)
23 * @format: TCW format
24 * @flags: TCW flags
25 * @tccbl: Transport-Command-Control-Block Length
26 * @r: Read Operations
27 * @w: Write Operations
28 * @output: Output-Data Address
29 * @input: Input-Data Address
30 * @tsb: Transport-Status-Block Address
31 * @tccb: Transport-Command-Control-Block Address
32 * @output_count: Output Count
33 * @input_count: Input Count
34 * @intrg: Interrogate TCW Address
35 */
36struct tcw {
37 u32 format:2;
38 u32 :6;
39 u32 flags:24;
40 u32 :8;
41 u32 tccbl:6;
42 u32 r:1;
43 u32 w:1;
44 u32 :16;
45 u64 output;
46 u64 input;
47 u64 tsb;
48 u64 tccb;
49 u32 output_count;
50 u32 input_count;
51 u32 :32;
52 u32 :32;
53 u32 :32;
54 u32 intrg;
55} __attribute__ ((packed, aligned(64)));
56
57#define TIDAW_FLAGS_LAST 1 << (7 - 0)
58#define TIDAW_FLAGS_SKIP 1 << (7 - 1)
59#define TIDAW_FLAGS_DATA_INT 1 << (7 - 2)
60#define TIDAW_FLAGS_TTIC 1 << (7 - 3)
61#define TIDAW_FLAGS_INSERT_CBC 1 << (7 - 4)
62
63/**
64 * struct tidaw - Transport-Indirect-Addressing Word (TIDAW)
65 * @flags: TIDAW flags. Can be an arithmetic OR of the following constants:
66 * %TIDAW_FLAGS_LAST, %TIDAW_FLAGS_SKIP, %TIDAW_FLAGS_DATA_INT,
67 * %TIDAW_FLAGS_TTIC, %TIDAW_FLAGS_INSERT_CBC
68 * @count: Count
69 * @addr: Address
70 */
71struct tidaw {
72 u32 flags:8;
73 u32 :24;
74 u32 count;
75 u64 addr;
76} __attribute__ ((packed, aligned(16)));
77
78/**
79 * struct tsa_iostat - I/O-Status Transport-Status Area (IO-Stat TSA)
80 * @dev_time: Device Time
81 * @def_time: Defer Time
82 * @queue_time: Queue Time
83 * @dev_busy_time: Device-Busy Time
84 * @dev_act_time: Device-Active-Only Time
85 * @sense: Sense Data (if present)
86 */
87struct tsa_iostat {
88 u32 dev_time;
89 u32 def_time;
90 u32 queue_time;
91 u32 dev_busy_time;
92 u32 dev_act_time;
93 u8 sense[32];
94} __attribute__ ((packed));
95
96/**
97 * struct tsa_ddpcs - Device-Detected-Program-Check Transport-Status Area (DDPC TSA)
98 * @rc: Reason Code
99 * @rcq: Reason Code Qualifier
100 * @sense: Sense Data (if present)
101 */
102struct tsa_ddpc {
103 u32 :24;
104 u32 rc:8;
105 u8 rcq[16];
106 u8 sense[32];
107} __attribute__ ((packed));
108
109#define TSA_INTRG_FLAGS_CU_STATE_VALID 1 << (7 - 0)
110#define TSA_INTRG_FLAGS_DEV_STATE_VALID 1 << (7 - 1)
111#define TSA_INTRG_FLAGS_OP_STATE_VALID 1 << (7 - 2)
112
113/**
114 * struct tsa_intrg - Interrogate Transport-Status Area (Intrg. TSA)
115 * @format: Format
116 * @flags: Flags. Can be an arithmetic OR of the following constants:
117 * %TSA_INTRG_FLAGS_CU_STATE_VALID, %TSA_INTRG_FLAGS_DEV_STATE_VALID,
118 * %TSA_INTRG_FLAGS_OP_STATE_VALID
119 * @cu_state: Controle-Unit State
120 * @dev_state: Device State
121 * @op_state: Operation State
122 * @sd_info: State-Dependent Information
123 * @dl_id: Device-Level Identifier
124 * @dd_data: Device-Dependent Data
125 */
126struct tsa_intrg {
127 u32 format:8;
128 u32 flags:8;
129 u32 cu_state:8;
130 u32 dev_state:8;
131 u32 op_state:8;
132 u32 :24;
133 u8 sd_info[12];
134 u32 dl_id;
135 u8 dd_data[28];
136} __attribute__ ((packed));
137
138#define TSB_FORMAT_NONE 0
139#define TSB_FORMAT_IOSTAT 1
140#define TSB_FORMAT_DDPC 2
141#define TSB_FORMAT_INTRG 3
142
143#define TSB_FLAGS_DCW_OFFSET_VALID 1 << (7 - 0)
144#define TSB_FLAGS_COUNT_VALID 1 << (7 - 1)
145#define TSB_FLAGS_CACHE_MISS 1 << (7 - 2)
146#define TSB_FLAGS_TIME_VALID 1 << (7 - 3)
147#define TSB_FLAGS_FORMAT(x) ((x) & 7)
148#define TSB_FORMAT(t) ((t)->flags & 7)
149
150/**
151 * struct tsb - Transport-Status Block (TSB)
152 * @length: Length
153 * @flags: Flags. Can be an arithmetic OR of the following constants:
154 * %TSB_FLAGS_DCW_OFFSET_VALID, %TSB_FLAGS_COUNT_VALID, %TSB_FLAGS_CACHE_MISS,
155 * %TSB_FLAGS_TIME_VALID
156 * @dcw_offset: DCW Offset
157 * @count: Count
158 * @tsa: Transport-Status-Area
159 */
160struct tsb {
161 u32 length:8;
162 u32 flags:8;
163 u32 dcw_offset:16;
164 u32 count;
165 u32 :32;
166 union {
167 struct tsa_iostat iostat;
168 struct tsa_ddpc ddpc;
169 struct tsa_intrg intrg;
170 } __attribute__ ((packed)) tsa;
171} __attribute__ ((packed, aligned(8)));
172
173#define DCW_INTRG_FORMAT_DEFAULT 0
174
175#define DCW_INTRG_RC_UNSPECIFIED 0
176#define DCW_INTRG_RC_TIMEOUT 1
177
178#define DCW_INTRG_RCQ_UNSPECIFIED 0
179#define DCW_INTRG_RCQ_PRIMARY 1
180#define DCW_INTRG_RCQ_SECONDARY 2
181
182#define DCW_INTRG_FLAGS_MPM 1 < (7 - 0)
183#define DCW_INTRG_FLAGS_PPR 1 < (7 - 1)
184#define DCW_INTRG_FLAGS_CRIT 1 < (7 - 2)
185
186/**
187 * struct dcw_intrg_data - Interrogate DCW data
188 * @format: Format. Should be %DCW_INTRG_FORMAT_DEFAULT
189 * @rc: Reason Code. Can be one of %DCW_INTRG_RC_UNSPECIFIED,
190 * %DCW_INTRG_RC_TIMEOUT
191 * @rcq: Reason Code Qualifier: Can be one of %DCW_INTRG_RCQ_UNSPECIFIED,
192 * %DCW_INTRG_RCQ_PRIMARY, %DCW_INTRG_RCQ_SECONDARY
193 * @lpm: Logical-Path Mask
194 * @pam: Path-Available Mask
195 * @pim: Path-Installed Mask
196 * @timeout: Timeout
197 * @flags: Flags. Can be an arithmetic OR of %DCW_INTRG_FLAGS_MPM,
198 * %DCW_INTRG_FLAGS_PPR, %DCW_INTRG_FLAGS_CRIT
199 * @time: Time
200 * @prog_id: Program Identifier
201 * @prog_data: Program-Dependent Data
202 */
203struct dcw_intrg_data {
204 u32 format:8;
205 u32 rc:8;
206 u32 rcq:8;
207 u32 lpm:8;
208 u32 pam:8;
209 u32 pim:8;
210 u32 timeout:16;
211 u32 flags:8;
212 u32 :24;
213 u32 :32;
214 u64 time;
215 u64 prog_id;
216 u8 prog_data[0];
217} __attribute__ ((packed));
218
219#define DCW_FLAGS_CC 1 << (7 - 1)
220
221#define DCW_CMD_WRITE 0x01
222#define DCW_CMD_READ 0x02
223#define DCW_CMD_CONTROL 0x03
224#define DCW_CMD_SENSE 0x04
225#define DCW_CMD_SENSE_ID 0xe4
226#define DCW_CMD_INTRG 0x40
227
228/**
229 * struct dcw - Device-Command Word (DCW)
230 * @cmd: Command Code. Can be one of %DCW_CMD_WRITE, %DCW_CMD_READ,
231 * %DCW_CMD_CONTROL, %DCW_CMD_SENSE, %DCW_CMD_SENSE_ID, %DCW_CMD_INTRG
232 * @flags: Flags. Can be an arithmetic OR of %DCW_FLAGS_CC
233 * @cd_count: Control-Data Count
234 * @count: Count
235 * @cd: Control Data
236 */
237struct dcw {
238 u32 cmd:8;
239 u32 flags:8;
240 u32 :8;
241 u32 cd_count:8;
242 u32 count;
243 u8 cd[0];
244} __attribute__ ((packed));
245
246#define TCCB_FORMAT_DEFAULT 0x7f
247#define TCCB_MAX_DCW 30
248#define TCCB_MAX_SIZE (sizeof(struct tccb_tcah) + \
249 TCCB_MAX_DCW * sizeof(struct dcw) + \
250 sizeof(struct tccb_tcat))
251#define TCCB_SAC_DEFAULT 0xf901
252#define TCCB_SAC_INTRG 0xf902
253
254/**
255 * struct tccb_tcah - Transport-Command-Area Header (TCAH)
256 * @format: Format. Should be %TCCB_FORMAT_DEFAULT
257 * @tcal: Transport-Command-Area Length
258 * @sac: Service-Action Code. Can be one of %TCCB_SAC_DEFAULT, %TCCB_SAC_INTRG
259 * @prio: Priority
260 */
261struct tccb_tcah {
262 u32 format:8;
263 u32 :24;
264 u32 :24;
265 u32 tcal:8;
266 u32 sac:16;
267 u32 :8;
268 u32 prio:8;
269 u32 :32;
270} __attribute__ ((packed));
271
272/**
273 * struct tccb_tcat - Transport-Command-Area Trailer (TCAT)
274 * @count: Transport Count
275 */
276struct tccb_tcat {
277 u32 :32;
278 u32 count;
279} __attribute__ ((packed));
280
281/**
282 * struct tccb - (partial) Transport-Command-Control Block (TCCB)
283 * @tcah: TCAH
284 * @tca: Transport-Command Area
285 */
286struct tccb {
287 struct tccb_tcah tcah;
288 u8 tca[0];
289} __attribute__ ((packed, aligned(8)));
290
291struct tcw *tcw_get_intrg(struct tcw *tcw);
292void *tcw_get_data(struct tcw *tcw);
293struct tccb *tcw_get_tccb(struct tcw *tcw);
294struct tsb *tcw_get_tsb(struct tcw *tcw);
295
296void tcw_init(struct tcw *tcw, int r, int w);
297void tcw_finalize(struct tcw *tcw, int num_tidaws);
298
299void tcw_set_intrg(struct tcw *tcw, struct tcw *intrg_tcw);
300void tcw_set_data(struct tcw *tcw, void *data, int use_tidal);
301void tcw_set_tccb(struct tcw *tcw, struct tccb *tccb);
302void tcw_set_tsb(struct tcw *tcw, struct tsb *tsb);
303
304void tccb_init(struct tccb *tccb, size_t tccb_size, u32 sac);
305void tsb_init(struct tsb *tsb);
306struct dcw *tccb_add_dcw(struct tccb *tccb, size_t tccb_size, u8 cmd, u8 flags,
307 void *cd, u8 cd_count, u32 count);
308struct tidaw *tcw_add_tidaw(struct tcw *tcw, int num_tidaws, u8 flags,
309 void *addr, u32 count);
310
311#endif /* _ASM_S390_FCX_H */
diff --git a/include/asm-s390/futex.h b/include/asm-s390/futex.h
deleted file mode 100644
index 5c5d02de49e..00000000000
--- a/include/asm-s390/futex.h
+++ /dev/null
@@ -1,52 +0,0 @@
1#ifndef _ASM_S390_FUTEX_H
2#define _ASM_S390_FUTEX_H
3
4#ifdef __KERNEL__
5
6#include <linux/futex.h>
7#include <linux/uaccess.h>
8#include <asm/errno.h>
9
10static inline int futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
11{
12 int op = (encoded_op >> 28) & 7;
13 int cmp = (encoded_op >> 24) & 15;
14 int oparg = (encoded_op << 8) >> 20;
15 int cmparg = (encoded_op << 20) >> 20;
16 int oldval, ret;
17
18 if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
19 oparg = 1 << oparg;
20
21 if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
22 return -EFAULT;
23
24 pagefault_disable();
25 ret = uaccess.futex_atomic_op(op, uaddr, oparg, &oldval);
26 pagefault_enable();
27
28 if (!ret) {
29 switch (cmp) {
30 case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
31 case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
32 case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
33 case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
34 case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
35 case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
36 default: ret = -ENOSYS;
37 }
38 }
39 return ret;
40}
41
42static inline int futex_atomic_cmpxchg_inatomic(int __user *uaddr,
43 int oldval, int newval)
44{
45 if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
46 return -EFAULT;
47
48 return uaccess.futex_atomic_cmpxchg(uaddr, oldval, newval);
49}
50
51#endif /* __KERNEL__ */
52#endif /* _ASM_S390_FUTEX_H */
diff --git a/include/asm-s390/hardirq.h b/include/asm-s390/hardirq.h
deleted file mode 100644
index 4b7cb964ff3..00000000000
--- a/include/asm-s390/hardirq.h
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * include/asm-s390/hardirq.h
3 *
4 * S390 version
5 * Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
7 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
8 *
9 * Derived from "include/asm-i386/hardirq.h"
10 */
11
12#ifndef __ASM_HARDIRQ_H
13#define __ASM_HARDIRQ_H
14
15#include <linux/threads.h>
16#include <linux/sched.h>
17#include <linux/cache.h>
18#include <linux/interrupt.h>
19#include <asm/lowcore.h>
20
21/* irq_cpustat_t is unused currently, but could be converted
22 * into a percpu variable instead of storing softirq_pending
23 * on the lowcore */
24typedef struct {
25 unsigned int __softirq_pending;
26} irq_cpustat_t;
27
28#define local_softirq_pending() (S390_lowcore.softirq_pending)
29
30#define __ARCH_IRQ_STAT
31#define __ARCH_HAS_DO_SOFTIRQ
32
33#define HARDIRQ_BITS 8
34
35void clock_comparator_work(void);
36
37#endif /* __ASM_HARDIRQ_H */
diff --git a/include/asm-s390/hugetlb.h b/include/asm-s390/hugetlb.h
deleted file mode 100644
index 670a1d1745d..00000000000
--- a/include/asm-s390/hugetlb.h
+++ /dev/null
@@ -1,184 +0,0 @@
1/*
2 * IBM System z Huge TLB Page Support for Kernel.
3 *
4 * Copyright IBM Corp. 2008
5 * Author(s): Gerald Schaefer <gerald.schaefer@de.ibm.com>
6 */
7
8#ifndef _ASM_S390_HUGETLB_H
9#define _ASM_S390_HUGETLB_H
10
11#include <asm/page.h>
12#include <asm/pgtable.h>
13
14
15#define is_hugepage_only_range(mm, addr, len) 0
16#define hugetlb_free_pgd_range free_pgd_range
17
18void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
19 pte_t *ptep, pte_t pte);
20
21/*
22 * If the arch doesn't supply something else, assume that hugepage
23 * size aligned regions are ok without further preparation.
24 */
25static inline int prepare_hugepage_range(struct file *file,
26 unsigned long addr, unsigned long len)
27{
28 if (len & ~HPAGE_MASK)
29 return -EINVAL;
30 if (addr & ~HPAGE_MASK)
31 return -EINVAL;
32 return 0;
33}
34
35#define hugetlb_prefault_arch_hook(mm) do { } while (0)
36
37int arch_prepare_hugepage(struct page *page);
38void arch_release_hugepage(struct page *page);
39
40static inline pte_t pte_mkhuge(pte_t pte)
41{
42 /*
43 * PROT_NONE needs to be remapped from the pte type to the ste type.
44 * The HW invalid bit is also different for pte and ste. The pte
45 * invalid bit happens to be the same as the ste _SEGMENT_ENTRY_LARGE
46 * bit, so we don't have to clear it.
47 */
48 if (pte_val(pte) & _PAGE_INVALID) {
49 if (pte_val(pte) & _PAGE_SWT)
50 pte_val(pte) |= _HPAGE_TYPE_NONE;
51 pte_val(pte) |= _SEGMENT_ENTRY_INV;
52 }
53 /*
54 * Clear SW pte bits SWT and SWX, there are no SW bits in a segment
55 * table entry.
56 */
57 pte_val(pte) &= ~(_PAGE_SWT | _PAGE_SWX);
58 /*
59 * Also set the change-override bit because we don't need dirty bit
60 * tracking for hugetlbfs pages.
61 */
62 pte_val(pte) |= (_SEGMENT_ENTRY_LARGE | _SEGMENT_ENTRY_CO);
63 return pte;
64}
65
66static inline pte_t huge_pte_wrprotect(pte_t pte)
67{
68 pte_val(pte) |= _PAGE_RO;
69 return pte;
70}
71
72static inline int huge_pte_none(pte_t pte)
73{
74 return (pte_val(pte) & _SEGMENT_ENTRY_INV) &&
75 !(pte_val(pte) & _SEGMENT_ENTRY_RO);
76}
77
78static inline pte_t huge_ptep_get(pte_t *ptep)
79{
80 pte_t pte = *ptep;
81 unsigned long mask;
82
83 if (!MACHINE_HAS_HPAGE) {
84 ptep = (pte_t *) (pte_val(pte) & _SEGMENT_ENTRY_ORIGIN);
85 if (ptep) {
86 mask = pte_val(pte) &
87 (_SEGMENT_ENTRY_INV | _SEGMENT_ENTRY_RO);
88 pte = pte_mkhuge(*ptep);
89 pte_val(pte) |= mask;
90 }
91 }
92 return pte;
93}
94
95static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
96 unsigned long addr, pte_t *ptep)
97{
98 pte_t pte = huge_ptep_get(ptep);
99
100 pmd_clear((pmd_t *) ptep);
101 return pte;
102}
103
104static inline void __pmd_csp(pmd_t *pmdp)
105{
106 register unsigned long reg2 asm("2") = pmd_val(*pmdp);
107 register unsigned long reg3 asm("3") = pmd_val(*pmdp) |
108 _SEGMENT_ENTRY_INV;
109 register unsigned long reg4 asm("4") = ((unsigned long) pmdp) + 5;
110
111 asm volatile(
112 " csp %1,%3"
113 : "=m" (*pmdp)
114 : "d" (reg2), "d" (reg3), "d" (reg4), "m" (*pmdp) : "cc");
115 pmd_val(*pmdp) = _SEGMENT_ENTRY_INV | _SEGMENT_ENTRY;
116}
117
118static inline void __pmd_idte(unsigned long address, pmd_t *pmdp)
119{
120 unsigned long sto = (unsigned long) pmdp -
121 pmd_index(address) * sizeof(pmd_t);
122
123 if (!(pmd_val(*pmdp) & _SEGMENT_ENTRY_INV)) {
124 asm volatile(
125 " .insn rrf,0xb98e0000,%2,%3,0,0"
126 : "=m" (*pmdp)
127 : "m" (*pmdp), "a" (sto),
128 "a" ((address & HPAGE_MASK))
129 );
130 }
131 pmd_val(*pmdp) = _SEGMENT_ENTRY_INV | _SEGMENT_ENTRY;
132}
133
134static inline void huge_ptep_invalidate(struct mm_struct *mm,
135 unsigned long address, pte_t *ptep)
136{
137 pmd_t *pmdp = (pmd_t *) ptep;
138
139 if (!MACHINE_HAS_IDTE) {
140 __pmd_csp(pmdp);
141 if (mm->context.noexec) {
142 pmdp = get_shadow_table(pmdp);
143 __pmd_csp(pmdp);
144 }
145 return;
146 }
147
148 __pmd_idte(address, pmdp);
149 if (mm->context.noexec) {
150 pmdp = get_shadow_table(pmdp);
151 __pmd_idte(address, pmdp);
152 }
153 return;
154}
155
156#define huge_ptep_set_access_flags(__vma, __addr, __ptep, __entry, __dirty) \
157({ \
158 int __changed = !pte_same(huge_ptep_get(__ptep), __entry); \
159 if (__changed) { \
160 huge_ptep_invalidate((__vma)->vm_mm, __addr, __ptep); \
161 set_huge_pte_at((__vma)->vm_mm, __addr, __ptep, __entry); \
162 } \
163 __changed; \
164})
165
166#define huge_ptep_set_wrprotect(__mm, __addr, __ptep) \
167({ \
168 pte_t __pte = huge_ptep_get(__ptep); \
169 if (pte_write(__pte)) { \
170 if (atomic_read(&(__mm)->mm_users) > 1 || \
171 (__mm) != current->active_mm) \
172 huge_ptep_invalidate(__mm, __addr, __ptep); \
173 set_huge_pte_at(__mm, __addr, __ptep, \
174 huge_pte_wrprotect(__pte)); \
175 } \
176})
177
178static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
179 unsigned long address, pte_t *ptep)
180{
181 huge_ptep_invalidate(vma->vm_mm, address, ptep);
182}
183
184#endif /* _ASM_S390_HUGETLB_H */
diff --git a/include/asm-s390/idals.h b/include/asm-s390/idals.h
deleted file mode 100644
index e82c10efe65..00000000000
--- a/include/asm-s390/idals.h
+++ /dev/null
@@ -1,256 +0,0 @@
1/*
2 * File...........: linux/include/asm-s390x/idals.h
3 * Author(s)......: Holger Smolinski <Holger.Smolinski@de.ibm.com>
4 * Martin Schwidefsky <schwidefsky@de.ibm.com>
5 * Bugreports.to..: <Linux390@de.ibm.com>
6 * (C) IBM Corporation, IBM Deutschland Entwicklung GmbH, 2000a
7
8 * History of changes
9 * 07/24/00 new file
10 * 05/04/02 code restructuring.
11 */
12
13#ifndef _S390_IDALS_H
14#define _S390_IDALS_H
15
16#include <linux/errno.h>
17#include <linux/err.h>
18#include <linux/types.h>
19#include <linux/slab.h>
20#include <asm/cio.h>
21#include <asm/uaccess.h>
22
23#ifdef __s390x__
24#define IDA_SIZE_LOG 12 /* 11 for 2k , 12 for 4k */
25#else
26#define IDA_SIZE_LOG 11 /* 11 for 2k , 12 for 4k */
27#endif
28#define IDA_BLOCK_SIZE (1L<<IDA_SIZE_LOG)
29
30/*
31 * Test if an address/length pair needs an idal list.
32 */
33static inline int
34idal_is_needed(void *vaddr, unsigned int length)
35{
36#ifdef __s390x__
37 return ((__pa(vaddr) + length - 1) >> 31) != 0;
38#else
39 return 0;
40#endif
41}
42
43
44/*
45 * Return the number of idal words needed for an address/length pair.
46 */
47static inline unsigned int
48idal_nr_words(void *vaddr, unsigned int length)
49{
50#ifdef __s390x__
51 if (idal_is_needed(vaddr, length))
52 return ((__pa(vaddr) & (IDA_BLOCK_SIZE-1)) + length +
53 (IDA_BLOCK_SIZE-1)) >> IDA_SIZE_LOG;
54#endif
55 return 0;
56}
57
58/*
59 * Create the list of idal words for an address/length pair.
60 */
61static inline unsigned long *
62idal_create_words(unsigned long *idaws, void *vaddr, unsigned int length)
63{
64#ifdef __s390x__
65 unsigned long paddr;
66 unsigned int cidaw;
67
68 paddr = __pa(vaddr);
69 cidaw = ((paddr & (IDA_BLOCK_SIZE-1)) + length +
70 (IDA_BLOCK_SIZE-1)) >> IDA_SIZE_LOG;
71 *idaws++ = paddr;
72 paddr &= -IDA_BLOCK_SIZE;
73 while (--cidaw > 0) {
74 paddr += IDA_BLOCK_SIZE;
75 *idaws++ = paddr;
76 }
77#endif
78 return idaws;
79}
80
81/*
82 * Sets the address of the data in CCW.
83 * If necessary it allocates an IDAL and sets the appropriate flags.
84 */
85static inline int
86set_normalized_cda(struct ccw1 * ccw, void *vaddr)
87{
88#ifdef __s390x__
89 unsigned int nridaws;
90 unsigned long *idal;
91
92 if (ccw->flags & CCW_FLAG_IDA)
93 return -EINVAL;
94 nridaws = idal_nr_words(vaddr, ccw->count);
95 if (nridaws > 0) {
96 idal = kmalloc(nridaws * sizeof(unsigned long),
97 GFP_ATOMIC | GFP_DMA );
98 if (idal == NULL)
99 return -ENOMEM;
100 idal_create_words(idal, vaddr, ccw->count);
101 ccw->flags |= CCW_FLAG_IDA;
102 vaddr = idal;
103 }
104#endif
105 ccw->cda = (__u32)(unsigned long) vaddr;
106 return 0;
107}
108
109/*
110 * Releases any allocated IDAL related to the CCW.
111 */
112static inline void
113clear_normalized_cda(struct ccw1 * ccw)
114{
115#ifdef __s390x__
116 if (ccw->flags & CCW_FLAG_IDA) {
117 kfree((void *)(unsigned long) ccw->cda);
118 ccw->flags &= ~CCW_FLAG_IDA;
119 }
120#endif
121 ccw->cda = 0;
122}
123
124/*
125 * Idal buffer extension
126 */
127struct idal_buffer {
128 size_t size;
129 size_t page_order;
130 void *data[0];
131};
132
133/*
134 * Allocate an idal buffer
135 */
136static inline struct idal_buffer *
137idal_buffer_alloc(size_t size, int page_order)
138{
139 struct idal_buffer *ib;
140 int nr_chunks, nr_ptrs, i;
141
142 nr_ptrs = (size + IDA_BLOCK_SIZE - 1) >> IDA_SIZE_LOG;
143 nr_chunks = (4096 << page_order) >> IDA_SIZE_LOG;
144 ib = kmalloc(sizeof(struct idal_buffer) + nr_ptrs*sizeof(void *),
145 GFP_DMA | GFP_KERNEL);
146 if (ib == NULL)
147 return ERR_PTR(-ENOMEM);
148 ib->size = size;
149 ib->page_order = page_order;
150 for (i = 0; i < nr_ptrs; i++) {
151 if ((i & (nr_chunks - 1)) != 0) {
152 ib->data[i] = ib->data[i-1] + IDA_BLOCK_SIZE;
153 continue;
154 }
155 ib->data[i] = (void *)
156 __get_free_pages(GFP_KERNEL, page_order);
157 if (ib->data[i] != NULL)
158 continue;
159 // Not enough memory
160 while (i >= nr_chunks) {
161 i -= nr_chunks;
162 free_pages((unsigned long) ib->data[i],
163 ib->page_order);
164 }
165 kfree(ib);
166 return ERR_PTR(-ENOMEM);
167 }
168 return ib;
169}
170
171/*
172 * Free an idal buffer.
173 */
174static inline void
175idal_buffer_free(struct idal_buffer *ib)
176{
177 int nr_chunks, nr_ptrs, i;
178
179 nr_ptrs = (ib->size + IDA_BLOCK_SIZE - 1) >> IDA_SIZE_LOG;
180 nr_chunks = (4096 << ib->page_order) >> IDA_SIZE_LOG;
181 for (i = 0; i < nr_ptrs; i += nr_chunks)
182 free_pages((unsigned long) ib->data[i], ib->page_order);
183 kfree(ib);
184}
185
186/*
187 * Test if a idal list is really needed.
188 */
189static inline int
190__idal_buffer_is_needed(struct idal_buffer *ib)
191{
192#ifdef __s390x__
193 return ib->size > (4096ul << ib->page_order) ||
194 idal_is_needed(ib->data[0], ib->size);
195#else
196 return ib->size > (4096ul << ib->page_order);
197#endif
198}
199
200/*
201 * Set channel data address to idal buffer.
202 */
203static inline void
204idal_buffer_set_cda(struct idal_buffer *ib, struct ccw1 *ccw)
205{
206 if (__idal_buffer_is_needed(ib)) {
207 // setup idals;
208 ccw->cda = (u32)(addr_t) ib->data;
209 ccw->flags |= CCW_FLAG_IDA;
210 } else
211 // we do not need idals - use direct addressing
212 ccw->cda = (u32)(addr_t) ib->data[0];
213 ccw->count = ib->size;
214}
215
216/*
217 * Copy count bytes from an idal buffer to user memory
218 */
219static inline size_t
220idal_buffer_to_user(struct idal_buffer *ib, void __user *to, size_t count)
221{
222 size_t left;
223 int i;
224
225 BUG_ON(count > ib->size);
226 for (i = 0; count > IDA_BLOCK_SIZE; i++) {
227 left = copy_to_user(to, ib->data[i], IDA_BLOCK_SIZE);
228 if (left)
229 return left + count - IDA_BLOCK_SIZE;
230 to = (void __user *) to + IDA_BLOCK_SIZE;
231 count -= IDA_BLOCK_SIZE;
232 }
233 return copy_to_user(to, ib->data[i], count);
234}
235
236/*
237 * Copy count bytes from user memory to an idal buffer
238 */
239static inline size_t
240idal_buffer_from_user(struct idal_buffer *ib, const void __user *from, size_t count)
241{
242 size_t left;
243 int i;
244
245 BUG_ON(count > ib->size);
246 for (i = 0; count > IDA_BLOCK_SIZE; i++) {
247 left = copy_from_user(ib->data[i], from, IDA_BLOCK_SIZE);
248 if (left)
249 return left + count - IDA_BLOCK_SIZE;
250 from = (void __user *) from + IDA_BLOCK_SIZE;
251 count -= IDA_BLOCK_SIZE;
252 }
253 return copy_from_user(ib->data[i], from, count);
254}
255
256#endif
diff --git a/include/asm-s390/io.h b/include/asm-s390/io.h
deleted file mode 100644
index b7ff6afc3ca..00000000000
--- a/include/asm-s390/io.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * include/asm-s390/io.h
3 *
4 * S390 version
5 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
7 *
8 * Derived from "include/asm-i386/io.h"
9 */
10
11#ifndef _S390_IO_H
12#define _S390_IO_H
13
14#ifdef __KERNEL__
15
16#include <asm/page.h>
17
18#define IO_SPACE_LIMIT 0xffffffff
19
20/*
21 * Change virtual addresses to physical addresses and vv.
22 * These are pretty trivial
23 */
24static inline unsigned long virt_to_phys(volatile void * address)
25{
26 unsigned long real_address;
27 asm volatile(
28 " lra %0,0(%1)\n"
29 " jz 0f\n"
30 " la %0,0\n"
31 "0:"
32 : "=a" (real_address) : "a" (address) : "cc");
33 return real_address;
34}
35
36static inline void * phys_to_virt(unsigned long address)
37{
38 return (void *) address;
39}
40
41/*
42 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
43 * access
44 */
45#define xlate_dev_mem_ptr(p) __va(p)
46
47/*
48 * Convert a virtual cached pointer to an uncached pointer
49 */
50#define xlate_dev_kmem_ptr(p) p
51
52#endif /* __KERNEL__ */
53
54#endif
diff --git a/include/asm-s390/ioctl.h b/include/asm-s390/ioctl.h
deleted file mode 100644
index b279fe06dfe..00000000000
--- a/include/asm-s390/ioctl.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/ioctl.h>
diff --git a/include/asm-s390/ioctls.h b/include/asm-s390/ioctls.h
deleted file mode 100644
index 40e481b1b46..00000000000
--- a/include/asm-s390/ioctls.h
+++ /dev/null
@@ -1,92 +0,0 @@
1/*
2 * include/asm-s390/ioctls.h
3 *
4 * S390 version
5 *
6 * Derived from "include/asm-i386/ioctls.h"
7 */
8
9#ifndef __ARCH_S390_IOCTLS_H__
10#define __ARCH_S390_IOCTLS_H__
11
12#include <asm/ioctl.h>
13
14/* 0x54 is just a magic number to make these relatively unique ('T') */
15
16#define TCGETS 0x5401
17#define TCSETS 0x5402
18#define TCSETSW 0x5403
19#define TCSETSF 0x5404
20#define TCGETA 0x5405
21#define TCSETA 0x5406
22#define TCSETAW 0x5407
23#define TCSETAF 0x5408
24#define TCSBRK 0x5409
25#define TCXONC 0x540A
26#define TCFLSH 0x540B
27#define TIOCEXCL 0x540C
28#define TIOCNXCL 0x540D
29#define TIOCSCTTY 0x540E
30#define TIOCGPGRP 0x540F
31#define TIOCSPGRP 0x5410
32#define TIOCOUTQ 0x5411
33#define TIOCSTI 0x5412
34#define TIOCGWINSZ 0x5413
35#define TIOCSWINSZ 0x5414
36#define TIOCMGET 0x5415
37#define TIOCMBIS 0x5416
38#define TIOCMBIC 0x5417
39#define TIOCMSET 0x5418
40#define TIOCGSOFTCAR 0x5419
41#define TIOCSSOFTCAR 0x541A
42#define FIONREAD 0x541B
43#define TIOCINQ FIONREAD
44#define TIOCLINUX 0x541C
45#define TIOCCONS 0x541D
46#define TIOCGSERIAL 0x541E
47#define TIOCSSERIAL 0x541F
48#define TIOCPKT 0x5420
49#define FIONBIO 0x5421
50#define TIOCNOTTY 0x5422
51#define TIOCSETD 0x5423
52#define TIOCGETD 0x5424
53#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */
54#define TIOCSBRK 0x5427 /* BSD compatibility */
55#define TIOCCBRK 0x5428 /* BSD compatibility */
56#define TIOCGSID 0x5429 /* Return the session ID of FD */
57#define TCGETS2 _IOR('T',0x2A, struct termios2)
58#define TCSETS2 _IOW('T',0x2B, struct termios2)
59#define TCSETSW2 _IOW('T',0x2C, struct termios2)
60#define TCSETSF2 _IOW('T',0x2D, struct termios2)
61#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
62#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */
63
64#define FIONCLEX 0x5450 /* these numbers need to be adjusted. */
65#define FIOCLEX 0x5451
66#define FIOASYNC 0x5452
67#define TIOCSERCONFIG 0x5453
68#define TIOCSERGWILD 0x5454
69#define TIOCSERSWILD 0x5455
70#define TIOCGLCKTRMIOS 0x5456
71#define TIOCSLCKTRMIOS 0x5457
72#define TIOCSERGSTRUCT 0x5458 /* For debugging only */
73#define TIOCSERGETLSR 0x5459 /* Get line status register */
74#define TIOCSERGETMULTI 0x545A /* Get multiport config */
75#define TIOCSERSETMULTI 0x545B /* Set multiport config */
76
77#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */
78#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */
79#define FIOQSIZE 0x545E
80
81/* Used for packet mode */
82#define TIOCPKT_DATA 0
83#define TIOCPKT_FLUSHREAD 1
84#define TIOCPKT_FLUSHWRITE 2
85#define TIOCPKT_STOP 4
86#define TIOCPKT_START 8
87#define TIOCPKT_NOSTOP 16
88#define TIOCPKT_DOSTOP 32
89
90#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */
91
92#endif
diff --git a/include/asm-s390/ipcbuf.h b/include/asm-s390/ipcbuf.h
deleted file mode 100644
index 37f293d12c8..00000000000
--- a/include/asm-s390/ipcbuf.h
+++ /dev/null
@@ -1,31 +0,0 @@
1#ifndef __S390_IPCBUF_H__
2#define __S390_IPCBUF_H__
3
4/*
5 * The user_ipc_perm structure for S/390 architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 32-bit mode_t and seq
11 * - 2 miscellaneous 32-bit values
12 */
13
14struct ipc64_perm
15{
16 __kernel_key_t key;
17 __kernel_uid32_t uid;
18 __kernel_gid32_t gid;
19 __kernel_uid32_t cuid;
20 __kernel_gid32_t cgid;
21 __kernel_mode_t mode;
22 unsigned short __pad1;
23 unsigned short seq;
24#ifndef __s390x__
25 unsigned short __pad2;
26#endif /* ! __s390x__ */
27 unsigned long __unused1;
28 unsigned long __unused2;
29};
30
31#endif /* __S390_IPCBUF_H__ */
diff --git a/include/asm-s390/ipl.h b/include/asm-s390/ipl.h
deleted file mode 100644
index eaca6dff540..00000000000
--- a/include/asm-s390/ipl.h
+++ /dev/null
@@ -1,167 +0,0 @@
1/*
2 * s390 (re)ipl support
3 *
4 * Copyright IBM Corp. 2007
5 */
6
7#ifndef _ASM_S390_IPL_H
8#define _ASM_S390_IPL_H
9
10#include <asm/types.h>
11#include <asm/cio.h>
12#include <asm/setup.h>
13
14#define IPL_PARMBLOCK_ORIGIN 0x2000
15
16#define IPL_PARM_BLK_FCP_LEN (sizeof(struct ipl_list_hdr) + \
17 sizeof(struct ipl_block_fcp))
18
19#define IPL_PARM_BLK0_FCP_LEN (sizeof(struct ipl_block_fcp) + 8)
20
21#define IPL_PARM_BLK_CCW_LEN (sizeof(struct ipl_list_hdr) + \
22 sizeof(struct ipl_block_ccw))
23
24#define IPL_PARM_BLK0_CCW_LEN (sizeof(struct ipl_block_ccw) + 8)
25
26#define IPL_MAX_SUPPORTED_VERSION (0)
27
28#define IPL_PARMBLOCK_START ((struct ipl_parameter_block *) \
29 IPL_PARMBLOCK_ORIGIN)
30#define IPL_PARMBLOCK_SIZE (IPL_PARMBLOCK_START->hdr.len)
31
32struct ipl_list_hdr {
33 u32 len;
34 u8 reserved1[3];
35 u8 version;
36 u32 blk0_len;
37 u8 pbt;
38 u8 flags;
39 u16 reserved2;
40} __attribute__((packed));
41
42struct ipl_block_fcp {
43 u8 reserved1[313-1];
44 u8 opt;
45 u8 reserved2[3];
46 u16 reserved3;
47 u16 devno;
48 u8 reserved4[4];
49 u64 wwpn;
50 u64 lun;
51 u32 bootprog;
52 u8 reserved5[12];
53 u64 br_lba;
54 u32 scp_data_len;
55 u8 reserved6[260];
56 u8 scp_data[];
57} __attribute__((packed));
58
59#define DIAG308_VMPARM_SIZE 64
60
61struct ipl_block_ccw {
62 u8 load_parm[8];
63 u8 reserved1[84];
64 u8 reserved2[2];
65 u16 devno;
66 u8 vm_flags;
67 u8 reserved3[3];
68 u32 vm_parm_len;
69 u8 nss_name[8];
70 u8 vm_parm[DIAG308_VMPARM_SIZE];
71 u8 reserved4[8];
72} __attribute__((packed));
73
74struct ipl_parameter_block {
75 struct ipl_list_hdr hdr;
76 union {
77 struct ipl_block_fcp fcp;
78 struct ipl_block_ccw ccw;
79 } ipl_info;
80} __attribute__((packed,aligned(4096)));
81
82/*
83 * IPL validity flags
84 */
85extern u32 ipl_flags;
86extern u32 dump_prefix_page;
87extern unsigned int zfcpdump_prefix_array[];
88
89extern void do_reipl(void);
90extern void do_halt(void);
91extern void do_poff(void);
92extern void ipl_save_parameters(void);
93extern void ipl_update_parameters(void);
94extern void get_ipl_vmparm(char *);
95
96enum {
97 IPL_DEVNO_VALID = 1,
98 IPL_PARMBLOCK_VALID = 2,
99 IPL_NSS_VALID = 4,
100};
101
102enum ipl_type {
103 IPL_TYPE_UNKNOWN = 1,
104 IPL_TYPE_CCW = 2,
105 IPL_TYPE_FCP = 4,
106 IPL_TYPE_FCP_DUMP = 8,
107 IPL_TYPE_NSS = 16,
108};
109
110struct ipl_info
111{
112 enum ipl_type type;
113 union {
114 struct {
115 struct ccw_dev_id dev_id;
116 } ccw;
117 struct {
118 struct ccw_dev_id dev_id;
119 u64 wwpn;
120 u64 lun;
121 } fcp;
122 struct {
123 char name[NSS_NAME_SIZE + 1];
124 } nss;
125 } data;
126};
127
128extern struct ipl_info ipl_info;
129extern void setup_ipl(void);
130
131/*
132 * DIAG 308 support
133 */
134enum diag308_subcode {
135 DIAG308_REL_HSA = 2,
136 DIAG308_IPL = 3,
137 DIAG308_DUMP = 4,
138 DIAG308_SET = 5,
139 DIAG308_STORE = 6,
140};
141
142enum diag308_ipl_type {
143 DIAG308_IPL_TYPE_FCP = 0,
144 DIAG308_IPL_TYPE_CCW = 2,
145};
146
147enum diag308_opt {
148 DIAG308_IPL_OPT_IPL = 0x10,
149 DIAG308_IPL_OPT_DUMP = 0x20,
150};
151
152enum diag308_flags {
153 DIAG308_FLAGS_LP_VALID = 0x80,
154};
155
156enum diag308_vm_flags {
157 DIAG308_VM_FLAGS_NSS_VALID = 0x80,
158 DIAG308_VM_FLAGS_VP_VALID = 0x40,
159};
160
161enum diag308_rc {
162 DIAG308_RC_OK = 1,
163};
164
165extern int diag308(unsigned long subcode, void *addr);
166
167#endif /* _ASM_S390_IPL_H */
diff --git a/include/asm-s390/irq.h b/include/asm-s390/irq.h
deleted file mode 100644
index 7da991a858f..00000000000
--- a/include/asm-s390/irq.h
+++ /dev/null
@@ -1,23 +0,0 @@
1#ifndef _ASM_IRQ_H
2#define _ASM_IRQ_H
3
4#ifdef __KERNEL__
5#include <linux/hardirq.h>
6
7/*
8 * the definition of irqs has changed in 2.5.46:
9 * NR_IRQS is no longer the number of i/o
10 * interrupts (65536), but rather the number
11 * of interrupt classes (2).
12 * Only external and i/o interrupts make much sense here (CH).
13 */
14
15enum interruption_class {
16 EXTERNAL_INTERRUPT,
17 IO_INTERRUPT,
18
19 NR_IRQS,
20};
21
22#endif /* __KERNEL__ */
23#endif
diff --git a/include/asm-s390/irq_regs.h b/include/asm-s390/irq_regs.h
deleted file mode 100644
index 3dd9c0b7027..00000000000
--- a/include/asm-s390/irq_regs.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/irq_regs.h>
diff --git a/include/asm-s390/irqflags.h b/include/asm-s390/irqflags.h
deleted file mode 100644
index 3f26131120b..00000000000
--- a/include/asm-s390/irqflags.h
+++ /dev/null
@@ -1,106 +0,0 @@
1/*
2 * include/asm-s390/irqflags.h
3 *
4 * Copyright (C) IBM Corp. 2006
5 * Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>
6 */
7
8#ifndef __ASM_IRQFLAGS_H
9#define __ASM_IRQFLAGS_H
10
11#ifdef __KERNEL__
12
13#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
14
15/* store then or system mask. */
16#define __raw_local_irq_stosm(__or) \
17({ \
18 unsigned long __mask; \
19 asm volatile( \
20 " stosm %0,%1" \
21 : "=Q" (__mask) : "i" (__or) : "memory"); \
22 __mask; \
23})
24
25/* store then and system mask. */
26#define __raw_local_irq_stnsm(__and) \
27({ \
28 unsigned long __mask; \
29 asm volatile( \
30 " stnsm %0,%1" \
31 : "=Q" (__mask) : "i" (__and) : "memory"); \
32 __mask; \
33})
34
35/* set system mask. */
36#define __raw_local_irq_ssm(__mask) \
37({ \
38 asm volatile("ssm %0" : : "Q" (__mask) : "memory"); \
39})
40
41#else /* __GNUC__ */
42
43/* store then or system mask. */
44#define __raw_local_irq_stosm(__or) \
45({ \
46 unsigned long __mask; \
47 asm volatile( \
48 " stosm 0(%1),%2" \
49 : "=m" (__mask) \
50 : "a" (&__mask), "i" (__or) : "memory"); \
51 __mask; \
52})
53
54/* store then and system mask. */
55#define __raw_local_irq_stnsm(__and) \
56({ \
57 unsigned long __mask; \
58 asm volatile( \
59 " stnsm 0(%1),%2" \
60 : "=m" (__mask) \
61 : "a" (&__mask), "i" (__and) : "memory"); \
62 __mask; \
63})
64
65/* set system mask. */
66#define __raw_local_irq_ssm(__mask) \
67({ \
68 asm volatile( \
69 " ssm 0(%0)" \
70 : : "a" (&__mask), "m" (__mask) : "memory"); \
71})
72
73#endif /* __GNUC__ */
74
75/* interrupt control.. */
76static inline unsigned long raw_local_irq_enable(void)
77{
78 return __raw_local_irq_stosm(0x03);
79}
80
81static inline unsigned long raw_local_irq_disable(void)
82{
83 return __raw_local_irq_stnsm(0xfc);
84}
85
86#define raw_local_save_flags(x) \
87do { \
88 typecheck(unsigned long, x); \
89 (x) = __raw_local_irq_stosm(0x00); \
90} while (0)
91
92static inline void raw_local_irq_restore(unsigned long flags)
93{
94 __raw_local_irq_ssm(flags);
95}
96
97static inline int raw_irqs_disabled_flags(unsigned long flags)
98{
99 return !(flags & (3UL << (BITS_PER_LONG - 8)));
100}
101
102/* For spinlocks etc */
103#define raw_local_irq_save(x) ((x) = raw_local_irq_disable())
104
105#endif /* __KERNEL__ */
106#endif /* __ASM_IRQFLAGS_H */
diff --git a/include/asm-s390/isc.h b/include/asm-s390/isc.h
deleted file mode 100644
index 34bb8916db4..00000000000
--- a/include/asm-s390/isc.h
+++ /dev/null
@@ -1,25 +0,0 @@
1#ifndef _ASM_S390_ISC_H
2#define _ASM_S390_ISC_H
3
4#include <linux/types.h>
5
6/*
7 * I/O interruption subclasses used by drivers.
8 * Please add all used iscs here so that it is possible to distribute
9 * isc usage between drivers.
10 * Reminder: 0 is highest priority, 7 lowest.
11 */
12#define MAX_ISC 7
13
14/* Regular I/O interrupts. */
15#define IO_SCH_ISC 3 /* regular I/O subchannels */
16#define CONSOLE_ISC 1 /* console I/O subchannel */
17#define CHSC_SCH_ISC 7 /* CHSC subchannels */
18/* Adapter interrupts. */
19#define QDIO_AIRQ_ISC IO_SCH_ISC /* I/O subchannel in qdio mode */
20
21/* Functions for registration of I/O interruption subclasses */
22void isc_register(unsigned int isc);
23void isc_unregister(unsigned int isc);
24
25#endif /* _ASM_S390_ISC_H */
diff --git a/include/asm-s390/itcw.h b/include/asm-s390/itcw.h
deleted file mode 100644
index a9bc5c36b32..00000000000
--- a/include/asm-s390/itcw.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * Functions for incremental construction of fcx enabled I/O control blocks.
3 *
4 * Copyright IBM Corp. 2008
5 * Author(s): Peter Oberparleiter <peter.oberparleiter@de.ibm.com>
6 */
7
8#ifndef _ASM_S390_ITCW_H
9#define _ASM_S390_ITCW_H _ASM_S390_ITCW_H
10
11#include <linux/types.h>
12#include <asm/fcx.h>
13
14#define ITCW_OP_READ 0
15#define ITCW_OP_WRITE 1
16
17struct itcw;
18
19struct tcw *itcw_get_tcw(struct itcw *itcw);
20size_t itcw_calc_size(int intrg, int max_tidaws, int intrg_max_tidaws);
21struct itcw *itcw_init(void *buffer, size_t size, int op, int intrg,
22 int max_tidaws, int intrg_max_tidaws);
23struct dcw *itcw_add_dcw(struct itcw *itcw, u8 cmd, u8 flags, void *cd,
24 u8 cd_count, u32 count);
25struct tidaw *itcw_add_tidaw(struct itcw *itcw, u8 flags, void *addr,
26 u32 count);
27void itcw_set_data(struct itcw *itcw, void *addr, int use_tidal);
28void itcw_finalize(struct itcw *itcw);
29
30#endif /* _ASM_S390_ITCW_H */
diff --git a/include/asm-s390/kdebug.h b/include/asm-s390/kdebug.h
deleted file mode 100644
index 40db27cd6e6..00000000000
--- a/include/asm-s390/kdebug.h
+++ /dev/null
@@ -1,27 +0,0 @@
1#ifndef _S390_KDEBUG_H
2#define _S390_KDEBUG_H
3
4/*
5 * Feb 2006 Ported to s390 <grundym@us.ibm.com>
6 */
7
8struct pt_regs;
9
10enum die_val {
11 DIE_OOPS = 1,
12 DIE_BPT,
13 DIE_SSTEP,
14 DIE_PANIC,
15 DIE_NMI,
16 DIE_DIE,
17 DIE_NMIWATCHDOG,
18 DIE_KERNELDEBUG,
19 DIE_TRAP,
20 DIE_GPF,
21 DIE_CALL,
22 DIE_NMI_IPI,
23};
24
25extern void die(const char *, struct pt_regs *, long);
26
27#endif
diff --git a/include/asm-s390/kexec.h b/include/asm-s390/kexec.h
deleted file mode 100644
index f219c6411e0..00000000000
--- a/include/asm-s390/kexec.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * include/asm-s390/kexec.h
3 *
4 * (C) Copyright IBM Corp. 2005
5 *
6 * Author(s): Rolf Adelsberger <adelsberger@de.ibm.com>
7 *
8 */
9
10#ifndef _S390_KEXEC_H
11#define _S390_KEXEC_H
12
13#ifdef __KERNEL__
14#include <asm/page.h>
15#endif
16#include <asm/processor.h>
17/*
18 * KEXEC_SOURCE_MEMORY_LIMIT maximum page get_free_page can return.
19 * I.e. Maximum page that is mapped directly into kernel memory,
20 * and kmap is not required.
21 */
22
23/* Maximum physical address we can use pages from */
24#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
25
26/* Maximum address we can reach in physical address mode */
27#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
28
29/* Maximum address we can use for the control pages */
30/* Not more than 2GB */
31#define KEXEC_CONTROL_MEMORY_LIMIT (1UL<<31)
32
33/* Allocate one page for the pdp and the second for the code */
34#define KEXEC_CONTROL_CODE_SIZE 4096
35
36/* The native architecture */
37#define KEXEC_ARCH KEXEC_ARCH_S390
38
39/* Provide a dummy definition to avoid build failures. */
40static inline void crash_setup_regs(struct pt_regs *newregs,
41 struct pt_regs *oldregs) { }
42
43#endif /*_S390_KEXEC_H */
diff --git a/include/asm-s390/kmap_types.h b/include/asm-s390/kmap_types.h
deleted file mode 100644
index fd157464822..00000000000
--- a/include/asm-s390/kmap_types.h
+++ /dev/null
@@ -1,23 +0,0 @@
1#ifdef __KERNEL__
2#ifndef _ASM_KMAP_TYPES_H
3#define _ASM_KMAP_TYPES_H
4
5enum km_type {
6 KM_BOUNCE_READ,
7 KM_SKB_SUNRPC_DATA,
8 KM_SKB_DATA_SOFTIRQ,
9 KM_USER0,
10 KM_USER1,
11 KM_BIO_SRC_IRQ,
12 KM_BIO_DST_IRQ,
13 KM_PTE0,
14 KM_PTE1,
15 KM_IRQ0,
16 KM_IRQ1,
17 KM_SOFTIRQ0,
18 KM_SOFTIRQ1,
19 KM_TYPE_NR
20};
21
22#endif
23#endif /* __KERNEL__ */
diff --git a/include/asm-s390/kprobes.h b/include/asm-s390/kprobes.h
deleted file mode 100644
index 330f68caffe..00000000000
--- a/include/asm-s390/kprobes.h
+++ /dev/null
@@ -1,103 +0,0 @@
1#ifndef _ASM_S390_KPROBES_H
2#define _ASM_S390_KPROBES_H
3/*
4 * Kernel Probes (KProbes)
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 *
20 * Copyright (C) IBM Corporation, 2002, 2006
21 *
22 * 2002-Oct Created by Vamsi Krishna S <vamsi_krishna@in.ibm.com> Kernel
23 * Probes initial implementation ( includes suggestions from
24 * Rusty Russell).
25 * 2004-Nov Modified for PPC64 by Ananth N Mavinakayanahalli
26 * <ananth@in.ibm.com>
27 * 2005-Dec Used as a template for s390 by Mike Grundy
28 * <grundym@us.ibm.com>
29 */
30#include <linux/types.h>
31#include <linux/ptrace.h>
32#include <linux/percpu.h>
33
34#define __ARCH_WANT_KPROBES_INSN_SLOT
35struct pt_regs;
36struct kprobe;
37
38typedef u16 kprobe_opcode_t;
39#define BREAKPOINT_INSTRUCTION 0x0002
40
41/* Maximum instruction size is 3 (16bit) halfwords: */
42#define MAX_INSN_SIZE 0x0003
43#define MAX_STACK_SIZE 64
44#define MIN_STACK_SIZE(ADDR) (((MAX_STACK_SIZE) < \
45 (((unsigned long)current_thread_info()) + THREAD_SIZE - (ADDR))) \
46 ? (MAX_STACK_SIZE) \
47 : (((unsigned long)current_thread_info()) + THREAD_SIZE - (ADDR)))
48
49#define kretprobe_blacklist_size 0
50
51#define KPROBE_SWAP_INST 0x10
52
53#define FIXUP_PSW_NORMAL 0x08
54#define FIXUP_BRANCH_NOT_TAKEN 0x04
55#define FIXUP_RETURN_REGISTER 0x02
56#define FIXUP_NOT_REQUIRED 0x01
57
58/* Architecture specific copy of original instruction */
59struct arch_specific_insn {
60 /* copy of original instruction */
61 kprobe_opcode_t *insn;
62 int fixup;
63 int ilen;
64 int reg;
65};
66
67struct ins_replace_args {
68 kprobe_opcode_t *ptr;
69 kprobe_opcode_t old;
70 kprobe_opcode_t new;
71};
72struct prev_kprobe {
73 struct kprobe *kp;
74 unsigned long status;
75 unsigned long saved_psw;
76 unsigned long kprobe_saved_imask;
77 unsigned long kprobe_saved_ctl[3];
78};
79
80/* per-cpu kprobe control block */
81struct kprobe_ctlblk {
82 unsigned long kprobe_status;
83 unsigned long kprobe_saved_imask;
84 unsigned long kprobe_saved_ctl[3];
85 struct pt_regs jprobe_saved_regs;
86 unsigned long jprobe_saved_r14;
87 unsigned long jprobe_saved_r15;
88 struct prev_kprobe prev_kprobe;
89 kprobe_opcode_t jprobes_stack[MAX_STACK_SIZE];
90};
91
92void arch_remove_kprobe(struct kprobe *p);
93void kretprobe_trampoline(void);
94int is_prohibited_opcode(kprobe_opcode_t *instruction);
95void get_instruction_type(struct arch_specific_insn *ainsn);
96
97int kprobe_fault_handler(struct pt_regs *regs, int trapnr);
98int kprobe_exceptions_notify(struct notifier_block *self,
99 unsigned long val, void *data);
100
101#define flush_insn_slot(p) do { } while (0)
102
103#endif /* _ASM_S390_KPROBES_H */
diff --git a/include/asm-s390/kvm.h b/include/asm-s390/kvm.h
deleted file mode 100644
index d74002f9579..00000000000
--- a/include/asm-s390/kvm.h
+++ /dev/null
@@ -1,45 +0,0 @@
1#ifndef __LINUX_KVM_S390_H
2#define __LINUX_KVM_S390_H
3
4/*
5 * asm-s390/kvm.h - KVM s390 specific structures and definitions
6 *
7 * Copyright IBM Corp. 2008
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License (version 2 only)
11 * as published by the Free Software Foundation.
12 *
13 * Author(s): Carsten Otte <cotte@de.ibm.com>
14 * Christian Borntraeger <borntraeger@de.ibm.com>
15 */
16#include <asm/types.h>
17
18/* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */
19struct kvm_pic_state {
20 /* no PIC for s390 */
21};
22
23struct kvm_ioapic_state {
24 /* no IOAPIC for s390 */
25};
26
27/* for KVM_GET_REGS and KVM_SET_REGS */
28struct kvm_regs {
29 /* general purpose regs for s390 */
30 __u64 gprs[16];
31};
32
33/* for KVM_GET_SREGS and KVM_SET_SREGS */
34struct kvm_sregs {
35 __u32 acrs[16];
36 __u64 crs[16];
37};
38
39/* for KVM_GET_FPU and KVM_SET_FPU */
40struct kvm_fpu {
41 __u32 fpc;
42 __u64 fprs[16];
43};
44
45#endif
diff --git a/include/asm-s390/kvm_host.h b/include/asm-s390/kvm_host.h
deleted file mode 100644
index 3c55e4107dc..00000000000
--- a/include/asm-s390/kvm_host.h
+++ /dev/null
@@ -1,235 +0,0 @@
1/*
2 * asm-s390/kvm_host.h - definition for kernel virtual machines on s390
3 *
4 * Copyright IBM Corp. 2008
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License (version 2 only)
8 * as published by the Free Software Foundation.
9 *
10 * Author(s): Carsten Otte <cotte@de.ibm.com>
11 */
12
13
14#ifndef ASM_KVM_HOST_H
15#define ASM_KVM_HOST_H
16#include <linux/kvm_host.h>
17#include <asm/debug.h>
18
19#define KVM_MAX_VCPUS 64
20#define KVM_MEMORY_SLOTS 32
21/* memory slots that does not exposed to userspace */
22#define KVM_PRIVATE_MEM_SLOTS 4
23
24struct kvm_guest_debug {
25};
26
27struct sca_entry {
28 atomic_t scn;
29 __u64 reserved;
30 __u64 sda;
31 __u64 reserved2[2];
32} __attribute__((packed));
33
34
35struct sca_block {
36 __u64 ipte_control;
37 __u64 reserved[5];
38 __u64 mcn;
39 __u64 reserved2;
40 struct sca_entry cpu[64];
41} __attribute__((packed));
42
43#define KVM_PAGES_PER_HPAGE 256
44
45#define CPUSTAT_HOST 0x80000000
46#define CPUSTAT_WAIT 0x10000000
47#define CPUSTAT_ECALL_PEND 0x08000000
48#define CPUSTAT_STOP_INT 0x04000000
49#define CPUSTAT_IO_INT 0x02000000
50#define CPUSTAT_EXT_INT 0x01000000
51#define CPUSTAT_RUNNING 0x00800000
52#define CPUSTAT_RETAINED 0x00400000
53#define CPUSTAT_TIMING_SUB 0x00020000
54#define CPUSTAT_SIE_SUB 0x00010000
55#define CPUSTAT_RRF 0x00008000
56#define CPUSTAT_SLSV 0x00004000
57#define CPUSTAT_SLSR 0x00002000
58#define CPUSTAT_ZARCH 0x00000800
59#define CPUSTAT_MCDS 0x00000100
60#define CPUSTAT_SM 0x00000080
61#define CPUSTAT_G 0x00000008
62#define CPUSTAT_J 0x00000002
63#define CPUSTAT_P 0x00000001
64
65struct kvm_s390_sie_block {
66 atomic_t cpuflags; /* 0x0000 */
67 __u32 prefix; /* 0x0004 */
68 __u8 reserved8[32]; /* 0x0008 */
69 __u64 cputm; /* 0x0028 */
70 __u64 ckc; /* 0x0030 */
71 __u64 epoch; /* 0x0038 */
72 __u8 reserved40[4]; /* 0x0040 */
73#define LCTL_CR0 0x8000
74 __u16 lctl; /* 0x0044 */
75 __s16 icpua; /* 0x0046 */
76 __u32 ictl; /* 0x0048 */
77 __u32 eca; /* 0x004c */
78 __u8 icptcode; /* 0x0050 */
79 __u8 reserved51; /* 0x0051 */
80 __u16 ihcpu; /* 0x0052 */
81 __u8 reserved54[2]; /* 0x0054 */
82 __u16 ipa; /* 0x0056 */
83 __u32 ipb; /* 0x0058 */
84 __u32 scaoh; /* 0x005c */
85 __u8 reserved60; /* 0x0060 */
86 __u8 ecb; /* 0x0061 */
87 __u8 reserved62[2]; /* 0x0062 */
88 __u32 scaol; /* 0x0064 */
89 __u8 reserved68[4]; /* 0x0068 */
90 __u32 todpr; /* 0x006c */
91 __u8 reserved70[16]; /* 0x0070 */
92 __u64 gmsor; /* 0x0080 */
93 __u64 gmslm; /* 0x0088 */
94 psw_t gpsw; /* 0x0090 */
95 __u64 gg14; /* 0x00a0 */
96 __u64 gg15; /* 0x00a8 */
97 __u8 reservedb0[30]; /* 0x00b0 */
98 __u16 iprcc; /* 0x00ce */
99 __u8 reservedd0[48]; /* 0x00d0 */
100 __u64 gcr[16]; /* 0x0100 */
101 __u64 gbea; /* 0x0180 */
102 __u8 reserved188[120]; /* 0x0188 */
103} __attribute__((packed));
104
105struct kvm_vcpu_stat {
106 u32 exit_userspace;
107 u32 exit_null;
108 u32 exit_external_request;
109 u32 exit_external_interrupt;
110 u32 exit_stop_request;
111 u32 exit_validity;
112 u32 exit_instruction;
113 u32 instruction_lctl;
114 u32 instruction_lctlg;
115 u32 exit_program_interruption;
116 u32 exit_instr_and_program;
117 u32 deliver_emergency_signal;
118 u32 deliver_service_signal;
119 u32 deliver_virtio_interrupt;
120 u32 deliver_stop_signal;
121 u32 deliver_prefix_signal;
122 u32 deliver_restart_signal;
123 u32 deliver_program_int;
124 u32 exit_wait_state;
125 u32 instruction_stidp;
126 u32 instruction_spx;
127 u32 instruction_stpx;
128 u32 instruction_stap;
129 u32 instruction_storage_key;
130 u32 instruction_stsch;
131 u32 instruction_chsc;
132 u32 instruction_stsi;
133 u32 instruction_stfl;
134 u32 instruction_sigp_sense;
135 u32 instruction_sigp_emergency;
136 u32 instruction_sigp_stop;
137 u32 instruction_sigp_arch;
138 u32 instruction_sigp_prefix;
139 u32 instruction_sigp_restart;
140 u32 diagnose_44;
141};
142
143struct kvm_s390_io_info {
144 __u16 subchannel_id; /* 0x0b8 */
145 __u16 subchannel_nr; /* 0x0ba */
146 __u32 io_int_parm; /* 0x0bc */
147 __u32 io_int_word; /* 0x0c0 */
148};
149
150struct kvm_s390_ext_info {
151 __u32 ext_params;
152 __u64 ext_params2;
153};
154
155#define PGM_OPERATION 0x01
156#define PGM_PRIVILEGED_OPERATION 0x02
157#define PGM_EXECUTE 0x03
158#define PGM_PROTECTION 0x04
159#define PGM_ADDRESSING 0x05
160#define PGM_SPECIFICATION 0x06
161#define PGM_DATA 0x07
162
163struct kvm_s390_pgm_info {
164 __u16 code;
165};
166
167struct kvm_s390_prefix_info {
168 __u32 address;
169};
170
171struct kvm_s390_interrupt_info {
172 struct list_head list;
173 u64 type;
174 union {
175 struct kvm_s390_io_info io;
176 struct kvm_s390_ext_info ext;
177 struct kvm_s390_pgm_info pgm;
178 struct kvm_s390_prefix_info prefix;
179 };
180};
181
182/* for local_interrupt.action_flags */
183#define ACTION_STORE_ON_STOP 1
184#define ACTION_STOP_ON_STOP 2
185
186struct kvm_s390_local_interrupt {
187 spinlock_t lock;
188 struct list_head list;
189 atomic_t active;
190 struct kvm_s390_float_interrupt *float_int;
191 int timer_due; /* event indicator for waitqueue below */
192 wait_queue_head_t wq;
193 atomic_t *cpuflags;
194 unsigned int action_bits;
195};
196
197struct kvm_s390_float_interrupt {
198 spinlock_t lock;
199 struct list_head list;
200 atomic_t active;
201 int next_rr_cpu;
202 unsigned long idle_mask [(64 + sizeof(long) - 1) / sizeof(long)];
203 struct kvm_s390_local_interrupt *local_int[64];
204};
205
206
207struct kvm_vcpu_arch {
208 struct kvm_s390_sie_block *sie_block;
209 unsigned long guest_gprs[16];
210 s390_fp_regs host_fpregs;
211 unsigned int host_acrs[NUM_ACRS];
212 s390_fp_regs guest_fpregs;
213 unsigned int guest_acrs[NUM_ACRS];
214 struct kvm_s390_local_interrupt local_int;
215 struct timer_list ckc_timer;
216 union {
217 cpuid_t cpu_id;
218 u64 stidp_data;
219 };
220};
221
222struct kvm_vm_stat {
223 u32 remote_tlb_flush;
224};
225
226struct kvm_arch{
227 unsigned long guest_origin;
228 unsigned long guest_memsize;
229 struct sca_block *sca;
230 debug_info_t *dbf;
231 struct kvm_s390_float_interrupt float_int;
232};
233
234extern int sie64a(struct kvm_s390_sie_block *, unsigned long *);
235#endif
diff --git a/include/asm-s390/kvm_para.h b/include/asm-s390/kvm_para.h
deleted file mode 100644
index 2c503796b61..00000000000
--- a/include/asm-s390/kvm_para.h
+++ /dev/null
@@ -1,150 +0,0 @@
1/*
2 * asm-s390/kvm_para.h - definition for paravirtual devices on s390
3 *
4 * Copyright IBM Corp. 2008
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License (version 2 only)
8 * as published by the Free Software Foundation.
9 *
10 * Author(s): Christian Borntraeger <borntraeger@de.ibm.com>
11 */
12
13#ifndef __S390_KVM_PARA_H
14#define __S390_KVM_PARA_H
15
16/*
17 * Hypercalls for KVM on s390. The calling convention is similar to the
18 * s390 ABI, so we use R2-R6 for parameters 1-5. In addition we use R1
19 * as hypercall number and R7 as parameter 6. The return value is
20 * written to R2. We use the diagnose instruction as hypercall. To avoid
21 * conflicts with existing diagnoses for LPAR and z/VM, we do not use
22 * the instruction encoded number, but specify the number in R1 and
23 * use 0x500 as KVM hypercall
24 *
25 * Copyright IBM Corp. 2007,2008
26 * Author(s): Christian Borntraeger <borntraeger@de.ibm.com>
27 *
28 * This work is licensed under the terms of the GNU GPL, version 2.
29 */
30
31static inline long kvm_hypercall0(unsigned long nr)
32{
33 register unsigned long __nr asm("1") = nr;
34 register long __rc asm("2");
35
36 asm volatile ("diag 2,4,0x500\n"
37 : "=d" (__rc) : "d" (__nr): "memory", "cc");
38 return __rc;
39}
40
41static inline long kvm_hypercall1(unsigned long nr, unsigned long p1)
42{
43 register unsigned long __nr asm("1") = nr;
44 register unsigned long __p1 asm("2") = p1;
45 register long __rc asm("2");
46
47 asm volatile ("diag 2,4,0x500\n"
48 : "=d" (__rc) : "d" (__nr), "0" (__p1) : "memory", "cc");
49 return __rc;
50}
51
52static inline long kvm_hypercall2(unsigned long nr, unsigned long p1,
53 unsigned long p2)
54{
55 register unsigned long __nr asm("1") = nr;
56 register unsigned long __p1 asm("2") = p1;
57 register unsigned long __p2 asm("3") = p2;
58 register long __rc asm("2");
59
60 asm volatile ("diag 2,4,0x500\n"
61 : "=d" (__rc) : "d" (__nr), "0" (__p1), "d" (__p2)
62 : "memory", "cc");
63 return __rc;
64}
65
66static inline long kvm_hypercall3(unsigned long nr, unsigned long p1,
67 unsigned long p2, unsigned long p3)
68{
69 register unsigned long __nr asm("1") = nr;
70 register unsigned long __p1 asm("2") = p1;
71 register unsigned long __p2 asm("3") = p2;
72 register unsigned long __p3 asm("4") = p3;
73 register long __rc asm("2");
74
75 asm volatile ("diag 2,4,0x500\n"
76 : "=d" (__rc) : "d" (__nr), "0" (__p1), "d" (__p2),
77 "d" (__p3) : "memory", "cc");
78 return __rc;
79}
80
81
82static inline long kvm_hypercall4(unsigned long nr, unsigned long p1,
83 unsigned long p2, unsigned long p3,
84 unsigned long p4)
85{
86 register unsigned long __nr asm("1") = nr;
87 register unsigned long __p1 asm("2") = p1;
88 register unsigned long __p2 asm("3") = p2;
89 register unsigned long __p3 asm("4") = p3;
90 register unsigned long __p4 asm("5") = p4;
91 register long __rc asm("2");
92
93 asm volatile ("diag 2,4,0x500\n"
94 : "=d" (__rc) : "d" (__nr), "0" (__p1), "d" (__p2),
95 "d" (__p3), "d" (__p4) : "memory", "cc");
96 return __rc;
97}
98
99static inline long kvm_hypercall5(unsigned long nr, unsigned long p1,
100 unsigned long p2, unsigned long p3,
101 unsigned long p4, unsigned long p5)
102{
103 register unsigned long __nr asm("1") = nr;
104 register unsigned long __p1 asm("2") = p1;
105 register unsigned long __p2 asm("3") = p2;
106 register unsigned long __p3 asm("4") = p3;
107 register unsigned long __p4 asm("5") = p4;
108 register unsigned long __p5 asm("6") = p5;
109 register long __rc asm("2");
110
111 asm volatile ("diag 2,4,0x500\n"
112 : "=d" (__rc) : "d" (__nr), "0" (__p1), "d" (__p2),
113 "d" (__p3), "d" (__p4), "d" (__p5) : "memory", "cc");
114 return __rc;
115}
116
117static inline long kvm_hypercall6(unsigned long nr, unsigned long p1,
118 unsigned long p2, unsigned long p3,
119 unsigned long p4, unsigned long p5,
120 unsigned long p6)
121{
122 register unsigned long __nr asm("1") = nr;
123 register unsigned long __p1 asm("2") = p1;
124 register unsigned long __p2 asm("3") = p2;
125 register unsigned long __p3 asm("4") = p3;
126 register unsigned long __p4 asm("5") = p4;
127 register unsigned long __p5 asm("6") = p5;
128 register unsigned long __p6 asm("7") = p6;
129 register long __rc asm("2");
130
131 asm volatile ("diag 2,4,0x500\n"
132 : "=d" (__rc) : "d" (__nr), "0" (__p1), "d" (__p2),
133 "d" (__p3), "d" (__p4), "d" (__p5), "d" (__p6)
134 : "memory", "cc");
135 return __rc;
136}
137
138/* kvm on s390 is always paravirtualization enabled */
139static inline int kvm_para_available(void)
140{
141 return 1;
142}
143
144/* No feature bits are currently assigned for kvm on s390 */
145static inline unsigned int kvm_arch_para_features(void)
146{
147 return 0;
148}
149
150#endif /* __S390_KVM_PARA_H */
diff --git a/include/asm-s390/kvm_virtio.h b/include/asm-s390/kvm_virtio.h
deleted file mode 100644
index 146100224de..00000000000
--- a/include/asm-s390/kvm_virtio.h
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * kvm_virtio.h - definition for virtio for kvm on s390
3 *
4 * Copyright IBM Corp. 2008
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License (version 2 only)
8 * as published by the Free Software Foundation.
9 *
10 * Author(s): Christian Borntraeger <borntraeger@de.ibm.com>
11 */
12
13#ifndef __KVM_S390_VIRTIO_H
14#define __KVM_S390_VIRTIO_H
15
16#include <linux/types.h>
17
18struct kvm_device_desc {
19 /* The device type: console, network, disk etc. Type 0 terminates. */
20 __u8 type;
21 /* The number of virtqueues (first in config array) */
22 __u8 num_vq;
23 /*
24 * The number of bytes of feature bits. Multiply by 2: one for host
25 * features and one for guest acknowledgements.
26 */
27 __u8 feature_len;
28 /* The number of bytes of the config array after virtqueues. */
29 __u8 config_len;
30 /* A status byte, written by the Guest. */
31 __u8 status;
32 __u8 config[0];
33};
34
35/*
36 * This is how we expect the device configuration field for a virtqueue
37 * to be laid out in config space.
38 */
39struct kvm_vqconfig {
40 /* The token returned with an interrupt. Set by the guest */
41 __u64 token;
42 /* The address of the virtio ring */
43 __u64 address;
44 /* The number of entries in the virtio_ring */
45 __u16 num;
46
47};
48
49#define KVM_S390_VIRTIO_NOTIFY 0
50#define KVM_S390_VIRTIO_RESET 1
51#define KVM_S390_VIRTIO_SET_STATUS 2
52
53#ifdef __KERNEL__
54/* early virtio console setup */
55#ifdef CONFIG_VIRTIO_CONSOLE
56extern void s390_virtio_console_init(void);
57#else
58static inline void s390_virtio_console_init(void)
59{
60}
61#endif /* CONFIG_VIRTIO_CONSOLE */
62#endif /* __KERNEL__ */
63#endif
diff --git a/include/asm-s390/linkage.h b/include/asm-s390/linkage.h
deleted file mode 100644
index 291c2d01c44..00000000000
--- a/include/asm-s390/linkage.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef __ASM_LINKAGE_H
2#define __ASM_LINKAGE_H
3
4/* Nothing to see here... */
5
6#endif
diff --git a/include/asm-s390/local.h b/include/asm-s390/local.h
deleted file mode 100644
index c11c530f74d..00000000000
--- a/include/asm-s390/local.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/local.h>
diff --git a/include/asm-s390/lowcore.h b/include/asm-s390/lowcore.h
deleted file mode 100644
index 0bc51d52a89..00000000000
--- a/include/asm-s390/lowcore.h
+++ /dev/null
@@ -1,433 +0,0 @@
1/*
2 * include/asm-s390/lowcore.h
3 *
4 * S390 version
5 * Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Hartmut Penner (hp@de.ibm.com),
7 * Martin Schwidefsky (schwidefsky@de.ibm.com),
8 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
9 */
10
11#ifndef _ASM_S390_LOWCORE_H
12#define _ASM_S390_LOWCORE_H
13
14#ifndef __s390x__
15#define __LC_EXT_OLD_PSW 0x018
16#define __LC_SVC_OLD_PSW 0x020
17#define __LC_PGM_OLD_PSW 0x028
18#define __LC_MCK_OLD_PSW 0x030
19#define __LC_IO_OLD_PSW 0x038
20#define __LC_EXT_NEW_PSW 0x058
21#define __LC_SVC_NEW_PSW 0x060
22#define __LC_PGM_NEW_PSW 0x068
23#define __LC_MCK_NEW_PSW 0x070
24#define __LC_IO_NEW_PSW 0x078
25#else /* !__s390x__ */
26#define __LC_EXT_OLD_PSW 0x0130
27#define __LC_SVC_OLD_PSW 0x0140
28#define __LC_PGM_OLD_PSW 0x0150
29#define __LC_MCK_OLD_PSW 0x0160
30#define __LC_IO_OLD_PSW 0x0170
31#define __LC_EXT_NEW_PSW 0x01b0
32#define __LC_SVC_NEW_PSW 0x01c0
33#define __LC_PGM_NEW_PSW 0x01d0
34#define __LC_MCK_NEW_PSW 0x01e0
35#define __LC_IO_NEW_PSW 0x01f0
36#endif /* !__s390x__ */
37
38#define __LC_IPL_PARMBLOCK_PTR 0x014
39#define __LC_EXT_PARAMS 0x080
40#define __LC_CPU_ADDRESS 0x084
41#define __LC_EXT_INT_CODE 0x086
42
43#define __LC_SVC_ILC 0x088
44#define __LC_SVC_INT_CODE 0x08A
45#define __LC_PGM_ILC 0x08C
46#define __LC_PGM_INT_CODE 0x08E
47
48#define __LC_PER_ATMID 0x096
49#define __LC_PER_ADDRESS 0x098
50#define __LC_PER_ACCESS_ID 0x0A1
51#define __LC_AR_MODE_ID 0x0A3
52
53#define __LC_SUBCHANNEL_ID 0x0B8
54#define __LC_SUBCHANNEL_NR 0x0BA
55#define __LC_IO_INT_PARM 0x0BC
56#define __LC_IO_INT_WORD 0x0C0
57#define __LC_MCCK_CODE 0x0E8
58
59#define __LC_LAST_BREAK 0x110
60
61#define __LC_RETURN_PSW 0x200
62
63#define __LC_SAVE_AREA 0xC00
64
65#ifndef __s390x__
66#define __LC_IRB 0x208
67#define __LC_SYNC_ENTER_TIMER 0x248
68#define __LC_ASYNC_ENTER_TIMER 0x250
69#define __LC_EXIT_TIMER 0x258
70#define __LC_LAST_UPDATE_TIMER 0x260
71#define __LC_USER_TIMER 0x268
72#define __LC_SYSTEM_TIMER 0x270
73#define __LC_LAST_UPDATE_CLOCK 0x278
74#define __LC_STEAL_CLOCK 0x280
75#define __LC_RETURN_MCCK_PSW 0x288
76#define __LC_KERNEL_STACK 0xC40
77#define __LC_THREAD_INFO 0xC44
78#define __LC_ASYNC_STACK 0xC48
79#define __LC_KERNEL_ASCE 0xC4C
80#define __LC_USER_ASCE 0xC50
81#define __LC_PANIC_STACK 0xC54
82#define __LC_CPUID 0xC60
83#define __LC_CPUADDR 0xC68
84#define __LC_IPLDEV 0xC7C
85#define __LC_CURRENT 0xC90
86#define __LC_INT_CLOCK 0xC98
87#else /* __s390x__ */
88#define __LC_IRB 0x210
89#define __LC_SYNC_ENTER_TIMER 0x250
90#define __LC_ASYNC_ENTER_TIMER 0x258
91#define __LC_EXIT_TIMER 0x260
92#define __LC_LAST_UPDATE_TIMER 0x268
93#define __LC_USER_TIMER 0x270
94#define __LC_SYSTEM_TIMER 0x278
95#define __LC_LAST_UPDATE_CLOCK 0x280
96#define __LC_STEAL_CLOCK 0x288
97#define __LC_RETURN_MCCK_PSW 0x290
98#define __LC_KERNEL_STACK 0xD40
99#define __LC_THREAD_INFO 0xD48
100#define __LC_ASYNC_STACK 0xD50
101#define __LC_KERNEL_ASCE 0xD58
102#define __LC_USER_ASCE 0xD60
103#define __LC_PANIC_STACK 0xD68
104#define __LC_CPUID 0xD80
105#define __LC_CPUADDR 0xD88
106#define __LC_IPLDEV 0xDB8
107#define __LC_CURRENT 0xDD8
108#define __LC_INT_CLOCK 0xDE8
109#endif /* __s390x__ */
110
111
112#define __LC_PANIC_MAGIC 0xE00
113#ifndef __s390x__
114#define __LC_PFAULT_INTPARM 0x080
115#define __LC_CPU_TIMER_SAVE_AREA 0x0D8
116#define __LC_CLOCK_COMP_SAVE_AREA 0x0E0
117#define __LC_PSW_SAVE_AREA 0x100
118#define __LC_PREFIX_SAVE_AREA 0x108
119#define __LC_AREGS_SAVE_AREA 0x120
120#define __LC_FPREGS_SAVE_AREA 0x160
121#define __LC_GPREGS_SAVE_AREA 0x180
122#define __LC_CREGS_SAVE_AREA 0x1C0
123#else /* __s390x__ */
124#define __LC_PFAULT_INTPARM 0x11B8
125#define __LC_FPREGS_SAVE_AREA 0x1200
126#define __LC_GPREGS_SAVE_AREA 0x1280
127#define __LC_PSW_SAVE_AREA 0x1300
128#define __LC_PREFIX_SAVE_AREA 0x1318
129#define __LC_FP_CREG_SAVE_AREA 0x131C
130#define __LC_TODREG_SAVE_AREA 0x1324
131#define __LC_CPU_TIMER_SAVE_AREA 0x1328
132#define __LC_CLOCK_COMP_SAVE_AREA 0x1331
133#define __LC_AREGS_SAVE_AREA 0x1340
134#define __LC_CREGS_SAVE_AREA 0x1380
135#endif /* __s390x__ */
136
137#ifndef __ASSEMBLY__
138
139#include <asm/processor.h>
140#include <linux/types.h>
141#include <asm/sigp.h>
142
143void restart_int_handler(void);
144void ext_int_handler(void);
145void system_call(void);
146void pgm_check_handler(void);
147void mcck_int_handler(void);
148void io_int_handler(void);
149
150struct save_area_s390 {
151 u32 ext_save;
152 u64 timer;
153 u64 clk_cmp;
154 u8 pad1[24];
155 u8 psw[8];
156 u32 pref_reg;
157 u8 pad2[20];
158 u32 acc_regs[16];
159 u64 fp_regs[4];
160 u32 gp_regs[16];
161 u32 ctrl_regs[16];
162} __attribute__((packed));
163
164struct save_area_s390x {
165 u64 fp_regs[16];
166 u64 gp_regs[16];
167 u8 psw[16];
168 u8 pad1[8];
169 u32 pref_reg;
170 u32 fp_ctrl_reg;
171 u8 pad2[4];
172 u32 tod_reg;
173 u64 timer;
174 u64 clk_cmp;
175 u8 pad3[8];
176 u32 acc_regs[16];
177 u64 ctrl_regs[16];
178} __attribute__((packed));
179
180union save_area {
181 struct save_area_s390 s390;
182 struct save_area_s390x s390x;
183};
184
185#define SAVE_AREA_BASE_S390 0xd4
186#define SAVE_AREA_BASE_S390X 0x1200
187
188#ifndef __s390x__
189#define SAVE_AREA_SIZE sizeof(struct save_area_s390)
190#define SAVE_AREA_BASE SAVE_AREA_BASE_S390
191#else
192#define SAVE_AREA_SIZE sizeof(struct save_area_s390x)
193#define SAVE_AREA_BASE SAVE_AREA_BASE_S390X
194#endif
195
196struct _lowcore
197{
198#ifndef __s390x__
199 /* prefix area: defined by architecture */
200 psw_t restart_psw; /* 0x000 */
201 __u32 ccw2[4]; /* 0x008 */
202 psw_t external_old_psw; /* 0x018 */
203 psw_t svc_old_psw; /* 0x020 */
204 psw_t program_old_psw; /* 0x028 */
205 psw_t mcck_old_psw; /* 0x030 */
206 psw_t io_old_psw; /* 0x038 */
207 __u8 pad1[0x58-0x40]; /* 0x040 */
208 psw_t external_new_psw; /* 0x058 */
209 psw_t svc_new_psw; /* 0x060 */
210 psw_t program_new_psw; /* 0x068 */
211 psw_t mcck_new_psw; /* 0x070 */
212 psw_t io_new_psw; /* 0x078 */
213 __u32 ext_params; /* 0x080 */
214 __u16 cpu_addr; /* 0x084 */
215 __u16 ext_int_code; /* 0x086 */
216 __u16 svc_ilc; /* 0x088 */
217 __u16 svc_code; /* 0x08a */
218 __u16 pgm_ilc; /* 0x08c */
219 __u16 pgm_code; /* 0x08e */
220 __u32 trans_exc_code; /* 0x090 */
221 __u16 mon_class_num; /* 0x094 */
222 __u16 per_perc_atmid; /* 0x096 */
223 __u32 per_address; /* 0x098 */
224 __u32 monitor_code; /* 0x09c */
225 __u8 exc_access_id; /* 0x0a0 */
226 __u8 per_access_id; /* 0x0a1 */
227 __u8 pad2[0xB8-0xA2]; /* 0x0a2 */
228 __u16 subchannel_id; /* 0x0b8 */
229 __u16 subchannel_nr; /* 0x0ba */
230 __u32 io_int_parm; /* 0x0bc */
231 __u32 io_int_word; /* 0x0c0 */
232 __u8 pad3[0xc8-0xc4]; /* 0x0c4 */
233 __u32 stfl_fac_list; /* 0x0c8 */
234 __u8 pad4[0xd4-0xcc]; /* 0x0cc */
235 __u32 extended_save_area_addr; /* 0x0d4 */
236 __u32 cpu_timer_save_area[2]; /* 0x0d8 */
237 __u32 clock_comp_save_area[2]; /* 0x0e0 */
238 __u32 mcck_interruption_code[2]; /* 0x0e8 */
239 __u8 pad5[0xf4-0xf0]; /* 0x0f0 */
240 __u32 external_damage_code; /* 0x0f4 */
241 __u32 failing_storage_address; /* 0x0f8 */
242 __u8 pad6[0x100-0xfc]; /* 0x0fc */
243 __u32 st_status_fixed_logout[4];/* 0x100 */
244 __u8 pad7[0x120-0x110]; /* 0x110 */
245 __u32 access_regs_save_area[16];/* 0x120 */
246 __u32 floating_pt_save_area[8]; /* 0x160 */
247 __u32 gpregs_save_area[16]; /* 0x180 */
248 __u32 cregs_save_area[16]; /* 0x1c0 */
249
250 psw_t return_psw; /* 0x200 */
251 __u8 irb[64]; /* 0x208 */
252 __u64 sync_enter_timer; /* 0x248 */
253 __u64 async_enter_timer; /* 0x250 */
254 __u64 exit_timer; /* 0x258 */
255 __u64 last_update_timer; /* 0x260 */
256 __u64 user_timer; /* 0x268 */
257 __u64 system_timer; /* 0x270 */
258 __u64 last_update_clock; /* 0x278 */
259 __u64 steal_clock; /* 0x280 */
260 psw_t return_mcck_psw; /* 0x288 */
261 __u8 pad8[0xc00-0x290]; /* 0x290 */
262
263 /* System info area */
264 __u32 save_area[16]; /* 0xc00 */
265 __u32 kernel_stack; /* 0xc40 */
266 __u32 thread_info; /* 0xc44 */
267 __u32 async_stack; /* 0xc48 */
268 __u32 kernel_asce; /* 0xc4c */
269 __u32 user_asce; /* 0xc50 */
270 __u32 panic_stack; /* 0xc54 */
271 __u32 user_exec_asce; /* 0xc58 */
272 __u8 pad10[0xc60-0xc5c]; /* 0xc5c */
273 /* entry.S sensitive area start */
274 struct cpuinfo_S390 cpu_data; /* 0xc60 */
275 __u32 ipl_device; /* 0xc7c */
276 /* entry.S sensitive area end */
277
278 /* SMP info area: defined by DJB */
279 __u64 clock_comparator; /* 0xc80 */
280 __u32 ext_call_fast; /* 0xc88 */
281 __u32 percpu_offset; /* 0xc8c */
282 __u32 current_task; /* 0xc90 */
283 __u32 softirq_pending; /* 0xc94 */
284 __u64 int_clock; /* 0xc98 */
285 __u8 pad11[0xe00-0xca0]; /* 0xca0 */
286
287 /* 0xe00 is used as indicator for dump tools */
288 /* whether the kernel died with panic() or not */
289 __u32 panic_magic; /* 0xe00 */
290
291 /* Align to the top 1k of prefix area */
292 __u8 pad12[0x1000-0xe04]; /* 0xe04 */
293#else /* !__s390x__ */
294 /* prefix area: defined by architecture */
295 __u32 ccw1[2]; /* 0x000 */
296 __u32 ccw2[4]; /* 0x008 */
297 __u8 pad1[0x80-0x18]; /* 0x018 */
298 __u32 ext_params; /* 0x080 */
299 __u16 cpu_addr; /* 0x084 */
300 __u16 ext_int_code; /* 0x086 */
301 __u16 svc_ilc; /* 0x088 */
302 __u16 svc_code; /* 0x08a */
303 __u16 pgm_ilc; /* 0x08c */
304 __u16 pgm_code; /* 0x08e */
305 __u32 data_exc_code; /* 0x090 */
306 __u16 mon_class_num; /* 0x094 */
307 __u16 per_perc_atmid; /* 0x096 */
308 addr_t per_address; /* 0x098 */
309 __u8 exc_access_id; /* 0x0a0 */
310 __u8 per_access_id; /* 0x0a1 */
311 __u8 op_access_id; /* 0x0a2 */
312 __u8 ar_access_id; /* 0x0a3 */
313 __u8 pad2[0xA8-0xA4]; /* 0x0a4 */
314 addr_t trans_exc_code; /* 0x0A0 */
315 addr_t monitor_code; /* 0x09c */
316 __u16 subchannel_id; /* 0x0b8 */
317 __u16 subchannel_nr; /* 0x0ba */
318 __u32 io_int_parm; /* 0x0bc */
319 __u32 io_int_word; /* 0x0c0 */
320 __u8 pad3[0xc8-0xc4]; /* 0x0c4 */
321 __u32 stfl_fac_list; /* 0x0c8 */
322 __u8 pad4[0xe8-0xcc]; /* 0x0cc */
323 __u32 mcck_interruption_code[2]; /* 0x0e8 */
324 __u8 pad5[0xf4-0xf0]; /* 0x0f0 */
325 __u32 external_damage_code; /* 0x0f4 */
326 addr_t failing_storage_address; /* 0x0f8 */
327 __u8 pad6[0x120-0x100]; /* 0x100 */
328 psw_t restart_old_psw; /* 0x120 */
329 psw_t external_old_psw; /* 0x130 */
330 psw_t svc_old_psw; /* 0x140 */
331 psw_t program_old_psw; /* 0x150 */
332 psw_t mcck_old_psw; /* 0x160 */
333 psw_t io_old_psw; /* 0x170 */
334 __u8 pad7[0x1a0-0x180]; /* 0x180 */
335 psw_t restart_psw; /* 0x1a0 */
336 psw_t external_new_psw; /* 0x1b0 */
337 psw_t svc_new_psw; /* 0x1c0 */
338 psw_t program_new_psw; /* 0x1d0 */
339 psw_t mcck_new_psw; /* 0x1e0 */
340 psw_t io_new_psw; /* 0x1f0 */
341 psw_t return_psw; /* 0x200 */
342 __u8 irb[64]; /* 0x210 */
343 __u64 sync_enter_timer; /* 0x250 */
344 __u64 async_enter_timer; /* 0x258 */
345 __u64 exit_timer; /* 0x260 */
346 __u64 last_update_timer; /* 0x268 */
347 __u64 user_timer; /* 0x270 */
348 __u64 system_timer; /* 0x278 */
349 __u64 last_update_clock; /* 0x280 */
350 __u64 steal_clock; /* 0x288 */
351 psw_t return_mcck_psw; /* 0x290 */
352 __u8 pad8[0xc00-0x2a0]; /* 0x2a0 */
353 /* System info area */
354 __u64 save_area[16]; /* 0xc00 */
355 __u8 pad9[0xd40-0xc80]; /* 0xc80 */
356 __u64 kernel_stack; /* 0xd40 */
357 __u64 thread_info; /* 0xd48 */
358 __u64 async_stack; /* 0xd50 */
359 __u64 kernel_asce; /* 0xd58 */
360 __u64 user_asce; /* 0xd60 */
361 __u64 panic_stack; /* 0xd68 */
362 __u64 user_exec_asce; /* 0xd70 */
363 __u8 pad10[0xd80-0xd78]; /* 0xd78 */
364 /* entry.S sensitive area start */
365 struct cpuinfo_S390 cpu_data; /* 0xd80 */
366 __u32 ipl_device; /* 0xdb8 */
367 __u32 pad11; /* 0xdbc */
368 /* entry.S sensitive area end */
369
370 /* SMP info area: defined by DJB */
371 __u64 clock_comparator; /* 0xdc0 */
372 __u64 ext_call_fast; /* 0xdc8 */
373 __u64 percpu_offset; /* 0xdd0 */
374 __u64 current_task; /* 0xdd8 */
375 __u32 softirq_pending; /* 0xde0 */
376 __u32 pad_0x0de4; /* 0xde4 */
377 __u64 int_clock; /* 0xde8 */
378 __u8 pad12[0xe00-0xdf0]; /* 0xdf0 */
379
380 /* 0xe00 is used as indicator for dump tools */
381 /* whether the kernel died with panic() or not */
382 __u32 panic_magic; /* 0xe00 */
383
384 __u8 pad13[0x11b8-0xe04]; /* 0xe04 */
385
386 /* 64 bit extparam used for pfault, diag 250 etc */
387 __u64 ext_params2; /* 0x11B8 */
388
389 __u8 pad14[0x1200-0x11C0]; /* 0x11C0 */
390
391 /* System info area */
392
393 __u64 floating_pt_save_area[16]; /* 0x1200 */
394 __u64 gpregs_save_area[16]; /* 0x1280 */
395 __u32 st_status_fixed_logout[4]; /* 0x1300 */
396 __u8 pad15[0x1318-0x1310]; /* 0x1310 */
397 __u32 prefixreg_save_area; /* 0x1318 */
398 __u32 fpt_creg_save_area; /* 0x131c */
399 __u8 pad16[0x1324-0x1320]; /* 0x1320 */
400 __u32 tod_progreg_save_area; /* 0x1324 */
401 __u32 cpu_timer_save_area[2]; /* 0x1328 */
402 __u32 clock_comp_save_area[2]; /* 0x1330 */
403 __u8 pad17[0x1340-0x1338]; /* 0x1338 */
404 __u32 access_regs_save_area[16]; /* 0x1340 */
405 __u64 cregs_save_area[16]; /* 0x1380 */
406
407 /* align to the top of the prefix area */
408
409 __u8 pad18[0x2000-0x1400]; /* 0x1400 */
410#endif /* !__s390x__ */
411} __attribute__((packed)); /* End structure*/
412
413#define S390_lowcore (*((struct _lowcore *) 0))
414extern struct _lowcore *lowcore_ptr[];
415
416static inline void set_prefix(__u32 address)
417{
418 asm volatile("spx %0" : : "m" (address) : "memory");
419}
420
421static inline __u32 store_prefix(void)
422{
423 __u32 address;
424
425 asm volatile("stpx %0" : "=m" (address));
426 return address;
427}
428
429#define __PANIC_MAGIC 0xDEADC0DE
430
431#endif
432
433#endif
diff --git a/include/asm-s390/mathemu.h b/include/asm-s390/mathemu.h
deleted file mode 100644
index e8dd1ba8edb..00000000000
--- a/include/asm-s390/mathemu.h
+++ /dev/null
@@ -1,29 +0,0 @@
1/*
2 * arch/s390/kernel/mathemu.h
3 * IEEE floating point emulation.
4 *
5 * S390 version
6 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
7 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
8 */
9
10#ifndef __MATHEMU__
11#define __MATHEMU__
12
13extern int math_emu_b3(__u8 *, struct pt_regs *);
14extern int math_emu_ed(__u8 *, struct pt_regs *);
15extern int math_emu_ldr(__u8 *);
16extern int math_emu_ler(__u8 *);
17extern int math_emu_std(__u8 *, struct pt_regs *);
18extern int math_emu_ld(__u8 *, struct pt_regs *);
19extern int math_emu_ste(__u8 *, struct pt_regs *);
20extern int math_emu_le(__u8 *, struct pt_regs *);
21extern int math_emu_lfpc(__u8 *, struct pt_regs *);
22extern int math_emu_stfpc(__u8 *, struct pt_regs *);
23extern int math_emu_srnm(__u8 *, struct pt_regs *);
24
25#endif /* __MATHEMU__ */
26
27
28
29
diff --git a/include/asm-s390/mman.h b/include/asm-s390/mman.h
deleted file mode 100644
index 7839767d837..00000000000
--- a/include/asm-s390/mman.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * include/asm-s390/mman.h
3 *
4 * S390 version
5 *
6 * Derived from "include/asm-i386/mman.h"
7 */
8
9#ifndef __S390_MMAN_H__
10#define __S390_MMAN_H__
11
12#include <asm-generic/mman.h>
13
14#define MAP_GROWSDOWN 0x0100 /* stack-like segment */
15#define MAP_DENYWRITE 0x0800 /* ETXTBSY */
16#define MAP_EXECUTABLE 0x1000 /* mark it as an executable */
17#define MAP_LOCKED 0x2000 /* pages are locked */
18#define MAP_NORESERVE 0x4000 /* don't check for reservations */
19#define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */
20#define MAP_NONBLOCK 0x10000 /* do not block on IO */
21
22#define MCL_CURRENT 1 /* lock all current mappings */
23#define MCL_FUTURE 2 /* lock all future mappings */
24
25#endif /* __S390_MMAN_H__ */
diff --git a/include/asm-s390/mmu.h b/include/asm-s390/mmu.h
deleted file mode 100644
index 5dd5e7b3476..00000000000
--- a/include/asm-s390/mmu.h
+++ /dev/null
@@ -1,13 +0,0 @@
1#ifndef __MMU_H
2#define __MMU_H
3
4typedef struct {
5 struct list_head crst_list;
6 struct list_head pgtable_list;
7 unsigned long asce_bits;
8 unsigned long asce_limit;
9 int noexec;
10 int pgstes;
11} mm_context_t;
12
13#endif
diff --git a/include/asm-s390/mmu_context.h b/include/asm-s390/mmu_context.h
deleted file mode 100644
index 4c2fbf48c9c..00000000000
--- a/include/asm-s390/mmu_context.h
+++ /dev/null
@@ -1,77 +0,0 @@
1/*
2 * include/asm-s390/mmu_context.h
3 *
4 * S390 version
5 *
6 * Derived from "include/asm-i386/mmu_context.h"
7 */
8
9#ifndef __S390_MMU_CONTEXT_H
10#define __S390_MMU_CONTEXT_H
11
12#include <asm/pgalloc.h>
13#include <asm/uaccess.h>
14#include <asm-generic/mm_hooks.h>
15
16static inline int init_new_context(struct task_struct *tsk,
17 struct mm_struct *mm)
18{
19 mm->context.asce_bits = _ASCE_TABLE_LENGTH | _ASCE_USER_BITS;
20#ifdef CONFIG_64BIT
21 mm->context.asce_bits |= _ASCE_TYPE_REGION3;
22#endif
23 if (current->mm->context.pgstes) {
24 mm->context.noexec = 0;
25 mm->context.pgstes = 1;
26 } else {
27 mm->context.noexec = s390_noexec;
28 mm->context.pgstes = 0;
29 }
30 mm->context.asce_limit = STACK_TOP_MAX;
31 crst_table_init((unsigned long *) mm->pgd, pgd_entry_type(mm));
32 return 0;
33}
34
35#define destroy_context(mm) do { } while (0)
36
37#ifndef __s390x__
38#define LCTL_OPCODE "lctl"
39#else
40#define LCTL_OPCODE "lctlg"
41#endif
42
43static inline void update_mm(struct mm_struct *mm, struct task_struct *tsk)
44{
45 pgd_t *pgd = mm->pgd;
46
47 S390_lowcore.user_asce = mm->context.asce_bits | __pa(pgd);
48 if (switch_amode) {
49 /* Load primary space page table origin. */
50 pgd = mm->context.noexec ? get_shadow_table(pgd) : pgd;
51 S390_lowcore.user_exec_asce = mm->context.asce_bits | __pa(pgd);
52 asm volatile(LCTL_OPCODE" 1,1,%0\n"
53 : : "m" (S390_lowcore.user_exec_asce) );
54 } else
55 /* Load home space page table origin. */
56 asm volatile(LCTL_OPCODE" 13,13,%0"
57 : : "m" (S390_lowcore.user_asce) );
58 set_fs(current->thread.mm_segment);
59}
60
61static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
62 struct task_struct *tsk)
63{
64 cpu_set(smp_processor_id(), next->cpu_vm_mask);
65 update_mm(next, tsk);
66}
67
68#define enter_lazy_tlb(mm,tsk) do { } while (0)
69#define deactivate_mm(tsk,mm) do { } while (0)
70
71static inline void activate_mm(struct mm_struct *prev,
72 struct mm_struct *next)
73{
74 switch_mm(prev, next, current);
75}
76
77#endif /* __S390_MMU_CONTEXT_H */
diff --git a/include/asm-s390/module.h b/include/asm-s390/module.h
deleted file mode 100644
index 1cc1c5af705..00000000000
--- a/include/asm-s390/module.h
+++ /dev/null
@@ -1,46 +0,0 @@
1#ifndef _ASM_S390_MODULE_H
2#define _ASM_S390_MODULE_H
3/*
4 * This file contains the s390 architecture specific module code.
5 */
6
7struct mod_arch_syminfo
8{
9 unsigned long got_offset;
10 unsigned long plt_offset;
11 int got_initialized;
12 int plt_initialized;
13};
14
15struct mod_arch_specific
16{
17 /* Starting offset of got in the module core memory. */
18 unsigned long got_offset;
19 /* Starting offset of plt in the module core memory. */
20 unsigned long plt_offset;
21 /* Size of the got. */
22 unsigned long got_size;
23 /* Size of the plt. */
24 unsigned long plt_size;
25 /* Number of symbols in syminfo. */
26 int nsyms;
27 /* Additional symbol information (got and plt offsets). */
28 struct mod_arch_syminfo *syminfo;
29};
30
31#ifdef __s390x__
32#define ElfW(x) Elf64_ ## x
33#define ELFW(x) ELF64_ ## x
34#else
35#define ElfW(x) Elf32_ ## x
36#define ELFW(x) ELF32_ ## x
37#endif
38
39#define Elf_Addr ElfW(Addr)
40#define Elf_Rela ElfW(Rela)
41#define Elf_Shdr ElfW(Shdr)
42#define Elf_Sym ElfW(Sym)
43#define Elf_Ehdr ElfW(Ehdr)
44#define ELF_R_SYM ELFW(R_SYM)
45#define ELF_R_TYPE ELFW(R_TYPE)
46#endif /* _ASM_S390_MODULE_H */
diff --git a/include/asm-s390/monwriter.h b/include/asm-s390/monwriter.h
deleted file mode 100644
index f0cbf96c52e..00000000000
--- a/include/asm-s390/monwriter.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * include/asm-s390/monwriter.h
3 *
4 * Copyright (C) IBM Corp. 2006
5 * Character device driver for writing z/VM APPLDATA monitor records
6 * Version 1.0
7 * Author(s): Melissa Howland <melissah@us.ibm.com>
8 *
9 */
10
11#ifndef _ASM_390_MONWRITER_H
12#define _ASM_390_MONWRITER_H
13
14/* mon_function values */
15#define MONWRITE_START_INTERVAL 0x00 /* start interval recording */
16#define MONWRITE_STOP_INTERVAL 0x01 /* stop interval or config recording */
17#define MONWRITE_GEN_EVENT 0x02 /* generate event record */
18#define MONWRITE_START_CONFIG 0x03 /* start configuration recording */
19
20/* the header the app uses in its write() data */
21struct monwrite_hdr {
22 unsigned char mon_function;
23 unsigned short applid;
24 unsigned char record_num;
25 unsigned short version;
26 unsigned short release;
27 unsigned short mod_level;
28 unsigned short datalen;
29 unsigned char hdrlen;
30
31} __attribute__((packed));
32
33#endif /* _ASM_390_MONWRITER_H */
diff --git a/include/asm-s390/msgbuf.h b/include/asm-s390/msgbuf.h
deleted file mode 100644
index 1bbdee92792..00000000000
--- a/include/asm-s390/msgbuf.h
+++ /dev/null
@@ -1,37 +0,0 @@
1#ifndef _S390_MSGBUF_H
2#define _S390_MSGBUF_H
3
4/*
5 * The msqid64_ds structure for S/390 architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 64-bit time_t to solve y2038 problem
11 * - 2 miscellaneous 32-bit values
12 */
13
14struct msqid64_ds {
15 struct ipc64_perm msg_perm;
16 __kernel_time_t msg_stime; /* last msgsnd time */
17#ifndef __s390x__
18 unsigned long __unused1;
19#endif /* ! __s390x__ */
20 __kernel_time_t msg_rtime; /* last msgrcv time */
21#ifndef __s390x__
22 unsigned long __unused2;
23#endif /* ! __s390x__ */
24 __kernel_time_t msg_ctime; /* last change time */
25#ifndef __s390x__
26 unsigned long __unused3;
27#endif /* ! __s390x__ */
28 unsigned long msg_cbytes; /* current number of bytes on queue */
29 unsigned long msg_qnum; /* number of messages in queue */
30 unsigned long msg_qbytes; /* max number of bytes on queue */
31 __kernel_pid_t msg_lspid; /* pid of last msgsnd */
32 __kernel_pid_t msg_lrpid; /* last receive pid */
33 unsigned long __unused4;
34 unsigned long __unused5;
35};
36
37#endif /* _S390_MSGBUF_H */
diff --git a/include/asm-s390/mutex.h b/include/asm-s390/mutex.h
deleted file mode 100644
index 458c1f7fbc1..00000000000
--- a/include/asm-s390/mutex.h
+++ /dev/null
@@ -1,9 +0,0 @@
1/*
2 * Pull in the generic implementation for the mutex fastpath.
3 *
4 * TODO: implement optimized primitives instead, or leave the generic
5 * implementation in place, or pick the atomic_xchg() based generic
6 * implementation. (see asm-generic/mutex-xchg.h for details)
7 */
8
9#include <asm-generic/mutex-dec.h>
diff --git a/include/asm-s390/page.h b/include/asm-s390/page.h
deleted file mode 100644
index 991ba939408..00000000000
--- a/include/asm-s390/page.h
+++ /dev/null
@@ -1,155 +0,0 @@
1/*
2 * include/asm-s390/page.h
3 *
4 * S390 version
5 * Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Hartmut Penner (hp@de.ibm.com)
7 */
8
9#ifndef _S390_PAGE_H
10#define _S390_PAGE_H
11
12#include <linux/const.h>
13#include <asm/types.h>
14
15/* PAGE_SHIFT determines the page size */
16#define PAGE_SHIFT 12
17#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT)
18#define PAGE_MASK (~(PAGE_SIZE-1))
19#define PAGE_DEFAULT_ACC 0
20#define PAGE_DEFAULT_KEY (PAGE_DEFAULT_ACC << 4)
21
22#define HPAGE_SHIFT 20
23#define HPAGE_SIZE (1UL << HPAGE_SHIFT)
24#define HPAGE_MASK (~(HPAGE_SIZE - 1))
25#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
26
27#define ARCH_HAS_SETCLEAR_HUGE_PTE
28#define ARCH_HAS_HUGE_PTE_TYPE
29#define ARCH_HAS_PREPARE_HUGEPAGE
30#define ARCH_HAS_HUGEPAGE_CLEAR_FLUSH
31
32#include <asm/setup.h>
33#ifndef __ASSEMBLY__
34
35static inline void clear_page(void *page)
36{
37 if (MACHINE_HAS_PFMF) {
38 asm volatile(
39 " .insn rre,0xb9af0000,%0,%1"
40 : : "d" (0x10000), "a" (page) : "memory", "cc");
41 } else {
42 register unsigned long reg1 asm ("1") = 0;
43 register void *reg2 asm ("2") = page;
44 register unsigned long reg3 asm ("3") = 4096;
45 asm volatile(
46 " mvcl 2,0"
47 : "+d" (reg2), "+d" (reg3) : "d" (reg1)
48 : "memory", "cc");
49 }
50}
51
52static inline void copy_page(void *to, void *from)
53{
54 if (MACHINE_HAS_MVPG) {
55 register unsigned long reg0 asm ("0") = 0;
56 asm volatile(
57 " mvpg %0,%1"
58 : : "a" (to), "a" (from), "d" (reg0)
59 : "memory", "cc");
60 } else
61 asm volatile(
62 " mvc 0(256,%0),0(%1)\n"
63 " mvc 256(256,%0),256(%1)\n"
64 " mvc 512(256,%0),512(%1)\n"
65 " mvc 768(256,%0),768(%1)\n"
66 " mvc 1024(256,%0),1024(%1)\n"
67 " mvc 1280(256,%0),1280(%1)\n"
68 " mvc 1536(256,%0),1536(%1)\n"
69 " mvc 1792(256,%0),1792(%1)\n"
70 " mvc 2048(256,%0),2048(%1)\n"
71 " mvc 2304(256,%0),2304(%1)\n"
72 " mvc 2560(256,%0),2560(%1)\n"
73 " mvc 2816(256,%0),2816(%1)\n"
74 " mvc 3072(256,%0),3072(%1)\n"
75 " mvc 3328(256,%0),3328(%1)\n"
76 " mvc 3584(256,%0),3584(%1)\n"
77 " mvc 3840(256,%0),3840(%1)\n"
78 : : "a" (to), "a" (from) : "memory");
79}
80
81#define clear_user_page(page, vaddr, pg) clear_page(page)
82#define copy_user_page(to, from, vaddr, pg) copy_page(to, from)
83
84#define __alloc_zeroed_user_highpage(movableflags, vma, vaddr) \
85 alloc_page_vma(GFP_HIGHUSER | __GFP_ZERO | movableflags, vma, vaddr)
86#define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE
87
88/*
89 * These are used to make use of C type-checking..
90 */
91
92typedef struct { unsigned long pgprot; } pgprot_t;
93typedef struct { unsigned long pte; } pte_t;
94typedef struct { unsigned long pmd; } pmd_t;
95typedef struct { unsigned long pud; } pud_t;
96typedef struct { unsigned long pgd; } pgd_t;
97typedef pte_t *pgtable_t;
98
99#define pgprot_val(x) ((x).pgprot)
100#define pte_val(x) ((x).pte)
101#define pmd_val(x) ((x).pmd)
102#define pud_val(x) ((x).pud)
103#define pgd_val(x) ((x).pgd)
104
105#define __pte(x) ((pte_t) { (x) } )
106#define __pmd(x) ((pmd_t) { (x) } )
107#define __pgd(x) ((pgd_t) { (x) } )
108#define __pgprot(x) ((pgprot_t) { (x) } )
109
110/* default storage key used for all pages */
111extern unsigned int default_storage_key;
112
113static inline void
114page_set_storage_key(unsigned long addr, unsigned int skey)
115{
116 asm volatile("sske %0,%1" : : "d" (skey), "a" (addr));
117}
118
119static inline unsigned int
120page_get_storage_key(unsigned long addr)
121{
122 unsigned int skey;
123
124 asm volatile("iske %0,%1" : "=d" (skey) : "a" (addr), "0" (0));
125 return skey;
126}
127
128#ifdef CONFIG_PAGE_STATES
129
130struct page;
131void arch_free_page(struct page *page, int order);
132void arch_alloc_page(struct page *page, int order);
133
134#define HAVE_ARCH_FREE_PAGE
135#define HAVE_ARCH_ALLOC_PAGE
136
137#endif
138
139#endif /* !__ASSEMBLY__ */
140
141#define __PAGE_OFFSET 0x0UL
142#define PAGE_OFFSET 0x0UL
143#define __pa(x) (unsigned long)(x)
144#define __va(x) (void *)(unsigned long)(x)
145#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
146#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
147#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
148
149#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | \
150 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
151
152#include <asm-generic/memory_model.h>
153#include <asm-generic/page.h>
154
155#endif /* _S390_PAGE_H */
diff --git a/include/asm-s390/param.h b/include/asm-s390/param.h
deleted file mode 100644
index 34aaa460334..00000000000
--- a/include/asm-s390/param.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * include/asm-s390/param.h
3 *
4 * S390 version
5 *
6 * Derived from "include/asm-i386/param.h"
7 */
8
9#ifndef _ASMS390_PARAM_H
10#define _ASMS390_PARAM_H
11
12#ifdef __KERNEL__
13# define HZ CONFIG_HZ /* Internal kernel timer frequency */
14# define USER_HZ 100 /* .. some user interfaces are in "ticks" */
15# define CLOCKS_PER_SEC (USER_HZ) /* like times() */
16#endif
17
18#ifndef HZ
19#define HZ 100
20#endif
21
22#define EXEC_PAGESIZE 4096
23
24#ifndef NOGROUP
25#define NOGROUP (-1)
26#endif
27
28#define MAXHOSTNAMELEN 64 /* max length of hostname */
29
30#endif
diff --git a/include/asm-s390/pci.h b/include/asm-s390/pci.h
deleted file mode 100644
index 42a145c9ddd..00000000000
--- a/include/asm-s390/pci.h
+++ /dev/null
@@ -1,10 +0,0 @@
1#ifndef __ASM_S390_PCI_H
2#define __ASM_S390_PCI_H
3
4/* S/390 systems don't have a PCI bus. This file is just here because some stupid .c code
5 * includes it even if CONFIG_PCI is not set.
6 */
7#define PCI_DMA_BUS_IS_PHYS (0)
8
9#endif /* __ASM_S390_PCI_H */
10
diff --git a/include/asm-s390/percpu.h b/include/asm-s390/percpu.h
deleted file mode 100644
index 408d60b4f75..00000000000
--- a/include/asm-s390/percpu.h
+++ /dev/null
@@ -1,37 +0,0 @@
1#ifndef __ARCH_S390_PERCPU__
2#define __ARCH_S390_PERCPU__
3
4#include <linux/compiler.h>
5#include <asm/lowcore.h>
6
7/*
8 * s390 uses its own implementation for per cpu data, the offset of
9 * the cpu local data area is cached in the cpu's lowcore memory.
10 * For 64 bit module code s390 forces the use of a GOT slot for the
11 * address of the per cpu variable. This is needed because the module
12 * may be more than 4G above the per cpu area.
13 */
14#if defined(__s390x__) && defined(MODULE)
15
16#define SHIFT_PERCPU_PTR(ptr,offset) (({ \
17 extern int simple_identifier_##var(void); \
18 unsigned long *__ptr; \
19 asm ( "larl %0, %1@GOTENT" \
20 : "=a" (__ptr) : "X" (ptr) ); \
21 (typeof(ptr))((*__ptr) + (offset)); }))
22
23#else
24
25#define SHIFT_PERCPU_PTR(ptr, offset) (({ \
26 extern int simple_identifier_##var(void); \
27 unsigned long __ptr; \
28 asm ( "" : "=a" (__ptr) : "0" (ptr) ); \
29 (typeof(ptr)) (__ptr + (offset)); }))
30
31#endif
32
33#define __my_cpu_offset S390_lowcore.percpu_offset
34
35#include <asm-generic/percpu.h>
36
37#endif /* __ARCH_S390_PERCPU__ */
diff --git a/include/asm-s390/pgalloc.h b/include/asm-s390/pgalloc.h
deleted file mode 100644
index f5b2bf3d7c1..00000000000
--- a/include/asm-s390/pgalloc.h
+++ /dev/null
@@ -1,174 +0,0 @@
1/*
2 * include/asm-s390/pgalloc.h
3 *
4 * S390 version
5 * Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Hartmut Penner (hp@de.ibm.com)
7 * Martin Schwidefsky (schwidefsky@de.ibm.com)
8 *
9 * Derived from "include/asm-i386/pgalloc.h"
10 * Copyright (C) 1994 Linus Torvalds
11 */
12
13#ifndef _S390_PGALLOC_H
14#define _S390_PGALLOC_H
15
16#include <linux/threads.h>
17#include <linux/gfp.h>
18#include <linux/mm.h>
19
20#define check_pgt_cache() do {} while (0)
21
22unsigned long *crst_table_alloc(struct mm_struct *, int);
23void crst_table_free(struct mm_struct *, unsigned long *);
24
25unsigned long *page_table_alloc(struct mm_struct *);
26void page_table_free(struct mm_struct *, unsigned long *);
27void disable_noexec(struct mm_struct *, struct task_struct *);
28
29static inline void clear_table(unsigned long *s, unsigned long val, size_t n)
30{
31 *s = val;
32 n = (n / 256) - 1;
33 asm volatile(
34#ifdef CONFIG_64BIT
35 " mvc 8(248,%0),0(%0)\n"
36#else
37 " mvc 4(252,%0),0(%0)\n"
38#endif
39 "0: mvc 256(256,%0),0(%0)\n"
40 " la %0,256(%0)\n"
41 " brct %1,0b\n"
42 : "+a" (s), "+d" (n));
43}
44
45static inline void crst_table_init(unsigned long *crst, unsigned long entry)
46{
47 clear_table(crst, entry, sizeof(unsigned long)*2048);
48 crst = get_shadow_table(crst);
49 if (crst)
50 clear_table(crst, entry, sizeof(unsigned long)*2048);
51}
52
53#ifndef __s390x__
54
55static inline unsigned long pgd_entry_type(struct mm_struct *mm)
56{
57 return _SEGMENT_ENTRY_EMPTY;
58}
59
60#define pud_alloc_one(mm,address) ({ BUG(); ((pud_t *)2); })
61#define pud_free(mm, x) do { } while (0)
62
63#define pmd_alloc_one(mm,address) ({ BUG(); ((pmd_t *)2); })
64#define pmd_free(mm, x) do { } while (0)
65
66#define pgd_populate(mm, pgd, pud) BUG()
67#define pgd_populate_kernel(mm, pgd, pud) BUG()
68
69#define pud_populate(mm, pud, pmd) BUG()
70#define pud_populate_kernel(mm, pud, pmd) BUG()
71
72#else /* __s390x__ */
73
74static inline unsigned long pgd_entry_type(struct mm_struct *mm)
75{
76 if (mm->context.asce_limit <= (1UL << 31))
77 return _SEGMENT_ENTRY_EMPTY;
78 if (mm->context.asce_limit <= (1UL << 42))
79 return _REGION3_ENTRY_EMPTY;
80 return _REGION2_ENTRY_EMPTY;
81}
82
83int crst_table_upgrade(struct mm_struct *, unsigned long limit);
84void crst_table_downgrade(struct mm_struct *, unsigned long limit);
85
86static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long address)
87{
88 unsigned long *table = crst_table_alloc(mm, mm->context.noexec);
89 if (table)
90 crst_table_init(table, _REGION3_ENTRY_EMPTY);
91 return (pud_t *) table;
92}
93#define pud_free(mm, pud) crst_table_free(mm, (unsigned long *) pud)
94
95static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long vmaddr)
96{
97 unsigned long *table = crst_table_alloc(mm, mm->context.noexec);
98 if (table)
99 crst_table_init(table, _SEGMENT_ENTRY_EMPTY);
100 return (pmd_t *) table;
101}
102#define pmd_free(mm, pmd) crst_table_free(mm, (unsigned long *) pmd)
103
104static inline void pgd_populate_kernel(struct mm_struct *mm,
105 pgd_t *pgd, pud_t *pud)
106{
107 pgd_val(*pgd) = _REGION2_ENTRY | __pa(pud);
108}
109
110static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgd, pud_t *pud)
111{
112 pgd_populate_kernel(mm, pgd, pud);
113 if (mm->context.noexec) {
114 pgd = get_shadow_table(pgd);
115 pud = get_shadow_table(pud);
116 pgd_populate_kernel(mm, pgd, pud);
117 }
118}
119
120static inline void pud_populate_kernel(struct mm_struct *mm,
121 pud_t *pud, pmd_t *pmd)
122{
123 pud_val(*pud) = _REGION3_ENTRY | __pa(pmd);
124}
125
126static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
127{
128 pud_populate_kernel(mm, pud, pmd);
129 if (mm->context.noexec) {
130 pud = get_shadow_table(pud);
131 pmd = get_shadow_table(pmd);
132 pud_populate_kernel(mm, pud, pmd);
133 }
134}
135
136#endif /* __s390x__ */
137
138static inline pgd_t *pgd_alloc(struct mm_struct *mm)
139{
140 INIT_LIST_HEAD(&mm->context.crst_list);
141 INIT_LIST_HEAD(&mm->context.pgtable_list);
142 return (pgd_t *) crst_table_alloc(mm, s390_noexec);
143}
144#define pgd_free(mm, pgd) crst_table_free(mm, (unsigned long *) pgd)
145
146static inline void pmd_populate_kernel(struct mm_struct *mm,
147 pmd_t *pmd, pte_t *pte)
148{
149 pmd_val(*pmd) = _SEGMENT_ENTRY + __pa(pte);
150}
151
152static inline void pmd_populate(struct mm_struct *mm,
153 pmd_t *pmd, pgtable_t pte)
154{
155 pmd_populate_kernel(mm, pmd, pte);
156 if (mm->context.noexec) {
157 pmd = get_shadow_table(pmd);
158 pmd_populate_kernel(mm, pmd, pte + PTRS_PER_PTE);
159 }
160}
161
162#define pmd_pgtable(pmd) \
163 (pgtable_t)(pmd_val(pmd) & -sizeof(pte_t)*PTRS_PER_PTE)
164
165/*
166 * page table entry allocation/free routines.
167 */
168#define pte_alloc_one_kernel(mm, vmaddr) ((pte_t *) page_table_alloc(mm))
169#define pte_alloc_one(mm, vmaddr) ((pte_t *) page_table_alloc(mm))
170
171#define pte_free_kernel(mm, pte) page_table_free(mm, (unsigned long *) pte)
172#define pte_free(mm, pte) page_table_free(mm, (unsigned long *) pte)
173
174#endif /* _S390_PGALLOC_H */
diff --git a/include/asm-s390/pgtable.h b/include/asm-s390/pgtable.h
deleted file mode 100644
index 0bdb704ae05..00000000000
--- a/include/asm-s390/pgtable.h
+++ /dev/null
@@ -1,1093 +0,0 @@
1/*
2 * include/asm-s390/pgtable.h
3 *
4 * S390 version
5 * Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Hartmut Penner (hp@de.ibm.com)
7 * Ulrich Weigand (weigand@de.ibm.com)
8 * Martin Schwidefsky (schwidefsky@de.ibm.com)
9 *
10 * Derived from "include/asm-i386/pgtable.h"
11 */
12
13#ifndef _ASM_S390_PGTABLE_H
14#define _ASM_S390_PGTABLE_H
15
16/*
17 * The Linux memory management assumes a three-level page table setup. For
18 * s390 31 bit we "fold" the mid level into the top-level page table, so
19 * that we physically have the same two-level page table as the s390 mmu
20 * expects in 31 bit mode. For s390 64 bit we use three of the five levels
21 * the hardware provides (region first and region second tables are not
22 * used).
23 *
24 * The "pgd_xxx()" functions are trivial for a folded two-level
25 * setup: the pgd is never bad, and a pmd always exists (as it's folded
26 * into the pgd entry)
27 *
28 * This file contains the functions and defines necessary to modify and use
29 * the S390 page table tree.
30 */
31#ifndef __ASSEMBLY__
32#include <linux/sched.h>
33#include <linux/mm_types.h>
34#include <asm/bitops.h>
35#include <asm/bug.h>
36#include <asm/processor.h>
37
38extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096)));
39extern void paging_init(void);
40extern void vmem_map_init(void);
41
42/*
43 * The S390 doesn't have any external MMU info: the kernel page
44 * tables contain all the necessary information.
45 */
46#define update_mmu_cache(vma, address, pte) do { } while (0)
47
48/*
49 * ZERO_PAGE is a global shared page that is always zero: used
50 * for zero-mapped memory areas etc..
51 */
52extern char empty_zero_page[PAGE_SIZE];
53#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
54#endif /* !__ASSEMBLY__ */
55
56/*
57 * PMD_SHIFT determines the size of the area a second-level page
58 * table can map
59 * PGDIR_SHIFT determines what a third-level page table entry can map
60 */
61#ifndef __s390x__
62# define PMD_SHIFT 20
63# define PUD_SHIFT 20
64# define PGDIR_SHIFT 20
65#else /* __s390x__ */
66# define PMD_SHIFT 20
67# define PUD_SHIFT 31
68# define PGDIR_SHIFT 42
69#endif /* __s390x__ */
70
71#define PMD_SIZE (1UL << PMD_SHIFT)
72#define PMD_MASK (~(PMD_SIZE-1))
73#define PUD_SIZE (1UL << PUD_SHIFT)
74#define PUD_MASK (~(PUD_SIZE-1))
75#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
76#define PGDIR_MASK (~(PGDIR_SIZE-1))
77
78/*
79 * entries per page directory level: the S390 is two-level, so
80 * we don't really have any PMD directory physically.
81 * for S390 segment-table entries are combined to one PGD
82 * that leads to 1024 pte per pgd
83 */
84#define PTRS_PER_PTE 256
85#ifndef __s390x__
86#define PTRS_PER_PMD 1
87#define PTRS_PER_PUD 1
88#else /* __s390x__ */
89#define PTRS_PER_PMD 2048
90#define PTRS_PER_PUD 2048
91#endif /* __s390x__ */
92#define PTRS_PER_PGD 2048
93
94#define FIRST_USER_ADDRESS 0
95
96#define pte_ERROR(e) \
97 printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e))
98#define pmd_ERROR(e) \
99 printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e))
100#define pud_ERROR(e) \
101 printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e))
102#define pgd_ERROR(e) \
103 printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e))
104
105#ifndef __ASSEMBLY__
106/*
107 * The vmalloc area will always be on the topmost area of the kernel
108 * mapping. We reserve 96MB (31bit) / 1GB (64bit) for vmalloc,
109 * which should be enough for any sane case.
110 * By putting vmalloc at the top, we maximise the gap between physical
111 * memory and vmalloc to catch misplaced memory accesses. As a side
112 * effect, this also makes sure that 64 bit module code cannot be used
113 * as system call address.
114 */
115#ifndef __s390x__
116#define VMALLOC_START 0x78000000UL
117#define VMALLOC_END 0x7e000000UL
118#define VMEM_MAP_END 0x80000000UL
119#else /* __s390x__ */
120#define VMALLOC_START 0x3e000000000UL
121#define VMALLOC_END 0x3e040000000UL
122#define VMEM_MAP_END 0x40000000000UL
123#endif /* __s390x__ */
124
125/*
126 * VMEM_MAX_PHYS is the highest physical address that can be added to the 1:1
127 * mapping. This needs to be calculated at compile time since the size of the
128 * VMEM_MAP is static but the size of struct page can change.
129 */
130#define VMEM_MAX_PAGES ((VMEM_MAP_END - VMALLOC_END) / sizeof(struct page))
131#define VMEM_MAX_PFN min(VMALLOC_START >> PAGE_SHIFT, VMEM_MAX_PAGES)
132#define VMEM_MAX_PHYS ((VMEM_MAX_PFN << PAGE_SHIFT) & ~((16 << 20) - 1))
133#define vmemmap ((struct page *) VMALLOC_END)
134
135/*
136 * A 31 bit pagetable entry of S390 has following format:
137 * | PFRA | | OS |
138 * 0 0IP0
139 * 00000000001111111111222222222233
140 * 01234567890123456789012345678901
141 *
142 * I Page-Invalid Bit: Page is not available for address-translation
143 * P Page-Protection Bit: Store access not possible for page
144 *
145 * A 31 bit segmenttable entry of S390 has following format:
146 * | P-table origin | |PTL
147 * 0 IC
148 * 00000000001111111111222222222233
149 * 01234567890123456789012345678901
150 *
151 * I Segment-Invalid Bit: Segment is not available for address-translation
152 * C Common-Segment Bit: Segment is not private (PoP 3-30)
153 * PTL Page-Table-Length: Page-table length (PTL+1*16 entries -> up to 256)
154 *
155 * The 31 bit segmenttable origin of S390 has following format:
156 *
157 * |S-table origin | | STL |
158 * X **GPS
159 * 00000000001111111111222222222233
160 * 01234567890123456789012345678901
161 *
162 * X Space-Switch event:
163 * G Segment-Invalid Bit: *
164 * P Private-Space Bit: Segment is not private (PoP 3-30)
165 * S Storage-Alteration:
166 * STL Segment-Table-Length: Segment-table length (STL+1*16 entries -> up to 2048)
167 *
168 * A 64 bit pagetable entry of S390 has following format:
169 * | PFRA |0IP0| OS |
170 * 0000000000111111111122222222223333333333444444444455555555556666
171 * 0123456789012345678901234567890123456789012345678901234567890123
172 *
173 * I Page-Invalid Bit: Page is not available for address-translation
174 * P Page-Protection Bit: Store access not possible for page
175 *
176 * A 64 bit segmenttable entry of S390 has following format:
177 * | P-table origin | TT
178 * 0000000000111111111122222222223333333333444444444455555555556666
179 * 0123456789012345678901234567890123456789012345678901234567890123
180 *
181 * I Segment-Invalid Bit: Segment is not available for address-translation
182 * C Common-Segment Bit: Segment is not private (PoP 3-30)
183 * P Page-Protection Bit: Store access not possible for page
184 * TT Type 00
185 *
186 * A 64 bit region table entry of S390 has following format:
187 * | S-table origin | TF TTTL
188 * 0000000000111111111122222222223333333333444444444455555555556666
189 * 0123456789012345678901234567890123456789012345678901234567890123
190 *
191 * I Segment-Invalid Bit: Segment is not available for address-translation
192 * TT Type 01
193 * TF
194 * TL Table length
195 *
196 * The 64 bit regiontable origin of S390 has following format:
197 * | region table origon | DTTL
198 * 0000000000111111111122222222223333333333444444444455555555556666
199 * 0123456789012345678901234567890123456789012345678901234567890123
200 *
201 * X Space-Switch event:
202 * G Segment-Invalid Bit:
203 * P Private-Space Bit:
204 * S Storage-Alteration:
205 * R Real space
206 * TL Table-Length:
207 *
208 * A storage key has the following format:
209 * | ACC |F|R|C|0|
210 * 0 3 4 5 6 7
211 * ACC: access key
212 * F : fetch protection bit
213 * R : referenced bit
214 * C : changed bit
215 */
216
217/* Hardware bits in the page table entry */
218#define _PAGE_RO 0x200 /* HW read-only bit */
219#define _PAGE_INVALID 0x400 /* HW invalid bit */
220
221/* Software bits in the page table entry */
222#define _PAGE_SWT 0x001 /* SW pte type bit t */
223#define _PAGE_SWX 0x002 /* SW pte type bit x */
224#define _PAGE_SPECIAL 0x004 /* SW associated with special page */
225#define __HAVE_ARCH_PTE_SPECIAL
226
227/* Set of bits not changed in pte_modify */
228#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL)
229
230/* Six different types of pages. */
231#define _PAGE_TYPE_EMPTY 0x400
232#define _PAGE_TYPE_NONE 0x401
233#define _PAGE_TYPE_SWAP 0x403
234#define _PAGE_TYPE_FILE 0x601 /* bit 0x002 is used for offset !! */
235#define _PAGE_TYPE_RO 0x200
236#define _PAGE_TYPE_RW 0x000
237#define _PAGE_TYPE_EX_RO 0x202
238#define _PAGE_TYPE_EX_RW 0x002
239
240/*
241 * Only four types for huge pages, using the invalid bit and protection bit
242 * of a segment table entry.
243 */
244#define _HPAGE_TYPE_EMPTY 0x020 /* _SEGMENT_ENTRY_INV */
245#define _HPAGE_TYPE_NONE 0x220
246#define _HPAGE_TYPE_RO 0x200 /* _SEGMENT_ENTRY_RO */
247#define _HPAGE_TYPE_RW 0x000
248
249/*
250 * PTE type bits are rather complicated. handle_pte_fault uses pte_present,
251 * pte_none and pte_file to find out the pte type WITHOUT holding the page
252 * table lock. ptep_clear_flush on the other hand uses ptep_clear_flush to
253 * invalidate a given pte. ipte sets the hw invalid bit and clears all tlbs
254 * for the page. The page table entry is set to _PAGE_TYPE_EMPTY afterwards.
255 * This change is done while holding the lock, but the intermediate step
256 * of a previously valid pte with the hw invalid bit set can be observed by
257 * handle_pte_fault. That makes it necessary that all valid pte types with
258 * the hw invalid bit set must be distinguishable from the four pte types
259 * empty, none, swap and file.
260 *
261 * irxt ipte irxt
262 * _PAGE_TYPE_EMPTY 1000 -> 1000
263 * _PAGE_TYPE_NONE 1001 -> 1001
264 * _PAGE_TYPE_SWAP 1011 -> 1011
265 * _PAGE_TYPE_FILE 11?1 -> 11?1
266 * _PAGE_TYPE_RO 0100 -> 1100
267 * _PAGE_TYPE_RW 0000 -> 1000
268 * _PAGE_TYPE_EX_RO 0110 -> 1110
269 * _PAGE_TYPE_EX_RW 0010 -> 1010
270 *
271 * pte_none is true for bits combinations 1000, 1010, 1100, 1110
272 * pte_present is true for bits combinations 0000, 0010, 0100, 0110, 1001
273 * pte_file is true for bits combinations 1101, 1111
274 * swap pte is 1011 and 0001, 0011, 0101, 0111 are invalid.
275 */
276
277/* Page status table bits for virtualization */
278#define RCP_PCL_BIT 55
279#define RCP_HR_BIT 54
280#define RCP_HC_BIT 53
281#define RCP_GR_BIT 50
282#define RCP_GC_BIT 49
283
284#ifndef __s390x__
285
286/* Bits in the segment table address-space-control-element */
287#define _ASCE_SPACE_SWITCH 0x80000000UL /* space switch event */
288#define _ASCE_ORIGIN_MASK 0x7ffff000UL /* segment table origin */
289#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
290#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
291#define _ASCE_TABLE_LENGTH 0x7f /* 128 x 64 entries = 8k */
292
293/* Bits in the segment table entry */
294#define _SEGMENT_ENTRY_ORIGIN 0x7fffffc0UL /* page table origin */
295#define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
296#define _SEGMENT_ENTRY_COMMON 0x10 /* common segment bit */
297#define _SEGMENT_ENTRY_PTL 0x0f /* page table length */
298
299#define _SEGMENT_ENTRY (_SEGMENT_ENTRY_PTL)
300#define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INV)
301
302#else /* __s390x__ */
303
304/* Bits in the segment/region table address-space-control-element */
305#define _ASCE_ORIGIN ~0xfffUL/* segment table origin */
306#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
307#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
308#define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
309#define _ASCE_REAL_SPACE 0x20 /* real space control */
310#define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
311#define _ASCE_TYPE_REGION1 0x0c /* region first table type */
312#define _ASCE_TYPE_REGION2 0x08 /* region second table type */
313#define _ASCE_TYPE_REGION3 0x04 /* region third table type */
314#define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
315#define _ASCE_TABLE_LENGTH 0x03 /* region table length */
316
317/* Bits in the region table entry */
318#define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */
319#define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
320#define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
321#define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
322#define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
323#define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
324#define _REGION_ENTRY_LENGTH 0x03 /* region third length */
325
326#define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH)
327#define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INV)
328#define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH)
329#define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INV)
330#define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH)
331#define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INV)
332
333/* Bits in the segment table entry */
334#define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */
335#define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
336#define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
337
338#define _SEGMENT_ENTRY (0)
339#define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INV)
340
341#define _SEGMENT_ENTRY_LARGE 0x400 /* STE-format control, large page */
342#define _SEGMENT_ENTRY_CO 0x100 /* change-recording override */
343
344#endif /* __s390x__ */
345
346/*
347 * A user page table pointer has the space-switch-event bit, the
348 * private-space-control bit and the storage-alteration-event-control
349 * bit set. A kernel page table pointer doesn't need them.
350 */
351#define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \
352 _ASCE_ALT_EVENT)
353
354/* Bits int the storage key */
355#define _PAGE_CHANGED 0x02 /* HW changed bit */
356#define _PAGE_REFERENCED 0x04 /* HW referenced bit */
357
358/*
359 * Page protection definitions.
360 */
361#define PAGE_NONE __pgprot(_PAGE_TYPE_NONE)
362#define PAGE_RO __pgprot(_PAGE_TYPE_RO)
363#define PAGE_RW __pgprot(_PAGE_TYPE_RW)
364#define PAGE_EX_RO __pgprot(_PAGE_TYPE_EX_RO)
365#define PAGE_EX_RW __pgprot(_PAGE_TYPE_EX_RW)
366
367#define PAGE_KERNEL PAGE_RW
368#define PAGE_COPY PAGE_RO
369
370/*
371 * Dependent on the EXEC_PROTECT option s390 can do execute protection.
372 * Write permission always implies read permission. In theory with a
373 * primary/secondary page table execute only can be implemented but
374 * it would cost an additional bit in the pte to distinguish all the
375 * different pte types. To avoid that execute permission currently
376 * implies read permission as well.
377 */
378 /*xwr*/
379#define __P000 PAGE_NONE
380#define __P001 PAGE_RO
381#define __P010 PAGE_RO
382#define __P011 PAGE_RO
383#define __P100 PAGE_EX_RO
384#define __P101 PAGE_EX_RO
385#define __P110 PAGE_EX_RO
386#define __P111 PAGE_EX_RO
387
388#define __S000 PAGE_NONE
389#define __S001 PAGE_RO
390#define __S010 PAGE_RW
391#define __S011 PAGE_RW
392#define __S100 PAGE_EX_RO
393#define __S101 PAGE_EX_RO
394#define __S110 PAGE_EX_RW
395#define __S111 PAGE_EX_RW
396
397#ifndef __s390x__
398# define PxD_SHADOW_SHIFT 1
399#else /* __s390x__ */
400# define PxD_SHADOW_SHIFT 2
401#endif /* __s390x__ */
402
403static inline void *get_shadow_table(void *table)
404{
405 unsigned long addr, offset;
406 struct page *page;
407
408 addr = (unsigned long) table;
409 offset = addr & ((PAGE_SIZE << PxD_SHADOW_SHIFT) - 1);
410 page = virt_to_page((void *)(addr ^ offset));
411 return (void *)(addr_t)(page->index ? (page->index | offset) : 0UL);
412}
413
414/*
415 * Certain architectures need to do special things when PTEs
416 * within a page table are directly modified. Thus, the following
417 * hook is made available.
418 */
419static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
420 pte_t *ptep, pte_t entry)
421{
422 *ptep = entry;
423 if (mm->context.noexec) {
424 if (!(pte_val(entry) & _PAGE_INVALID) &&
425 (pte_val(entry) & _PAGE_SWX))
426 pte_val(entry) |= _PAGE_RO;
427 else
428 pte_val(entry) = _PAGE_TYPE_EMPTY;
429 ptep[PTRS_PER_PTE] = entry;
430 }
431}
432
433/*
434 * pgd/pmd/pte query functions
435 */
436#ifndef __s390x__
437
438static inline int pgd_present(pgd_t pgd) { return 1; }
439static inline int pgd_none(pgd_t pgd) { return 0; }
440static inline int pgd_bad(pgd_t pgd) { return 0; }
441
442static inline int pud_present(pud_t pud) { return 1; }
443static inline int pud_none(pud_t pud) { return 0; }
444static inline int pud_bad(pud_t pud) { return 0; }
445
446#else /* __s390x__ */
447
448static inline int pgd_present(pgd_t pgd)
449{
450 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2)
451 return 1;
452 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL;
453}
454
455static inline int pgd_none(pgd_t pgd)
456{
457 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2)
458 return 0;
459 return (pgd_val(pgd) & _REGION_ENTRY_INV) != 0UL;
460}
461
462static inline int pgd_bad(pgd_t pgd)
463{
464 /*
465 * With dynamic page table levels the pgd can be a region table
466 * entry or a segment table entry. Check for the bit that are
467 * invalid for either table entry.
468 */
469 unsigned long mask =
470 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV &
471 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH;
472 return (pgd_val(pgd) & mask) != 0;
473}
474
475static inline int pud_present(pud_t pud)
476{
477 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3)
478 return 1;
479 return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL;
480}
481
482static inline int pud_none(pud_t pud)
483{
484 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3)
485 return 0;
486 return (pud_val(pud) & _REGION_ENTRY_INV) != 0UL;
487}
488
489static inline int pud_bad(pud_t pud)
490{
491 /*
492 * With dynamic page table levels the pud can be a region table
493 * entry or a segment table entry. Check for the bit that are
494 * invalid for either table entry.
495 */
496 unsigned long mask =
497 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV &
498 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH;
499 return (pud_val(pud) & mask) != 0;
500}
501
502#endif /* __s390x__ */
503
504static inline int pmd_present(pmd_t pmd)
505{
506 return (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) != 0UL;
507}
508
509static inline int pmd_none(pmd_t pmd)
510{
511 return (pmd_val(pmd) & _SEGMENT_ENTRY_INV) != 0UL;
512}
513
514static inline int pmd_bad(pmd_t pmd)
515{
516 unsigned long mask = ~_SEGMENT_ENTRY_ORIGIN & ~_SEGMENT_ENTRY_INV;
517 return (pmd_val(pmd) & mask) != _SEGMENT_ENTRY;
518}
519
520static inline int pte_none(pte_t pte)
521{
522 return (pte_val(pte) & _PAGE_INVALID) && !(pte_val(pte) & _PAGE_SWT);
523}
524
525static inline int pte_present(pte_t pte)
526{
527 unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT | _PAGE_SWX;
528 return (pte_val(pte) & mask) == _PAGE_TYPE_NONE ||
529 (!(pte_val(pte) & _PAGE_INVALID) &&
530 !(pte_val(pte) & _PAGE_SWT));
531}
532
533static inline int pte_file(pte_t pte)
534{
535 unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT;
536 return (pte_val(pte) & mask) == _PAGE_TYPE_FILE;
537}
538
539static inline int pte_special(pte_t pte)
540{
541 return (pte_val(pte) & _PAGE_SPECIAL);
542}
543
544#define __HAVE_ARCH_PTE_SAME
545#define pte_same(a,b) (pte_val(a) == pte_val(b))
546
547static inline void rcp_lock(pte_t *ptep)
548{
549#ifdef CONFIG_PGSTE
550 unsigned long *pgste = (unsigned long *) (ptep + PTRS_PER_PTE);
551 preempt_disable();
552 while (test_and_set_bit(RCP_PCL_BIT, pgste))
553 ;
554#endif
555}
556
557static inline void rcp_unlock(pte_t *ptep)
558{
559#ifdef CONFIG_PGSTE
560 unsigned long *pgste = (unsigned long *) (ptep + PTRS_PER_PTE);
561 clear_bit(RCP_PCL_BIT, pgste);
562 preempt_enable();
563#endif
564}
565
566/* forward declaration for SetPageUptodate in page-flags.h*/
567static inline void page_clear_dirty(struct page *page);
568#include <linux/page-flags.h>
569
570static inline void ptep_rcp_copy(pte_t *ptep)
571{
572#ifdef CONFIG_PGSTE
573 struct page *page = virt_to_page(pte_val(*ptep));
574 unsigned int skey;
575 unsigned long *pgste = (unsigned long *) (ptep + PTRS_PER_PTE);
576
577 skey = page_get_storage_key(page_to_phys(page));
578 if (skey & _PAGE_CHANGED)
579 set_bit_simple(RCP_GC_BIT, pgste);
580 if (skey & _PAGE_REFERENCED)
581 set_bit_simple(RCP_GR_BIT, pgste);
582 if (test_and_clear_bit_simple(RCP_HC_BIT, pgste))
583 SetPageDirty(page);
584 if (test_and_clear_bit_simple(RCP_HR_BIT, pgste))
585 SetPageReferenced(page);
586#endif
587}
588
589/*
590 * query functions pte_write/pte_dirty/pte_young only work if
591 * pte_present() is true. Undefined behaviour if not..
592 */
593static inline int pte_write(pte_t pte)
594{
595 return (pte_val(pte) & _PAGE_RO) == 0;
596}
597
598static inline int pte_dirty(pte_t pte)
599{
600 /* A pte is neither clean nor dirty on s/390. The dirty bit
601 * is in the storage key. See page_test_and_clear_dirty for
602 * details.
603 */
604 return 0;
605}
606
607static inline int pte_young(pte_t pte)
608{
609 /* A pte is neither young nor old on s/390. The young bit
610 * is in the storage key. See page_test_and_clear_young for
611 * details.
612 */
613 return 0;
614}
615
616/*
617 * pgd/pmd/pte modification functions
618 */
619
620#ifndef __s390x__
621
622#define pgd_clear(pgd) do { } while (0)
623#define pud_clear(pud) do { } while (0)
624
625#else /* __s390x__ */
626
627static inline void pgd_clear_kernel(pgd_t * pgd)
628{
629 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
630 pgd_val(*pgd) = _REGION2_ENTRY_EMPTY;
631}
632
633static inline void pgd_clear(pgd_t * pgd)
634{
635 pgd_t *shadow = get_shadow_table(pgd);
636
637 pgd_clear_kernel(pgd);
638 if (shadow)
639 pgd_clear_kernel(shadow);
640}
641
642static inline void pud_clear_kernel(pud_t *pud)
643{
644 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
645 pud_val(*pud) = _REGION3_ENTRY_EMPTY;
646}
647
648static inline void pud_clear(pud_t *pud)
649{
650 pud_t *shadow = get_shadow_table(pud);
651
652 pud_clear_kernel(pud);
653 if (shadow)
654 pud_clear_kernel(shadow);
655}
656
657#endif /* __s390x__ */
658
659static inline void pmd_clear_kernel(pmd_t * pmdp)
660{
661 pmd_val(*pmdp) = _SEGMENT_ENTRY_EMPTY;
662}
663
664static inline void pmd_clear(pmd_t *pmd)
665{
666 pmd_t *shadow = get_shadow_table(pmd);
667
668 pmd_clear_kernel(pmd);
669 if (shadow)
670 pmd_clear_kernel(shadow);
671}
672
673static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
674{
675 if (mm->context.pgstes)
676 ptep_rcp_copy(ptep);
677 pte_val(*ptep) = _PAGE_TYPE_EMPTY;
678 if (mm->context.noexec)
679 pte_val(ptep[PTRS_PER_PTE]) = _PAGE_TYPE_EMPTY;
680}
681
682/*
683 * The following pte modification functions only work if
684 * pte_present() is true. Undefined behaviour if not..
685 */
686static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
687{
688 pte_val(pte) &= _PAGE_CHG_MASK;
689 pte_val(pte) |= pgprot_val(newprot);
690 return pte;
691}
692
693static inline pte_t pte_wrprotect(pte_t pte)
694{
695 /* Do not clobber _PAGE_TYPE_NONE pages! */
696 if (!(pte_val(pte) & _PAGE_INVALID))
697 pte_val(pte) |= _PAGE_RO;
698 return pte;
699}
700
701static inline pte_t pte_mkwrite(pte_t pte)
702{
703 pte_val(pte) &= ~_PAGE_RO;
704 return pte;
705}
706
707static inline pte_t pte_mkclean(pte_t pte)
708{
709 /* The only user of pte_mkclean is the fork() code.
710 We must *not* clear the *physical* page dirty bit
711 just because fork() wants to clear the dirty bit in
712 *one* of the page's mappings. So we just do nothing. */
713 return pte;
714}
715
716static inline pte_t pte_mkdirty(pte_t pte)
717{
718 /* We do not explicitly set the dirty bit because the
719 * sske instruction is slow. It is faster to let the
720 * next instruction set the dirty bit.
721 */
722 return pte;
723}
724
725static inline pte_t pte_mkold(pte_t pte)
726{
727 /* S/390 doesn't keep its dirty/referenced bit in the pte.
728 * There is no point in clearing the real referenced bit.
729 */
730 return pte;
731}
732
733static inline pte_t pte_mkyoung(pte_t pte)
734{
735 /* S/390 doesn't keep its dirty/referenced bit in the pte.
736 * There is no point in setting the real referenced bit.
737 */
738 return pte;
739}
740
741static inline pte_t pte_mkspecial(pte_t pte)
742{
743 pte_val(pte) |= _PAGE_SPECIAL;
744 return pte;
745}
746
747#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
748static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
749 unsigned long addr, pte_t *ptep)
750{
751#ifdef CONFIG_PGSTE
752 unsigned long physpage;
753 int young;
754 unsigned long *pgste;
755
756 if (!vma->vm_mm->context.pgstes)
757 return 0;
758 physpage = pte_val(*ptep) & PAGE_MASK;
759 pgste = (unsigned long *) (ptep + PTRS_PER_PTE);
760
761 young = ((page_get_storage_key(physpage) & _PAGE_REFERENCED) != 0);
762 rcp_lock(ptep);
763 if (young)
764 set_bit_simple(RCP_GR_BIT, pgste);
765 young |= test_and_clear_bit_simple(RCP_HR_BIT, pgste);
766 rcp_unlock(ptep);
767 return young;
768#endif
769 return 0;
770}
771
772#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
773static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
774 unsigned long address, pte_t *ptep)
775{
776 /* No need to flush TLB
777 * On s390 reference bits are in storage key and never in TLB
778 * With virtualization we handle the reference bit, without we
779 * we can simply return */
780#ifdef CONFIG_PGSTE
781 return ptep_test_and_clear_young(vma, address, ptep);
782#endif
783 return 0;
784}
785
786static inline void __ptep_ipte(unsigned long address, pte_t *ptep)
787{
788 if (!(pte_val(*ptep) & _PAGE_INVALID)) {
789#ifndef __s390x__
790 /* pto must point to the start of the segment table */
791 pte_t *pto = (pte_t *) (((unsigned long) ptep) & 0x7ffffc00);
792#else
793 /* ipte in zarch mode can do the math */
794 pte_t *pto = ptep;
795#endif
796 asm volatile(
797 " ipte %2,%3"
798 : "=m" (*ptep) : "m" (*ptep),
799 "a" (pto), "a" (address));
800 }
801}
802
803static inline void ptep_invalidate(struct mm_struct *mm,
804 unsigned long address, pte_t *ptep)
805{
806 if (mm->context.pgstes) {
807 rcp_lock(ptep);
808 __ptep_ipte(address, ptep);
809 ptep_rcp_copy(ptep);
810 pte_val(*ptep) = _PAGE_TYPE_EMPTY;
811 rcp_unlock(ptep);
812 return;
813 }
814 __ptep_ipte(address, ptep);
815 pte_val(*ptep) = _PAGE_TYPE_EMPTY;
816 if (mm->context.noexec) {
817 __ptep_ipte(address, ptep + PTRS_PER_PTE);
818 pte_val(*(ptep + PTRS_PER_PTE)) = _PAGE_TYPE_EMPTY;
819 }
820}
821
822/*
823 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush
824 * both clear the TLB for the unmapped pte. The reason is that
825 * ptep_get_and_clear is used in common code (e.g. change_pte_range)
826 * to modify an active pte. The sequence is
827 * 1) ptep_get_and_clear
828 * 2) set_pte_at
829 * 3) flush_tlb_range
830 * On s390 the tlb needs to get flushed with the modification of the pte
831 * if the pte is active. The only way how this can be implemented is to
832 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range
833 * is a nop.
834 */
835#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
836#define ptep_get_and_clear(__mm, __address, __ptep) \
837({ \
838 pte_t __pte = *(__ptep); \
839 if (atomic_read(&(__mm)->mm_users) > 1 || \
840 (__mm) != current->active_mm) \
841 ptep_invalidate(__mm, __address, __ptep); \
842 else \
843 pte_clear((__mm), (__address), (__ptep)); \
844 __pte; \
845})
846
847#define __HAVE_ARCH_PTEP_CLEAR_FLUSH
848static inline pte_t ptep_clear_flush(struct vm_area_struct *vma,
849 unsigned long address, pte_t *ptep)
850{
851 pte_t pte = *ptep;
852 ptep_invalidate(vma->vm_mm, address, ptep);
853 return pte;
854}
855
856/*
857 * The batched pte unmap code uses ptep_get_and_clear_full to clear the
858 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all
859 * tlbs of an mm if it can guarantee that the ptes of the mm_struct
860 * cannot be accessed while the batched unmap is running. In this case
861 * full==1 and a simple pte_clear is enough. See tlb.h.
862 */
863#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
864static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
865 unsigned long addr,
866 pte_t *ptep, int full)
867{
868 pte_t pte = *ptep;
869
870 if (full)
871 pte_clear(mm, addr, ptep);
872 else
873 ptep_invalidate(mm, addr, ptep);
874 return pte;
875}
876
877#define __HAVE_ARCH_PTEP_SET_WRPROTECT
878#define ptep_set_wrprotect(__mm, __addr, __ptep) \
879({ \
880 pte_t __pte = *(__ptep); \
881 if (pte_write(__pte)) { \
882 if (atomic_read(&(__mm)->mm_users) > 1 || \
883 (__mm) != current->active_mm) \
884 ptep_invalidate(__mm, __addr, __ptep); \
885 set_pte_at(__mm, __addr, __ptep, pte_wrprotect(__pte)); \
886 } \
887})
888
889#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
890#define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __dirty) \
891({ \
892 int __changed = !pte_same(*(__ptep), __entry); \
893 if (__changed) { \
894 ptep_invalidate((__vma)->vm_mm, __addr, __ptep); \
895 set_pte_at((__vma)->vm_mm, __addr, __ptep, __entry); \
896 } \
897 __changed; \
898})
899
900/*
901 * Test and clear dirty bit in storage key.
902 * We can't clear the changed bit atomically. This is a potential
903 * race against modification of the referenced bit. This function
904 * should therefore only be called if it is not mapped in any
905 * address space.
906 */
907#define __HAVE_ARCH_PAGE_TEST_DIRTY
908static inline int page_test_dirty(struct page *page)
909{
910 return (page_get_storage_key(page_to_phys(page)) & _PAGE_CHANGED) != 0;
911}
912
913#define __HAVE_ARCH_PAGE_CLEAR_DIRTY
914static inline void page_clear_dirty(struct page *page)
915{
916 page_set_storage_key(page_to_phys(page), PAGE_DEFAULT_KEY);
917}
918
919/*
920 * Test and clear referenced bit in storage key.
921 */
922#define __HAVE_ARCH_PAGE_TEST_AND_CLEAR_YOUNG
923static inline int page_test_and_clear_young(struct page *page)
924{
925 unsigned long physpage = page_to_phys(page);
926 int ccode;
927
928 asm volatile(
929 " rrbe 0,%1\n"
930 " ipm %0\n"
931 " srl %0,28\n"
932 : "=d" (ccode) : "a" (physpage) : "cc" );
933 return ccode & 2;
934}
935
936/*
937 * Conversion functions: convert a page and protection to a page entry,
938 * and a page entry and page directory to the page they refer to.
939 */
940static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
941{
942 pte_t __pte;
943 pte_val(__pte) = physpage + pgprot_val(pgprot);
944 return __pte;
945}
946
947static inline pte_t mk_pte(struct page *page, pgprot_t pgprot)
948{
949 unsigned long physpage = page_to_phys(page);
950
951 return mk_pte_phys(physpage, pgprot);
952}
953
954#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
955#define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
956#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
957#define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
958
959#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
960#define pgd_offset_k(address) pgd_offset(&init_mm, address)
961
962#ifndef __s390x__
963
964#define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
965#define pud_deref(pmd) ({ BUG(); 0UL; })
966#define pgd_deref(pmd) ({ BUG(); 0UL; })
967
968#define pud_offset(pgd, address) ((pud_t *) pgd)
969#define pmd_offset(pud, address) ((pmd_t *) pud + pmd_index(address))
970
971#else /* __s390x__ */
972
973#define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
974#define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN)
975#define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN)
976
977static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address)
978{
979 pud_t *pud = (pud_t *) pgd;
980 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
981 pud = (pud_t *) pgd_deref(*pgd);
982 return pud + pud_index(address);
983}
984
985static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address)
986{
987 pmd_t *pmd = (pmd_t *) pud;
988 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
989 pmd = (pmd_t *) pud_deref(*pud);
990 return pmd + pmd_index(address);
991}
992
993#endif /* __s390x__ */
994
995#define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot))
996#define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)
997#define pte_page(x) pfn_to_page(pte_pfn(x))
998
999#define pmd_page(pmd) pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)
1000
1001/* Find an entry in the lowest level page table.. */
1002#define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr))
1003#define pte_offset_kernel(pmd, address) pte_offset(pmd,address)
1004#define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address)
1005#define pte_offset_map_nested(pmd, address) pte_offset_kernel(pmd, address)
1006#define pte_unmap(pte) do { } while (0)
1007#define pte_unmap_nested(pte) do { } while (0)
1008
1009/*
1010 * 31 bit swap entry format:
1011 * A page-table entry has some bits we have to treat in a special way.
1012 * Bits 0, 20 and bit 23 have to be zero, otherwise an specification
1013 * exception will occur instead of a page translation exception. The
1014 * specifiation exception has the bad habit not to store necessary
1015 * information in the lowcore.
1016 * Bit 21 and bit 22 are the page invalid bit and the page protection
1017 * bit. We set both to indicate a swapped page.
1018 * Bit 30 and 31 are used to distinguish the different page types. For
1019 * a swapped page these bits need to be zero.
1020 * This leaves the bits 1-19 and bits 24-29 to store type and offset.
1021 * We use the 5 bits from 25-29 for the type and the 20 bits from 1-19
1022 * plus 24 for the offset.
1023 * 0| offset |0110|o|type |00|
1024 * 0 0000000001111111111 2222 2 22222 33
1025 * 0 1234567890123456789 0123 4 56789 01
1026 *
1027 * 64 bit swap entry format:
1028 * A page-table entry has some bits we have to treat in a special way.
1029 * Bits 52 and bit 55 have to be zero, otherwise an specification
1030 * exception will occur instead of a page translation exception. The
1031 * specifiation exception has the bad habit not to store necessary
1032 * information in the lowcore.
1033 * Bit 53 and bit 54 are the page invalid bit and the page protection
1034 * bit. We set both to indicate a swapped page.
1035 * Bit 62 and 63 are used to distinguish the different page types. For
1036 * a swapped page these bits need to be zero.
1037 * This leaves the bits 0-51 and bits 56-61 to store type and offset.
1038 * We use the 5 bits from 57-61 for the type and the 53 bits from 0-51
1039 * plus 56 for the offset.
1040 * | offset |0110|o|type |00|
1041 * 0000000000111111111122222222223333333333444444444455 5555 5 55566 66
1042 * 0123456789012345678901234567890123456789012345678901 2345 6 78901 23
1043 */
1044#ifndef __s390x__
1045#define __SWP_OFFSET_MASK (~0UL >> 12)
1046#else
1047#define __SWP_OFFSET_MASK (~0UL >> 11)
1048#endif
1049static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
1050{
1051 pte_t pte;
1052 offset &= __SWP_OFFSET_MASK;
1053 pte_val(pte) = _PAGE_TYPE_SWAP | ((type & 0x1f) << 2) |
1054 ((offset & 1UL) << 7) | ((offset & ~1UL) << 11);
1055 return pte;
1056}
1057
1058#define __swp_type(entry) (((entry).val >> 2) & 0x1f)
1059#define __swp_offset(entry) (((entry).val >> 11) | (((entry).val >> 7) & 1))
1060#define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) })
1061
1062#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
1063#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
1064
1065#ifndef __s390x__
1066# define PTE_FILE_MAX_BITS 26
1067#else /* __s390x__ */
1068# define PTE_FILE_MAX_BITS 59
1069#endif /* __s390x__ */
1070
1071#define pte_to_pgoff(__pte) \
1072 ((((__pte).pte >> 12) << 7) + (((__pte).pte >> 1) & 0x7f))
1073
1074#define pgoff_to_pte(__off) \
1075 ((pte_t) { ((((__off) & 0x7f) << 1) + (((__off) >> 7) << 12)) \
1076 | _PAGE_TYPE_FILE })
1077
1078#endif /* !__ASSEMBLY__ */
1079
1080#define kern_addr_valid(addr) (1)
1081
1082extern int vmem_add_mapping(unsigned long start, unsigned long size);
1083extern int vmem_remove_mapping(unsigned long start, unsigned long size);
1084extern int s390_enable_sie(void);
1085
1086/*
1087 * No page table caches to initialise
1088 */
1089#define pgtable_cache_init() do { } while (0)
1090
1091#include <asm-generic/pgtable.h>
1092
1093#endif /* _S390_PAGE_H */
diff --git a/include/asm-s390/poll.h b/include/asm-s390/poll.h
deleted file mode 100644
index c98509d3149..00000000000
--- a/include/asm-s390/poll.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/poll.h>
diff --git a/include/asm-s390/posix_types.h b/include/asm-s390/posix_types.h
deleted file mode 100644
index 397d93fba3a..00000000000
--- a/include/asm-s390/posix_types.h
+++ /dev/null
@@ -1,111 +0,0 @@
1/*
2 * include/asm-s390/posix_types.h
3 *
4 * S390 version
5 *
6 * Derived from "include/asm-i386/posix_types.h"
7 */
8
9#ifndef __ARCH_S390_POSIX_TYPES_H
10#define __ARCH_S390_POSIX_TYPES_H
11
12/*
13 * This file is generally used by user-level software, so you need to
14 * be a little careful about namespace pollution etc. Also, we cannot
15 * assume GCC is being used.
16 */
17
18typedef long __kernel_off_t;
19typedef int __kernel_pid_t;
20typedef unsigned long __kernel_size_t;
21typedef long __kernel_time_t;
22typedef long __kernel_suseconds_t;
23typedef long __kernel_clock_t;
24typedef int __kernel_timer_t;
25typedef int __kernel_clockid_t;
26typedef int __kernel_daddr_t;
27typedef char * __kernel_caddr_t;
28typedef unsigned short __kernel_uid16_t;
29typedef unsigned short __kernel_gid16_t;
30
31#ifdef __GNUC__
32typedef long long __kernel_loff_t;
33#endif
34
35#ifndef __s390x__
36
37typedef unsigned long __kernel_ino_t;
38typedef unsigned short __kernel_mode_t;
39typedef unsigned short __kernel_nlink_t;
40typedef unsigned short __kernel_ipc_pid_t;
41typedef unsigned short __kernel_uid_t;
42typedef unsigned short __kernel_gid_t;
43typedef int __kernel_ssize_t;
44typedef int __kernel_ptrdiff_t;
45typedef unsigned int __kernel_uid32_t;
46typedef unsigned int __kernel_gid32_t;
47typedef unsigned short __kernel_old_uid_t;
48typedef unsigned short __kernel_old_gid_t;
49typedef unsigned short __kernel_old_dev_t;
50
51#else /* __s390x__ */
52
53typedef unsigned int __kernel_ino_t;
54typedef unsigned int __kernel_mode_t;
55typedef unsigned int __kernel_nlink_t;
56typedef int __kernel_ipc_pid_t;
57typedef unsigned int __kernel_uid_t;
58typedef unsigned int __kernel_gid_t;
59typedef long __kernel_ssize_t;
60typedef long __kernel_ptrdiff_t;
61typedef unsigned long __kernel_sigset_t; /* at least 32 bits */
62typedef __kernel_uid_t __kernel_old_uid_t;
63typedef __kernel_gid_t __kernel_old_gid_t;
64typedef __kernel_uid_t __kernel_uid32_t;
65typedef __kernel_gid_t __kernel_gid32_t;
66typedef unsigned short __kernel_old_dev_t;
67
68#endif /* __s390x__ */
69
70typedef struct {
71#if defined(__KERNEL__) || defined(__USE_ALL)
72 int val[2];
73#else /* !defined(__KERNEL__) && !defined(__USE_ALL)*/
74 int __val[2];
75#endif /* !defined(__KERNEL__) && !defined(__USE_ALL)*/
76} __kernel_fsid_t;
77
78
79#ifdef __KERNEL__
80
81#undef __FD_SET
82static inline void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
83{
84 unsigned long _tmp = fd / __NFDBITS;
85 unsigned long _rem = fd % __NFDBITS;
86 fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
87}
88
89#undef __FD_CLR
90static inline void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
91{
92 unsigned long _tmp = fd / __NFDBITS;
93 unsigned long _rem = fd % __NFDBITS;
94 fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
95}
96
97#undef __FD_ISSET
98static inline int __FD_ISSET(unsigned long fd, const __kernel_fd_set *fdsetp)
99{
100 unsigned long _tmp = fd / __NFDBITS;
101 unsigned long _rem = fd % __NFDBITS;
102 return (fdsetp->fds_bits[_tmp] & (1UL<<_rem)) != 0;
103}
104
105#undef __FD_ZERO
106#define __FD_ZERO(fdsetp) \
107 ((void) memset ((void *) (fdsetp), 0, sizeof (__kernel_fd_set)))
108
109#endif /* __KERNEL__ */
110
111#endif
diff --git a/include/asm-s390/processor.h b/include/asm-s390/processor.h
deleted file mode 100644
index 4af80af2a88..00000000000
--- a/include/asm-s390/processor.h
+++ /dev/null
@@ -1,360 +0,0 @@
1/*
2 * include/asm-s390/processor.h
3 *
4 * S390 version
5 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Hartmut Penner (hp@de.ibm.com),
7 * Martin Schwidefsky (schwidefsky@de.ibm.com)
8 *
9 * Derived from "include/asm-i386/processor.h"
10 * Copyright (C) 1994, Linus Torvalds
11 */
12
13#ifndef __ASM_S390_PROCESSOR_H
14#define __ASM_S390_PROCESSOR_H
15
16#include <asm/ptrace.h>
17
18#ifdef __KERNEL__
19/*
20 * Default implementation of macro that returns current
21 * instruction pointer ("program counter").
22 */
23#define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })
24
25/*
26 * CPU type and hardware bug flags. Kept separately for each CPU.
27 * Members of this structure are referenced in head.S, so think twice
28 * before touching them. [mj]
29 */
30
31typedef struct
32{
33 unsigned int version : 8;
34 unsigned int ident : 24;
35 unsigned int machine : 16;
36 unsigned int unused : 16;
37} __attribute__ ((packed)) cpuid_t;
38
39static inline void get_cpu_id(cpuid_t *ptr)
40{
41 asm volatile("stidp 0(%1)" : "=m" (*ptr) : "a" (ptr));
42}
43
44struct cpuinfo_S390
45{
46 cpuid_t cpu_id;
47 __u16 cpu_addr;
48 __u16 cpu_nr;
49 unsigned long loops_per_jiffy;
50 unsigned long *pgd_quick;
51#ifdef __s390x__
52 unsigned long *pmd_quick;
53#endif /* __s390x__ */
54 unsigned long *pte_quick;
55 unsigned long pgtable_cache_sz;
56};
57
58extern void s390_adjust_jiffies(void);
59extern void print_cpu_info(struct cpuinfo_S390 *);
60extern int get_cpu_capability(unsigned int *);
61
62/*
63 * User space process size: 2GB for 31 bit, 4TB for 64 bit.
64 */
65#ifndef __s390x__
66
67#define TASK_SIZE (1UL << 31)
68#define TASK_UNMAPPED_BASE (1UL << 30)
69
70#else /* __s390x__ */
71
72#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk,TIF_31BIT) ? \
73 (1UL << 31) : (1UL << 53))
74#define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \
75 (1UL << 30) : (1UL << 41))
76#define TASK_SIZE TASK_SIZE_OF(current)
77
78#endif /* __s390x__ */
79
80#ifdef __KERNEL__
81
82#ifndef __s390x__
83#define STACK_TOP (1UL << 31)
84#define STACK_TOP_MAX (1UL << 31)
85#else /* __s390x__ */
86#define STACK_TOP (1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
87#define STACK_TOP_MAX (1UL << 42)
88#endif /* __s390x__ */
89
90
91#endif
92
93#define HAVE_ARCH_PICK_MMAP_LAYOUT
94
95typedef struct {
96 __u32 ar4;
97} mm_segment_t;
98
99/*
100 * Thread structure
101 */
102struct thread_struct {
103 s390_fp_regs fp_regs;
104 unsigned int acrs[NUM_ACRS];
105 unsigned long ksp; /* kernel stack pointer */
106 mm_segment_t mm_segment;
107 unsigned long prot_addr; /* address of protection-excep. */
108 unsigned int trap_no;
109 per_struct per_info;
110 /* Used to give failing instruction back to user for ieee exceptions */
111 unsigned long ieee_instruction_pointer;
112 /* pfault_wait is used to block the process on a pfault event */
113 unsigned long pfault_wait;
114};
115
116typedef struct thread_struct thread_struct;
117
118/*
119 * Stack layout of a C stack frame.
120 */
121#ifndef __PACK_STACK
122struct stack_frame {
123 unsigned long back_chain;
124 unsigned long empty1[5];
125 unsigned long gprs[10];
126 unsigned int empty2[8];
127};
128#else
129struct stack_frame {
130 unsigned long empty1[5];
131 unsigned int empty2[8];
132 unsigned long gprs[10];
133 unsigned long back_chain;
134};
135#endif
136
137#define ARCH_MIN_TASKALIGN 8
138
139#define INIT_THREAD { \
140 .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \
141}
142
143/*
144 * Do necessary setup to start up a new thread.
145 */
146#define start_thread(regs, new_psw, new_stackp) do { \
147 set_fs(USER_DS); \
148 regs->psw.mask = psw_user_bits; \
149 regs->psw.addr = new_psw | PSW_ADDR_AMODE; \
150 regs->gprs[15] = new_stackp; \
151} while (0)
152
153#define start_thread31(regs, new_psw, new_stackp) do { \
154 set_fs(USER_DS); \
155 regs->psw.mask = psw_user32_bits; \
156 regs->psw.addr = new_psw | PSW_ADDR_AMODE; \
157 regs->gprs[15] = new_stackp; \
158 crst_table_downgrade(current->mm, 1UL << 31); \
159} while (0)
160
161/* Forward declaration, a strange C thing */
162struct task_struct;
163struct mm_struct;
164struct seq_file;
165
166/* Free all resources held by a thread. */
167extern void release_thread(struct task_struct *);
168extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
169
170/* Prepare to copy thread state - unlazy all lazy status */
171#define prepare_to_copy(tsk) do { } while (0)
172
173/*
174 * Return saved PC of a blocked thread.
175 */
176extern unsigned long thread_saved_pc(struct task_struct *t);
177
178/*
179 * Print register of task into buffer. Used in fs/proc/array.c.
180 */
181extern void task_show_regs(struct seq_file *m, struct task_struct *task);
182
183extern void show_code(struct pt_regs *regs);
184
185unsigned long get_wchan(struct task_struct *p);
186#define task_pt_regs(tsk) ((struct pt_regs *) \
187 (task_stack_page(tsk) + THREAD_SIZE) - 1)
188#define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr)
189#define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15])
190
191/*
192 * Give up the time slice of the virtual PU.
193 */
194static inline void cpu_relax(void)
195{
196 if (MACHINE_HAS_DIAG44)
197 asm volatile("diag 0,0,68");
198 barrier();
199}
200
201static inline void psw_set_key(unsigned int key)
202{
203 asm volatile("spka 0(%0)" : : "d" (key));
204}
205
206/*
207 * Set PSW to specified value.
208 */
209static inline void __load_psw(psw_t psw)
210{
211#ifndef __s390x__
212 asm volatile("lpsw 0(%0)" : : "a" (&psw), "m" (psw) : "cc");
213#else
214 asm volatile("lpswe 0(%0)" : : "a" (&psw), "m" (psw) : "cc");
215#endif
216}
217
218/*
219 * Set PSW mask to specified value, while leaving the
220 * PSW addr pointing to the next instruction.
221 */
222
223static inline void __load_psw_mask (unsigned long mask)
224{
225 unsigned long addr;
226 psw_t psw;
227
228 psw.mask = mask;
229
230#ifndef __s390x__
231 asm volatile(
232 " basr %0,0\n"
233 "0: ahi %0,1f-0b\n"
234 " st %0,4(%1)\n"
235 " lpsw 0(%1)\n"
236 "1:"
237 : "=&d" (addr) : "a" (&psw), "m" (psw) : "memory", "cc");
238#else /* __s390x__ */
239 asm volatile(
240 " larl %0,1f\n"
241 " stg %0,8(%1)\n"
242 " lpswe 0(%1)\n"
243 "1:"
244 : "=&d" (addr) : "a" (&psw), "m" (psw) : "memory", "cc");
245#endif /* __s390x__ */
246}
247
248/*
249 * Function to stop a processor until an interruption occurred
250 */
251static inline void enabled_wait(void)
252{
253 __load_psw_mask(PSW_BASE_BITS | PSW_MASK_IO | PSW_MASK_EXT |
254 PSW_MASK_MCHECK | PSW_MASK_WAIT | PSW_DEFAULT_KEY);
255}
256
257/*
258 * Function to drop a processor into disabled wait state
259 */
260
261static inline void disabled_wait(unsigned long code)
262{
263 unsigned long ctl_buf;
264 psw_t dw_psw;
265
266 dw_psw.mask = PSW_BASE_BITS | PSW_MASK_WAIT;
267 dw_psw.addr = code;
268 /*
269 * Store status and then load disabled wait psw,
270 * the processor is dead afterwards
271 */
272#ifndef __s390x__
273 asm volatile(
274 " stctl 0,0,0(%2)\n"
275 " ni 0(%2),0xef\n" /* switch off protection */
276 " lctl 0,0,0(%2)\n"
277 " stpt 0xd8\n" /* store timer */
278 " stckc 0xe0\n" /* store clock comparator */
279 " stpx 0x108\n" /* store prefix register */
280 " stam 0,15,0x120\n" /* store access registers */
281 " std 0,0x160\n" /* store f0 */
282 " std 2,0x168\n" /* store f2 */
283 " std 4,0x170\n" /* store f4 */
284 " std 6,0x178\n" /* store f6 */
285 " stm 0,15,0x180\n" /* store general registers */
286 " stctl 0,15,0x1c0\n" /* store control registers */
287 " oi 0x1c0,0x10\n" /* fake protection bit */
288 " lpsw 0(%1)"
289 : "=m" (ctl_buf)
290 : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc");
291#else /* __s390x__ */
292 asm volatile(
293 " stctg 0,0,0(%2)\n"
294 " ni 4(%2),0xef\n" /* switch off protection */
295 " lctlg 0,0,0(%2)\n"
296 " lghi 1,0x1000\n"
297 " stpt 0x328(1)\n" /* store timer */
298 " stckc 0x330(1)\n" /* store clock comparator */
299 " stpx 0x318(1)\n" /* store prefix register */
300 " stam 0,15,0x340(1)\n"/* store access registers */
301 " stfpc 0x31c(1)\n" /* store fpu control */
302 " std 0,0x200(1)\n" /* store f0 */
303 " std 1,0x208(1)\n" /* store f1 */
304 " std 2,0x210(1)\n" /* store f2 */
305 " std 3,0x218(1)\n" /* store f3 */
306 " std 4,0x220(1)\n" /* store f4 */
307 " std 5,0x228(1)\n" /* store f5 */
308 " std 6,0x230(1)\n" /* store f6 */
309 " std 7,0x238(1)\n" /* store f7 */
310 " std 8,0x240(1)\n" /* store f8 */
311 " std 9,0x248(1)\n" /* store f9 */
312 " std 10,0x250(1)\n" /* store f10 */
313 " std 11,0x258(1)\n" /* store f11 */
314 " std 12,0x260(1)\n" /* store f12 */
315 " std 13,0x268(1)\n" /* store f13 */
316 " std 14,0x270(1)\n" /* store f14 */
317 " std 15,0x278(1)\n" /* store f15 */
318 " stmg 0,15,0x280(1)\n"/* store general registers */
319 " stctg 0,15,0x380(1)\n"/* store control registers */
320 " oi 0x384(1),0x10\n"/* fake protection bit */
321 " lpswe 0(%1)"
322 : "=m" (ctl_buf)
323 : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0");
324#endif /* __s390x__ */
325}
326
327/*
328 * Basic Machine Check/Program Check Handler.
329 */
330
331extern void s390_base_mcck_handler(void);
332extern void s390_base_pgm_handler(void);
333extern void s390_base_ext_handler(void);
334
335extern void (*s390_base_mcck_handler_fn)(void);
336extern void (*s390_base_pgm_handler_fn)(void);
337extern void (*s390_base_ext_handler_fn)(void);
338
339#define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL
340
341#endif
342
343/*
344 * Helper macro for exception table entries
345 */
346#ifndef __s390x__
347#define EX_TABLE(_fault,_target) \
348 ".section __ex_table,\"a\"\n" \
349 " .align 4\n" \
350 " .long " #_fault "," #_target "\n" \
351 ".previous\n"
352#else
353#define EX_TABLE(_fault,_target) \
354 ".section __ex_table,\"a\"\n" \
355 " .align 8\n" \
356 " .quad " #_fault "," #_target "\n" \
357 ".previous\n"
358#endif
359
360#endif /* __ASM_S390_PROCESSOR_H */
diff --git a/include/asm-s390/ptrace.h b/include/asm-s390/ptrace.h
deleted file mode 100644
index af2c9ac28a0..00000000000
--- a/include/asm-s390/ptrace.h
+++ /dev/null
@@ -1,499 +0,0 @@
1/*
2 * include/asm-s390/ptrace.h
3 *
4 * S390 version
5 * Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
7 */
8
9#ifndef _S390_PTRACE_H
10#define _S390_PTRACE_H
11
12/*
13 * Offsets in the user_regs_struct. They are used for the ptrace
14 * system call and in entry.S
15 */
16#ifndef __s390x__
17
18#define PT_PSWMASK 0x00
19#define PT_PSWADDR 0x04
20#define PT_GPR0 0x08
21#define PT_GPR1 0x0C
22#define PT_GPR2 0x10
23#define PT_GPR3 0x14
24#define PT_GPR4 0x18
25#define PT_GPR5 0x1C
26#define PT_GPR6 0x20
27#define PT_GPR7 0x24
28#define PT_GPR8 0x28
29#define PT_GPR9 0x2C
30#define PT_GPR10 0x30
31#define PT_GPR11 0x34
32#define PT_GPR12 0x38
33#define PT_GPR13 0x3C
34#define PT_GPR14 0x40
35#define PT_GPR15 0x44
36#define PT_ACR0 0x48
37#define PT_ACR1 0x4C
38#define PT_ACR2 0x50
39#define PT_ACR3 0x54
40#define PT_ACR4 0x58
41#define PT_ACR5 0x5C
42#define PT_ACR6 0x60
43#define PT_ACR7 0x64
44#define PT_ACR8 0x68
45#define PT_ACR9 0x6C
46#define PT_ACR10 0x70
47#define PT_ACR11 0x74
48#define PT_ACR12 0x78
49#define PT_ACR13 0x7C
50#define PT_ACR14 0x80
51#define PT_ACR15 0x84
52#define PT_ORIGGPR2 0x88
53#define PT_FPC 0x90
54/*
55 * A nasty fact of life that the ptrace api
56 * only supports passing of longs.
57 */
58#define PT_FPR0_HI 0x98
59#define PT_FPR0_LO 0x9C
60#define PT_FPR1_HI 0xA0
61#define PT_FPR1_LO 0xA4
62#define PT_FPR2_HI 0xA8
63#define PT_FPR2_LO 0xAC
64#define PT_FPR3_HI 0xB0
65#define PT_FPR3_LO 0xB4
66#define PT_FPR4_HI 0xB8
67#define PT_FPR4_LO 0xBC
68#define PT_FPR5_HI 0xC0
69#define PT_FPR5_LO 0xC4
70#define PT_FPR6_HI 0xC8
71#define PT_FPR6_LO 0xCC
72#define PT_FPR7_HI 0xD0
73#define PT_FPR7_LO 0xD4
74#define PT_FPR8_HI 0xD8
75#define PT_FPR8_LO 0XDC
76#define PT_FPR9_HI 0xE0
77#define PT_FPR9_LO 0xE4
78#define PT_FPR10_HI 0xE8
79#define PT_FPR10_LO 0xEC
80#define PT_FPR11_HI 0xF0
81#define PT_FPR11_LO 0xF4
82#define PT_FPR12_HI 0xF8
83#define PT_FPR12_LO 0xFC
84#define PT_FPR13_HI 0x100
85#define PT_FPR13_LO 0x104
86#define PT_FPR14_HI 0x108
87#define PT_FPR14_LO 0x10C
88#define PT_FPR15_HI 0x110
89#define PT_FPR15_LO 0x114
90#define PT_CR_9 0x118
91#define PT_CR_10 0x11C
92#define PT_CR_11 0x120
93#define PT_IEEE_IP 0x13C
94#define PT_LASTOFF PT_IEEE_IP
95#define PT_ENDREGS 0x140-1
96
97#define GPR_SIZE 4
98#define CR_SIZE 4
99
100#define STACK_FRAME_OVERHEAD 96 /* size of minimum stack frame */
101
102#else /* __s390x__ */
103
104#define PT_PSWMASK 0x00
105#define PT_PSWADDR 0x08
106#define PT_GPR0 0x10
107#define PT_GPR1 0x18
108#define PT_GPR2 0x20
109#define PT_GPR3 0x28
110#define PT_GPR4 0x30
111#define PT_GPR5 0x38
112#define PT_GPR6 0x40
113#define PT_GPR7 0x48
114#define PT_GPR8 0x50
115#define PT_GPR9 0x58
116#define PT_GPR10 0x60
117#define PT_GPR11 0x68
118#define PT_GPR12 0x70
119#define PT_GPR13 0x78
120#define PT_GPR14 0x80
121#define PT_GPR15 0x88
122#define PT_ACR0 0x90
123#define PT_ACR1 0x94
124#define PT_ACR2 0x98
125#define PT_ACR3 0x9C
126#define PT_ACR4 0xA0
127#define PT_ACR5 0xA4
128#define PT_ACR6 0xA8
129#define PT_ACR7 0xAC
130#define PT_ACR8 0xB0
131#define PT_ACR9 0xB4
132#define PT_ACR10 0xB8
133#define PT_ACR11 0xBC
134#define PT_ACR12 0xC0
135#define PT_ACR13 0xC4
136#define PT_ACR14 0xC8
137#define PT_ACR15 0xCC
138#define PT_ORIGGPR2 0xD0
139#define PT_FPC 0xD8
140#define PT_FPR0 0xE0
141#define PT_FPR1 0xE8
142#define PT_FPR2 0xF0
143#define PT_FPR3 0xF8
144#define PT_FPR4 0x100
145#define PT_FPR5 0x108
146#define PT_FPR6 0x110
147#define PT_FPR7 0x118
148#define PT_FPR8 0x120
149#define PT_FPR9 0x128
150#define PT_FPR10 0x130
151#define PT_FPR11 0x138
152#define PT_FPR12 0x140
153#define PT_FPR13 0x148
154#define PT_FPR14 0x150
155#define PT_FPR15 0x158
156#define PT_CR_9 0x160
157#define PT_CR_10 0x168
158#define PT_CR_11 0x170
159#define PT_IEEE_IP 0x1A8
160#define PT_LASTOFF PT_IEEE_IP
161#define PT_ENDREGS 0x1B0-1
162
163#define GPR_SIZE 8
164#define CR_SIZE 8
165
166#define STACK_FRAME_OVERHEAD 160 /* size of minimum stack frame */
167
168#endif /* __s390x__ */
169
170#define NUM_GPRS 16
171#define NUM_FPRS 16
172#define NUM_CRS 16
173#define NUM_ACRS 16
174
175#define FPR_SIZE 8
176#define FPC_SIZE 4
177#define FPC_PAD_SIZE 4 /* gcc insists on aligning the fpregs */
178#define ACR_SIZE 4
179
180
181#define PTRACE_OLDSETOPTIONS 21
182
183#ifndef __ASSEMBLY__
184#include <linux/stddef.h>
185#include <linux/types.h>
186
187typedef union
188{
189 float f;
190 double d;
191 __u64 ui;
192 struct
193 {
194 __u32 hi;
195 __u32 lo;
196 } fp;
197} freg_t;
198
199typedef struct
200{
201 __u32 fpc;
202 freg_t fprs[NUM_FPRS];
203} s390_fp_regs;
204
205#define FPC_EXCEPTION_MASK 0xF8000000
206#define FPC_FLAGS_MASK 0x00F80000
207#define FPC_DXC_MASK 0x0000FF00
208#define FPC_RM_MASK 0x00000003
209#define FPC_VALID_MASK 0xF8F8FF03
210
211/* this typedef defines how a Program Status Word looks like */
212typedef struct
213{
214 unsigned long mask;
215 unsigned long addr;
216} __attribute__ ((aligned(8))) psw_t;
217
218typedef struct
219{
220 __u32 mask;
221 __u32 addr;
222} __attribute__ ((aligned(8))) psw_compat_t;
223
224#ifndef __s390x__
225
226#define PSW_MASK_PER 0x40000000UL
227#define PSW_MASK_DAT 0x04000000UL
228#define PSW_MASK_IO 0x02000000UL
229#define PSW_MASK_EXT 0x01000000UL
230#define PSW_MASK_KEY 0x00F00000UL
231#define PSW_MASK_MCHECK 0x00040000UL
232#define PSW_MASK_WAIT 0x00020000UL
233#define PSW_MASK_PSTATE 0x00010000UL
234#define PSW_MASK_ASC 0x0000C000UL
235#define PSW_MASK_CC 0x00003000UL
236#define PSW_MASK_PM 0x00000F00UL
237
238#define PSW_ADDR_AMODE 0x80000000UL
239#define PSW_ADDR_INSN 0x7FFFFFFFUL
240
241#define PSW_BASE_BITS 0x00080000UL
242#define PSW_DEFAULT_KEY (((unsigned long) PAGE_DEFAULT_ACC) << 20)
243
244#define PSW_ASC_PRIMARY 0x00000000UL
245#define PSW_ASC_ACCREG 0x00004000UL
246#define PSW_ASC_SECONDARY 0x00008000UL
247#define PSW_ASC_HOME 0x0000C000UL
248
249#else /* __s390x__ */
250
251#define PSW_MASK_PER 0x4000000000000000UL
252#define PSW_MASK_DAT 0x0400000000000000UL
253#define PSW_MASK_IO 0x0200000000000000UL
254#define PSW_MASK_EXT 0x0100000000000000UL
255#define PSW_MASK_KEY 0x00F0000000000000UL
256#define PSW_MASK_MCHECK 0x0004000000000000UL
257#define PSW_MASK_WAIT 0x0002000000000000UL
258#define PSW_MASK_PSTATE 0x0001000000000000UL
259#define PSW_MASK_ASC 0x0000C00000000000UL
260#define PSW_MASK_CC 0x0000300000000000UL
261#define PSW_MASK_PM 0x00000F0000000000UL
262
263#define PSW_ADDR_AMODE 0x0000000000000000UL
264#define PSW_ADDR_INSN 0xFFFFFFFFFFFFFFFFUL
265
266#define PSW_BASE_BITS 0x0000000180000000UL
267#define PSW_BASE32_BITS 0x0000000080000000UL
268#define PSW_DEFAULT_KEY (((unsigned long) PAGE_DEFAULT_ACC) << 52)
269
270#define PSW_ASC_PRIMARY 0x0000000000000000UL
271#define PSW_ASC_ACCREG 0x0000400000000000UL
272#define PSW_ASC_SECONDARY 0x0000800000000000UL
273#define PSW_ASC_HOME 0x0000C00000000000UL
274
275extern long psw_user32_bits;
276
277#endif /* __s390x__ */
278
279extern long psw_kernel_bits;
280extern long psw_user_bits;
281
282/* This macro merges a NEW PSW mask specified by the user into
283 the currently active PSW mask CURRENT, modifying only those
284 bits in CURRENT that the user may be allowed to change: this
285 is the condition code and the program mask bits. */
286#define PSW_MASK_MERGE(CURRENT,NEW) \
287 (((CURRENT) & ~(PSW_MASK_CC|PSW_MASK_PM)) | \
288 ((NEW) & (PSW_MASK_CC|PSW_MASK_PM)))
289
290/*
291 * The s390_regs structure is used to define the elf_gregset_t.
292 */
293typedef struct
294{
295 psw_t psw;
296 unsigned long gprs[NUM_GPRS];
297 unsigned int acrs[NUM_ACRS];
298 unsigned long orig_gpr2;
299} s390_regs;
300
301typedef struct
302{
303 psw_compat_t psw;
304 __u32 gprs[NUM_GPRS];
305 __u32 acrs[NUM_ACRS];
306 __u32 orig_gpr2;
307} s390_compat_regs;
308
309
310#ifdef __KERNEL__
311#include <asm/setup.h>
312#include <asm/page.h>
313
314/*
315 * The pt_regs struct defines the way the registers are stored on
316 * the stack during a system call.
317 */
318struct pt_regs
319{
320 unsigned long args[1];
321 psw_t psw;
322 unsigned long gprs[NUM_GPRS];
323 unsigned long orig_gpr2;
324 unsigned short ilc;
325 unsigned short trap;
326};
327#endif
328
329/*
330 * Now for the program event recording (trace) definitions.
331 */
332typedef struct
333{
334 unsigned long cr[3];
335} per_cr_words;
336
337#define PER_EM_MASK 0xE8000000UL
338
339typedef struct
340{
341#ifdef __s390x__
342 unsigned : 32;
343#endif /* __s390x__ */
344 unsigned em_branching : 1;
345 unsigned em_instruction_fetch : 1;
346 /*
347 * Switching on storage alteration automatically fixes
348 * the storage alteration event bit in the users std.
349 */
350 unsigned em_storage_alteration : 1;
351 unsigned em_gpr_alt_unused : 1;
352 unsigned em_store_real_address : 1;
353 unsigned : 3;
354 unsigned branch_addr_ctl : 1;
355 unsigned : 1;
356 unsigned storage_alt_space_ctl : 1;
357 unsigned : 21;
358 unsigned long starting_addr;
359 unsigned long ending_addr;
360} per_cr_bits;
361
362typedef struct
363{
364 unsigned short perc_atmid;
365 unsigned long address;
366 unsigned char access_id;
367} per_lowcore_words;
368
369typedef struct
370{
371 unsigned perc_branching : 1;
372 unsigned perc_instruction_fetch : 1;
373 unsigned perc_storage_alteration : 1;
374 unsigned perc_gpr_alt_unused : 1;
375 unsigned perc_store_real_address : 1;
376 unsigned : 3;
377 unsigned atmid_psw_bit_31 : 1;
378 unsigned atmid_validity_bit : 1;
379 unsigned atmid_psw_bit_32 : 1;
380 unsigned atmid_psw_bit_5 : 1;
381 unsigned atmid_psw_bit_16 : 1;
382 unsigned atmid_psw_bit_17 : 1;
383 unsigned si : 2;
384 unsigned long address;
385 unsigned : 4;
386 unsigned access_id : 4;
387} per_lowcore_bits;
388
389typedef struct
390{
391 union {
392 per_cr_words words;
393 per_cr_bits bits;
394 } control_regs;
395 /*
396 * Use these flags instead of setting em_instruction_fetch
397 * directly they are used so that single stepping can be
398 * switched on & off while not affecting other tracing
399 */
400 unsigned single_step : 1;
401 unsigned instruction_fetch : 1;
402 unsigned : 30;
403 /*
404 * These addresses are copied into cr10 & cr11 if single
405 * stepping is switched off
406 */
407 unsigned long starting_addr;
408 unsigned long ending_addr;
409 union {
410 per_lowcore_words words;
411 per_lowcore_bits bits;
412 } lowcore;
413} per_struct;
414
415typedef struct
416{
417 unsigned int len;
418 unsigned long kernel_addr;
419 unsigned long process_addr;
420} ptrace_area;
421
422/*
423 * S/390 specific non posix ptrace requests. I chose unusual values so
424 * they are unlikely to clash with future ptrace definitions.
425 */
426#define PTRACE_PEEKUSR_AREA 0x5000
427#define PTRACE_POKEUSR_AREA 0x5001
428#define PTRACE_PEEKTEXT_AREA 0x5002
429#define PTRACE_PEEKDATA_AREA 0x5003
430#define PTRACE_POKETEXT_AREA 0x5004
431#define PTRACE_POKEDATA_AREA 0x5005
432
433/*
434 * PT_PROT definition is loosely based on hppa bsd definition in
435 * gdb/hppab-nat.c
436 */
437#define PTRACE_PROT 21
438
439typedef enum
440{
441 ptprot_set_access_watchpoint,
442 ptprot_set_write_watchpoint,
443 ptprot_disable_watchpoint
444} ptprot_flags;
445
446typedef struct
447{
448 unsigned long lowaddr;
449 unsigned long hiaddr;
450 ptprot_flags prot;
451} ptprot_area;
452
453/* Sequence of bytes for breakpoint illegal instruction. */
454#define S390_BREAKPOINT {0x0,0x1}
455#define S390_BREAKPOINT_U16 ((__u16)0x0001)
456#define S390_SYSCALL_OPCODE ((__u16)0x0a00)
457#define S390_SYSCALL_SIZE 2
458
459/*
460 * The user_regs_struct defines the way the user registers are
461 * store on the stack for signal handling.
462 */
463struct user_regs_struct
464{
465 psw_t psw;
466 unsigned long gprs[NUM_GPRS];
467 unsigned int acrs[NUM_ACRS];
468 unsigned long orig_gpr2;
469 s390_fp_regs fp_regs;
470 /*
471 * These per registers are in here so that gdb can modify them
472 * itself as there is no "official" ptrace interface for hardware
473 * watchpoints. This is the way intel does it.
474 */
475 per_struct per_info;
476 unsigned long ieee_instruction_pointer;
477 /* Used to give failing instruction back to user for ieee exceptions */
478};
479
480#ifdef __KERNEL__
481/*
482 * These are defined as per linux/ptrace.h, which see.
483 */
484#define arch_has_single_step() (1)
485struct task_struct;
486extern void user_enable_single_step(struct task_struct *);
487extern void user_disable_single_step(struct task_struct *);
488
489#define __ARCH_WANT_COMPAT_SYS_PTRACE
490
491#define user_mode(regs) (((regs)->psw.mask & PSW_MASK_PSTATE) != 0)
492#define instruction_pointer(regs) ((regs)->psw.addr & PSW_ADDR_INSN)
493#define regs_return_value(regs)((regs)->gprs[2])
494#define profile_pc(regs) instruction_pointer(regs)
495extern void show_regs(struct pt_regs * regs);
496#endif /* __KERNEL__ */
497#endif /* __ASSEMBLY__ */
498
499#endif /* _S390_PTRACE_H */
diff --git a/include/asm-s390/qdio.h b/include/asm-s390/qdio.h
deleted file mode 100644
index 6813772171f..00000000000
--- a/include/asm-s390/qdio.h
+++ /dev/null
@@ -1,382 +0,0 @@
1/*
2 * linux/include/asm-s390/qdio.h
3 *
4 * Copyright 2000,2008 IBM Corp.
5 * Author(s): Utz Bacher <utz.bacher@de.ibm.com>
6 * Jan Glauber <jang@linux.vnet.ibm.com>
7 *
8 */
9#ifndef __QDIO_H__
10#define __QDIO_H__
11
12#include <linux/interrupt.h>
13#include <asm/cio.h>
14#include <asm/ccwdev.h>
15
16#define QDIO_MAX_QUEUES_PER_IRQ 32
17#define QDIO_MAX_BUFFERS_PER_Q 128
18#define QDIO_MAX_BUFFERS_MASK (QDIO_MAX_BUFFERS_PER_Q - 1)
19#define QDIO_MAX_ELEMENTS_PER_BUFFER 16
20#define QDIO_SBAL_SIZE 256
21
22#define QDIO_QETH_QFMT 0
23#define QDIO_ZFCP_QFMT 1
24#define QDIO_IQDIO_QFMT 2
25
26/**
27 * struct qdesfmt0 - queue descriptor, format 0
28 * @sliba: storage list information block address
29 * @sla: storage list address
30 * @slsba: storage list state block address
31 * @akey: access key for DLIB
32 * @bkey: access key for SL
33 * @ckey: access key for SBALs
34 * @dkey: access key for SLSB
35 */
36struct qdesfmt0 {
37 u64 sliba;
38 u64 sla;
39 u64 slsba;
40 u32 : 32;
41 u32 akey : 4;
42 u32 bkey : 4;
43 u32 ckey : 4;
44 u32 dkey : 4;
45 u32 : 16;
46} __attribute__ ((packed));
47
48/**
49 * struct qdr - queue description record (QDR)
50 * @qfmt: queue format
51 * @pfmt: implementation dependent parameter format
52 * @ac: adapter characteristics
53 * @iqdcnt: input queue descriptor count
54 * @oqdcnt: output queue descriptor count
55 * @iqdsz: inpout queue descriptor size
56 * @oqdsz: output queue descriptor size
57 * @qiba: queue information block address
58 * @qkey: queue information block key
59 * @qdf0: queue descriptions
60 */
61struct qdr {
62 u32 qfmt : 8;
63 u32 pfmt : 8;
64 u32 : 8;
65 u32 ac : 8;
66 u32 : 8;
67 u32 iqdcnt : 8;
68 u32 : 8;
69 u32 oqdcnt : 8;
70 u32 : 8;
71 u32 iqdsz : 8;
72 u32 : 8;
73 u32 oqdsz : 8;
74 /* private: */
75 u32 res[9];
76 /* public: */
77 u64 qiba;
78 u32 : 32;
79 u32 qkey : 4;
80 u32 : 28;
81 struct qdesfmt0 qdf0[126];
82} __attribute__ ((packed, aligned(4096)));
83
84#define QIB_AC_OUTBOUND_PCI_SUPPORTED 0x40
85#define QIB_RFLAGS_ENABLE_QEBSM 0x80
86
87/**
88 * struct qib - queue information block (QIB)
89 * @qfmt: queue format
90 * @pfmt: implementation dependent parameter format
91 * @rflags: QEBSM
92 * @ac: adapter characteristics
93 * @isliba: absolute address of first input SLIB
94 * @osliba: absolute address of first output SLIB
95 * @ebcnam: adapter identifier in EBCDIC
96 * @parm: implementation dependent parameters
97 */
98struct qib {
99 u32 qfmt : 8;
100 u32 pfmt : 8;
101 u32 rflags : 8;
102 u32 ac : 8;
103 u32 : 32;
104 u64 isliba;
105 u64 osliba;
106 u32 : 32;
107 u32 : 32;
108 u8 ebcnam[8];
109 /* private: */
110 u8 res[88];
111 /* public: */
112 u8 parm[QDIO_MAX_BUFFERS_PER_Q];
113} __attribute__ ((packed, aligned(256)));
114
115/**
116 * struct slibe - storage list information block element (SLIBE)
117 * @parms: implementation dependent parameters
118 */
119struct slibe {
120 u64 parms;
121};
122
123/**
124 * struct slib - storage list information block (SLIB)
125 * @nsliba: next SLIB address (if any)
126 * @sla: SL address
127 * @slsba: SLSB address
128 * @slibe: SLIB elements
129 */
130struct slib {
131 u64 nsliba;
132 u64 sla;
133 u64 slsba;
134 /* private: */
135 u8 res[1000];
136 /* public: */
137 struct slibe slibe[QDIO_MAX_BUFFERS_PER_Q];
138} __attribute__ ((packed, aligned(2048)));
139
140/**
141 * struct sbal_flags - storage block address list flags
142 * @last: last entry
143 * @cont: contiguous storage
144 * @frag: fragmentation
145 */
146struct sbal_flags {
147 u8 : 1;
148 u8 last : 1;
149 u8 cont : 1;
150 u8 : 1;
151 u8 frag : 2;
152 u8 : 2;
153} __attribute__ ((packed));
154
155#define SBAL_FLAGS_FIRST_FRAG 0x04000000UL
156#define SBAL_FLAGS_MIDDLE_FRAG 0x08000000UL
157#define SBAL_FLAGS_LAST_FRAG 0x0c000000UL
158#define SBAL_FLAGS_LAST_ENTRY 0x40000000UL
159#define SBAL_FLAGS_CONTIGUOUS 0x20000000UL
160
161#define SBAL_FLAGS0_DATA_CONTINUATION 0x20UL
162
163/* Awesome OpenFCP extensions */
164#define SBAL_FLAGS0_TYPE_STATUS 0x00UL
165#define SBAL_FLAGS0_TYPE_WRITE 0x08UL
166#define SBAL_FLAGS0_TYPE_READ 0x10UL
167#define SBAL_FLAGS0_TYPE_WRITE_READ 0x18UL
168#define SBAL_FLAGS0_MORE_SBALS 0x04UL
169#define SBAL_FLAGS0_COMMAND 0x02UL
170#define SBAL_FLAGS0_LAST_SBAL 0x00UL
171#define SBAL_FLAGS0_ONLY_SBAL SBAL_FLAGS0_COMMAND
172#define SBAL_FLAGS0_MIDDLE_SBAL SBAL_FLAGS0_MORE_SBALS
173#define SBAL_FLAGS0_FIRST_SBAL SBAL_FLAGS0_MORE_SBALS | SBAL_FLAGS0_COMMAND
174#define SBAL_FLAGS0_PCI 0x40
175
176/**
177 * struct sbal_sbalf_0 - sbal flags for sbale 0
178 * @pci: PCI indicator
179 * @cont: data continuation
180 * @sbtype: storage-block type (FCP)
181 */
182struct sbal_sbalf_0 {
183 u8 : 1;
184 u8 pci : 1;
185 u8 cont : 1;
186 u8 sbtype : 2;
187 u8 : 3;
188} __attribute__ ((packed));
189
190/**
191 * struct sbal_sbalf_1 - sbal flags for sbale 1
192 * @key: storage key
193 */
194struct sbal_sbalf_1 {
195 u8 : 4;
196 u8 key : 4;
197} __attribute__ ((packed));
198
199/**
200 * struct sbal_sbalf_14 - sbal flags for sbale 14
201 * @erridx: error index
202 */
203struct sbal_sbalf_14 {
204 u8 : 4;
205 u8 erridx : 4;
206} __attribute__ ((packed));
207
208/**
209 * struct sbal_sbalf_15 - sbal flags for sbale 15
210 * @reason: reason for error state
211 */
212struct sbal_sbalf_15 {
213 u8 reason;
214} __attribute__ ((packed));
215
216/**
217 * union sbal_sbalf - storage block address list flags
218 * @i0: sbalf0
219 * @i1: sbalf1
220 * @i14: sbalf14
221 * @i15: sblaf15
222 * @value: raw value
223 */
224union sbal_sbalf {
225 struct sbal_sbalf_0 i0;
226 struct sbal_sbalf_1 i1;
227 struct sbal_sbalf_14 i14;
228 struct sbal_sbalf_15 i15;
229 u8 value;
230};
231
232/**
233 * struct qdio_buffer_element - SBAL entry
234 * @flags: flags
235 * @length: length
236 * @addr: address
237*/
238struct qdio_buffer_element {
239 u32 flags;
240 u32 length;
241#ifdef CONFIG_32BIT
242 /* private: */
243 void *reserved;
244 /* public: */
245#endif
246 void *addr;
247} __attribute__ ((packed, aligned(16)));
248
249/**
250 * struct qdio_buffer - storage block address list (SBAL)
251 * @element: SBAL entries
252 */
253struct qdio_buffer {
254 struct qdio_buffer_element element[QDIO_MAX_ELEMENTS_PER_BUFFER];
255} __attribute__ ((packed, aligned(256)));
256
257/**
258 * struct sl_element - storage list entry
259 * @sbal: absolute SBAL address
260 */
261struct sl_element {
262#ifdef CONFIG_32BIT
263 /* private: */
264 unsigned long reserved;
265 /* public: */
266#endif
267 unsigned long sbal;
268} __attribute__ ((packed));
269
270/**
271 * struct sl - storage list (SL)
272 * @element: SL entries
273 */
274struct sl {
275 struct sl_element element[QDIO_MAX_BUFFERS_PER_Q];
276} __attribute__ ((packed, aligned(1024)));
277
278/**
279 * struct slsb - storage list state block (SLSB)
280 * @val: state per buffer
281 */
282struct slsb {
283 u8 val[QDIO_MAX_BUFFERS_PER_Q];
284} __attribute__ ((packed, aligned(256)));
285
286struct qdio_ssqd_desc {
287 u8 flags;
288 u8:8;
289 u16 sch;
290 u8 qfmt;
291 u8 parm;
292 u8 qdioac1;
293 u8 sch_class;
294 u8 pcnt;
295 u8 icnt;
296 u8:8;
297 u8 ocnt;
298 u8:8;
299 u8 mbccnt;
300 u16 qdioac2;
301 u64 sch_token;
302 u64:64;
303} __attribute__ ((packed));
304
305/* params are: ccw_device, qdio_error, queue_number,
306 first element processed, number of elements processed, int_parm */
307typedef void qdio_handler_t(struct ccw_device *, unsigned int, int,
308 int, int, unsigned long);
309
310/* qdio errors reported to the upper-layer program */
311#define QDIO_ERROR_SIGA_ACCESS_EXCEPTION 0x10
312#define QDIO_ERROR_SIGA_BUSY 0x20
313#define QDIO_ERROR_ACTIVATE_CHECK_CONDITION 0x40
314#define QDIO_ERROR_SLSB_STATE 0x80
315
316/* for qdio_initialize */
317#define QDIO_INBOUND_0COPY_SBALS 0x01
318#define QDIO_OUTBOUND_0COPY_SBALS 0x02
319#define QDIO_USE_OUTBOUND_PCIS 0x04
320
321/* for qdio_cleanup */
322#define QDIO_FLAG_CLEANUP_USING_CLEAR 0x01
323#define QDIO_FLAG_CLEANUP_USING_HALT 0x02
324
325/**
326 * struct qdio_initialize - qdio initalization data
327 * @cdev: associated ccw device
328 * @q_format: queue format
329 * @adapter_name: name for the adapter
330 * @qib_param_field_format: format for qib_parm_field
331 * @qib_param_field: pointer to 128 bytes or NULL, if no param field
332 * @input_slib_elements: pointer to no_input_qs * 128 words of data or NULL
333 * @output_slib_elements: pointer to no_output_qs * 128 words of data or NULL
334 * @no_input_qs: number of input queues
335 * @no_output_qs: number of output queues
336 * @input_handler: handler to be called for input queues
337 * @output_handler: handler to be called for output queues
338 * @int_parm: interruption parameter
339 * @flags: initialization flags
340 * @input_sbal_addr_array: address of no_input_qs * 128 pointers
341 * @output_sbal_addr_array: address of no_output_qs * 128 pointers
342 */
343struct qdio_initialize {
344 struct ccw_device *cdev;
345 unsigned char q_format;
346 unsigned char adapter_name[8];
347 unsigned int qib_param_field_format;
348 unsigned char *qib_param_field;
349 unsigned long *input_slib_elements;
350 unsigned long *output_slib_elements;
351 unsigned int no_input_qs;
352 unsigned int no_output_qs;
353 qdio_handler_t *input_handler;
354 qdio_handler_t *output_handler;
355 unsigned long int_parm;
356 unsigned long flags;
357 void **input_sbal_addr_array;
358 void **output_sbal_addr_array;
359};
360
361#define QDIO_STATE_INACTIVE 0x00000002 /* after qdio_cleanup */
362#define QDIO_STATE_ESTABLISHED 0x00000004 /* after qdio_establish */
363#define QDIO_STATE_ACTIVE 0x00000008 /* after qdio_activate */
364#define QDIO_STATE_STOPPED 0x00000010 /* after queues went down */
365
366#define QDIO_FLAG_SYNC_INPUT 0x01
367#define QDIO_FLAG_SYNC_OUTPUT 0x02
368#define QDIO_FLAG_PCI_OUT 0x10
369
370extern int qdio_initialize(struct qdio_initialize *init_data);
371extern int qdio_allocate(struct qdio_initialize *init_data);
372extern int qdio_establish(struct qdio_initialize *init_data);
373extern int qdio_activate(struct ccw_device *);
374
375extern int do_QDIO(struct ccw_device*, unsigned int flags,
376 int q_nr, int qidx, int count);
377extern int qdio_cleanup(struct ccw_device*, int how);
378extern int qdio_shutdown(struct ccw_device*, int how);
379extern int qdio_free(struct ccw_device *);
380extern struct qdio_ssqd_desc *qdio_get_ssqd_desc(struct ccw_device *cdev);
381
382#endif /* __QDIO_H__ */
diff --git a/include/asm-s390/qeth.h b/include/asm-s390/qeth.h
deleted file mode 100644
index 930d378ef75..00000000000
--- a/include/asm-s390/qeth.h
+++ /dev/null
@@ -1,78 +0,0 @@
1/*
2 * include/asm-s390/qeth.h
3 *
4 * ioctl definitions for qeth driver
5 *
6 * Copyright (C) 2004 IBM Corporation
7 *
8 * Author(s): Thomas Spatzier <tspat@de.ibm.com>
9 *
10 */
11#ifndef __ASM_S390_QETH_IOCTL_H__
12#define __ASM_S390_QETH_IOCTL_H__
13#include <linux/ioctl.h>
14
15#define SIOC_QETH_ARP_SET_NO_ENTRIES (SIOCDEVPRIVATE)
16#define SIOC_QETH_ARP_QUERY_INFO (SIOCDEVPRIVATE + 1)
17#define SIOC_QETH_ARP_ADD_ENTRY (SIOCDEVPRIVATE + 2)
18#define SIOC_QETH_ARP_REMOVE_ENTRY (SIOCDEVPRIVATE + 3)
19#define SIOC_QETH_ARP_FLUSH_CACHE (SIOCDEVPRIVATE + 4)
20#define SIOC_QETH_ADP_SET_SNMP_CONTROL (SIOCDEVPRIVATE + 5)
21#define SIOC_QETH_GET_CARD_TYPE (SIOCDEVPRIVATE + 6)
22
23struct qeth_arp_cache_entry {
24 __u8 macaddr[6];
25 __u8 reserved1[2];
26 __u8 ipaddr[16]; /* for both IPv4 and IPv6 */
27 __u8 reserved2[32];
28} __attribute__ ((packed));
29
30struct qeth_arp_qi_entry7 {
31 __u8 media_specific[32];
32 __u8 macaddr_type;
33 __u8 ipaddr_type;
34 __u8 macaddr[6];
35 __u8 ipaddr[4];
36} __attribute__((packed));
37
38struct qeth_arp_qi_entry7_short {
39 __u8 macaddr_type;
40 __u8 ipaddr_type;
41 __u8 macaddr[6];
42 __u8 ipaddr[4];
43} __attribute__((packed));
44
45struct qeth_arp_qi_entry5 {
46 __u8 media_specific[32];
47 __u8 macaddr_type;
48 __u8 ipaddr_type;
49 __u8 ipaddr[4];
50} __attribute__((packed));
51
52struct qeth_arp_qi_entry5_short {
53 __u8 macaddr_type;
54 __u8 ipaddr_type;
55 __u8 ipaddr[4];
56} __attribute__((packed));
57
58/*
59 * can be set by user if no "media specific information" is wanted
60 * -> saves a lot of space in user space buffer
61 */
62#define QETH_QARP_STRIP_ENTRIES 0x8000
63#define QETH_QARP_REQUEST_MASK 0x00ff
64
65/* data sent to user space as result of query arp ioctl */
66#define QETH_QARP_USER_DATA_SIZE 20000
67#define QETH_QARP_MASK_OFFSET 4
68#define QETH_QARP_ENTRIES_OFFSET 6
69struct qeth_arp_query_user_data {
70 union {
71 __u32 data_len; /* set by user space program */
72 __u32 no_entries; /* set by kernel */
73 } u;
74 __u16 mask_bits;
75 char *entries;
76} __attribute__((packed));
77
78#endif /* __ASM_S390_QETH_IOCTL_H__ */
diff --git a/include/asm-s390/reset.h b/include/asm-s390/reset.h
deleted file mode 100644
index f584f4a5258..00000000000
--- a/include/asm-s390/reset.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * include/asm-s390/reset.h
3 *
4 * Copyright IBM Corp. 2006
5 * Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>
6 */
7
8#ifndef _ASM_S390_RESET_H
9#define _ASM_S390_RESET_H
10
11#include <linux/list.h>
12
13struct reset_call {
14 struct list_head list;
15 void (*fn)(void);
16};
17
18extern void register_reset_call(struct reset_call *reset);
19extern void unregister_reset_call(struct reset_call *reset);
20extern void s390_reset_system(void);
21#endif /* _ASM_S390_RESET_H */
diff --git a/include/asm-s390/resource.h b/include/asm-s390/resource.h
deleted file mode 100644
index 366c01de04f..00000000000
--- a/include/asm-s390/resource.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/*
2 * include/asm-s390/resource.h
3 *
4 * S390 version
5 *
6 * Derived from "include/asm-i386/resources.h"
7 */
8
9#ifndef _S390_RESOURCE_H
10#define _S390_RESOURCE_H
11
12#include <asm-generic/resource.h>
13
14#endif
15
diff --git a/include/asm-s390/rwsem.h b/include/asm-s390/rwsem.h
deleted file mode 100644
index 9d2a1797180..00000000000
--- a/include/asm-s390/rwsem.h
+++ /dev/null
@@ -1,387 +0,0 @@
1#ifndef _S390_RWSEM_H
2#define _S390_RWSEM_H
3
4/*
5 * include/asm-s390/rwsem.h
6 *
7 * S390 version
8 * Copyright (C) 2002 IBM Deutschland Entwicklung GmbH, IBM Corporation
9 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
10 *
11 * Based on asm-alpha/semaphore.h and asm-i386/rwsem.h
12 */
13
14/*
15 *
16 * The MSW of the count is the negated number of active writers and waiting
17 * lockers, and the LSW is the total number of active locks
18 *
19 * The lock count is initialized to 0 (no active and no waiting lockers).
20 *
21 * When a writer subtracts WRITE_BIAS, it'll get 0xffff0001 for the case of an
22 * uncontended lock. This can be determined because XADD returns the old value.
23 * Readers increment by 1 and see a positive value when uncontended, negative
24 * if there are writers (and maybe) readers waiting (in which case it goes to
25 * sleep).
26 *
27 * The value of WAITING_BIAS supports up to 32766 waiting processes. This can
28 * be extended to 65534 by manually checking the whole MSW rather than relying
29 * on the S flag.
30 *
31 * The value of ACTIVE_BIAS supports up to 65535 active processes.
32 *
33 * This should be totally fair - if anything is waiting, a process that wants a
34 * lock will go to the back of the queue. When the currently active lock is
35 * released, if there's a writer at the front of the queue, then that and only
36 * that will be woken up; if there's a bunch of consequtive readers at the
37 * front, then they'll all be woken up, but no other readers will be.
38 */
39
40#ifndef _LINUX_RWSEM_H
41#error "please don't include asm/rwsem.h directly, use linux/rwsem.h instead"
42#endif
43
44#ifdef __KERNEL__
45
46#include <linux/list.h>
47#include <linux/spinlock.h>
48
49struct rwsem_waiter;
50
51extern struct rw_semaphore *rwsem_down_read_failed(struct rw_semaphore *);
52extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *);
53extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *);
54extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *);
55extern struct rw_semaphore *rwsem_downgrade_write(struct rw_semaphore *);
56
57/*
58 * the semaphore definition
59 */
60struct rw_semaphore {
61 signed long count;
62 spinlock_t wait_lock;
63 struct list_head wait_list;
64#ifdef CONFIG_DEBUG_LOCK_ALLOC
65 struct lockdep_map dep_map;
66#endif
67};
68
69#ifndef __s390x__
70#define RWSEM_UNLOCKED_VALUE 0x00000000
71#define RWSEM_ACTIVE_BIAS 0x00000001
72#define RWSEM_ACTIVE_MASK 0x0000ffff
73#define RWSEM_WAITING_BIAS (-0x00010000)
74#else /* __s390x__ */
75#define RWSEM_UNLOCKED_VALUE 0x0000000000000000L
76#define RWSEM_ACTIVE_BIAS 0x0000000000000001L
77#define RWSEM_ACTIVE_MASK 0x00000000ffffffffL
78#define RWSEM_WAITING_BIAS (-0x0000000100000000L)
79#endif /* __s390x__ */
80#define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS
81#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
82
83/*
84 * initialisation
85 */
86
87#ifdef CONFIG_DEBUG_LOCK_ALLOC
88# define __RWSEM_DEP_MAP_INIT(lockname) , .dep_map = { .name = #lockname }
89#else
90# define __RWSEM_DEP_MAP_INIT(lockname)
91#endif
92
93#define __RWSEM_INITIALIZER(name) \
94 { RWSEM_UNLOCKED_VALUE, __SPIN_LOCK_UNLOCKED((name).wait.lock), \
95 LIST_HEAD_INIT((name).wait_list) __RWSEM_DEP_MAP_INIT(name) }
96
97#define DECLARE_RWSEM(name) \
98 struct rw_semaphore name = __RWSEM_INITIALIZER(name)
99
100static inline void init_rwsem(struct rw_semaphore *sem)
101{
102 sem->count = RWSEM_UNLOCKED_VALUE;
103 spin_lock_init(&sem->wait_lock);
104 INIT_LIST_HEAD(&sem->wait_list);
105}
106
107extern void __init_rwsem(struct rw_semaphore *sem, const char *name,
108 struct lock_class_key *key);
109
110#define init_rwsem(sem) \
111do { \
112 static struct lock_class_key __key; \
113 \
114 __init_rwsem((sem), #sem, &__key); \
115} while (0)
116
117
118/*
119 * lock for reading
120 */
121static inline void __down_read(struct rw_semaphore *sem)
122{
123 signed long old, new;
124
125 asm volatile(
126#ifndef __s390x__
127 " l %0,0(%3)\n"
128 "0: lr %1,%0\n"
129 " ahi %1,%5\n"
130 " cs %0,%1,0(%3)\n"
131 " jl 0b"
132#else /* __s390x__ */
133 " lg %0,0(%3)\n"
134 "0: lgr %1,%0\n"
135 " aghi %1,%5\n"
136 " csg %0,%1,0(%3)\n"
137 " jl 0b"
138#endif /* __s390x__ */
139 : "=&d" (old), "=&d" (new), "=m" (sem->count)
140 : "a" (&sem->count), "m" (sem->count),
141 "i" (RWSEM_ACTIVE_READ_BIAS) : "cc", "memory");
142 if (old < 0)
143 rwsem_down_read_failed(sem);
144}
145
146/*
147 * trylock for reading -- returns 1 if successful, 0 if contention
148 */
149static inline int __down_read_trylock(struct rw_semaphore *sem)
150{
151 signed long old, new;
152
153 asm volatile(
154#ifndef __s390x__
155 " l %0,0(%3)\n"
156 "0: ltr %1,%0\n"
157 " jm 1f\n"
158 " ahi %1,%5\n"
159 " cs %0,%1,0(%3)\n"
160 " jl 0b\n"
161 "1:"
162#else /* __s390x__ */
163 " lg %0,0(%3)\n"
164 "0: ltgr %1,%0\n"
165 " jm 1f\n"
166 " aghi %1,%5\n"
167 " csg %0,%1,0(%3)\n"
168 " jl 0b\n"
169 "1:"
170#endif /* __s390x__ */
171 : "=&d" (old), "=&d" (new), "=m" (sem->count)
172 : "a" (&sem->count), "m" (sem->count),
173 "i" (RWSEM_ACTIVE_READ_BIAS) : "cc", "memory");
174 return old >= 0 ? 1 : 0;
175}
176
177/*
178 * lock for writing
179 */
180static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
181{
182 signed long old, new, tmp;
183
184 tmp = RWSEM_ACTIVE_WRITE_BIAS;
185 asm volatile(
186#ifndef __s390x__
187 " l %0,0(%3)\n"
188 "0: lr %1,%0\n"
189 " a %1,%5\n"
190 " cs %0,%1,0(%3)\n"
191 " jl 0b"
192#else /* __s390x__ */
193 " lg %0,0(%3)\n"
194 "0: lgr %1,%0\n"
195 " ag %1,%5\n"
196 " csg %0,%1,0(%3)\n"
197 " jl 0b"
198#endif /* __s390x__ */
199 : "=&d" (old), "=&d" (new), "=m" (sem->count)
200 : "a" (&sem->count), "m" (sem->count), "m" (tmp)
201 : "cc", "memory");
202 if (old != 0)
203 rwsem_down_write_failed(sem);
204}
205
206static inline void __down_write(struct rw_semaphore *sem)
207{
208 __down_write_nested(sem, 0);
209}
210
211/*
212 * trylock for writing -- returns 1 if successful, 0 if contention
213 */
214static inline int __down_write_trylock(struct rw_semaphore *sem)
215{
216 signed long old;
217
218 asm volatile(
219#ifndef __s390x__
220 " l %0,0(%2)\n"
221 "0: ltr %0,%0\n"
222 " jnz 1f\n"
223 " cs %0,%4,0(%2)\n"
224 " jl 0b\n"
225#else /* __s390x__ */
226 " lg %0,0(%2)\n"
227 "0: ltgr %0,%0\n"
228 " jnz 1f\n"
229 " csg %0,%4,0(%2)\n"
230 " jl 0b\n"
231#endif /* __s390x__ */
232 "1:"
233 : "=&d" (old), "=m" (sem->count)
234 : "a" (&sem->count), "m" (sem->count),
235 "d" (RWSEM_ACTIVE_WRITE_BIAS) : "cc", "memory");
236 return (old == RWSEM_UNLOCKED_VALUE) ? 1 : 0;
237}
238
239/*
240 * unlock after reading
241 */
242static inline void __up_read(struct rw_semaphore *sem)
243{
244 signed long old, new;
245
246 asm volatile(
247#ifndef __s390x__
248 " l %0,0(%3)\n"
249 "0: lr %1,%0\n"
250 " ahi %1,%5\n"
251 " cs %0,%1,0(%3)\n"
252 " jl 0b"
253#else /* __s390x__ */
254 " lg %0,0(%3)\n"
255 "0: lgr %1,%0\n"
256 " aghi %1,%5\n"
257 " csg %0,%1,0(%3)\n"
258 " jl 0b"
259#endif /* __s390x__ */
260 : "=&d" (old), "=&d" (new), "=m" (sem->count)
261 : "a" (&sem->count), "m" (sem->count),
262 "i" (-RWSEM_ACTIVE_READ_BIAS)
263 : "cc", "memory");
264 if (new < 0)
265 if ((new & RWSEM_ACTIVE_MASK) == 0)
266 rwsem_wake(sem);
267}
268
269/*
270 * unlock after writing
271 */
272static inline void __up_write(struct rw_semaphore *sem)
273{
274 signed long old, new, tmp;
275
276 tmp = -RWSEM_ACTIVE_WRITE_BIAS;
277 asm volatile(
278#ifndef __s390x__
279 " l %0,0(%3)\n"
280 "0: lr %1,%0\n"
281 " a %1,%5\n"
282 " cs %0,%1,0(%3)\n"
283 " jl 0b"
284#else /* __s390x__ */
285 " lg %0,0(%3)\n"
286 "0: lgr %1,%0\n"
287 " ag %1,%5\n"
288 " csg %0,%1,0(%3)\n"
289 " jl 0b"
290#endif /* __s390x__ */
291 : "=&d" (old), "=&d" (new), "=m" (sem->count)
292 : "a" (&sem->count), "m" (sem->count), "m" (tmp)
293 : "cc", "memory");
294 if (new < 0)
295 if ((new & RWSEM_ACTIVE_MASK) == 0)
296 rwsem_wake(sem);
297}
298
299/*
300 * downgrade write lock to read lock
301 */
302static inline void __downgrade_write(struct rw_semaphore *sem)
303{
304 signed long old, new, tmp;
305
306 tmp = -RWSEM_WAITING_BIAS;
307 asm volatile(
308#ifndef __s390x__
309 " l %0,0(%3)\n"
310 "0: lr %1,%0\n"
311 " a %1,%5\n"
312 " cs %0,%1,0(%3)\n"
313 " jl 0b"
314#else /* __s390x__ */
315 " lg %0,0(%3)\n"
316 "0: lgr %1,%0\n"
317 " ag %1,%5\n"
318 " csg %0,%1,0(%3)\n"
319 " jl 0b"
320#endif /* __s390x__ */
321 : "=&d" (old), "=&d" (new), "=m" (sem->count)
322 : "a" (&sem->count), "m" (sem->count), "m" (tmp)
323 : "cc", "memory");
324 if (new > 1)
325 rwsem_downgrade_wake(sem);
326}
327
328/*
329 * implement atomic add functionality
330 */
331static inline void rwsem_atomic_add(long delta, struct rw_semaphore *sem)
332{
333 signed long old, new;
334
335 asm volatile(
336#ifndef __s390x__
337 " l %0,0(%3)\n"
338 "0: lr %1,%0\n"
339 " ar %1,%5\n"
340 " cs %0,%1,0(%3)\n"
341 " jl 0b"
342#else /* __s390x__ */
343 " lg %0,0(%3)\n"
344 "0: lgr %1,%0\n"
345 " agr %1,%5\n"
346 " csg %0,%1,0(%3)\n"
347 " jl 0b"
348#endif /* __s390x__ */
349 : "=&d" (old), "=&d" (new), "=m" (sem->count)
350 : "a" (&sem->count), "m" (sem->count), "d" (delta)
351 : "cc", "memory");
352}
353
354/*
355 * implement exchange and add functionality
356 */
357static inline long rwsem_atomic_update(long delta, struct rw_semaphore *sem)
358{
359 signed long old, new;
360
361 asm volatile(
362#ifndef __s390x__
363 " l %0,0(%3)\n"
364 "0: lr %1,%0\n"
365 " ar %1,%5\n"
366 " cs %0,%1,0(%3)\n"
367 " jl 0b"
368#else /* __s390x__ */
369 " lg %0,0(%3)\n"
370 "0: lgr %1,%0\n"
371 " agr %1,%5\n"
372 " csg %0,%1,0(%3)\n"
373 " jl 0b"
374#endif /* __s390x__ */
375 : "=&d" (old), "=&d" (new), "=m" (sem->count)
376 : "a" (&sem->count), "m" (sem->count), "d" (delta)
377 : "cc", "memory");
378 return new;
379}
380
381static inline int rwsem_is_locked(struct rw_semaphore *sem)
382{
383 return (sem->count != 0);
384}
385
386#endif /* __KERNEL__ */
387#endif /* _S390_RWSEM_H */
diff --git a/include/asm-s390/s390_ext.h b/include/asm-s390/s390_ext.h
deleted file mode 100644
index 2afc060266a..00000000000
--- a/include/asm-s390/s390_ext.h
+++ /dev/null
@@ -1,32 +0,0 @@
1#ifndef _S390_EXTINT_H
2#define _S390_EXTINT_H
3
4/*
5 * include/asm-s390/s390_ext.h
6 *
7 * S390 version
8 * Copyright IBM Corp. 1999,2007
9 * Author(s): Holger Smolinski (Holger.Smolinski@de.ibm.com),
10 * Martin Schwidefsky (schwidefsky@de.ibm.com)
11 */
12
13#include <linux/types.h>
14
15typedef void (*ext_int_handler_t)(__u16 code);
16
17typedef struct ext_int_info_t {
18 struct ext_int_info_t *next;
19 ext_int_handler_t handler;
20 __u16 code;
21} ext_int_info_t;
22
23extern ext_int_info_t *ext_int_hash[];
24
25int register_external_interrupt(__u16 code, ext_int_handler_t handler);
26int register_early_external_interrupt(__u16 code, ext_int_handler_t handler,
27 ext_int_info_t *info);
28int unregister_external_interrupt(__u16 code, ext_int_handler_t handler);
29int unregister_early_external_interrupt(__u16 code, ext_int_handler_t handler,
30 ext_int_info_t *info);
31
32#endif
diff --git a/include/asm-s390/s390_rdev.h b/include/asm-s390/s390_rdev.h
deleted file mode 100644
index 6fa20442a48..00000000000
--- a/include/asm-s390/s390_rdev.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/*
2 * include/asm-s390/ccwdev.h
3 *
4 * Copyright (C) 2002,2005 IBM Deutschland Entwicklung GmbH, IBM Corporation
5 * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
6 * Carsten Otte <cotte@de.ibm.com>
7 *
8 * Interface for s390 root device
9 */
10
11#ifndef _S390_RDEV_H_
12#define _S390_RDEV_H_
13extern struct device *s390_root_dev_register(const char *);
14extern void s390_root_dev_unregister(struct device *);
15#endif /* _S390_RDEV_H_ */
diff --git a/include/asm-s390/scatterlist.h b/include/asm-s390/scatterlist.h
deleted file mode 100644
index 29ec8e28c8d..00000000000
--- a/include/asm-s390/scatterlist.h
+++ /dev/null
@@ -1,19 +0,0 @@
1#ifndef _ASMS390_SCATTERLIST_H
2#define _ASMS390_SCATTERLIST_H
3
4struct scatterlist {
5#ifdef CONFIG_DEBUG_SG
6 unsigned long sg_magic;
7#endif
8 unsigned long page_link;
9 unsigned int offset;
10 unsigned int length;
11};
12
13#ifdef __s390x__
14#define ISA_DMA_THRESHOLD (0xffffffffffffffffUL)
15#else
16#define ISA_DMA_THRESHOLD (0xffffffffUL)
17#endif
18
19#endif /* _ASMS390X_SCATTERLIST_H */
diff --git a/include/asm-s390/schid.h b/include/asm-s390/schid.h
deleted file mode 100644
index 7bdc0fe1569..00000000000
--- a/include/asm-s390/schid.h
+++ /dev/null
@@ -1,31 +0,0 @@
1#ifndef ASM_SCHID_H
2#define ASM_SCHID_H
3
4struct subchannel_id {
5 __u32 cssid : 8;
6 __u32 : 4;
7 __u32 m : 1;
8 __u32 ssid : 2;
9 __u32 one : 1;
10 __u32 sch_no : 16;
11} __attribute__ ((packed, aligned(4)));
12
13#ifdef __KERNEL__
14
15/* Helper function for sane state of pre-allocated subchannel_id. */
16static inline void
17init_subchannel_id(struct subchannel_id *schid)
18{
19 memset(schid, 0, sizeof(struct subchannel_id));
20 schid->one = 1;
21}
22
23static inline int
24schid_equal(struct subchannel_id *schid1, struct subchannel_id *schid2)
25{
26 return !memcmp(schid1, schid2, sizeof(struct subchannel_id));
27}
28
29#endif /* __KERNEL__ */
30
31#endif /* ASM_SCHID_H */
diff --git a/include/asm-s390/sclp.h b/include/asm-s390/sclp.h
deleted file mode 100644
index fed7bee650a..00000000000
--- a/include/asm-s390/sclp.h
+++ /dev/null
@@ -1,58 +0,0 @@
1/*
2 * include/asm-s390/sclp.h
3 *
4 * Copyright IBM Corp. 2007
5 * Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>
6 */
7
8#ifndef _ASM_S390_SCLP_H
9#define _ASM_S390_SCLP_H
10
11#include <linux/types.h>
12#include <asm/chpid.h>
13
14#define SCLP_CHP_INFO_MASK_SIZE 32
15
16struct sclp_chp_info {
17 u8 recognized[SCLP_CHP_INFO_MASK_SIZE];
18 u8 standby[SCLP_CHP_INFO_MASK_SIZE];
19 u8 configured[SCLP_CHP_INFO_MASK_SIZE];
20};
21
22#define LOADPARM_LEN 8
23
24struct sclp_ipl_info {
25 int is_valid;
26 int has_dump;
27 char loadparm[LOADPARM_LEN];
28};
29
30struct sclp_cpu_entry {
31 u8 address;
32 u8 reserved0[13];
33 u8 type;
34 u8 reserved1;
35} __attribute__((packed));
36
37struct sclp_cpu_info {
38 unsigned int configured;
39 unsigned int standby;
40 unsigned int combined;
41 int has_cpu_type;
42 struct sclp_cpu_entry cpu[255];
43};
44
45int sclp_get_cpu_info(struct sclp_cpu_info *info);
46int sclp_cpu_configure(u8 cpu);
47int sclp_cpu_deconfigure(u8 cpu);
48void sclp_facilities_detect(void);
49unsigned long long sclp_get_rnmax(void);
50unsigned long long sclp_get_rzm(void);
51int sclp_sdias_blk_count(void);
52int sclp_sdias_copy(void *dest, int blk_num, int nr_blks);
53int sclp_chp_configure(struct chp_id chpid);
54int sclp_chp_deconfigure(struct chp_id chpid);
55int sclp_chp_read_info(struct sclp_chp_info *info);
56void sclp_get_ipl_info(struct sclp_ipl_info *info);
57
58#endif /* _ASM_S390_SCLP_H */
diff --git a/include/asm-s390/sections.h b/include/asm-s390/sections.h
deleted file mode 100644
index fbd9116eb17..00000000000
--- a/include/asm-s390/sections.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef _S390_SECTIONS_H
2#define _S390_SECTIONS_H
3
4#include <asm-generic/sections.h>
5
6extern char _eshared[], _ehead[];
7
8#endif
diff --git a/include/asm-s390/segment.h b/include/asm-s390/segment.h
deleted file mode 100644
index 8bfce3475b1..00000000000
--- a/include/asm-s390/segment.h
+++ /dev/null
@@ -1,4 +0,0 @@
1#ifndef _ASM_SEGMENT_H
2#define _ASM_SEGMENT_H
3
4#endif
diff --git a/include/asm-s390/sembuf.h b/include/asm-s390/sembuf.h
deleted file mode 100644
index 32626b0cac4..00000000000
--- a/include/asm-s390/sembuf.h
+++ /dev/null
@@ -1,29 +0,0 @@
1#ifndef _S390_SEMBUF_H
2#define _S390_SEMBUF_H
3
4/*
5 * The semid64_ds structure for S/390 architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 64-bit time_t to solve y2038 problem (for !__s390x__)
11 * - 2 miscellaneous 32-bit values
12 */
13
14struct semid64_ds {
15 struct ipc64_perm sem_perm; /* permissions .. see ipc.h */
16 __kernel_time_t sem_otime; /* last semop time */
17#ifndef __s390x__
18 unsigned long __unused1;
19#endif /* ! __s390x__ */
20 __kernel_time_t sem_ctime; /* last change time */
21#ifndef __s390x__
22 unsigned long __unused2;
23#endif /* ! __s390x__ */
24 unsigned long sem_nsems; /* no. of semaphores in array */
25 unsigned long __unused3;
26 unsigned long __unused4;
27};
28
29#endif /* _S390_SEMBUF_H */
diff --git a/include/asm-s390/setup.h b/include/asm-s390/setup.h
deleted file mode 100644
index 4ba14e463e8..00000000000
--- a/include/asm-s390/setup.h
+++ /dev/null
@@ -1,141 +0,0 @@
1/*
2 * include/asm-s390/setup.h
3 *
4 * S390 version
5 * Copyright IBM Corp. 1999,2006
6 */
7
8#ifndef _ASM_S390_SETUP_H
9#define _ASM_S390_SETUP_H
10
11#define COMMAND_LINE_SIZE 1024
12
13#define ARCH_COMMAND_LINE_SIZE 896
14
15#ifdef __KERNEL__
16
17#include <asm/types.h>
18
19#define PARMAREA 0x10400
20#define MEMORY_CHUNKS 256
21
22#ifndef __ASSEMBLY__
23
24#ifndef __s390x__
25#define IPL_DEVICE (*(unsigned long *) (0x10404))
26#define INITRD_START (*(unsigned long *) (0x1040C))
27#define INITRD_SIZE (*(unsigned long *) (0x10414))
28#else /* __s390x__ */
29#define IPL_DEVICE (*(unsigned long *) (0x10400))
30#define INITRD_START (*(unsigned long *) (0x10408))
31#define INITRD_SIZE (*(unsigned long *) (0x10410))
32#endif /* __s390x__ */
33#define COMMAND_LINE ((char *) (0x10480))
34
35#define CHUNK_READ_WRITE 0
36#define CHUNK_READ_ONLY 1
37
38struct mem_chunk {
39 unsigned long addr;
40 unsigned long size;
41 int type;
42};
43
44extern struct mem_chunk memory_chunk[];
45extern unsigned long real_memory_size;
46
47void detect_memory_layout(struct mem_chunk chunk[]);
48
49#ifdef CONFIG_S390_SWITCH_AMODE
50extern unsigned int switch_amode;
51#else
52#define switch_amode (0)
53#endif
54
55#ifdef CONFIG_S390_EXEC_PROTECT
56extern unsigned int s390_noexec;
57#else
58#define s390_noexec (0)
59#endif
60
61/*
62 * Machine features detected in head.S
63 */
64extern unsigned long machine_flags;
65
66#define MACHINE_FLAG_VM (1UL << 0)
67#define MACHINE_FLAG_IEEE (1UL << 1)
68#define MACHINE_FLAG_P390 (1UL << 2)
69#define MACHINE_FLAG_CSP (1UL << 3)
70#define MACHINE_FLAG_MVPG (1UL << 4)
71#define MACHINE_FLAG_DIAG44 (1UL << 5)
72#define MACHINE_FLAG_IDTE (1UL << 6)
73#define MACHINE_FLAG_DIAG9C (1UL << 7)
74#define MACHINE_FLAG_MVCOS (1UL << 8)
75#define MACHINE_FLAG_KVM (1UL << 9)
76#define MACHINE_FLAG_HPAGE (1UL << 10)
77#define MACHINE_FLAG_PFMF (1UL << 11)
78
79#define MACHINE_IS_VM (machine_flags & MACHINE_FLAG_VM)
80#define MACHINE_IS_KVM (machine_flags & MACHINE_FLAG_KVM)
81#define MACHINE_HAS_DIAG9C (machine_flags & MACHINE_FLAG_DIAG9C)
82
83#ifndef __s390x__
84#define MACHINE_HAS_IEEE (machine_flags & MACHINE_FLAG_IEEE)
85#define MACHINE_HAS_CSP (machine_flags & MACHINE_FLAG_CSP)
86#define MACHINE_HAS_IDTE (0)
87#define MACHINE_HAS_DIAG44 (1)
88#define MACHINE_HAS_MVPG (machine_flags & MACHINE_FLAG_MVPG)
89#define MACHINE_HAS_MVCOS (0)
90#define MACHINE_HAS_HPAGE (0)
91#define MACHINE_HAS_PFMF (0)
92#else /* __s390x__ */
93#define MACHINE_HAS_IEEE (1)
94#define MACHINE_HAS_CSP (1)
95#define MACHINE_HAS_IDTE (machine_flags & MACHINE_FLAG_IDTE)
96#define MACHINE_HAS_DIAG44 (machine_flags & MACHINE_FLAG_DIAG44)
97#define MACHINE_HAS_MVPG (1)
98#define MACHINE_HAS_MVCOS (machine_flags & MACHINE_FLAG_MVCOS)
99#define MACHINE_HAS_HPAGE (machine_flags & MACHINE_FLAG_HPAGE)
100#define MACHINE_HAS_PFMF (machine_flags & MACHINE_FLAG_PFMF)
101#endif /* __s390x__ */
102
103#define ZFCPDUMP_HSA_SIZE (32UL<<20)
104
105/*
106 * Console mode. Override with conmode=
107 */
108extern unsigned int console_mode;
109extern unsigned int console_devno;
110extern unsigned int console_irq;
111
112extern char vmhalt_cmd[];
113extern char vmpoff_cmd[];
114
115#define CONSOLE_IS_UNDEFINED (console_mode == 0)
116#define CONSOLE_IS_SCLP (console_mode == 1)
117#define CONSOLE_IS_3215 (console_mode == 2)
118#define CONSOLE_IS_3270 (console_mode == 3)
119#define SET_CONSOLE_SCLP do { console_mode = 1; } while (0)
120#define SET_CONSOLE_3215 do { console_mode = 2; } while (0)
121#define SET_CONSOLE_3270 do { console_mode = 3; } while (0)
122
123#define NSS_NAME_SIZE 8
124extern char kernel_nss_name[];
125
126#else /* __ASSEMBLY__ */
127
128#ifndef __s390x__
129#define IPL_DEVICE 0x10404
130#define INITRD_START 0x1040C
131#define INITRD_SIZE 0x10414
132#else /* __s390x__ */
133#define IPL_DEVICE 0x10400
134#define INITRD_START 0x10408
135#define INITRD_SIZE 0x10410
136#endif /* __s390x__ */
137#define COMMAND_LINE 0x10480
138
139#endif /* __ASSEMBLY__ */
140#endif /* __KERNEL__ */
141#endif /* _ASM_S390_SETUP_H */
diff --git a/include/asm-s390/sfp-machine.h b/include/asm-s390/sfp-machine.h
deleted file mode 100644
index 4e16aede4b0..00000000000
--- a/include/asm-s390/sfp-machine.h
+++ /dev/null
@@ -1,142 +0,0 @@
1/* Machine-dependent software floating-point definitions.
2 S/390 kernel version.
3 Copyright (C) 1997,1998,1999 Free Software Foundation, Inc.
4 This file is part of the GNU C Library.
5 Contributed by Richard Henderson (rth@cygnus.com),
6 Jakub Jelinek (jj@ultra.linux.cz),
7 David S. Miller (davem@redhat.com) and
8 Peter Maydell (pmaydell@chiark.greenend.org.uk).
9
10 The GNU C Library is free software; you can redistribute it and/or
11 modify it under the terms of the GNU Library General Public License as
12 published by the Free Software Foundation; either version 2 of the
13 License, or (at your option) any later version.
14
15 The GNU C Library is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 Library General Public License for more details.
19
20 You should have received a copy of the GNU Library General Public
21 License along with the GNU C Library; see the file COPYING.LIB. If
22 not, write to the Free Software Foundation, Inc.,
23 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24
25#ifndef _SFP_MACHINE_H
26#define _SFP_MACHINE_H
27
28
29#define _FP_W_TYPE_SIZE 32
30#define _FP_W_TYPE unsigned int
31#define _FP_WS_TYPE signed int
32#define _FP_I_TYPE int
33
34#define _FP_MUL_MEAT_S(R,X,Y) \
35 _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm)
36#define _FP_MUL_MEAT_D(R,X,Y) \
37 _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
38#define _FP_MUL_MEAT_Q(R,X,Y) \
39 _FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
40
41#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_udiv(S,R,X,Y)
42#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y)
43#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y)
44
45#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1)
46#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1), -1
47#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1
48#define _FP_NANSIGN_S 0
49#define _FP_NANSIGN_D 0
50#define _FP_NANSIGN_Q 0
51
52#define _FP_KEEPNANFRACP 1
53
54/*
55 * If one NaN is signaling and the other is not,
56 * we choose that one, otherwise we choose X.
57 */
58#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
59 do { \
60 if ((_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs) \
61 && !(_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs)) \
62 { \
63 R##_s = Y##_s; \
64 _FP_FRAC_COPY_##wc(R,Y); \
65 } \
66 else \
67 { \
68 R##_s = X##_s; \
69 _FP_FRAC_COPY_##wc(R,X); \
70 } \
71 R##_c = FP_CLS_NAN; \
72 } while (0)
73
74/* Some assembly to speed things up. */
75#define __FP_FRAC_ADD_3(r2,r1,r0,x2,x1,x0,y2,y1,y0) ({ \
76 unsigned int __r2 = (x2) + (y2); \
77 unsigned int __r1 = (x1); \
78 unsigned int __r0 = (x0); \
79 asm volatile( \
80 " alr %2,%3\n" \
81 " brc 12,0f\n" \
82 " lhi 0,1\n" \
83 " alr %1,0\n" \
84 " brc 12,0f\n" \
85 " alr %0,0\n" \
86 "0:" \
87 : "+&d" (__r2), "+&d" (__r1), "+&d" (__r0) \
88 : "d" (y0), "i" (1) : "cc", "0" ); \
89 asm volatile( \
90 " alr %1,%2\n" \
91 " brc 12,0f\n" \
92 " ahi %0,1\n" \
93 "0:" \
94 : "+&d" (__r2), "+&d" (__r1) \
95 : "d" (y1) : "cc"); \
96 (r2) = __r2; \
97 (r1) = __r1; \
98 (r0) = __r0; \
99})
100
101#define __FP_FRAC_SUB_3(r2,r1,r0,x2,x1,x0,y2,y1,y0) ({ \
102 unsigned int __r2 = (x2) - (y2); \
103 unsigned int __r1 = (x1); \
104 unsigned int __r0 = (x0); \
105 asm volatile( \
106 " slr %2,%3\n" \
107 " brc 3,0f\n" \
108 " lhi 0,1\n" \
109 " slr %1,0\n" \
110 " brc 3,0f\n" \
111 " slr %0,0\n" \
112 "0:" \
113 : "+&d" (__r2), "+&d" (__r1), "+&d" (__r0) \
114 : "d" (y0) : "cc", "0"); \
115 asm volatile( \
116 " slr %1,%2\n" \
117 " brc 3,0f\n" \
118 " ahi %0,-1\n" \
119 "0:" \
120 : "+&d" (__r2), "+&d" (__r1) \
121 : "d" (y1) : "cc"); \
122 (r2) = __r2; \
123 (r1) = __r1; \
124 (r0) = __r0; \
125})
126
127#define __FP_FRAC_DEC_3(x2,x1,x0,y2,y1,y0) __FP_FRAC_SUB_3(x2,x1,x0,x2,x1,x0,y2,y1,y0)
128
129/* Obtain the current rounding mode. */
130#define FP_ROUNDMODE mode
131
132/* Exception flags. */
133#define FP_EX_INVALID 0x800000
134#define FP_EX_DIVZERO 0x400000
135#define FP_EX_OVERFLOW 0x200000
136#define FP_EX_UNDERFLOW 0x100000
137#define FP_EX_INEXACT 0x080000
138
139/* We write the results always */
140#define FP_INHIBIT_RESULTS 0
141
142#endif
diff --git a/include/asm-s390/sfp-util.h b/include/asm-s390/sfp-util.h
deleted file mode 100644
index 0addc6466d9..00000000000
--- a/include/asm-s390/sfp-util.h
+++ /dev/null
@@ -1,77 +0,0 @@
1#include <linux/kernel.h>
2#include <linux/sched.h>
3#include <linux/types.h>
4#include <asm/byteorder.h>
5
6#define add_ssaaaa(sh, sl, ah, al, bh, bl) ({ \
7 unsigned int __sh = (ah); \
8 unsigned int __sl = (al); \
9 asm volatile( \
10 " alr %1,%3\n" \
11 " brc 12,0f\n" \
12 " ahi %0,1\n" \
13 "0: alr %0,%2" \
14 : "+&d" (__sh), "+d" (__sl) \
15 : "d" (bh), "d" (bl) : "cc"); \
16 (sh) = __sh; \
17 (sl) = __sl; \
18})
19
20#define sub_ddmmss(sh, sl, ah, al, bh, bl) ({ \
21 unsigned int __sh = (ah); \
22 unsigned int __sl = (al); \
23 asm volatile( \
24 " slr %1,%3\n" \
25 " brc 3,0f\n" \
26 " ahi %0,-1\n" \
27 "0: slr %0,%2" \
28 : "+&d" (__sh), "+d" (__sl) \
29 : "d" (bh), "d" (bl) : "cc"); \
30 (sh) = __sh; \
31 (sl) = __sl; \
32})
33
34/* a umul b = a mul b + (a>=2<<31) ? b<<32:0 + (b>=2<<31) ? a<<32:0 */
35#define umul_ppmm(wh, wl, u, v) ({ \
36 unsigned int __wh = u; \
37 unsigned int __wl = v; \
38 asm volatile( \
39 " ltr 1,%0\n" \
40 " mr 0,%1\n" \
41 " jnm 0f\n" \
42 " alr 0,%1\n" \
43 "0: ltr %1,%1\n" \
44 " jnm 1f\n" \
45 " alr 0,%0\n" \
46 "1: lr %0,0\n" \
47 " lr %1,1\n" \
48 : "+d" (__wh), "+d" (__wl) \
49 : : "0", "1", "cc"); \
50 wh = __wh; \
51 wl = __wl; \
52})
53
54#ifdef __s390x__
55#define udiv_qrnnd(q, r, n1, n0, d) \
56 do { unsigned long __n; \
57 unsigned int __r, __d; \
58 __n = ((unsigned long)(n1) << 32) + n0; \
59 __d = (d); \
60 (q) = __n / __d; \
61 (r) = __n % __d; \
62 } while (0)
63#else
64#define udiv_qrnnd(q, r, n1, n0, d) \
65 do { unsigned int __r; \
66 (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \
67 (r) = __r; \
68 } while (0)
69extern unsigned long __udiv_qrnnd (unsigned int *, unsigned int,
70 unsigned int , unsigned int);
71#endif
72
73#define UDIV_NEEDS_NORMALIZATION 0
74
75#define abort() return 0
76
77#define __BYTE_ORDER __BIG_ENDIAN
diff --git a/include/asm-s390/shmbuf.h b/include/asm-s390/shmbuf.h
deleted file mode 100644
index eed2e280ce3..00000000000
--- a/include/asm-s390/shmbuf.h
+++ /dev/null
@@ -1,48 +0,0 @@
1#ifndef _S390_SHMBUF_H
2#define _S390_SHMBUF_H
3
4/*
5 * The shmid64_ds structure for S/390 architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 64-bit time_t to solve y2038 problem (for !__s390x__)
11 * - 2 miscellaneous 32-bit values
12 */
13
14struct shmid64_ds {
15 struct ipc64_perm shm_perm; /* operation perms */
16 size_t shm_segsz; /* size of segment (bytes) */
17 __kernel_time_t shm_atime; /* last attach time */
18#ifndef __s390x__
19 unsigned long __unused1;
20#endif /* ! __s390x__ */
21 __kernel_time_t shm_dtime; /* last detach time */
22#ifndef __s390x__
23 unsigned long __unused2;
24#endif /* ! __s390x__ */
25 __kernel_time_t shm_ctime; /* last change time */
26#ifndef __s390x__
27 unsigned long __unused3;
28#endif /* ! __s390x__ */
29 __kernel_pid_t shm_cpid; /* pid of creator */
30 __kernel_pid_t shm_lpid; /* pid of last operator */
31 unsigned long shm_nattch; /* no. of current attaches */
32 unsigned long __unused4;
33 unsigned long __unused5;
34};
35
36struct shminfo64 {
37 unsigned long shmmax;
38 unsigned long shmmin;
39 unsigned long shmmni;
40 unsigned long shmseg;
41 unsigned long shmall;
42 unsigned long __unused1;
43 unsigned long __unused2;
44 unsigned long __unused3;
45 unsigned long __unused4;
46};
47
48#endif /* _S390_SHMBUF_H */
diff --git a/include/asm-s390/shmparam.h b/include/asm-s390/shmparam.h
deleted file mode 100644
index c2e0c0508e7..00000000000
--- a/include/asm-s390/shmparam.h
+++ /dev/null
@@ -1,13 +0,0 @@
1/*
2 * include/asm-s390/shmparam.h
3 *
4 * S390 version
5 *
6 * Derived from "include/asm-i386/shmparam.h"
7 */
8#ifndef _ASM_S390_SHMPARAM_H
9#define _ASM_S390_SHMPARAM_H
10
11#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */
12
13#endif /* _ASM_S390_SHMPARAM_H */
diff --git a/include/asm-s390/sigcontext.h b/include/asm-s390/sigcontext.h
deleted file mode 100644
index aeb6e0b1332..00000000000
--- a/include/asm-s390/sigcontext.h
+++ /dev/null
@@ -1,71 +0,0 @@
1/*
2 * include/asm-s390/sigcontext.h
3 *
4 * S390 version
5 * Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 */
7
8#ifndef _ASM_S390_SIGCONTEXT_H
9#define _ASM_S390_SIGCONTEXT_H
10
11#include <linux/compiler.h>
12
13#define __NUM_GPRS 16
14#define __NUM_FPRS 16
15#define __NUM_ACRS 16
16
17#ifndef __s390x__
18
19/* Has to be at least _NSIG_WORDS from asm/signal.h */
20#define _SIGCONTEXT_NSIG 64
21#define _SIGCONTEXT_NSIG_BPW 32
22/* Size of stack frame allocated when calling signal handler. */
23#define __SIGNAL_FRAMESIZE 96
24
25#else /* __s390x__ */
26
27/* Has to be at least _NSIG_WORDS from asm/signal.h */
28#define _SIGCONTEXT_NSIG 64
29#define _SIGCONTEXT_NSIG_BPW 64
30/* Size of stack frame allocated when calling signal handler. */
31#define __SIGNAL_FRAMESIZE 160
32
33#endif /* __s390x__ */
34
35#define _SIGCONTEXT_NSIG_WORDS (_SIGCONTEXT_NSIG / _SIGCONTEXT_NSIG_BPW)
36#define _SIGMASK_COPY_SIZE (sizeof(unsigned long)*_SIGCONTEXT_NSIG_WORDS)
37
38typedef struct
39{
40 unsigned long mask;
41 unsigned long addr;
42} __attribute__ ((aligned(8))) _psw_t;
43
44typedef struct
45{
46 _psw_t psw;
47 unsigned long gprs[__NUM_GPRS];
48 unsigned int acrs[__NUM_ACRS];
49} _s390_regs_common;
50
51typedef struct
52{
53 unsigned int fpc;
54 double fprs[__NUM_FPRS];
55} _s390_fp_regs;
56
57typedef struct
58{
59 _s390_regs_common regs;
60 _s390_fp_regs fpregs;
61} _sigregs;
62
63struct sigcontext
64{
65 unsigned long oldmask[_SIGCONTEXT_NSIG_WORDS];
66 _sigregs __user *sregs;
67};
68
69
70#endif
71
diff --git a/include/asm-s390/siginfo.h b/include/asm-s390/siginfo.h
deleted file mode 100644
index e0ff1ab054b..00000000000
--- a/include/asm-s390/siginfo.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/*
2 * include/asm-s390/siginfo.h
3 *
4 * S390 version
5 *
6 * Derived from "include/asm-i386/siginfo.h"
7 */
8
9#ifndef _S390_SIGINFO_H
10#define _S390_SIGINFO_H
11
12#ifdef __s390x__
13#define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
14#endif
15
16#include <asm-generic/siginfo.h>
17
18#endif
diff --git a/include/asm-s390/signal.h b/include/asm-s390/signal.h
deleted file mode 100644
index f6cfddb278c..00000000000
--- a/include/asm-s390/signal.h
+++ /dev/null
@@ -1,172 +0,0 @@
1/*
2 * include/asm-s390/signal.h
3 *
4 * S390 version
5 *
6 * Derived from "include/asm-i386/signal.h"
7 */
8
9#ifndef _ASMS390_SIGNAL_H
10#define _ASMS390_SIGNAL_H
11
12#include <linux/types.h>
13#include <linux/time.h>
14
15/* Avoid too many header ordering problems. */
16struct siginfo;
17struct pt_regs;
18
19#ifdef __KERNEL__
20/* Most things should be clean enough to redefine this at will, if care
21 is taken to make libc match. */
22#include <asm/sigcontext.h>
23#define _NSIG _SIGCONTEXT_NSIG
24#define _NSIG_BPW _SIGCONTEXT_NSIG_BPW
25#define _NSIG_WORDS _SIGCONTEXT_NSIG_WORDS
26
27typedef unsigned long old_sigset_t; /* at least 32 bits */
28
29typedef struct {
30 unsigned long sig[_NSIG_WORDS];
31} sigset_t;
32
33#else
34/* Here we must cater to libcs that poke about in kernel headers. */
35
36#define NSIG 32
37typedef unsigned long sigset_t;
38
39#endif /* __KERNEL__ */
40
41#define SIGHUP 1
42#define SIGINT 2
43#define SIGQUIT 3
44#define SIGILL 4
45#define SIGTRAP 5
46#define SIGABRT 6
47#define SIGIOT 6
48#define SIGBUS 7
49#define SIGFPE 8
50#define SIGKILL 9
51#define SIGUSR1 10
52#define SIGSEGV 11
53#define SIGUSR2 12
54#define SIGPIPE 13
55#define SIGALRM 14
56#define SIGTERM 15
57#define SIGSTKFLT 16
58#define SIGCHLD 17
59#define SIGCONT 18
60#define SIGSTOP 19
61#define SIGTSTP 20
62#define SIGTTIN 21
63#define SIGTTOU 22
64#define SIGURG 23
65#define SIGXCPU 24
66#define SIGXFSZ 25
67#define SIGVTALRM 26
68#define SIGPROF 27
69#define SIGWINCH 28
70#define SIGIO 29
71#define SIGPOLL SIGIO
72/*
73#define SIGLOST 29
74*/
75#define SIGPWR 30
76#define SIGSYS 31
77#define SIGUNUSED 31
78
79/* These should not be considered constants from userland. */
80#define SIGRTMIN 32
81#define SIGRTMAX _NSIG
82
83/*
84 * SA_FLAGS values:
85 *
86 * SA_ONSTACK indicates that a registered stack_t will be used.
87 * SA_RESTART flag to get restarting signals (which were the default long ago)
88 * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
89 * SA_RESETHAND clears the handler when the signal is delivered.
90 * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
91 * SA_NODEFER prevents the current signal from being masked in the handler.
92 *
93 * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
94 * Unix names RESETHAND and NODEFER respectively.
95 */
96#define SA_NOCLDSTOP 0x00000001
97#define SA_NOCLDWAIT 0x00000002
98#define SA_SIGINFO 0x00000004
99#define SA_ONSTACK 0x08000000
100#define SA_RESTART 0x10000000
101#define SA_NODEFER 0x40000000
102#define SA_RESETHAND 0x80000000
103
104#define SA_NOMASK SA_NODEFER
105#define SA_ONESHOT SA_RESETHAND
106
107#define SA_RESTORER 0x04000000
108
109/*
110 * sigaltstack controls
111 */
112#define SS_ONSTACK 1
113#define SS_DISABLE 2
114
115#define MINSIGSTKSZ 2048
116#define SIGSTKSZ 8192
117
118#include <asm-generic/signal.h>
119
120#ifdef __KERNEL__
121struct old_sigaction {
122 __sighandler_t sa_handler;
123 old_sigset_t sa_mask;
124 unsigned long sa_flags;
125 void (*sa_restorer)(void);
126};
127
128struct sigaction {
129 __sighandler_t sa_handler;
130 unsigned long sa_flags;
131 void (*sa_restorer)(void);
132 sigset_t sa_mask; /* mask last for extensibility */
133};
134
135struct k_sigaction {
136 struct sigaction sa;
137};
138
139#define ptrace_signal_deliver(regs, cookie) do { } while (0)
140
141#else
142/* Here we must cater to libcs that poke about in kernel headers. */
143
144struct sigaction {
145 union {
146 __sighandler_t _sa_handler;
147 void (*_sa_sigaction)(int, struct siginfo *, void *);
148 } _u;
149#ifndef __s390x__ /* lovely */
150 sigset_t sa_mask;
151 unsigned long sa_flags;
152 void (*sa_restorer)(void);
153#else /* __s390x__ */
154 unsigned long sa_flags;
155 void (*sa_restorer)(void);
156 sigset_t sa_mask;
157#endif /* __s390x__ */
158};
159
160#define sa_handler _u._sa_handler
161#define sa_sigaction _u._sa_sigaction
162
163#endif /* __KERNEL__ */
164
165typedef struct sigaltstack {
166 void __user *ss_sp;
167 int ss_flags;
168 size_t ss_size;
169} stack_t;
170
171
172#endif
diff --git a/include/asm-s390/sigp.h b/include/asm-s390/sigp.h
deleted file mode 100644
index e16d56f8dfe..00000000000
--- a/include/asm-s390/sigp.h
+++ /dev/null
@@ -1,126 +0,0 @@
1/*
2 * include/asm-s390/sigp.h
3 *
4 * S390 version
5 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
7 * Martin Schwidefsky (schwidefsky@de.ibm.com)
8 * Heiko Carstens (heiko.carstens@de.ibm.com)
9 *
10 * sigp.h by D.J. Barrow (c) IBM 1999
11 * contains routines / structures for signalling other S/390 processors in an
12 * SMP configuration.
13 */
14
15#ifndef __SIGP__
16#define __SIGP__
17
18#include <asm/ptrace.h>
19#include <asm/atomic.h>
20
21/* get real cpu address from logical cpu number */
22extern volatile int __cpu_logical_map[];
23
24typedef enum
25{
26 sigp_unassigned=0x0,
27 sigp_sense,
28 sigp_external_call,
29 sigp_emergency_signal,
30 sigp_start,
31 sigp_stop,
32 sigp_restart,
33 sigp_unassigned1,
34 sigp_unassigned2,
35 sigp_stop_and_store_status,
36 sigp_unassigned3,
37 sigp_initial_cpu_reset,
38 sigp_cpu_reset,
39 sigp_set_prefix,
40 sigp_store_status_at_address,
41 sigp_store_extended_status_at_address
42} sigp_order_code;
43
44typedef __u32 sigp_status_word;
45
46typedef enum
47{
48 sigp_order_code_accepted=0,
49 sigp_status_stored,
50 sigp_busy,
51 sigp_not_operational
52} sigp_ccode;
53
54
55/*
56 * Definitions for the external call
57 */
58
59/* 'Bit' signals, asynchronous */
60typedef enum
61{
62 ec_schedule=0,
63 ec_call_function,
64 ec_bit_last
65} ec_bit_sig;
66
67/*
68 * Signal processor
69 */
70static inline sigp_ccode
71signal_processor(__u16 cpu_addr, sigp_order_code order_code)
72{
73 register unsigned long reg1 asm ("1") = 0;
74 sigp_ccode ccode;
75
76 asm volatile(
77 " sigp %1,%2,0(%3)\n"
78 " ipm %0\n"
79 " srl %0,28\n"
80 : "=d" (ccode)
81 : "d" (reg1), "d" (__cpu_logical_map[cpu_addr]),
82 "a" (order_code) : "cc" , "memory");
83 return ccode;
84}
85
86/*
87 * Signal processor with parameter
88 */
89static inline sigp_ccode
90signal_processor_p(__u32 parameter, __u16 cpu_addr, sigp_order_code order_code)
91{
92 register unsigned int reg1 asm ("1") = parameter;
93 sigp_ccode ccode;
94
95 asm volatile(
96 " sigp %1,%2,0(%3)\n"
97 " ipm %0\n"
98 " srl %0,28\n"
99 : "=d" (ccode)
100 : "d" (reg1), "d" (__cpu_logical_map[cpu_addr]),
101 "a" (order_code) : "cc" , "memory");
102 return ccode;
103}
104
105/*
106 * Signal processor with parameter and return status
107 */
108static inline sigp_ccode
109signal_processor_ps(__u32 *statusptr, __u32 parameter, __u16 cpu_addr,
110 sigp_order_code order_code)
111{
112 register unsigned int reg1 asm ("1") = parameter;
113 sigp_ccode ccode;
114
115 asm volatile(
116 " sigp %1,%2,0(%3)\n"
117 " ipm %0\n"
118 " srl %0,28\n"
119 : "=d" (ccode), "+d" (reg1)
120 : "d" (__cpu_logical_map[cpu_addr]), "a" (order_code)
121 : "cc" , "memory");
122 *statusptr = reg1;
123 return ccode;
124}
125
126#endif /* __SIGP__ */
diff --git a/include/asm-s390/smp.h b/include/asm-s390/smp.h
deleted file mode 100644
index ae89cf2478f..00000000000
--- a/include/asm-s390/smp.h
+++ /dev/null
@@ -1,116 +0,0 @@
1/*
2 * include/asm-s390/smp.h
3 *
4 * S390 version
5 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
7 * Martin Schwidefsky (schwidefsky@de.ibm.com)
8 * Heiko Carstens (heiko.carstens@de.ibm.com)
9 */
10#ifndef __ASM_SMP_H
11#define __ASM_SMP_H
12
13#include <linux/threads.h>
14#include <linux/cpumask.h>
15#include <linux/bitops.h>
16
17#if defined(__KERNEL__) && defined(CONFIG_SMP) && !defined(__ASSEMBLY__)
18
19#include <asm/lowcore.h>
20#include <asm/sigp.h>
21#include <asm/ptrace.h>
22#include <asm/system.h>
23
24/*
25 s390 specific smp.c headers
26 */
27typedef struct
28{
29 int intresting;
30 sigp_ccode ccode;
31 __u32 status;
32 __u16 cpu;
33} sigp_info;
34
35extern void machine_restart_smp(char *);
36extern void machine_halt_smp(void);
37extern void machine_power_off_smp(void);
38
39#define NO_PROC_ID 0xFF /* No processor magic marker */
40
41/*
42 * This magic constant controls our willingness to transfer
43 * a process across CPUs. Such a transfer incurs misses on the L1
44 * cache, and on a P6 or P5 with multiple L2 caches L2 hits. My
45 * gut feeling is this will vary by board in value. For a board
46 * with separate L2 cache it probably depends also on the RSS, and
47 * for a board with shared L2 cache it ought to decay fast as other
48 * processes are run.
49 */
50
51#define PROC_CHANGE_PENALTY 20 /* Schedule penalty */
52
53#define raw_smp_processor_id() (S390_lowcore.cpu_data.cpu_nr)
54
55static inline __u16 hard_smp_processor_id(void)
56{
57 return stap();
58}
59
60/*
61 * returns 1 if cpu is in stopped/check stopped state or not operational
62 * returns 0 otherwise
63 */
64static inline int
65smp_cpu_not_running(int cpu)
66{
67 __u32 status;
68
69 switch (signal_processor_ps(&status, 0, cpu, sigp_sense)) {
70 case sigp_order_code_accepted:
71 case sigp_status_stored:
72 /* Check for stopped and check stop state */
73 if (status & 0x50)
74 return 1;
75 break;
76 case sigp_not_operational:
77 return 1;
78 default:
79 break;
80 }
81 return 0;
82}
83
84#define cpu_logical_map(cpu) (cpu)
85
86extern int __cpu_disable (void);
87extern void __cpu_die (unsigned int cpu);
88extern void cpu_die (void) __attribute__ ((noreturn));
89extern int __cpu_up (unsigned int cpu);
90
91extern struct mutex smp_cpu_state_mutex;
92extern int smp_cpu_polarization[];
93
94extern int smp_call_function_mask(cpumask_t mask, void (*func)(void *),
95 void *info, int wait);
96#endif
97
98#ifndef CONFIG_SMP
99static inline void smp_send_stop(void)
100{
101 /* Disable all interrupts/machine checks */
102 __load_psw_mask(psw_kernel_bits & ~PSW_MASK_MCHECK);
103}
104
105#define hard_smp_processor_id() 0
106#define smp_cpu_not_running(cpu) 1
107#endif
108
109#ifdef CONFIG_HOTPLUG_CPU
110extern int smp_rescan_cpus(void);
111#else
112static inline int smp_rescan_cpus(void) { return 0; }
113#endif
114
115extern union save_area *zfcpdump_save_areas[NR_CPUS + 1];
116#endif
diff --git a/include/asm-s390/socket.h b/include/asm-s390/socket.h
deleted file mode 100644
index c786ab623b2..00000000000
--- a/include/asm-s390/socket.h
+++ /dev/null
@@ -1,65 +0,0 @@
1/*
2 * include/asm-s390/socket.h
3 *
4 * S390 version
5 *
6 * Derived from "include/asm-i386/socket.h"
7 */
8
9#ifndef _ASM_SOCKET_H
10#define _ASM_SOCKET_H
11
12#include <asm/sockios.h>
13
14/* For setsockopt(2) */
15#define SOL_SOCKET 1
16
17#define SO_DEBUG 1
18#define SO_REUSEADDR 2
19#define SO_TYPE 3
20#define SO_ERROR 4
21#define SO_DONTROUTE 5
22#define SO_BROADCAST 6
23#define SO_SNDBUF 7
24#define SO_RCVBUF 8
25#define SO_SNDBUFFORCE 32
26#define SO_RCVBUFFORCE 33
27#define SO_KEEPALIVE 9
28#define SO_OOBINLINE 10
29#define SO_NO_CHECK 11
30#define SO_PRIORITY 12
31#define SO_LINGER 13
32#define SO_BSDCOMPAT 14
33/* To add :#define SO_REUSEPORT 15 */
34#define SO_PASSCRED 16
35#define SO_PEERCRED 17
36#define SO_RCVLOWAT 18
37#define SO_SNDLOWAT 19
38#define SO_RCVTIMEO 20
39#define SO_SNDTIMEO 21
40
41/* Security levels - as per NRL IPv6 - don't actually do anything */
42#define SO_SECURITY_AUTHENTICATION 22
43#define SO_SECURITY_ENCRYPTION_TRANSPORT 23
44#define SO_SECURITY_ENCRYPTION_NETWORK 24
45
46#define SO_BINDTODEVICE 25
47
48/* Socket filtering */
49#define SO_ATTACH_FILTER 26
50#define SO_DETACH_FILTER 27
51
52#define SO_PEERNAME 28
53#define SO_TIMESTAMP 29
54#define SCM_TIMESTAMP SO_TIMESTAMP
55
56#define SO_ACCEPTCONN 30
57
58#define SO_PEERSEC 31
59#define SO_PASSSEC 34
60#define SO_TIMESTAMPNS 35
61#define SCM_TIMESTAMPNS SO_TIMESTAMPNS
62
63#define SO_MARK 36
64
65#endif /* _ASM_SOCKET_H */
diff --git a/include/asm-s390/sockios.h b/include/asm-s390/sockios.h
deleted file mode 100644
index f4fc16c7da5..00000000000
--- a/include/asm-s390/sockios.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * include/asm-s390/sockios.h
3 *
4 * S390 version
5 *
6 * Derived from "include/asm-i386/sockios.h"
7 */
8
9#ifndef __ARCH_S390_SOCKIOS__
10#define __ARCH_S390_SOCKIOS__
11
12/* Socket-level I/O control calls. */
13#define FIOSETOWN 0x8901
14#define SIOCSPGRP 0x8902
15#define FIOGETOWN 0x8903
16#define SIOCGPGRP 0x8904
17#define SIOCATMARK 0x8905
18#define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */
19#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */
20
21#endif
diff --git a/include/asm-s390/sparsemem.h b/include/asm-s390/sparsemem.h
deleted file mode 100644
index 545d219e6a2..00000000000
--- a/include/asm-s390/sparsemem.h
+++ /dev/null
@@ -1,18 +0,0 @@
1#ifndef _ASM_S390_SPARSEMEM_H
2#define _ASM_S390_SPARSEMEM_H
3
4#ifdef CONFIG_64BIT
5
6#define SECTION_SIZE_BITS 28
7#define MAX_PHYSADDR_BITS 42
8#define MAX_PHYSMEM_BITS 42
9
10#else
11
12#define SECTION_SIZE_BITS 25
13#define MAX_PHYSADDR_BITS 31
14#define MAX_PHYSMEM_BITS 31
15
16#endif /* CONFIG_64BIT */
17
18#endif /* _ASM_S390_SPARSEMEM_H */
diff --git a/include/asm-s390/spinlock.h b/include/asm-s390/spinlock.h
deleted file mode 100644
index df84ae96915..00000000000
--- a/include/asm-s390/spinlock.h
+++ /dev/null
@@ -1,178 +0,0 @@
1/*
2 * include/asm-s390/spinlock.h
3 *
4 * S390 version
5 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
7 *
8 * Derived from "include/asm-i386/spinlock.h"
9 */
10
11#ifndef __ASM_SPINLOCK_H
12#define __ASM_SPINLOCK_H
13
14#include <linux/smp.h>
15
16#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
17
18static inline int
19_raw_compare_and_swap(volatile unsigned int *lock,
20 unsigned int old, unsigned int new)
21{
22 asm volatile(
23 " cs %0,%3,%1"
24 : "=d" (old), "=Q" (*lock)
25 : "0" (old), "d" (new), "Q" (*lock)
26 : "cc", "memory" );
27 return old;
28}
29
30#else /* __GNUC__ */
31
32static inline int
33_raw_compare_and_swap(volatile unsigned int *lock,
34 unsigned int old, unsigned int new)
35{
36 asm volatile(
37 " cs %0,%3,0(%4)"
38 : "=d" (old), "=m" (*lock)
39 : "0" (old), "d" (new), "a" (lock), "m" (*lock)
40 : "cc", "memory" );
41 return old;
42}
43
44#endif /* __GNUC__ */
45
46/*
47 * Simple spin lock operations. There are two variants, one clears IRQ's
48 * on the local processor, one does not.
49 *
50 * We make no fairness assumptions. They have a cost.
51 *
52 * (the type definitions are in asm/spinlock_types.h)
53 */
54
55#define __raw_spin_is_locked(x) ((x)->owner_cpu != 0)
56#define __raw_spin_unlock_wait(lock) \
57 do { while (__raw_spin_is_locked(lock)) \
58 _raw_spin_relax(lock); } while (0)
59
60extern void _raw_spin_lock_wait(raw_spinlock_t *);
61extern void _raw_spin_lock_wait_flags(raw_spinlock_t *, unsigned long flags);
62extern int _raw_spin_trylock_retry(raw_spinlock_t *);
63extern void _raw_spin_relax(raw_spinlock_t *lock);
64
65static inline void __raw_spin_lock(raw_spinlock_t *lp)
66{
67 int old;
68
69 old = _raw_compare_and_swap(&lp->owner_cpu, 0, ~smp_processor_id());
70 if (likely(old == 0))
71 return;
72 _raw_spin_lock_wait(lp);
73}
74
75static inline void __raw_spin_lock_flags(raw_spinlock_t *lp,
76 unsigned long flags)
77{
78 int old;
79
80 old = _raw_compare_and_swap(&lp->owner_cpu, 0, ~smp_processor_id());
81 if (likely(old == 0))
82 return;
83 _raw_spin_lock_wait_flags(lp, flags);
84}
85
86static inline int __raw_spin_trylock(raw_spinlock_t *lp)
87{
88 int old;
89
90 old = _raw_compare_and_swap(&lp->owner_cpu, 0, ~smp_processor_id());
91 if (likely(old == 0))
92 return 1;
93 return _raw_spin_trylock_retry(lp);
94}
95
96static inline void __raw_spin_unlock(raw_spinlock_t *lp)
97{
98 _raw_compare_and_swap(&lp->owner_cpu, lp->owner_cpu, 0);
99}
100
101/*
102 * Read-write spinlocks, allowing multiple readers
103 * but only one writer.
104 *
105 * NOTE! it is quite common to have readers in interrupts
106 * but no interrupt writers. For those circumstances we
107 * can "mix" irq-safe locks - any writer needs to get a
108 * irq-safe write-lock, but readers can get non-irqsafe
109 * read-locks.
110 */
111
112/**
113 * read_can_lock - would read_trylock() succeed?
114 * @lock: the rwlock in question.
115 */
116#define __raw_read_can_lock(x) ((int)(x)->lock >= 0)
117
118/**
119 * write_can_lock - would write_trylock() succeed?
120 * @lock: the rwlock in question.
121 */
122#define __raw_write_can_lock(x) ((x)->lock == 0)
123
124extern void _raw_read_lock_wait(raw_rwlock_t *lp);
125extern int _raw_read_trylock_retry(raw_rwlock_t *lp);
126extern void _raw_write_lock_wait(raw_rwlock_t *lp);
127extern int _raw_write_trylock_retry(raw_rwlock_t *lp);
128
129static inline void __raw_read_lock(raw_rwlock_t *rw)
130{
131 unsigned int old;
132 old = rw->lock & 0x7fffffffU;
133 if (_raw_compare_and_swap(&rw->lock, old, old + 1) != old)
134 _raw_read_lock_wait(rw);
135}
136
137static inline void __raw_read_unlock(raw_rwlock_t *rw)
138{
139 unsigned int old, cmp;
140
141 old = rw->lock;
142 do {
143 cmp = old;
144 old = _raw_compare_and_swap(&rw->lock, old, old - 1);
145 } while (cmp != old);
146}
147
148static inline void __raw_write_lock(raw_rwlock_t *rw)
149{
150 if (unlikely(_raw_compare_and_swap(&rw->lock, 0, 0x80000000) != 0))
151 _raw_write_lock_wait(rw);
152}
153
154static inline void __raw_write_unlock(raw_rwlock_t *rw)
155{
156 _raw_compare_and_swap(&rw->lock, 0x80000000, 0);
157}
158
159static inline int __raw_read_trylock(raw_rwlock_t *rw)
160{
161 unsigned int old;
162 old = rw->lock & 0x7fffffffU;
163 if (likely(_raw_compare_and_swap(&rw->lock, old, old + 1) == old))
164 return 1;
165 return _raw_read_trylock_retry(rw);
166}
167
168static inline int __raw_write_trylock(raw_rwlock_t *rw)
169{
170 if (likely(_raw_compare_and_swap(&rw->lock, 0, 0x80000000) == 0))
171 return 1;
172 return _raw_write_trylock_retry(rw);
173}
174
175#define _raw_read_relax(lock) cpu_relax()
176#define _raw_write_relax(lock) cpu_relax()
177
178#endif /* __ASM_SPINLOCK_H */
diff --git a/include/asm-s390/spinlock_types.h b/include/asm-s390/spinlock_types.h
deleted file mode 100644
index 654abc40de0..00000000000
--- a/include/asm-s390/spinlock_types.h
+++ /dev/null
@@ -1,20 +0,0 @@
1#ifndef __ASM_SPINLOCK_TYPES_H
2#define __ASM_SPINLOCK_TYPES_H
3
4#ifndef __LINUX_SPINLOCK_TYPES_H
5# error "please don't include this file directly"
6#endif
7
8typedef struct {
9 volatile unsigned int owner_cpu;
10} __attribute__ ((aligned (4))) raw_spinlock_t;
11
12#define __RAW_SPIN_LOCK_UNLOCKED { 0 }
13
14typedef struct {
15 volatile unsigned int lock;
16} raw_rwlock_t;
17
18#define __RAW_RW_LOCK_UNLOCKED { 0 }
19
20#endif
diff --git a/include/asm-s390/stat.h b/include/asm-s390/stat.h
deleted file mode 100644
index d92959eebb6..00000000000
--- a/include/asm-s390/stat.h
+++ /dev/null
@@ -1,105 +0,0 @@
1/*
2 * include/asm-s390/stat.h
3 *
4 * S390 version
5 *
6 * Derived from "include/asm-i386/stat.h"
7 */
8
9#ifndef _S390_STAT_H
10#define _S390_STAT_H
11
12#ifndef __s390x__
13struct __old_kernel_stat {
14 unsigned short st_dev;
15 unsigned short st_ino;
16 unsigned short st_mode;
17 unsigned short st_nlink;
18 unsigned short st_uid;
19 unsigned short st_gid;
20 unsigned short st_rdev;
21 unsigned long st_size;
22 unsigned long st_atime;
23 unsigned long st_mtime;
24 unsigned long st_ctime;
25};
26
27struct stat {
28 unsigned short st_dev;
29 unsigned short __pad1;
30 unsigned long st_ino;
31 unsigned short st_mode;
32 unsigned short st_nlink;
33 unsigned short st_uid;
34 unsigned short st_gid;
35 unsigned short st_rdev;
36 unsigned short __pad2;
37 unsigned long st_size;
38 unsigned long st_blksize;
39 unsigned long st_blocks;
40 unsigned long st_atime;
41 unsigned long st_atime_nsec;
42 unsigned long st_mtime;
43 unsigned long st_mtime_nsec;
44 unsigned long st_ctime;
45 unsigned long st_ctime_nsec;
46 unsigned long __unused4;
47 unsigned long __unused5;
48};
49
50/* This matches struct stat64 in glibc2.1, hence the absolutely
51 * insane amounts of padding around dev_t's.
52 */
53struct stat64 {
54 unsigned long long st_dev;
55 unsigned int __pad1;
56#define STAT64_HAS_BROKEN_ST_INO 1
57 unsigned long __st_ino;
58 unsigned int st_mode;
59 unsigned int st_nlink;
60 unsigned long st_uid;
61 unsigned long st_gid;
62 unsigned long long st_rdev;
63 unsigned int __pad3;
64 long long st_size;
65 unsigned long st_blksize;
66 unsigned char __pad4[4];
67 unsigned long __pad5; /* future possible st_blocks high bits */
68 unsigned long st_blocks; /* Number 512-byte blocks allocated. */
69 unsigned long st_atime;
70 unsigned long st_atime_nsec;
71 unsigned long st_mtime;
72 unsigned long st_mtime_nsec;
73 unsigned long st_ctime;
74 unsigned long st_ctime_nsec; /* will be high 32 bits of ctime someday */
75 unsigned long long st_ino;
76};
77
78#else /* __s390x__ */
79
80struct stat {
81 unsigned long st_dev;
82 unsigned long st_ino;
83 unsigned long st_nlink;
84 unsigned int st_mode;
85 unsigned int st_uid;
86 unsigned int st_gid;
87 unsigned int __pad1;
88 unsigned long st_rdev;
89 unsigned long st_size;
90 unsigned long st_atime;
91 unsigned long st_atime_nsec;
92 unsigned long st_mtime;
93 unsigned long st_mtime_nsec;
94 unsigned long st_ctime;
95 unsigned long st_ctime_nsec;
96 unsigned long st_blksize;
97 long st_blocks;
98 unsigned long __unused[3];
99};
100
101#endif /* __s390x__ */
102
103#define STAT_HAVE_NSEC 1
104
105#endif
diff --git a/include/asm-s390/statfs.h b/include/asm-s390/statfs.h
deleted file mode 100644
index 099a4557919..00000000000
--- a/include/asm-s390/statfs.h
+++ /dev/null
@@ -1,71 +0,0 @@
1/*
2 * include/asm-s390/statfs.h
3 *
4 * S390 version
5 *
6 * Derived from "include/asm-i386/statfs.h"
7 */
8
9#ifndef _S390_STATFS_H
10#define _S390_STATFS_H
11
12#ifndef __s390x__
13#include <asm-generic/statfs.h>
14#else
15
16#ifndef __KERNEL_STRICT_NAMES
17
18#include <linux/types.h>
19
20typedef __kernel_fsid_t fsid_t;
21
22#endif
23
24/*
25 * This is ugly -- we're already 64-bit clean, so just duplicate the
26 * definitions.
27 */
28struct statfs {
29 int f_type;
30 int f_bsize;
31 long f_blocks;
32 long f_bfree;
33 long f_bavail;
34 long f_files;
35 long f_ffree;
36 __kernel_fsid_t f_fsid;
37 int f_namelen;
38 int f_frsize;
39 int f_spare[5];
40};
41
42struct statfs64 {
43 int f_type;
44 int f_bsize;
45 long f_blocks;
46 long f_bfree;
47 long f_bavail;
48 long f_files;
49 long f_ffree;
50 __kernel_fsid_t f_fsid;
51 int f_namelen;
52 int f_frsize;
53 int f_spare[5];
54};
55
56struct compat_statfs64 {
57 __u32 f_type;
58 __u32 f_bsize;
59 __u64 f_blocks;
60 __u64 f_bfree;
61 __u64 f_bavail;
62 __u64 f_files;
63 __u64 f_ffree;
64 __kernel_fsid_t f_fsid;
65 __u32 f_namelen;
66 __u32 f_frsize;
67 __u32 f_spare[5];
68};
69
70#endif /* __s390x__ */
71#endif
diff --git a/include/asm-s390/string.h b/include/asm-s390/string.h
deleted file mode 100644
index d074673a6d9..00000000000
--- a/include/asm-s390/string.h
+++ /dev/null
@@ -1,143 +0,0 @@
1/*
2 * include/asm-s390/string.h
3 *
4 * S390 version
5 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
7 */
8
9#ifndef _S390_STRING_H_
10#define _S390_STRING_H_
11
12#ifdef __KERNEL__
13
14#ifndef _LINUX_TYPES_H
15#include <linux/types.h>
16#endif
17
18#define __HAVE_ARCH_MEMCHR /* inline & arch function */
19#define __HAVE_ARCH_MEMCMP /* arch function */
20#define __HAVE_ARCH_MEMCPY /* gcc builtin & arch function */
21#define __HAVE_ARCH_MEMSCAN /* inline & arch function */
22#define __HAVE_ARCH_MEMSET /* gcc builtin & arch function */
23#define __HAVE_ARCH_STRCAT /* inline & arch function */
24#define __HAVE_ARCH_STRCMP /* arch function */
25#define __HAVE_ARCH_STRCPY /* inline & arch function */
26#define __HAVE_ARCH_STRLCAT /* arch function */
27#define __HAVE_ARCH_STRLCPY /* arch function */
28#define __HAVE_ARCH_STRLEN /* inline & arch function */
29#define __HAVE_ARCH_STRNCAT /* arch function */
30#define __HAVE_ARCH_STRNCPY /* arch function */
31#define __HAVE_ARCH_STRNLEN /* inline & arch function */
32#define __HAVE_ARCH_STRRCHR /* arch function */
33#define __HAVE_ARCH_STRSTR /* arch function */
34
35/* Prototypes for non-inlined arch strings functions. */
36extern int memcmp(const void *, const void *, size_t);
37extern void *memcpy(void *, const void *, size_t);
38extern void *memset(void *, int, size_t);
39extern int strcmp(const char *,const char *);
40extern size_t strlcat(char *, const char *, size_t);
41extern size_t strlcpy(char *, const char *, size_t);
42extern char *strncat(char *, const char *, size_t);
43extern char *strncpy(char *, const char *, size_t);
44extern char *strrchr(const char *, int);
45extern char *strstr(const char *, const char *);
46
47#undef __HAVE_ARCH_MEMMOVE
48#undef __HAVE_ARCH_STRCHR
49#undef __HAVE_ARCH_STRNCHR
50#undef __HAVE_ARCH_STRNCMP
51#undef __HAVE_ARCH_STRNICMP
52#undef __HAVE_ARCH_STRPBRK
53#undef __HAVE_ARCH_STRSEP
54#undef __HAVE_ARCH_STRSPN
55
56#if !defined(IN_ARCH_STRING_C)
57
58static inline void *memchr(const void * s, int c, size_t n)
59{
60 register int r0 asm("0") = (char) c;
61 const void *ret = s + n;
62
63 asm volatile(
64 "0: srst %0,%1\n"
65 " jo 0b\n"
66 " jl 1f\n"
67 " la %0,0\n"
68 "1:"
69 : "+a" (ret), "+&a" (s) : "d" (r0) : "cc");
70 return (void *) ret;
71}
72
73static inline void *memscan(void *s, int c, size_t n)
74{
75 register int r0 asm("0") = (char) c;
76 const void *ret = s + n;
77
78 asm volatile(
79 "0: srst %0,%1\n"
80 " jo 0b\n"
81 : "+a" (ret), "+&a" (s) : "d" (r0) : "cc");
82 return (void *) ret;
83}
84
85static inline char *strcat(char *dst, const char *src)
86{
87 register int r0 asm("0") = 0;
88 unsigned long dummy;
89 char *ret = dst;
90
91 asm volatile(
92 "0: srst %0,%1\n"
93 " jo 0b\n"
94 "1: mvst %0,%2\n"
95 " jo 1b"
96 : "=&a" (dummy), "+a" (dst), "+a" (src)
97 : "d" (r0), "0" (0) : "cc", "memory" );
98 return ret;
99}
100
101static inline char *strcpy(char *dst, const char *src)
102{
103 register int r0 asm("0") = 0;
104 char *ret = dst;
105
106 asm volatile(
107 "0: mvst %0,%1\n"
108 " jo 0b"
109 : "+&a" (dst), "+&a" (src) : "d" (r0)
110 : "cc", "memory");
111 return ret;
112}
113
114static inline size_t strlen(const char *s)
115{
116 register unsigned long r0 asm("0") = 0;
117 const char *tmp = s;
118
119 asm volatile(
120 "0: srst %0,%1\n"
121 " jo 0b"
122 : "+d" (r0), "+a" (tmp) : : "cc");
123 return r0 - (unsigned long) s;
124}
125
126static inline size_t strnlen(const char * s, size_t n)
127{
128 register int r0 asm("0") = 0;
129 const char *tmp = s;
130 const char *end = s + n;
131
132 asm volatile(
133 "0: srst %0,%1\n"
134 " jo 0b"
135 : "+a" (end), "+a" (tmp) : "d" (r0) : "cc");
136 return end - s;
137}
138
139#endif /* !IN_ARCH_STRING_C */
140
141#endif /* __KERNEL__ */
142
143#endif /* __S390_STRING_H_ */
diff --git a/include/asm-s390/suspend.h b/include/asm-s390/suspend.h
deleted file mode 100644
index 1f34580e67a..00000000000
--- a/include/asm-s390/suspend.h
+++ /dev/null
@@ -1,5 +0,0 @@
1#ifndef __ASM_S390_SUSPEND_H
2#define __ASM_S390_SUSPEND_H
3
4#endif
5
diff --git a/include/asm-s390/sysinfo.h b/include/asm-s390/sysinfo.h
deleted file mode 100644
index 79d01343f8b..00000000000
--- a/include/asm-s390/sysinfo.h
+++ /dev/null
@@ -1,121 +0,0 @@
1/*
2 * definition for store system information stsi
3 *
4 * Copyright IBM Corp. 2001,2008
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License (version 2 only)
8 * as published by the Free Software Foundation.
9 *
10 * Author(s): Ulrich Weigand <weigand@de.ibm.com>
11 * Christian Borntraeger <borntraeger@de.ibm.com>
12 */
13
14#ifndef __ASM_S390_SYSINFO_H
15#define __ASM_S390_SYSINFO_H
16
17struct sysinfo_1_1_1 {
18 char reserved_0[32];
19 char manufacturer[16];
20 char type[4];
21 char reserved_1[12];
22 char model_capacity[16];
23 char sequence[16];
24 char plant[4];
25 char model[16];
26 char model_perm_cap[16];
27 char model_temp_cap[16];
28 char model_cap_rating[4];
29 char model_perm_cap_rating[4];
30 char model_temp_cap_rating[4];
31};
32
33struct sysinfo_1_2_1 {
34 char reserved_0[80];
35 char sequence[16];
36 char plant[4];
37 char reserved_1[2];
38 unsigned short cpu_address;
39};
40
41struct sysinfo_1_2_2 {
42 char format;
43 char reserved_0[1];
44 unsigned short acc_offset;
45 char reserved_1[24];
46 unsigned int secondary_capability;
47 unsigned int capability;
48 unsigned short cpus_total;
49 unsigned short cpus_configured;
50 unsigned short cpus_standby;
51 unsigned short cpus_reserved;
52 unsigned short adjustment[0];
53};
54
55struct sysinfo_1_2_2_extension {
56 unsigned int alt_capability;
57 unsigned short alt_adjustment[0];
58};
59
60struct sysinfo_2_2_1 {
61 char reserved_0[80];
62 char sequence[16];
63 char plant[4];
64 unsigned short cpu_id;
65 unsigned short cpu_address;
66};
67
68struct sysinfo_2_2_2 {
69 char reserved_0[32];
70 unsigned short lpar_number;
71 char reserved_1;
72 unsigned char characteristics;
73 unsigned short cpus_total;
74 unsigned short cpus_configured;
75 unsigned short cpus_standby;
76 unsigned short cpus_reserved;
77 char name[8];
78 unsigned int caf;
79 char reserved_2[16];
80 unsigned short cpus_dedicated;
81 unsigned short cpus_shared;
82};
83
84#define LPAR_CHAR_DEDICATED (1 << 7)
85#define LPAR_CHAR_SHARED (1 << 6)
86#define LPAR_CHAR_LIMITED (1 << 5)
87
88struct sysinfo_3_2_2 {
89 char reserved_0[31];
90 unsigned char count;
91 struct {
92 char reserved_0[4];
93 unsigned short cpus_total;
94 unsigned short cpus_configured;
95 unsigned short cpus_standby;
96 unsigned short cpus_reserved;
97 char name[8];
98 unsigned int caf;
99 char cpi[16];
100 char reserved_1[24];
101
102 } vm[8];
103};
104
105static inline int stsi(void *sysinfo, int fc, int sel1, int sel2)
106{
107 register int r0 asm("0") = (fc << 28) | sel1;
108 register int r1 asm("1") = sel2;
109
110 asm volatile(
111 " stsi 0(%2)\n"
112 "0: jz 2f\n"
113 "1: lhi %0,%3\n"
114 "2:\n"
115 EX_TABLE(0b, 1b)
116 : "+d" (r0) : "d" (r1), "a" (sysinfo), "K" (-ENOSYS)
117 : "cc", "memory");
118 return r0;
119}
120
121#endif /* __ASM_S390_SYSINFO_H */
diff --git a/include/asm-s390/system.h b/include/asm-s390/system.h
deleted file mode 100644
index 819e7d99ca0..00000000000
--- a/include/asm-s390/system.h
+++ /dev/null
@@ -1,462 +0,0 @@
1/*
2 * include/asm-s390/system.h
3 *
4 * S390 version
5 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
7 *
8 * Derived from "include/asm-i386/system.h"
9 */
10
11#ifndef __ASM_SYSTEM_H
12#define __ASM_SYSTEM_H
13
14#include <linux/kernel.h>
15#include <asm/types.h>
16#include <asm/ptrace.h>
17#include <asm/setup.h>
18#include <asm/processor.h>
19#include <asm/lowcore.h>
20
21#ifdef __KERNEL__
22
23struct task_struct;
24
25extern struct task_struct *__switch_to(void *, void *);
26
27static inline void save_fp_regs(s390_fp_regs *fpregs)
28{
29 asm volatile(
30 " std 0,8(%1)\n"
31 " std 2,24(%1)\n"
32 " std 4,40(%1)\n"
33 " std 6,56(%1)"
34 : "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory");
35 if (!MACHINE_HAS_IEEE)
36 return;
37 asm volatile(
38 " stfpc 0(%1)\n"
39 " std 1,16(%1)\n"
40 " std 3,32(%1)\n"
41 " std 5,48(%1)\n"
42 " std 7,64(%1)\n"
43 " std 8,72(%1)\n"
44 " std 9,80(%1)\n"
45 " std 10,88(%1)\n"
46 " std 11,96(%1)\n"
47 " std 12,104(%1)\n"
48 " std 13,112(%1)\n"
49 " std 14,120(%1)\n"
50 " std 15,128(%1)\n"
51 : "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory");
52}
53
54static inline void restore_fp_regs(s390_fp_regs *fpregs)
55{
56 asm volatile(
57 " ld 0,8(%0)\n"
58 " ld 2,24(%0)\n"
59 " ld 4,40(%0)\n"
60 " ld 6,56(%0)"
61 : : "a" (fpregs), "m" (*fpregs));
62 if (!MACHINE_HAS_IEEE)
63 return;
64 asm volatile(
65 " lfpc 0(%0)\n"
66 " ld 1,16(%0)\n"
67 " ld 3,32(%0)\n"
68 " ld 5,48(%0)\n"
69 " ld 7,64(%0)\n"
70 " ld 8,72(%0)\n"
71 " ld 9,80(%0)\n"
72 " ld 10,88(%0)\n"
73 " ld 11,96(%0)\n"
74 " ld 12,104(%0)\n"
75 " ld 13,112(%0)\n"
76 " ld 14,120(%0)\n"
77 " ld 15,128(%0)\n"
78 : : "a" (fpregs), "m" (*fpregs));
79}
80
81static inline void save_access_regs(unsigned int *acrs)
82{
83 asm volatile("stam 0,15,0(%0)" : : "a" (acrs) : "memory");
84}
85
86static inline void restore_access_regs(unsigned int *acrs)
87{
88 asm volatile("lam 0,15,0(%0)" : : "a" (acrs));
89}
90
91#define switch_to(prev,next,last) do { \
92 if (prev == next) \
93 break; \
94 save_fp_regs(&prev->thread.fp_regs); \
95 restore_fp_regs(&next->thread.fp_regs); \
96 save_access_regs(&prev->thread.acrs[0]); \
97 restore_access_regs(&next->thread.acrs[0]); \
98 prev = __switch_to(prev,next); \
99} while (0)
100
101#ifdef CONFIG_VIRT_CPU_ACCOUNTING
102extern void account_vtime(struct task_struct *);
103extern void account_tick_vtime(struct task_struct *);
104extern void account_system_vtime(struct task_struct *);
105#else
106#define account_vtime(x) do { /* empty */ } while (0)
107#endif
108
109#ifdef CONFIG_PFAULT
110extern void pfault_irq_init(void);
111extern int pfault_init(void);
112extern void pfault_fini(void);
113#else /* CONFIG_PFAULT */
114#define pfault_irq_init() do { } while (0)
115#define pfault_init() ({-1;})
116#define pfault_fini() do { } while (0)
117#endif /* CONFIG_PFAULT */
118
119#ifdef CONFIG_PAGE_STATES
120extern void cmma_init(void);
121#else
122static inline void cmma_init(void) { }
123#endif
124
125#define finish_arch_switch(prev) do { \
126 set_fs(current->thread.mm_segment); \
127 account_vtime(prev); \
128} while (0)
129
130#define nop() asm volatile("nop")
131
132#define xchg(ptr,x) \
133({ \
134 __typeof__(*(ptr)) __ret; \
135 __ret = (__typeof__(*(ptr))) \
136 __xchg((unsigned long)(x), (void *)(ptr),sizeof(*(ptr))); \
137 __ret; \
138})
139
140extern void __xchg_called_with_bad_pointer(void);
141
142static inline unsigned long __xchg(unsigned long x, void * ptr, int size)
143{
144 unsigned long addr, old;
145 int shift;
146
147 switch (size) {
148 case 1:
149 addr = (unsigned long) ptr;
150 shift = (3 ^ (addr & 3)) << 3;
151 addr ^= addr & 3;
152 asm volatile(
153 " l %0,0(%4)\n"
154 "0: lr 0,%0\n"
155 " nr 0,%3\n"
156 " or 0,%2\n"
157 " cs %0,0,0(%4)\n"
158 " jl 0b\n"
159 : "=&d" (old), "=m" (*(int *) addr)
160 : "d" (x << shift), "d" (~(255 << shift)), "a" (addr),
161 "m" (*(int *) addr) : "memory", "cc", "0");
162 return old >> shift;
163 case 2:
164 addr = (unsigned long) ptr;
165 shift = (2 ^ (addr & 2)) << 3;
166 addr ^= addr & 2;
167 asm volatile(
168 " l %0,0(%4)\n"
169 "0: lr 0,%0\n"
170 " nr 0,%3\n"
171 " or 0,%2\n"
172 " cs %0,0,0(%4)\n"
173 " jl 0b\n"
174 : "=&d" (old), "=m" (*(int *) addr)
175 : "d" (x << shift), "d" (~(65535 << shift)), "a" (addr),
176 "m" (*(int *) addr) : "memory", "cc", "0");
177 return old >> shift;
178 case 4:
179 asm volatile(
180 " l %0,0(%3)\n"
181 "0: cs %0,%2,0(%3)\n"
182 " jl 0b\n"
183 : "=&d" (old), "=m" (*(int *) ptr)
184 : "d" (x), "a" (ptr), "m" (*(int *) ptr)
185 : "memory", "cc");
186 return old;
187#ifdef __s390x__
188 case 8:
189 asm volatile(
190 " lg %0,0(%3)\n"
191 "0: csg %0,%2,0(%3)\n"
192 " jl 0b\n"
193 : "=&d" (old), "=m" (*(long *) ptr)
194 : "d" (x), "a" (ptr), "m" (*(long *) ptr)
195 : "memory", "cc");
196 return old;
197#endif /* __s390x__ */
198 }
199 __xchg_called_with_bad_pointer();
200 return x;
201}
202
203/*
204 * Atomic compare and exchange. Compare OLD with MEM, if identical,
205 * store NEW in MEM. Return the initial value in MEM. Success is
206 * indicated by comparing RETURN with OLD.
207 */
208
209#define __HAVE_ARCH_CMPXCHG 1
210
211#define cmpxchg(ptr, o, n) \
212 ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \
213 (unsigned long)(n), sizeof(*(ptr))))
214
215extern void __cmpxchg_called_with_bad_pointer(void);
216
217static inline unsigned long
218__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
219{
220 unsigned long addr, prev, tmp;
221 int shift;
222
223 switch (size) {
224 case 1:
225 addr = (unsigned long) ptr;
226 shift = (3 ^ (addr & 3)) << 3;
227 addr ^= addr & 3;
228 asm volatile(
229 " l %0,0(%4)\n"
230 "0: nr %0,%5\n"
231 " lr %1,%0\n"
232 " or %0,%2\n"
233 " or %1,%3\n"
234 " cs %0,%1,0(%4)\n"
235 " jnl 1f\n"
236 " xr %1,%0\n"
237 " nr %1,%5\n"
238 " jnz 0b\n"
239 "1:"
240 : "=&d" (prev), "=&d" (tmp)
241 : "d" (old << shift), "d" (new << shift), "a" (ptr),
242 "d" (~(255 << shift))
243 : "memory", "cc");
244 return prev >> shift;
245 case 2:
246 addr = (unsigned long) ptr;
247 shift = (2 ^ (addr & 2)) << 3;
248 addr ^= addr & 2;
249 asm volatile(
250 " l %0,0(%4)\n"
251 "0: nr %0,%5\n"
252 " lr %1,%0\n"
253 " or %0,%2\n"
254 " or %1,%3\n"
255 " cs %0,%1,0(%4)\n"
256 " jnl 1f\n"
257 " xr %1,%0\n"
258 " nr %1,%5\n"
259 " jnz 0b\n"
260 "1:"
261 : "=&d" (prev), "=&d" (tmp)
262 : "d" (old << shift), "d" (new << shift), "a" (ptr),
263 "d" (~(65535 << shift))
264 : "memory", "cc");
265 return prev >> shift;
266 case 4:
267 asm volatile(
268 " cs %0,%2,0(%3)\n"
269 : "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
270 : "memory", "cc");
271 return prev;
272#ifdef __s390x__
273 case 8:
274 asm volatile(
275 " csg %0,%2,0(%3)\n"
276 : "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
277 : "memory", "cc");
278 return prev;
279#endif /* __s390x__ */
280 }
281 __cmpxchg_called_with_bad_pointer();
282 return old;
283}
284
285/*
286 * Force strict CPU ordering.
287 * And yes, this is required on UP too when we're talking
288 * to devices.
289 *
290 * This is very similar to the ppc eieio/sync instruction in that is
291 * does a checkpoint syncronisation & makes sure that
292 * all memory ops have completed wrt other CPU's ( see 7-15 POP DJB ).
293 */
294
295#define eieio() asm volatile("bcr 15,0" : : : "memory")
296#define SYNC_OTHER_CORES(x) eieio()
297#define mb() eieio()
298#define rmb() eieio()
299#define wmb() eieio()
300#define read_barrier_depends() do { } while(0)
301#define smp_mb() mb()
302#define smp_rmb() rmb()
303#define smp_wmb() wmb()
304#define smp_read_barrier_depends() read_barrier_depends()
305#define smp_mb__before_clear_bit() smp_mb()
306#define smp_mb__after_clear_bit() smp_mb()
307
308
309#define set_mb(var, value) do { var = value; mb(); } while (0)
310
311#ifdef __s390x__
312
313#define __ctl_load(array, low, high) ({ \
314 typedef struct { char _[sizeof(array)]; } addrtype; \
315 asm volatile( \
316 " lctlg %1,%2,0(%0)\n" \
317 : : "a" (&array), "i" (low), "i" (high), \
318 "m" (*(addrtype *)(&array))); \
319 })
320
321#define __ctl_store(array, low, high) ({ \
322 typedef struct { char _[sizeof(array)]; } addrtype; \
323 asm volatile( \
324 " stctg %2,%3,0(%1)\n" \
325 : "=m" (*(addrtype *)(&array)) \
326 : "a" (&array), "i" (low), "i" (high)); \
327 })
328
329#else /* __s390x__ */
330
331#define __ctl_load(array, low, high) ({ \
332 typedef struct { char _[sizeof(array)]; } addrtype; \
333 asm volatile( \
334 " lctl %1,%2,0(%0)\n" \
335 : : "a" (&array), "i" (low), "i" (high), \
336 "m" (*(addrtype *)(&array))); \
337})
338
339#define __ctl_store(array, low, high) ({ \
340 typedef struct { char _[sizeof(array)]; } addrtype; \
341 asm volatile( \
342 " stctl %2,%3,0(%1)\n" \
343 : "=m" (*(addrtype *)(&array)) \
344 : "a" (&array), "i" (low), "i" (high)); \
345 })
346
347#endif /* __s390x__ */
348
349#define __ctl_set_bit(cr, bit) ({ \
350 unsigned long __dummy; \
351 __ctl_store(__dummy, cr, cr); \
352 __dummy |= 1UL << (bit); \
353 __ctl_load(__dummy, cr, cr); \
354})
355
356#define __ctl_clear_bit(cr, bit) ({ \
357 unsigned long __dummy; \
358 __ctl_store(__dummy, cr, cr); \
359 __dummy &= ~(1UL << (bit)); \
360 __ctl_load(__dummy, cr, cr); \
361})
362
363#include <linux/irqflags.h>
364
365#include <asm-generic/cmpxchg-local.h>
366
367static inline unsigned long __cmpxchg_local(volatile void *ptr,
368 unsigned long old,
369 unsigned long new, int size)
370{
371 switch (size) {
372 case 1:
373 case 2:
374 case 4:
375#ifdef __s390x__
376 case 8:
377#endif
378 return __cmpxchg(ptr, old, new, size);
379 default:
380 return __cmpxchg_local_generic(ptr, old, new, size);
381 }
382
383 return old;
384}
385
386/*
387 * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
388 * them available.
389 */
390#define cmpxchg_local(ptr, o, n) \
391 ((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \
392 (unsigned long)(n), sizeof(*(ptr))))
393#ifdef __s390x__
394#define cmpxchg64_local(ptr, o, n) \
395 ({ \
396 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
397 cmpxchg_local((ptr), (o), (n)); \
398 })
399#else
400#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
401#endif
402
403/*
404 * Use to set psw mask except for the first byte which
405 * won't be changed by this function.
406 */
407static inline void
408__set_psw_mask(unsigned long mask)
409{
410 __load_psw_mask(mask | (__raw_local_irq_stosm(0x00) & ~(-1UL >> 8)));
411}
412
413#define local_mcck_enable() __set_psw_mask(psw_kernel_bits)
414#define local_mcck_disable() __set_psw_mask(psw_kernel_bits & ~PSW_MASK_MCHECK)
415
416int stfle(unsigned long long *list, int doublewords);
417
418#ifdef CONFIG_SMP
419
420extern void smp_ctl_set_bit(int cr, int bit);
421extern void smp_ctl_clear_bit(int cr, int bit);
422#define ctl_set_bit(cr, bit) smp_ctl_set_bit(cr, bit)
423#define ctl_clear_bit(cr, bit) smp_ctl_clear_bit(cr, bit)
424
425#else
426
427#define ctl_set_bit(cr, bit) __ctl_set_bit(cr, bit)
428#define ctl_clear_bit(cr, bit) __ctl_clear_bit(cr, bit)
429
430#endif /* CONFIG_SMP */
431
432static inline unsigned int stfl(void)
433{
434 asm volatile(
435 " .insn s,0xb2b10000,0(0)\n" /* stfl */
436 "0:\n"
437 EX_TABLE(0b,0b));
438 return S390_lowcore.stfl_fac_list;
439}
440
441static inline unsigned short stap(void)
442{
443 unsigned short cpu_address;
444
445 asm volatile("stap %0" : "=m" (cpu_address));
446 return cpu_address;
447}
448
449extern void (*_machine_restart)(char *command);
450extern void (*_machine_halt)(void);
451extern void (*_machine_power_off)(void);
452
453#define arch_align_stack(x) (x)
454
455#ifdef CONFIG_TRACE_IRQFLAGS
456extern psw_t sysc_restore_trace_psw;
457extern psw_t io_restore_trace_psw;
458#endif
459
460#endif /* __KERNEL__ */
461
462#endif
diff --git a/include/asm-s390/tape390.h b/include/asm-s390/tape390.h
deleted file mode 100644
index 884fba48f1f..00000000000
--- a/include/asm-s390/tape390.h
+++ /dev/null
@@ -1,103 +0,0 @@
1/*************************************************************************
2 *
3 * tape390.h
4 * enables user programs to display messages and control encryption
5 * on s390 tape devices
6 *
7 * Copyright IBM Corp. 2001,2006
8 * Author(s): Michael Holzheu <holzheu@de.ibm.com>
9 *
10 *************************************************************************/
11
12#ifndef _TAPE390_H
13#define _TAPE390_H
14
15#define TAPE390_DISPLAY _IOW('d', 1, struct display_struct)
16
17/*
18 * The TAPE390_DISPLAY ioctl calls the Load Display command
19 * which transfers 17 bytes of data from the channel to the subsystem:
20 * - 1 format control byte, and
21 * - two 8-byte messages
22 *
23 * Format control byte:
24 * 0-2: New Message Overlay
25 * 3: Alternate Messages
26 * 4: Blink Message
27 * 5: Display Low/High Message
28 * 6: Reserved
29 * 7: Automatic Load Request
30 *
31 */
32
33typedef struct display_struct {
34 char cntrl;
35 char message1[8];
36 char message2[8];
37} display_struct;
38
39/*
40 * Tape encryption support
41 */
42
43struct tape390_crypt_info {
44 char capability;
45 char status;
46 char medium_status;
47} __attribute__ ((packed));
48
49
50/* Macros for "capable" field */
51#define TAPE390_CRYPT_SUPPORTED_MASK 0x01
52#define TAPE390_CRYPT_SUPPORTED(x) \
53 ((x.capability & TAPE390_CRYPT_SUPPORTED_MASK))
54
55/* Macros for "status" field */
56#define TAPE390_CRYPT_ON_MASK 0x01
57#define TAPE390_CRYPT_ON(x) (((x.status) & TAPE390_CRYPT_ON_MASK))
58
59/* Macros for "medium status" field */
60#define TAPE390_MEDIUM_LOADED_MASK 0x01
61#define TAPE390_MEDIUM_ENCRYPTED_MASK 0x02
62#define TAPE390_MEDIUM_ENCRYPTED(x) \
63 (((x.medium_status) & TAPE390_MEDIUM_ENCRYPTED_MASK))
64#define TAPE390_MEDIUM_LOADED(x) \
65 (((x.medium_status) & TAPE390_MEDIUM_LOADED_MASK))
66
67/*
68 * The TAPE390_CRYPT_SET ioctl is used to switch on/off encryption.
69 * The "encryption_capable" and "tape_status" fields are ignored for this ioctl!
70 */
71#define TAPE390_CRYPT_SET _IOW('d', 2, struct tape390_crypt_info)
72
73/*
74 * The TAPE390_CRYPT_QUERY ioctl is used to query the encryption state.
75 */
76#define TAPE390_CRYPT_QUERY _IOR('d', 3, struct tape390_crypt_info)
77
78/* Values for "kekl1/2_type" and "kekl1/2_type_on_tape" fields */
79#define TAPE390_KEKL_TYPE_NONE 0
80#define TAPE390_KEKL_TYPE_LABEL 1
81#define TAPE390_KEKL_TYPE_HASH 2
82
83struct tape390_kekl {
84 unsigned char type;
85 unsigned char type_on_tape;
86 char label[65];
87} __attribute__ ((packed));
88
89struct tape390_kekl_pair {
90 struct tape390_kekl kekl[2];
91} __attribute__ ((packed));
92
93/*
94 * The TAPE390_KEKL_SET ioctl is used to set Key Encrypting Key labels.
95 */
96#define TAPE390_KEKL_SET _IOW('d', 4, struct tape390_kekl_pair)
97
98/*
99 * The TAPE390_KEKL_QUERY ioctl is used to query Key Encrypting Key labels.
100 */
101#define TAPE390_KEKL_QUERY _IOR('d', 5, struct tape390_kekl_pair)
102
103#endif
diff --git a/include/asm-s390/termbits.h b/include/asm-s390/termbits.h
deleted file mode 100644
index 58731853d52..00000000000
--- a/include/asm-s390/termbits.h
+++ /dev/null
@@ -1,206 +0,0 @@
1/*
2 * include/asm-s390/termbits.h
3 *
4 * S390 version
5 *
6 * Derived from "include/asm-i386/termbits.h"
7 */
8
9#ifndef __ARCH_S390_TERMBITS_H__
10#define __ARCH_S390_TERMBITS_H__
11
12#include <linux/posix_types.h>
13
14typedef unsigned char cc_t;
15typedef unsigned int speed_t;
16typedef unsigned int tcflag_t;
17
18#define NCCS 19
19struct termios {
20 tcflag_t c_iflag; /* input mode flags */
21 tcflag_t c_oflag; /* output mode flags */
22 tcflag_t c_cflag; /* control mode flags */
23 tcflag_t c_lflag; /* local mode flags */
24 cc_t c_line; /* line discipline */
25 cc_t c_cc[NCCS]; /* control characters */
26};
27
28struct termios2 {
29 tcflag_t c_iflag; /* input mode flags */
30 tcflag_t c_oflag; /* output mode flags */
31 tcflag_t c_cflag; /* control mode flags */
32 tcflag_t c_lflag; /* local mode flags */
33 cc_t c_line; /* line discipline */
34 cc_t c_cc[NCCS]; /* control characters */
35 speed_t c_ispeed; /* input speed */
36 speed_t c_ospeed; /* output speed */
37};
38
39struct ktermios {
40 tcflag_t c_iflag; /* input mode flags */
41 tcflag_t c_oflag; /* output mode flags */
42 tcflag_t c_cflag; /* control mode flags */
43 tcflag_t c_lflag; /* local mode flags */
44 cc_t c_line; /* line discipline */
45 cc_t c_cc[NCCS]; /* control characters */
46 speed_t c_ispeed; /* input speed */
47 speed_t c_ospeed; /* output speed */
48};
49
50/* c_cc characters */
51#define VINTR 0
52#define VQUIT 1
53#define VERASE 2
54#define VKILL 3
55#define VEOF 4
56#define VTIME 5
57#define VMIN 6
58#define VSWTC 7
59#define VSTART 8
60#define VSTOP 9
61#define VSUSP 10
62#define VEOL 11
63#define VREPRINT 12
64#define VDISCARD 13
65#define VWERASE 14
66#define VLNEXT 15
67#define VEOL2 16
68
69/* c_iflag bits */
70#define IGNBRK 0000001
71#define BRKINT 0000002
72#define IGNPAR 0000004
73#define PARMRK 0000010
74#define INPCK 0000020
75#define ISTRIP 0000040
76#define INLCR 0000100
77#define IGNCR 0000200
78#define ICRNL 0000400
79#define IUCLC 0001000
80#define IXON 0002000
81#define IXANY 0004000
82#define IXOFF 0010000
83#define IMAXBEL 0020000
84#define IUTF8 0040000
85
86/* c_oflag bits */
87#define OPOST 0000001
88#define OLCUC 0000002
89#define ONLCR 0000004
90#define OCRNL 0000010
91#define ONOCR 0000020
92#define ONLRET 0000040
93#define OFILL 0000100
94#define OFDEL 0000200
95#define NLDLY 0000400
96#define NL0 0000000
97#define NL1 0000400
98#define CRDLY 0003000
99#define CR0 0000000
100#define CR1 0001000
101#define CR2 0002000
102#define CR3 0003000
103#define TABDLY 0014000
104#define TAB0 0000000
105#define TAB1 0004000
106#define TAB2 0010000
107#define TAB3 0014000
108#define XTABS 0014000
109#define BSDLY 0020000
110#define BS0 0000000
111#define BS1 0020000
112#define VTDLY 0040000
113#define VT0 0000000
114#define VT1 0040000
115#define FFDLY 0100000
116#define FF0 0000000
117#define FF1 0100000
118
119/* c_cflag bit meaning */
120#define CBAUD 0010017
121#define B0 0000000 /* hang up */
122#define B50 0000001
123#define B75 0000002
124#define B110 0000003
125#define B134 0000004
126#define B150 0000005
127#define B200 0000006
128#define B300 0000007
129#define B600 0000010
130#define B1200 0000011
131#define B1800 0000012
132#define B2400 0000013
133#define B4800 0000014
134#define B9600 0000015
135#define B19200 0000016
136#define B38400 0000017
137#define EXTA B19200
138#define EXTB B38400
139#define CSIZE 0000060
140#define CS5 0000000
141#define CS6 0000020
142#define CS7 0000040
143#define CS8 0000060
144#define CSTOPB 0000100
145#define CREAD 0000200
146#define PARENB 0000400
147#define PARODD 0001000
148#define HUPCL 0002000
149#define CLOCAL 0004000
150#define CBAUDEX 0010000
151#define BOTHER 0010000
152#define B57600 0010001
153#define B115200 0010002
154#define B230400 0010003
155#define B460800 0010004
156#define B500000 0010005
157#define B576000 0010006
158#define B921600 0010007
159#define B1000000 0010010
160#define B1152000 0010011
161#define B1500000 0010012
162#define B2000000 0010013
163#define B2500000 0010014
164#define B3000000 0010015
165#define B3500000 0010016
166#define B4000000 0010017
167#define CIBAUD 002003600000 /* input baud rate */
168#define CMSPAR 010000000000 /* mark or space (stick) parity */
169#define CRTSCTS 020000000000 /* flow control */
170
171#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
172
173/* c_lflag bits */
174#define ISIG 0000001
175#define ICANON 0000002
176#define XCASE 0000004
177#define ECHO 0000010
178#define ECHOE 0000020
179#define ECHOK 0000040
180#define ECHONL 0000100
181#define NOFLSH 0000200
182#define TOSTOP 0000400
183#define ECHOCTL 0001000
184#define ECHOPRT 0002000
185#define ECHOKE 0004000
186#define FLUSHO 0010000
187#define PENDIN 0040000
188#define IEXTEN 0100000
189
190/* tcflow() and TCXONC use these */
191#define TCOOFF 0
192#define TCOON 1
193#define TCIOFF 2
194#define TCION 3
195
196/* tcflush() and TCFLSH use these */
197#define TCIFLUSH 0
198#define TCOFLUSH 1
199#define TCIOFLUSH 2
200
201/* tcsetattr uses these */
202#define TCSANOW 0
203#define TCSADRAIN 1
204#define TCSAFLUSH 2
205
206#endif
diff --git a/include/asm-s390/termios.h b/include/asm-s390/termios.h
deleted file mode 100644
index 67f66278f53..00000000000
--- a/include/asm-s390/termios.h
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * include/asm-s390/termios.h
3 *
4 * S390 version
5 *
6 * Derived from "include/asm-i386/termios.h"
7 */
8
9#ifndef _S390_TERMIOS_H
10#define _S390_TERMIOS_H
11
12#include <asm/termbits.h>
13#include <asm/ioctls.h>
14
15struct winsize {
16 unsigned short ws_row;
17 unsigned short ws_col;
18 unsigned short ws_xpixel;
19 unsigned short ws_ypixel;
20};
21
22#define NCC 8
23struct termio {
24 unsigned short c_iflag; /* input mode flags */
25 unsigned short c_oflag; /* output mode flags */
26 unsigned short c_cflag; /* control mode flags */
27 unsigned short c_lflag; /* local mode flags */
28 unsigned char c_line; /* line discipline */
29 unsigned char c_cc[NCC]; /* control characters */
30};
31
32/* modem lines */
33#define TIOCM_LE 0x001
34#define TIOCM_DTR 0x002
35#define TIOCM_RTS 0x004
36#define TIOCM_ST 0x008
37#define TIOCM_SR 0x010
38#define TIOCM_CTS 0x020
39#define TIOCM_CAR 0x040
40#define TIOCM_RNG 0x080
41#define TIOCM_DSR 0x100
42#define TIOCM_CD TIOCM_CAR
43#define TIOCM_RI TIOCM_RNG
44#define TIOCM_OUT1 0x2000
45#define TIOCM_OUT2 0x4000
46#define TIOCM_LOOP 0x8000
47
48/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
49
50#ifdef __KERNEL__
51
52/* intr=^C quit=^\ erase=del kill=^U
53 eof=^D vtime=\0 vmin=\1 sxtc=\0
54 start=^Q stop=^S susp=^Z eol=\0
55 reprint=^R discard=^U werase=^W lnext=^V
56 eol2=\0
57*/
58#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
59
60#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2))
61#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2))
62
63#include <asm-generic/termios.h>
64
65#endif /* __KERNEL__ */
66
67#endif /* _S390_TERMIOS_H */
diff --git a/include/asm-s390/thread_info.h b/include/asm-s390/thread_info.h
deleted file mode 100644
index 91a8f93ad35..00000000000
--- a/include/asm-s390/thread_info.h
+++ /dev/null
@@ -1,118 +0,0 @@
1/*
2 * include/asm-s390/thread_info.h
3 *
4 * S390 version
5 * Copyright (C) IBM Corp. 2002,2006
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
7 */
8
9#ifndef _ASM_THREAD_INFO_H
10#define _ASM_THREAD_INFO_H
11
12#ifdef __KERNEL__
13
14/*
15 * Size of kernel stack for each process
16 */
17#ifndef __s390x__
18#ifndef __SMALL_STACK
19#define THREAD_ORDER 1
20#define ASYNC_ORDER 1
21#else
22#define THREAD_ORDER 0
23#define ASYNC_ORDER 0
24#endif
25#else /* __s390x__ */
26#ifndef __SMALL_STACK
27#define THREAD_ORDER 2
28#define ASYNC_ORDER 2
29#else
30#define THREAD_ORDER 1
31#define ASYNC_ORDER 1
32#endif
33#endif /* __s390x__ */
34
35#define THREAD_SIZE (PAGE_SIZE << THREAD_ORDER)
36#define ASYNC_SIZE (PAGE_SIZE << ASYNC_ORDER)
37
38#ifndef __ASSEMBLY__
39#include <asm/processor.h>
40#include <asm/lowcore.h>
41
42/*
43 * low level task data that entry.S needs immediate access to
44 * - this struct should fit entirely inside of one cache line
45 * - this struct shares the supervisor stack pages
46 * - if the contents of this structure are changed, the assembly constants must also be changed
47 */
48struct thread_info {
49 struct task_struct *task; /* main task structure */
50 struct exec_domain *exec_domain; /* execution domain */
51 unsigned long flags; /* low level flags */
52 unsigned int cpu; /* current CPU */
53 int preempt_count; /* 0 => preemptable, <0 => BUG */
54 struct restart_block restart_block;
55};
56
57/*
58 * macros/functions for gaining access to the thread information structure
59 */
60#define INIT_THREAD_INFO(tsk) \
61{ \
62 .task = &tsk, \
63 .exec_domain = &default_exec_domain, \
64 .flags = 0, \
65 .cpu = 0, \
66 .preempt_count = 1, \
67 .restart_block = { \
68 .fn = do_no_restart_syscall, \
69 }, \
70}
71
72#define init_thread_info (init_thread_union.thread_info)
73#define init_stack (init_thread_union.stack)
74
75/* how to get the thread information struct from C */
76static inline struct thread_info *current_thread_info(void)
77{
78 return (struct thread_info *)((*(unsigned long *) __LC_KERNEL_STACK)-THREAD_SIZE);
79}
80
81#define THREAD_SIZE_ORDER THREAD_ORDER
82
83#endif
84
85/*
86 * thread information flags bit numbers
87 */
88#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
89#define TIF_SIGPENDING 2 /* signal pending */
90#define TIF_NEED_RESCHED 3 /* rescheduling necessary */
91#define TIF_RESTART_SVC 4 /* restart svc with new svc number */
92#define TIF_SYSCALL_AUDIT 5 /* syscall auditing active */
93#define TIF_SINGLE_STEP 6 /* deliver sigtrap on return to user */
94#define TIF_MCCK_PENDING 7 /* machine check handling is pending */
95#define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */
96#define TIF_POLLING_NRFLAG 17 /* true if poll_idle() is polling
97 TIF_NEED_RESCHED */
98#define TIF_31BIT 18 /* 32bit process */
99#define TIF_MEMDIE 19
100#define TIF_RESTORE_SIGMASK 20 /* restore signal mask in do_signal() */
101
102#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
103#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK)
104#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
105#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
106#define _TIF_RESTART_SVC (1<<TIF_RESTART_SVC)
107#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT)
108#define _TIF_SINGLE_STEP (1<<TIF_SINGLE_STEP)
109#define _TIF_MCCK_PENDING (1<<TIF_MCCK_PENDING)
110#define _TIF_USEDFPU (1<<TIF_USEDFPU)
111#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
112#define _TIF_31BIT (1<<TIF_31BIT)
113
114#endif /* __KERNEL__ */
115
116#define PREEMPT_ACTIVE 0x4000000
117
118#endif /* _ASM_THREAD_INFO_H */
diff --git a/include/asm-s390/timer.h b/include/asm-s390/timer.h
deleted file mode 100644
index d98d79e35cd..00000000000
--- a/include/asm-s390/timer.h
+++ /dev/null
@@ -1,65 +0,0 @@
1/*
2 * include/asm-s390/timer.h
3 *
4 * (C) Copyright IBM Corp. 2003,2006
5 * Virtual CPU timer
6 *
7 * Author: Jan Glauber (jang@de.ibm.com)
8 */
9
10#ifndef _ASM_S390_TIMER_H
11#define _ASM_S390_TIMER_H
12
13#ifdef __KERNEL__
14
15#include <linux/timer.h>
16
17#define VTIMER_MAX_SLICE (0x7ffffffffffff000LL)
18
19struct vtimer_list {
20 struct list_head entry;
21
22 int cpu;
23 __u64 expires;
24 __u64 interval;
25
26 spinlock_t lock;
27 unsigned long magic;
28
29 void (*function)(unsigned long);
30 unsigned long data;
31};
32
33/* the offset value will wrap after ca. 71 years */
34struct vtimer_queue {
35 struct list_head list;
36 spinlock_t lock;
37 __u64 to_expire; /* current event expire time */
38 __u64 offset; /* list offset to zero */
39 __u64 idle; /* temp var for idle */
40};
41
42extern void init_virt_timer(struct vtimer_list *timer);
43extern void add_virt_timer(void *new);
44extern void add_virt_timer_periodic(void *new);
45extern int mod_virt_timer(struct vtimer_list *timer, __u64 expires);
46extern int del_virt_timer(struct vtimer_list *timer);
47
48extern void init_cpu_vtimer(void);
49extern void vtime_init(void);
50
51#ifdef CONFIG_VIRT_TIMER
52
53extern void vtime_start_cpu_timer(void);
54extern void vtime_stop_cpu_timer(void);
55
56#else
57
58static inline void vtime_start_cpu_timer(void) { }
59static inline void vtime_stop_cpu_timer(void) { }
60
61#endif /* CONFIG_VIRT_TIMER */
62
63#endif /* __KERNEL__ */
64
65#endif /* _ASM_S390_TIMER_H */
diff --git a/include/asm-s390/timex.h b/include/asm-s390/timex.h
deleted file mode 100644
index d744c3d62de..00000000000
--- a/include/asm-s390/timex.h
+++ /dev/null
@@ -1,88 +0,0 @@
1/*
2 * include/asm-s390/timex.h
3 *
4 * S390 version
5 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 *
7 * Derived from "include/asm-i386/timex.h"
8 * Copyright (C) 1992, Linus Torvalds
9 */
10
11#ifndef _ASM_S390_TIMEX_H
12#define _ASM_S390_TIMEX_H
13
14/* Inline functions for clock register access. */
15static inline int set_clock(__u64 time)
16{
17 int cc;
18
19 asm volatile(
20 " sck 0(%2)\n"
21 " ipm %0\n"
22 " srl %0,28\n"
23 : "=d" (cc) : "m" (time), "a" (&time) : "cc");
24 return cc;
25}
26
27static inline int store_clock(__u64 *time)
28{
29 int cc;
30
31 asm volatile(
32 " stck 0(%2)\n"
33 " ipm %0\n"
34 " srl %0,28\n"
35 : "=d" (cc), "=m" (*time) : "a" (time) : "cc");
36 return cc;
37}
38
39static inline void set_clock_comparator(__u64 time)
40{
41 asm volatile("sckc 0(%1)" : : "m" (time), "a" (&time));
42}
43
44static inline void store_clock_comparator(__u64 *time)
45{
46 asm volatile("stckc 0(%1)" : "=m" (*time) : "a" (time));
47}
48
49#define CLOCK_TICK_RATE 1193180 /* Underlying HZ */
50
51typedef unsigned long long cycles_t;
52
53static inline unsigned long long get_clock (void)
54{
55 unsigned long long clk;
56
57#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
58 asm volatile("stck %0" : "=Q" (clk) : : "cc");
59#else /* __GNUC__ */
60 asm volatile("stck 0(%1)" : "=m" (clk) : "a" (&clk) : "cc");
61#endif /* __GNUC__ */
62 return clk;
63}
64
65static inline unsigned long long get_clock_xt(void)
66{
67 unsigned char clk[16];
68
69#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
70 asm volatile("stcke %0" : "=Q" (clk) : : "cc");
71#else /* __GNUC__ */
72 asm volatile("stcke 0(%1)" : "=m" (clk)
73 : "a" (clk) : "cc");
74#endif /* __GNUC__ */
75
76 return *((unsigned long long *)&clk[1]);
77}
78
79static inline cycles_t get_cycles(void)
80{
81 return (cycles_t) get_clock() >> 2;
82}
83
84int get_sync_clock(unsigned long long *clock);
85void init_cpu_timer(void);
86unsigned long long monotonic_clock(void);
87
88#endif
diff --git a/include/asm-s390/tlb.h b/include/asm-s390/tlb.h
deleted file mode 100644
index 3d8a96d39d9..00000000000
--- a/include/asm-s390/tlb.h
+++ /dev/null
@@ -1,156 +0,0 @@
1#ifndef _S390_TLB_H
2#define _S390_TLB_H
3
4/*
5 * TLB flushing on s390 is complicated. The following requirement
6 * from the principles of operation is the most arduous:
7 *
8 * "A valid table entry must not be changed while it is attached
9 * to any CPU and may be used for translation by that CPU except to
10 * (1) invalidate the entry by using INVALIDATE PAGE TABLE ENTRY,
11 * or INVALIDATE DAT TABLE ENTRY, (2) alter bits 56-63 of a page
12 * table entry, or (3) make a change by means of a COMPARE AND SWAP
13 * AND PURGE instruction that purges the TLB."
14 *
15 * The modification of a pte of an active mm struct therefore is
16 * a two step process: i) invalidate the pte, ii) store the new pte.
17 * This is true for the page protection bit as well.
18 * The only possible optimization is to flush at the beginning of
19 * a tlb_gather_mmu cycle if the mm_struct is currently not in use.
20 *
21 * Pages used for the page tables is a different story. FIXME: more
22 */
23
24#include <linux/mm.h>
25#include <linux/swap.h>
26#include <asm/processor.h>
27#include <asm/pgalloc.h>
28#include <asm/smp.h>
29#include <asm/tlbflush.h>
30
31#ifndef CONFIG_SMP
32#define TLB_NR_PTRS 1
33#else
34#define TLB_NR_PTRS 508
35#endif
36
37struct mmu_gather {
38 struct mm_struct *mm;
39 unsigned int fullmm;
40 unsigned int nr_ptes;
41 unsigned int nr_pxds;
42 void *array[TLB_NR_PTRS];
43};
44
45DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
46
47static inline struct mmu_gather *tlb_gather_mmu(struct mm_struct *mm,
48 unsigned int full_mm_flush)
49{
50 struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
51
52 tlb->mm = mm;
53 tlb->fullmm = full_mm_flush || (num_online_cpus() == 1) ||
54 (atomic_read(&mm->mm_users) <= 1 && mm == current->active_mm);
55 tlb->nr_ptes = 0;
56 tlb->nr_pxds = TLB_NR_PTRS;
57 if (tlb->fullmm)
58 __tlb_flush_mm(mm);
59 return tlb;
60}
61
62static inline void tlb_flush_mmu(struct mmu_gather *tlb,
63 unsigned long start, unsigned long end)
64{
65 if (!tlb->fullmm && (tlb->nr_ptes > 0 || tlb->nr_pxds < TLB_NR_PTRS))
66 __tlb_flush_mm(tlb->mm);
67 while (tlb->nr_ptes > 0)
68 pte_free(tlb->mm, tlb->array[--tlb->nr_ptes]);
69 while (tlb->nr_pxds < TLB_NR_PTRS)
70 /* pgd_free frees the pointer as region or segment table */
71 pgd_free(tlb->mm, tlb->array[tlb->nr_pxds++]);
72}
73
74static inline void tlb_finish_mmu(struct mmu_gather *tlb,
75 unsigned long start, unsigned long end)
76{
77 tlb_flush_mmu(tlb, start, end);
78
79 /* keep the page table cache within bounds */
80 check_pgt_cache();
81
82 put_cpu_var(mmu_gathers);
83}
84
85/*
86 * Release the page cache reference for a pte removed by
87 * tlb_ptep_clear_flush. In both flush modes the tlb fo a page cache page
88 * has already been freed, so just do free_page_and_swap_cache.
89 */
90static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
91{
92 free_page_and_swap_cache(page);
93}
94
95/*
96 * pte_free_tlb frees a pte table and clears the CRSTE for the
97 * page table from the tlb.
98 */
99static inline void pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte)
100{
101 if (!tlb->fullmm) {
102 tlb->array[tlb->nr_ptes++] = pte;
103 if (tlb->nr_ptes >= tlb->nr_pxds)
104 tlb_flush_mmu(tlb, 0, 0);
105 } else
106 pte_free(tlb->mm, pte);
107}
108
109/*
110 * pmd_free_tlb frees a pmd table and clears the CRSTE for the
111 * segment table entry from the tlb.
112 * If the mm uses a two level page table the single pmd is freed
113 * as the pgd. pmd_free_tlb checks the asce_limit against 2GB
114 * to avoid the double free of the pmd in this case.
115 */
116static inline void pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd)
117{
118#ifdef __s390x__
119 if (tlb->mm->context.asce_limit <= (1UL << 31))
120 return;
121 if (!tlb->fullmm) {
122 tlb->array[--tlb->nr_pxds] = pmd;
123 if (tlb->nr_ptes >= tlb->nr_pxds)
124 tlb_flush_mmu(tlb, 0, 0);
125 } else
126 pmd_free(tlb->mm, pmd);
127#endif
128}
129
130/*
131 * pud_free_tlb frees a pud table and clears the CRSTE for the
132 * region third table entry from the tlb.
133 * If the mm uses a three level page table the single pud is freed
134 * as the pgd. pud_free_tlb checks the asce_limit against 4TB
135 * to avoid the double free of the pud in this case.
136 */
137static inline void pud_free_tlb(struct mmu_gather *tlb, pud_t *pud)
138{
139#ifdef __s390x__
140 if (tlb->mm->context.asce_limit <= (1UL << 42))
141 return;
142 if (!tlb->fullmm) {
143 tlb->array[--tlb->nr_pxds] = pud;
144 if (tlb->nr_ptes >= tlb->nr_pxds)
145 tlb_flush_mmu(tlb, 0, 0);
146 } else
147 pud_free(tlb->mm, pud);
148#endif
149}
150
151#define tlb_start_vma(tlb, vma) do { } while (0)
152#define tlb_end_vma(tlb, vma) do { } while (0)
153#define tlb_remove_tlb_entry(tlb, ptep, addr) do { } while (0)
154#define tlb_migrate_finish(mm) do { } while (0)
155
156#endif /* _S390_TLB_H */
diff --git a/include/asm-s390/tlbflush.h b/include/asm-s390/tlbflush.h
deleted file mode 100644
index d60394b9745..00000000000
--- a/include/asm-s390/tlbflush.h
+++ /dev/null
@@ -1,140 +0,0 @@
1#ifndef _S390_TLBFLUSH_H
2#define _S390_TLBFLUSH_H
3
4#include <linux/mm.h>
5#include <linux/sched.h>
6#include <asm/processor.h>
7#include <asm/pgalloc.h>
8
9/*
10 * Flush all tlb entries on the local cpu.
11 */
12static inline void __tlb_flush_local(void)
13{
14 asm volatile("ptlb" : : : "memory");
15}
16
17#ifdef CONFIG_SMP
18/*
19 * Flush all tlb entries on all cpus.
20 */
21void smp_ptlb_all(void);
22
23static inline void __tlb_flush_global(void)
24{
25 register unsigned long reg2 asm("2");
26 register unsigned long reg3 asm("3");
27 register unsigned long reg4 asm("4");
28 long dummy;
29
30#ifndef __s390x__
31 if (!MACHINE_HAS_CSP) {
32 smp_ptlb_all();
33 return;
34 }
35#endif /* __s390x__ */
36
37 dummy = 0;
38 reg2 = reg3 = 0;
39 reg4 = ((unsigned long) &dummy) + 1;
40 asm volatile(
41 " csp %0,%2"
42 : : "d" (reg2), "d" (reg3), "d" (reg4), "m" (dummy) : "cc" );
43}
44
45static inline void __tlb_flush_full(struct mm_struct *mm)
46{
47 cpumask_t local_cpumask;
48
49 preempt_disable();
50 /*
51 * If the process only ran on the local cpu, do a local flush.
52 */
53 local_cpumask = cpumask_of_cpu(smp_processor_id());
54 if (cpus_equal(mm->cpu_vm_mask, local_cpumask))
55 __tlb_flush_local();
56 else
57 __tlb_flush_global();
58 preempt_enable();
59}
60#else
61#define __tlb_flush_full(mm) __tlb_flush_local()
62#endif
63
64/*
65 * Flush all tlb entries of a page table on all cpus.
66 */
67static inline void __tlb_flush_idte(unsigned long asce)
68{
69 asm volatile(
70 " .insn rrf,0xb98e0000,0,%0,%1,0"
71 : : "a" (2048), "a" (asce) : "cc" );
72}
73
74static inline void __tlb_flush_mm(struct mm_struct * mm)
75{
76 if (unlikely(cpus_empty(mm->cpu_vm_mask)))
77 return;
78 /*
79 * If the machine has IDTE we prefer to do a per mm flush
80 * on all cpus instead of doing a local flush if the mm
81 * only ran on the local cpu.
82 */
83 if (MACHINE_HAS_IDTE) {
84 if (mm->context.noexec)
85 __tlb_flush_idte((unsigned long)
86 get_shadow_table(mm->pgd) |
87 mm->context.asce_bits);
88 __tlb_flush_idte((unsigned long) mm->pgd |
89 mm->context.asce_bits);
90 return;
91 }
92 __tlb_flush_full(mm);
93}
94
95static inline void __tlb_flush_mm_cond(struct mm_struct * mm)
96{
97 if (atomic_read(&mm->mm_users) <= 1 && mm == current->active_mm)
98 __tlb_flush_mm(mm);
99}
100
101/*
102 * TLB flushing:
103 * flush_tlb() - flushes the current mm struct TLBs
104 * flush_tlb_all() - flushes all processes TLBs
105 * flush_tlb_mm(mm) - flushes the specified mm context TLB's
106 * flush_tlb_page(vma, vmaddr) - flushes one page
107 * flush_tlb_range(vma, start, end) - flushes a range of pages
108 * flush_tlb_kernel_range(start, end) - flushes a range of kernel pages
109 */
110
111/*
112 * flush_tlb_mm goes together with ptep_set_wrprotect for the
113 * copy_page_range operation and flush_tlb_range is related to
114 * ptep_get_and_clear for change_protection. ptep_set_wrprotect and
115 * ptep_get_and_clear do not flush the TLBs directly if the mm has
116 * only one user. At the end of the update the flush_tlb_mm and
117 * flush_tlb_range functions need to do the flush.
118 */
119#define flush_tlb() do { } while (0)
120#define flush_tlb_all() do { } while (0)
121#define flush_tlb_page(vma, addr) do { } while (0)
122
123static inline void flush_tlb_mm(struct mm_struct *mm)
124{
125 __tlb_flush_mm_cond(mm);
126}
127
128static inline void flush_tlb_range(struct vm_area_struct *vma,
129 unsigned long start, unsigned long end)
130{
131 __tlb_flush_mm_cond(vma->vm_mm);
132}
133
134static inline void flush_tlb_kernel_range(unsigned long start,
135 unsigned long end)
136{
137 __tlb_flush_mm(&init_mm);
138}
139
140#endif /* _S390_TLBFLUSH_H */
diff --git a/include/asm-s390/todclk.h b/include/asm-s390/todclk.h
deleted file mode 100644
index c7f62055488..00000000000
--- a/include/asm-s390/todclk.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * File...........: linux/include/asm/todclk.h
3 * Author(s)......: Holger Smolinski <Holger.Smolinski@de.ibm.com>
4 * Bugreports.to..: <Linux390@de.ibm.com>
5 * (C) IBM Corporation, IBM Deutschland Entwicklung GmbH, 1999,2000
6 *
7 * History of changes (starts July 2000)
8 */
9
10#ifndef __ASM_TODCLK_H
11#define __ASM_TODCLK_H
12
13#ifdef __KERNEL__
14
15#define TOD_uSEC (0x1000ULL)
16#define TOD_mSEC (1000 * TOD_uSEC)
17#define TOD_SEC (1000 * TOD_mSEC)
18#define TOD_MIN (60 * TOD_SEC)
19#define TOD_HOUR (60 * TOD_MIN)
20
21#endif
22
23#endif
diff --git a/include/asm-s390/topology.h b/include/asm-s390/topology.h
deleted file mode 100644
index d96c9164345..00000000000
--- a/include/asm-s390/topology.h
+++ /dev/null
@@ -1,33 +0,0 @@
1#ifndef _ASM_S390_TOPOLOGY_H
2#define _ASM_S390_TOPOLOGY_H
3
4#include <linux/cpumask.h>
5
6#define mc_capable() (1)
7
8cpumask_t cpu_coregroup_map(unsigned int cpu);
9
10extern cpumask_t cpu_core_map[NR_CPUS];
11
12#define topology_core_siblings(cpu) (cpu_core_map[cpu])
13
14int topology_set_cpu_management(int fc);
15void topology_schedule_update(void);
16
17#define POLARIZATION_UNKNWN (-1)
18#define POLARIZATION_HRZ (0)
19#define POLARIZATION_VL (1)
20#define POLARIZATION_VM (2)
21#define POLARIZATION_VH (3)
22
23#ifdef CONFIG_SMP
24void s390_init_cpu_topology(void);
25#else
26static inline void s390_init_cpu_topology(void)
27{
28};
29#endif
30
31#include <asm-generic/topology.h>
32
33#endif /* _ASM_S390_TOPOLOGY_H */
diff --git a/include/asm-s390/types.h b/include/asm-s390/types.h
deleted file mode 100644
index 41c54765613..00000000000
--- a/include/asm-s390/types.h
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * include/asm-s390/types.h
3 *
4 * S390 version
5 *
6 * Derived from "include/asm-i386/types.h"
7 */
8
9#ifndef _S390_TYPES_H
10#define _S390_TYPES_H
11
12#ifndef __s390x__
13# include <asm-generic/int-ll64.h>
14#else
15# include <asm-generic/int-l64.h>
16#endif
17
18#ifndef __ASSEMBLY__
19
20typedef unsigned short umode_t;
21
22/* A address type so that arithmetic can be done on it & it can be upgraded to
23 64 bit when necessary
24*/
25typedef unsigned long addr_t;
26typedef __signed__ long saddr_t;
27
28#endif /* __ASSEMBLY__ */
29
30/*
31 * These aren't exported outside the kernel to avoid name space clashes
32 */
33#ifdef __KERNEL__
34
35#ifndef __s390x__
36#define BITS_PER_LONG 32
37#else
38#define BITS_PER_LONG 64
39#endif
40
41#ifndef __ASSEMBLY__
42
43typedef u64 dma64_addr_t;
44#ifdef __s390x__
45/* DMA addresses come in 32-bit and 64-bit flavours. */
46typedef u64 dma_addr_t;
47#else
48typedef u32 dma_addr_t;
49#endif
50
51#ifndef __s390x__
52typedef union {
53 unsigned long long pair;
54 struct {
55 unsigned long even;
56 unsigned long odd;
57 } subreg;
58} register_pair;
59
60#endif /* ! __s390x__ */
61#endif /* __ASSEMBLY__ */
62#endif /* __KERNEL__ */
63#endif /* _S390_TYPES_H */
diff --git a/include/asm-s390/uaccess.h b/include/asm-s390/uaccess.h
deleted file mode 100644
index 0235970278f..00000000000
--- a/include/asm-s390/uaccess.h
+++ /dev/null
@@ -1,363 +0,0 @@
1/*
2 * include/asm-s390/uaccess.h
3 *
4 * S390 version
5 * Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Hartmut Penner (hp@de.ibm.com),
7 * Martin Schwidefsky (schwidefsky@de.ibm.com)
8 *
9 * Derived from "include/asm-i386/uaccess.h"
10 */
11#ifndef __S390_UACCESS_H
12#define __S390_UACCESS_H
13
14/*
15 * User space memory access functions
16 */
17#include <linux/sched.h>
18#include <linux/errno.h>
19
20#define VERIFY_READ 0
21#define VERIFY_WRITE 1
22
23
24/*
25 * The fs value determines whether argument validity checking should be
26 * performed or not. If get_fs() == USER_DS, checking is performed, with
27 * get_fs() == KERNEL_DS, checking is bypassed.
28 *
29 * For historical reasons, these macros are grossly misnamed.
30 */
31
32#define MAKE_MM_SEG(a) ((mm_segment_t) { (a) })
33
34
35#define KERNEL_DS MAKE_MM_SEG(0)
36#define USER_DS MAKE_MM_SEG(1)
37
38#define get_ds() (KERNEL_DS)
39#define get_fs() (current->thread.mm_segment)
40
41#define set_fs(x) \
42({ \
43 unsigned long __pto; \
44 current->thread.mm_segment = (x); \
45 __pto = current->thread.mm_segment.ar4 ? \
46 S390_lowcore.user_asce : S390_lowcore.kernel_asce; \
47 __ctl_load(__pto, 7, 7); \
48})
49
50#define segment_eq(a,b) ((a).ar4 == (b).ar4)
51
52
53static inline int __access_ok(const void __user *addr, unsigned long size)
54{
55 return 1;
56}
57#define access_ok(type,addr,size) __access_ok(addr,size)
58
59/*
60 * The exception table consists of pairs of addresses: the first is the
61 * address of an instruction that is allowed to fault, and the second is
62 * the address at which the program should continue. No registers are
63 * modified, so it is entirely up to the continuation code to figure out
64 * what to do.
65 *
66 * All the routines below use bits of fixup code that are out of line
67 * with the main instruction path. This means when everything is well,
68 * we don't even have to jump over them. Further, they do not intrude
69 * on our cache or tlb entries.
70 */
71
72struct exception_table_entry
73{
74 unsigned long insn, fixup;
75};
76
77struct uaccess_ops {
78 size_t (*copy_from_user)(size_t, const void __user *, void *);
79 size_t (*copy_from_user_small)(size_t, const void __user *, void *);
80 size_t (*copy_to_user)(size_t, void __user *, const void *);
81 size_t (*copy_to_user_small)(size_t, void __user *, const void *);
82 size_t (*copy_in_user)(size_t, void __user *, const void __user *);
83 size_t (*clear_user)(size_t, void __user *);
84 size_t (*strnlen_user)(size_t, const char __user *);
85 size_t (*strncpy_from_user)(size_t, const char __user *, char *);
86 int (*futex_atomic_op)(int op, int __user *, int oparg, int *old);
87 int (*futex_atomic_cmpxchg)(int __user *, int old, int new);
88};
89
90extern struct uaccess_ops uaccess;
91extern struct uaccess_ops uaccess_std;
92extern struct uaccess_ops uaccess_mvcos;
93extern struct uaccess_ops uaccess_mvcos_switch;
94extern struct uaccess_ops uaccess_pt;
95
96static inline int __put_user_fn(size_t size, void __user *ptr, void *x)
97{
98 size = uaccess.copy_to_user_small(size, ptr, x);
99 return size ? -EFAULT : size;
100}
101
102static inline int __get_user_fn(size_t size, const void __user *ptr, void *x)
103{
104 size = uaccess.copy_from_user_small(size, ptr, x);
105 return size ? -EFAULT : size;
106}
107
108/*
109 * These are the main single-value transfer routines. They automatically
110 * use the right size if we just have the right pointer type.
111 */
112#define __put_user(x, ptr) \
113({ \
114 __typeof__(*(ptr)) __x = (x); \
115 int __pu_err = -EFAULT; \
116 __chk_user_ptr(ptr); \
117 switch (sizeof (*(ptr))) { \
118 case 1: \
119 case 2: \
120 case 4: \
121 case 8: \
122 __pu_err = __put_user_fn(sizeof (*(ptr)), \
123 ptr, &__x); \
124 break; \
125 default: \
126 __put_user_bad(); \
127 break; \
128 } \
129 __pu_err; \
130})
131
132#define put_user(x, ptr) \
133({ \
134 might_sleep(); \
135 __put_user(x, ptr); \
136})
137
138
139extern int __put_user_bad(void) __attribute__((noreturn));
140
141#define __get_user(x, ptr) \
142({ \
143 int __gu_err = -EFAULT; \
144 __chk_user_ptr(ptr); \
145 switch (sizeof(*(ptr))) { \
146 case 1: { \
147 unsigned char __x; \
148 __gu_err = __get_user_fn(sizeof (*(ptr)), \
149 ptr, &__x); \
150 (x) = *(__force __typeof__(*(ptr)) *) &__x; \
151 break; \
152 }; \
153 case 2: { \
154 unsigned short __x; \
155 __gu_err = __get_user_fn(sizeof (*(ptr)), \
156 ptr, &__x); \
157 (x) = *(__force __typeof__(*(ptr)) *) &__x; \
158 break; \
159 }; \
160 case 4: { \
161 unsigned int __x; \
162 __gu_err = __get_user_fn(sizeof (*(ptr)), \
163 ptr, &__x); \
164 (x) = *(__force __typeof__(*(ptr)) *) &__x; \
165 break; \
166 }; \
167 case 8: { \
168 unsigned long long __x; \
169 __gu_err = __get_user_fn(sizeof (*(ptr)), \
170 ptr, &__x); \
171 (x) = *(__force __typeof__(*(ptr)) *) &__x; \
172 break; \
173 }; \
174 default: \
175 __get_user_bad(); \
176 break; \
177 } \
178 __gu_err; \
179})
180
181#define get_user(x, ptr) \
182({ \
183 might_sleep(); \
184 __get_user(x, ptr); \
185})
186
187extern int __get_user_bad(void) __attribute__((noreturn));
188
189#define __put_user_unaligned __put_user
190#define __get_user_unaligned __get_user
191
192/**
193 * __copy_to_user: - Copy a block of data into user space, with less checking.
194 * @to: Destination address, in user space.
195 * @from: Source address, in kernel space.
196 * @n: Number of bytes to copy.
197 *
198 * Context: User context only. This function may sleep.
199 *
200 * Copy data from kernel space to user space. Caller must check
201 * the specified block with access_ok() before calling this function.
202 *
203 * Returns number of bytes that could not be copied.
204 * On success, this will be zero.
205 */
206static inline unsigned long __must_check
207__copy_to_user(void __user *to, const void *from, unsigned long n)
208{
209 if (__builtin_constant_p(n) && (n <= 256))
210 return uaccess.copy_to_user_small(n, to, from);
211 else
212 return uaccess.copy_to_user(n, to, from);
213}
214
215#define __copy_to_user_inatomic __copy_to_user
216#define __copy_from_user_inatomic __copy_from_user
217
218/**
219 * copy_to_user: - Copy a block of data into user space.
220 * @to: Destination address, in user space.
221 * @from: Source address, in kernel space.
222 * @n: Number of bytes to copy.
223 *
224 * Context: User context only. This function may sleep.
225 *
226 * Copy data from kernel space to user space.
227 *
228 * Returns number of bytes that could not be copied.
229 * On success, this will be zero.
230 */
231static inline unsigned long __must_check
232copy_to_user(void __user *to, const void *from, unsigned long n)
233{
234 might_sleep();
235 if (access_ok(VERIFY_WRITE, to, n))
236 n = __copy_to_user(to, from, n);
237 return n;
238}
239
240/**
241 * __copy_from_user: - Copy a block of data from user space, with less checking.
242 * @to: Destination address, in kernel space.
243 * @from: Source address, in user space.
244 * @n: Number of bytes to copy.
245 *
246 * Context: User context only. This function may sleep.
247 *
248 * Copy data from user space to kernel space. Caller must check
249 * the specified block with access_ok() before calling this function.
250 *
251 * Returns number of bytes that could not be copied.
252 * On success, this will be zero.
253 *
254 * If some data could not be copied, this function will pad the copied
255 * data to the requested size using zero bytes.
256 */
257static inline unsigned long __must_check
258__copy_from_user(void *to, const void __user *from, unsigned long n)
259{
260 if (__builtin_constant_p(n) && (n <= 256))
261 return uaccess.copy_from_user_small(n, from, to);
262 else
263 return uaccess.copy_from_user(n, from, to);
264}
265
266/**
267 * copy_from_user: - Copy a block of data from user space.
268 * @to: Destination address, in kernel space.
269 * @from: Source address, in user space.
270 * @n: Number of bytes to copy.
271 *
272 * Context: User context only. This function may sleep.
273 *
274 * Copy data from user space to kernel space.
275 *
276 * Returns number of bytes that could not be copied.
277 * On success, this will be zero.
278 *
279 * If some data could not be copied, this function will pad the copied
280 * data to the requested size using zero bytes.
281 */
282static inline unsigned long __must_check
283copy_from_user(void *to, const void __user *from, unsigned long n)
284{
285 might_sleep();
286 if (access_ok(VERIFY_READ, from, n))
287 n = __copy_from_user(to, from, n);
288 else
289 memset(to, 0, n);
290 return n;
291}
292
293static inline unsigned long __must_check
294__copy_in_user(void __user *to, const void __user *from, unsigned long n)
295{
296 return uaccess.copy_in_user(n, to, from);
297}
298
299static inline unsigned long __must_check
300copy_in_user(void __user *to, const void __user *from, unsigned long n)
301{
302 might_sleep();
303 if (__access_ok(from,n) && __access_ok(to,n))
304 n = __copy_in_user(to, from, n);
305 return n;
306}
307
308/*
309 * Copy a null terminated string from userspace.
310 */
311static inline long __must_check
312strncpy_from_user(char *dst, const char __user *src, long count)
313{
314 long res = -EFAULT;
315 might_sleep();
316 if (access_ok(VERIFY_READ, src, 1))
317 res = uaccess.strncpy_from_user(count, src, dst);
318 return res;
319}
320
321static inline unsigned long
322strnlen_user(const char __user * src, unsigned long n)
323{
324 might_sleep();
325 return uaccess.strnlen_user(n, src);
326}
327
328/**
329 * strlen_user: - Get the size of a string in user space.
330 * @str: The string to measure.
331 *
332 * Context: User context only. This function may sleep.
333 *
334 * Get the size of a NUL-terminated string in user space.
335 *
336 * Returns the size of the string INCLUDING the terminating NUL.
337 * On exception, returns 0.
338 *
339 * If there is a limit on the length of a valid string, you may wish to
340 * consider using strnlen_user() instead.
341 */
342#define strlen_user(str) strnlen_user(str, ~0UL)
343
344/*
345 * Zero Userspace
346 */
347
348static inline unsigned long __must_check
349__clear_user(void __user *to, unsigned long n)
350{
351 return uaccess.clear_user(n, to);
352}
353
354static inline unsigned long __must_check
355clear_user(void __user *to, unsigned long n)
356{
357 might_sleep();
358 if (access_ok(VERIFY_WRITE, to, n))
359 n = uaccess.clear_user(n, to);
360 return n;
361}
362
363#endif /* __S390_UACCESS_H */
diff --git a/include/asm-s390/ucontext.h b/include/asm-s390/ucontext.h
deleted file mode 100644
index d69bec0b03f..00000000000
--- a/include/asm-s390/ucontext.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * include/asm-s390/ucontext.h
3 *
4 * S390 version
5 *
6 * Derived from "include/asm-i386/ucontext.h"
7 */
8
9#ifndef _ASM_S390_UCONTEXT_H
10#define _ASM_S390_UCONTEXT_H
11
12struct ucontext {
13 unsigned long uc_flags;
14 struct ucontext *uc_link;
15 stack_t uc_stack;
16 _sigregs uc_mcontext;
17 sigset_t uc_sigmask; /* mask last for extensibility */
18};
19
20#endif /* !_ASM_S390_UCONTEXT_H */
diff --git a/include/asm-s390/unaligned.h b/include/asm-s390/unaligned.h
deleted file mode 100644
index da9627afe5d..00000000000
--- a/include/asm-s390/unaligned.h
+++ /dev/null
@@ -1,13 +0,0 @@
1#ifndef _ASM_S390_UNALIGNED_H
2#define _ASM_S390_UNALIGNED_H
3
4/*
5 * The S390 can do unaligned accesses itself.
6 */
7#include <linux/unaligned/access_ok.h>
8#include <linux/unaligned/generic.h>
9
10#define get_unaligned __get_unaligned_be
11#define put_unaligned __put_unaligned_be
12
13#endif /* _ASM_S390_UNALIGNED_H */
diff --git a/include/asm-s390/unistd.h b/include/asm-s390/unistd.h
deleted file mode 100644
index 583da807ea9..00000000000
--- a/include/asm-s390/unistd.h
+++ /dev/null
@@ -1,405 +0,0 @@
1/*
2 * include/asm-s390/unistd.h
3 *
4 * S390 version
5 *
6 * Derived from "include/asm-i386/unistd.h"
7 */
8
9#ifndef _ASM_S390_UNISTD_H_
10#define _ASM_S390_UNISTD_H_
11
12/*
13 * This file contains the system call numbers.
14 */
15
16#define __NR_exit 1
17#define __NR_fork 2
18#define __NR_read 3
19#define __NR_write 4
20#define __NR_open 5
21#define __NR_close 6
22#define __NR_restart_syscall 7
23#define __NR_creat 8
24#define __NR_link 9
25#define __NR_unlink 10
26#define __NR_execve 11
27#define __NR_chdir 12
28#define __NR_mknod 14
29#define __NR_chmod 15
30#define __NR_lseek 19
31#define __NR_getpid 20
32#define __NR_mount 21
33#define __NR_umount 22
34#define __NR_ptrace 26
35#define __NR_alarm 27
36#define __NR_pause 29
37#define __NR_utime 30
38#define __NR_access 33
39#define __NR_nice 34
40#define __NR_sync 36
41#define __NR_kill 37
42#define __NR_rename 38
43#define __NR_mkdir 39
44#define __NR_rmdir 40
45#define __NR_dup 41
46#define __NR_pipe 42
47#define __NR_times 43
48#define __NR_brk 45
49#define __NR_signal 48
50#define __NR_acct 51
51#define __NR_umount2 52
52#define __NR_ioctl 54
53#define __NR_fcntl 55
54#define __NR_setpgid 57
55#define __NR_umask 60
56#define __NR_chroot 61
57#define __NR_ustat 62
58#define __NR_dup2 63
59#define __NR_getppid 64
60#define __NR_getpgrp 65
61#define __NR_setsid 66
62#define __NR_sigaction 67
63#define __NR_sigsuspend 72
64#define __NR_sigpending 73
65#define __NR_sethostname 74
66#define __NR_setrlimit 75
67#define __NR_getrusage 77
68#define __NR_gettimeofday 78
69#define __NR_settimeofday 79
70#define __NR_symlink 83
71#define __NR_readlink 85
72#define __NR_uselib 86
73#define __NR_swapon 87
74#define __NR_reboot 88
75#define __NR_readdir 89
76#define __NR_mmap 90
77#define __NR_munmap 91
78#define __NR_truncate 92
79#define __NR_ftruncate 93
80#define __NR_fchmod 94
81#define __NR_getpriority 96
82#define __NR_setpriority 97
83#define __NR_statfs 99
84#define __NR_fstatfs 100
85#define __NR_socketcall 102
86#define __NR_syslog 103
87#define __NR_setitimer 104
88#define __NR_getitimer 105
89#define __NR_stat 106
90#define __NR_lstat 107
91#define __NR_fstat 108
92#define __NR_lookup_dcookie 110
93#define __NR_vhangup 111
94#define __NR_idle 112
95#define __NR_wait4 114
96#define __NR_swapoff 115
97#define __NR_sysinfo 116
98#define __NR_ipc 117
99#define __NR_fsync 118
100#define __NR_sigreturn 119
101#define __NR_clone 120
102#define __NR_setdomainname 121
103#define __NR_uname 122
104#define __NR_adjtimex 124
105#define __NR_mprotect 125
106#define __NR_sigprocmask 126
107#define __NR_create_module 127
108#define __NR_init_module 128
109#define __NR_delete_module 129
110#define __NR_get_kernel_syms 130
111#define __NR_quotactl 131
112#define __NR_getpgid 132
113#define __NR_fchdir 133
114#define __NR_bdflush 134
115#define __NR_sysfs 135
116#define __NR_personality 136
117#define __NR_afs_syscall 137 /* Syscall for Andrew File System */
118#define __NR_getdents 141
119#define __NR_flock 143
120#define __NR_msync 144
121#define __NR_readv 145
122#define __NR_writev 146
123#define __NR_getsid 147
124#define __NR_fdatasync 148
125#define __NR__sysctl 149
126#define __NR_mlock 150
127#define __NR_munlock 151
128#define __NR_mlockall 152
129#define __NR_munlockall 153
130#define __NR_sched_setparam 154
131#define __NR_sched_getparam 155
132#define __NR_sched_setscheduler 156
133#define __NR_sched_getscheduler 157
134#define __NR_sched_yield 158
135#define __NR_sched_get_priority_max 159
136#define __NR_sched_get_priority_min 160
137#define __NR_sched_rr_get_interval 161
138#define __NR_nanosleep 162
139#define __NR_mremap 163
140#define __NR_query_module 167
141#define __NR_poll 168
142#define __NR_nfsservctl 169
143#define __NR_prctl 172
144#define __NR_rt_sigreturn 173
145#define __NR_rt_sigaction 174
146#define __NR_rt_sigprocmask 175
147#define __NR_rt_sigpending 176
148#define __NR_rt_sigtimedwait 177
149#define __NR_rt_sigqueueinfo 178
150#define __NR_rt_sigsuspend 179
151#define __NR_pread64 180
152#define __NR_pwrite64 181
153#define __NR_getcwd 183
154#define __NR_capget 184
155#define __NR_capset 185
156#define __NR_sigaltstack 186
157#define __NR_sendfile 187
158#define __NR_getpmsg 188
159#define __NR_putpmsg 189
160#define __NR_vfork 190
161#define __NR_pivot_root 217
162#define __NR_mincore 218
163#define __NR_madvise 219
164#define __NR_getdents64 220
165#define __NR_readahead 222
166#define __NR_setxattr 224
167#define __NR_lsetxattr 225
168#define __NR_fsetxattr 226
169#define __NR_getxattr 227
170#define __NR_lgetxattr 228
171#define __NR_fgetxattr 229
172#define __NR_listxattr 230
173#define __NR_llistxattr 231
174#define __NR_flistxattr 232
175#define __NR_removexattr 233
176#define __NR_lremovexattr 234
177#define __NR_fremovexattr 235
178#define __NR_gettid 236
179#define __NR_tkill 237
180#define __NR_futex 238
181#define __NR_sched_setaffinity 239
182#define __NR_sched_getaffinity 240
183#define __NR_tgkill 241
184/* Number 242 is reserved for tux */
185#define __NR_io_setup 243
186#define __NR_io_destroy 244
187#define __NR_io_getevents 245
188#define __NR_io_submit 246
189#define __NR_io_cancel 247
190#define __NR_exit_group 248
191#define __NR_epoll_create 249
192#define __NR_epoll_ctl 250
193#define __NR_epoll_wait 251
194#define __NR_set_tid_address 252
195#define __NR_fadvise64 253
196#define __NR_timer_create 254
197#define __NR_timer_settime (__NR_timer_create+1)
198#define __NR_timer_gettime (__NR_timer_create+2)
199#define __NR_timer_getoverrun (__NR_timer_create+3)
200#define __NR_timer_delete (__NR_timer_create+4)
201#define __NR_clock_settime (__NR_timer_create+5)
202#define __NR_clock_gettime (__NR_timer_create+6)
203#define __NR_clock_getres (__NR_timer_create+7)
204#define __NR_clock_nanosleep (__NR_timer_create+8)
205/* Number 263 is reserved for vserver */
206#define __NR_statfs64 265
207#define __NR_fstatfs64 266
208#define __NR_remap_file_pages 267
209/* Number 268 is reserved for new sys_mbind */
210/* Number 269 is reserved for new sys_get_mempolicy */
211/* Number 270 is reserved for new sys_set_mempolicy */
212#define __NR_mq_open 271
213#define __NR_mq_unlink 272
214#define __NR_mq_timedsend 273
215#define __NR_mq_timedreceive 274
216#define __NR_mq_notify 275
217#define __NR_mq_getsetattr 276
218#define __NR_kexec_load 277
219#define __NR_add_key 278
220#define __NR_request_key 279
221#define __NR_keyctl 280
222#define __NR_waitid 281
223#define __NR_ioprio_set 282
224#define __NR_ioprio_get 283
225#define __NR_inotify_init 284
226#define __NR_inotify_add_watch 285
227#define __NR_inotify_rm_watch 286
228/* Number 287 is reserved for new sys_migrate_pages */
229#define __NR_openat 288
230#define __NR_mkdirat 289
231#define __NR_mknodat 290
232#define __NR_fchownat 291
233#define __NR_futimesat 292
234#define __NR_unlinkat 294
235#define __NR_renameat 295
236#define __NR_linkat 296
237#define __NR_symlinkat 297
238#define __NR_readlinkat 298
239#define __NR_fchmodat 299
240#define __NR_faccessat 300
241#define __NR_pselect6 301
242#define __NR_ppoll 302
243#define __NR_unshare 303
244#define __NR_set_robust_list 304
245#define __NR_get_robust_list 305
246#define __NR_splice 306
247#define __NR_sync_file_range 307
248#define __NR_tee 308
249#define __NR_vmsplice 309
250/* Number 310 is reserved for new sys_move_pages */
251#define __NR_getcpu 311
252#define __NR_epoll_pwait 312
253#define __NR_utimes 313
254#define __NR_fallocate 314
255#define __NR_utimensat 315
256#define __NR_signalfd 316
257#define __NR_timerfd 317
258#define __NR_eventfd 318
259#define __NR_timerfd_create 319
260#define __NR_timerfd_settime 320
261#define __NR_timerfd_gettime 321
262#define NR_syscalls 322
263
264/*
265 * There are some system calls that are not present on 64 bit, some
266 * have a different name although they do the same (e.g. __NR_chown32
267 * is __NR_chown on 64 bit).
268 */
269#ifndef __s390x__
270
271#define __NR_time 13
272#define __NR_lchown 16
273#define __NR_setuid 23
274#define __NR_getuid 24
275#define __NR_stime 25
276#define __NR_setgid 46
277#define __NR_getgid 47
278#define __NR_geteuid 49
279#define __NR_getegid 50
280#define __NR_setreuid 70
281#define __NR_setregid 71
282#define __NR_getrlimit 76
283#define __NR_getgroups 80
284#define __NR_setgroups 81
285#define __NR_fchown 95
286#define __NR_ioperm 101
287#define __NR_setfsuid 138
288#define __NR_setfsgid 139
289#define __NR__llseek 140
290#define __NR__newselect 142
291#define __NR_setresuid 164
292#define __NR_getresuid 165
293#define __NR_setresgid 170
294#define __NR_getresgid 171
295#define __NR_chown 182
296#define __NR_ugetrlimit 191 /* SuS compliant getrlimit */
297#define __NR_mmap2 192
298#define __NR_truncate64 193
299#define __NR_ftruncate64 194
300#define __NR_stat64 195
301#define __NR_lstat64 196
302#define __NR_fstat64 197
303#define __NR_lchown32 198
304#define __NR_getuid32 199
305#define __NR_getgid32 200
306#define __NR_geteuid32 201
307#define __NR_getegid32 202
308#define __NR_setreuid32 203
309#define __NR_setregid32 204
310#define __NR_getgroups32 205
311#define __NR_setgroups32 206
312#define __NR_fchown32 207
313#define __NR_setresuid32 208
314#define __NR_getresuid32 209
315#define __NR_setresgid32 210
316#define __NR_getresgid32 211
317#define __NR_chown32 212
318#define __NR_setuid32 213
319#define __NR_setgid32 214
320#define __NR_setfsuid32 215
321#define __NR_setfsgid32 216
322#define __NR_fcntl64 221
323#define __NR_sendfile64 223
324#define __NR_fadvise64_64 264
325#define __NR_fstatat64 293
326
327#else
328
329#define __NR_select 142
330#define __NR_getrlimit 191 /* SuS compliant getrlimit */
331#define __NR_lchown 198
332#define __NR_getuid 199
333#define __NR_getgid 200
334#define __NR_geteuid 201
335#define __NR_getegid 202
336#define __NR_setreuid 203
337#define __NR_setregid 204
338#define __NR_getgroups 205
339#define __NR_setgroups 206
340#define __NR_fchown 207
341#define __NR_setresuid 208
342#define __NR_getresuid 209
343#define __NR_setresgid 210
344#define __NR_getresgid 211
345#define __NR_chown 212
346#define __NR_setuid 213
347#define __NR_setgid 214
348#define __NR_setfsuid 215
349#define __NR_setfsgid 216
350#define __NR_newfstatat 293
351
352#endif
353
354#ifdef __KERNEL__
355
356#ifndef CONFIG_64BIT
357#define __IGNORE_select
358#else
359#define __IGNORE_time
360#endif
361
362/* Ignore NUMA system calls. Not wired up on s390. */
363#define __IGNORE_mbind
364#define __IGNORE_get_mempolicy
365#define __IGNORE_set_mempolicy
366#define __IGNORE_migrate_pages
367#define __IGNORE_move_pages
368
369#define __ARCH_WANT_IPC_PARSE_VERSION
370#define __ARCH_WANT_OLD_READDIR
371#define __ARCH_WANT_SYS_ALARM
372#define __ARCH_WANT_SYS_GETHOSTNAME
373#define __ARCH_WANT_SYS_PAUSE
374#define __ARCH_WANT_SYS_SIGNAL
375#define __ARCH_WANT_SYS_UTIME
376#define __ARCH_WANT_SYS_SOCKETCALL
377#define __ARCH_WANT_SYS_FADVISE64
378#define __ARCH_WANT_SYS_GETPGRP
379#define __ARCH_WANT_SYS_LLSEEK
380#define __ARCH_WANT_SYS_NICE
381#define __ARCH_WANT_SYS_OLD_GETRLIMIT
382#define __ARCH_WANT_SYS_OLDUMOUNT
383#define __ARCH_WANT_SYS_SIGPENDING
384#define __ARCH_WANT_SYS_SIGPROCMASK
385#define __ARCH_WANT_SYS_RT_SIGACTION
386#define __ARCH_WANT_SYS_RT_SIGSUSPEND
387# ifndef CONFIG_64BIT
388# define __ARCH_WANT_STAT64
389# define __ARCH_WANT_SYS_TIME
390# endif
391# ifdef CONFIG_COMPAT
392# define __ARCH_WANT_COMPAT_SYS_TIME
393# define __ARCH_WANT_COMPAT_SYS_RT_SIGSUSPEND
394# endif
395
396/*
397 * "Conditional" syscalls
398 *
399 * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
400 * but it doesn't work on all toolchains, so we just do it by hand
401 */
402#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
403
404#endif /* __KERNEL__ */
405#endif /* _ASM_S390_UNISTD_H_ */
diff --git a/include/asm-s390/user.h b/include/asm-s390/user.h
deleted file mode 100644
index 1b050e35fdc..00000000000
--- a/include/asm-s390/user.h
+++ /dev/null
@@ -1,76 +0,0 @@
1/*
2 * include/asm-s390/user.h
3 *
4 * S390 version
5 *
6 * Derived from "include/asm-i386/usr.h"
7 */
8
9#ifndef _S390_USER_H
10#define _S390_USER_H
11
12#include <asm/page.h>
13#include <asm/ptrace.h>
14/* Core file format: The core file is written in such a way that gdb
15 can understand it and provide useful information to the user (under
16 linux we use the 'trad-core' bfd). There are quite a number of
17 obstacles to being able to view the contents of the floating point
18 registers, and until these are solved you will not be able to view the
19 contents of them. Actually, you can read in the core file and look at
20 the contents of the user struct to find out what the floating point
21 registers contain.
22 The actual file contents are as follows:
23 UPAGE: 1 page consisting of a user struct that tells gdb what is present
24 in the file. Directly after this is a copy of the task_struct, which
25 is currently not used by gdb, but it may come in useful at some point.
26 All of the registers are stored as part of the upage. The upage should
27 always be only one page.
28 DATA: The data area is stored. We use current->end_text to
29 current->brk to pick up all of the user variables, plus any memory
30 that may have been malloced. No attempt is made to determine if a page
31 is demand-zero or if a page is totally unused, we just cover the entire
32 range. All of the addresses are rounded in such a way that an integral
33 number of pages is written.
34 STACK: We need the stack information in order to get a meaningful
35 backtrace. We need to write the data from (esp) to
36 current->start_stack, so we round each of these off in order to be able
37 to write an integer number of pages.
38 The minimum core file size is 3 pages, or 12288 bytes.
39*/
40
41
42/*
43 * This is the old layout of "struct pt_regs", and
44 * is still the layout used by user mode (the new
45 * pt_regs doesn't have all registers as the kernel
46 * doesn't use the extra segment registers)
47 */
48
49/* When the kernel dumps core, it starts by dumping the user struct -
50 this will be used by gdb to figure out where the data and stack segments
51 are within the file, and what virtual addresses to use. */
52struct user {
53/* We start with the registers, to mimic the way that "memory" is returned
54 from the ptrace(3,...) function. */
55 struct user_regs_struct regs; /* Where the registers are actually stored */
56/* The rest of this junk is to help gdb figure out what goes where */
57 unsigned long int u_tsize; /* Text segment size (pages). */
58 unsigned long int u_dsize; /* Data segment size (pages). */
59 unsigned long int u_ssize; /* Stack segment size (pages). */
60 unsigned long start_code; /* Starting virtual address of text. */
61 unsigned long start_stack; /* Starting virtual address of stack area.
62 This is actually the bottom of the stack,
63 the top of the stack is always found in the
64 esp register. */
65 long int signal; /* Signal that caused the core dump. */
66 unsigned long u_ar0; /* Used by gdb to help find the values for */
67 /* the registers. */
68 unsigned long magic; /* To uniquely identify a core file */
69 char u_comm[32]; /* User command that was responsible */
70};
71#define NBPG PAGE_SIZE
72#define UPAGES 1
73#define HOST_TEXT_START_ADDR (u.start_code)
74#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
75
76#endif /* _S390_USER_H */
diff --git a/include/asm-s390/vtoc.h b/include/asm-s390/vtoc.h
deleted file mode 100644
index 3a5267d90d2..00000000000
--- a/include/asm-s390/vtoc.h
+++ /dev/null
@@ -1,203 +0,0 @@
1/*
2 * include/asm-s390/vtoc.h
3 *
4 * This file contains volume label definitions for DASD devices.
5 *
6 * (C) Copyright IBM Corp. 2005
7 *
8 * Author(s): Volker Sameske <sameske@de.ibm.com>
9 *
10 */
11
12#ifndef _ASM_S390_VTOC_H
13#define _ASM_S390_VTOC_H
14
15#include <linux/types.h>
16
17struct vtoc_ttr
18{
19 __u16 tt;
20 __u8 r;
21} __attribute__ ((packed));
22
23struct vtoc_cchhb
24{
25 __u16 cc;
26 __u16 hh;
27 __u8 b;
28} __attribute__ ((packed));
29
30struct vtoc_cchh
31{
32 __u16 cc;
33 __u16 hh;
34} __attribute__ ((packed));
35
36struct vtoc_labeldate
37{
38 __u8 year;
39 __u16 day;
40} __attribute__ ((packed));
41
42struct vtoc_volume_label
43{
44 char volkey[4]; /* volume key = volume label */
45 char vollbl[4]; /* volume label */
46 char volid[6]; /* volume identifier */
47 __u8 security; /* security byte */
48 struct vtoc_cchhb vtoc; /* VTOC address */
49 char res1[5]; /* reserved */
50 char cisize[4]; /* CI-size for FBA,... */
51 /* ...blanks for CKD */
52 char blkperci[4]; /* no of blocks per CI (FBA), blanks for CKD */
53 char labperci[4]; /* no of labels per CI (FBA), blanks for CKD */
54 char res2[4]; /* reserved */
55 char lvtoc[14]; /* owner code for LVTOC */
56 char res3[29]; /* reserved */
57} __attribute__ ((packed));
58
59struct vtoc_extent
60{
61 __u8 typeind; /* extent type indicator */
62 __u8 seqno; /* extent sequence number */
63 struct vtoc_cchh llimit; /* starting point of this extent */
64 struct vtoc_cchh ulimit; /* ending point of this extent */
65} __attribute__ ((packed));
66
67struct vtoc_dev_const
68{
69 __u16 DS4DSCYL; /* number of logical cyls */
70 __u16 DS4DSTRK; /* number of tracks in a logical cylinder */
71 __u16 DS4DEVTK; /* device track length */
72 __u8 DS4DEVI; /* non-last keyed record overhead */
73 __u8 DS4DEVL; /* last keyed record overhead */
74 __u8 DS4DEVK; /* non-keyed record overhead differential */
75 __u8 DS4DEVFG; /* flag byte */
76 __u16 DS4DEVTL; /* device tolerance */
77 __u8 DS4DEVDT; /* number of DSCB's per track */
78 __u8 DS4DEVDB; /* number of directory blocks per track */
79} __attribute__ ((packed));
80
81struct vtoc_format1_label
82{
83 char DS1DSNAM[44]; /* data set name */
84 __u8 DS1FMTID; /* format identifier */
85 char DS1DSSN[6]; /* data set serial number */
86 __u16 DS1VOLSQ; /* volume sequence number */
87 struct vtoc_labeldate DS1CREDT; /* creation date: ydd */
88 struct vtoc_labeldate DS1EXPDT; /* expiration date */
89 __u8 DS1NOEPV; /* number of extents on volume */
90 __u8 DS1NOBDB; /* no. of bytes used in last direction blk */
91 __u8 DS1FLAG1; /* flag 1 */
92 char DS1SYSCD[13]; /* system code */
93 struct vtoc_labeldate DS1REFD; /* date last referenced */
94 __u8 DS1SMSFG; /* system managed storage indicators */
95 __u8 DS1SCXTF; /* sec. space extension flag byte */
96 __u16 DS1SCXTV; /* secondary space extension value */
97 __u8 DS1DSRG1; /* data set organisation byte 1 */
98 __u8 DS1DSRG2; /* data set organisation byte 2 */
99 __u8 DS1RECFM; /* record format */
100 __u8 DS1OPTCD; /* option code */
101 __u16 DS1BLKL; /* block length */
102 __u16 DS1LRECL; /* record length */
103 __u8 DS1KEYL; /* key length */
104 __u16 DS1RKP; /* relative key position */
105 __u8 DS1DSIND; /* data set indicators */
106 __u8 DS1SCAL1; /* secondary allocation flag byte */
107 char DS1SCAL3[3]; /* secondary allocation quantity */
108 struct vtoc_ttr DS1LSTAR; /* last used track and block on track */
109 __u16 DS1TRBAL; /* space remaining on last used track */
110 __u16 res1; /* reserved */
111 struct vtoc_extent DS1EXT1; /* first extent description */
112 struct vtoc_extent DS1EXT2; /* second extent description */
113 struct vtoc_extent DS1EXT3; /* third extent description */
114 struct vtoc_cchhb DS1PTRDS; /* possible pointer to f2 or f3 DSCB */
115} __attribute__ ((packed));
116
117struct vtoc_format4_label
118{
119 char DS4KEYCD[44]; /* key code for VTOC labels: 44 times 0x04 */
120 __u8 DS4IDFMT; /* format identifier */
121 struct vtoc_cchhb DS4HPCHR; /* highest address of a format 1 DSCB */
122 __u16 DS4DSREC; /* number of available DSCB's */
123 struct vtoc_cchh DS4HCCHH; /* CCHH of next available alternate track */
124 __u16 DS4NOATK; /* number of remaining alternate tracks */
125 __u8 DS4VTOCI; /* VTOC indicators */
126 __u8 DS4NOEXT; /* number of extents in VTOC */
127 __u8 DS4SMSFG; /* system managed storage indicators */
128 __u8 DS4DEVAC; /* number of alternate cylinders.
129 * Subtract from first two bytes of
130 * DS4DEVSZ to get number of usable
131 * cylinders. can be zero. valid
132 * only if DS4DEVAV on. */
133 struct vtoc_dev_const DS4DEVCT; /* device constants */
134 char DS4AMTIM[8]; /* VSAM time stamp */
135 char DS4AMCAT[3]; /* VSAM catalog indicator */
136 char DS4R2TIM[8]; /* VSAM volume/catalog match time stamp */
137 char res1[5]; /* reserved */
138 char DS4F6PTR[5]; /* pointer to first format 6 DSCB */
139 struct vtoc_extent DS4VTOCE; /* VTOC extent description */
140 char res2[10]; /* reserved */
141 __u8 DS4EFLVL; /* extended free-space management level */
142 struct vtoc_cchhb DS4EFPTR; /* pointer to extended free-space info */
143 char res3[9]; /* reserved */
144} __attribute__ ((packed));
145
146struct vtoc_ds5ext
147{
148 __u16 t; /* RTA of the first track of free extent */
149 __u16 fc; /* number of whole cylinders in free ext. */
150 __u8 ft; /* number of remaining free tracks */
151} __attribute__ ((packed));
152
153struct vtoc_format5_label
154{
155 char DS5KEYID[4]; /* key identifier */
156 struct vtoc_ds5ext DS5AVEXT; /* first available (free-space) extent. */
157 struct vtoc_ds5ext DS5EXTAV[7]; /* seven available extents */
158 __u8 DS5FMTID; /* format identifier */
159 struct vtoc_ds5ext DS5MAVET[18]; /* eighteen available extents */
160 struct vtoc_cchhb DS5PTRDS; /* pointer to next format5 DSCB */
161} __attribute__ ((packed));
162
163struct vtoc_ds7ext
164{
165 __u32 a; /* starting RTA value */
166 __u32 b; /* ending RTA value + 1 */
167} __attribute__ ((packed));
168
169struct vtoc_format7_label
170{
171 char DS7KEYID[4]; /* key identifier */
172 struct vtoc_ds7ext DS7EXTNT[5]; /* space for 5 extent descriptions */
173 __u8 DS7FMTID; /* format identifier */
174 struct vtoc_ds7ext DS7ADEXT[11]; /* space for 11 extent descriptions */
175 char res1[2]; /* reserved */
176 struct vtoc_cchhb DS7PTRDS; /* pointer to next FMT7 DSCB */
177} __attribute__ ((packed));
178
179struct vtoc_cms_label {
180 __u8 label_id[4]; /* Label identifier */
181 __u8 vol_id[6]; /* Volid */
182 __u16 version_id; /* Version identifier */
183 __u32 block_size; /* Disk block size */
184 __u32 origin_ptr; /* Disk origin pointer */
185 __u32 usable_count; /* Number of usable cylinders/blocks */
186 __u32 formatted_count; /* Maximum number of formatted cylinders/
187 * blocks */
188 __u32 block_count; /* Disk size in CMS blocks */
189 __u32 used_count; /* Number of CMS blocks in use */
190 __u32 fst_size; /* File Status Table (FST) size */
191 __u32 fst_count; /* Number of FSTs per CMS block */
192 __u8 format_date[6]; /* Disk FORMAT date */
193 __u8 reserved1[2];
194 __u32 disk_offset; /* Disk offset when reserved*/
195 __u32 map_block; /* Allocation Map Block with next hole */
196 __u32 hblk_disp; /* Displacement into HBLK data of next hole */
197 __u32 user_disp; /* Displacement into user part of Allocation
198 * map */
199 __u8 reserved2[4];
200 __u8 segment_name[8]; /* Name of shared segment */
201} __attribute__ ((packed));
202
203#endif /* _ASM_S390_VTOC_H */
diff --git a/include/asm-s390/xor.h b/include/asm-s390/xor.h
deleted file mode 100644
index c82eb12a5b1..00000000000
--- a/include/asm-s390/xor.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/xor.h>
diff --git a/include/asm-s390/zcrypt.h b/include/asm-s390/zcrypt.h
deleted file mode 100644
index 00d3bbd4411..00000000000
--- a/include/asm-s390/zcrypt.h
+++ /dev/null
@@ -1,276 +0,0 @@
1/*
2 * include/asm-s390/zcrypt.h
3 *
4 * zcrypt 2.1.0 (user-visible header)
5 *
6 * Copyright (C) 2001, 2006 IBM Corporation
7 * Author(s): Robert Burroughs
8 * Eric Rossman (edrossma@us.ibm.com)
9 *
10 * Hotplug & misc device support: Jochen Roehrig (roehrig@de.ibm.com)
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#ifndef __ASM_S390_ZCRYPT_H
28#define __ASM_S390_ZCRYPT_H
29
30#define ZCRYPT_VERSION 2
31#define ZCRYPT_RELEASE 1
32#define ZCRYPT_VARIANT 1
33
34#include <linux/ioctl.h>
35#include <linux/compiler.h>
36
37/**
38 * struct ica_rsa_modexpo
39 *
40 * Requirements:
41 * - outputdatalength is at least as large as inputdatalength.
42 * - All key parts are right justified in their fields, padded on
43 * the left with zeroes.
44 * - length(b_key) = inputdatalength
45 * - length(n_modulus) = inputdatalength
46 */
47struct ica_rsa_modexpo {
48 char __user * inputdata;
49 unsigned int inputdatalength;
50 char __user * outputdata;
51 unsigned int outputdatalength;
52 char __user * b_key;
53 char __user * n_modulus;
54};
55
56/**
57 * struct ica_rsa_modexpo_crt
58 *
59 * Requirements:
60 * - inputdatalength is even.
61 * - outputdatalength is at least as large as inputdatalength.
62 * - All key parts are right justified in their fields, padded on
63 * the left with zeroes.
64 * - length(bp_key) = inputdatalength/2 + 8
65 * - length(bq_key) = inputdatalength/2
66 * - length(np_key) = inputdatalength/2 + 8
67 * - length(nq_key) = inputdatalength/2
68 * - length(u_mult_inv) = inputdatalength/2 + 8
69 */
70struct ica_rsa_modexpo_crt {
71 char __user * inputdata;
72 unsigned int inputdatalength;
73 char __user * outputdata;
74 unsigned int outputdatalength;
75 char __user * bp_key;
76 char __user * bq_key;
77 char __user * np_prime;
78 char __user * nq_prime;
79 char __user * u_mult_inv;
80};
81
82/**
83 * CPRBX
84 * Note that all shorts and ints are big-endian.
85 * All pointer fields are 16 bytes long, and mean nothing.
86 *
87 * A request CPRB is followed by a request_parameter_block.
88 *
89 * The request (or reply) parameter block is organized thus:
90 * function code
91 * VUD block
92 * key block
93 */
94struct CPRBX {
95 unsigned short cprb_len; /* CPRB length 220 */
96 unsigned char cprb_ver_id; /* CPRB version id. 0x02 */
97 unsigned char pad_000[3]; /* Alignment pad bytes */
98 unsigned char func_id[2]; /* function id 0x5432 */
99 unsigned char cprb_flags[4]; /* Flags */
100 unsigned int req_parml; /* request parameter buffer len */
101 unsigned int req_datal; /* request data buffer */
102 unsigned int rpl_msgbl; /* reply message block length */
103 unsigned int rpld_parml; /* replied parameter block len */
104 unsigned int rpl_datal; /* reply data block len */
105 unsigned int rpld_datal; /* replied data block len */
106 unsigned int req_extbl; /* request extension block len */
107 unsigned char pad_001[4]; /* reserved */
108 unsigned int rpld_extbl; /* replied extension block len */
109 unsigned char padx000[16 - sizeof (char *)];
110 unsigned char * req_parmb; /* request parm block 'address' */
111 unsigned char padx001[16 - sizeof (char *)];
112 unsigned char * req_datab; /* request data block 'address' */
113 unsigned char padx002[16 - sizeof (char *)];
114 unsigned char * rpl_parmb; /* reply parm block 'address' */
115 unsigned char padx003[16 - sizeof (char *)];
116 unsigned char * rpl_datab; /* reply data block 'address' */
117 unsigned char padx004[16 - sizeof (char *)];
118 unsigned char * req_extb; /* request extension block 'addr'*/
119 unsigned char padx005[16 - sizeof (char *)];
120 unsigned char * rpl_extb; /* reply extension block 'address'*/
121 unsigned short ccp_rtcode; /* server return code */
122 unsigned short ccp_rscode; /* server reason code */
123 unsigned int mac_data_len; /* Mac Data Length */
124 unsigned char logon_id[8]; /* Logon Identifier */
125 unsigned char mac_value[8]; /* Mac Value */
126 unsigned char mac_content_flgs;/* Mac content flag byte */
127 unsigned char pad_002; /* Alignment */
128 unsigned short domain; /* Domain */
129 unsigned char usage_domain[4];/* Usage domain */
130 unsigned char cntrl_domain[4];/* Control domain */
131 unsigned char S390enf_mask[4];/* S/390 enforcement mask */
132 unsigned char pad_004[36]; /* reserved */
133} __attribute__((packed));
134
135/**
136 * xcRB
137 */
138struct ica_xcRB {
139 unsigned short agent_ID;
140 unsigned int user_defined;
141 unsigned short request_ID;
142 unsigned int request_control_blk_length;
143 unsigned char padding1[16 - sizeof (char *)];
144 char __user * request_control_blk_addr;
145 unsigned int request_data_length;
146 char padding2[16 - sizeof (char *)];
147 char __user * request_data_address;
148 unsigned int reply_control_blk_length;
149 char padding3[16 - sizeof (char *)];
150 char __user * reply_control_blk_addr;
151 unsigned int reply_data_length;
152 char padding4[16 - sizeof (char *)];
153 char __user * reply_data_addr;
154 unsigned short priority_window;
155 unsigned int status;
156} __attribute__((packed));
157#define AUTOSELECT ((unsigned int)0xFFFFFFFF)
158
159#define ZCRYPT_IOCTL_MAGIC 'z'
160
161/**
162 * Interface notes:
163 *
164 * The ioctl()s which are implemented (along with relevant details)
165 * are:
166 *
167 * ICARSAMODEXPO
168 * Perform an RSA operation using a Modulus-Exponent pair
169 * This takes an ica_rsa_modexpo struct as its arg.
170 *
171 * NOTE: please refer to the comments preceding this structure
172 * for the implementation details for the contents of the
173 * block
174 *
175 * ICARSACRT
176 * Perform an RSA operation using a Chinese-Remainder Theorem key
177 * This takes an ica_rsa_modexpo_crt struct as its arg.
178 *
179 * NOTE: please refer to the comments preceding this structure
180 * for the implementation details for the contents of the
181 * block
182 *
183 * ZSECSENDCPRB
184 * Send an arbitrary CPRB to a crypto card.
185 *
186 * Z90STAT_STATUS_MASK
187 * Return an 64 element array of unsigned chars for the status of
188 * all devices.
189 * 0x01: PCICA
190 * 0x02: PCICC
191 * 0x03: PCIXCC_MCL2
192 * 0x04: PCIXCC_MCL3
193 * 0x05: CEX2C
194 * 0x06: CEX2A
195 * 0x0d: device is disabled via the proc filesystem
196 *
197 * Z90STAT_QDEPTH_MASK
198 * Return an 64 element array of unsigned chars for the queue
199 * depth of all devices.
200 *
201 * Z90STAT_PERDEV_REQCNT
202 * Return an 64 element array of unsigned integers for the number
203 * of successfully completed requests per device since the device
204 * was detected and made available.
205 *
206 * Z90STAT_REQUESTQ_COUNT
207 * Return an integer count of the number of entries waiting to be
208 * sent to a device.
209 *
210 * Z90STAT_PENDINGQ_COUNT
211 * Return an integer count of the number of entries sent to all
212 * devices awaiting the reply.
213 *
214 * Z90STAT_TOTALOPEN_COUNT
215 * Return an integer count of the number of open file handles.
216 *
217 * Z90STAT_DOMAIN_INDEX
218 * Return the integer value of the Cryptographic Domain.
219 *
220 * The following ioctls are deprecated and should be no longer used:
221 *
222 * Z90STAT_TOTALCOUNT
223 * Return an integer count of all device types together.
224 *
225 * Z90STAT_PCICACOUNT
226 * Return an integer count of all PCICAs.
227 *
228 * Z90STAT_PCICCCOUNT
229 * Return an integer count of all PCICCs.
230 *
231 * Z90STAT_PCIXCCMCL2COUNT
232 * Return an integer count of all MCL2 PCIXCCs.
233 *
234 * Z90STAT_PCIXCCMCL3COUNT
235 * Return an integer count of all MCL3 PCIXCCs.
236 *
237 * Z90STAT_CEX2CCOUNT
238 * Return an integer count of all CEX2Cs.
239 *
240 * Z90STAT_CEX2ACOUNT
241 * Return an integer count of all CEX2As.
242 *
243 * ICAZ90STATUS
244 * Return some device driver status in a ica_z90_status struct
245 * This takes an ica_z90_status struct as its arg.
246 *
247 * Z90STAT_PCIXCCCOUNT
248 * Return an integer count of all PCIXCCs (MCL2 + MCL3).
249 * This is DEPRECATED now that MCL3 PCIXCCs are treated differently from
250 * MCL2 PCIXCCs.
251 */
252
253/**
254 * Supported ioctl calls
255 */
256#define ICARSAMODEXPO _IOC(_IOC_READ|_IOC_WRITE, ZCRYPT_IOCTL_MAGIC, 0x05, 0)
257#define ICARSACRT _IOC(_IOC_READ|_IOC_WRITE, ZCRYPT_IOCTL_MAGIC, 0x06, 0)
258#define ZSECSENDCPRB _IOC(_IOC_READ|_IOC_WRITE, ZCRYPT_IOCTL_MAGIC, 0x81, 0)
259
260/* New status calls */
261#define Z90STAT_TOTALCOUNT _IOR(ZCRYPT_IOCTL_MAGIC, 0x40, int)
262#define Z90STAT_PCICACOUNT _IOR(ZCRYPT_IOCTL_MAGIC, 0x41, int)
263#define Z90STAT_PCICCCOUNT _IOR(ZCRYPT_IOCTL_MAGIC, 0x42, int)
264#define Z90STAT_PCIXCCMCL2COUNT _IOR(ZCRYPT_IOCTL_MAGIC, 0x4b, int)
265#define Z90STAT_PCIXCCMCL3COUNT _IOR(ZCRYPT_IOCTL_MAGIC, 0x4c, int)
266#define Z90STAT_CEX2CCOUNT _IOR(ZCRYPT_IOCTL_MAGIC, 0x4d, int)
267#define Z90STAT_CEX2ACOUNT _IOR(ZCRYPT_IOCTL_MAGIC, 0x4e, int)
268#define Z90STAT_REQUESTQ_COUNT _IOR(ZCRYPT_IOCTL_MAGIC, 0x44, int)
269#define Z90STAT_PENDINGQ_COUNT _IOR(ZCRYPT_IOCTL_MAGIC, 0x45, int)
270#define Z90STAT_TOTALOPEN_COUNT _IOR(ZCRYPT_IOCTL_MAGIC, 0x46, int)
271#define Z90STAT_DOMAIN_INDEX _IOR(ZCRYPT_IOCTL_MAGIC, 0x47, int)
272#define Z90STAT_STATUS_MASK _IOR(ZCRYPT_IOCTL_MAGIC, 0x48, char[64])
273#define Z90STAT_QDEPTH_MASK _IOR(ZCRYPT_IOCTL_MAGIC, 0x49, char[64])
274#define Z90STAT_PERDEV_REQCNT _IOR(ZCRYPT_IOCTL_MAGIC, 0x4a, int[64])
275
276#endif /* __ASM_S390_ZCRYPT_H */
diff --git a/include/asm-sh/.gitignore b/include/asm-sh/.gitignore
deleted file mode 100644
index 9218ef82b69..00000000000
--- a/include/asm-sh/.gitignore
+++ /dev/null
@@ -1,3 +0,0 @@
1cpu
2mach
3machtypes.h
diff --git a/include/asm-sh/Kbuild b/include/asm-sh/Kbuild
deleted file mode 100644
index 43910cdf78a..00000000000
--- a/include/asm-sh/Kbuild
+++ /dev/null
@@ -1,8 +0,0 @@
1include include/asm-generic/Kbuild.asm
2
3header-y += cpu-features.h
4
5unifdef-y += unistd_32.h
6unifdef-y += unistd_64.h
7unifdef-y += posix_types_32.h
8unifdef-y += posix_types_64.h
diff --git a/include/asm-sh/a.out.h b/include/asm-sh/a.out.h
deleted file mode 100644
index 1f93130e179..00000000000
--- a/include/asm-sh/a.out.h
+++ /dev/null
@@ -1,20 +0,0 @@
1#ifndef __ASM_SH_A_OUT_H
2#define __ASM_SH_A_OUT_H
3
4struct exec
5{
6 unsigned long a_info; /* Use macros N_MAGIC, etc for access */
7 unsigned a_text; /* length of text, in bytes */
8 unsigned a_data; /* length of data, in bytes */
9 unsigned a_bss; /* length of uninitialized data area for file, in bytes */
10 unsigned a_syms; /* length of symbol table data in file, in bytes */
11 unsigned a_entry; /* start address */
12 unsigned a_trsize; /* length of relocation info for text, in bytes */
13 unsigned a_drsize; /* length of relocation info for data, in bytes */
14};
15
16#define N_TRSIZE(a) ((a).a_trsize)
17#define N_DRSIZE(a) ((a).a_drsize)
18#define N_SYMSIZE(a) ((a).a_syms)
19
20#endif /* __ASM_SH_A_OUT_H */
diff --git a/include/asm-sh/adc.h b/include/asm-sh/adc.h
deleted file mode 100644
index 5f85cf74d59..00000000000
--- a/include/asm-sh/adc.h
+++ /dev/null
@@ -1,13 +0,0 @@
1#ifndef __ASM_ADC_H
2#define __ASM_ADC_H
3#ifdef __KERNEL__
4/*
5 * Copyright (C) 2004 Andriy Skulysh
6 */
7
8#include <asm/cpu/adc.h>
9
10int adc_single(unsigned int channel);
11
12#endif /* __KERNEL__ */
13#endif /* __ASM_ADC_H */
diff --git a/include/asm-sh/addrspace.h b/include/asm-sh/addrspace.h
deleted file mode 100644
index fa544fc38c2..00000000000
--- a/include/asm-sh/addrspace.h
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1999 by Kaz Kojima
7 *
8 * Defitions for the address spaces of the SH CPUs.
9 */
10#ifndef __ASM_SH_ADDRSPACE_H
11#define __ASM_SH_ADDRSPACE_H
12
13#ifdef __KERNEL__
14
15#include <asm/cpu/addrspace.h>
16
17/* If this CPU supports segmentation, hook up the helpers */
18#ifdef P1SEG
19
20/*
21 [ P0/U0 (virtual) ] 0x00000000 <------ User space
22 [ P1 (fixed) cached ] 0x80000000 <------ Kernel space
23 [ P2 (fixed) non-cachable] 0xA0000000 <------ Physical access
24 [ P3 (virtual) cached] 0xC0000000 <------ vmalloced area
25 [ P4 control ] 0xE0000000
26 */
27
28/* Returns the privileged segment base of a given address */
29#define PXSEG(a) (((unsigned long)(a)) & 0xe0000000)
30
31/* Returns the physical address of a PnSEG (n=1,2) address */
32#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff)
33
34#ifdef CONFIG_29BIT
35/*
36 * Map an address to a certain privileged segment
37 */
38#define P1SEGADDR(a) \
39 ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG))
40#define P2SEGADDR(a) \
41 ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG))
42#define P3SEGADDR(a) \
43 ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG))
44#define P4SEGADDR(a) \
45 ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG))
46#endif /* 29BIT */
47#endif /* P1SEG */
48
49/* Check if an address can be reached in 29 bits */
50#define IS_29BIT(a) (((unsigned long)(a)) < 0x20000000)
51
52#endif /* __KERNEL__ */
53#endif /* __ASM_SH_ADDRSPACE_H */
diff --git a/include/asm-sh/atomic-grb.h b/include/asm-sh/atomic-grb.h
deleted file mode 100644
index 4c5b7dbfced..00000000000
--- a/include/asm-sh/atomic-grb.h
+++ /dev/null
@@ -1,169 +0,0 @@
1#ifndef __ASM_SH_ATOMIC_GRB_H
2#define __ASM_SH_ATOMIC_GRB_H
3
4static inline void atomic_add(int i, atomic_t *v)
5{
6 int tmp;
7
8 __asm__ __volatile__ (
9 " .align 2 \n\t"
10 " mova 1f, r0 \n\t" /* r0 = end point */
11 " mov r15, r1 \n\t" /* r1 = saved sp */
12 " mov #-6, r15 \n\t" /* LOGIN: r15 = size */
13 " mov.l @%1, %0 \n\t" /* load old value */
14 " add %2, %0 \n\t" /* add */
15 " mov.l %0, @%1 \n\t" /* store new value */
16 "1: mov r1, r15 \n\t" /* LOGOUT */
17 : "=&r" (tmp),
18 "+r" (v)
19 : "r" (i)
20 : "memory" , "r0", "r1");
21}
22
23static inline void atomic_sub(int i, atomic_t *v)
24{
25 int tmp;
26
27 __asm__ __volatile__ (
28 " .align 2 \n\t"
29 " mova 1f, r0 \n\t" /* r0 = end point */
30 " mov r15, r1 \n\t" /* r1 = saved sp */
31 " mov #-6, r15 \n\t" /* LOGIN: r15 = size */
32 " mov.l @%1, %0 \n\t" /* load old value */
33 " sub %2, %0 \n\t" /* sub */
34 " mov.l %0, @%1 \n\t" /* store new value */
35 "1: mov r1, r15 \n\t" /* LOGOUT */
36 : "=&r" (tmp),
37 "+r" (v)
38 : "r" (i)
39 : "memory" , "r0", "r1");
40}
41
42static inline int atomic_add_return(int i, atomic_t *v)
43{
44 int tmp;
45
46 __asm__ __volatile__ (
47 " .align 2 \n\t"
48 " mova 1f, r0 \n\t" /* r0 = end point */
49 " mov r15, r1 \n\t" /* r1 = saved sp */
50 " mov #-6, r15 \n\t" /* LOGIN: r15 = size */
51 " mov.l @%1, %0 \n\t" /* load old value */
52 " add %2, %0 \n\t" /* add */
53 " mov.l %0, @%1 \n\t" /* store new value */
54 "1: mov r1, r15 \n\t" /* LOGOUT */
55 : "=&r" (tmp),
56 "+r" (v)
57 : "r" (i)
58 : "memory" , "r0", "r1");
59
60 return tmp;
61}
62
63static inline int atomic_sub_return(int i, atomic_t *v)
64{
65 int tmp;
66
67 __asm__ __volatile__ (
68 " .align 2 \n\t"
69 " mova 1f, r0 \n\t" /* r0 = end point */
70 " mov r15, r1 \n\t" /* r1 = saved sp */
71 " mov #-6, r15 \n\t" /* LOGIN: r15 = size */
72 " mov.l @%1, %0 \n\t" /* load old value */
73 " sub %2, %0 \n\t" /* sub */
74 " mov.l %0, @%1 \n\t" /* store new value */
75 "1: mov r1, r15 \n\t" /* LOGOUT */
76 : "=&r" (tmp),
77 "+r" (v)
78 : "r" (i)
79 : "memory", "r0", "r1");
80
81 return tmp;
82}
83
84static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
85{
86 int tmp;
87 unsigned int _mask = ~mask;
88
89 __asm__ __volatile__ (
90 " .align 2 \n\t"
91 " mova 1f, r0 \n\t" /* r0 = end point */
92 " mov r15, r1 \n\t" /* r1 = saved sp */
93 " mov #-6, r15 \n\t" /* LOGIN: r15 = size */
94 " mov.l @%1, %0 \n\t" /* load old value */
95 " and %2, %0 \n\t" /* add */
96 " mov.l %0, @%1 \n\t" /* store new value */
97 "1: mov r1, r15 \n\t" /* LOGOUT */
98 : "=&r" (tmp),
99 "+r" (v)
100 : "r" (_mask)
101 : "memory" , "r0", "r1");
102}
103
104static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
105{
106 int tmp;
107
108 __asm__ __volatile__ (
109 " .align 2 \n\t"
110 " mova 1f, r0 \n\t" /* r0 = end point */
111 " mov r15, r1 \n\t" /* r1 = saved sp */
112 " mov #-6, r15 \n\t" /* LOGIN: r15 = size */
113 " mov.l @%1, %0 \n\t" /* load old value */
114 " or %2, %0 \n\t" /* or */
115 " mov.l %0, @%1 \n\t" /* store new value */
116 "1: mov r1, r15 \n\t" /* LOGOUT */
117 : "=&r" (tmp),
118 "+r" (v)
119 : "r" (mask)
120 : "memory" , "r0", "r1");
121}
122
123static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
124{
125 int ret;
126
127 __asm__ __volatile__ (
128 " .align 2 \n\t"
129 " mova 1f, r0 \n\t"
130 " nop \n\t"
131 " mov r15, r1 \n\t"
132 " mov #-8, r15 \n\t"
133 " mov.l @%1, %0 \n\t"
134 " cmp/eq %2, %0 \n\t"
135 " bf 1f \n\t"
136 " mov.l %3, @%1 \n\t"
137 "1: mov r1, r15 \n\t"
138 : "=&r" (ret)
139 : "r" (v), "r" (old), "r" (new)
140 : "memory" , "r0", "r1" , "t");
141
142 return ret;
143}
144
145static inline int atomic_add_unless(atomic_t *v, int a, int u)
146{
147 int ret;
148 unsigned long tmp;
149
150 __asm__ __volatile__ (
151 " .align 2 \n\t"
152 " mova 1f, r0 \n\t"
153 " nop \n\t"
154 " mov r15, r1 \n\t"
155 " mov #-12, r15 \n\t"
156 " mov.l @%2, %1 \n\t"
157 " mov %1, %0 \n\t"
158 " cmp/eq %4, %0 \n\t"
159 " bt/s 1f \n\t"
160 " add %3, %1 \n\t"
161 " mov.l %1, @%2 \n\t"
162 "1: mov r1, r15 \n\t"
163 : "=&r" (ret), "=&r" (tmp)
164 : "r" (v), "r" (a), "r" (u)
165 : "memory" , "r0", "r1" , "t");
166
167 return ret != u;
168}
169#endif /* __ASM_SH_ATOMIC_GRB_H */
diff --git a/include/asm-sh/atomic-irq.h b/include/asm-sh/atomic-irq.h
deleted file mode 100644
index 74f7943cff6..00000000000
--- a/include/asm-sh/atomic-irq.h
+++ /dev/null
@@ -1,71 +0,0 @@
1#ifndef __ASM_SH_ATOMIC_IRQ_H
2#define __ASM_SH_ATOMIC_IRQ_H
3
4/*
5 * To get proper branch prediction for the main line, we must branch
6 * forward to code at the end of this object's .text section, then
7 * branch back to restart the operation.
8 */
9static inline void atomic_add(int i, atomic_t *v)
10{
11 unsigned long flags;
12
13 local_irq_save(flags);
14 *(long *)v += i;
15 local_irq_restore(flags);
16}
17
18static inline void atomic_sub(int i, atomic_t *v)
19{
20 unsigned long flags;
21
22 local_irq_save(flags);
23 *(long *)v -= i;
24 local_irq_restore(flags);
25}
26
27static inline int atomic_add_return(int i, atomic_t *v)
28{
29 unsigned long temp, flags;
30
31 local_irq_save(flags);
32 temp = *(long *)v;
33 temp += i;
34 *(long *)v = temp;
35 local_irq_restore(flags);
36
37 return temp;
38}
39
40static inline int atomic_sub_return(int i, atomic_t *v)
41{
42 unsigned long temp, flags;
43
44 local_irq_save(flags);
45 temp = *(long *)v;
46 temp -= i;
47 *(long *)v = temp;
48 local_irq_restore(flags);
49
50 return temp;
51}
52
53static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
54{
55 unsigned long flags;
56
57 local_irq_save(flags);
58 *(long *)v &= ~mask;
59 local_irq_restore(flags);
60}
61
62static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
63{
64 unsigned long flags;
65
66 local_irq_save(flags);
67 *(long *)v |= mask;
68 local_irq_restore(flags);
69}
70
71#endif /* __ASM_SH_ATOMIC_IRQ_H */
diff --git a/include/asm-sh/atomic-llsc.h b/include/asm-sh/atomic-llsc.h
deleted file mode 100644
index 4b00b78e3f4..00000000000
--- a/include/asm-sh/atomic-llsc.h
+++ /dev/null
@@ -1,107 +0,0 @@
1#ifndef __ASM_SH_ATOMIC_LLSC_H
2#define __ASM_SH_ATOMIC_LLSC_H
3
4/*
5 * To get proper branch prediction for the main line, we must branch
6 * forward to code at the end of this object's .text section, then
7 * branch back to restart the operation.
8 */
9static inline void atomic_add(int i, atomic_t *v)
10{
11 unsigned long tmp;
12
13 __asm__ __volatile__ (
14"1: movli.l @%2, %0 ! atomic_add \n"
15" add %1, %0 \n"
16" movco.l %0, @%2 \n"
17" bf 1b \n"
18 : "=&z" (tmp)
19 : "r" (i), "r" (&v->counter)
20 : "t");
21}
22
23static inline void atomic_sub(int i, atomic_t *v)
24{
25 unsigned long tmp;
26
27 __asm__ __volatile__ (
28"1: movli.l @%2, %0 ! atomic_sub \n"
29" sub %1, %0 \n"
30" movco.l %0, @%2 \n"
31" bf 1b \n"
32 : "=&z" (tmp)
33 : "r" (i), "r" (&v->counter)
34 : "t");
35}
36
37/*
38 * SH-4A note:
39 *
40 * We basically get atomic_xxx_return() for free compared with
41 * atomic_xxx(). movli.l/movco.l require r0 due to the instruction
42 * encoding, so the retval is automatically set without having to
43 * do any special work.
44 */
45static inline int atomic_add_return(int i, atomic_t *v)
46{
47 unsigned long temp;
48
49 __asm__ __volatile__ (
50"1: movli.l @%2, %0 ! atomic_add_return \n"
51" add %1, %0 \n"
52" movco.l %0, @%2 \n"
53" bf 1b \n"
54" synco \n"
55 : "=&z" (temp)
56 : "r" (i), "r" (&v->counter)
57 : "t");
58
59 return temp;
60}
61
62static inline int atomic_sub_return(int i, atomic_t *v)
63{
64 unsigned long temp;
65
66 __asm__ __volatile__ (
67"1: movli.l @%2, %0 ! atomic_sub_return \n"
68" sub %1, %0 \n"
69" movco.l %0, @%2 \n"
70" bf 1b \n"
71" synco \n"
72 : "=&z" (temp)
73 : "r" (i), "r" (&v->counter)
74 : "t");
75
76 return temp;
77}
78
79static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
80{
81 unsigned long tmp;
82
83 __asm__ __volatile__ (
84"1: movli.l @%2, %0 ! atomic_clear_mask \n"
85" and %1, %0 \n"
86" movco.l %0, @%2 \n"
87" bf 1b \n"
88 : "=&z" (tmp)
89 : "r" (~mask), "r" (&v->counter)
90 : "t");
91}
92
93static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
94{
95 unsigned long tmp;
96
97 __asm__ __volatile__ (
98"1: movli.l @%2, %0 ! atomic_set_mask \n"
99" or %1, %0 \n"
100" movco.l %0, @%2 \n"
101" bf 1b \n"
102 : "=&z" (tmp)
103 : "r" (mask), "r" (&v->counter)
104 : "t");
105}
106
107#endif /* __ASM_SH_ATOMIC_LLSC_H */
diff --git a/include/asm-sh/atomic.h b/include/asm-sh/atomic.h
deleted file mode 100644
index c043ef00302..00000000000
--- a/include/asm-sh/atomic.h
+++ /dev/null
@@ -1,89 +0,0 @@
1#ifndef __ASM_SH_ATOMIC_H
2#define __ASM_SH_ATOMIC_H
3
4/*
5 * Atomic operations that C can't guarantee us. Useful for
6 * resource counting etc..
7 *
8 */
9
10typedef struct { volatile int counter; } atomic_t;
11
12#define ATOMIC_INIT(i) ( (atomic_t) { (i) } )
13
14#define atomic_read(v) ((v)->counter)
15#define atomic_set(v,i) ((v)->counter = (i))
16
17#include <linux/compiler.h>
18#include <asm/system.h>
19
20#if defined(CONFIG_GUSA_RB)
21#include <asm/atomic-grb.h>
22#elif defined(CONFIG_CPU_SH4A)
23#include <asm/atomic-llsc.h>
24#else
25#include <asm/atomic-irq.h>
26#endif
27
28#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
29
30#define atomic_dec_return(v) atomic_sub_return(1,(v))
31#define atomic_inc_return(v) atomic_add_return(1,(v))
32
33/*
34 * atomic_inc_and_test - increment and test
35 * @v: pointer of type atomic_t
36 *
37 * Atomically increments @v by 1
38 * and returns true if the result is zero, or false for all
39 * other cases.
40 */
41#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
42
43#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
44#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
45
46#define atomic_inc(v) atomic_add(1,(v))
47#define atomic_dec(v) atomic_sub(1,(v))
48
49#ifndef CONFIG_GUSA_RB
50static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
51{
52 int ret;
53 unsigned long flags;
54
55 local_irq_save(flags);
56 ret = v->counter;
57 if (likely(ret == old))
58 v->counter = new;
59 local_irq_restore(flags);
60
61 return ret;
62}
63
64static inline int atomic_add_unless(atomic_t *v, int a, int u)
65{
66 int ret;
67 unsigned long flags;
68
69 local_irq_save(flags);
70 ret = v->counter;
71 if (ret != u)
72 v->counter += a;
73 local_irq_restore(flags);
74
75 return ret != u;
76}
77#endif
78
79#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
80#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
81
82/* Atomic operations are already serializing on SH */
83#define smp_mb__before_atomic_dec() barrier()
84#define smp_mb__after_atomic_dec() barrier()
85#define smp_mb__before_atomic_inc() barrier()
86#define smp_mb__after_atomic_inc() barrier()
87
88#include <asm-generic/atomic.h>
89#endif /* __ASM_SH_ATOMIC_H */
diff --git a/include/asm-sh/auxvec.h b/include/asm-sh/auxvec.h
deleted file mode 100644
index a6b9d4f4859..00000000000
--- a/include/asm-sh/auxvec.h
+++ /dev/null
@@ -1,36 +0,0 @@
1#ifndef __ASM_SH_AUXVEC_H
2#define __ASM_SH_AUXVEC_H
3
4/*
5 * Architecture-neutral AT_ values in 0-17, leave some room
6 * for more of them.
7 */
8
9/*
10 * This entry gives some information about the FPU initialization
11 * performed by the kernel.
12 */
13#define AT_FPUCW 18 /* Used FPU control word. */
14
15#ifdef CONFIG_VSYSCALL
16/*
17 * Only define this in the vsyscall case, the entry point to
18 * the vsyscall page gets placed here. The kernel will attempt
19 * to build a gate VMA we don't care about otherwise..
20 */
21#define AT_SYSINFO_EHDR 33
22#endif
23
24/*
25 * More complete cache descriptions than AT_[DIU]CACHEBSIZE. If the
26 * value is -1, then the cache doesn't exist. Otherwise:
27 *
28 * bit 0-3: Cache set-associativity; 0 means fully associative.
29 * bit 4-7: Log2 of cacheline size.
30 * bit 8-31: Size of the entire cache >> 8.
31 */
32#define AT_L1I_CACHESHAPE 34
33#define AT_L1D_CACHESHAPE 35
34#define AT_L2_CACHESHAPE 36
35
36#endif /* __ASM_SH_AUXVEC_H */
diff --git a/include/asm-sh/bitops-grb.h b/include/asm-sh/bitops-grb.h
deleted file mode 100644
index a5907b94395..00000000000
--- a/include/asm-sh/bitops-grb.h
+++ /dev/null
@@ -1,169 +0,0 @@
1#ifndef __ASM_SH_BITOPS_GRB_H
2#define __ASM_SH_BITOPS_GRB_H
3
4static inline void set_bit(int nr, volatile void * addr)
5{
6 int mask;
7 volatile unsigned int *a = addr;
8 unsigned long tmp;
9
10 a += nr >> 5;
11 mask = 1 << (nr & 0x1f);
12
13 __asm__ __volatile__ (
14 " .align 2 \n\t"
15 " mova 1f, r0 \n\t" /* r0 = end point */
16 " mov r15, r1 \n\t" /* r1 = saved sp */
17 " mov #-6, r15 \n\t" /* LOGIN: r15 = size */
18 " mov.l @%1, %0 \n\t" /* load old value */
19 " or %2, %0 \n\t" /* or */
20 " mov.l %0, @%1 \n\t" /* store new value */
21 "1: mov r1, r15 \n\t" /* LOGOUT */
22 : "=&r" (tmp),
23 "+r" (a)
24 : "r" (mask)
25 : "memory" , "r0", "r1");
26}
27
28static inline void clear_bit(int nr, volatile void * addr)
29{
30 int mask;
31 volatile unsigned int *a = addr;
32 unsigned long tmp;
33
34 a += nr >> 5;
35 mask = ~(1 << (nr & 0x1f));
36 __asm__ __volatile__ (
37 " .align 2 \n\t"
38 " mova 1f, r0 \n\t" /* r0 = end point */
39 " mov r15, r1 \n\t" /* r1 = saved sp */
40 " mov #-6, r15 \n\t" /* LOGIN: r15 = size */
41 " mov.l @%1, %0 \n\t" /* load old value */
42 " and %2, %0 \n\t" /* and */
43 " mov.l %0, @%1 \n\t" /* store new value */
44 "1: mov r1, r15 \n\t" /* LOGOUT */
45 : "=&r" (tmp),
46 "+r" (a)
47 : "r" (mask)
48 : "memory" , "r0", "r1");
49}
50
51static inline void change_bit(int nr, volatile void * addr)
52{
53 int mask;
54 volatile unsigned int *a = addr;
55 unsigned long tmp;
56
57 a += nr >> 5;
58 mask = 1 << (nr & 0x1f);
59 __asm__ __volatile__ (
60 " .align 2 \n\t"
61 " mova 1f, r0 \n\t" /* r0 = end point */
62 " mov r15, r1 \n\t" /* r1 = saved sp */
63 " mov #-6, r15 \n\t" /* LOGIN: r15 = size */
64 " mov.l @%1, %0 \n\t" /* load old value */
65 " xor %2, %0 \n\t" /* xor */
66 " mov.l %0, @%1 \n\t" /* store new value */
67 "1: mov r1, r15 \n\t" /* LOGOUT */
68 : "=&r" (tmp),
69 "+r" (a)
70 : "r" (mask)
71 : "memory" , "r0", "r1");
72}
73
74static inline int test_and_set_bit(int nr, volatile void * addr)
75{
76 int mask, retval;
77 volatile unsigned int *a = addr;
78 unsigned long tmp;
79
80 a += nr >> 5;
81 mask = 1 << (nr & 0x1f);
82
83 __asm__ __volatile__ (
84 " .align 2 \n\t"
85 " mova 1f, r0 \n\t" /* r0 = end point */
86 " mov r15, r1 \n\t" /* r1 = saved sp */
87 " mov #-14, r15 \n\t" /* LOGIN: r15 = size */
88 " mov.l @%2, %0 \n\t" /* load old value */
89 " mov %0, %1 \n\t"
90 " tst %1, %3 \n\t" /* T = ((*a & mask) == 0) */
91 " mov #-1, %1 \n\t" /* retvat = -1 */
92 " negc %1, %1 \n\t" /* retval = (mask & *a) != 0 */
93 " or %3, %0 \n\t"
94 " mov.l %0, @%2 \n\t" /* store new value */
95 "1: mov r1, r15 \n\t" /* LOGOUT */
96 : "=&r" (tmp),
97 "=&r" (retval),
98 "+r" (a)
99 : "r" (mask)
100 : "memory" , "r0", "r1" ,"t");
101
102 return retval;
103}
104
105static inline int test_and_clear_bit(int nr, volatile void * addr)
106{
107 int mask, retval,not_mask;
108 volatile unsigned int *a = addr;
109 unsigned long tmp;
110
111 a += nr >> 5;
112 mask = 1 << (nr & 0x1f);
113
114 not_mask = ~mask;
115
116 __asm__ __volatile__ (
117 " .align 2 \n\t"
118 " mova 1f, r0 \n\t" /* r0 = end point */
119 " mov r15, r1 \n\t" /* r1 = saved sp */
120 " mov #-14, r15 \n\t" /* LOGIN */
121 " mov.l @%2, %0 \n\t" /* load old value */
122 " mov %0, %1 \n\t" /* %1 = *a */
123 " tst %1, %3 \n\t" /* T = ((*a & mask) == 0) */
124 " mov #-1, %1 \n\t" /* retvat = -1 */
125 " negc %1, %1 \n\t" /* retval = (mask & *a) != 0 */
126 " and %4, %0 \n\t"
127 " mov.l %0, @%2 \n\t" /* store new value */
128 "1: mov r1, r15 \n\t" /* LOGOUT */
129 : "=&r" (tmp),
130 "=&r" (retval),
131 "+r" (a)
132 : "r" (mask),
133 "r" (not_mask)
134 : "memory" , "r0", "r1", "t");
135
136 return retval;
137}
138
139static inline int test_and_change_bit(int nr, volatile void * addr)
140{
141 int mask, retval;
142 volatile unsigned int *a = addr;
143 unsigned long tmp;
144
145 a += nr >> 5;
146 mask = 1 << (nr & 0x1f);
147
148 __asm__ __volatile__ (
149 " .align 2 \n\t"
150 " mova 1f, r0 \n\t" /* r0 = end point */
151 " mov r15, r1 \n\t" /* r1 = saved sp */
152 " mov #-14, r15 \n\t" /* LOGIN */
153 " mov.l @%2, %0 \n\t" /* load old value */
154 " mov %0, %1 \n\t" /* %1 = *a */
155 " tst %1, %3 \n\t" /* T = ((*a & mask) == 0) */
156 " mov #-1, %1 \n\t" /* retvat = -1 */
157 " negc %1, %1 \n\t" /* retval = (mask & *a) != 0 */
158 " xor %3, %0 \n\t"
159 " mov.l %0, @%2 \n\t" /* store new value */
160 "1: mov r1, r15 \n\t" /* LOGOUT */
161 : "=&r" (tmp),
162 "=&r" (retval),
163 "+r" (a)
164 : "r" (mask)
165 : "memory" , "r0", "r1", "t");
166
167 return retval;
168}
169#endif /* __ASM_SH_BITOPS_GRB_H */
diff --git a/include/asm-sh/bitops-irq.h b/include/asm-sh/bitops-irq.h
deleted file mode 100644
index 653a1275058..00000000000
--- a/include/asm-sh/bitops-irq.h
+++ /dev/null
@@ -1,91 +0,0 @@
1#ifndef __ASM_SH_BITOPS_IRQ_H
2#define __ASM_SH_BITOPS_IRQ_H
3
4static inline void set_bit(int nr, volatile void *addr)
5{
6 int mask;
7 volatile unsigned int *a = addr;
8 unsigned long flags;
9
10 a += nr >> 5;
11 mask = 1 << (nr & 0x1f);
12 local_irq_save(flags);
13 *a |= mask;
14 local_irq_restore(flags);
15}
16
17static inline void clear_bit(int nr, volatile void *addr)
18{
19 int mask;
20 volatile unsigned int *a = addr;
21 unsigned long flags;
22
23 a += nr >> 5;
24 mask = 1 << (nr & 0x1f);
25 local_irq_save(flags);
26 *a &= ~mask;
27 local_irq_restore(flags);
28}
29
30static inline void change_bit(int nr, volatile void *addr)
31{
32 int mask;
33 volatile unsigned int *a = addr;
34 unsigned long flags;
35
36 a += nr >> 5;
37 mask = 1 << (nr & 0x1f);
38 local_irq_save(flags);
39 *a ^= mask;
40 local_irq_restore(flags);
41}
42
43static inline int test_and_set_bit(int nr, volatile void *addr)
44{
45 int mask, retval;
46 volatile unsigned int *a = addr;
47 unsigned long flags;
48
49 a += nr >> 5;
50 mask = 1 << (nr & 0x1f);
51 local_irq_save(flags);
52 retval = (mask & *a) != 0;
53 *a |= mask;
54 local_irq_restore(flags);
55
56 return retval;
57}
58
59static inline int test_and_clear_bit(int nr, volatile void *addr)
60{
61 int mask, retval;
62 volatile unsigned int *a = addr;
63 unsigned long flags;
64
65 a += nr >> 5;
66 mask = 1 << (nr & 0x1f);
67 local_irq_save(flags);
68 retval = (mask & *a) != 0;
69 *a &= ~mask;
70 local_irq_restore(flags);
71
72 return retval;
73}
74
75static inline int test_and_change_bit(int nr, volatile void *addr)
76{
77 int mask, retval;
78 volatile unsigned int *a = addr;
79 unsigned long flags;
80
81 a += nr >> 5;
82 mask = 1 << (nr & 0x1f);
83 local_irq_save(flags);
84 retval = (mask & *a) != 0;
85 *a ^= mask;
86 local_irq_restore(flags);
87
88 return retval;
89}
90
91#endif /* __ASM_SH_BITOPS_IRQ_H */
diff --git a/include/asm-sh/bitops.h b/include/asm-sh/bitops.h
deleted file mode 100644
index d7d382f63ee..00000000000
--- a/include/asm-sh/bitops.h
+++ /dev/null
@@ -1,103 +0,0 @@
1#ifndef __ASM_SH_BITOPS_H
2#define __ASM_SH_BITOPS_H
3
4#ifdef __KERNEL__
5
6#ifndef _LINUX_BITOPS_H
7#error only <linux/bitops.h> can be included directly
8#endif
9
10#include <asm/system.h>
11/* For __swab32 */
12#include <asm/byteorder.h>
13
14#ifdef CONFIG_GUSA_RB
15#include <asm/bitops-grb.h>
16#else
17#include <asm/bitops-irq.h>
18#endif
19
20
21/*
22 * clear_bit() doesn't provide any barrier for the compiler.
23 */
24#define smp_mb__before_clear_bit() barrier()
25#define smp_mb__after_clear_bit() barrier()
26
27#include <asm-generic/bitops/non-atomic.h>
28
29#ifdef CONFIG_SUPERH32
30static inline unsigned long ffz(unsigned long word)
31{
32 unsigned long result;
33
34 __asm__("1:\n\t"
35 "shlr %1\n\t"
36 "bt/s 1b\n\t"
37 " add #1, %0"
38 : "=r" (result), "=r" (word)
39 : "0" (~0L), "1" (word)
40 : "t");
41 return result;
42}
43
44/**
45 * __ffs - find first bit in word.
46 * @word: The word to search
47 *
48 * Undefined if no bit exists, so code should check against 0 first.
49 */
50static inline unsigned long __ffs(unsigned long word)
51{
52 unsigned long result;
53
54 __asm__("1:\n\t"
55 "shlr %1\n\t"
56 "bf/s 1b\n\t"
57 " add #1, %0"
58 : "=r" (result), "=r" (word)
59 : "0" (~0L), "1" (word)
60 : "t");
61 return result;
62}
63#else
64static inline unsigned long ffz(unsigned long word)
65{
66 unsigned long result, __d2, __d3;
67
68 __asm__("gettr tr0, %2\n\t"
69 "pta $+32, tr0\n\t"
70 "andi %1, 1, %3\n\t"
71 "beq %3, r63, tr0\n\t"
72 "pta $+4, tr0\n"
73 "0:\n\t"
74 "shlri.l %1, 1, %1\n\t"
75 "addi %0, 1, %0\n\t"
76 "andi %1, 1, %3\n\t"
77 "beqi %3, 1, tr0\n"
78 "1:\n\t"
79 "ptabs %2, tr0\n\t"
80 : "=r" (result), "=r" (word), "=r" (__d2), "=r" (__d3)
81 : "0" (0L), "1" (word));
82
83 return result;
84}
85
86#include <asm-generic/bitops/__ffs.h>
87#endif
88
89#include <asm-generic/bitops/find.h>
90#include <asm-generic/bitops/ffs.h>
91#include <asm-generic/bitops/hweight.h>
92#include <asm-generic/bitops/lock.h>
93#include <asm-generic/bitops/sched.h>
94#include <asm-generic/bitops/ext2-non-atomic.h>
95#include <asm-generic/bitops/ext2-atomic.h>
96#include <asm-generic/bitops/minix.h>
97#include <asm-generic/bitops/fls.h>
98#include <asm-generic/bitops/__fls.h>
99#include <asm-generic/bitops/fls64.h>
100
101#endif /* __KERNEL__ */
102
103#endif /* __ASM_SH_BITOPS_H */
diff --git a/include/asm-sh/bug.h b/include/asm-sh/bug.h
deleted file mode 100644
index c0171804016..00000000000
--- a/include/asm-sh/bug.h
+++ /dev/null
@@ -1,79 +0,0 @@
1#ifndef __ASM_SH_BUG_H
2#define __ASM_SH_BUG_H
3
4#define TRAPA_BUG_OPCODE 0xc33e /* trapa #0x3e */
5
6#ifdef CONFIG_GENERIC_BUG
7#define HAVE_ARCH_BUG
8#define HAVE_ARCH_WARN_ON
9
10/**
11 * _EMIT_BUG_ENTRY
12 * %1 - __FILE__
13 * %2 - __LINE__
14 * %3 - trap type
15 * %4 - sizeof(struct bug_entry)
16 *
17 * The trapa opcode itself sits in %0.
18 * The %O notation is used to avoid # generation.
19 *
20 * The offending file and line are encoded in the __bug_table section.
21 */
22#ifdef CONFIG_DEBUG_BUGVERBOSE
23#define _EMIT_BUG_ENTRY \
24 "\t.pushsection __bug_table,\"a\"\n" \
25 "2:\t.long 1b, %O1\n" \
26 "\t.short %O2, %O3\n" \
27 "\t.org 2b+%O4\n" \
28 "\t.popsection\n"
29#else
30#define _EMIT_BUG_ENTRY \
31 "\t.pushsection __bug_table,\"a\"\n" \
32 "2:\t.long 1b\n" \
33 "\t.short %O3\n" \
34 "\t.org 2b+%O4\n" \
35 "\t.popsection\n"
36#endif
37
38#define BUG() \
39do { \
40 __asm__ __volatile__ ( \
41 "1:\t.short %O0\n" \
42 _EMIT_BUG_ENTRY \
43 : \
44 : "n" (TRAPA_BUG_OPCODE), \
45 "i" (__FILE__), \
46 "i" (__LINE__), "i" (0), \
47 "i" (sizeof(struct bug_entry))); \
48} while (0)
49
50#define __WARN() \
51do { \
52 __asm__ __volatile__ ( \
53 "1:\t.short %O0\n" \
54 _EMIT_BUG_ENTRY \
55 : \
56 : "n" (TRAPA_BUG_OPCODE), \
57 "i" (__FILE__), \
58 "i" (__LINE__), \
59 "i" (BUGFLAG_WARNING), \
60 "i" (sizeof(struct bug_entry))); \
61} while (0)
62
63#define WARN_ON(x) ({ \
64 int __ret_warn_on = !!(x); \
65 if (__builtin_constant_p(__ret_warn_on)) { \
66 if (__ret_warn_on) \
67 __WARN(); \
68 } else { \
69 if (unlikely(__ret_warn_on)) \
70 __WARN(); \
71 } \
72 unlikely(__ret_warn_on); \
73})
74
75#endif /* CONFIG_GENERIC_BUG */
76
77#include <asm-generic/bug.h>
78
79#endif /* __ASM_SH_BUG_H */
diff --git a/include/asm-sh/bugs.h b/include/asm-sh/bugs.h
deleted file mode 100644
index 121b2ecddfc..00000000000
--- a/include/asm-sh/bugs.h
+++ /dev/null
@@ -1,73 +0,0 @@
1#ifndef __ASM_SH_BUGS_H
2#define __ASM_SH_BUGS_H
3
4/*
5 * This is included by init/main.c to check for architecture-dependent bugs.
6 *
7 * Needs:
8 * void check_bugs(void);
9 */
10
11/*
12 * I don't know of any Super-H bugs yet.
13 */
14
15#include <asm/processor.h>
16
17static void __init check_bugs(void)
18{
19 extern unsigned long loops_per_jiffy;
20 char *p = &init_utsname()->machine[2]; /* "sh" */
21
22 current_cpu_data.loops_per_jiffy = loops_per_jiffy;
23
24 switch (current_cpu_data.type) {
25 case CPU_SH7619:
26 *p++ = '2';
27 break;
28 case CPU_SH7203 ... CPU_MXG:
29 *p++ = '2';
30 *p++ = 'a';
31 break;
32 case CPU_SH7705 ... CPU_SH7729:
33 *p++ = '3';
34 break;
35 case CPU_SH7750 ... CPU_SH4_501:
36 *p++ = '4';
37 break;
38 case CPU_SH7763 ... CPU_SHX3:
39 *p++ = '4';
40 *p++ = 'a';
41 break;
42 case CPU_SH7343 ... CPU_SH7366:
43 *p++ = '4';
44 *p++ = 'a';
45 *p++ = 'l';
46 *p++ = '-';
47 *p++ = 'd';
48 *p++ = 's';
49 *p++ = 'p';
50 break;
51 case CPU_SH5_101 ... CPU_SH5_103:
52 *p++ = '6';
53 *p++ = '4';
54 break;
55 case CPU_SH_NONE:
56 /*
57 * Specifically use CPU_SH_NONE rather than default:,
58 * so we're able to have the compiler whine about
59 * unhandled enumerations.
60 */
61 break;
62 }
63
64 printk("CPU: %s\n", get_cpu_subtype(&current_cpu_data));
65
66#ifndef __LITTLE_ENDIAN__
67 /* 'eb' means 'Endian Big' */
68 *p++ = 'e';
69 *p++ = 'b';
70#endif
71 *p = '\0';
72}
73#endif /* __ASM_SH_BUGS_H */
diff --git a/include/asm-sh/byteorder.h b/include/asm-sh/byteorder.h
deleted file mode 100644
index 4c13e611756..00000000000
--- a/include/asm-sh/byteorder.h
+++ /dev/null
@@ -1,70 +0,0 @@
1#ifndef __ASM_SH_BYTEORDER_H
2#define __ASM_SH_BYTEORDER_H
3
4/*
5 * Copyright (C) 1999 Niibe Yutaka
6 * Copyright (C) 2000, 2001 Paolo Alberelli
7 */
8#include <linux/compiler.h>
9#include <linux/types.h>
10
11static inline __attribute_const__ __u32 ___arch__swab32(__u32 x)
12{
13 __asm__(
14#ifdef __SH5__
15 "byterev %0, %0\n\t"
16 "shari %0, 32, %0"
17#else
18 "swap.b %0, %0\n\t"
19 "swap.w %0, %0\n\t"
20 "swap.b %0, %0"
21#endif
22 : "=r" (x)
23 : "0" (x));
24
25 return x;
26}
27
28static inline __attribute_const__ __u16 ___arch__swab16(__u16 x)
29{
30 __asm__(
31#ifdef __SH5__
32 "byterev %0, %0\n\t"
33 "shari %0, 32, %0"
34#else
35 "swap.b %0, %0"
36#endif
37 : "=r" (x)
38 : "0" (x));
39
40 return x;
41}
42
43static inline __u64 ___arch__swab64(__u64 val)
44{
45 union {
46 struct { __u32 a,b; } s;
47 __u64 u;
48 } v, w;
49 v.u = val;
50 w.s.b = ___arch__swab32(v.s.a);
51 w.s.a = ___arch__swab32(v.s.b);
52 return w.u;
53}
54
55#define __arch__swab64(x) ___arch__swab64(x)
56#define __arch__swab32(x) ___arch__swab32(x)
57#define __arch__swab16(x) ___arch__swab16(x)
58
59#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
60# define __BYTEORDER_HAS_U64__
61# define __SWAB_64_THRU_32__
62#endif
63
64#ifdef __LITTLE_ENDIAN__
65#include <linux/byteorder/little_endian.h>
66#else
67#include <linux/byteorder/big_endian.h>
68#endif
69
70#endif /* __ASM_SH_BYTEORDER_H */
diff --git a/include/asm-sh/cache.h b/include/asm-sh/cache.h
deleted file mode 100644
index 083419f47c6..00000000000
--- a/include/asm-sh/cache.h
+++ /dev/null
@@ -1,51 +0,0 @@
1/* $Id: cache.h,v 1.6 2004/03/11 18:08:05 lethal Exp $
2 *
3 * include/asm-sh/cache.h
4 *
5 * Copyright 1999 (C) Niibe Yutaka
6 * Copyright 2002, 2003 (C) Paul Mundt
7 */
8#ifndef __ASM_SH_CACHE_H
9#define __ASM_SH_CACHE_H
10#ifdef __KERNEL__
11
12#include <linux/init.h>
13#include <asm/cpu/cache.h>
14
15#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
16
17#define __read_mostly __attribute__((__section__(".data.read_mostly")))
18
19#ifndef __ASSEMBLY__
20struct cache_info {
21 unsigned int ways; /* Number of cache ways */
22 unsigned int sets; /* Number of cache sets */
23 unsigned int linesz; /* Cache line size (bytes) */
24
25 unsigned int way_size; /* sets * line size */
26
27 /*
28 * way_incr is the address offset for accessing the next way
29 * in memory mapped cache array ops.
30 */
31 unsigned int way_incr;
32 unsigned int entry_shift;
33 unsigned int entry_mask;
34
35 /*
36 * Compute a mask which selects the address bits which overlap between
37 * 1. those used to select the cache set during indexing
38 * 2. those in the physical page number.
39 */
40 unsigned int alias_mask;
41
42 unsigned int n_aliases; /* Number of aliases */
43
44 unsigned long flags;
45};
46
47int __init detect_cpu_and_cache_system(void);
48
49#endif /* __ASSEMBLY__ */
50#endif /* __KERNEL__ */
51#endif /* __ASM_SH_CACHE_H */
diff --git a/include/asm-sh/cacheflush.h b/include/asm-sh/cacheflush.h
deleted file mode 100644
index e034c360411..00000000000
--- a/include/asm-sh/cacheflush.h
+++ /dev/null
@@ -1,81 +0,0 @@
1#ifndef __ASM_SH_CACHEFLUSH_H
2#define __ASM_SH_CACHEFLUSH_H
3
4#ifdef __KERNEL__
5
6#ifdef CONFIG_CACHE_OFF
7/*
8 * Nothing to do when the cache is disabled, initial flush and explicit
9 * disabling is handled at CPU init time.
10 *
11 * See arch/sh/kernel/cpu/init.c:cache_init().
12 */
13#define p3_cache_init() do { } while (0)
14#define flush_cache_all() do { } while (0)
15#define flush_cache_mm(mm) do { } while (0)
16#define flush_cache_dup_mm(mm) do { } while (0)
17#define flush_cache_range(vma, start, end) do { } while (0)
18#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
19#define flush_dcache_page(page) do { } while (0)
20#define flush_icache_range(start, end) do { } while (0)
21#define flush_icache_page(vma,pg) do { } while (0)
22#define flush_dcache_mmap_lock(mapping) do { } while (0)
23#define flush_dcache_mmap_unlock(mapping) do { } while (0)
24#define flush_cache_sigtramp(vaddr) do { } while (0)
25#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
26#define __flush_wback_region(start, size) do { (void)(start); } while (0)
27#define __flush_purge_region(start, size) do { (void)(start); } while (0)
28#define __flush_invalidate_region(start, size) do { (void)(start); } while (0)
29#else
30#include <asm/cpu/cacheflush.h>
31
32/*
33 * Consistent DMA requires that the __flush_xxx() primitives must be set
34 * for any of the enabled non-coherent caches (most of the UP CPUs),
35 * regardless of PIPT or VIPT cache configurations.
36 */
37
38/* Flush (write-back only) a region (smaller than a page) */
39extern void __flush_wback_region(void *start, int size);
40/* Flush (write-back & invalidate) a region (smaller than a page) */
41extern void __flush_purge_region(void *start, int size);
42/* Flush (invalidate only) a region (smaller than a page) */
43extern void __flush_invalidate_region(void *start, int size);
44#endif
45
46#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
47static inline void flush_kernel_dcache_page(struct page *page)
48{
49 flush_dcache_page(page);
50}
51
52#if defined(CONFIG_CPU_SH4) && !defined(CONFIG_CACHE_OFF)
53extern void copy_to_user_page(struct vm_area_struct *vma,
54 struct page *page, unsigned long vaddr, void *dst, const void *src,
55 unsigned long len);
56
57extern void copy_from_user_page(struct vm_area_struct *vma,
58 struct page *page, unsigned long vaddr, void *dst, const void *src,
59 unsigned long len);
60#else
61#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
62 do { \
63 flush_cache_page(vma, vaddr, page_to_pfn(page));\
64 memcpy(dst, src, len); \
65 flush_icache_user_range(vma, page, vaddr, len); \
66 } while (0)
67
68#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
69 do { \
70 flush_cache_page(vma, vaddr, page_to_pfn(page));\
71 memcpy(dst, src, len); \
72 } while (0)
73#endif
74
75#define flush_cache_vmap(start, end) flush_cache_all()
76#define flush_cache_vunmap(start, end) flush_cache_all()
77
78#define HAVE_ARCH_UNMAPPED_AREA
79
80#endif /* __KERNEL__ */
81#endif /* __ASM_SH_CACHEFLUSH_H */
diff --git a/include/asm-sh/checksum.h b/include/asm-sh/checksum.h
deleted file mode 100644
index 67496ab0ef0..00000000000
--- a/include/asm-sh/checksum.h
+++ /dev/null
@@ -1,5 +0,0 @@
1#ifdef CONFIG_SUPERH32
2# include "checksum_32.h"
3#else
4# include "checksum_64.h"
5#endif
diff --git a/include/asm-sh/checksum_32.h b/include/asm-sh/checksum_32.h
deleted file mode 100644
index 14b7ac2f0a0..00000000000
--- a/include/asm-sh/checksum_32.h
+++ /dev/null
@@ -1,215 +0,0 @@
1#ifndef __ASM_SH_CHECKSUM_H
2#define __ASM_SH_CHECKSUM_H
3
4/*
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 *
9 * Copyright (C) 1999 by Kaz Kojima & Niibe Yutaka
10 */
11
12#include <linux/in6.h>
13
14/*
15 * computes the checksum of a memory block at buff, length len,
16 * and adds in "sum" (32-bit)
17 *
18 * returns a 32-bit number suitable for feeding into itself
19 * or csum_tcpudp_magic
20 *
21 * this function must be called with even lengths, except
22 * for the last fragment, which may be odd
23 *
24 * it's best to have buff aligned on a 32-bit boundary
25 */
26asmlinkage __wsum csum_partial(const void *buff, int len, __wsum sum);
27
28/*
29 * the same as csum_partial, but copies from src while it
30 * checksums, and handles user-space pointer exceptions correctly, when needed.
31 *
32 * here even more important to align src and dst on a 32-bit (or even
33 * better 64-bit) boundary
34 */
35
36asmlinkage __wsum csum_partial_copy_generic(const void *src, void *dst,
37 int len, __wsum sum,
38 int *src_err_ptr, int *dst_err_ptr);
39
40/*
41 * Note: when you get a NULL pointer exception here this means someone
42 * passed in an incorrect kernel address to one of these functions.
43 *
44 * If you use these functions directly please don't forget the
45 * access_ok().
46 */
47static inline
48__wsum csum_partial_copy_nocheck(const void *src, void *dst,
49 int len, __wsum sum)
50{
51 return csum_partial_copy_generic(src, dst, len, sum, NULL, NULL);
52}
53
54static inline
55__wsum csum_partial_copy_from_user(const void __user *src, void *dst,
56 int len, __wsum sum, int *err_ptr)
57{
58 return csum_partial_copy_generic((__force const void *)src, dst,
59 len, sum, err_ptr, NULL);
60}
61
62/*
63 * Fold a partial checksum
64 */
65
66static inline __sum16 csum_fold(__wsum sum)
67{
68 unsigned int __dummy;
69 __asm__("swap.w %0, %1\n\t"
70 "extu.w %0, %0\n\t"
71 "extu.w %1, %1\n\t"
72 "add %1, %0\n\t"
73 "swap.w %0, %1\n\t"
74 "add %1, %0\n\t"
75 "not %0, %0\n\t"
76 : "=r" (sum), "=&r" (__dummy)
77 : "0" (sum)
78 : "t");
79 return (__force __sum16)sum;
80}
81
82/*
83 * This is a version of ip_compute_csum() optimized for IP headers,
84 * which always checksum on 4 octet boundaries.
85 *
86 * i386 version by Jorge Cwik <jorge@laser.satlink.net>, adapted
87 * for linux by * Arnt Gulbrandsen.
88 */
89static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
90{
91 unsigned int sum, __dummy0, __dummy1;
92
93 __asm__ __volatile__(
94 "mov.l @%1+, %0\n\t"
95 "mov.l @%1+, %3\n\t"
96 "add #-2, %2\n\t"
97 "clrt\n\t"
98 "1:\t"
99 "addc %3, %0\n\t"
100 "movt %4\n\t"
101 "mov.l @%1+, %3\n\t"
102 "dt %2\n\t"
103 "bf/s 1b\n\t"
104 " cmp/eq #1, %4\n\t"
105 "addc %3, %0\n\t"
106 "addc %2, %0" /* Here %2 is 0, add carry-bit */
107 /* Since the input registers which are loaded with iph and ihl
108 are modified, we must also specify them as outputs, or gcc
109 will assume they contain their original values. */
110 : "=r" (sum), "=r" (iph), "=r" (ihl), "=&r" (__dummy0), "=&z" (__dummy1)
111 : "1" (iph), "2" (ihl)
112 : "t", "memory");
113
114 return csum_fold(sum);
115}
116
117static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
118 unsigned short len,
119 unsigned short proto,
120 __wsum sum)
121{
122#ifdef __LITTLE_ENDIAN__
123 unsigned long len_proto = (proto + len) << 8;
124#else
125 unsigned long len_proto = proto + len;
126#endif
127 __asm__("clrt\n\t"
128 "addc %0, %1\n\t"
129 "addc %2, %1\n\t"
130 "addc %3, %1\n\t"
131 "movt %0\n\t"
132 "add %1, %0"
133 : "=r" (sum), "=r" (len_proto)
134 : "r" (daddr), "r" (saddr), "1" (len_proto), "0" (sum)
135 : "t");
136
137 return sum;
138}
139
140/*
141 * computes the checksum of the TCP/UDP pseudo-header
142 * returns a 16-bit checksum, already complemented
143 */
144static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
145 unsigned short len,
146 unsigned short proto,
147 __wsum sum)
148{
149 return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum));
150}
151
152/*
153 * this routine is used for miscellaneous IP-like checksums, mainly
154 * in icmp.c
155 */
156static inline __sum16 ip_compute_csum(const void *buff, int len)
157{
158 return csum_fold(csum_partial(buff, len, 0));
159}
160
161#define _HAVE_ARCH_IPV6_CSUM
162static inline __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
163 const struct in6_addr *daddr,
164 __u32 len, unsigned short proto,
165 __wsum sum)
166{
167 unsigned int __dummy;
168 __asm__("clrt\n\t"
169 "mov.l @(0,%2), %1\n\t"
170 "addc %1, %0\n\t"
171 "mov.l @(4,%2), %1\n\t"
172 "addc %1, %0\n\t"
173 "mov.l @(8,%2), %1\n\t"
174 "addc %1, %0\n\t"
175 "mov.l @(12,%2), %1\n\t"
176 "addc %1, %0\n\t"
177 "mov.l @(0,%3), %1\n\t"
178 "addc %1, %0\n\t"
179 "mov.l @(4,%3), %1\n\t"
180 "addc %1, %0\n\t"
181 "mov.l @(8,%3), %1\n\t"
182 "addc %1, %0\n\t"
183 "mov.l @(12,%3), %1\n\t"
184 "addc %1, %0\n\t"
185 "addc %4, %0\n\t"
186 "addc %5, %0\n\t"
187 "movt %1\n\t"
188 "add %1, %0\n"
189 : "=r" (sum), "=&r" (__dummy)
190 : "r" (saddr), "r" (daddr),
191 "r" (htonl(len)), "r" (htonl(proto)), "0" (sum)
192 : "t");
193
194 return csum_fold(sum);
195}
196
197/*
198 * Copy and checksum to user
199 */
200#define HAVE_CSUM_COPY_USER
201static inline __wsum csum_and_copy_to_user(const void *src,
202 void __user *dst,
203 int len, __wsum sum,
204 int *err_ptr)
205{
206 if (access_ok(VERIFY_WRITE, dst, len))
207 return csum_partial_copy_generic((__force const void *)src,
208 dst, len, sum, NULL, err_ptr);
209
210 if (len)
211 *err_ptr = -EFAULT;
212
213 return (__force __wsum)-1; /* invalid checksum */
214}
215#endif /* __ASM_SH_CHECKSUM_H */
diff --git a/include/asm-sh/checksum_64.h b/include/asm-sh/checksum_64.h
deleted file mode 100644
index 9c62a031a8f..00000000000
--- a/include/asm-sh/checksum_64.h
+++ /dev/null
@@ -1,78 +0,0 @@
1#ifndef __ASM_SH_CHECKSUM_64_H
2#define __ASM_SH_CHECKSUM_64_H
3
4/*
5 * include/asm-sh/checksum_64.h
6 *
7 * Copyright (C) 2000, 2001 Paolo Alberelli
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13
14/*
15 * computes the checksum of a memory block at buff, length len,
16 * and adds in "sum" (32-bit)
17 *
18 * returns a 32-bit number suitable for feeding into itself
19 * or csum_tcpudp_magic
20 *
21 * this function must be called with even lengths, except
22 * for the last fragment, which may be odd
23 *
24 * it's best to have buff aligned on a 32-bit boundary
25 */
26asmlinkage __wsum csum_partial(const void *buff, int len, __wsum sum);
27
28/*
29 * Note: when you get a NULL pointer exception here this means someone
30 * passed in an incorrect kernel address to one of these functions.
31 *
32 * If you use these functions directly please don't forget the
33 * access_ok().
34 */
35
36
37__wsum csum_partial_copy_nocheck(const void *src, void *dst, int len,
38 __wsum sum);
39
40__wsum csum_partial_copy_from_user(const void __user *src, void *dst,
41 int len, __wsum sum, int *err_ptr);
42
43static inline __sum16 csum_fold(__wsum csum)
44{
45 u32 sum = (__force u32)csum;
46 sum = (sum & 0xffff) + (sum >> 16);
47 sum = (sum & 0xffff) + (sum >> 16);
48 return (__force __sum16)~sum;
49}
50
51__sum16 ip_fast_csum(const void *iph, unsigned int ihl);
52
53__wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
54 unsigned short len, unsigned short proto,
55 __wsum sum);
56
57/*
58 * computes the checksum of the TCP/UDP pseudo-header
59 * returns a 16-bit checksum, already complemented
60 */
61static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
62 unsigned short len,
63 unsigned short proto,
64 __wsum sum)
65{
66 return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
67}
68
69/*
70 * this routine is used for miscellaneous IP-like checksums, mainly
71 * in icmp.c
72 */
73static inline __sum16 ip_compute_csum(const void *buff, int len)
74{
75 return csum_fold(csum_partial(buff, len, 0));
76}
77
78#endif /* __ASM_SH_CHECKSUM_64_H */
diff --git a/include/asm-sh/clock.h b/include/asm-sh/clock.h
deleted file mode 100644
index b550a27a704..00000000000
--- a/include/asm-sh/clock.h
+++ /dev/null
@@ -1,82 +0,0 @@
1#ifndef __ASM_SH_CLOCK_H
2#define __ASM_SH_CLOCK_H
3
4#include <linux/kref.h>
5#include <linux/list.h>
6#include <linux/seq_file.h>
7#include <linux/clk.h>
8
9struct clk;
10
11struct clk_ops {
12 void (*init)(struct clk *clk);
13 void (*enable)(struct clk *clk);
14 void (*disable)(struct clk *clk);
15 void (*recalc)(struct clk *clk);
16 int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id);
17 long (*round_rate)(struct clk *clk, unsigned long rate);
18};
19
20struct clk {
21 struct list_head node;
22 const char *name;
23 int id;
24 struct module *owner;
25
26 struct clk *parent;
27 struct clk_ops *ops;
28
29 struct kref kref;
30
31 unsigned long rate;
32 unsigned long flags;
33};
34
35#define CLK_ALWAYS_ENABLED (1 << 0)
36#define CLK_RATE_PROPAGATES (1 << 1)
37
38/* Should be defined by processor-specific code */
39void arch_init_clk_ops(struct clk_ops **, int type);
40
41/* arch/sh/kernel/cpu/clock.c */
42int clk_init(void);
43
44int __clk_enable(struct clk *);
45void __clk_disable(struct clk *);
46
47void clk_recalc_rate(struct clk *);
48
49int clk_register(struct clk *);
50void clk_unregister(struct clk *);
51
52/* the exported API, in addition to clk_set_rate */
53/**
54 * clk_set_rate_ex - set the clock rate for a clock source, with additional parameter
55 * @clk: clock source
56 * @rate: desired clock rate in Hz
57 * @algo_id: algorithm id to be passed down to ops->set_rate
58 *
59 * Returns success (0) or negative errno.
60 */
61int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id);
62
63enum clk_sh_algo_id {
64 NO_CHANGE = 0,
65
66 IUS_N1_N1,
67 IUS_322,
68 IUS_522,
69 IUS_N11,
70
71 SB_N1,
72
73 SB3_N1,
74 SB3_32,
75 SB3_43,
76 SB3_54,
77
78 BP_N1,
79
80 IP_N1,
81};
82#endif /* __ASM_SH_CLOCK_H */
diff --git a/include/asm-sh/cmpxchg-grb.h b/include/asm-sh/cmpxchg-grb.h
deleted file mode 100644
index e2681abe764..00000000000
--- a/include/asm-sh/cmpxchg-grb.h
+++ /dev/null
@@ -1,70 +0,0 @@
1#ifndef __ASM_SH_CMPXCHG_GRB_H
2#define __ASM_SH_CMPXCHG_GRB_H
3
4static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
5{
6 unsigned long retval;
7
8 __asm__ __volatile__ (
9 " .align 2 \n\t"
10 " mova 1f, r0 \n\t" /* r0 = end point */
11 " nop \n\t"
12 " mov r15, r1 \n\t" /* r1 = saved sp */
13 " mov #-4, r15 \n\t" /* LOGIN */
14 " mov.l @%1, %0 \n\t" /* load old value */
15 " mov.l %2, @%1 \n\t" /* store new value */
16 "1: mov r1, r15 \n\t" /* LOGOUT */
17 : "=&r" (retval),
18 "+r" (m)
19 : "r" (val)
20 : "memory", "r0", "r1");
21
22 return retval;
23}
24
25static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val)
26{
27 unsigned long retval;
28
29 __asm__ __volatile__ (
30 " .align 2 \n\t"
31 " mova 1f, r0 \n\t" /* r0 = end point */
32 " mov r15, r1 \n\t" /* r1 = saved sp */
33 " mov #-6, r15 \n\t" /* LOGIN */
34 " mov.b @%1, %0 \n\t" /* load old value */
35 " extu.b %0, %0 \n\t" /* extend as unsigned */
36 " mov.b %2, @%1 \n\t" /* store new value */
37 "1: mov r1, r15 \n\t" /* LOGOUT */
38 : "=&r" (retval),
39 "+r" (m)
40 : "r" (val)
41 : "memory" , "r0", "r1");
42
43 return retval;
44}
45
46static inline unsigned long __cmpxchg_u32(volatile int *m, unsigned long old,
47 unsigned long new)
48{
49 unsigned long retval;
50
51 __asm__ __volatile__ (
52 " .align 2 \n\t"
53 " mova 1f, r0 \n\t" /* r0 = end point */
54 " nop \n\t"
55 " mov r15, r1 \n\t" /* r1 = saved sp */
56 " mov #-8, r15 \n\t" /* LOGIN */
57 " mov.l @%1, %0 \n\t" /* load old value */
58 " cmp/eq %0, %2 \n\t"
59 " bf 1f \n\t" /* if not equal */
60 " mov.l %2, @%1 \n\t" /* store new value */
61 "1: mov r1, r15 \n\t" /* LOGOUT */
62 : "=&r" (retval),
63 "+r" (m)
64 : "r" (new)
65 : "memory" , "r0", "r1", "t");
66
67 return retval;
68}
69
70#endif /* __ASM_SH_CMPXCHG_GRB_H */
diff --git a/include/asm-sh/cmpxchg-irq.h b/include/asm-sh/cmpxchg-irq.h
deleted file mode 100644
index 43049ec0554..00000000000
--- a/include/asm-sh/cmpxchg-irq.h
+++ /dev/null
@@ -1,40 +0,0 @@
1#ifndef __ASM_SH_CMPXCHG_IRQ_H
2#define __ASM_SH_CMPXCHG_IRQ_H
3
4static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
5{
6 unsigned long flags, retval;
7
8 local_irq_save(flags);
9 retval = *m;
10 *m = val;
11 local_irq_restore(flags);
12 return retval;
13}
14
15static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val)
16{
17 unsigned long flags, retval;
18
19 local_irq_save(flags);
20 retval = *m;
21 *m = val & 0xff;
22 local_irq_restore(flags);
23 return retval;
24}
25
26static inline unsigned long __cmpxchg_u32(volatile int *m, unsigned long old,
27 unsigned long new)
28{
29 __u32 retval;
30 unsigned long flags;
31
32 local_irq_save(flags);
33 retval = *m;
34 if (retval == old)
35 *m = new;
36 local_irq_restore(flags); /* implies memory barrier */
37 return retval;
38}
39
40#endif /* __ASM_SH_CMPXCHG_IRQ_H */
diff --git a/include/asm-sh/cpu-features.h b/include/asm-sh/cpu-features.h
deleted file mode 100644
index 86308aa3973..00000000000
--- a/include/asm-sh/cpu-features.h
+++ /dev/null
@@ -1,25 +0,0 @@
1#ifndef __ASM_SH_CPU_FEATURES_H
2#define __ASM_SH_CPU_FEATURES_H
3
4/*
5 * Processor flags
6 *
7 * Note: When adding a new flag, keep cpu_flags[] in
8 * arch/sh/kernel/setup.c in sync so symbolic name
9 * mapping of the processor flags has a chance of being
10 * reasonably accurate.
11 *
12 * These flags are also available through the ELF
13 * auxiliary vector as AT_HWCAP.
14 */
15#define CPU_HAS_FPU 0x0001 /* Hardware FPU support */
16#define CPU_HAS_P2_FLUSH_BUG 0x0002 /* Need to flush the cache in P2 area */
17#define CPU_HAS_MMU_PAGE_ASSOC 0x0004 /* SH3: TLB way selection bit support */
18#define CPU_HAS_DSP 0x0008 /* SH-DSP: DSP support */
19#define CPU_HAS_PERF_COUNTER 0x0010 /* Hardware performance counters */
20#define CPU_HAS_PTEA 0x0020 /* PTEA register */
21#define CPU_HAS_LLSC 0x0040 /* movli.l/movco.l */
22#define CPU_HAS_L2_CACHE 0x0080 /* Secondary cache / URAM */
23#define CPU_HAS_OP32 0x0100 /* 32-bit instruction support */
24
25#endif /* __ASM_SH_CPU_FEATURES_H */
diff --git a/include/asm-sh/cpu-sh2/addrspace.h b/include/asm-sh/cpu-sh2/addrspace.h
deleted file mode 100644
index 2b9ab93efa4..00000000000
--- a/include/asm-sh/cpu-sh2/addrspace.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * Definitions for the address spaces of the SH-2 CPUs.
3 *
4 * Copyright (C) 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH2_ADDRSPACE_H
11#define __ASM_CPU_SH2_ADDRSPACE_H
12
13#define P0SEG 0x00000000
14#define P1SEG 0x80000000
15#define P2SEG 0xa0000000
16#define P3SEG 0xc0000000
17#define P4SEG 0xe0000000
18
19#endif /* __ASM_CPU_SH2_ADDRSPACE_H */
diff --git a/include/asm-sh/cpu-sh2/cache.h b/include/asm-sh/cpu-sh2/cache.h
deleted file mode 100644
index 4e0b1650068..00000000000
--- a/include/asm-sh/cpu-sh2/cache.h
+++ /dev/null
@@ -1,41 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh2/cache.h
3 *
4 * Copyright (C) 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH2_CACHE_H
11#define __ASM_CPU_SH2_CACHE_H
12
13#define L1_CACHE_SHIFT 4
14
15#define SH_CACHE_VALID 1
16#define SH_CACHE_UPDATED 2
17#define SH_CACHE_COMBINED 4
18#define SH_CACHE_ASSOC 8
19
20#if defined(CONFIG_CPU_SUBTYPE_SH7619)
21#define CCR 0xffffffec
22
23#define CCR_CACHE_CE 0x01 /* Cache enable */
24#define CCR_CACHE_WT 0x06 /* CCR[bit1=1,bit2=1] */
25 /* 0x00000000-0x7fffffff: Write-through */
26 /* 0x80000000-0x9fffffff: Write-back */
27 /* 0xc0000000-0xdfffffff: Write-through */
28#define CCR_CACHE_CB 0x00 /* CCR[bit1=0,bit2=0] */
29 /* 0x00000000-0x7fffffff: Write-back */
30 /* 0x80000000-0x9fffffff: Write-through */
31 /* 0xc0000000-0xdfffffff: Write-back */
32#define CCR_CACHE_CF 0x08 /* Cache invalidate */
33
34#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
35#define CACHE_OC_DATA_ARRAY 0xf1000000
36
37#define CCR_CACHE_ENABLE CCR_CACHE_CE
38#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
39#endif
40
41#endif /* __ASM_CPU_SH2_CACHE_H */
diff --git a/include/asm-sh/cpu-sh2/cacheflush.h b/include/asm-sh/cpu-sh2/cacheflush.h
deleted file mode 100644
index 2979efb26de..00000000000
--- a/include/asm-sh/cpu-sh2/cacheflush.h
+++ /dev/null
@@ -1,44 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh2/cacheflush.h
3 *
4 * Copyright (C) 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH2_CACHEFLUSH_H
11#define __ASM_CPU_SH2_CACHEFLUSH_H
12
13/*
14 * Cache flushing:
15 *
16 * - flush_cache_all() flushes entire cache
17 * - flush_cache_mm(mm) flushes the specified mm context's cache lines
18 * - flush_cache_dup mm(mm) handles cache flushing when forking
19 * - flush_cache_page(mm, vmaddr, pfn) flushes a single page
20 * - flush_cache_range(vma, start, end) flushes a range of pages
21 *
22 * - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
23 * - flush_icache_range(start, end) flushes(invalidates) a range for icache
24 * - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
25 *
26 * Caches are indexed (effectively) by physical address on SH-2, so
27 * we don't need them.
28 */
29#define flush_cache_all() do { } while (0)
30#define flush_cache_mm(mm) do { } while (0)
31#define flush_cache_dup_mm(mm) do { } while (0)
32#define flush_cache_range(vma, start, end) do { } while (0)
33#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
34#define flush_dcache_page(page) do { } while (0)
35#define flush_dcache_mmap_lock(mapping) do { } while (0)
36#define flush_dcache_mmap_unlock(mapping) do { } while (0)
37#define flush_icache_range(start, end) do { } while (0)
38#define flush_icache_page(vma,pg) do { } while (0)
39#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
40#define flush_cache_sigtramp(vaddr) do { } while (0)
41
42#define p3_cache_init() do { } while (0)
43#endif /* __ASM_CPU_SH2_CACHEFLUSH_H */
44
diff --git a/include/asm-sh/cpu-sh2/dma.h b/include/asm-sh/cpu-sh2/dma.h
deleted file mode 100644
index d66b43cdc63..00000000000
--- a/include/asm-sh/cpu-sh2/dma.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * Definitions for the SH-2 DMAC.
3 *
4 * Copyright (C) 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH2_DMA_H
11#define __ASM_CPU_SH2_DMA_H
12
13#define SH_MAX_DMA_CHANNELS 2
14
15#define SAR ((unsigned long[]){ 0xffffff80, 0xffffff90 })
16#define DAR ((unsigned long[]){ 0xffffff84, 0xffffff94 })
17#define DMATCR ((unsigned long[]){ 0xffffff88, 0xffffff98 })
18#define CHCR ((unsigned long[]){ 0xfffffffc, 0xffffff9c })
19
20#define DMAOR 0xffffffb0
21
22#endif /* __ASM_CPU_SH2_DMA_H */
23
diff --git a/include/asm-sh/cpu-sh2/freq.h b/include/asm-sh/cpu-sh2/freq.h
deleted file mode 100644
index 31de475da70..00000000000
--- a/include/asm-sh/cpu-sh2/freq.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh2/freq.h
3 *
4 * Copyright (C) 2006 Yoshinori Sato
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH2_FREQ_H
11#define __ASM_CPU_SH2_FREQ_H
12
13#if defined(CONFIG_CPU_SUBTYPE_SH7619)
14#define FREQCR 0xf815ff80
15#endif
16
17#endif /* __ASM_CPU_SH2_FREQ_H */
18
diff --git a/include/asm-sh/cpu-sh2/mmu_context.h b/include/asm-sh/cpu-sh2/mmu_context.h
deleted file mode 100644
index beeb299e01e..00000000000
--- a/include/asm-sh/cpu-sh2/mmu_context.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh2/mmu_context.h
3 *
4 * Copyright (C) 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH2_MMU_CONTEXT_H
11#define __ASM_CPU_SH2_MMU_CONTEXT_H
12
13/* No MMU */
14
15#endif /* __ASM_CPU_SH2_MMU_CONTEXT_H */
16
diff --git a/include/asm-sh/cpu-sh2/rtc.h b/include/asm-sh/cpu-sh2/rtc.h
deleted file mode 100644
index 39e2d6e9478..00000000000
--- a/include/asm-sh/cpu-sh2/rtc.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef __ASM_SH_CPU_SH2_RTC_H
2#define __ASM_SH_CPU_SH2_RTC_H
3
4#define rtc_reg_size sizeof(u16)
5#define RTC_BIT_INVERTED 0
6#define RTC_DEF_CAPABILITIES 0UL
7
8#endif /* __ASM_SH_CPU_SH2_RTC_H */
diff --git a/include/asm-sh/cpu-sh2/sigcontext.h b/include/asm-sh/cpu-sh2/sigcontext.h
deleted file mode 100644
index fe5c15dd6e8..00000000000
--- a/include/asm-sh/cpu-sh2/sigcontext.h
+++ /dev/null
@@ -1,17 +0,0 @@
1#ifndef __ASM_CPU_SH2_SIGCONTEXT_H
2#define __ASM_CPU_SH2_SIGCONTEXT_H
3
4struct sigcontext {
5 unsigned long oldmask;
6
7 /* CPU registers */
8 unsigned long sc_regs[16];
9 unsigned long sc_pc;
10 unsigned long sc_pr;
11 unsigned long sc_sr;
12 unsigned long sc_gbr;
13 unsigned long sc_mach;
14 unsigned long sc_macl;
15};
16
17#endif /* __ASM_CPU_SH2_SIGCONTEXT_H */
diff --git a/include/asm-sh/cpu-sh2/timer.h b/include/asm-sh/cpu-sh2/timer.h
deleted file mode 100644
index a39c241e819..00000000000
--- a/include/asm-sh/cpu-sh2/timer.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef __ASM_CPU_SH2_TIMER_H
2#define __ASM_CPU_SH2_TIMER_H
3
4/* Nothing needed yet */
5
6#endif /* __ASM_CPU_SH2_TIMER_H */
diff --git a/include/asm-sh/cpu-sh2/ubc.h b/include/asm-sh/cpu-sh2/ubc.h
deleted file mode 100644
index ba0e87f19c7..00000000000
--- a/include/asm-sh/cpu-sh2/ubc.h
+++ /dev/null
@@ -1,32 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh2/ubc.h
3 *
4 * Copyright (C) 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH2_UBC_H
11#define __ASM_CPU_SH2_UBC_H
12
13#define UBC_BARA 0xffffff40
14#define UBC_BAMRA 0xffffff44
15#define UBC_BBRA 0xffffff48
16#define UBC_BARB 0xffffff60
17#define UBC_BAMRB 0xffffff64
18#define UBC_BBRB 0xffffff68
19#define UBC_BDRB 0xffffff70
20#define UBC_BDMRB 0xffffff74
21#define UBC_BRCR 0xffffff78
22
23/*
24 * We don't have any ASID changes to make in the UBC on the SH-2.
25 *
26 * Make these purposely invalid to track misuse.
27 */
28#define UBC_BASRA 0x00000000
29#define UBC_BASRB 0x00000000
30
31#endif /* __ASM_CPU_SH2_UBC_H */
32
diff --git a/include/asm-sh/cpu-sh2/watchdog.h b/include/asm-sh/cpu-sh2/watchdog.h
deleted file mode 100644
index 393161c9c6d..00000000000
--- a/include/asm-sh/cpu-sh2/watchdog.h
+++ /dev/null
@@ -1,69 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh2/watchdog.h
3 *
4 * Copyright (C) 2002, 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH2_WATCHDOG_H
11#define __ASM_CPU_SH2_WATCHDOG_H
12
13/*
14 * More SH-2 brilliance .. its not good enough that we can't read
15 * and write the same sizes to WTCNT, now we have to read and write
16 * with different sizes at different addresses for WTCNT _and_ RSTCSR.
17 *
18 * At least on the bright side no one has managed to screw over WTCSR
19 * in this fashion .. yet.
20 */
21/* Register definitions */
22#define WTCNT 0xfffffe80
23#define WTCSR 0xfffffe80
24#define RSTCSR 0xfffffe82
25
26#define WTCNT_R (WTCNT + 1)
27#define RSTCSR_R (RSTCSR + 1)
28
29/* Bit definitions */
30#define WTCSR_IOVF 0x80
31#define WTCSR_WT 0x40
32#define WTCSR_TME 0x20
33#define WTCSR_RSTS 0x00
34
35#define RSTCSR_RSTS 0x20
36
37/**
38 * sh_wdt_read_rstcsr - Read from Reset Control/Status Register
39 *
40 * Reads back the RSTCSR value.
41 */
42static inline __u8 sh_wdt_read_rstcsr(void)
43{
44 /*
45 * Same read/write brain-damage as for WTCNT here..
46 */
47 return ctrl_inb(RSTCSR_R);
48}
49
50/**
51 * sh_wdt_write_csr - Write to Reset Control/Status Register
52 *
53 * @val: Value to write
54 *
55 * Writes the given value @val to the lower byte of the control/status
56 * register. The upper byte is set manually on each write.
57 */
58static inline void sh_wdt_write_rstcsr(__u8 val)
59{
60 /*
61 * Note: Due to the brain-damaged nature of this register,
62 * we can't presently touch the WOVF bit, since the upper byte
63 * has to be swapped for this. So just leave it alone..
64 */
65 ctrl_outw((WTCNT_HIGH << 8) | (__u16)val, RSTCSR);
66}
67
68#endif /* __ASM_CPU_SH2_WATCHDOG_H */
69
diff --git a/include/asm-sh/cpu-sh2a/addrspace.h b/include/asm-sh/cpu-sh2a/addrspace.h
deleted file mode 100644
index 795ddd6856a..00000000000
--- a/include/asm-sh/cpu-sh2a/addrspace.h
+++ /dev/null
@@ -1,10 +0,0 @@
1#ifndef __ASM_SH_CPU_SH2A_ADDRSPACE_H
2#define __ASM_SH_CPU_SH2A_ADDRSPACE_H
3
4#define P0SEG 0x00000000
5#define P1SEG 0x00000000
6#define P2SEG 0x20000000
7#define P3SEG 0x00000000
8#define P4SEG 0x80000000
9
10#endif /* __ASM_SH_CPU_SH2A_ADDRSPACE_H */
diff --git a/include/asm-sh/cpu-sh2a/cache.h b/include/asm-sh/cpu-sh2a/cache.h
deleted file mode 100644
index afe228b3f49..00000000000
--- a/include/asm-sh/cpu-sh2a/cache.h
+++ /dev/null
@@ -1,40 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh2a/cache.h
3 *
4 * Copyright (C) 2004 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH2A_CACHE_H
11#define __ASM_CPU_SH2A_CACHE_H
12
13#define L1_CACHE_SHIFT 4
14
15#define SH_CACHE_VALID 1
16#define SH_CACHE_UPDATED 2
17#define SH_CACHE_COMBINED 4
18#define SH_CACHE_ASSOC 8
19
20#define CCR 0xfffc1000 /* CCR1 */
21#define CCR2 0xfffc1004
22
23/*
24 * Most of the SH-2A CCR1 definitions resemble the SH-4 ones. All others not
25 * listed here are reserved.
26 */
27#define CCR_CACHE_CB 0x0000 /* Hack */
28#define CCR_CACHE_OCE 0x0001
29#define CCR_CACHE_WT 0x0002
30#define CCR_CACHE_OCI 0x0008 /* OCF */
31#define CCR_CACHE_ICE 0x0100
32#define CCR_CACHE_ICI 0x0800 /* ICF */
33
34#define CACHE_IC_ADDRESS_ARRAY 0xf0000000
35#define CACHE_OC_ADDRESS_ARRAY 0xf0800000
36
37#define CCR_CACHE_ENABLE (CCR_CACHE_OCE | CCR_CACHE_ICE)
38#define CCR_CACHE_INVALIDATE (CCR_CACHE_OCI | CCR_CACHE_ICI)
39
40#endif /* __ASM_CPU_SH2A_CACHE_H */
diff --git a/include/asm-sh/cpu-sh2a/cacheflush.h b/include/asm-sh/cpu-sh2a/cacheflush.h
deleted file mode 100644
index fa3186c7335..00000000000
--- a/include/asm-sh/cpu-sh2a/cacheflush.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm/cpu-sh2/cacheflush.h>
diff --git a/include/asm-sh/cpu-sh2a/dma.h b/include/asm-sh/cpu-sh2a/dma.h
deleted file mode 100644
index 0d5ad85c1de..00000000000
--- a/include/asm-sh/cpu-sh2a/dma.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm/cpu-sh2/dma.h>
diff --git a/include/asm-sh/cpu-sh2a/freq.h b/include/asm-sh/cpu-sh2a/freq.h
deleted file mode 100644
index 830fd43b6cd..00000000000
--- a/include/asm-sh/cpu-sh2a/freq.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh2a/freq.h
3 *
4 * Copyright (C) 2006 Yoshinori Sato
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH2A_FREQ_H
11#define __ASM_CPU_SH2A_FREQ_H
12
13#define FREQCR 0xfffe0010
14
15#endif /* __ASM_CPU_SH2A_FREQ_H */
16
diff --git a/include/asm-sh/cpu-sh2a/mmu_context.h b/include/asm-sh/cpu-sh2a/mmu_context.h
deleted file mode 100644
index cd2387f7db9..00000000000
--- a/include/asm-sh/cpu-sh2a/mmu_context.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm/cpu-sh2/mmu_context.h>
diff --git a/include/asm-sh/cpu-sh2a/rtc.h b/include/asm-sh/cpu-sh2a/rtc.h
deleted file mode 100644
index afb511e2bed..00000000000
--- a/include/asm-sh/cpu-sh2a/rtc.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef __ASM_SH_CPU_SH2A_RTC_H
2#define __ASM_SH_CPU_SH2A_RTC_H
3
4#define rtc_reg_size sizeof(u16)
5#define RTC_BIT_INVERTED 0
6#define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR
7
8#endif /* __ASM_SH_CPU_SH2A_RTC_H */
diff --git a/include/asm-sh/cpu-sh2a/timer.h b/include/asm-sh/cpu-sh2a/timer.h
deleted file mode 100644
index fee504adf11..00000000000
--- a/include/asm-sh/cpu-sh2a/timer.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm/cpu-sh2/timer.h>
diff --git a/include/asm-sh/cpu-sh2a/ubc.h b/include/asm-sh/cpu-sh2a/ubc.h
deleted file mode 100644
index cf28062b96a..00000000000
--- a/include/asm-sh/cpu-sh2a/ubc.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm/cpu-sh2/ubc.h>
diff --git a/include/asm-sh/cpu-sh2a/watchdog.h b/include/asm-sh/cpu-sh2a/watchdog.h
deleted file mode 100644
index c1b3e248847..00000000000
--- a/include/asm-sh/cpu-sh2a/watchdog.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm/cpu-sh2/watchdog.h>
diff --git a/include/asm-sh/cpu-sh3/adc.h b/include/asm-sh/cpu-sh3/adc.h
deleted file mode 100644
index b289e3ca19a..00000000000
--- a/include/asm-sh/cpu-sh3/adc.h
+++ /dev/null
@@ -1,28 +0,0 @@
1#ifndef __ASM_CPU_SH3_ADC_H
2#define __ASM_CPU_SH3_ADC_H
3
4/*
5 * Copyright (C) 2004 Andriy Skulysh
6 */
7
8
9#define ADDRAH 0xa4000080
10#define ADDRAL 0xa4000082
11#define ADDRBH 0xa4000084
12#define ADDRBL 0xa4000086
13#define ADDRCH 0xa4000088
14#define ADDRCL 0xa400008a
15#define ADDRDH 0xa400008c
16#define ADDRDL 0xa400008e
17#define ADCSR 0xa4000090
18
19#define ADCSR_ADF 0x80
20#define ADCSR_ADIE 0x40
21#define ADCSR_ADST 0x20
22#define ADCSR_MULTI 0x10
23#define ADCSR_CKS 0x08
24#define ADCSR_CH_MASK 0x07
25
26#define ADCR 0xa4000092
27
28#endif /* __ASM_CPU_SH3_ADC_H */
diff --git a/include/asm-sh/cpu-sh3/addrspace.h b/include/asm-sh/cpu-sh3/addrspace.h
deleted file mode 100644
index 0f94726c7d6..00000000000
--- a/include/asm-sh/cpu-sh3/addrspace.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1999 by Kaz Kojima
7 *
8 * Defitions for the address spaces of the SH-3 CPUs.
9 */
10#ifndef __ASM_CPU_SH3_ADDRSPACE_H
11#define __ASM_CPU_SH3_ADDRSPACE_H
12
13#define P0SEG 0x00000000
14#define P1SEG 0x80000000
15#define P2SEG 0xa0000000
16#define P3SEG 0xc0000000
17#define P4SEG 0xe0000000
18
19#endif /* __ASM_CPU_SH3_ADDRSPACE_H */
diff --git a/include/asm-sh/cpu-sh3/cache.h b/include/asm-sh/cpu-sh3/cache.h
deleted file mode 100644
index bee2d81c56b..00000000000
--- a/include/asm-sh/cpu-sh3/cache.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh3/cache.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH3_CACHE_H
11#define __ASM_CPU_SH3_CACHE_H
12
13#define L1_CACHE_SHIFT 4
14
15#define SH_CACHE_VALID 1
16#define SH_CACHE_UPDATED 2
17#define SH_CACHE_COMBINED 4
18#define SH_CACHE_ASSOC 8
19
20#define CCR 0xffffffec /* Address of Cache Control Register */
21
22#define CCR_CACHE_CE 0x01 /* Cache Enable */
23#define CCR_CACHE_WT 0x02 /* Write-Through (for P0,U0,P3) (else writeback) */
24#define CCR_CACHE_CB 0x04 /* Write-Back (for P1) (else writethrough) */
25#define CCR_CACHE_CF 0x08 /* Cache Flush */
26#define CCR_CACHE_ORA 0x20 /* RAM mode */
27
28#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
29#define CACHE_PHYSADDR_MASK 0x1ffffc00
30
31#define CCR_CACHE_ENABLE CCR_CACHE_CE
32#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
33
34#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
35 defined(CONFIG_CPU_SUBTYPE_SH7710) || \
36 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
37 defined(CONFIG_CPU_SUBTYPE_SH7721)
38#define CCR3_REG 0xa40000b4
39#define CCR_CACHE_16KB 0x00010000
40#define CCR_CACHE_32KB 0x00020000
41#endif
42
43#endif /* __ASM_CPU_SH3_CACHE_H */
diff --git a/include/asm-sh/cpu-sh3/cacheflush.h b/include/asm-sh/cpu-sh3/cacheflush.h
deleted file mode 100644
index f70d8ef76a1..00000000000
--- a/include/asm-sh/cpu-sh3/cacheflush.h
+++ /dev/null
@@ -1,70 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh3/cacheflush.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH3_CACHEFLUSH_H
11#define __ASM_CPU_SH3_CACHEFLUSH_H
12
13/*
14 * Cache flushing:
15 *
16 * - flush_cache_all() flushes entire cache
17 * - flush_cache_mm(mm) flushes the specified mm context's cache lines
18 * - flush_cache_dup mm(mm) handles cache flushing when forking
19 * - flush_cache_page(mm, vmaddr, pfn) flushes a single page
20 * - flush_cache_range(vma, start, end) flushes a range of pages
21 *
22 * - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
23 * - flush_icache_range(start, end) flushes(invalidates) a range for icache
24 * - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
25 *
26 * Caches are indexed (effectively) by physical address on SH-3, so
27 * we don't need them.
28 */
29
30#if defined(CONFIG_SH7705_CACHE_32KB)
31
32/* SH7705 is an SH3 processor with 32KB cache. This has alias issues like the
33 * SH4. Unlike the SH4 this is a unified cache so we need to do some work
34 * in mmap when 'exec'ing a new binary
35 */
36 /* 32KB cache, 4kb PAGE sizes need to check bit 12 */
37#define CACHE_ALIAS 0x00001000
38
39#define PG_mapped PG_arch_1
40
41void flush_cache_all(void);
42void flush_cache_mm(struct mm_struct *mm);
43#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
44void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
45 unsigned long end);
46void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn);
47void flush_dcache_page(struct page *pg);
48void flush_icache_range(unsigned long start, unsigned long end);
49void flush_icache_page(struct vm_area_struct *vma, struct page *page);
50#else
51#define flush_cache_all() do { } while (0)
52#define flush_cache_mm(mm) do { } while (0)
53#define flush_cache_dup_mm(mm) do { } while (0)
54#define flush_cache_range(vma, start, end) do { } while (0)
55#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
56#define flush_dcache_page(page) do { } while (0)
57#define flush_icache_range(start, end) do { } while (0)
58#define flush_icache_page(vma,pg) do { } while (0)
59#endif
60
61#define flush_dcache_mmap_lock(mapping) do { } while (0)
62#define flush_dcache_mmap_unlock(mapping) do { } while (0)
63
64/* SH3 has unified cache so no special action needed here */
65#define flush_cache_sigtramp(vaddr) do { } while (0)
66#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
67
68#define p3_cache_init() do { } while (0)
69
70#endif /* __ASM_CPU_SH3_CACHEFLUSH_H */
diff --git a/include/asm-sh/cpu-sh3/dac.h b/include/asm-sh/cpu-sh3/dac.h
deleted file mode 100644
index 05fda8316eb..00000000000
--- a/include/asm-sh/cpu-sh3/dac.h
+++ /dev/null
@@ -1,41 +0,0 @@
1#ifndef __ASM_CPU_SH3_DAC_H
2#define __ASM_CPU_SH3_DAC_H
3
4/*
5 * Copyright (C) 2003 Andriy Skulysh
6 */
7
8
9#define DADR0 0xa40000a0
10#define DADR1 0xa40000a2
11#define DACR 0xa40000a4
12#define DACR_DAOE1 0x80
13#define DACR_DAOE0 0x40
14#define DACR_DAE 0x20
15
16
17static __inline__ void sh_dac_enable(int channel)
18{
19 unsigned char v;
20 v = ctrl_inb(DACR);
21 if(channel) v |= DACR_DAOE1;
22 else v |= DACR_DAOE0;
23 ctrl_outb(v,DACR);
24}
25
26static __inline__ void sh_dac_disable(int channel)
27{
28 unsigned char v;
29 v = ctrl_inb(DACR);
30 if(channel) v &= ~DACR_DAOE1;
31 else v &= ~DACR_DAOE0;
32 ctrl_outb(v,DACR);
33}
34
35static __inline__ void sh_dac_output(u8 value, int channel)
36{
37 if(channel) ctrl_outb(value,DADR1);
38 else ctrl_outb(value,DADR0);
39}
40
41#endif /* __ASM_CPU_SH3_DAC_H */
diff --git a/include/asm-sh/cpu-sh3/dma.h b/include/asm-sh/cpu-sh3/dma.h
deleted file mode 100644
index 6813c3220a1..00000000000
--- a/include/asm-sh/cpu-sh3/dma.h
+++ /dev/null
@@ -1,51 +0,0 @@
1#ifndef __ASM_CPU_SH3_DMA_H
2#define __ASM_CPU_SH3_DMA_H
3
4
5#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
6 defined(CONFIG_CPU_SUBTYPE_SH7721)
7#define SH_DMAC_BASE 0xa4010020
8#else
9#define SH_DMAC_BASE 0xa4000020
10#endif
11
12#if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7709)
13#define DMTE0_IRQ 48
14#define DMTE1_IRQ 49
15#define DMTE2_IRQ 50
16#define DMTE3_IRQ 51
17#define DMTE4_IRQ 76
18#define DMTE5_IRQ 77
19#endif
20
21/* Definitions for the SuperH DMAC */
22#define TM_BURST 0x00000020
23#define TS_8 0x00000000
24#define TS_16 0x00000008
25#define TS_32 0x00000010
26#define TS_128 0x00000018
27
28#define CHCR_TS_MASK 0x18
29#define CHCR_TS_SHIFT 3
30
31#define DMAOR_INIT DMAOR_DME
32
33/*
34 * The SuperH DMAC supports a number of transmit sizes, we list them here,
35 * with their respective values as they appear in the CHCR registers.
36 */
37enum {
38 XMIT_SZ_8BIT,
39 XMIT_SZ_16BIT,
40 XMIT_SZ_32BIT,
41 XMIT_SZ_128BIT,
42};
43
44static unsigned int ts_shift[] __maybe_unused = {
45 [XMIT_SZ_8BIT] = 0,
46 [XMIT_SZ_16BIT] = 1,
47 [XMIT_SZ_32BIT] = 2,
48 [XMIT_SZ_128BIT] = 4,
49};
50
51#endif /* __ASM_CPU_SH3_DMA_H */
diff --git a/include/asm-sh/cpu-sh3/freq.h b/include/asm-sh/cpu-sh3/freq.h
deleted file mode 100644
index 53c62302b2e..00000000000
--- a/include/asm-sh/cpu-sh3/freq.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh3/freq.h
3 *
4 * Copyright (C) 2002, 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH3_FREQ_H
11#define __ASM_CPU_SH3_FREQ_H
12
13#ifdef CONFIG_CPU_SUBTYPE_SH7712
14#define FRQCR 0xA415FF80
15#else
16#define FRQCR 0xffffff80
17#endif
18
19#define MIN_DIVISOR_NR 0
20#define MAX_DIVISOR_NR 4
21
22#define FRQCR_CKOEN 0x0100
23#define FRQCR_PLLEN 0x0080
24#define FRQCR_PSTBY 0x0040
25
26#endif /* __ASM_CPU_SH3_FREQ_H */
27
diff --git a/include/asm-sh/cpu-sh3/gpio.h b/include/asm-sh/cpu-sh3/gpio.h
deleted file mode 100644
index 4e53eb314b8..00000000000
--- a/include/asm-sh/cpu-sh3/gpio.h
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh3/gpio.h
3 *
4 * Copyright (C) 2007 Markus Brunner, Mark Jonas
5 *
6 * Addresses for the Pin Function Controller
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#ifndef _CPU_SH3_GPIO_H
13#define _CPU_SH3_GPIO_H
14
15#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
16 defined(CONFIG_CPU_SUBTYPE_SH7721)
17
18/* Control registers */
19#define PORT_PACR 0xA4050100UL
20#define PORT_PBCR 0xA4050102UL
21#define PORT_PCCR 0xA4050104UL
22#define PORT_PDCR 0xA4050106UL
23#define PORT_PECR 0xA4050108UL
24#define PORT_PFCR 0xA405010AUL
25#define PORT_PGCR 0xA405010CUL
26#define PORT_PHCR 0xA405010EUL
27#define PORT_PJCR 0xA4050110UL
28#define PORT_PKCR 0xA4050112UL
29#define PORT_PLCR 0xA4050114UL
30#define PORT_PMCR 0xA4050116UL
31#define PORT_PPCR 0xA4050118UL
32#define PORT_PRCR 0xA405011AUL
33#define PORT_PSCR 0xA405011CUL
34#define PORT_PTCR 0xA405011EUL
35#define PORT_PUCR 0xA4050120UL
36#define PORT_PVCR 0xA4050122UL
37
38/* Data registers */
39#define PORT_PADR 0xA4050140UL
40/* Address of PORT_PBDR is wrong in the datasheet, see errata 2005-09-21 */
41#define PORT_PBDR 0xA4050142UL
42#define PORT_PCDR 0xA4050144UL
43#define PORT_PDDR 0xA4050146UL
44#define PORT_PEDR 0xA4050148UL
45#define PORT_PFDR 0xA405014AUL
46#define PORT_PGDR 0xA405014CUL
47#define PORT_PHDR 0xA405014EUL
48#define PORT_PJDR 0xA4050150UL
49#define PORT_PKDR 0xA4050152UL
50#define PORT_PLDR 0xA4050154UL
51#define PORT_PMDR 0xA4050156UL
52#define PORT_PPDR 0xA4050158UL
53#define PORT_PRDR 0xA405015AUL
54#define PORT_PSDR 0xA405015CUL
55#define PORT_PTDR 0xA405015EUL
56#define PORT_PUDR 0xA4050160UL
57#define PORT_PVDR 0xA4050162UL
58
59/* Pin Select Registers */
60#define PORT_PSELA 0xA4050124UL
61#define PORT_PSELB 0xA4050126UL
62#define PORT_PSELC 0xA4050128UL
63#define PORT_PSELD 0xA405012AUL
64
65#endif
66
67#endif
diff --git a/include/asm-sh/cpu-sh3/mmu_context.h b/include/asm-sh/cpu-sh3/mmu_context.h
deleted file mode 100644
index ab09da73ce7..00000000000
--- a/include/asm-sh/cpu-sh3/mmu_context.h
+++ /dev/null
@@ -1,44 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh3/mmu_context.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH3_MMU_CONTEXT_H
11#define __ASM_CPU_SH3_MMU_CONTEXT_H
12
13#define MMU_PTEH 0xFFFFFFF0 /* Page table entry register HIGH */
14#define MMU_PTEL 0xFFFFFFF4 /* Page table entry register LOW */
15#define MMU_TTB 0xFFFFFFF8 /* Translation table base register */
16#define MMU_TEA 0xFFFFFFFC /* TLB Exception Address */
17
18#define MMUCR 0xFFFFFFE0 /* MMU Control Register */
19
20#define MMU_TLB_ADDRESS_ARRAY 0xF2000000
21#define MMU_PAGE_ASSOC_BIT 0x80
22
23#define MMU_NTLB_ENTRIES 128 /* for 7708 */
24#define MMU_NTLB_WAYS 4
25#define MMU_CONTROL_INIT 0x007 /* SV=0, TF=1, IX=1, AT=1 */
26
27#define TRA 0xffffffd0
28#define EXPEVT 0xffffffd4
29
30#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
31 defined(CONFIG_CPU_SUBTYPE_SH7706) || \
32 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
33 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
34 defined(CONFIG_CPU_SUBTYPE_SH7710) || \
35 defined(CONFIG_CPU_SUBTYPE_SH7712) || \
36 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
37 defined(CONFIG_CPU_SUBTYPE_SH7721)
38#define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */
39#else
40#define INTEVT 0xffffffd8
41#endif
42
43#endif /* __ASM_CPU_SH3_MMU_CONTEXT_H */
44
diff --git a/include/asm-sh/cpu-sh3/rtc.h b/include/asm-sh/cpu-sh3/rtc.h
deleted file mode 100644
index 319404aaee3..00000000000
--- a/include/asm-sh/cpu-sh3/rtc.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef __ASM_SH_CPU_SH3_RTC_H
2#define __ASM_SH_CPU_SH3_RTC_H
3
4#define rtc_reg_size sizeof(u16)
5#define RTC_BIT_INVERTED 0 /* No bug on SH7708, SH7709A */
6#define RTC_DEF_CAPABILITIES 0UL
7
8#endif /* __ASM_SH_CPU_SH3_RTC_H */
diff --git a/include/asm-sh/cpu-sh3/sigcontext.h b/include/asm-sh/cpu-sh3/sigcontext.h
deleted file mode 100644
index 17310dc03dc..00000000000
--- a/include/asm-sh/cpu-sh3/sigcontext.h
+++ /dev/null
@@ -1,17 +0,0 @@
1#ifndef __ASM_CPU_SH3_SIGCONTEXT_H
2#define __ASM_CPU_SH3_SIGCONTEXT_H
3
4struct sigcontext {
5 unsigned long oldmask;
6
7 /* CPU registers */
8 unsigned long sc_regs[16];
9 unsigned long sc_pc;
10 unsigned long sc_pr;
11 unsigned long sc_sr;
12 unsigned long sc_gbr;
13 unsigned long sc_mach;
14 unsigned long sc_macl;
15};
16
17#endif /* __ASM_CPU_SH3_SIGCONTEXT_H */
diff --git a/include/asm-sh/cpu-sh3/timer.h b/include/asm-sh/cpu-sh3/timer.h
deleted file mode 100644
index 793acf12aa0..00000000000
--- a/include/asm-sh/cpu-sh3/timer.h
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh3/timer.h
3 *
4 * Copyright (C) 2004 Lineo Solutions, Inc.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH3_TIMER_H
11#define __ASM_CPU_SH3_TIMER_H
12
13/*
14 * ---------------------------------------------------------------------------
15 * TMU Common definitions for SH3 processors
16 * SH7706
17 * SH7709S
18 * SH7727
19 * SH7729R
20 * SH7710
21 * SH7720
22 * SH7710
23 * ---------------------------------------------------------------------------
24 */
25
26#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
27#define TMU_TOCR 0xfffffe90 /* Byte access */
28#endif
29
30#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
31 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
32 defined(CONFIG_CPU_SUBTYPE_SH7721)
33#define TMU_012_TSTR 0xa412fe92 /* Byte access */
34
35#define TMU0_TCOR 0xa412fe94 /* Long access */
36#define TMU0_TCNT 0xa412fe98 /* Long access */
37#define TMU0_TCR 0xa412fe9c /* Word access */
38
39#define TMU1_TCOR 0xa412fea0 /* Long access */
40#define TMU1_TCNT 0xa412fea4 /* Long access */
41#define TMU1_TCR 0xa412fea8 /* Word access */
42
43#define TMU2_TCOR 0xa412feac /* Long access */
44#define TMU2_TCNT 0xa412feb0 /* Long access */
45#define TMU2_TCR 0xa412feb4 /* Word access */
46
47#else
48#define TMU_012_TSTR 0xfffffe92 /* Byte access */
49
50#define TMU0_TCOR 0xfffffe94 /* Long access */
51#define TMU0_TCNT 0xfffffe98 /* Long access */
52#define TMU0_TCR 0xfffffe9c /* Word access */
53
54#define TMU1_TCOR 0xfffffea0 /* Long access */
55#define TMU1_TCNT 0xfffffea4 /* Long access */
56#define TMU1_TCR 0xfffffea8 /* Word access */
57
58#define TMU2_TCOR 0xfffffeac /* Long access */
59#define TMU2_TCNT 0xfffffeb0 /* Long access */
60#define TMU2_TCR 0xfffffeb4 /* Word access */
61#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
62#define TMU2_TCPR2 0xfffffeb8 /* Long access */
63#endif
64#endif
65
66#endif /* __ASM_CPU_SH3_TIMER_H */
67
diff --git a/include/asm-sh/cpu-sh3/ubc.h b/include/asm-sh/cpu-sh3/ubc.h
deleted file mode 100644
index 4e6381d5ff7..00000000000
--- a/include/asm-sh/cpu-sh3/ubc.h
+++ /dev/null
@@ -1,42 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh3/ubc.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 * Copyright (C) 2003 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#ifndef __ASM_CPU_SH3_UBC_H
12#define __ASM_CPU_SH3_UBC_H
13
14#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
15 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
16 defined(CONFIG_CPU_SUBTYPE_SH7721)
17#define UBC_BARA 0xa4ffffb0
18#define UBC_BAMRA 0xa4ffffb4
19#define UBC_BBRA 0xa4ffffb8
20#define UBC_BASRA 0xffffffe4
21#define UBC_BARB 0xa4ffffa0
22#define UBC_BAMRB 0xa4ffffa4
23#define UBC_BBRB 0xa4ffffa8
24#define UBC_BASRB 0xffffffe8
25#define UBC_BDRB 0xa4ffff90
26#define UBC_BDMRB 0xa4ffff94
27#define UBC_BRCR 0xa4ffff98
28#else
29#define UBC_BARA 0xffffffb0
30#define UBC_BAMRA 0xffffffb4
31#define UBC_BBRA 0xffffffb8
32#define UBC_BASRA 0xffffffe4
33#define UBC_BARB 0xffffffa0
34#define UBC_BAMRB 0xffffffa4
35#define UBC_BBRB 0xffffffa8
36#define UBC_BASRB 0xffffffe8
37#define UBC_BDRB 0xffffff90
38#define UBC_BDMRB 0xffffff94
39#define UBC_BRCR 0xffffff98
40#endif
41
42#endif /* __ASM_CPU_SH3_UBC_H */
diff --git a/include/asm-sh/cpu-sh3/watchdog.h b/include/asm-sh/cpu-sh3/watchdog.h
deleted file mode 100644
index 4ee0347298d..00000000000
--- a/include/asm-sh/cpu-sh3/watchdog.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh3/watchdog.h
3 *
4 * Copyright (C) 2002, 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH3_WATCHDOG_H
11#define __ASM_CPU_SH3_WATCHDOG_H
12
13/* Register definitions */
14#define WTCNT 0xffffff84
15#define WTCSR 0xffffff86
16
17/* Bit definitions */
18#define WTCSR_TME 0x80
19#define WTCSR_WT 0x40
20#define WTCSR_RSTS 0x20
21#define WTCSR_WOVF 0x10
22#define WTCSR_IOVF 0x08
23
24#endif /* __ASM_CPU_SH3_WATCHDOG_H */
25
diff --git a/include/asm-sh/cpu-sh4/addrspace.h b/include/asm-sh/cpu-sh4/addrspace.h
deleted file mode 100644
index a3fa733c1c7..00000000000
--- a/include/asm-sh/cpu-sh4/addrspace.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1999 by Kaz Kojima
7 *
8 * Defitions for the address spaces of the SH-4 CPUs.
9 */
10#ifndef __ASM_CPU_SH4_ADDRSPACE_H
11#define __ASM_CPU_SH4_ADDRSPACE_H
12
13#define P0SEG 0x00000000
14#define P1SEG 0x80000000
15#define P2SEG 0xa0000000
16#define P3SEG 0xc0000000
17#define P4SEG 0xe0000000
18
19/* Detailed P4SEG */
20#define P4SEG_STORE_QUE (P4SEG)
21#define P4SEG_IC_ADDR 0xf0000000
22#define P4SEG_IC_DATA 0xf1000000
23#define P4SEG_ITLB_ADDR 0xf2000000
24#define P4SEG_ITLB_DATA 0xf3000000
25#define P4SEG_OC_ADDR 0xf4000000
26#define P4SEG_OC_DATA 0xf5000000
27#define P4SEG_TLB_ADDR 0xf6000000
28#define P4SEG_TLB_DATA 0xf7000000
29#define P4SEG_REG_BASE 0xff000000
30
31#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
32#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
33
34#endif /* __ASM_CPU_SH4_ADDRSPACE_H */
35
diff --git a/include/asm-sh/cpu-sh4/cache.h b/include/asm-sh/cpu-sh4/cache.h
deleted file mode 100644
index 1c61ebf5c8e..00000000000
--- a/include/asm-sh/cpu-sh4/cache.h
+++ /dev/null
@@ -1,42 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh4/cache.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH4_CACHE_H
11#define __ASM_CPU_SH4_CACHE_H
12
13#define L1_CACHE_SHIFT 5
14
15#define SH_CACHE_VALID 1
16#define SH_CACHE_UPDATED 2
17#define SH_CACHE_COMBINED 4
18#define SH_CACHE_ASSOC 8
19
20#define CCR 0xff00001c /* Address of Cache Control Register */
21#define CCR_CACHE_OCE 0x0001 /* Operand Cache Enable */
22#define CCR_CACHE_WT 0x0002 /* Write-Through (for P0,U0,P3) (else writeback)*/
23#define CCR_CACHE_CB 0x0004 /* Copy-Back (for P1) (else writethrough) */
24#define CCR_CACHE_OCI 0x0008 /* OC Invalidate */
25#define CCR_CACHE_ORA 0x0020 /* OC RAM Mode */
26#define CCR_CACHE_OIX 0x0080 /* OC Index Enable */
27#define CCR_CACHE_ICE 0x0100 /* Instruction Cache Enable */
28#define CCR_CACHE_ICI 0x0800 /* IC Invalidate */
29#define CCR_CACHE_IIX 0x8000 /* IC Index Enable */
30#ifndef CONFIG_CPU_SH4A
31#define CCR_CACHE_EMODE 0x80000000 /* EMODE Enable */
32#endif
33
34/* Default CCR setup: 8k+16k-byte cache,P1-wb,enable */
35#define CCR_CACHE_ENABLE (CCR_CACHE_OCE|CCR_CACHE_ICE)
36#define CCR_CACHE_INVALIDATE (CCR_CACHE_OCI|CCR_CACHE_ICI)
37
38#define CACHE_IC_ADDRESS_ARRAY 0xf0000000
39#define CACHE_OC_ADDRESS_ARRAY 0xf4000000
40
41#endif /* __ASM_CPU_SH4_CACHE_H */
42
diff --git a/include/asm-sh/cpu-sh4/cacheflush.h b/include/asm-sh/cpu-sh4/cacheflush.h
deleted file mode 100644
index 5fd5c89ef86..00000000000
--- a/include/asm-sh/cpu-sh4/cacheflush.h
+++ /dev/null
@@ -1,44 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh4/cacheflush.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 * Copyright (C) 2003 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#ifndef __ASM_CPU_SH4_CACHEFLUSH_H
12#define __ASM_CPU_SH4_CACHEFLUSH_H
13
14/*
15 * Caches are broken on SH-4 (unless we use write-through
16 * caching; in which case they're only semi-broken),
17 * so we need them.
18 */
19void flush_cache_all(void);
20void flush_dcache_all(void);
21void flush_cache_mm(struct mm_struct *mm);
22#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
23void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
24 unsigned long end);
25void flush_cache_page(struct vm_area_struct *vma, unsigned long addr,
26 unsigned long pfn);
27void flush_dcache_page(struct page *pg);
28
29#define flush_dcache_mmap_lock(mapping) do { } while (0)
30#define flush_dcache_mmap_unlock(mapping) do { } while (0)
31
32void flush_icache_range(unsigned long start, unsigned long end);
33void flush_cache_sigtramp(unsigned long addr);
34void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
35 unsigned long addr, int len);
36
37#define flush_icache_page(vma,pg) do { } while (0)
38
39/* Initialization of P3 area for copy_user_page */
40void p3_cache_init(void);
41
42#define PG_mapped PG_arch_1
43
44#endif /* __ASM_CPU_SH4_CACHEFLUSH_H */
diff --git a/include/asm-sh/cpu-sh4/dma-sh7780.h b/include/asm-sh/cpu-sh4/dma-sh7780.h
deleted file mode 100644
index 71b426a6e48..00000000000
--- a/include/asm-sh/cpu-sh4/dma-sh7780.h
+++ /dev/null
@@ -1,39 +0,0 @@
1#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H
2#define __ASM_SH_CPU_SH4_DMA_SH7780_H
3
4#define REQ_HE 0x000000C0
5#define REQ_H 0x00000080
6#define REQ_LE 0x00000040
7#define TM_BURST 0x0000020
8#define TS_8 0x00000000
9#define TS_16 0x00000008
10#define TS_32 0x00000010
11#define TS_16BLK 0x00000018
12#define TS_32BLK 0x00100000
13
14/*
15 * The SuperH DMAC supports a number of transmit sizes, we list them here,
16 * with their respective values as they appear in the CHCR registers.
17 *
18 * Defaults to a 64-bit transfer size.
19 */
20enum {
21 XMIT_SZ_8BIT,
22 XMIT_SZ_16BIT,
23 XMIT_SZ_32BIT,
24 XMIT_SZ_128BIT,
25 XMIT_SZ_256BIT,
26};
27
28/*
29 * The DMA count is defined as the number of bytes to transfer.
30 */
31static unsigned int ts_shift[] __maybe_unused = {
32 [XMIT_SZ_8BIT] = 0,
33 [XMIT_SZ_16BIT] = 1,
34 [XMIT_SZ_32BIT] = 2,
35 [XMIT_SZ_128BIT] = 4,
36 [XMIT_SZ_256BIT] = 5,
37};
38
39#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */
diff --git a/include/asm-sh/cpu-sh4/dma.h b/include/asm-sh/cpu-sh4/dma.h
deleted file mode 100644
index aaf71b018c2..00000000000
--- a/include/asm-sh/cpu-sh4/dma.h
+++ /dev/null
@@ -1,65 +0,0 @@
1#ifndef __ASM_CPU_SH4_DMA_H
2#define __ASM_CPU_SH4_DMA_H
3
4#define DMAOR_INIT ( 0x8000 | DMAOR_DME )
5
6/* SH7751/7760/7780 DMA IRQ sources */
7#define DMTE0_IRQ 34
8#define DMTE1_IRQ 35
9#define DMTE2_IRQ 36
10#define DMTE3_IRQ 37
11#define DMTE4_IRQ 44
12#define DMTE5_IRQ 45
13#define DMTE6_IRQ 46
14#define DMTE7_IRQ 47
15#define DMAE_IRQ 38
16
17#ifdef CONFIG_CPU_SH4A
18#define SH_DMAC_BASE 0xfc808020
19
20#define CHCR_TS_MASK 0x18
21#define CHCR_TS_SHIFT 3
22
23#include <asm/cpu/dma-sh7780.h>
24#else
25#define SH_DMAC_BASE 0xffa00000
26
27/* Definitions for the SuperH DMAC */
28#define TM_BURST 0x0000080
29#define TS_8 0x00000010
30#define TS_16 0x00000020
31#define TS_32 0x00000030
32#define TS_64 0x00000000
33
34#define CHCR_TS_MASK 0x70
35#define CHCR_TS_SHIFT 4
36
37#define DMAOR_COD 0x00000008
38
39/*
40 * The SuperH DMAC supports a number of transmit sizes, we list them here,
41 * with their respective values as they appear in the CHCR registers.
42 *
43 * Defaults to a 64-bit transfer size.
44 */
45enum {
46 XMIT_SZ_64BIT,
47 XMIT_SZ_8BIT,
48 XMIT_SZ_16BIT,
49 XMIT_SZ_32BIT,
50 XMIT_SZ_256BIT,
51};
52
53/*
54 * The DMA count is defined as the number of bytes to transfer.
55 */
56static unsigned int ts_shift[] __maybe_unused = {
57 [XMIT_SZ_64BIT] = 3,
58 [XMIT_SZ_8BIT] = 0,
59 [XMIT_SZ_16BIT] = 1,
60 [XMIT_SZ_32BIT] = 2,
61 [XMIT_SZ_256BIT] = 5,
62};
63#endif
64
65#endif /* __ASM_CPU_SH4_DMA_H */
diff --git a/include/asm-sh/cpu-sh4/fpu.h b/include/asm-sh/cpu-sh4/fpu.h
deleted file mode 100644
index febef734252..00000000000
--- a/include/asm-sh/cpu-sh4/fpu.h
+++ /dev/null
@@ -1,32 +0,0 @@
1/*
2 * linux/arch/sh/kernel/cpu/sh4/sh4_fpu.h
3 *
4 * Copyright (C) 2006 STMicroelectronics Limited
5 * Author: Carl Shaw <carl.shaw@st.com>
6 *
7 * May be copied or modified under the terms of the GNU General Public
8 * License Version 2. See linux/COPYING for more information.
9 *
10 * Definitions for SH4 FPU operations
11 */
12
13#ifndef __CPU_SH4_FPU_H
14#define __CPU_SH4_FPU_H
15
16#define FPSCR_ENABLE_MASK 0x00000f80UL
17
18#define FPSCR_FMOV_DOUBLE (1<<1)
19
20#define FPSCR_CAUSE_INEXACT (1<<12)
21#define FPSCR_CAUSE_UNDERFLOW (1<<13)
22#define FPSCR_CAUSE_OVERFLOW (1<<14)
23#define FPSCR_CAUSE_DIVZERO (1<<15)
24#define FPSCR_CAUSE_INVALID (1<<16)
25#define FPSCR_CAUSE_ERROR (1<<17)
26
27#define FPSCR_DBL_PRECISION (1<<19)
28#define FPSCR_ROUNDING_MODE(x) ((x >> 20) & 3)
29#define FPSCR_RM_NEAREST (0)
30#define FPSCR_RM_ZERO (1)
31
32#endif
diff --git a/include/asm-sh/cpu-sh4/freq.h b/include/asm-sh/cpu-sh4/freq.h
deleted file mode 100644
index da46e67ae26..00000000000
--- a/include/asm-sh/cpu-sh4/freq.h
+++ /dev/null
@@ -1,40 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh4/freq.h
3 *
4 * Copyright (C) 2002, 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH4_FREQ_H
11#define __ASM_CPU_SH4_FREQ_H
12
13#if defined(CONFIG_CPU_SUBTYPE_SH7722) || \
14 defined(CONFIG_CPU_SUBTYPE_SH7723) || \
15 defined(CONFIG_CPU_SUBTYPE_SH7366)
16#define FRQCR 0xa4150000
17#define VCLKCR 0xa4150004
18#define SCLKACR 0xa4150008
19#define SCLKBCR 0xa415000c
20#define IrDACLKCR 0xa4150010
21#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
22 defined(CONFIG_CPU_SUBTYPE_SH7780)
23#define FRQCR 0xffc80000
24#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
25#define FRQCR0 0xffc80000
26#define FRQCR1 0xffc80004
27#define FRQMR1 0xffc80014
28#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
29#define FRQCR 0xffc00014
30#else
31#define FRQCR 0xffc00000
32#define FRQCR_PSTBY 0x0200
33#define FRQCR_PLLEN 0x0400
34#define FRQCR_CKOEN 0x0800
35#endif
36#define MIN_DIVISOR_NR 0
37#define MAX_DIVISOR_NR 3
38
39#endif /* __ASM_CPU_SH4_FREQ_H */
40
diff --git a/include/asm-sh/cpu-sh4/mmu_context.h b/include/asm-sh/cpu-sh4/mmu_context.h
deleted file mode 100644
index 9ea8eb27b18..00000000000
--- a/include/asm-sh/cpu-sh4/mmu_context.h
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh4/mmu_context.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH4_MMU_CONTEXT_H
11#define __ASM_CPU_SH4_MMU_CONTEXT_H
12
13#define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */
14#define MMU_PTEL 0xFF000004 /* Page table entry register LOW */
15#define MMU_TTB 0xFF000008 /* Translation table base register */
16#define MMU_TEA 0xFF00000C /* TLB Exception Address */
17#define MMU_PTEA 0xFF000034 /* Page table entry assistance register */
18
19#define MMUCR 0xFF000010 /* MMU Control Register */
20
21#define MMU_ITLB_ADDRESS_ARRAY 0xF2000000
22#define MMU_UTLB_ADDRESS_ARRAY 0xF6000000
23#define MMU_PAGE_ASSOC_BIT 0x80
24
25#define MMUCR_TI (1<<2)
26
27#ifdef CONFIG_X2TLB
28#define MMUCR_ME (1 << 7)
29#else
30#define MMUCR_ME (0)
31#endif
32
33#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_SUBTYPE_ST40)
34#define MMUCR_SE (1 << 4)
35#else
36#define MMUCR_SE (0)
37#endif
38
39#ifdef CONFIG_SH_STORE_QUEUES
40#define MMUCR_SQMD (1 << 9)
41#else
42#define MMUCR_SQMD (0)
43#endif
44
45#define MMU_NTLB_ENTRIES 64
46#define MMU_CONTROL_INIT (0x05|MMUCR_SQMD|MMUCR_ME|MMUCR_SE)
47
48#define MMU_ITLB_DATA_ARRAY 0xF3000000
49#define MMU_UTLB_DATA_ARRAY 0xF7000000
50
51#define MMU_UTLB_ENTRIES 64
52#define MMU_U_ENTRY_SHIFT 8
53#define MMU_UTLB_VALID 0x100
54#define MMU_ITLB_ENTRIES 4
55#define MMU_I_ENTRY_SHIFT 8
56#define MMU_ITLB_VALID 0x100
57
58#define TRA 0xff000020
59#define EXPEVT 0xff000024
60#define INTEVT 0xff000028
61
62#endif /* __ASM_CPU_SH4_MMU_CONTEXT_H */
63
diff --git a/include/asm-sh/cpu-sh4/rtc.h b/include/asm-sh/cpu-sh4/rtc.h
deleted file mode 100644
index 25b1e6adfe8..00000000000
--- a/include/asm-sh/cpu-sh4/rtc.h
+++ /dev/null
@@ -1,13 +0,0 @@
1#ifndef __ASM_SH_CPU_SH4_RTC_H
2#define __ASM_SH_CPU_SH4_RTC_H
3
4#ifdef CONFIG_CPU_SUBTYPE_SH7723
5#define rtc_reg_size sizeof(u16)
6#else
7#define rtc_reg_size sizeof(u32)
8#endif
9
10#define RTC_BIT_INVERTED 0x40 /* bug on SH7750, SH7750S */
11#define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR
12
13#endif /* __ASM_SH_CPU_SH4_RTC_H */
diff --git a/include/asm-sh/cpu-sh4/sigcontext.h b/include/asm-sh/cpu-sh4/sigcontext.h
deleted file mode 100644
index ab392f120e0..00000000000
--- a/include/asm-sh/cpu-sh4/sigcontext.h
+++ /dev/null
@@ -1,24 +0,0 @@
1#ifndef __ASM_CPU_SH4_SIGCONTEXT_H
2#define __ASM_CPU_SH4_SIGCONTEXT_H
3
4struct sigcontext {
5 unsigned long oldmask;
6
7 /* CPU registers */
8 unsigned long sc_regs[16];
9 unsigned long sc_pc;
10 unsigned long sc_pr;
11 unsigned long sc_sr;
12 unsigned long sc_gbr;
13 unsigned long sc_mach;
14 unsigned long sc_macl;
15
16 /* FPU registers */
17 unsigned long sc_fpregs[16];
18 unsigned long sc_xfpregs[16];
19 unsigned int sc_fpscr;
20 unsigned int sc_fpul;
21 unsigned int sc_ownedfp;
22};
23
24#endif /* __ASM_CPU_SH4_SIGCONTEXT_H */
diff --git a/include/asm-sh/cpu-sh4/sq.h b/include/asm-sh/cpu-sh4/sq.h
deleted file mode 100644
index 586d6491816..00000000000
--- a/include/asm-sh/cpu-sh4/sq.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh4/sq.h
3 *
4 * Copyright (C) 2001, 2002, 2003 Paul Mundt
5 * Copyright (C) 2001, 2002 M. R. Brown
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#ifndef __ASM_CPU_SH4_SQ_H
12#define __ASM_CPU_SH4_SQ_H
13
14#include <asm/addrspace.h>
15
16/*
17 * Store queues range from e0000000-e3fffffc, allowing approx. 64MB to be
18 * mapped to any physical address space. Since data is written (and aligned)
19 * to 32-byte boundaries, we need to be sure that all allocations are aligned.
20 */
21#define SQ_SIZE 32
22#define SQ_ALIGN_MASK (~(SQ_SIZE - 1))
23#define SQ_ALIGN(addr) (((addr)+SQ_SIZE-1) & SQ_ALIGN_MASK)
24
25#define SQ_QACR0 (P4SEG_REG_BASE + 0x38)
26#define SQ_QACR1 (P4SEG_REG_BASE + 0x3c)
27#define SQ_ADDRMAX (P4SEG_STORE_QUE + 0x04000000)
28
29/* arch/sh/kernel/cpu/sh4/sq.c */
30unsigned long sq_remap(unsigned long phys, unsigned int size,
31 const char *name, unsigned long flags);
32void sq_unmap(unsigned long vaddr);
33void sq_flush_range(unsigned long start, unsigned int len);
34
35#endif /* __ASM_CPU_SH4_SQ_H */
diff --git a/include/asm-sh/cpu-sh4/timer.h b/include/asm-sh/cpu-sh4/timer.h
deleted file mode 100644
index d1e796b9688..00000000000
--- a/include/asm-sh/cpu-sh4/timer.h
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh4/timer.h
3 *
4 * Copyright (C) 2004 Lineo Solutions, Inc.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH4_TIMER_H
11#define __ASM_CPU_SH4_TIMER_H
12
13/*
14 * ---------------------------------------------------------------------------
15 * TMU Common definitions for SH4 processors
16 * SH7750S/SH7750R
17 * SH7751/SH7751R
18 * SH7760
19 * SH-X3
20 * ---------------------------------------------------------------------------
21 */
22#ifdef CONFIG_CPU_SUBTYPE_SHX3
23#define TMU_012_BASE 0xffc10000
24#define TMU_345_BASE 0xffc20000
25#else
26#define TMU_012_BASE 0xffd80000
27#define TMU_345_BASE 0xfe100000
28#endif
29
30#define TMU_TOCR TMU_012_BASE /* Not supported on all CPUs */
31
32#define TMU_012_TSTR (TMU_012_BASE + 0x04)
33#define TMU_345_TSTR (TMU_345_BASE + 0x04)
34
35#define TMU0_TCOR (TMU_012_BASE + 0x08)
36#define TMU0_TCNT (TMU_012_BASE + 0x0c)
37#define TMU0_TCR (TMU_012_BASE + 0x10)
38
39#define TMU1_TCOR (TMU_012_BASE + 0x14)
40#define TMU1_TCNT (TMU_012_BASE + 0x18)
41#define TMU1_TCR (TMU_012_BASE + 0x1c)
42
43#define TMU2_TCOR (TMU_012_BASE + 0x20)
44#define TMU2_TCNT (TMU_012_BASE + 0x24)
45#define TMU2_TCR (TMU_012_BASE + 0x28)
46#define TMU2_TCPR (TMU_012_BASE + 0x2c)
47
48#define TMU3_TCOR (TMU_345_BASE + 0x08)
49#define TMU3_TCNT (TMU_345_BASE + 0x0c)
50#define TMU3_TCR (TMU_345_BASE + 0x10)
51
52#define TMU4_TCOR (TMU_345_BASE + 0x14)
53#define TMU4_TCNT (TMU_345_BASE + 0x18)
54#define TMU4_TCR (TMU_345_BASE + 0x1c)
55
56#define TMU5_TCOR (TMU_345_BASE + 0x20)
57#define TMU5_TCNT (TMU_345_BASE + 0x24)
58#define TMU5_TCR (TMU_345_BASE + 0x28)
59
60#endif /* __ASM_CPU_SH4_TIMER_H */
diff --git a/include/asm-sh/cpu-sh4/ubc.h b/include/asm-sh/cpu-sh4/ubc.h
deleted file mode 100644
index c86e1705093..00000000000
--- a/include/asm-sh/cpu-sh4/ubc.h
+++ /dev/null
@@ -1,64 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh4/ubc.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 * Copyright (C) 2003 Paul Mundt
6 * Copyright (C) 2006 Lineo Solutions Inc. support SH4A UBC
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#ifndef __ASM_CPU_SH4_UBC_H
13#define __ASM_CPU_SH4_UBC_H
14
15#if defined(CONFIG_CPU_SH4A)
16#define UBC_CBR0 0xff200000
17#define UBC_CRR0 0xff200004
18#define UBC_CAR0 0xff200008
19#define UBC_CAMR0 0xff20000c
20#define UBC_CBR1 0xff200020
21#define UBC_CRR1 0xff200024
22#define UBC_CAR1 0xff200028
23#define UBC_CAMR1 0xff20002c
24#define UBC_CDR1 0xff200030
25#define UBC_CDMR1 0xff200034
26#define UBC_CETR1 0xff200038
27#define UBC_CCMFR 0xff200600
28#define UBC_CBCR 0xff200620
29
30/* CBR */
31#define UBC_CBR_AIE (0x01<<30)
32#define UBC_CBR_ID_INST (0x01<<4)
33#define UBC_CBR_RW_READ (0x01<<1)
34#define UBC_CBR_CE (0x01)
35
36#define UBC_CBR_AIV_MASK (0x00FF0000)
37#define UBC_CBR_AIV_SHIFT (16)
38#define UBC_CBR_AIV_SET(asid) (((asid)<<UBC_CBR_AIV_SHIFT) & UBC_CBR_AIV_MASK)
39
40#define UBC_CBR_INIT 0x20000000
41
42/* CRR */
43#define UBC_CRR_RES (0x01<<13)
44#define UBC_CRR_PCB (0x01<<1)
45#define UBC_CRR_BIE (0x01)
46
47#define UBC_CRR_INIT 0x00002000
48
49#else /* CONFIG_CPU_SH4 */
50#define UBC_BARA 0xff200000
51#define UBC_BAMRA 0xff200004
52#define UBC_BBRA 0xff200008
53#define UBC_BASRA 0xff000014
54#define UBC_BARB 0xff20000c
55#define UBC_BAMRB 0xff200010
56#define UBC_BBRB 0xff200014
57#define UBC_BASRB 0xff000018
58#define UBC_BDRB 0xff200018
59#define UBC_BDMRB 0xff20001c
60#define UBC_BRCR 0xff200020
61#endif /* CONFIG_CPU_SH4 */
62
63#endif /* __ASM_CPU_SH4_UBC_H */
64
diff --git a/include/asm-sh/cpu-sh4/watchdog.h b/include/asm-sh/cpu-sh4/watchdog.h
deleted file mode 100644
index 259f6a0ce23..00000000000
--- a/include/asm-sh/cpu-sh4/watchdog.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh4/watchdog.h
3 *
4 * Copyright (C) 2002, 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH4_WATCHDOG_H
11#define __ASM_CPU_SH4_WATCHDOG_H
12
13/* Register definitions */
14#define WTCNT 0xffc00008
15#define WTCSR 0xffc0000c
16
17/* Bit definitions */
18#define WTCSR_TME 0x80
19#define WTCSR_WT 0x40
20#define WTCSR_RSTS 0x20
21#define WTCSR_WOVF 0x10
22#define WTCSR_IOVF 0x08
23
24#endif /* __ASM_CPU_SH4_WATCHDOG_H */
25
diff --git a/include/asm-sh/cpu-sh5/addrspace.h b/include/asm-sh/cpu-sh5/addrspace.h
deleted file mode 100644
index dc36b9a03af..00000000000
--- a/include/asm-sh/cpu-sh5/addrspace.h
+++ /dev/null
@@ -1,11 +0,0 @@
1#ifndef __ASM_SH_CPU_SH5_ADDRSPACE_H
2#define __ASM_SH_CPU_SH5_ADDRSPACE_H
3
4#define PHYS_PERIPHERAL_BLOCK 0x09000000
5#define PHYS_DMAC_BLOCK 0x0e000000
6#define PHYS_PCI_BLOCK 0x60000000
7#define PHYS_EMI_BLOCK 0xff000000
8
9/* No segmentation.. */
10
11#endif /* __ASM_SH_CPU_SH5_ADDRSPACE_H */
diff --git a/include/asm-sh/cpu-sh5/cache.h b/include/asm-sh/cpu-sh5/cache.h
deleted file mode 100644
index ed050ab526f..00000000000
--- a/include/asm-sh/cpu-sh5/cache.h
+++ /dev/null
@@ -1,97 +0,0 @@
1#ifndef __ASM_SH_CPU_SH5_CACHE_H
2#define __ASM_SH_CPU_SH5_CACHE_H
3
4/*
5 * include/asm-sh/cpu-sh5/cache.h
6 *
7 * Copyright (C) 2000, 2001 Paolo Alberelli
8 * Copyright (C) 2003, 2004 Paul Mundt
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
12 * for more details.
13 */
14
15#define L1_CACHE_SHIFT 5
16
17/* Valid and Dirty bits */
18#define SH_CACHE_VALID (1LL<<0)
19#define SH_CACHE_UPDATED (1LL<<57)
20
21/* Unimplemented compat bits.. */
22#define SH_CACHE_COMBINED 0
23#define SH_CACHE_ASSOC 0
24
25/* Cache flags */
26#define SH_CACHE_MODE_WT (1LL<<0)
27#define SH_CACHE_MODE_WB (1LL<<1)
28
29/*
30 * Control Registers.
31 */
32#define ICCR_BASE 0x01600000 /* Instruction Cache Control Register */
33#define ICCR_REG0 0 /* Register 0 offset */
34#define ICCR_REG1 1 /* Register 1 offset */
35#define ICCR0 ICCR_BASE+ICCR_REG0
36#define ICCR1 ICCR_BASE+ICCR_REG1
37
38#define ICCR0_OFF 0x0 /* Set ICACHE off */
39#define ICCR0_ON 0x1 /* Set ICACHE on */
40#define ICCR0_ICI 0x2 /* Invalidate all in IC */
41
42#define ICCR1_NOLOCK 0x0 /* Set No Locking */
43
44#define OCCR_BASE 0x01E00000 /* Operand Cache Control Register */
45#define OCCR_REG0 0 /* Register 0 offset */
46#define OCCR_REG1 1 /* Register 1 offset */
47#define OCCR0 OCCR_BASE+OCCR_REG0
48#define OCCR1 OCCR_BASE+OCCR_REG1
49
50#define OCCR0_OFF 0x0 /* Set OCACHE off */
51#define OCCR0_ON 0x1 /* Set OCACHE on */
52#define OCCR0_OCI 0x2 /* Invalidate all in OC */
53#define OCCR0_WT 0x4 /* Set OCACHE in WT Mode */
54#define OCCR0_WB 0x0 /* Set OCACHE in WB Mode */
55
56#define OCCR1_NOLOCK 0x0 /* Set No Locking */
57
58/*
59 * SH-5
60 * A bit of description here, for neff=32.
61 *
62 * |<--- tag (19 bits) --->|
63 * +-----------------------------+-----------------+------+----------+------+
64 * | | | ways |set index |offset|
65 * +-----------------------------+-----------------+------+----------+------+
66 * ^ 2 bits 8 bits 5 bits
67 * +- Bit 31
68 *
69 * Cacheline size is based on offset: 5 bits = 32 bytes per line
70 * A cache line is identified by a tag + set but OCACHETAG/ICACHETAG
71 * have a broader space for registers. These are outlined by
72 * CACHE_?C_*_STEP below.
73 *
74 */
75
76/* Instruction cache */
77#define CACHE_IC_ADDRESS_ARRAY 0x01000000
78
79/* Operand Cache */
80#define CACHE_OC_ADDRESS_ARRAY 0x01800000
81
82/* These declarations relate to cache 'synonyms' in the operand cache. A
83 'synonym' occurs where effective address bits overlap between those used for
84 indexing the cache sets and those passed to the MMU for translation. In the
85 case of SH5-101 & SH5-103, only bit 12 is affected for 4k pages. */
86
87#define CACHE_OC_N_SYNBITS 1 /* Number of synonym bits */
88#define CACHE_OC_SYN_SHIFT 12
89/* Mask to select synonym bit(s) */
90#define CACHE_OC_SYN_MASK (((1UL<<CACHE_OC_N_SYNBITS)-1)<<CACHE_OC_SYN_SHIFT)
91
92/*
93 * Instruction cache can't be invalidated based on physical addresses.
94 * No Instruction Cache defines required, then.
95 */
96
97#endif /* __ASM_SH_CPU_SH5_CACHE_H */
diff --git a/include/asm-sh/cpu-sh5/cacheflush.h b/include/asm-sh/cpu-sh5/cacheflush.h
deleted file mode 100644
index 5a11f0b7e66..00000000000
--- a/include/asm-sh/cpu-sh5/cacheflush.h
+++ /dev/null
@@ -1,33 +0,0 @@
1#ifndef __ASM_SH_CPU_SH5_CACHEFLUSH_H
2#define __ASM_SH_CPU_SH5_CACHEFLUSH_H
3
4#ifndef __ASSEMBLY__
5
6struct vm_area_struct;
7struct page;
8struct mm_struct;
9
10extern void flush_cache_all(void);
11extern void flush_cache_mm(struct mm_struct *mm);
12extern void flush_cache_sigtramp(unsigned long vaddr);
13extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
14 unsigned long end);
15extern void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn);
16extern void flush_dcache_page(struct page *pg);
17extern void flush_icache_range(unsigned long start, unsigned long end);
18extern void flush_icache_user_range(struct vm_area_struct *vma,
19 struct page *page, unsigned long addr,
20 int len);
21
22#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
23
24#define flush_dcache_mmap_lock(mapping) do { } while (0)
25#define flush_dcache_mmap_unlock(mapping) do { } while (0)
26
27#define flush_icache_page(vma, page) do { } while (0)
28void p3_cache_init(void);
29
30#endif /* __ASSEMBLY__ */
31
32#endif /* __ASM_SH_CPU_SH5_CACHEFLUSH_H */
33
diff --git a/include/asm-sh/cpu-sh5/dma.h b/include/asm-sh/cpu-sh5/dma.h
deleted file mode 100644
index 7bf6bb3d35e..00000000000
--- a/include/asm-sh/cpu-sh5/dma.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef __ASM_SH_CPU_SH5_DMA_H
2#define __ASM_SH_CPU_SH5_DMA_H
3
4/* Nothing yet */
5
6#endif /* __ASM_SH_CPU_SH5_DMA_H */
diff --git a/include/asm-sh/cpu-sh5/irq.h b/include/asm-sh/cpu-sh5/irq.h
deleted file mode 100644
index f0f0756e6e8..00000000000
--- a/include/asm-sh/cpu-sh5/irq.h
+++ /dev/null
@@ -1,117 +0,0 @@
1#ifndef __ASM_SH_CPU_SH5_IRQ_H
2#define __ASM_SH_CPU_SH5_IRQ_H
3
4/*
5 * include/asm-sh/cpu-sh5/irq.h
6 *
7 * Copyright (C) 2000, 2001 Paolo Alberelli
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13
14
15/*
16 * Encoded IRQs are not considered worth to be supported.
17 * Main reason is that there's no per-encoded-interrupt
18 * enable/disable mechanism (as there was in SH3/4).
19 * An all enabled/all disabled is worth only if there's
20 * a cascaded IC to disable/enable/ack on. Until such
21 * IC is available there's no such support.
22 *
23 * Presumably Encoded IRQs may use extra IRQs beyond 64,
24 * below. Some logic must be added to cope with IRQ_IRL?
25 * in an exclusive way.
26 *
27 * Priorities are set at Platform level, when IRQ_IRL0-3
28 * are set to 0 Encoding is allowed. Otherwise it's not
29 * allowed.
30 */
31
32/* Independent IRQs */
33#define IRQ_IRL0 0
34#define IRQ_IRL1 1
35#define IRQ_IRL2 2
36#define IRQ_IRL3 3
37
38#define IRQ_INTA 4
39#define IRQ_INTB 5
40#define IRQ_INTC 6
41#define IRQ_INTD 7
42
43#define IRQ_SERR 12
44#define IRQ_ERR 13
45#define IRQ_PWR3 14
46#define IRQ_PWR2 15
47#define IRQ_PWR1 16
48#define IRQ_PWR0 17
49
50#define IRQ_DMTE0 18
51#define IRQ_DMTE1 19
52#define IRQ_DMTE2 20
53#define IRQ_DMTE3 21
54#define IRQ_DAERR 22
55
56#define IRQ_TUNI0 32
57#define IRQ_TUNI1 33
58#define IRQ_TUNI2 34
59#define IRQ_TICPI2 35
60
61#define IRQ_ATI 36
62#define IRQ_PRI 37
63#define IRQ_CUI 38
64
65#define IRQ_ERI 39
66#define IRQ_RXI 40
67#define IRQ_BRI 41
68#define IRQ_TXI 42
69
70#define IRQ_ITI 63
71
72#define NR_INTC_IRQS 64
73
74#ifdef CONFIG_SH_CAYMAN
75#define NR_EXT_IRQS 32
76#define START_EXT_IRQS 64
77
78/* PCI bus 2 uses encoded external interrupts on the Cayman board */
79#define IRQ_P2INTA (START_EXT_IRQS + (3*8) + 0)
80#define IRQ_P2INTB (START_EXT_IRQS + (3*8) + 1)
81#define IRQ_P2INTC (START_EXT_IRQS + (3*8) + 2)
82#define IRQ_P2INTD (START_EXT_IRQS + (3*8) + 3)
83
84#define I8042_KBD_IRQ (START_EXT_IRQS + 2)
85#define I8042_AUX_IRQ (START_EXT_IRQS + 6)
86
87#define IRQ_CFCARD (START_EXT_IRQS + 7)
88#define IRQ_PCMCIA (0)
89
90#else
91#define NR_EXT_IRQS 0
92#endif
93
94/* Default IRQs, fixed */
95#define TIMER_IRQ IRQ_TUNI0
96#define RTC_IRQ IRQ_CUI
97
98/* Default Priorities, Platform may choose differently */
99#define NO_PRIORITY 0 /* Disabled */
100#define TIMER_PRIORITY 2
101#define RTC_PRIORITY TIMER_PRIORITY
102#define SCIF_PRIORITY 3
103#define INTD_PRIORITY 3
104#define IRL3_PRIORITY 4
105#define INTC_PRIORITY 6
106#define IRL2_PRIORITY 7
107#define INTB_PRIORITY 9
108#define IRL1_PRIORITY 10
109#define INTA_PRIORITY 12
110#define IRL0_PRIORITY 13
111#define TOP_PRIORITY 15
112
113extern int intc_evt_to_irq[(0xE20/0x20)+1];
114int intc_irq_describe(char* p, int irq);
115extern int platform_int_priority[NR_INTC_IRQS];
116
117#endif /* __ASM_SH_CPU_SH5_IRQ_H */
diff --git a/include/asm-sh/cpu-sh5/mmu_context.h b/include/asm-sh/cpu-sh5/mmu_context.h
deleted file mode 100644
index 68a1d2cff45..00000000000
--- a/include/asm-sh/cpu-sh5/mmu_context.h
+++ /dev/null
@@ -1,21 +0,0 @@
1#ifndef __ASM_SH_CPU_SH5_MMU_CONTEXT_H
2#define __ASM_SH_CPU_SH5_MMU_CONTEXT_H
3
4/* Common defines */
5#define TLB_STEP 0x00000010
6#define TLB_PTEH 0x00000000
7#define TLB_PTEL 0x00000008
8
9/* PTEH defines */
10#define PTEH_ASID_SHIFT 2
11#define PTEH_VALID 0x0000000000000001
12#define PTEH_SHARED 0x0000000000000002
13#define PTEH_MATCH_ASID 0x00000000000003ff
14
15#ifndef __ASSEMBLY__
16/* This has to be a common function because the next location to fill
17 * information is shared. */
18extern void __do_tlb_refill(unsigned long address, unsigned long long is_text_not_data, pte_t *pte);
19#endif /* __ASSEMBLY__ */
20
21#endif /* __ASM_SH_CPU_SH5_MMU_CONTEXT_H */
diff --git a/include/asm-sh/cpu-sh5/registers.h b/include/asm-sh/cpu-sh5/registers.h
deleted file mode 100644
index 6664ea6f156..00000000000
--- a/include/asm-sh/cpu-sh5/registers.h
+++ /dev/null
@@ -1,106 +0,0 @@
1#ifndef __ASM_SH_CPU_SH5_REGISTERS_H
2#define __ASM_SH_CPU_SH5_REGISTERS_H
3
4/*
5 * include/asm-sh/cpu-sh5/registers.h
6 *
7 * Copyright (C) 2000, 2001 Paolo Alberelli
8 * Copyright (C) 2004 Richard Curnow
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
12 * for more details.
13 */
14
15#ifdef __ASSEMBLY__
16/* =====================================================================
17**
18** Section 1: acts on assembly sources pre-processed by GPP ( <source.S>).
19** Assigns symbolic names to control & target registers.
20*/
21
22/*
23 * Define some useful aliases for control registers.
24 */
25#define SR cr0
26#define SSR cr1
27#define PSSR cr2
28 /* cr3 UNDEFINED */
29#define INTEVT cr4
30#define EXPEVT cr5
31#define PEXPEVT cr6
32#define TRA cr7
33#define SPC cr8
34#define PSPC cr9
35#define RESVEC cr10
36#define VBR cr11
37 /* cr12 UNDEFINED */
38#define TEA cr13
39 /* cr14-cr15 UNDEFINED */
40#define DCR cr16
41#define KCR0 cr17
42#define KCR1 cr18
43 /* cr19-cr31 UNDEFINED */
44 /* cr32-cr61 RESERVED */
45#define CTC cr62
46#define USR cr63
47
48/*
49 * ABI dependent registers (general purpose set)
50 */
51#define RET r2
52#define ARG1 r2
53#define ARG2 r3
54#define ARG3 r4
55#define ARG4 r5
56#define ARG5 r6
57#define ARG6 r7
58#define SP r15
59#define LINK r18
60#define ZERO r63
61
62/*
63 * Status register defines: used only by assembly sources (and
64 * syntax independednt)
65 */
66#define SR_RESET_VAL 0x0000000050008000
67#define SR_HARMLESS 0x00000000500080f0 /* Write ignores for most */
68#define SR_ENABLE_FPU 0xffffffffffff7fff /* AND with this */
69
70#if defined (CONFIG_SH64_SR_WATCH)
71#define SR_ENABLE_MMU 0x0000000084000000 /* OR with this */
72#else
73#define SR_ENABLE_MMU 0x0000000080000000 /* OR with this */
74#endif
75
76#define SR_UNBLOCK_EXC 0xffffffffefffffff /* AND with this */
77#define SR_BLOCK_EXC 0x0000000010000000 /* OR with this */
78
79#else /* Not __ASSEMBLY__ syntax */
80
81/*
82** Stringify reg. name
83*/
84#define __str(x) #x
85
86/* Stringify control register names for use in inline assembly */
87#define __SR __str(SR)
88#define __SSR __str(SSR)
89#define __PSSR __str(PSSR)
90#define __INTEVT __str(INTEVT)
91#define __EXPEVT __str(EXPEVT)
92#define __PEXPEVT __str(PEXPEVT)
93#define __TRA __str(TRA)
94#define __SPC __str(SPC)
95#define __PSPC __str(PSPC)
96#define __RESVEC __str(RESVEC)
97#define __VBR __str(VBR)
98#define __TEA __str(TEA)
99#define __DCR __str(DCR)
100#define __KCR0 __str(KCR0)
101#define __KCR1 __str(KCR1)
102#define __CTC __str(CTC)
103#define __USR __str(USR)
104
105#endif /* __ASSEMBLY__ */
106#endif /* __ASM_SH_CPU_SH5_REGISTERS_H */
diff --git a/include/asm-sh/cpu-sh5/rtc.h b/include/asm-sh/cpu-sh5/rtc.h
deleted file mode 100644
index 12ea0ed144e..00000000000
--- a/include/asm-sh/cpu-sh5/rtc.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef __ASM_SH_CPU_SH5_RTC_H
2#define __ASM_SH_CPU_SH5_RTC_H
3
4#define rtc_reg_size sizeof(u32)
5#define RTC_BIT_INVERTED 0 /* The SH-5 RTC is surprisingly sane! */
6#define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR
7
8#endif /* __ASM_SH_CPU_SH5_RTC_H */
diff --git a/include/asm-sh/cpu-sh5/timer.h b/include/asm-sh/cpu-sh5/timer.h
deleted file mode 100644
index 88da9b341a3..00000000000
--- a/include/asm-sh/cpu-sh5/timer.h
+++ /dev/null
@@ -1,4 +0,0 @@
1#ifndef __ASM_SH_CPU_SH5_TIMER_H
2#define __ASM_SH_CPU_SH5_TIMER_H
3
4#endif /* __ASM_SH_CPU_SH5_TIMER_H */
diff --git a/include/asm-sh/cputime.h b/include/asm-sh/cputime.h
deleted file mode 100644
index 6ca395d1393..00000000000
--- a/include/asm-sh/cputime.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef __SH_CPUTIME_H
2#define __SH_CPUTIME_H
3
4#include <asm-generic/cputime.h>
5
6#endif /* __SH_CPUTIME_H */
diff --git a/include/asm-sh/current.h b/include/asm-sh/current.h
deleted file mode 100644
index 62b63880b33..00000000000
--- a/include/asm-sh/current.h
+++ /dev/null
@@ -1,20 +0,0 @@
1#ifndef __ASM_SH_CURRENT_H
2#define __ASM_SH_CURRENT_H
3
4/*
5 * Copyright (C) 1999 Niibe Yutaka
6 *
7 */
8
9#include <linux/thread_info.h>
10
11struct task_struct;
12
13static __inline__ struct task_struct * get_current(void)
14{
15 return current_thread_info()->task;
16}
17
18#define current get_current()
19
20#endif /* __ASM_SH_CURRENT_H */
diff --git a/include/asm-sh/delay.h b/include/asm-sh/delay.h
deleted file mode 100644
index 4b16bf9b56b..00000000000
--- a/include/asm-sh/delay.h
+++ /dev/null
@@ -1,26 +0,0 @@
1#ifndef __ASM_SH_DELAY_H
2#define __ASM_SH_DELAY_H
3
4/*
5 * Copyright (C) 1993 Linus Torvalds
6 *
7 * Delay routines calling functions in arch/sh/lib/delay.c
8 */
9
10extern void __bad_udelay(void);
11extern void __bad_ndelay(void);
12
13extern void __udelay(unsigned long usecs);
14extern void __ndelay(unsigned long nsecs);
15extern void __const_udelay(unsigned long xloops);
16extern void __delay(unsigned long loops);
17
18#define udelay(n) (__builtin_constant_p(n) ? \
19 ((n) > 20000 ? __bad_udelay() : __const_udelay((n) * 0x10c6ul)) : \
20 __udelay(n))
21
22#define ndelay(n) (__builtin_constant_p(n) ? \
23 ((n) > 20000 ? __bad_ndelay() : __const_udelay((n) * 5ul)) : \
24 __ndelay(n))
25
26#endif /* __ASM_SH_DELAY_H */
diff --git a/include/asm-sh/device.h b/include/asm-sh/device.h
deleted file mode 100644
index d8f9872b0e2..00000000000
--- a/include/asm-sh/device.h
+++ /dev/null
@@ -1,7 +0,0 @@
1/*
2 * Arch specific extensions to struct device
3 *
4 * This file is released under the GPLv2
5 */
6#include <asm-generic/device.h>
7
diff --git a/include/asm-sh/div64.h b/include/asm-sh/div64.h
deleted file mode 100644
index 6cd978cefb2..00000000000
--- a/include/asm-sh/div64.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/div64.h>
diff --git a/include/asm-sh/dma-mapping.h b/include/asm-sh/dma-mapping.h
deleted file mode 100644
index 6c0b8a2de14..00000000000
--- a/include/asm-sh/dma-mapping.h
+++ /dev/null
@@ -1,192 +0,0 @@
1#ifndef __ASM_SH_DMA_MAPPING_H
2#define __ASM_SH_DMA_MAPPING_H
3
4#include <linux/mm.h>
5#include <linux/scatterlist.h>
6#include <asm/cacheflush.h>
7#include <asm/io.h>
8
9extern struct bus_type pci_bus_type;
10
11#define dma_supported(dev, mask) (1)
12
13static inline int dma_set_mask(struct device *dev, u64 mask)
14{
15 if (!dev->dma_mask || !dma_supported(dev, mask))
16 return -EIO;
17
18 *dev->dma_mask = mask;
19
20 return 0;
21}
22
23void *dma_alloc_coherent(struct device *dev, size_t size,
24 dma_addr_t *dma_handle, gfp_t flag);
25
26void dma_free_coherent(struct device *dev, size_t size,
27 void *vaddr, dma_addr_t dma_handle);
28
29void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
30 enum dma_data_direction dir);
31
32#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
33#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
34#define dma_is_consistent(d, h) (1)
35
36static inline dma_addr_t dma_map_single(struct device *dev,
37 void *ptr, size_t size,
38 enum dma_data_direction dir)
39{
40#if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT)
41 if (dev->bus == &pci_bus_type)
42 return virt_to_phys(ptr);
43#endif
44 dma_cache_sync(dev, ptr, size, dir);
45
46 return virt_to_phys(ptr);
47}
48
49#define dma_unmap_single(dev, addr, size, dir) do { } while (0)
50
51static inline int dma_map_sg(struct device *dev, struct scatterlist *sg,
52 int nents, enum dma_data_direction dir)
53{
54 int i;
55
56 for (i = 0; i < nents; i++) {
57#if !defined(CONFIG_PCI) || defined(CONFIG_SH_PCIDMA_NONCOHERENT)
58 dma_cache_sync(dev, sg_virt(&sg[i]), sg[i].length, dir);
59#endif
60 sg[i].dma_address = sg_phys(&sg[i]);
61 }
62
63 return nents;
64}
65
66#define dma_unmap_sg(dev, sg, nents, dir) do { } while (0)
67
68static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
69 unsigned long offset, size_t size,
70 enum dma_data_direction dir)
71{
72 return dma_map_single(dev, page_address(page) + offset, size, dir);
73}
74
75static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
76 size_t size, enum dma_data_direction dir)
77{
78 dma_unmap_single(dev, dma_address, size, dir);
79}
80
81static inline void dma_sync_single(struct device *dev, dma_addr_t dma_handle,
82 size_t size, enum dma_data_direction dir)
83{
84#if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT)
85 if (dev->bus == &pci_bus_type)
86 return;
87#endif
88 dma_cache_sync(dev, phys_to_virt(dma_handle), size, dir);
89}
90
91static inline void dma_sync_single_range(struct device *dev,
92 dma_addr_t dma_handle,
93 unsigned long offset, size_t size,
94 enum dma_data_direction dir)
95{
96#if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT)
97 if (dev->bus == &pci_bus_type)
98 return;
99#endif
100 dma_cache_sync(dev, phys_to_virt(dma_handle) + offset, size, dir);
101}
102
103static inline void dma_sync_sg(struct device *dev, struct scatterlist *sg,
104 int nelems, enum dma_data_direction dir)
105{
106 int i;
107
108 for (i = 0; i < nelems; i++) {
109#if !defined(CONFIG_PCI) || defined(CONFIG_SH_PCIDMA_NONCOHERENT)
110 dma_cache_sync(dev, sg_virt(&sg[i]), sg[i].length, dir);
111#endif
112 sg[i].dma_address = sg_phys(&sg[i]);
113 }
114}
115
116static inline void dma_sync_single_for_cpu(struct device *dev,
117 dma_addr_t dma_handle, size_t size,
118 enum dma_data_direction dir)
119{
120 dma_sync_single(dev, dma_handle, size, dir);
121}
122
123static inline void dma_sync_single_for_device(struct device *dev,
124 dma_addr_t dma_handle,
125 size_t size,
126 enum dma_data_direction dir)
127{
128 dma_sync_single(dev, dma_handle, size, dir);
129}
130
131static inline void dma_sync_single_range_for_cpu(struct device *dev,
132 dma_addr_t dma_handle,
133 unsigned long offset,
134 size_t size,
135 enum dma_data_direction direction)
136{
137 dma_sync_single_for_cpu(dev, dma_handle+offset, size, direction);
138}
139
140static inline void dma_sync_single_range_for_device(struct device *dev,
141 dma_addr_t dma_handle,
142 unsigned long offset,
143 size_t size,
144 enum dma_data_direction direction)
145{
146 dma_sync_single_for_device(dev, dma_handle+offset, size, direction);
147}
148
149
150static inline void dma_sync_sg_for_cpu(struct device *dev,
151 struct scatterlist *sg, int nelems,
152 enum dma_data_direction dir)
153{
154 dma_sync_sg(dev, sg, nelems, dir);
155}
156
157static inline void dma_sync_sg_for_device(struct device *dev,
158 struct scatterlist *sg, int nelems,
159 enum dma_data_direction dir)
160{
161 dma_sync_sg(dev, sg, nelems, dir);
162}
163
164
165static inline int dma_get_cache_alignment(void)
166{
167 /*
168 * Each processor family will define its own L1_CACHE_SHIFT,
169 * L1_CACHE_BYTES wraps to this, so this is always safe.
170 */
171 return L1_CACHE_BYTES;
172}
173
174static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
175{
176 return dma_addr == 0;
177}
178
179#define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
180
181extern int
182dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
183 dma_addr_t device_addr, size_t size, int flags);
184
185extern void
186dma_release_declared_memory(struct device *dev);
187
188extern void *
189dma_mark_declared_memory_occupied(struct device *dev,
190 dma_addr_t device_addr, size_t size);
191
192#endif /* __ASM_SH_DMA_MAPPING_H */
diff --git a/include/asm-sh/dma.h b/include/asm-sh/dma.h
deleted file mode 100644
index a65b02fd186..00000000000
--- a/include/asm-sh/dma.h
+++ /dev/null
@@ -1,166 +0,0 @@
1/*
2 * include/asm-sh/dma.h
3 *
4 * Copyright (C) 2003, 2004 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_SH_DMA_H
11#define __ASM_SH_DMA_H
12#ifdef __KERNEL__
13
14#include <linux/spinlock.h>
15#include <linux/wait.h>
16#include <linux/sched.h>
17#include <linux/sysdev.h>
18#include <asm/cpu/dma.h>
19
20/* The maximum address that we can perform a DMA transfer to on this platform */
21/* Don't define MAX_DMA_ADDRESS; it's useless on the SuperH and any
22 occurrence should be flagged as an error. */
23/* But... */
24/* XXX: This is not applicable to SuperH, just needed for alloc_bootmem */
25#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x10000000)
26
27#ifdef CONFIG_NR_DMA_CHANNELS
28# define MAX_DMA_CHANNELS (CONFIG_NR_DMA_CHANNELS)
29#else
30# define MAX_DMA_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS)
31#endif
32
33/*
34 * Read and write modes can mean drastically different things depending on the
35 * channel configuration. Consult your DMAC documentation and module
36 * implementation for further clues.
37 */
38#define DMA_MODE_READ 0x00
39#define DMA_MODE_WRITE 0x01
40#define DMA_MODE_MASK 0x01
41
42#define DMA_AUTOINIT 0x10
43
44/*
45 * DMAC (dma_info) flags
46 */
47enum {
48 DMAC_CHANNELS_CONFIGURED = 0x01,
49 DMAC_CHANNELS_TEI_CAPABLE = 0x02, /* Transfer end interrupt */
50};
51
52/*
53 * DMA channel capabilities / flags
54 */
55enum {
56 DMA_CONFIGURED = 0x01,
57
58 /*
59 * Transfer end interrupt, inherited from DMAC.
60 * wait_queue used in dma_wait_for_completion.
61 */
62 DMA_TEI_CAPABLE = 0x02,
63};
64
65extern spinlock_t dma_spin_lock;
66
67struct dma_channel;
68
69struct dma_ops {
70 int (*request)(struct dma_channel *chan);
71 void (*free)(struct dma_channel *chan);
72
73 int (*get_residue)(struct dma_channel *chan);
74 int (*xfer)(struct dma_channel *chan);
75 int (*configure)(struct dma_channel *chan, unsigned long flags);
76 int (*extend)(struct dma_channel *chan, unsigned long op, void *param);
77};
78
79struct dma_channel {
80 char dev_id[16]; /* unique name per DMAC of channel */
81
82 unsigned int chan; /* DMAC channel number */
83 unsigned int vchan; /* Virtual channel number */
84
85 unsigned int mode;
86 unsigned int count;
87
88 unsigned long sar;
89 unsigned long dar;
90
91 const char **caps;
92
93 unsigned long flags;
94 atomic_t busy;
95
96 wait_queue_head_t wait_queue;
97
98 struct sys_device dev;
99 void *priv_data;
100};
101
102struct dma_info {
103 struct platform_device *pdev;
104
105 const char *name;
106 unsigned int nr_channels;
107 unsigned long flags;
108
109 struct dma_ops *ops;
110 struct dma_channel *channels;
111
112 struct list_head list;
113 int first_channel_nr;
114 int first_vchannel_nr;
115};
116
117struct dma_chan_caps {
118 int ch_num;
119 const char **caplist;
120};
121
122#define to_dma_channel(channel) container_of(channel, struct dma_channel, dev)
123
124/* arch/sh/drivers/dma/dma-api.c */
125extern int dma_xfer(unsigned int chan, unsigned long from,
126 unsigned long to, size_t size, unsigned int mode);
127
128#define dma_write(chan, from, to, size) \
129 dma_xfer(chan, from, to, size, DMA_MODE_WRITE)
130#define dma_write_page(chan, from, to) \
131 dma_write(chan, from, to, PAGE_SIZE)
132
133#define dma_read(chan, from, to, size) \
134 dma_xfer(chan, from, to, size, DMA_MODE_READ)
135#define dma_read_page(chan, from, to) \
136 dma_read(chan, from, to, PAGE_SIZE)
137
138extern int request_dma_bycap(const char **dmac, const char **caps,
139 const char *dev_id);
140extern int request_dma(unsigned int chan, const char *dev_id);
141extern void free_dma(unsigned int chan);
142extern int get_dma_residue(unsigned int chan);
143extern struct dma_info *get_dma_info(unsigned int chan);
144extern struct dma_channel *get_dma_channel(unsigned int chan);
145extern void dma_wait_for_completion(unsigned int chan);
146extern void dma_configure_channel(unsigned int chan, unsigned long flags);
147
148extern int register_dmac(struct dma_info *info);
149extern void unregister_dmac(struct dma_info *info);
150extern struct dma_info *get_dma_info_by_name(const char *dmac_name);
151
152extern int dma_extend(unsigned int chan, unsigned long op, void *param);
153extern int register_chan_caps(const char *dmac, struct dma_chan_caps *capslist);
154
155/* arch/sh/drivers/dma/dma-sysfs.c */
156extern int dma_create_sysfs_files(struct dma_channel *, struct dma_info *);
157extern void dma_remove_sysfs_files(struct dma_channel *, struct dma_info *);
158
159#ifdef CONFIG_PCI
160extern int isa_dma_bridge_buggy;
161#else
162#define isa_dma_bridge_buggy (0)
163#endif
164
165#endif /* __KERNEL__ */
166#endif /* __ASM_SH_DMA_H */
diff --git a/include/asm-sh/dmabrg.h b/include/asm-sh/dmabrg.h
deleted file mode 100644
index c5edba216cf..00000000000
--- a/include/asm-sh/dmabrg.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * SH7760 DMABRG (USB/Audio) support
3 */
4
5#ifndef _DMABRG_H_
6#define _DMABRG_H_
7
8/* IRQ sources */
9#define DMABRGIRQ_USBDMA 0
10#define DMABRGIRQ_USBDMAERR 1
11#define DMABRGIRQ_A0TXF 2
12#define DMABRGIRQ_A0TXH 3
13#define DMABRGIRQ_A0RXF 4
14#define DMABRGIRQ_A0RXH 5
15#define DMABRGIRQ_A1TXF 6
16#define DMABRGIRQ_A1TXH 7
17#define DMABRGIRQ_A1RXF 8
18#define DMABRGIRQ_A1RXH 9
19
20extern int dmabrg_request_irq(unsigned int, void(*)(void *), void *);
21extern void dmabrg_free_irq(unsigned int);
22
23#endif
diff --git a/include/asm-sh/dreamcast/dma.h b/include/asm-sh/dreamcast/dma.h
deleted file mode 100644
index ddd68e78870..00000000000
--- a/include/asm-sh/dreamcast/dma.h
+++ /dev/null
@@ -1,34 +0,0 @@
1/*
2 * include/asm-sh/dreamcast/dma.h
3 *
4 * Copyright (C) 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_SH_DREAMCAST_DMA_H
11#define __ASM_SH_DREAMCAST_DMA_H
12
13/* Number of DMA channels */
14#define ONCHIP_NR_DMA_CHANNELS 4
15#define G2_NR_DMA_CHANNELS 4
16#define PVR2_NR_DMA_CHANNELS 1
17
18/* Channels for cascading */
19#define PVR2_CASCADE_CHAN 2
20#define G2_CASCADE_CHAN 3
21
22/* PVR2 DMA Registers */
23#define PVR2_DMA_BASE 0xa05f6800
24#define PVR2_DMA_ADDR (PVR2_DMA_BASE + 0)
25#define PVR2_DMA_COUNT (PVR2_DMA_BASE + 4)
26#define PVR2_DMA_MODE (PVR2_DMA_BASE + 8)
27#define PVR2_DMA_LMMODE0 (PVR2_DMA_BASE + 132)
28#define PVR2_DMA_LMMODE1 (PVR2_DMA_BASE + 136)
29
30/* G2 DMA Register */
31#define G2_DMA_BASE 0xa05f7800
32
33#endif /* __ASM_SH_DREAMCAST_DMA_H */
34
diff --git a/include/asm-sh/dreamcast/maple.h b/include/asm-sh/dreamcast/maple.h
deleted file mode 100644
index 51f6a87f1f1..00000000000
--- a/include/asm-sh/dreamcast/maple.h
+++ /dev/null
@@ -1,37 +0,0 @@
1#ifndef __ASM_MAPLE_H
2#define __ASM_MAPLE_H
3
4#define MAPLE_PORTS 4
5#define MAPLE_PNP_INTERVAL HZ
6#define MAPLE_MAXPACKETS 8
7#define MAPLE_DMA_ORDER 14
8#define MAPLE_DMA_SIZE (1 << MAPLE_DMA_ORDER)
9#define MAPLE_DMA_PAGES ((MAPLE_DMA_ORDER > PAGE_SHIFT) ? \
10 MAPLE_DMA_ORDER - PAGE_SHIFT : 0)
11
12/* Maple Bus registers */
13#define MAPLE_BASE 0xa05f6c00
14#define MAPLE_DMAADDR (MAPLE_BASE+0x04)
15#define MAPLE_TRIGTYPE (MAPLE_BASE+0x10)
16#define MAPLE_ENABLE (MAPLE_BASE+0x14)
17#define MAPLE_STATE (MAPLE_BASE+0x18)
18#define MAPLE_SPEED (MAPLE_BASE+0x80)
19#define MAPLE_RESET (MAPLE_BASE+0x8c)
20
21#define MAPLE_MAGIC 0x6155404f
22#define MAPLE_2MBPS 0
23#define MAPLE_TIMEOUT(n) ((n)<<15)
24
25/* Function codes */
26#define MAPLE_FUNC_CONTROLLER 0x001
27#define MAPLE_FUNC_MEMCARD 0x002
28#define MAPLE_FUNC_LCD 0x004
29#define MAPLE_FUNC_CLOCK 0x008
30#define MAPLE_FUNC_MICROPHONE 0x010
31#define MAPLE_FUNC_ARGUN 0x020
32#define MAPLE_FUNC_KEYBOARD 0x040
33#define MAPLE_FUNC_LIGHTGUN 0x080
34#define MAPLE_FUNC_PURUPURU 0x100
35#define MAPLE_FUNC_MOUSE 0x200
36
37#endif /* __ASM_MAPLE_H */
diff --git a/include/asm-sh/dreamcast/pci.h b/include/asm-sh/dreamcast/pci.h
deleted file mode 100644
index e401b24b0d8..00000000000
--- a/include/asm-sh/dreamcast/pci.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * include/asm-sh/dreamcast/pci.h
3 *
4 * Copyright (C) 2001, 2002 M. R. Brown
5 * Copyright (C) 2002, 2003 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#ifndef __ASM_SH_DREAMCAST_PCI_H
12#define __ASM_SH_DREAMCAST_PCI_H
13
14#include <asm/mach/sysasic.h>
15
16#define GAPSPCI_REGS 0x01001400
17#define GAPSPCI_DMA_BASE 0x01840000
18#define GAPSPCI_DMA_SIZE 32768
19#define GAPSPCI_BBA_CONFIG 0x01001600
20#define GAPSPCI_BBA_CONFIG_SIZE 0x2000
21
22#define GAPSPCI_IRQ HW_EVENT_EXTERNAL
23
24#endif /* __ASM_SH_DREAMCAST_PCI_H */
25
diff --git a/include/asm-sh/dreamcast/sysasic.h b/include/asm-sh/dreamcast/sysasic.h
deleted file mode 100644
index f33426608a8..00000000000
--- a/include/asm-sh/dreamcast/sysasic.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/* include/asm-sh/dreamcast/sysasic.h
2 *
3 * Definitions for the Dreamcast System ASIC and related peripherals.
4 *
5 * Copyright (c) 2001 M. R. Brown <mrbrown@linuxdc.org>
6 * Copyright (C) 2003 Paul Mundt <lethal@linux-sh.org>
7 *
8 * This file is part of the LinuxDC project (www.linuxdc.org)
9 *
10 * Released under the terms of the GNU GPL v2.0.
11 *
12 */
13#ifndef __ASM_SH_DREAMCAST_SYSASIC_H
14#define __ASM_SH_DREAMCAST_SYSASIC_H
15
16#include <asm/irq.h>
17
18/* Hardware events -
19
20 Each of these events correspond to a bit within the Event Mask Registers/
21 Event Status Registers. Because of the virtual IRQ numbering scheme, a
22 base offset must be used when calculating the virtual IRQ that each event
23 takes.
24*/
25
26#define HW_EVENT_IRQ_BASE 48
27
28/* IRQ 13 */
29#define HW_EVENT_VSYNC (HW_EVENT_IRQ_BASE + 5) /* VSync */
30#define HW_EVENT_MAPLE_DMA (HW_EVENT_IRQ_BASE + 12) /* Maple DMA complete */
31#define HW_EVENT_GDROM_DMA (HW_EVENT_IRQ_BASE + 14) /* GD-ROM DMA complete */
32#define HW_EVENT_G2_DMA (HW_EVENT_IRQ_BASE + 15) /* G2 DMA complete */
33#define HW_EVENT_PVR2_DMA (HW_EVENT_IRQ_BASE + 19) /* PVR2 DMA complete */
34
35/* IRQ 11 */
36#define HW_EVENT_GDROM_CMD (HW_EVENT_IRQ_BASE + 32) /* GD-ROM cmd. complete */
37#define HW_EVENT_AICA_SYS (HW_EVENT_IRQ_BASE + 33) /* AICA-related */
38#define HW_EVENT_EXTERNAL (HW_EVENT_IRQ_BASE + 35) /* Ext. (expansion) */
39
40#define HW_EVENT_IRQ_MAX (HW_EVENT_IRQ_BASE + 95)
41
42#endif /* __ASM_SH_DREAMCAST_SYSASIC_H */
43
diff --git a/include/asm-sh/edosk7705.h b/include/asm-sh/edosk7705.h
deleted file mode 100644
index 5bdc9d9be3d..00000000000
--- a/include/asm-sh/edosk7705.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * include/asm-sh/edosk7705.h
3 *
4 * Modified version of io_se.h for the EDOSK7705 specific functions.
5 *
6 * May be copied or modified under the terms of the GNU General Public
7 * License. See linux/COPYING for more information.
8 *
9 * IO functions for an Hitachi EDOSK7705 development board
10 */
11
12#ifndef __ASM_SH_EDOSK7705_IO_H
13#define __ASM_SH_EDOSK7705_IO_H
14
15#include <asm/io_generic.h>
16
17extern unsigned char sh_edosk7705_inb(unsigned long port);
18extern unsigned int sh_edosk7705_inl(unsigned long port);
19
20extern void sh_edosk7705_outb(unsigned char value, unsigned long port);
21extern void sh_edosk7705_outl(unsigned int value, unsigned long port);
22
23extern void sh_edosk7705_insb(unsigned long port, void *addr, unsigned long count);
24extern void sh_edosk7705_insl(unsigned long port, void *addr, unsigned long count);
25extern void sh_edosk7705_outsb(unsigned long port, const void *addr, unsigned long count);
26extern void sh_edosk7705_outsl(unsigned long port, const void *addr, unsigned long count);
27
28extern unsigned long sh_edosk7705_isa_port2addr(unsigned long offset);
29
30#endif /* __ASM_SH_EDOSK7705_IO_H */
diff --git a/include/asm-sh/elf.h b/include/asm-sh/elf.h
deleted file mode 100644
index 05092da1aa5..00000000000
--- a/include/asm-sh/elf.h
+++ /dev/null
@@ -1,193 +0,0 @@
1#ifndef __ASM_SH_ELF_H
2#define __ASM_SH_ELF_H
3
4#include <asm/auxvec.h>
5#include <asm/ptrace.h>
6#include <asm/user.h>
7
8/* SH (particularly SHcompact) relocation types */
9#define R_SH_NONE 0
10#define R_SH_DIR32 1
11#define R_SH_REL32 2
12#define R_SH_DIR8WPN 3
13#define R_SH_IND12W 4
14#define R_SH_DIR8WPL 5
15#define R_SH_DIR8WPZ 6
16#define R_SH_DIR8BP 7
17#define R_SH_DIR8W 8
18#define R_SH_DIR8L 9
19#define R_SH_SWITCH16 25
20#define R_SH_SWITCH32 26
21#define R_SH_USES 27
22#define R_SH_COUNT 28
23#define R_SH_ALIGN 29
24#define R_SH_CODE 30
25#define R_SH_DATA 31
26#define R_SH_LABEL 32
27#define R_SH_SWITCH8 33
28#define R_SH_GNU_VTINHERIT 34
29#define R_SH_GNU_VTENTRY 35
30#define R_SH_TLS_GD_32 144
31#define R_SH_TLS_LD_32 145
32#define R_SH_TLS_LDO_32 146
33#define R_SH_TLS_IE_32 147
34#define R_SH_TLS_LE_32 148
35#define R_SH_TLS_DTPMOD32 149
36#define R_SH_TLS_DTPOFF32 150
37#define R_SH_TLS_TPOFF32 151
38#define R_SH_GOT32 160
39#define R_SH_PLT32 161
40#define R_SH_COPY 162
41#define R_SH_GLOB_DAT 163
42#define R_SH_JMP_SLOT 164
43#define R_SH_RELATIVE 165
44#define R_SH_GOTOFF 166
45#define R_SH_GOTPC 167
46/* SHmedia relocs */
47#define R_SH_IMM_LOW16 246
48#define R_SH_IMM_LOW16_PCREL 247
49#define R_SH_IMM_MEDLOW16 248
50#define R_SH_IMM_MEDLOW16_PCREL 249
51/* Keep this the last entry. */
52#define R_SH_NUM 256
53
54/*
55 * ELF register definitions..
56 */
57
58typedef unsigned long elf_greg_t;
59
60#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t))
61typedef elf_greg_t elf_gregset_t[ELF_NGREG];
62
63typedef struct user_fpu_struct elf_fpregset_t;
64
65/*
66 * These are used to set parameters in the core dumps.
67 */
68#define ELF_CLASS ELFCLASS32
69#ifdef __LITTLE_ENDIAN__
70#define ELF_DATA ELFDATA2LSB
71#else
72#define ELF_DATA ELFDATA2MSB
73#endif
74#define ELF_ARCH EM_SH
75
76#ifdef __KERNEL__
77/*
78 * This is used to ensure we don't load something for the wrong architecture.
79 */
80#define elf_check_arch(x) ( (x)->e_machine == EM_SH )
81
82#define USE_ELF_CORE_DUMP
83#define ELF_EXEC_PAGESIZE PAGE_SIZE
84
85/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
86 use of this is to invoke "./ld.so someprog" to test out a new version of
87 the loader. We need to make sure that it is out of the way of the program
88 that it will "exec", and that there is sufficient room for the brk. */
89
90#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3)
91
92#define ELF_CORE_COPY_REGS(_dest,_regs) \
93 memcpy((char *) &_dest, (char *) _regs, \
94 sizeof(struct pt_regs));
95
96/* This yields a mask that user programs can use to figure out what
97 instruction set this CPU supports. This could be done in user space,
98 but it's not easy, and we've already done it here. */
99
100#define ELF_HWCAP (boot_cpu_data.flags)
101
102/* This yields a string that ld.so will use to load implementation
103 specific libraries for optimization. This is more specific in
104 intent than poking at uname or /proc/cpuinfo.
105
106 For the moment, we have only optimizations for the Intel generations,
107 but that could change... */
108
109#define ELF_PLATFORM (utsname()->machine)
110
111#ifdef __SH5__
112#define ELF_PLAT_INIT(_r, load_addr) \
113 do { _r->regs[0]=0; _r->regs[1]=0; _r->regs[2]=0; _r->regs[3]=0; \
114 _r->regs[4]=0; _r->regs[5]=0; _r->regs[6]=0; _r->regs[7]=0; \
115 _r->regs[8]=0; _r->regs[9]=0; _r->regs[10]=0; _r->regs[11]=0; \
116 _r->regs[12]=0; _r->regs[13]=0; _r->regs[14]=0; _r->regs[15]=0; \
117 _r->regs[16]=0; _r->regs[17]=0; _r->regs[18]=0; _r->regs[19]=0; \
118 _r->regs[20]=0; _r->regs[21]=0; _r->regs[22]=0; _r->regs[23]=0; \
119 _r->regs[24]=0; _r->regs[25]=0; _r->regs[26]=0; _r->regs[27]=0; \
120 _r->regs[28]=0; _r->regs[29]=0; _r->regs[30]=0; _r->regs[31]=0; \
121 _r->regs[32]=0; _r->regs[33]=0; _r->regs[34]=0; _r->regs[35]=0; \
122 _r->regs[36]=0; _r->regs[37]=0; _r->regs[38]=0; _r->regs[39]=0; \
123 _r->regs[40]=0; _r->regs[41]=0; _r->regs[42]=0; _r->regs[43]=0; \
124 _r->regs[44]=0; _r->regs[45]=0; _r->regs[46]=0; _r->regs[47]=0; \
125 _r->regs[48]=0; _r->regs[49]=0; _r->regs[50]=0; _r->regs[51]=0; \
126 _r->regs[52]=0; _r->regs[53]=0; _r->regs[54]=0; _r->regs[55]=0; \
127 _r->regs[56]=0; _r->regs[57]=0; _r->regs[58]=0; _r->regs[59]=0; \
128 _r->regs[60]=0; _r->regs[61]=0; _r->regs[62]=0; \
129 _r->tregs[0]=0; _r->tregs[1]=0; _r->tregs[2]=0; _r->tregs[3]=0; \
130 _r->tregs[4]=0; _r->tregs[5]=0; _r->tregs[6]=0; _r->tregs[7]=0; \
131 _r->sr = SR_FD | SR_MMU; } while (0)
132#else
133#define ELF_PLAT_INIT(_r, load_addr) \
134 do { _r->regs[0]=0; _r->regs[1]=0; _r->regs[2]=0; _r->regs[3]=0; \
135 _r->regs[4]=0; _r->regs[5]=0; _r->regs[6]=0; _r->regs[7]=0; \
136 _r->regs[8]=0; _r->regs[9]=0; _r->regs[10]=0; _r->regs[11]=0; \
137 _r->regs[12]=0; _r->regs[13]=0; _r->regs[14]=0; \
138 _r->sr = SR_FD; } while (0)
139#endif
140
141#define SET_PERSONALITY(ex, ibcs2) set_personality(PER_LINUX_32BIT)
142struct task_struct;
143extern int dump_task_regs (struct task_struct *, elf_gregset_t *);
144extern int dump_task_fpu (struct task_struct *, elf_fpregset_t *);
145
146#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs)
147#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) dump_task_fpu(tsk, elf_fpregs)
148
149#ifdef CONFIG_VSYSCALL
150/* vDSO has arch_setup_additional_pages */
151#define ARCH_HAS_SETUP_ADDITIONAL_PAGES
152struct linux_binprm;
153extern int arch_setup_additional_pages(struct linux_binprm *bprm,
154 int executable_stack);
155
156extern unsigned int vdso_enabled;
157extern void __kernel_vsyscall;
158
159#define VDSO_BASE ((unsigned long)current->mm->context.vdso)
160#define VDSO_SYM(x) (VDSO_BASE + (unsigned long)(x))
161
162#define VSYSCALL_AUX_ENT \
163 if (vdso_enabled) \
164 NEW_AUX_ENT(AT_SYSINFO_EHDR, VDSO_BASE);
165#else
166#define VSYSCALL_AUX_ENT
167#endif /* CONFIG_VSYSCALL */
168
169#ifdef CONFIG_SH_FPU
170#define FPU_AUX_ENT NEW_AUX_ENT(AT_FPUCW, FPSCR_INIT)
171#else
172#define FPU_AUX_ENT
173#endif
174
175extern int l1i_cache_shape, l1d_cache_shape, l2_cache_shape;
176
177/* update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes */
178#define ARCH_DLINFO \
179do { \
180 /* Optional FPU initialization */ \
181 FPU_AUX_ENT; \
182 \
183 /* Optional vsyscall entry */ \
184 VSYSCALL_AUX_ENT; \
185 \
186 /* Cache desc */ \
187 NEW_AUX_ENT(AT_L1I_CACHESHAPE, l1i_cache_shape); \
188 NEW_AUX_ENT(AT_L1D_CACHESHAPE, l1d_cache_shape); \
189 NEW_AUX_ENT(AT_L2_CACHESHAPE, l2_cache_shape); \
190} while (0)
191
192#endif /* __KERNEL__ */
193#endif /* __ASM_SH_ELF_H */
diff --git a/include/asm-sh/emergency-restart.h b/include/asm-sh/emergency-restart.h
deleted file mode 100644
index 108d8c48e42..00000000000
--- a/include/asm-sh/emergency-restart.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _ASM_EMERGENCY_RESTART_H
2#define _ASM_EMERGENCY_RESTART_H
3
4#include <asm-generic/emergency-restart.h>
5
6#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-sh/entry-macros.S b/include/asm-sh/entry-macros.S
deleted file mode 100644
index 2dab0b8d945..00000000000
--- a/include/asm-sh/entry-macros.S
+++ /dev/null
@@ -1,33 +0,0 @@
1! entry.S macro define
2
3 .macro cli
4 stc sr, r0
5 or #0xf0, r0
6 ldc r0, sr
7 .endm
8
9 .macro sti
10 mov #0xf0, r11
11 extu.b r11, r11
12 not r11, r11
13 stc sr, r10
14 and r11, r10
15#ifdef CONFIG_CPU_HAS_SR_RB
16 stc k_g_imask, r11
17 or r11, r10
18#endif
19 ldc r10, sr
20 .endm
21
22 .macro get_current_thread_info, ti, tmp
23#ifdef CONFIG_CPU_HAS_SR_RB
24 stc r7_bank, \ti
25#else
26 mov #((THREAD_SIZE - 1) >> 10) ^ 0xff, \tmp
27 shll8 \tmp
28 shll2 \tmp
29 mov r15, \ti
30 and \tmp, \ti
31#endif
32 .endm
33
diff --git a/include/asm-sh/errno.h b/include/asm-sh/errno.h
deleted file mode 100644
index 51cf6f9cebb..00000000000
--- a/include/asm-sh/errno.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef __ASM_SH_ERRNO_H
2#define __ASM_SH_ERRNO_H
3
4#include <asm-generic/errno.h>
5
6#endif /* __ASM_SH_ERRNO_H */
diff --git a/include/asm-sh/fb.h b/include/asm-sh/fb.h
deleted file mode 100644
index d92e99cd8c8..00000000000
--- a/include/asm-sh/fb.h
+++ /dev/null
@@ -1,19 +0,0 @@
1#ifndef _ASM_FB_H_
2#define _ASM_FB_H_
3
4#include <linux/fb.h>
5#include <linux/fs.h>
6#include <asm/page.h>
7
8static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
9 unsigned long off)
10{
11 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
12}
13
14static inline int fb_is_primary_device(struct fb_info *info)
15{
16 return 0;
17}
18
19#endif /* _ASM_FB_H_ */
diff --git a/include/asm-sh/fcntl.h b/include/asm-sh/fcntl.h
deleted file mode 100644
index 46ab12db573..00000000000
--- a/include/asm-sh/fcntl.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/fcntl.h>
diff --git a/include/asm-sh/fixmap.h b/include/asm-sh/fixmap.h
deleted file mode 100644
index 721fcc4d5e9..00000000000
--- a/include/asm-sh/fixmap.h
+++ /dev/null
@@ -1,117 +0,0 @@
1/*
2 * fixmap.h: compile-time virtual memory allocation
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1998 Ingo Molnar
9 *
10 * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999
11 */
12
13#ifndef _ASM_FIXMAP_H
14#define _ASM_FIXMAP_H
15
16#include <linux/kernel.h>
17#include <asm/page.h>
18#ifdef CONFIG_HIGHMEM
19#include <linux/threads.h>
20#include <asm/kmap_types.h>
21#endif
22
23/*
24 * Here we define all the compile-time 'special' virtual
25 * addresses. The point is to have a constant address at
26 * compile time, but to set the physical address only
27 * in the boot process. We allocate these special addresses
28 * from the end of P3 backwards.
29 * Also this lets us do fail-safe vmalloc(), we
30 * can guarantee that these special addresses and
31 * vmalloc()-ed addresses never overlap.
32 *
33 * these 'compile-time allocated' memory buffers are
34 * fixed-size 4k pages. (or larger if used with an increment
35 * highger than 1) use fixmap_set(idx,phys) to associate
36 * physical memory with fixmap indices.
37 *
38 * TLB entries of such buffers will not be flushed across
39 * task switches.
40 */
41
42/*
43 * on UP currently we will have no trace of the fixmap mechanizm,
44 * no page table allocations, etc. This might change in the
45 * future, say framebuffers for the console driver(s) could be
46 * fix-mapped?
47 */
48enum fixed_addresses {
49#define FIX_N_COLOURS 16
50 FIX_CMAP_BEGIN,
51 FIX_CMAP_END = FIX_CMAP_BEGIN + FIX_N_COLOURS,
52 FIX_UNCACHED,
53#ifdef CONFIG_HIGHMEM
54 FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */
55 FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
56#endif
57 __end_of_fixed_addresses
58};
59
60extern void __set_fixmap(enum fixed_addresses idx,
61 unsigned long phys, pgprot_t flags);
62
63#define set_fixmap(idx, phys) \
64 __set_fixmap(idx, phys, PAGE_KERNEL)
65/*
66 * Some hardware wants to get fixmapped without caching.
67 */
68#define set_fixmap_nocache(idx, phys) \
69 __set_fixmap(idx, phys, PAGE_KERNEL_NOCACHE)
70/*
71 * used by vmalloc.c.
72 *
73 * Leave one empty page between vmalloc'ed areas and
74 * the start of the fixmap, and leave one page empty
75 * at the top of mem..
76 */
77#ifdef CONFIG_SUPERH32
78#define FIXADDR_TOP (P4SEG - PAGE_SIZE)
79#else
80#define FIXADDR_TOP (0xff000000 - PAGE_SIZE)
81#endif
82#define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT)
83#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
84
85#define __fix_to_virt(x) (FIXADDR_TOP - ((x) << PAGE_SHIFT))
86#define __virt_to_fix(x) ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
87
88extern void __this_fixmap_does_not_exist(void);
89
90/*
91 * 'index to address' translation. If anyone tries to use the idx
92 * directly without tranlation, we catch the bug with a NULL-deference
93 * kernel oops. Illegal ranges of incoming indices are caught too.
94 */
95static inline unsigned long fix_to_virt(const unsigned int idx)
96{
97 /*
98 * this branch gets completely eliminated after inlining,
99 * except when someone tries to use fixaddr indices in an
100 * illegal way. (such as mixing up address types or using
101 * out-of-range indices).
102 *
103 * If it doesn't get removed, the linker will complain
104 * loudly with a reasonably clear error message..
105 */
106 if (idx >= __end_of_fixed_addresses)
107 __this_fixmap_does_not_exist();
108
109 return __fix_to_virt(idx);
110}
111
112static inline unsigned long virt_to_fix(const unsigned long vaddr)
113{
114 BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
115 return __virt_to_fix(vaddr);
116}
117#endif
diff --git a/include/asm-sh/flat.h b/include/asm-sh/flat.h
deleted file mode 100644
index 0cc800299e0..00000000000
--- a/include/asm-sh/flat.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * include/asm-sh/flat.h
3 *
4 * uClinux flat-format executables
5 *
6 * Copyright (C) 2003 Paul Mundt
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive for
10 * more details.
11 */
12#ifndef __ASM_SH_FLAT_H
13#define __ASM_SH_FLAT_H
14
15#define flat_stack_align(sp) /* nothing needed */
16#define flat_argvp_envp_on_stack() 0
17#define flat_old_ram_flag(flags) (flags)
18#define flat_reloc_valid(reloc, size) ((reloc) <= (size))
19#define flat_get_addr_from_rp(rp, relval, flags, p) get_unaligned(rp)
20#define flat_put_addr_at_rp(rp, val, relval) put_unaligned(val,rp)
21#define flat_get_relocate_addr(rel) (rel)
22#define flat_set_persistent(relval, p) ({ (void)p; 0; })
23
24#endif /* __ASM_SH_FLAT_H */
diff --git a/include/asm-sh/fpu.h b/include/asm-sh/fpu.h
deleted file mode 100644
index 91462fea150..00000000000
--- a/include/asm-sh/fpu.h
+++ /dev/null
@@ -1,55 +0,0 @@
1#ifndef __ASM_SH_FPU_H
2#define __ASM_SH_FPU_H
3
4#ifndef __ASSEMBLY__
5#include <linux/preempt.h>
6#include <asm/ptrace.h>
7
8#ifdef CONFIG_SH_FPU
9static inline void release_fpu(struct pt_regs *regs)
10{
11 regs->sr |= SR_FD;
12}
13
14static inline void grab_fpu(struct pt_regs *regs)
15{
16 regs->sr &= ~SR_FD;
17}
18
19struct task_struct;
20
21extern void save_fpu(struct task_struct *__tsk, struct pt_regs *regs);
22#else
23
24#define release_fpu(regs) do { } while (0)
25#define grab_fpu(regs) do { } while (0)
26
27static inline void save_fpu(struct task_struct *tsk, struct pt_regs *regs)
28{
29 clear_tsk_thread_flag(tsk, TIF_USEDFPU);
30}
31#endif
32
33extern int do_fpu_inst(unsigned short, struct pt_regs *);
34
35static inline void unlazy_fpu(struct task_struct *tsk, struct pt_regs *regs)
36{
37 preempt_disable();
38 if (test_tsk_thread_flag(tsk, TIF_USEDFPU))
39 save_fpu(tsk, regs);
40 preempt_enable();
41}
42
43static inline void clear_fpu(struct task_struct *tsk, struct pt_regs *regs)
44{
45 preempt_disable();
46 if (test_tsk_thread_flag(tsk, TIF_USEDFPU)) {
47 clear_tsk_thread_flag(tsk, TIF_USEDFPU);
48 release_fpu(regs);
49 }
50 preempt_enable();
51}
52
53#endif /* __ASSEMBLY__ */
54
55#endif /* __ASM_SH_FPU_H */
diff --git a/include/asm-sh/freq.h b/include/asm-sh/freq.h
deleted file mode 100644
index 39c0e091cf5..00000000000
--- a/include/asm-sh/freq.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/*
2 * include/asm-sh/freq.h
3 *
4 * Copyright (C) 2002, 2003 Paul Mundt
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11#ifndef __ASM_SH_FREQ_H
12#define __ASM_SH_FREQ_H
13#ifdef __KERNEL__
14
15#include <asm/cpu/freq.h>
16
17#endif /* __KERNEL__ */
18#endif /* __ASM_SH_FREQ_H */
diff --git a/include/asm-sh/futex-irq.h b/include/asm-sh/futex-irq.h
deleted file mode 100644
index a9f16a7f9ae..00000000000
--- a/include/asm-sh/futex-irq.h
+++ /dev/null
@@ -1,111 +0,0 @@
1#ifndef __ASM_SH_FUTEX_IRQ_H
2#define __ASM_SH_FUTEX_IRQ_H
3
4#include <asm/system.h>
5
6static inline int atomic_futex_op_xchg_set(int oparg, int __user *uaddr,
7 int *oldval)
8{
9 unsigned long flags;
10 int ret;
11
12 local_irq_save(flags);
13
14 ret = get_user(*oldval, uaddr);
15 if (!ret)
16 ret = put_user(oparg, uaddr);
17
18 local_irq_restore(flags);
19
20 return ret;
21}
22
23static inline int atomic_futex_op_xchg_add(int oparg, int __user *uaddr,
24 int *oldval)
25{
26 unsigned long flags;
27 int ret;
28
29 local_irq_save(flags);
30
31 ret = get_user(*oldval, uaddr);
32 if (!ret)
33 ret = put_user(*oldval + oparg, uaddr);
34
35 local_irq_restore(flags);
36
37 return ret;
38}
39
40static inline int atomic_futex_op_xchg_or(int oparg, int __user *uaddr,
41 int *oldval)
42{
43 unsigned long flags;
44 int ret;
45
46 local_irq_save(flags);
47
48 ret = get_user(*oldval, uaddr);
49 if (!ret)
50 ret = put_user(*oldval | oparg, uaddr);
51
52 local_irq_restore(flags);
53
54 return ret;
55}
56
57static inline int atomic_futex_op_xchg_and(int oparg, int __user *uaddr,
58 int *oldval)
59{
60 unsigned long flags;
61 int ret;
62
63 local_irq_save(flags);
64
65 ret = get_user(*oldval, uaddr);
66 if (!ret)
67 ret = put_user(*oldval & oparg, uaddr);
68
69 local_irq_restore(flags);
70
71 return ret;
72}
73
74static inline int atomic_futex_op_xchg_xor(int oparg, int __user *uaddr,
75 int *oldval)
76{
77 unsigned long flags;
78 int ret;
79
80 local_irq_save(flags);
81
82 ret = get_user(*oldval, uaddr);
83 if (!ret)
84 ret = put_user(*oldval ^ oparg, uaddr);
85
86 local_irq_restore(flags);
87
88 return ret;
89}
90
91static inline int atomic_futex_op_cmpxchg_inatomic(int __user *uaddr,
92 int oldval, int newval)
93{
94 unsigned long flags;
95 int ret, prev = 0;
96
97 local_irq_save(flags);
98
99 ret = get_user(prev, uaddr);
100 if (!ret && oldval == prev)
101 ret = put_user(newval, uaddr);
102
103 local_irq_restore(flags);
104
105 if (ret)
106 return ret;
107
108 return prev;
109}
110
111#endif /* __ASM_SH_FUTEX_IRQ_H */
diff --git a/include/asm-sh/futex.h b/include/asm-sh/futex.h
deleted file mode 100644
index 68256ec5fa3..00000000000
--- a/include/asm-sh/futex.h
+++ /dev/null
@@ -1,77 +0,0 @@
1#ifndef __ASM_SH_FUTEX_H
2#define __ASM_SH_FUTEX_H
3
4#ifdef __KERNEL__
5
6#include <linux/futex.h>
7#include <linux/uaccess.h>
8#include <asm/errno.h>
9
10/* XXX: UP variants, fix for SH-4A and SMP.. */
11#include <asm/futex-irq.h>
12
13static inline int futex_atomic_op_inuser(int encoded_op, int __user *uaddr)
14{
15 int op = (encoded_op >> 28) & 7;
16 int cmp = (encoded_op >> 24) & 15;
17 int oparg = (encoded_op << 8) >> 20;
18 int cmparg = (encoded_op << 20) >> 20;
19 int oldval = 0, ret;
20
21 if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
22 oparg = 1 << oparg;
23
24 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
25 return -EFAULT;
26
27 pagefault_disable();
28
29 switch (op) {
30 case FUTEX_OP_SET:
31 ret = atomic_futex_op_xchg_set(oparg, uaddr, &oldval);
32 break;
33 case FUTEX_OP_ADD:
34 ret = atomic_futex_op_xchg_add(oparg, uaddr, &oldval);
35 break;
36 case FUTEX_OP_OR:
37 ret = atomic_futex_op_xchg_or(oparg, uaddr, &oldval);
38 break;
39 case FUTEX_OP_ANDN:
40 ret = atomic_futex_op_xchg_and(~oparg, uaddr, &oldval);
41 break;
42 case FUTEX_OP_XOR:
43 ret = atomic_futex_op_xchg_xor(oparg, uaddr, &oldval);
44 break;
45 default:
46 ret = -ENOSYS;
47 break;
48 }
49
50 pagefault_enable();
51
52 if (!ret) {
53 switch (cmp) {
54 case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
55 case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
56 case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
57 case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
58 case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
59 case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
60 default: ret = -ENOSYS;
61 }
62 }
63
64 return ret;
65}
66
67static inline int
68futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
69{
70 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
71 return -EFAULT;
72
73 return atomic_futex_op_cmpxchg_inatomic(uaddr, oldval, newval);
74}
75
76#endif /* __KERNEL__ */
77#endif /* __ASM_SH_FUTEX_H */
diff --git a/include/asm-sh/gpio.h b/include/asm-sh/gpio.h
deleted file mode 100644
index 9bb27e0f11a..00000000000
--- a/include/asm-sh/gpio.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * include/asm-sh/gpio.h
3 *
4 * Copyright (C) 2007 Markus Brunner, Mark Jonas
5 *
6 * Addresses for the Pin Function Controller
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#ifndef __ASM_SH_GPIO_H
13#define __ASM_SH_GPIO_H
14
15#if defined(CONFIG_CPU_SH3)
16#include <asm/cpu/gpio.h>
17#endif
18
19#endif /* __ASM_SH_GPIO_H */
diff --git a/include/asm-sh/hardirq.h b/include/asm-sh/hardirq.h
deleted file mode 100644
index 715ee237fc7..00000000000
--- a/include/asm-sh/hardirq.h
+++ /dev/null
@@ -1,16 +0,0 @@
1#ifndef __ASM_SH_HARDIRQ_H
2#define __ASM_SH_HARDIRQ_H
3
4#include <linux/threads.h>
5#include <linux/irq.h>
6
7/* entry.S is sensitive to the offsets of these fields */
8typedef struct {
9 unsigned int __softirq_pending;
10} ____cacheline_aligned irq_cpustat_t;
11
12#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
13
14extern void ack_bad_irq(unsigned int irq);
15
16#endif /* __ASM_SH_HARDIRQ_H */
diff --git a/include/asm-sh/hd64461.h b/include/asm-sh/hd64461.h
deleted file mode 100644
index 8c1353baf00..00000000000
--- a/include/asm-sh/hd64461.h
+++ /dev/null
@@ -1,250 +0,0 @@
1#ifndef __ASM_SH_HD64461
2#define __ASM_SH_HD64461
3/*
4 * Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
5 * Copyright (C) 2004 Paul Mundt
6 * Copyright (C) 2000 YAEGASHI Takeshi
7 *
8 * Hitachi HD64461 companion chip support
9 * (please note manual reference 0x10000000 = 0xb0000000)
10 */
11
12/* Constants for PCMCIA mappings */
13#define HD64461_PCC_WINDOW 0x01000000
14
15/* Area 6 - Slot 0 - memory and/or IO card */
16#define HD64461_PCC0_BASE (CONFIG_HD64461_IOBASE + 0x8000000)
17#define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) /* 0xb80000000 */
18#define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) /* 0xb90000000 */
19#define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) /* 0xba0000000 */
20
21/* Area 5 - Slot 1 - memory card only */
22#define HD64461_PCC1_BASE (CONFIG_HD64461_IOBASE + 0x4000000)
23#define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) /* 0xb4000000 */
24#define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) /* 0xb5000000 */
25
26/* Standby Control Register for HD64461 */
27#define HD64461_STBCR CONFIG_HD64461_IOBASE
28#define HD64461_STBCR_CKIO_STBY 0x2000
29#define HD64461_STBCR_SAFECKE_IST 0x1000
30#define HD64461_STBCR_SLCKE_IST 0x0800
31#define HD64461_STBCR_SAFECKE_OST 0x0400
32#define HD64461_STBCR_SLCKE_OST 0x0200
33#define HD64461_STBCR_SMIAST 0x0100
34#define HD64461_STBCR_SLCDST 0x0080
35#define HD64461_STBCR_SPC0ST 0x0040
36#define HD64461_STBCR_SPC1ST 0x0020
37#define HD64461_STBCR_SAFEST 0x0010
38#define HD64461_STBCR_STM0ST 0x0008
39#define HD64461_STBCR_STM1ST 0x0004
40#define HD64461_STBCR_SIRST 0x0002
41#define HD64461_STBCR_SURTST 0x0001
42
43/* System Configuration Register */
44#define HD64461_SYSCR (CONFIG_HD64461_IOBASE + 0x02)
45
46/* CPU Data Bus Control Register */
47#define HD64461_SCPUCR (CONFIG_HD64461_IOBASE + 0x04)
48
49/* Base Address Register */
50#define HD64461_LCDCBAR (CONFIG_HD64461_IOBASE + 0x1000)
51
52/* Line increment address */
53#define HD64461_LCDCLOR (CONFIG_HD64461_IOBASE + 0x1002)
54
55/* Controls LCD controller */
56#define HD64461_LCDCCR (CONFIG_HD64461_IOBASE + 0x1004)
57
58/* LCCDR control bits */
59#define HD64461_LCDCCR_STBACK 0x0400 /* Standby Back */
60#define HD64461_LCDCCR_STREQ 0x0100 /* Standby Request */
61#define HD64461_LCDCCR_MOFF 0x0080 /* Memory Off */
62#define HD64461_LCDCCR_REFSEL 0x0040 /* Refresh Select */
63#define HD64461_LCDCCR_EPON 0x0020 /* End Power On */
64#define HD64461_LCDCCR_SPON 0x0010 /* Start Power On */
65
66/* Controls LCD (1) */
67#define HD64461_LDR1 (CONFIG_HD64461_IOBASE + 0x1010)
68#define HD64461_LDR1_DON 0x01 /* Display On */
69#define HD64461_LDR1_DINV 0x80 /* Display Invert */
70
71/* Controls LCD (2) */
72#define HD64461_LDR2 (CONFIG_HD64461_IOBASE + 0x1012)
73#define HD64461_LDHNCR (CONFIG_HD64461_IOBASE + 0x1014) /* Number of horizontal characters */
74#define HD64461_LDHNSR (CONFIG_HD64461_IOBASE + 0x1016) /* Specify output start position + width of CL1 */
75#define HD64461_LDVNTR (CONFIG_HD64461_IOBASE + 0x1018) /* Specify total vertical lines */
76#define HD64461_LDVNDR (CONFIG_HD64461_IOBASE + 0x101a) /* specify number of display vertical lines */
77#define HD64461_LDVSPR (CONFIG_HD64461_IOBASE + 0x101c) /* specify vertical synchronization pos and AC nr */
78
79/* Controls LCD (3) */
80#define HD64461_LDR3 (CONFIG_HD64461_IOBASE + 0x101e)
81
82/* Palette Registers */
83#define HD64461_CPTWAR (CONFIG_HD64461_IOBASE + 0x1030) /* Color Palette Write Address Register */
84#define HD64461_CPTWDR (CONFIG_HD64461_IOBASE + 0x1032) /* Color Palette Write Data Register */
85#define HD64461_CPTRAR (CONFIG_HD64461_IOBASE + 0x1034) /* Color Palette Read Address Register */
86#define HD64461_CPTRDR (CONFIG_HD64461_IOBASE + 0x1036) /* Color Palette Read Data Register */
87
88#define HD64461_GRDOR (CONFIG_HD64461_IOBASE + 0x1040) /* Display Resolution Offset Register */
89#define HD64461_GRSCR (CONFIG_HD64461_IOBASE + 0x1042) /* Solid Color Register */
90#define HD64461_GRCFGR (CONFIG_HD64461_IOBASE + 0x1044) /* Accelerator Configuration Register */
91
92#define HD64461_GRCFGR_ACCSTATUS 0x10 /* Accelerator Status */
93#define HD64461_GRCFGR_ACCRESET 0x08 /* Accelerator Reset */
94#define HD64461_GRCFGR_ACCSTART_BITBLT 0x06 /* Accelerator Start BITBLT */
95#define HD64461_GRCFGR_ACCSTART_LINE 0x04 /* Accelerator Start Line Drawing */
96#define HD64461_GRCFGR_COLORDEPTH16 0x01 /* Sets Colordepth 16 for Accelerator */
97#define HD64461_GRCFGR_COLORDEPTH8 0x01 /* Sets Colordepth 8 for Accelerator */
98
99/* Line Drawing Registers */
100#define HD64461_LNSARH (CONFIG_HD64461_IOBASE + 0x1046) /* Line Start Address Register (H) */
101#define HD64461_LNSARL (CONFIG_HD64461_IOBASE + 0x1048) /* Line Start Address Register (L) */
102#define HD64461_LNAXLR (CONFIG_HD64461_IOBASE + 0x104a) /* Axis Pixel Length Register */
103#define HD64461_LNDGR (CONFIG_HD64461_IOBASE + 0x104c) /* Diagonal Register */
104#define HD64461_LNAXR (CONFIG_HD64461_IOBASE + 0x104e) /* Axial Register */
105#define HD64461_LNERTR (CONFIG_HD64461_IOBASE + 0x1050) /* Start Error Term Register */
106#define HD64461_LNMDR (CONFIG_HD64461_IOBASE + 0x1052) /* Line Mode Register */
107
108/* BitBLT Registers */
109#define HD64461_BBTSSARH (CONFIG_HD64461_IOBASE + 0x1054) /* Source Start Address Register (H) */
110#define HD64461_BBTSSARL (CONFIG_HD64461_IOBASE + 0x1056) /* Source Start Address Register (L) */
111#define HD64461_BBTDSARH (CONFIG_HD64461_IOBASE + 0x1058) /* Destination Start Address Register (H) */
112#define HD64461_BBTDSARL (CONFIG_HD64461_IOBASE + 0x105a) /* Destination Start Address Register (L) */
113#define HD64461_BBTDWR (CONFIG_HD64461_IOBASE + 0x105c) /* Destination Block Width Register */
114#define HD64461_BBTDHR (CONFIG_HD64461_IOBASE + 0x105e) /* Destination Block Height Register */
115#define HD64461_BBTPARH (CONFIG_HD64461_IOBASE + 0x1060) /* Pattern Start Address Register (H) */
116#define HD64461_BBTPARL (CONFIG_HD64461_IOBASE + 0x1062) /* Pattern Start Address Register (L) */
117#define HD64461_BBTMARH (CONFIG_HD64461_IOBASE + 0x1064) /* Mask Start Address Register (H) */
118#define HD64461_BBTMARL (CONFIG_HD64461_IOBASE + 0x1066) /* Mask Start Address Register (L) */
119#define HD64461_BBTROPR (CONFIG_HD64461_IOBASE + 0x1068) /* ROP Register */
120#define HD64461_BBTMDR (CONFIG_HD64461_IOBASE + 0x106a) /* BitBLT Mode Register */
121
122/* PC Card Controller Registers */
123/* Maps to Physical Area 6 */
124#define HD64461_PCC0ISR (CONFIG_HD64461_IOBASE + 0x2000) /* socket 0 interface status */
125#define HD64461_PCC0GCR (CONFIG_HD64461_IOBASE + 0x2002) /* socket 0 general control */
126#define HD64461_PCC0CSCR (CONFIG_HD64461_IOBASE + 0x2004) /* socket 0 card status change */
127#define HD64461_PCC0CSCIER (CONFIG_HD64461_IOBASE + 0x2006) /* socket 0 card status change interrupt enable */
128#define HD64461_PCC0SCR (CONFIG_HD64461_IOBASE + 0x2008) /* socket 0 software control */
129/* Maps to Physical Area 5 */
130#define HD64461_PCC1ISR (CONFIG_HD64461_IOBASE + 0x2010) /* socket 1 interface status */
131#define HD64461_PCC1GCR (CONFIG_HD64461_IOBASE + 0x2012) /* socket 1 general control */
132#define HD64461_PCC1CSCR (CONFIG_HD64461_IOBASE + 0x2014) /* socket 1 card status change */
133#define HD64461_PCC1CSCIER (CONFIG_HD64461_IOBASE + 0x2016) /* socket 1 card status change interrupt enable */
134#define HD64461_PCC1SCR (CONFIG_HD64461_IOBASE + 0x2018) /* socket 1 software control */
135
136/* PCC Interface Status Register */
137#define HD64461_PCCISR_READY 0x80 /* card ready */
138#define HD64461_PCCISR_MWP 0x40 /* card write-protected */
139#define HD64461_PCCISR_VS2 0x20 /* voltage select pin 2 */
140#define HD64461_PCCISR_VS1 0x10 /* voltage select pin 1 */
141#define HD64461_PCCISR_CD2 0x08 /* card detect 2 */
142#define HD64461_PCCISR_CD1 0x04 /* card detect 1 */
143#define HD64461_PCCISR_BVD2 0x02 /* battery 1 */
144#define HD64461_PCCISR_BVD1 0x01 /* battery 1 */
145
146#define HD64461_PCCISR_PCD_MASK 0x0c /* card detect */
147#define HD64461_PCCISR_BVD_MASK 0x03 /* battery voltage */
148#define HD64461_PCCISR_BVD_BATGOOD 0x03 /* battery good */
149#define HD64461_PCCISR_BVD_BATWARN 0x01 /* battery low warning */
150#define HD64461_PCCISR_BVD_BATDEAD1 0x02 /* battery dead */
151#define HD64461_PCCISR_BVD_BATDEAD2 0x00 /* battery dead */
152
153/* PCC General Control Register */
154#define HD64461_PCCGCR_DRVE 0x80 /* output drive */
155#define HD64461_PCCGCR_PCCR 0x40 /* PC card reset */
156#define HD64461_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */
157#define HD64461_PCCGCR_VCC0 0x10 /* voltage control pin VCC0SEL0 */
158#define HD64461_PCCGCR_PMMOD 0x08 /* memory mode */
159#define HD64461_PCCGCR_PA25 0x04 /* pin A25 */
160#define HD64461_PCCGCR_PA24 0x02 /* pin A24 */
161#define HD64461_PCCGCR_REG 0x01 /* pin PCC0REG# */
162
163/* PCC Card Status Change Register */
164#define HD64461_PCCCSCR_SCDI 0x80 /* sw card detect intr */
165#define HD64461_PCCCSCR_SRV1 0x40 /* reserved */
166#define HD64461_PCCCSCR_IREQ 0x20 /* IREQ intr req */
167#define HD64461_PCCCSCR_SC 0x10 /* STSCHG (status change) pin */
168#define HD64461_PCCCSCR_CDC 0x08 /* CD (card detect) change */
169#define HD64461_PCCCSCR_RC 0x04 /* READY change */
170#define HD64461_PCCCSCR_BW 0x02 /* battery warning change */
171#define HD64461_PCCCSCR_BD 0x01 /* battery dead change */
172
173/* PCC Card Status Change Interrupt Enable Register */
174#define HD64461_PCCCSCIER_CRE 0x80 /* change reset enable */
175#define HD64461_PCCCSCIER_IREQE_MASK 0x60 /* IREQ enable */
176#define HD64461_PCCCSCIER_IREQE_DISABLED 0x00 /* IREQ disabled */
177#define HD64461_PCCCSCIER_IREQE_LEVEL 0x20 /* IREQ level-triggered */
178#define HD64461_PCCCSCIER_IREQE_FALLING 0x40 /* IREQ falling-edge-trig */
179#define HD64461_PCCCSCIER_IREQE_RISING 0x60 /* IREQ rising-edge-trig */
180
181#define HD64461_PCCCSCIER_SCE 0x10 /* status change enable */
182#define HD64461_PCCCSCIER_CDE 0x08 /* card detect change enable */
183#define HD64461_PCCCSCIER_RE 0x04 /* ready change enable */
184#define HD64461_PCCCSCIER_BWE 0x02 /* battery warn change enable */
185#define HD64461_PCCCSCIER_BDE 0x01 /* battery dead change enable*/
186
187/* PCC Software Control Register */
188#define HD64461_PCCSCR_VCC1 0x02 /* voltage control pin 1 */
189#define HD64461_PCCSCR_SWP 0x01 /* write protect */
190
191/* PCC0 Output Pins Control Register */
192#define HD64461_P0OCR (CONFIG_HD64461_IOBASE + 0x202a)
193
194/* PCC1 Output Pins Control Register */
195#define HD64461_P1OCR (CONFIG_HD64461_IOBASE + 0x202c)
196
197/* PC Card General Control Register */
198#define HD64461_PGCR (CONFIG_HD64461_IOBASE + 0x202e)
199
200/* Port Control Registers */
201#define HD64461_GPACR (CONFIG_HD64461_IOBASE + 0x4000) /* Port A - Handles IRDA/TIMER */
202#define HD64461_GPBCR (CONFIG_HD64461_IOBASE + 0x4002) /* Port B - Handles UART */
203#define HD64461_GPCCR (CONFIG_HD64461_IOBASE + 0x4004) /* Port C - Handles PCMCIA 1 */
204#define HD64461_GPDCR (CONFIG_HD64461_IOBASE + 0x4006) /* Port D - Handles PCMCIA 1 */
205
206/* Port Control Data Registers */
207#define HD64461_GPADR (CONFIG_HD64461_IOBASE + 0x4010) /* A */
208#define HD64461_GPBDR (CONFIG_HD64461_IOBASE + 0x4012) /* B */
209#define HD64461_GPCDR (CONFIG_HD64461_IOBASE + 0x4014) /* C */
210#define HD64461_GPDDR (CONFIG_HD64461_IOBASE + 0x4016) /* D */
211
212/* Interrupt Control Registers */
213#define HD64461_GPAICR (CONFIG_HD64461_IOBASE + 0x4020) /* A */
214#define HD64461_GPBICR (CONFIG_HD64461_IOBASE + 0x4022) /* B */
215#define HD64461_GPCICR (CONFIG_HD64461_IOBASE + 0x4024) /* C */
216#define HD64461_GPDICR (CONFIG_HD64461_IOBASE + 0x4026) /* D */
217
218/* Interrupt Status Registers */
219#define HD64461_GPAISR (CONFIG_HD64461_IOBASE + 0x4040) /* A */
220#define HD64461_GPBISR (CONFIG_HD64461_IOBASE + 0x4042) /* B */
221#define HD64461_GPCISR (CONFIG_HD64461_IOBASE + 0x4044) /* C */
222#define HD64461_GPDISR (CONFIG_HD64461_IOBASE + 0x4046) /* D */
223
224/* Interrupt Request Register & Interrupt Mask Register */
225#define HD64461_NIRR (CONFIG_HD64461_IOBASE + 0x5000)
226#define HD64461_NIMR (CONFIG_HD64461_IOBASE + 0x5002)
227
228#define HD64461_IRQBASE OFFCHIP_IRQ_BASE
229#define OFFCHIP_IRQ_BASE 64
230#define HD64461_IRQ_NUM 16
231
232#define HD64461_IRQ_UART (HD64461_IRQBASE+5)
233#define HD64461_IRQ_IRDA (HD64461_IRQBASE+6)
234#define HD64461_IRQ_TMU1 (HD64461_IRQBASE+9)
235#define HD64461_IRQ_TMU0 (HD64461_IRQBASE+10)
236#define HD64461_IRQ_GPIO (HD64461_IRQBASE+11)
237#define HD64461_IRQ_AFE (HD64461_IRQBASE+12)
238#define HD64461_IRQ_PCC1 (HD64461_IRQBASE+13)
239#define HD64461_IRQ_PCC0 (HD64461_IRQBASE+14)
240
241#define __IO_PREFIX hd64461
242#include <asm/io_generic.h>
243
244/* arch/sh/cchips/hd6446x/hd64461/setup.c */
245int hd64461_irq_demux(int irq);
246void hd64461_register_irq_demux(int irq,
247 int (*demux) (int irq, void *dev), void *dev);
248void hd64461_unregister_irq_demux(int irq);
249
250#endif
diff --git a/include/asm-sh/hd64465/gpio.h b/include/asm-sh/hd64465/gpio.h
deleted file mode 100644
index a3cdca2713d..00000000000
--- a/include/asm-sh/hd64465/gpio.h
+++ /dev/null
@@ -1,46 +0,0 @@
1#ifndef _ASM_SH_HD64465_GPIO_
2#define _ASM_SH_HD64465_GPIO_ 1
3/*
4 * $Id: gpio.h,v 1.3 2003/05/04 19:30:14 lethal Exp $
5 *
6 * Hitachi HD64465 companion chip: General Purpose IO pins support.
7 * This layer enables other device drivers to configure GPIO
8 * pins, get and set their values, and register an interrupt
9 * routine for when input pins change in hardware.
10 *
11 * by Greg Banks <gbanks@pocketpenguins.com>
12 * (c) 2000 PocketPenguins Inc.
13 */
14#include <asm/hd64465.h>
15
16/* Macro to construct a portpin number (used in all
17 * subsequent functions) from a port letter and a pin
18 * number, e.g. HD64465_GPIO_PORTPIN('A', 5).
19 */
20#define HD64465_GPIO_PORTPIN(port,pin) (((port)-'A')<<3|(pin))
21
22/* Pin configuration constants for _configure() */
23#define HD64465_GPIO_FUNCTION2 0 /* use the pin's *other* function */
24#define HD64465_GPIO_OUT 1 /* output */
25#define HD64465_GPIO_IN_PULLUP 2 /* input, pull-up MOS on */
26#define HD64465_GPIO_IN 3 /* input */
27
28/* Configure a pin's direction */
29extern void hd64465_gpio_configure(int portpin, int direction);
30
31/* Get, set value */
32extern void hd64465_gpio_set_pin(int portpin, unsigned int value);
33extern unsigned int hd64465_gpio_get_pin(int portpin);
34extern void hd64465_gpio_set_port(int port, unsigned int value);
35extern unsigned int hd64465_gpio_get_port(int port);
36
37/* mode constants for _register_irq() */
38#define HD64465_GPIO_FALLING 0
39#define HD64465_GPIO_RISING 1
40
41/* Interrupt on external value change */
42extern void hd64465_gpio_register_irq(int portpin, int mode,
43 void (*handler)(int portpin, void *dev), void *dev);
44extern void hd64465_gpio_unregister_irq(int portpin);
45
46#endif /* _ASM_SH_HD64465_GPIO_ */
diff --git a/include/asm-sh/hd64465/hd64465.h b/include/asm-sh/hd64465/hd64465.h
deleted file mode 100644
index cfd0e803d2a..00000000000
--- a/include/asm-sh/hd64465/hd64465.h
+++ /dev/null
@@ -1,256 +0,0 @@
1#ifndef _ASM_SH_HD64465_
2#define _ASM_SH_HD64465_ 1
3/*
4 * $Id: hd64465.h,v 1.3 2003/05/04 19:30:15 lethal Exp $
5 *
6 * Hitachi HD64465 companion chip support
7 *
8 * by Greg Banks <gbanks@pocketpenguins.com>
9 * (c) 2000 PocketPenguins Inc.
10 *
11 * Derived from <asm/hd64461.h> which bore the message:
12 * Copyright (C) 2000 YAEGASHI Takeshi
13 */
14#include <asm/io.h>
15#include <asm/irq.h>
16
17/*
18 * Note that registers are defined here as virtual port numbers,
19 * which have no meaning except to get translated by hd64465_isa_port2addr()
20 * to an address in the range 0xb0000000-0xb3ffffff. Note that
21 * this translation happens to consist of adding the lower 16 bits
22 * of the virtual port number to 0xb0000000. Note also that the manual
23 * shows addresses as absolute physical addresses starting at 0x10000000,
24 * so e.g. the NIRR register is listed as 0x15000 here, 0x10005000 in the
25 * manual, and accessed using address 0xb0005000 - Greg.
26 */
27
28/* System registers */
29#define HD64465_REG_SRR 0x1000c /* System Revision Register */
30#define HD64465_REG_SDID 0x10010 /* System Device ID Reg */
31#define HD64465_SDID 0x8122 /* 64465 device ID */
32
33/* Power Management registers */
34#define HD64465_REG_SMSCR 0x10000 /* System Module Standby Control Reg */
35#define HD64465_SMSCR_PS2ST 0x4000 /* PS/2 Standby */
36#define HD64465_SMSCR_ADCST 0x1000 /* ADC Standby */
37#define HD64465_SMSCR_UARTST 0x0800 /* UART Standby */
38#define HD64465_SMSCR_SCDIST 0x0200 /* Serial Codec Standby */
39#define HD64465_SMSCR_PPST 0x0100 /* Parallel Port Standby */
40#define HD64465_SMSCR_PC0ST 0x0040 /* PCMCIA0 Standby */
41#define HD64465_SMSCR_PC1ST 0x0020 /* PCMCIA1 Standby */
42#define HD64465_SMSCR_AFEST 0x0010 /* AFE Standby */
43#define HD64465_SMSCR_TM0ST 0x0008 /* Timer0 Standby */
44#define HD64465_SMSCR_TM1ST 0x0004 /* Timer1 Standby */
45#define HD64465_SMSCR_IRDAST 0x0002 /* IRDA Standby */
46#define HD64465_SMSCR_KBCST 0x0001 /* Keyboard Controller Standby */
47
48/* Interrupt Controller registers */
49#define HD64465_REG_NIRR 0x15000 /* Interrupt Request Register */
50#define HD64465_REG_NIMR 0x15002 /* Interrupt Mask Register */
51#define HD64465_REG_NITR 0x15004 /* Interrupt Trigger Mode Register */
52
53/* Timer registers */
54#define HD64465_REG_TCVR1 0x16000 /* Timer 1 constant value register */
55#define HD64465_REG_TCVR0 0x16002 /* Timer 0 constant value register */
56#define HD64465_REG_TRVR1 0x16004 /* Timer 1 read value register */
57#define HD64465_REG_TRVR0 0x16006 /* Timer 0 read value register */
58#define HD64465_REG_TCR1 0x16008 /* Timer 1 control register */
59#define HD64465_REG_TCR0 0x1600A /* Timer 0 control register */
60#define HD64465_TCR_EADT 0x10 /* Enable ADTRIG# signal */
61#define HD64465_TCR_ETMO 0x08 /* Enable TMO signal */
62#define HD64465_TCR_PST_MASK 0x06 /* Clock Prescale */
63#define HD64465_TCR_PST_1 0x06 /* 1:1 */
64#define HD64465_TCR_PST_4 0x04 /* 1:4 */
65#define HD64465_TCR_PST_8 0x02 /* 1:8 */
66#define HD64465_TCR_PST_16 0x00 /* 1:16 */
67#define HD64465_TCR_TSTP 0x01 /* Start/Stop timer */
68#define HD64465_REG_TIRR 0x1600C /* Timer interrupt request register */
69#define HD64465_REG_TIDR 0x1600E /* Timer interrupt disable register */
70#define HD64465_REG_PWM1CS 0x16010 /* PWM 1 clock scale register */
71#define HD64465_REG_PWM1LPC 0x16012 /* PWM 1 low pulse width counter register */
72#define HD64465_REG_PWM1HPC 0x16014 /* PWM 1 high pulse width counter register */
73#define HD64465_REG_PWM0CS 0x16018 /* PWM 0 clock scale register */
74#define HD64465_REG_PWM0LPC 0x1601A /* PWM 0 low pulse width counter register */
75#define HD64465_REG_PWM0HPC 0x1601C /* PWM 0 high pulse width counter register */
76
77/* Analog/Digital Converter registers */
78#define HD64465_REG_ADDRA 0x1E000 /* A/D data register A */
79#define HD64465_REG_ADDRB 0x1E002 /* A/D data register B */
80#define HD64465_REG_ADDRC 0x1E004 /* A/D data register C */
81#define HD64465_REG_ADDRD 0x1E006 /* A/D data register D */
82#define HD64465_REG_ADCSR 0x1E008 /* A/D control/status register */
83#define HD64465_ADCSR_ADF 0x80 /* A/D End Flag */
84#define HD64465_ADCSR_ADST 0x40 /* A/D Start Flag */
85#define HD64465_ADCSR_ADIS 0x20 /* A/D Interrupt Status */
86#define HD64465_ADCSR_TRGE 0x10 /* A/D Trigger Enable */
87#define HD64465_ADCSR_ADIE 0x08 /* A/D Interrupt Enable */
88#define HD64465_ADCSR_SCAN 0x04 /* A/D Scan Mode */
89#define HD64465_ADCSR_CH_MASK 0x03 /* A/D Channel */
90#define HD64465_REG_ADCALCR 0x1E00A /* A/D calibration sample control */
91#define HD64465_REG_ADCAL 0x1E00C /* A/D calibration data register */
92
93
94/* General Purpose I/O ports registers */
95#define HD64465_REG_GPACR 0x14000 /* Port A Control Register */
96#define HD64465_REG_GPBCR 0x14002 /* Port B Control Register */
97#define HD64465_REG_GPCCR 0x14004 /* Port C Control Register */
98#define HD64465_REG_GPDCR 0x14006 /* Port D Control Register */
99#define HD64465_REG_GPECR 0x14008 /* Port E Control Register */
100#define HD64465_REG_GPADR 0x14010 /* Port A Data Register */
101#define HD64465_REG_GPBDR 0x14012 /* Port B Data Register */
102#define HD64465_REG_GPCDR 0x14014 /* Port C Data Register */
103#define HD64465_REG_GPDDR 0x14016 /* Port D Data Register */
104#define HD64465_REG_GPEDR 0x14018 /* Port E Data Register */
105#define HD64465_REG_GPAICR 0x14020 /* Port A Interrupt Control Register */
106#define HD64465_REG_GPBICR 0x14022 /* Port B Interrupt Control Register */
107#define HD64465_REG_GPCICR 0x14024 /* Port C Interrupt Control Register */
108#define HD64465_REG_GPDICR 0x14026 /* Port D Interrupt Control Register */
109#define HD64465_REG_GPEICR 0x14028 /* Port E Interrupt Control Register */
110#define HD64465_REG_GPAISR 0x14040 /* Port A Interrupt Status Register */
111#define HD64465_REG_GPBISR 0x14042 /* Port B Interrupt Status Register */
112#define HD64465_REG_GPCISR 0x14044 /* Port C Interrupt Status Register */
113#define HD64465_REG_GPDISR 0x14046 /* Port D Interrupt Status Register */
114#define HD64465_REG_GPEISR 0x14048 /* Port E Interrupt Status Register */
115
116/* PCMCIA bridge interface */
117#define HD64465_REG_PCC0ISR 0x12000 /* socket 0 interface status */
118#define HD64465_PCCISR_PREADY 0x80 /* mem card ready / io card IREQ */
119#define HD64465_PCCISR_PIREQ 0x80
120#define HD64465_PCCISR_PMWP 0x40 /* mem card write-protected */
121#define HD64465_PCCISR_PVS2 0x20 /* voltage select pin 2 */
122#define HD64465_PCCISR_PVS1 0x10 /* voltage select pin 1 */
123#define HD64465_PCCISR_PCD_MASK 0x0c /* card detect */
124#define HD64465_PCCISR_PBVD_MASK 0x03 /* battery voltage */
125#define HD64465_PCCISR_PBVD_BATGOOD 0x03 /* battery good */
126#define HD64465_PCCISR_PBVD_BATWARN 0x01 /* battery low warning */
127#define HD64465_PCCISR_PBVD_BATDEAD1 0x02 /* battery dead */
128#define HD64465_PCCISR_PBVD_BATDEAD2 0x00 /* battery dead */
129#define HD64465_REG_PCC0GCR 0x12002 /* socket 0 general control */
130#define HD64465_PCCGCR_PDRV 0x80 /* output drive */
131#define HD64465_PCCGCR_PCCR 0x40 /* PC card reset */
132#define HD64465_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */
133#define HD64465_PCCGCR_PVCC0 0x10 /* voltage control pin VCC0SEL0 */
134#define HD64465_PCCGCR_PMMOD 0x08 /* memory mode */
135#define HD64465_PCCGCR_PPA25 0x04 /* pin A25 */
136#define HD64465_PCCGCR_PPA24 0x02 /* pin A24 */
137#define HD64465_PCCGCR_PREG 0x01 /* ping PCC0REG# */
138#define HD64465_REG_PCC0CSCR 0x12004 /* socket 0 card status change */
139#define HD64465_PCCCSCR_PSCDI 0x80 /* sw card detect intr */
140#define HD64465_PCCCSCR_PSWSEL 0x40 /* power select */
141#define HD64465_PCCCSCR_PIREQ 0x20 /* IREQ intr req */
142#define HD64465_PCCCSCR_PSC 0x10 /* STSCHG (status change) pin */
143#define HD64465_PCCCSCR_PCDC 0x08 /* CD (card detect) change */
144#define HD64465_PCCCSCR_PRC 0x04 /* ready change */
145#define HD64465_PCCCSCR_PBW 0x02 /* battery warning change */
146#define HD64465_PCCCSCR_PBD 0x01 /* battery dead change */
147#define HD64465_REG_PCC0CSCIER 0x12006 /* socket 0 card status change interrupt enable */
148#define HD64465_PCCCSCIER_PCRE 0x80 /* change reset enable */
149#define HD64465_PCCCSCIER_PIREQE_MASK 0x60 /* IREQ enable */
150#define HD64465_PCCCSCIER_PIREQE_DISABLED 0x00 /* IREQ disabled */
151#define HD64465_PCCCSCIER_PIREQE_LEVEL 0x20 /* IREQ level-triggered */
152#define HD64465_PCCCSCIER_PIREQE_FALLING 0x40 /* IREQ falling-edge-trig */
153#define HD64465_PCCCSCIER_PIREQE_RISING 0x60 /* IREQ rising-edge-trig */
154#define HD64465_PCCCSCIER_PSCE 0x10 /* status change enable */
155#define HD64465_PCCCSCIER_PCDE 0x08 /* card detect change enable */
156#define HD64465_PCCCSCIER_PRE 0x04 /* ready change enable */
157#define HD64465_PCCCSCIER_PBWE 0x02 /* battery warn change enable */
158#define HD64465_PCCCSCIER_PBDE 0x01 /* battery dead change enable*/
159#define HD64465_REG_PCC0SCR 0x12008 /* socket 0 software control */
160#define HD64465_PCCSCR_SHDN 0x10 /* TPS2206 SHutDowN pin */
161#define HD64465_PCCSCR_SWP 0x01 /* write protect */
162#define HD64465_REG_PCCPSR 0x1200A /* serial power switch control */
163#define HD64465_REG_PCC1ISR 0x12010 /* socket 1 interface status */
164#define HD64465_REG_PCC1GCR 0x12012 /* socket 1 general control */
165#define HD64465_REG_PCC1CSCR 0x12014 /* socket 1 card status change */
166#define HD64465_REG_PCC1CSCIER 0x12016 /* socket 1 card status change interrupt enable */
167#define HD64465_REG_PCC1SCR 0x12018 /* socket 1 software control */
168
169
170/* PS/2 Keyboard and mouse controller -- *not* register compatible */
171#define HD64465_REG_KBCSR 0x1dc00 /* Keyboard Control/Status reg */
172#define HD64465_KBCSR_KBCIE 0x8000 /* KBCK Input Enable */
173#define HD64465_KBCSR_KBCOE 0x4000 /* KBCK Output Enable */
174#define HD64465_KBCSR_KBDOE 0x2000 /* KB DATA Output Enable */
175#define HD64465_KBCSR_KBCD 0x1000 /* KBCK Driven */
176#define HD64465_KBCSR_KBDD 0x0800 /* KB DATA Driven */
177#define HD64465_KBCSR_KBCS 0x0400 /* KBCK pin Status */
178#define HD64465_KBCSR_KBDS 0x0200 /* KB DATA pin Status */
179#define HD64465_KBCSR_KBDP 0x0100 /* KB DATA Parity bit */
180#define HD64465_KBCSR_KBD_MASK 0x00ff /* KD DATA shift reg */
181#define HD64465_REG_KBISR 0x1dc04 /* Keyboard Interrupt Status reg */
182#define HD64465_KBISR_KBRDF 0x0001 /* KB Received Data Full */
183#define HD64465_REG_MSCSR 0x1dc10 /* Mouse Control/Status reg */
184#define HD64465_REG_MSISR 0x1dc14 /* Mouse Interrupt Status reg */
185
186
187/*
188 * Logical address at which the HD64465 is mapped. Note that this
189 * should always be in the P2 segment (uncached and untranslated).
190 */
191#ifndef CONFIG_HD64465_IOBASE
192#define CONFIG_HD64465_IOBASE 0xb0000000
193#endif
194/*
195 * The HD64465 multiplexes all its modules' interrupts onto
196 * this single interrupt.
197 */
198#ifndef CONFIG_HD64465_IRQ
199#define CONFIG_HD64465_IRQ 5
200#endif
201
202
203#define _HD64465_IO_MASK 0xf8000000
204#define is_hd64465_addr(addr) \
205 ((addr & _HD64465_IO_MASK) == (CONFIG_HD64465_IOBASE & _HD64465_IO_MASK))
206
207/*
208 * A range of 16 virtual interrupts generated by
209 * demuxing the HD64465 muxed interrupt.
210 */
211#define HD64465_IRQ_BASE OFFCHIP_IRQ_BASE
212#define HD64465_IRQ_NUM 16
213#define HD64465_IRQ_ADC (HD64465_IRQ_BASE+0)
214#define HD64465_IRQ_USB (HD64465_IRQ_BASE+1)
215#define HD64465_IRQ_SCDI (HD64465_IRQ_BASE+2)
216#define HD64465_IRQ_PARALLEL (HD64465_IRQ_BASE+3)
217/* bit 4 is reserved */
218#define HD64465_IRQ_UART (HD64465_IRQ_BASE+5)
219#define HD64465_IRQ_IRDA (HD64465_IRQ_BASE+6)
220#define HD64465_IRQ_PS2MOUSE (HD64465_IRQ_BASE+7)
221#define HD64465_IRQ_KBC (HD64465_IRQ_BASE+8)
222#define HD64465_IRQ_TIMER1 (HD64465_IRQ_BASE+9)
223#define HD64465_IRQ_TIMER0 (HD64465_IRQ_BASE+10)
224#define HD64465_IRQ_GPIO (HD64465_IRQ_BASE+11)
225#define HD64465_IRQ_AFE (HD64465_IRQ_BASE+12)
226#define HD64465_IRQ_PCMCIA1 (HD64465_IRQ_BASE+13)
227#define HD64465_IRQ_PCMCIA0 (HD64465_IRQ_BASE+14)
228#define HD64465_IRQ_PS2KBD (HD64465_IRQ_BASE+15)
229
230/* Constants for PCMCIA mappings */
231#define HD64465_PCC_WINDOW 0x01000000
232
233#define HD64465_PCC0_BASE 0xb8000000 /* area 6 */
234#define HD64465_PCC0_ATTR (HD64465_PCC0_BASE)
235#define HD64465_PCC0_COMM (HD64465_PCC0_BASE+HD64465_PCC_WINDOW)
236#define HD64465_PCC0_IO (HD64465_PCC0_BASE+2*HD64465_PCC_WINDOW)
237
238#define HD64465_PCC1_BASE 0xb4000000 /* area 5 */
239#define HD64465_PCC1_ATTR (HD64465_PCC1_BASE)
240#define HD64465_PCC1_COMM (HD64465_PCC1_BASE+HD64465_PCC_WINDOW)
241#define HD64465_PCC1_IO (HD64465_PCC1_BASE+2*HD64465_PCC_WINDOW)
242
243/*
244 * Base of USB controller interface (as memory)
245 */
246#define HD64465_USB_BASE (CONFIG_HD64465_IOBASE+0xb000)
247#define HD64465_USB_LEN 0x1000
248/*
249 * Base of embedded SRAM, used for USB controller.
250 */
251#define HD64465_SRAM_BASE (CONFIG_HD64465_IOBASE+0x9000)
252#define HD64465_SRAM_LEN 0x1000
253
254
255
256#endif /* _ASM_SH_HD64465_ */
diff --git a/include/asm-sh/hd64465/io.h b/include/asm-sh/hd64465/io.h
deleted file mode 100644
index 139f1472e5b..00000000000
--- a/include/asm-sh/hd64465/io.h
+++ /dev/null
@@ -1,44 +0,0 @@
1/*
2 * include/asm-sh/hd64465/io.h
3 *
4 * By Greg Banks <gbanks@pocketpenguins.com>
5 * (c) 2000 PocketPenguins Inc.
6 *
7 * Derived from io_hd64461.h, which bore the message:
8 * Copyright 2000 Stuart Menefy (stuart.menefy@st.com)
9 *
10 * May be copied or modified under the terms of the GNU General Public
11 * License. See linux/COPYING for more information.
12 *
13 * IO functions for an HD64465 "Windows CE Intelligent Peripheral Controller".
14 */
15
16#ifndef _ASM_SH_IO_HD64465_H
17#define _ASM_SH_IO_HD64465_H
18
19extern unsigned char hd64465_inb(unsigned long port);
20extern unsigned short hd64465_inw(unsigned long port);
21extern unsigned int hd64465_inl(unsigned long port);
22
23extern void hd64465_outb(unsigned char value, unsigned long port);
24extern void hd64465_outw(unsigned short value, unsigned long port);
25extern void hd64465_outl(unsigned int value, unsigned long port);
26
27extern unsigned char hd64465_inb_p(unsigned long port);
28extern void hd64465_outb_p(unsigned char value, unsigned long port);
29
30extern unsigned long hd64465_isa_port2addr(unsigned long offset);
31extern int hd64465_irq_demux(int irq);
32/* Provision for generic secondary demux step -- used by PCMCIA code */
33extern void hd64465_register_irq_demux(int irq,
34 int (*demux)(int irq, void *dev), void *dev);
35extern void hd64465_unregister_irq_demux(int irq);
36/* Set this variable to 1 to see port traffic */
37extern int hd64465_io_debug;
38/* Map a range of ports to a range of kernel virtual memory.
39 */
40extern void hd64465_port_map(unsigned short baseport, unsigned int nports,
41 unsigned long addr, unsigned char shift);
42extern void hd64465_port_unmap(unsigned short baseport, unsigned int nports);
43
44#endif /* _ASM_SH_IO_HD64465_H */
diff --git a/include/asm-sh/heartbeat.h b/include/asm-sh/heartbeat.h
deleted file mode 100644
index 724a43ed245..00000000000
--- a/include/asm-sh/heartbeat.h
+++ /dev/null
@@ -1,17 +0,0 @@
1#ifndef __ASM_SH_HEARTBEAT_H
2#define __ASM_SH_HEARTBEAT_H
3
4#include <linux/timer.h>
5
6#define HEARTBEAT_INVERTED (1 << 0)
7
8struct heartbeat_data {
9 void __iomem *base;
10 unsigned char *bit_pos;
11 unsigned int nr_bits;
12 struct timer_list timer;
13 unsigned int regsize;
14 unsigned long flags;
15};
16
17#endif /* __ASM_SH_HEARTBEAT_H */
diff --git a/include/asm-sh/hp6xx.h b/include/asm-sh/hp6xx.h
deleted file mode 100644
index 0d4165a32dc..00000000000
--- a/include/asm-sh/hp6xx.h
+++ /dev/null
@@ -1,58 +0,0 @@
1#ifndef __ASM_SH_HP6XX_H
2#define __ASM_SH_HP6XX_H
3
4/*
5 * Copyright (C) 2003, 2004, 2005 Andriy Skulysh
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 *
11 */
12
13#define HP680_BTN_IRQ 32 /* IRQ0_IRQ */
14#define HP680_TS_IRQ 35 /* IRQ3_IRQ */
15#define HP680_HD64461_IRQ 36 /* IRQ4_IRQ */
16
17#define DAC_LCD_BRIGHTNESS 0
18#define DAC_SPEAKER_VOLUME 1
19
20#define PGDR_OPENED 0x01
21#define PGDR_MAIN_BATTERY_OUT 0x04
22#define PGDR_PLAY_BUTTON 0x08
23#define PGDR_REWIND_BUTTON 0x10
24#define PGDR_RECORD_BUTTON 0x20
25
26#define PHDR_TS_PEN_DOWN 0x08
27
28#define PJDR_LED_BLINK 0x02
29
30#define PKDR_LED_GREEN 0x10
31
32#define SCPDR_TS_SCAN_ENABLE 0x20
33#define SCPDR_TS_SCAN_Y 0x02
34#define SCPDR_TS_SCAN_X 0x01
35
36#define SCPCR_TS_ENABLE 0x405
37#define SCPCR_TS_MASK 0xc0f
38
39#define ADC_CHANNEL_TS_Y 1
40#define ADC_CHANNEL_TS_X 2
41#define ADC_CHANNEL_BATTERY 3
42#define ADC_CHANNEL_BACKUP 4
43#define ADC_CHANNEL_CHARGE 5
44
45#define HD64461_GPADR_SPEAKER 0x01
46#define HD64461_GPADR_PCMCIA0 (0x02|0x08)
47
48#define HD64461_GPBDR_LCDOFF 0x01
49#define HD64461_GPBDR_LCD_CONTRAST_MASK 0x78
50#define HD64461_GPBDR_LED_RED 0x80
51
52#include <asm/hd64461.h>
53#include <asm/io.h>
54
55#define PJDR 0xa4000130
56#define PKDR 0xa4000132
57
58#endif /* __ASM_SH_HP6XX_H */
diff --git a/include/asm-sh/hugetlb.h b/include/asm-sh/hugetlb.h
deleted file mode 100644
index 967068fb79a..00000000000
--- a/include/asm-sh/hugetlb.h
+++ /dev/null
@@ -1,92 +0,0 @@
1#ifndef _ASM_SH_HUGETLB_H
2#define _ASM_SH_HUGETLB_H
3
4#include <asm/page.h>
5
6
7static inline int is_hugepage_only_range(struct mm_struct *mm,
8 unsigned long addr,
9 unsigned long len) {
10 return 0;
11}
12
13/*
14 * If the arch doesn't supply something else, assume that hugepage
15 * size aligned regions are ok without further preparation.
16 */
17static inline int prepare_hugepage_range(struct file *file,
18 unsigned long addr, unsigned long len)
19{
20 if (len & ~HPAGE_MASK)
21 return -EINVAL;
22 if (addr & ~HPAGE_MASK)
23 return -EINVAL;
24 return 0;
25}
26
27static inline void hugetlb_prefault_arch_hook(struct mm_struct *mm) {
28}
29
30static inline void hugetlb_free_pgd_range(struct mmu_gather *tlb,
31 unsigned long addr, unsigned long end,
32 unsigned long floor,
33 unsigned long ceiling)
34{
35 free_pgd_range(tlb, addr, end, floor, ceiling);
36}
37
38static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
39 pte_t *ptep, pte_t pte)
40{
41 set_pte_at(mm, addr, ptep, pte);
42}
43
44static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
45 unsigned long addr, pte_t *ptep)
46{
47 return ptep_get_and_clear(mm, addr, ptep);
48}
49
50static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
51 unsigned long addr, pte_t *ptep)
52{
53}
54
55static inline int huge_pte_none(pte_t pte)
56{
57 return pte_none(pte);
58}
59
60static inline pte_t huge_pte_wrprotect(pte_t pte)
61{
62 return pte_wrprotect(pte);
63}
64
65static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
66 unsigned long addr, pte_t *ptep)
67{
68 ptep_set_wrprotect(mm, addr, ptep);
69}
70
71static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
72 unsigned long addr, pte_t *ptep,
73 pte_t pte, int dirty)
74{
75 return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
76}
77
78static inline pte_t huge_ptep_get(pte_t *ptep)
79{
80 return *ptep;
81}
82
83static inline int arch_prepare_hugepage(struct page *page)
84{
85 return 0;
86}
87
88static inline void arch_release_hugepage(struct page *page)
89{
90}
91
92#endif /* _ASM_SH_HUGETLB_H */
diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h
deleted file mode 100644
index 7438d1e21bc..00000000000
--- a/include/asm-sh/hw_irq.h
+++ /dev/null
@@ -1,123 +0,0 @@
1#ifndef __ASM_SH_HW_IRQ_H
2#define __ASM_SH_HW_IRQ_H
3
4#include <linux/init.h>
5#include <asm/atomic.h>
6
7extern atomic_t irq_err_count;
8
9struct ipr_data {
10 unsigned char irq;
11 unsigned char ipr_idx; /* Index for the IPR registered */
12 unsigned char shift; /* Number of bits to shift the data */
13 unsigned char priority; /* The priority */
14};
15
16struct ipr_desc {
17 unsigned long *ipr_offsets;
18 unsigned int nr_offsets;
19 struct ipr_data *ipr_data;
20 unsigned int nr_irqs;
21 struct irq_chip chip;
22};
23
24void register_ipr_controller(struct ipr_desc *);
25
26typedef unsigned char intc_enum;
27
28struct intc_vect {
29 intc_enum enum_id;
30 unsigned short vect;
31};
32
33#define INTC_VECT(enum_id, vect) { enum_id, vect }
34#define INTC_IRQ(enum_id, irq) INTC_VECT(enum_id, irq2evt(irq))
35
36struct intc_group {
37 intc_enum enum_id;
38 intc_enum enum_ids[32];
39};
40
41#define INTC_GROUP(enum_id, ids...) { enum_id, { ids } }
42
43struct intc_mask_reg {
44 unsigned long set_reg, clr_reg, reg_width;
45 intc_enum enum_ids[32];
46#ifdef CONFIG_SMP
47 unsigned long smp;
48#endif
49};
50
51struct intc_prio_reg {
52 unsigned long set_reg, clr_reg, reg_width, field_width;
53 intc_enum enum_ids[16];
54#ifdef CONFIG_SMP
55 unsigned long smp;
56#endif
57};
58
59struct intc_sense_reg {
60 unsigned long reg, reg_width, field_width;
61 intc_enum enum_ids[16];
62};
63
64#ifdef CONFIG_SMP
65#define INTC_SMP(stride, nr) .smp = (stride) | ((nr) << 8)
66#else
67#define INTC_SMP(stride, nr)
68#endif
69
70struct intc_desc {
71 struct intc_vect *vectors;
72 unsigned int nr_vectors;
73 struct intc_group *groups;
74 unsigned int nr_groups;
75 struct intc_mask_reg *mask_regs;
76 unsigned int nr_mask_regs;
77 struct intc_prio_reg *prio_regs;
78 unsigned int nr_prio_regs;
79 struct intc_sense_reg *sense_regs;
80 unsigned int nr_sense_regs;
81 char *name;
82#ifdef CONFIG_CPU_SH3
83 struct intc_mask_reg *ack_regs;
84 unsigned int nr_ack_regs;
85#endif
86};
87
88#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
89#define DECLARE_INTC_DESC(symbol, chipname, vectors, groups, \
90 mask_regs, prio_regs, sense_regs) \
91struct intc_desc symbol __initdata = { \
92 _INTC_ARRAY(vectors), _INTC_ARRAY(groups), \
93 _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
94 _INTC_ARRAY(sense_regs), \
95 chipname, \
96}
97
98#ifdef CONFIG_CPU_SH3
99#define DECLARE_INTC_DESC_ACK(symbol, chipname, vectors, groups, \
100 mask_regs, prio_regs, sense_regs, ack_regs) \
101struct intc_desc symbol __initdata = { \
102 _INTC_ARRAY(vectors), _INTC_ARRAY(groups), \
103 _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
104 _INTC_ARRAY(sense_regs), \
105 chipname, \
106 _INTC_ARRAY(ack_regs), \
107}
108#endif
109
110void __init register_intc_controller(struct intc_desc *desc);
111int intc_set_priority(unsigned int irq, unsigned int prio);
112
113void __init plat_irq_setup(void);
114#ifdef CONFIG_CPU_SH3
115void __init plat_irq_setup_sh3(void);
116#endif
117
118enum { IRQ_MODE_IRQ, IRQ_MODE_IRQ7654, IRQ_MODE_IRQ3210,
119 IRQ_MODE_IRL7654_MASK, IRQ_MODE_IRL3210_MASK,
120 IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 };
121void __init plat_irq_setup_pins(int mode);
122
123#endif /* __ASM_SH_HW_IRQ_H */
diff --git a/include/asm-sh/i2c-sh7760.h b/include/asm-sh/i2c-sh7760.h
deleted file mode 100644
index 24182116711..00000000000
--- a/include/asm-sh/i2c-sh7760.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * MMIO/IRQ and platform data for SH7760 I2C channels
3 */
4
5#ifndef _I2C_SH7760_H_
6#define _I2C_SH7760_H_
7
8#define SH7760_I2C_DEVNAME "sh7760-i2c"
9
10#define SH7760_I2C0_MMIO 0xFE140000
11#define SH7760_I2C0_MMIOEND 0xFE14003B
12#define SH7760_I2C0_IRQ 62
13
14#define SH7760_I2C1_MMIO 0xFE150000
15#define SH7760_I2C1_MMIOEND 0xFE15003B
16#define SH7760_I2C1_IRQ 63
17
18struct sh7760_i2c_platdata {
19 unsigned int speed_khz;
20};
21
22#endif
diff --git a/include/asm-sh/ilsel.h b/include/asm-sh/ilsel.h
deleted file mode 100644
index e3d304b280f..00000000000
--- a/include/asm-sh/ilsel.h
+++ /dev/null
@@ -1,45 +0,0 @@
1#ifndef __ASM_SH_ILSEL_H
2#define __ASM_SH_ILSEL_H
3
4typedef enum {
5 ILSEL_NONE,
6 ILSEL_LAN,
7 ILSEL_USBH_I,
8 ILSEL_USBH_S,
9 ILSEL_USBH_V,
10 ILSEL_RTC,
11 ILSEL_USBP_I,
12 ILSEL_USBP_S,
13 ILSEL_USBP_V,
14 ILSEL_KEY,
15
16 /*
17 * ILSEL Aliases - corner cases for interleaved level tables.
18 *
19 * Someone thought this was a good idea and less hassle than
20 * demuxing a shared vector, really.
21 */
22
23 /* ILSEL0 and 2 */
24 ILSEL_FPGA0,
25 ILSEL_FPGA1,
26 ILSEL_EX1,
27 ILSEL_EX2,
28 ILSEL_EX3,
29 ILSEL_EX4,
30
31 /* ILSEL1 and 3 */
32 ILSEL_FPGA2 = ILSEL_FPGA0,
33 ILSEL_FPGA3 = ILSEL_FPGA1,
34 ILSEL_EX5 = ILSEL_EX1,
35 ILSEL_EX6 = ILSEL_EX2,
36 ILSEL_EX7 = ILSEL_EX3,
37 ILSEL_EX8 = ILSEL_EX4,
38} ilsel_source_t;
39
40/* arch/sh/boards/renesas/x3proto/ilsel.c */
41int ilsel_enable(ilsel_source_t set);
42int ilsel_enable_fixed(ilsel_source_t set, unsigned int level);
43void ilsel_disable(unsigned int irq);
44
45#endif /* __ASM_SH_ILSEL_H */
diff --git a/include/asm-sh/io.h b/include/asm-sh/io.h
deleted file mode 100644
index a4fbf0c84fb..00000000000
--- a/include/asm-sh/io.h
+++ /dev/null
@@ -1,366 +0,0 @@
1#ifndef __ASM_SH_IO_H
2#define __ASM_SH_IO_H
3
4/*
5 * Convention:
6 * read{b,w,l}/write{b,w,l} are for PCI,
7 * while in{b,w,l}/out{b,w,l} are for ISA
8 * These may (will) be platform specific function.
9 * In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p
10 * and 'string' versions: ins{b,w,l}/outs{b,w,l}
11 * For read{b,w,l} and write{b,w,l} there are also __raw versions, which
12 * do not have a memory barrier after them.
13 *
14 * In addition, we have
15 * ctrl_in{b,w,l}/ctrl_out{b,w,l} for SuperH specific I/O.
16 * which are processor specific.
17 */
18
19/*
20 * We follow the Alpha convention here:
21 * __inb expands to an inline function call (which calls via the mv)
22 * _inb is a real function call (note ___raw fns are _ version of __raw)
23 * inb by default expands to _inb, but the machine specific code may
24 * define it to __inb if it chooses.
25 */
26#include <asm/cache.h>
27#include <asm/system.h>
28#include <asm/addrspace.h>
29#include <asm/machvec.h>
30#include <asm/pgtable.h>
31#include <asm-generic/iomap.h>
32
33#ifdef __KERNEL__
34
35/*
36 * Depending on which platform we are running on, we need different
37 * I/O functions.
38 */
39#define __IO_PREFIX generic
40#include <asm/io_generic.h>
41#include <asm/io_trapped.h>
42
43#define maybebadio(port) \
44 printk(KERN_ERR "bad PC-like io %s:%u for port 0x%lx at 0x%08x\n", \
45 __FUNCTION__, __LINE__, (port), (u32)__builtin_return_address(0))
46
47/*
48 * Since boards are able to define their own set of I/O routines through
49 * their respective machine vector, we always wrap through the mv.
50 *
51 * Also, in the event that a board hasn't provided its own definition for
52 * a given routine, it will be wrapped to generic code at run-time.
53 */
54
55#define __inb(p) sh_mv.mv_inb((p))
56#define __inw(p) sh_mv.mv_inw((p))
57#define __inl(p) sh_mv.mv_inl((p))
58#define __outb(x,p) sh_mv.mv_outb((x),(p))
59#define __outw(x,p) sh_mv.mv_outw((x),(p))
60#define __outl(x,p) sh_mv.mv_outl((x),(p))
61
62#define __inb_p(p) sh_mv.mv_inb_p((p))
63#define __inw_p(p) sh_mv.mv_inw_p((p))
64#define __inl_p(p) sh_mv.mv_inl_p((p))
65#define __outb_p(x,p) sh_mv.mv_outb_p((x),(p))
66#define __outw_p(x,p) sh_mv.mv_outw_p((x),(p))
67#define __outl_p(x,p) sh_mv.mv_outl_p((x),(p))
68
69#define __insb(p,b,c) sh_mv.mv_insb((p), (b), (c))
70#define __insw(p,b,c) sh_mv.mv_insw((p), (b), (c))
71#define __insl(p,b,c) sh_mv.mv_insl((p), (b), (c))
72#define __outsb(p,b,c) sh_mv.mv_outsb((p), (b), (c))
73#define __outsw(p,b,c) sh_mv.mv_outsw((p), (b), (c))
74#define __outsl(p,b,c) sh_mv.mv_outsl((p), (b), (c))
75
76#define __readb(a) sh_mv.mv_readb((a))
77#define __readw(a) sh_mv.mv_readw((a))
78#define __readl(a) sh_mv.mv_readl((a))
79#define __writeb(v,a) sh_mv.mv_writeb((v),(a))
80#define __writew(v,a) sh_mv.mv_writew((v),(a))
81#define __writel(v,a) sh_mv.mv_writel((v),(a))
82
83#define inb __inb
84#define inw __inw
85#define inl __inl
86#define outb __outb
87#define outw __outw
88#define outl __outl
89
90#define inb_p __inb_p
91#define inw_p __inw_p
92#define inl_p __inl_p
93#define outb_p __outb_p
94#define outw_p __outw_p
95#define outl_p __outl_p
96
97#define insb __insb
98#define insw __insw
99#define insl __insl
100#define outsb __outsb
101#define outsw __outsw
102#define outsl __outsl
103
104#define __raw_readb(a) __readb((void __iomem *)(a))
105#define __raw_readw(a) __readw((void __iomem *)(a))
106#define __raw_readl(a) __readl((void __iomem *)(a))
107#define __raw_writeb(v, a) __writeb(v, (void __iomem *)(a))
108#define __raw_writew(v, a) __writew(v, (void __iomem *)(a))
109#define __raw_writel(v, a) __writel(v, (void __iomem *)(a))
110
111void __raw_writesl(unsigned long addr, const void *data, int longlen);
112void __raw_readsl(unsigned long addr, void *data, int longlen);
113
114/*
115 * The platform header files may define some of these macros to use
116 * the inlined versions where appropriate. These macros may also be
117 * redefined by userlevel programs.
118 */
119#ifdef __readb
120# define readb(a) ({ unsigned int r_ = __raw_readb(a); mb(); r_; })
121#endif
122#ifdef __raw_readw
123# define readw(a) ({ unsigned int r_ = __raw_readw(a); mb(); r_; })
124#endif
125#ifdef __raw_readl
126# define readl(a) ({ unsigned int r_ = __raw_readl(a); mb(); r_; })
127#endif
128
129#ifdef __raw_writeb
130# define writeb(v,a) ({ __raw_writeb((v),(a)); mb(); })
131#endif
132#ifdef __raw_writew
133# define writew(v,a) ({ __raw_writew((v),(a)); mb(); })
134#endif
135#ifdef __raw_writel
136# define writel(v,a) ({ __raw_writel((v),(a)); mb(); })
137#endif
138
139#define __BUILD_MEMORY_STRING(bwlq, type) \
140 \
141static inline void writes##bwlq(volatile void __iomem *mem, \
142 const void *addr, unsigned int count) \
143{ \
144 const volatile type *__addr = addr; \
145 \
146 while (count--) { \
147 __raw_write##bwlq(*__addr, mem); \
148 __addr++; \
149 } \
150} \
151 \
152static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \
153 unsigned int count) \
154{ \
155 volatile type *__addr = addr; \
156 \
157 while (count--) { \
158 *__addr = __raw_read##bwlq(mem); \
159 __addr++; \
160 } \
161}
162
163__BUILD_MEMORY_STRING(b, u8)
164__BUILD_MEMORY_STRING(w, u16)
165#define writesl __raw_writesl
166#define readsl __raw_readsl
167
168#define readb_relaxed(a) readb(a)
169#define readw_relaxed(a) readw(a)
170#define readl_relaxed(a) readl(a)
171
172/* Simple MMIO */
173#define ioread8(a) readb(a)
174#define ioread16(a) readw(a)
175#define ioread16be(a) be16_to_cpu(__raw_readw((a)))
176#define ioread32(a) readl(a)
177#define ioread32be(a) be32_to_cpu(__raw_readl((a)))
178
179#define iowrite8(v,a) writeb((v),(a))
180#define iowrite16(v,a) writew((v),(a))
181#define iowrite16be(v,a) __raw_writew(cpu_to_be16((v)),(a))
182#define iowrite32(v,a) writel((v),(a))
183#define iowrite32be(v,a) __raw_writel(cpu_to_be32((v)),(a))
184
185#define ioread8_rep(a, d, c) readsb((a), (d), (c))
186#define ioread16_rep(a, d, c) readsw((a), (d), (c))
187#define ioread32_rep(a, d, c) readsl((a), (d), (c))
188
189#define iowrite8_rep(a, s, c) writesb((a), (s), (c))
190#define iowrite16_rep(a, s, c) writesw((a), (s), (c))
191#define iowrite32_rep(a, s, c) writesl((a), (s), (c))
192
193#define mmiowb() wmb() /* synco on SH-4A, otherwise a nop */
194
195#define IO_SPACE_LIMIT 0xffffffff
196
197/*
198 * This function provides a method for the generic case where a board-specific
199 * ioport_map simply needs to return the port + some arbitrary port base.
200 *
201 * We use this at board setup time to implicitly set the port base, and
202 * as a result, we can use the generic ioport_map.
203 */
204static inline void __set_io_port_base(unsigned long pbase)
205{
206 extern unsigned long generic_io_base;
207
208 generic_io_base = pbase;
209}
210
211#define __ioport_map(p, n) sh_mv.mv_ioport_map((p), (n))
212
213/* We really want to try and get these to memcpy etc */
214extern void memcpy_fromio(void *, volatile void __iomem *, unsigned long);
215extern void memcpy_toio(volatile void __iomem *, const void *, unsigned long);
216extern void memset_io(volatile void __iomem *, int, unsigned long);
217
218/* SuperH on-chip I/O functions */
219static inline unsigned char ctrl_inb(unsigned long addr)
220{
221 return *(volatile unsigned char*)addr;
222}
223
224static inline unsigned short ctrl_inw(unsigned long addr)
225{
226 return *(volatile unsigned short*)addr;
227}
228
229static inline unsigned int ctrl_inl(unsigned long addr)
230{
231 return *(volatile unsigned long*)addr;
232}
233
234static inline unsigned long long ctrl_inq(unsigned long addr)
235{
236 return *(volatile unsigned long long*)addr;
237}
238
239static inline void ctrl_outb(unsigned char b, unsigned long addr)
240{
241 *(volatile unsigned char*)addr = b;
242}
243
244static inline void ctrl_outw(unsigned short b, unsigned long addr)
245{
246 *(volatile unsigned short*)addr = b;
247}
248
249static inline void ctrl_outl(unsigned int b, unsigned long addr)
250{
251 *(volatile unsigned long*)addr = b;
252}
253
254static inline void ctrl_outq(unsigned long long b, unsigned long addr)
255{
256 *(volatile unsigned long long*)addr = b;
257}
258
259static inline void ctrl_delay(void)
260{
261#ifdef P2SEG
262 ctrl_inw(P2SEG);
263#endif
264}
265
266/* Quad-word real-mode I/O, don't ask.. */
267unsigned long long peek_real_address_q(unsigned long long addr);
268unsigned long long poke_real_address_q(unsigned long long addr,
269 unsigned long long val);
270
271#if !defined(CONFIG_MMU)
272#define virt_to_phys(address) ((unsigned long)(address))
273#define phys_to_virt(address) ((void *)(address))
274#else
275#define virt_to_phys(address) (__pa(address))
276#define phys_to_virt(address) (__va(address))
277#endif
278
279/*
280 * On 32-bit SH, we traditionally have the whole physical address space
281 * mapped at all times (as MIPS does), so "ioremap()" and "iounmap()" do
282 * not need to do anything but place the address in the proper segment.
283 * This is true for P1 and P2 addresses, as well as some P3 ones.
284 * However, most of the P3 addresses and newer cores using extended
285 * addressing need to map through page tables, so the ioremap()
286 * implementation becomes a bit more complicated.
287 *
288 * See arch/sh/mm/ioremap.c for additional notes on this.
289 *
290 * We cheat a bit and always return uncachable areas until we've fixed
291 * the drivers to handle caching properly.
292 *
293 * On the SH-5 the concept of segmentation in the 1:1 PXSEG sense simply
294 * doesn't exist, so everything must go through page tables.
295 */
296#ifdef CONFIG_MMU
297void __iomem *__ioremap(unsigned long offset, unsigned long size,
298 unsigned long flags);
299void __iounmap(void __iomem *addr);
300
301/* arch/sh/mm/ioremap_64.c */
302unsigned long onchip_remap(unsigned long addr, unsigned long size,
303 const char *name);
304extern void onchip_unmap(unsigned long vaddr);
305#else
306#define __ioremap(offset, size, flags) ((void __iomem *)(offset))
307#define __iounmap(addr) do { } while (0)
308#define onchip_remap(addr, size, name) (addr)
309#define onchip_unmap(addr) do { } while (0)
310#endif /* CONFIG_MMU */
311
312static inline void __iomem *
313__ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
314{
315#ifdef CONFIG_SUPERH32
316 unsigned long last_addr = offset + size - 1;
317#endif
318 void __iomem *ret;
319
320 ret = __ioremap_trapped(offset, size);
321 if (ret)
322 return ret;
323
324#ifdef CONFIG_SUPERH32
325 /*
326 * For P1 and P2 space this is trivial, as everything is already
327 * mapped. Uncached access for P1 addresses are done through P2.
328 * In the P3 case or for addresses outside of the 29-bit space,
329 * mapping must be done by the PMB or by using page tables.
330 */
331 if (likely(PXSEG(offset) < P3SEG && PXSEG(last_addr) < P3SEG)) {
332 if (unlikely(flags & _PAGE_CACHABLE))
333 return (void __iomem *)P1SEGADDR(offset);
334
335 return (void __iomem *)P2SEGADDR(offset);
336 }
337#endif
338
339 return __ioremap(offset, size, flags);
340}
341
342#define ioremap(offset, size) \
343 __ioremap_mode((offset), (size), 0)
344#define ioremap_nocache(offset, size) \
345 __ioremap_mode((offset), (size), 0)
346#define ioremap_cache(offset, size) \
347 __ioremap_mode((offset), (size), _PAGE_CACHABLE)
348#define p3_ioremap(offset, size, flags) \
349 __ioremap((offset), (size), (flags))
350#define iounmap(addr) \
351 __iounmap((addr))
352
353/*
354 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
355 * access
356 */
357#define xlate_dev_mem_ptr(p) __va(p)
358
359/*
360 * Convert a virtual cached pointer to an uncached pointer
361 */
362#define xlate_dev_kmem_ptr(p) p
363
364#endif /* __KERNEL__ */
365
366#endif /* __ASM_SH_IO_H */
diff --git a/include/asm-sh/io_generic.h b/include/asm-sh/io_generic.h
deleted file mode 100644
index 92fc6070d7b..00000000000
--- a/include/asm-sh/io_generic.h
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * Trivial I/O routine definitions, intentionally meant to be included
3 * multiple times. Ugly I/O routine concatenation helpers taken from
4 * alpha. Must be included _before_ io.h to avoid preprocessor-induced
5 * routine mismatch.
6 */
7#define IO_CONCAT(a,b) _IO_CONCAT(a,b)
8#define _IO_CONCAT(a,b) a ## _ ## b
9
10#ifndef __IO_PREFIX
11#error "Don't include this header without a valid system prefix"
12#endif
13
14u8 IO_CONCAT(__IO_PREFIX,inb)(unsigned long);
15u16 IO_CONCAT(__IO_PREFIX,inw)(unsigned long);
16u32 IO_CONCAT(__IO_PREFIX,inl)(unsigned long);
17
18void IO_CONCAT(__IO_PREFIX,outb)(u8, unsigned long);
19void IO_CONCAT(__IO_PREFIX,outw)(u16, unsigned long);
20void IO_CONCAT(__IO_PREFIX,outl)(u32, unsigned long);
21
22u8 IO_CONCAT(__IO_PREFIX,inb_p)(unsigned long);
23u16 IO_CONCAT(__IO_PREFIX,inw_p)(unsigned long);
24u32 IO_CONCAT(__IO_PREFIX,inl_p)(unsigned long);
25void IO_CONCAT(__IO_PREFIX,outb_p)(u8, unsigned long);
26void IO_CONCAT(__IO_PREFIX,outw_p)(u16, unsigned long);
27void IO_CONCAT(__IO_PREFIX,outl_p)(u32, unsigned long);
28
29void IO_CONCAT(__IO_PREFIX,insb)(unsigned long, void *dst, unsigned long count);
30void IO_CONCAT(__IO_PREFIX,insw)(unsigned long, void *dst, unsigned long count);
31void IO_CONCAT(__IO_PREFIX,insl)(unsigned long, void *dst, unsigned long count);
32void IO_CONCAT(__IO_PREFIX,outsb)(unsigned long, const void *src, unsigned long count);
33void IO_CONCAT(__IO_PREFIX,outsw)(unsigned long, const void *src, unsigned long count);
34void IO_CONCAT(__IO_PREFIX,outsl)(unsigned long, const void *src, unsigned long count);
35
36u8 IO_CONCAT(__IO_PREFIX,readb)(void __iomem *);
37u16 IO_CONCAT(__IO_PREFIX,readw)(void __iomem *);
38u32 IO_CONCAT(__IO_PREFIX,readl)(void __iomem *);
39void IO_CONCAT(__IO_PREFIX,writeb)(u8, void __iomem *);
40void IO_CONCAT(__IO_PREFIX,writew)(u16, void __iomem *);
41void IO_CONCAT(__IO_PREFIX,writel)(u32, void __iomem *);
42
43void *IO_CONCAT(__IO_PREFIX,ioremap)(unsigned long offset, unsigned long size);
44void IO_CONCAT(__IO_PREFIX,iounmap)(void *addr);
45
46void __iomem *IO_CONCAT(__IO_PREFIX,ioport_map)(unsigned long addr, unsigned int size);
47void IO_CONCAT(__IO_PREFIX,ioport_unmap)(void __iomem *addr);
48
49#undef __IO_PREFIX
diff --git a/include/asm-sh/io_trapped.h b/include/asm-sh/io_trapped.h
deleted file mode 100644
index f1251d4f0ba..00000000000
--- a/include/asm-sh/io_trapped.h
+++ /dev/null
@@ -1,58 +0,0 @@
1#ifndef __ASM_SH_IO_TRAPPED_H
2#define __ASM_SH_IO_TRAPPED_H
3
4#include <linux/list.h>
5#include <linux/ioport.h>
6#include <asm/page.h>
7
8#define IO_TRAPPED_MAGIC 0xfeedbeef
9
10struct trapped_io {
11 unsigned int magic;
12 struct resource *resource;
13 unsigned int num_resources;
14 unsigned int minimum_bus_width;
15 struct list_head list;
16 void __iomem *virt_base;
17} __aligned(PAGE_SIZE);
18
19#ifdef CONFIG_IO_TRAPPED
20int register_trapped_io(struct trapped_io *tiop);
21int handle_trapped_io(struct pt_regs *regs, unsigned long address);
22
23void __iomem *match_trapped_io_handler(struct list_head *list,
24 unsigned long offset,
25 unsigned long size);
26
27#ifdef CONFIG_HAS_IOMEM
28extern struct list_head trapped_mem;
29
30static inline void __iomem *
31__ioremap_trapped(unsigned long offset, unsigned long size)
32{
33 return match_trapped_io_handler(&trapped_mem, offset, size);
34}
35#else
36#define __ioremap_trapped(offset, size) NULL
37#endif
38
39#ifdef CONFIG_HAS_IOPORT
40extern struct list_head trapped_io;
41
42static inline void __iomem *
43__ioport_map_trapped(unsigned long offset, unsigned long size)
44{
45 return match_trapped_io_handler(&trapped_io, offset, size);
46}
47#else
48#define __ioport_map_trapped(offset, size) NULL
49#endif
50
51#else
52#define register_trapped_io(tiop) (-1)
53#define handle_trapped_io(tiop, address) 0
54#define __ioremap_trapped(offset, size) NULL
55#define __ioport_map_trapped(offset, size) NULL
56#endif
57
58#endif /* __ASM_SH_IO_TRAPPED_H */
diff --git a/include/asm-sh/ioctl.h b/include/asm-sh/ioctl.h
deleted file mode 100644
index b279fe06dfe..00000000000
--- a/include/asm-sh/ioctl.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/ioctl.h>
diff --git a/include/asm-sh/ioctls.h b/include/asm-sh/ioctls.h
deleted file mode 100644
index c212c371a4a..00000000000
--- a/include/asm-sh/ioctls.h
+++ /dev/null
@@ -1,103 +0,0 @@
1#ifndef __ASM_SH_IOCTLS_H
2#define __ASM_SH_IOCTLS_H
3
4#include <asm/ioctl.h>
5
6#define FIOCLEX _IO('f', 1)
7#define FIONCLEX _IO('f', 2)
8#define FIOASYNC _IOW('f', 125, int)
9#define FIONBIO _IOW('f', 126, int)
10#define FIONREAD _IOR('f', 127, int)
11#define TIOCINQ FIONREAD
12#define FIOQSIZE _IOR('f', 128, loff_t)
13
14#define TCGETS 0x5401
15#define TCSETS 0x5402
16#define TCSETSW 0x5403
17#define TCSETSF 0x5404
18
19#define TCGETA 0x80127417 /* _IOR('t', 23, struct termio) */
20#define TCSETA 0x40127418 /* _IOW('t', 24, struct termio) */
21#define TCSETAW 0x40127419 /* _IOW('t', 25, struct termio) */
22#define TCSETAF 0x4012741C /* _IOW('t', 28, struct termio) */
23
24#define TCSBRK _IO('t', 29)
25#define TCXONC _IO('t', 30)
26#define TCFLSH _IO('t', 31)
27
28#define TIOCSWINSZ 0x40087467 /* _IOW('t', 103, struct winsize) */
29#define TIOCGWINSZ 0x80087468 /* _IOR('t', 104, struct winsize) */
30#define TIOCSTART _IO('t', 110) /* start output, like ^Q */
31#define TIOCSTOP _IO('t', 111) /* stop output, like ^S */
32#define TIOCOUTQ _IOR('t', 115, int) /* output queue size */
33
34#define TIOCSPGRP _IOW('t', 118, int)
35#define TIOCGPGRP _IOR('t', 119, int)
36
37#define TIOCEXCL _IO('T', 12) /* 0x540C */
38#define TIOCNXCL _IO('T', 13) /* 0x540D */
39#define TIOCSCTTY _IO('T', 14) /* 0x540E */
40
41#define TIOCSTI _IOW('T', 18, char) /* 0x5412 */
42#define TIOCMGET _IOR('T', 21, unsigned int) /* 0x5415 */
43#define TIOCMBIS _IOW('T', 22, unsigned int) /* 0x5416 */
44#define TIOCMBIC _IOW('T', 23, unsigned int) /* 0x5417 */
45#define TIOCMSET _IOW('T', 24, unsigned int) /* 0x5418 */
46# define TIOCM_LE 0x001
47# define TIOCM_DTR 0x002
48# define TIOCM_RTS 0x004
49# define TIOCM_ST 0x008
50# define TIOCM_SR 0x010
51# define TIOCM_CTS 0x020
52# define TIOCM_CAR 0x040
53# define TIOCM_RNG 0x080
54# define TIOCM_DSR 0x100
55# define TIOCM_CD TIOCM_CAR
56# define TIOCM_RI TIOCM_RNG
57
58#define TIOCGSOFTCAR _IOR('T', 25, unsigned int) /* 0x5419 */
59#define TIOCSSOFTCAR _IOW('T', 26, unsigned int) /* 0x541A */
60#define TIOCLINUX _IOW('T', 28, char) /* 0x541C */
61#define TIOCCONS _IO('T', 29) /* 0x541D */
62#define TIOCGSERIAL 0x803C541E /* _IOR('T', 30, struct serial_struct) 0x541E */
63#define TIOCSSERIAL 0x403C541F /* _IOW('T', 31, struct serial_struct) 0x541F */
64#define TIOCPKT _IOW('T', 32, int) /* 0x5420 */
65# define TIOCPKT_DATA 0
66# define TIOCPKT_FLUSHREAD 1
67# define TIOCPKT_FLUSHWRITE 2
68# define TIOCPKT_STOP 4
69# define TIOCPKT_START 8
70# define TIOCPKT_NOSTOP 16
71# define TIOCPKT_DOSTOP 32
72
73
74#define TIOCNOTTY _IO('T', 34) /* 0x5422 */
75#define TIOCSETD _IOW('T', 35, int) /* 0x5423 */
76#define TIOCGETD _IOR('T', 36, int) /* 0x5424 */
77#define TCSBRKP _IOW('T', 37, int) /* 0x5425 */ /* Needed for POSIX tcsendbreak() */
78#define TIOCSBRK _IO('T', 39) /* 0x5427 */ /* BSD compatibility */
79#define TIOCCBRK _IO('T', 40) /* 0x5428 */ /* BSD compatibility */
80#define TIOCGSID _IOR('T', 41, pid_t) /* 0x5429 */ /* Return the session ID of FD */
81#define TCGETS2 _IOR('T', 42, struct termios2)
82#define TCSETS2 _IOW('T', 43, struct termios2)
83#define TCSETSW2 _IOW('T', 44, struct termios2)
84#define TCSETSF2 _IOW('T', 45, struct termios2)
85#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
86#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */
87
88#define TIOCSERCONFIG _IO('T', 83) /* 0x5453 */
89#define TIOCSERGWILD _IOR('T', 84, int) /* 0x5454 */
90#define TIOCSERSWILD _IOW('T', 85, int) /* 0x5455 */
91#define TIOCGLCKTRMIOS 0x5456
92#define TIOCSLCKTRMIOS 0x5457
93#define TIOCSERGSTRUCT 0x80d85458 /* _IOR('T', 88, struct async_struct) 0x5458 */ /* For debugging only */
94#define TIOCSERGETLSR _IOR('T', 89, unsigned int) /* 0x5459 */ /* Get line status register */
95 /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
96# define TIOCSER_TEMT 0x01 /* Transmitter physically empty */
97#define TIOCSERGETMULTI 0x80A8545A /* _IOR('T', 90, struct serial_multiport_struct) 0x545A */ /* Get multiport config */
98#define TIOCSERSETMULTI 0x40A8545B /* _IOW('T', 91, struct serial_multiport_struct) 0x545B */ /* Set multiport config */
99
100#define TIOCMIWAIT _IO('T', 92) /* 0x545C */ /* wait for a change on serial input line(s) */
101#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */
102
103#endif /* __ASM_SH_IOCTLS_H */
diff --git a/include/asm-sh/ipcbuf.h b/include/asm-sh/ipcbuf.h
deleted file mode 100644
index 5ffc9972a7e..00000000000
--- a/include/asm-sh/ipcbuf.h
+++ /dev/null
@@ -1,29 +0,0 @@
1#ifndef __ASM_SH_IPCBUF_H__
2#define __ASM_SH_IPCBUF_H__
3
4/*
5 * The ipc64_perm structure for i386 architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 32-bit mode_t and seq
11 * - 2 miscellaneous 32-bit values
12 */
13
14struct ipc64_perm
15{
16 __kernel_key_t key;
17 __kernel_uid32_t uid;
18 __kernel_gid32_t gid;
19 __kernel_uid32_t cuid;
20 __kernel_gid32_t cgid;
21 __kernel_mode_t mode;
22 unsigned short __pad1;
23 unsigned short seq;
24 unsigned short __pad2;
25 unsigned long __unused1;
26 unsigned long __unused2;
27};
28
29#endif /* __ASM_SH_IPCBUF_H__ */
diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h
deleted file mode 100644
index ca66e5df69d..00000000000
--- a/include/asm-sh/irq.h
+++ /dev/null
@@ -1,57 +0,0 @@
1#ifndef __ASM_SH_IRQ_H
2#define __ASM_SH_IRQ_H
3
4#include <asm/machvec.h>
5
6/*
7 * A sane default based on a reasonable vector table size, platforms are
8 * advised to cap this at the hard limit that they're interested in
9 * through the machvec.
10 */
11#define NR_IRQS 256
12
13/*
14 * Convert back and forth between INTEVT and IRQ values.
15 */
16#ifdef CONFIG_CPU_HAS_INTEVT
17#define evt2irq(evt) (((evt) >> 5) - 16)
18#define irq2evt(irq) (((irq) + 16) << 5)
19#else
20#define evt2irq(evt) (evt)
21#define irq2evt(irq) (irq)
22#endif
23
24/*
25 * Simple Mask Register Support
26 */
27extern void make_maskreg_irq(unsigned int irq);
28extern unsigned short *irq_mask_register;
29
30/*
31 * PINT IRQs
32 */
33void init_IRQ_pint(void);
34void make_imask_irq(unsigned int irq);
35
36static inline int generic_irq_demux(int irq)
37{
38 return irq;
39}
40
41#define irq_canonicalize(irq) (irq)
42#define irq_demux(irq) sh_mv.mv_irq_demux(irq)
43
44#ifdef CONFIG_IRQSTACKS
45extern void irq_ctx_init(int cpu);
46extern void irq_ctx_exit(int cpu);
47# define __ARCH_HAS_DO_SOFTIRQ
48#else
49# define irq_ctx_init(cpu) do { } while (0)
50# define irq_ctx_exit(cpu) do { } while (0)
51#endif
52
53#ifdef CONFIG_CPU_SH5
54#include <asm/cpu/irq.h>
55#endif
56
57#endif /* __ASM_SH_IRQ_H */
diff --git a/include/asm-sh/irq_regs.h b/include/asm-sh/irq_regs.h
deleted file mode 100644
index 3dd9c0b7027..00000000000
--- a/include/asm-sh/irq_regs.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/irq_regs.h>
diff --git a/include/asm-sh/irqflags.h b/include/asm-sh/irqflags.h
deleted file mode 100644
index 46e71da5be6..00000000000
--- a/include/asm-sh/irqflags.h
+++ /dev/null
@@ -1,34 +0,0 @@
1#ifndef __ASM_SH_IRQFLAGS_H
2#define __ASM_SH_IRQFLAGS_H
3
4#ifdef CONFIG_SUPERH32
5#include "irqflags_32.h"
6#else
7#include "irqflags_64.h"
8#endif
9
10#define raw_local_save_flags(flags) \
11 do { (flags) = __raw_local_save_flags(); } while (0)
12
13static inline int raw_irqs_disabled_flags(unsigned long flags)
14{
15 return (flags != 0);
16}
17
18static inline int raw_irqs_disabled(void)
19{
20 unsigned long flags = __raw_local_save_flags();
21
22 return raw_irqs_disabled_flags(flags);
23}
24
25#define raw_local_irq_save(flags) \
26 do { (flags) = __raw_local_irq_save(); } while (0)
27
28static inline void raw_local_irq_restore(unsigned long flags)
29{
30 if ((flags & 0xf0) != 0xf0)
31 raw_local_irq_enable();
32}
33
34#endif /* __ASM_SH_IRQFLAGS_H */
diff --git a/include/asm-sh/irqflags_32.h b/include/asm-sh/irqflags_32.h
deleted file mode 100644
index 60218f54134..00000000000
--- a/include/asm-sh/irqflags_32.h
+++ /dev/null
@@ -1,99 +0,0 @@
1#ifndef __ASM_SH_IRQFLAGS_32_H
2#define __ASM_SH_IRQFLAGS_32_H
3
4static inline void raw_local_irq_enable(void)
5{
6 unsigned long __dummy0, __dummy1;
7
8 __asm__ __volatile__ (
9 "stc sr, %0\n\t"
10 "and %1, %0\n\t"
11#ifdef CONFIG_CPU_HAS_SR_RB
12 "stc r6_bank, %1\n\t"
13 "or %1, %0\n\t"
14#endif
15 "ldc %0, sr\n\t"
16 : "=&r" (__dummy0), "=r" (__dummy1)
17 : "1" (~0x000000f0)
18 : "memory"
19 );
20}
21
22static inline void raw_local_irq_disable(void)
23{
24 unsigned long flags;
25
26 __asm__ __volatile__ (
27 "stc sr, %0\n\t"
28 "or #0xf0, %0\n\t"
29 "ldc %0, sr\n\t"
30 : "=&z" (flags)
31 : /* no inputs */
32 : "memory"
33 );
34}
35
36static inline void set_bl_bit(void)
37{
38 unsigned long __dummy0, __dummy1;
39
40 __asm__ __volatile__ (
41 "stc sr, %0\n\t"
42 "or %2, %0\n\t"
43 "and %3, %0\n\t"
44 "ldc %0, sr\n\t"
45 : "=&r" (__dummy0), "=r" (__dummy1)
46 : "r" (0x10000000), "r" (0xffffff0f)
47 : "memory"
48 );
49}
50
51static inline void clear_bl_bit(void)
52{
53 unsigned long __dummy0, __dummy1;
54
55 __asm__ __volatile__ (
56 "stc sr, %0\n\t"
57 "and %2, %0\n\t"
58 "ldc %0, sr\n\t"
59 : "=&r" (__dummy0), "=r" (__dummy1)
60 : "1" (~0x10000000)
61 : "memory"
62 );
63}
64
65static inline unsigned long __raw_local_save_flags(void)
66{
67 unsigned long flags;
68
69 __asm__ __volatile__ (
70 "stc sr, %0\n\t"
71 "and #0xf0, %0\n\t"
72 : "=&z" (flags)
73 : /* no inputs */
74 : "memory"
75 );
76
77 return flags;
78}
79
80static inline unsigned long __raw_local_irq_save(void)
81{
82 unsigned long flags, __dummy;
83
84 __asm__ __volatile__ (
85 "stc sr, %1\n\t"
86 "mov %1, %0\n\t"
87 "or #0xf0, %0\n\t"
88 "ldc %0, sr\n\t"
89 "mov %1, %0\n\t"
90 "and #0xf0, %0\n\t"
91 : "=&z" (flags), "=&r" (__dummy)
92 : /* no inputs */
93 : "memory"
94 );
95
96 return flags;
97}
98
99#endif /* __ASM_SH_IRQFLAGS_32_H */
diff --git a/include/asm-sh/irqflags_64.h b/include/asm-sh/irqflags_64.h
deleted file mode 100644
index 4f6b8a56e7b..00000000000
--- a/include/asm-sh/irqflags_64.h
+++ /dev/null
@@ -1,85 +0,0 @@
1#ifndef __ASM_SH_IRQFLAGS_64_H
2#define __ASM_SH_IRQFLAGS_64_H
3
4#include <asm/cpu/registers.h>
5
6#define SR_MASK_LL 0x00000000000000f0LL
7#define SR_BL_LL 0x0000000010000000LL
8
9static inline void raw_local_irq_enable(void)
10{
11 unsigned long long __dummy0, __dummy1 = ~SR_MASK_LL;
12
13 __asm__ __volatile__("getcon " __SR ", %0\n\t"
14 "and %0, %1, %0\n\t"
15 "putcon %0, " __SR "\n\t"
16 : "=&r" (__dummy0)
17 : "r" (__dummy1));
18}
19
20static inline void raw_local_irq_disable(void)
21{
22 unsigned long long __dummy0, __dummy1 = SR_MASK_LL;
23
24 __asm__ __volatile__("getcon " __SR ", %0\n\t"
25 "or %0, %1, %0\n\t"
26 "putcon %0, " __SR "\n\t"
27 : "=&r" (__dummy0)
28 : "r" (__dummy1));
29}
30
31static inline void set_bl_bit(void)
32{
33 unsigned long long __dummy0, __dummy1 = SR_BL_LL;
34
35 __asm__ __volatile__("getcon " __SR ", %0\n\t"
36 "or %0, %1, %0\n\t"
37 "putcon %0, " __SR "\n\t"
38 : "=&r" (__dummy0)
39 : "r" (__dummy1));
40
41}
42
43static inline void clear_bl_bit(void)
44{
45 unsigned long long __dummy0, __dummy1 = ~SR_BL_LL;
46
47 __asm__ __volatile__("getcon " __SR ", %0\n\t"
48 "and %0, %1, %0\n\t"
49 "putcon %0, " __SR "\n\t"
50 : "=&r" (__dummy0)
51 : "r" (__dummy1));
52}
53
54static inline unsigned long __raw_local_save_flags(void)
55{
56 unsigned long long __dummy = SR_MASK_LL;
57 unsigned long flags;
58
59 __asm__ __volatile__ (
60 "getcon " __SR ", %0\n\t"
61 "and %0, %1, %0"
62 : "=&r" (flags)
63 : "r" (__dummy));
64
65 return flags;
66}
67
68static inline unsigned long __raw_local_irq_save(void)
69{
70 unsigned long long __dummy0, __dummy1 = SR_MASK_LL;
71 unsigned long flags;
72
73 __asm__ __volatile__ (
74 "getcon " __SR ", %1\n\t"
75 "or %1, r63, %0\n\t"
76 "or %1, %2, %1\n\t"
77 "putcon %1, " __SR "\n\t"
78 "and %0, %2, %0"
79 : "=&r" (flags), "=&r" (__dummy0)
80 : "r" (__dummy1));
81
82 return flags;
83}
84
85#endif /* __ASM_SH_IRQFLAGS_64_H */
diff --git a/include/asm-sh/kdebug.h b/include/asm-sh/kdebug.h
deleted file mode 100644
index 49cd69051a8..00000000000
--- a/include/asm-sh/kdebug.h
+++ /dev/null
@@ -1,9 +0,0 @@
1#ifndef __ASM_SH_KDEBUG_H
2#define __ASM_SH_KDEBUG_H
3
4/* Grossly misnamed. */
5enum die_val {
6 DIE_TRAP,
7};
8
9#endif /* __ASM_SH_KDEBUG_H */
diff --git a/include/asm-sh/kexec.h b/include/asm-sh/kexec.h
deleted file mode 100644
index 00f4260ef09..00000000000
--- a/include/asm-sh/kexec.h
+++ /dev/null
@@ -1,62 +0,0 @@
1#ifndef __ASM_SH_KEXEC_H
2#define __ASM_SH_KEXEC_H
3
4#include <asm/ptrace.h>
5#include <asm/string.h>
6
7/*
8 * KEXEC_SOURCE_MEMORY_LIMIT maximum page get_free_page can return.
9 * I.e. Maximum page that is mapped directly into kernel memory,
10 * and kmap is not required.
11 *
12 * Someone correct me if FIXADDR_START - PAGEOFFSET is not the correct
13 * calculation for the amount of memory directly mappable into the
14 * kernel memory space.
15 */
16
17/* Maximum physical address we can use pages from */
18#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
19/* Maximum address we can reach in physical address mode */
20#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
21/* Maximum address we can use for the control code buffer */
22#define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE
23
24#define KEXEC_CONTROL_CODE_SIZE 4096
25
26/* The native architecture */
27#define KEXEC_ARCH KEXEC_ARCH_SH
28
29static inline void crash_setup_regs(struct pt_regs *newregs,
30 struct pt_regs *oldregs)
31{
32 if (oldregs)
33 memcpy(newregs, oldregs, sizeof(*newregs));
34 else {
35 __asm__ __volatile__ ("mov r0, %0" : "=r" (newregs->regs[0]));
36 __asm__ __volatile__ ("mov r1, %0" : "=r" (newregs->regs[1]));
37 __asm__ __volatile__ ("mov r2, %0" : "=r" (newregs->regs[2]));
38 __asm__ __volatile__ ("mov r3, %0" : "=r" (newregs->regs[3]));
39 __asm__ __volatile__ ("mov r4, %0" : "=r" (newregs->regs[4]));
40 __asm__ __volatile__ ("mov r5, %0" : "=r" (newregs->regs[5]));
41 __asm__ __volatile__ ("mov r6, %0" : "=r" (newregs->regs[6]));
42 __asm__ __volatile__ ("mov r7, %0" : "=r" (newregs->regs[7]));
43 __asm__ __volatile__ ("mov r8, %0" : "=r" (newregs->regs[8]));
44 __asm__ __volatile__ ("mov r9, %0" : "=r" (newregs->regs[9]));
45 __asm__ __volatile__ ("mov r10, %0" : "=r" (newregs->regs[10]));
46 __asm__ __volatile__ ("mov r11, %0" : "=r" (newregs->regs[11]));
47 __asm__ __volatile__ ("mov r12, %0" : "=r" (newregs->regs[12]));
48 __asm__ __volatile__ ("mov r13, %0" : "=r" (newregs->regs[13]));
49 __asm__ __volatile__ ("mov r14, %0" : "=r" (newregs->regs[14]));
50 __asm__ __volatile__ ("mov r15, %0" : "=r" (newregs->regs[15]));
51
52 __asm__ __volatile__ ("sts pr, %0" : "=r" (newregs->pr));
53 __asm__ __volatile__ ("sts macl, %0" : "=r" (newregs->macl));
54 __asm__ __volatile__ ("sts mach, %0" : "=r" (newregs->mach));
55
56 __asm__ __volatile__ ("stc gbr, %0" : "=r" (newregs->gbr));
57 __asm__ __volatile__ ("stc sr, %0" : "=r" (newregs->sr));
58
59 newregs->pc = (unsigned long)current_text_addr();
60 }
61}
62#endif /* __ASM_SH_KEXEC_H */
diff --git a/include/asm-sh/kgdb.h b/include/asm-sh/kgdb.h
deleted file mode 100644
index 24e42078f36..00000000000
--- a/include/asm-sh/kgdb.h
+++ /dev/null
@@ -1,69 +0,0 @@
1/*
2 * May be copied or modified under the terms of the GNU General Public
3 * License. See linux/COPYING for more information.
4 *
5 * Based on original code by Glenn Engel, Jim Kingdon,
6 * David Grothe <dave@gcom.com>, Tigran Aivazian, <tigran@sco.com> and
7 * Amit S. Kale <akale@veritas.com>
8 *
9 * Super-H port based on sh-stub.c (Ben Lee and Steve Chamberlain) by
10 * Henry Bell <henry.bell@st.com>
11 *
12 * Header file for low-level support for remote debug using GDB.
13 *
14 */
15
16#ifndef __KGDB_H
17#define __KGDB_H
18
19#include <asm/ptrace.h>
20
21/* Same as pt_regs but has vbr in place of syscall_nr */
22struct kgdb_regs {
23 unsigned long regs[16];
24 unsigned long pc;
25 unsigned long pr;
26 unsigned long sr;
27 unsigned long gbr;
28 unsigned long mach;
29 unsigned long macl;
30 unsigned long vbr;
31};
32
33/* State info */
34extern char kgdb_in_gdb_mode;
35extern int kgdb_nofault; /* Ignore bus errors (in gdb mem access) */
36extern char in_nmi; /* Debounce flag to prevent NMI reentry*/
37
38/* SCI */
39extern int kgdb_portnum;
40extern int kgdb_baud;
41extern char kgdb_parity;
42extern char kgdb_bits;
43
44/* Init and interface stuff */
45extern int kgdb_init(void);
46extern int (*kgdb_getchar)(void);
47extern void (*kgdb_putchar)(int);
48
49/* Trap functions */
50typedef void (kgdb_debug_hook_t)(struct pt_regs *regs);
51typedef void (kgdb_bus_error_hook_t)(void);
52extern kgdb_debug_hook_t *kgdb_debug_hook;
53extern kgdb_bus_error_hook_t *kgdb_bus_err_hook;
54
55/* Console */
56struct console;
57void kgdb_console_write(struct console *co, const char *s, unsigned count);
58extern int kgdb_console_setup(struct console *, char *);
59
60/* Prototypes for jmp fns */
61#define _JBLEN 9
62typedef int jmp_buf[_JBLEN];
63extern void longjmp(jmp_buf __jmpb, int __retval);
64extern int setjmp(jmp_buf __jmpb);
65
66/* Forced breakpoint */
67#define breakpoint() __asm__ __volatile__("trapa #0x3c")
68
69#endif
diff --git a/include/asm-sh/kmap_types.h b/include/asm-sh/kmap_types.h
deleted file mode 100644
index 84d565c696b..00000000000
--- a/include/asm-sh/kmap_types.h
+++ /dev/null
@@ -1,32 +0,0 @@
1#ifndef __SH_KMAP_TYPES_H
2#define __SH_KMAP_TYPES_H
3
4/* Dummy header just to define km_type. */
5
6
7#ifdef CONFIG_DEBUG_HIGHMEM
8# define D(n) __KM_FENCE_##n ,
9#else
10# define D(n)
11#endif
12
13enum km_type {
14D(0) KM_BOUNCE_READ,
15D(1) KM_SKB_SUNRPC_DATA,
16D(2) KM_SKB_DATA_SOFTIRQ,
17D(3) KM_USER0,
18D(4) KM_USER1,
19D(5) KM_BIO_SRC_IRQ,
20D(6) KM_BIO_DST_IRQ,
21D(7) KM_PTE0,
22D(8) KM_PTE1,
23D(9) KM_IRQ0,
24D(10) KM_IRQ1,
25D(11) KM_SOFTIRQ0,
26D(12) KM_SOFTIRQ1,
27D(13) KM_TYPE_NR
28};
29
30#undef D
31
32#endif
diff --git a/include/asm-sh/landisk/gio.h b/include/asm-sh/landisk/gio.h
deleted file mode 100644
index 35d7368b718..00000000000
--- a/include/asm-sh/landisk/gio.h
+++ /dev/null
@@ -1,37 +0,0 @@
1#ifndef __ASM_SH_LANDISK_GIO_H
2#define __ASM_SH_LANDISK_GIO_H
3
4#include <linux/ioctl.h>
5
6/* version */
7#define VERSION_STR "1.00"
8
9/* Driver name */
10#define GIO_DRIVER_NAME "/dev/giodrv"
11
12/* Use 'k' as magic number */
13#define GIODRV_IOC_MAGIC 'k'
14
15#define GIODRV_IOCRESET _IO(GIODRV_IOC_MAGIC, 0)
16/*
17 * S means "Set" through a ptr,
18 * T means "Tell" directly
19 * G means "Get" (to a pointed var)
20 * Q means "Query", response is on the return value
21 * X means "eXchange": G and S atomically
22 * H means "sHift": T and Q atomically
23 */
24#define GIODRV_IOCSGIODATA1 _IOW(GIODRV_IOC_MAGIC, 1, unsigned char *)
25#define GIODRV_IOCGGIODATA1 _IOR(GIODRV_IOC_MAGIC, 2, unsigned char *)
26#define GIODRV_IOCSGIODATA2 _IOW(GIODRV_IOC_MAGIC, 3, unsigned short *)
27#define GIODRV_IOCGGIODATA2 _IOR(GIODRV_IOC_MAGIC, 4, unsigned short *)
28#define GIODRV_IOCSGIODATA4 _IOW(GIODRV_IOC_MAGIC, 5, unsigned long *)
29#define GIODRV_IOCGGIODATA4 _IOR(GIODRV_IOC_MAGIC, 6, unsigned long *)
30#define GIODRV_IOCSGIOSETADDR _IOW(GIODRV_IOC_MAGIC, 7, unsigned long *)
31#define GIODRV_IOCHARDRESET _IO(GIODRV_IOC_MAGIC, 8) /* debugging tool */
32#define GIODRV_IOC_MAXNR 8
33
34#define GIO_READ 0x00000000
35#define GIO_WRITE 0x00000001
36
37#endif /* __ASM_SH_LANDISK_GIO_H */
diff --git a/include/asm-sh/landisk/iodata_landisk.h b/include/asm-sh/landisk/iodata_landisk.h
deleted file mode 100644
index 6fb04ab38b9..00000000000
--- a/include/asm-sh/landisk/iodata_landisk.h
+++ /dev/null
@@ -1,42 +0,0 @@
1#ifndef __ASM_SH_IODATA_LANDISK_H
2#define __ASM_SH_IODATA_LANDISK_H
3
4/*
5 * linux/include/asm-sh/landisk/iodata_landisk.h
6 *
7 * Copyright (C) 2000 Atom Create Engineering Co., Ltd.
8 *
9 * IO-DATA LANDISK support
10 */
11
12/* Box specific addresses. */
13
14#define PA_USB 0xa4000000 /* USB Controller M66590 */
15
16#define PA_ATARST 0xb0000000 /* ATA/FATA Access Control Register */
17#define PA_LED 0xb0000001 /* LED Control Register */
18#define PA_STATUS 0xb0000002 /* Switch Status Register */
19#define PA_SHUTDOWN 0xb0000003 /* Shutdown Control Register */
20#define PA_PCIPME 0xb0000004 /* PCI PME Status Register */
21#define PA_IMASK 0xb0000005 /* Interrupt Mask Register */
22/* 2003.10.31 I-O DATA NSD NWG add. for shutdown port clear */
23#define PA_PWRINT_CLR 0xb0000006 /* Shutdown Interrupt clear Register */
24
25#define PA_PIDE_OFFSET 0x40 /* CF IDE Offset */
26#define PA_SIDE_OFFSET 0x40 /* HDD IDE Offset */
27
28#define IRQ_PCIINTA 5 /* PCI INTA IRQ */
29#define IRQ_PCIINTB 6 /* PCI INTB IRQ */
30#define IRQ_PCIINDC 7 /* PCI INTC IRQ */
31#define IRQ_PCIINTD 8 /* PCI INTD IRQ */
32#define IRQ_ATA 9 /* ATA IRQ */
33#define IRQ_FATA 10 /* FATA IRQ */
34#define IRQ_POWER 11 /* Power Switch IRQ */
35#define IRQ_BUTTON 12 /* USL-5P Button IRQ */
36#define IRQ_FAULT 13 /* USL-5P Fault IRQ */
37
38#define __IO_PREFIX landisk
39#include <asm/io_generic.h>
40
41#endif /* __ASM_SH_IODATA_LANDISK_H */
42
diff --git a/include/asm-sh/lboxre2.h b/include/asm-sh/lboxre2.h
deleted file mode 100644
index e6d16050492..00000000000
--- a/include/asm-sh/lboxre2.h
+++ /dev/null
@@ -1,27 +0,0 @@
1#ifndef __ASM_SH_LBOXRE2_H
2#define __ASM_SH_LBOXRE2_H
3
4/*
5 * Copyright (C) 2007 Nobuhiro Iwamatsu
6 *
7 * NTT COMWARE L-BOX RE2 support
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 *
13 */
14
15#define IRQ_CF1 9 /* CF1 */
16#define IRQ_CF0 10 /* CF0 */
17#define IRQ_INTD 11 /* INTD */
18#define IRQ_ETH1 12 /* Ether1 */
19#define IRQ_ETH0 13 /* Ether0 */
20#define IRQ_INTA 14 /* INTA */
21
22void init_lboxre2_IRQ(void);
23
24#define __IO_PREFIX lboxre2
25#include <asm/io_generic.h>
26
27#endif /* __ASM_SH_LBOXRE2_H */
diff --git a/include/asm-sh/linkage.h b/include/asm-sh/linkage.h
deleted file mode 100644
index 3565a4f4009..00000000000
--- a/include/asm-sh/linkage.h
+++ /dev/null
@@ -1,7 +0,0 @@
1#ifndef __ASM_LINKAGE_H
2#define __ASM_LINKAGE_H
3
4#define __ALIGN .balign 4
5#define __ALIGN_STR ".balign 4"
6
7#endif
diff --git a/include/asm-sh/local.h b/include/asm-sh/local.h
deleted file mode 100644
index 9ed9b9cb459..00000000000
--- a/include/asm-sh/local.h
+++ /dev/null
@@ -1,7 +0,0 @@
1#ifndef __ASM_SH_LOCAL_H
2#define __ASM_SH_LOCAL_H
3
4#include <asm-generic/local.h>
5
6#endif /* __ASM_SH_LOCAL_H */
7
diff --git a/include/asm-sh/machvec.h b/include/asm-sh/machvec.h
deleted file mode 100644
index b2e4124070a..00000000000
--- a/include/asm-sh/machvec.h
+++ /dev/null
@@ -1,70 +0,0 @@
1/*
2 * include/asm-sh/machvec.h
3 *
4 * Copyright 2000 Stuart Menefy (stuart.menefy@st.com)
5 *
6 * May be copied or modified under the terms of the GNU General Public
7 * License. See linux/COPYING for more information.
8 */
9
10#ifndef _ASM_SH_MACHVEC_H
11#define _ASM_SH_MACHVEC_H
12
13#include <linux/types.h>
14#include <linux/time.h>
15#include <asm/machtypes.h>
16
17struct device;
18
19struct sh_machine_vector {
20 void (*mv_setup)(char **cmdline_p);
21 const char *mv_name;
22 int mv_nr_irqs;
23
24 u8 (*mv_inb)(unsigned long);
25 u16 (*mv_inw)(unsigned long);
26 u32 (*mv_inl)(unsigned long);
27 void (*mv_outb)(u8, unsigned long);
28 void (*mv_outw)(u16, unsigned long);
29 void (*mv_outl)(u32, unsigned long);
30
31 u8 (*mv_inb_p)(unsigned long);
32 u16 (*mv_inw_p)(unsigned long);
33 u32 (*mv_inl_p)(unsigned long);
34 void (*mv_outb_p)(u8, unsigned long);
35 void (*mv_outw_p)(u16, unsigned long);
36 void (*mv_outl_p)(u32, unsigned long);
37
38 void (*mv_insb)(unsigned long, void *dst, unsigned long count);
39 void (*mv_insw)(unsigned long, void *dst, unsigned long count);
40 void (*mv_insl)(unsigned long, void *dst, unsigned long count);
41 void (*mv_outsb)(unsigned long, const void *src, unsigned long count);
42 void (*mv_outsw)(unsigned long, const void *src, unsigned long count);
43 void (*mv_outsl)(unsigned long, const void *src, unsigned long count);
44
45 u8 (*mv_readb)(void __iomem *);
46 u16 (*mv_readw)(void __iomem *);
47 u32 (*mv_readl)(void __iomem *);
48 void (*mv_writeb)(u8, void __iomem *);
49 void (*mv_writew)(u16, void __iomem *);
50 void (*mv_writel)(u32, void __iomem *);
51
52 int (*mv_irq_demux)(int irq);
53
54 void (*mv_init_irq)(void);
55 void (*mv_init_pci)(void);
56
57 void (*mv_heartbeat)(void);
58
59 void __iomem *(*mv_ioport_map)(unsigned long port, unsigned int size);
60 void (*mv_ioport_unmap)(void __iomem *);
61};
62
63extern struct sh_machine_vector sh_mv;
64
65#define get_system_type() sh_mv.mv_name
66
67#define __initmv \
68 __used __section(.machvec.init)
69
70#endif /* _ASM_SH_MACHVEC_H */
diff --git a/include/asm-sh/magicpanelr2.h b/include/asm-sh/magicpanelr2.h
deleted file mode 100644
index c644a77ee35..00000000000
--- a/include/asm-sh/magicpanelr2.h
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * include/asm-sh/magicpanelr2.h
3 *
4 * Copyright (C) 2007 Markus Brunner, Mark Jonas
5 *
6 * I/O addresses and bitmasks for Magic Panel Release 2 board
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12
13#ifndef __ASM_SH_MAGICPANELR2_H
14#define __ASM_SH_MAGICPANELR2_H
15
16#include <asm/gpio.h>
17
18#define __IO_PREFIX mpr2
19#include <asm/io_generic.h>
20
21
22#define SETBITS_OUTB(mask, reg) ctrl_outb(ctrl_inb(reg) | mask, reg)
23#define SETBITS_OUTW(mask, reg) ctrl_outw(ctrl_inw(reg) | mask, reg)
24#define SETBITS_OUTL(mask, reg) ctrl_outl(ctrl_inl(reg) | mask, reg)
25#define CLRBITS_OUTB(mask, reg) ctrl_outb(ctrl_inb(reg) & ~mask, reg)
26#define CLRBITS_OUTW(mask, reg) ctrl_outw(ctrl_inw(reg) & ~mask, reg)
27#define CLRBITS_OUTL(mask, reg) ctrl_outl(ctrl_inl(reg) & ~mask, reg)
28
29
30#define PA_LED PORT_PADR /* LED */
31
32
33/* BSC */
34#define CMNCR 0xA4FD0000UL
35#define CS0BCR 0xA4FD0004UL
36#define CS2BCR 0xA4FD0008UL
37#define CS3BCR 0xA4FD000CUL
38#define CS4BCR 0xA4FD0010UL
39#define CS5ABCR 0xA4FD0014UL
40#define CS5BBCR 0xA4FD0018UL
41#define CS6ABCR 0xA4FD001CUL
42#define CS6BBCR 0xA4FD0020UL
43#define CS0WCR 0xA4FD0024UL
44#define CS2WCR 0xA4FD0028UL
45#define CS3WCR 0xA4FD002CUL
46#define CS4WCR 0xA4FD0030UL
47#define CS5AWCR 0xA4FD0034UL
48#define CS5BWCR 0xA4FD0038UL
49#define CS6AWCR 0xA4FD003CUL
50#define CS6BWCR 0xA4FD0040UL
51
52
53/* usb */
54
55#define PORT_UTRCTL 0xA405012CUL
56#define PORT_UCLKCR_W 0xA40A0008UL
57
58#define INTC_ICR0 0xA414FEE0UL
59#define INTC_ICR1 0xA4140010UL
60#define INTC_ICR2 0xA4140012UL
61
62/* MTD */
63
64#define MPR2_MTD_BOOTLOADER_SIZE 0x00060000UL
65#define MPR2_MTD_KERNEL_SIZE 0x00200000UL
66
67#endif /* __ASM_SH_MAGICPANELR2_H */
diff --git a/include/asm-sh/mc146818rtc.h b/include/asm-sh/mc146818rtc.h
deleted file mode 100644
index 0aee96a9733..00000000000
--- a/include/asm-sh/mc146818rtc.h
+++ /dev/null
@@ -1,7 +0,0 @@
1/*
2 * Machine dependent access functions for RTC registers.
3 */
4#ifndef _ASM_MC146818RTC_H
5#define _ASM_MC146818RTC_H
6
7#endif /* _ASM_MC146818RTC_H */
diff --git a/include/asm-sh/microdev.h b/include/asm-sh/microdev.h
deleted file mode 100644
index 1aed15856e1..00000000000
--- a/include/asm-sh/microdev.h
+++ /dev/null
@@ -1,80 +0,0 @@
1/*
2 * linux/include/asm-sh/microdev.h
3 *
4 * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com)
5 *
6 * Definitions for the SuperH SH4-202 MicroDev board.
7 *
8 * May be copied or modified under the terms of the GNU General Public
9 * License. See linux/COPYING for more information.
10 */
11#ifndef __ASM_SH_MICRODEV_H
12#define __ASM_SH_MICRODEV_H
13
14extern void init_microdev_irq(void);
15extern void microdev_print_fpga_intc_status(void);
16
17/*
18 * The following are useful macros for manipulating the interrupt
19 * controller (INTC) on the CPU-board FPGA. should be noted that there
20 * is an INTC on the FPGA, and a separate INTC on the SH4-202 core -
21 * these are two different things, both of which need to be prorammed to
22 * correctly route - unfortunately, they have the same name and
23 * abbreviations!
24 */
25#define MICRODEV_FPGA_INTC_BASE 0xa6110000ul /* INTC base address on CPU-board FPGA */
26#define MICRODEV_FPGA_INTENB_REG (MICRODEV_FPGA_INTC_BASE+0ul) /* Interrupt Enable Register on INTC on CPU-board FPGA */
27#define MICRODEV_FPGA_INTDSB_REG (MICRODEV_FPGA_INTC_BASE+8ul) /* Interrupt Disable Register on INTC on CPU-board FPGA */
28#define MICRODEV_FPGA_INTC_MASK(n) (1ul<<(n)) /* Interrupt mask to enable/disable INTC in CPU-board FPGA */
29#define MICRODEV_FPGA_INTPRI_REG(n) (MICRODEV_FPGA_INTC_BASE+0x10+((n)/8)*8)/* Interrupt Priority Register on INTC on CPU-board FPGA */
30#define MICRODEV_FPGA_INTPRI_LEVEL(n,x) ((x)<<(((n)%8)*4)) /* MICRODEV_FPGA_INTPRI_LEVEL(int_number, int_level) */
31#define MICRODEV_FPGA_INTPRI_MASK(n) (MICRODEV_FPGA_INTPRI_LEVEL((n),0xful)) /* Interrupt Priority Mask on INTC on CPU-board FPGA */
32#define MICRODEV_FPGA_INTSRC_REG (MICRODEV_FPGA_INTC_BASE+0x30ul) /* Interrupt Source Register on INTC on CPU-board FPGA */
33#define MICRODEV_FPGA_INTREQ_REG (MICRODEV_FPGA_INTC_BASE+0x38ul) /* Interrupt Request Register on INTC on CPU-board FPGA */
34
35
36/*
37 * The following are the IRQ numbers for the Linux Kernel for external
38 * interrupts. i.e. the numbers seen by 'cat /proc/interrupt'.
39 */
40#define MICRODEV_LINUX_IRQ_KEYBOARD 1 /* SuperIO Keyboard */
41#define MICRODEV_LINUX_IRQ_SERIAL1 2 /* SuperIO Serial #1 */
42#define MICRODEV_LINUX_IRQ_ETHERNET 3 /* on-board Ethnernet */
43#define MICRODEV_LINUX_IRQ_SERIAL2 4 /* SuperIO Serial #2 */
44#define MICRODEV_LINUX_IRQ_USB_HC 7 /* on-board USB HC */
45#define MICRODEV_LINUX_IRQ_MOUSE 12 /* SuperIO PS/2 Mouse */
46#define MICRODEV_LINUX_IRQ_IDE2 13 /* SuperIO IDE #2 */
47#define MICRODEV_LINUX_IRQ_IDE1 14 /* SuperIO IDE #1 */
48
49/*
50 * The following are the IRQ numbers for the INTC on the FPGA for
51 * external interrupts. i.e. the bits in the INTC registers in the
52 * FPGA.
53 */
54#define MICRODEV_FPGA_IRQ_KEYBOARD 1 /* SuperIO Keyboard */
55#define MICRODEV_FPGA_IRQ_SERIAL1 3 /* SuperIO Serial #1 */
56#define MICRODEV_FPGA_IRQ_SERIAL2 4 /* SuperIO Serial #2 */
57#define MICRODEV_FPGA_IRQ_MOUSE 12 /* SuperIO PS/2 Mouse */
58#define MICRODEV_FPGA_IRQ_IDE1 14 /* SuperIO IDE #1 */
59#define MICRODEV_FPGA_IRQ_IDE2 15 /* SuperIO IDE #2 */
60#define MICRODEV_FPGA_IRQ_USB_HC 16 /* on-board USB HC */
61#define MICRODEV_FPGA_IRQ_ETHERNET 18 /* on-board Ethnernet */
62
63#define MICRODEV_IRQ_PCI_INTA 8
64#define MICRODEV_IRQ_PCI_INTB 9
65#define MICRODEV_IRQ_PCI_INTC 10
66#define MICRODEV_IRQ_PCI_INTD 11
67
68#define __IO_PREFIX microdev
69#include <asm/io_generic.h>
70
71#if defined(CONFIG_PCI)
72unsigned char microdev_pci_inb(unsigned long port);
73unsigned short microdev_pci_inw(unsigned long port);
74unsigned long microdev_pci_inl(unsigned long port);
75void microdev_pci_outb(unsigned char data, unsigned long port);
76void microdev_pci_outw(unsigned short data, unsigned long port);
77void microdev_pci_outl(unsigned long data, unsigned long port);
78#endif
79
80#endif /* __ASM_SH_MICRODEV_H */
diff --git a/include/asm-sh/migor.h b/include/asm-sh/migor.h
deleted file mode 100644
index 2329363afdc..00000000000
--- a/include/asm-sh/migor.h
+++ /dev/null
@@ -1,58 +0,0 @@
1#ifndef __ASM_SH_MIGOR_H
2#define __ASM_SH_MIGOR_H
3
4/*
5 * linux/include/asm-sh/migor.h
6 *
7 * Copyright (C) 2008 Renesas Solutions
8 *
9 * Portions Copyright (C) 2007 Nobuhiro Iwamatsu
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 *
15 */
16#include <asm/addrspace.h>
17
18/* GPIO */
19#define MSTPCR0 0xa4150030
20#define MSTPCR1 0xa4150034
21#define MSTPCR2 0xa4150038
22
23#define PORT_PACR 0xa4050100
24#define PORT_PDCR 0xa4050106
25#define PORT_PECR 0xa4050108
26#define PORT_PHCR 0xa405010e
27#define PORT_PJCR 0xa4050110
28#define PORT_PKCR 0xa4050112
29#define PORT_PLCR 0xa4050114
30#define PORT_PMCR 0xa4050116
31#define PORT_PRCR 0xa405011c
32#define PORT_PWCR 0xa4050146
33#define PORT_PXCR 0xa4050148
34#define PORT_PYCR 0xa405014a
35#define PORT_PZCR 0xa405014c
36#define PORT_PADR 0xa4050120
37#define PORT_PWDR 0xa4050166
38
39#define PORT_HIZCRA 0xa4050158
40#define PORT_HIZCRC 0xa405015c
41
42#define PORT_MSELCRB 0xa4050182
43
44#define MSTPCR1 0xa4150034
45#define MSTPCR2 0xa4150038
46
47#define PORT_PSELA 0xa405014e
48#define PORT_PSELB 0xa4050150
49#define PORT_PSELC 0xa4050152
50#define PORT_PSELD 0xa4050154
51
52#define PORT_HIZCRA 0xa4050158
53#define PORT_HIZCRB 0xa405015a
54#define PORT_HIZCRC 0xa405015c
55
56#define BSC_CS6ABCR 0xfec1001c
57
58#endif /* __ASM_SH_MIGOR_H */
diff --git a/include/asm-sh/mman.h b/include/asm-sh/mman.h
deleted file mode 100644
index 156eb0225cf..00000000000
--- a/include/asm-sh/mman.h
+++ /dev/null
@@ -1,17 +0,0 @@
1#ifndef __ASM_SH_MMAN_H
2#define __ASM_SH_MMAN_H
3
4#include <asm-generic/mman.h>
5
6#define MAP_GROWSDOWN 0x0100 /* stack-like segment */
7#define MAP_DENYWRITE 0x0800 /* ETXTBSY */
8#define MAP_EXECUTABLE 0x1000 /* mark it as an executable */
9#define MAP_LOCKED 0x2000 /* pages are locked */
10#define MAP_NORESERVE 0x4000 /* don't check for reservations */
11#define MAP_POPULATE 0x8000 /* populate (prefault) page tables */
12#define MAP_NONBLOCK 0x10000 /* do not block on IO */
13
14#define MCL_CURRENT 1 /* lock all current mappings */
15#define MCL_FUTURE 2 /* lock all future mappings */
16
17#endif /* __ASM_SH_MMAN_H */
diff --git a/include/asm-sh/mmu.h b/include/asm-sh/mmu.h
deleted file mode 100644
index eb0358c097d..00000000000
--- a/include/asm-sh/mmu.h
+++ /dev/null
@@ -1,72 +0,0 @@
1#ifndef __MMU_H
2#define __MMU_H
3
4/* Default "unsigned long" context */
5typedef unsigned long mm_context_id_t[NR_CPUS];
6
7typedef struct {
8#ifdef CONFIG_MMU
9 mm_context_id_t id;
10 void *vdso;
11#else
12 struct vm_list_struct *vmlist;
13 unsigned long end_brk;
14#endif
15} mm_context_t;
16
17/*
18 * Privileged Space Mapping Buffer (PMB) definitions
19 */
20#define PMB_PASCR 0xff000070
21#define PMB_IRMCR 0xff000078
22
23#define PMB_ADDR 0xf6100000
24#define PMB_DATA 0xf7100000
25#define PMB_ENTRY_MAX 16
26#define PMB_E_MASK 0x0000000f
27#define PMB_E_SHIFT 8
28
29#define PMB_SZ_16M 0x00000000
30#define PMB_SZ_64M 0x00000010
31#define PMB_SZ_128M 0x00000080
32#define PMB_SZ_512M 0x00000090
33#define PMB_SZ_MASK PMB_SZ_512M
34#define PMB_C 0x00000008
35#define PMB_WT 0x00000001
36#define PMB_UB 0x00000200
37#define PMB_V 0x00000100
38
39#define PMB_NO_ENTRY (-1)
40
41struct pmb_entry;
42
43struct pmb_entry {
44 unsigned long vpn;
45 unsigned long ppn;
46 unsigned long flags;
47
48 /*
49 * 0 .. NR_PMB_ENTRIES for specific entry selection, or
50 * PMB_NO_ENTRY to search for a free one
51 */
52 int entry;
53
54 struct pmb_entry *next;
55 /* Adjacent entry link for contiguous multi-entry mappings */
56 struct pmb_entry *link;
57};
58
59/* arch/sh/mm/pmb.c */
60int __set_pmb_entry(unsigned long vpn, unsigned long ppn,
61 unsigned long flags, int *entry);
62int set_pmb_entry(struct pmb_entry *pmbe);
63void clear_pmb_entry(struct pmb_entry *pmbe);
64struct pmb_entry *pmb_alloc(unsigned long vpn, unsigned long ppn,
65 unsigned long flags);
66void pmb_free(struct pmb_entry *pmbe);
67long pmb_remap(unsigned long virt, unsigned long phys,
68 unsigned long size, unsigned long flags);
69void pmb_unmap(unsigned long addr);
70
71#endif /* __MMU_H */
72
diff --git a/include/asm-sh/mmu_context.h b/include/asm-sh/mmu_context.h
deleted file mode 100644
index 87e812f68bb..00000000000
--- a/include/asm-sh/mmu_context.h
+++ /dev/null
@@ -1,184 +0,0 @@
1/*
2 * Copyright (C) 1999 Niibe Yutaka
3 * Copyright (C) 2003 - 2007 Paul Mundt
4 *
5 * ASID handling idea taken from MIPS implementation.
6 */
7#ifndef __ASM_SH_MMU_CONTEXT_H
8#define __ASM_SH_MMU_CONTEXT_H
9
10#ifdef __KERNEL__
11#include <asm/cpu/mmu_context.h>
12#include <asm/tlbflush.h>
13#include <asm/uaccess.h>
14#include <asm/io.h>
15#include <asm-generic/mm_hooks.h>
16
17/*
18 * The MMU "context" consists of two things:
19 * (a) TLB cache version (or round, cycle whatever expression you like)
20 * (b) ASID (Address Space IDentifier)
21 */
22#define MMU_CONTEXT_ASID_MASK 0x000000ff
23#define MMU_CONTEXT_VERSION_MASK 0xffffff00
24#define MMU_CONTEXT_FIRST_VERSION 0x00000100
25#define NO_CONTEXT 0
26
27/* ASID is 8-bit value, so it can't be 0x100 */
28#define MMU_NO_ASID 0x100
29
30#ifdef CONFIG_MMU
31#define asid_cache(cpu) (cpu_data[cpu].asid_cache)
32#define cpu_context(cpu, mm) ((mm)->context.id[cpu])
33
34#define cpu_asid(cpu, mm) \
35 (cpu_context((cpu), (mm)) & MMU_CONTEXT_ASID_MASK)
36
37/*
38 * Virtual Page Number mask
39 */
40#define MMU_VPN_MASK 0xfffff000
41
42#if defined(CONFIG_SUPERH32)
43#include "mmu_context_32.h"
44#else
45#include "mmu_context_64.h"
46#endif
47
48/*
49 * Get MMU context if needed.
50 */
51static inline void get_mmu_context(struct mm_struct *mm, unsigned int cpu)
52{
53 unsigned long asid = asid_cache(cpu);
54
55 /* Check if we have old version of context. */
56 if (((cpu_context(cpu, mm) ^ asid) & MMU_CONTEXT_VERSION_MASK) == 0)
57 /* It's up to date, do nothing */
58 return;
59
60 /* It's old, we need to get new context with new version. */
61 if (!(++asid & MMU_CONTEXT_ASID_MASK)) {
62 /*
63 * We exhaust ASID of this version.
64 * Flush all TLB and start new cycle.
65 */
66 flush_tlb_all();
67
68#ifdef CONFIG_SUPERH64
69 /*
70 * The SH-5 cache uses the ASIDs, requiring both the I and D
71 * cache to be flushed when the ASID is exhausted. Weak.
72 */
73 flush_cache_all();
74#endif
75
76 /*
77 * Fix version; Note that we avoid version #0
78 * to distingush NO_CONTEXT.
79 */
80 if (!asid)
81 asid = MMU_CONTEXT_FIRST_VERSION;
82 }
83
84 cpu_context(cpu, mm) = asid_cache(cpu) = asid;
85}
86
87/*
88 * Initialize the context related info for a new mm_struct
89 * instance.
90 */
91static inline int init_new_context(struct task_struct *tsk,
92 struct mm_struct *mm)
93{
94 int i;
95
96 for (i = 0; i < num_online_cpus(); i++)
97 cpu_context(i, mm) = NO_CONTEXT;
98
99 return 0;
100}
101
102/*
103 * After we have set current->mm to a new value, this activates
104 * the context for the new mm so we see the new mappings.
105 */
106static inline void activate_context(struct mm_struct *mm, unsigned int cpu)
107{
108 get_mmu_context(mm, cpu);
109 set_asid(cpu_asid(cpu, mm));
110}
111
112static inline void switch_mm(struct mm_struct *prev,
113 struct mm_struct *next,
114 struct task_struct *tsk)
115{
116 unsigned int cpu = smp_processor_id();
117
118 if (likely(prev != next)) {
119 cpu_set(cpu, next->cpu_vm_mask);
120 set_TTB(next->pgd);
121 activate_context(next, cpu);
122 } else
123 if (!cpu_test_and_set(cpu, next->cpu_vm_mask))
124 activate_context(next, cpu);
125}
126#else
127#define get_mmu_context(mm) do { } while (0)
128#define init_new_context(tsk,mm) (0)
129#define destroy_context(mm) do { } while (0)
130#define set_asid(asid) do { } while (0)
131#define get_asid() (0)
132#define cpu_asid(cpu, mm) ({ (void)cpu; 0; })
133#define switch_and_save_asid(asid) (0)
134#define set_TTB(pgd) do { } while (0)
135#define get_TTB() (0)
136#define activate_context(mm,cpu) do { } while (0)
137#define switch_mm(prev,next,tsk) do { } while (0)
138#endif /* CONFIG_MMU */
139
140#define activate_mm(prev, next) switch_mm((prev),(next),NULL)
141#define deactivate_mm(tsk,mm) do { } while (0)
142#define enter_lazy_tlb(mm,tsk) do { } while (0)
143
144#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4)
145/*
146 * If this processor has an MMU, we need methods to turn it off/on ..
147 * paging_init() will also have to be updated for the processor in
148 * question.
149 */
150static inline void enable_mmu(void)
151{
152 unsigned int cpu = smp_processor_id();
153
154 /* Enable MMU */
155 ctrl_outl(MMU_CONTROL_INIT, MMUCR);
156 ctrl_barrier();
157
158 if (asid_cache(cpu) == NO_CONTEXT)
159 asid_cache(cpu) = MMU_CONTEXT_FIRST_VERSION;
160
161 set_asid(asid_cache(cpu) & MMU_CONTEXT_ASID_MASK);
162}
163
164static inline void disable_mmu(void)
165{
166 unsigned long cr;
167
168 cr = ctrl_inl(MMUCR);
169 cr &= ~MMU_CONTROL_INIT;
170 ctrl_outl(cr, MMUCR);
171
172 ctrl_barrier();
173}
174#else
175/*
176 * MMU control handlers for processors lacking memory
177 * management hardware.
178 */
179#define enable_mmu() do { } while (0)
180#define disable_mmu() do { } while (0)
181#endif
182
183#endif /* __KERNEL__ */
184#endif /* __ASM_SH_MMU_CONTEXT_H */
diff --git a/include/asm-sh/mmu_context_32.h b/include/asm-sh/mmu_context_32.h
deleted file mode 100644
index f4f9aebd68b..00000000000
--- a/include/asm-sh/mmu_context_32.h
+++ /dev/null
@@ -1,47 +0,0 @@
1#ifndef __ASM_SH_MMU_CONTEXT_32_H
2#define __ASM_SH_MMU_CONTEXT_32_H
3
4/*
5 * Destroy context related info for an mm_struct that is about
6 * to be put to rest.
7 */
8static inline void destroy_context(struct mm_struct *mm)
9{
10 /* Do nothing */
11}
12
13static inline void set_asid(unsigned long asid)
14{
15 unsigned long __dummy;
16
17 __asm__ __volatile__ ("mov.l %2, %0\n\t"
18 "and %3, %0\n\t"
19 "or %1, %0\n\t"
20 "mov.l %0, %2"
21 : "=&r" (__dummy)
22 : "r" (asid), "m" (__m(MMU_PTEH)),
23 "r" (0xffffff00));
24}
25
26static inline unsigned long get_asid(void)
27{
28 unsigned long asid;
29
30 __asm__ __volatile__ ("mov.l %1, %0"
31 : "=r" (asid)
32 : "m" (__m(MMU_PTEH)));
33 asid &= MMU_CONTEXT_ASID_MASK;
34 return asid;
35}
36
37/* MMU_TTB is used for optimizing the fault handling. */
38static inline void set_TTB(pgd_t *pgd)
39{
40 ctrl_outl((unsigned long)pgd, MMU_TTB);
41}
42
43static inline pgd_t *get_TTB(void)
44{
45 return (pgd_t *)ctrl_inl(MMU_TTB);
46}
47#endif /* __ASM_SH_MMU_CONTEXT_32_H */
diff --git a/include/asm-sh/mmu_context_64.h b/include/asm-sh/mmu_context_64.h
deleted file mode 100644
index 9649f1c07ca..00000000000
--- a/include/asm-sh/mmu_context_64.h
+++ /dev/null
@@ -1,78 +0,0 @@
1#ifndef __ASM_SH_MMU_CONTEXT_64_H
2#define __ASM_SH_MMU_CONTEXT_64_H
3
4/*
5 * sh64-specific mmu_context interface.
6 *
7 * Copyright (C) 2000, 2001 Paolo Alberelli
8 * Copyright (C) 2003 - 2007 Paul Mundt
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
12 * for more details.
13 */
14#include <asm/cpu/registers.h>
15#include <asm/cacheflush.h>
16
17#define SR_ASID_MASK 0xffffffffff00ffffULL
18#define SR_ASID_SHIFT 16
19
20/*
21 * Destroy context related info for an mm_struct that is about
22 * to be put to rest.
23 */
24static inline void destroy_context(struct mm_struct *mm)
25{
26 /* Well, at least free TLB entries */
27 flush_tlb_mm(mm);
28}
29
30static inline unsigned long get_asid(void)
31{
32 unsigned long long sr;
33
34 asm volatile ("getcon " __SR ", %0\n\t"
35 : "=r" (sr));
36
37 sr = (sr >> SR_ASID_SHIFT) & MMU_CONTEXT_ASID_MASK;
38 return (unsigned long) sr;
39}
40
41/* Set ASID into SR */
42static inline void set_asid(unsigned long asid)
43{
44 unsigned long long sr, pc;
45
46 asm volatile ("getcon " __SR ", %0" : "=r" (sr));
47
48 sr = (sr & SR_ASID_MASK) | (asid << SR_ASID_SHIFT);
49
50 /*
51 * It is possible that this function may be inlined and so to avoid
52 * the assembler reporting duplicate symbols we make use of the
53 * gas trick of generating symbols using numerics and forward
54 * reference.
55 */
56 asm volatile ("movi 1, %1\n\t"
57 "shlli %1, 28, %1\n\t"
58 "or %0, %1, %1\n\t"
59 "putcon %1, " __SR "\n\t"
60 "putcon %0, " __SSR "\n\t"
61 "movi 1f, %1\n\t"
62 "ori %1, 1 , %1\n\t"
63 "putcon %1, " __SPC "\n\t"
64 "rte\n"
65 "1:\n\t"
66 : "=r" (sr), "=r" (pc) : "0" (sr));
67}
68
69/* arch/sh/kernel/cpu/sh5/entry.S */
70extern unsigned long switch_and_save_asid(unsigned long new_asid);
71
72/* No spare register to twiddle, so use a software cache */
73extern pgd_t *mmu_pdtp_cache;
74
75#define set_TTB(pgd) (mmu_pdtp_cache = (pgd))
76#define get_TTB() (mmu_pdtp_cache)
77
78#endif /* __ASM_SH_MMU_CONTEXT_64_H */
diff --git a/include/asm-sh/mmzone.h b/include/asm-sh/mmzone.h
deleted file mode 100644
index 2969253c404..00000000000
--- a/include/asm-sh/mmzone.h
+++ /dev/null
@@ -1,48 +0,0 @@
1#ifndef __ASM_SH_MMZONE_H
2#define __ASM_SH_MMZONE_H
3
4#ifdef __KERNEL__
5
6#ifdef CONFIG_NEED_MULTIPLE_NODES
7extern struct pglist_data *node_data[];
8#define NODE_DATA(nid) (node_data[nid])
9
10#define node_start_pfn(nid) (NODE_DATA(nid)->node_start_pfn)
11#define node_end_pfn(nid) (NODE_DATA(nid)->node_start_pfn + \
12 NODE_DATA(nid)->node_spanned_pages)
13
14static inline int pfn_to_nid(unsigned long pfn)
15{
16 int nid;
17
18 for (nid = 0; nid < MAX_NUMNODES; nid++)
19 if (pfn >= node_start_pfn(nid) && pfn <= node_end_pfn(nid))
20 break;
21
22 return nid;
23}
24
25static inline struct pglist_data *pfn_to_pgdat(unsigned long pfn)
26{
27 return NODE_DATA(pfn_to_nid(pfn));
28}
29
30/* arch/sh/mm/numa.c */
31void __init setup_bootmem_node(int nid, unsigned long start, unsigned long end);
32#else
33static inline void
34setup_bootmem_node(int nid, unsigned long start, unsigned long end)
35{
36}
37#endif /* CONFIG_NEED_MULTIPLE_NODES */
38
39/* Platform specific mem init */
40void __init plat_mem_setup(void);
41
42/* arch/sh/kernel/setup.c */
43void __init setup_bootmem_allocator(unsigned long start_pfn);
44void __init __add_active_range(unsigned int nid, unsigned long start_pfn,
45 unsigned long end_pfn);
46
47#endif /* __KERNEL__ */
48#endif /* __ASM_SH_MMZONE_H */
diff --git a/include/asm-sh/module.h b/include/asm-sh/module.h
deleted file mode 100644
index 46eccd33166..00000000000
--- a/include/asm-sh/module.h
+++ /dev/null
@@ -1,44 +0,0 @@
1#ifndef _ASM_SH_MODULE_H
2#define _ASM_SH_MODULE_H
3
4/*
5 * This file contains the SH architecture specific module code.
6 */
7
8struct mod_arch_specific {
9 /* Nothing to see here .. */
10};
11
12#define Elf_Shdr Elf32_Shdr
13#define Elf_Sym Elf32_Sym
14#define Elf_Ehdr Elf32_Ehdr
15
16#ifdef CONFIG_CPU_LITTLE_ENDIAN
17# ifdef CONFIG_CPU_SH2
18# define MODULE_PROC_FAMILY "SH2LE "
19# elif defined CONFIG_CPU_SH3
20# define MODULE_PROC_FAMILY "SH3LE "
21# elif defined CONFIG_CPU_SH4
22# define MODULE_PROC_FAMILY "SH4LE "
23# elif defined CONFIG_CPU_SH5
24# define MODULE_PROC_FAMILY "SH5LE "
25# else
26# error unknown processor family
27# endif
28#else
29# ifdef CONFIG_CPU_SH2
30# define MODULE_PROC_FAMILY "SH2BE "
31# elif defined CONFIG_CPU_SH3
32# define MODULE_PROC_FAMILY "SH3BE "
33# elif defined CONFIG_CPU_SH4
34# define MODULE_PROC_FAMILY "SH4BE "
35# elif defined CONFIG_CPU_SH5
36# define MODULE_PROC_FAMILY "SH5BE "
37# else
38# error unknown processor family
39# endif
40#endif
41
42#define MODULE_ARCH_VERMAGIC MODULE_PROC_FAMILY
43
44#endif /* _ASM_SH_MODULE_H */
diff --git a/include/asm-sh/msgbuf.h b/include/asm-sh/msgbuf.h
deleted file mode 100644
index 517432343fb..00000000000
--- a/include/asm-sh/msgbuf.h
+++ /dev/null
@@ -1,31 +0,0 @@
1#ifndef __ASM_SH_MSGBUF_H
2#define __ASM_SH_MSGBUF_H
3
4/*
5 * The msqid64_ds structure for i386 architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 64-bit time_t to solve y2038 problem
11 * - 2 miscellaneous 32-bit values
12 */
13
14struct msqid64_ds {
15 struct ipc64_perm msg_perm;
16 __kernel_time_t msg_stime; /* last msgsnd time */
17 unsigned long __unused1;
18 __kernel_time_t msg_rtime; /* last msgrcv time */
19 unsigned long __unused2;
20 __kernel_time_t msg_ctime; /* last change time */
21 unsigned long __unused3;
22 unsigned long msg_cbytes; /* current number of bytes on queue */
23 unsigned long msg_qnum; /* number of messages in queue */
24 unsigned long msg_qbytes; /* max number of bytes on queue */
25 __kernel_pid_t msg_lspid; /* pid of last msgsnd */
26 __kernel_pid_t msg_lrpid; /* last receive pid */
27 unsigned long __unused4;
28 unsigned long __unused5;
29};
30
31#endif /* __ASM_SH_MSGBUF_H */
diff --git a/include/asm-sh/mutex.h b/include/asm-sh/mutex.h
deleted file mode 100644
index 458c1f7fbc1..00000000000
--- a/include/asm-sh/mutex.h
+++ /dev/null
@@ -1,9 +0,0 @@
1/*
2 * Pull in the generic implementation for the mutex fastpath.
3 *
4 * TODO: implement optimized primitives instead, or leave the generic
5 * implementation in place, or pick the atomic_xchg() based generic
6 * implementation. (see asm-generic/mutex-xchg.h for details)
7 */
8
9#include <asm-generic/mutex-dec.h>
diff --git a/include/asm-sh/page.h b/include/asm-sh/page.h
deleted file mode 100644
index 5dc01d2fcc4..00000000000
--- a/include/asm-sh/page.h
+++ /dev/null
@@ -1,181 +0,0 @@
1#ifndef __ASM_SH_PAGE_H
2#define __ASM_SH_PAGE_H
3
4/*
5 * Copyright (C) 1999 Niibe Yutaka
6 */
7
8#include <linux/const.h>
9
10/* PAGE_SHIFT determines the page size */
11#if defined(CONFIG_PAGE_SIZE_4KB)
12# define PAGE_SHIFT 12
13#elif defined(CONFIG_PAGE_SIZE_8KB)
14# define PAGE_SHIFT 13
15#elif defined(CONFIG_PAGE_SIZE_64KB)
16# define PAGE_SHIFT 16
17#else
18# error "Bogus kernel page size?"
19#endif
20
21#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
22#define PAGE_MASK (~(PAGE_SIZE-1))
23#define PTE_MASK PAGE_MASK
24
25#if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
26#define HPAGE_SHIFT 16
27#elif defined(CONFIG_HUGETLB_PAGE_SIZE_256K)
28#define HPAGE_SHIFT 18
29#elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
30#define HPAGE_SHIFT 20
31#elif defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
32#define HPAGE_SHIFT 22
33#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64MB)
34#define HPAGE_SHIFT 26
35#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512MB)
36#define HPAGE_SHIFT 29
37#endif
38
39#ifdef CONFIG_HUGETLB_PAGE
40#define HPAGE_SIZE (1UL << HPAGE_SHIFT)
41#define HPAGE_MASK (~(HPAGE_SIZE-1))
42#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT-PAGE_SHIFT)
43#endif
44
45#ifndef __ASSEMBLY__
46
47extern unsigned long shm_align_mask;
48extern unsigned long max_low_pfn, min_low_pfn;
49extern unsigned long memory_start, memory_end;
50
51extern void clear_page(void *to);
52extern void copy_page(void *to, void *from);
53
54#if !defined(CONFIG_CACHE_OFF) && defined(CONFIG_MMU) && \
55 (defined(CONFIG_CPU_SH5) || defined(CONFIG_CPU_SH4) || \
56 defined(CONFIG_SH7705_CACHE_32KB))
57struct page;
58struct vm_area_struct;
59extern void clear_user_page(void *to, unsigned long address, struct page *page);
60extern void copy_user_page(void *to, void *from, unsigned long address,
61 struct page *page);
62#if defined(CONFIG_CPU_SH4)
63extern void copy_user_highpage(struct page *to, struct page *from,
64 unsigned long vaddr, struct vm_area_struct *vma);
65#define __HAVE_ARCH_COPY_USER_HIGHPAGE
66#endif
67#else
68#define clear_user_page(page, vaddr, pg) clear_page(page)
69#define copy_user_page(to, from, vaddr, pg) copy_page(to, from)
70#endif
71
72/*
73 * These are used to make use of C type-checking..
74 */
75#ifdef CONFIG_X2TLB
76typedef struct { unsigned long pte_low, pte_high; } pte_t;
77typedef struct { unsigned long long pgprot; } pgprot_t;
78typedef struct { unsigned long long pgd; } pgd_t;
79#define pte_val(x) \
80 ((x).pte_low | ((unsigned long long)(x).pte_high << 32))
81#define __pte(x) \
82 ({ pte_t __pte = {(x), ((unsigned long long)(x)) >> 32}; __pte; })
83#elif defined(CONFIG_SUPERH32)
84typedef struct { unsigned long pte_low; } pte_t;
85typedef struct { unsigned long pgprot; } pgprot_t;
86typedef struct { unsigned long pgd; } pgd_t;
87#define pte_val(x) ((x).pte_low)
88#define __pte(x) ((pte_t) { (x) } )
89#else
90typedef struct { unsigned long long pte_low; } pte_t;
91typedef struct { unsigned long pgprot; } pgprot_t;
92typedef struct { unsigned long pgd; } pgd_t;
93#define pte_val(x) ((x).pte_low)
94#define __pte(x) ((pte_t) { (x) } )
95#endif
96
97#define pgd_val(x) ((x).pgd)
98#define pgprot_val(x) ((x).pgprot)
99
100#define __pgd(x) ((pgd_t) { (x) } )
101#define __pgprot(x) ((pgprot_t) { (x) } )
102
103typedef struct page *pgtable_t;
104
105#endif /* !__ASSEMBLY__ */
106
107/*
108 * __MEMORY_START and SIZE are the physical addresses and size of RAM.
109 */
110#define __MEMORY_START CONFIG_MEMORY_START
111#define __MEMORY_SIZE CONFIG_MEMORY_SIZE
112
113/*
114 * PAGE_OFFSET is the virtual address of the start of kernel address
115 * space.
116 */
117#define PAGE_OFFSET CONFIG_PAGE_OFFSET
118
119/*
120 * Virtual to physical RAM address translation.
121 *
122 * In 29 bit mode, the physical offset of RAM from address 0 is visible in
123 * the kernel virtual address space, and thus we don't have to take
124 * this into account when translating. However in 32 bit mode this offset
125 * is not visible (it is part of the PMB mapping) and so needs to be
126 * added or subtracted as required.
127 */
128#ifdef CONFIG_32BIT
129#define __pa(x) ((unsigned long)(x)-PAGE_OFFSET+__MEMORY_START)
130#define __va(x) ((void *)((unsigned long)(x)+PAGE_OFFSET-__MEMORY_START))
131#else
132#define __pa(x) ((unsigned long)(x)-PAGE_OFFSET)
133#define __va(x) ((void *)((unsigned long)(x)+PAGE_OFFSET))
134#endif
135
136#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
137#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
138
139/*
140 * PFN = physical frame number (ie PFN 0 == physical address 0)
141 * PFN_START is the PFN of the first page of RAM. By defining this we
142 * don't have struct page entries for the portion of address space
143 * between physical address 0 and the start of RAM.
144 */
145#define PFN_START (__MEMORY_START >> PAGE_SHIFT)
146#define ARCH_PFN_OFFSET (PFN_START)
147#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
148#ifdef CONFIG_FLATMEM
149#define pfn_valid(pfn) ((pfn) >= min_low_pfn && (pfn) < max_low_pfn)
150#endif
151#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
152
153#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
154 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
155
156#include <asm-generic/memory_model.h>
157#include <asm-generic/page.h>
158
159/* vDSO support */
160#ifdef CONFIG_VSYSCALL
161#define __HAVE_ARCH_GATE_AREA
162#endif
163
164/*
165 * Some drivers need to perform DMA into kmalloc'ed buffers
166 * and so we have to increase the kmalloc minalign for this.
167 */
168#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES
169
170#ifdef CONFIG_SUPERH64
171/*
172 * While BYTES_PER_WORD == 4 on the current sh64 ABI, GCC will still
173 * happily generate {ld/st}.q pairs, requiring us to have 8-byte
174 * alignment to avoid traps. The kmalloc alignment is gauranteed by
175 * virtue of L1_CACHE_BYTES, requiring this to only be special cased
176 * for slab caches.
177 */
178#define ARCH_SLAB_MINALIGN 8
179#endif
180
181#endif /* __ASM_SH_PAGE_H */
diff --git a/include/asm-sh/param.h b/include/asm-sh/param.h
deleted file mode 100644
index ae245afdfd6..00000000000
--- a/include/asm-sh/param.h
+++ /dev/null
@@ -1,22 +0,0 @@
1#ifndef __ASM_SH_PARAM_H
2#define __ASM_SH_PARAM_H
3
4#ifdef __KERNEL__
5# define HZ CONFIG_HZ
6# define USER_HZ 100 /* User interfaces are in "ticks" */
7# define CLOCKS_PER_SEC (USER_HZ) /* frequency at which times() counts */
8#endif
9
10#ifndef HZ
11#define HZ 100
12#endif
13
14#define EXEC_PAGESIZE 4096
15
16#ifndef NOGROUP
17#define NOGROUP (-1)
18#endif
19
20#define MAXHOSTNAMELEN 64 /* max length of hostname */
21
22#endif /* __ASM_SH_PARAM_H */
diff --git a/include/asm-sh/parport.h b/include/asm-sh/parport.h
deleted file mode 100644
index f67ba60a2ac..00000000000
--- a/include/asm-sh/parport.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * Copyright (C) 1999, 2000 Tim Waugh <tim@cyberelk.demon.co.uk>
3 *
4 * This file should only be included by drivers/parport/parport_pc.c.
5 */
6#ifndef __ASM_SH_PARPORT_H
7#define __ASM_SH_PARPORT_H
8
9static int __devinit parport_pc_find_isa_ports(int autoirq, int autodma);
10
11static int __devinit parport_pc_find_nonpci_ports(int autoirq, int autodma)
12{
13 return parport_pc_find_isa_ports(autoirq, autodma);
14}
15
16#endif /* __ASM_SH_PARPORT_H */
diff --git a/include/asm-sh/pci.h b/include/asm-sh/pci.h
deleted file mode 100644
index df1d383e18a..00000000000
--- a/include/asm-sh/pci.h
+++ /dev/null
@@ -1,144 +0,0 @@
1#ifndef __ASM_SH_PCI_H
2#define __ASM_SH_PCI_H
3
4#ifdef __KERNEL__
5
6#include <linux/dma-mapping.h>
7
8/* Can be used to override the logic in pci_scan_bus for skipping
9 already-configured bus numbers - to be used for buggy BIOSes
10 or architectures with incomplete PCI setup by the loader */
11
12#define pcibios_assign_all_busses() 1
13#define pcibios_scan_all_fns(a, b) 0
14
15/*
16 * A board can define one or more PCI channels that represent built-in (or
17 * external) PCI controllers.
18 */
19struct pci_channel {
20 struct pci_ops *pci_ops;
21 struct resource *io_resource;
22 struct resource *mem_resource;
23 int first_devfn;
24 int last_devfn;
25};
26
27/*
28 * Each board initializes this array and terminates it with a NULL entry.
29 */
30extern struct pci_channel board_pci_channels[];
31
32#define PCIBIOS_MIN_IO board_pci_channels->io_resource->start
33#define PCIBIOS_MIN_MEM board_pci_channels->mem_resource->start
34
35/*
36 * I/O routine helpers
37 */
38#if defined(CONFIG_CPU_SUBTYPE_SH7780) || defined(CONFIG_CPU_SUBTYPE_SH7785)
39#define PCI_IO_AREA 0xFE400000
40#define PCI_IO_SIZE 0x00400000
41#elif defined(CONFIG_CPU_SH5)
42extern unsigned long PCI_IO_AREA;
43#define PCI_IO_SIZE 0x00010000
44#else
45#define PCI_IO_AREA 0xFE240000
46#define PCI_IO_SIZE 0x00040000
47#endif
48
49#define PCI_MEM_SIZE 0x01000000
50
51#define SH4_PCIIOBR_MASK 0xFFFC0000
52#define pci_ioaddr(addr) (PCI_IO_AREA + (addr & ~SH4_PCIIOBR_MASK))
53
54#if defined(CONFIG_PCI)
55#define is_pci_ioaddr(port) \
56 (((port) >= PCIBIOS_MIN_IO) && \
57 ((port) < (PCIBIOS_MIN_IO + PCI_IO_SIZE)))
58#define is_pci_memaddr(port) \
59 (((port) >= PCIBIOS_MIN_MEM) && \
60 ((port) < (PCIBIOS_MIN_MEM + PCI_MEM_SIZE)))
61#else
62#define is_pci_ioaddr(port) (0)
63#define is_pci_memaddr(port) (0)
64#endif
65
66struct pci_dev;
67
68extern void pcibios_set_master(struct pci_dev *dev);
69
70static inline void pcibios_penalize_isa_irq(int irq, int active)
71{
72 /* We don't do dynamic PCI IRQ allocation */
73}
74
75/* Dynamic DMA mapping stuff.
76 * SuperH has everything mapped statically like x86.
77 */
78
79/* The PCI address space does equal the physical memory
80 * address space. The networking and block device layers use
81 * this boolean for bounce buffer decisions.
82 */
83#define PCI_DMA_BUS_IS_PHYS (1)
84
85#include <linux/types.h>
86#include <linux/slab.h>
87#include <asm/scatterlist.h>
88#include <linux/string.h>
89#include <asm/io.h>
90
91/* pci_unmap_{single,page} being a nop depends upon the
92 * configuration.
93 */
94#ifdef CONFIG_SH_PCIDMA_NONCOHERENT
95#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
96 dma_addr_t ADDR_NAME;
97#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
98 __u32 LEN_NAME;
99#define pci_unmap_addr(PTR, ADDR_NAME) \
100 ((PTR)->ADDR_NAME)
101#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
102 (((PTR)->ADDR_NAME) = (VAL))
103#define pci_unmap_len(PTR, LEN_NAME) \
104 ((PTR)->LEN_NAME)
105#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
106 (((PTR)->LEN_NAME) = (VAL))
107#else
108#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
109#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
110#define pci_unmap_addr(PTR, ADDR_NAME) (0)
111#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
112#define pci_unmap_len(PTR, LEN_NAME) (0)
113#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0)
114#endif
115
116#ifdef CONFIG_PCI
117static inline void pci_dma_burst_advice(struct pci_dev *pdev,
118 enum pci_dma_burst_strategy *strat,
119 unsigned long *strategy_parameter)
120{
121 *strat = PCI_DMA_BURST_INFINITY;
122 *strategy_parameter = ~0UL;
123}
124#endif
125
126/* Board-specific fixup routines. */
127void pcibios_fixup(void);
128int pcibios_init_platform(void);
129int pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin);
130
131#ifdef CONFIG_PCI_AUTO
132int pciauto_assign_resources(int busno, struct pci_channel *hose);
133#endif
134
135#endif /* __KERNEL__ */
136
137/* generic pci stuff */
138#include <asm-generic/pci.h>
139
140/* generic DMA-mapping stuff */
141#include <asm-generic/pci-dma-compat.h>
142
143#endif /* __ASM_SH_PCI_H */
144
diff --git a/include/asm-sh/percpu.h b/include/asm-sh/percpu.h
deleted file mode 100644
index 4db4b39a439..00000000000
--- a/include/asm-sh/percpu.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef __ARCH_SH_PERCPU
2#define __ARCH_SH_PERCPU
3
4#include <asm-generic/percpu.h>
5
6#endif /* __ARCH_SH_PERCPU */
diff --git a/include/asm-sh/pgalloc.h b/include/asm-sh/pgalloc.h
deleted file mode 100644
index 84dd2db7104..00000000000
--- a/include/asm-sh/pgalloc.h
+++ /dev/null
@@ -1,96 +0,0 @@
1#ifndef __ASM_SH_PGALLOC_H
2#define __ASM_SH_PGALLOC_H
3
4#include <linux/quicklist.h>
5#include <asm/page.h>
6
7#define QUICK_PGD 0 /* We preserve special mappings over free */
8#define QUICK_PT 1 /* Other page table pages that are zero on free */
9
10static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
11 pte_t *pte)
12{
13 set_pmd(pmd, __pmd((unsigned long)pte));
14}
15
16static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
17 pgtable_t pte)
18{
19 set_pmd(pmd, __pmd((unsigned long)page_address(pte)));
20}
21#define pmd_pgtable(pmd) pmd_page(pmd)
22
23static inline void pgd_ctor(void *x)
24{
25 pgd_t *pgd = x;
26
27 memcpy(pgd + USER_PTRS_PER_PGD,
28 swapper_pg_dir + USER_PTRS_PER_PGD,
29 (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
30}
31
32/*
33 * Allocate and free page tables.
34 */
35static inline pgd_t *pgd_alloc(struct mm_struct *mm)
36{
37 return quicklist_alloc(QUICK_PGD, GFP_KERNEL | __GFP_REPEAT, pgd_ctor);
38}
39
40static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
41{
42 quicklist_free(QUICK_PGD, NULL, pgd);
43}
44
45static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
46 unsigned long address)
47{
48 return quicklist_alloc(QUICK_PT, GFP_KERNEL | __GFP_REPEAT, NULL);
49}
50
51static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
52 unsigned long address)
53{
54 struct page *page;
55 void *pg;
56
57 pg = quicklist_alloc(QUICK_PT, GFP_KERNEL | __GFP_REPEAT, NULL);
58 if (!pg)
59 return NULL;
60 page = virt_to_page(pg);
61 pgtable_page_ctor(page);
62 return page;
63}
64
65static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
66{
67 quicklist_free(QUICK_PT, NULL, pte);
68}
69
70static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
71{
72 pgtable_page_dtor(pte);
73 quicklist_free_page(QUICK_PT, NULL, pte);
74}
75
76#define __pte_free_tlb(tlb,pte) \
77do { \
78 pgtable_page_dtor(pte); \
79 tlb_remove_page((tlb), (pte)); \
80} while (0)
81
82/*
83 * allocating and freeing a pmd is trivial: the 1-entry pmd is
84 * inside the pgd, so has no extra memory associated with it.
85 */
86
87#define pmd_free(mm, x) do { } while (0)
88#define __pmd_free_tlb(tlb,x) do { } while (0)
89
90static inline void check_pgt_cache(void)
91{
92 quicklist_trim(QUICK_PGD, NULL, 25, 16);
93 quicklist_trim(QUICK_PT, NULL, 25, 16);
94}
95
96#endif /* __ASM_SH_PGALLOC_H */
diff --git a/include/asm-sh/pgtable.h b/include/asm-sh/pgtable.h
deleted file mode 100644
index a4a8f8b9346..00000000000
--- a/include/asm-sh/pgtable.h
+++ /dev/null
@@ -1,152 +0,0 @@
1/*
2 * This file contains the functions and defines necessary to modify and
3 * use the SuperH page table tree.
4 *
5 * Copyright (C) 1999 Niibe Yutaka
6 * Copyright (C) 2002 - 2007 Paul Mundt
7 *
8 * This file is subject to the terms and conditions of the GNU General
9 * Public License. See the file "COPYING" in the main directory of this
10 * archive for more details.
11 */
12#ifndef __ASM_SH_PGTABLE_H
13#define __ASM_SH_PGTABLE_H
14
15#include <asm-generic/pgtable-nopmd.h>
16#include <asm/page.h>
17
18#ifndef __ASSEMBLY__
19#include <asm/addrspace.h>
20#include <asm/fixmap.h>
21
22/*
23 * ZERO_PAGE is a global shared page that is always zero: used
24 * for zero-mapped memory areas etc..
25 */
26extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
27#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
28
29#endif /* !__ASSEMBLY__ */
30
31/*
32 * Effective and physical address definitions, to aid with sign
33 * extension.
34 */
35#define NEFF 32
36#define NEFF_SIGN (1LL << (NEFF - 1))
37#define NEFF_MASK (-1LL << NEFF)
38
39#ifdef CONFIG_29BIT
40#define NPHYS 29
41#else
42#define NPHYS 32
43#endif
44
45#define NPHYS_SIGN (1LL << (NPHYS - 1))
46#define NPHYS_MASK (-1LL << NPHYS)
47
48/*
49 * traditional two-level paging structure
50 */
51/* PTE bits */
52#if defined(CONFIG_X2TLB) || defined(CONFIG_SUPERH64)
53# define PTE_MAGNITUDE 3 /* 64-bit PTEs on extended mode SH-X2 TLB */
54#else
55# define PTE_MAGNITUDE 2 /* 32-bit PTEs */
56#endif
57#define PTE_SHIFT PAGE_SHIFT
58#define PTE_BITS (PTE_SHIFT - PTE_MAGNITUDE)
59
60/* PGD bits */
61#define PGDIR_SHIFT (PTE_SHIFT + PTE_BITS)
62#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
63#define PGDIR_MASK (~(PGDIR_SIZE-1))
64
65/* Entries per level */
66#define PTRS_PER_PTE (PAGE_SIZE / (1 << PTE_MAGNITUDE))
67#define PTRS_PER_PGD (PAGE_SIZE / sizeof(pgd_t))
68
69#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
70#define FIRST_USER_ADDRESS 0
71
72#ifdef CONFIG_32BIT
73#define PHYS_ADDR_MASK 0xffffffff
74#else
75#define PHYS_ADDR_MASK 0x1fffffff
76#endif
77
78#define PTE_PHYS_MASK (PHYS_ADDR_MASK & PAGE_MASK)
79
80#ifdef CONFIG_SUPERH32
81#define VMALLOC_START (P3SEG)
82#else
83#define VMALLOC_START (0xf0000000)
84#endif
85#define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
86
87#if defined(CONFIG_SUPERH32)
88#include <asm/pgtable_32.h>
89#else
90#include <asm/pgtable_64.h>
91#endif
92
93/*
94 * SH-X and lower (legacy) SuperH parts (SH-3, SH-4, some SH-4A) can't do page
95 * protection for execute, and considers it the same as a read. Also, write
96 * permission implies read permission. This is the closest we can get..
97 *
98 * SH-X2 (SH7785) and later parts take this to the opposite end of the extreme,
99 * not only supporting separate execute, read, and write bits, but having
100 * completely separate permission bits for user and kernel space.
101 */
102 /*xwr*/
103#define __P000 PAGE_NONE
104#define __P001 PAGE_READONLY
105#define __P010 PAGE_COPY
106#define __P011 PAGE_COPY
107#define __P100 PAGE_EXECREAD
108#define __P101 PAGE_EXECREAD
109#define __P110 PAGE_COPY
110#define __P111 PAGE_COPY
111
112#define __S000 PAGE_NONE
113#define __S001 PAGE_READONLY
114#define __S010 PAGE_WRITEONLY
115#define __S011 PAGE_SHARED
116#define __S100 PAGE_EXECREAD
117#define __S101 PAGE_EXECREAD
118#define __S110 PAGE_RWX
119#define __S111 PAGE_RWX
120
121typedef pte_t *pte_addr_t;
122
123#define kern_addr_valid(addr) (1)
124
125#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
126 remap_pfn_range(vma, vaddr, pfn, size, prot)
127
128#define pte_pfn(x) ((unsigned long)(((x).pte_low >> PAGE_SHIFT)))
129
130/*
131 * No page table caches to initialise
132 */
133#define pgtable_cache_init() do { } while (0)
134
135#if !defined(CONFIG_CACHE_OFF) && (defined(CONFIG_CPU_SH4) || \
136 defined(CONFIG_SH7705_CACHE_32KB))
137struct mm_struct;
138#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
139pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
140#endif
141
142struct vm_area_struct;
143extern void update_mmu_cache(struct vm_area_struct * vma,
144 unsigned long address, pte_t pte);
145extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
146extern void paging_init(void);
147extern void page_table_range_init(unsigned long start, unsigned long end,
148 pgd_t *pgd);
149
150#include <asm-generic/pgtable.h>
151
152#endif /* __ASM_SH_PGTABLE_H */
diff --git a/include/asm-sh/pgtable_32.h b/include/asm-sh/pgtable_32.h
deleted file mode 100644
index cbc731d35c2..00000000000
--- a/include/asm-sh/pgtable_32.h
+++ /dev/null
@@ -1,477 +0,0 @@
1#ifndef __ASM_SH_PGTABLE_32_H
2#define __ASM_SH_PGTABLE_32_H
3
4/*
5 * Linux PTEL encoding.
6 *
7 * Hardware and software bit definitions for the PTEL value (see below for
8 * notes on SH-X2 MMUs and 64-bit PTEs):
9 *
10 * - Bits 0 and 7 are reserved on SH-3 (_PAGE_WT and _PAGE_SZ1 on SH-4).
11 *
12 * - Bit 1 is the SH-bit, but is unused on SH-3 due to an MMU bug (the
13 * hardware PTEL value can't have the SH-bit set when MMUCR.IX is set,
14 * which is the default in cpu-sh3/mmu_context.h:MMU_CONTROL_INIT).
15 *
16 * In order to keep this relatively clean, do not use these for defining
17 * SH-3 specific flags until all of the other unused bits have been
18 * exhausted.
19 *
20 * - Bit 9 is reserved by everyone and used by _PAGE_PROTNONE.
21 *
22 * - Bits 10 and 11 are low bits of the PPN that are reserved on >= 4K pages.
23 * Bit 10 is used for _PAGE_ACCESSED, bit 11 remains unused.
24 *
25 * - On 29 bit platforms, bits 31 to 29 are used for the space attributes
26 * and timing control which (together with bit 0) are moved into the
27 * old-style PTEA on the parts that support it.
28 *
29 * XXX: Leave the _PAGE_FILE and _PAGE_WT overhaul for a rainy day.
30 *
31 * SH-X2 MMUs and extended PTEs
32 *
33 * SH-X2 supports an extended mode TLB with split data arrays due to the
34 * number of bits needed for PR and SZ (now EPR and ESZ) encodings. The PR and
35 * SZ bit placeholders still exist in data array 1, but are implemented as
36 * reserved bits, with the real logic existing in data array 2.
37 *
38 * The downside to this is that we can no longer fit everything in to a 32-bit
39 * PTE encoding, so a 64-bit pte_t is necessary for these parts. On the plus
40 * side, this gives us quite a few spare bits to play with for future usage.
41 */
42/* Legacy and compat mode bits */
43#define _PAGE_WT 0x001 /* WT-bit on SH-4, 0 on SH-3 */
44#define _PAGE_HW_SHARED 0x002 /* SH-bit : shared among processes */
45#define _PAGE_DIRTY 0x004 /* D-bit : page changed */
46#define _PAGE_CACHABLE 0x008 /* C-bit : cachable */
47#define _PAGE_SZ0 0x010 /* SZ0-bit : Size of page */
48#define _PAGE_RW 0x020 /* PR0-bit : write access allowed */
49#define _PAGE_USER 0x040 /* PR1-bit : user space access allowed*/
50#define _PAGE_SZ1 0x080 /* SZ1-bit : Size of page (on SH-4) */
51#define _PAGE_PRESENT 0x100 /* V-bit : page is valid */
52#define _PAGE_PROTNONE 0x200 /* software: if not present */
53#define _PAGE_ACCESSED 0x400 /* software: page referenced */
54#define _PAGE_FILE _PAGE_WT /* software: pagecache or swap? */
55
56#define _PAGE_SZ_MASK (_PAGE_SZ0 | _PAGE_SZ1)
57#define _PAGE_PR_MASK (_PAGE_RW | _PAGE_USER)
58
59/* Extended mode bits */
60#define _PAGE_EXT_ESZ0 0x0010 /* ESZ0-bit: Size of page */
61#define _PAGE_EXT_ESZ1 0x0020 /* ESZ1-bit: Size of page */
62#define _PAGE_EXT_ESZ2 0x0040 /* ESZ2-bit: Size of page */
63#define _PAGE_EXT_ESZ3 0x0080 /* ESZ3-bit: Size of page */
64
65#define _PAGE_EXT_USER_EXEC 0x0100 /* EPR0-bit: User space executable */
66#define _PAGE_EXT_USER_WRITE 0x0200 /* EPR1-bit: User space writable */
67#define _PAGE_EXT_USER_READ 0x0400 /* EPR2-bit: User space readable */
68
69#define _PAGE_EXT_KERN_EXEC 0x0800 /* EPR3-bit: Kernel space executable */
70#define _PAGE_EXT_KERN_WRITE 0x1000 /* EPR4-bit: Kernel space writable */
71#define _PAGE_EXT_KERN_READ 0x2000 /* EPR5-bit: Kernel space readable */
72
73/* Wrapper for extended mode pgprot twiddling */
74#define _PAGE_EXT(x) ((unsigned long long)(x) << 32)
75
76/* software: moves to PTEA.TC (Timing Control) */
77#define _PAGE_PCC_AREA5 0x00000000 /* use BSC registers for area5 */
78#define _PAGE_PCC_AREA6 0x80000000 /* use BSC registers for area6 */
79
80/* software: moves to PTEA.SA[2:0] (Space Attributes) */
81#define _PAGE_PCC_IODYN 0x00000001 /* IO space, dynamically sized bus */
82#define _PAGE_PCC_IO8 0x20000000 /* IO space, 8 bit bus */
83#define _PAGE_PCC_IO16 0x20000001 /* IO space, 16 bit bus */
84#define _PAGE_PCC_COM8 0x40000000 /* Common Memory space, 8 bit bus */
85#define _PAGE_PCC_COM16 0x40000001 /* Common Memory space, 16 bit bus */
86#define _PAGE_PCC_ATR8 0x60000000 /* Attribute Memory space, 8 bit bus */
87#define _PAGE_PCC_ATR16 0x60000001 /* Attribute Memory space, 6 bit bus */
88
89/* Mask which drops unused bits from the PTEL value */
90#if defined(CONFIG_CPU_SH3)
91#define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED| \
92 _PAGE_FILE | _PAGE_SZ1 | \
93 _PAGE_HW_SHARED)
94#elif defined(CONFIG_X2TLB)
95/* Get rid of the legacy PR/SZ bits when using extended mode */
96#define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED | \
97 _PAGE_FILE | _PAGE_PR_MASK | _PAGE_SZ_MASK)
98#else
99#define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED | _PAGE_FILE)
100#endif
101
102#define _PAGE_FLAGS_HARDWARE_MASK (PHYS_ADDR_MASK & ~(_PAGE_CLEAR_FLAGS))
103
104/* Hardware flags, page size encoding */
105#if defined(CONFIG_X2TLB)
106# if defined(CONFIG_PAGE_SIZE_4KB)
107# define _PAGE_FLAGS_HARD _PAGE_EXT(_PAGE_EXT_ESZ0)
108# elif defined(CONFIG_PAGE_SIZE_8KB)
109# define _PAGE_FLAGS_HARD _PAGE_EXT(_PAGE_EXT_ESZ1)
110# elif defined(CONFIG_PAGE_SIZE_64KB)
111# define _PAGE_FLAGS_HARD _PAGE_EXT(_PAGE_EXT_ESZ2)
112# endif
113#else
114# if defined(CONFIG_PAGE_SIZE_4KB)
115# define _PAGE_FLAGS_HARD _PAGE_SZ0
116# elif defined(CONFIG_PAGE_SIZE_64KB)
117# define _PAGE_FLAGS_HARD _PAGE_SZ1
118# endif
119#endif
120
121#if defined(CONFIG_X2TLB)
122# if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
123# define _PAGE_SZHUGE (_PAGE_EXT_ESZ2)
124# elif defined(CONFIG_HUGETLB_PAGE_SIZE_256K)
125# define _PAGE_SZHUGE (_PAGE_EXT_ESZ0 | _PAGE_EXT_ESZ2)
126# elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
127# define _PAGE_SZHUGE (_PAGE_EXT_ESZ0 | _PAGE_EXT_ESZ1 | _PAGE_EXT_ESZ2)
128# elif defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
129# define _PAGE_SZHUGE (_PAGE_EXT_ESZ3)
130# elif defined(CONFIG_HUGETLB_PAGE_SIZE_64MB)
131# define _PAGE_SZHUGE (_PAGE_EXT_ESZ2 | _PAGE_EXT_ESZ3)
132# endif
133#else
134# if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
135# define _PAGE_SZHUGE (_PAGE_SZ1)
136# elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
137# define _PAGE_SZHUGE (_PAGE_SZ0 | _PAGE_SZ1)
138# endif
139#endif
140
141/*
142 * Stub out _PAGE_SZHUGE if we don't have a good definition for it,
143 * to make pte_mkhuge() happy.
144 */
145#ifndef _PAGE_SZHUGE
146# define _PAGE_SZHUGE (_PAGE_FLAGS_HARD)
147#endif
148
149#define _PAGE_CHG_MASK \
150 (PTE_MASK | _PAGE_ACCESSED | _PAGE_CACHABLE | _PAGE_DIRTY)
151
152#ifndef __ASSEMBLY__
153
154#if defined(CONFIG_X2TLB) /* SH-X2 TLB */
155#define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_CACHABLE | \
156 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
157
158#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
159 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
160 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
161 _PAGE_EXT_KERN_WRITE | \
162 _PAGE_EXT_USER_READ | \
163 _PAGE_EXT_USER_WRITE))
164
165#define PAGE_EXECREAD __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
166 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
167 _PAGE_EXT(_PAGE_EXT_KERN_EXEC | \
168 _PAGE_EXT_KERN_READ | \
169 _PAGE_EXT_USER_EXEC | \
170 _PAGE_EXT_USER_READ))
171
172#define PAGE_COPY PAGE_EXECREAD
173
174#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
175 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
176 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
177 _PAGE_EXT_USER_READ))
178
179#define PAGE_WRITEONLY __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
180 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
181 _PAGE_EXT(_PAGE_EXT_KERN_WRITE | \
182 _PAGE_EXT_USER_WRITE))
183
184#define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
185 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
186 _PAGE_EXT(_PAGE_EXT_KERN_WRITE | \
187 _PAGE_EXT_KERN_READ | \
188 _PAGE_EXT_KERN_EXEC | \
189 _PAGE_EXT_USER_WRITE | \
190 _PAGE_EXT_USER_READ | \
191 _PAGE_EXT_USER_EXEC))
192
193#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
194 _PAGE_DIRTY | _PAGE_ACCESSED | \
195 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD | \
196 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
197 _PAGE_EXT_KERN_WRITE | \
198 _PAGE_EXT_KERN_EXEC))
199
200#define PAGE_KERNEL_NOCACHE \
201 __pgprot(_PAGE_PRESENT | _PAGE_DIRTY | \
202 _PAGE_ACCESSED | _PAGE_HW_SHARED | \
203 _PAGE_FLAGS_HARD | \
204 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
205 _PAGE_EXT_KERN_WRITE | \
206 _PAGE_EXT_KERN_EXEC))
207
208#define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
209 _PAGE_DIRTY | _PAGE_ACCESSED | \
210 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD | \
211 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
212 _PAGE_EXT_KERN_EXEC))
213
214#define PAGE_KERNEL_PCC(slot, type) \
215 __pgprot(_PAGE_PRESENT | _PAGE_DIRTY | \
216 _PAGE_ACCESSED | _PAGE_FLAGS_HARD | \
217 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
218 _PAGE_EXT_KERN_WRITE | \
219 _PAGE_EXT_KERN_EXEC) \
220 (slot ? _PAGE_PCC_AREA5 : _PAGE_PCC_AREA6) | \
221 (type))
222
223#elif defined(CONFIG_MMU) /* SH-X TLB */
224#define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_CACHABLE | \
225 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
226
227#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | \
228 _PAGE_CACHABLE | _PAGE_ACCESSED | \
229 _PAGE_FLAGS_HARD)
230
231#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | \
232 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
233
234#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | \
235 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
236
237#define PAGE_EXECREAD PAGE_READONLY
238#define PAGE_RWX PAGE_SHARED
239#define PAGE_WRITEONLY PAGE_SHARED
240
241#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_CACHABLE | \
242 _PAGE_DIRTY | _PAGE_ACCESSED | \
243 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
244
245#define PAGE_KERNEL_NOCACHE \
246 __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | \
247 _PAGE_ACCESSED | _PAGE_HW_SHARED | \
248 _PAGE_FLAGS_HARD)
249
250#define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
251 _PAGE_DIRTY | _PAGE_ACCESSED | \
252 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
253
254#define PAGE_KERNEL_PCC(slot, type) \
255 __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | \
256 _PAGE_ACCESSED | _PAGE_FLAGS_HARD | \
257 (slot ? _PAGE_PCC_AREA5 : _PAGE_PCC_AREA6) | \
258 (type))
259#else /* no mmu */
260#define PAGE_NONE __pgprot(0)
261#define PAGE_SHARED __pgprot(0)
262#define PAGE_COPY __pgprot(0)
263#define PAGE_EXECREAD __pgprot(0)
264#define PAGE_RWX __pgprot(0)
265#define PAGE_READONLY __pgprot(0)
266#define PAGE_WRITEONLY __pgprot(0)
267#define PAGE_KERNEL __pgprot(0)
268#define PAGE_KERNEL_NOCACHE __pgprot(0)
269#define PAGE_KERNEL_RO __pgprot(0)
270
271#define PAGE_KERNEL_PCC(slot, type) \
272 __pgprot(0)
273#endif
274
275#endif /* __ASSEMBLY__ */
276
277#ifndef __ASSEMBLY__
278
279/*
280 * Certain architectures need to do special things when PTEs
281 * within a page table are directly modified. Thus, the following
282 * hook is made available.
283 */
284#ifdef CONFIG_X2TLB
285static inline void set_pte(pte_t *ptep, pte_t pte)
286{
287 ptep->pte_high = pte.pte_high;
288 smp_wmb();
289 ptep->pte_low = pte.pte_low;
290}
291#else
292#define set_pte(pteptr, pteval) (*(pteptr) = pteval)
293#endif
294
295#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
296
297/*
298 * (pmds are folded into pgds so this doesn't get actually called,
299 * but the define is needed for a generic inline function.)
300 */
301#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
302
303#define pfn_pte(pfn, prot) \
304 __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
305#define pfn_pmd(pfn, prot) \
306 __pmd(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
307
308#define pte_none(x) (!pte_val(x))
309#define pte_present(x) ((x).pte_low & (_PAGE_PRESENT | _PAGE_PROTNONE))
310
311#define pte_clear(mm,addr,xp) do { set_pte_at(mm, addr, xp, __pte(0)); } while (0)
312
313#define pmd_none(x) (!pmd_val(x))
314#define pmd_present(x) (pmd_val(x))
315#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
316#define pmd_bad(x) (pmd_val(x) & ~PAGE_MASK)
317
318#define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
319#define pte_page(x) pfn_to_page(pte_pfn(x))
320
321/*
322 * The following only work if pte_present() is true.
323 * Undefined behaviour if not..
324 */
325#define pte_not_present(pte) (!((pte).pte_low & _PAGE_PRESENT))
326#define pte_dirty(pte) ((pte).pte_low & _PAGE_DIRTY)
327#define pte_young(pte) ((pte).pte_low & _PAGE_ACCESSED)
328#define pte_file(pte) ((pte).pte_low & _PAGE_FILE)
329#define pte_special(pte) (0)
330
331#ifdef CONFIG_X2TLB
332#define pte_write(pte) ((pte).pte_high & _PAGE_EXT_USER_WRITE)
333#else
334#define pte_write(pte) ((pte).pte_low & _PAGE_RW)
335#endif
336
337#define PTE_BIT_FUNC(h,fn,op) \
338static inline pte_t pte_##fn(pte_t pte) { pte.pte_##h op; return pte; }
339
340#ifdef CONFIG_X2TLB
341/*
342 * We cheat a bit in the SH-X2 TLB case. As the permission bits are
343 * individually toggled (and user permissions are entirely decoupled from
344 * kernel permissions), we attempt to couple them a bit more sanely here.
345 */
346PTE_BIT_FUNC(high, wrprotect, &= ~_PAGE_EXT_USER_WRITE);
347PTE_BIT_FUNC(high, mkwrite, |= _PAGE_EXT_USER_WRITE | _PAGE_EXT_KERN_WRITE);
348PTE_BIT_FUNC(high, mkhuge, |= _PAGE_SZHUGE);
349#else
350PTE_BIT_FUNC(low, wrprotect, &= ~_PAGE_RW);
351PTE_BIT_FUNC(low, mkwrite, |= _PAGE_RW);
352PTE_BIT_FUNC(low, mkhuge, |= _PAGE_SZHUGE);
353#endif
354
355PTE_BIT_FUNC(low, mkclean, &= ~_PAGE_DIRTY);
356PTE_BIT_FUNC(low, mkdirty, |= _PAGE_DIRTY);
357PTE_BIT_FUNC(low, mkold, &= ~_PAGE_ACCESSED);
358PTE_BIT_FUNC(low, mkyoung, |= _PAGE_ACCESSED);
359
360static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
361
362/*
363 * Macro and implementation to make a page protection as uncachable.
364 */
365#define pgprot_writecombine(prot) \
366 __pgprot(pgprot_val(prot) & ~_PAGE_CACHABLE)
367
368#define pgprot_noncached pgprot_writecombine
369
370/*
371 * Conversion functions: convert a page and protection to a page entry,
372 * and a page entry and page directory to the page they refer to.
373 *
374 * extern pte_t mk_pte(struct page *page, pgprot_t pgprot)
375 */
376#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
377
378static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
379{
380 pte.pte_low &= _PAGE_CHG_MASK;
381 pte.pte_low |= pgprot_val(newprot);
382
383#ifdef CONFIG_X2TLB
384 pte.pte_high |= pgprot_val(newprot) >> 32;
385#endif
386
387 return pte;
388}
389
390#define pmd_page_vaddr(pmd) ((unsigned long)pmd_val(pmd))
391#define pmd_page(pmd) (virt_to_page(pmd_val(pmd)))
392
393/* to find an entry in a page-table-directory. */
394#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
395#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
396
397/* to find an entry in a kernel page-table-directory */
398#define pgd_offset_k(address) pgd_offset(&init_mm, address)
399
400/* Find an entry in the third-level page table.. */
401#define pte_index(address) ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
402#define pte_offset_kernel(dir, address) \
403 ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(address))
404#define pte_offset_map(dir, address) pte_offset_kernel(dir, address)
405#define pte_offset_map_nested(dir, address) pte_offset_kernel(dir, address)
406
407#define pte_unmap(pte) do { } while (0)
408#define pte_unmap_nested(pte) do { } while (0)
409
410#ifdef CONFIG_X2TLB
411#define pte_ERROR(e) \
412 printk("%s:%d: bad pte %p(%08lx%08lx).\n", __FILE__, __LINE__, \
413 &(e), (e).pte_high, (e).pte_low)
414#define pgd_ERROR(e) \
415 printk("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e))
416#else
417#define pte_ERROR(e) \
418 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
419#define pgd_ERROR(e) \
420 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
421#endif
422
423/*
424 * Encode and de-code a swap entry
425 *
426 * Constraints:
427 * _PAGE_FILE at bit 0
428 * _PAGE_PRESENT at bit 8
429 * _PAGE_PROTNONE at bit 9
430 *
431 * For the normal case, we encode the swap type into bits 0:7 and the
432 * swap offset into bits 10:30. For the 64-bit PTE case, we keep the
433 * preserved bits in the low 32-bits and use the upper 32 as the swap
434 * offset (along with a 5-bit type), following the same approach as x86
435 * PAE. This keeps the logic quite simple, and allows for a full 32
436 * PTE_FILE_MAX_BITS, as opposed to the 29-bits we're constrained with
437 * in the pte_low case.
438 *
439 * As is evident by the Alpha code, if we ever get a 64-bit unsigned
440 * long (swp_entry_t) to match up with the 64-bit PTEs, this all becomes
441 * much cleaner..
442 *
443 * NOTE: We should set ZEROs at the position of _PAGE_PRESENT
444 * and _PAGE_PROTNONE bits
445 */
446#ifdef CONFIG_X2TLB
447#define __swp_type(x) ((x).val & 0x1f)
448#define __swp_offset(x) ((x).val >> 5)
449#define __swp_entry(type, offset) ((swp_entry_t){ (type) | (offset) << 5})
450#define __pte_to_swp_entry(pte) ((swp_entry_t){ (pte).pte_high })
451#define __swp_entry_to_pte(x) ((pte_t){ 0, (x).val })
452
453/*
454 * Encode and decode a nonlinear file mapping entry
455 */
456#define pte_to_pgoff(pte) ((pte).pte_high)
457#define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) })
458
459#define PTE_FILE_MAX_BITS 32
460#else
461#define __swp_type(x) ((x).val & 0xff)
462#define __swp_offset(x) ((x).val >> 10)
463#define __swp_entry(type, offset) ((swp_entry_t){(type) | (offset) <<10})
464
465#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 1 })
466#define __swp_entry_to_pte(x) ((pte_t) { (x).val << 1 })
467
468/*
469 * Encode and decode a nonlinear file mapping entry
470 */
471#define PTE_FILE_MAX_BITS 29
472#define pte_to_pgoff(pte) (pte_val(pte) >> 1)
473#define pgoff_to_pte(off) ((pte_t) { ((off) << 1) | _PAGE_FILE })
474#endif
475
476#endif /* __ASSEMBLY__ */
477#endif /* __ASM_SH_PGTABLE_32_H */
diff --git a/include/asm-sh/pgtable_64.h b/include/asm-sh/pgtable_64.h
deleted file mode 100644
index c78990cda55..00000000000
--- a/include/asm-sh/pgtable_64.h
+++ /dev/null
@@ -1,314 +0,0 @@
1#ifndef __ASM_SH_PGTABLE_64_H
2#define __ASM_SH_PGTABLE_64_H
3
4/*
5 * include/asm-sh/pgtable_64.h
6 *
7 * This file contains the functions and defines necessary to modify and use
8 * the SuperH page table tree.
9 *
10 * Copyright (C) 2000, 2001 Paolo Alberelli
11 * Copyright (C) 2003, 2004 Paul Mundt
12 * Copyright (C) 2003, 2004 Richard Curnow
13 *
14 * This file is subject to the terms and conditions of the GNU General Public
15 * License. See the file "COPYING" in the main directory of this archive
16 * for more details.
17 */
18#include <linux/threads.h>
19#include <asm/processor.h>
20#include <asm/page.h>
21
22/*
23 * Error outputs.
24 */
25#define pte_ERROR(e) \
26 printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
27#define pgd_ERROR(e) \
28 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
29
30/*
31 * Table setting routines. Used within arch/mm only.
32 */
33#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
34
35static __inline__ void set_pte(pte_t *pteptr, pte_t pteval)
36{
37 unsigned long long x = ((unsigned long long) pteval.pte_low);
38 unsigned long long *xp = (unsigned long long *) pteptr;
39 /*
40 * Sign-extend based on NPHYS.
41 */
42 *(xp) = (x & NPHYS_SIGN) ? (x | NPHYS_MASK) : x;
43}
44#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
45
46static __inline__ void pmd_set(pmd_t *pmdp,pte_t *ptep)
47{
48 pmd_val(*pmdp) = (unsigned long) ptep;
49}
50
51/*
52 * PGD defines. Top level.
53 */
54
55/* To find an entry in a generic PGD. */
56#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
57#define __pgd_offset(address) pgd_index(address)
58#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
59
60/* To find an entry in a kernel PGD. */
61#define pgd_offset_k(address) pgd_offset(&init_mm, address)
62
63/*
64 * PMD level access routines. Same notes as above.
65 */
66#define _PMD_EMPTY 0x0
67/* Either the PMD is empty or present, it's not paged out */
68#define pmd_present(pmd_entry) (pmd_val(pmd_entry) & _PAGE_PRESENT)
69#define pmd_clear(pmd_entry_p) (set_pmd((pmd_entry_p), __pmd(_PMD_EMPTY)))
70#define pmd_none(pmd_entry) (pmd_val((pmd_entry)) == _PMD_EMPTY)
71#define pmd_bad(pmd_entry) ((pmd_val(pmd_entry) & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
72
73#define pmd_page_vaddr(pmd_entry) \
74 ((unsigned long) __va(pmd_val(pmd_entry) & PAGE_MASK))
75
76#define pmd_page(pmd) \
77 (virt_to_page(pmd_val(pmd)))
78
79/* PMD to PTE dereferencing */
80#define pte_index(address) \
81 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
82
83#define pte_offset_kernel(dir, addr) \
84 ((pte_t *) ((pmd_val(*(dir))) & PAGE_MASK) + pte_index((addr)))
85
86#define pte_offset_map(dir,addr) pte_offset_kernel(dir, addr)
87#define pte_offset_map_nested(dir,addr) pte_offset_kernel(dir, addr)
88#define pte_unmap(pte) do { } while (0)
89#define pte_unmap_nested(pte) do { } while (0)
90
91#ifndef __ASSEMBLY__
92#define IOBASE_VADDR 0xff000000
93#define IOBASE_END 0xffffffff
94
95/*
96 * PTEL coherent flags.
97 * See Chapter 17 ST50 CPU Core Volume 1, Architecture.
98 */
99/* The bits that are required in the SH-5 TLB are placed in the h/w-defined
100 positions, to avoid expensive bit shuffling on every refill. The remaining
101 bits are used for s/w purposes and masked out on each refill.
102
103 Note, the PTE slots are used to hold data of type swp_entry_t when a page is
104 swapped out. Only the _PAGE_PRESENT flag is significant when the page is
105 swapped out, and it must be placed so that it doesn't overlap either the
106 type or offset fields of swp_entry_t. For x86, offset is at [31:8] and type
107 at [6:1], with _PAGE_PRESENT at bit 0 for both pte_t and swp_entry_t. This
108 scheme doesn't map to SH-5 because bit [0] controls cacheability. So bit
109 [2] is used for _PAGE_PRESENT and the type field of swp_entry_t is split
110 into 2 pieces. That is handled by SWP_ENTRY and SWP_TYPE below. */
111#define _PAGE_WT 0x001 /* CB0: if cacheable, 1->write-thru, 0->write-back */
112#define _PAGE_DEVICE 0x001 /* CB0: if uncacheable, 1->device (i.e. no write-combining or reordering at bus level) */
113#define _PAGE_CACHABLE 0x002 /* CB1: uncachable/cachable */
114#define _PAGE_PRESENT 0x004 /* software: page referenced */
115#define _PAGE_FILE 0x004 /* software: only when !present */
116#define _PAGE_SIZE0 0x008 /* SZ0-bit : size of page */
117#define _PAGE_SIZE1 0x010 /* SZ1-bit : size of page */
118#define _PAGE_SHARED 0x020 /* software: reflects PTEH's SH */
119#define _PAGE_READ 0x040 /* PR0-bit : read access allowed */
120#define _PAGE_EXECUTE 0x080 /* PR1-bit : execute access allowed */
121#define _PAGE_WRITE 0x100 /* PR2-bit : write access allowed */
122#define _PAGE_USER 0x200 /* PR3-bit : user space access allowed */
123#define _PAGE_DIRTY 0x400 /* software: page accessed in write */
124#define _PAGE_ACCESSED 0x800 /* software: page referenced */
125
126/* Mask which drops software flags */
127#define _PAGE_FLAGS_HARDWARE_MASK 0xfffffffffffff3dbLL
128
129/*
130 * HugeTLB support
131 */
132#if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
133#define _PAGE_SZHUGE (_PAGE_SIZE0)
134#elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
135#define _PAGE_SZHUGE (_PAGE_SIZE1)
136#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512MB)
137#define _PAGE_SZHUGE (_PAGE_SIZE0 | _PAGE_SIZE1)
138#endif
139
140/*
141 * Stub out _PAGE_SZHUGE if we don't have a good definition for it,
142 * to make pte_mkhuge() happy.
143 */
144#ifndef _PAGE_SZHUGE
145# define _PAGE_SZHUGE (0)
146#endif
147
148/*
149 * Default flags for a Kernel page.
150 * This is fundametally also SHARED because the main use of this define
151 * (other than for PGD/PMD entries) is for the VMALLOC pool which is
152 * contextless.
153 *
154 * _PAGE_EXECUTE is required for modules
155 *
156 */
157#define _KERNPG_TABLE (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
158 _PAGE_EXECUTE | \
159 _PAGE_CACHABLE | _PAGE_ACCESSED | _PAGE_DIRTY | \
160 _PAGE_SHARED)
161
162/* Default flags for a User page */
163#define _PAGE_TABLE (_KERNPG_TABLE | _PAGE_USER)
164
165#define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
166
167/*
168 * We have full permissions (Read/Write/Execute/Shared).
169 */
170#define _PAGE_COMMON (_PAGE_PRESENT | _PAGE_USER | \
171 _PAGE_CACHABLE | _PAGE_ACCESSED)
172
173#define PAGE_NONE __pgprot(_PAGE_CACHABLE | _PAGE_ACCESSED)
174#define PAGE_SHARED __pgprot(_PAGE_COMMON | _PAGE_READ | _PAGE_WRITE | \
175 _PAGE_SHARED)
176#define PAGE_EXECREAD __pgprot(_PAGE_COMMON | _PAGE_READ | _PAGE_EXECUTE)
177
178/*
179 * We need to include PAGE_EXECUTE in PAGE_COPY because it is the default
180 * protection mode for the stack.
181 */
182#define PAGE_COPY PAGE_EXECREAD
183
184#define PAGE_READONLY __pgprot(_PAGE_COMMON | _PAGE_READ)
185#define PAGE_WRITEONLY __pgprot(_PAGE_COMMON | _PAGE_WRITE)
186#define PAGE_RWX __pgprot(_PAGE_COMMON | _PAGE_READ | \
187 _PAGE_WRITE | _PAGE_EXECUTE)
188#define PAGE_KERNEL __pgprot(_KERNPG_TABLE)
189
190#define PAGE_KERNEL_NOCACHE \
191 __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
192 _PAGE_EXECUTE | _PAGE_ACCESSED | \
193 _PAGE_DIRTY | _PAGE_SHARED)
194
195/* Make it a device mapping for maximum safety (e.g. for mapping device
196 registers into user-space via /dev/map). */
197#define pgprot_noncached(x) __pgprot(((x).pgprot & ~(_PAGE_CACHABLE)) | _PAGE_DEVICE)
198#define pgprot_writecombine(prot) __pgprot(pgprot_val(prot) & ~_PAGE_CACHABLE)
199
200/*
201 * Handling allocation failures during page table setup.
202 */
203extern void __handle_bad_pmd_kernel(pmd_t * pmd);
204#define __handle_bad_pmd(x) __handle_bad_pmd_kernel(x)
205
206/*
207 * PTE level access routines.
208 *
209 * Note1:
210 * It's the tree walk leaf. This is physical address to be stored.
211 *
212 * Note 2:
213 * Regarding the choice of _PTE_EMPTY:
214
215 We must choose a bit pattern that cannot be valid, whether or not the page
216 is present. bit[2]==1 => present, bit[2]==0 => swapped out. If swapped
217 out, bits [31:8], [6:3], [1:0] are under swapper control, so only bit[7] is
218 left for us to select. If we force bit[7]==0 when swapped out, we could use
219 the combination bit[7,2]=2'b10 to indicate an empty PTE. Alternatively, if
220 we force bit[7]==1 when swapped out, we can use all zeroes to indicate
221 empty. This is convenient, because the page tables get cleared to zero
222 when they are allocated.
223
224 */
225#define _PTE_EMPTY 0x0
226#define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
227#define pte_clear(mm,addr,xp) (set_pte_at(mm, addr, xp, __pte(_PTE_EMPTY)))
228#define pte_none(x) (pte_val(x) == _PTE_EMPTY)
229
230/*
231 * Some definitions to translate between mem_map, PTEs, and page
232 * addresses:
233 */
234
235/*
236 * Given a PTE, return the index of the mem_map[] entry corresponding
237 * to the page frame the PTE. Get the absolute physical address, make
238 * a relative physical address and translate it to an index.
239 */
240#define pte_pagenr(x) (((unsigned long) (pte_val(x)) - \
241 __MEMORY_START) >> PAGE_SHIFT)
242
243/*
244 * Given a PTE, return the "struct page *".
245 */
246#define pte_page(x) (mem_map + pte_pagenr(x))
247
248/*
249 * Return number of (down rounded) MB corresponding to x pages.
250 */
251#define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
252
253
254/*
255 * The following have defined behavior only work if pte_present() is true.
256 */
257static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
258static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
259static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; }
260static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
261static inline int pte_special(pte_t pte){ return 0; }
262
263static inline pte_t pte_wrprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_WRITE)); return pte; }
264static inline pte_t pte_mkclean(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_DIRTY)); return pte; }
265static inline pte_t pte_mkold(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_ACCESSED)); return pte; }
266static inline pte_t pte_mkwrite(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_WRITE)); return pte; }
267static inline pte_t pte_mkdirty(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_DIRTY)); return pte; }
268static inline pte_t pte_mkyoung(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_ACCESSED)); return pte; }
269static inline pte_t pte_mkhuge(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_SZHUGE)); return pte; }
270static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
271
272
273/*
274 * Conversion functions: convert a page and protection to a page entry.
275 *
276 * extern pte_t mk_pte(struct page *page, pgprot_t pgprot)
277 */
278#define mk_pte(page,pgprot) \
279({ \
280 pte_t __pte; \
281 \
282 set_pte(&__pte, __pte((((page)-mem_map) << PAGE_SHIFT) | \
283 __MEMORY_START | pgprot_val((pgprot)))); \
284 __pte; \
285})
286
287/*
288 * This takes a (absolute) physical page address that is used
289 * by the remapping functions
290 */
291#define mk_pte_phys(physpage, pgprot) \
292({ pte_t __pte; set_pte(&__pte, __pte(physpage | pgprot_val(pgprot))); __pte; })
293
294static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
295{ set_pte(&pte, __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot))); return pte; }
296
297/* Encode and decode a swap entry */
298#define __swp_type(x) (((x).val & 3) + (((x).val >> 1) & 0x3c))
299#define __swp_offset(x) ((x).val >> 8)
300#define __swp_entry(type, offset) ((swp_entry_t) { ((offset << 8) + ((type & 0x3c) << 1) + (type & 3)) })
301#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
302#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
303
304/* Encode and decode a nonlinear file mapping entry */
305#define PTE_FILE_MAX_BITS 29
306#define pte_to_pgoff(pte) (pte_val(pte))
307#define pgoff_to_pte(off) ((pte_t) { (off) | _PAGE_FILE })
308
309#endif /* !__ASSEMBLY__ */
310
311#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
312#define pfn_pmd(pfn, prot) __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
313
314#endif /* __ASM_SH_PGTABLE_64_H */
diff --git a/include/asm-sh/pm.h b/include/asm-sh/pm.h
deleted file mode 100644
index 56fdbd6b1c9..00000000000
--- a/include/asm-sh/pm.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright 2006 (c) Andriy Skulysh <askulysh@gmail.com>
7 *
8 */
9#ifndef __ASM_SH_PM_H
10#define __ASM_SH_PM_H
11
12extern u8 wakeup_start;
13extern u8 wakeup_end;
14
15void pm_enter(void);
16
17#endif
diff --git a/include/asm-sh/poll.h b/include/asm-sh/poll.h
deleted file mode 100644
index c98509d3149..00000000000
--- a/include/asm-sh/poll.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/poll.h>
diff --git a/include/asm-sh/posix_types.h b/include/asm-sh/posix_types.h
deleted file mode 100644
index 4eeb723aee7..00000000000
--- a/include/asm-sh/posix_types.h
+++ /dev/null
@@ -1,13 +0,0 @@
1#ifdef __KERNEL__
2# ifdef CONFIG_SUPERH32
3# include "posix_types_32.h"
4# else
5# include "posix_types_64.h"
6# endif
7#else
8# ifdef __SH5__
9# include "posix_types_64.h"
10# else
11# include "posix_types_32.h"
12# endif
13#endif /* __KERNEL__ */
diff --git a/include/asm-sh/posix_types_32.h b/include/asm-sh/posix_types_32.h
deleted file mode 100644
index 0a3d2f54ab2..00000000000
--- a/include/asm-sh/posix_types_32.h
+++ /dev/null
@@ -1,122 +0,0 @@
1#ifndef __ASM_SH_POSIX_TYPES_H
2#define __ASM_SH_POSIX_TYPES_H
3
4/*
5 * This file is generally used by user-level software, so you need to
6 * be a little careful about namespace pollution etc. Also, we cannot
7 * assume GCC is being used.
8 */
9
10typedef unsigned long __kernel_ino_t;
11typedef unsigned short __kernel_mode_t;
12typedef unsigned short __kernel_nlink_t;
13typedef long __kernel_off_t;
14typedef int __kernel_pid_t;
15typedef unsigned short __kernel_ipc_pid_t;
16typedef unsigned short __kernel_uid_t;
17typedef unsigned short __kernel_gid_t;
18typedef unsigned int __kernel_size_t;
19typedef int __kernel_ssize_t;
20typedef int __kernel_ptrdiff_t;
21typedef long __kernel_time_t;
22typedef long __kernel_suseconds_t;
23typedef long __kernel_clock_t;
24typedef int __kernel_timer_t;
25typedef int __kernel_clockid_t;
26typedef int __kernel_daddr_t;
27typedef char * __kernel_caddr_t;
28typedef unsigned short __kernel_uid16_t;
29typedef unsigned short __kernel_gid16_t;
30typedef unsigned int __kernel_uid32_t;
31typedef unsigned int __kernel_gid32_t;
32
33typedef unsigned short __kernel_old_uid_t;
34typedef unsigned short __kernel_old_gid_t;
35typedef unsigned short __kernel_old_dev_t;
36
37#ifdef __GNUC__
38typedef long long __kernel_loff_t;
39#endif
40
41typedef struct {
42#if defined(__KERNEL__) || defined(__USE_ALL)
43 int val[2];
44#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
45 int __val[2];
46#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
47} __kernel_fsid_t;
48
49#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
50
51#undef __FD_SET
52static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
53{
54 unsigned long __tmp = __fd / __NFDBITS;
55 unsigned long __rem = __fd % __NFDBITS;
56 __fdsetp->fds_bits[__tmp] |= (1UL<<__rem);
57}
58
59#undef __FD_CLR
60static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp)
61{
62 unsigned long __tmp = __fd / __NFDBITS;
63 unsigned long __rem = __fd % __NFDBITS;
64 __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem);
65}
66
67
68#undef __FD_ISSET
69static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p)
70{
71 unsigned long __tmp = __fd / __NFDBITS;
72 unsigned long __rem = __fd % __NFDBITS;
73 return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0;
74}
75
76/*
77 * This will unroll the loop for the normal constant case (8 ints,
78 * for a 256-bit fd_set)
79 */
80#undef __FD_ZERO
81static __inline__ void __FD_ZERO(__kernel_fd_set *__p)
82{
83 unsigned long *__tmp = __p->fds_bits;
84 int __i;
85
86 if (__builtin_constant_p(__FDSET_LONGS)) {
87 switch (__FDSET_LONGS) {
88 case 16:
89 __tmp[ 0] = 0; __tmp[ 1] = 0;
90 __tmp[ 2] = 0; __tmp[ 3] = 0;
91 __tmp[ 4] = 0; __tmp[ 5] = 0;
92 __tmp[ 6] = 0; __tmp[ 7] = 0;
93 __tmp[ 8] = 0; __tmp[ 9] = 0;
94 __tmp[10] = 0; __tmp[11] = 0;
95 __tmp[12] = 0; __tmp[13] = 0;
96 __tmp[14] = 0; __tmp[15] = 0;
97 return;
98
99 case 8:
100 __tmp[ 0] = 0; __tmp[ 1] = 0;
101 __tmp[ 2] = 0; __tmp[ 3] = 0;
102 __tmp[ 4] = 0; __tmp[ 5] = 0;
103 __tmp[ 6] = 0; __tmp[ 7] = 0;
104 return;
105
106 case 4:
107 __tmp[ 0] = 0; __tmp[ 1] = 0;
108 __tmp[ 2] = 0; __tmp[ 3] = 0;
109 return;
110 }
111 }
112 __i = __FDSET_LONGS;
113 while (__i) {
114 __i--;
115 *__tmp = 0;
116 __tmp++;
117 }
118}
119
120#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
121
122#endif /* __ASM_SH_POSIX_TYPES_H */
diff --git a/include/asm-sh/posix_types_64.h b/include/asm-sh/posix_types_64.h
deleted file mode 100644
index 0620317a6f0..00000000000
--- a/include/asm-sh/posix_types_64.h
+++ /dev/null
@@ -1,131 +0,0 @@
1#ifndef __ASM_SH64_POSIX_TYPES_H
2#define __ASM_SH64_POSIX_TYPES_H
3
4/*
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 *
9 * include/asm-sh64/posix_types.h
10 *
11 * Copyright (C) 2000, 2001 Paolo Alberelli
12 * Copyright (C) 2003 Paul Mundt
13 *
14 * This file is generally used by user-level software, so you need to
15 * be a little careful about namespace pollution etc. Also, we cannot
16 * assume GCC is being used.
17 */
18
19typedef unsigned long __kernel_ino_t;
20typedef unsigned short __kernel_mode_t;
21typedef unsigned short __kernel_nlink_t;
22typedef long __kernel_off_t;
23typedef int __kernel_pid_t;
24typedef unsigned short __kernel_ipc_pid_t;
25typedef unsigned short __kernel_uid_t;
26typedef unsigned short __kernel_gid_t;
27typedef long unsigned int __kernel_size_t;
28typedef int __kernel_ssize_t;
29typedef int __kernel_ptrdiff_t;
30typedef long __kernel_time_t;
31typedef long __kernel_suseconds_t;
32typedef long __kernel_clock_t;
33typedef int __kernel_timer_t;
34typedef int __kernel_clockid_t;
35typedef int __kernel_daddr_t;
36typedef char * __kernel_caddr_t;
37typedef unsigned short __kernel_uid16_t;
38typedef unsigned short __kernel_gid16_t;
39typedef unsigned int __kernel_uid32_t;
40typedef unsigned int __kernel_gid32_t;
41
42typedef unsigned short __kernel_old_uid_t;
43typedef unsigned short __kernel_old_gid_t;
44typedef unsigned short __kernel_old_dev_t;
45
46#ifdef __GNUC__
47typedef long long __kernel_loff_t;
48#endif
49
50typedef struct {
51#if defined(__KERNEL__) || defined(__USE_ALL)
52 int val[2];
53#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
54 int __val[2];
55#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
56} __kernel_fsid_t;
57
58#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
59
60#undef __FD_SET
61static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
62{
63 unsigned long __tmp = __fd / __NFDBITS;
64 unsigned long __rem = __fd % __NFDBITS;
65 __fdsetp->fds_bits[__tmp] |= (1UL<<__rem);
66}
67
68#undef __FD_CLR
69static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp)
70{
71 unsigned long __tmp = __fd / __NFDBITS;
72 unsigned long __rem = __fd % __NFDBITS;
73 __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem);
74}
75
76
77#undef __FD_ISSET
78static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p)
79{
80 unsigned long __tmp = __fd / __NFDBITS;
81 unsigned long __rem = __fd % __NFDBITS;
82 return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0;
83}
84
85/*
86 * This will unroll the loop for the normal constant case (8 ints,
87 * for a 256-bit fd_set)
88 */
89#undef __FD_ZERO
90static __inline__ void __FD_ZERO(__kernel_fd_set *__p)
91{
92 unsigned long *__tmp = __p->fds_bits;
93 int __i;
94
95 if (__builtin_constant_p(__FDSET_LONGS)) {
96 switch (__FDSET_LONGS) {
97 case 16:
98 __tmp[ 0] = 0; __tmp[ 1] = 0;
99 __tmp[ 2] = 0; __tmp[ 3] = 0;
100 __tmp[ 4] = 0; __tmp[ 5] = 0;
101 __tmp[ 6] = 0; __tmp[ 7] = 0;
102 __tmp[ 8] = 0; __tmp[ 9] = 0;
103 __tmp[10] = 0; __tmp[11] = 0;
104 __tmp[12] = 0; __tmp[13] = 0;
105 __tmp[14] = 0; __tmp[15] = 0;
106 return;
107
108 case 8:
109 __tmp[ 0] = 0; __tmp[ 1] = 0;
110 __tmp[ 2] = 0; __tmp[ 3] = 0;
111 __tmp[ 4] = 0; __tmp[ 5] = 0;
112 __tmp[ 6] = 0; __tmp[ 7] = 0;
113 return;
114
115 case 4:
116 __tmp[ 0] = 0; __tmp[ 1] = 0;
117 __tmp[ 2] = 0; __tmp[ 3] = 0;
118 return;
119 }
120 }
121 __i = __FDSET_LONGS;
122 while (__i) {
123 __i--;
124 *__tmp = 0;
125 __tmp++;
126 }
127}
128
129#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
130
131#endif /* __ASM_SH64_POSIX_TYPES_H */
diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h
deleted file mode 100644
index b7c7ce80f03..00000000000
--- a/include/asm-sh/processor.h
+++ /dev/null
@@ -1,65 +0,0 @@
1#ifndef __ASM_SH_PROCESSOR_H
2#define __ASM_SH_PROCESSOR_H
3
4#include <asm/cpu-features.h>
5
6#ifndef __ASSEMBLY__
7/*
8 * CPU type and hardware bug flags. Kept separately for each CPU.
9 *
10 * Each one of these also needs a CONFIG_CPU_SUBTYPE_xxx entry
11 * in arch/sh/mm/Kconfig, as well as an entry in arch/sh/kernel/setup.c
12 * for parsing the subtype in get_cpu_subtype().
13 */
14enum cpu_type {
15 /* SH-2 types */
16 CPU_SH7619,
17
18 /* SH-2A types */
19 CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_MXG,
20
21 /* SH-3 types */
22 CPU_SH7705, CPU_SH7706, CPU_SH7707,
23 CPU_SH7708, CPU_SH7708S, CPU_SH7708R,
24 CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712,
25 CPU_SH7720, CPU_SH7721, CPU_SH7729,
26
27 /* SH-4 types */
28 CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,
29 CPU_SH7760, CPU_SH4_202, CPU_SH4_501,
30
31 /* SH-4A types */
32 CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785,
33 CPU_SH7723, CPU_SHX3,
34
35 /* SH4AL-DSP types */
36 CPU_SH7343, CPU_SH7722, CPU_SH7366,
37
38 /* SH-5 types */
39 CPU_SH5_101, CPU_SH5_103,
40
41 /* Unknown subtype */
42 CPU_SH_NONE
43};
44
45/* Forward decl */
46struct sh_cpuinfo;
47
48/* arch/sh/kernel/setup.c */
49const char *get_cpu_subtype(struct sh_cpuinfo *c);
50
51#ifdef CONFIG_VSYSCALL
52int vsyscall_init(void);
53#else
54#define vsyscall_init() do { } while (0)
55#endif
56
57#endif /* __ASSEMBLY__ */
58
59#ifdef CONFIG_SUPERH32
60# include "processor_32.h"
61#else
62# include "processor_64.h"
63#endif
64
65#endif /* __ASM_SH_PROCESSOR_H */
diff --git a/include/asm-sh/processor_32.h b/include/asm-sh/processor_32.h
deleted file mode 100644
index c09305d6a9d..00000000000
--- a/include/asm-sh/processor_32.h
+++ /dev/null
@@ -1,219 +0,0 @@
1/*
2 * include/asm-sh/processor.h
3 *
4 * Copyright (C) 1999, 2000 Niibe Yutaka
5 * Copyright (C) 2002, 2003 Paul Mundt
6 */
7
8#ifndef __ASM_SH_PROCESSOR_32_H
9#define __ASM_SH_PROCESSOR_32_H
10#ifdef __KERNEL__
11
12#include <linux/compiler.h>
13#include <asm/page.h>
14#include <asm/types.h>
15#include <asm/cache.h>
16#include <asm/ptrace.h>
17
18/*
19 * Default implementation of macro that returns current
20 * instruction pointer ("program counter").
21 */
22#define current_text_addr() ({ void *pc; __asm__("mova 1f, %0\n1:":"=z" (pc)); pc; })
23
24/* Core Processor Version Register */
25#define CCN_PVR 0xff000030
26#define CCN_CVR 0xff000040
27#define CCN_PRR 0xff000044
28
29struct sh_cpuinfo {
30 unsigned int type;
31 unsigned long loops_per_jiffy;
32 unsigned long asid_cache;
33
34 struct cache_info icache; /* Primary I-cache */
35 struct cache_info dcache; /* Primary D-cache */
36 struct cache_info scache; /* Secondary cache */
37
38 unsigned long flags;
39} __attribute__ ((aligned(L1_CACHE_BYTES)));
40
41extern struct sh_cpuinfo cpu_data[];
42#define boot_cpu_data cpu_data[0]
43#define current_cpu_data cpu_data[smp_processor_id()]
44#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
45
46/*
47 * User space process size: 2GB.
48 *
49 * Since SH7709 and SH7750 have "area 7", we can't use 0x7c000000--0x7fffffff
50 */
51#define TASK_SIZE 0x7c000000UL
52
53#define STACK_TOP TASK_SIZE
54#define STACK_TOP_MAX STACK_TOP
55
56/* This decides where the kernel will search for a free chunk of vm
57 * space during mmap's.
58 */
59#define TASK_UNMAPPED_BASE (TASK_SIZE / 3)
60
61/*
62 * Bit of SR register
63 *
64 * FD-bit:
65 * When it's set, it means the processor doesn't have right to use FPU,
66 * and it results exception when the floating operation is executed.
67 *
68 * IMASK-bit:
69 * Interrupt level mask
70 */
71#define SR_DSP 0x00001000
72#define SR_IMASK 0x000000f0
73#define SR_FD 0x00008000
74
75/*
76 * FPU structure and data
77 */
78
79struct sh_fpu_hard_struct {
80 unsigned long fp_regs[16];
81 unsigned long xfp_regs[16];
82 unsigned long fpscr;
83 unsigned long fpul;
84
85 long status; /* software status information */
86};
87
88/* Dummy fpu emulator */
89struct sh_fpu_soft_struct {
90 unsigned long fp_regs[16];
91 unsigned long xfp_regs[16];
92 unsigned long fpscr;
93 unsigned long fpul;
94
95 unsigned char lookahead;
96 unsigned long entry_pc;
97};
98
99union sh_fpu_union {
100 struct sh_fpu_hard_struct hard;
101 struct sh_fpu_soft_struct soft;
102};
103
104struct thread_struct {
105 /* Saved registers when thread is descheduled */
106 unsigned long sp;
107 unsigned long pc;
108
109 /* Hardware debugging registers */
110 unsigned long ubc_pc;
111
112 /* floating point info */
113 union sh_fpu_union fpu;
114};
115
116typedef struct {
117 unsigned long seg;
118} mm_segment_t;
119
120/* Count of active tasks with UBC settings */
121extern int ubc_usercnt;
122
123#define INIT_THREAD { \
124 .sp = sizeof(init_stack) + (long) &init_stack, \
125}
126
127/*
128 * Do necessary setup to start up a newly executed thread.
129 */
130#define start_thread(regs, new_pc, new_sp) \
131 set_fs(USER_DS); \
132 regs->pr = 0; \
133 regs->sr = SR_FD; /* User mode. */ \
134 regs->pc = new_pc; \
135 regs->regs[15] = new_sp
136
137/* Forward declaration, a strange C thing */
138struct task_struct;
139struct mm_struct;
140
141/* Free all resources held by a thread. */
142extern void release_thread(struct task_struct *);
143
144/* Prepare to copy thread state - unlazy all lazy status */
145#define prepare_to_copy(tsk) do { } while (0)
146
147/*
148 * create a kernel thread without removing it from tasklists
149 */
150extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
151
152/* Copy and release all segment info associated with a VM */
153#define copy_segments(p, mm) do { } while(0)
154#define release_segments(mm) do { } while(0)
155
156/*
157 * FPU lazy state save handling.
158 */
159
160static __inline__ void disable_fpu(void)
161{
162 unsigned long __dummy;
163
164 /* Set FD flag in SR */
165 __asm__ __volatile__("stc sr, %0\n\t"
166 "or %1, %0\n\t"
167 "ldc %0, sr"
168 : "=&r" (__dummy)
169 : "r" (SR_FD));
170}
171
172static __inline__ void enable_fpu(void)
173{
174 unsigned long __dummy;
175
176 /* Clear out FD flag in SR */
177 __asm__ __volatile__("stc sr, %0\n\t"
178 "and %1, %0\n\t"
179 "ldc %0, sr"
180 : "=&r" (__dummy)
181 : "r" (~SR_FD));
182}
183
184/* Double presision, NANS as NANS, rounding to nearest, no exceptions */
185#define FPSCR_INIT 0x00080000
186
187#define FPSCR_CAUSE_MASK 0x0001f000 /* Cause bits */
188#define FPSCR_FLAG_MASK 0x0000007c /* Flag bits */
189
190/*
191 * Return saved PC of a blocked thread.
192 */
193#define thread_saved_pc(tsk) (tsk->thread.pc)
194
195void show_trace(struct task_struct *tsk, unsigned long *sp,
196 struct pt_regs *regs);
197extern unsigned long get_wchan(struct task_struct *p);
198
199#define KSTK_EIP(tsk) (task_pt_regs(tsk)->pc)
200#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[15])
201
202#define cpu_sleep() __asm__ __volatile__ ("sleep" : : : "memory")
203#define cpu_relax() barrier()
204
205#if defined(CONFIG_CPU_SH2A) || defined(CONFIG_CPU_SH3) || \
206 defined(CONFIG_CPU_SH4)
207#define PREFETCH_STRIDE L1_CACHE_BYTES
208#define ARCH_HAS_PREFETCH
209#define ARCH_HAS_PREFETCHW
210static inline void prefetch(void *x)
211{
212 __asm__ __volatile__ ("pref @%0\n\t" : : "r" (x) : "memory");
213}
214
215#define prefetchw(x) prefetch(x)
216#endif
217
218#endif /* __KERNEL__ */
219#endif /* __ASM_SH_PROCESSOR_32_H */
diff --git a/include/asm-sh/processor_64.h b/include/asm-sh/processor_64.h
deleted file mode 100644
index 88a2edf8fa5..00000000000
--- a/include/asm-sh/processor_64.h
+++ /dev/null
@@ -1,279 +0,0 @@
1#ifndef __ASM_SH_PROCESSOR_64_H
2#define __ASM_SH_PROCESSOR_64_H
3
4/*
5 * include/asm-sh/processor_64.h
6 *
7 * Copyright (C) 2000, 2001 Paolo Alberelli
8 * Copyright (C) 2003 Paul Mundt
9 * Copyright (C) 2004 Richard Curnow
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15#ifndef __ASSEMBLY__
16
17#include <linux/compiler.h>
18#include <asm/page.h>
19#include <asm/types.h>
20#include <asm/cache.h>
21#include <asm/ptrace.h>
22#include <asm/cpu/registers.h>
23
24/*
25 * Default implementation of macro that returns current
26 * instruction pointer ("program counter").
27 */
28#define current_text_addr() ({ \
29void *pc; \
30unsigned long long __dummy = 0; \
31__asm__("gettr tr0, %1\n\t" \
32 "pta 4, tr0\n\t" \
33 "gettr tr0, %0\n\t" \
34 "ptabs %1, tr0\n\t" \
35 :"=r" (pc), "=r" (__dummy) \
36 : "1" (__dummy)); \
37pc; })
38
39/*
40 * TLB information structure
41 *
42 * Defined for both I and D tlb, per-processor.
43 */
44struct tlb_info {
45 unsigned long long next;
46 unsigned long long first;
47 unsigned long long last;
48
49 unsigned int entries;
50 unsigned int step;
51
52 unsigned long flags;
53};
54
55struct sh_cpuinfo {
56 enum cpu_type type;
57 unsigned long loops_per_jiffy;
58 unsigned long asid_cache;
59
60 unsigned int cpu_clock, master_clock, bus_clock, module_clock;
61
62 /* Cache info */
63 struct cache_info icache;
64 struct cache_info dcache;
65 struct cache_info scache;
66
67 /* TLB info */
68 struct tlb_info itlb;
69 struct tlb_info dtlb;
70
71 unsigned long flags;
72};
73
74extern struct sh_cpuinfo cpu_data[];
75#define boot_cpu_data cpu_data[0]
76#define current_cpu_data cpu_data[smp_processor_id()]
77#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
78
79#endif
80
81/*
82 * User space process size: 2GB - 4k.
83 */
84#define TASK_SIZE 0x7ffff000UL
85
86#define STACK_TOP TASK_SIZE
87#define STACK_TOP_MAX STACK_TOP
88
89/* This decides where the kernel will search for a free chunk of vm
90 * space during mmap's.
91 */
92#define TASK_UNMAPPED_BASE (TASK_SIZE / 3)
93
94/*
95 * Bit of SR register
96 *
97 * FD-bit:
98 * When it's set, it means the processor doesn't have right to use FPU,
99 * and it results exception when the floating operation is executed.
100 *
101 * IMASK-bit:
102 * Interrupt level mask
103 *
104 * STEP-bit:
105 * Single step bit
106 *
107 */
108#if defined(CONFIG_SH64_SR_WATCH)
109#define SR_MMU 0x84000000
110#else
111#define SR_MMU 0x80000000
112#endif
113
114#define SR_IMASK 0x000000f0
115#define SR_FD 0x00008000
116#define SR_SSTEP 0x08000000
117
118#ifndef __ASSEMBLY__
119
120/*
121 * FPU structure and data : require 8-byte alignment as we need to access it
122 with fld.p, fst.p
123 */
124
125struct sh_fpu_hard_struct {
126 unsigned long fp_regs[64];
127 unsigned int fpscr;
128 /* long status; * software status information */
129};
130
131#if 0
132/* Dummy fpu emulator */
133struct sh_fpu_soft_struct {
134 unsigned long long fp_regs[32];
135 unsigned int fpscr;
136 unsigned char lookahead;
137 unsigned long entry_pc;
138};
139#endif
140
141union sh_fpu_union {
142 struct sh_fpu_hard_struct hard;
143 /* 'hard' itself only produces 32 bit alignment, yet we need
144 to access it using 64 bit load/store as well. */
145 unsigned long long alignment_dummy;
146};
147
148struct thread_struct {
149 unsigned long sp;
150 unsigned long pc;
151 /* This stores the address of the pt_regs built during a context
152 switch, or of the register save area built for a kernel mode
153 exception. It is used for backtracing the stack of a sleeping task
154 or one that traps in kernel mode. */
155 struct pt_regs *kregs;
156 /* This stores the address of the pt_regs constructed on entry from
157 user mode. It is a fixed value over the lifetime of a process, or
158 NULL for a kernel thread. */
159 struct pt_regs *uregs;
160
161 unsigned long trap_no, error_code;
162 unsigned long address;
163 /* Hardware debugging registers may come here */
164
165 /* floating point info */
166 union sh_fpu_union fpu;
167};
168
169typedef struct {
170 unsigned long seg;
171} mm_segment_t;
172
173#define INIT_MMAP \
174{ &init_mm, 0, 0, NULL, PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL }
175
176extern struct pt_regs fake_swapper_regs;
177
178#define INIT_THREAD { \
179 .sp = sizeof(init_stack) + \
180 (long) &init_stack, \
181 .pc = 0, \
182 .kregs = &fake_swapper_regs, \
183 .uregs = NULL, \
184 .trap_no = 0, \
185 .error_code = 0, \
186 .address = 0, \
187 .fpu = { { { 0, } }, } \
188}
189
190/*
191 * Do necessary setup to start up a newly executed thread.
192 */
193#define SR_USER (SR_MMU | SR_FD)
194
195#define start_thread(regs, new_pc, new_sp) \
196 set_fs(USER_DS); \
197 regs->sr = SR_USER; /* User mode. */ \
198 regs->pc = new_pc - 4; /* Compensate syscall exit */ \
199 regs->pc |= 1; /* Set SHmedia ! */ \
200 regs->regs[18] = 0; \
201 regs->regs[15] = new_sp
202
203/* Forward declaration, a strange C thing */
204struct task_struct;
205struct mm_struct;
206
207/* Free all resources held by a thread. */
208extern void release_thread(struct task_struct *);
209/*
210 * create a kernel thread without removing it from tasklists
211 */
212extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
213
214
215/* Copy and release all segment info associated with a VM */
216#define copy_segments(p, mm) do { } while (0)
217#define release_segments(mm) do { } while (0)
218#define forget_segments() do { } while (0)
219#define prepare_to_copy(tsk) do { } while (0)
220/*
221 * FPU lazy state save handling.
222 */
223
224static inline void disable_fpu(void)
225{
226 unsigned long long __dummy;
227
228 /* Set FD flag in SR */
229 __asm__ __volatile__("getcon " __SR ", %0\n\t"
230 "or %0, %1, %0\n\t"
231 "putcon %0, " __SR "\n\t"
232 : "=&r" (__dummy)
233 : "r" (SR_FD));
234}
235
236static inline void enable_fpu(void)
237{
238 unsigned long long __dummy;
239
240 /* Clear out FD flag in SR */
241 __asm__ __volatile__("getcon " __SR ", %0\n\t"
242 "and %0, %1, %0\n\t"
243 "putcon %0, " __SR "\n\t"
244 : "=&r" (__dummy)
245 : "r" (~SR_FD));
246}
247
248/* Round to nearest, no exceptions on inexact, overflow, underflow,
249 zero-divide, invalid. Configure option for whether to flush denorms to
250 zero, or except if a denorm is encountered. */
251#if defined(CONFIG_SH64_FPU_DENORM_FLUSH)
252#define FPSCR_INIT 0x00040000
253#else
254#define FPSCR_INIT 0x00000000
255#endif
256
257#ifdef CONFIG_SH_FPU
258/* Initialise the FP state of a task */
259void fpinit(struct sh_fpu_hard_struct *fpregs);
260#else
261#define fpinit(fpregs) do { } while (0)
262#endif
263
264extern struct task_struct *last_task_used_math;
265
266/*
267 * Return saved PC of a blocked thread.
268 */
269#define thread_saved_pc(tsk) (tsk->thread.pc)
270
271extern unsigned long get_wchan(struct task_struct *p);
272
273#define KSTK_EIP(tsk) ((tsk)->thread.pc)
274#define KSTK_ESP(tsk) ((tsk)->thread.sp)
275
276#define cpu_relax() barrier()
277
278#endif /* __ASSEMBLY__ */
279#endif /* __ASM_SH_PROCESSOR_64_H */
diff --git a/include/asm-sh/ptrace.h b/include/asm-sh/ptrace.h
deleted file mode 100644
index 7d36dc3bee6..00000000000
--- a/include/asm-sh/ptrace.h
+++ /dev/null
@@ -1,125 +0,0 @@
1#ifndef __ASM_SH_PTRACE_H
2#define __ASM_SH_PTRACE_H
3
4/*
5 * Copyright (C) 1999, 2000 Niibe Yutaka
6 *
7 */
8#if defined(__SH5__)
9struct pt_regs {
10 unsigned long long pc;
11 unsigned long long sr;
12 unsigned long long syscall_nr;
13 unsigned long long regs[63];
14 unsigned long long tregs[8];
15 unsigned long long pad[2];
16};
17#else
18/*
19 * GCC defines register number like this:
20 * -----------------------------
21 * 0 - 15 are integer registers
22 * 17 - 22 are control/special registers
23 * 24 - 39 fp registers
24 * 40 - 47 xd registers
25 * 48 - fpscr register
26 * -----------------------------
27 *
28 * We follows above, except:
29 * 16 --- program counter (PC)
30 * 22 --- syscall #
31 * 23 --- floating point communication register
32 */
33#define REG_REG0 0
34#define REG_REG15 15
35
36#define REG_PC 16
37
38#define REG_PR 17
39#define REG_SR 18
40#define REG_GBR 19
41#define REG_MACH 20
42#define REG_MACL 21
43
44#define REG_SYSCALL 22
45
46#define REG_FPREG0 23
47#define REG_FPREG15 38
48#define REG_XFREG0 39
49#define REG_XFREG15 54
50
51#define REG_FPSCR 55
52#define REG_FPUL 56
53
54/*
55 * This struct defines the way the registers are stored on the
56 * kernel stack during a system call or other kernel entry.
57 */
58struct pt_regs {
59 unsigned long regs[16];
60 unsigned long pc;
61 unsigned long pr;
62 unsigned long sr;
63 unsigned long gbr;
64 unsigned long mach;
65 unsigned long macl;
66 long tra;
67};
68
69/*
70 * This struct defines the way the DSP registers are stored on the
71 * kernel stack during a system call or other kernel entry.
72 */
73struct pt_dspregs {
74 unsigned long a1;
75 unsigned long a0g;
76 unsigned long a1g;
77 unsigned long m0;
78 unsigned long m1;
79 unsigned long a0;
80 unsigned long x0;
81 unsigned long x1;
82 unsigned long y0;
83 unsigned long y1;
84 unsigned long dsr;
85 unsigned long rs;
86 unsigned long re;
87 unsigned long mod;
88};
89
90#define PTRACE_GETDSPREGS 55
91#define PTRACE_SETDSPREGS 56
92#endif
93
94#ifdef __KERNEL__
95#include <asm/addrspace.h>
96
97#define user_mode(regs) (((regs)->sr & 0x40000000)==0)
98#define instruction_pointer(regs) ((unsigned long)(regs)->pc)
99
100extern void show_regs(struct pt_regs *);
101
102#ifdef CONFIG_SH_DSP
103#define task_pt_regs(task) \
104 ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \
105 - sizeof(struct pt_dspregs) - sizeof(unsigned long)) - 1)
106#else
107#define task_pt_regs(task) \
108 ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \
109 - sizeof(unsigned long)) - 1)
110#endif
111
112static inline unsigned long profile_pc(struct pt_regs *regs)
113{
114 unsigned long pc = instruction_pointer(regs);
115
116#ifdef P2SEG
117 if (pc >= P2SEG && pc < P3SEG)
118 pc -= 0x20000000;
119#endif
120
121 return pc;
122}
123#endif /* __KERNEL__ */
124
125#endif /* __ASM_SH_PTRACE_H */
diff --git a/include/asm-sh/push-switch.h b/include/asm-sh/push-switch.h
deleted file mode 100644
index 4903f9e52dd..00000000000
--- a/include/asm-sh/push-switch.h
+++ /dev/null
@@ -1,31 +0,0 @@
1#ifndef __ASM_SH_PUSH_SWITCH_H
2#define __ASM_SH_PUSH_SWITCH_H
3
4#include <linux/timer.h>
5#include <linux/interrupt.h>
6#include <linux/workqueue.h>
7#include <linux/platform_device.h>
8
9struct push_switch {
10 /* switch state */
11 unsigned int state:1;
12 /* debounce timer */
13 struct timer_list debounce;
14 /* workqueue */
15 struct work_struct work;
16 /* platform device, for workqueue handler */
17 struct platform_device *pdev;
18};
19
20struct push_switch_platform_info {
21 /* IRQ handler */
22 irqreturn_t (*irq_handler)(int irq, void *data);
23 /* Special IRQ flags */
24 unsigned int irq_flags;
25 /* Bit location of switch */
26 unsigned int bit;
27 /* Symbolic switch name */
28 const char *name;
29};
30
31#endif /* __ASM_SH_PUSH_SWITCH_H */
diff --git a/include/asm-sh/r7780rp.h b/include/asm-sh/r7780rp.h
deleted file mode 100644
index 306f7359f7d..00000000000
--- a/include/asm-sh/r7780rp.h
+++ /dev/null
@@ -1,198 +0,0 @@
1#ifndef __ASM_SH_RENESAS_R7780RP_H
2#define __ASM_SH_RENESAS_R7780RP_H
3
4/* Box specific addresses. */
5#if defined(CONFIG_SH_R7780MP)
6#define PA_BCR 0xa4000000 /* FPGA */
7#define PA_SDPOW (-1)
8
9#define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */
10#define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */
11#define PA_IRLPRI1 (PA_BCR+0x0004) /* Interrupt Priorty 1 */
12#define PA_IRLPRI2 (PA_BCR+0x0006) /* Interrupt Priorty 2 */
13#define PA_IRLPRI3 (PA_BCR+0x0008) /* Interrupt Priorty 3 */
14#define PA_IRLPRI4 (PA_BCR+0x000a) /* Interrupt Priorty 4 */
15#define PA_RSTCTL (PA_BCR+0x000c) /* Reset Control */
16#define PA_PCIBD (PA_BCR+0x000e) /* PCI Board detect control */
17#define PA_PCICD (PA_BCR+0x0010) /* PCI Conector detect control */
18#define PA_EXTGIO (PA_BCR+0x0016) /* Extension GPIO Control */
19#define PA_IVDRMON (PA_BCR+0x0018) /* iVDR Moniter control */
20#define PA_IVDRCTL (PA_BCR+0x001a) /* iVDR control */
21#define PA_OBLED (PA_BCR+0x001c) /* On Board LED control */
22#define PA_OBSW (PA_BCR+0x001e) /* On Board Switch control */
23#define PA_AUDIOSEL (PA_BCR+0x0020) /* Sound Interface Select control */
24#define PA_EXTPLR (PA_BCR+0x001e) /* Extention Pin Polarity control */
25#define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */
26#define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */
27#define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */
28#define PA_TPXPOS (PA_BCR+0x0106) /* Touch Panel X position control */
29#define PA_TPYPOS (PA_BCR+0x0108) /* Touch Panel Y position control */
30#define PA_DBSW (PA_BCR+0x0200) /* Debug Board Switch control */
31#define PA_CFCTL (PA_BCR+0x0300) /* CF Timing control */
32#define PA_CFPOW (PA_BCR+0x0302) /* CF Power control */
33#define PA_CFCDINTCLR (PA_BCR+0x0304) /* CF Insert Interrupt clear */
34#define PA_SCSMR0 (PA_BCR+0x0400) /* SCIF0 Serial mode control */
35#define PA_SCBRR0 (PA_BCR+0x0404) /* SCIF0 Bit rate control */
36#define PA_SCSCR0 (PA_BCR+0x0408) /* SCIF0 Serial control */
37#define PA_SCFTDR0 (PA_BCR+0x040c) /* SCIF0 Send FIFO control */
38#define PA_SCFSR0 (PA_BCR+0x0410) /* SCIF0 Serial status control */
39#define PA_SCFRDR0 (PA_BCR+0x0414) /* SCIF0 Receive FIFO control */
40#define PA_SCFCR0 (PA_BCR+0x0418) /* SCIF0 FIFO control */
41#define PA_SCTFDR0 (PA_BCR+0x041c) /* SCIF0 Send FIFO data control */
42#define PA_SCRFDR0 (PA_BCR+0x0420) /* SCIF0 Receive FIFO data control */
43#define PA_SCSPTR0 (PA_BCR+0x0424) /* SCIF0 Serial Port control */
44#define PA_SCLSR0 (PA_BCR+0x0428) /* SCIF0 Line Status control */
45#define PA_SCRER0 (PA_BCR+0x042c) /* SCIF0 Serial Error control */
46#define PA_SCSMR1 (PA_BCR+0x0500) /* SCIF1 Serial mode control */
47#define PA_SCBRR1 (PA_BCR+0x0504) /* SCIF1 Bit rate control */
48#define PA_SCSCR1 (PA_BCR+0x0508) /* SCIF1 Serial control */
49#define PA_SCFTDR1 (PA_BCR+0x050c) /* SCIF1 Send FIFO control */
50#define PA_SCFSR1 (PA_BCR+0x0510) /* SCIF1 Serial status control */
51#define PA_SCFRDR1 (PA_BCR+0x0514) /* SCIF1 Receive FIFO control */
52#define PA_SCFCR1 (PA_BCR+0x0518) /* SCIF1 FIFO control */
53#define PA_SCTFDR1 (PA_BCR+0x051c) /* SCIF1 Send FIFO data control */
54#define PA_SCRFDR1 (PA_BCR+0x0520) /* SCIF1 Receive FIFO data control */
55#define PA_SCSPTR1 (PA_BCR+0x0524) /* SCIF1 Serial Port control */
56#define PA_SCLSR1 (PA_BCR+0x0528) /* SCIF1 Line Status control */
57#define PA_SCRER1 (PA_BCR+0x052c) /* SCIF1 Serial Error control */
58#define PA_SMCR (PA_BCR+0x0600) /* 2-wire Serial control */
59#define PA_SMSMADR (PA_BCR+0x0602) /* 2-wire Serial Slave control */
60#define PA_SMMR (PA_BCR+0x0604) /* 2-wire Serial Mode control */
61#define PA_SMSADR1 (PA_BCR+0x0606) /* 2-wire Serial Address1 control */
62#define PA_SMTRDR1 (PA_BCR+0x0646) /* 2-wire Serial Data1 control */
63#define PA_VERREG (PA_BCR+0x0700) /* FPGA Version Register */
64#define PA_POFF (PA_BCR+0x0800) /* System Power Off control */
65#define PA_PMR (PA_BCR+0x0900) /* */
66
67#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
68#define IVDR_CK_ON 8 /* iVDR Clock ON */
69
70#elif defined(CONFIG_SH_R7780RP)
71#define PA_POFF (-1)
72
73#define PA_BCR 0xa5000000 /* FPGA */
74#define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */
75#define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */
76#define PA_SDPOW (PA_BCR+0x0004) /* SD Power control */
77#define PA_RSTCTL (PA_BCR+0x0006) /* Device Reset control */
78#define PA_PCIBD (PA_BCR+0x0008) /* PCI Board detect control */
79#define PA_PCICD (PA_BCR+0x000a) /* PCI Conector detect control */
80#define PA_ZIGIO1 (PA_BCR+0x000c) /* Zigbee IO control 1 */
81#define PA_ZIGIO2 (PA_BCR+0x000e) /* Zigbee IO control 2 */
82#define PA_ZIGIO3 (PA_BCR+0x0010) /* Zigbee IO control 3 */
83#define PA_ZIGIO4 (PA_BCR+0x0012) /* Zigbee IO control 4 */
84#define PA_IVDRMON (PA_BCR+0x0014) /* iVDR Moniter control */
85#define PA_IVDRCTL (PA_BCR+0x0016) /* iVDR control */
86#define PA_OBLED (PA_BCR+0x0018) /* On Board LED control */
87#define PA_OBSW (PA_BCR+0x001a) /* On Board Switch control */
88#define PA_AUDIOSEL (PA_BCR+0x001c) /* Sound Interface Select control */
89#define PA_EXTPLR (PA_BCR+0x001e) /* Extention Pin Polarity control */
90#define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */
91#define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */
92#define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */
93#define PA_TPXPOS (PA_BCR+0x0106) /* Touch Panel X position control */
94#define PA_TPYPOS (PA_BCR+0x0108) /* Touch Panel Y position control */
95#define PA_DBDET (PA_BCR+0x0200) /* Debug Board detect control */
96#define PA_DBDISPCTL (PA_BCR+0x0202) /* Debug Board Dot timing control */
97#define PA_DBSW (PA_BCR+0x0204) /* Debug Board Switch control */
98#define PA_CFCTL (PA_BCR+0x0300) /* CF Timing control */
99#define PA_CFPOW (PA_BCR+0x0302) /* CF Power control */
100#define PA_CFCDINTCLR (PA_BCR+0x0304) /* CF Insert Interrupt clear */
101#define PA_SCSMR (PA_BCR+0x0400) /* SCIF Serial mode control */
102#define PA_SCBRR (PA_BCR+0x0402) /* SCIF Bit rate control */
103#define PA_SCSCR (PA_BCR+0x0404) /* SCIF Serial control */
104#define PA_SCFDTR (PA_BCR+0x0406) /* SCIF Send FIFO control */
105#define PA_SCFSR (PA_BCR+0x0408) /* SCIF Serial status control */
106#define PA_SCFRDR (PA_BCR+0x040a) /* SCIF Receive FIFO control */
107#define PA_SCFCR (PA_BCR+0x040c) /* SCIF FIFO control */
108#define PA_SCFDR (PA_BCR+0x040e) /* SCIF FIFO data control */
109#define PA_SCLSR (PA_BCR+0x0412) /* SCIF Line Status control */
110#define PA_SMCR (PA_BCR+0x0500) /* 2-wire Serial control */
111#define PA_SMSMADR (PA_BCR+0x0502) /* 2-wire Serial Slave control */
112#define PA_SMMR (PA_BCR+0x0504) /* 2-wire Serial Mode control */
113#define PA_SMSADR1 (PA_BCR+0x0506) /* 2-wire Serial Address1 control */
114#define PA_SMTRDR1 (PA_BCR+0x0546) /* 2-wire Serial Data1 control */
115#define PA_VERREG (PA_BCR+0x0600) /* FPGA Version Register */
116
117#define PA_AX88796L 0xa5800400 /* AX88796L Area */
118#define PA_SC1602BSLB 0xa6000000 /* SC1602BSLB Area */
119#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
120#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */
121
122#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
123
124#define IVDR_CK_ON 8 /* iVDR Clock ON */
125
126#elif defined(CONFIG_SH_R7785RP)
127#define PA_BCR 0xa4000000 /* FPGA */
128#define PA_SDPOW (-1)
129
130#define PA_PCISCR (PA_BCR+0x0000)
131#define PA_IRLPRA (PA_BCR+0x0002)
132#define PA_IRLPRB (PA_BCR+0x0004)
133#define PA_IRLPRC (PA_BCR+0x0006)
134#define PA_IRLPRD (PA_BCR+0x0008)
135#define IRLCNTR1 (PA_BCR+0x0010)
136#define PA_IRLPRE (PA_BCR+0x000a)
137#define PA_IRLPRF (PA_BCR+0x000c)
138#define PA_EXIRLCR (PA_BCR+0x000e)
139#define PA_IRLMCR1 (PA_BCR+0x0010)
140#define PA_IRLMCR2 (PA_BCR+0x0012)
141#define PA_IRLSSR1 (PA_BCR+0x0014)
142#define PA_IRLSSR2 (PA_BCR+0x0016)
143#define PA_CFTCR (PA_BCR+0x0100)
144#define PA_CFPCR (PA_BCR+0x0102)
145#define PA_PCICR (PA_BCR+0x0110)
146#define PA_IVDRCTL (PA_BCR+0x0112)
147#define PA_IVDRSR (PA_BCR+0x0114)
148#define PA_PDRSTCR (PA_BCR+0x0116)
149#define PA_POFF (PA_BCR+0x0120)
150#define PA_LCDCR (PA_BCR+0x0130)
151#define PA_TPCR (PA_BCR+0x0140)
152#define PA_TPCKCR (PA_BCR+0x0142)
153#define PA_TPRSTR (PA_BCR+0x0144)
154#define PA_TPXPDR (PA_BCR+0x0146)
155#define PA_TPYPDR (PA_BCR+0x0148)
156#define PA_GPIOPFR (PA_BCR+0x0150)
157#define PA_GPIODR (PA_BCR+0x0152)
158#define PA_OBLED (PA_BCR+0x0154)
159#define PA_SWSR (PA_BCR+0x0156)
160#define PA_VERREG (PA_BCR+0x0158)
161#define PA_SMCR (PA_BCR+0x0200)
162#define PA_SMSMADR (PA_BCR+0x0202)
163#define PA_SMMR (PA_BCR+0x0204)
164#define PA_SMSADR1 (PA_BCR+0x0206)
165#define PA_SMSADR32 (PA_BCR+0x0244)
166#define PA_SMTRDR1 (PA_BCR+0x0246)
167#define PA_SMTRDR16 (PA_BCR+0x0264)
168#define PA_CU3MDR (PA_BCR+0x0300)
169#define PA_CU5MDR (PA_BCR+0x0302)
170#define PA_MMSR (PA_BCR+0x0400)
171
172#define IVDR_CK_ON 4 /* iVDR Clock ON */
173#endif
174
175#define HL_FPGA_IRQ_BASE 200
176#define HL_NR_IRL 15
177
178#define IRQ_AX88796 (HL_FPGA_IRQ_BASE + 0)
179#define IRQ_CF (HL_FPGA_IRQ_BASE + 1)
180#define IRQ_PSW (HL_FPGA_IRQ_BASE + 2)
181#define IRQ_EXT0 (HL_FPGA_IRQ_BASE + 3)
182#define IRQ_EXT1 (HL_FPGA_IRQ_BASE + 4)
183#define IRQ_EXT2 (HL_FPGA_IRQ_BASE + 5)
184#define IRQ_EXT3 (HL_FPGA_IRQ_BASE + 6)
185#define IRQ_EXT4 (HL_FPGA_IRQ_BASE + 7)
186#define IRQ_EXT5 (HL_FPGA_IRQ_BASE + 8)
187#define IRQ_EXT6 (HL_FPGA_IRQ_BASE + 9)
188#define IRQ_EXT7 (HL_FPGA_IRQ_BASE + 10)
189#define IRQ_SMBUS (HL_FPGA_IRQ_BASE + 11)
190#define IRQ_TP (HL_FPGA_IRQ_BASE + 12)
191#define IRQ_RTC (HL_FPGA_IRQ_BASE + 13)
192#define IRQ_TH_ALERT (HL_FPGA_IRQ_BASE + 14)
193#define IRQ_SCIF0 (HL_FPGA_IRQ_BASE + 15)
194#define IRQ_SCIF1 (HL_FPGA_IRQ_BASE + 16)
195
196unsigned char *highlander_plat_irq_setup(void);
197
198#endif /* __ASM_SH_RENESAS_R7780RP */
diff --git a/include/asm-sh/resource.h b/include/asm-sh/resource.h
deleted file mode 100644
index 9c2499a86ec..00000000000
--- a/include/asm-sh/resource.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef __ASM_SH_RESOURCE_H
2#define __ASM_SH_RESOURCE_H
3
4#include <asm-generic/resource.h>
5
6#endif /* __ASM_SH_RESOURCE_H */
diff --git a/include/asm-sh/rtc.h b/include/asm-sh/rtc.h
deleted file mode 100644
index ec45ba8e11d..00000000000
--- a/include/asm-sh/rtc.h
+++ /dev/null
@@ -1,16 +0,0 @@
1#ifndef _ASM_RTC_H
2#define _ASM_RTC_H
3
4extern void (*board_time_init)(void);
5extern void (*rtc_sh_get_time)(struct timespec *);
6extern int (*rtc_sh_set_time)(const time_t);
7
8#define RTC_CAP_4_DIGIT_YEAR (1 << 0)
9
10struct sh_rtc_platform_info {
11 unsigned long capabilities;
12};
13
14#include <asm/cpu/rtc.h>
15
16#endif /* _ASM_RTC_H */
diff --git a/include/asm-sh/rts7751r2d.h b/include/asm-sh/rts7751r2d.h
deleted file mode 100644
index 0a800157b82..00000000000
--- a/include/asm-sh/rts7751r2d.h
+++ /dev/null
@@ -1,70 +0,0 @@
1#ifndef __ASM_SH_RENESAS_RTS7751R2D_H
2#define __ASM_SH_RENESAS_RTS7751R2D_H
3
4/*
5 * linux/include/asm-sh/renesas_rts7751r2d.h
6 *
7 * Copyright (C) 2000 Atom Create Engineering Co., Ltd.
8 *
9 * Renesas Technology Sales RTS7751R2D support
10 */
11
12/* Board specific addresses. */
13
14#define PA_BCR 0xa4000000 /* FPGA */
15#define PA_IRLMON 0xa4000002 /* Interrupt Status control */
16#define PA_CFCTL 0xa4000004 /* CF Timing control */
17#define PA_CFPOW 0xa4000006 /* CF Power control */
18#define PA_DISPCTL 0xa4000008 /* Display Timing control */
19#define PA_SDMPOW 0xa400000a /* SD Power control */
20#define PA_RTCCE 0xa400000c /* RTC(9701) Enable control */
21#define PA_PCICD 0xa400000e /* PCI Extention detect control */
22#define PA_VOYAGERRTS 0xa4000020 /* VOYAGER Reset control */
23
24#define PA_R2D1_AXRST 0xa4000022 /* AX_LAN Reset control */
25#define PA_R2D1_CFRST 0xa4000024 /* CF Reset control */
26#define PA_R2D1_ADMRTS 0xa4000026 /* SD Reset control */
27#define PA_R2D1_EXTRST 0xa4000028 /* Extention Reset control */
28#define PA_R2D1_CFCDINTCLR 0xa400002a /* CF Insert Interrupt clear */
29
30#define PA_R2DPLUS_CFRST 0xa4000022 /* CF Reset control */
31#define PA_R2DPLUS_ADMRTS 0xa4000024 /* SD Reset control */
32#define PA_R2DPLUS_EXTRST 0xa4000026 /* Extention Reset control */
33#define PA_R2DPLUS_CFCDINTCLR 0xa4000028 /* CF Insert Interrupt clear */
34#define PA_R2DPLUS_KEYCTLCLR 0xa400002a /* Key Interrupt clear */
35
36#define PA_POWOFF 0xa4000030 /* Board Power OFF control */
37#define PA_VERREG 0xa4000032 /* FPGA Version Register */
38#define PA_INPORT 0xa4000034 /* KEY Input Port control */
39#define PA_OUTPORT 0xa4000036 /* LED control */
40#define PA_BVERREG 0xa4000038 /* Board Revision Register */
41
42#define PA_AX88796L 0xaa000400 /* AX88796L Area */
43#define PA_VOYAGER 0xab000000 /* VOYAGER GX Area */
44#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
45#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */
46
47#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
48
49#define R2D_FPGA_IRQ_BASE 100
50
51#define IRQ_VOYAGER (R2D_FPGA_IRQ_BASE + 0)
52#define IRQ_EXT (R2D_FPGA_IRQ_BASE + 1)
53#define IRQ_TP (R2D_FPGA_IRQ_BASE + 2)
54#define IRQ_RTC_T (R2D_FPGA_IRQ_BASE + 3)
55#define IRQ_RTC_A (R2D_FPGA_IRQ_BASE + 4)
56#define IRQ_SDCARD (R2D_FPGA_IRQ_BASE + 5)
57#define IRQ_CF_CD (R2D_FPGA_IRQ_BASE + 6)
58#define IRQ_CF_IDE (R2D_FPGA_IRQ_BASE + 7)
59#define IRQ_AX88796 (R2D_FPGA_IRQ_BASE + 8)
60#define IRQ_KEY (R2D_FPGA_IRQ_BASE + 9)
61#define IRQ_PCI_INTA (R2D_FPGA_IRQ_BASE + 10)
62#define IRQ_PCI_INTB (R2D_FPGA_IRQ_BASE + 11)
63#define IRQ_PCI_INTC (R2D_FPGA_IRQ_BASE + 12)
64#define IRQ_PCI_INTD (R2D_FPGA_IRQ_BASE + 13)
65
66/* arch/sh/boards/renesas/rts7751r2d/irq.c */
67void init_rts7751r2d_IRQ(void);
68int rts7751r2d_irq_demux(int);
69
70#endif /* __ASM_SH_RENESAS_RTS7751R2D */
diff --git a/include/asm-sh/rwsem.h b/include/asm-sh/rwsem.h
deleted file mode 100644
index 1987f3ea7f1..00000000000
--- a/include/asm-sh/rwsem.h
+++ /dev/null
@@ -1,188 +0,0 @@
1/*
2 * include/asm-sh/rwsem.h: R/W semaphores for SH using the stuff
3 * in lib/rwsem.c.
4 */
5
6#ifndef _ASM_SH_RWSEM_H
7#define _ASM_SH_RWSEM_H
8
9#ifndef _LINUX_RWSEM_H
10#error "please don't include asm/rwsem.h directly, use linux/rwsem.h instead"
11#endif
12
13#ifdef __KERNEL__
14#include <linux/list.h>
15#include <linux/spinlock.h>
16#include <asm/atomic.h>
17#include <asm/system.h>
18
19/*
20 * the semaphore definition
21 */
22struct rw_semaphore {
23 long count;
24#define RWSEM_UNLOCKED_VALUE 0x00000000
25#define RWSEM_ACTIVE_BIAS 0x00000001
26#define RWSEM_ACTIVE_MASK 0x0000ffff
27#define RWSEM_WAITING_BIAS (-0x00010000)
28#define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS
29#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
30 spinlock_t wait_lock;
31 struct list_head wait_list;
32#ifdef CONFIG_DEBUG_LOCK_ALLOC
33 struct lockdep_map dep_map;
34#endif
35};
36
37#ifdef CONFIG_DEBUG_LOCK_ALLOC
38# define __RWSEM_DEP_MAP_INIT(lockname) , .dep_map = { .name = #lockname }
39#else
40# define __RWSEM_DEP_MAP_INIT(lockname)
41#endif
42
43#define __RWSEM_INITIALIZER(name) \
44 { RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, \
45 LIST_HEAD_INIT((name).wait_list) \
46 __RWSEM_DEP_MAP_INIT(name) }
47
48#define DECLARE_RWSEM(name) \
49 struct rw_semaphore name = __RWSEM_INITIALIZER(name)
50
51extern struct rw_semaphore *rwsem_down_read_failed(struct rw_semaphore *sem);
52extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem);
53extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem);
54extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem);
55
56extern void __init_rwsem(struct rw_semaphore *sem, const char *name,
57 struct lock_class_key *key);
58
59#define init_rwsem(sem) \
60do { \
61 static struct lock_class_key __key; \
62 \
63 __init_rwsem((sem), #sem, &__key); \
64} while (0)
65
66static inline void init_rwsem(struct rw_semaphore *sem)
67{
68 sem->count = RWSEM_UNLOCKED_VALUE;
69 spin_lock_init(&sem->wait_lock);
70 INIT_LIST_HEAD(&sem->wait_list);
71}
72
73/*
74 * lock for reading
75 */
76static inline void __down_read(struct rw_semaphore *sem)
77{
78 if (atomic_inc_return((atomic_t *)(&sem->count)) > 0)
79 smp_wmb();
80 else
81 rwsem_down_read_failed(sem);
82}
83
84static inline int __down_read_trylock(struct rw_semaphore *sem)
85{
86 int tmp;
87
88 while ((tmp = sem->count) >= 0) {
89 if (tmp == cmpxchg(&sem->count, tmp,
90 tmp + RWSEM_ACTIVE_READ_BIAS)) {
91 smp_wmb();
92 return 1;
93 }
94 }
95 return 0;
96}
97
98/*
99 * lock for writing
100 */
101static inline void __down_write(struct rw_semaphore *sem)
102{
103 int tmp;
104
105 tmp = atomic_add_return(RWSEM_ACTIVE_WRITE_BIAS,
106 (atomic_t *)(&sem->count));
107 if (tmp == RWSEM_ACTIVE_WRITE_BIAS)
108 smp_wmb();
109 else
110 rwsem_down_write_failed(sem);
111}
112
113static inline int __down_write_trylock(struct rw_semaphore *sem)
114{
115 int tmp;
116
117 tmp = cmpxchg(&sem->count, RWSEM_UNLOCKED_VALUE,
118 RWSEM_ACTIVE_WRITE_BIAS);
119 smp_wmb();
120 return tmp == RWSEM_UNLOCKED_VALUE;
121}
122
123/*
124 * unlock after reading
125 */
126static inline void __up_read(struct rw_semaphore *sem)
127{
128 int tmp;
129
130 smp_wmb();
131 tmp = atomic_dec_return((atomic_t *)(&sem->count));
132 if (tmp < -1 && (tmp & RWSEM_ACTIVE_MASK) == 0)
133 rwsem_wake(sem);
134}
135
136/*
137 * unlock after writing
138 */
139static inline void __up_write(struct rw_semaphore *sem)
140{
141 smp_wmb();
142 if (atomic_sub_return(RWSEM_ACTIVE_WRITE_BIAS,
143 (atomic_t *)(&sem->count)) < 0)
144 rwsem_wake(sem);
145}
146
147/*
148 * implement atomic add functionality
149 */
150static inline void rwsem_atomic_add(int delta, struct rw_semaphore *sem)
151{
152 atomic_add(delta, (atomic_t *)(&sem->count));
153}
154
155/*
156 * downgrade write lock to read lock
157 */
158static inline void __downgrade_write(struct rw_semaphore *sem)
159{
160 int tmp;
161
162 smp_wmb();
163 tmp = atomic_add_return(-RWSEM_WAITING_BIAS, (atomic_t *)(&sem->count));
164 if (tmp < 0)
165 rwsem_downgrade_wake(sem);
166}
167
168static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
169{
170 __down_write(sem);
171}
172
173/*
174 * implement exchange and add functionality
175 */
176static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
177{
178 smp_mb();
179 return atomic_add_return(delta, (atomic_t *)(&sem->count));
180}
181
182static inline int rwsem_is_locked(struct rw_semaphore *sem)
183{
184 return (sem->count != 0);
185}
186
187#endif /* __KERNEL__ */
188#endif /* _ASM_SH_RWSEM_H */
diff --git a/include/asm-sh/scatterlist.h b/include/asm-sh/scatterlist.h
deleted file mode 100644
index 2084d037369..00000000000
--- a/include/asm-sh/scatterlist.h
+++ /dev/null
@@ -1,27 +0,0 @@
1#ifndef __ASM_SH_SCATTERLIST_H
2#define __ASM_SH_SCATTERLIST_H
3
4#include <asm/types.h>
5
6struct scatterlist {
7#ifdef CONFIG_DEBUG_SG
8 unsigned long sg_magic;
9#endif
10 unsigned long page_link;
11 unsigned int offset;/* for highmem, page offset */
12 dma_addr_t dma_address;
13 unsigned int length;
14};
15
16#define ISA_DMA_THRESHOLD PHYS_ADDR_MASK
17
18/* These macros should be used after a pci_map_sg call has been done
19 * to get bus addresses of each of the SG entries and their lengths.
20 * You should only work with the number of sg entries pci_map_sg
21 * returns, or alternatively stop on the first sg_dma_len(sg) which
22 * is 0.
23 */
24#define sg_dma_address(sg) ((sg)->dma_address)
25#define sg_dma_len(sg) ((sg)->length)
26
27#endif /* !(__ASM_SH_SCATTERLIST_H) */
diff --git a/include/asm-sh/sdk7780.h b/include/asm-sh/sdk7780.h
deleted file mode 100644
index 697dc865f21..00000000000
--- a/include/asm-sh/sdk7780.h
+++ /dev/null
@@ -1,81 +0,0 @@
1#ifndef __ASM_SH_RENESAS_SDK7780_H
2#define __ASM_SH_RENESAS_SDK7780_H
3
4/*
5 * linux/include/asm-sh/sdk7780.h
6 *
7 * Renesas Solutions SH7780 SDK Support
8 * Copyright (C) 2008 Nicholas Beck <nbeck@mpc-data.co.uk>
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
12 * for more details.
13 */
14#include <asm/addrspace.h>
15
16/* Box specific addresses. */
17#define SE_AREA0_WIDTH 4 /* Area0: 32bit */
18#define PA_ROM 0xa0000000 /* EPROM */
19#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
20#define PA_FROM 0xa0800000 /* Flash-ROM */
21#define PA_FROM_SIZE 0x00400000 /* Flash-ROM size 4M byte */
22#define PA_EXT1 0xa4000000
23#define PA_EXT1_SIZE 0x04000000
24#define PA_SDRAM 0xa8000000 /* DDR-SDRAM(Area2/3) 128MB */
25#define PA_SDRAM_SIZE 0x08000000
26
27#define PA_EXT4 0xb0000000
28#define PA_EXT4_SIZE 0x04000000
29#define PA_EXT_USER PA_EXT4 /* User Expansion Space */
30
31#define PA_PERIPHERAL PA_AREA5_IO
32
33/* SRAM/Reserved */
34#define PA_RESERVED (PA_PERIPHERAL + 0)
35/* FPGA base address */
36#define PA_FPGA (PA_PERIPHERAL + 0x01000000)
37/* SMC LAN91C111 */
38#define PA_LAN (PA_PERIPHERAL + 0x01800000)
39
40
41#define FPGA_SRSTR (PA_FPGA + 0x000) /* System reset */
42#define FPGA_IRQ0SR (PA_FPGA + 0x010) /* IRQ0 status */
43#define FPGA_IRQ0MR (PA_FPGA + 0x020) /* IRQ0 mask */
44#define FPGA_BDMR (PA_FPGA + 0x030) /* Board operating mode */
45#define FPGA_INTT0PRTR (PA_FPGA + 0x040) /* Interrupt test mode0 port */
46#define FPGA_INTT0SELR (PA_FPGA + 0x050) /* Int. test mode0 select */
47#define FPGA_INTT1POLR (PA_FPGA + 0x060) /* Int. test mode0 polarity */
48#define FPGA_NMIR (PA_FPGA + 0x070) /* NMI source */
49#define FPGA_NMIMR (PA_FPGA + 0x080) /* NMI mask */
50#define FPGA_IRQR (PA_FPGA + 0x090) /* IRQX source */
51#define FPGA_IRQMR (PA_FPGA + 0x0A0) /* IRQX mask */
52#define FPGA_SLEDR (PA_FPGA + 0x0B0) /* LED control */
53#define PA_LED FPGA_SLEDR
54#define FPGA_MAPSWR (PA_FPGA + 0x0C0) /* Map switch */
55#define FPGA_FPVERR (PA_FPGA + 0x0D0) /* FPGA version */
56#define FPGA_FPDATER (PA_FPGA + 0x0E0) /* FPGA date */
57#define FPGA_RSE (PA_FPGA + 0x100) /* Reset source */
58#define FPGA_EASR (PA_FPGA + 0x110) /* External area select */
59#define FPGA_SPER (PA_FPGA + 0x120) /* Serial port enable */
60#define FPGA_IMSR (PA_FPGA + 0x130) /* Interrupt mode select */
61#define FPGA_PCIMR (PA_FPGA + 0x140) /* PCI Mode */
62#define FPGA_DIPSWMR (PA_FPGA + 0x150) /* DIPSW monitor */
63#define FPGA_FPODR (PA_FPGA + 0x160) /* Output port data */
64#define FPGA_ATAESR (PA_FPGA + 0x170) /* ATA extended bus status */
65#define FPGA_IRQPOLR (PA_FPGA + 0x180) /* IRQx polarity */
66
67
68#define SDK7780_NR_IRL 15
69/* IDE/ATA interrupt */
70#define IRQ_CFCARD 14
71/* SMC interrupt */
72#define IRQ_ETHERNET 6
73
74
75/* arch/sh/boards/renesas/sdk7780/irq.c */
76void init_sdk7780_IRQ(void);
77
78#define __IO_PREFIX sdk7780
79#include <asm/io_generic.h>
80
81#endif /* __ASM_SH_RENESAS_SDK7780_H */
diff --git a/include/asm-sh/se.h b/include/asm-sh/se.h
deleted file mode 100644
index bd2596c014a..00000000000
--- a/include/asm-sh/se.h
+++ /dev/null
@@ -1,82 +0,0 @@
1#ifndef __ASM_SH_HITACHI_SE_H
2#define __ASM_SH_HITACHI_SE_H
3
4/*
5 * linux/include/asm-sh/hitachi_se.h
6 *
7 * Copyright (C) 2000 Kazumoto Kojima
8 *
9 * Hitachi SolutionEngine support
10 */
11
12/* Box specific addresses. */
13
14#define PA_ROM 0x00000000 /* EPROM */
15#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
16#define PA_FROM 0x01000000 /* EPROM */
17#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
18#define PA_EXT1 0x04000000
19#define PA_EXT1_SIZE 0x04000000
20#define PA_EXT2 0x08000000
21#define PA_EXT2_SIZE 0x04000000
22#define PA_SDRAM 0x0c000000
23#define PA_SDRAM_SIZE 0x04000000
24
25#define PA_EXT4 0x12000000
26#define PA_EXT4_SIZE 0x02000000
27#define PA_EXT5 0x14000000
28#define PA_EXT5_SIZE 0x04000000
29#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */
30
31#define PA_83902 0xb0000000 /* DP83902A */
32#define PA_83902_IF 0xb0040000 /* DP83902A remote io port */
33#define PA_83902_RST 0xb0080000 /* DP83902A reset port */
34
35#define PA_SUPERIO 0xb0400000 /* SMC37C935A super io chip */
36#define PA_DIPSW0 0xb0800000 /* Dip switch 5,6 */
37#define PA_DIPSW1 0xb0800002 /* Dip switch 7,8 */
38#define PA_LED 0xb0c00000 /* LED */
39#if defined(CONFIG_CPU_SUBTYPE_SH7705)
40#define PA_BCR 0xb0e00000
41#else
42#define PA_BCR 0xb1400000 /* FPGA */
43#endif
44
45#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */
46#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */
47#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */
48#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */
49#define MRSHPC_OPTION (PA_MRSHPC + 6)
50#define MRSHPC_CSR (PA_MRSHPC + 8)
51#define MRSHPC_ISR (PA_MRSHPC + 10)
52#define MRSHPC_ICR (PA_MRSHPC + 12)
53#define MRSHPC_CPWCR (PA_MRSHPC + 14)
54#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
55#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
56#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
57#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
58#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
59#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
60#define MRSHPC_CDCR (PA_MRSHPC + 28)
61#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
62
63#define BCR_ILCRA (PA_BCR + 0)
64#define BCR_ILCRB (PA_BCR + 2)
65#define BCR_ILCRC (PA_BCR + 4)
66#define BCR_ILCRD (PA_BCR + 6)
67#define BCR_ILCRE (PA_BCR + 8)
68#define BCR_ILCRF (PA_BCR + 10)
69#define BCR_ILCRG (PA_BCR + 12)
70
71#if defined(CONFIG_CPU_SUBTYPE_SH7705)
72#define IRQ_STNIC 12
73#define IRQ_CFCARD 14
74#else
75#define IRQ_STNIC 10
76#define IRQ_CFCARD 7
77#endif
78
79#define __IO_PREFIX se
80#include <asm/io_generic.h>
81
82#endif /* __ASM_SH_HITACHI_SE_H */
diff --git a/include/asm-sh/se7206.h b/include/asm-sh/se7206.h
deleted file mode 100644
index 698eb80389a..00000000000
--- a/include/asm-sh/se7206.h
+++ /dev/null
@@ -1,13 +0,0 @@
1#ifndef __ASM_SH_SE7206_H
2#define __ASM_SH_SE7206_H
3
4#define PA_SMSC 0x30000000
5#define PA_MRSHPC 0x34000000
6#define PA_LED 0x31400000
7
8void init_se7206_IRQ(void);
9
10#define __IO_PREFIX se7206
11#include <asm/io_generic.h>
12
13#endif /* __ASM_SH_SE7206_H */
diff --git a/include/asm-sh/se7343.h b/include/asm-sh/se7343.h
deleted file mode 100644
index e7914a54aa9..00000000000
--- a/include/asm-sh/se7343.h
+++ /dev/null
@@ -1,82 +0,0 @@
1#ifndef __ASM_SH_HITACHI_SE7343_H
2#define __ASM_SH_HITACHI_SE7343_H
3
4/*
5 * include/asm-sh/se/se7343.h
6 *
7 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
8 *
9 * SH-Mobile SolutionEngine 7343 support
10 */
11
12/* Box specific addresses. */
13
14/* Area 0 */
15#define PA_ROM 0x00000000 /* EPROM */
16#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte(Actually 2MB) */
17#define PA_FROM 0x00400000 /* Flash ROM */
18#define PA_FROM_SIZE 0x00400000 /* Flash size 4M byte */
19#define PA_SRAM 0x00800000 /* SRAM */
20#define PA_FROM_SIZE 0x00400000 /* SRAM size 4M byte */
21/* Area 1 */
22#define PA_EXT1 0x04000000
23#define PA_EXT1_SIZE 0x04000000
24/* Area 2 */
25#define PA_EXT2 0x08000000
26#define PA_EXT2_SIZE 0x04000000
27/* Area 3 */
28#define PA_SDRAM 0x0c000000
29#define PA_SDRAM_SIZE 0x04000000
30/* Area 4 */
31#define PA_PCIC 0x10000000 /* MR-SHPC-01 PCMCIA */
32#define PA_MRSHPC 0xb03fffe0 /* MR-SHPC-01 PCMCIA controller */
33#define PA_MRSHPC_MW1 0xb0400000 /* MR-SHPC-01 memory window base */
34#define PA_MRSHPC_MW2 0xb0500000 /* MR-SHPC-01 attribute window base */
35#define PA_MRSHPC_IO 0xb0600000 /* MR-SHPC-01 I/O window base */
36#define MRSHPC_OPTION (PA_MRSHPC + 6)
37#define MRSHPC_CSR (PA_MRSHPC + 8)
38#define MRSHPC_ISR (PA_MRSHPC + 10)
39#define MRSHPC_ICR (PA_MRSHPC + 12)
40#define MRSHPC_CPWCR (PA_MRSHPC + 14)
41#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
42#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
43#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
44#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
45#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
46#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
47#define MRSHPC_CDCR (PA_MRSHPC + 28)
48#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
49#define PA_LED 0xb0C00000 /* LED */
50#define LED_SHIFT 0
51#define PA_DIPSW 0xb0900000 /* Dip switch 31 */
52#define PA_CPLD_MODESET 0xb1400004 /* CPLD Mode set register */
53#define PA_CPLD_ST 0xb1400008 /* CPLD Interrupt status register */
54#define PA_CPLD_IMSK 0xb140000a /* CPLD Interrupt mask register */
55/* Area 5 */
56#define PA_EXT5 0x14000000
57#define PA_EXT5_SIZE 0x04000000
58/* Area 6 */
59#define PA_LCD1 0xb8000000
60#define PA_LCD2 0xb8800000
61
62#define __IO_PREFIX sh7343se
63#include <asm/io_generic.h>
64
65/* External Multiplexed interrupts */
66#define PC_IRQ0 OFFCHIP_IRQ_BASE
67#define PC_IRQ1 (PC_IRQ0 + 1)
68#define PC_IRQ2 (PC_IRQ1 + 1)
69#define PC_IRQ3 (PC_IRQ2 + 1)
70
71#define EXT_IRQ0 (PC_IRQ3 + 1)
72#define EXT_IRQ1 (EXT_IRQ0 + 1)
73#define EXT_IRQ2 (EXT_IRQ1 + 1)
74#define EXT_IRQ3 (EXT_IRQ2 + 1)
75
76#define USB_IRQ0 (EXT_IRQ3 + 1)
77#define USB_IRQ1 (USB_IRQ0 + 1)
78
79#define UART_IRQ0 (USB_IRQ1 + 1)
80#define UART_IRQ1 (UART_IRQ0 + 1)
81
82#endif /* __ASM_SH_HITACHI_SE7343_H */
diff --git a/include/asm-sh/se7721.h b/include/asm-sh/se7721.h
deleted file mode 100644
index b957f604119..00000000000
--- a/include/asm-sh/se7721.h
+++ /dev/null
@@ -1,70 +0,0 @@
1/*
2 * Copyright (C) 2008 Renesas Solutions Corp.
3 *
4 * Hitachi UL SolutionEngine 7721 Support.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 */
11
12#ifndef __ASM_SH_SE7721_H
13#define __ASM_SH_SE7721_H
14#include <asm/addrspace.h>
15
16/* Box specific addresses. */
17#define SE_AREA0_WIDTH 2 /* Area0: 32bit */
18#define PA_ROM 0xa0000000 /* EPROM */
19#define PA_ROM_SIZE 0x00200000 /* EPROM size 2M byte */
20#define PA_FROM 0xa1000000 /* Flash-ROM */
21#define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */
22#define PA_EXT1 0xa4000000
23#define PA_EXT1_SIZE 0x04000000
24#define PA_SDRAM 0xaC000000 /* SDRAM(Area3) 64MB */
25#define PA_SDRAM_SIZE 0x04000000
26
27#define PA_EXT4 0xb0000000
28#define PA_EXT4_SIZE 0x04000000
29
30#define PA_PERIPHERAL 0xB8000000
31
32#define PA_PCIC PA_PERIPHERAL
33#define PA_MRSHPC (PA_PERIPHERAL + 0x003fffe0)
34#define PA_MRSHPC_MW1 (PA_PERIPHERAL + 0x00400000)
35#define PA_MRSHPC_MW2 (PA_PERIPHERAL + 0x00500000)
36#define PA_MRSHPC_IO (PA_PERIPHERAL + 0x00600000)
37#define MRSHPC_OPTION (PA_MRSHPC + 6)
38#define MRSHPC_CSR (PA_MRSHPC + 8)
39#define MRSHPC_ISR (PA_MRSHPC + 10)
40#define MRSHPC_ICR (PA_MRSHPC + 12)
41#define MRSHPC_CPWCR (PA_MRSHPC + 14)
42#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
43#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
44#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
45#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
46#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
47#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
48#define MRSHPC_CDCR (PA_MRSHPC + 28)
49#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
50
51#define PA_LED 0xB6800000 /* 8bit LED */
52#define PA_FPGA 0xB7000000 /* FPGA base address */
53
54#define MRSHPC_IRQ0 10
55
56#define FPGA_ILSR1 (PA_FPGA + 0x02)
57#define FPGA_ILSR2 (PA_FPGA + 0x03)
58#define FPGA_ILSR3 (PA_FPGA + 0x04)
59#define FPGA_ILSR4 (PA_FPGA + 0x05)
60#define FPGA_ILSR5 (PA_FPGA + 0x06)
61#define FPGA_ILSR6 (PA_FPGA + 0x07)
62#define FPGA_ILSR7 (PA_FPGA + 0x08)
63#define FPGA_ILSR8 (PA_FPGA + 0x09)
64
65void init_se7721_IRQ(void);
66
67#define __IO_PREFIX se7721
68#include <asm/io_generic.h>
69
70#endif /* __ASM_SH_SE7721_H */
diff --git a/include/asm-sh/se7722.h b/include/asm-sh/se7722.h
deleted file mode 100644
index 3690fe5857a..00000000000
--- a/include/asm-sh/se7722.h
+++ /dev/null
@@ -1,116 +0,0 @@
1#ifndef __ASM_SH_SE7722_H
2#define __ASM_SH_SE7722_H
3
4/*
5 * linux/include/asm-sh/se7722.h
6 *
7 * Copyright (C) 2007 Nobuhiro Iwamatsu
8 *
9 * Hitachi UL SolutionEngine 7722 Support.
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 *
15 */
16#include <asm/addrspace.h>
17
18/* Box specific addresses. */
19#define SE_AREA0_WIDTH 4 /* Area0: 32bit */
20#define PA_ROM 0xa0000000 /* EPROM */
21#define PA_ROM_SIZE 0x00200000 /* EPROM size 2M byte */
22#define PA_FROM 0xa1000000 /* Flash-ROM */
23#define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */
24#define PA_EXT1 0xa4000000
25#define PA_EXT1_SIZE 0x04000000
26#define PA_SDRAM 0xaC000000 /* DDR-SDRAM(Area3) 64MB */
27#define PA_SDRAM_SIZE 0x04000000
28
29#define PA_EXT4 0xb0000000
30#define PA_EXT4_SIZE 0x04000000
31
32#define PA_PERIPHERAL 0xB0000000
33
34#define PA_PCIC PA_PERIPHERAL /* MR-SHPC-01 PCMCIA */
35#define PA_MRSHPC (PA_PERIPHERAL + 0x003fffe0) /* MR-SHPC-01 PCMCIA controller */
36#define PA_MRSHPC_MW1 (PA_PERIPHERAL + 0x00400000) /* MR-SHPC-01 memory window base */
37#define PA_MRSHPC_MW2 (PA_PERIPHERAL + 0x00500000) /* MR-SHPC-01 attribute window base */
38#define PA_MRSHPC_IO (PA_PERIPHERAL + 0x00600000) /* MR-SHPC-01 I/O window base */
39#define MRSHPC_OPTION (PA_MRSHPC + 6)
40#define MRSHPC_CSR (PA_MRSHPC + 8)
41#define MRSHPC_ISR (PA_MRSHPC + 10)
42#define MRSHPC_ICR (PA_MRSHPC + 12)
43#define MRSHPC_CPWCR (PA_MRSHPC + 14)
44#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
45#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
46#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
47#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
48#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
49#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
50#define MRSHPC_CDCR (PA_MRSHPC + 28)
51#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
52
53#define PA_LED (PA_PERIPHERAL + 0x00800000) /* 8bit LED */
54#define PA_FPGA (PA_PERIPHERAL + 0x01800000) /* FPGA base address */
55
56#define PA_LAN (PA_AREA6_IO + 0) /* SMC LAN91C111 */
57/* GPIO */
58#define MSTPCR0 0xA4150030UL
59#define MSTPCR1 0xA4150034UL
60#define MSTPCR2 0xA4150038UL
61
62#define FPGA_IN 0xb1840000UL
63#define FPGA_OUT 0xb1840004UL
64
65#define PORT_PECR 0xA4050108UL
66#define PORT_PJCR 0xA4050110UL
67#define PORT_PSELD 0xA4050154UL
68#define PORT_PSELB 0xA4050150UL
69
70#define PORT_PSELC 0xA4050152UL
71#define PORT_PKCR 0xA4050112UL
72#define PORT_PHCR 0xA405010EUL
73#define PORT_PLCR 0xA4050114UL
74#define PORT_PMCR 0xA4050116UL
75#define PORT_PRCR 0xA405011CUL
76#define PORT_PXCR 0xA4050148UL
77#define PORT_PSELA 0xA405014EUL
78#define PORT_PYCR 0xA405014AUL
79#define PORT_PZCR 0xA405014CUL
80#define PORT_HIZCRA 0xA4050158UL
81#define PORT_HIZCRC 0xA405015CUL
82
83/* IRQ */
84#define IRQ0_IRQ 32
85#define IRQ1_IRQ 33
86
87#define IRQ01_MODE 0xb1800000
88#define IRQ01_STS 0xb1800004
89#define IRQ01_MASK 0xb1800008
90
91/* Bits in IRQ01_* registers */
92
93#define SE7722_FPGA_IRQ_USB 0 /* IRQ0 */
94#define SE7722_FPGA_IRQ_SMC 1 /* IRQ0 */
95#define SE7722_FPGA_IRQ_MRSHPC0 2 /* IRQ1 */
96#define SE7722_FPGA_IRQ_MRSHPC1 3 /* IRQ1 */
97#define SE7722_FPGA_IRQ_MRSHPC2 4 /* IRQ1 */
98#define SE7722_FPGA_IRQ_MRSHPC3 5 /* IRQ1 */
99
100#define SE7722_FPGA_IRQ_NR 6
101#define SE7722_FPGA_IRQ_BASE 110
102
103#define MRSHPC_IRQ3 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC3)
104#define MRSHPC_IRQ2 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC2)
105#define MRSHPC_IRQ1 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC1)
106#define MRSHPC_IRQ0 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC0)
107#define SMC_IRQ (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_SMC)
108#define USB_IRQ (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_USB)
109
110/* arch/sh/boards/se/7722/irq.c */
111void init_se7722_IRQ(void);
112
113#define __IO_PREFIX se7722
114#include <asm/io_generic.h>
115
116#endif /* __ASM_SH_SE7722_H */
diff --git a/include/asm-sh/se7751.h b/include/asm-sh/se7751.h
deleted file mode 100644
index b36792ac5d6..00000000000
--- a/include/asm-sh/se7751.h
+++ /dev/null
@@ -1,73 +0,0 @@
1#ifndef __ASM_SH_HITACHI_7751SE_H
2#define __ASM_SH_HITACHI_7751SE_H
3
4/*
5 * linux/include/asm-sh/hitachi_7751se.h
6 *
7 * Copyright (C) 2000 Kazumoto Kojima
8 *
9 * Hitachi SolutionEngine support
10
11 * Modified for 7751 Solution Engine by
12 * Ian da Silva and Jeremy Siegel, 2001.
13 */
14
15/* Box specific addresses. */
16
17#define PA_ROM 0x00000000 /* EPROM */
18#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
19#define PA_FROM 0x01000000 /* EPROM */
20#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
21#define PA_EXT1 0x04000000
22#define PA_EXT1_SIZE 0x04000000
23#define PA_EXT2 0x08000000
24#define PA_EXT2_SIZE 0x04000000
25#define PA_SDRAM 0x0c000000
26#define PA_SDRAM_SIZE 0x04000000
27
28#define PA_EXT4 0x12000000
29#define PA_EXT4_SIZE 0x02000000
30#define PA_EXT5 0x14000000
31#define PA_EXT5_SIZE 0x04000000
32#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */
33
34#define PA_DIPSW0 0xb9000000 /* Dip switch 5,6 */
35#define PA_DIPSW1 0xb9000002 /* Dip switch 7,8 */
36#define PA_LED 0xba000000 /* LED */
37#define PA_BCR 0xbb000000 /* FPGA on the MS7751SE01 */
38
39#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */
40#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */
41#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */
42#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */
43#define MRSHPC_MODE (PA_MRSHPC + 4)
44#define MRSHPC_OPTION (PA_MRSHPC + 6)
45#define MRSHPC_CSR (PA_MRSHPC + 8)
46#define MRSHPC_ISR (PA_MRSHPC + 10)
47#define MRSHPC_ICR (PA_MRSHPC + 12)
48#define MRSHPC_CPWCR (PA_MRSHPC + 14)
49#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
50#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
51#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
52#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
53#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
54#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
55#define MRSHPC_CDCR (PA_MRSHPC + 28)
56#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
57
58#define BCR_ILCRA (PA_BCR + 0)
59#define BCR_ILCRB (PA_BCR + 2)
60#define BCR_ILCRC (PA_BCR + 4)
61#define BCR_ILCRD (PA_BCR + 6)
62#define BCR_ILCRE (PA_BCR + 8)
63#define BCR_ILCRF (PA_BCR + 10)
64#define BCR_ILCRG (PA_BCR + 12)
65
66#define IRQ_79C973 13
67
68void init_7751se_IRQ(void);
69
70#define __IO_PREFIX sh7751se
71#include <asm/io_generic.h>
72
73#endif /* __ASM_SH_HITACHI_7751SE_H */
diff --git a/include/asm-sh/se7780.h b/include/asm-sh/se7780.h
deleted file mode 100644
index 40e9b41458c..00000000000
--- a/include/asm-sh/se7780.h
+++ /dev/null
@@ -1,108 +0,0 @@
1#ifndef __ASM_SH_SE7780_H
2#define __ASM_SH_SE7780_H
3
4/*
5 * linux/include/asm-sh/se7780.h
6 *
7 * Copyright (C) 2006,2007 Nobuhiro Iwamatsu
8 *
9 * Hitachi UL SolutionEngine 7780 Support.
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15#include <asm/addrspace.h>
16
17/* Box specific addresses. */
18#define SE_AREA0_WIDTH 4 /* Area0: 32bit */
19#define PA_ROM 0xa0000000 /* EPROM */
20#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
21#define PA_FROM 0xa1000000 /* Flash-ROM */
22#define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */
23#define PA_EXT1 0xa4000000
24#define PA_EXT1_SIZE 0x04000000
25#define PA_SM501 PA_EXT1 /* Graphic IC (SM501) */
26#define PA_SM501_SIZE PA_EXT1_SIZE /* Graphic IC (SM501) */
27#define PA_SDRAM 0xa8000000 /* DDR-SDRAM(Area2/3) 128MB */
28#define PA_SDRAM_SIZE 0x08000000
29
30#define PA_EXT4 0xb0000000
31#define PA_EXT4_SIZE 0x04000000
32#define PA_EXT_FLASH PA_EXT4 /* Expansion Flash-ROM */
33
34#define PA_PERIPHERAL PA_AREA6_IO /* SW6-6=ON */
35
36#define PA_LAN (PA_PERIPHERAL + 0) /* SMC LAN91C111 */
37#define PA_LED_DISP (PA_PERIPHERAL + 0x02000000) /* 8words LED Display */
38#define DISP_CHAR_RAM (7 << 3)
39#define DISP_SEL0_ADDR (DISP_CHAR_RAM + 0)
40#define DISP_SEL1_ADDR (DISP_CHAR_RAM + 1)
41#define DISP_SEL2_ADDR (DISP_CHAR_RAM + 2)
42#define DISP_SEL3_ADDR (DISP_CHAR_RAM + 3)
43#define DISP_SEL4_ADDR (DISP_CHAR_RAM + 4)
44#define DISP_SEL5_ADDR (DISP_CHAR_RAM + 5)
45#define DISP_SEL6_ADDR (DISP_CHAR_RAM + 6)
46#define DISP_SEL7_ADDR (DISP_CHAR_RAM + 7)
47
48#define DISP_UDC_RAM (5 << 3)
49#define PA_FPGA (PA_PERIPHERAL + 0x03000000) /* FPGA base address */
50
51/* FPGA register address and bit */
52#define FPGA_SFTRST (PA_FPGA + 0) /* Soft reset register */
53#define FPGA_INTMSK1 (PA_FPGA + 2) /* Interrupt Mask register 1 */
54#define FPGA_INTMSK2 (PA_FPGA + 4) /* Interrupt Mask register 2 */
55#define FPGA_INTSEL1 (PA_FPGA + 6) /* Interrupt select register 1 */
56#define FPGA_INTSEL2 (PA_FPGA + 8) /* Interrupt select register 2 */
57#define FPGA_INTSEL3 (PA_FPGA + 10) /* Interrupt select register 3 */
58#define FPGA_PCI_INTSEL1 (PA_FPGA + 12) /* PCI Interrupt select register 1 */
59#define FPGA_PCI_INTSEL2 (PA_FPGA + 14) /* PCI Interrupt select register 2 */
60#define FPGA_INTSET (PA_FPGA + 16) /* IRQ/IRL select register */
61#define FPGA_INTSTS1 (PA_FPGA + 18) /* Interrupt status register 1 */
62#define FPGA_INTSTS2 (PA_FPGA + 20) /* Interrupt status register 2 */
63#define FPGA_REQSEL (PA_FPGA + 22) /* REQ/GNT select register */
64#define FPGA_DBG_LED (PA_FPGA + 32) /* Debug LED(D-LED[8:1] */
65#define PA_LED FPGA_DBG_LED
66#define FPGA_IVDRID (PA_FPGA + 36) /* iVDR ID Register */
67#define FPGA_IVDRPW (PA_FPGA + 38) /* iVDR Power ON Register */
68#define FPGA_MMCID (PA_FPGA + 40) /* MMC ID Register */
69
70/* FPGA INTSEL position */
71/* INTSEL1 */
72#define IRQPOS_SMC91CX (0 * 4)
73#define IRQPOS_SM501 (1 * 4)
74/* INTSEL2 */
75#define IRQPOS_EXTINT1 (0 * 4)
76#define IRQPOS_EXTINT2 (1 * 4)
77#define IRQPOS_EXTINT3 (2 * 4)
78#define IRQPOS_EXTINT4 (3 * 4)
79/* INTSEL3 */
80#define IRQPOS_PCCPW (0 * 4)
81
82/* IDE interrupt */
83#define IRQ_IDE0 67 /* iVDR */
84
85/* SMC interrupt */
86#define SMC_IRQ 8
87
88/* SM501 interrupt */
89#define SM501_IRQ 0
90
91/* interrupt pin */
92#define IRQPIN_EXTINT1 0 /* IRQ0 pin */
93#define IRQPIN_EXTINT2 1 /* IRQ1 pin */
94#define IRQPIN_EXTINT3 2 /* IRQ2 pin */
95#define IRQPIN_SMC91CX 3 /* IRQ3 pin */
96#define IRQPIN_EXTINT4 4 /* IRQ4 pin */
97#define IRQPIN_PCC0 5 /* IRQ5 pin */
98#define IRQPIN_PCC2 6 /* IRQ6 pin */
99#define IRQPIN_SM501 7 /* IRQ7 pin */
100#define IRQPIN_PCCPW 7 /* IRQ7 pin */
101
102/* arch/sh/boards/se/7780/irq.c */
103void init_se7780_IRQ(void);
104
105#define __IO_PREFIX se7780
106#include <asm/io_generic.h>
107
108#endif /* __ASM_SH_SE7780_H */
diff --git a/include/asm-sh/sections.h b/include/asm-sh/sections.h
deleted file mode 100644
index 8f8f4ad400d..00000000000
--- a/include/asm-sh/sections.h
+++ /dev/null
@@ -1,11 +0,0 @@
1#ifndef __ASM_SH_SECTIONS_H
2#define __ASM_SH_SECTIONS_H
3
4#include <asm-generic/sections.h>
5
6extern long __machvec_start, __machvec_end;
7extern char __uncached_start, __uncached_end;
8extern char _ebss[];
9
10#endif /* __ASM_SH_SECTIONS_H */
11
diff --git a/include/asm-sh/segment.h b/include/asm-sh/segment.h
deleted file mode 100644
index e417eab4c7d..00000000000
--- a/include/asm-sh/segment.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef __ASM_SH_SEGMENT_H
2#define __ASM_SH_SEGMENT_H
3
4/* Only here because we have some old header files that expect it.. */
5
6#endif /* __ASM_SH_SEGMENT_H */
diff --git a/include/asm-sh/sembuf.h b/include/asm-sh/sembuf.h
deleted file mode 100644
index d79f3bd570b..00000000000
--- a/include/asm-sh/sembuf.h
+++ /dev/null
@@ -1,25 +0,0 @@
1#ifndef __ASM_SH_SEMBUF_H
2#define __ASM_SH_SEMBUF_H
3
4/*
5 * The semid64_ds structure for i386 architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 64-bit time_t to solve y2038 problem
11 * - 2 miscellaneous 32-bit values
12 */
13
14struct semid64_ds {
15 struct ipc64_perm sem_perm; /* permissions .. see ipc.h */
16 __kernel_time_t sem_otime; /* last semop time */
17 unsigned long __unused1;
18 __kernel_time_t sem_ctime; /* last change time */
19 unsigned long __unused2;
20 unsigned long sem_nsems; /* no. of semaphores in array */
21 unsigned long __unused3;
22 unsigned long __unused4;
23};
24
25#endif /* __ASM_SH_SEMBUF_H */
diff --git a/include/asm-sh/serial.h b/include/asm-sh/serial.h
deleted file mode 100644
index 21f6d330f18..00000000000
--- a/include/asm-sh/serial.h
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * include/asm-sh/serial.h
3 *
4 * Configuration details for 8250, 16450, 16550, etc. serial ports
5 */
6
7#ifndef _ASM_SERIAL_H
8#define _ASM_SERIAL_H
9
10#include <linux/kernel.h>
11
12/*
13 * This assumes you have a 1.8432 MHz clock for your UART.
14 *
15 * It'd be nice if someone built a serial card with a 24.576 MHz
16 * clock, since the 16550A is capable of handling a top speed of 1.5
17 * megabits/second; but this requires the faster clock.
18 */
19#define BASE_BAUD ( 1843200 / 16 )
20
21#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
22
23#ifdef CONFIG_HD64465
24#include <asm/hd64465.h>
25
26#define SERIAL_PORT_DFNS \
27 /* UART CLK PORT IRQ FLAGS */ \
28 { 0, BASE_BAUD, 0x3F8, HD64465_IRQ_UART, STD_COM_FLAGS } /* ttyS0 */
29
30#else
31
32#define SERIAL_PORT_DFNS
33
34#endif
35
36#endif /* _ASM_SERIAL_H */
diff --git a/include/asm-sh/setup.h b/include/asm-sh/setup.h
deleted file mode 100644
index 55a2bd328d9..00000000000
--- a/include/asm-sh/setup.h
+++ /dev/null
@@ -1,27 +0,0 @@
1#ifndef _SH_SETUP_H
2#define _SH_SETUP_H
3
4#define COMMAND_LINE_SIZE 256
5
6#ifdef __KERNEL__
7
8/*
9 * This is set up by the setup-routine at boot-time
10 */
11#define PARAM ((unsigned char *)empty_zero_page)
12
13#define MOUNT_ROOT_RDONLY (*(unsigned long *) (PARAM+0x000))
14#define RAMDISK_FLAGS (*(unsigned long *) (PARAM+0x004))
15#define ORIG_ROOT_DEV (*(unsigned long *) (PARAM+0x008))
16#define LOADER_TYPE (*(unsigned long *) (PARAM+0x00c))
17#define INITRD_START (*(unsigned long *) (PARAM+0x010))
18#define INITRD_SIZE (*(unsigned long *) (PARAM+0x014))
19/* ... */
20#define COMMAND_LINE ((char *) (PARAM+0x100))
21
22int setup_early_printk(char *);
23void sh_mv_setup(void);
24
25#endif /* __KERNEL__ */
26
27#endif /* _SH_SETUP_H */
diff --git a/include/asm-sh/sfp-machine.h b/include/asm-sh/sfp-machine.h
deleted file mode 100644
index d3c548443f2..00000000000
--- a/include/asm-sh/sfp-machine.h
+++ /dev/null
@@ -1,84 +0,0 @@
1/* Machine-dependent software floating-point definitions.
2 SuperH kernel version.
3 Copyright (C) 1997,1998,1999 Free Software Foundation, Inc.
4 This file is part of the GNU C Library.
5 Contributed by Richard Henderson (rth@cygnus.com),
6 Jakub Jelinek (jj@ultra.linux.cz),
7 David S. Miller (davem@redhat.com) and
8 Peter Maydell (pmaydell@chiark.greenend.org.uk).
9
10 The GNU C Library is free software; you can redistribute it and/or
11 modify it under the terms of the GNU Library General Public License as
12 published by the Free Software Foundation; either version 2 of the
13 License, or (at your option) any later version.
14
15 The GNU C Library is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 Library General Public License for more details.
19
20 You should have received a copy of the GNU Library General Public
21 License along with the GNU C Library; see the file COPYING.LIB. If
22 not, write to the Free Software Foundation, Inc.,
23 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24
25#ifndef _SFP_MACHINE_H
26#define _SFP_MACHINE_H
27
28#define _FP_W_TYPE_SIZE 32
29#define _FP_W_TYPE unsigned long
30#define _FP_WS_TYPE signed long
31#define _FP_I_TYPE long
32
33#define _FP_MUL_MEAT_S(R,X,Y) \
34 _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm)
35#define _FP_MUL_MEAT_D(R,X,Y) \
36 _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
37#define _FP_MUL_MEAT_Q(R,X,Y) \
38 _FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
39
40#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_udiv(S,R,X,Y)
41#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y)
42#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y)
43
44#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1)
45#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1), -1
46#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1
47#define _FP_NANSIGN_S 0
48#define _FP_NANSIGN_D 0
49#define _FP_NANSIGN_Q 0
50
51#define _FP_KEEPNANFRACP 1
52
53/*
54 * If one NaN is signaling and the other is not,
55 * we choose that one, otherwise we choose X.
56 */
57#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
58 do { \
59 if ((_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs) \
60 && !(_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs)) \
61 { \
62 R##_s = Y##_s; \
63 _FP_FRAC_COPY_##wc(R,Y); \
64 } \
65 else \
66 { \
67 R##_s = X##_s; \
68 _FP_FRAC_COPY_##wc(R,X); \
69 } \
70 R##_c = FP_CLS_NAN; \
71 } while (0)
72
73//#define FP_ROUNDMODE FPSCR_RM
74#define FP_DENORM_ZERO 1/*FPSCR_DN*/
75
76/* Exception flags. */
77#define FP_EX_INVALID (1<<4)
78#define FP_EX_DIVZERO (1<<3)
79#define FP_EX_OVERFLOW (1<<2)
80#define FP_EX_UNDERFLOW (1<<1)
81#define FP_EX_INEXACT (1<<0)
82
83#endif
84
diff --git a/include/asm-sh/sh03/io.h b/include/asm-sh/sh03/io.h
deleted file mode 100644
index c39c785bba9..00000000000
--- a/include/asm-sh/sh03/io.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * include/asm-sh/sh03/io.h
3 *
4 * Copyright 2004 Interface Co.,Ltd. Saito.K
5 *
6 * IO functions for an Interface CTP/PCI-SH03
7 */
8
9#ifndef _ASM_SH_IO_SH03_H
10#define _ASM_SH_IO_SH03_H
11
12#include <linux/time.h>
13
14#define IRL0_IRQ 2
15#define IRL0_PRIORITY 13
16#define IRL1_IRQ 5
17#define IRL1_PRIORITY 10
18#define IRL2_IRQ 8
19#define IRL2_PRIORITY 7
20#define IRL3_IRQ 11
21#define IRL3_PRIORITY 4
22
23void heartbeat_sh03(void);
24
25#endif /* _ASM_SH_IO_SH03_H */
diff --git a/include/asm-sh/sh03/sh03.h b/include/asm-sh/sh03/sh03.h
deleted file mode 100644
index 19c40b80428..00000000000
--- a/include/asm-sh/sh03/sh03.h
+++ /dev/null
@@ -1,18 +0,0 @@
1#ifndef __ASM_SH_SH03_H
2#define __ASM_SH_SH03_H
3
4/*
5 * linux/include/asm-sh/sh03/sh03.h
6 *
7 * Copyright (C) 2004 Interface Co., Ltd. Saito.K
8 *
9 * Interface CTP/PCI-SH03 support
10 */
11
12#define PA_PCI_IO (0xbe240000) /* PCI I/O space */
13#define PA_PCI_MEM (0xbd000000) /* PCI MEM space */
14
15#define PCIPAR (0xa4000cf8) /* PCI Config address */
16#define PCIPDR (0xa4000cfc) /* PCI Config data */
17
18#endif /* __ASM_SH_SH03_H */
diff --git a/include/asm-sh/sh7760fb.h b/include/asm-sh/sh7760fb.h
deleted file mode 100644
index 8767f61acec..00000000000
--- a/include/asm-sh/sh7760fb.h
+++ /dev/null
@@ -1,197 +0,0 @@
1/*
2 * sh7760fb.h -- platform data for SH7760/SH7763 LCDC framebuffer driver.
3 *
4 * (c) 2006-2008 MSC Vertriebsges.m.b.H.,
5 * Manuel Lauss <mano@roarinelk.homelinux.net>
6 * (c) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
7 */
8
9#ifndef _ASM_SH_SH7760FB_H
10#define _ASM_SH_SH7760FB_H
11
12/*
13 * some bits of the colormap registers should be written as zero.
14 * create a mask for that.
15 */
16#define SH7760FB_PALETTE_MASK 0x00f8fcf8
17
18/* The LCDC dma engine always sets bits 27-26 to 1: this is Area3 */
19#define SH7760FB_DMA_MASK 0x0C000000
20
21/* palette */
22#define LDPR(x) (((x) << 2))
23
24/* framebuffer registers and bits */
25#define LDICKR 0x400
26#define LDMTR 0x402
27/* see sh7760fb.h for LDMTR bits */
28#define LDDFR 0x404
29#define LDDFR_PABD (1 << 8)
30#define LDDFR_COLOR_MASK 0x7F
31#define LDSMR 0x406
32#define LDSMR_ROT (1 << 13)
33#define LDSARU 0x408
34#define LDSARL 0x40c
35#define LDLAOR 0x410
36#define LDPALCR 0x412
37#define LDPALCR_PALS (1 << 4)
38#define LDPALCR_PALEN (1 << 0)
39#define LDHCNR 0x414
40#define LDHSYNR 0x416
41#define LDVDLNR 0x418
42#define LDVTLNR 0x41a
43#define LDVSYNR 0x41c
44#define LDACLNR 0x41e
45#define LDINTR 0x420
46#define LDPMMR 0x424
47#define LDPSPR 0x426
48#define LDCNTR 0x428
49#define LDCNTR_DON (1 << 0)
50#define LDCNTR_DON2 (1 << 4)
51
52#ifdef CONFIG_CPU_SUBTYPE_SH7763
53# define LDLIRNR 0x440
54/* LDINTR bit */
55# define LDINTR_MINTEN (1 << 15)
56# define LDINTR_FINTEN (1 << 14)
57# define LDINTR_VSINTEN (1 << 13)
58# define LDINTR_VEINTEN (1 << 12)
59# define LDINTR_MINTS (1 << 11)
60# define LDINTR_FINTS (1 << 10)
61# define LDINTR_VSINTS (1 << 9)
62# define LDINTR_VEINTS (1 << 8)
63# define VINT_START (LDINTR_VSINTEN)
64# define VINT_CHECK (LDINTR_VSINTS)
65#else
66/* LDINTR bit */
67# define LDINTR_VINTSEL (1 << 12)
68# define LDINTR_VINTE (1 << 8)
69# define LDINTR_VINTS (1 << 0)
70# define VINT_START (LDINTR_VINTSEL)
71# define VINT_CHECK (LDINTR_VINTS)
72#endif
73
74/* HSYNC polarity inversion */
75#define LDMTR_FLMPOL (1 << 15)
76
77/* VSYNC polarity inversion */
78#define LDMTR_CL1POL (1 << 14)
79
80/* DISPLAY-ENABLE polarity inversion */
81#define LDMTR_DISPEN_LOWACT (1 << 13)
82
83/* DISPLAY DATA BUS polarity inversion */
84#define LDMTR_DPOL_LOWACT (1 << 12)
85
86/* AC modulation signal enable */
87#define LDMTR_MCNT (1 << 10)
88
89/* Disable output of HSYNC during VSYNC period */
90#define LDMTR_CL1CNT (1 << 9)
91
92/* Disable output of VSYNC during VSYNC period */
93#define LDMTR_CL2CNT (1 << 8)
94
95/* Display types supported by the LCDC */
96#define LDMTR_STN_MONO_4 0x00
97#define LDMTR_STN_MONO_8 0x01
98#define LDMTR_STN_COLOR_4 0x08
99#define LDMTR_STN_COLOR_8 0x09
100#define LDMTR_STN_COLOR_12 0x0A
101#define LDMTR_STN_COLOR_16 0x0B
102#define LDMTR_DSTN_MONO_8 0x11
103#define LDMTR_DSTN_MONO_16 0x13
104#define LDMTR_DSTN_COLOR_8 0x19
105#define LDMTR_DSTN_COLOR_12 0x1A
106#define LDMTR_DSTN_COLOR_16 0x1B
107#define LDMTR_TFT_COLOR_16 0x2B
108
109/* framebuffer color layout */
110#define LDDFR_1BPP_MONO 0x00
111#define LDDFR_2BPP_MONO 0x01
112#define LDDFR_4BPP_MONO 0x02
113#define LDDFR_6BPP_MONO 0x04
114#define LDDFR_4BPP 0x0A
115#define LDDFR_8BPP 0x0C
116#define LDDFR_16BPP_RGB555 0x1D
117#define LDDFR_16BPP_RGB565 0x2D
118
119/* LCDC Pixclock sources */
120#define LCDC_CLKSRC_BUSCLOCK 0
121#define LCDC_CLKSRC_PERIPHERAL 1
122#define LCDC_CLKSRC_EXTERNAL 2
123
124#define LDICKR_CLKSRC(x) \
125 (((x) & 3) << 12)
126
127/* LCDC pixclock input divider. Set to 1 at a minimum! */
128#define LDICKR_CLKDIV(x) \
129 ((x) & 0x1f)
130
131struct sh7760fb_platdata {
132
133 /* Set this member to a valid fb_videmode for the display you
134 * wish to use. The following members must be initialized:
135 * xres, yres, hsync_len, vsync_len, sync,
136 * {left,right,upper,lower}_margin.
137 * The driver uses the above members to calculate register values
138 * and memory requirements. Other members are ignored but may
139 * be used by other framebuffer layer components.
140 */
141 struct fb_videomode *def_mode;
142
143 /* LDMTR includes display type and signal polarity. The
144 * HSYNC/VSYNC polarities are derived from the fb_var_screeninfo
145 * data above; however the polarities of the following signals
146 * must be encoded in the ldmtr member:
147 * Display Enable signal (default high-active) DISPEN_LOWACT
148 * Display Data signals (default high-active) DPOL_LOWACT
149 * AC Modulation signal (default off) MCNT
150 * Hsync-During-Vsync suppression (default off) CL1CNT
151 * Vsync-during-vsync suppression (default off) CL2CNT
152 * NOTE: also set a display type!
153 * (one of LDMTR_{STN,DSTN,TFT}_{MONO,COLOR}_{4,8,12,16})
154 */
155 u16 ldmtr;
156
157 /* LDDFR controls framebuffer image format (depth, organization)
158 * Use ONE of the LDDFR_?BPP_* macros!
159 */
160 u16 lddfr;
161
162 /* LDPMMR and LDPSPR control the timing of the power signals
163 * for the display. Please read the SH7760 Hardware Manual,
164 * Chapters 30.3.17, 30.3.18 and 30.4.6!
165 */
166 u16 ldpmmr;
167 u16 ldpspr;
168
169 /* LDACLNR contains the line numbers after which the AC modulation
170 * signal is to toggle. Set to ZERO for TFTs or displays which
171 * do not need it. (Chapter 30.3.15 in SH7760 Hardware Manual).
172 */
173 u16 ldaclnr;
174
175 /* LDICKR contains information on pixelclock source and config.
176 * Please use the LDICKR_CLKSRC() and LDICKR_CLKDIV() macros.
177 * minimal value for CLKDIV() must be 1!.
178 */
179 u16 ldickr;
180
181 /* set this member to 1 if you wish to use the LCDC's hardware
182 * rotation function. This is limited to displays <= 320x200
183 * pixels resolution!
184 */
185 int rotate; /* set to 1 to rotate 90 CCW */
186
187 /* set this to 1 to suppress vsync irq use. */
188 int novsync;
189
190 /* blanking hook for platform. Set this if your platform can do
191 * more than the LCDC in terms of blanking (e.g. disable clock
192 * generator / backlight power supply / etc.
193 */
194 void (*blank) (int);
195};
196
197#endif /* _ASM_SH_SH7760FB_H */
diff --git a/include/asm-sh/sh_bios.h b/include/asm-sh/sh_bios.h
deleted file mode 100644
index 0ca261956e3..00000000000
--- a/include/asm-sh/sh_bios.h
+++ /dev/null
@@ -1,19 +0,0 @@
1#ifndef __ASM_SH_BIOS_H
2#define __ASM_SH_BIOS_H
3
4/*
5 * Copyright (C) 2000 Greg Banks, Mitch Davis
6 * C API to interface to the standard LinuxSH BIOS
7 * usually from within the early stages of kernel boot.
8 */
9
10
11extern void sh_bios_console_write(const char *buf, unsigned int len);
12extern void sh_bios_char_out(char ch);
13extern int sh_bios_in_gdb_mode(void);
14extern void sh_bios_gdb_detach(void);
15
16extern void sh_bios_get_node_addr(unsigned char *node_addr);
17extern void sh_bios_shutdown(unsigned int how);
18
19#endif /* __ASM_SH_BIOS_H */
diff --git a/include/asm-sh/sh_keysc.h b/include/asm-sh/sh_keysc.h
deleted file mode 100644
index b5a4dd5a972..00000000000
--- a/include/asm-sh/sh_keysc.h
+++ /dev/null
@@ -1,13 +0,0 @@
1#ifndef __ASM_KEYSC_H__
2#define __ASM_KEYSC_H__
3
4#define SH_KEYSC_MAXKEYS 30
5
6struct sh_keysc_info {
7 enum { SH_KEYSC_MODE_1, SH_KEYSC_MODE_2, SH_KEYSC_MODE_3 } mode;
8 int scan_timing; /* 0 -> 7, see KYCR1, SCN[2:0] */
9 int delay;
10 int keycodes[SH_KEYSC_MAXKEYS];
11};
12
13#endif /* __ASM_KEYSC_H__ */
diff --git a/include/asm-sh/sh_mobile_lcdc.h b/include/asm-sh/sh_mobile_lcdc.h
deleted file mode 100644
index 27677727df4..00000000000
--- a/include/asm-sh/sh_mobile_lcdc.h
+++ /dev/null
@@ -1,66 +0,0 @@
1#ifndef __ASM_SH_MOBILE_LCDC_H__
2#define __ASM_SH_MOBILE_LCDC_H__
3
4#include <linux/fb.h>
5
6enum { RGB8, /* 24bpp, 8:8:8 */
7 RGB9, /* 18bpp, 9:9 */
8 RGB12A, /* 24bpp, 12:12 */
9 RGB12B, /* 12bpp */
10 RGB16, /* 16bpp */
11 RGB18, /* 18bpp */
12 RGB24, /* 24bpp */
13 SYS8A, /* 24bpp, 8:8:8 */
14 SYS8B, /* 18bpp, 8:8:2 */
15 SYS8C, /* 18bpp, 2:8:8 */
16 SYS8D, /* 16bpp, 8:8 */
17 SYS9, /* 18bpp, 9:9 */
18 SYS12, /* 24bpp, 12:12 */
19 SYS16A, /* 16bpp */
20 SYS16B, /* 18bpp, 16:2 */
21 SYS16C, /* 18bpp, 2:16 */
22 SYS18, /* 18bpp */
23 SYS24 };/* 24bpp */
24
25enum { LCDC_CHAN_DISABLED = 0,
26 LCDC_CHAN_MAINLCD,
27 LCDC_CHAN_SUBLCD };
28
29enum { LCDC_CLK_BUS, LCDC_CLK_PERIPHERAL, LCDC_CLK_EXTERNAL };
30
31struct sh_mobile_lcdc_sys_bus_cfg {
32 unsigned long ldmt2r;
33 unsigned long ldmt3r;
34};
35
36struct sh_mobile_lcdc_sys_bus_ops {
37 void (*write_index)(void *handle, unsigned long data);
38 void (*write_data)(void *handle, unsigned long data);
39 unsigned long (*read_data)(void *handle);
40};
41
42struct sh_mobile_lcdc_board_cfg {
43 void *board_data;
44 int (*setup_sys)(void *board_data, void *sys_ops_handle,
45 struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
46 void (*display_on)(void *board_data);
47 void (*display_off)(void *board_data);
48};
49
50struct sh_mobile_lcdc_chan_cfg {
51 int chan;
52 int bpp;
53 int interface_type; /* selects RGBn or SYSn I/F, see above */
54 int clock_divider;
55 struct fb_videomode lcd_cfg;
56 struct sh_mobile_lcdc_board_cfg board_cfg;
57 struct sh_mobile_lcdc_sys_bus_cfg sys_bus_cfg; /* only for SYSn I/F */
58};
59
60struct sh_mobile_lcdc_info {
61 unsigned long lddckr;
62 int clock_source;
63 struct sh_mobile_lcdc_chan_cfg ch[2];
64};
65
66#endif /* __ASM_SH_MOBILE_LCDC_H__ */
diff --git a/include/asm-sh/shmbuf.h b/include/asm-sh/shmbuf.h
deleted file mode 100644
index b2101f49052..00000000000
--- a/include/asm-sh/shmbuf.h
+++ /dev/null
@@ -1,42 +0,0 @@
1#ifndef __ASM_SH_SHMBUF_H
2#define __ASM_SH_SHMBUF_H
3
4/*
5 * The shmid64_ds structure for i386 architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 64-bit time_t to solve y2038 problem
11 * - 2 miscellaneous 32-bit values
12 */
13
14struct shmid64_ds {
15 struct ipc64_perm shm_perm; /* operation perms */
16 size_t shm_segsz; /* size of segment (bytes) */
17 __kernel_time_t shm_atime; /* last attach time */
18 unsigned long __unused1;
19 __kernel_time_t shm_dtime; /* last detach time */
20 unsigned long __unused2;
21 __kernel_time_t shm_ctime; /* last change time */
22 unsigned long __unused3;
23 __kernel_pid_t shm_cpid; /* pid of creator */
24 __kernel_pid_t shm_lpid; /* pid of last operator */
25 unsigned long shm_nattch; /* no. of current attaches */
26 unsigned long __unused4;
27 unsigned long __unused5;
28};
29
30struct shminfo64 {
31 unsigned long shmmax;
32 unsigned long shmmin;
33 unsigned long shmmni;
34 unsigned long shmseg;
35 unsigned long shmall;
36 unsigned long __unused1;
37 unsigned long __unused2;
38 unsigned long __unused3;
39 unsigned long __unused4;
40};
41
42#endif /* __ASM_SH_SHMBUF_H */
diff --git a/include/asm-sh/shmin.h b/include/asm-sh/shmin.h
deleted file mode 100644
index 36ba138a81f..00000000000
--- a/include/asm-sh/shmin.h
+++ /dev/null
@@ -1,9 +0,0 @@
1#ifndef __ASM_SH_SHMIN_H
2#define __ASM_SH_SHMIN_H
3
4#define SHMIN_IO_BASE 0xb0000000UL
5
6#define SHMIN_NE_IRQ IRQ2_IRQ
7#define SHMIN_NE_BASE 0x300
8
9#endif
diff --git a/include/asm-sh/shmparam.h b/include/asm-sh/shmparam.h
deleted file mode 100644
index ba1758d9010..00000000000
--- a/include/asm-sh/shmparam.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * include/asm-sh/shmparam.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 * Copyright (C) 2006 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#ifndef __ASM_SH_SHMPARAM_H
12#define __ASM_SH_SHMPARAM_H
13
14/*
15 * SH-4 and SH-3 7705 have an aliasing dcache. Bump this up to a sensible value
16 * for everyone, and work out the specifics from the probed cache descriptor.
17 */
18#define SHMLBA 0x4000 /* attach addr a multiple of this */
19
20#define __ARCH_FORCE_SHMLBA
21
22#endif /* __ASM_SH_SHMPARAM_H */
diff --git a/include/asm-sh/sigcontext.h b/include/asm-sh/sigcontext.h
deleted file mode 100644
index 8ce1435bc0b..00000000000
--- a/include/asm-sh/sigcontext.h
+++ /dev/null
@@ -1,40 +0,0 @@
1#ifndef __ASM_SH_SIGCONTEXT_H
2#define __ASM_SH_SIGCONTEXT_H
3
4struct sigcontext {
5 unsigned long oldmask;
6
7#if defined(__SH5__) || defined(CONFIG_CPU_SH5)
8 /* CPU registers */
9 unsigned long long sc_regs[63];
10 unsigned long long sc_tregs[8];
11 unsigned long long sc_pc;
12 unsigned long long sc_sr;
13
14 /* FPU registers */
15 unsigned long long sc_fpregs[32];
16 unsigned int sc_fpscr;
17 unsigned int sc_fpvalid;
18#else
19 /* CPU registers */
20 unsigned long sc_regs[16];
21 unsigned long sc_pc;
22 unsigned long sc_pr;
23 unsigned long sc_sr;
24 unsigned long sc_gbr;
25 unsigned long sc_mach;
26 unsigned long sc_macl;
27
28#if defined(__SH4__) || defined(CONFIG_CPU_SH4) || \
29 defined(__SH2A__) || defined(CONFIG_CPU_SH2A)
30 /* FPU registers */
31 unsigned long sc_fpregs[16];
32 unsigned long sc_xfpregs[16];
33 unsigned int sc_fpscr;
34 unsigned int sc_fpul;
35 unsigned int sc_ownedfp;
36#endif
37#endif
38};
39
40#endif /* __ASM_SH_SIGCONTEXT_H */
diff --git a/include/asm-sh/siginfo.h b/include/asm-sh/siginfo.h
deleted file mode 100644
index 813040ed68a..00000000000
--- a/include/asm-sh/siginfo.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef __ASM_SH_SIGINFO_H
2#define __ASM_SH_SIGINFO_H
3
4#include <asm-generic/siginfo.h>
5
6#endif /* __ASM_SH_SIGINFO_H */
diff --git a/include/asm-sh/signal.h b/include/asm-sh/signal.h
deleted file mode 100644
index 5c5c1e85208..00000000000
--- a/include/asm-sh/signal.h
+++ /dev/null
@@ -1,160 +0,0 @@
1#ifndef __ASM_SH_SIGNAL_H
2#define __ASM_SH_SIGNAL_H
3
4#include <linux/types.h>
5
6/* Avoid too many header ordering problems. */
7struct pt_regs;
8struct siginfo;
9
10#ifdef __KERNEL__
11/* Most things should be clean enough to redefine this at will, if care
12 is taken to make libc match. */
13
14#define _NSIG 64
15#define _NSIG_BPW 32
16#define _NSIG_WORDS (_NSIG / _NSIG_BPW)
17
18typedef unsigned long old_sigset_t; /* at least 32 bits */
19
20typedef struct {
21 unsigned long sig[_NSIG_WORDS];
22} sigset_t;
23
24#else
25/* Here we must cater to libcs that poke about in kernel headers. */
26
27#define NSIG 32
28typedef unsigned long sigset_t;
29
30#endif /* __KERNEL__ */
31
32#define SIGHUP 1
33#define SIGINT 2
34#define SIGQUIT 3
35#define SIGILL 4
36#define SIGTRAP 5
37#define SIGABRT 6
38#define SIGIOT 6
39#define SIGBUS 7
40#define SIGFPE 8
41#define SIGKILL 9
42#define SIGUSR1 10
43#define SIGSEGV 11
44#define SIGUSR2 12
45#define SIGPIPE 13
46#define SIGALRM 14
47#define SIGTERM 15
48#define SIGSTKFLT 16
49#define SIGCHLD 17
50#define SIGCONT 18
51#define SIGSTOP 19
52#define SIGTSTP 20
53#define SIGTTIN 21
54#define SIGTTOU 22
55#define SIGURG 23
56#define SIGXCPU 24
57#define SIGXFSZ 25
58#define SIGVTALRM 26
59#define SIGPROF 27
60#define SIGWINCH 28
61#define SIGIO 29
62#define SIGPOLL SIGIO
63/*
64#define SIGLOST 29
65*/
66#define SIGPWR 30
67#define SIGSYS 31
68#define SIGUNUSED 31
69
70/* These should not be considered constants from userland. */
71#define SIGRTMIN 32
72#define SIGRTMAX _NSIG
73
74/*
75 * SA_FLAGS values:
76 *
77 * SA_ONSTACK indicates that a registered stack_t will be used.
78 * SA_RESTART flag to get restarting signals (which were the default long ago)
79 * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
80 * SA_RESETHAND clears the handler when the signal is delivered.
81 * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
82 * SA_NODEFER prevents the current signal from being masked in the handler.
83 *
84 * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
85 * Unix names RESETHAND and NODEFER respectively.
86 */
87#define SA_NOCLDSTOP 0x00000001
88#define SA_NOCLDWAIT 0x00000002
89#define SA_SIGINFO 0x00000004
90#define SA_ONSTACK 0x08000000
91#define SA_RESTART 0x10000000
92#define SA_NODEFER 0x40000000
93#define SA_RESETHAND 0x80000000
94
95#define SA_NOMASK SA_NODEFER
96#define SA_ONESHOT SA_RESETHAND
97
98#define SA_RESTORER 0x04000000
99
100/*
101 * sigaltstack controls
102 */
103#define SS_ONSTACK 1
104#define SS_DISABLE 2
105
106#define MINSIGSTKSZ 2048
107#define SIGSTKSZ 8192
108
109#include <asm-generic/signal.h>
110
111#ifdef __KERNEL__
112struct old_sigaction {
113 __sighandler_t sa_handler;
114 old_sigset_t sa_mask;
115 unsigned long sa_flags;
116 void (*sa_restorer)(void);
117};
118
119struct sigaction {
120 __sighandler_t sa_handler;
121 unsigned long sa_flags;
122 void (*sa_restorer)(void);
123 sigset_t sa_mask; /* mask last for extensibility */
124};
125
126struct k_sigaction {
127 struct sigaction sa;
128};
129#else
130/* Here we must cater to libcs that poke about in kernel headers. */
131
132struct sigaction {
133 union {
134 __sighandler_t _sa_handler;
135 void (*_sa_sigaction)(int, struct siginfo *, void *);
136 } _u;
137 sigset_t sa_mask;
138 unsigned long sa_flags;
139 void (*sa_restorer)(void);
140};
141
142#define sa_handler _u._sa_handler
143#define sa_sigaction _u._sa_sigaction
144
145#endif /* __KERNEL__ */
146
147typedef struct sigaltstack {
148 void *ss_sp;
149 int ss_flags;
150 size_t ss_size;
151} stack_t;
152
153#ifdef __KERNEL__
154#include <asm/sigcontext.h>
155
156#define ptrace_signal_deliver(regs, cookie) do { } while (0)
157
158#endif /* __KERNEL__ */
159
160#endif /* __ASM_SH_SIGNAL_H */
diff --git a/include/asm-sh/smc37c93x.h b/include/asm-sh/smc37c93x.h
deleted file mode 100644
index 585da2a8fc4..00000000000
--- a/include/asm-sh/smc37c93x.h
+++ /dev/null
@@ -1,190 +0,0 @@
1#ifndef __ASM_SH_SMC37C93X_H
2#define __ASM_SH_SMC37C93X_H
3
4/*
5 * linux/include/asm-sh/smc37c93x.h
6 *
7 * Copyright (C) 2000 Kazumoto Kojima
8 *
9 * SMSC 37C93x Super IO Chip support
10 */
11
12/* Default base I/O address */
13#define FDC_PRIMARY_BASE 0x3f0
14#define IDE1_PRIMARY_BASE 0x1f0
15#define IDE1_SECONDARY_BASE 0x170
16#define PARPORT_PRIMARY_BASE 0x378
17#define COM1_PRIMARY_BASE 0x2f8
18#define COM2_PRIMARY_BASE 0x3f8
19#define RTC_PRIMARY_BASE 0x070
20#define KBC_PRIMARY_BASE 0x060
21#define AUXIO_PRIMARY_BASE 0x000 /* XXX */
22
23/* Logical device number */
24#define LDN_FDC 0
25#define LDN_IDE1 1
26#define LDN_IDE2 2
27#define LDN_PARPORT 3
28#define LDN_COM1 4
29#define LDN_COM2 5
30#define LDN_RTC 6
31#define LDN_KBC 7
32#define LDN_AUXIO 8
33
34/* Configuration port and key */
35#define CONFIG_PORT 0x3f0
36#define INDEX_PORT CONFIG_PORT
37#define DATA_PORT 0x3f1
38#define CONFIG_ENTER 0x55
39#define CONFIG_EXIT 0xaa
40
41/* Configuration index */
42#define CURRENT_LDN_INDEX 0x07
43#define POWER_CONTROL_INDEX 0x22
44#define ACTIVATE_INDEX 0x30
45#define IO_BASE_HI_INDEX 0x60
46#define IO_BASE_LO_INDEX 0x61
47#define IRQ_SELECT_INDEX 0x70
48#define DMA_SELECT_INDEX 0x74
49
50#define GPIO46_INDEX 0xc6
51#define GPIO47_INDEX 0xc7
52
53/* UART stuff. Only for debugging. */
54/* UART Register */
55
56#define UART_RBR 0x0 /* Receiver Buffer Register (Read Only) */
57#define UART_THR 0x0 /* Transmitter Holding Register (Write Only) */
58#define UART_IER 0x2 /* Interrupt Enable Register */
59#define UART_IIR 0x4 /* Interrupt Ident Register (Read Only) */
60#define UART_FCR 0x4 /* FIFO Control Register (Write Only) */
61#define UART_LCR 0x6 /* Line Control Register */
62#define UART_MCR 0x8 /* MODEM Control Register */
63#define UART_LSR 0xa /* Line Status Register */
64#define UART_MSR 0xc /* MODEM Status Register */
65#define UART_SCR 0xe /* Scratch Register */
66#define UART_DLL 0x0 /* Divisor Latch (LS) */
67#define UART_DLM 0x2 /* Divisor Latch (MS) */
68
69#ifndef __ASSEMBLY__
70typedef struct uart_reg {
71 volatile __u16 rbr;
72 volatile __u16 ier;
73 volatile __u16 iir;
74 volatile __u16 lcr;
75 volatile __u16 mcr;
76 volatile __u16 lsr;
77 volatile __u16 msr;
78 volatile __u16 scr;
79} uart_reg;
80#endif /* ! __ASSEMBLY__ */
81
82/* Alias for Write Only Register */
83
84#define thr rbr
85#define tcr iir
86
87/* Alias for Divisor Latch Register */
88
89#define dll rbr
90#define dlm ier
91#define fcr iir
92
93/* Interrupt Enable Register */
94
95#define IER_ERDAI 0x0100 /* Enable Received Data Available Interrupt */
96#define IER_ETHREI 0x0200 /* Enable Transmitter Holding Register Empty Interrupt */
97#define IER_ELSI 0x0400 /* Enable Receiver Line Status Interrupt */
98#define IER_EMSI 0x0800 /* Enable MODEM Status Interrupt */
99
100/* Interrupt Ident Register */
101
102#define IIR_IP 0x0100 /* "0" if Interrupt Pending */
103#define IIR_IIB0 0x0200 /* Interrupt ID Bit 0 */
104#define IIR_IIB1 0x0400 /* Interrupt ID Bit 1 */
105#define IIR_IIB2 0x0800 /* Interrupt ID Bit 2 */
106#define IIR_FIFO 0xc000 /* FIFOs enabled */
107
108/* FIFO Control Register */
109
110#define FCR_FEN 0x0100 /* FIFO enable */
111#define FCR_RFRES 0x0200 /* Receiver FIFO reset */
112#define FCR_TFRES 0x0400 /* Transmitter FIFO reset */
113#define FCR_DMA 0x0800 /* DMA mode select */
114#define FCR_RTL 0x4000 /* Receiver triger (LSB) */
115#define FCR_RTM 0x8000 /* Receiver triger (MSB) */
116
117/* Line Control Register */
118
119#define LCR_WLS0 0x0100 /* Word Length Select Bit 0 */
120#define LCR_WLS1 0x0200 /* Word Length Select Bit 1 */
121#define LCR_STB 0x0400 /* Number of Stop Bits */
122#define LCR_PEN 0x0800 /* Parity Enable */
123#define LCR_EPS 0x1000 /* Even Parity Select */
124#define LCR_SP 0x2000 /* Stick Parity */
125#define LCR_SB 0x4000 /* Set Break */
126#define LCR_DLAB 0x8000 /* Divisor Latch Access Bit */
127
128/* MODEM Control Register */
129
130#define MCR_DTR 0x0100 /* Data Terminal Ready */
131#define MCR_RTS 0x0200 /* Request to Send */
132#define MCR_OUT1 0x0400 /* Out 1 */
133#define MCR_IRQEN 0x0800 /* IRQ Enable */
134#define MCR_LOOP 0x1000 /* Loop */
135
136/* Line Status Register */
137
138#define LSR_DR 0x0100 /* Data Ready */
139#define LSR_OE 0x0200 /* Overrun Error */
140#define LSR_PE 0x0400 /* Parity Error */
141#define LSR_FE 0x0800 /* Framing Error */
142#define LSR_BI 0x1000 /* Break Interrupt */
143#define LSR_THRE 0x2000 /* Transmitter Holding Register Empty */
144#define LSR_TEMT 0x4000 /* Transmitter Empty */
145#define LSR_FIFOE 0x8000 /* Receiver FIFO error */
146
147/* MODEM Status Register */
148
149#define MSR_DCTS 0x0100 /* Delta Clear to Send */
150#define MSR_DDSR 0x0200 /* Delta Data Set Ready */
151#define MSR_TERI 0x0400 /* Trailing Edge Ring Indicator */
152#define MSR_DDCD 0x0800 /* Delta Data Carrier Detect */
153#define MSR_CTS 0x1000 /* Clear to Send */
154#define MSR_DSR 0x2000 /* Data Set Ready */
155#define MSR_RI 0x4000 /* Ring Indicator */
156#define MSR_DCD 0x8000 /* Data Carrier Detect */
157
158/* Baud Rate Divisor */
159
160#define UART_CLK (1843200) /* 1.8432 MHz */
161#define UART_BAUD(x) (UART_CLK / (16 * (x)))
162
163/* RTC register definition */
164#define RTC_SECONDS 0
165#define RTC_SECONDS_ALARM 1
166#define RTC_MINUTES 2
167#define RTC_MINUTES_ALARM 3
168#define RTC_HOURS 4
169#define RTC_HOURS_ALARM 5
170#define RTC_DAY_OF_WEEK 6
171#define RTC_DAY_OF_MONTH 7
172#define RTC_MONTH 8
173#define RTC_YEAR 9
174#define RTC_FREQ_SELECT 10
175# define RTC_UIP 0x80
176# define RTC_DIV_CTL 0x70
177/* This RTC can work under 32.768KHz clock only. */
178# define RTC_OSC_ENABLE 0x20
179# define RTC_OSC_DISABLE 0x00
180#define RTC_CONTROL 11
181# define RTC_SET 0x80
182# define RTC_PIE 0x40
183# define RTC_AIE 0x20
184# define RTC_UIE 0x10
185# define RTC_SQWE 0x08
186# define RTC_DM_BINARY 0x04
187# define RTC_24H 0x02
188# define RTC_DST_EN 0x01
189
190#endif /* __ASM_SH_SMC37C93X_H */
diff --git a/include/asm-sh/smp.h b/include/asm-sh/smp.h
deleted file mode 100644
index 593343cd26e..00000000000
--- a/include/asm-sh/smp.h
+++ /dev/null
@@ -1,50 +0,0 @@
1#ifndef __ASM_SH_SMP_H
2#define __ASM_SH_SMP_H
3
4#include <linux/bitops.h>
5#include <linux/cpumask.h>
6
7#ifdef CONFIG_SMP
8
9#include <linux/spinlock.h>
10#include <asm/atomic.h>
11#include <asm/current.h>
12
13#define raw_smp_processor_id() (current_thread_info()->cpu)
14#define hard_smp_processor_id() plat_smp_processor_id()
15
16/* Map from cpu id to sequential logical cpu number. */
17extern int __cpu_number_map[NR_CPUS];
18#define cpu_number_map(cpu) __cpu_number_map[cpu]
19
20/* The reverse map from sequential logical cpu number to cpu id. */
21extern int __cpu_logical_map[NR_CPUS];
22#define cpu_logical_map(cpu) __cpu_logical_map[cpu]
23
24/* I've no idea what the real meaning of this is */
25#define PROC_CHANGE_PENALTY 20
26
27#define NO_PROC_ID (-1)
28
29#define SMP_MSG_FUNCTION 0
30#define SMP_MSG_RESCHEDULE 1
31#define SMP_MSG_FUNCTION_SINGLE 2
32#define SMP_MSG_NR 3
33
34void plat_smp_setup(void);
35void plat_prepare_cpus(unsigned int max_cpus);
36int plat_smp_processor_id(void);
37void plat_start_cpu(unsigned int cpu, unsigned long entry_point);
38void plat_send_ipi(unsigned int cpu, unsigned int message);
39int plat_register_ipi_handler(unsigned int message,
40 void (*handler)(void *), void *arg);
41extern void arch_send_call_function_single_ipi(int cpu);
42extern void arch_send_call_function_ipi(cpumask_t mask);
43
44#else
45
46#define hard_smp_processor_id() (0)
47
48#endif /* CONFIG_SMP */
49
50#endif /* __ASM_SH_SMP_H */
diff --git a/include/asm-sh/snapgear.h b/include/asm-sh/snapgear.h
deleted file mode 100644
index 042d95f51c4..00000000000
--- a/include/asm-sh/snapgear.h
+++ /dev/null
@@ -1,71 +0,0 @@
1/*
2 * include/asm-sh/snapgear.h
3 *
4 * Modified version of io_se.h for the snapgear-specific functions.
5 *
6 * May be copied or modified under the terms of the GNU General Public
7 * License. See linux/COPYING for more information.
8 *
9 * IO functions for a SnapGear
10 */
11
12#ifndef _ASM_SH_IO_SNAPGEAR_H
13#define _ASM_SH_IO_SNAPGEAR_H
14
15#if defined(CONFIG_CPU_SH4)
16/*
17 * The external interrupt lines, these take up ints 0 - 15 inclusive
18 * depending on the priority for the interrupt. In fact the priority
19 * is the interrupt :-)
20 */
21
22#define IRL0_IRQ 2
23#define IRL0_PRIORITY 13
24
25#define IRL1_IRQ 5
26#define IRL1_PRIORITY 10
27
28#define IRL2_IRQ 8
29#define IRL2_PRIORITY 7
30
31#define IRL3_IRQ 11
32#define IRL3_PRIORITY 4
33#endif
34
35#define __IO_PREFIX snapgear
36#include <asm/io_generic.h>
37
38#ifdef CONFIG_SH_SECUREEDGE5410
39/*
40 * We need to remember what was written to the ioport as some bits
41 * are shared with other functions and you cannot read back what was
42 * written :-|
43 *
44 * Bit Read Write
45 * -----------------------------------------------
46 * D0 DCD on ttySC1 power
47 * D1 Reset Switch heatbeat
48 * D2 ttySC0 CTS (7100) LAN
49 * D3 - WAN
50 * D4 ttySC0 DCD (7100) CONSOLE
51 * D5 - ONLINE
52 * D6 - VPN
53 * D7 - DTR on ttySC1
54 * D8 - ttySC0 RTS (7100)
55 * D9 - ttySC0 DTR (7100)
56 * D10 - RTC SCLK
57 * D11 RTC DATA RTC DATA
58 * D12 - RTS RESET
59 */
60
61#define SECUREEDGE_IOPORT_ADDR ((volatile short *) 0xb0000000)
62extern unsigned short secureedge5410_ioport;
63
64#define SECUREEDGE_WRITE_IOPORT(val, mask) (*SECUREEDGE_IOPORT_ADDR = \
65 (secureedge5410_ioport = \
66 ((secureedge5410_ioport & ~(mask)) | ((val) & (mask)))))
67#define SECUREEDGE_READ_IOPORT() \
68 ((*SECUREEDGE_IOPORT_ADDR&0x0817) | (secureedge5410_ioport&~0x0817))
69#endif
70
71#endif /* _ASM_SH_IO_SNAPGEAR_H */
diff --git a/include/asm-sh/socket.h b/include/asm-sh/socket.h
deleted file mode 100644
index 6d4bf651295..00000000000
--- a/include/asm-sh/socket.h
+++ /dev/null
@@ -1,57 +0,0 @@
1#ifndef __ASM_SH_SOCKET_H
2#define __ASM_SH_SOCKET_H
3
4#include <asm/sockios.h>
5
6/* For setsockopt(2) */
7#define SOL_SOCKET 1
8
9#define SO_DEBUG 1
10#define SO_REUSEADDR 2
11#define SO_TYPE 3
12#define SO_ERROR 4
13#define SO_DONTROUTE 5
14#define SO_BROADCAST 6
15#define SO_SNDBUF 7
16#define SO_RCVBUF 8
17#define SO_RCVBUFFORCE 32
18#define SO_SNDBUFFORCE 33
19#define SO_KEEPALIVE 9
20#define SO_OOBINLINE 10
21#define SO_NO_CHECK 11
22#define SO_PRIORITY 12
23#define SO_LINGER 13
24#define SO_BSDCOMPAT 14
25/* To add :#define SO_REUSEPORT 15 */
26#define SO_PASSCRED 16
27#define SO_PEERCRED 17
28#define SO_RCVLOWAT 18
29#define SO_SNDLOWAT 19
30#define SO_RCVTIMEO 20
31#define SO_SNDTIMEO 21
32
33/* Security levels - as per NRL IPv6 - don't actually do anything */
34#define SO_SECURITY_AUTHENTICATION 22
35#define SO_SECURITY_ENCRYPTION_TRANSPORT 23
36#define SO_SECURITY_ENCRYPTION_NETWORK 24
37
38#define SO_BINDTODEVICE 25
39
40/* Socket filtering */
41#define SO_ATTACH_FILTER 26
42#define SO_DETACH_FILTER 27
43
44#define SO_PEERNAME 28
45#define SO_TIMESTAMP 29
46#define SCM_TIMESTAMP SO_TIMESTAMP
47
48#define SO_ACCEPTCONN 30
49
50#define SO_PEERSEC 31
51#define SO_PASSSEC 34
52#define SO_TIMESTAMPNS 35
53#define SCM_TIMESTAMPNS SO_TIMESTAMPNS
54
55#define SO_MARK 36
56
57#endif /* __ASM_SH_SOCKET_H */
diff --git a/include/asm-sh/sockios.h b/include/asm-sh/sockios.h
deleted file mode 100644
index cf8b96b1f9a..00000000000
--- a/include/asm-sh/sockios.h
+++ /dev/null
@@ -1,14 +0,0 @@
1#ifndef __ASM_SH_SOCKIOS_H
2#define __ASM_SH_SOCKIOS_H
3
4/* Socket-level I/O control calls. */
5#define FIOGETOWN _IOR('f', 123, int)
6#define FIOSETOWN _IOW('f', 124, int)
7
8#define SIOCATMARK _IOR('s', 7, int)
9#define SIOCSPGRP _IOW('s', 8, pid_t)
10#define SIOCGPGRP _IOR('s', 9, pid_t)
11
12#define SIOCGSTAMP _IOR('s', 100, struct timeval) /* Get stamp (timeval) */
13#define SIOCGSTAMPNS _IOR('s', 101, struct timespec) /* Get stamp (timespec) */
14#endif /* __ASM_SH_SOCKIOS_H */
diff --git a/include/asm-sh/sparsemem.h b/include/asm-sh/sparsemem.h
deleted file mode 100644
index 547a540b666..00000000000
--- a/include/asm-sh/sparsemem.h
+++ /dev/null
@@ -1,16 +0,0 @@
1#ifndef __ASM_SH_SPARSEMEM_H
2#define __ASM_SH_SPARSEMEM_H
3
4#ifdef __KERNEL__
5/*
6 * SECTION_SIZE_BITS 2^N: how big each section will be
7 * MAX_PHYSADDR_BITS 2^N: how much physical address space we have
8 * MAX_PHYSMEM_BITS 2^N: how much memory we can have in that space
9 */
10#define SECTION_SIZE_BITS 26
11#define MAX_PHYSADDR_BITS 32
12#define MAX_PHYSMEM_BITS 32
13
14#endif
15
16#endif /* __ASM_SH_SPARSEMEM_H */
diff --git a/include/asm-sh/spi.h b/include/asm-sh/spi.h
deleted file mode 100644
index e96f5b0953c..00000000000
--- a/include/asm-sh/spi.h
+++ /dev/null
@@ -1,13 +0,0 @@
1#ifndef __ASM_SPI_H__
2#define __ASM_SPI_H__
3
4struct sh_spi_info;
5
6struct sh_spi_info {
7 int bus_num;
8 int num_chipselect;
9
10 void (*chip_select)(struct sh_spi_info *spi, int cs, int state);
11};
12
13#endif /* __ASM_SPI_H__ */
diff --git a/include/asm-sh/spinlock.h b/include/asm-sh/spinlock.h
deleted file mode 100644
index e793181d64d..00000000000
--- a/include/asm-sh/spinlock.h
+++ /dev/null
@@ -1,223 +0,0 @@
1/*
2 * include/asm-sh/spinlock.h
3 *
4 * Copyright (C) 2002, 2003 Paul Mundt
5 * Copyright (C) 2006, 2007 Akio Idehara
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#ifndef __ASM_SH_SPINLOCK_H
12#define __ASM_SH_SPINLOCK_H
13
14/*
15 * The only locking implemented here uses SH-4A opcodes. For others,
16 * split this out as per atomic-*.h.
17 */
18#ifndef CONFIG_CPU_SH4A
19#error "Need movli.l/movco.l for spinlocks"
20#endif
21
22/*
23 * Your basic SMP spinlocks, allowing only a single CPU anywhere
24 */
25
26#define __raw_spin_is_locked(x) ((x)->lock <= 0)
27#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
28#define __raw_spin_unlock_wait(x) \
29 do { cpu_relax(); } while ((x)->lock)
30
31/*
32 * Simple spin lock operations. There are two variants, one clears IRQ's
33 * on the local processor, one does not.
34 *
35 * We make no fairness assumptions. They have a cost.
36 */
37static inline void __raw_spin_lock(raw_spinlock_t *lock)
38{
39 unsigned long tmp;
40 unsigned long oldval;
41
42 __asm__ __volatile__ (
43 "1: \n\t"
44 "movli.l @%2, %0 ! __raw_spin_lock \n\t"
45 "mov %0, %1 \n\t"
46 "mov #0, %0 \n\t"
47 "movco.l %0, @%2 \n\t"
48 "bf 1b \n\t"
49 "cmp/pl %1 \n\t"
50 "bf 1b \n\t"
51 : "=&z" (tmp), "=&r" (oldval)
52 : "r" (&lock->lock)
53 : "t", "memory"
54 );
55}
56
57static inline void __raw_spin_unlock(raw_spinlock_t *lock)
58{
59 unsigned long tmp;
60
61 __asm__ __volatile__ (
62 "mov #1, %0 ! __raw_spin_unlock \n\t"
63 "mov.l %0, @%1 \n\t"
64 : "=&z" (tmp)
65 : "r" (&lock->lock)
66 : "t", "memory"
67 );
68}
69
70static inline int __raw_spin_trylock(raw_spinlock_t *lock)
71{
72 unsigned long tmp, oldval;
73
74 __asm__ __volatile__ (
75 "1: \n\t"
76 "movli.l @%2, %0 ! __raw_spin_trylock \n\t"
77 "mov %0, %1 \n\t"
78 "mov #0, %0 \n\t"
79 "movco.l %0, @%2 \n\t"
80 "bf 1b \n\t"
81 "synco \n\t"
82 : "=&z" (tmp), "=&r" (oldval)
83 : "r" (&lock->lock)
84 : "t", "memory"
85 );
86
87 return oldval;
88}
89
90/*
91 * Read-write spinlocks, allowing multiple readers but only one writer.
92 *
93 * NOTE! it is quite common to have readers in interrupts but no interrupt
94 * writers. For those circumstances we can "mix" irq-safe locks - any writer
95 * needs to get a irq-safe write-lock, but readers can get non-irqsafe
96 * read-locks.
97 */
98
99/**
100 * read_can_lock - would read_trylock() succeed?
101 * @lock: the rwlock in question.
102 */
103#define __raw_read_can_lock(x) ((x)->lock > 0)
104
105/**
106 * write_can_lock - would write_trylock() succeed?
107 * @lock: the rwlock in question.
108 */
109#define __raw_write_can_lock(x) ((x)->lock == RW_LOCK_BIAS)
110
111static inline void __raw_read_lock(raw_rwlock_t *rw)
112{
113 unsigned long tmp;
114
115 __asm__ __volatile__ (
116 "1: \n\t"
117 "movli.l @%1, %0 ! __raw_read_lock \n\t"
118 "cmp/pl %0 \n\t"
119 "bf 1b \n\t"
120 "add #-1, %0 \n\t"
121 "movco.l %0, @%1 \n\t"
122 "bf 1b \n\t"
123 : "=&z" (tmp)
124 : "r" (&rw->lock)
125 : "t", "memory"
126 );
127}
128
129static inline void __raw_read_unlock(raw_rwlock_t *rw)
130{
131 unsigned long tmp;
132
133 __asm__ __volatile__ (
134 "1: \n\t"
135 "movli.l @%1, %0 ! __raw_read_unlock \n\t"
136 "add #1, %0 \n\t"
137 "movco.l %0, @%1 \n\t"
138 "bf 1b \n\t"
139 : "=&z" (tmp)
140 : "r" (&rw->lock)
141 : "t", "memory"
142 );
143}
144
145static inline void __raw_write_lock(raw_rwlock_t *rw)
146{
147 unsigned long tmp;
148
149 __asm__ __volatile__ (
150 "1: \n\t"
151 "movli.l @%1, %0 ! __raw_write_lock \n\t"
152 "cmp/hs %2, %0 \n\t"
153 "bf 1b \n\t"
154 "sub %2, %0 \n\t"
155 "movco.l %0, @%1 \n\t"
156 "bf 1b \n\t"
157 : "=&z" (tmp)
158 : "r" (&rw->lock), "r" (RW_LOCK_BIAS)
159 : "t", "memory"
160 );
161}
162
163static inline void __raw_write_unlock(raw_rwlock_t *rw)
164{
165 __asm__ __volatile__ (
166 "mov.l %1, @%0 ! __raw_write_unlock \n\t"
167 :
168 : "r" (&rw->lock), "r" (RW_LOCK_BIAS)
169 : "t", "memory"
170 );
171}
172
173static inline int __raw_read_trylock(raw_rwlock_t *rw)
174{
175 unsigned long tmp, oldval;
176
177 __asm__ __volatile__ (
178 "1: \n\t"
179 "movli.l @%2, %0 ! __raw_read_trylock \n\t"
180 "mov %0, %1 \n\t"
181 "cmp/pl %0 \n\t"
182 "bf 2f \n\t"
183 "add #-1, %0 \n\t"
184 "movco.l %0, @%2 \n\t"
185 "bf 1b \n\t"
186 "2: \n\t"
187 "synco \n\t"
188 : "=&z" (tmp), "=&r" (oldval)
189 : "r" (&rw->lock)
190 : "t", "memory"
191 );
192
193 return (oldval > 0);
194}
195
196static inline int __raw_write_trylock(raw_rwlock_t *rw)
197{
198 unsigned long tmp, oldval;
199
200 __asm__ __volatile__ (
201 "1: \n\t"
202 "movli.l @%2, %0 ! __raw_write_trylock \n\t"
203 "mov %0, %1 \n\t"
204 "cmp/hs %3, %0 \n\t"
205 "bf 2f \n\t"
206 "sub %3, %0 \n\t"
207 "2: \n\t"
208 "movco.l %0, @%2 \n\t"
209 "bf 1b \n\t"
210 "synco \n\t"
211 : "=&z" (tmp), "=&r" (oldval)
212 : "r" (&rw->lock), "r" (RW_LOCK_BIAS)
213 : "t", "memory"
214 );
215
216 return (oldval > (RW_LOCK_BIAS - 1));
217}
218
219#define _raw_spin_relax(lock) cpu_relax()
220#define _raw_read_relax(lock) cpu_relax()
221#define _raw_write_relax(lock) cpu_relax()
222
223#endif /* __ASM_SH_SPINLOCK_H */
diff --git a/include/asm-sh/spinlock_types.h b/include/asm-sh/spinlock_types.h
deleted file mode 100644
index b4d244e7b60..00000000000
--- a/include/asm-sh/spinlock_types.h
+++ /dev/null
@@ -1,21 +0,0 @@
1#ifndef __ASM_SH_SPINLOCK_TYPES_H
2#define __ASM_SH_SPINLOCK_TYPES_H
3
4#ifndef __LINUX_SPINLOCK_TYPES_H
5# error "please don't include this file directly"
6#endif
7
8typedef struct {
9 volatile unsigned int lock;
10} raw_spinlock_t;
11
12#define __RAW_SPIN_LOCK_UNLOCKED { 1 }
13
14typedef struct {
15 volatile unsigned int lock;
16} raw_rwlock_t;
17
18#define RW_LOCK_BIAS 0x01000000
19#define __RAW_RW_LOCK_UNLOCKED { RW_LOCK_BIAS }
20
21#endif
diff --git a/include/asm-sh/stat.h b/include/asm-sh/stat.h
deleted file mode 100644
index e1810cc6e3d..00000000000
--- a/include/asm-sh/stat.h
+++ /dev/null
@@ -1,138 +0,0 @@
1#ifndef __ASM_SH_STAT_H
2#define __ASM_SH_STAT_H
3
4struct __old_kernel_stat {
5 unsigned short st_dev;
6 unsigned short st_ino;
7 unsigned short st_mode;
8 unsigned short st_nlink;
9 unsigned short st_uid;
10 unsigned short st_gid;
11 unsigned short st_rdev;
12 unsigned long st_size;
13 unsigned long st_atime;
14 unsigned long st_mtime;
15 unsigned long st_ctime;
16};
17
18#if defined(__SH5__) || defined(CONFIG_CPU_SH5)
19struct stat {
20 unsigned short st_dev;
21 unsigned short __pad1;
22 unsigned long st_ino;
23 unsigned short st_mode;
24 unsigned short st_nlink;
25 unsigned short st_uid;
26 unsigned short st_gid;
27 unsigned short st_rdev;
28 unsigned short __pad2;
29 unsigned long st_size;
30 unsigned long st_blksize;
31 unsigned long st_blocks;
32 unsigned long st_atime;
33 unsigned long st_atime_nsec;
34 unsigned long st_mtime;
35 unsigned long st_mtime_nsec;
36 unsigned long st_ctime;
37 unsigned long st_ctime_nsec;
38 unsigned long __unused4;
39 unsigned long __unused5;
40};
41
42/* This matches struct stat64 in glibc2.1, hence the absolutely
43 * insane amounts of padding around dev_t's.
44 */
45struct stat64 {
46 unsigned short st_dev;
47 unsigned char __pad0[10];
48
49 unsigned long st_ino;
50 unsigned int st_mode;
51 unsigned int st_nlink;
52
53 unsigned long st_uid;
54 unsigned long st_gid;
55
56 unsigned short st_rdev;
57 unsigned char __pad3[10];
58
59 long long st_size;
60 unsigned long st_blksize;
61
62 unsigned long st_blocks; /* Number 512-byte blocks allocated. */
63 unsigned long __pad4; /* future possible st_blocks high bits */
64
65 unsigned long st_atime;
66 unsigned long st_atime_nsec;
67
68 unsigned long st_mtime;
69 unsigned long st_mtime_nsec;
70
71 unsigned long st_ctime;
72 unsigned long st_ctime_nsec; /* will be high 32 bits of ctime someday */
73
74 unsigned long __unused1;
75 unsigned long __unused2;
76};
77#else
78struct stat {
79 unsigned long st_dev;
80 unsigned long st_ino;
81 unsigned short st_mode;
82 unsigned short st_nlink;
83 unsigned short st_uid;
84 unsigned short st_gid;
85 unsigned long st_rdev;
86 unsigned long st_size;
87 unsigned long st_blksize;
88 unsigned long st_blocks;
89 unsigned long st_atime;
90 unsigned long st_atime_nsec;
91 unsigned long st_mtime;
92 unsigned long st_mtime_nsec;
93 unsigned long st_ctime;
94 unsigned long st_ctime_nsec;
95 unsigned long __unused4;
96 unsigned long __unused5;
97};
98
99/* This matches struct stat64 in glibc2.1, hence the absolutely
100 * insane amounts of padding around dev_t's.
101 */
102struct stat64 {
103 unsigned long long st_dev;
104 unsigned char __pad0[4];
105
106#define STAT64_HAS_BROKEN_ST_INO 1
107 unsigned long __st_ino;
108
109 unsigned int st_mode;
110 unsigned int st_nlink;
111
112 unsigned long st_uid;
113 unsigned long st_gid;
114
115 unsigned long long st_rdev;
116 unsigned char __pad3[4];
117
118 long long st_size;
119 unsigned long st_blksize;
120
121 unsigned long long st_blocks; /* Number 512-byte blocks allocated. */
122
123 unsigned long st_atime;
124 unsigned long st_atime_nsec;
125
126 unsigned long st_mtime;
127 unsigned long st_mtime_nsec;
128
129 unsigned long st_ctime;
130 unsigned long st_ctime_nsec;
131
132 unsigned long long st_ino;
133};
134
135#define STAT_HAVE_NSEC 1
136#endif
137
138#endif /* __ASM_SH_STAT_H */
diff --git a/include/asm-sh/statfs.h b/include/asm-sh/statfs.h
deleted file mode 100644
index 9202a023328..00000000000
--- a/include/asm-sh/statfs.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef __ASM_SH_STATFS_H
2#define __ASM_SH_STATFS_H
3
4#include <asm-generic/statfs.h>
5
6#endif /* __ASM_SH_STATFS_H */
diff --git a/include/asm-sh/string.h b/include/asm-sh/string.h
deleted file mode 100644
index 8c1ea21dc0a..00000000000
--- a/include/asm-sh/string.h
+++ /dev/null
@@ -1,5 +0,0 @@
1#ifdef CONFIG_SUPERH32
2# include "string_32.h"
3#else
4# include "string_64.h"
5#endif
diff --git a/include/asm-sh/string_32.h b/include/asm-sh/string_32.h
deleted file mode 100644
index 55f8db6bc1d..00000000000
--- a/include/asm-sh/string_32.h
+++ /dev/null
@@ -1,131 +0,0 @@
1#ifndef __ASM_SH_STRING_H
2#define __ASM_SH_STRING_H
3
4#ifdef __KERNEL__
5
6/*
7 * Copyright (C) 1999 Niibe Yutaka
8 * But consider these trivial functions to be public domain.
9 */
10
11#define __HAVE_ARCH_STRCPY
12static inline char *strcpy(char *__dest, const char *__src)
13{
14 register char *__xdest = __dest;
15 unsigned long __dummy;
16
17 __asm__ __volatile__("1:\n\t"
18 "mov.b @%1+, %2\n\t"
19 "mov.b %2, @%0\n\t"
20 "cmp/eq #0, %2\n\t"
21 "bf/s 1b\n\t"
22 " add #1, %0\n\t"
23 : "=r" (__dest), "=r" (__src), "=&z" (__dummy)
24 : "0" (__dest), "1" (__src)
25 : "memory", "t");
26
27 return __xdest;
28}
29
30#define __HAVE_ARCH_STRNCPY
31static inline char *strncpy(char *__dest, const char *__src, size_t __n)
32{
33 register char *__xdest = __dest;
34 unsigned long __dummy;
35
36 if (__n == 0)
37 return __xdest;
38
39 __asm__ __volatile__(
40 "1:\n"
41 "mov.b @%1+, %2\n\t"
42 "mov.b %2, @%0\n\t"
43 "cmp/eq #0, %2\n\t"
44 "bt/s 2f\n\t"
45 " cmp/eq %5,%1\n\t"
46 "bf/s 1b\n\t"
47 " add #1, %0\n"
48 "2:"
49 : "=r" (__dest), "=r" (__src), "=&z" (__dummy)
50 : "0" (__dest), "1" (__src), "r" (__src+__n)
51 : "memory", "t");
52
53 return __xdest;
54}
55
56#define __HAVE_ARCH_STRCMP
57static inline int strcmp(const char *__cs, const char *__ct)
58{
59 register int __res;
60 unsigned long __dummy;
61
62 __asm__ __volatile__(
63 "mov.b @%1+, %3\n"
64 "1:\n\t"
65 "mov.b @%0+, %2\n\t"
66 "cmp/eq #0, %3\n\t"
67 "bt 2f\n\t"
68 "cmp/eq %2, %3\n\t"
69 "bt/s 1b\n\t"
70 " mov.b @%1+, %3\n\t"
71 "add #-2, %1\n\t"
72 "mov.b @%1, %3\n\t"
73 "sub %3, %2\n"
74 "2:"
75 : "=r" (__cs), "=r" (__ct), "=&r" (__res), "=&z" (__dummy)
76 : "0" (__cs), "1" (__ct)
77 : "t");
78
79 return __res;
80}
81
82#define __HAVE_ARCH_STRNCMP
83static inline int strncmp(const char *__cs, const char *__ct, size_t __n)
84{
85 register int __res;
86 unsigned long __dummy;
87
88 if (__n == 0)
89 return 0;
90
91 __asm__ __volatile__(
92 "mov.b @%1+, %3\n"
93 "1:\n\t"
94 "mov.b @%0+, %2\n\t"
95 "cmp/eq %6, %0\n\t"
96 "bt/s 2f\n\t"
97 " cmp/eq #0, %3\n\t"
98 "bt/s 3f\n\t"
99 " cmp/eq %3, %2\n\t"
100 "bt/s 1b\n\t"
101 " mov.b @%1+, %3\n\t"
102 "add #-2, %1\n\t"
103 "mov.b @%1, %3\n"
104 "2:\n\t"
105 "sub %3, %2\n"
106 "3:"
107 :"=r" (__cs), "=r" (__ct), "=&r" (__res), "=&z" (__dummy)
108 : "0" (__cs), "1" (__ct), "r" (__cs+__n)
109 : "t");
110
111 return __res;
112}
113
114#define __HAVE_ARCH_MEMSET
115extern void *memset(void *__s, int __c, size_t __count);
116
117#define __HAVE_ARCH_MEMCPY
118extern void *memcpy(void *__to, __const__ void *__from, size_t __n);
119
120#define __HAVE_ARCH_MEMMOVE
121extern void *memmove(void *__dest, __const__ void *__src, size_t __n);
122
123#define __HAVE_ARCH_MEMCHR
124extern void *memchr(const void *__s, int __c, size_t __n);
125
126#define __HAVE_ARCH_STRLEN
127extern size_t strlen(const char *);
128
129#endif /* __KERNEL__ */
130
131#endif /* __ASM_SH_STRING_H */
diff --git a/include/asm-sh/string_64.h b/include/asm-sh/string_64.h
deleted file mode 100644
index aa1fef229c7..00000000000
--- a/include/asm-sh/string_64.h
+++ /dev/null
@@ -1,17 +0,0 @@
1#ifndef __ASM_SH_STRING_64_H
2#define __ASM_SH_STRING_64_H
3
4/*
5 * include/asm-sh/string_64.h
6 *
7 * Copyright (C) 2000, 2001 Paolo Alberelli
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13
14#define __HAVE_ARCH_MEMCPY
15extern void *memcpy(void *dest, const void *src, size_t count);
16
17#endif /* __ASM_SH_STRING_64_H */
diff --git a/include/asm-sh/system.h b/include/asm-sh/system.h
deleted file mode 100644
index e65b6b822cb..00000000000
--- a/include/asm-sh/system.h
+++ /dev/null
@@ -1,198 +0,0 @@
1#ifndef __ASM_SH_SYSTEM_H
2#define __ASM_SH_SYSTEM_H
3
4/*
5 * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima
6 * Copyright (C) 2002 Paul Mundt
7 */
8
9#include <linux/irqflags.h>
10#include <linux/compiler.h>
11#include <linux/linkage.h>
12#include <asm/types.h>
13#include <asm/ptrace.h>
14
15#define AT_VECTOR_SIZE_ARCH 5 /* entries in ARCH_DLINFO */
16
17#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
18#define __icbi() \
19{ \
20 unsigned long __addr; \
21 __addr = 0xa8000000; \
22 __asm__ __volatile__( \
23 "icbi %0\n\t" \
24 : /* no output */ \
25 : "m" (__m(__addr))); \
26}
27#endif
28
29/*
30 * A brief note on ctrl_barrier(), the control register write barrier.
31 *
32 * Legacy SH cores typically require a sequence of 8 nops after
33 * modification of a control register in order for the changes to take
34 * effect. On newer cores (like the sh4a and sh5) this is accomplished
35 * with icbi.
36 *
37 * Also note that on sh4a in the icbi case we can forego a synco for the
38 * write barrier, as it's not necessary for control registers.
39 *
40 * Historically we have only done this type of barrier for the MMUCR, but
41 * it's also necessary for the CCR, so we make it generic here instead.
42 */
43#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
44#define mb() __asm__ __volatile__ ("synco": : :"memory")
45#define rmb() mb()
46#define wmb() __asm__ __volatile__ ("synco": : :"memory")
47#define ctrl_barrier() __icbi()
48#define read_barrier_depends() do { } while(0)
49#else
50#define mb() __asm__ __volatile__ ("": : :"memory")
51#define rmb() mb()
52#define wmb() __asm__ __volatile__ ("": : :"memory")
53#define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop")
54#define read_barrier_depends() do { } while(0)
55#endif
56
57#ifdef CONFIG_SMP
58#define smp_mb() mb()
59#define smp_rmb() rmb()
60#define smp_wmb() wmb()
61#define smp_read_barrier_depends() read_barrier_depends()
62#else
63#define smp_mb() barrier()
64#define smp_rmb() barrier()
65#define smp_wmb() barrier()
66#define smp_read_barrier_depends() do { } while(0)
67#endif
68
69#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
70
71#ifdef CONFIG_GUSA_RB
72#include <asm/cmpxchg-grb.h>
73#else
74#include <asm/cmpxchg-irq.h>
75#endif
76
77extern void __xchg_called_with_bad_pointer(void);
78
79#define __xchg(ptr, x, size) \
80({ \
81 unsigned long __xchg__res; \
82 volatile void *__xchg_ptr = (ptr); \
83 switch (size) { \
84 case 4: \
85 __xchg__res = xchg_u32(__xchg_ptr, x); \
86 break; \
87 case 1: \
88 __xchg__res = xchg_u8(__xchg_ptr, x); \
89 break; \
90 default: \
91 __xchg_called_with_bad_pointer(); \
92 __xchg__res = x; \
93 break; \
94 } \
95 \
96 __xchg__res; \
97})
98
99#define xchg(ptr,x) \
100 ((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr))))
101
102/* This function doesn't exist, so you'll get a linker error
103 * if something tries to do an invalid cmpxchg(). */
104extern void __cmpxchg_called_with_bad_pointer(void);
105
106#define __HAVE_ARCH_CMPXCHG 1
107
108static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
109 unsigned long new, int size)
110{
111 switch (size) {
112 case 4:
113 return __cmpxchg_u32(ptr, old, new);
114 }
115 __cmpxchg_called_with_bad_pointer();
116 return old;
117}
118
119#define cmpxchg(ptr,o,n) \
120 ({ \
121 __typeof__(*(ptr)) _o_ = (o); \
122 __typeof__(*(ptr)) _n_ = (n); \
123 (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
124 (unsigned long)_n_, sizeof(*(ptr))); \
125 })
126
127extern void die(const char *str, struct pt_regs *regs, long err) __attribute__ ((noreturn));
128
129extern void *set_exception_table_vec(unsigned int vec, void *handler);
130
131static inline void *set_exception_table_evt(unsigned int evt, void *handler)
132{
133 return set_exception_table_vec(evt >> 5, handler);
134}
135
136/*
137 * SH-2A has both 16 and 32-bit opcodes, do lame encoding checks.
138 */
139#ifdef CONFIG_CPU_SH2A
140extern unsigned int instruction_size(unsigned int insn);
141#elif defined(CONFIG_SUPERH32)
142#define instruction_size(insn) (2)
143#else
144#define instruction_size(insn) (4)
145#endif
146
147extern unsigned long cached_to_uncached;
148
149extern struct dentry *sh_debugfs_root;
150
151/* XXX
152 * disable hlt during certain critical i/o operations
153 */
154#define HAVE_DISABLE_HLT
155void disable_hlt(void);
156void enable_hlt(void);
157
158void default_idle(void);
159void per_cpu_trap_init(void);
160
161asmlinkage void break_point_trap(void);
162
163#ifdef CONFIG_SUPERH32
164#define BUILD_TRAP_HANDLER(name) \
165asmlinkage void name##_trap_handler(unsigned long r4, unsigned long r5, \
166 unsigned long r6, unsigned long r7, \
167 struct pt_regs __regs)
168
169#define TRAP_HANDLER_DECL \
170 struct pt_regs *regs = RELOC_HIDE(&__regs, 0); \
171 unsigned int vec = regs->tra; \
172 (void)vec;
173#else
174#define BUILD_TRAP_HANDLER(name) \
175asmlinkage void name##_trap_handler(unsigned int vec, struct pt_regs *regs)
176#define TRAP_HANDLER_DECL
177#endif
178
179BUILD_TRAP_HANDLER(address_error);
180BUILD_TRAP_HANDLER(debug);
181BUILD_TRAP_HANDLER(bug);
182BUILD_TRAP_HANDLER(fpu_error);
183BUILD_TRAP_HANDLER(fpu_state_restore);
184
185#define arch_align_stack(x) (x)
186
187struct mem_access {
188 unsigned long (*from)(void *dst, const void *src, unsigned long cnt);
189 unsigned long (*to)(void *dst, const void *src, unsigned long cnt);
190};
191
192#ifdef CONFIG_SUPERH32
193# include "system_32.h"
194#else
195# include "system_64.h"
196#endif
197
198#endif
diff --git a/include/asm-sh/system_32.h b/include/asm-sh/system_32.h
deleted file mode 100644
index f11bcf0855e..00000000000
--- a/include/asm-sh/system_32.h
+++ /dev/null
@@ -1,102 +0,0 @@
1#ifndef __ASM_SH_SYSTEM_32_H
2#define __ASM_SH_SYSTEM_32_H
3
4#include <linux/types.h>
5
6struct task_struct *__switch_to(struct task_struct *prev,
7 struct task_struct *next);
8
9/*
10 * switch_to() should switch tasks to task nr n, first
11 */
12#define switch_to(prev, next, last) \
13do { \
14 register u32 *__ts1 __asm__ ("r1") = (u32 *)&prev->thread.sp; \
15 register u32 *__ts2 __asm__ ("r2") = (u32 *)&prev->thread.pc; \
16 register u32 *__ts4 __asm__ ("r4") = (u32 *)prev; \
17 register u32 *__ts5 __asm__ ("r5") = (u32 *)next; \
18 register u32 *__ts6 __asm__ ("r6") = (u32 *)&next->thread.sp; \
19 register u32 __ts7 __asm__ ("r7") = next->thread.pc; \
20 struct task_struct *__last; \
21 \
22 __asm__ __volatile__ ( \
23 ".balign 4\n\t" \
24 "stc.l gbr, @-r15\n\t" \
25 "sts.l pr, @-r15\n\t" \
26 "mov.l r8, @-r15\n\t" \
27 "mov.l r9, @-r15\n\t" \
28 "mov.l r10, @-r15\n\t" \
29 "mov.l r11, @-r15\n\t" \
30 "mov.l r12, @-r15\n\t" \
31 "mov.l r13, @-r15\n\t" \
32 "mov.l r14, @-r15\n\t" \
33 "mov.l r15, @r1\t! save SP\n\t" \
34 "mov.l @r6, r15\t! change to new stack\n\t" \
35 "mova 1f, %0\n\t" \
36 "mov.l %0, @r2\t! save PC\n\t" \
37 "mov.l 2f, %0\n\t" \
38 "jmp @%0\t! call __switch_to\n\t" \
39 " lds r7, pr\t! with return to new PC\n\t" \
40 ".balign 4\n" \
41 "2:\n\t" \
42 ".long __switch_to\n" \
43 "1:\n\t" \
44 "mov.l @r15+, r14\n\t" \
45 "mov.l @r15+, r13\n\t" \
46 "mov.l @r15+, r12\n\t" \
47 "mov.l @r15+, r11\n\t" \
48 "mov.l @r15+, r10\n\t" \
49 "mov.l @r15+, r9\n\t" \
50 "mov.l @r15+, r8\n\t" \
51 "lds.l @r15+, pr\n\t" \
52 "ldc.l @r15+, gbr\n\t" \
53 : "=z" (__last) \
54 : "r" (__ts1), "r" (__ts2), "r" (__ts4), \
55 "r" (__ts5), "r" (__ts6), "r" (__ts7) \
56 : "r3", "t"); \
57 \
58 last = __last; \
59} while (0)
60
61#define __uses_jump_to_uncached __attribute__ ((__section__ (".uncached.text")))
62
63/*
64 * Jump to uncached area.
65 * When handling TLB or caches, we need to do it from an uncached area.
66 */
67#define jump_to_uncached() \
68do { \
69 unsigned long __dummy; \
70 \
71 __asm__ __volatile__( \
72 "mova 1f, %0\n\t" \
73 "add %1, %0\n\t" \
74 "jmp @%0\n\t" \
75 " nop\n\t" \
76 ".balign 4\n" \
77 "1:" \
78 : "=&z" (__dummy) \
79 : "r" (cached_to_uncached)); \
80} while (0)
81
82/*
83 * Back to cached area.
84 */
85#define back_to_cached() \
86do { \
87 unsigned long __dummy; \
88 ctrl_barrier(); \
89 __asm__ __volatile__( \
90 "mov.l 1f, %0\n\t" \
91 "jmp @%0\n\t" \
92 " nop\n\t" \
93 ".balign 4\n" \
94 "1: .long 2f\n" \
95 "2:" \
96 : "=&r" (__dummy)); \
97} while (0)
98
99int handle_unaligned_access(opcode_t instruction, struct pt_regs *regs,
100 struct mem_access *ma);
101
102#endif /* __ASM_SH_SYSTEM_32_H */
diff --git a/include/asm-sh/system_64.h b/include/asm-sh/system_64.h
deleted file mode 100644
index 943acf5ea07..00000000000
--- a/include/asm-sh/system_64.h
+++ /dev/null
@@ -1,40 +0,0 @@
1#ifndef __ASM_SH_SYSTEM_64_H
2#define __ASM_SH_SYSTEM_64_H
3
4/*
5 * include/asm-sh/system_64.h
6 *
7 * Copyright (C) 2000, 2001 Paolo Alberelli
8 * Copyright (C) 2003 Paul Mundt
9 * Copyright (C) 2004 Richard Curnow
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15#include <asm/processor.h>
16
17/*
18 * switch_to() should switch tasks to task nr n, first
19 */
20struct task_struct *sh64_switch_to(struct task_struct *prev,
21 struct thread_struct *prev_thread,
22 struct task_struct *next,
23 struct thread_struct *next_thread);
24
25#define switch_to(prev,next,last) \
26do { \
27 if (last_task_used_math != next) { \
28 struct pt_regs *regs = next->thread.uregs; \
29 if (regs) regs->sr |= SR_FD; \
30 } \
31 last = sh64_switch_to(prev, &prev->thread, next, \
32 &next->thread); \
33} while (0)
34
35#define __uses_jump_to_uncached
36
37#define jump_to_uncached() do { } while (0)
38#define back_to_cached() do { } while (0)
39
40#endif /* __ASM_SH_SYSTEM_64_H */
diff --git a/include/asm-sh/systemh7751.h b/include/asm-sh/systemh7751.h
deleted file mode 100644
index 4161122c84e..00000000000
--- a/include/asm-sh/systemh7751.h
+++ /dev/null
@@ -1,71 +0,0 @@
1#ifndef __ASM_SH_SYSTEMH_7751SYSTEMH_H
2#define __ASM_SH_SYSTEMH_7751SYSTEMH_H
3
4/*
5 * linux/include/asm-sh/systemh/7751systemh.h
6 *
7 * Copyright (C) 2000 Kazumoto Kojima
8 *
9 * Hitachi SystemH support
10
11 * Modified for 7751 SystemH by
12 * Jonathan Short, 2002.
13 */
14
15/* Box specific addresses. */
16
17#define PA_ROM 0x00000000 /* EPROM */
18#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
19#define PA_FROM 0x01000000 /* EPROM */
20#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
21#define PA_EXT1 0x04000000
22#define PA_EXT1_SIZE 0x04000000
23#define PA_EXT2 0x08000000
24#define PA_EXT2_SIZE 0x04000000
25#define PA_SDRAM 0x0c000000
26#define PA_SDRAM_SIZE 0x04000000
27
28#define PA_EXT4 0x12000000
29#define PA_EXT4_SIZE 0x02000000
30#define PA_EXT5 0x14000000
31#define PA_EXT5_SIZE 0x04000000
32#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */
33
34#define PA_DIPSW0 0xb9000000 /* Dip switch 5,6 */
35#define PA_DIPSW1 0xb9000002 /* Dip switch 7,8 */
36#define PA_LED 0xba000000 /* LED */
37#define PA_BCR 0xbb000000 /* FPGA on the MS7751SE01 */
38
39#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */
40#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */
41#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */
42#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */
43#define MRSHPC_MODE (PA_MRSHPC + 4)
44#define MRSHPC_OPTION (PA_MRSHPC + 6)
45#define MRSHPC_CSR (PA_MRSHPC + 8)
46#define MRSHPC_ISR (PA_MRSHPC + 10)
47#define MRSHPC_ICR (PA_MRSHPC + 12)
48#define MRSHPC_CPWCR (PA_MRSHPC + 14)
49#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
50#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
51#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
52#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
53#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
54#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
55#define MRSHPC_CDCR (PA_MRSHPC + 28)
56#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
57
58#define BCR_ILCRA (PA_BCR + 0)
59#define BCR_ILCRB (PA_BCR + 2)
60#define BCR_ILCRC (PA_BCR + 4)
61#define BCR_ILCRD (PA_BCR + 6)
62#define BCR_ILCRE (PA_BCR + 8)
63#define BCR_ILCRF (PA_BCR + 10)
64#define BCR_ILCRG (PA_BCR + 12)
65
66#define IRQ_79C973 13
67
68#define __IO_PREFIX sh7751systemh
69#include <asm/io_generic.h>
70
71#endif /* __ASM_SH_SYSTEMH_7751SYSTEMH_H */
diff --git a/include/asm-sh/termbits.h b/include/asm-sh/termbits.h
deleted file mode 100644
index 77db116948c..00000000000
--- a/include/asm-sh/termbits.h
+++ /dev/null
@@ -1,198 +0,0 @@
1#ifndef __ASM_SH_TERMBITS_H
2#define __ASM_SH_TERMBITS_H
3
4#include <linux/posix_types.h>
5
6typedef unsigned char cc_t;
7typedef unsigned int speed_t;
8typedef unsigned int tcflag_t;
9
10#define NCCS 19
11struct termios {
12 tcflag_t c_iflag; /* input mode flags */
13 tcflag_t c_oflag; /* output mode flags */
14 tcflag_t c_cflag; /* control mode flags */
15 tcflag_t c_lflag; /* local mode flags */
16 cc_t c_line; /* line discipline */
17 cc_t c_cc[NCCS]; /* control characters */
18};
19
20struct termios2 {
21 tcflag_t c_iflag; /* input mode flags */
22 tcflag_t c_oflag; /* output mode flags */
23 tcflag_t c_cflag; /* control mode flags */
24 tcflag_t c_lflag; /* local mode flags */
25 cc_t c_line; /* line discipline */
26 cc_t c_cc[NCCS]; /* control characters */
27 speed_t c_ispeed; /* input speed */
28 speed_t c_ospeed; /* output speed */
29};
30
31struct ktermios {
32 tcflag_t c_iflag; /* input mode flags */
33 tcflag_t c_oflag; /* output mode flags */
34 tcflag_t c_cflag; /* control mode flags */
35 tcflag_t c_lflag; /* local mode flags */
36 cc_t c_line; /* line discipline */
37 cc_t c_cc[NCCS]; /* control characters */
38 speed_t c_ispeed; /* input speed */
39 speed_t c_ospeed; /* output speed */
40};
41
42/* c_cc characters */
43#define VINTR 0
44#define VQUIT 1
45#define VERASE 2
46#define VKILL 3
47#define VEOF 4
48#define VTIME 5
49#define VMIN 6
50#define VSWTC 7
51#define VSTART 8
52#define VSTOP 9
53#define VSUSP 10
54#define VEOL 11
55#define VREPRINT 12
56#define VDISCARD 13
57#define VWERASE 14
58#define VLNEXT 15
59#define VEOL2 16
60
61/* c_iflag bits */
62#define IGNBRK 0000001
63#define BRKINT 0000002
64#define IGNPAR 0000004
65#define PARMRK 0000010
66#define INPCK 0000020
67#define ISTRIP 0000040
68#define INLCR 0000100
69#define IGNCR 0000200
70#define ICRNL 0000400
71#define IUCLC 0001000
72#define IXON 0002000
73#define IXANY 0004000
74#define IXOFF 0010000
75#define IMAXBEL 0020000
76#define IUTF8 0040000
77
78/* c_oflag bits */
79#define OPOST 0000001
80#define OLCUC 0000002
81#define ONLCR 0000004
82#define OCRNL 0000010
83#define ONOCR 0000020
84#define ONLRET 0000040
85#define OFILL 0000100
86#define OFDEL 0000200
87#define NLDLY 0000400
88#define NL0 0000000
89#define NL1 0000400
90#define CRDLY 0003000
91#define CR0 0000000
92#define CR1 0001000
93#define CR2 0002000
94#define CR3 0003000
95#define TABDLY 0014000
96#define TAB0 0000000
97#define TAB1 0004000
98#define TAB2 0010000
99#define TAB3 0014000
100#define XTABS 0014000
101#define BSDLY 0020000
102#define BS0 0000000
103#define BS1 0020000
104#define VTDLY 0040000
105#define VT0 0000000
106#define VT1 0040000
107#define FFDLY 0100000
108#define FF0 0000000
109#define FF1 0100000
110
111/* c_cflag bit meaning */
112#define CBAUD 0010017
113#define B0 0000000 /* hang up */
114#define B50 0000001
115#define B75 0000002
116#define B110 0000003
117#define B134 0000004
118#define B150 0000005
119#define B200 0000006
120#define B300 0000007
121#define B600 0000010
122#define B1200 0000011
123#define B1800 0000012
124#define B2400 0000013
125#define B4800 0000014
126#define B9600 0000015
127#define B19200 0000016
128#define B38400 0000017
129#define EXTA B19200
130#define EXTB B38400
131#define CSIZE 0000060
132#define CS5 0000000
133#define CS6 0000020
134#define CS7 0000040
135#define CS8 0000060
136#define CSTOPB 0000100
137#define CREAD 0000200
138#define PARENB 0000400
139#define PARODD 0001000
140#define HUPCL 0002000
141#define CLOCAL 0004000
142#define CBAUDEX 0010000
143#define BOTHER 0010000
144#define B57600 0010001
145#define B115200 0010002
146#define B230400 0010003
147#define B460800 0010004
148#define B500000 0010005
149#define B576000 0010006
150#define B921600 0010007
151#define B1000000 0010010
152#define B1152000 0010011
153#define B1500000 0010012
154#define B2000000 0010013
155#define B2500000 0010014
156#define B3000000 0010015
157#define B3500000 0010016
158#define B4000000 0010017
159#define CIBAUD 002003600000 /* input baud rate */
160#define CMSPAR 010000000000 /* mark or space (stick) parity */
161#define CRTSCTS 020000000000 /* flow control */
162
163#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
164
165/* c_lflag bits */
166#define ISIG 0000001
167#define ICANON 0000002
168#define XCASE 0000004
169#define ECHO 0000010
170#define ECHOE 0000020
171#define ECHOK 0000040
172#define ECHONL 0000100
173#define NOFLSH 0000200
174#define TOSTOP 0000400
175#define ECHOCTL 0001000
176#define ECHOPRT 0002000
177#define ECHOKE 0004000
178#define FLUSHO 0010000
179#define PENDIN 0040000
180#define IEXTEN 0100000
181
182/* tcflow() and TCXONC use these */
183#define TCOOFF 0
184#define TCOON 1
185#define TCIOFF 2
186#define TCION 3
187
188/* tcflush() and TCFLSH use these */
189#define TCIFLUSH 0
190#define TCOFLUSH 1
191#define TCIOFLUSH 2
192
193/* tcsetattr uses these */
194#define TCSANOW 0
195#define TCSADRAIN 1
196#define TCSAFLUSH 2
197
198#endif /* __ASM_SH_TERMBITS_H */
diff --git a/include/asm-sh/termios.h b/include/asm-sh/termios.h
deleted file mode 100644
index 0a8c793c76f..00000000000
--- a/include/asm-sh/termios.h
+++ /dev/null
@@ -1,90 +0,0 @@
1#ifndef __ASM_SH_TERMIOS_H
2#define __ASM_SH_TERMIOS_H
3
4#include <asm/termbits.h>
5#include <asm/ioctls.h>
6
7struct winsize {
8 unsigned short ws_row;
9 unsigned short ws_col;
10 unsigned short ws_xpixel;
11 unsigned short ws_ypixel;
12};
13
14#define NCC 8
15struct termio {
16 unsigned short c_iflag; /* input mode flags */
17 unsigned short c_oflag; /* output mode flags */
18 unsigned short c_cflag; /* control mode flags */
19 unsigned short c_lflag; /* local mode flags */
20 unsigned char c_line; /* line discipline */
21 unsigned char c_cc[NCC]; /* control characters */
22};
23
24/* modem lines */
25#define TIOCM_LE 0x001
26#define TIOCM_DTR 0x002
27#define TIOCM_RTS 0x004
28#define TIOCM_ST 0x008
29#define TIOCM_SR 0x010
30#define TIOCM_CTS 0x020
31#define TIOCM_CAR 0x040
32#define TIOCM_RNG 0x080
33#define TIOCM_DSR 0x100
34#define TIOCM_CD TIOCM_CAR
35#define TIOCM_RI TIOCM_RNG
36#define TIOCM_OUT1 0x2000
37#define TIOCM_OUT2 0x4000
38#define TIOCM_LOOP 0x8000
39
40/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
41
42#ifdef __KERNEL__
43
44/* intr=^C quit=^\ erase=del kill=^U
45 eof=^D vtime=\0 vmin=\1 sxtc=\0
46 start=^Q stop=^S susp=^Z eol=\0
47 reprint=^R discard=^U werase=^W lnext=^V
48 eol2=\0
49*/
50#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
51
52/*
53 * Translate a "termio" structure into a "termios". Ugh.
54 */
55#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \
56 unsigned short __tmp; \
57 get_user(__tmp,&(termio)->x); \
58 *(unsigned short *) &(termios)->x = __tmp; \
59}
60
61#define user_termio_to_kernel_termios(termios, termio) \
62({ \
63 SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \
64 SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \
65 SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \
66 SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \
67 copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
68})
69
70/*
71 * Translate a "termios" structure into a "termio". Ugh.
72 */
73#define kernel_termios_to_user_termio(termio, termios) \
74({ \
75 put_user((termios)->c_iflag, &(termio)->c_iflag); \
76 put_user((termios)->c_oflag, &(termio)->c_oflag); \
77 put_user((termios)->c_cflag, &(termio)->c_cflag); \
78 put_user((termios)->c_lflag, &(termio)->c_lflag); \
79 put_user((termios)->c_line, &(termio)->c_line); \
80 copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
81})
82
83#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2))
84#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2))
85#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios))
86#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios))
87
88#endif /* __KERNEL__ */
89
90#endif /* __ASM_SH_TERMIOS_H */
diff --git a/include/asm-sh/thread_info.h b/include/asm-sh/thread_info.h
deleted file mode 100644
index 5131e390752..00000000000
--- a/include/asm-sh/thread_info.h
+++ /dev/null
@@ -1,139 +0,0 @@
1#ifndef __ASM_SH_THREAD_INFO_H
2#define __ASM_SH_THREAD_INFO_H
3
4/* SuperH version
5 * Copyright (C) 2002 Niibe Yutaka
6 *
7 * The copyright of original i386 version is:
8 *
9 * Copyright (C) 2002 David Howells (dhowells@redhat.com)
10 * - Incorporating suggestions made by Linus Torvalds and Dave Miller
11 */
12#ifdef __KERNEL__
13#include <asm/page.h>
14
15#ifndef __ASSEMBLY__
16#include <asm/processor.h>
17
18struct thread_info {
19 struct task_struct *task; /* main task structure */
20 struct exec_domain *exec_domain; /* execution domain */
21 unsigned long flags; /* low level flags */
22 __u32 cpu;
23 int preempt_count; /* 0 => preemptable, <0 => BUG */
24 mm_segment_t addr_limit; /* thread address space */
25 struct restart_block restart_block;
26 unsigned long previous_sp; /* sp of previous stack in case
27 of nested IRQ stacks */
28 __u8 supervisor_stack[0];
29};
30
31#endif
32
33#define PREEMPT_ACTIVE 0x10000000
34
35#if defined(CONFIG_4KSTACKS)
36#define THREAD_SIZE_ORDER (0)
37#elif defined(CONFIG_PAGE_SIZE_4KB)
38#define THREAD_SIZE_ORDER (1)
39#elif defined(CONFIG_PAGE_SIZE_8KB)
40#define THREAD_SIZE_ORDER (1)
41#elif defined(CONFIG_PAGE_SIZE_64KB)
42#define THREAD_SIZE_ORDER (0)
43#else
44#error "Unknown thread size"
45#endif
46
47#define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER)
48#define STACK_WARN (THREAD_SIZE >> 3)
49
50/*
51 * macros/functions for gaining access to the thread information structure
52 */
53#ifndef __ASSEMBLY__
54#define INIT_THREAD_INFO(tsk) \
55{ \
56 .task = &tsk, \
57 .exec_domain = &default_exec_domain, \
58 .flags = 0, \
59 .cpu = 0, \
60 .preempt_count = 1, \
61 .addr_limit = KERNEL_DS, \
62 .restart_block = { \
63 .fn = do_no_restart_syscall, \
64 }, \
65}
66
67#define init_thread_info (init_thread_union.thread_info)
68#define init_stack (init_thread_union.stack)
69
70/* how to get the current stack pointer from C */
71register unsigned long current_stack_pointer asm("r15") __used;
72
73/* how to get the thread information struct from C */
74static inline struct thread_info *current_thread_info(void)
75{
76 struct thread_info *ti;
77#if defined(CONFIG_SUPERH64)
78 __asm__ __volatile__ ("getcon cr17, %0" : "=r" (ti));
79#elif defined(CONFIG_CPU_HAS_SR_RB)
80 __asm__ __volatile__ ("stc r7_bank, %0" : "=r" (ti));
81#else
82 unsigned long __dummy;
83
84 __asm__ __volatile__ (
85 "mov r15, %0\n\t"
86 "and %1, %0\n\t"
87 : "=&r" (ti), "=r" (__dummy)
88 : "1" (~(THREAD_SIZE - 1))
89 : "memory");
90#endif
91
92 return ti;
93}
94
95#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
96
97/* thread information allocation */
98#ifdef CONFIG_DEBUG_STACK_USAGE
99#define alloc_thread_info(ti) kzalloc(THREAD_SIZE, GFP_KERNEL)
100#else
101#define alloc_thread_info(ti) kmalloc(THREAD_SIZE, GFP_KERNEL)
102#endif
103#define free_thread_info(ti) kfree(ti)
104
105#endif /* __ASSEMBLY__ */
106
107/*
108 * thread information flags
109 * - these are process state flags that various assembly files may need to access
110 * - pending work-to-be-done flags are in LSW
111 * - other flags in MSW
112 */
113#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
114#define TIF_SIGPENDING 1 /* signal pending */
115#define TIF_NEED_RESCHED 2 /* rescheduling necessary */
116#define TIF_RESTORE_SIGMASK 3 /* restore signal mask in do_signal() */
117#define TIF_SINGLESTEP 4 /* singlestepping active */
118#define TIF_SYSCALL_AUDIT 5
119#define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */
120#define TIF_POLLING_NRFLAG 17 /* true if poll_idle() is polling TIF_NEED_RESCHED */
121#define TIF_MEMDIE 18
122#define TIF_FREEZE 19
123
124#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
125#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
126#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
127#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK)
128#define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP)
129#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT)
130#define _TIF_USEDFPU (1<<TIF_USEDFPU)
131#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
132#define _TIF_FREEZE (1<<TIF_FREEZE)
133
134#define _TIF_WORK_MASK 0x000000FE /* work to do on interrupt/exception return */
135#define _TIF_ALLWORK_MASK 0x000000FF /* work to do on any return to u-space */
136
137#endif /* __KERNEL__ */
138
139#endif /* __ASM_SH_THREAD_INFO_H */
diff --git a/include/asm-sh/timer.h b/include/asm-sh/timer.h
deleted file mode 100644
index 701ba84c704..00000000000
--- a/include/asm-sh/timer.h
+++ /dev/null
@@ -1,45 +0,0 @@
1#ifndef __ASM_SH_TIMER_H
2#define __ASM_SH_TIMER_H
3
4#include <linux/sysdev.h>
5#include <linux/clocksource.h>
6#include <asm/cpu/timer.h>
7
8struct sys_timer_ops {
9 int (*init)(void);
10 int (*start)(void);
11 int (*stop)(void);
12 cycle_t (*read)(void);
13#ifndef CONFIG_GENERIC_TIME
14 unsigned long (*get_offset)(void);
15#endif
16};
17
18struct sys_timer {
19 const char *name;
20
21 struct sys_device dev;
22 struct sys_timer_ops *ops;
23};
24
25#define TICK_SIZE (tick_nsec / 1000)
26
27extern struct sys_timer tmu_timer, cmt_timer, mtu2_timer;
28extern struct sys_timer *sys_timer;
29
30#ifndef CONFIG_GENERIC_TIME
31static inline unsigned long get_timer_offset(void)
32{
33 return sys_timer->ops->get_offset();
34}
35#endif
36
37/* arch/sh/kernel/timers/timer.c */
38struct sys_timer *get_sys_timer(void);
39
40/* arch/sh/kernel/time.c */
41void handle_timer_tick(void);
42extern unsigned long sh_hpt_frequency;
43extern struct clocksource clocksource_sh;
44
45#endif /* __ASM_SH_TIMER_H */
diff --git a/include/asm-sh/timex.h b/include/asm-sh/timex.h
deleted file mode 100644
index a873e24113c..00000000000
--- a/include/asm-sh/timex.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/*
2 * linux/include/asm-sh/timex.h
3 *
4 * sh architecture timex specifications
5 */
6#ifndef __ASM_SH_TIMEX_H
7#define __ASM_SH_TIMEX_H
8
9#define CLOCK_TICK_RATE (CONFIG_SH_PCLK_FREQ / 4) /* Underlying HZ */
10
11typedef unsigned long long cycles_t;
12
13static __inline__ cycles_t get_cycles (void)
14{
15 return 0;
16}
17
18#endif /* __ASM_SH_TIMEX_H */
diff --git a/include/asm-sh/titan.h b/include/asm-sh/titan.h
deleted file mode 100644
index 03f3583c891..00000000000
--- a/include/asm-sh/titan.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/*
2 * Platform defintions for Titan
3 */
4#ifndef _ASM_SH_TITAN_H
5#define _ASM_SH_TITAN_H
6
7#define __IO_PREFIX titan
8#include <asm/io_generic.h>
9
10/* IRQ assignments */
11#define TITAN_IRQ_WAN 2 /* eth0 (WAN) */
12#define TITAN_IRQ_LAN 5 /* eth1 (LAN) */
13#define TITAN_IRQ_MPCIA 8 /* mPCI A */
14#define TITAN_IRQ_MPCIB 11 /* mPCI B */
15#define TITAN_IRQ_USB 11 /* USB */
16
17#endif /* __ASM_SH_TITAN_H */
diff --git a/include/asm-sh/tlb.h b/include/asm-sh/tlb.h
deleted file mode 100644
index 88ff1ae8a6b..00000000000
--- a/include/asm-sh/tlb.h
+++ /dev/null
@@ -1,27 +0,0 @@
1#ifndef __ASM_SH_TLB_H
2#define __ASM_SH_TLB_H
3
4#ifdef CONFIG_SUPERH64
5# include "tlb_64.h"
6#endif
7
8#ifndef __ASSEMBLY__
9
10#define tlb_start_vma(tlb, vma) \
11 flush_cache_range(vma, vma->vm_start, vma->vm_end)
12
13#define tlb_end_vma(tlb, vma) \
14 flush_tlb_range(vma, vma->vm_start, vma->vm_end)
15
16#define __tlb_remove_tlb_entry(tlb, pte, address) do { } while (0)
17
18/*
19 * Flush whole TLBs for MM
20 */
21#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
22
23#include <linux/pagemap.h>
24#include <asm-generic/tlb.h>
25
26#endif /* __ASSEMBLY__ */
27#endif /* __ASM_SH_TLB_H */
diff --git a/include/asm-sh/tlb_64.h b/include/asm-sh/tlb_64.h
deleted file mode 100644
index 0a96f3af69e..00000000000
--- a/include/asm-sh/tlb_64.h
+++ /dev/null
@@ -1,77 +0,0 @@
1/*
2 * include/asm-sh/tlb_64.h
3 *
4 * Copyright (C) 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_SH_TLB_64_H
11#define __ASM_SH_TLB_64_H
12
13/* ITLB defines */
14#define ITLB_FIXED 0x00000000 /* First fixed ITLB, see head.S */
15#define ITLB_LAST_VAR_UNRESTRICTED 0x000003F0 /* Last ITLB */
16
17/* DTLB defines */
18#define DTLB_FIXED 0x00800000 /* First fixed DTLB, see head.S */
19#define DTLB_LAST_VAR_UNRESTRICTED 0x008003F0 /* Last DTLB */
20
21#ifndef __ASSEMBLY__
22
23/**
24 * for_each_dtlb_entry
25 *
26 * @tlb: TLB entry
27 *
28 * Iterate over free (non-wired) DTLB entries
29 */
30#define for_each_dtlb_entry(tlb) \
31 for (tlb = cpu_data->dtlb.first; \
32 tlb <= cpu_data->dtlb.last; \
33 tlb += cpu_data->dtlb.step)
34
35/**
36 * for_each_itlb_entry
37 *
38 * @tlb: TLB entry
39 *
40 * Iterate over free (non-wired) ITLB entries
41 */
42#define for_each_itlb_entry(tlb) \
43 for (tlb = cpu_data->itlb.first; \
44 tlb <= cpu_data->itlb.last; \
45 tlb += cpu_data->itlb.step)
46
47/**
48 * __flush_tlb_slot
49 *
50 * @slot: Address of TLB slot.
51 *
52 * Flushes TLB slot @slot.
53 */
54static inline void __flush_tlb_slot(unsigned long long slot)
55{
56 __asm__ __volatile__ ("putcfg %0, 0, r63\n" : : "r" (slot));
57}
58
59#ifdef CONFIG_MMU
60/* arch/sh64/mm/tlb.c */
61int sh64_tlb_init(void);
62unsigned long long sh64_next_free_dtlb_entry(void);
63unsigned long long sh64_get_wired_dtlb_entry(void);
64int sh64_put_wired_dtlb_entry(unsigned long long entry);
65void sh64_setup_tlb_slot(unsigned long long config_addr, unsigned long eaddr,
66 unsigned long asid, unsigned long paddr);
67void sh64_teardown_tlb_slot(unsigned long long config_addr);
68#else
69#define sh64_tlb_init() do { } while (0)
70#define sh64_next_free_dtlb_entry() (0)
71#define sh64_get_wired_dtlb_entry() (0)
72#define sh64_put_wired_dtlb_entry(entry) do { } while (0)
73#define sh64_setup_tlb_slot(conf, virt, asid, phys) do { } while (0)
74#define sh64_teardown_tlb_slot(addr) do { } while (0)
75#endif /* CONFIG_MMU */
76#endif /* __ASSEMBLY__ */
77#endif /* __ASM_SH_TLB_64_H */
diff --git a/include/asm-sh/tlbflush.h b/include/asm-sh/tlbflush.h
deleted file mode 100644
index e0ac97221ae..00000000000
--- a/include/asm-sh/tlbflush.h
+++ /dev/null
@@ -1,49 +0,0 @@
1#ifndef __ASM_SH_TLBFLUSH_H
2#define __ASM_SH_TLBFLUSH_H
3
4/*
5 * TLB flushing:
6 *
7 * - flush_tlb_all() flushes all processes TLBs
8 * - flush_tlb_mm(mm) flushes the specified mm context TLB's
9 * - flush_tlb_page(vma, vmaddr) flushes one page
10 * - flush_tlb_range(vma, start, end) flushes a range of pages
11 * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
12 */
13extern void local_flush_tlb_all(void);
14extern void local_flush_tlb_mm(struct mm_struct *mm);
15extern void local_flush_tlb_range(struct vm_area_struct *vma,
16 unsigned long start,
17 unsigned long end);
18extern void local_flush_tlb_page(struct vm_area_struct *vma,
19 unsigned long page);
20extern void local_flush_tlb_kernel_range(unsigned long start,
21 unsigned long end);
22extern void local_flush_tlb_one(unsigned long asid, unsigned long page);
23
24#ifdef CONFIG_SMP
25
26extern void flush_tlb_all(void);
27extern void flush_tlb_mm(struct mm_struct *mm);
28extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
29 unsigned long end);
30extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
31extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
32extern void flush_tlb_one(unsigned long asid, unsigned long page);
33
34#else
35
36#define flush_tlb_all() local_flush_tlb_all()
37#define flush_tlb_mm(mm) local_flush_tlb_mm(mm)
38#define flush_tlb_page(vma, page) local_flush_tlb_page(vma, page)
39#define flush_tlb_one(asid, page) local_flush_tlb_one(asid, page)
40
41#define flush_tlb_range(vma, start, end) \
42 local_flush_tlb_range(vma, start, end)
43
44#define flush_tlb_kernel_range(start, end) \
45 local_flush_tlb_kernel_range(start, end)
46
47#endif /* CONFIG_SMP */
48
49#endif /* __ASM_SH_TLBFLUSH_H */
diff --git a/include/asm-sh/topology.h b/include/asm-sh/topology.h
deleted file mode 100644
index 95f0085e098..00000000000
--- a/include/asm-sh/topology.h
+++ /dev/null
@@ -1,47 +0,0 @@
1#ifndef _ASM_SH_TOPOLOGY_H
2#define _ASM_SH_TOPOLOGY_H
3
4#ifdef CONFIG_NUMA
5
6/* sched_domains SD_NODE_INIT for sh machines */
7#define SD_NODE_INIT (struct sched_domain) { \
8 .span = CPU_MASK_NONE, \
9 .parent = NULL, \
10 .child = NULL, \
11 .groups = NULL, \
12 .min_interval = 8, \
13 .max_interval = 32, \
14 .busy_factor = 32, \
15 .imbalance_pct = 125, \
16 .cache_nice_tries = 2, \
17 .busy_idx = 3, \
18 .idle_idx = 2, \
19 .newidle_idx = 2, \
20 .wake_idx = 1, \
21 .forkexec_idx = 1, \
22 .flags = SD_LOAD_BALANCE \
23 | SD_BALANCE_FORK \
24 | SD_BALANCE_EXEC \
25 | SD_SERIALIZE \
26 | SD_WAKE_BALANCE, \
27 .last_balance = jiffies, \
28 .balance_interval = 1, \
29 .nr_balance_failed = 0, \
30}
31
32#define cpu_to_node(cpu) ((void)(cpu),0)
33#define parent_node(node) ((void)(node),0)
34
35#define node_to_cpumask(node) ((void)node, cpu_online_map)
36#define node_to_first_cpu(node) ((void)(node),0)
37
38#define pcibus_to_node(bus) ((void)(bus), -1)
39#define pcibus_to_cpumask(bus) (pcibus_to_node(bus) == -1 ? \
40 CPU_MASK_ALL : \
41 node_to_cpumask(pcibus_to_node(bus)) \
42 )
43#endif
44
45#include <asm-generic/topology.h>
46
47#endif /* _ASM_SH_TOPOLOGY_H */
diff --git a/include/asm-sh/types.h b/include/asm-sh/types.h
deleted file mode 100644
index beea4e6f8df..00000000000
--- a/include/asm-sh/types.h
+++ /dev/null
@@ -1,35 +0,0 @@
1#ifndef __ASM_SH_TYPES_H
2#define __ASM_SH_TYPES_H
3
4#include <asm-generic/int-ll64.h>
5
6#ifndef __ASSEMBLY__
7
8typedef unsigned short umode_t;
9
10#endif /* __ASSEMBLY__ */
11
12/*
13 * These aren't exported outside the kernel to avoid name space clashes
14 */
15#ifdef __KERNEL__
16
17#define BITS_PER_LONG 32
18
19#ifndef __ASSEMBLY__
20
21/* Dma addresses are 32-bits wide. */
22
23typedef u32 dma_addr_t;
24
25#ifdef CONFIG_SUPERH32
26typedef u16 opcode_t;
27#else
28typedef u32 opcode_t;
29#endif
30
31#endif /* __ASSEMBLY__ */
32
33#endif /* __KERNEL__ */
34
35#endif /* __ASM_SH_TYPES_H */
diff --git a/include/asm-sh/uaccess.h b/include/asm-sh/uaccess.h
deleted file mode 100644
index b3440c305b5..00000000000
--- a/include/asm-sh/uaccess.h
+++ /dev/null
@@ -1,34 +0,0 @@
1#ifndef __ASM_SH_UACCESS_H
2#define __ASM_SH_UACCESS_H
3
4#ifdef CONFIG_SUPERH32
5# include "uaccess_32.h"
6#else
7# include "uaccess_64.h"
8#endif
9
10static inline unsigned long
11copy_from_user(void *to, const void __user *from, unsigned long n)
12{
13 unsigned long __copy_from = (unsigned long) from;
14 __kernel_size_t __copy_size = (__kernel_size_t) n;
15
16 if (__copy_size && __access_ok(__copy_from, __copy_size))
17 return __copy_user(to, from, __copy_size);
18
19 return __copy_size;
20}
21
22static inline unsigned long
23copy_to_user(void __user *to, const void *from, unsigned long n)
24{
25 unsigned long __copy_to = (unsigned long) to;
26 __kernel_size_t __copy_size = (__kernel_size_t) n;
27
28 if (__copy_size && __access_ok(__copy_to, __copy_size))
29 return __copy_user(to, from, __copy_size);
30
31 return __copy_size;
32}
33
34#endif /* __ASM_SH_UACCESS_H */
diff --git a/include/asm-sh/uaccess_32.h b/include/asm-sh/uaccess_32.h
deleted file mode 100644
index 1e41fda74bd..00000000000
--- a/include/asm-sh/uaccess_32.h
+++ /dev/null
@@ -1,489 +0,0 @@
1/* $Id: uaccess.h,v 1.11 2003/10/13 07:21:20 lethal Exp $
2 *
3 * User space memory access functions
4 *
5 * Copyright (C) 1999, 2002 Niibe Yutaka
6 * Copyright (C) 2003 Paul Mundt
7 *
8 * Based on:
9 * MIPS implementation version 1.15 by
10 * Copyright (C) 1996, 1997, 1998 by Ralf Baechle
11 * and i386 version.
12 */
13#ifndef __ASM_SH_UACCESS_32_H
14#define __ASM_SH_UACCESS_32_H
15
16#include <linux/errno.h>
17#include <linux/sched.h>
18
19#define VERIFY_READ 0
20#define VERIFY_WRITE 1
21
22/*
23 * The fs value determines whether argument validity checking should be
24 * performed or not. If get_fs() == USER_DS, checking is performed, with
25 * get_fs() == KERNEL_DS, checking is bypassed.
26 *
27 * For historical reasons (Data Segment Register?), these macros are misnamed.
28 */
29
30#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) })
31
32#define KERNEL_DS MAKE_MM_SEG(0xFFFFFFFFUL)
33#define USER_DS MAKE_MM_SEG(PAGE_OFFSET)
34
35#define segment_eq(a,b) ((a).seg == (b).seg)
36
37#define get_ds() (KERNEL_DS)
38
39#if !defined(CONFIG_MMU)
40/* NOMMU is always true */
41#define __addr_ok(addr) (1)
42
43static inline mm_segment_t get_fs(void)
44{
45 return USER_DS;
46}
47
48static inline void set_fs(mm_segment_t s)
49{
50}
51
52/*
53 * __access_ok: Check if address with size is OK or not.
54 *
55 * If we don't have an MMU (or if its disabled) the only thing we really have
56 * to look out for is if the address resides somewhere outside of what
57 * available RAM we have.
58 */
59static inline int __access_ok(unsigned long addr, unsigned long size)
60{
61 return 1;
62}
63#else /* CONFIG_MMU */
64#define __addr_ok(addr) \
65 ((unsigned long)(addr) < (current_thread_info()->addr_limit.seg))
66
67#define get_fs() (current_thread_info()->addr_limit)
68#define set_fs(x) (current_thread_info()->addr_limit = (x))
69
70/*
71 * __access_ok: Check if address with size is OK or not.
72 *
73 * Uhhuh, this needs 33-bit arithmetic. We have a carry..
74 *
75 * sum := addr + size; carry? --> flag = true;
76 * if (sum >= addr_limit) flag = true;
77 */
78static inline int __access_ok(unsigned long addr, unsigned long size)
79{
80 unsigned long flag, sum;
81
82 __asm__("clrt\n\t"
83 "addc %3, %1\n\t"
84 "movt %0\n\t"
85 "cmp/hi %4, %1\n\t"
86 "rotcl %0"
87 :"=&r" (flag), "=r" (sum)
88 :"1" (addr), "r" (size),
89 "r" (current_thread_info()->addr_limit.seg)
90 :"t");
91 return flag == 0;
92}
93#endif /* CONFIG_MMU */
94
95#define access_ok(type, addr, size) \
96 (__chk_user_ptr(addr), \
97 __access_ok((unsigned long __force)(addr), (size)))
98
99/*
100 * Uh, these should become the main single-value transfer routines ...
101 * They automatically use the right size if we just have the right
102 * pointer type ...
103 *
104 * As SuperH uses the same address space for kernel and user data, we
105 * can just do these as direct assignments.
106 *
107 * Careful to not
108 * (a) re-use the arguments for side effects (sizeof is ok)
109 * (b) require any knowledge of processes at this stage
110 */
111#define put_user(x,ptr) __put_user_check((x), (ptr), sizeof(*(ptr)))
112#define get_user(x,ptr) __get_user_check((x), (ptr), sizeof(*(ptr)))
113
114/*
115 * The "__xxx" versions do not do address space checking, useful when
116 * doing multiple accesses to the same area (the user has to do the
117 * checks by hand with "access_ok()")
118 */
119#define __put_user(x,ptr) __put_user_nocheck((x), (ptr), sizeof(*(ptr)))
120#define __get_user(x,ptr) __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
121
122struct __large_struct { unsigned long buf[100]; };
123#define __m(x) (*(struct __large_struct __user *)(x))
124
125#define __get_user_size(x,ptr,size,retval) \
126do { \
127 retval = 0; \
128 switch (size) { \
129 case 1: \
130 __get_user_asm(x, ptr, retval, "b"); \
131 break; \
132 case 2: \
133 __get_user_asm(x, ptr, retval, "w"); \
134 break; \
135 case 4: \
136 __get_user_asm(x, ptr, retval, "l"); \
137 break; \
138 default: \
139 __get_user_unknown(); \
140 break; \
141 } \
142} while (0)
143
144#define __get_user_nocheck(x,ptr,size) \
145({ \
146 long __gu_err; \
147 unsigned long __gu_val; \
148 const __typeof__(*(ptr)) __user *__gu_addr = (ptr); \
149 __chk_user_ptr(ptr); \
150 __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
151 (x) = (__typeof__(*(ptr)))__gu_val; \
152 __gu_err; \
153})
154
155#define __get_user_check(x,ptr,size) \
156({ \
157 long __gu_err = -EFAULT; \
158 unsigned long __gu_val = 0; \
159 const __typeof__(*(ptr)) *__gu_addr = (ptr); \
160 if (likely(access_ok(VERIFY_READ, __gu_addr, (size)))) \
161 __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
162 (x) = (__typeof__(*(ptr)))__gu_val; \
163 __gu_err; \
164})
165
166#define __get_user_asm(x, addr, err, insn) \
167({ \
168__asm__ __volatile__( \
169 "1:\n\t" \
170 "mov." insn " %2, %1\n\t" \
171 "2:\n" \
172 ".section .fixup,\"ax\"\n" \
173 "3:\n\t" \
174 "mov #0, %1\n\t" \
175 "mov.l 4f, %0\n\t" \
176 "jmp @%0\n\t" \
177 " mov %3, %0\n\t" \
178 ".balign 4\n" \
179 "4: .long 2b\n\t" \
180 ".previous\n" \
181 ".section __ex_table,\"a\"\n\t" \
182 ".long 1b, 3b\n\t" \
183 ".previous" \
184 :"=&r" (err), "=&r" (x) \
185 :"m" (__m(addr)), "i" (-EFAULT), "0" (err)); })
186
187extern void __get_user_unknown(void);
188
189#define __put_user_size(x,ptr,size,retval) \
190do { \
191 retval = 0; \
192 switch (size) { \
193 case 1: \
194 __put_user_asm(x, ptr, retval, "b"); \
195 break; \
196 case 2: \
197 __put_user_asm(x, ptr, retval, "w"); \
198 break; \
199 case 4: \
200 __put_user_asm(x, ptr, retval, "l"); \
201 break; \
202 case 8: \
203 __put_user_u64(x, ptr, retval); \
204 break; \
205 default: \
206 __put_user_unknown(); \
207 } \
208} while (0)
209
210#define __put_user_nocheck(x,ptr,size) \
211({ \
212 long __pu_err; \
213 __typeof__(*(ptr)) __user *__pu_addr = (ptr); \
214 __chk_user_ptr(ptr); \
215 __put_user_size((x), __pu_addr, (size), __pu_err); \
216 __pu_err; \
217})
218
219#define __put_user_check(x,ptr,size) \
220({ \
221 long __pu_err = -EFAULT; \
222 __typeof__(*(ptr)) __user *__pu_addr = (ptr); \
223 if (likely(access_ok(VERIFY_WRITE, __pu_addr, size))) \
224 __put_user_size((x), __pu_addr, (size), \
225 __pu_err); \
226 __pu_err; \
227})
228
229#define __put_user_asm(x, addr, err, insn) \
230({ \
231__asm__ __volatile__( \
232 "1:\n\t" \
233 "mov." insn " %1, %2\n\t" \
234 "2:\n" \
235 ".section .fixup,\"ax\"\n" \
236 "3:\n\t" \
237 "mov.l 4f, %0\n\t" \
238 "jmp @%0\n\t" \
239 " mov %3, %0\n\t" \
240 ".balign 4\n" \
241 "4: .long 2b\n\t" \
242 ".previous\n" \
243 ".section __ex_table,\"a\"\n\t" \
244 ".long 1b, 3b\n\t" \
245 ".previous" \
246 :"=&r" (err) \
247 :"r" (x), "m" (__m(addr)), "i" (-EFAULT), "0" (err) \
248 :"memory"); })
249
250#if defined(CONFIG_CPU_LITTLE_ENDIAN)
251#define __put_user_u64(val,addr,retval) \
252({ \
253__asm__ __volatile__( \
254 "1:\n\t" \
255 "mov.l %R1,%2\n\t" \
256 "mov.l %S1,%T2\n\t" \
257 "2:\n" \
258 ".section .fixup,\"ax\"\n" \
259 "3:\n\t" \
260 "mov.l 4f,%0\n\t" \
261 "jmp @%0\n\t" \
262 " mov %3,%0\n\t" \
263 ".balign 4\n" \
264 "4: .long 2b\n\t" \
265 ".previous\n" \
266 ".section __ex_table,\"a\"\n\t" \
267 ".long 1b, 3b\n\t" \
268 ".previous" \
269 : "=r" (retval) \
270 : "r" (val), "m" (__m(addr)), "i" (-EFAULT), "0" (retval) \
271 : "memory"); })
272#else
273#define __put_user_u64(val,addr,retval) \
274({ \
275__asm__ __volatile__( \
276 "1:\n\t" \
277 "mov.l %S1,%2\n\t" \
278 "mov.l %R1,%T2\n\t" \
279 "2:\n" \
280 ".section .fixup,\"ax\"\n" \
281 "3:\n\t" \
282 "mov.l 4f,%0\n\t" \
283 "jmp @%0\n\t" \
284 " mov %3,%0\n\t" \
285 ".balign 4\n" \
286 "4: .long 2b\n\t" \
287 ".previous\n" \
288 ".section __ex_table,\"a\"\n\t" \
289 ".long 1b, 3b\n\t" \
290 ".previous" \
291 : "=r" (retval) \
292 : "r" (val), "m" (__m(addr)), "i" (-EFAULT), "0" (retval) \
293 : "memory"); })
294#endif
295
296extern void __put_user_unknown(void);
297
298/* Generic arbitrary sized copy. */
299/* Return the number of bytes NOT copied */
300__kernel_size_t __copy_user(void *to, const void *from, __kernel_size_t n);
301
302
303static __always_inline unsigned long
304__copy_from_user(void *to, const void __user *from, unsigned long n)
305{
306 return __copy_user(to, (__force void *)from, n);
307}
308
309static __always_inline unsigned long __must_check
310__copy_to_user(void __user *to, const void *from, unsigned long n)
311{
312 return __copy_user((__force void *)to, from, n);
313}
314
315#define __copy_to_user_inatomic __copy_to_user
316#define __copy_from_user_inatomic __copy_from_user
317
318/*
319 * Clear the area and return remaining number of bytes
320 * (on failure. Usually it's 0.)
321 */
322extern __kernel_size_t __clear_user(void *addr, __kernel_size_t size);
323
324#define clear_user(addr,n) ({ \
325void * __cl_addr = (addr); \
326unsigned long __cl_size = (n); \
327if (__cl_size && __access_ok(((unsigned long)(__cl_addr)), __cl_size)) \
328__cl_size = __clear_user(__cl_addr, __cl_size); \
329__cl_size; })
330
331static __inline__ int
332__strncpy_from_user(unsigned long __dest, unsigned long __user __src, int __count)
333{
334 __kernel_size_t res;
335 unsigned long __dummy, _d, _s, _c;
336
337 __asm__ __volatile__(
338 "9:\n"
339 "mov.b @%2+, %1\n\t"
340 "cmp/eq #0, %1\n\t"
341 "bt/s 2f\n"
342 "1:\n"
343 "mov.b %1, @%3\n\t"
344 "dt %4\n\t"
345 "bf/s 9b\n\t"
346 " add #1, %3\n\t"
347 "2:\n\t"
348 "sub %4, %0\n"
349 "3:\n"
350 ".section .fixup,\"ax\"\n"
351 "4:\n\t"
352 "mov.l 5f, %1\n\t"
353 "jmp @%1\n\t"
354 " mov %9, %0\n\t"
355 ".balign 4\n"
356 "5: .long 3b\n"
357 ".previous\n"
358 ".section __ex_table,\"a\"\n"
359 " .balign 4\n"
360 " .long 9b,4b\n"
361 ".previous"
362 : "=r" (res), "=&z" (__dummy), "=r" (_s), "=r" (_d), "=r"(_c)
363 : "0" (__count), "2" (__src), "3" (__dest), "4" (__count),
364 "i" (-EFAULT)
365 : "memory", "t");
366
367 return res;
368}
369
370/**
371 * strncpy_from_user: - Copy a NUL terminated string from userspace.
372 * @dst: Destination address, in kernel space. This buffer must be at
373 * least @count bytes long.
374 * @src: Source address, in user space.
375 * @count: Maximum number of bytes to copy, including the trailing NUL.
376 *
377 * Copies a NUL-terminated string from userspace to kernel space.
378 *
379 * On success, returns the length of the string (not including the trailing
380 * NUL).
381 *
382 * If access to userspace fails, returns -EFAULT (some data may have been
383 * copied).
384 *
385 * If @count is smaller than the length of the string, copies @count bytes
386 * and returns @count.
387 */
388#define strncpy_from_user(dest,src,count) ({ \
389unsigned long __sfu_src = (unsigned long) (src); \
390int __sfu_count = (int) (count); \
391long __sfu_res = -EFAULT; \
392if(__access_ok(__sfu_src, __sfu_count)) { \
393__sfu_res = __strncpy_from_user((unsigned long) (dest), __sfu_src, __sfu_count); \
394} __sfu_res; })
395
396/*
397 * Return the size of a string (including the ending 0 even when we have
398 * exceeded the maximum string length).
399 */
400static __inline__ long __strnlen_user(const char __user *__s, long __n)
401{
402 unsigned long res;
403 unsigned long __dummy;
404
405 __asm__ __volatile__(
406 "1:\t"
407 "mov.b @(%0,%3), %1\n\t"
408 "cmp/eq %4, %0\n\t"
409 "bt/s 2f\n\t"
410 " add #1, %0\n\t"
411 "tst %1, %1\n\t"
412 "bf 1b\n\t"
413 "2:\n"
414 ".section .fixup,\"ax\"\n"
415 "3:\n\t"
416 "mov.l 4f, %1\n\t"
417 "jmp @%1\n\t"
418 " mov #0, %0\n"
419 ".balign 4\n"
420 "4: .long 2b\n"
421 ".previous\n"
422 ".section __ex_table,\"a\"\n"
423 " .balign 4\n"
424 " .long 1b,3b\n"
425 ".previous"
426 : "=z" (res), "=&r" (__dummy)
427 : "0" (0), "r" (__s), "r" (__n)
428 : "t");
429 return res;
430}
431
432/**
433 * strnlen_user: - Get the size of a string in user space.
434 * @s: The string to measure.
435 * @n: The maximum valid length
436 *
437 * Context: User context only. This function may sleep.
438 *
439 * Get the size of a NUL-terminated string in user space.
440 *
441 * Returns the size of the string INCLUDING the terminating NUL.
442 * On exception, returns 0.
443 * If the string is too long, returns a value greater than @n.
444 */
445static __inline__ long strnlen_user(const char __user *s, long n)
446{
447 if (!__addr_ok(s))
448 return 0;
449 else
450 return __strnlen_user(s, n);
451}
452
453/**
454 * strlen_user: - Get the size of a string in user space.
455 * @str: The string to measure.
456 *
457 * Context: User context only. This function may sleep.
458 *
459 * Get the size of a NUL-terminated string in user space.
460 *
461 * Returns the size of the string INCLUDING the terminating NUL.
462 * On exception, returns 0.
463 *
464 * If there is a limit on the length of a valid string, you may wish to
465 * consider using strnlen_user() instead.
466 */
467#define strlen_user(str) strnlen_user(str, ~0UL >> 1)
468
469/*
470 * The exception table consists of pairs of addresses: the first is the
471 * address of an instruction that is allowed to fault, and the second is
472 * the address at which the program should continue. No registers are
473 * modified, so it is entirely up to the continuation code to figure out
474 * what to do.
475 *
476 * All the routines below use bits of fixup code that are out of line
477 * with the main instruction path. This means when everything is well,
478 * we don't even have to jump over them. Further, they do not intrude
479 * on our cache or tlb entries.
480 */
481
482struct exception_table_entry
483{
484 unsigned long insn, fixup;
485};
486
487extern int fixup_exception(struct pt_regs *regs);
488
489#endif /* __ASM_SH_UACCESS_32_H */
diff --git a/include/asm-sh/uaccess_64.h b/include/asm-sh/uaccess_64.h
deleted file mode 100644
index a9b68d09484..00000000000
--- a/include/asm-sh/uaccess_64.h
+++ /dev/null
@@ -1,285 +0,0 @@
1#ifndef __ASM_SH_UACCESS_64_H
2#define __ASM_SH_UACCESS_64_H
3
4/*
5 * include/asm-sh/uaccess_64.h
6 *
7 * Copyright (C) 2000, 2001 Paolo Alberelli
8 * Copyright (C) 2003, 2004 Paul Mundt
9 *
10 * User space memory access functions
11 *
12 * Copyright (C) 1999 Niibe Yutaka
13 *
14 * Based on:
15 * MIPS implementation version 1.15 by
16 * Copyright (C) 1996, 1997, 1998 by Ralf Baechle
17 * and i386 version.
18 *
19 * This file is subject to the terms and conditions of the GNU General Public
20 * License. See the file "COPYING" in the main directory of this archive
21 * for more details.
22 */
23#include <linux/errno.h>
24#include <linux/sched.h>
25
26#define VERIFY_READ 0
27#define VERIFY_WRITE 1
28
29/*
30 * The fs value determines whether argument validity checking should be
31 * performed or not. If get_fs() == USER_DS, checking is performed, with
32 * get_fs() == KERNEL_DS, checking is bypassed.
33 *
34 * For historical reasons (Data Segment Register?), these macros are misnamed.
35 */
36
37#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) })
38
39#define KERNEL_DS MAKE_MM_SEG(0xFFFFFFFF)
40#define USER_DS MAKE_MM_SEG(0x80000000)
41
42#define get_ds() (KERNEL_DS)
43#define get_fs() (current_thread_info()->addr_limit)
44#define set_fs(x) (current_thread_info()->addr_limit=(x))
45
46#define segment_eq(a,b) ((a).seg == (b).seg)
47
48#define __addr_ok(addr) ((unsigned long)(addr) < (current_thread_info()->addr_limit.seg))
49
50/*
51 * Uhhuh, this needs 33-bit arithmetic. We have a carry..
52 *
53 * sum := addr + size; carry? --> flag = true;
54 * if (sum >= addr_limit) flag = true;
55 */
56#define __range_ok(addr,size) (((unsigned long) (addr) + (size) < (current_thread_info()->addr_limit.seg)) ? 0 : 1)
57
58#define access_ok(type,addr,size) (__range_ok(addr,size) == 0)
59#define __access_ok(addr,size) (__range_ok(addr,size) == 0)
60
61/*
62 * Uh, these should become the main single-value transfer routines ...
63 * They automatically use the right size if we just have the right
64 * pointer type ...
65 *
66 * As MIPS uses the same address space for kernel and user data, we
67 * can just do these as direct assignments.
68 *
69 * Careful to not
70 * (a) re-use the arguments for side effects (sizeof is ok)
71 * (b) require any knowledge of processes at this stage
72 */
73#define put_user(x,ptr) __put_user_check((x),(ptr),sizeof(*(ptr)))
74#define get_user(x,ptr) __get_user_check((x),(ptr),sizeof(*(ptr)))
75
76/*
77 * The "__xxx" versions do not do address space checking, useful when
78 * doing multiple accesses to the same area (the user has to do the
79 * checks by hand with "access_ok()")
80 */
81#define __put_user(x,ptr) __put_user_nocheck((x),(ptr),sizeof(*(ptr)))
82#define __get_user(x,ptr) __get_user_nocheck((x),(ptr),sizeof(*(ptr)))
83
84/*
85 * The "xxx_ret" versions return constant specified in third argument, if
86 * something bad happens. These macros can be optimized for the
87 * case of just returning from the function xxx_ret is used.
88 */
89
90#define put_user_ret(x,ptr,ret) ({ \
91if (put_user(x,ptr)) return ret; })
92
93#define get_user_ret(x,ptr,ret) ({ \
94if (get_user(x,ptr)) return ret; })
95
96#define __put_user_ret(x,ptr,ret) ({ \
97if (__put_user(x,ptr)) return ret; })
98
99#define __get_user_ret(x,ptr,ret) ({ \
100if (__get_user(x,ptr)) return ret; })
101
102struct __large_struct { unsigned long buf[100]; };
103#define __m(x) (*(struct __large_struct *)(x))
104
105#define __get_user_size(x,ptr,size,retval) \
106do { \
107 retval = 0; \
108 switch (size) { \
109 case 1: \
110 retval = __get_user_asm_b(x, ptr); \
111 break; \
112 case 2: \
113 retval = __get_user_asm_w(x, ptr); \
114 break; \
115 case 4: \
116 retval = __get_user_asm_l(x, ptr); \
117 break; \
118 case 8: \
119 retval = __get_user_asm_q(x, ptr); \
120 break; \
121 default: \
122 __get_user_unknown(); \
123 break; \
124 } \
125} while (0)
126
127#define __get_user_nocheck(x,ptr,size) \
128({ \
129 long __gu_err, __gu_val; \
130 __get_user_size((void *)&__gu_val, (long)(ptr), \
131 (size), __gu_err); \
132 (x) = (__typeof__(*(ptr)))__gu_val; \
133 __gu_err; \
134})
135
136#define __get_user_check(x,ptr,size) \
137({ \
138 long __gu_addr = (long)(ptr); \
139 long __gu_err = -EFAULT, __gu_val; \
140 if (__access_ok(__gu_addr, (size))) \
141 __get_user_size((void *)&__gu_val, __gu_addr, \
142 (size), __gu_err); \
143 (x) = (__typeof__(*(ptr))) __gu_val; \
144 __gu_err; \
145})
146
147extern long __get_user_asm_b(void *, long);
148extern long __get_user_asm_w(void *, long);
149extern long __get_user_asm_l(void *, long);
150extern long __get_user_asm_q(void *, long);
151extern void __get_user_unknown(void);
152
153#define __put_user_size(x,ptr,size,retval) \
154do { \
155 retval = 0; \
156 switch (size) { \
157 case 1: \
158 retval = __put_user_asm_b(x, ptr); \
159 break; \
160 case 2: \
161 retval = __put_user_asm_w(x, ptr); \
162 break; \
163 case 4: \
164 retval = __put_user_asm_l(x, ptr); \
165 break; \
166 case 8: \
167 retval = __put_user_asm_q(x, ptr); \
168 break; \
169 default: \
170 __put_user_unknown(); \
171 } \
172} while (0)
173
174#define __put_user_nocheck(x,ptr,size) \
175({ \
176 long __pu_err; \
177 __typeof__(*(ptr)) __pu_val = (x); \
178 __put_user_size((void *)&__pu_val, (long)(ptr), (size), __pu_err); \
179 __pu_err; \
180})
181
182#define __put_user_check(x,ptr,size) \
183({ \
184 long __pu_err = -EFAULT; \
185 long __pu_addr = (long)(ptr); \
186 __typeof__(*(ptr)) __pu_val = (x); \
187 \
188 if (__access_ok(__pu_addr, (size))) \
189 __put_user_size((void *)&__pu_val, __pu_addr, (size), __pu_err);\
190 __pu_err; \
191})
192
193extern long __put_user_asm_b(void *, long);
194extern long __put_user_asm_w(void *, long);
195extern long __put_user_asm_l(void *, long);
196extern long __put_user_asm_q(void *, long);
197extern void __put_user_unknown(void);
198
199
200/* Generic arbitrary sized copy. */
201/* Return the number of bytes NOT copied */
202/* XXX: should be such that: 4byte and the rest. */
203extern __kernel_size_t __copy_user(void *__to, const void *__from, __kernel_size_t __n);
204
205#define copy_to_user_ret(to,from,n,retval) ({ \
206if (copy_to_user(to,from,n)) \
207 return retval; \
208})
209
210#define __copy_to_user(to,from,n) \
211 __copy_user((void *)(to), \
212 (void *)(from), n)
213
214#define __copy_to_user_ret(to,from,n,retval) ({ \
215if (__copy_to_user(to,from,n)) \
216 return retval; \
217})
218
219#define copy_from_user_ret(to,from,n,retval) ({ \
220if (copy_from_user(to,from,n)) \
221 return retval; \
222})
223
224#define __copy_from_user(to,from,n) \
225 __copy_user((void *)(to), \
226 (void *)(from), n)
227
228#define __copy_from_user_ret(to,from,n,retval) ({ \
229if (__copy_from_user(to,from,n)) \
230 return retval; \
231})
232
233#define __copy_to_user_inatomic __copy_to_user
234#define __copy_from_user_inatomic __copy_from_user
235
236/* XXX: Not sure it works well..
237 should be such that: 4byte clear and the rest. */
238extern __kernel_size_t __clear_user(void *addr, __kernel_size_t size);
239
240#define clear_user(addr,n) ({ \
241void * __cl_addr = (addr); \
242unsigned long __cl_size = (n); \
243if (__cl_size && __access_ok(((unsigned long)(__cl_addr)), __cl_size)) \
244__cl_size = __clear_user(__cl_addr, __cl_size); \
245__cl_size; })
246
247extern int __strncpy_from_user(unsigned long __dest, unsigned long __src, int __count);
248
249#define strncpy_from_user(dest,src,count) ({ \
250unsigned long __sfu_src = (unsigned long) (src); \
251int __sfu_count = (int) (count); \
252long __sfu_res = -EFAULT; \
253if(__access_ok(__sfu_src, __sfu_count)) { \
254__sfu_res = __strncpy_from_user((unsigned long) (dest), __sfu_src, __sfu_count); \
255} __sfu_res; })
256
257#define strlen_user(str) strnlen_user(str, ~0UL >> 1)
258
259/*
260 * Return the size of a string (including the ending 0!)
261 */
262extern long __strnlen_user(const char *__s, long __n);
263
264static inline long strnlen_user(const char *s, long n)
265{
266 if (!__addr_ok(s))
267 return 0;
268 else
269 return __strnlen_user(s, n);
270}
271
272struct exception_table_entry
273{
274 unsigned long insn, fixup;
275};
276
277#ifdef CONFIG_MMU
278#define ARCH_HAS_SEARCH_EXTABLE
279#endif
280
281/* Returns 0 if exception not found and fixup.unit otherwise. */
282extern unsigned long search_exception_table(unsigned long addr);
283extern const struct exception_table_entry *search_exception_tables (unsigned long addr);
284
285#endif /* __ASM_SH_UACCESS_64_H */
diff --git a/include/asm-sh/ubc.h b/include/asm-sh/ubc.h
deleted file mode 100644
index 56f4e30dc49..00000000000
--- a/include/asm-sh/ubc.h
+++ /dev/null
@@ -1,64 +0,0 @@
1/*
2 * include/asm-sh/ubc.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 * Copyright (C) 2002, 2003 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#ifndef __ASM_SH_UBC_H
12#define __ASM_SH_UBC_H
13#ifdef __KERNEL__
14
15#include <asm/cpu/ubc.h>
16
17/* User Break Controller */
18#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
19#define UBC_TYPE_SH7729 (current_cpu_data.type == CPU_SH7729)
20#else
21#define UBC_TYPE_SH7729 0
22#endif
23
24#define BAMR_ASID (1 << 2)
25#define BAMR_NONE 0
26#define BAMR_10 0x1
27#define BAMR_12 0x2
28#define BAMR_ALL 0x3
29#define BAMR_16 0x8
30#define BAMR_20 0x9
31
32#define BBR_INST (1 << 4)
33#define BBR_DATA (2 << 4)
34#define BBR_READ (1 << 2)
35#define BBR_WRITE (2 << 2)
36#define BBR_BYTE 0x1
37#define BBR_HALF 0x2
38#define BBR_LONG 0x3
39#define BBR_QUAD (1 << 6) /* SH7750 */
40#define BBR_CPU (1 << 6) /* SH7709A,SH7729 */
41#define BBR_DMA (2 << 6) /* SH7709A,SH7729 */
42
43#define BRCR_CMFA (1 << 15)
44#define BRCR_CMFB (1 << 14)
45#define BRCR_PCTE (1 << 11)
46#define BRCR_PCBA (1 << 10) /* 1: after execution */
47#define BRCR_DBEB (1 << 7)
48#define BRCR_PCBB (1 << 6)
49#define BRCR_SEQ (1 << 3)
50#define BRCR_UBDE (1 << 0)
51
52#ifndef __ASSEMBLY__
53/* arch/sh/kernel/cpu/ubc.S */
54extern void ubc_sleep(void);
55
56#ifdef CONFIG_UBC_WAKEUP
57extern void ubc_wakeup(void);
58#else
59#define ubc_wakeup() do { } while (0)
60#endif
61#endif
62
63#endif /* __KERNEL__ */
64#endif /* __ASM_SH_UBC_H */
diff --git a/include/asm-sh/ucontext.h b/include/asm-sh/ucontext.h
deleted file mode 100644
index 202ef1d5a3c..00000000000
--- a/include/asm-sh/ucontext.h
+++ /dev/null
@@ -1,12 +0,0 @@
1#ifndef __ASM_SH_UCONTEXT_H
2#define __ASM_SH_UCONTEXT_H
3
4struct ucontext {
5 unsigned long uc_flags;
6 struct ucontext *uc_link;
7 stack_t uc_stack;
8 struct sigcontext uc_mcontext;
9 sigset_t uc_sigmask; /* mask last for extensibility */
10};
11
12#endif /* __ASM_SH_UCONTEXT_H */
diff --git a/include/asm-sh/unaligned.h b/include/asm-sh/unaligned.h
deleted file mode 100644
index c1641a01d50..00000000000
--- a/include/asm-sh/unaligned.h
+++ /dev/null
@@ -1,19 +0,0 @@
1#ifndef _ASM_SH_UNALIGNED_H
2#define _ASM_SH_UNALIGNED_H
3
4/* SH can't handle unaligned accesses. */
5#ifdef __LITTLE_ENDIAN__
6# include <linux/unaligned/le_struct.h>
7# include <linux/unaligned/be_byteshift.h>
8# include <linux/unaligned/generic.h>
9# define get_unaligned __get_unaligned_le
10# define put_unaligned __put_unaligned_le
11#else
12# include <linux/unaligned/be_struct.h>
13# include <linux/unaligned/le_byteshift.h>
14# include <linux/unaligned/generic.h>
15# define get_unaligned __get_unaligned_be
16# define put_unaligned __put_unaligned_be
17#endif
18
19#endif /* _ASM_SH_UNALIGNED_H */
diff --git a/include/asm-sh/unistd.h b/include/asm-sh/unistd.h
deleted file mode 100644
index 4b21f369c28..00000000000
--- a/include/asm-sh/unistd.h
+++ /dev/null
@@ -1,5 +0,0 @@
1#ifdef CONFIG_SUPERH32
2# include "unistd_32.h"
3#else
4# include "unistd_64.h"
5#endif
diff --git a/include/asm-sh/unistd_32.h b/include/asm-sh/unistd_32.h
deleted file mode 100644
index 0b07212ec65..00000000000
--- a/include/asm-sh/unistd_32.h
+++ /dev/null
@@ -1,378 +0,0 @@
1#ifndef __ASM_SH_UNISTD_H
2#define __ASM_SH_UNISTD_H
3
4/*
5 * Copyright (C) 1999 Niibe Yutaka
6 */
7
8/*
9 * This file contains the system call numbers.
10 */
11
12#define __NR_restart_syscall 0
13#define __NR_exit 1
14#define __NR_fork 2
15#define __NR_read 3
16#define __NR_write 4
17#define __NR_open 5
18#define __NR_close 6
19#define __NR_waitpid 7
20#define __NR_creat 8
21#define __NR_link 9
22#define __NR_unlink 10
23#define __NR_execve 11
24#define __NR_chdir 12
25#define __NR_time 13
26#define __NR_mknod 14
27#define __NR_chmod 15
28#define __NR_lchown 16
29#define __NR_break 17
30#define __NR_oldstat 18
31#define __NR_lseek 19
32#define __NR_getpid 20
33#define __NR_mount 21
34#define __NR_umount 22
35#define __NR_setuid 23
36#define __NR_getuid 24
37#define __NR_stime 25
38#define __NR_ptrace 26
39#define __NR_alarm 27
40#define __NR_oldfstat 28
41#define __NR_pause 29
42#define __NR_utime 30
43#define __NR_stty 31
44#define __NR_gtty 32
45#define __NR_access 33
46#define __NR_nice 34
47#define __NR_ftime 35
48#define __NR_sync 36
49#define __NR_kill 37
50#define __NR_rename 38
51#define __NR_mkdir 39
52#define __NR_rmdir 40
53#define __NR_dup 41
54#define __NR_pipe 42
55#define __NR_times 43
56#define __NR_prof 44
57#define __NR_brk 45
58#define __NR_setgid 46
59#define __NR_getgid 47
60#define __NR_signal 48
61#define __NR_geteuid 49
62#define __NR_getegid 50
63#define __NR_acct 51
64#define __NR_umount2 52
65#define __NR_lock 53
66#define __NR_ioctl 54
67#define __NR_fcntl 55
68#define __NR_mpx 56
69#define __NR_setpgid 57
70#define __NR_ulimit 58
71#define __NR_oldolduname 59
72#define __NR_umask 60
73#define __NR_chroot 61
74#define __NR_ustat 62
75#define __NR_dup2 63
76#define __NR_getppid 64
77#define __NR_getpgrp 65
78#define __NR_setsid 66
79#define __NR_sigaction 67
80#define __NR_sgetmask 68
81#define __NR_ssetmask 69
82#define __NR_setreuid 70
83#define __NR_setregid 71
84#define __NR_sigsuspend 72
85#define __NR_sigpending 73
86#define __NR_sethostname 74
87#define __NR_setrlimit 75
88#define __NR_getrlimit 76 /* Back compatible 2Gig limited rlimit */
89#define __NR_getrusage 77
90#define __NR_gettimeofday 78
91#define __NR_settimeofday 79
92#define __NR_getgroups 80
93#define __NR_setgroups 81
94#define __NR_select 82
95#define __NR_symlink 83
96#define __NR_oldlstat 84
97#define __NR_readlink 85
98#define __NR_uselib 86
99#define __NR_swapon 87
100#define __NR_reboot 88
101#define __NR_readdir 89
102#define __NR_mmap 90
103#define __NR_munmap 91
104#define __NR_truncate 92
105#define __NR_ftruncate 93
106#define __NR_fchmod 94
107#define __NR_fchown 95
108#define __NR_getpriority 96
109#define __NR_setpriority 97
110#define __NR_profil 98
111#define __NR_statfs 99
112#define __NR_fstatfs 100
113#define __NR_ioperm 101
114#define __NR_socketcall 102
115#define __NR_syslog 103
116#define __NR_setitimer 104
117#define __NR_getitimer 105
118#define __NR_stat 106
119#define __NR_lstat 107
120#define __NR_fstat 108
121#define __NR_olduname 109
122#define __NR_iopl 110
123#define __NR_vhangup 111
124#define __NR_idle 112
125#define __NR_vm86old 113
126#define __NR_wait4 114
127#define __NR_swapoff 115
128#define __NR_sysinfo 116
129#define __NR_ipc 117
130#define __NR_fsync 118
131#define __NR_sigreturn 119
132#define __NR_clone 120
133#define __NR_setdomainname 121
134#define __NR_uname 122
135#define __NR_modify_ldt 123
136#define __NR_adjtimex 124
137#define __NR_mprotect 125
138#define __NR_sigprocmask 126
139#define __NR_create_module 127
140#define __NR_init_module 128
141#define __NR_delete_module 129
142#define __NR_get_kernel_syms 130
143#define __NR_quotactl 131
144#define __NR_getpgid 132
145#define __NR_fchdir 133
146#define __NR_bdflush 134
147#define __NR_sysfs 135
148#define __NR_personality 136
149#define __NR_afs_syscall 137 /* Syscall for Andrew File System */
150#define __NR_setfsuid 138
151#define __NR_setfsgid 139
152#define __NR__llseek 140
153#define __NR_getdents 141
154#define __NR__newselect 142
155#define __NR_flock 143
156#define __NR_msync 144
157#define __NR_readv 145
158#define __NR_writev 146
159#define __NR_getsid 147
160#define __NR_fdatasync 148
161#define __NR__sysctl 149
162#define __NR_mlock 150
163#define __NR_munlock 151
164#define __NR_mlockall 152
165#define __NR_munlockall 153
166#define __NR_sched_setparam 154
167#define __NR_sched_getparam 155
168#define __NR_sched_setscheduler 156
169#define __NR_sched_getscheduler 157
170#define __NR_sched_yield 158
171#define __NR_sched_get_priority_max 159
172#define __NR_sched_get_priority_min 160
173#define __NR_sched_rr_get_interval 161
174#define __NR_nanosleep 162
175#define __NR_mremap 163
176#define __NR_setresuid 164
177#define __NR_getresuid 165
178#define __NR_vm86 166
179#define __NR_query_module 167
180#define __NR_poll 168
181#define __NR_nfsservctl 169
182#define __NR_setresgid 170
183#define __NR_getresgid 171
184#define __NR_prctl 172
185#define __NR_rt_sigreturn 173
186#define __NR_rt_sigaction 174
187#define __NR_rt_sigprocmask 175
188#define __NR_rt_sigpending 176
189#define __NR_rt_sigtimedwait 177
190#define __NR_rt_sigqueueinfo 178
191#define __NR_rt_sigsuspend 179
192#define __NR_pread64 180
193#define __NR_pwrite64 181
194#define __NR_chown 182
195#define __NR_getcwd 183
196#define __NR_capget 184
197#define __NR_capset 185
198#define __NR_sigaltstack 186
199#define __NR_sendfile 187
200#define __NR_streams1 188 /* some people actually want it */
201#define __NR_streams2 189 /* some people actually want it */
202#define __NR_vfork 190
203#define __NR_ugetrlimit 191 /* SuS compliant getrlimit */
204#define __NR_mmap2 192
205#define __NR_truncate64 193
206#define __NR_ftruncate64 194
207#define __NR_stat64 195
208#define __NR_lstat64 196
209#define __NR_fstat64 197
210#define __NR_lchown32 198
211#define __NR_getuid32 199
212#define __NR_getgid32 200
213#define __NR_geteuid32 201
214#define __NR_getegid32 202
215#define __NR_setreuid32 203
216#define __NR_setregid32 204
217#define __NR_getgroups32 205
218#define __NR_setgroups32 206
219#define __NR_fchown32 207
220#define __NR_setresuid32 208
221#define __NR_getresuid32 209
222#define __NR_setresgid32 210
223#define __NR_getresgid32 211
224#define __NR_chown32 212
225#define __NR_setuid32 213
226#define __NR_setgid32 214
227#define __NR_setfsuid32 215
228#define __NR_setfsgid32 216
229#define __NR_pivot_root 217
230#define __NR_mincore 218
231#define __NR_madvise 219
232#define __NR_getdents64 220
233#define __NR_fcntl64 221
234/* 223 is unused */
235#define __NR_gettid 224
236#define __NR_readahead 225
237#define __NR_setxattr 226
238#define __NR_lsetxattr 227
239#define __NR_fsetxattr 228
240#define __NR_getxattr 229
241#define __NR_lgetxattr 230
242#define __NR_fgetxattr 231
243#define __NR_listxattr 232
244#define __NR_llistxattr 233
245#define __NR_flistxattr 234
246#define __NR_removexattr 235
247#define __NR_lremovexattr 236
248#define __NR_fremovexattr 237
249#define __NR_tkill 238
250#define __NR_sendfile64 239
251#define __NR_futex 240
252#define __NR_sched_setaffinity 241
253#define __NR_sched_getaffinity 242
254#define __NR_set_thread_area 243
255#define __NR_get_thread_area 244
256#define __NR_io_setup 245
257#define __NR_io_destroy 246
258#define __NR_io_getevents 247
259#define __NR_io_submit 248
260#define __NR_io_cancel 249
261#define __NR_fadvise64 250
262
263#define __NR_exit_group 252
264#define __NR_lookup_dcookie 253
265#define __NR_epoll_create 254
266#define __NR_epoll_ctl 255
267#define __NR_epoll_wait 256
268#define __NR_remap_file_pages 257
269#define __NR_set_tid_address 258
270#define __NR_timer_create 259
271#define __NR_timer_settime (__NR_timer_create+1)
272#define __NR_timer_gettime (__NR_timer_create+2)
273#define __NR_timer_getoverrun (__NR_timer_create+3)
274#define __NR_timer_delete (__NR_timer_create+4)
275#define __NR_clock_settime (__NR_timer_create+5)
276#define __NR_clock_gettime (__NR_timer_create+6)
277#define __NR_clock_getres (__NR_timer_create+7)
278#define __NR_clock_nanosleep (__NR_timer_create+8)
279#define __NR_statfs64 268
280#define __NR_fstatfs64 269
281#define __NR_tgkill 270
282#define __NR_utimes 271
283#define __NR_fadvise64_64 272
284#define __NR_vserver 273
285#define __NR_mbind 274
286#define __NR_get_mempolicy 275
287#define __NR_set_mempolicy 276
288#define __NR_mq_open 277
289#define __NR_mq_unlink (__NR_mq_open+1)
290#define __NR_mq_timedsend (__NR_mq_open+2)
291#define __NR_mq_timedreceive (__NR_mq_open+3)
292#define __NR_mq_notify (__NR_mq_open+4)
293#define __NR_mq_getsetattr (__NR_mq_open+5)
294#define __NR_kexec_load 283
295#define __NR_waitid 284
296#define __NR_add_key 285
297#define __NR_request_key 286
298#define __NR_keyctl 287
299#define __NR_ioprio_set 288
300#define __NR_ioprio_get 289
301#define __NR_inotify_init 290
302#define __NR_inotify_add_watch 291
303#define __NR_inotify_rm_watch 292
304/* 293 is unused */
305#define __NR_migrate_pages 294
306#define __NR_openat 295
307#define __NR_mkdirat 296
308#define __NR_mknodat 297
309#define __NR_fchownat 298
310#define __NR_futimesat 299
311#define __NR_fstatat64 300
312#define __NR_unlinkat 301
313#define __NR_renameat 302
314#define __NR_linkat 303
315#define __NR_symlinkat 304
316#define __NR_readlinkat 305
317#define __NR_fchmodat 306
318#define __NR_faccessat 307
319#define __NR_pselect6 308
320#define __NR_ppoll 309
321#define __NR_unshare 310
322#define __NR_set_robust_list 311
323#define __NR_get_robust_list 312
324#define __NR_splice 313
325#define __NR_sync_file_range 314
326#define __NR_tee 315
327#define __NR_vmsplice 316
328#define __NR_move_pages 317
329#define __NR_getcpu 318
330#define __NR_epoll_pwait 319
331#define __NR_utimensat 320
332#define __NR_signalfd 321
333#define __NR_timerfd_create 322
334#define __NR_eventfd 323
335#define __NR_fallocate 324
336#define __NR_timerfd_settime 325
337#define __NR_timerfd_gettime 326
338
339#define NR_syscalls 327
340
341#ifdef __KERNEL__
342
343#define __ARCH_WANT_IPC_PARSE_VERSION
344#define __ARCH_WANT_OLD_READDIR
345#define __ARCH_WANT_OLD_STAT
346#define __ARCH_WANT_STAT64
347#define __ARCH_WANT_SYS_ALARM
348#define __ARCH_WANT_SYS_GETHOSTNAME
349#define __ARCH_WANT_SYS_PAUSE
350#define __ARCH_WANT_SYS_SGETMASK
351#define __ARCH_WANT_SYS_SIGNAL
352#define __ARCH_WANT_SYS_TIME
353#define __ARCH_WANT_SYS_UTIME
354#define __ARCH_WANT_SYS_WAITPID
355#define __ARCH_WANT_SYS_SOCKETCALL
356#define __ARCH_WANT_SYS_FADVISE64
357#define __ARCH_WANT_SYS_GETPGRP
358#define __ARCH_WANT_SYS_LLSEEK
359#define __ARCH_WANT_SYS_NICE
360#define __ARCH_WANT_SYS_OLD_GETRLIMIT
361#define __ARCH_WANT_SYS_OLDUMOUNT
362#define __ARCH_WANT_SYS_SIGPENDING
363#define __ARCH_WANT_SYS_SIGPROCMASK
364#define __ARCH_WANT_SYS_RT_SIGACTION
365#define __ARCH_WANT_SYS_RT_SIGSUSPEND
366
367/*
368 * "Conditional" syscalls
369 *
370 * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
371 * but it doesn't work on all toolchains, so we just do it by hand
372 */
373#ifndef cond_syscall
374#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
375#endif
376
377#endif /* __KERNEL__ */
378#endif /* __ASM_SH_UNISTD_H */
diff --git a/include/asm-sh/unistd_64.h b/include/asm-sh/unistd_64.h
deleted file mode 100644
index 9d21eab5242..00000000000
--- a/include/asm-sh/unistd_64.h
+++ /dev/null
@@ -1,417 +0,0 @@
1#ifndef __ASM_SH_UNISTD_64_H
2#define __ASM_SH_UNISTD_64_H
3
4/*
5 * include/asm-sh/unistd_64.h
6 *
7 * This file contains the system call numbers.
8 *
9 * Copyright (C) 2000, 2001 Paolo Alberelli
10 * Copyright (C) 2003 - 2007 Paul Mundt
11 * Copyright (C) 2004 Sean McGoogan
12 *
13 * This file is subject to the terms and conditions of the GNU General Public
14 * License. See the file "COPYING" in the main directory of this archive
15 * for more details.
16 */
17#define __NR_restart_syscall 0
18#define __NR_exit 1
19#define __NR_fork 2
20#define __NR_read 3
21#define __NR_write 4
22#define __NR_open 5
23#define __NR_close 6
24#define __NR_waitpid 7
25#define __NR_creat 8
26#define __NR_link 9
27#define __NR_unlink 10
28#define __NR_execve 11
29#define __NR_chdir 12
30#define __NR_time 13
31#define __NR_mknod 14
32#define __NR_chmod 15
33#define __NR_lchown 16
34#define __NR_break 17
35#define __NR_oldstat 18
36#define __NR_lseek 19
37#define __NR_getpid 20
38#define __NR_mount 21
39#define __NR_umount 22
40#define __NR_setuid 23
41#define __NR_getuid 24
42#define __NR_stime 25
43#define __NR_ptrace 26
44#define __NR_alarm 27
45#define __NR_oldfstat 28
46#define __NR_pause 29
47#define __NR_utime 30
48#define __NR_stty 31
49#define __NR_gtty 32
50#define __NR_access 33
51#define __NR_nice 34
52#define __NR_ftime 35
53#define __NR_sync 36
54#define __NR_kill 37
55#define __NR_rename 38
56#define __NR_mkdir 39
57#define __NR_rmdir 40
58#define __NR_dup 41
59#define __NR_pipe 42
60#define __NR_times 43
61#define __NR_prof 44
62#define __NR_brk 45
63#define __NR_setgid 46
64#define __NR_getgid 47
65#define __NR_signal 48
66#define __NR_geteuid 49
67#define __NR_getegid 50
68#define __NR_acct 51
69#define __NR_umount2 52
70#define __NR_lock 53
71#define __NR_ioctl 54
72#define __NR_fcntl 55
73#define __NR_mpx 56
74#define __NR_setpgid 57
75#define __NR_ulimit 58
76#define __NR_oldolduname 59
77#define __NR_umask 60
78#define __NR_chroot 61
79#define __NR_ustat 62
80#define __NR_dup2 63
81#define __NR_getppid 64
82#define __NR_getpgrp 65
83#define __NR_setsid 66
84#define __NR_sigaction 67
85#define __NR_sgetmask 68
86#define __NR_ssetmask 69
87#define __NR_setreuid 70
88#define __NR_setregid 71
89#define __NR_sigsuspend 72
90#define __NR_sigpending 73
91#define __NR_sethostname 74
92#define __NR_setrlimit 75
93#define __NR_getrlimit 76 /* Back compatible 2Gig limited rlimit */
94#define __NR_getrusage 77
95#define __NR_gettimeofday 78
96#define __NR_settimeofday 79
97#define __NR_getgroups 80
98#define __NR_setgroups 81
99#define __NR_select 82
100#define __NR_symlink 83
101#define __NR_oldlstat 84
102#define __NR_readlink 85
103#define __NR_uselib 86
104#define __NR_swapon 87
105#define __NR_reboot 88
106#define __NR_readdir 89
107#define __NR_mmap 90
108#define __NR_munmap 91
109#define __NR_truncate 92
110#define __NR_ftruncate 93
111#define __NR_fchmod 94
112#define __NR_fchown 95
113#define __NR_getpriority 96
114#define __NR_setpriority 97
115#define __NR_profil 98
116#define __NR_statfs 99
117#define __NR_fstatfs 100
118#define __NR_ioperm 101
119#define __NR_socketcall 102 /* old implementation of socket systemcall */
120#define __NR_syslog 103
121#define __NR_setitimer 104
122#define __NR_getitimer 105
123#define __NR_stat 106
124#define __NR_lstat 107
125#define __NR_fstat 108
126#define __NR_olduname 109
127#define __NR_iopl 110
128#define __NR_vhangup 111
129#define __NR_idle 112
130#define __NR_vm86old 113
131#define __NR_wait4 114
132#define __NR_swapoff 115
133#define __NR_sysinfo 116
134#define __NR_ipc 117
135#define __NR_fsync 118
136#define __NR_sigreturn 119
137#define __NR_clone 120
138#define __NR_setdomainname 121
139#define __NR_uname 122
140#define __NR_modify_ldt 123
141#define __NR_adjtimex 124
142#define __NR_mprotect 125
143#define __NR_sigprocmask 126
144#define __NR_create_module 127
145#define __NR_init_module 128
146#define __NR_delete_module 129
147#define __NR_get_kernel_syms 130
148#define __NR_quotactl 131
149#define __NR_getpgid 132
150#define __NR_fchdir 133
151#define __NR_bdflush 134
152#define __NR_sysfs 135
153#define __NR_personality 136
154#define __NR_afs_syscall 137 /* Syscall for Andrew File System */
155#define __NR_setfsuid 138
156#define __NR_setfsgid 139
157#define __NR__llseek 140
158#define __NR_getdents 141
159#define __NR__newselect 142
160#define __NR_flock 143
161#define __NR_msync 144
162#define __NR_readv 145
163#define __NR_writev 146
164#define __NR_getsid 147
165#define __NR_fdatasync 148
166#define __NR__sysctl 149
167#define __NR_mlock 150
168#define __NR_munlock 151
169#define __NR_mlockall 152
170#define __NR_munlockall 153
171#define __NR_sched_setparam 154
172#define __NR_sched_getparam 155
173#define __NR_sched_setscheduler 156
174#define __NR_sched_getscheduler 157
175#define __NR_sched_yield 158
176#define __NR_sched_get_priority_max 159
177#define __NR_sched_get_priority_min 160
178#define __NR_sched_rr_get_interval 161
179#define __NR_nanosleep 162
180#define __NR_mremap 163
181#define __NR_setresuid 164
182#define __NR_getresuid 165
183#define __NR_vm86 166
184#define __NR_query_module 167
185#define __NR_poll 168
186#define __NR_nfsservctl 169
187#define __NR_setresgid 170
188#define __NR_getresgid 171
189#define __NR_prctl 172
190#define __NR_rt_sigreturn 173
191#define __NR_rt_sigaction 174
192#define __NR_rt_sigprocmask 175
193#define __NR_rt_sigpending 176
194#define __NR_rt_sigtimedwait 177
195#define __NR_rt_sigqueueinfo 178
196#define __NR_rt_sigsuspend 179
197#define __NR_pread64 180
198#define __NR_pwrite64 181
199#define __NR_chown 182
200#define __NR_getcwd 183
201#define __NR_capget 184
202#define __NR_capset 185
203#define __NR_sigaltstack 186
204#define __NR_sendfile 187
205#define __NR_streams1 188 /* some people actually want it */
206#define __NR_streams2 189 /* some people actually want it */
207#define __NR_vfork 190
208#define __NR_ugetrlimit 191 /* SuS compliant getrlimit */
209#define __NR_mmap2 192
210#define __NR_truncate64 193
211#define __NR_ftruncate64 194
212#define __NR_stat64 195
213#define __NR_lstat64 196
214#define __NR_fstat64 197
215#define __NR_lchown32 198
216#define __NR_getuid32 199
217#define __NR_getgid32 200
218#define __NR_geteuid32 201
219#define __NR_getegid32 202
220#define __NR_setreuid32 203
221#define __NR_setregid32 204
222#define __NR_getgroups32 205
223#define __NR_setgroups32 206
224#define __NR_fchown32 207
225#define __NR_setresuid32 208
226#define __NR_getresuid32 209
227#define __NR_setresgid32 210
228#define __NR_getresgid32 211
229#define __NR_chown32 212
230#define __NR_setuid32 213
231#define __NR_setgid32 214
232#define __NR_setfsuid32 215
233#define __NR_setfsgid32 216
234#define __NR_pivot_root 217
235#define __NR_mincore 218
236#define __NR_madvise 219
237
238/* Non-multiplexed socket family */
239#define __NR_socket 220
240#define __NR_bind 221
241#define __NR_connect 222
242#define __NR_listen 223
243#define __NR_accept 224
244#define __NR_getsockname 225
245#define __NR_getpeername 226
246#define __NR_socketpair 227
247#define __NR_send 228
248#define __NR_sendto 229
249#define __NR_recv 230
250#define __NR_recvfrom 231
251#define __NR_shutdown 232
252#define __NR_setsockopt 233
253#define __NR_getsockopt 234
254#define __NR_sendmsg 235
255#define __NR_recvmsg 236
256
257/* Non-multiplexed IPC family */
258#define __NR_semop 237
259#define __NR_semget 238
260#define __NR_semctl 239
261#define __NR_msgsnd 240
262#define __NR_msgrcv 241
263#define __NR_msgget 242
264#define __NR_msgctl 243
265#if 0
266#define __NR_shmatcall 244
267#endif
268#define __NR_shmdt 245
269#define __NR_shmget 246
270#define __NR_shmctl 247
271
272#define __NR_getdents64 248
273#define __NR_fcntl64 249
274/* 223 is unused */
275#define __NR_gettid 252
276#define __NR_readahead 253
277#define __NR_setxattr 254
278#define __NR_lsetxattr 255
279#define __NR_fsetxattr 256
280#define __NR_getxattr 257
281#define __NR_lgetxattr 258
282#define __NR_fgetxattr 269
283#define __NR_listxattr 260
284#define __NR_llistxattr 261
285#define __NR_flistxattr 262
286#define __NR_removexattr 263
287#define __NR_lremovexattr 264
288#define __NR_fremovexattr 265
289#define __NR_tkill 266
290#define __NR_sendfile64 267
291#define __NR_futex 268
292#define __NR_sched_setaffinity 269
293#define __NR_sched_getaffinity 270
294#define __NR_set_thread_area 271
295#define __NR_get_thread_area 272
296#define __NR_io_setup 273
297#define __NR_io_destroy 274
298#define __NR_io_getevents 275
299#define __NR_io_submit 276
300#define __NR_io_cancel 277
301#define __NR_fadvise64 278
302#define __NR_exit_group 280
303
304#define __NR_lookup_dcookie 281
305#define __NR_epoll_create 282
306#define __NR_epoll_ctl 283
307#define __NR_epoll_wait 284
308#define __NR_remap_file_pages 285
309#define __NR_set_tid_address 286
310#define __NR_timer_create 287
311#define __NR_timer_settime (__NR_timer_create+1)
312#define __NR_timer_gettime (__NR_timer_create+2)
313#define __NR_timer_getoverrun (__NR_timer_create+3)
314#define __NR_timer_delete (__NR_timer_create+4)
315#define __NR_clock_settime (__NR_timer_create+5)
316#define __NR_clock_gettime (__NR_timer_create+6)
317#define __NR_clock_getres (__NR_timer_create+7)
318#define __NR_clock_nanosleep (__NR_timer_create+8)
319#define __NR_statfs64 296
320#define __NR_fstatfs64 297
321#define __NR_tgkill 298
322#define __NR_utimes 299
323#define __NR_fadvise64_64 300
324#define __NR_vserver 301
325#define __NR_mbind 302
326#define __NR_get_mempolicy 303
327#define __NR_set_mempolicy 304
328#define __NR_mq_open 305
329#define __NR_mq_unlink (__NR_mq_open+1)
330#define __NR_mq_timedsend (__NR_mq_open+2)
331#define __NR_mq_timedreceive (__NR_mq_open+3)
332#define __NR_mq_notify (__NR_mq_open+4)
333#define __NR_mq_getsetattr (__NR_mq_open+5)
334#define __NR_kexec_load 311
335#define __NR_waitid 312
336#define __NR_add_key 313
337#define __NR_request_key 314
338#define __NR_keyctl 315
339#define __NR_ioprio_set 316
340#define __NR_ioprio_get 317
341#define __NR_inotify_init 318
342#define __NR_inotify_add_watch 319
343#define __NR_inotify_rm_watch 320
344/* 321 is unused */
345#define __NR_migrate_pages 322
346#define __NR_openat 323
347#define __NR_mkdirat 324
348#define __NR_mknodat 325
349#define __NR_fchownat 326
350#define __NR_futimesat 327
351#define __NR_fstatat64 328
352#define __NR_unlinkat 329
353#define __NR_renameat 330
354#define __NR_linkat 331
355#define __NR_symlinkat 332
356#define __NR_readlinkat 333
357#define __NR_fchmodat 334
358#define __NR_faccessat 335
359#define __NR_pselect6 336
360#define __NR_ppoll 337
361#define __NR_unshare 338
362#define __NR_set_robust_list 339
363#define __NR_get_robust_list 340
364#define __NR_splice 341
365#define __NR_sync_file_range 342
366#define __NR_tee 343
367#define __NR_vmsplice 344
368#define __NR_move_pages 345
369#define __NR_getcpu 346
370#define __NR_epoll_pwait 347
371#define __NR_utimensat 348
372#define __NR_signalfd 349
373#define __NR_timerfd_create 350
374#define __NR_eventfd 351
375#define __NR_fallocate 352
376#define __NR_timerfd_settime 353
377#define __NR_timerfd_gettime 354
378
379#ifdef __KERNEL__
380
381#define NR_syscalls 353
382
383#define __ARCH_WANT_IPC_PARSE_VERSION
384#define __ARCH_WANT_OLD_READDIR
385#define __ARCH_WANT_OLD_STAT
386#define __ARCH_WANT_STAT64
387#define __ARCH_WANT_SYS_ALARM
388#define __ARCH_WANT_SYS_GETHOSTNAME
389#define __ARCH_WANT_SYS_PAUSE
390#define __ARCH_WANT_SYS_SGETMASK
391#define __ARCH_WANT_SYS_SIGNAL
392#define __ARCH_WANT_SYS_TIME
393#define __ARCH_WANT_SYS_UTIME
394#define __ARCH_WANT_SYS_WAITPID
395#define __ARCH_WANT_SYS_SOCKETCALL
396#define __ARCH_WANT_SYS_FADVISE64
397#define __ARCH_WANT_SYS_GETPGRP
398#define __ARCH_WANT_SYS_LLSEEK
399#define __ARCH_WANT_SYS_NICE
400#define __ARCH_WANT_SYS_OLD_GETRLIMIT
401#define __ARCH_WANT_SYS_OLDUMOUNT
402#define __ARCH_WANT_SYS_SIGPENDING
403#define __ARCH_WANT_SYS_SIGPROCMASK
404#define __ARCH_WANT_SYS_RT_SIGACTION
405
406/*
407 * "Conditional" syscalls
408 *
409 * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
410 * but it doesn't work on all toolchains, so we just do it by hand
411 */
412#ifndef cond_syscall
413#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
414#endif
415
416#endif /* __KERNEL__ */
417#endif /* __ASM_SH_UNISTD_64_H */
diff --git a/include/asm-sh/user.h b/include/asm-sh/user.h
deleted file mode 100644
index 8fd3cf6c58d..00000000000
--- a/include/asm-sh/user.h
+++ /dev/null
@@ -1,67 +0,0 @@
1#ifndef __ASM_SH_USER_H
2#define __ASM_SH_USER_H
3
4#include <asm/ptrace.h>
5#include <asm/page.h>
6
7/*
8 * Core file format: The core file is written in such a way that gdb
9 * can understand it and provide useful information to the user (under
10 * linux we use the `trad-core' bfd). The file contents are as follows:
11 *
12 * upage: 1 page consisting of a user struct that tells gdb
13 * what is present in the file. Directly after this is a
14 * copy of the task_struct, which is currently not used by gdb,
15 * but it may come in handy at some point. All of the registers
16 * are stored as part of the upage. The upage should always be
17 * only one page long.
18 * data: The data segment follows next. We use current->end_text to
19 * current->brk to pick up all of the user variables, plus any memory
20 * that may have been sbrk'ed. No attempt is made to determine if a
21 * page is demand-zero or if a page is totally unused, we just cover
22 * the entire range. All of the addresses are rounded in such a way
23 * that an integral number of pages is written.
24 * stack: We need the stack information in order to get a meaningful
25 * backtrace. We need to write the data from usp to
26 * current->start_stack, so we round each of these in order to be able
27 * to write an integer number of pages.
28 */
29
30#if defined(__SH5__) || defined(CONFIG_CPU_SH5)
31struct user_fpu_struct {
32 unsigned long fp_regs[32];
33 unsigned int fpscr;
34};
35#else
36struct user_fpu_struct {
37 unsigned long fp_regs[16];
38 unsigned long xfp_regs[16];
39 unsigned long fpscr;
40 unsigned long fpul;
41};
42#endif
43
44struct user {
45 struct pt_regs regs; /* entire machine state */
46 struct user_fpu_struct fpu; /* Math Co-processor registers */
47 int u_fpvalid; /* True if math co-processor being used */
48 size_t u_tsize; /* text size (pages) */
49 size_t u_dsize; /* data size (pages) */
50 size_t u_ssize; /* stack size (pages) */
51 unsigned long start_code; /* text starting address */
52 unsigned long start_data; /* data starting address */
53 unsigned long start_stack; /* stack starting address */
54 long int signal; /* signal causing core dump */
55 unsigned long u_ar0; /* help gdb find registers */
56 struct user_fpu_struct* u_fpstate; /* Math Co-processor pointer */
57 unsigned long magic; /* identifies a core file */
58 char u_comm[32]; /* user command name */
59};
60
61#define NBPG PAGE_SIZE
62#define UPAGES 1
63#define HOST_TEXT_START_ADDR (u.start_code)
64#define HOST_DATA_START_ADDR (u.start_data)
65#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
66
67#endif /* __ASM_SH_USER_H */
diff --git a/include/asm-sh/vga.h b/include/asm-sh/vga.h
deleted file mode 100644
index 06a5de8ace1..00000000000
--- a/include/asm-sh/vga.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef __ASM_SH_VGA_H
2#define __ASM_SH_VGA_H
3
4/* Stupid drivers. */
5
6#endif /* __ASM_SH_VGA_H */
diff --git a/include/asm-sh/watchdog.h b/include/asm-sh/watchdog.h
deleted file mode 100644
index d19ea62ef8c..00000000000
--- a/include/asm-sh/watchdog.h
+++ /dev/null
@@ -1,107 +0,0 @@
1/*
2 * include/asm-sh/watchdog.h
3 *
4 * Copyright (C) 2002, 2003 Paul Mundt
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11#ifndef __ASM_SH_WATCHDOG_H
12#define __ASM_SH_WATCHDOG_H
13#ifdef __KERNEL__
14
15#include <linux/types.h>
16#include <asm/cpu/watchdog.h>
17#include <asm/io.h>
18
19/*
20 * See asm/cpu-sh2/watchdog.h for explanation of this stupidity..
21 */
22#ifndef WTCNT_R
23# define WTCNT_R WTCNT
24#endif
25
26#ifndef WTCSR_R
27# define WTCSR_R WTCSR
28#endif
29
30#define WTCNT_HIGH 0x5a
31#define WTCSR_HIGH 0xa5
32
33#define WTCSR_CKS2 0x04
34#define WTCSR_CKS1 0x02
35#define WTCSR_CKS0 0x01
36
37/*
38 * CKS0-2 supports a number of clock division ratios. At the time the watchdog
39 * is enabled, it defaults to a 41 usec overflow period .. we overload this to
40 * something a little more reasonable, and really can't deal with anything
41 * lower than WTCSR_CKS_1024, else we drop back into the usec range.
42 *
43 * Clock Division Ratio Overflow Period
44 * --------------------------------------------
45 * 1/32 (initial value) 41 usecs
46 * 1/64 82 usecs
47 * 1/128 164 usecs
48 * 1/256 328 usecs
49 * 1/512 656 usecs
50 * 1/1024 1.31 msecs
51 * 1/2048 2.62 msecs
52 * 1/4096 5.25 msecs
53 */
54#define WTCSR_CKS_32 0x00
55#define WTCSR_CKS_64 0x01
56#define WTCSR_CKS_128 0x02
57#define WTCSR_CKS_256 0x03
58#define WTCSR_CKS_512 0x04
59#define WTCSR_CKS_1024 0x05
60#define WTCSR_CKS_2048 0x06
61#define WTCSR_CKS_4096 0x07
62
63/**
64 * sh_wdt_read_cnt - Read from Counter
65 * Reads back the WTCNT value.
66 */
67static inline __u8 sh_wdt_read_cnt(void)
68{
69 return ctrl_inb(WTCNT_R);
70}
71
72/**
73 * sh_wdt_write_cnt - Write to Counter
74 * @val: Value to write
75 *
76 * Writes the given value @val to the lower byte of the timer counter.
77 * The upper byte is set manually on each write.
78 */
79static inline void sh_wdt_write_cnt(__u8 val)
80{
81 ctrl_outw((WTCNT_HIGH << 8) | (__u16)val, WTCNT);
82}
83
84/**
85 * sh_wdt_read_csr - Read from Control/Status Register
86 *
87 * Reads back the WTCSR value.
88 */
89static inline __u8 sh_wdt_read_csr(void)
90{
91 return ctrl_inb(WTCSR_R);
92}
93
94/**
95 * sh_wdt_write_csr - Write to Control/Status Register
96 * @val: Value to write
97 *
98 * Writes the given value @val to the lower byte of the control/status
99 * register. The upper byte is set manually on each write.
100 */
101static inline void sh_wdt_write_csr(__u8 val)
102{
103 ctrl_outw((WTCSR_HIGH << 8) | (__u16)val, WTCSR);
104}
105
106#endif /* __KERNEL__ */
107#endif /* __ASM_SH_WATCHDOG_H */
diff --git a/include/asm-sh/xor.h b/include/asm-sh/xor.h
deleted file mode 100644
index c82eb12a5b1..00000000000
--- a/include/asm-sh/xor.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/xor.h>
diff --git a/include/asm-sparc/Kbuild b/include/asm-sparc/Kbuild
deleted file mode 100644
index 6cdaf9d33b3..00000000000
--- a/include/asm-sparc/Kbuild
+++ /dev/null
@@ -1 +0,0 @@
1# dummy file to avoid breaking make headers_install
diff --git a/include/asm-sparc/agp.h b/include/asm-sparc/agp.h
deleted file mode 100644
index c2456870b05..00000000000
--- a/include/asm-sparc/agp.h
+++ /dev/null
@@ -1,20 +0,0 @@
1#ifndef AGP_H
2#define AGP_H 1
3
4/* dummy for now */
5
6#define map_page_into_agp(page)
7#define unmap_page_from_agp(page)
8#define flush_agp_cache() mb()
9
10/* Convert a physical address to an address suitable for the GART. */
11#define phys_to_gart(x) (x)
12#define gart_to_phys(x) (x)
13
14/* GATT allocation. Returns/accepts GATT kernel virtual address. */
15#define alloc_gatt_pages(order) \
16 ((char *)__get_free_pages(GFP_KERNEL, (order)))
17#define free_gatt_pages(table, order) \
18 free_pages((unsigned long)(table), (order))
19
20#endif
diff --git a/include/asm-sparc/apb.h b/include/asm-sparc/apb.h
deleted file mode 100644
index 8f3b57db810..00000000000
--- a/include/asm-sparc/apb.h
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * apb.h: Advanced PCI Bridge Configuration Registers and Bits
3 *
4 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
5 */
6
7#ifndef _SPARC64_APB_H
8#define _SPARC64_APB_H
9
10#define APB_TICK_REGISTER 0xb0
11#define APB_INT_ACK 0xb8
12#define APB_PRIMARY_MASTER_RETRY_LIMIT 0xc0
13#define APB_DMA_ASFR 0xc8
14#define APB_DMA_AFAR 0xd0
15#define APB_PIO_TARGET_RETRY_LIMIT 0xd8
16#define APB_PIO_TARGET_LATENCY_TIMER 0xd9
17#define APB_DMA_TARGET_RETRY_LIMIT 0xda
18#define APB_DMA_TARGET_LATENCY_TIMER 0xdb
19#define APB_SECONDARY_MASTER_RETRY_LIMIT 0xdc
20#define APB_SECONDARY_CONTROL 0xdd
21#define APB_IO_ADDRESS_MAP 0xde
22#define APB_MEM_ADDRESS_MAP 0xdf
23
24#define APB_PCI_CONTROL_LOW 0xe0
25# define APB_PCI_CTL_LOW_ARB_PARK (1 << 21)
26# define APB_PCI_CTL_LOW_ERRINT_EN (1 << 8)
27
28#define APB_PCI_CONTROL_HIGH 0xe4
29# define APB_PCI_CTL_HIGH_SERR (1 << 2)
30# define APB_PCI_CTL_HIGH_ARBITER_EN (1 << 0)
31
32#define APB_PIO_ASFR 0xe8
33#define APB_PIO_AFAR 0xf0
34#define APB_DIAG_REGISTER 0xf8
35
36#endif /* !(_SPARC64_APB_H) */
diff --git a/include/asm-sparc/apc.h b/include/asm-sparc/apc.h
deleted file mode 100644
index 24e9a7d4d97..00000000000
--- a/include/asm-sparc/apc.h
+++ /dev/null
@@ -1,64 +0,0 @@
1/* apc - Driver definitions for power management functions
2 * of Aurora Personality Chip (APC) on SPARCstation-4/5 and
3 * derivatives
4 *
5 * Copyright (c) 2001 Eric Brower (ebrower@usa.net)
6 *
7 */
8
9#ifndef _SPARC_APC_H
10#define _SPARC_APC_H
11
12#include <linux/ioctl.h>
13
14#define APC_IOC 'A'
15
16#define APCIOCGFANCTL _IOR(APC_IOC, 0x00, int) /* Get fan speed */
17#define APCIOCSFANCTL _IOW(APC_IOC, 0x01, int) /* Set fan speed */
18
19#define APCIOCGCPWR _IOR(APC_IOC, 0x02, int) /* Get CPOWER state */
20#define APCIOCSCPWR _IOW(APC_IOC, 0x03, int) /* Set CPOWER state */
21
22#define APCIOCGBPORT _IOR(APC_IOC, 0x04, int) /* Get BPORT state */
23#define APCIOCSBPORT _IOW(APC_IOC, 0x05, int) /* Set BPORT state */
24
25/*
26 * Register offsets
27 */
28#define APC_IDLE_REG 0x00
29#define APC_FANCTL_REG 0x20
30#define APC_CPOWER_REG 0x24
31#define APC_BPORT_REG 0x30
32
33#define APC_REGMASK 0x01
34#define APC_BPMASK 0x03
35
36/*
37 * IDLE - CPU standby values (set to initiate standby)
38 */
39#define APC_IDLE_ON 0x01
40
41/*
42 * FANCTL - Fan speed control state values
43 */
44#define APC_FANCTL_HI 0x00 /* Fan speed high */
45#define APC_FANCTL_LO 0x01 /* Fan speed low */
46
47/*
48 * CPWR - Convenience power outlet state values
49 */
50#define APC_CPOWER_ON 0x00 /* Conv power on */
51#define APC_CPOWER_OFF 0x01 /* Conv power off */
52
53/*
54 * BPA/BPB - Read-Write "Bit Ports" state values (reset to 0 at power-on)
55 *
56 * WARNING: Internal usage of bit ports is platform dependent--
57 * don't modify BPORT settings unless you know what you are doing.
58 *
59 * On SS5 BPA seems to toggle onboard ethernet loopback... -E
60 */
61#define APC_BPORT_A 0x01 /* Bit Port A */
62#define APC_BPORT_B 0x02 /* Bit Port B */
63
64#endif /* !(_SPARC_APC_H) */
diff --git a/include/asm-sparc/asi.h b/include/asm-sparc/asi.h
deleted file mode 100644
index 74703c5ef98..00000000000
--- a/include/asm-sparc/asi.h
+++ /dev/null
@@ -1,262 +0,0 @@
1#ifndef _SPARC_ASI_H
2#define _SPARC_ASI_H
3
4/* asi.h: Address Space Identifier values for the sparc.
5 *
6 * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
7 *
8 * Pioneer work for sun4m: Paul Hatchman (paul@sfe.com.au)
9 * Joint edition for sun4c+sun4m: Pete A. Zaitcev <zaitcev@ipmce.su>
10 */
11
12/* The first batch are for the sun4c. */
13
14#define ASI_NULL1 0x00
15#define ASI_NULL2 0x01
16
17/* sun4c and sun4 control registers and mmu/vac ops */
18#define ASI_CONTROL 0x02
19#define ASI_SEGMAP 0x03
20#define ASI_PTE 0x04
21#define ASI_HWFLUSHSEG 0x05
22#define ASI_HWFLUSHPAGE 0x06
23#define ASI_REGMAP 0x06
24#define ASI_HWFLUSHCONTEXT 0x07
25
26#define ASI_USERTXT 0x08
27#define ASI_KERNELTXT 0x09
28#define ASI_USERDATA 0x0a
29#define ASI_KERNELDATA 0x0b
30
31/* VAC Cache flushing on sun4c and sun4 */
32#define ASI_FLUSHSEG 0x0c
33#define ASI_FLUSHPG 0x0d
34#define ASI_FLUSHCTX 0x0e
35
36/* SPARCstation-5: only 6 bits are decoded. */
37/* wo = Write Only, rw = Read Write; */
38/* ss = Single Size, as = All Sizes; */
39#define ASI_M_RES00 0x00 /* Don't touch... */
40#define ASI_M_UNA01 0x01 /* Same here... */
41#define ASI_M_MXCC 0x02 /* Access to TI VIKING MXCC registers */
42#define ASI_M_FLUSH_PROBE 0x03 /* Reference MMU Flush/Probe; rw, ss */
43#define ASI_M_MMUREGS 0x04 /* MMU Registers; rw, ss */
44#define ASI_M_TLBDIAG 0x05 /* MMU TLB only Diagnostics */
45#define ASI_M_DIAGS 0x06 /* Reference MMU Diagnostics */
46#define ASI_M_IODIAG 0x07 /* MMU I/O TLB only Diagnostics */
47#define ASI_M_USERTXT 0x08 /* Same as ASI_USERTXT; rw, as */
48#define ASI_M_KERNELTXT 0x09 /* Same as ASI_KERNELTXT; rw, as */
49#define ASI_M_USERDATA 0x0A /* Same as ASI_USERDATA; rw, as */
50#define ASI_M_KERNELDATA 0x0B /* Same as ASI_KERNELDATA; rw, as */
51#define ASI_M_TXTC_TAG 0x0C /* Instruction Cache Tag; rw, ss */
52#define ASI_M_TXTC_DATA 0x0D /* Instruction Cache Data; rw, ss */
53#define ASI_M_DATAC_TAG 0x0E /* Data Cache Tag; rw, ss */
54#define ASI_M_DATAC_DATA 0x0F /* Data Cache Data; rw, ss */
55
56/* The following cache flushing ASIs work only with the 'sta'
57 * instruction. Results are unpredictable for 'swap' and 'ldstuba',
58 * so don't do it.
59 */
60
61/* These ASI flushes affect external caches too. */
62#define ASI_M_FLUSH_PAGE 0x10 /* Flush I&D Cache Line (page); wo, ss */
63#define ASI_M_FLUSH_SEG 0x11 /* Flush I&D Cache Line (seg); wo, ss */
64#define ASI_M_FLUSH_REGION 0x12 /* Flush I&D Cache Line (region); wo, ss */
65#define ASI_M_FLUSH_CTX 0x13 /* Flush I&D Cache Line (context); wo, ss */
66#define ASI_M_FLUSH_USER 0x14 /* Flush I&D Cache Line (user); wo, ss */
67
68/* Block-copy operations are available only on certain V8 cpus. */
69#define ASI_M_BCOPY 0x17 /* Block copy */
70
71/* These affect only the ICACHE and are Ross HyperSparc and TurboSparc specific. */
72#define ASI_M_IFLUSH_PAGE 0x18 /* Flush I Cache Line (page); wo, ss */
73#define ASI_M_IFLUSH_SEG 0x19 /* Flush I Cache Line (seg); wo, ss */
74#define ASI_M_IFLUSH_REGION 0x1A /* Flush I Cache Line (region); wo, ss */
75#define ASI_M_IFLUSH_CTX 0x1B /* Flush I Cache Line (context); wo, ss */
76#define ASI_M_IFLUSH_USER 0x1C /* Flush I Cache Line (user); wo, ss */
77
78/* Block-fill operations are available on certain V8 cpus */
79#define ASI_M_BFILL 0x1F
80
81/* This allows direct access to main memory, actually 0x20 to 0x2f are
82 * the available ASI's for physical ram pass-through, but I don't have
83 * any idea what the other ones do....
84 */
85
86#define ASI_M_BYPASS 0x20 /* Reference MMU bypass; rw, as */
87#define ASI_M_FBMEM 0x29 /* Graphics card frame buffer access */
88#define ASI_M_VMEUS 0x2A /* VME user 16-bit access */
89#define ASI_M_VMEPS 0x2B /* VME priv 16-bit access */
90#define ASI_M_VMEUT 0x2C /* VME user 32-bit access */
91#define ASI_M_VMEPT 0x2D /* VME priv 32-bit access */
92#define ASI_M_SBUS 0x2E /* Direct SBus access */
93#define ASI_M_CTL 0x2F /* Control Space (ECC and MXCC are here) */
94
95
96/* This is ROSS HyperSparc only. */
97#define ASI_M_FLUSH_IWHOLE 0x31 /* Flush entire ICACHE; wo, ss */
98
99/* Tsunami/Viking/TurboSparc i/d cache flash clear. */
100#define ASI_M_IC_FLCLEAR 0x36
101#define ASI_M_DC_FLCLEAR 0x37
102
103#define ASI_M_DCDR 0x39 /* Data Cache Diagnostics Register rw, ss */
104
105#define ASI_M_VIKING_TMP1 0x40 /* Emulation temporary 1 on Viking */
106/* only available on SuperSparc I */
107/* #define ASI_M_VIKING_TMP2 0x41 */ /* Emulation temporary 2 on Viking */
108
109#define ASI_M_ACTION 0x4c /* Breakpoint Action Register (GNU/Viking) */
110
111/* V9 Architecture mandary ASIs. */
112#define ASI_N 0x04 /* Nucleus */
113#define ASI_NL 0x0c /* Nucleus, little endian */
114#define ASI_AIUP 0x10 /* Primary, user */
115#define ASI_AIUS 0x11 /* Secondary, user */
116#define ASI_AIUPL 0x18 /* Primary, user, little endian */
117#define ASI_AIUSL 0x19 /* Secondary, user, little endian */
118#define ASI_P 0x80 /* Primary, implicit */
119#define ASI_S 0x81 /* Secondary, implicit */
120#define ASI_PNF 0x82 /* Primary, no fault */
121#define ASI_SNF 0x83 /* Secondary, no fault */
122#define ASI_PL 0x88 /* Primary, implicit, l-endian */
123#define ASI_SL 0x89 /* Secondary, implicit, l-endian */
124#define ASI_PNFL 0x8a /* Primary, no fault, l-endian */
125#define ASI_SNFL 0x8b /* Secondary, no fault, l-endian */
126
127/* SpitFire and later extended ASIs. The "(III)" marker designates
128 * UltraSparc-III and later specific ASIs. The "(CMT)" marker designates
129 * Chip Multi Threading specific ASIs. "(NG)" designates Niagara specific
130 * ASIs, "(4V)" designates SUN4V specific ASIs.
131 */
132#define ASI_PHYS_USE_EC 0x14 /* PADDR, E-cachable */
133#define ASI_PHYS_BYPASS_EC_E 0x15 /* PADDR, E-bit */
134#define ASI_BLK_AIUP_4V 0x16 /* (4V) Prim, user, block ld/st */
135#define ASI_BLK_AIUS_4V 0x17 /* (4V) Sec, user, block ld/st */
136#define ASI_PHYS_USE_EC_L 0x1c /* PADDR, E-cachable, little endian*/
137#define ASI_PHYS_BYPASS_EC_E_L 0x1d /* PADDR, E-bit, little endian */
138#define ASI_BLK_AIUP_L_4V 0x1e /* (4V) Prim, user, block, l-endian*/
139#define ASI_BLK_AIUS_L_4V 0x1f /* (4V) Sec, user, block, l-endian */
140#define ASI_SCRATCHPAD 0x20 /* (4V) Scratch Pad Registers */
141#define ASI_MMU 0x21 /* (4V) MMU Context Registers */
142#define ASI_BLK_INIT_QUAD_LDD_AIUS 0x23 /* (NG) init-store, twin load,
143 * secondary, user
144 */
145#define ASI_NUCLEUS_QUAD_LDD 0x24 /* Cachable, qword load */
146#define ASI_QUEUE 0x25 /* (4V) Interrupt Queue Registers */
147#define ASI_QUAD_LDD_PHYS_4V 0x26 /* (4V) Physical, qword load */
148#define ASI_NUCLEUS_QUAD_LDD_L 0x2c /* Cachable, qword load, l-endian */
149#define ASI_QUAD_LDD_PHYS_L_4V 0x2e /* (4V) Phys, qword load, l-endian */
150#define ASI_PCACHE_DATA_STATUS 0x30 /* (III) PCache data stat RAM diag */
151#define ASI_PCACHE_DATA 0x31 /* (III) PCache data RAM diag */
152#define ASI_PCACHE_TAG 0x32 /* (III) PCache tag RAM diag */
153#define ASI_PCACHE_SNOOP_TAG 0x33 /* (III) PCache snoop tag RAM diag */
154#define ASI_QUAD_LDD_PHYS 0x34 /* (III+) PADDR, qword load */
155#define ASI_WCACHE_VALID_BITS 0x38 /* (III) WCache Valid Bits diag */
156#define ASI_WCACHE_DATA 0x39 /* (III) WCache data RAM diag */
157#define ASI_WCACHE_TAG 0x3a /* (III) WCache tag RAM diag */
158#define ASI_WCACHE_SNOOP_TAG 0x3b /* (III) WCache snoop tag RAM diag */
159#define ASI_QUAD_LDD_PHYS_L 0x3c /* (III+) PADDR, qw-load, l-endian */
160#define ASI_SRAM_FAST_INIT 0x40 /* (III+) Fast SRAM init */
161#define ASI_CORE_AVAILABLE 0x41 /* (CMT) LP Available */
162#define ASI_CORE_ENABLE_STAT 0x41 /* (CMT) LP Enable Status */
163#define ASI_CORE_ENABLE 0x41 /* (CMT) LP Enable RW */
164#define ASI_XIR_STEERING 0x41 /* (CMT) XIR Steering RW */
165#define ASI_CORE_RUNNING_RW 0x41 /* (CMT) LP Running RW */
166#define ASI_CORE_RUNNING_W1S 0x41 /* (CMT) LP Running Write-One Set */
167#define ASI_CORE_RUNNING_W1C 0x41 /* (CMT) LP Running Write-One Clr */
168#define ASI_CORE_RUNNING_STAT 0x41 /* (CMT) LP Running Status */
169#define ASI_CMT_ERROR_STEERING 0x41 /* (CMT) Error Steering RW */
170#define ASI_DCACHE_INVALIDATE 0x42 /* (III) DCache Invalidate diag */
171#define ASI_DCACHE_UTAG 0x43 /* (III) DCache uTag diag */
172#define ASI_DCACHE_SNOOP_TAG 0x44 /* (III) DCache snoop tag RAM diag */
173#define ASI_LSU_CONTROL 0x45 /* Load-store control unit */
174#define ASI_DCU_CONTROL_REG 0x45 /* (III) DCache Unit Control reg */
175#define ASI_DCACHE_DATA 0x46 /* DCache data-ram diag access */
176#define ASI_DCACHE_TAG 0x47 /* Dcache tag/valid ram diag access*/
177#define ASI_INTR_DISPATCH_STAT 0x48 /* IRQ vector dispatch status */
178#define ASI_INTR_RECEIVE 0x49 /* IRQ vector receive status */
179#define ASI_UPA_CONFIG 0x4a /* UPA config space */
180#define ASI_JBUS_CONFIG 0x4a /* (IIIi) JBUS Config Register */
181#define ASI_SAFARI_CONFIG 0x4a /* (III) Safari Config Register */
182#define ASI_SAFARI_ADDRESS 0x4a /* (III) Safari Address Register */
183#define ASI_ESTATE_ERROR_EN 0x4b /* E-cache error enable space */
184#define ASI_AFSR 0x4c /* Async fault status register */
185#define ASI_AFAR 0x4d /* Async fault address register */
186#define ASI_EC_TAG_DATA 0x4e /* E-cache tag/valid ram diag acc */
187#define ASI_IMMU 0x50 /* Insn-MMU main register space */
188#define ASI_IMMU_TSB_8KB_PTR 0x51 /* Insn-MMU 8KB TSB pointer reg */
189#define ASI_IMMU_TSB_64KB_PTR 0x52 /* Insn-MMU 64KB TSB pointer reg */
190#define ASI_ITLB_DATA_IN 0x54 /* Insn-MMU TLB data in reg */
191#define ASI_ITLB_DATA_ACCESS 0x55 /* Insn-MMU TLB data access reg */
192#define ASI_ITLB_TAG_READ 0x56 /* Insn-MMU TLB tag read reg */
193#define ASI_IMMU_DEMAP 0x57 /* Insn-MMU TLB demap */
194#define ASI_DMMU 0x58 /* Data-MMU main register space */
195#define ASI_DMMU_TSB_8KB_PTR 0x59 /* Data-MMU 8KB TSB pointer reg */
196#define ASI_DMMU_TSB_64KB_PTR 0x5a /* Data-MMU 16KB TSB pointer reg */
197#define ASI_DMMU_TSB_DIRECT_PTR 0x5b /* Data-MMU TSB direct pointer reg */
198#define ASI_DTLB_DATA_IN 0x5c /* Data-MMU TLB data in reg */
199#define ASI_DTLB_DATA_ACCESS 0x5d /* Data-MMU TLB data access reg */
200#define ASI_DTLB_TAG_READ 0x5e /* Data-MMU TLB tag read reg */
201#define ASI_DMMU_DEMAP 0x5f /* Data-MMU TLB demap */
202#define ASI_IIU_INST_TRAP 0x60 /* (III) Instruction Breakpoint */
203#define ASI_INTR_ID 0x63 /* (CMT) Interrupt ID register */
204#define ASI_CORE_ID 0x63 /* (CMT) LP ID register */
205#define ASI_CESR_ID 0x63 /* (CMT) CESR ID register */
206#define ASI_IC_INSTR 0x66 /* Insn cache instrucion ram diag */
207#define ASI_IC_TAG 0x67 /* Insn cache tag/valid ram diag */
208#define ASI_IC_STAG 0x68 /* (III) Insn cache snoop tag ram */
209#define ASI_IC_PRE_DECODE 0x6e /* Insn cache pre-decode ram diag */
210#define ASI_IC_NEXT_FIELD 0x6f /* Insn cache next-field ram diag */
211#define ASI_BRPRED_ARRAY 0x6f /* (III) Branch Prediction RAM diag*/
212#define ASI_BLK_AIUP 0x70 /* Primary, user, block load/store */
213#define ASI_BLK_AIUS 0x71 /* Secondary, user, block ld/st */
214#define ASI_MCU_CTRL_REG 0x72 /* (III) Memory controller regs */
215#define ASI_EC_DATA 0x74 /* (III) E-cache data staging reg */
216#define ASI_EC_CTRL 0x75 /* (III) E-cache control reg */
217#define ASI_EC_W 0x76 /* E-cache diag write access */
218#define ASI_UDB_ERROR_W 0x77 /* External UDB error regs W */
219#define ASI_UDB_CONTROL_W 0x77 /* External UDB control regs W */
220#define ASI_INTR_W 0x77 /* IRQ vector dispatch write */
221#define ASI_INTR_DATAN_W 0x77 /* (III) Out irq vector data reg N */
222#define ASI_INTR_DISPATCH_W 0x77 /* (III) Interrupt vector dispatch */
223#define ASI_BLK_AIUPL 0x78 /* Primary, user, little, blk ld/st*/
224#define ASI_BLK_AIUSL 0x79 /* Secondary, user, little, blk ld/st*/
225#define ASI_EC_R 0x7e /* E-cache diag read access */
226#define ASI_UDBH_ERROR_R 0x7f /* External UDB error regs rd hi */
227#define ASI_UDBL_ERROR_R 0x7f /* External UDB error regs rd low */
228#define ASI_UDBH_CONTROL_R 0x7f /* External UDB control regs rd hi */
229#define ASI_UDBL_CONTROL_R 0x7f /* External UDB control regs rd low*/
230#define ASI_INTR_R 0x7f /* IRQ vector dispatch read */
231#define ASI_INTR_DATAN_R 0x7f /* (III) In irq vector data reg N */
232#define ASI_PST8_P 0xc0 /* Primary, 8 8-bit, partial */
233#define ASI_PST8_S 0xc1 /* Secondary, 8 8-bit, partial */
234#define ASI_PST16_P 0xc2 /* Primary, 4 16-bit, partial */
235#define ASI_PST16_S 0xc3 /* Secondary, 4 16-bit, partial */
236#define ASI_PST32_P 0xc4 /* Primary, 2 32-bit, partial */
237#define ASI_PST32_S 0xc5 /* Secondary, 2 32-bit, partial */
238#define ASI_PST8_PL 0xc8 /* Primary, 8 8-bit, partial, L */
239#define ASI_PST8_SL 0xc9 /* Secondary, 8 8-bit, partial, L */
240#define ASI_PST16_PL 0xca /* Primary, 4 16-bit, partial, L */
241#define ASI_PST16_SL 0xcb /* Secondary, 4 16-bit, partial, L */
242#define ASI_PST32_PL 0xcc /* Primary, 2 32-bit, partial, L */
243#define ASI_PST32_SL 0xcd /* Secondary, 2 32-bit, partial, L */
244#define ASI_FL8_P 0xd0 /* Primary, 1 8-bit, fpu ld/st */
245#define ASI_FL8_S 0xd1 /* Secondary, 1 8-bit, fpu ld/st */
246#define ASI_FL16_P 0xd2 /* Primary, 1 16-bit, fpu ld/st */
247#define ASI_FL16_S 0xd3 /* Secondary, 1 16-bit, fpu ld/st */
248#define ASI_FL8_PL 0xd8 /* Primary, 1 8-bit, fpu ld/st, L */
249#define ASI_FL8_SL 0xd9 /* Secondary, 1 8-bit, fpu ld/st, L*/
250#define ASI_FL16_PL 0xda /* Primary, 1 16-bit, fpu ld/st, L */
251#define ASI_FL16_SL 0xdb /* Secondary, 1 16-bit, fpu ld/st,L*/
252#define ASI_BLK_COMMIT_P 0xe0 /* Primary, blk store commit */
253#define ASI_BLK_COMMIT_S 0xe1 /* Secondary, blk store commit */
254#define ASI_BLK_INIT_QUAD_LDD_P 0xe2 /* (NG) init-store, twin load,
255 * primary, implicit
256 */
257#define ASI_BLK_P 0xf0 /* Primary, blk ld/st */
258#define ASI_BLK_S 0xf1 /* Secondary, blk ld/st */
259#define ASI_BLK_PL 0xf8 /* Primary, blk ld/st, little */
260#define ASI_BLK_SL 0xf9 /* Secondary, blk ld/st, little */
261
262#endif /* _SPARC_ASI_H */
diff --git a/include/asm-sparc/asmmacro.h b/include/asm-sparc/asmmacro.h
deleted file mode 100644
index a619a4d97aa..00000000000
--- a/include/asm-sparc/asmmacro.h
+++ /dev/null
@@ -1,45 +0,0 @@
1/* asmmacro.h: Assembler macros.
2 *
3 * Copyright (C) 1996 David S. Miller (davem@caipfs.rutgers.edu)
4 */
5
6#ifndef _SPARC_ASMMACRO_H
7#define _SPARC_ASMMACRO_H
8
9#include <asm/btfixup.h>
10#include <asm/asi.h>
11
12#define GET_PROCESSOR4M_ID(reg) \
13 rd %tbr, %reg; \
14 srl %reg, 12, %reg; \
15 and %reg, 3, %reg;
16
17#define GET_PROCESSOR4D_ID(reg) \
18 lda [%g0] ASI_M_VIKING_TMP1, %reg;
19
20/* All trap entry points _must_ begin with this macro or else you
21 * lose. It makes sure the kernel has a proper window so that
22 * c-code can be called.
23 */
24#define SAVE_ALL_HEAD \
25 sethi %hi(trap_setup), %l4; \
26 jmpl %l4 + %lo(trap_setup), %l6;
27#define SAVE_ALL \
28 SAVE_ALL_HEAD \
29 nop;
30
31/* All traps low-level code here must end with this macro. */
32#define RESTORE_ALL b ret_trap_entry; clr %l6;
33
34/* sun4 probably wants half word accesses to ASI_SEGMAP, while sun4c+
35 likes byte accesses. These are to avoid ifdef mania. */
36
37#ifdef CONFIG_SUN4
38#define lduXa lduha
39#define stXa stha
40#else
41#define lduXa lduba
42#define stXa stba
43#endif
44
45#endif /* !(_SPARC_ASMMACRO_H) */
diff --git a/include/asm-sparc/atomic.h b/include/asm-sparc/atomic.h
deleted file mode 100644
index 66d8166ec1d..00000000000
--- a/include/asm-sparc/atomic.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_ATOMIC_H
2#define ___ASM_SPARC_ATOMIC_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/atomic_64.h>
5#else
6#include <asm-sparc/atomic_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/atomic_32.h b/include/asm-sparc/atomic_32.h
deleted file mode 100644
index 5c944b5a804..00000000000
--- a/include/asm-sparc/atomic_32.h
+++ /dev/null
@@ -1,165 +0,0 @@
1/* atomic.h: These still suck, but the I-cache hit rate is higher.
2 *
3 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 2000 Anton Blanchard (anton@linuxcare.com.au)
5 * Copyright (C) 2007 Kyle McMartin (kyle@parisc-linux.org)
6 *
7 * Additions by Keith M Wesolowski (wesolows@foobazco.org) based
8 * on asm-parisc/atomic.h Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>.
9 */
10
11#ifndef __ARCH_SPARC_ATOMIC__
12#define __ARCH_SPARC_ATOMIC__
13
14#include <linux/types.h>
15
16typedef struct { volatile int counter; } atomic_t;
17
18#ifdef __KERNEL__
19
20#define ATOMIC_INIT(i) { (i) }
21
22extern int __atomic_add_return(int, atomic_t *);
23extern int atomic_cmpxchg(atomic_t *, int, int);
24#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
25extern int atomic_add_unless(atomic_t *, int, int);
26extern void atomic_set(atomic_t *, int);
27
28#define atomic_read(v) ((v)->counter)
29
30#define atomic_add(i, v) ((void)__atomic_add_return( (int)(i), (v)))
31#define atomic_sub(i, v) ((void)__atomic_add_return(-(int)(i), (v)))
32#define atomic_inc(v) ((void)__atomic_add_return( 1, (v)))
33#define atomic_dec(v) ((void)__atomic_add_return( -1, (v)))
34
35#define atomic_add_return(i, v) (__atomic_add_return( (int)(i), (v)))
36#define atomic_sub_return(i, v) (__atomic_add_return(-(int)(i), (v)))
37#define atomic_inc_return(v) (__atomic_add_return( 1, (v)))
38#define atomic_dec_return(v) (__atomic_add_return( -1, (v)))
39
40#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
41
42/*
43 * atomic_inc_and_test - increment and test
44 * @v: pointer of type atomic_t
45 *
46 * Atomically increments @v by 1
47 * and returns true if the result is zero, or false for all
48 * other cases.
49 */
50#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
51
52#define atomic_dec_and_test(v) (atomic_dec_return(v) == 0)
53#define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)
54
55#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
56
57/* This is the old 24-bit implementation. It's still used internally
58 * by some sparc-specific code, notably the semaphore implementation.
59 */
60typedef struct { volatile int counter; } atomic24_t;
61
62#ifndef CONFIG_SMP
63
64#define ATOMIC24_INIT(i) { (i) }
65#define atomic24_read(v) ((v)->counter)
66#define atomic24_set(v, i) (((v)->counter) = i)
67
68#else
69/* We do the bulk of the actual work out of line in two common
70 * routines in assembler, see arch/sparc/lib/atomic.S for the
71 * "fun" details.
72 *
73 * For SMP the trick is you embed the spin lock byte within
74 * the word, use the low byte so signedness is easily retained
75 * via a quick arithmetic shift. It looks like this:
76 *
77 * ----------------------------------------
78 * | signed 24-bit counter value | lock | atomic_t
79 * ----------------------------------------
80 * 31 8 7 0
81 */
82
83#define ATOMIC24_INIT(i) { ((i) << 8) }
84
85static inline int atomic24_read(const atomic24_t *v)
86{
87 int ret = v->counter;
88
89 while(ret & 0xff)
90 ret = v->counter;
91
92 return ret >> 8;
93}
94
95#define atomic24_set(v, i) (((v)->counter) = ((i) << 8))
96#endif
97
98static inline int __atomic24_add(int i, atomic24_t *v)
99{
100 register volatile int *ptr asm("g1");
101 register int increment asm("g2");
102 register int tmp1 asm("g3");
103 register int tmp2 asm("g4");
104 register int tmp3 asm("g7");
105
106 ptr = &v->counter;
107 increment = i;
108
109 __asm__ __volatile__(
110 "mov %%o7, %%g4\n\t"
111 "call ___atomic24_add\n\t"
112 " add %%o7, 8, %%o7\n"
113 : "=&r" (increment), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3)
114 : "0" (increment), "r" (ptr)
115 : "memory", "cc");
116
117 return increment;
118}
119
120static inline int __atomic24_sub(int i, atomic24_t *v)
121{
122 register volatile int *ptr asm("g1");
123 register int increment asm("g2");
124 register int tmp1 asm("g3");
125 register int tmp2 asm("g4");
126 register int tmp3 asm("g7");
127
128 ptr = &v->counter;
129 increment = i;
130
131 __asm__ __volatile__(
132 "mov %%o7, %%g4\n\t"
133 "call ___atomic24_sub\n\t"
134 " add %%o7, 8, %%o7\n"
135 : "=&r" (increment), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3)
136 : "0" (increment), "r" (ptr)
137 : "memory", "cc");
138
139 return increment;
140}
141
142#define atomic24_add(i, v) ((void)__atomic24_add((i), (v)))
143#define atomic24_sub(i, v) ((void)__atomic24_sub((i), (v)))
144
145#define atomic24_dec_return(v) __atomic24_sub(1, (v))
146#define atomic24_inc_return(v) __atomic24_add(1, (v))
147
148#define atomic24_sub_and_test(i, v) (__atomic24_sub((i), (v)) == 0)
149#define atomic24_dec_and_test(v) (__atomic24_sub(1, (v)) == 0)
150
151#define atomic24_inc(v) ((void)__atomic24_add(1, (v)))
152#define atomic24_dec(v) ((void)__atomic24_sub(1, (v)))
153
154#define atomic24_add_negative(i, v) (__atomic24_add((i), (v)) < 0)
155
156/* Atomic operations are already serializing */
157#define smp_mb__before_atomic_dec() barrier()
158#define smp_mb__after_atomic_dec() barrier()
159#define smp_mb__before_atomic_inc() barrier()
160#define smp_mb__after_atomic_inc() barrier()
161
162#endif /* !(__KERNEL__) */
163
164#include <asm-generic/atomic.h>
165#endif /* !(__ARCH_SPARC_ATOMIC__) */
diff --git a/include/asm-sparc/atomic_64.h b/include/asm-sparc/atomic_64.h
deleted file mode 100644
index 2c71ec4a3b1..00000000000
--- a/include/asm-sparc/atomic_64.h
+++ /dev/null
@@ -1,128 +0,0 @@
1/* atomic.h: Thankfully the V9 is at least reasonable for this
2 * stuff.
3 *
4 * Copyright (C) 1996, 1997, 2000 David S. Miller (davem@redhat.com)
5 */
6
7#ifndef __ARCH_SPARC64_ATOMIC__
8#define __ARCH_SPARC64_ATOMIC__
9
10#include <linux/types.h>
11#include <asm/system.h>
12
13typedef struct { volatile int counter; } atomic_t;
14typedef struct { volatile __s64 counter; } atomic64_t;
15
16#define ATOMIC_INIT(i) { (i) }
17#define ATOMIC64_INIT(i) { (i) }
18
19#define atomic_read(v) ((v)->counter)
20#define atomic64_read(v) ((v)->counter)
21
22#define atomic_set(v, i) (((v)->counter) = i)
23#define atomic64_set(v, i) (((v)->counter) = i)
24
25extern void atomic_add(int, atomic_t *);
26extern void atomic64_add(int, atomic64_t *);
27extern void atomic_sub(int, atomic_t *);
28extern void atomic64_sub(int, atomic64_t *);
29
30extern int atomic_add_ret(int, atomic_t *);
31extern int atomic64_add_ret(int, atomic64_t *);
32extern int atomic_sub_ret(int, atomic_t *);
33extern int atomic64_sub_ret(int, atomic64_t *);
34
35#define atomic_dec_return(v) atomic_sub_ret(1, v)
36#define atomic64_dec_return(v) atomic64_sub_ret(1, v)
37
38#define atomic_inc_return(v) atomic_add_ret(1, v)
39#define atomic64_inc_return(v) atomic64_add_ret(1, v)
40
41#define atomic_sub_return(i, v) atomic_sub_ret(i, v)
42#define atomic64_sub_return(i, v) atomic64_sub_ret(i, v)
43
44#define atomic_add_return(i, v) atomic_add_ret(i, v)
45#define atomic64_add_return(i, v) atomic64_add_ret(i, v)
46
47/*
48 * atomic_inc_and_test - increment and test
49 * @v: pointer of type atomic_t
50 *
51 * Atomically increments @v by 1
52 * and returns true if the result is zero, or false for all
53 * other cases.
54 */
55#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
56#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
57
58#define atomic_sub_and_test(i, v) (atomic_sub_ret(i, v) == 0)
59#define atomic64_sub_and_test(i, v) (atomic64_sub_ret(i, v) == 0)
60
61#define atomic_dec_and_test(v) (atomic_sub_ret(1, v) == 0)
62#define atomic64_dec_and_test(v) (atomic64_sub_ret(1, v) == 0)
63
64#define atomic_inc(v) atomic_add(1, v)
65#define atomic64_inc(v) atomic64_add(1, v)
66
67#define atomic_dec(v) atomic_sub(1, v)
68#define atomic64_dec(v) atomic64_sub(1, v)
69
70#define atomic_add_negative(i, v) (atomic_add_ret(i, v) < 0)
71#define atomic64_add_negative(i, v) (atomic64_add_ret(i, v) < 0)
72
73#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
74#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
75
76static inline int atomic_add_unless(atomic_t *v, int a, int u)
77{
78 int c, old;
79 c = atomic_read(v);
80 for (;;) {
81 if (unlikely(c == (u)))
82 break;
83 old = atomic_cmpxchg((v), c, c + (a));
84 if (likely(old == c))
85 break;
86 c = old;
87 }
88 return c != (u);
89}
90
91#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
92
93#define atomic64_cmpxchg(v, o, n) \
94 ((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n)))
95#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
96
97static inline int atomic64_add_unless(atomic64_t *v, long a, long u)
98{
99 long c, old;
100 c = atomic64_read(v);
101 for (;;) {
102 if (unlikely(c == (u)))
103 break;
104 old = atomic64_cmpxchg((v), c, c + (a));
105 if (likely(old == c))
106 break;
107 c = old;
108 }
109 return c != (u);
110}
111
112#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
113
114/* Atomic operations are already serializing */
115#ifdef CONFIG_SMP
116#define smp_mb__before_atomic_dec() membar_storeload_loadload();
117#define smp_mb__after_atomic_dec() membar_storeload_storestore();
118#define smp_mb__before_atomic_inc() membar_storeload_loadload();
119#define smp_mb__after_atomic_inc() membar_storeload_storestore();
120#else
121#define smp_mb__before_atomic_dec() barrier()
122#define smp_mb__after_atomic_dec() barrier()
123#define smp_mb__before_atomic_inc() barrier()
124#define smp_mb__after_atomic_inc() barrier()
125#endif
126
127#include <asm-generic/atomic.h>
128#endif /* !(__ARCH_SPARC64_ATOMIC__) */
diff --git a/include/asm-sparc/auxio.h b/include/asm-sparc/auxio.h
deleted file mode 100644
index 24c6f3c0f57..00000000000
--- a/include/asm-sparc/auxio.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_AUXIO_H
2#define ___ASM_SPARC_AUXIO_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/auxio_64.h>
5#else
6#include <asm-sparc/auxio_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/auxio_32.h b/include/asm-sparc/auxio_32.h
deleted file mode 100644
index 4db8f23db20..00000000000
--- a/include/asm-sparc/auxio_32.h
+++ /dev/null
@@ -1,89 +0,0 @@
1/*
2 * auxio.h: Definitions and code for the Auxiliary I/O register.
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 */
6#ifndef _SPARC_AUXIO_H
7#define _SPARC_AUXIO_H
8
9#include <asm/system.h>
10#include <asm/vaddrs.h>
11
12/* This register is an unsigned char in IO space. It does two things.
13 * First, it is used to control the front panel LED light on machines
14 * that have it (good for testing entry points to trap handlers and irq's)
15 * Secondly, it controls various floppy drive parameters.
16 */
17#define AUXIO_ORMEIN 0xf0 /* All writes must set these bits. */
18#define AUXIO_ORMEIN4M 0xc0 /* sun4m - All writes must set these bits. */
19#define AUXIO_FLPY_DENS 0x20 /* Floppy density, high if set. Read only. */
20#define AUXIO_FLPY_DCHG 0x10 /* A disk change occurred. Read only. */
21#define AUXIO_EDGE_ON 0x10 /* sun4m - On means Jumper block is in. */
22#define AUXIO_FLPY_DSEL 0x08 /* Drive select/start-motor. Write only. */
23#define AUXIO_LINK_TEST 0x08 /* sun4m - On means TPE Carrier detect. */
24
25/* Set the following to one, then zero, after doing a pseudo DMA transfer. */
26#define AUXIO_FLPY_TCNT 0x04 /* Floppy terminal count. Write only. */
27
28/* Set the following to zero to eject the floppy. */
29#define AUXIO_FLPY_EJCT 0x02 /* Eject floppy disk. Write only. */
30#define AUXIO_LED 0x01 /* On if set, off if unset. Read/Write */
31
32#ifndef __ASSEMBLY__
33
34/*
35 * NOTE: these routines are implementation dependent--
36 * understand the hardware you are querying!
37 */
38extern void set_auxio(unsigned char bits_on, unsigned char bits_off);
39extern unsigned char get_auxio(void); /* .../asm-sparc/floppy.h */
40
41/*
42 * The following routines are provided for driver-compatibility
43 * with sparc64 (primarily sunlance.c)
44 */
45
46#define AUXIO_LTE_ON 1
47#define AUXIO_LTE_OFF 0
48
49/* auxio_set_lte - Set Link Test Enable (TPE Link Detect)
50 *
51 * on - AUXIO_LTE_ON or AUXIO_LTE_OFF
52 */
53#define auxio_set_lte(on) \
54do { \
55 if(on) { \
56 set_auxio(AUXIO_LINK_TEST, 0); \
57 } else { \
58 set_auxio(0, AUXIO_LINK_TEST); \
59 } \
60} while (0)
61
62#define AUXIO_LED_ON 1
63#define AUXIO_LED_OFF 0
64
65/* auxio_set_led - Set system front panel LED
66 *
67 * on - AUXIO_LED_ON or AUXIO_LED_OFF
68 */
69#define auxio_set_led(on) \
70do { \
71 if(on) { \
72 set_auxio(AUXIO_LED, 0); \
73 } else { \
74 set_auxio(0, AUXIO_LED); \
75 } \
76} while (0)
77
78#endif /* !(__ASSEMBLY__) */
79
80
81/* AUXIO2 (Power Off Control) */
82extern __volatile__ unsigned char * auxio_power_register;
83
84#define AUXIO_POWER_DETECT_FAILURE 32
85#define AUXIO_POWER_CLEAR_FAILURE 2
86#define AUXIO_POWER_OFF 1
87
88
89#endif /* !(_SPARC_AUXIO_H) */
diff --git a/include/asm-sparc/auxio_64.h b/include/asm-sparc/auxio_64.h
deleted file mode 100644
index f61cd1e3e39..00000000000
--- a/include/asm-sparc/auxio_64.h
+++ /dev/null
@@ -1,100 +0,0 @@
1/*
2 * auxio.h: Definitions and code for the Auxiliary I/O registers.
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 *
6 * Refactoring for unified NCR/PCIO support 2002 Eric Brower (ebrower@usa.net)
7 */
8#ifndef _SPARC64_AUXIO_H
9#define _SPARC64_AUXIO_H
10
11/* AUXIO implementations:
12 * sbus-based NCR89C105 "Slavio"
13 * LED/Floppy (AUX1) register
14 * Power (AUX2) register
15 *
16 * ebus-based auxio on PCIO
17 * LED Auxio Register
18 * Power Auxio Register
19 *
20 * Register definitions from NCR _NCR89C105 Chip Specification_
21 *
22 * SLAVIO AUX1 @ 0x1900000
23 * -------------------------------------------------
24 * | (R) | (R) | D | (R) | E | M | T | L |
25 * -------------------------------------------------
26 * (R) - bit 7:6,4 are reserved and should be masked in s/w
27 * D - Floppy Density Sense (1=high density) R/O
28 * E - Link Test Enable, directly reflected on AT&T 7213 LTE pin
29 * M - Monitor/Mouse Mux, directly reflected on MON_MSE_MUX pin
30 * T - Terminal Count: sends TC pulse to 82077 floppy controller
31 * L - System LED on front panel (0=off, 1=on)
32 */
33#define AUXIO_AUX1_MASK 0xc0 /* Mask bits */
34#define AUXIO_AUX1_FDENS 0x20 /* Floppy Density Sense */
35#define AUXIO_AUX1_LTE 0x08 /* Link Test Enable */
36#define AUXIO_AUX1_MMUX 0x04 /* Monitor/Mouse Mux */
37#define AUXIO_AUX1_FTCNT 0x02 /* Terminal Count, */
38#define AUXIO_AUX1_LED 0x01 /* System LED */
39
40/* SLAVIO AUX2 @ 0x1910000
41 * -------------------------------------------------
42 * | (R) | (R) | D | (R) | (R) | (R) | C | F |
43 * -------------------------------------------------
44 * (R) - bits 7:6,4:2 are reserved and should be masked in s/w
45 * D - Power Failure Detect (1=power fail)
46 * C - Clear Power Failure Detect Int (1=clear)
47 * F - Power Off (1=power off)
48 */
49#define AUXIO_AUX2_MASK 0xdc /* Mask Bits */
50#define AUXIO_AUX2_PFAILDET 0x20 /* Power Fail Detect */
51#define AUXIO_AUX2_PFAILCLR 0x02 /* Clear Pwr Fail Det Intr */
52#define AUXIO_AUX2_PWR_OFF 0x01 /* Power Off */
53
54/* Register definitions from Sun Microsystems _PCIO_ p/n 802-7837
55 *
56 * PCIO LED Auxio @ 0x726000
57 * -------------------------------------------------
58 * | 31:1 Unused | LED |
59 * -------------------------------------------------
60 * Bits 31:1 unused
61 * LED - System LED on front panel (0=off, 1=on)
62 */
63#define AUXIO_PCIO_LED 0x01 /* System LED */
64
65/* PCIO Power Auxio @ 0x724000
66 * -------------------------------------------------
67 * | 31:2 Unused | CPO | SPO |
68 * -------------------------------------------------
69 * Bits 31:2 unused
70 * CPO - Courtesy Power Off (1=off)
71 * SPO - System Power Off (1=off)
72 */
73#define AUXIO_PCIO_CPWR_OFF 0x02 /* Courtesy Power Off */
74#define AUXIO_PCIO_SPWR_OFF 0x01 /* System Power Off */
75
76#ifndef __ASSEMBLY__
77
78extern void __iomem *auxio_register;
79
80#define AUXIO_LTE_ON 1
81#define AUXIO_LTE_OFF 0
82
83/* auxio_set_lte - Set Link Test Enable (TPE Link Detect)
84 *
85 * on - AUXIO_LTE_ON or AUXIO_LTE_OFF
86 */
87extern void auxio_set_lte(int on);
88
89#define AUXIO_LED_ON 1
90#define AUXIO_LED_OFF 0
91
92/* auxio_set_led - Set system front panel LED
93 *
94 * on - AUXIO_LED_ON or AUXIO_LED_OFF
95 */
96extern void auxio_set_led(int on);
97
98#endif /* ifndef __ASSEMBLY__ */
99
100#endif /* !(_SPARC64_AUXIO_H) */
diff --git a/include/asm-sparc/auxvec.h b/include/asm-sparc/auxvec.h
deleted file mode 100644
index ad6f360261f..00000000000
--- a/include/asm-sparc/auxvec.h
+++ /dev/null
@@ -1,4 +0,0 @@
1#ifndef __ASMSPARC_AUXVEC_H
2#define __ASMSPARC_AUXVEC_H
3
4#endif /* !(__ASMSPARC_AUXVEC_H) */
diff --git a/include/asm-sparc/backoff.h b/include/asm-sparc/backoff.h
deleted file mode 100644
index fa1fdf67e35..00000000000
--- a/include/asm-sparc/backoff.h
+++ /dev/null
@@ -1,31 +0,0 @@
1#ifndef _SPARC64_BACKOFF_H
2#define _SPARC64_BACKOFF_H
3
4#define BACKOFF_LIMIT (4 * 1024)
5
6#ifdef CONFIG_SMP
7
8#define BACKOFF_SETUP(reg) \
9 mov 1, reg
10
11#define BACKOFF_SPIN(reg, tmp, label) \
12 mov reg, tmp; \
1388: brnz,pt tmp, 88b; \
14 sub tmp, 1, tmp; \
15 set BACKOFF_LIMIT, tmp; \
16 cmp reg, tmp; \
17 bg,pn %xcc, label; \
18 nop; \
19 ba,pt %xcc, label; \
20 sllx reg, 1, reg;
21
22#else
23
24#define BACKOFF_SETUP(reg)
25#define BACKOFF_SPIN(reg, tmp, label) \
26 ba,pt %xcc, label; \
27 nop;
28
29#endif
30
31#endif /* _SPARC64_BACKOFF_H */
diff --git a/include/asm-sparc/bbc.h b/include/asm-sparc/bbc.h
deleted file mode 100644
index 423a85800aa..00000000000
--- a/include/asm-sparc/bbc.h
+++ /dev/null
@@ -1,225 +0,0 @@
1/*
2 * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
3 * systems.
4 *
5 * Copyright (C) 2000 David S. Miller (davem@redhat.com)
6 */
7
8#ifndef _SPARC64_BBC_H
9#define _SPARC64_BBC_H
10
11/* Register sizes are indicated by "B" (Byte, 1-byte),
12 * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
13 * "Q" (Quad, 8 bytes) inside brackets.
14 */
15
16#define BBC_AID 0x00 /* [B] Agent ID */
17#define BBC_DEVP 0x01 /* [B] Device Present */
18#define BBC_ARB 0x02 /* [B] Arbitration */
19#define BBC_QUIESCE 0x03 /* [B] Quiesce */
20#define BBC_WDACTION 0x04 /* [B] Watchdog Action */
21#define BBC_SPG 0x06 /* [B] Soft POR Gen */
22#define BBC_SXG 0x07 /* [B] Soft XIR Gen */
23#define BBC_PSRC 0x08 /* [W] POR Source */
24#define BBC_XSRC 0x0c /* [B] XIR Source */
25#define BBC_CSC 0x0d /* [B] Clock Synthesizers Control*/
26#define BBC_ES_CTRL 0x0e /* [H] Energy Star Control */
27#define BBC_ES_ACT 0x10 /* [W] E* Assert Change Time */
28#define BBC_ES_DACT 0x14 /* [B] E* De-Assert Change Time */
29#define BBC_ES_DABT 0x15 /* [B] E* De-Assert Bypass Time */
30#define BBC_ES_ABT 0x16 /* [H] E* Assert Bypass Time */
31#define BBC_ES_PST 0x18 /* [W] E* PLL Settle Time */
32#define BBC_ES_FSL 0x1c /* [W] E* Frequency Switch Latency*/
33#define BBC_EBUST 0x20 /* [Q] EBUS Timing */
34#define BBC_JTAG_CMD 0x28 /* [W] JTAG+ Command */
35#define BBC_JTAG_CTRL 0x2c /* [B] JTAG+ Control */
36#define BBC_I2C_SEL 0x2d /* [B] I2C Selection */
37#define BBC_I2C_0_S1 0x2e /* [B] I2C ctrlr-0 reg S1 */
38#define BBC_I2C_0_S0 0x2f /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
39#define BBC_I2C_1_S1 0x30 /* [B] I2C ctrlr-1 reg S1 */
40#define BBC_I2C_1_S0 0x31 /* [B] I2C ctrlr-1 regs S0,S0',S2,S3*/
41#define BBC_KBD_BEEP 0x32 /* [B] Keyboard Beep */
42#define BBC_KBD_BCNT 0x34 /* [W] Keyboard Beep Counter */
43
44#define BBC_REGS_SIZE 0x40
45
46/* There is a 2K scratch ram area at offset 0x80000 but I doubt
47 * we will use it for anything.
48 */
49
50/* Agent ID register. This register shows the Safari Agent ID
51 * for the processors. The value returned depends upon which
52 * cpu is reading the register.
53 */
54#define BBC_AID_ID 0x07 /* Safari ID */
55#define BBC_AID_RESV 0xf8 /* Reserved */
56
57/* Device Present register. One can determine which cpus are actually
58 * present in the machine by interrogating this register.
59 */
60#define BBC_DEVP_CPU0 0x01 /* Processor 0 present */
61#define BBC_DEVP_CPU1 0x02 /* Processor 1 present */
62#define BBC_DEVP_CPU2 0x04 /* Processor 2 present */
63#define BBC_DEVP_CPU3 0x08 /* Processor 3 present */
64#define BBC_DEVP_RESV 0xf0 /* Reserved */
65
66/* Arbitration register. This register is used to block access to
67 * the BBC from a particular cpu.
68 */
69#define BBC_ARB_CPU0 0x01 /* Enable cpu 0 BBC arbitratrion */
70#define BBC_ARB_CPU1 0x02 /* Enable cpu 1 BBC arbitratrion */
71#define BBC_ARB_CPU2 0x04 /* Enable cpu 2 BBC arbitratrion */
72#define BBC_ARB_CPU3 0x08 /* Enable cpu 3 BBC arbitratrion */
73#define BBC_ARB_RESV 0xf0 /* Reserved */
74
75/* Quiesce register. Bus and BBC segments for cpus can be disabled
76 * with this register, ie. for hot plugging.
77 */
78#define BBC_QUIESCE_S02 0x01 /* Quiesce Safari segment for cpu 0 and 2 */
79#define BBC_QUIESCE_S13 0x02 /* Quiesce Safari segment for cpu 1 and 3 */
80#define BBC_QUIESCE_B02 0x04 /* Quiesce BBC segment for cpu 0 and 2 */
81#define BBC_QUIESCE_B13 0x08 /* Quiesce BBC segment for cpu 1 and 3 */
82#define BBC_QUIESCE_FD0 0x10 /* Disable Fatal_Error[0] reporting */
83#define BBC_QUIESCE_FD1 0x20 /* Disable Fatal_Error[1] reporting */
84#define BBC_QUIESCE_FD2 0x40 /* Disable Fatal_Error[2] reporting */
85#define BBC_QUIESCE_FD3 0x80 /* Disable Fatal_Error[3] reporting */
86
87/* Watchdog Action register. When the watchdog device timer expires
88 * a line is enabled to the BBC. The action BBC takes when this line
89 * is asserted can be controlled by this regiser.
90 */
91#define BBC_WDACTION_RST 0x01 /* When set, watchdog causes system reset.
92 * When clear, BBC ignores watchdog signal.
93 */
94#define BBC_WDACTION_RESV 0xfe /* Reserved */
95
96/* Soft_POR_GEN register. The POR (Power On Reset) signal may be asserted
97 * for specific processors or all processors via this register.
98 */
99#define BBC_SPG_CPU0 0x01 /* Assert POR for processor 0 */
100#define BBC_SPG_CPU1 0x02 /* Assert POR for processor 1 */
101#define BBC_SPG_CPU2 0x04 /* Assert POR for processor 2 */
102#define BBC_SPG_CPU3 0x08 /* Assert POR for processor 3 */
103#define BBC_SPG_CPUALL 0x10 /* Reset all processors and reset
104 * the entire system.
105 */
106#define BBC_SPG_RESV 0xe0 /* Reserved */
107
108/* Soft_XIR_GEN register. The XIR (eXternally Initiated Reset) signal
109 * may be asserted to specific processors via this register.
110 */
111#define BBC_SXG_CPU0 0x01 /* Assert XIR for processor 0 */
112#define BBC_SXG_CPU1 0x02 /* Assert XIR for processor 1 */
113#define BBC_SXG_CPU2 0x04 /* Assert XIR for processor 2 */
114#define BBC_SXG_CPU3 0x08 /* Assert XIR for processor 3 */
115#define BBC_SXG_RESV 0xf0 /* Reserved */
116
117/* POR Source register. One may identify the cause of the most recent
118 * reset by reading this register.
119 */
120#define BBC_PSRC_SPG0 0x0001 /* CPU 0 reset via BBC_SPG register */
121#define BBC_PSRC_SPG1 0x0002 /* CPU 1 reset via BBC_SPG register */
122#define BBC_PSRC_SPG2 0x0004 /* CPU 2 reset via BBC_SPG register */
123#define BBC_PSRC_SPG3 0x0008 /* CPU 3 reset via BBC_SPG register */
124#define BBC_PSRC_SPGSYS 0x0010 /* System reset via BBC_SPG register */
125#define BBC_PSRC_JTAG 0x0020 /* System reset via JTAG+ */
126#define BBC_PSRC_BUTTON 0x0040 /* System reset via push-button dongle */
127#define BBC_PSRC_PWRUP 0x0080 /* System reset via power-up */
128#define BBC_PSRC_FE0 0x0100 /* CPU 0 reported Fatal_Error */
129#define BBC_PSRC_FE1 0x0200 /* CPU 1 reported Fatal_Error */
130#define BBC_PSRC_FE2 0x0400 /* CPU 2 reported Fatal_Error */
131#define BBC_PSRC_FE3 0x0800 /* CPU 3 reported Fatal_Error */
132#define BBC_PSRC_FE4 0x1000 /* Schizo reported Fatal_Error */
133#define BBC_PSRC_FE5 0x2000 /* Safari device 5 reported Fatal_Error */
134#define BBC_PSRC_FE6 0x4000 /* CPMS reported Fatal_Error */
135#define BBC_PSRC_SYNTH 0x8000 /* System reset when on-board clock synthesizers
136 * were updated.
137 */
138#define BBC_PSRC_WDT 0x10000 /* System reset via Super I/O watchdog */
139#define BBC_PSRC_RSC 0x20000 /* System reset via RSC remote monitoring
140 * device
141 */
142
143/* XIR Source register. The source of an XIR event sent to a processor may
144 * be determined via this register.
145 */
146#define BBC_XSRC_SXG0 0x01 /* CPU 0 received XIR via Soft_XIR_GEN reg */
147#define BBC_XSRC_SXG1 0x02 /* CPU 1 received XIR via Soft_XIR_GEN reg */
148#define BBC_XSRC_SXG2 0x04 /* CPU 2 received XIR via Soft_XIR_GEN reg */
149#define BBC_XSRC_SXG3 0x08 /* CPU 3 received XIR via Soft_XIR_GEN reg */
150#define BBC_XSRC_JTAG 0x10 /* All CPUs received XIR via JTAG+ */
151#define BBC_XSRC_W_OR_B 0x20 /* All CPUs received XIR either because:
152 * a) Super I/O watchdog fired, or
153 * b) XIR push button was activated
154 */
155#define BBC_XSRC_RESV 0xc0 /* Reserved */
156
157/* Clock Synthesizers Control register. This register provides the big-bang
158 * programming interface to the two clock synthesizers of the machine.
159 */
160#define BBC_CSC_SLOAD 0x01 /* Directly connected to S_LOAD pins */
161#define BBC_CSC_SDATA 0x02 /* Directly connected to S_DATA pins */
162#define BBC_CSC_SCLOCK 0x04 /* Directly connected to S_CLOCK pins */
163#define BBC_CSC_RESV 0x78 /* Reserved */
164#define BBC_CSC_RST 0x80 /* Generate system reset when S_LOAD==1 */
165
166/* Energy Star Control register. This register is used to generate the
167 * clock frequency change trigger to the main system devices (Schizo and
168 * the processors). The transition occurs when bits in this register
169 * go from 0 to 1, only one bit must be set at once else no action
170 * occurs. Basically the sequence of events is:
171 * a) Choose new frequency: full, 1/2 or 1/32
172 * b) Program this desired frequency into the cpus and Schizo.
173 * c) Set the same value in this register.
174 * d) 16 system clocks later, clear this register.
175 */
176#define BBC_ES_CTRL_1_1 0x01 /* Full frequency */
177#define BBC_ES_CTRL_1_2 0x02 /* 1/2 frequency */
178#define BBC_ES_CTRL_1_32 0x20 /* 1/32 frequency */
179#define BBC_ES_RESV 0xdc /* Reserved */
180
181/* Energy Star Assert Change Time register. This determines the number
182 * of BBC clock cycles (which is half the system frequency) between
183 * the detection of FREEZE_ACK being asserted and the assertion of
184 * the CLK_CHANGE_L[2:0] signals.
185 */
186#define BBC_ES_ACT_VAL 0xff
187
188/* Energy Star Assert Bypass Time register. This determines the number
189 * of BBC clock cycles (which is half the system frequency) between
190 * the assertion of the CLK_CHANGE_L[2:0] signals and the assertion of
191 * the ESTAR_PLL_BYPASS signal.
192 */
193#define BBC_ES_ABT_VAL 0xffff
194
195/* Energy Star PLL Settle Time register. This determines the number of
196 * BBC clock cycles (which is half the system frequency) between the
197 * de-assertion of CLK_CHANGE_L[2:0] and the de-assertion of the FREEZE_L
198 * signal.
199 */
200#define BBC_ES_PST_VAL 0xffffffff
201
202/* Energy Star Frequency Switch Latency register. This is the number of
203 * BBC clocks between the de-assertion of CLK_CHANGE_L[2:0] and the first
204 * edge of the Safari clock at the new frequency.
205 */
206#define BBC_ES_FSL_VAL 0xffffffff
207
208/* Keyboard Beep control register. This is a simple enabler for the audio
209 * beep sound.
210 */
211#define BBC_KBD_BEEP_ENABLE 0x01 /* Enable beep */
212#define BBC_KBD_BEEP_RESV 0xfe /* Reserved */
213
214/* Keyboard Beep Counter register. There is a free-running counter inside
215 * the BBC which runs at half the system clock. The bit set in this register
216 * determines when the audio sound is generated. So for example if bit
217 * 10 is set, the audio beep will oscillate at 1/(2**12). The keyboard beep
218 * generator automatically selects a different bit to use if the system clock
219 * is changed via Energy Star.
220 */
221#define BBC_KBD_BCNT_BITS 0x0007fc00
222#define BBC_KBC_BCNT_RESV 0xfff803ff
223
224#endif /* _SPARC64_BBC_H */
225
diff --git a/include/asm-sparc/bitext.h b/include/asm-sparc/bitext.h
deleted file mode 100644
index 297b2f2fcb4..00000000000
--- a/include/asm-sparc/bitext.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * bitext.h: Bit string operations on the sparc, specific to architecture.
3 *
4 * Copyright 2002 Pete Zaitcev <zaitcev@yahoo.com>
5 */
6
7#ifndef _SPARC_BITEXT_H
8#define _SPARC_BITEXT_H
9
10#include <linux/spinlock.h>
11
12struct bit_map {
13 spinlock_t lock;
14 unsigned long *map;
15 int size;
16 int used;
17 int last_off;
18 int last_size;
19 int first_free;
20 int num_colors;
21};
22
23extern int bit_map_string_get(struct bit_map *t, int len, int align);
24extern void bit_map_clear(struct bit_map *t, int offset, int len);
25extern void bit_map_init(struct bit_map *t, unsigned long *map, int size);
26
27#endif /* defined(_SPARC_BITEXT_H) */
diff --git a/include/asm-sparc/bitops.h b/include/asm-sparc/bitops.h
deleted file mode 100644
index 1a2949d0193..00000000000
--- a/include/asm-sparc/bitops.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_BITOPS_H
2#define ___ASM_SPARC_BITOPS_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/bitops_64.h>
5#else
6#include <asm-sparc/bitops_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/bitops_32.h b/include/asm-sparc/bitops_32.h
deleted file mode 100644
index 68b98a7e645..00000000000
--- a/include/asm-sparc/bitops_32.h
+++ /dev/null
@@ -1,111 +0,0 @@
1/*
2 * bitops.h: Bit string operations on the Sparc.
3 *
4 * Copyright 1995 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright 1996 Eddie C. Dost (ecd@skynet.be)
6 * Copyright 2001 Anton Blanchard (anton@samba.org)
7 */
8
9#ifndef _SPARC_BITOPS_H
10#define _SPARC_BITOPS_H
11
12#include <linux/compiler.h>
13#include <asm/byteorder.h>
14
15#ifdef __KERNEL__
16
17#ifndef _LINUX_BITOPS_H
18#error only <linux/bitops.h> can be included directly
19#endif
20
21extern unsigned long ___set_bit(unsigned long *addr, unsigned long mask);
22extern unsigned long ___clear_bit(unsigned long *addr, unsigned long mask);
23extern unsigned long ___change_bit(unsigned long *addr, unsigned long mask);
24
25/*
26 * Set bit 'nr' in 32-bit quantity at address 'addr' where bit '0'
27 * is in the highest of the four bytes and bit '31' is the high bit
28 * within the first byte. Sparc is BIG-Endian. Unless noted otherwise
29 * all bit-ops return 0 if bit was previously clear and != 0 otherwise.
30 */
31static inline int test_and_set_bit(unsigned long nr, volatile unsigned long *addr)
32{
33 unsigned long *ADDR, mask;
34
35 ADDR = ((unsigned long *) addr) + (nr >> 5);
36 mask = 1 << (nr & 31);
37
38 return ___set_bit(ADDR, mask) != 0;
39}
40
41static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
42{
43 unsigned long *ADDR, mask;
44
45 ADDR = ((unsigned long *) addr) + (nr >> 5);
46 mask = 1 << (nr & 31);
47
48 (void) ___set_bit(ADDR, mask);
49}
50
51static inline int test_and_clear_bit(unsigned long nr, volatile unsigned long *addr)
52{
53 unsigned long *ADDR, mask;
54
55 ADDR = ((unsigned long *) addr) + (nr >> 5);
56 mask = 1 << (nr & 31);
57
58 return ___clear_bit(ADDR, mask) != 0;
59}
60
61static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
62{
63 unsigned long *ADDR, mask;
64
65 ADDR = ((unsigned long *) addr) + (nr >> 5);
66 mask = 1 << (nr & 31);
67
68 (void) ___clear_bit(ADDR, mask);
69}
70
71static inline int test_and_change_bit(unsigned long nr, volatile unsigned long *addr)
72{
73 unsigned long *ADDR, mask;
74
75 ADDR = ((unsigned long *) addr) + (nr >> 5);
76 mask = 1 << (nr & 31);
77
78 return ___change_bit(ADDR, mask) != 0;
79}
80
81static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
82{
83 unsigned long *ADDR, mask;
84
85 ADDR = ((unsigned long *) addr) + (nr >> 5);
86 mask = 1 << (nr & 31);
87
88 (void) ___change_bit(ADDR, mask);
89}
90
91#include <asm-generic/bitops/non-atomic.h>
92
93#define smp_mb__before_clear_bit() do { } while(0)
94#define smp_mb__after_clear_bit() do { } while(0)
95
96#include <asm-generic/bitops/ffz.h>
97#include <asm-generic/bitops/__ffs.h>
98#include <asm-generic/bitops/sched.h>
99#include <asm-generic/bitops/ffs.h>
100#include <asm-generic/bitops/fls.h>
101#include <asm-generic/bitops/fls64.h>
102#include <asm-generic/bitops/hweight.h>
103#include <asm-generic/bitops/lock.h>
104#include <asm-generic/bitops/find.h>
105#include <asm-generic/bitops/ext2-non-atomic.h>
106#include <asm-generic/bitops/ext2-atomic.h>
107#include <asm-generic/bitops/minix.h>
108
109#endif /* __KERNEL__ */
110
111#endif /* defined(_SPARC_BITOPS_H) */
diff --git a/include/asm-sparc/bitops_64.h b/include/asm-sparc/bitops_64.h
deleted file mode 100644
index bb87b808022..00000000000
--- a/include/asm-sparc/bitops_64.h
+++ /dev/null
@@ -1,107 +0,0 @@
1/*
2 * bitops.h: Bit string operations on the V9.
3 *
4 * Copyright 1996, 1997 David S. Miller (davem@caip.rutgers.edu)
5 */
6
7#ifndef _SPARC64_BITOPS_H
8#define _SPARC64_BITOPS_H
9
10#ifndef _LINUX_BITOPS_H
11#error only <linux/bitops.h> can be included directly
12#endif
13
14#include <linux/compiler.h>
15#include <asm/byteorder.h>
16
17extern int test_and_set_bit(unsigned long nr, volatile unsigned long *addr);
18extern int test_and_clear_bit(unsigned long nr, volatile unsigned long *addr);
19extern int test_and_change_bit(unsigned long nr, volatile unsigned long *addr);
20extern void set_bit(unsigned long nr, volatile unsigned long *addr);
21extern void clear_bit(unsigned long nr, volatile unsigned long *addr);
22extern void change_bit(unsigned long nr, volatile unsigned long *addr);
23
24#include <asm-generic/bitops/non-atomic.h>
25
26#ifdef CONFIG_SMP
27#define smp_mb__before_clear_bit() membar_storeload_loadload()
28#define smp_mb__after_clear_bit() membar_storeload_storestore()
29#else
30#define smp_mb__before_clear_bit() barrier()
31#define smp_mb__after_clear_bit() barrier()
32#endif
33
34#include <asm-generic/bitops/ffz.h>
35#include <asm-generic/bitops/__ffs.h>
36#include <asm-generic/bitops/fls.h>
37#include <asm-generic/bitops/__fls.h>
38#include <asm-generic/bitops/fls64.h>
39
40#ifdef __KERNEL__
41
42#include <asm-generic/bitops/sched.h>
43#include <asm-generic/bitops/ffs.h>
44
45/*
46 * hweightN: returns the hamming weight (i.e. the number
47 * of bits set) of a N-bit word
48 */
49
50#ifdef ULTRA_HAS_POPULATION_COUNT
51
52static inline unsigned int hweight64(unsigned long w)
53{
54 unsigned int res;
55
56 __asm__ ("popc %1,%0" : "=r" (res) : "r" (w));
57 return res;
58}
59
60static inline unsigned int hweight32(unsigned int w)
61{
62 unsigned int res;
63
64 __asm__ ("popc %1,%0" : "=r" (res) : "r" (w & 0xffffffff));
65 return res;
66}
67
68static inline unsigned int hweight16(unsigned int w)
69{
70 unsigned int res;
71
72 __asm__ ("popc %1,%0" : "=r" (res) : "r" (w & 0xffff));
73 return res;
74}
75
76static inline unsigned int hweight8(unsigned int w)
77{
78 unsigned int res;
79
80 __asm__ ("popc %1,%0" : "=r" (res) : "r" (w & 0xff));
81 return res;
82}
83
84#else
85
86#include <asm-generic/bitops/hweight.h>
87
88#endif
89#include <asm-generic/bitops/lock.h>
90#endif /* __KERNEL__ */
91
92#include <asm-generic/bitops/find.h>
93
94#ifdef __KERNEL__
95
96#include <asm-generic/bitops/ext2-non-atomic.h>
97
98#define ext2_set_bit_atomic(lock,nr,addr) \
99 test_and_set_bit((nr) ^ 0x38,(unsigned long *)(addr))
100#define ext2_clear_bit_atomic(lock,nr,addr) \
101 test_and_clear_bit((nr) ^ 0x38,(unsigned long *)(addr))
102
103#include <asm-generic/bitops/minix.h>
104
105#endif /* __KERNEL__ */
106
107#endif /* defined(_SPARC64_BITOPS_H) */
diff --git a/include/asm-sparc/bpp.h b/include/asm-sparc/bpp.h
deleted file mode 100644
index 31f515e499a..00000000000
--- a/include/asm-sparc/bpp.h
+++ /dev/null
@@ -1,73 +0,0 @@
1#ifndef _SPARC_BPP_H
2#define _SPARC_BPP_H
3
4/*
5 * Copyright (c) 1995 Picture Elements
6 * Stephen Williams
7 * Gus Baldauf
8 *
9 * Linux/SPARC port by Peter Zaitcev.
10 * Integration into SPARC tree by Tom Dyas.
11 */
12
13#include <linux/ioctl.h>
14
15/*
16 * This is a driver that supports IEEE Std 1284-1994 communications
17 * with compliant or compatible devices. It will use whatever features
18 * the device supports, prefering those that are typically faster.
19 *
20 * When the device is opened, it is left in COMPATIBILITY mode, and
21 * writes work like any printer device. The driver only attempt to
22 * negotiate 1284 modes when needed so that plugs can be pulled,
23 * switch boxes switched, etc., without disrupting things. It will
24 * also leave the device in compatibility mode when closed.
25 */
26
27
28
29/*
30 * This driver also supplies ioctls to manually manipulate the
31 * pins. This is great for testing devices, or writing code to deal
32 * with bizzarro-mode of the ACME Special TurboThingy Plus.
33 *
34 * NOTE: These ioctl currently do not interact well with
35 * read/write. Caveat emptor.
36 *
37 * PUT_PINS allows us to assign the sense of all the pins, including
38 * the data pins if being driven by the host. The GET_PINS returns the
39 * pins that the peripheral drives, including data if appropriate.
40 */
41
42# define BPP_PUT_PINS _IOW('B', 1, int)
43# define BPP_GET_PINS _IOR('B', 2, char) /* that's bogus - should've been _IO */
44# define BPP_PUT_DATA _IOW('B', 3, int)
45# define BPP_GET_DATA _IOR('B', 4, char) /* ditto */
46
47/*
48 * Set the data bus to input mode. Disengage the data bin driver and
49 * be prepared to read values from the peripheral. If the arg is 0,
50 * then revert the bus to output mode.
51 */
52# define BPP_SET_INPUT _IOW('B', 5, int)
53
54/*
55 * These bits apply to the PUT operation...
56 */
57# define BPP_PP_nStrobe 0x0001
58# define BPP_PP_nAutoFd 0x0002
59# define BPP_PP_nInit 0x0004
60# define BPP_PP_nSelectIn 0x0008
61
62/*
63 * These apply to the GET operation, which also reads the current value
64 * of the previously put values. A bit mask of these will be returned
65 * as a bit mask in the return code of the ioctl().
66 */
67# define BPP_GP_nAck 0x0100
68# define BPP_GP_Busy 0x0200
69# define BPP_GP_PError 0x0400
70# define BPP_GP_Select 0x0800
71# define BPP_GP_nFault 0x1000
72
73#endif
diff --git a/include/asm-sparc/btfixup.h b/include/asm-sparc/btfixup.h
deleted file mode 100644
index 08277e6fb4c..00000000000
--- a/include/asm-sparc/btfixup.h
+++ /dev/null
@@ -1,208 +0,0 @@
1/*
2 * asm-sparc/btfixup.h: Macros for boot time linking.
3 *
4 * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
5 */
6
7#ifndef _SPARC_BTFIXUP_H
8#define _SPARC_BTFIXUP_H
9
10#include <linux/init.h>
11
12#ifndef __ASSEMBLY__
13
14#ifdef MODULE
15extern unsigned int ___illegal_use_of_BTFIXUP_SIMM13_in_module(void);
16extern unsigned int ___illegal_use_of_BTFIXUP_SETHI_in_module(void);
17extern unsigned int ___illegal_use_of_BTFIXUP_HALF_in_module(void);
18extern unsigned int ___illegal_use_of_BTFIXUP_INT_in_module(void);
19
20#define BTFIXUP_SIMM13(__name) ___illegal_use_of_BTFIXUP_SIMM13_in_module()
21#define BTFIXUP_HALF(__name) ___illegal_use_of_BTFIXUP_HALF_in_module()
22#define BTFIXUP_SETHI(__name) ___illegal_use_of_BTFIXUP_SETHI_in_module()
23#define BTFIXUP_INT(__name) ___illegal_use_of_BTFIXUP_INT_in_module()
24#define BTFIXUP_BLACKBOX(__name) ___illegal_use_of_BTFIXUP_BLACKBOX_in_module
25
26#else
27
28#define BTFIXUP_SIMM13(__name) ___sf_##__name()
29#define BTFIXUP_HALF(__name) ___af_##__name()
30#define BTFIXUP_SETHI(__name) ___hf_##__name()
31#define BTFIXUP_INT(__name) ((unsigned int)&___i_##__name)
32/* This must be written in assembly and present in a sethi */
33#define BTFIXUP_BLACKBOX(__name) ___b_##__name
34#endif /* MODULE */
35
36/* Fixup call xx */
37
38#define BTFIXUPDEF_CALL(__type, __name, __args...) \
39 extern __type ___f_##__name(__args); \
40 extern unsigned ___fs_##__name[3];
41#define BTFIXUPDEF_CALL_CONST(__type, __name, __args...) \
42 extern __type ___f_##__name(__args) __attribute_const__; \
43 extern unsigned ___fs_##__name[3];
44#define BTFIXUP_CALL(__name) ___f_##__name
45
46#define BTFIXUPDEF_BLACKBOX(__name) \
47 extern unsigned ___bs_##__name[2];
48
49/* Put bottom 13bits into some register variable */
50
51#define BTFIXUPDEF_SIMM13(__name) \
52 static inline unsigned int ___sf_##__name(void) __attribute_const__; \
53 extern unsigned ___ss_##__name[2]; \
54 static inline unsigned int ___sf_##__name(void) { \
55 unsigned int ret; \
56 __asm__ ("or %%g0, ___s_" #__name ", %0" : "=r"(ret)); \
57 return ret; \
58 }
59#define BTFIXUPDEF_SIMM13_INIT(__name,__val) \
60 static inline unsigned int ___sf_##__name(void) __attribute_const__; \
61 extern unsigned ___ss_##__name[2]; \
62 static inline unsigned int ___sf_##__name(void) { \
63 unsigned int ret; \
64 __asm__ ("or %%g0, ___s_" #__name "__btset_" #__val ", %0" : "=r"(ret));\
65 return ret; \
66 }
67
68/* Put either bottom 13 bits, or upper 22 bits into some register variable
69 * (depending on the value, this will lead into sethi FIX, reg; or
70 * mov FIX, reg; )
71 */
72
73#define BTFIXUPDEF_HALF(__name) \
74 static inline unsigned int ___af_##__name(void) __attribute_const__; \
75 extern unsigned ___as_##__name[2]; \
76 static inline unsigned int ___af_##__name(void) { \
77 unsigned int ret; \
78 __asm__ ("or %%g0, ___a_" #__name ", %0" : "=r"(ret)); \
79 return ret; \
80 }
81#define BTFIXUPDEF_HALF_INIT(__name,__val) \
82 static inline unsigned int ___af_##__name(void) __attribute_const__; \
83 extern unsigned ___as_##__name[2]; \
84 static inline unsigned int ___af_##__name(void) { \
85 unsigned int ret; \
86 __asm__ ("or %%g0, ___a_" #__name "__btset_" #__val ", %0" : "=r"(ret));\
87 return ret; \
88 }
89
90/* Put upper 22 bits into some register variable */
91
92#define BTFIXUPDEF_SETHI(__name) \
93 static inline unsigned int ___hf_##__name(void) __attribute_const__; \
94 extern unsigned ___hs_##__name[2]; \
95 static inline unsigned int ___hf_##__name(void) { \
96 unsigned int ret; \
97 __asm__ ("sethi %%hi(___h_" #__name "), %0" : "=r"(ret)); \
98 return ret; \
99 }
100#define BTFIXUPDEF_SETHI_INIT(__name,__val) \
101 static inline unsigned int ___hf_##__name(void) __attribute_const__; \
102 extern unsigned ___hs_##__name[2]; \
103 static inline unsigned int ___hf_##__name(void) { \
104 unsigned int ret; \
105 __asm__ ("sethi %%hi(___h_" #__name "__btset_" #__val "), %0" : \
106 "=r"(ret)); \
107 return ret; \
108 }
109
110/* Put a full 32bit integer into some register variable */
111
112#define BTFIXUPDEF_INT(__name) \
113 extern unsigned char ___i_##__name; \
114 extern unsigned ___is_##__name[2];
115
116#define BTFIXUPCALL_NORM 0x00000000 /* Always call */
117#define BTFIXUPCALL_NOP 0x01000000 /* Possibly optimize to nop */
118#define BTFIXUPCALL_RETINT(i) (0x90102000|((i) & 0x1fff)) /* Possibly optimize to mov i, %o0 */
119#define BTFIXUPCALL_ORINT(i) (0x90122000|((i) & 0x1fff)) /* Possibly optimize to or %o0, i, %o0 */
120#define BTFIXUPCALL_RETO0 0x01000000 /* Return first parameter, actually a nop */
121#define BTFIXUPCALL_ANDNINT(i) (0x902a2000|((i) & 0x1fff)) /* Possibly optimize to andn %o0, i, %o0 */
122#define BTFIXUPCALL_SWAPO0O1 0xd27a0000 /* Possibly optimize to swap [%o0],%o1 */
123#define BTFIXUPCALL_SWAPO0G0 0xc07a0000 /* Possibly optimize to swap [%o0],%g0 */
124#define BTFIXUPCALL_SWAPG1G2 0xc4784000 /* Possibly optimize to swap [%g1],%g2 */
125#define BTFIXUPCALL_STG0O0 0xc0220000 /* Possibly optimize to st %g0,[%o0] */
126#define BTFIXUPCALL_STO1O0 0xd2220000 /* Possibly optimize to st %o1,[%o0] */
127
128#define BTFIXUPSET_CALL(__name, __addr, __insn) \
129 do { \
130 ___fs_##__name[0] |= 1; \
131 ___fs_##__name[1] = (unsigned long)__addr; \
132 ___fs_##__name[2] = __insn; \
133 } while (0)
134
135#define BTFIXUPSET_BLACKBOX(__name, __func) \
136 do { \
137 ___bs_##__name[0] |= 1; \
138 ___bs_##__name[1] = (unsigned long)__func; \
139 } while (0)
140
141#define BTFIXUPCOPY_CALL(__name, __from) \
142 do { \
143 ___fs_##__name[0] |= 1; \
144 ___fs_##__name[1] = ___fs_##__from[1]; \
145 ___fs_##__name[2] = ___fs_##__from[2]; \
146 } while (0)
147
148#define BTFIXUPSET_SIMM13(__name, __val) \
149 do { \
150 ___ss_##__name[0] |= 1; \
151 ___ss_##__name[1] = (unsigned)__val; \
152 } while (0)
153
154#define BTFIXUPCOPY_SIMM13(__name, __from) \
155 do { \
156 ___ss_##__name[0] |= 1; \
157 ___ss_##__name[1] = ___ss_##__from[1]; \
158 } while (0)
159
160#define BTFIXUPSET_HALF(__name, __val) \
161 do { \
162 ___as_##__name[0] |= 1; \
163 ___as_##__name[1] = (unsigned)__val; \
164 } while (0)
165
166#define BTFIXUPCOPY_HALF(__name, __from) \
167 do { \
168 ___as_##__name[0] |= 1; \
169 ___as_##__name[1] = ___as_##__from[1]; \
170 } while (0)
171
172#define BTFIXUPSET_SETHI(__name, __val) \
173 do { \
174 ___hs_##__name[0] |= 1; \
175 ___hs_##__name[1] = (unsigned)__val; \
176 } while (0)
177
178#define BTFIXUPCOPY_SETHI(__name, __from) \
179 do { \
180 ___hs_##__name[0] |= 1; \
181 ___hs_##__name[1] = ___hs_##__from[1]; \
182 } while (0)
183
184#define BTFIXUPSET_INT(__name, __val) \
185 do { \
186 ___is_##__name[0] |= 1; \
187 ___is_##__name[1] = (unsigned)__val; \
188 } while (0)
189
190#define BTFIXUPCOPY_INT(__name, __from) \
191 do { \
192 ___is_##__name[0] |= 1; \
193 ___is_##__name[1] = ___is_##__from[1]; \
194 } while (0)
195
196#define BTFIXUPVAL_CALL(__name) \
197 ((unsigned long)___fs_##__name[1])
198
199extern void btfixup(void);
200
201#else /* __ASSEMBLY__ */
202
203#define BTFIXUP_SETHI(__name) %hi(___h_ ## __name)
204#define BTFIXUP_SETHI_INIT(__name,__val) %hi(___h_ ## __name ## __btset_ ## __val)
205
206#endif /* __ASSEMBLY__ */
207
208#endif /* !(_SPARC_BTFIXUP_H) */
diff --git a/include/asm-sparc/bug.h b/include/asm-sparc/bug.h
deleted file mode 100644
index 8a59e5a8c21..00000000000
--- a/include/asm-sparc/bug.h
+++ /dev/null
@@ -1,22 +0,0 @@
1#ifndef _SPARC_BUG_H
2#define _SPARC_BUG_H
3
4#ifdef CONFIG_BUG
5#include <linux/compiler.h>
6
7#ifdef CONFIG_DEBUG_BUGVERBOSE
8extern void do_BUG(const char *file, int line);
9#define BUG() do { \
10 do_BUG(__FILE__, __LINE__); \
11 __builtin_trap(); \
12} while (0)
13#else
14#define BUG() __builtin_trap()
15#endif
16
17#define HAVE_ARCH_BUG
18#endif
19
20#include <asm-generic/bug.h>
21
22#endif
diff --git a/include/asm-sparc/bugs.h b/include/asm-sparc/bugs.h
deleted file mode 100644
index 2dfc07bc8e5..00000000000
--- a/include/asm-sparc/bugs.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/* include/asm-sparc/bugs.h: Sparc probes for various bugs.
2 *
3 * Copyright (C) 1996, 2007 David S. Miller (davem@davemloft.net)
4 */
5
6#ifdef CONFIG_SPARC32
7#include <asm/cpudata.h>
8#endif
9
10#ifdef CONFIG_SPARC64
11#include <asm/sstate.h>
12#endif
13
14extern unsigned long loops_per_jiffy;
15
16static void __init check_bugs(void)
17{
18#if defined(CONFIG_SPARC32) && !defined(CONFIG_SMP)
19 cpu_data(0).udelay_val = loops_per_jiffy;
20#endif
21#ifdef CONFIG_SPARC64
22 sstate_running();
23#endif
24}
diff --git a/include/asm-sparc/byteorder.h b/include/asm-sparc/byteorder.h
deleted file mode 100644
index bcd83aa351c..00000000000
--- a/include/asm-sparc/byteorder.h
+++ /dev/null
@@ -1,57 +0,0 @@
1#ifndef _SPARC_BYTEORDER_H
2#define _SPARC_BYTEORDER_H
3
4#include <asm/types.h>
5#include <asm/asi.h>
6
7#ifdef __GNUC__
8
9#ifdef CONFIG_SPARC32
10#define __SWAB_64_THRU_32__
11#endif
12
13#ifdef CONFIG_SPARC64
14
15static inline __u16 ___arch__swab16p(const __u16 *addr)
16{
17 __u16 ret;
18
19 __asm__ __volatile__ ("lduha [%1] %2, %0"
20 : "=r" (ret)
21 : "r" (addr), "i" (ASI_PL));
22 return ret;
23}
24
25static inline __u32 ___arch__swab32p(const __u32 *addr)
26{
27 __u32 ret;
28
29 __asm__ __volatile__ ("lduwa [%1] %2, %0"
30 : "=r" (ret)
31 : "r" (addr), "i" (ASI_PL));
32 return ret;
33}
34
35static inline __u64 ___arch__swab64p(const __u64 *addr)
36{
37 __u64 ret;
38
39 __asm__ __volatile__ ("ldxa [%1] %2, %0"
40 : "=r" (ret)
41 : "r" (addr), "i" (ASI_PL));
42 return ret;
43}
44
45#define __arch__swab16p(x) ___arch__swab16p(x)
46#define __arch__swab32p(x) ___arch__swab32p(x)
47#define __arch__swab64p(x) ___arch__swab64p(x)
48
49#endif /* CONFIG_SPARC64 */
50
51#define __BYTEORDER_HAS_U64__
52
53#endif
54
55#include <linux/byteorder/big_endian.h>
56
57#endif /* _SPARC_BYTEORDER_H */
diff --git a/include/asm-sparc/cache.h b/include/asm-sparc/cache.h
deleted file mode 100644
index 41f85ae4bd4..00000000000
--- a/include/asm-sparc/cache.h
+++ /dev/null
@@ -1,138 +0,0 @@
1/* cache.h: Cache specific code for the Sparc. These include flushing
2 * and direct tag/data line access.
3 *
4 * Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net)
5 */
6
7#ifndef _SPARC_CACHE_H
8#define _SPARC_CACHE_H
9
10#define L1_CACHE_SHIFT 5
11#define L1_CACHE_BYTES 32
12#define L1_CACHE_ALIGN(x) ((((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)))
13
14#ifdef CONFIG_SPARC32
15#define SMP_CACHE_BYTES_SHIFT 5
16#else
17#define SMP_CACHE_BYTES_SHIFT 6
18#endif
19
20#define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_SHIFT)
21
22#define __read_mostly __attribute__((__section__(".data.read_mostly")))
23
24#ifdef CONFIG_SPARC32
25#include <asm/asi.h>
26
27/* Direct access to the instruction cache is provided through and
28 * alternate address space. The IDC bit must be off in the ICCR on
29 * HyperSparcs for these accesses to work. The code below does not do
30 * any checking, the caller must do so. These routines are for
31 * diagnostics only, but could end up being useful. Use with care.
32 * Also, you are asking for trouble if you execute these in one of the
33 * three instructions following a %asr/%psr access or modification.
34 */
35
36/* First, cache-tag access. */
37static inline unsigned int get_icache_tag(int setnum, int tagnum)
38{
39 unsigned int vaddr, retval;
40
41 vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5);
42 __asm__ __volatile__("lda [%1] %2, %0\n\t" :
43 "=r" (retval) :
44 "r" (vaddr), "i" (ASI_M_TXTC_TAG));
45 return retval;
46}
47
48static inline void put_icache_tag(int setnum, int tagnum, unsigned int entry)
49{
50 unsigned int vaddr;
51
52 vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5);
53 __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
54 "r" (entry), "r" (vaddr), "i" (ASI_M_TXTC_TAG) :
55 "memory");
56}
57
58/* Second cache-data access. The data is returned two-32bit quantities
59 * at a time.
60 */
61static inline void get_icache_data(int setnum, int tagnum, int subblock,
62 unsigned int *data)
63{
64 unsigned int value1, value2, vaddr;
65
66 vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) |
67 ((subblock&0x3) << 3);
68 __asm__ __volatile__("ldda [%2] %3, %%g2\n\t"
69 "or %%g0, %%g2, %0\n\t"
70 "or %%g0, %%g3, %1\n\t" :
71 "=r" (value1), "=r" (value2) :
72 "r" (vaddr), "i" (ASI_M_TXTC_DATA) :
73 "g2", "g3");
74 data[0] = value1; data[1] = value2;
75}
76
77static inline void put_icache_data(int setnum, int tagnum, int subblock,
78 unsigned int *data)
79{
80 unsigned int value1, value2, vaddr;
81
82 vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) |
83 ((subblock&0x3) << 3);
84 value1 = data[0]; value2 = data[1];
85 __asm__ __volatile__("or %%g0, %0, %%g2\n\t"
86 "or %%g0, %1, %%g3\n\t"
87 "stda %%g2, [%2] %3\n\t" : :
88 "r" (value1), "r" (value2),
89 "r" (vaddr), "i" (ASI_M_TXTC_DATA) :
90 "g2", "g3", "memory" /* no joke */);
91}
92
93/* Different types of flushes with the ICACHE. Some of the flushes
94 * affect both the ICACHE and the external cache. Others only clear
95 * the ICACHE entries on the cpu itself. V8's (most) allow
96 * granularity of flushes on the packet (element in line), whole line,
97 * and entire cache (ie. all lines) level. The ICACHE only flushes are
98 * ROSS HyperSparc specific and are in ross.h
99 */
100
101/* Flushes which clear out both the on-chip and external caches */
102static inline void flush_ei_page(unsigned int addr)
103{
104 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
105 "r" (addr), "i" (ASI_M_FLUSH_PAGE) :
106 "memory");
107}
108
109static inline void flush_ei_seg(unsigned int addr)
110{
111 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
112 "r" (addr), "i" (ASI_M_FLUSH_SEG) :
113 "memory");
114}
115
116static inline void flush_ei_region(unsigned int addr)
117{
118 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
119 "r" (addr), "i" (ASI_M_FLUSH_REGION) :
120 "memory");
121}
122
123static inline void flush_ei_ctx(unsigned int addr)
124{
125 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
126 "r" (addr), "i" (ASI_M_FLUSH_CTX) :
127 "memory");
128}
129
130static inline void flush_ei_user(unsigned int addr)
131{
132 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
133 "r" (addr), "i" (ASI_M_FLUSH_USER) :
134 "memory");
135}
136#endif /* CONFIG_SPARC32 */
137
138#endif /* !(_SPARC_CACHE_H) */
diff --git a/include/asm-sparc/cacheflush.h b/include/asm-sparc/cacheflush.h
deleted file mode 100644
index 2b6a37957c2..00000000000
--- a/include/asm-sparc/cacheflush.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_CACHEFLUSH_H
2#define ___ASM_SPARC_CACHEFLUSH_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/cacheflush_64.h>
5#else
6#include <asm-sparc/cacheflush_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/cacheflush_32.h b/include/asm-sparc/cacheflush_32.h
deleted file mode 100644
index 68ac1091027..00000000000
--- a/include/asm-sparc/cacheflush_32.h
+++ /dev/null
@@ -1,85 +0,0 @@
1#ifndef _SPARC_CACHEFLUSH_H
2#define _SPARC_CACHEFLUSH_H
3
4#include <linux/mm.h> /* Common for other includes */
5// #include <linux/kernel.h> from pgalloc.h
6// #include <linux/sched.h> from pgalloc.h
7
8// #include <asm/page.h>
9#include <asm/btfixup.h>
10
11/*
12 * Fine grained cache flushing.
13 */
14#ifdef CONFIG_SMP
15
16BTFIXUPDEF_CALL(void, local_flush_cache_all, void)
17BTFIXUPDEF_CALL(void, local_flush_cache_mm, struct mm_struct *)
18BTFIXUPDEF_CALL(void, local_flush_cache_range, struct vm_area_struct *, unsigned long, unsigned long)
19BTFIXUPDEF_CALL(void, local_flush_cache_page, struct vm_area_struct *, unsigned long)
20
21#define local_flush_cache_all() BTFIXUP_CALL(local_flush_cache_all)()
22#define local_flush_cache_mm(mm) BTFIXUP_CALL(local_flush_cache_mm)(mm)
23#define local_flush_cache_range(vma,start,end) BTFIXUP_CALL(local_flush_cache_range)(vma,start,end)
24#define local_flush_cache_page(vma,addr) BTFIXUP_CALL(local_flush_cache_page)(vma,addr)
25
26BTFIXUPDEF_CALL(void, local_flush_page_to_ram, unsigned long)
27BTFIXUPDEF_CALL(void, local_flush_sig_insns, struct mm_struct *, unsigned long)
28
29#define local_flush_page_to_ram(addr) BTFIXUP_CALL(local_flush_page_to_ram)(addr)
30#define local_flush_sig_insns(mm,insn_addr) BTFIXUP_CALL(local_flush_sig_insns)(mm,insn_addr)
31
32extern void smp_flush_cache_all(void);
33extern void smp_flush_cache_mm(struct mm_struct *mm);
34extern void smp_flush_cache_range(struct vm_area_struct *vma,
35 unsigned long start,
36 unsigned long end);
37extern void smp_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
38
39extern void smp_flush_page_to_ram(unsigned long page);
40extern void smp_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
41
42#endif /* CONFIG_SMP */
43
44BTFIXUPDEF_CALL(void, flush_cache_all, void)
45BTFIXUPDEF_CALL(void, flush_cache_mm, struct mm_struct *)
46BTFIXUPDEF_CALL(void, flush_cache_range, struct vm_area_struct *, unsigned long, unsigned long)
47BTFIXUPDEF_CALL(void, flush_cache_page, struct vm_area_struct *, unsigned long)
48
49#define flush_cache_all() BTFIXUP_CALL(flush_cache_all)()
50#define flush_cache_mm(mm) BTFIXUP_CALL(flush_cache_mm)(mm)
51#define flush_cache_dup_mm(mm) BTFIXUP_CALL(flush_cache_mm)(mm)
52#define flush_cache_range(vma,start,end) BTFIXUP_CALL(flush_cache_range)(vma,start,end)
53#define flush_cache_page(vma,addr,pfn) BTFIXUP_CALL(flush_cache_page)(vma,addr)
54#define flush_icache_range(start, end) do { } while (0)
55#define flush_icache_page(vma, pg) do { } while (0)
56
57#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
58
59#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
60 do { \
61 flush_cache_page(vma, vaddr, page_to_pfn(page));\
62 memcpy(dst, src, len); \
63 } while (0)
64#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
65 do { \
66 flush_cache_page(vma, vaddr, page_to_pfn(page));\
67 memcpy(dst, src, len); \
68 } while (0)
69
70BTFIXUPDEF_CALL(void, __flush_page_to_ram, unsigned long)
71BTFIXUPDEF_CALL(void, flush_sig_insns, struct mm_struct *, unsigned long)
72
73#define __flush_page_to_ram(addr) BTFIXUP_CALL(__flush_page_to_ram)(addr)
74#define flush_sig_insns(mm,insn_addr) BTFIXUP_CALL(flush_sig_insns)(mm,insn_addr)
75
76extern void sparc_flush_page_to_ram(struct page *page);
77
78#define flush_dcache_page(page) sparc_flush_page_to_ram(page)
79#define flush_dcache_mmap_lock(mapping) do { } while (0)
80#define flush_dcache_mmap_unlock(mapping) do { } while (0)
81
82#define flush_cache_vmap(start, end) flush_cache_all()
83#define flush_cache_vunmap(start, end) flush_cache_all()
84
85#endif /* _SPARC_CACHEFLUSH_H */
diff --git a/include/asm-sparc/cacheflush_64.h b/include/asm-sparc/cacheflush_64.h
deleted file mode 100644
index c43321729b3..00000000000
--- a/include/asm-sparc/cacheflush_64.h
+++ /dev/null
@@ -1,76 +0,0 @@
1#ifndef _SPARC64_CACHEFLUSH_H
2#define _SPARC64_CACHEFLUSH_H
3
4#include <asm/page.h>
5
6#ifndef __ASSEMBLY__
7
8#include <linux/mm.h>
9
10/* Cache flush operations. */
11
12/* These are the same regardless of whether this is an SMP kernel or not. */
13#define flush_cache_mm(__mm) \
14 do { if ((__mm) == current->mm) flushw_user(); } while(0)
15#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
16#define flush_cache_range(vma, start, end) \
17 flush_cache_mm((vma)->vm_mm)
18#define flush_cache_page(vma, page, pfn) \
19 flush_cache_mm((vma)->vm_mm)
20
21/*
22 * On spitfire, the icache doesn't snoop local stores and we don't
23 * use block commit stores (which invalidate icache lines) during
24 * module load, so we need this.
25 */
26extern void flush_icache_range(unsigned long start, unsigned long end);
27extern void __flush_icache_page(unsigned long);
28
29extern void __flush_dcache_page(void *addr, int flush_icache);
30extern void flush_dcache_page_impl(struct page *page);
31#ifdef CONFIG_SMP
32extern void smp_flush_dcache_page_impl(struct page *page, int cpu);
33extern void flush_dcache_page_all(struct mm_struct *mm, struct page *page);
34#else
35#define smp_flush_dcache_page_impl(page,cpu) flush_dcache_page_impl(page)
36#define flush_dcache_page_all(mm,page) flush_dcache_page_impl(page)
37#endif
38
39extern void __flush_dcache_range(unsigned long start, unsigned long end);
40extern void flush_dcache_page(struct page *page);
41
42#define flush_icache_page(vma, pg) do { } while(0)
43#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
44
45extern void flush_ptrace_access(struct vm_area_struct *, struct page *,
46 unsigned long uaddr, void *kaddr,
47 unsigned long len, int write);
48
49#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
50 do { \
51 flush_cache_page(vma, vaddr, page_to_pfn(page)); \
52 memcpy(dst, src, len); \
53 flush_ptrace_access(vma, page, vaddr, src, len, 0); \
54 } while (0)
55
56#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
57 do { \
58 flush_cache_page(vma, vaddr, page_to_pfn(page)); \
59 memcpy(dst, src, len); \
60 flush_ptrace_access(vma, page, vaddr, dst, len, 1); \
61 } while (0)
62
63#define flush_dcache_mmap_lock(mapping) do { } while (0)
64#define flush_dcache_mmap_unlock(mapping) do { } while (0)
65
66#define flush_cache_vmap(start, end) do { } while (0)
67#define flush_cache_vunmap(start, end) do { } while (0)
68
69#ifdef CONFIG_DEBUG_PAGEALLOC
70/* internal debugging function */
71void kernel_map_pages(struct page *page, int numpages, int enable);
72#endif
73
74#endif /* !__ASSEMBLY__ */
75
76#endif /* _SPARC64_CACHEFLUSH_H */
diff --git a/include/asm-sparc/chafsr.h b/include/asm-sparc/chafsr.h
deleted file mode 100644
index 85c69b38220..00000000000
--- a/include/asm-sparc/chafsr.h
+++ /dev/null
@@ -1,241 +0,0 @@
1#ifndef _SPARC64_CHAFSR_H
2#define _SPARC64_CHAFSR_H
3
4/* Cheetah Asynchronous Fault Status register, ASI=0x4C VA<63:0>=0x0 */
5
6/* Comments indicate which processor variants on which the bit definition
7 * is valid. Codes are:
8 * ch --> cheetah
9 * ch+ --> cheetah plus
10 * jp --> jalapeno
11 */
12
13/* All bits of this register except M_SYNDROME and E_SYNDROME are
14 * read, write 1 to clear. M_SYNDROME and E_SYNDROME are read-only.
15 */
16
17/* Software bit set by linux trap handlers to indicate that the trap was
18 * signalled at %tl >= 1.
19 */
20#define CHAFSR_TL1 (1UL << 63UL) /* n/a */
21
22/* Unmapped error from system bus for prefetch queue or
23 * store queue read operation
24 */
25#define CHPAFSR_DTO (1UL << 59UL) /* ch+ */
26
27/* Bus error from system bus for prefetch queue or store queue
28 * read operation
29 */
30#define CHPAFSR_DBERR (1UL << 58UL) /* ch+ */
31
32/* Hardware corrected E-cache Tag ECC error */
33#define CHPAFSR_THCE (1UL << 57UL) /* ch+ */
34/* System interface protocol error, hw timeout caused */
35#define JPAFSR_JETO (1UL << 57UL) /* jp */
36
37/* SW handled correctable E-cache Tag ECC error */
38#define CHPAFSR_TSCE (1UL << 56UL) /* ch+ */
39/* Parity error on system snoop results */
40#define JPAFSR_SCE (1UL << 56UL) /* jp */
41
42/* Uncorrectable E-cache Tag ECC error */
43#define CHPAFSR_TUE (1UL << 55UL) /* ch+ */
44/* System interface protocol error, illegal command detected */
45#define JPAFSR_JEIC (1UL << 55UL) /* jp */
46
47/* Uncorrectable system bus data ECC error due to prefetch
48 * or store fill request
49 */
50#define CHPAFSR_DUE (1UL << 54UL) /* ch+ */
51/* System interface protocol error, illegal ADTYPE detected */
52#define JPAFSR_JEIT (1UL << 54UL) /* jp */
53
54/* Multiple errors of the same type have occurred. This bit is set when
55 * an uncorrectable error or a SW correctable error occurs and the status
56 * bit to report that error is already set. When multiple errors of
57 * different types are indicated by setting multiple status bits.
58 *
59 * This bit is not set if multiple HW corrected errors with the same
60 * status bit occur, only uncorrectable and SW correctable ones have
61 * this behavior.
62 *
63 * This bit is not set when multiple ECC errors happen within a single
64 * 64-byte system bus transaction. Only the first ECC error in a 16-byte
65 * subunit will be logged. All errors in subsequent 16-byte subunits
66 * from the same 64-byte transaction are ignored.
67 */
68#define CHAFSR_ME (1UL << 53UL) /* ch,ch+,jp */
69
70/* Privileged state error has occurred. This is a capture of PSTATE.PRIV
71 * at the time the error is detected.
72 */
73#define CHAFSR_PRIV (1UL << 52UL) /* ch,ch+,jp */
74
75/* The following bits 51 (CHAFSR_PERR) to 33 (CHAFSR_CE) are sticky error
76 * bits and record the most recently detected errors. Bits accumulate
77 * errors that have been detected since the last write to clear the bit.
78 */
79
80/* System interface protocol error. The processor asserts its' ERROR
81 * pin when this event occurs and it also logs a specific cause code
82 * into a JTAG scannable flop.
83 */
84#define CHAFSR_PERR (1UL << 51UL) /* ch,ch+,jp */
85
86/* Internal processor error. The processor asserts its' ERROR
87 * pin when this event occurs and it also logs a specific cause code
88 * into a JTAG scannable flop.
89 */
90#define CHAFSR_IERR (1UL << 50UL) /* ch,ch+,jp */
91
92/* System request parity error on incoming address */
93#define CHAFSR_ISAP (1UL << 49UL) /* ch,ch+,jp */
94
95/* HW Corrected system bus MTAG ECC error */
96#define CHAFSR_EMC (1UL << 48UL) /* ch,ch+ */
97/* Parity error on L2 cache tag SRAM */
98#define JPAFSR_ETP (1UL << 48UL) /* jp */
99
100/* Uncorrectable system bus MTAG ECC error */
101#define CHAFSR_EMU (1UL << 47UL) /* ch,ch+ */
102/* Out of range memory error has occurred */
103#define JPAFSR_OM (1UL << 47UL) /* jp */
104
105/* HW Corrected system bus data ECC error for read of interrupt vector */
106#define CHAFSR_IVC (1UL << 46UL) /* ch,ch+ */
107/* Error due to unsupported store */
108#define JPAFSR_UMS (1UL << 46UL) /* jp */
109
110/* Uncorrectable system bus data ECC error for read of interrupt vector */
111#define CHAFSR_IVU (1UL << 45UL) /* ch,ch+,jp */
112
113/* Unmapped error from system bus */
114#define CHAFSR_TO (1UL << 44UL) /* ch,ch+,jp */
115
116/* Bus error response from system bus */
117#define CHAFSR_BERR (1UL << 43UL) /* ch,ch+,jp */
118
119/* SW Correctable E-cache ECC error for instruction fetch or data access
120 * other than block load.
121 */
122#define CHAFSR_UCC (1UL << 42UL) /* ch,ch+,jp */
123
124/* Uncorrectable E-cache ECC error for instruction fetch or data access
125 * other than block load.
126 */
127#define CHAFSR_UCU (1UL << 41UL) /* ch,ch+,jp */
128
129/* Copyout HW Corrected ECC error */
130#define CHAFSR_CPC (1UL << 40UL) /* ch,ch+,jp */
131
132/* Copyout Uncorrectable ECC error */
133#define CHAFSR_CPU (1UL << 39UL) /* ch,ch+,jp */
134
135/* HW Corrected ECC error from E-cache for writeback */
136#define CHAFSR_WDC (1UL << 38UL) /* ch,ch+,jp */
137
138/* Uncorrectable ECC error from E-cache for writeback */
139#define CHAFSR_WDU (1UL << 37UL) /* ch,ch+,jp */
140
141/* HW Corrected ECC error from E-cache for store merge or block load */
142#define CHAFSR_EDC (1UL << 36UL) /* ch,ch+,jp */
143
144/* Uncorrectable ECC error from E-cache for store merge or block load */
145#define CHAFSR_EDU (1UL << 35UL) /* ch,ch+,jp */
146
147/* Uncorrectable system bus data ECC error for read of memory or I/O */
148#define CHAFSR_UE (1UL << 34UL) /* ch,ch+,jp */
149
150/* HW Corrected system bus data ECC error for read of memory or I/O */
151#define CHAFSR_CE (1UL << 33UL) /* ch,ch+,jp */
152
153/* Uncorrectable ECC error from remote cache/memory */
154#define JPAFSR_RUE (1UL << 32UL) /* jp */
155
156/* Correctable ECC error from remote cache/memory */
157#define JPAFSR_RCE (1UL << 31UL) /* jp */
158
159/* JBUS parity error on returned read data */
160#define JPAFSR_BP (1UL << 30UL) /* jp */
161
162/* JBUS parity error on data for writeback or block store */
163#define JPAFSR_WBP (1UL << 29UL) /* jp */
164
165/* Foreign read to DRAM incurring correctable ECC error */
166#define JPAFSR_FRC (1UL << 28UL) /* jp */
167
168/* Foreign read to DRAM incurring uncorrectable ECC error */
169#define JPAFSR_FRU (1UL << 27UL) /* jp */
170
171#define CHAFSR_ERRORS (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP | CHAFSR_EMC | \
172 CHAFSR_EMU | CHAFSR_IVC | CHAFSR_IVU | CHAFSR_TO | \
173 CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | CHAFSR_CPC | \
174 CHAFSR_CPU | CHAFSR_WDC | CHAFSR_WDU | CHAFSR_EDC | \
175 CHAFSR_EDU | CHAFSR_UE | CHAFSR_CE)
176#define CHPAFSR_ERRORS (CHPAFSR_DTO | CHPAFSR_DBERR | CHPAFSR_THCE | \
177 CHPAFSR_TSCE | CHPAFSR_TUE | CHPAFSR_DUE | \
178 CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP | CHAFSR_EMC | \
179 CHAFSR_EMU | CHAFSR_IVC | CHAFSR_IVU | CHAFSR_TO | \
180 CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | CHAFSR_CPC | \
181 CHAFSR_CPU | CHAFSR_WDC | CHAFSR_WDU | CHAFSR_EDC | \
182 CHAFSR_EDU | CHAFSR_UE | CHAFSR_CE)
183#define JPAFSR_ERRORS (JPAFSR_JETO | JPAFSR_SCE | JPAFSR_JEIC | \
184 JPAFSR_JEIT | CHAFSR_PERR | CHAFSR_IERR | \
185 CHAFSR_ISAP | JPAFSR_ETP | JPAFSR_OM | \
186 JPAFSR_UMS | CHAFSR_IVU | CHAFSR_TO | \
187 CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | \
188 CHAFSR_CPC | CHAFSR_CPU | CHAFSR_WDC | \
189 CHAFSR_WDU | CHAFSR_EDC | CHAFSR_EDU | \
190 CHAFSR_UE | CHAFSR_CE | JPAFSR_RUE | \
191 JPAFSR_RCE | JPAFSR_BP | JPAFSR_WBP | \
192 JPAFSR_FRC | JPAFSR_FRU)
193
194/* Active JBUS request signal when error occurred */
195#define JPAFSR_JBREQ (0x7UL << 24UL) /* jp */
196#define JPAFSR_JBREQ_SHIFT 24UL
197
198/* L2 cache way information */
199#define JPAFSR_ETW (0x3UL << 22UL) /* jp */
200#define JPAFSR_ETW_SHIFT 22UL
201
202/* System bus MTAG ECC syndrome. This field captures the status of the
203 * first occurrence of the highest-priority error according to the M_SYND
204 * overwrite policy. After the AFSR sticky bit, corresponding to the error
205 * for which the M_SYND is reported, is cleared, the contents of the M_SYND
206 * field will be unchanged by will be unfrozen for further error capture.
207 */
208#define CHAFSR_M_SYNDROME (0xfUL << 16UL) /* ch,ch+,jp */
209#define CHAFSR_M_SYNDROME_SHIFT 16UL
210
211/* Agenid Id of the foreign device causing the UE/CE errors */
212#define JPAFSR_AID (0x1fUL << 9UL) /* jp */
213#define JPAFSR_AID_SHIFT 9UL
214
215/* System bus or E-cache data ECC syndrome. This field captures the status
216 * of the first occurrence of the highest-priority error according to the
217 * E_SYND overwrite policy. After the AFSR sticky bit, corresponding to the
218 * error for which the E_SYND is reported, is cleare, the contents of the E_SYND
219 * field will be unchanged but will be unfrozen for further error capture.
220 */
221#define CHAFSR_E_SYNDROME (0x1ffUL << 0UL) /* ch,ch+,jp */
222#define CHAFSR_E_SYNDROME_SHIFT 0UL
223
224/* The AFSR must be explicitly cleared by software, it is not cleared automatically
225 * by a read. Writes to bits <51:33> with bits set will clear the corresponding
226 * bits in the AFSR. Bits associated with disrupting traps must be cleared before
227 * interrupts are re-enabled to prevent multiple traps for the same error. I.e.
228 * PSTATE.IE and AFSR bits control delivery of disrupting traps.
229 *
230 * Since there is only one AFAR, when multiple events have been logged by the
231 * bits in the AFSR, at most one of these events will have its status captured
232 * in the AFAR. The highest priority of those event bits will get AFAR logging.
233 * The AFAR will be unlocked and available to capture the address of another event
234 * as soon as the one bit in AFSR that corresponds to the event logged in AFAR is
235 * cleared. For example, if AFSR.CE is detected, then AFSR.UE (which overwrites
236 * the AFAR), and AFSR.UE is cleared by not AFSR.CE, then the AFAR will be unlocked
237 * and ready for another event, even though AFSR.CE is still set. The same rules
238 * also apply to the M_SYNDROME and E_SYNDROME fields of the AFSR.
239 */
240
241#endif /* _SPARC64_CHAFSR_H */
diff --git a/include/asm-sparc/checksum.h b/include/asm-sparc/checksum.h
deleted file mode 100644
index 4e3553d4f6e..00000000000
--- a/include/asm-sparc/checksum.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_CHECKSUM_H
2#define ___ASM_SPARC_CHECKSUM_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/checksum_64.h>
5#else
6#include <asm-sparc/checksum_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/checksum_32.h b/include/asm-sparc/checksum_32.h
deleted file mode 100644
index bdbda1453aa..00000000000
--- a/include/asm-sparc/checksum_32.h
+++ /dev/null
@@ -1,241 +0,0 @@
1#ifndef __SPARC_CHECKSUM_H
2#define __SPARC_CHECKSUM_H
3
4/* checksum.h: IP/UDP/TCP checksum routines on the Sparc.
5 *
6 * Copyright(C) 1995 Linus Torvalds
7 * Copyright(C) 1995 Miguel de Icaza
8 * Copyright(C) 1996 David S. Miller
9 * Copyright(C) 1996 Eddie C. Dost
10 * Copyright(C) 1997 Jakub Jelinek
11 *
12 * derived from:
13 * Alpha checksum c-code
14 * ix86 inline assembly
15 * RFC1071 Computing the Internet Checksum
16 */
17
18#include <linux/in6.h>
19#include <asm/uaccess.h>
20
21/* computes the checksum of a memory block at buff, length len,
22 * and adds in "sum" (32-bit)
23 *
24 * returns a 32-bit number suitable for feeding into itself
25 * or csum_tcpudp_magic
26 *
27 * this function must be called with even lengths, except
28 * for the last fragment, which may be odd
29 *
30 * it's best to have buff aligned on a 32-bit boundary
31 */
32extern __wsum csum_partial(const void *buff, int len, __wsum sum);
33
34/* the same as csum_partial, but copies from fs:src while it
35 * checksums
36 *
37 * here even more important to align src and dst on a 32-bit (or even
38 * better 64-bit) boundary
39 */
40
41extern unsigned int __csum_partial_copy_sparc_generic (const unsigned char *, unsigned char *);
42
43static inline __wsum
44csum_partial_copy_nocheck(const void *src, void *dst, int len, __wsum sum)
45{
46 register unsigned int ret asm("o0") = (unsigned int)src;
47 register char *d asm("o1") = dst;
48 register int l asm("g1") = len;
49
50 __asm__ __volatile__ (
51 "call __csum_partial_copy_sparc_generic\n\t"
52 " mov %6, %%g7\n"
53 : "=&r" (ret), "=&r" (d), "=&r" (l)
54 : "0" (ret), "1" (d), "2" (l), "r" (sum)
55 : "o2", "o3", "o4", "o5", "o7",
56 "g2", "g3", "g4", "g5", "g7",
57 "memory", "cc");
58 return (__force __wsum)ret;
59}
60
61static inline __wsum
62csum_partial_copy_from_user(const void __user *src, void *dst, int len,
63 __wsum sum, int *err)
64 {
65 register unsigned long ret asm("o0") = (unsigned long)src;
66 register char *d asm("o1") = dst;
67 register int l asm("g1") = len;
68 register __wsum s asm("g7") = sum;
69
70 __asm__ __volatile__ (
71 ".section __ex_table,#alloc\n\t"
72 ".align 4\n\t"
73 ".word 1f,2\n\t"
74 ".previous\n"
75 "1:\n\t"
76 "call __csum_partial_copy_sparc_generic\n\t"
77 " st %8, [%%sp + 64]\n"
78 : "=&r" (ret), "=&r" (d), "=&r" (l), "=&r" (s)
79 : "0" (ret), "1" (d), "2" (l), "3" (s), "r" (err)
80 : "o2", "o3", "o4", "o5", "o7", "g2", "g3", "g4", "g5",
81 "cc", "memory");
82 return (__force __wsum)ret;
83}
84
85static inline __wsum
86csum_partial_copy_to_user(const void *src, void __user *dst, int len,
87 __wsum sum, int *err)
88{
89 if (!access_ok (VERIFY_WRITE, dst, len)) {
90 *err = -EFAULT;
91 return sum;
92 } else {
93 register unsigned long ret asm("o0") = (unsigned long)src;
94 register char __user *d asm("o1") = dst;
95 register int l asm("g1") = len;
96 register __wsum s asm("g7") = sum;
97
98 __asm__ __volatile__ (
99 ".section __ex_table,#alloc\n\t"
100 ".align 4\n\t"
101 ".word 1f,1\n\t"
102 ".previous\n"
103 "1:\n\t"
104 "call __csum_partial_copy_sparc_generic\n\t"
105 " st %8, [%%sp + 64]\n"
106 : "=&r" (ret), "=&r" (d), "=&r" (l), "=&r" (s)
107 : "0" (ret), "1" (d), "2" (l), "3" (s), "r" (err)
108 : "o2", "o3", "o4", "o5", "o7",
109 "g2", "g3", "g4", "g5",
110 "cc", "memory");
111 return (__force __wsum)ret;
112 }
113}
114
115#define HAVE_CSUM_COPY_USER
116#define csum_and_copy_to_user csum_partial_copy_to_user
117
118/* ihl is always 5 or greater, almost always is 5, and iph is word aligned
119 * the majority of the time.
120 */
121static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
122{
123 __sum16 sum;
124
125 /* Note: We must read %2 before we touch %0 for the first time,
126 * because GCC can legitimately use the same register for
127 * both operands.
128 */
129 __asm__ __volatile__("sub\t%2, 4, %%g4\n\t"
130 "ld\t[%1 + 0x00], %0\n\t"
131 "ld\t[%1 + 0x04], %%g2\n\t"
132 "ld\t[%1 + 0x08], %%g3\n\t"
133 "addcc\t%%g2, %0, %0\n\t"
134 "addxcc\t%%g3, %0, %0\n\t"
135 "ld\t[%1 + 0x0c], %%g2\n\t"
136 "ld\t[%1 + 0x10], %%g3\n\t"
137 "addxcc\t%%g2, %0, %0\n\t"
138 "addx\t%0, %%g0, %0\n"
139 "1:\taddcc\t%%g3, %0, %0\n\t"
140 "add\t%1, 4, %1\n\t"
141 "addxcc\t%0, %%g0, %0\n\t"
142 "subcc\t%%g4, 1, %%g4\n\t"
143 "be,a\t2f\n\t"
144 "sll\t%0, 16, %%g2\n\t"
145 "b\t1b\n\t"
146 "ld\t[%1 + 0x10], %%g3\n"
147 "2:\taddcc\t%0, %%g2, %%g2\n\t"
148 "srl\t%%g2, 16, %0\n\t"
149 "addx\t%0, %%g0, %0\n\t"
150 "xnor\t%%g0, %0, %0"
151 : "=r" (sum), "=&r" (iph)
152 : "r" (ihl), "1" (iph)
153 : "g2", "g3", "g4", "cc", "memory");
154 return sum;
155}
156
157/* Fold a partial checksum without adding pseudo headers. */
158static inline __sum16 csum_fold(__wsum sum)
159{
160 unsigned int tmp;
161
162 __asm__ __volatile__("addcc\t%0, %1, %1\n\t"
163 "srl\t%1, 16, %1\n\t"
164 "addx\t%1, %%g0, %1\n\t"
165 "xnor\t%%g0, %1, %0"
166 : "=&r" (sum), "=r" (tmp)
167 : "0" (sum), "1" ((__force u32)sum<<16)
168 : "cc");
169 return (__force __sum16)sum;
170}
171
172static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
173 unsigned short len,
174 unsigned short proto,
175 __wsum sum)
176{
177 __asm__ __volatile__("addcc\t%1, %0, %0\n\t"
178 "addxcc\t%2, %0, %0\n\t"
179 "addxcc\t%3, %0, %0\n\t"
180 "addx\t%0, %%g0, %0\n\t"
181 : "=r" (sum), "=r" (saddr)
182 : "r" (daddr), "r" (proto + len), "0" (sum),
183 "1" (saddr)
184 : "cc");
185 return sum;
186}
187
188/*
189 * computes the checksum of the TCP/UDP pseudo-header
190 * returns a 16-bit checksum, already complemented
191 */
192static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
193 unsigned short len,
194 unsigned short proto,
195 __wsum sum)
196{
197 return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
198}
199
200#define _HAVE_ARCH_IPV6_CSUM
201
202static inline __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
203 const struct in6_addr *daddr,
204 __u32 len, unsigned short proto,
205 __wsum sum)
206{
207 __asm__ __volatile__ (
208 "addcc %3, %4, %%g4\n\t"
209 "addxcc %5, %%g4, %%g4\n\t"
210 "ld [%2 + 0x0c], %%g2\n\t"
211 "ld [%2 + 0x08], %%g3\n\t"
212 "addxcc %%g2, %%g4, %%g4\n\t"
213 "ld [%2 + 0x04], %%g2\n\t"
214 "addxcc %%g3, %%g4, %%g4\n\t"
215 "ld [%2 + 0x00], %%g3\n\t"
216 "addxcc %%g2, %%g4, %%g4\n\t"
217 "ld [%1 + 0x0c], %%g2\n\t"
218 "addxcc %%g3, %%g4, %%g4\n\t"
219 "ld [%1 + 0x08], %%g3\n\t"
220 "addxcc %%g2, %%g4, %%g4\n\t"
221 "ld [%1 + 0x04], %%g2\n\t"
222 "addxcc %%g3, %%g4, %%g4\n\t"
223 "ld [%1 + 0x00], %%g3\n\t"
224 "addxcc %%g2, %%g4, %%g4\n\t"
225 "addxcc %%g3, %%g4, %0\n\t"
226 "addx 0, %0, %0\n"
227 : "=&r" (sum)
228 : "r" (saddr), "r" (daddr),
229 "r"(htonl(len)), "r"(htonl(proto)), "r"(sum)
230 : "g2", "g3", "g4", "cc");
231
232 return csum_fold(sum);
233}
234
235/* this routine is used for miscellaneous IP-like checksums, mainly in icmp.c */
236static inline __sum16 ip_compute_csum(const void *buff, int len)
237{
238 return csum_fold(csum_partial(buff, len, 0));
239}
240
241#endif /* !(__SPARC_CHECKSUM_H) */
diff --git a/include/asm-sparc/checksum_64.h b/include/asm-sparc/checksum_64.h
deleted file mode 100644
index 019b9615e43..00000000000
--- a/include/asm-sparc/checksum_64.h
+++ /dev/null
@@ -1,167 +0,0 @@
1#ifndef __SPARC64_CHECKSUM_H
2#define __SPARC64_CHECKSUM_H
3
4/* checksum.h: IP/UDP/TCP checksum routines on the V9.
5 *
6 * Copyright(C) 1995 Linus Torvalds
7 * Copyright(C) 1995 Miguel de Icaza
8 * Copyright(C) 1996 David S. Miller
9 * Copyright(C) 1996 Eddie C. Dost
10 * Copyright(C) 1997 Jakub Jelinek
11 *
12 * derived from:
13 * Alpha checksum c-code
14 * ix86 inline assembly
15 * RFC1071 Computing the Internet Checksum
16 */
17
18#include <linux/in6.h>
19#include <asm/uaccess.h>
20
21/* computes the checksum of a memory block at buff, length len,
22 * and adds in "sum" (32-bit)
23 *
24 * returns a 32-bit number suitable for feeding into itself
25 * or csum_tcpudp_magic
26 *
27 * this function must be called with even lengths, except
28 * for the last fragment, which may be odd
29 *
30 * it's best to have buff aligned on a 32-bit boundary
31 */
32extern __wsum csum_partial(const void * buff, int len, __wsum sum);
33
34/* the same as csum_partial, but copies from user space while it
35 * checksums
36 *
37 * here even more important to align src and dst on a 32-bit (or even
38 * better 64-bit) boundary
39 */
40extern __wsum csum_partial_copy_nocheck(const void *src, void *dst,
41 int len, __wsum sum);
42
43extern long __csum_partial_copy_from_user(const void __user *src,
44 void *dst, int len,
45 __wsum sum);
46
47static inline __wsum
48csum_partial_copy_from_user(const void __user *src,
49 void *dst, int len,
50 __wsum sum, int *err)
51{
52 long ret = __csum_partial_copy_from_user(src, dst, len, sum);
53 if (ret < 0)
54 *err = -EFAULT;
55 return (__force __wsum) ret;
56}
57
58/*
59 * Copy and checksum to user
60 */
61#define HAVE_CSUM_COPY_USER
62extern long __csum_partial_copy_to_user(const void *src,
63 void __user *dst, int len,
64 __wsum sum);
65
66static inline __wsum
67csum_and_copy_to_user(const void *src,
68 void __user *dst, int len,
69 __wsum sum, int *err)
70{
71 long ret = __csum_partial_copy_to_user(src, dst, len, sum);
72 if (ret < 0)
73 *err = -EFAULT;
74 return (__force __wsum) ret;
75}
76
77/* ihl is always 5 or greater, almost always is 5, and iph is word aligned
78 * the majority of the time.
79 */
80extern __sum16 ip_fast_csum(const void *iph, unsigned int ihl);
81
82/* Fold a partial checksum without adding pseudo headers. */
83static inline __sum16 csum_fold(__wsum sum)
84{
85 unsigned int tmp;
86
87 __asm__ __volatile__(
88" addcc %0, %1, %1\n"
89" srl %1, 16, %1\n"
90" addc %1, %%g0, %1\n"
91" xnor %%g0, %1, %0\n"
92 : "=&r" (sum), "=r" (tmp)
93 : "0" (sum), "1" ((__force u32)sum<<16)
94 : "cc");
95 return (__force __sum16)sum;
96}
97
98static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
99 unsigned int len,
100 unsigned short proto,
101 __wsum sum)
102{
103 __asm__ __volatile__(
104" addcc %1, %0, %0\n"
105" addccc %2, %0, %0\n"
106" addccc %3, %0, %0\n"
107" addc %0, %%g0, %0\n"
108 : "=r" (sum), "=r" (saddr)
109 : "r" (daddr), "r" (proto + len), "0" (sum), "1" (saddr)
110 : "cc");
111 return sum;
112}
113
114/*
115 * computes the checksum of the TCP/UDP pseudo-header
116 * returns a 16-bit checksum, already complemented
117 */
118static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
119 unsigned short len,
120 unsigned short proto,
121 __wsum sum)
122{
123 return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
124}
125
126#define _HAVE_ARCH_IPV6_CSUM
127
128static inline __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
129 const struct in6_addr *daddr,
130 __u32 len, unsigned short proto,
131 __wsum sum)
132{
133 __asm__ __volatile__ (
134" addcc %3, %4, %%g7\n"
135" addccc %5, %%g7, %%g7\n"
136" lduw [%2 + 0x0c], %%g2\n"
137" lduw [%2 + 0x08], %%g3\n"
138" addccc %%g2, %%g7, %%g7\n"
139" lduw [%2 + 0x04], %%g2\n"
140" addccc %%g3, %%g7, %%g7\n"
141" lduw [%2 + 0x00], %%g3\n"
142" addccc %%g2, %%g7, %%g7\n"
143" lduw [%1 + 0x0c], %%g2\n"
144" addccc %%g3, %%g7, %%g7\n"
145" lduw [%1 + 0x08], %%g3\n"
146" addccc %%g2, %%g7, %%g7\n"
147" lduw [%1 + 0x04], %%g2\n"
148" addccc %%g3, %%g7, %%g7\n"
149" lduw [%1 + 0x00], %%g3\n"
150" addccc %%g2, %%g7, %%g7\n"
151" addccc %%g3, %%g7, %0\n"
152" addc 0, %0, %0\n"
153 : "=&r" (sum)
154 : "r" (saddr), "r" (daddr), "r"(htonl(len)),
155 "r"(htonl(proto)), "r"(sum)
156 : "g2", "g3", "g7", "cc");
157
158 return csum_fold(sum);
159}
160
161/* this routine is used for miscellaneous IP-like checksums, mainly in icmp.c */
162static inline __sum16 ip_compute_csum(const void *buff, int len)
163{
164 return csum_fold(csum_partial(buff, len, 0));
165}
166
167#endif /* !(__SPARC64_CHECKSUM_H) */
diff --git a/include/asm-sparc/chmctrl.h b/include/asm-sparc/chmctrl.h
deleted file mode 100644
index 859b4a4b0d3..00000000000
--- a/include/asm-sparc/chmctrl.h
+++ /dev/null
@@ -1,183 +0,0 @@
1#ifndef _SPARC64_CHMCTRL_H
2#define _SPARC64_CHMCTRL_H
3
4/* Cheetah memory controller programmable registers. */
5#define CHMCTRL_TCTRL1 0x00 /* Memory Timing Control I */
6#define CHMCTRL_TCTRL2 0x08 /* Memory Timing Control II */
7#define CHMCTRL_TCTRL3 0x38 /* Memory Timing Control III */
8#define CHMCTRL_TCTRL4 0x40 /* Memory Timing Control IV */
9#define CHMCTRL_DECODE1 0x10 /* Memory Address Decode I */
10#define CHMCTRL_DECODE2 0x18 /* Memory Address Decode II */
11#define CHMCTRL_DECODE3 0x20 /* Memory Address Decode III */
12#define CHMCTRL_DECODE4 0x28 /* Memory Address Decode IV */
13#define CHMCTRL_MACTRL 0x30 /* Memory Address Control */
14
15/* Memory Timing Control I */
16#define TCTRL1_SDRAMCTL_DLY 0xf000000000000000UL
17#define TCTRL1_SDRAMCTL_DLY_SHIFT 60
18#define TCTRL1_SDRAMCLK_DLY 0x0e00000000000000UL
19#define TCTRL1_SDRAMCLK_DLY_SHIFT 57
20#define TCTRL1_R 0x0100000000000000UL
21#define TCTRL1_R_SHIFT 56
22#define TCTRL1_AUTORFR_CYCLE 0x00fe000000000000UL
23#define TCTRL1_AUTORFR_CYCLE_SHIFT 49
24#define TCTRL1_RD_WAIT 0x0001f00000000000UL
25#define TCTRL1_RD_WAIT_SHIFT 44
26#define TCTRL1_PC_CYCLE 0x00000fc000000000UL
27#define TCTRL1_PC_CYCLE_SHIFT 38
28#define TCTRL1_WR_MORE_RAS_PW 0x0000003f00000000UL
29#define TCTRL1_WR_MORE_RAS_PW_SHIFT 32
30#define TCTRL1_RD_MORE_RAW_PW 0x00000000fc000000UL
31#define TCTRL1_RD_MORE_RAS_PW_SHIFT 26
32#define TCTRL1_ACT_WR_DLY 0x0000000003f00000UL
33#define TCTRL1_ACT_WR_DLY_SHIFT 20
34#define TCTRL1_ACT_RD_DLY 0x00000000000fc000UL
35#define TCTRL1_ACT_RD_DLY_SHIFT 14
36#define TCTRL1_BANK_PRESENT 0x0000000000003000UL
37#define TCTRL1_BANK_PRESENT_SHIFT 12
38#define TCTRL1_RFR_INT 0x0000000000000ff8UL
39#define TCTRL1_RFR_INT_SHIFT 3
40#define TCTRL1_SET_MODE_REG 0x0000000000000004UL
41#define TCTRL1_SET_MODE_REG_SHIFT 2
42#define TCTRL1_RFR_ENABLE 0x0000000000000002UL
43#define TCTRL1_RFR_ENABLE_SHIFT 1
44#define TCTRL1_PRECHG_ALL 0x0000000000000001UL
45#define TCTRL1_PRECHG_ALL_SHIFT 0
46
47/* Memory Timing Control II */
48#define TCTRL2_WR_MSEL_DLY 0xfc00000000000000UL
49#define TCTRL2_WR_MSEL_DLY_SHIFT 58
50#define TCTRL2_RD_MSEL_DLY 0x03f0000000000000UL
51#define TCTRL2_RD_MSEL_DLY_SHIFT 52
52#define TCTRL2_WRDATA_THLD 0x000c000000000000UL
53#define TCTRL2_WRDATA_THLD_SHIFT 50
54#define TCTRL2_RDWR_RD_TI_DLY 0x0003f00000000000UL
55#define TCTRL2_RDWR_RD_TI_DLY_SHIFT 44
56#define TCTRL2_AUTOPRECHG_ENBL 0x0000080000000000UL
57#define TCTRL2_AUTOPRECHG_ENBL_SHIFT 43
58#define TCTRL2_RDWR_PI_MORE_DLY 0x000007c000000000UL
59#define TCTRL2_RDWR_PI_MORE_DLY_SHIFT 38
60#define TCTRL2_RDWR_1_DLY 0x0000003f00000000UL
61#define TCTRL2_RDWR_1_DLY_SHIFT 32
62#define TCTRL2_WRWR_PI_MORE_DLY 0x00000000f8000000UL
63#define TCTRL2_WRWR_PI_MORE_DLY_SHIFT 27
64#define TCTRL2_WRWR_1_DLY 0x0000000007e00000UL
65#define TCTRL2_WRWR_1_DLY_SHIFT 21
66#define TCTRL2_RDWR_RD_PI_MORE_DLY 0x00000000001f0000UL
67#define TCTRL2_RDWR_RD_PI_MORE_DLY_SHIFT 16
68#define TCTRL2_R 0x0000000000008000UL
69#define TCTRL2_R_SHIFT 15
70#define TCTRL2_SDRAM_MODE_REG_DATA 0x0000000000007fffUL
71#define TCTRL2_SDRAM_MODE_REG_DATA_SHIFT 0
72
73/* Memory Timing Control III */
74#define TCTRL3_SDRAM_CTL_DLY 0xf000000000000000UL
75#define TCTRL3_SDRAM_CTL_DLY_SHIFT 60
76#define TCTRL3_SDRAM_CLK_DLY 0x0e00000000000000UL
77#define TCTRL3_SDRAM_CLK_DLY_SHIFT 57
78#define TCTRL3_R 0x0100000000000000UL
79#define TCTRL3_R_SHIFT 56
80#define TCTRL3_AUTO_RFR_CYCLE 0x00fe000000000000UL
81#define TCTRL3_AUTO_RFR_CYCLE_SHIFT 49
82#define TCTRL3_RD_WAIT 0x0001f00000000000UL
83#define TCTRL3_RD_WAIT_SHIFT 44
84#define TCTRL3_PC_CYCLE 0x00000fc000000000UL
85#define TCTRL3_PC_CYCLE_SHIFT 38
86#define TCTRL3_WR_MORE_RAW_PW 0x0000003f00000000UL
87#define TCTRL3_WR_MORE_RAW_PW_SHIFT 32
88#define TCTRL3_RD_MORE_RAW_PW 0x00000000fc000000UL
89#define TCTRL3_RD_MORE_RAW_PW_SHIFT 26
90#define TCTRL3_ACT_WR_DLY 0x0000000003f00000UL
91#define TCTRL3_ACT_WR_DLY_SHIFT 20
92#define TCTRL3_ACT_RD_DLY 0x00000000000fc000UL
93#define TCTRL3_ACT_RD_DLY_SHIFT 14
94#define TCTRL3_BANK_PRESENT 0x0000000000003000UL
95#define TCTRL3_BANK_PRESENT_SHIFT 12
96#define TCTRL3_RFR_INT 0x0000000000000ff8UL
97#define TCTRL3_RFR_INT_SHIFT 3
98#define TCTRL3_SET_MODE_REG 0x0000000000000004UL
99#define TCTRL3_SET_MODE_REG_SHIFT 2
100#define TCTRL3_RFR_ENABLE 0x0000000000000002UL
101#define TCTRL3_RFR_ENABLE_SHIFT 1
102#define TCTRL3_PRECHG_ALL 0x0000000000000001UL
103#define TCTRL3_PRECHG_ALL_SHIFT 0
104
105/* Memory Timing Control IV */
106#define TCTRL4_WR_MSEL_DLY 0xfc00000000000000UL
107#define TCTRL4_WR_MSEL_DLY_SHIFT 58
108#define TCTRL4_RD_MSEL_DLY 0x03f0000000000000UL
109#define TCTRL4_RD_MSEL_DLY_SHIFT 52
110#define TCTRL4_WRDATA_THLD 0x000c000000000000UL
111#define TCTRL4_WRDATA_THLD_SHIFT 50
112#define TCTRL4_RDWR_RD_RI_DLY 0x0003f00000000000UL
113#define TCTRL4_RDWR_RD_RI_DLY_SHIFT 44
114#define TCTRL4_AUTO_PRECHG_ENBL 0x0000080000000000UL
115#define TCTRL4_AUTO_PRECHG_ENBL_SHIFT 43
116#define TCTRL4_RD_WR_PI_MORE_DLY 0x000007c000000000UL
117#define TCTRL4_RD_WR_PI_MORE_DLY_SHIFT 38
118#define TCTRL4_RD_WR_TI_DLY 0x0000003f00000000UL
119#define TCTRL4_RD_WR_TI_DLY_SHIFT 32
120#define TCTRL4_WR_WR_PI_MORE_DLY 0x00000000f8000000UL
121#define TCTRL4_WR_WR_PI_MORE_DLY_SHIFT 27
122#define TCTRL4_WR_WR_TI_DLY 0x0000000007e00000UL
123#define TCTRL4_WR_WR_TI_DLY_SHIFT 21
124#define TCTRL4_RDWR_RD_PI_MORE_DLY 0x00000000001f000UL0
125#define TCTRL4_RDWR_RD_PI_MORE_DLY_SHIFT 16
126#define TCTRL4_R 0x0000000000008000UL
127#define TCTRL4_R_SHIFT 15
128#define TCTRL4_SDRAM_MODE_REG_DATA 0x0000000000007fffUL
129#define TCTRL4_SDRAM_MODE_REG_DATA_SHIFT 0
130
131/* All 4 memory address decoding registers have the
132 * same layout.
133 */
134#define MEM_DECODE_VALID 0x8000000000000000UL /* Valid */
135#define MEM_DECODE_VALID_SHIFT 63
136#define MEM_DECODE_UK 0x001ffe0000000000UL /* Upper mask */
137#define MEM_DECODE_UK_SHIFT 41
138#define MEM_DECODE_UM 0x0000001ffff00000UL /* Upper match */
139#define MEM_DECODE_UM_SHIFT 20
140#define MEM_DECODE_LK 0x000000000003c000UL /* Lower mask */
141#define MEM_DECODE_LK_SHIFT 14
142#define MEM_DECODE_LM 0x0000000000000f00UL /* Lower match */
143#define MEM_DECODE_LM_SHIFT 8
144
145#define PA_UPPER_BITS 0x000007fffc000000UL
146#define PA_UPPER_BITS_SHIFT 26
147#define PA_LOWER_BITS 0x00000000000003c0UL
148#define PA_LOWER_BITS_SHIFT 6
149
150#define MACTRL_R0 0x8000000000000000UL
151#define MACTRL_R0_SHIFT 63
152#define MACTRL_ADDR_LE_PW 0x7000000000000000UL
153#define MACTRL_ADDR_LE_PW_SHIFT 60
154#define MACTRL_CMD_PW 0x0f00000000000000UL
155#define MACTRL_CMD_PW_SHIFT 56
156#define MACTRL_HALF_MODE_WR_MSEL_DLY 0x00fc000000000000UL
157#define MACTRL_HALF_MODE_WR_MSEL_DLY_SHIFT 50
158#define MACTRL_HALF_MODE_RD_MSEL_DLY 0x0003f00000000000UL
159#define MACTRL_HALF_MODE_RD_MSEL_DLY_SHIFT 44
160#define MACTRL_HALF_MODE_SDRAM_CTL_DLY 0x00000f0000000000UL
161#define MACTRL_HALF_MODE_SDRAM_CTL_DLY_SHIFT 40
162#define MACTRL_HALF_MODE_SDRAM_CLK_DLY 0x000000e000000000UL
163#define MACTRL_HALF_MODE_SDRAM_CLK_DLY_SHIFT 37
164#define MACTRL_R1 0x0000001000000000UL
165#define MACTRL_R1_SHIFT 36
166#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B3 0x0000000f00000000UL
167#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B3_SHIFT 32
168#define MACTRL_ENC_INTLV_B3 0x00000000f8000000UL
169#define MACTRL_ENC_INTLV_B3_SHIFT 27
170#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B2 0x0000000007800000UL
171#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B2_SHIFT 23
172#define MACTRL_ENC_INTLV_B2 0x00000000007c0000UL
173#define MACTRL_ENC_INTLV_B2_SHIFT 18
174#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B1 0x000000000003c000UL
175#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B1_SHIFT 14
176#define MACTRL_ENC_INTLV_B1 0x0000000000003e00UL
177#define MACTRL_ENC_INTLV_B1_SHIFT 9
178#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B0 0x00000000000001e0UL
179#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B0_SHIFT 5
180#define MACTRL_ENC_INTLV_B0 0x000000000000001fUL
181#define MACTRL_ENC_INTLV_B0_SHIFT 0
182
183#endif /* _SPARC64_CHMCTRL_H */
diff --git a/include/asm-sparc/clock.h b/include/asm-sparc/clock.h
deleted file mode 100644
index 2cf99dadec5..00000000000
--- a/include/asm-sparc/clock.h
+++ /dev/null
@@ -1,11 +0,0 @@
1/*
2 * clock.h: Definitions for clock operations on the Sparc.
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 */
6#ifndef _SPARC_CLOCK_H
7#define _SPARC_CLOCK_H
8
9/* Foo for now. */
10
11#endif /* !(_SPARC_CLOCK_H) */
diff --git a/include/asm-sparc/cmt.h b/include/asm-sparc/cmt.h
deleted file mode 100644
index 870db592857..00000000000
--- a/include/asm-sparc/cmt.h
+++ /dev/null
@@ -1,59 +0,0 @@
1#ifndef _SPARC64_CMT_H
2#define _SPARC64_CMT_H
3
4/* cmt.h: Chip Multi-Threading register definitions
5 *
6 * Copyright (C) 2004 David S. Miller (davem@redhat.com)
7 */
8
9/* ASI_CORE_ID - private */
10#define LP_ID 0x0000000000000010UL
11#define LP_ID_MAX 0x00000000003f0000UL
12#define LP_ID_ID 0x000000000000003fUL
13
14/* ASI_INTR_ID - private */
15#define LP_INTR_ID 0x0000000000000000UL
16#define LP_INTR_ID_ID 0x00000000000003ffUL
17
18/* ASI_CESR_ID - private */
19#define CESR_ID 0x0000000000000040UL
20#define CESR_ID_ID 0x00000000000000ffUL
21
22/* ASI_CORE_AVAILABLE - shared */
23#define LP_AVAIL 0x0000000000000000UL
24#define LP_AVAIL_1 0x0000000000000002UL
25#define LP_AVAIL_0 0x0000000000000001UL
26
27/* ASI_CORE_ENABLE_STATUS - shared */
28#define LP_ENAB_STAT 0x0000000000000010UL
29#define LP_ENAB_STAT_1 0x0000000000000002UL
30#define LP_ENAB_STAT_0 0x0000000000000001UL
31
32/* ASI_CORE_ENABLE - shared */
33#define LP_ENAB 0x0000000000000020UL
34#define LP_ENAB_1 0x0000000000000002UL
35#define LP_ENAB_0 0x0000000000000001UL
36
37/* ASI_CORE_RUNNING - shared */
38#define LP_RUNNING_RW 0x0000000000000050UL
39#define LP_RUNNING_W1S 0x0000000000000060UL
40#define LP_RUNNING_W1C 0x0000000000000068UL
41#define LP_RUNNING_1 0x0000000000000002UL
42#define LP_RUNNING_0 0x0000000000000001UL
43
44/* ASI_CORE_RUNNING_STAT - shared */
45#define LP_RUN_STAT 0x0000000000000058UL
46#define LP_RUN_STAT_1 0x0000000000000002UL
47#define LP_RUN_STAT_0 0x0000000000000001UL
48
49/* ASI_XIR_STEERING - shared */
50#define LP_XIR_STEER 0x0000000000000030UL
51#define LP_XIR_STEER_1 0x0000000000000002UL
52#define LP_XIR_STEER_0 0x0000000000000001UL
53
54/* ASI_CMT_ERROR_STEERING - shared */
55#define CMT_ER_STEER 0x0000000000000040UL
56#define CMT_ER_STEER_1 0x0000000000000002UL
57#define CMT_ER_STEER_0 0x0000000000000001UL
58
59#endif /* _SPARC64_CMT_H */
diff --git a/include/asm-sparc/compat.h b/include/asm-sparc/compat.h
deleted file mode 100644
index f260b58f5ce..00000000000
--- a/include/asm-sparc/compat.h
+++ /dev/null
@@ -1,243 +0,0 @@
1#ifndef _ASM_SPARC64_COMPAT_H
2#define _ASM_SPARC64_COMPAT_H
3/*
4 * Architecture specific compatibility types
5 */
6#include <linux/types.h>
7
8#define COMPAT_USER_HZ 100
9
10typedef u32 compat_size_t;
11typedef s32 compat_ssize_t;
12typedef s32 compat_time_t;
13typedef s32 compat_clock_t;
14typedef s32 compat_pid_t;
15typedef u16 __compat_uid_t;
16typedef u16 __compat_gid_t;
17typedef u32 __compat_uid32_t;
18typedef u32 __compat_gid32_t;
19typedef u16 compat_mode_t;
20typedef u32 compat_ino_t;
21typedef u16 compat_dev_t;
22typedef s32 compat_off_t;
23typedef s64 compat_loff_t;
24typedef s16 compat_nlink_t;
25typedef u16 compat_ipc_pid_t;
26typedef s32 compat_daddr_t;
27typedef u32 compat_caddr_t;
28typedef __kernel_fsid_t compat_fsid_t;
29typedef s32 compat_key_t;
30typedef s32 compat_timer_t;
31
32typedef s32 compat_int_t;
33typedef s32 compat_long_t;
34typedef s64 compat_s64;
35typedef u32 compat_uint_t;
36typedef u32 compat_ulong_t;
37typedef u64 compat_u64;
38
39struct compat_timespec {
40 compat_time_t tv_sec;
41 s32 tv_nsec;
42};
43
44struct compat_timeval {
45 compat_time_t tv_sec;
46 s32 tv_usec;
47};
48
49struct compat_stat {
50 compat_dev_t st_dev;
51 compat_ino_t st_ino;
52 compat_mode_t st_mode;
53 compat_nlink_t st_nlink;
54 __compat_uid_t st_uid;
55 __compat_gid_t st_gid;
56 compat_dev_t st_rdev;
57 compat_off_t st_size;
58 compat_time_t st_atime;
59 compat_ulong_t st_atime_nsec;
60 compat_time_t st_mtime;
61 compat_ulong_t st_mtime_nsec;
62 compat_time_t st_ctime;
63 compat_ulong_t st_ctime_nsec;
64 compat_off_t st_blksize;
65 compat_off_t st_blocks;
66 u32 __unused4[2];
67};
68
69struct compat_stat64 {
70 unsigned long long st_dev;
71
72 unsigned long long st_ino;
73
74 unsigned int st_mode;
75 unsigned int st_nlink;
76
77 unsigned int st_uid;
78 unsigned int st_gid;
79
80 unsigned long long st_rdev;
81
82 unsigned char __pad3[8];
83
84 long long st_size;
85 unsigned int st_blksize;
86
87 unsigned char __pad4[8];
88 unsigned int st_blocks;
89
90 unsigned int st_atime;
91 unsigned int st_atime_nsec;
92
93 unsigned int st_mtime;
94 unsigned int st_mtime_nsec;
95
96 unsigned int st_ctime;
97 unsigned int st_ctime_nsec;
98
99 unsigned int __unused4;
100 unsigned int __unused5;
101};
102
103struct compat_flock {
104 short l_type;
105 short l_whence;
106 compat_off_t l_start;
107 compat_off_t l_len;
108 compat_pid_t l_pid;
109 short __unused;
110};
111
112#define F_GETLK64 12
113#define F_SETLK64 13
114#define F_SETLKW64 14
115
116struct compat_flock64 {
117 short l_type;
118 short l_whence;
119 compat_loff_t l_start;
120 compat_loff_t l_len;
121 compat_pid_t l_pid;
122 short __unused;
123};
124
125struct compat_statfs {
126 int f_type;
127 int f_bsize;
128 int f_blocks;
129 int f_bfree;
130 int f_bavail;
131 int f_files;
132 int f_ffree;
133 compat_fsid_t f_fsid;
134 int f_namelen; /* SunOS ignores this field. */
135 int f_frsize;
136 int f_spare[5];
137};
138
139#define COMPAT_RLIM_INFINITY 0x7fffffff
140
141typedef u32 compat_old_sigset_t;
142
143#define _COMPAT_NSIG 64
144#define _COMPAT_NSIG_BPW 32
145
146typedef u32 compat_sigset_word;
147
148#define COMPAT_OFF_T_MAX 0x7fffffff
149#define COMPAT_LOFF_T_MAX 0x7fffffffffffffffL
150
151/*
152 * A pointer passed in from user mode. This should not
153 * be used for syscall parameters, just declare them
154 * as pointers because the syscall entry code will have
155 * appropriately converted them already.
156 */
157typedef u32 compat_uptr_t;
158
159static inline void __user *compat_ptr(compat_uptr_t uptr)
160{
161 return (void __user *)(unsigned long)uptr;
162}
163
164static inline compat_uptr_t ptr_to_compat(void __user *uptr)
165{
166 return (u32)(unsigned long)uptr;
167}
168
169static inline void __user *compat_alloc_user_space(long len)
170{
171 struct pt_regs *regs = current_thread_info()->kregs;
172 unsigned long usp = regs->u_regs[UREG_I6];
173
174 if (!(test_thread_flag(TIF_32BIT)))
175 usp += STACK_BIAS;
176 else
177 usp &= 0xffffffffUL;
178
179 usp -= len;
180 usp &= ~0x7UL;
181
182 return (void __user *) usp;
183}
184
185struct compat_ipc64_perm {
186 compat_key_t key;
187 __compat_uid32_t uid;
188 __compat_gid32_t gid;
189 __compat_uid32_t cuid;
190 __compat_gid32_t cgid;
191 unsigned short __pad1;
192 compat_mode_t mode;
193 unsigned short __pad2;
194 unsigned short seq;
195 unsigned long __unused1; /* yes they really are 64bit pads */
196 unsigned long __unused2;
197};
198
199struct compat_semid64_ds {
200 struct compat_ipc64_perm sem_perm;
201 unsigned int __pad1;
202 compat_time_t sem_otime;
203 unsigned int __pad2;
204 compat_time_t sem_ctime;
205 u32 sem_nsems;
206 u32 __unused1;
207 u32 __unused2;
208};
209
210struct compat_msqid64_ds {
211 struct compat_ipc64_perm msg_perm;
212 unsigned int __pad1;
213 compat_time_t msg_stime;
214 unsigned int __pad2;
215 compat_time_t msg_rtime;
216 unsigned int __pad3;
217 compat_time_t msg_ctime;
218 unsigned int msg_cbytes;
219 unsigned int msg_qnum;
220 unsigned int msg_qbytes;
221 compat_pid_t msg_lspid;
222 compat_pid_t msg_lrpid;
223 unsigned int __unused1;
224 unsigned int __unused2;
225};
226
227struct compat_shmid64_ds {
228 struct compat_ipc64_perm shm_perm;
229 unsigned int __pad1;
230 compat_time_t shm_atime;
231 unsigned int __pad2;
232 compat_time_t shm_dtime;
233 unsigned int __pad3;
234 compat_time_t shm_ctime;
235 compat_size_t shm_segsz;
236 compat_pid_t shm_cpid;
237 compat_pid_t shm_lpid;
238 unsigned int shm_nattch;
239 unsigned int __unused1;
240 unsigned int __unused2;
241};
242
243#endif /* _ASM_SPARC64_COMPAT_H */
diff --git a/include/asm-sparc/compat_signal.h b/include/asm-sparc/compat_signal.h
deleted file mode 100644
index b759eab9b51..00000000000
--- a/include/asm-sparc/compat_signal.h
+++ /dev/null
@@ -1,29 +0,0 @@
1#ifndef _COMPAT_SIGNAL_H
2#define _COMPAT_SIGNAL_H
3
4#include <linux/compat.h>
5#include <asm/signal.h>
6
7#ifdef CONFIG_COMPAT
8struct __new_sigaction32 {
9 unsigned sa_handler;
10 unsigned int sa_flags;
11 unsigned sa_restorer; /* not used by Linux/SPARC yet */
12 compat_sigset_t sa_mask;
13};
14
15struct __old_sigaction32 {
16 unsigned sa_handler;
17 compat_old_sigset_t sa_mask;
18 unsigned int sa_flags;
19 unsigned sa_restorer; /* not used by Linux/SPARC yet */
20};
21
22typedef struct sigaltstack32 {
23 u32 ss_sp;
24 int ss_flags;
25 compat_size_t ss_size;
26} stack_t32;
27#endif
28
29#endif /* !(_COMPAT_SIGNAL_H) */
diff --git a/include/asm-sparc/contregs.h b/include/asm-sparc/contregs.h
deleted file mode 100644
index 48fa8a4ef35..00000000000
--- a/include/asm-sparc/contregs.h
+++ /dev/null
@@ -1,53 +0,0 @@
1#ifndef _SPARC_CONTREGS_H
2#define _SPARC_CONTREGS_H
3
4/* contregs.h: Addresses of registers in the ASI_CONTROL alternate address
5 * space. These are for the mmu's context register, etc.
6 *
7 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
8 */
9
10/* 3=sun3
11 4=sun4 (as in sun4 sysmaint student book)
12 c=sun4c (according to davem) */
13
14#define AC_IDPROM 0x00000000 /* 34 ID PROM, R/O, byte, 32 bytes */
15#define AC_PAGEMAP 0x10000000 /* 3 Pagemap R/W, long */
16#define AC_SEGMAP 0x20000000 /* 3 Segment map, byte */
17#define AC_CONTEXT 0x30000000 /* 34c current mmu-context */
18#define AC_SENABLE 0x40000000 /* 34c system dvma/cache/reset enable reg*/
19#define AC_UDVMA_ENB 0x50000000 /* 34 Not used on Sun boards, byte */
20#define AC_BUS_ERROR 0x60000000 /* 34 Not cleared on read, byte. */
21#define AC_SYNC_ERR 0x60000000 /* c fault type */
22#define AC_SYNC_VA 0x60000004 /* c fault virtual address */
23#define AC_ASYNC_ERR 0x60000008 /* c asynchronous fault type */
24#define AC_ASYNC_VA 0x6000000c /* c async fault virtual address */
25#define AC_LEDS 0x70000000 /* 34 Zero turns on LEDs, byte */
26#define AC_CACHETAGS 0x80000000 /* 34c direct access to the VAC tags */
27#define AC_CACHEDDATA 0x90000000 /* 3 c direct access to the VAC data */
28#define AC_UDVMA_MAP 0xD0000000 /* 4 Not used on Sun boards, byte */
29#define AC_VME_VECTOR 0xE0000000 /* 4 For non-Autovector VME, byte */
30#define AC_BOOT_SCC 0xF0000000 /* 34 bypass to access Zilog 8530. byte.*/
31
32/* s=Swift, h=Ross_HyperSPARC, v=TI_Viking, t=Tsunami, r=Ross_Cypress */
33#define AC_M_PCR 0x0000 /* shv Processor Control Reg */
34#define AC_M_CTPR 0x0100 /* shv Context Table Pointer Reg */
35#define AC_M_CXR 0x0200 /* shv Context Register */
36#define AC_M_SFSR 0x0300 /* shv Synchronous Fault Status Reg */
37#define AC_M_SFAR 0x0400 /* shv Synchronous Fault Address Reg */
38#define AC_M_AFSR 0x0500 /* hv Asynchronous Fault Status Reg */
39#define AC_M_AFAR 0x0600 /* hv Asynchronous Fault Address Reg */
40#define AC_M_RESET 0x0700 /* hv Reset Reg */
41#define AC_M_RPR 0x1000 /* hv Root Pointer Reg */
42#define AC_M_TSUTRCR 0x1000 /* s TLB Replacement Ctrl Reg */
43#define AC_M_IAPTP 0x1100 /* hv Instruction Access PTP */
44#define AC_M_DAPTP 0x1200 /* hv Data Access PTP */
45#define AC_M_ITR 0x1300 /* hv Index Tag Register */
46#define AC_M_TRCR 0x1400 /* hv TLB Replacement Control Reg */
47#define AC_M_SFSRX 0x1300 /* s Synch Fault Status Reg prim */
48#define AC_M_SFARX 0x1400 /* s Synch Fault Address Reg prim */
49#define AC_M_RPR1 0x1500 /* h Root Pointer Reg (entry 2) */
50#define AC_M_IAPTP1 0x1600 /* h Instruction Access PTP (entry 2) */
51#define AC_M_DAPTP1 0x1700 /* h Data Access PTP (entry 2) */
52
53#endif /* _SPARC_CONTREGS_H */
diff --git a/include/asm-sparc/cpudata.h b/include/asm-sparc/cpudata.h
deleted file mode 100644
index b76fac0c8d8..00000000000
--- a/include/asm-sparc/cpudata.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_CPUDATA_H
2#define ___ASM_SPARC_CPUDATA_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/cpudata_64.h>
5#else
6#include <asm-sparc/cpudata_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/cpudata_32.h b/include/asm-sparc/cpudata_32.h
deleted file mode 100644
index a2c4d51d36c..00000000000
--- a/include/asm-sparc/cpudata_32.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/* cpudata.h: Per-cpu parameters.
2 *
3 * Copyright (C) 2004 Keith M Wesolowski (wesolows@foobazco.org)
4 *
5 * Based on include/asm-sparc64/cpudata.h and Linux 2.4 smp.h
6 * both (C) David S. Miller.
7 */
8
9#ifndef _SPARC_CPUDATA_H
10#define _SPARC_CPUDATA_H
11
12#include <linux/percpu.h>
13
14typedef struct {
15 unsigned long udelay_val;
16 unsigned long clock_tick;
17 unsigned int multiplier;
18 unsigned int counter;
19 int prom_node;
20 int mid;
21 int next;
22} cpuinfo_sparc;
23
24DECLARE_PER_CPU(cpuinfo_sparc, __cpu_data);
25#define cpu_data(__cpu) per_cpu(__cpu_data, (__cpu))
26
27#endif /* _SPARC_CPUDATA_H */
diff --git a/include/asm-sparc/cpudata_64.h b/include/asm-sparc/cpudata_64.h
deleted file mode 100644
index 532975ecfe1..00000000000
--- a/include/asm-sparc/cpudata_64.h
+++ /dev/null
@@ -1,240 +0,0 @@
1/* cpudata.h: Per-cpu parameters.
2 *
3 * Copyright (C) 2003, 2005, 2006 David S. Miller (davem@davemloft.net)
4 */
5
6#ifndef _SPARC64_CPUDATA_H
7#define _SPARC64_CPUDATA_H
8
9#include <asm/hypervisor.h>
10#include <asm/asi.h>
11
12#ifndef __ASSEMBLY__
13
14#include <linux/percpu.h>
15#include <linux/threads.h>
16
17typedef struct {
18 /* Dcache line 1 */
19 unsigned int __softirq_pending; /* must be 1st, see rtrap.S */
20 unsigned int __pad0;
21 unsigned long clock_tick; /* %tick's per second */
22 unsigned long __pad;
23 unsigned int __pad1;
24 unsigned int __pad2;
25
26 /* Dcache line 2, rarely used */
27 unsigned int dcache_size;
28 unsigned int dcache_line_size;
29 unsigned int icache_size;
30 unsigned int icache_line_size;
31 unsigned int ecache_size;
32 unsigned int ecache_line_size;
33 int core_id;
34 int proc_id;
35} cpuinfo_sparc;
36
37DECLARE_PER_CPU(cpuinfo_sparc, __cpu_data);
38#define cpu_data(__cpu) per_cpu(__cpu_data, (__cpu))
39#define local_cpu_data() __get_cpu_var(__cpu_data)
40
41/* Trap handling code needs to get at a few critical values upon
42 * trap entry and to process TSB misses. These cannot be in the
43 * per_cpu() area as we really need to lock them into the TLB and
44 * thus make them part of the main kernel image. As a result we
45 * try to make this as small as possible.
46 *
47 * This is padded out and aligned to 64-bytes to avoid false sharing
48 * on SMP.
49 */
50
51/* If you modify the size of this structure, please update
52 * TRAP_BLOCK_SZ_SHIFT below.
53 */
54struct thread_info;
55struct trap_per_cpu {
56/* D-cache line 1: Basic thread information, cpu and device mondo queues */
57 struct thread_info *thread;
58 unsigned long pgd_paddr;
59 unsigned long cpu_mondo_pa;
60 unsigned long dev_mondo_pa;
61
62/* D-cache line 2: Error Mondo Queue and kernel buffer pointers */
63 unsigned long resum_mondo_pa;
64 unsigned long resum_kernel_buf_pa;
65 unsigned long nonresum_mondo_pa;
66 unsigned long nonresum_kernel_buf_pa;
67
68/* Dcache lines 3, 4, 5, and 6: Hypervisor Fault Status */
69 struct hv_fault_status fault_info;
70
71/* Dcache line 7: Physical addresses of CPU send mondo block and CPU list. */
72 unsigned long cpu_mondo_block_pa;
73 unsigned long cpu_list_pa;
74 unsigned long tsb_huge;
75 unsigned long tsb_huge_temp;
76
77/* Dcache line 8: IRQ work list, and keep trap_block a power-of-2 in size. */
78 unsigned long irq_worklist_pa;
79 unsigned int cpu_mondo_qmask;
80 unsigned int dev_mondo_qmask;
81 unsigned int resum_qmask;
82 unsigned int nonresum_qmask;
83 void *hdesc;
84} __attribute__((aligned(64)));
85extern struct trap_per_cpu trap_block[NR_CPUS];
86extern void init_cur_cpu_trap(struct thread_info *);
87extern void setup_tba(void);
88extern int ncpus_probed;
89extern void __init cpu_probe(void);
90extern const struct seq_operations cpuinfo_op;
91
92extern unsigned long real_hard_smp_processor_id(void);
93
94struct cpuid_patch_entry {
95 unsigned int addr;
96 unsigned int cheetah_safari[4];
97 unsigned int cheetah_jbus[4];
98 unsigned int starfire[4];
99 unsigned int sun4v[4];
100};
101extern struct cpuid_patch_entry __cpuid_patch, __cpuid_patch_end;
102
103struct sun4v_1insn_patch_entry {
104 unsigned int addr;
105 unsigned int insn;
106};
107extern struct sun4v_1insn_patch_entry __sun4v_1insn_patch,
108 __sun4v_1insn_patch_end;
109
110struct sun4v_2insn_patch_entry {
111 unsigned int addr;
112 unsigned int insns[2];
113};
114extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
115 __sun4v_2insn_patch_end;
116
117#endif /* !(__ASSEMBLY__) */
118
119#define TRAP_PER_CPU_THREAD 0x00
120#define TRAP_PER_CPU_PGD_PADDR 0x08
121#define TRAP_PER_CPU_CPU_MONDO_PA 0x10
122#define TRAP_PER_CPU_DEV_MONDO_PA 0x18
123#define TRAP_PER_CPU_RESUM_MONDO_PA 0x20
124#define TRAP_PER_CPU_RESUM_KBUF_PA 0x28
125#define TRAP_PER_CPU_NONRESUM_MONDO_PA 0x30
126#define TRAP_PER_CPU_NONRESUM_KBUF_PA 0x38
127#define TRAP_PER_CPU_FAULT_INFO 0x40
128#define TRAP_PER_CPU_CPU_MONDO_BLOCK_PA 0xc0
129#define TRAP_PER_CPU_CPU_LIST_PA 0xc8
130#define TRAP_PER_CPU_TSB_HUGE 0xd0
131#define TRAP_PER_CPU_TSB_HUGE_TEMP 0xd8
132#define TRAP_PER_CPU_IRQ_WORKLIST_PA 0xe0
133#define TRAP_PER_CPU_CPU_MONDO_QMASK 0xe8
134#define TRAP_PER_CPU_DEV_MONDO_QMASK 0xec
135#define TRAP_PER_CPU_RESUM_QMASK 0xf0
136#define TRAP_PER_CPU_NONRESUM_QMASK 0xf4
137
138#define TRAP_BLOCK_SZ_SHIFT 8
139
140#include <asm/scratchpad.h>
141
142#define __GET_CPUID(REG) \
143 /* Spitfire implementation (default). */ \
144661: ldxa [%g0] ASI_UPA_CONFIG, REG; \
145 srlx REG, 17, REG; \
146 and REG, 0x1f, REG; \
147 nop; \
148 .section .cpuid_patch, "ax"; \
149 /* Instruction location. */ \
150 .word 661b; \
151 /* Cheetah Safari implementation. */ \
152 ldxa [%g0] ASI_SAFARI_CONFIG, REG; \
153 srlx REG, 17, REG; \
154 and REG, 0x3ff, REG; \
155 nop; \
156 /* Cheetah JBUS implementation. */ \
157 ldxa [%g0] ASI_JBUS_CONFIG, REG; \
158 srlx REG, 17, REG; \
159 and REG, 0x1f, REG; \
160 nop; \
161 /* Starfire implementation. */ \
162 sethi %hi(0x1fff40000d0 >> 9), REG; \
163 sllx REG, 9, REG; \
164 or REG, 0xd0, REG; \
165 lduwa [REG] ASI_PHYS_BYPASS_EC_E, REG;\
166 /* sun4v implementation. */ \
167 mov SCRATCHPAD_CPUID, REG; \
168 ldxa [REG] ASI_SCRATCHPAD, REG; \
169 nop; \
170 nop; \
171 .previous;
172
173#ifdef CONFIG_SMP
174
175#define TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
176 __GET_CPUID(TMP) \
177 sethi %hi(trap_block), DEST; \
178 sllx TMP, TRAP_BLOCK_SZ_SHIFT, TMP; \
179 or DEST, %lo(trap_block), DEST; \
180 add DEST, TMP, DEST; \
181
182/* Clobbers TMP, current address space PGD phys address into DEST. */
183#define TRAP_LOAD_PGD_PHYS(DEST, TMP) \
184 TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
185 ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
186
187/* Clobbers TMP, loads local processor's IRQ work area into DEST. */
188#define TRAP_LOAD_IRQ_WORK_PA(DEST, TMP) \
189 TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
190 add DEST, TRAP_PER_CPU_IRQ_WORKLIST_PA, DEST;
191
192/* Clobbers TMP, loads DEST with current thread info pointer. */
193#define TRAP_LOAD_THREAD_REG(DEST, TMP) \
194 TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
195 ldx [DEST + TRAP_PER_CPU_THREAD], DEST;
196
197/* Given the current thread info pointer in THR, load the per-cpu
198 * area base of the current processor into DEST. REG1, REG2, and REG3 are
199 * clobbered.
200 *
201 * You absolutely cannot use DEST as a temporary in this code. The
202 * reason is that traps can happen during execution, and return from
203 * trap will load the fully resolved DEST per-cpu base. This can corrupt
204 * the calculations done by the macro mid-stream.
205 */
206#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3) \
207 lduh [THR + TI_CPU], REG1; \
208 sethi %hi(__per_cpu_shift), REG3; \
209 sethi %hi(__per_cpu_base), REG2; \
210 ldx [REG3 + %lo(__per_cpu_shift)], REG3; \
211 ldx [REG2 + %lo(__per_cpu_base)], REG2; \
212 sllx REG1, REG3, REG3; \
213 add REG3, REG2, DEST;
214
215#else
216
217#define TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
218 sethi %hi(trap_block), DEST; \
219 or DEST, %lo(trap_block), DEST; \
220
221/* Uniprocessor versions, we know the cpuid is zero. */
222#define TRAP_LOAD_PGD_PHYS(DEST, TMP) \
223 TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
224 ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
225
226/* Clobbers TMP, loads local processor's IRQ work area into DEST. */
227#define TRAP_LOAD_IRQ_WORK_PA(DEST, TMP) \
228 TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
229 add DEST, TRAP_PER_CPU_IRQ_WORKLIST_PA, DEST;
230
231#define TRAP_LOAD_THREAD_REG(DEST, TMP) \
232 TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
233 ldx [DEST + TRAP_PER_CPU_THREAD], DEST;
234
235/* No per-cpu areas on uniprocessor, so no need to load DEST. */
236#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)
237
238#endif /* !(CONFIG_SMP) */
239
240#endif /* _SPARC64_CPUDATA_H */
diff --git a/include/asm-sparc/cputime.h b/include/asm-sparc/cputime.h
deleted file mode 100644
index 1a642b81e01..00000000000
--- a/include/asm-sparc/cputime.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef __SPARC_CPUTIME_H
2#define __SPARC_CPUTIME_H
3
4#include <asm-generic/cputime.h>
5
6#endif /* __SPARC_CPUTIME_H */
diff --git a/include/asm-sparc/current.h b/include/asm-sparc/current.h
deleted file mode 100644
index 8a1d9d6643b..00000000000
--- a/include/asm-sparc/current.h
+++ /dev/null
@@ -1,34 +0,0 @@
1/* include/asm-sparc/current.h
2 *
3 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
4 * Copyright (C) 2002 Pete Zaitcev (zaitcev@yahoo.com)
5 * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
6 *
7 * Derived from "include/asm-s390/current.h" by
8 * Martin Schwidefsky (schwidefsky@de.ibm.com)
9 * Derived from "include/asm-i386/current.h"
10*/
11#ifndef _SPARC_CURRENT_H
12#define _SPARC_CURRENT_H
13
14#include <linux/thread_info.h>
15
16#ifdef CONFIG_SPARC64
17register struct task_struct *current asm("g4");
18#endif
19
20#ifdef CONFIG_SPARC32
21/* We might want to consider using %g4 like sparc64 to shave a few cycles.
22 *
23 * Two stage process (inline + #define) for type-checking.
24 * We also obfuscate get_current() to check if anyone used that by mistake.
25 */
26struct task_struct;
27static inline struct task_struct *__get_current(void)
28{
29 return current_thread_info()->task;
30}
31#define current __get_current()
32#endif
33
34#endif /* !(_SPARC_CURRENT_H) */
diff --git a/include/asm-sparc/cypress.h b/include/asm-sparc/cypress.h
deleted file mode 100644
index 95e9772ea39..00000000000
--- a/include/asm-sparc/cypress.h
+++ /dev/null
@@ -1,79 +0,0 @@
1/*
2 * cypress.h: Cypress module specific definitions and defines.
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 */
6
7#ifndef _SPARC_CYPRESS_H
8#define _SPARC_CYPRESS_H
9
10/* Cypress chips have %psr 'impl' of '0001' and 'vers' of '0001'. */
11
12/* The MMU control register fields on the Sparc Cypress 604/605 MMU's.
13 *
14 * ---------------------------------------------------------------
15 * |implvers| MCA | MCM |MV| MID |BM| C|RSV|MR|CM|CL|CE|RSV|NF|ME|
16 * ---------------------------------------------------------------
17 * 31 24 23-22 21-20 19 18-15 14 13 12 11 10 9 8 7-2 1 0
18 *
19 * MCA: MultiChip Access -- Used for configuration of multiple
20 * CY7C604/605 cache units.
21 * MCM: MultiChip Mask -- Again, for multiple cache unit config.
22 * MV: MultiChip Valid -- Indicates MCM and MCA have valid settings.
23 * MID: ModuleID -- Unique processor ID for MBus transactions. (605 only)
24 * BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode
25 * C: Cacheable -- Indicates whether accesses are cacheable while
26 * the MMU is off. 0=no 1=yes
27 * MR: MemoryReflection -- Indicates whether the bus attached to the
28 * MBus supports memory reflection. 0=no 1=yes (605 only)
29 * CM: CacheMode -- Indicates whether the cache is operating in write
30 * through or copy-back mode. 0=write-through 1=copy-back
31 * CL: CacheLock -- Indicates if the entire cache is locked or not.
32 * 0=not-locked 1=locked (604 only)
33 * CE: CacheEnable -- Is the virtual cache on? 0=no 1=yes
34 * NF: NoFault -- Do faults generate traps? 0=yes 1=no
35 * ME: MmuEnable -- Is the MMU doing translations? 0=no 1=yes
36 */
37
38#define CYPRESS_MCA 0x00c00000
39#define CYPRESS_MCM 0x00300000
40#define CYPRESS_MVALID 0x00080000
41#define CYPRESS_MIDMASK 0x00078000 /* Only on 605 */
42#define CYPRESS_BMODE 0x00004000
43#define CYPRESS_ACENABLE 0x00002000
44#define CYPRESS_MRFLCT 0x00000800 /* Only on 605 */
45#define CYPRESS_CMODE 0x00000400
46#define CYPRESS_CLOCK 0x00000200 /* Only on 604 */
47#define CYPRESS_CENABLE 0x00000100
48#define CYPRESS_NFAULT 0x00000002
49#define CYPRESS_MENABLE 0x00000001
50
51static inline void cypress_flush_page(unsigned long page)
52{
53 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
54 "r" (page), "i" (ASI_M_FLUSH_PAGE));
55}
56
57static inline void cypress_flush_segment(unsigned long addr)
58{
59 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
60 "r" (addr), "i" (ASI_M_FLUSH_SEG));
61}
62
63static inline void cypress_flush_region(unsigned long addr)
64{
65 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
66 "r" (addr), "i" (ASI_M_FLUSH_REGION));
67}
68
69static inline void cypress_flush_context(void)
70{
71 __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t" : :
72 "i" (ASI_M_FLUSH_CTX));
73}
74
75/* XXX Displacement flushes for buggy chips and initial testing
76 * XXX go here.
77 */
78
79#endif /* !(_SPARC_CYPRESS_H) */
diff --git a/include/asm-sparc/dcr.h b/include/asm-sparc/dcr.h
deleted file mode 100644
index 620c9ba642e..00000000000
--- a/include/asm-sparc/dcr.h
+++ /dev/null
@@ -1,14 +0,0 @@
1#ifndef _SPARC64_DCR_H
2#define _SPARC64_DCR_H
3
4/* UltraSparc-III/III+ Dispatch Control Register, ASR 0x12 */
5#define DCR_DPE 0x0000000000001000 /* III+: D$ Parity Error Enable */
6#define DCR_OBS 0x0000000000000fc0 /* Observability Bus Controls */
7#define DCR_BPE 0x0000000000000020 /* Branch Predict Enable */
8#define DCR_RPE 0x0000000000000010 /* Return Address Prediction Enable */
9#define DCR_SI 0x0000000000000008 /* Single Instruction Disable */
10#define DCR_IPE 0x0000000000000004 /* III+: I$ Parity Error Enable */
11#define DCR_IFPOE 0x0000000000000002 /* IRQ FP Operation Enable */
12#define DCR_MS 0x0000000000000001 /* Multi-Scalar dispatch */
13
14#endif /* _SPARC64_DCR_H */
diff --git a/include/asm-sparc/dcu.h b/include/asm-sparc/dcu.h
deleted file mode 100644
index 0f704e106a1..00000000000
--- a/include/asm-sparc/dcu.h
+++ /dev/null
@@ -1,27 +0,0 @@
1#ifndef _SPARC64_DCU_H
2#define _SPARC64_DCU_H
3
4#include <linux/const.h>
5
6/* UltraSparc-III Data Cache Unit Control Register */
7#define DCU_CP _AC(0x0002000000000000,UL) /* Phys Cache Enable w/o mmu */
8#define DCU_CV _AC(0x0001000000000000,UL) /* Virt Cache Enable w/o mmu */
9#define DCU_ME _AC(0x0000800000000000,UL) /* NC-store Merging Enable */
10#define DCU_RE _AC(0x0000400000000000,UL) /* RAW bypass Enable */
11#define DCU_PE _AC(0x0000200000000000,UL) /* PCache Enable */
12#define DCU_HPE _AC(0x0000100000000000,UL) /* HW prefetch Enable */
13#define DCU_SPE _AC(0x0000080000000000,UL) /* SW prefetch Enable */
14#define DCU_SL _AC(0x0000040000000000,UL) /* Secondary ld-steering Enab*/
15#define DCU_WE _AC(0x0000020000000000,UL) /* WCache enable */
16#define DCU_PM _AC(0x000001fe00000000,UL) /* PA Watchpoint Byte Mask */
17#define DCU_VM _AC(0x00000001fe000000,UL) /* VA Watchpoint Byte Mask */
18#define DCU_PR _AC(0x0000000001000000,UL) /* PA Watchpoint Read Enable */
19#define DCU_PW _AC(0x0000000000800000,UL) /* PA Watchpoint Write Enable*/
20#define DCU_VR _AC(0x0000000000400000,UL) /* VA Watchpoint Read Enable */
21#define DCU_VW _AC(0x0000000000200000,UL) /* VA Watchpoint Write Enable*/
22#define DCU_DM _AC(0x0000000000000008,UL) /* DMMU Enable */
23#define DCU_IM _AC(0x0000000000000004,UL) /* IMMU Enable */
24#define DCU_DC _AC(0x0000000000000002,UL) /* Data Cache Enable */
25#define DCU_IC _AC(0x0000000000000001,UL) /* Instruction Cache Enable */
26
27#endif /* _SPARC64_DCU_H */
diff --git a/include/asm-sparc/delay.h b/include/asm-sparc/delay.h
deleted file mode 100644
index 6210a3ce975..00000000000
--- a/include/asm-sparc/delay.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_DELAY_H
2#define ___ASM_SPARC_DELAY_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/delay_64.h>
5#else
6#include <asm-sparc/delay_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/delay_32.h b/include/asm-sparc/delay_32.h
deleted file mode 100644
index bc9aba2bead..00000000000
--- a/include/asm-sparc/delay_32.h
+++ /dev/null
@@ -1,34 +0,0 @@
1/*
2 * delay.h: Linux delay routines on the Sparc.
3 *
4 * Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu).
5 */
6
7#ifndef __SPARC_DELAY_H
8#define __SPARC_DELAY_H
9
10#include <asm/cpudata.h>
11
12static inline void __delay(unsigned long loops)
13{
14 __asm__ __volatile__("cmp %0, 0\n\t"
15 "1: bne 1b\n\t"
16 "subcc %0, 1, %0\n" :
17 "=&r" (loops) :
18 "0" (loops) :
19 "cc");
20}
21
22/* This is too messy with inline asm on the Sparc. */
23extern void __udelay(unsigned long usecs, unsigned long lpj);
24extern void __ndelay(unsigned long nsecs, unsigned long lpj);
25
26#ifdef CONFIG_SMP
27#define __udelay_val cpu_data(smp_processor_id()).udelay_val
28#else /* SMP */
29#define __udelay_val loops_per_jiffy
30#endif /* SMP */
31#define udelay(__usecs) __udelay(__usecs, __udelay_val)
32#define ndelay(__nsecs) __ndelay(__nsecs, __udelay_val)
33
34#endif /* defined(__SPARC_DELAY_H) */
diff --git a/include/asm-sparc/delay_64.h b/include/asm-sparc/delay_64.h
deleted file mode 100644
index a77aa622d76..00000000000
--- a/include/asm-sparc/delay_64.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/* delay.h: Linux delay routines on sparc64.
2 *
3 * Copyright (C) 1996, 2004, 2007 David S. Miller (davem@davemloft.net).
4 */
5
6#ifndef _SPARC64_DELAY_H
7#define _SPARC64_DELAY_H
8
9#ifndef __ASSEMBLY__
10
11extern void __delay(unsigned long loops);
12extern void udelay(unsigned long usecs);
13#define mdelay(n) udelay((n) * 1000)
14
15#endif /* !__ASSEMBLY__ */
16
17#endif /* _SPARC64_DELAY_H */
diff --git a/include/asm-sparc/device.h b/include/asm-sparc/device.h
deleted file mode 100644
index 19790eb99cc..00000000000
--- a/include/asm-sparc/device.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * Arch specific extensions to struct device
3 *
4 * This file is released under the GPLv2
5 */
6#ifndef _ASM_SPARC_DEVICE_H
7#define _ASM_SPARC_DEVICE_H
8
9struct device_node;
10struct of_device;
11
12struct dev_archdata {
13 void *iommu;
14 void *stc;
15 void *host_controller;
16
17 struct device_node *prom_node;
18 struct of_device *op;
19
20 int numa_node;
21};
22
23#endif /* _ASM_SPARC_DEVICE_H */
diff --git a/include/asm-sparc/display7seg.h b/include/asm-sparc/display7seg.h
deleted file mode 100644
index 86d4a901df2..00000000000
--- a/include/asm-sparc/display7seg.h
+++ /dev/null
@@ -1,79 +0,0 @@
1/*
2 *
3 * display7seg - Driver interface for the 7-segment display
4 * present on Sun Microsystems CP1400 and CP1500
5 *
6 * Copyright (c) 2000 Eric Brower <ebrower@usa.net>
7 *
8 */
9
10#ifndef __display7seg_h__
11#define __display7seg_h__
12
13#define D7S_IOC 'p'
14
15#define D7SIOCRD _IOR(D7S_IOC, 0x45, int) /* Read device state */
16#define D7SIOCWR _IOW(D7S_IOC, 0x46, int) /* Write device state */
17#define D7SIOCTM _IO (D7S_IOC, 0x47) /* Translate mode (FLIP)*/
18
19/*
20 * ioctl flag definitions
21 *
22 * POINT - Toggle decimal point (0=absent 1=present)
23 * ALARM - Toggle alarm LED (0=green 1=red)
24 * FLIP - Toggle inverted mode (0=normal 1=flipped)
25 * bits 0-4 - Character displayed (see definitions below)
26 *
27 * Display segments are defined as follows,
28 * subject to D7S_FLIP register state:
29 *
30 * a
31 * ---
32 * f| |b
33 * -g-
34 * e| |c
35 * ---
36 * d
37 */
38
39#define D7S_POINT (1 << 7) /* Decimal point*/
40#define D7S_ALARM (1 << 6) /* Alarm LED */
41#define D7S_FLIP (1 << 5) /* Flip display */
42
43#define D7S_0 0x00 /* Numerals 0-9 */
44#define D7S_1 0x01
45#define D7S_2 0x02
46#define D7S_3 0x03
47#define D7S_4 0x04
48#define D7S_5 0x05
49#define D7S_6 0x06
50#define D7S_7 0x07
51#define D7S_8 0x08
52#define D7S_9 0x09
53#define D7S_A 0x0A /* Letters A-F, H, L, P */
54#define D7S_B 0x0B
55#define D7S_C 0x0C
56#define D7S_D 0x0D
57#define D7S_E 0x0E
58#define D7S_F 0x0F
59#define D7S_H 0x10
60#define D7S_E2 0x11
61#define D7S_L 0x12
62#define D7S_P 0x13
63#define D7S_SEGA 0x14 /* Individual segments */
64#define D7S_SEGB 0x15
65#define D7S_SEGC 0x16
66#define D7S_SEGD 0x17
67#define D7S_SEGE 0x18
68#define D7S_SEGF 0x19
69#define D7S_SEGG 0x1A
70#define D7S_SEGABFG 0x1B /* Segment groupings */
71#define D7S_SEGCDEG 0x1C
72#define D7S_SEGBCEF 0x1D
73#define D7S_SEGADG 0x1E
74#define D7S_BLANK 0x1F /* Clear all segments */
75
76#define D7S_MIN_VAL 0x0
77#define D7S_MAX_VAL 0x1F
78
79#endif /* ifndef __display7seg_h__ */
diff --git a/include/asm-sparc/div64.h b/include/asm-sparc/div64.h
deleted file mode 100644
index 6cd978cefb2..00000000000
--- a/include/asm-sparc/div64.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/div64.h>
diff --git a/include/asm-sparc/dma-mapping.h b/include/asm-sparc/dma-mapping.h
deleted file mode 100644
index 7483504259c..00000000000
--- a/include/asm-sparc/dma-mapping.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_DMA_MAPPING_H
2#define ___ASM_SPARC_DMA_MAPPING_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/dma-mapping_64.h>
5#else
6#include <asm-sparc/dma-mapping_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/dma-mapping_32.h b/include/asm-sparc/dma-mapping_32.h
deleted file mode 100644
index f3a641e6b2c..00000000000
--- a/include/asm-sparc/dma-mapping_32.h
+++ /dev/null
@@ -1,11 +0,0 @@
1#ifndef _ASM_SPARC_DMA_MAPPING_H
2#define _ASM_SPARC_DMA_MAPPING_H
3
4
5#ifdef CONFIG_PCI
6#include <asm-generic/dma-mapping.h>
7#else
8#include <asm-generic/dma-mapping-broken.h>
9#endif /* PCI */
10
11#endif /* _ASM_SPARC_DMA_MAPPING_H */
diff --git a/include/asm-sparc/dma-mapping_64.h b/include/asm-sparc/dma-mapping_64.h
deleted file mode 100644
index bfa64f9702d..00000000000
--- a/include/asm-sparc/dma-mapping_64.h
+++ /dev/null
@@ -1,154 +0,0 @@
1#ifndef _ASM_SPARC64_DMA_MAPPING_H
2#define _ASM_SPARC64_DMA_MAPPING_H
3
4#include <linux/scatterlist.h>
5#include <linux/mm.h>
6
7#define DMA_ERROR_CODE (~(dma_addr_t)0x0)
8
9struct dma_ops {
10 void *(*alloc_coherent)(struct device *dev, size_t size,
11 dma_addr_t *dma_handle, gfp_t flag);
12 void (*free_coherent)(struct device *dev, size_t size,
13 void *cpu_addr, dma_addr_t dma_handle);
14 dma_addr_t (*map_single)(struct device *dev, void *cpu_addr,
15 size_t size,
16 enum dma_data_direction direction);
17 void (*unmap_single)(struct device *dev, dma_addr_t dma_addr,
18 size_t size,
19 enum dma_data_direction direction);
20 int (*map_sg)(struct device *dev, struct scatterlist *sg, int nents,
21 enum dma_data_direction direction);
22 void (*unmap_sg)(struct device *dev, struct scatterlist *sg,
23 int nhwentries,
24 enum dma_data_direction direction);
25 void (*sync_single_for_cpu)(struct device *dev,
26 dma_addr_t dma_handle, size_t size,
27 enum dma_data_direction direction);
28 void (*sync_sg_for_cpu)(struct device *dev, struct scatterlist *sg,
29 int nelems,
30 enum dma_data_direction direction);
31};
32extern const struct dma_ops *dma_ops;
33
34extern int dma_supported(struct device *dev, u64 mask);
35extern int dma_set_mask(struct device *dev, u64 dma_mask);
36
37static inline void *dma_alloc_coherent(struct device *dev, size_t size,
38 dma_addr_t *dma_handle, gfp_t flag)
39{
40 return dma_ops->alloc_coherent(dev, size, dma_handle, flag);
41}
42
43static inline void dma_free_coherent(struct device *dev, size_t size,
44 void *cpu_addr, dma_addr_t dma_handle)
45{
46 dma_ops->free_coherent(dev, size, cpu_addr, dma_handle);
47}
48
49static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
50 size_t size,
51 enum dma_data_direction direction)
52{
53 return dma_ops->map_single(dev, cpu_addr, size, direction);
54}
55
56static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
57 size_t size,
58 enum dma_data_direction direction)
59{
60 dma_ops->unmap_single(dev, dma_addr, size, direction);
61}
62
63static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
64 unsigned long offset, size_t size,
65 enum dma_data_direction direction)
66{
67 return dma_ops->map_single(dev, page_address(page) + offset,
68 size, direction);
69}
70
71static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
72 size_t size,
73 enum dma_data_direction direction)
74{
75 dma_ops->unmap_single(dev, dma_address, size, direction);
76}
77
78static inline int dma_map_sg(struct device *dev, struct scatterlist *sg,
79 int nents, enum dma_data_direction direction)
80{
81 return dma_ops->map_sg(dev, sg, nents, direction);
82}
83
84static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
85 int nents, enum dma_data_direction direction)
86{
87 dma_ops->unmap_sg(dev, sg, nents, direction);
88}
89
90static inline void dma_sync_single_for_cpu(struct device *dev,
91 dma_addr_t dma_handle, size_t size,
92 enum dma_data_direction direction)
93{
94 dma_ops->sync_single_for_cpu(dev, dma_handle, size, direction);
95}
96
97static inline void dma_sync_single_for_device(struct device *dev,
98 dma_addr_t dma_handle,
99 size_t size,
100 enum dma_data_direction direction)
101{
102 /* No flushing needed to sync cpu writes to the device. */
103}
104
105static inline void dma_sync_single_range_for_cpu(struct device *dev,
106 dma_addr_t dma_handle,
107 unsigned long offset,
108 size_t size,
109 enum dma_data_direction direction)
110{
111 dma_sync_single_for_cpu(dev, dma_handle+offset, size, direction);
112}
113
114static inline void dma_sync_single_range_for_device(struct device *dev,
115 dma_addr_t dma_handle,
116 unsigned long offset,
117 size_t size,
118 enum dma_data_direction direction)
119{
120 /* No flushing needed to sync cpu writes to the device. */
121}
122
123
124static inline void dma_sync_sg_for_cpu(struct device *dev,
125 struct scatterlist *sg, int nelems,
126 enum dma_data_direction direction)
127{
128 dma_ops->sync_sg_for_cpu(dev, sg, nelems, direction);
129}
130
131static inline void dma_sync_sg_for_device(struct device *dev,
132 struct scatterlist *sg, int nelems,
133 enum dma_data_direction direction)
134{
135 /* No flushing needed to sync cpu writes to the device. */
136}
137
138static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
139{
140 return (dma_addr == DMA_ERROR_CODE);
141}
142
143static inline int dma_get_cache_alignment(void)
144{
145 /* no easy way to get cache size on all processors, so return
146 * the maximum possible, to be safe */
147 return (1 << INTERNODE_CACHE_SHIFT);
148}
149
150#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
151#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
152#define dma_is_consistent(d, h) (1)
153
154#endif /* _ASM_SPARC64_DMA_MAPPING_H */
diff --git a/include/asm-sparc/dma.h b/include/asm-sparc/dma.h
deleted file mode 100644
index 8cc69bfaae2..00000000000
--- a/include/asm-sparc/dma.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_DMA_H
2#define ___ASM_SPARC_DMA_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/dma_64.h>
5#else
6#include <asm-sparc/dma_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/dma_32.h b/include/asm-sparc/dma_32.h
deleted file mode 100644
index 959d6c8a71a..00000000000
--- a/include/asm-sparc/dma_32.h
+++ /dev/null
@@ -1,288 +0,0 @@
1/* include/asm-sparc/dma.h
2 *
3 * Copyright 1995 (C) David S. Miller (davem@davemloft.net)
4 */
5
6#ifndef _ASM_SPARC_DMA_H
7#define _ASM_SPARC_DMA_H
8
9#include <linux/kernel.h>
10#include <linux/types.h>
11
12#include <asm/vac-ops.h> /* for invalidate's, etc. */
13#include <asm/sbus.h>
14#include <asm/delay.h>
15#include <asm/oplib.h>
16#include <asm/system.h>
17#include <asm/io.h>
18#include <linux/spinlock.h>
19
20struct page;
21extern spinlock_t dma_spin_lock;
22
23static inline unsigned long claim_dma_lock(void)
24{
25 unsigned long flags;
26 spin_lock_irqsave(&dma_spin_lock, flags);
27 return flags;
28}
29
30static inline void release_dma_lock(unsigned long flags)
31{
32 spin_unlock_irqrestore(&dma_spin_lock, flags);
33}
34
35/* These are irrelevant for Sparc DMA, but we leave it in so that
36 * things can compile.
37 */
38#define MAX_DMA_CHANNELS 8
39#define MAX_DMA_ADDRESS (~0UL)
40#define DMA_MODE_READ 1
41#define DMA_MODE_WRITE 2
42
43/* Useful constants */
44#define SIZE_16MB (16*1024*1024)
45#define SIZE_64K (64*1024)
46
47/* SBUS DMA controller reg offsets */
48#define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */
49#define DMA_ADDR 0x04UL /* rw DMA transfer address register 0x04 */
50#define DMA_COUNT 0x08UL /* rw DMA transfer count register 0x08 */
51#define DMA_TEST 0x0cUL /* rw DMA test/debug register 0x0c */
52
53/* DVMA chip revisions */
54enum dvma_rev {
55 dvmarev0,
56 dvmaesc1,
57 dvmarev1,
58 dvmarev2,
59 dvmarev3,
60 dvmarevplus,
61 dvmahme
62};
63
64#define DMA_HASCOUNT(rev) ((rev)==dvmaesc1)
65
66/* Linux DMA information structure, filled during probe. */
67struct sbus_dma {
68 struct sbus_dma *next;
69 struct sbus_dev *sdev;
70 void __iomem *regs;
71
72 /* Status, misc info */
73 int node; /* Prom node for this DMA device */
74 int running; /* Are we doing DMA now? */
75 int allocated; /* Are we "owned" by anyone yet? */
76
77 /* Transfer information. */
78 unsigned long addr; /* Start address of current transfer */
79 int nbytes; /* Size of current transfer */
80 int realbytes; /* For splitting up large transfers, etc. */
81
82 /* DMA revision */
83 enum dvma_rev revision;
84};
85
86extern struct sbus_dma *dma_chain;
87
88/* Broken hardware... */
89#ifdef CONFIG_SUN4
90/* Have to sort this out. Does rev0 work fine on sun4[cmd] without isbroken?
91 * Or is rev0 present only on sun4 boxes? -jj */
92#define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev0 || (dma)->revision == dvmarev1)
93#else
94#define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev1)
95#endif
96#define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1)
97
98/* Main routines in dma.c */
99extern void dvma_init(struct sbus_bus *);
100
101/* Fields in the cond_reg register */
102/* First, the version identification bits */
103#define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */
104#define DMA_VERS0 0x00000000 /* Sunray DMA version */
105#define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */
106#define DMA_VERS1 0x80000000 /* DMA rev 1 */
107#define DMA_VERS2 0xa0000000 /* DMA rev 2 */
108#define DMA_VERHME 0xb0000000 /* DMA hme gate array */
109#define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */
110
111#define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */
112#define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */
113#define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */
114#define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */
115#define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */
116#define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */
117#define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */
118#define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */
119#define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */
120#define DMA_RST_BPP DMA_RST_SCSI /* Reset the BPP controller */
121#define DMA_ST_WRITE 0x00000100 /* write from device to memory */
122#define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */
123#define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */
124#define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */
125#define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */
126#define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */
127#define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */
128#define DMA_TERM_CNTR 0x00004000 /* Terminal counter */
129#define DMA_SCSI_SBUS64 0x00008000 /* HME: Enable 64-bit SBUS mode. */
130#define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */
131#define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */
132#define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */
133#define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */
134#define DMA_E_BURSTS 0x000c0000 /* ENET: SBUS r/w burst mask */
135#define DMA_E_BURST32 0x00040000 /* ENET: SBUS 32 byte r/w burst */
136#define DMA_E_BURST16 0x00000000 /* ENET: SBUS 16 byte r/w burst */
137#define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */
138#define DMA_BRST64 0x00080000 /* SCSI: 64byte bursts (HME on UltraSparc only) */
139#define DMA_BRST32 0x00040000 /* SCSI/BPP: 32byte bursts */
140#define DMA_BRST16 0x00000000 /* SCSI/BPP: 16byte bursts */
141#define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */
142#define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */
143#define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */
144#define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */
145#define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */
146#define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */
147#define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */
148#define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */
149#define DMA_BPP_ON DMA_SCSI_ON /* Enable BPP dma */
150#define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */
151#define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */
152#define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */
153#define DMA_RESET_FAS366 0x08000000 /* HME: Assert RESET to FAS366 */
154
155/* Values describing the burst-size property from the PROM */
156#define DMA_BURST1 0x01
157#define DMA_BURST2 0x02
158#define DMA_BURST4 0x04
159#define DMA_BURST8 0x08
160#define DMA_BURST16 0x10
161#define DMA_BURST32 0x20
162#define DMA_BURST64 0x40
163#define DMA_BURSTBITS 0x7f
164
165/* Determine highest possible final transfer address given a base */
166#define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
167
168/* Yes, I hack a lot of elisp in my spare time... */
169#define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR))
170#define DMA_IRQ_P(regs) ((((regs)->cond_reg) & (DMA_HNDL_INTR | DMA_HNDL_ERROR)))
171#define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE))
172#define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE)))
173#define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
174#define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
175#define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
176#define DMA_SETSTART(regs, addr) ((((regs)->st_addr) = (char *) addr))
177#define DMA_BEGINDMA_W(regs) \
178 ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))
179#define DMA_BEGINDMA_R(regs) \
180 ((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE)))))
181
182/* For certain DMA chips, we need to disable ints upon irq entry
183 * and turn them back on when we are done. So in any ESP interrupt
184 * handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT
185 * when leaving the handler. You have been warned...
186 */
187#define DMA_IRQ_ENTRY(dma, dregs) do { \
188 if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
189 } while (0)
190
191#define DMA_IRQ_EXIT(dma, dregs) do { \
192 if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \
193 } while(0)
194
195#if 0 /* P3 this stuff is inline in ledma.c:init_restart_ledma() */
196/* Pause until counter runs out or BIT isn't set in the DMA condition
197 * register.
198 */
199static inline void sparc_dma_pause(struct sparc_dma_registers *regs,
200 unsigned long bit)
201{
202 int ctr = 50000; /* Let's find some bugs ;) */
203
204 /* Busy wait until the bit is not set any more */
205 while((regs->cond_reg&bit) && (ctr>0)) {
206 ctr--;
207 __delay(5);
208 }
209
210 /* Check for bogus outcome. */
211 if(!ctr)
212 panic("DMA timeout");
213}
214
215/* Reset the friggin' thing... */
216#define DMA_RESET(dma) do { \
217 struct sparc_dma_registers *regs = dma->regs; \
218 /* Let the current FIFO drain itself */ \
219 sparc_dma_pause(regs, (DMA_FIFO_ISDRAIN)); \
220 /* Reset the logic */ \
221 regs->cond_reg |= (DMA_RST_SCSI); /* assert */ \
222 __delay(400); /* let the bits set ;) */ \
223 regs->cond_reg &= ~(DMA_RST_SCSI); /* de-assert */ \
224 sparc_dma_enable_interrupts(regs); /* Re-enable interrupts */ \
225 /* Enable FAST transfers if available */ \
226 if(dma->revision>dvmarev1) regs->cond_reg |= DMA_3CLKS; \
227 dma->running = 0; \
228} while(0)
229#endif
230
231#define for_each_dvma(dma) \
232 for((dma) = dma_chain; (dma); (dma) = (dma)->next)
233
234extern int get_dma_list(char *);
235extern int request_dma(unsigned int, __const__ char *);
236extern void free_dma(unsigned int);
237
238/* From PCI */
239
240#ifdef CONFIG_PCI
241extern int isa_dma_bridge_buggy;
242#else
243#define isa_dma_bridge_buggy (0)
244#endif
245
246/* Routines for data transfer buffers. */
247BTFIXUPDEF_CALL(char *, mmu_lockarea, char *, unsigned long)
248BTFIXUPDEF_CALL(void, mmu_unlockarea, char *, unsigned long)
249
250#define mmu_lockarea(vaddr,len) BTFIXUP_CALL(mmu_lockarea)(vaddr,len)
251#define mmu_unlockarea(vaddr,len) BTFIXUP_CALL(mmu_unlockarea)(vaddr,len)
252
253/* These are implementations for sbus_map_sg/sbus_unmap_sg... collapse later */
254BTFIXUPDEF_CALL(__u32, mmu_get_scsi_one, char *, unsigned long, struct sbus_bus *sbus)
255BTFIXUPDEF_CALL(void, mmu_get_scsi_sgl, struct scatterlist *, int, struct sbus_bus *sbus)
256BTFIXUPDEF_CALL(void, mmu_release_scsi_one, __u32, unsigned long, struct sbus_bus *sbus)
257BTFIXUPDEF_CALL(void, mmu_release_scsi_sgl, struct scatterlist *, int, struct sbus_bus *sbus)
258
259#define mmu_get_scsi_one(vaddr,len,sbus) BTFIXUP_CALL(mmu_get_scsi_one)(vaddr,len,sbus)
260#define mmu_get_scsi_sgl(sg,sz,sbus) BTFIXUP_CALL(mmu_get_scsi_sgl)(sg,sz,sbus)
261#define mmu_release_scsi_one(vaddr,len,sbus) BTFIXUP_CALL(mmu_release_scsi_one)(vaddr,len,sbus)
262#define mmu_release_scsi_sgl(sg,sz,sbus) BTFIXUP_CALL(mmu_release_scsi_sgl)(sg,sz,sbus)
263
264/*
265 * mmu_map/unmap are provided by iommu/iounit; Invalid to call on IIep.
266 *
267 * The mmu_map_dma_area establishes two mappings in one go.
268 * These mappings point to pages normally mapped at 'va' (linear address).
269 * First mapping is for CPU visible address at 'a', uncached.
270 * This is an alias, but it works because it is an uncached mapping.
271 * Second mapping is for device visible address, or "bus" address.
272 * The bus address is returned at '*pba'.
273 *
274 * These functions seem distinct, but are hard to split. On sun4c,
275 * at least for now, 'a' is equal to bus address, and retured in *pba.
276 * On sun4m, page attributes depend on the CPU type, so we have to
277 * know if we are mapping RAM or I/O, so it has to be an additional argument
278 * to a separate mapping function for CPU visible mappings.
279 */
280BTFIXUPDEF_CALL(int, mmu_map_dma_area, dma_addr_t *, unsigned long, unsigned long, int len)
281BTFIXUPDEF_CALL(struct page *, mmu_translate_dvma, unsigned long busa)
282BTFIXUPDEF_CALL(void, mmu_unmap_dma_area, unsigned long busa, int len)
283
284#define mmu_map_dma_area(pba,va,a,len) BTFIXUP_CALL(mmu_map_dma_area)(pba,va,a,len)
285#define mmu_unmap_dma_area(ba,len) BTFIXUP_CALL(mmu_unmap_dma_area)(ba,len)
286#define mmu_translate_dvma(ba) BTFIXUP_CALL(mmu_translate_dvma)(ba)
287
288#endif /* !(_ASM_SPARC_DMA_H) */
diff --git a/include/asm-sparc/dma_64.h b/include/asm-sparc/dma_64.h
deleted file mode 100644
index 9d4c024bd3b..00000000000
--- a/include/asm-sparc/dma_64.h
+++ /dev/null
@@ -1,205 +0,0 @@
1/*
2 * include/asm-sparc64/dma.h
3 *
4 * Copyright 1996 (C) David S. Miller (davem@caip.rutgers.edu)
5 */
6
7#ifndef _ASM_SPARC64_DMA_H
8#define _ASM_SPARC64_DMA_H
9
10#include <linux/kernel.h>
11#include <linux/types.h>
12#include <linux/spinlock.h>
13
14#include <asm/sbus.h>
15#include <asm/delay.h>
16#include <asm/oplib.h>
17
18/* These are irrelevant for Sparc DMA, but we leave it in so that
19 * things can compile.
20 */
21#define MAX_DMA_CHANNELS 8
22#define DMA_MODE_READ 1
23#define DMA_MODE_WRITE 2
24#define MAX_DMA_ADDRESS (~0UL)
25
26/* Useful constants */
27#define SIZE_16MB (16*1024*1024)
28#define SIZE_64K (64*1024)
29
30/* SBUS DMA controller reg offsets */
31#define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */
32#define DMA_ADDR 0x04UL /* rw DMA transfer address register 0x04 */
33#define DMA_COUNT 0x08UL /* rw DMA transfer count register 0x08 */
34#define DMA_TEST 0x0cUL /* rw DMA test/debug register 0x0c */
35
36/* DVMA chip revisions */
37enum dvma_rev {
38 dvmarev0,
39 dvmaesc1,
40 dvmarev1,
41 dvmarev2,
42 dvmarev3,
43 dvmarevplus,
44 dvmahme
45};
46
47#define DMA_HASCOUNT(rev) ((rev)==dvmaesc1)
48
49/* Linux DMA information structure, filled during probe. */
50struct sbus_dma {
51 struct sbus_dma *next;
52 struct sbus_dev *sdev;
53 void __iomem *regs;
54
55 /* Status, misc info */
56 int node; /* Prom node for this DMA device */
57 int running; /* Are we doing DMA now? */
58 int allocated; /* Are we "owned" by anyone yet? */
59
60 /* Transfer information. */
61 u32 addr; /* Start address of current transfer */
62 int nbytes; /* Size of current transfer */
63 int realbytes; /* For splitting up large transfers, etc. */
64
65 /* DMA revision */
66 enum dvma_rev revision;
67};
68
69extern struct sbus_dma *dma_chain;
70
71/* Broken hardware... */
72#define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev1)
73#define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1)
74
75/* Main routines in dma.c */
76extern void dvma_init(struct sbus_bus *);
77
78/* Fields in the cond_reg register */
79/* First, the version identification bits */
80#define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */
81#define DMA_VERS0 0x00000000 /* Sunray DMA version */
82#define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */
83#define DMA_VERS1 0x80000000 /* DMA rev 1 */
84#define DMA_VERS2 0xa0000000 /* DMA rev 2 */
85#define DMA_VERHME 0xb0000000 /* DMA hme gate array */
86#define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */
87
88#define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */
89#define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */
90#define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */
91#define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */
92#define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */
93#define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */
94#define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */
95#define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */
96#define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */
97#define DMA_ST_WRITE 0x00000100 /* write from device to memory */
98#define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */
99#define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */
100#define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */
101#define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */
102#define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */
103#define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */
104#define DMA_TERM_CNTR 0x00004000 /* Terminal counter */
105#define DMA_SCSI_SBUS64 0x00008000 /* HME: Enable 64-bit SBUS mode. */
106#define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */
107#define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */
108#define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */
109#define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */
110#define DMA_E_BURSTS 0x000c0000 /* ENET: SBUS r/w burst mask */
111#define DMA_E_BURST32 0x00040000 /* ENET: SBUS 32 byte r/w burst */
112#define DMA_E_BURST16 0x00000000 /* ENET: SBUS 16 byte r/w burst */
113#define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */
114#define DMA_BRST64 0x000c0000 /* SCSI: 64byte bursts (HME on UltraSparc only) */
115#define DMA_BRST32 0x00040000 /* SCSI: 32byte bursts */
116#define DMA_BRST16 0x00000000 /* SCSI: 16byte bursts */
117#define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */
118#define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */
119#define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */
120#define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */
121#define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */
122#define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */
123#define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */
124#define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */
125#define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */
126#define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */
127#define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */
128#define DMA_RESET_FAS366 0x08000000 /* HME: Assert RESET to FAS366 */
129
130/* Values describing the burst-size property from the PROM */
131#define DMA_BURST1 0x01
132#define DMA_BURST2 0x02
133#define DMA_BURST4 0x04
134#define DMA_BURST8 0x08
135#define DMA_BURST16 0x10
136#define DMA_BURST32 0x20
137#define DMA_BURST64 0x40
138#define DMA_BURSTBITS 0x7f
139
140/* Determine highest possible final transfer address given a base */
141#define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
142
143/* Yes, I hack a lot of elisp in my spare time... */
144#define DMA_ERROR_P(regs) ((sbus_readl((regs) + DMA_CSR) & DMA_HNDL_ERROR))
145#define DMA_IRQ_P(regs) ((sbus_readl((regs) + DMA_CSR)) & (DMA_HNDL_INTR | DMA_HNDL_ERROR))
146#define DMA_WRITE_P(regs) ((sbus_readl((regs) + DMA_CSR) & DMA_ST_WRITE))
147#define DMA_OFF(__regs) \
148do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
149 tmp &= ~DMA_ENABLE; \
150 sbus_writel(tmp, (__regs) + DMA_CSR); \
151} while(0)
152#define DMA_INTSOFF(__regs) \
153do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
154 tmp &= ~DMA_INT_ENAB; \
155 sbus_writel(tmp, (__regs) + DMA_CSR); \
156} while(0)
157#define DMA_INTSON(__regs) \
158do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
159 tmp |= DMA_INT_ENAB; \
160 sbus_writel(tmp, (__regs) + DMA_CSR); \
161} while(0)
162#define DMA_PUNTFIFO(__regs) \
163do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
164 tmp |= DMA_FIFO_INV; \
165 sbus_writel(tmp, (__regs) + DMA_CSR); \
166} while(0)
167#define DMA_SETSTART(__regs, __addr) \
168 sbus_writel((u32)(__addr), (__regs) + DMA_ADDR);
169#define DMA_BEGINDMA_W(__regs) \
170do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
171 tmp |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB); \
172 sbus_writel(tmp, (__regs) + DMA_CSR); \
173} while(0)
174#define DMA_BEGINDMA_R(__regs) \
175do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
176 tmp |= (DMA_ENABLE|DMA_INT_ENAB); \
177 tmp &= ~DMA_ST_WRITE; \
178 sbus_writel(tmp, (__regs) + DMA_CSR); \
179} while(0)
180
181/* For certain DMA chips, we need to disable ints upon irq entry
182 * and turn them back on when we are done. So in any ESP interrupt
183 * handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT
184 * when leaving the handler. You have been warned...
185 */
186#define DMA_IRQ_ENTRY(dma, dregs) do { \
187 if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
188 } while (0)
189
190#define DMA_IRQ_EXIT(dma, dregs) do { \
191 if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \
192 } while(0)
193
194#define for_each_dvma(dma) \
195 for((dma) = dma_chain; (dma); (dma) = (dma)->next)
196
197/* From PCI */
198
199#ifdef CONFIG_PCI
200extern int isa_dma_bridge_buggy;
201#else
202#define isa_dma_bridge_buggy (0)
203#endif
204
205#endif /* !(_ASM_SPARC64_DMA_H) */
diff --git a/include/asm-sparc/ebus.h b/include/asm-sparc/ebus.h
deleted file mode 100644
index a5da2d00cd1..00000000000
--- a/include/asm-sparc/ebus.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_EBUS_H
2#define ___ASM_SPARC_EBUS_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/ebus_64.h>
5#else
6#include <asm-sparc/ebus_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/ebus_32.h b/include/asm-sparc/ebus_32.h
deleted file mode 100644
index 29cb7dfc6b7..00000000000
--- a/include/asm-sparc/ebus_32.h
+++ /dev/null
@@ -1,99 +0,0 @@
1/*
2 * ebus.h: PCI to Ebus pseudo driver software state.
3 *
4 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
5 *
6 * Adopted for sparc by V. Roganov and G. Raiko.
7 */
8
9#ifndef __SPARC_EBUS_H
10#define __SPARC_EBUS_H
11
12#ifndef _LINUX_IOPORT_H
13#include <linux/ioport.h>
14#endif
15#include <asm/oplib.h>
16#include <asm/prom.h>
17#include <asm/of_device.h>
18
19struct linux_ebus_child {
20 struct linux_ebus_child *next;
21 struct linux_ebus_device *parent;
22 struct linux_ebus *bus;
23 struct device_node *prom_node;
24 struct resource resource[PROMREG_MAX];
25 int num_addrs;
26 unsigned int irqs[PROMINTR_MAX];
27 int num_irqs;
28};
29
30struct linux_ebus_device {
31 struct of_device ofdev;
32 struct linux_ebus_device *next;
33 struct linux_ebus_child *children;
34 struct linux_ebus *bus;
35 struct device_node *prom_node;
36 struct resource resource[PROMREG_MAX];
37 int num_addrs;
38 unsigned int irqs[PROMINTR_MAX];
39 int num_irqs;
40};
41#define to_ebus_device(d) container_of(d, struct linux_ebus_device, ofdev.dev)
42
43struct linux_ebus {
44 struct of_device ofdev;
45 struct linux_ebus *next;
46 struct linux_ebus_device *devices;
47 struct linux_pbm_info *parent;
48 struct pci_dev *self;
49 struct device_node *prom_node;
50};
51#define to_ebus(d) container_of(d, struct linux_ebus, ofdev.dev)
52
53struct linux_ebus_dma {
54 unsigned int dcsr;
55 unsigned int dacr;
56 unsigned int dbcr;
57};
58
59#define EBUS_DCSR_INT_PEND 0x00000001
60#define EBUS_DCSR_ERR_PEND 0x00000002
61#define EBUS_DCSR_DRAIN 0x00000004
62#define EBUS_DCSR_INT_EN 0x00000010
63#define EBUS_DCSR_RESET 0x00000080
64#define EBUS_DCSR_WRITE 0x00000100
65#define EBUS_DCSR_EN_DMA 0x00000200
66#define EBUS_DCSR_CYC_PEND 0x00000400
67#define EBUS_DCSR_DIAG_RD_DONE 0x00000800
68#define EBUS_DCSR_DIAG_WR_DONE 0x00001000
69#define EBUS_DCSR_EN_CNT 0x00002000
70#define EBUS_DCSR_TC 0x00004000
71#define EBUS_DCSR_DIS_CSR_DRN 0x00010000
72#define EBUS_DCSR_BURST_SZ_MASK 0x000c0000
73#define EBUS_DCSR_BURST_SZ_1 0x00080000
74#define EBUS_DCSR_BURST_SZ_4 0x00000000
75#define EBUS_DCSR_BURST_SZ_8 0x00040000
76#define EBUS_DCSR_BURST_SZ_16 0x000c0000
77#define EBUS_DCSR_DIAG_EN 0x00100000
78#define EBUS_DCSR_DIS_ERR_PEND 0x00400000
79#define EBUS_DCSR_TCI_DIS 0x00800000
80#define EBUS_DCSR_EN_NEXT 0x01000000
81#define EBUS_DCSR_DMA_ON 0x02000000
82#define EBUS_DCSR_A_LOADED 0x04000000
83#define EBUS_DCSR_NA_LOADED 0x08000000
84#define EBUS_DCSR_DEV_ID_MASK 0xf0000000
85
86extern struct linux_ebus *ebus_chain;
87
88extern void ebus_init(void);
89
90#define for_each_ebus(bus) \
91 for((bus) = ebus_chain; (bus); (bus) = (bus)->next)
92
93#define for_each_ebusdev(dev, bus) \
94 for((dev) = (bus)->devices; (dev); (dev) = (dev)->next)
95
96#define for_each_edevchild(dev, child) \
97 for((child) = (dev)->children; (child); (child) = (child)->next)
98
99#endif /* !(__SPARC_EBUS_H) */
diff --git a/include/asm-sparc/ebus_64.h b/include/asm-sparc/ebus_64.h
deleted file mode 100644
index fcc62b97ced..00000000000
--- a/include/asm-sparc/ebus_64.h
+++ /dev/null
@@ -1,94 +0,0 @@
1/*
2 * ebus.h: PCI to Ebus pseudo driver software state.
3 *
4 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 David S. Miller (davem@redhat.com)
6 */
7
8#ifndef __SPARC64_EBUS_H
9#define __SPARC64_EBUS_H
10
11#include <asm/oplib.h>
12#include <asm/prom.h>
13#include <asm/of_device.h>
14
15struct linux_ebus_child {
16 struct linux_ebus_child *next;
17 struct linux_ebus_device *parent;
18 struct linux_ebus *bus;
19 struct device_node *prom_node;
20 struct resource resource[PROMREG_MAX];
21 int num_addrs;
22 unsigned int irqs[PROMINTR_MAX];
23 int num_irqs;
24};
25
26struct linux_ebus_device {
27 struct of_device ofdev;
28 struct linux_ebus_device *next;
29 struct linux_ebus_child *children;
30 struct linux_ebus *bus;
31 struct device_node *prom_node;
32 struct resource resource[PROMREG_MAX];
33 int num_addrs;
34 unsigned int irqs[PROMINTR_MAX];
35 int num_irqs;
36};
37#define to_ebus_device(d) container_of(d, struct linux_ebus_device, ofdev.dev)
38
39struct linux_ebus {
40 struct of_device ofdev;
41 struct linux_ebus *next;
42 struct linux_ebus_device *devices;
43 struct pci_dev *self;
44 int index;
45 int is_rio;
46 struct device_node *prom_node;
47};
48#define to_ebus(d) container_of(d, struct linux_ebus, ofdev.dev)
49
50struct ebus_dma_info {
51 spinlock_t lock;
52 void __iomem *regs;
53
54 unsigned int flags;
55#define EBUS_DMA_FLAG_USE_EBDMA_HANDLER 0x00000001
56#define EBUS_DMA_FLAG_TCI_DISABLE 0x00000002
57
58 /* These are only valid is EBUS_DMA_FLAG_USE_EBDMA_HANDLER is
59 * set.
60 */
61 void (*callback)(struct ebus_dma_info *p, int event, void *cookie);
62 void *client_cookie;
63 unsigned int irq;
64#define EBUS_DMA_EVENT_ERROR 1
65#define EBUS_DMA_EVENT_DMA 2
66#define EBUS_DMA_EVENT_DEVICE 4
67
68 unsigned char name[64];
69};
70
71extern int ebus_dma_register(struct ebus_dma_info *p);
72extern int ebus_dma_irq_enable(struct ebus_dma_info *p, int on);
73extern void ebus_dma_unregister(struct ebus_dma_info *p);
74extern int ebus_dma_request(struct ebus_dma_info *p, dma_addr_t bus_addr,
75 size_t len);
76extern void ebus_dma_prepare(struct ebus_dma_info *p, int write);
77extern unsigned int ebus_dma_residue(struct ebus_dma_info *p);
78extern unsigned int ebus_dma_addr(struct ebus_dma_info *p);
79extern void ebus_dma_enable(struct ebus_dma_info *p, int on);
80
81extern struct linux_ebus *ebus_chain;
82
83extern void ebus_init(void);
84
85#define for_each_ebus(bus) \
86 for((bus) = ebus_chain; (bus); (bus) = (bus)->next)
87
88#define for_each_ebusdev(dev, bus) \
89 for((dev) = (bus)->devices; (dev); (dev) = (dev)->next)
90
91#define for_each_edevchild(dev, child) \
92 for((child) = (dev)->children; (child); (child) = (child)->next)
93
94#endif /* !(__SPARC64_EBUS_H) */
diff --git a/include/asm-sparc/ecc.h b/include/asm-sparc/ecc.h
deleted file mode 100644
index ccb84b66fef..00000000000
--- a/include/asm-sparc/ecc.h
+++ /dev/null
@@ -1,122 +0,0 @@
1/*
2 * ecc.h: Definitions and defines for the external cache/memory
3 * controller on the sun4m.
4 *
5 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
6 */
7
8#ifndef _SPARC_ECC_H
9#define _SPARC_ECC_H
10
11/* These registers are accessed through the SRMMU passthrough ASI 0x20 */
12#define ECC_ENABLE 0x00000000 /* ECC enable register */
13#define ECC_FSTATUS 0x00000008 /* ECC fault status register */
14#define ECC_FADDR 0x00000010 /* ECC fault address register */
15#define ECC_DIGNOSTIC 0x00000018 /* ECC diagnostics register */
16#define ECC_MBAENAB 0x00000020 /* MBus arbiter enable register */
17#define ECC_DMESG 0x00001000 /* Diagnostic message passing area */
18
19/* ECC MBus Arbiter Enable register:
20 *
21 * ----------------------------------------
22 * | |SBUS|MOD3|MOD2|MOD1|RSV|
23 * ----------------------------------------
24 * 31 5 4 3 2 1 0
25 *
26 * SBUS: Enable MBus Arbiter on the SBus 0=off 1=on
27 * MOD3: Enable MBus Arbiter on MBus module 3 0=off 1=on
28 * MOD2: Enable MBus Arbiter on MBus module 2 0=off 1=on
29 * MOD1: Enable MBus Arbiter on MBus module 1 0=off 1=on
30 */
31
32#define ECC_MBAE_SBUS 0x00000010
33#define ECC_MBAE_MOD3 0x00000008
34#define ECC_MBAE_MOD2 0x00000004
35#define ECC_MBAE_MOD1 0x00000002
36
37/* ECC Fault Control Register layout:
38 *
39 * -----------------------------
40 * | RESV | ECHECK | EINT |
41 * -----------------------------
42 * 31 2 1 0
43 *
44 * ECHECK: Enable ECC checking. 0=off 1=on
45 * EINT: Enable Interrupts for correctable errors. 0=off 1=on
46 */
47#define ECC_FCR_CHECK 0x00000002
48#define ECC_FCR_INTENAB 0x00000001
49
50/* ECC Fault Address Register Zero layout:
51 *
52 * -----------------------------------------------------
53 * | MID | S | RSV | VA | BM |AT| C| SZ |TYP| PADDR |
54 * -----------------------------------------------------
55 * 31-28 27 26-22 21-14 13 12 11 10-8 7-4 3-0
56 *
57 * MID: ModuleID of the faulting processor. ie. who did it?
58 * S: Supervisor/Privileged access? 0=no 1=yes
59 * VA: Bits 19-12 of the virtual faulting address, these are the
60 * superset bits in the virtual cache and can be used for
61 * a flush operation if necessary.
62 * BM: Boot mode? 0=no 1=yes This is just like the SRMMU boot
63 * mode bit.
64 * AT: Did this fault happen during an atomic instruction? 0=no
65 * 1=yes. This means either an 'ldstub' or 'swap' instruction
66 * was in progress (but not finished) when this fault happened.
67 * This indicated whether the bus was locked when the fault
68 * occurred.
69 * C: Did the pte for this access indicate that it was cacheable?
70 * 0=no 1=yes
71 * SZ: The size of the transaction.
72 * TYP: The transaction type.
73 * PADDR: Bits 35-32 of the physical address for the fault.
74 */
75#define ECC_FADDR0_MIDMASK 0xf0000000
76#define ECC_FADDR0_S 0x08000000
77#define ECC_FADDR0_VADDR 0x003fc000
78#define ECC_FADDR0_BMODE 0x00002000
79#define ECC_FADDR0_ATOMIC 0x00001000
80#define ECC_FADDR0_CACHE 0x00000800
81#define ECC_FADDR0_SIZE 0x00000700
82#define ECC_FADDR0_TYPE 0x000000f0
83#define ECC_FADDR0_PADDR 0x0000000f
84
85/* ECC Fault Address Register One layout:
86 *
87 * -------------------------------------
88 * | Physical Address 31-0 |
89 * -------------------------------------
90 * 31 0
91 *
92 * You get the upper 4 bits of the physical address from the
93 * PADDR field in ECC Fault Address Zero register.
94 */
95
96/* ECC Fault Status Register layout:
97 *
98 * ----------------------------------------------
99 * | RESV|C2E|MULT|SYNDROME|DWORD|UNC|TIMEO|BS|C|
100 * ----------------------------------------------
101 * 31-18 17 16 15-8 7-4 3 2 1 0
102 *
103 * C2E: A C2 graphics error occurred. 0=no 1=yes (SS10 only)
104 * MULT: Multiple errors occurred ;-O 0=no 1=prom_panic(yes)
105 * SYNDROME: Controller is mentally unstable.
106 * DWORD:
107 * UNC: Uncorrectable error. 0=no 1=yes
108 * TIMEO: Timeout occurred. 0=no 1=yes
109 * BS: C2 graphics bad slot access. 0=no 1=yes (SS10 only)
110 * C: Correctable error? 0=no 1=yes
111 */
112
113#define ECC_FSR_C2ERR 0x00020000
114#define ECC_FSR_MULT 0x00010000
115#define ECC_FSR_SYND 0x0000ff00
116#define ECC_FSR_DWORD 0x000000f0
117#define ECC_FSR_UNC 0x00000008
118#define ECC_FSR_TIMEO 0x00000004
119#define ECC_FSR_BADSLOT 0x00000002
120#define ECC_FSR_C 0x00000001
121
122#endif /* !(_SPARC_ECC_H) */
diff --git a/include/asm-sparc/eeprom.h b/include/asm-sparc/eeprom.h
deleted file mode 100644
index e17beeceb40..00000000000
--- a/include/asm-sparc/eeprom.h
+++ /dev/null
@@ -1,9 +0,0 @@
1/*
2 * eeprom.h: Definitions for the Sun eeprom.
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 */
6
7/* The EEPROM and the Mostek Mk48t02 use the same IO address space
8 * for their registers/data areas. The IDPROM lives here too.
9 */
diff --git a/include/asm-sparc/elf.h b/include/asm-sparc/elf.h
deleted file mode 100644
index f035c45d7b5..00000000000
--- a/include/asm-sparc/elf.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_ELF_H
2#define ___ASM_SPARC_ELF_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/elf_64.h>
5#else
6#include <asm-sparc/elf_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/elf_32.h b/include/asm-sparc/elf_32.h
deleted file mode 100644
index d043f80bc2f..00000000000
--- a/include/asm-sparc/elf_32.h
+++ /dev/null
@@ -1,145 +0,0 @@
1#ifndef __ASMSPARC_ELF_H
2#define __ASMSPARC_ELF_H
3
4/*
5 * ELF register definitions..
6 */
7
8#include <asm/ptrace.h>
9
10/*
11 * Sparc section types
12 */
13#define STT_REGISTER 13
14
15/*
16 * Sparc ELF relocation types
17 */
18#define R_SPARC_NONE 0
19#define R_SPARC_8 1
20#define R_SPARC_16 2
21#define R_SPARC_32 3
22#define R_SPARC_DISP8 4
23#define R_SPARC_DISP16 5
24#define R_SPARC_DISP32 6
25#define R_SPARC_WDISP30 7
26#define R_SPARC_WDISP22 8
27#define R_SPARC_HI22 9
28#define R_SPARC_22 10
29#define R_SPARC_13 11
30#define R_SPARC_LO10 12
31#define R_SPARC_GOT10 13
32#define R_SPARC_GOT13 14
33#define R_SPARC_GOT22 15
34#define R_SPARC_PC10 16
35#define R_SPARC_PC22 17
36#define R_SPARC_WPLT30 18
37#define R_SPARC_COPY 19
38#define R_SPARC_GLOB_DAT 20
39#define R_SPARC_JMP_SLOT 21
40#define R_SPARC_RELATIVE 22
41#define R_SPARC_UA32 23
42#define R_SPARC_PLT32 24
43#define R_SPARC_HIPLT22 25
44#define R_SPARC_LOPLT10 26
45#define R_SPARC_PCPLT32 27
46#define R_SPARC_PCPLT22 28
47#define R_SPARC_PCPLT10 29
48#define R_SPARC_10 30
49#define R_SPARC_11 31
50#define R_SPARC_64 32
51#define R_SPARC_OLO10 33
52#define R_SPARC_WDISP16 40
53#define R_SPARC_WDISP19 41
54#define R_SPARC_7 43
55#define R_SPARC_5 44
56#define R_SPARC_6 45
57
58/* Bits present in AT_HWCAP, primarily for Sparc32. */
59
60#define HWCAP_SPARC_FLUSH 1 /* CPU supports flush instruction. */
61#define HWCAP_SPARC_STBAR 2
62#define HWCAP_SPARC_SWAP 4
63#define HWCAP_SPARC_MULDIV 8
64#define HWCAP_SPARC_V9 16
65#define HWCAP_SPARC_ULTRA3 32
66
67#define CORE_DUMP_USE_REGSET
68
69/* Format is:
70 * G0 --> G7
71 * O0 --> O7
72 * L0 --> L7
73 * I0 --> I7
74 * PSR, PC, nPC, Y, WIM, TBR
75 */
76typedef unsigned long elf_greg_t;
77#define ELF_NGREG 38
78typedef elf_greg_t elf_gregset_t[ELF_NGREG];
79
80typedef struct {
81 union {
82 unsigned long pr_regs[32];
83 double pr_dregs[16];
84 } pr_fr;
85 unsigned long __unused;
86 unsigned long pr_fsr;
87 unsigned char pr_qcnt;
88 unsigned char pr_q_entrysize;
89 unsigned char pr_en;
90 unsigned int pr_q[64];
91} elf_fpregset_t;
92
93#include <asm/mbus.h>
94
95/*
96 * This is used to ensure we don't load something for the wrong architecture.
97 */
98#define elf_check_arch(x) ((x)->e_machine == EM_SPARC)
99
100/*
101 * These are used to set parameters in the core dumps.
102 */
103#define ELF_ARCH EM_SPARC
104#define ELF_CLASS ELFCLASS32
105#define ELF_DATA ELFDATA2MSB
106
107#define USE_ELF_CORE_DUMP
108#ifndef CONFIG_SUN4
109#define ELF_EXEC_PAGESIZE 4096
110#else
111#define ELF_EXEC_PAGESIZE 8192
112#endif
113
114
115/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
116 use of this is to invoke "./ld.so someprog" to test out a new version of
117 the loader. We need to make sure that it is out of the way of the program
118 that it will "exec", and that there is sufficient room for the brk. */
119
120#define ELF_ET_DYN_BASE (TASK_UNMAPPED_BASE)
121
122/* This yields a mask that user programs can use to figure out what
123 instruction set this cpu supports. This can NOT be done in userspace
124 on Sparc. */
125
126/* Sun4c has none of the capabilities, most sun4m's have them all.
127 * XXX This is gross, set some global variable at boot time. -DaveM
128 */
129#define ELF_HWCAP ((ARCH_SUN4C_SUN4) ? 0 : \
130 (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR | \
131 HWCAP_SPARC_SWAP | \
132 ((srmmu_modtype != Cypress && \
133 srmmu_modtype != Cypress_vE && \
134 srmmu_modtype != Cypress_vD) ? \
135 HWCAP_SPARC_MULDIV : 0)))
136
137/* This yields a string that ld.so will use to load implementation
138 specific libraries for optimization. This is more specific in
139 intent than poking at uname or /proc/cpuinfo. */
140
141#define ELF_PLATFORM (NULL)
142
143#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
144
145#endif /* !(__ASMSPARC_ELF_H) */
diff --git a/include/asm-sparc/elf_64.h b/include/asm-sparc/elf_64.h
deleted file mode 100644
index 0818a1308f4..00000000000
--- a/include/asm-sparc/elf_64.h
+++ /dev/null
@@ -1,217 +0,0 @@
1#ifndef __ASM_SPARC64_ELF_H
2#define __ASM_SPARC64_ELF_H
3
4/*
5 * ELF register definitions..
6 */
7
8#include <asm/ptrace.h>
9#include <asm/processor.h>
10#include <asm/uaccess.h>
11#include <asm/spitfire.h>
12
13/*
14 * Sparc section types
15 */
16#define STT_REGISTER 13
17
18/*
19 * Sparc ELF relocation types
20 */
21#define R_SPARC_NONE 0
22#define R_SPARC_8 1
23#define R_SPARC_16 2
24#define R_SPARC_32 3
25#define R_SPARC_DISP8 4
26#define R_SPARC_DISP16 5
27#define R_SPARC_DISP32 6
28#define R_SPARC_WDISP30 7
29#define R_SPARC_WDISP22 8
30#define R_SPARC_HI22 9
31#define R_SPARC_22 10
32#define R_SPARC_13 11
33#define R_SPARC_LO10 12
34#define R_SPARC_GOT10 13
35#define R_SPARC_GOT13 14
36#define R_SPARC_GOT22 15
37#define R_SPARC_PC10 16
38#define R_SPARC_PC22 17
39#define R_SPARC_WPLT30 18
40#define R_SPARC_COPY 19
41#define R_SPARC_GLOB_DAT 20
42#define R_SPARC_JMP_SLOT 21
43#define R_SPARC_RELATIVE 22
44#define R_SPARC_UA32 23
45#define R_SPARC_PLT32 24
46#define R_SPARC_HIPLT22 25
47#define R_SPARC_LOPLT10 26
48#define R_SPARC_PCPLT32 27
49#define R_SPARC_PCPLT22 28
50#define R_SPARC_PCPLT10 29
51#define R_SPARC_10 30
52#define R_SPARC_11 31
53#define R_SPARC_64 32
54#define R_SPARC_OLO10 33
55#define R_SPARC_WDISP16 40
56#define R_SPARC_WDISP19 41
57#define R_SPARC_7 43
58#define R_SPARC_5 44
59#define R_SPARC_6 45
60
61/* Bits present in AT_HWCAP, primarily for Sparc32. */
62
63#define HWCAP_SPARC_FLUSH 1 /* CPU supports flush instruction. */
64#define HWCAP_SPARC_STBAR 2
65#define HWCAP_SPARC_SWAP 4
66#define HWCAP_SPARC_MULDIV 8
67#define HWCAP_SPARC_V9 16
68#define HWCAP_SPARC_ULTRA3 32
69#define HWCAP_SPARC_BLKINIT 64
70#define HWCAP_SPARC_N2 128
71
72#define CORE_DUMP_USE_REGSET
73
74/*
75 * These are used to set parameters in the core dumps.
76 */
77#define ELF_ARCH EM_SPARCV9
78#define ELF_CLASS ELFCLASS64
79#define ELF_DATA ELFDATA2MSB
80
81/* Format of 64-bit elf_gregset_t is:
82 * G0 --> G7
83 * O0 --> O7
84 * L0 --> L7
85 * I0 --> I7
86 * TSTATE
87 * TPC
88 * TNPC
89 * Y
90 */
91typedef unsigned long elf_greg_t;
92#define ELF_NGREG 36
93typedef elf_greg_t elf_gregset_t[ELF_NGREG];
94
95typedef struct {
96 unsigned long pr_regs[32];
97 unsigned long pr_fsr;
98 unsigned long pr_gsr;
99 unsigned long pr_fprs;
100} elf_fpregset_t;
101
102/* Format of 32-bit elf_gregset_t is:
103 * G0 --> G7
104 * O0 --> O7
105 * L0 --> L7
106 * I0 --> I7
107 * PSR, PC, nPC, Y, WIM, TBR
108 */
109typedef unsigned int compat_elf_greg_t;
110#define COMPAT_ELF_NGREG 38
111typedef compat_elf_greg_t compat_elf_gregset_t[COMPAT_ELF_NGREG];
112
113typedef struct {
114 union {
115 unsigned int pr_regs[32];
116 unsigned long pr_dregs[16];
117 } pr_fr;
118 unsigned int __unused;
119 unsigned int pr_fsr;
120 unsigned char pr_qcnt;
121 unsigned char pr_q_entrysize;
122 unsigned char pr_en;
123 unsigned int pr_q[64];
124} compat_elf_fpregset_t;
125
126/* UltraSparc extensions. Still unused, but will be eventually. */
127typedef struct {
128 unsigned int pr_type;
129 unsigned int pr_align;
130 union {
131 struct {
132 union {
133 unsigned int pr_regs[32];
134 unsigned long pr_dregs[16];
135 long double pr_qregs[8];
136 } pr_xfr;
137 } pr_v8p;
138 unsigned int pr_xfsr;
139 unsigned int pr_fprs;
140 unsigned int pr_xg[8];
141 unsigned int pr_xo[8];
142 unsigned long pr_tstate;
143 unsigned int pr_filler[8];
144 } pr_un;
145} elf_xregset_t;
146
147/*
148 * This is used to ensure we don't load something for the wrong architecture.
149 */
150#define elf_check_arch(x) ((x)->e_machine == ELF_ARCH)
151#define compat_elf_check_arch(x) ((x)->e_machine == EM_SPARC || \
152 (x)->e_machine == EM_SPARC32PLUS)
153#define compat_start_thread start_thread32
154
155#define USE_ELF_CORE_DUMP
156#define ELF_EXEC_PAGESIZE PAGE_SIZE
157
158/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
159 use of this is to invoke "./ld.so someprog" to test out a new version of
160 the loader. We need to make sure that it is out of the way of the program
161 that it will "exec", and that there is sufficient room for the brk. */
162
163#define ELF_ET_DYN_BASE 0x0000010000000000UL
164#define COMPAT_ELF_ET_DYN_BASE 0x0000000070000000UL
165
166
167/* This yields a mask that user programs can use to figure out what
168 instruction set this cpu supports. */
169
170/* On Ultra, we support all of the v8 capabilities. */
171static inline unsigned int sparc64_elf_hwcap(void)
172{
173 unsigned int cap = (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR |
174 HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV |
175 HWCAP_SPARC_V9);
176
177 if (tlb_type == cheetah || tlb_type == cheetah_plus)
178 cap |= HWCAP_SPARC_ULTRA3;
179 else if (tlb_type == hypervisor) {
180 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 ||
181 sun4v_chip_type == SUN4V_CHIP_NIAGARA2)
182 cap |= HWCAP_SPARC_BLKINIT;
183 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2)
184 cap |= HWCAP_SPARC_N2;
185 }
186
187 return cap;
188}
189
190#define ELF_HWCAP sparc64_elf_hwcap();
191
192/* This yields a string that ld.so will use to load implementation
193 specific libraries for optimization. This is more specific in
194 intent than poking at uname or /proc/cpuinfo. */
195
196#define ELF_PLATFORM (NULL)
197
198#define SET_PERSONALITY(ex, ibcs2) \
199do { unsigned long new_flags = current_thread_info()->flags; \
200 new_flags &= _TIF_32BIT; \
201 if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
202 new_flags |= _TIF_32BIT; \
203 else \
204 new_flags &= ~_TIF_32BIT; \
205 if ((current_thread_info()->flags & _TIF_32BIT) \
206 != new_flags) \
207 set_thread_flag(TIF_ABI_PENDING); \
208 else \
209 clear_thread_flag(TIF_ABI_PENDING); \
210 /* flush_thread will update pgd cache */ \
211 if (ibcs2) \
212 set_personality(PER_SVR4); \
213 else if (current->personality != PER_LINUX32) \
214 set_personality(PER_LINUX); \
215} while (0)
216
217#endif /* !(__ASM_SPARC64_ELF_H) */
diff --git a/include/asm-sparc/emergency-restart.h b/include/asm-sparc/emergency-restart.h
deleted file mode 100644
index 108d8c48e42..00000000000
--- a/include/asm-sparc/emergency-restart.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _ASM_EMERGENCY_RESTART_H
2#define _ASM_EMERGENCY_RESTART_H
3
4#include <asm-generic/emergency-restart.h>
5
6#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-sparc/envctrl.h b/include/asm-sparc/envctrl.h
deleted file mode 100644
index 624fa7e2da8..00000000000
--- a/include/asm-sparc/envctrl.h
+++ /dev/null
@@ -1,103 +0,0 @@
1/*
2 *
3 * envctrl.h: Definitions for access to the i2c environment
4 * monitoring on Ultrasparc systems.
5 *
6 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
7 * Copyright (C) 2000 Vinh Truong (vinh.truong@eng.sun.com)
8 * VT - Add all ioctl commands and environment status definitions
9 * VT - Add application note
10 */
11#ifndef _SPARC64_ENVCTRL_H
12#define _SPARC64_ENVCTRL_H 1
13
14#include <linux/ioctl.h>
15
16/* Application note:
17 *
18 * The driver supports 4 operations: open(), close(), ioctl(), read()
19 * The device name is /dev/envctrl.
20 * Below is sample usage:
21 *
22 * fd = open("/dev/envtrl", O_RDONLY);
23 * if (ioctl(fd, ENVCTRL_READ_SHUTDOWN_TEMPERATURE, 0) < 0)
24 * printf("error\n");
25 * ret = read(fd, buf, 10);
26 * close(fd);
27 *
28 * Notice in the case of cpu voltage and temperature, the default is
29 * cpu0. If we need to know the info of cpu1, cpu2, cpu3, we need to
30 * pass in cpu number in ioctl() last parameter. For example, to
31 * get the voltage of cpu2:
32 *
33 * ioctlbuf[0] = 2;
34 * if (ioctl(fd, ENVCTRL_READ_CPU_VOLTAGE, ioctlbuf) < 0)
35 * printf("error\n");
36 * ret = read(fd, buf, 10);
37 *
38 * All the return values are in ascii. So check read return value
39 * and do appropriate conversions in your application.
40 */
41
42/* IOCTL commands */
43
44/* Note: these commands reflect possible monitor features.
45 * Some boards choose to support some of the features only.
46 */
47#define ENVCTRL_RD_CPU_TEMPERATURE _IOR('p', 0x40, int)
48#define ENVCTRL_RD_CPU_VOLTAGE _IOR('p', 0x41, int)
49#define ENVCTRL_RD_FAN_STATUS _IOR('p', 0x42, int)
50#define ENVCTRL_RD_WARNING_TEMPERATURE _IOR('p', 0x43, int)
51#define ENVCTRL_RD_SHUTDOWN_TEMPERATURE _IOR('p', 0x44, int)
52#define ENVCTRL_RD_VOLTAGE_STATUS _IOR('p', 0x45, int)
53#define ENVCTRL_RD_SCSI_TEMPERATURE _IOR('p', 0x46, int)
54#define ENVCTRL_RD_ETHERNET_TEMPERATURE _IOR('p', 0x47, int)
55#define ENVCTRL_RD_MTHRBD_TEMPERATURE _IOR('p', 0x48, int)
56
57#define ENVCTRL_RD_GLOBALADDRESS _IOR('p', 0x49, int)
58
59/* Read return values for a voltage status request. */
60#define ENVCTRL_VOLTAGE_POWERSUPPLY_GOOD 0x01
61#define ENVCTRL_VOLTAGE_BAD 0x02
62#define ENVCTRL_POWERSUPPLY_BAD 0x03
63#define ENVCTRL_VOLTAGE_POWERSUPPLY_BAD 0x04
64
65/* Read return values for a fan status request.
66 * A failure match means either the fan fails or
67 * the fan is not connected. Some boards have optional
68 * connectors to connect extra fans.
69 *
70 * There are maximum 8 monitor fans. Some are cpu fans
71 * some are system fans. The mask below only indicates
72 * fan by order number.
73 * Below is a sample application:
74 *
75 * if (ioctl(fd, ENVCTRL_READ_FAN_STATUS, 0) < 0) {
76 * printf("ioctl fan failed\n");
77 * }
78 * if (read(fd, rslt, 1) <= 0) {
79 * printf("error or fan not monitored\n");
80 * } else {
81 * if (rslt[0] == ENVCTRL_ALL_FANS_GOOD) {
82 * printf("all fans good\n");
83 * } else if (rslt[0] == ENVCTRL_ALL_FANS_BAD) {
84 * printf("all fans bad\n");
85 * } else {
86 * if (rslt[0] & ENVCTRL_FAN0_FAILURE_MASK) {
87 * printf("fan 0 failed or not connected\n");
88 * }
89 * ......
90 */
91
92#define ENVCTRL_ALL_FANS_GOOD 0x00
93#define ENVCTRL_FAN0_FAILURE_MASK 0x01
94#define ENVCTRL_FAN1_FAILURE_MASK 0x02
95#define ENVCTRL_FAN2_FAILURE_MASK 0x04
96#define ENVCTRL_FAN3_FAILURE_MASK 0x08
97#define ENVCTRL_FAN4_FAILURE_MASK 0x10
98#define ENVCTRL_FAN5_FAILURE_MASK 0x20
99#define ENVCTRL_FAN6_FAILURE_MASK 0x40
100#define ENVCTRL_FAN7_FAILURE_MASK 0x80
101#define ENVCTRL_ALL_FANS_BAD 0xFF
102
103#endif /* !(_SPARC64_ENVCTRL_H) */
diff --git a/include/asm-sparc/errno.h b/include/asm-sparc/errno.h
deleted file mode 100644
index a9ef172977d..00000000000
--- a/include/asm-sparc/errno.h
+++ /dev/null
@@ -1,113 +0,0 @@
1#ifndef _SPARC_ERRNO_H
2#define _SPARC_ERRNO_H
3
4/* These match the SunOS error numbering scheme. */
5
6#include <asm-generic/errno-base.h>
7
8#define EWOULDBLOCK EAGAIN /* Operation would block */
9#define EINPROGRESS 36 /* Operation now in progress */
10#define EALREADY 37 /* Operation already in progress */
11#define ENOTSOCK 38 /* Socket operation on non-socket */
12#define EDESTADDRREQ 39 /* Destination address required */
13#define EMSGSIZE 40 /* Message too long */
14#define EPROTOTYPE 41 /* Protocol wrong type for socket */
15#define ENOPROTOOPT 42 /* Protocol not available */
16#define EPROTONOSUPPORT 43 /* Protocol not supported */
17#define ESOCKTNOSUPPORT 44 /* Socket type not supported */
18#define EOPNOTSUPP 45 /* Op not supported on transport endpoint */
19#define EPFNOSUPPORT 46 /* Protocol family not supported */
20#define EAFNOSUPPORT 47 /* Address family not supported by protocol */
21#define EADDRINUSE 48 /* Address already in use */
22#define EADDRNOTAVAIL 49 /* Cannot assign requested address */
23#define ENETDOWN 50 /* Network is down */
24#define ENETUNREACH 51 /* Network is unreachable */
25#define ENETRESET 52 /* Net dropped connection because of reset */
26#define ECONNABORTED 53 /* Software caused connection abort */
27#define ECONNRESET 54 /* Connection reset by peer */
28#define ENOBUFS 55 /* No buffer space available */
29#define EISCONN 56 /* Transport endpoint is already connected */
30#define ENOTCONN 57 /* Transport endpoint is not connected */
31#define ESHUTDOWN 58 /* No send after transport endpoint shutdown */
32#define ETOOMANYREFS 59 /* Too many references: cannot splice */
33#define ETIMEDOUT 60 /* Connection timed out */
34#define ECONNREFUSED 61 /* Connection refused */
35#define ELOOP 62 /* Too many symbolic links encountered */
36#define ENAMETOOLONG 63 /* File name too long */
37#define EHOSTDOWN 64 /* Host is down */
38#define EHOSTUNREACH 65 /* No route to host */
39#define ENOTEMPTY 66 /* Directory not empty */
40#define EPROCLIM 67 /* SUNOS: Too many processes */
41#define EUSERS 68 /* Too many users */
42#define EDQUOT 69 /* Quota exceeded */
43#define ESTALE 70 /* Stale NFS file handle */
44#define EREMOTE 71 /* Object is remote */
45#define ENOSTR 72 /* Device not a stream */
46#define ETIME 73 /* Timer expired */
47#define ENOSR 74 /* Out of streams resources */
48#define ENOMSG 75 /* No message of desired type */
49#define EBADMSG 76 /* Not a data message */
50#define EIDRM 77 /* Identifier removed */
51#define EDEADLK 78 /* Resource deadlock would occur */
52#define ENOLCK 79 /* No record locks available */
53#define ENONET 80 /* Machine is not on the network */
54#define ERREMOTE 81 /* SunOS: Too many lvls of remote in path */
55#define ENOLINK 82 /* Link has been severed */
56#define EADV 83 /* Advertise error */
57#define ESRMNT 84 /* Srmount error */
58#define ECOMM 85 /* Communication error on send */
59#define EPROTO 86 /* Protocol error */
60#define EMULTIHOP 87 /* Multihop attempted */
61#define EDOTDOT 88 /* RFS specific error */
62#define EREMCHG 89 /* Remote address changed */
63#define ENOSYS 90 /* Function not implemented */
64
65/* The rest have no SunOS equivalent. */
66#define ESTRPIPE 91 /* Streams pipe error */
67#define EOVERFLOW 92 /* Value too large for defined data type */
68#define EBADFD 93 /* File descriptor in bad state */
69#define ECHRNG 94 /* Channel number out of range */
70#define EL2NSYNC 95 /* Level 2 not synchronized */
71#define EL3HLT 96 /* Level 3 halted */
72#define EL3RST 97 /* Level 3 reset */
73#define ELNRNG 98 /* Link number out of range */
74#define EUNATCH 99 /* Protocol driver not attached */
75#define ENOCSI 100 /* No CSI structure available */
76#define EL2HLT 101 /* Level 2 halted */
77#define EBADE 102 /* Invalid exchange */
78#define EBADR 103 /* Invalid request descriptor */
79#define EXFULL 104 /* Exchange full */
80#define ENOANO 105 /* No anode */
81#define EBADRQC 106 /* Invalid request code */
82#define EBADSLT 107 /* Invalid slot */
83#define EDEADLOCK 108 /* File locking deadlock error */
84#define EBFONT 109 /* Bad font file format */
85#define ELIBEXEC 110 /* Cannot exec a shared library directly */
86#define ENODATA 111 /* No data available */
87#define ELIBBAD 112 /* Accessing a corrupted shared library */
88#define ENOPKG 113 /* Package not installed */
89#define ELIBACC 114 /* Can not access a needed shared library */
90#define ENOTUNIQ 115 /* Name not unique on network */
91#define ERESTART 116 /* Interrupted syscall should be restarted */
92#define EUCLEAN 117 /* Structure needs cleaning */
93#define ENOTNAM 118 /* Not a XENIX named type file */
94#define ENAVAIL 119 /* No XENIX semaphores available */
95#define EISNAM 120 /* Is a named type file */
96#define EREMOTEIO 121 /* Remote I/O error */
97#define EILSEQ 122 /* Illegal byte sequence */
98#define ELIBMAX 123 /* Atmpt to link in too many shared libs */
99#define ELIBSCN 124 /* .lib section in a.out corrupted */
100
101#define ENOMEDIUM 125 /* No medium found */
102#define EMEDIUMTYPE 126 /* Wrong medium type */
103#define ECANCELED 127 /* Operation Cancelled */
104#define ENOKEY 128 /* Required key not available */
105#define EKEYEXPIRED 129 /* Key has expired */
106#define EKEYREVOKED 130 /* Key has been revoked */
107#define EKEYREJECTED 131 /* Key was rejected by service */
108
109/* for robust mutexes */
110#define EOWNERDEAD 132 /* Owner died */
111#define ENOTRECOVERABLE 133 /* State not recoverable */
112
113#endif
diff --git a/include/asm-sparc/estate.h b/include/asm-sparc/estate.h
deleted file mode 100644
index 520c08560d1..00000000000
--- a/include/asm-sparc/estate.h
+++ /dev/null
@@ -1,49 +0,0 @@
1#ifndef _SPARC64_ESTATE_H
2#define _SPARC64_ESTATE_H
3
4/* UltraSPARC-III E-cache Error Enable */
5#define ESTATE_ERROR_FMT 0x0000000000040000 /* Force MTAG ECC */
6#define ESTATE_ERROR_FMESS 0x000000000003c000 /* Forced MTAG ECC val */
7#define ESTATE_ERROR_FMD 0x0000000000002000 /* Force DATA ECC */
8#define ESTATE_ERROR_FDECC 0x0000000000001ff0 /* Forced DATA ECC val */
9#define ESTATE_ERROR_UCEEN 0x0000000000000008 /* See below */
10#define ESTATE_ERROR_NCEEN 0x0000000000000002 /* See below */
11#define ESTATE_ERROR_CEEN 0x0000000000000001 /* See below */
12
13/* UCEEN enables the fast_ECC_error trap for: 1) software correctable E-cache
14 * errors 2) uncorrectable E-cache errors. Such events only occur on reads
15 * of the E-cache by the local processor for: 1) data loads 2) instruction
16 * fetches 3) atomic operations. Such events _cannot_ occur for: 1) merge
17 * 2) writeback 2) copyout. The AFSR bits associated with these traps are
18 * UCC and UCU.
19 */
20
21/* NCEEN enables instruction_access_error, data_access_error, and ECC_error traps
22 * for uncorrectable ECC errors and system errors.
23 *
24 * Uncorrectable system bus data error or MTAG ECC error, system bus TimeOUT,
25 * or system bus BusERR:
26 * 1) As the result of an instruction fetch, will generate instruction_access_error
27 * 2) As the result of a load etc. will generate data_access_error.
28 * 3) As the result of store merge completion, writeback, or copyout will
29 * generate a disrupting ECC_error trap.
30 * 4) As the result of such errors on instruction vector fetch can generate any
31 * of the 3 trap types.
32 *
33 * The AFSR bits associated with these traps are EMU, EDU, WDU, CPU, IVU, UE,
34 * BERR, and TO.
35 */
36
37/* CEEN enables the ECC_error trap for hardware corrected ECC errors. System bus
38 * reads resulting in a hardware corrected data or MTAG ECC error will generate an
39 * ECC_error disrupting trap with this bit enabled.
40 *
41 * This same trap will also be generated when a hardware corrected ECC error results
42 * during store merge, writeback, and copyout operations.
43 */
44
45/* In general, if the trap enable bits above are disabled the AFSR bits will still
46 * log the events even though the trap will not be generated by the processor.
47 */
48
49#endif /* _SPARC64_ESTATE_H */
diff --git a/include/asm-sparc/fb.h b/include/asm-sparc/fb.h
deleted file mode 100644
index b83e4472965..00000000000
--- a/include/asm-sparc/fb.h
+++ /dev/null
@@ -1,29 +0,0 @@
1#ifndef _SPARC_FB_H_
2#define _SPARC_FB_H_
3#include <linux/fb.h>
4#include <linux/fs.h>
5#include <asm/page.h>
6#include <asm/prom.h>
7
8static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
9 unsigned long off)
10{
11#ifdef CONFIG_SPARC64
12 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
13#endif
14}
15
16static inline int fb_is_primary_device(struct fb_info *info)
17{
18 struct device *dev = info->device;
19 struct device_node *node;
20
21 node = dev->archdata.prom_node;
22 if (node &&
23 node == of_console_device)
24 return 1;
25
26 return 0;
27}
28
29#endif /* _SPARC_FB_H_ */
diff --git a/include/asm-sparc/fbio.h b/include/asm-sparc/fbio.h
deleted file mode 100644
index b9215a0907d..00000000000
--- a/include/asm-sparc/fbio.h
+++ /dev/null
@@ -1,330 +0,0 @@
1#ifndef __LINUX_FBIO_H
2#define __LINUX_FBIO_H
3
4#include <linux/compiler.h>
5#include <linux/types.h>
6
7/* Constants used for fbio SunOS compatibility */
8/* (C) 1996 Miguel de Icaza */
9
10/* Frame buffer types */
11#define FBTYPE_NOTYPE -1
12#define FBTYPE_SUN1BW 0 /* mono */
13#define FBTYPE_SUN1COLOR 1
14#define FBTYPE_SUN2BW 2
15#define FBTYPE_SUN2COLOR 3
16#define FBTYPE_SUN2GP 4
17#define FBTYPE_SUN5COLOR 5
18#define FBTYPE_SUN3COLOR 6
19#define FBTYPE_MEMCOLOR 7
20#define FBTYPE_SUN4COLOR 8
21
22#define FBTYPE_NOTSUN1 9
23#define FBTYPE_NOTSUN2 10
24#define FBTYPE_NOTSUN3 11
25
26#define FBTYPE_SUNFAST_COLOR 12 /* cg6 */
27#define FBTYPE_SUNROP_COLOR 13
28#define FBTYPE_SUNFB_VIDEO 14
29#define FBTYPE_SUNGIFB 15
30#define FBTYPE_SUNGPLAS 16
31#define FBTYPE_SUNGP3 17
32#define FBTYPE_SUNGT 18
33#define FBTYPE_SUNLEO 19 /* zx Leo card */
34#define FBTYPE_MDICOLOR 20 /* cg14 */
35#define FBTYPE_TCXCOLOR 21 /* SUNW,tcx card */
36
37#define FBTYPE_LASTPLUSONE 21 /* This is not last + 1 in fact... */
38
39/* Does not seem to be listed in the Sun file either */
40#define FBTYPE_CREATOR 22
41#define FBTYPE_PCI_IGA1682 23
42#define FBTYPE_P9100COLOR 24
43
44#define FBTYPE_PCI_GENERIC 1000
45#define FBTYPE_PCI_MACH64 1001
46
47/* fbio ioctls */
48/* Returned by FBIOGTYPE */
49struct fbtype {
50 int fb_type; /* fb type, see above */
51 int fb_height; /* pixels */
52 int fb_width; /* pixels */
53 int fb_depth;
54 int fb_cmsize; /* color map entries */
55 int fb_size; /* fb size in bytes */
56};
57#define FBIOGTYPE _IOR('F', 0, struct fbtype)
58
59struct fbcmap {
60 int index; /* first element (0 origin) */
61 int count;
62 unsigned char __user *red;
63 unsigned char __user *green;
64 unsigned char __user *blue;
65};
66
67#ifdef __KERNEL__
68#define FBIOPUTCMAP_SPARC _IOW('F', 3, struct fbcmap)
69#define FBIOGETCMAP_SPARC _IOW('F', 4, struct fbcmap)
70#else
71#define FBIOPUTCMAP _IOW('F', 3, struct fbcmap)
72#define FBIOGETCMAP _IOW('F', 4, struct fbcmap)
73#endif
74
75/* # of device specific values */
76#define FB_ATTR_NDEVSPECIFIC 8
77/* # of possible emulations */
78#define FB_ATTR_NEMUTYPES 4
79
80struct fbsattr {
81 int flags;
82 int emu_type; /* -1 if none */
83 int dev_specific[FB_ATTR_NDEVSPECIFIC];
84};
85
86struct fbgattr {
87 int real_type; /* real frame buffer type */
88 int owner; /* unknown */
89 struct fbtype fbtype; /* real frame buffer fbtype */
90 struct fbsattr sattr;
91 int emu_types[FB_ATTR_NEMUTYPES]; /* supported emulations */
92};
93#define FBIOSATTR _IOW('F', 5, struct fbgattr) /* Unsupported: */
94#define FBIOGATTR _IOR('F', 6, struct fbgattr) /* supported */
95
96#define FBIOSVIDEO _IOW('F', 7, int)
97#define FBIOGVIDEO _IOR('F', 8, int)
98
99struct fbcursor {
100 short set; /* what to set, choose from the list above */
101 short enable; /* cursor on/off */
102 struct fbcurpos pos; /* cursor position */
103 struct fbcurpos hot; /* cursor hot spot */
104 struct fbcmap cmap; /* color map info */
105 struct fbcurpos size; /* cursor bit map size */
106 char __user *image; /* cursor image bits */
107 char __user *mask; /* cursor mask bits */
108};
109
110/* set/get cursor attributes/shape */
111#define FBIOSCURSOR _IOW('F', 24, struct fbcursor)
112#define FBIOGCURSOR _IOWR('F', 25, struct fbcursor)
113
114/* set/get cursor position */
115#define FBIOSCURPOS _IOW('F', 26, struct fbcurpos)
116#define FBIOGCURPOS _IOW('F', 27, struct fbcurpos)
117
118/* get max cursor size */
119#define FBIOGCURMAX _IOR('F', 28, struct fbcurpos)
120
121/* wid manipulation */
122struct fb_wid_alloc {
123#define FB_WID_SHARED_8 0
124#define FB_WID_SHARED_24 1
125#define FB_WID_DBL_8 2
126#define FB_WID_DBL_24 3
127 __u32 wa_type;
128 __s32 wa_index; /* Set on return */
129 __u32 wa_count;
130};
131struct fb_wid_item {
132 __u32 wi_type;
133 __s32 wi_index;
134 __u32 wi_attrs;
135 __u32 wi_values[32];
136};
137struct fb_wid_list {
138 __u32 wl_flags;
139 __u32 wl_count;
140 struct fb_wid_item *wl_list;
141};
142
143#define FBIO_WID_ALLOC _IOWR('F', 30, struct fb_wid_alloc)
144#define FBIO_WID_FREE _IOW('F', 31, struct fb_wid_alloc)
145#define FBIO_WID_PUT _IOW('F', 32, struct fb_wid_list)
146#define FBIO_WID_GET _IOWR('F', 33, struct fb_wid_list)
147
148/* Creator ioctls */
149#define FFB_IOCTL ('F'<<8)
150#define FFB_SYS_INFO (FFB_IOCTL|80)
151#define FFB_CLUTREAD (FFB_IOCTL|81)
152#define FFB_CLUTPOST (FFB_IOCTL|82)
153#define FFB_SETDIAGMODE (FFB_IOCTL|83)
154#define FFB_GETMONITORID (FFB_IOCTL|84)
155#define FFB_GETVIDEOMODE (FFB_IOCTL|85)
156#define FFB_SETVIDEOMODE (FFB_IOCTL|86)
157#define FFB_SETSERVER (FFB_IOCTL|87)
158#define FFB_SETOVCTL (FFB_IOCTL|88)
159#define FFB_GETOVCTL (FFB_IOCTL|89)
160#define FFB_GETSAXNUM (FFB_IOCTL|90)
161#define FFB_FBDEBUG (FFB_IOCTL|91)
162
163/* Cg14 ioctls */
164#define MDI_IOCTL ('M'<<8)
165#define MDI_RESET (MDI_IOCTL|1)
166#define MDI_GET_CFGINFO (MDI_IOCTL|2)
167#define MDI_SET_PIXELMODE (MDI_IOCTL|3)
168# define MDI_32_PIX 32
169# define MDI_16_PIX 16
170# define MDI_8_PIX 8
171
172struct mdi_cfginfo {
173 int mdi_ncluts; /* Number of implemented CLUTs in this MDI */
174 int mdi_type; /* FBTYPE name */
175 int mdi_height; /* height */
176 int mdi_width; /* widht */
177 int mdi_size; /* available ram */
178 int mdi_mode; /* 8bpp, 16bpp or 32bpp */
179 int mdi_pixfreq; /* pixel clock (from PROM) */
180};
181
182/* SparcLinux specific ioctl for the MDI, should be replaced for
183 * the SET_XLUT/SET_CLUTn ioctls instead
184 */
185#define MDI_CLEAR_XLUT (MDI_IOCTL|9)
186
187/* leo & ffb ioctls */
188struct fb_clut_alloc {
189 __u32 clutid; /* Set on return */
190 __u32 flag;
191 __u32 index;
192};
193
194struct fb_clut {
195#define FB_CLUT_WAIT 0x00000001 /* Not yet implemented */
196 __u32 flag;
197 __u32 clutid;
198 __u32 offset;
199 __u32 count;
200 char * red;
201 char * green;
202 char * blue;
203};
204
205struct fb_clut32 {
206 __u32 flag;
207 __u32 clutid;
208 __u32 offset;
209 __u32 count;
210 __u32 red;
211 __u32 green;
212 __u32 blue;
213};
214
215#define LEO_CLUTALLOC _IOWR('L', 53, struct fb_clut_alloc)
216#define LEO_CLUTFREE _IOW('L', 54, struct fb_clut_alloc)
217#define LEO_CLUTREAD _IOW('L', 55, struct fb_clut)
218#define LEO_CLUTPOST _IOW('L', 56, struct fb_clut)
219#define LEO_SETGAMMA _IOW('L', 68, int) /* Not yet implemented */
220#define LEO_GETGAMMA _IOR('L', 69, int) /* Not yet implemented */
221
222#ifdef __KERNEL__
223/* Addresses on the fd of a cgsix that are mappable */
224#define CG6_FBC 0x70000000
225#define CG6_TEC 0x70001000
226#define CG6_BTREGS 0x70002000
227#define CG6_FHC 0x70004000
228#define CG6_THC 0x70005000
229#define CG6_ROM 0x70006000
230#define CG6_RAM 0x70016000
231#define CG6_DHC 0x80000000
232
233#define CG3_MMAP_OFFSET 0x4000000
234
235/* Addresses on the fd of a tcx that are mappable */
236#define TCX_RAM8BIT 0x00000000
237#define TCX_RAM24BIT 0x01000000
238#define TCX_UNK3 0x10000000
239#define TCX_UNK4 0x20000000
240#define TCX_CONTROLPLANE 0x28000000
241#define TCX_UNK6 0x30000000
242#define TCX_UNK7 0x38000000
243#define TCX_TEC 0x70000000
244#define TCX_BTREGS 0x70002000
245#define TCX_THC 0x70004000
246#define TCX_DHC 0x70008000
247#define TCX_ALT 0x7000a000
248#define TCX_SYNC 0x7000e000
249#define TCX_UNK2 0x70010000
250
251/* CG14 definitions */
252
253/* Offsets into the OBIO space: */
254#define CG14_REGS 0 /* registers */
255#define CG14_CURSORREGS 0x1000 /* cursor registers */
256#define CG14_DACREGS 0x2000 /* DAC registers */
257#define CG14_XLUT 0x3000 /* X Look Up Table -- ??? */
258#define CG14_CLUT1 0x4000 /* Color Look Up Table */
259#define CG14_CLUT2 0x5000 /* Color Look Up Table */
260#define CG14_CLUT3 0x6000 /* Color Look Up Table */
261#define CG14_AUTO 0xf000
262
263#endif /* KERNEL */
264
265/* These are exported to userland for applications to use */
266/* Mappable offsets for the cg14: control registers */
267#define MDI_DIRECT_MAP 0x10000000
268#define MDI_CTLREG_MAP 0x20000000
269#define MDI_CURSOR_MAP 0x30000000
270#define MDI_SHDW_VRT_MAP 0x40000000
271
272/* Mappable offsets for the cg14: frame buffer resolutions */
273/* 32 bits */
274#define MDI_CHUNKY_XBGR_MAP 0x50000000
275#define MDI_CHUNKY_BGR_MAP 0x60000000
276
277/* 16 bits */
278#define MDI_PLANAR_X16_MAP 0x70000000
279#define MDI_PLANAR_C16_MAP 0x80000000
280
281/* 8 bit is done as CG3 MMAP offset */
282/* 32 bits, planar */
283#define MDI_PLANAR_X32_MAP 0x90000000
284#define MDI_PLANAR_B32_MAP 0xa0000000
285#define MDI_PLANAR_G32_MAP 0xb0000000
286#define MDI_PLANAR_R32_MAP 0xc0000000
287
288/* Mappable offsets on leo */
289#define LEO_SS0_MAP 0x00000000
290#define LEO_LC_SS0_USR_MAP 0x00800000
291#define LEO_LD_SS0_MAP 0x00801000
292#define LEO_LX_CURSOR_MAP 0x00802000
293#define LEO_SS1_MAP 0x00803000
294#define LEO_LC_SS1_USR_MAP 0x01003000
295#define LEO_LD_SS1_MAP 0x01004000
296#define LEO_UNK_MAP 0x01005000
297#define LEO_LX_KRN_MAP 0x01006000
298#define LEO_LC_SS0_KRN_MAP 0x01007000
299#define LEO_LC_SS1_KRN_MAP 0x01008000
300#define LEO_LD_GBL_MAP 0x01009000
301#define LEO_UNK2_MAP 0x0100a000
302
303#ifdef __KERNEL__
304struct fbcmap32 {
305 int index; /* first element (0 origin) */
306 int count;
307 u32 red;
308 u32 green;
309 u32 blue;
310};
311
312#define FBIOPUTCMAP32 _IOW('F', 3, struct fbcmap32)
313#define FBIOGETCMAP32 _IOW('F', 4, struct fbcmap32)
314
315struct fbcursor32 {
316 short set; /* what to set, choose from the list above */
317 short enable; /* cursor on/off */
318 struct fbcurpos pos; /* cursor position */
319 struct fbcurpos hot; /* cursor hot spot */
320 struct fbcmap32 cmap; /* color map info */
321 struct fbcurpos size; /* cursor bit map size */
322 u32 image; /* cursor image bits */
323 u32 mask; /* cursor mask bits */
324};
325
326#define FBIOSCURSOR32 _IOW('F', 24, struct fbcursor32)
327#define FBIOGCURSOR32 _IOW('F', 25, struct fbcursor32)
328#endif
329
330#endif /* __LINUX_FBIO_H */
diff --git a/include/asm-sparc/fcntl.h b/include/asm-sparc/fcntl.h
deleted file mode 100644
index d4d9c9d852c..00000000000
--- a/include/asm-sparc/fcntl.h
+++ /dev/null
@@ -1,40 +0,0 @@
1#ifndef _SPARC_FCNTL_H
2#define _SPARC_FCNTL_H
3
4/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
5 located on an ext2 file system */
6#define O_APPEND 0x0008
7#define FASYNC 0x0040 /* fcntl, for BSD compatibility */
8#define O_CREAT 0x0200 /* not fcntl */
9#define O_TRUNC 0x0400 /* not fcntl */
10#define O_EXCL 0x0800 /* not fcntl */
11#define O_SYNC 0x2000
12#define O_NONBLOCK 0x4000
13#if defined(__sparc__) && defined(__arch64__)
14#define O_NDELAY 0x0004
15#else
16#define O_NDELAY (0x0004 | O_NONBLOCK)
17#endif
18#define O_NOCTTY 0x8000 /* not fcntl */
19#define O_LARGEFILE 0x40000
20#define O_DIRECT 0x100000 /* direct disk access hint */
21#define O_NOATIME 0x200000
22#define O_CLOEXEC 0x400000
23
24#define F_GETOWN 5 /* for sockets. */
25#define F_SETOWN 6 /* for sockets. */
26#define F_GETLK 7
27#define F_SETLK 8
28#define F_SETLKW 9
29
30/* for posix fcntl() and lockf() */
31#define F_RDLCK 1
32#define F_WRLCK 2
33#define F_UNLCK 3
34
35#define __ARCH_FLOCK_PAD short __unused;
36#define __ARCH_FLOCK64_PAD short __unused;
37
38#include <asm-generic/fcntl.h>
39
40#endif
diff --git a/include/asm-sparc/fhc.h b/include/asm-sparc/fhc.h
deleted file mode 100644
index 788cbc46a11..00000000000
--- a/include/asm-sparc/fhc.h
+++ /dev/null
@@ -1,121 +0,0 @@
1/*
2 * fhc.h: Structures for central/fhc pseudo driver on Sunfire/Starfire/Wildfire.
3 *
4 * Copyright (C) 1997, 1999 David S. Miller (davem@redhat.com)
5 */
6
7#ifndef _SPARC64_FHC_H
8#define _SPARC64_FHC_H
9
10#include <linux/timer.h>
11
12#include <asm/oplib.h>
13#include <asm/prom.h>
14#include <asm/upa.h>
15
16struct linux_fhc;
17
18/* Clock board register offsets. */
19#define CLOCK_CTRL 0x00UL /* Main control */
20#define CLOCK_STAT1 0x10UL /* Status one */
21#define CLOCK_STAT2 0x20UL /* Status two */
22#define CLOCK_PWRSTAT 0x30UL /* Power status */
23#define CLOCK_PWRPRES 0x40UL /* Power presence */
24#define CLOCK_TEMP 0x50UL /* Temperature */
25#define CLOCK_IRQDIAG 0x60UL /* IRQ diagnostics */
26#define CLOCK_PWRSTAT2 0x70UL /* Power status two */
27
28#define CLOCK_CTRL_LLED 0x04 /* Left LED, 0 == on */
29#define CLOCK_CTRL_MLED 0x02 /* Mid LED, 1 == on */
30#define CLOCK_CTRL_RLED 0x01 /* RIght LED, 1 == on */
31
32struct linux_central {
33 struct linux_fhc *child;
34 unsigned long cfreg;
35 unsigned long clkregs;
36 unsigned long clkver;
37 int slots;
38 struct device_node *prom_node;
39
40 struct linux_prom_ranges central_ranges[PROMREG_MAX];
41 int num_central_ranges;
42};
43
44/* Firehose controller register offsets */
45struct fhc_regs {
46 unsigned long pregs; /* FHC internal regs */
47#define FHC_PREGS_ID 0x00UL /* FHC ID */
48#define FHC_ID_VERS 0xf0000000 /* Version of this FHC */
49#define FHC_ID_PARTID 0x0ffff000 /* Part ID code (0x0f9f == FHC) */
50#define FHC_ID_MANUF 0x0000007e /* Manufacturer (0x3e == SUN's JEDEC)*/
51#define FHC_ID_RESV 0x00000001 /* Read as one */
52#define FHC_PREGS_RCS 0x10UL /* FHC Reset Control/Status Register */
53#define FHC_RCS_POR 0x80000000 /* Last reset was a power cycle */
54#define FHC_RCS_SPOR 0x40000000 /* Last reset was sw power on reset */
55#define FHC_RCS_SXIR 0x20000000 /* Last reset was sw XIR reset */
56#define FHC_RCS_BPOR 0x10000000 /* Last reset was due to POR button */
57#define FHC_RCS_BXIR 0x08000000 /* Last reset was due to XIR button */
58#define FHC_RCS_WEVENT 0x04000000 /* CPU reset was due to wakeup event */
59#define FHC_RCS_CFATAL 0x02000000 /* Centerplane Fatal Error signalled */
60#define FHC_RCS_FENAB 0x01000000 /* Fatal errors elicit system reset */
61#define FHC_PREGS_CTRL 0x20UL /* FHC Control Register */
62#define FHC_CONTROL_ICS 0x00100000 /* Ignore Centerplane Signals */
63#define FHC_CONTROL_FRST 0x00080000 /* Fatal Error Reset Enable */
64#define FHC_CONTROL_LFAT 0x00040000 /* AC/DC signalled a local error */
65#define FHC_CONTROL_SLINE 0x00010000 /* Firmware Synchronization Line */
66#define FHC_CONTROL_DCD 0x00008000 /* DC-->DC Converter Disable */
67#define FHC_CONTROL_POFF 0x00004000 /* AC/DC Controller PLL Disable */
68#define FHC_CONTROL_FOFF 0x00002000 /* FHC Controller PLL Disable */
69#define FHC_CONTROL_AOFF 0x00001000 /* CPU A SRAM/SBD Low Power Mode */
70#define FHC_CONTROL_BOFF 0x00000800 /* CPU B SRAM/SBD Low Power Mode */
71#define FHC_CONTROL_PSOFF 0x00000400 /* Turns off this FHC's power supply */
72#define FHC_CONTROL_IXIST 0x00000200 /* 0=FHC tells clock board it exists */
73#define FHC_CONTROL_XMSTR 0x00000100 /* 1=Causes this FHC to be XIR master*/
74#define FHC_CONTROL_LLED 0x00000040 /* 0=Left LED ON */
75#define FHC_CONTROL_MLED 0x00000020 /* 1=Middle LED ON */
76#define FHC_CONTROL_RLED 0x00000010 /* 1=Right LED */
77#define FHC_CONTROL_BPINS 0x00000003 /* Spare Bidirectional Pins */
78#define FHC_PREGS_BSR 0x30UL /* FHC Board Status Register */
79#define FHC_BSR_DA64 0x00040000 /* Port A: 0=128bit 1=64bit data path */
80#define FHC_BSR_DB64 0x00020000 /* Port B: 0=128bit 1=64bit data path */
81#define FHC_BSR_BID 0x0001e000 /* Board ID */
82#define FHC_BSR_SA 0x00001c00 /* Port A UPA Speed (from the pins) */
83#define FHC_BSR_SB 0x00000380 /* Port B UPA Speed (from the pins) */
84#define FHC_BSR_NDIAG 0x00000040 /* Not in Diag Mode */
85#define FHC_BSR_NTBED 0x00000020 /* Not in TestBED Mode */
86#define FHC_BSR_NIA 0x0000001c /* Jumper, bit 18 in PROM space */
87#define FHC_BSR_SI 0x00000001 /* Spare input pin value */
88#define FHC_PREGS_ECC 0x40UL /* FHC ECC Control Register (16 bits) */
89#define FHC_PREGS_JCTRL 0xf0UL /* FHC JTAG Control Register */
90#define FHC_JTAG_CTRL_MENAB 0x80000000 /* Indicates this is JTAG Master */
91#define FHC_JTAG_CTRL_MNONE 0x40000000 /* Indicates no JTAG Master present */
92#define FHC_PREGS_JCMD 0x100UL /* FHC JTAG Command Register */
93 unsigned long ireg; /* FHC IGN reg */
94#define FHC_IREG_IGN 0x00UL /* This FHC's IGN */
95 unsigned long ffregs; /* FHC fanfail regs */
96#define FHC_FFREGS_IMAP 0x00UL /* FHC Fanfail IMAP */
97#define FHC_FFREGS_ICLR 0x10UL /* FHC Fanfail ICLR */
98 unsigned long sregs; /* FHC system regs */
99#define FHC_SREGS_IMAP 0x00UL /* FHC System IMAP */
100#define FHC_SREGS_ICLR 0x10UL /* FHC System ICLR */
101 unsigned long uregs; /* FHC uart regs */
102#define FHC_UREGS_IMAP 0x00UL /* FHC Uart IMAP */
103#define FHC_UREGS_ICLR 0x10UL /* FHC Uart ICLR */
104 unsigned long tregs; /* FHC TOD regs */
105#define FHC_TREGS_IMAP 0x00UL /* FHC TOD IMAP */
106#define FHC_TREGS_ICLR 0x10UL /* FHC TOD ICLR */
107};
108
109struct linux_fhc {
110 struct linux_fhc *next;
111 struct linux_central *parent; /* NULL if not central FHC */
112 struct fhc_regs fhc_regs;
113 int board;
114 int jtag_master;
115 struct device_node *prom_node;
116
117 struct linux_prom_ranges fhc_ranges[PROMREG_MAX];
118 int num_fhc_ranges;
119};
120
121#endif /* !(_SPARC64_FHC_H) */
diff --git a/include/asm-sparc/fixmap.h b/include/asm-sparc/fixmap.h
deleted file mode 100644
index f18fc0755ad..00000000000
--- a/include/asm-sparc/fixmap.h
+++ /dev/null
@@ -1,110 +0,0 @@
1/*
2 * fixmap.h: compile-time virtual memory allocation
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1998 Ingo Molnar
9 *
10 * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999
11 */
12
13#ifndef _ASM_FIXMAP_H
14#define _ASM_FIXMAP_H
15
16#include <linux/kernel.h>
17#include <asm/page.h>
18#ifdef CONFIG_HIGHMEM
19#include <linux/threads.h>
20#include <asm/kmap_types.h>
21#endif
22
23/*
24 * Here we define all the compile-time 'special' virtual
25 * addresses. The point is to have a constant address at
26 * compile time, but to set the physical address only
27 * in the boot process. We allocate these special addresses
28 * from the top of unused virtual memory (0xfd000000 - 1 page) backwards.
29 * Also this lets us do fail-safe vmalloc(), we
30 * can guarantee that these special addresses and
31 * vmalloc()-ed addresses never overlap.
32 *
33 * these 'compile-time allocated' memory buffers are
34 * fixed-size 4k pages. (or larger if used with an increment
35 * highger than 1) use fixmap_set(idx,phys) to associate
36 * physical memory with fixmap indices.
37 *
38 * TLB entries of such buffers will not be flushed across
39 * task switches.
40 */
41
42/*
43 * on UP currently we will have no trace of the fixmap mechanism,
44 * no page table allocations, etc. This might change in the
45 * future, say framebuffers for the console driver(s) could be
46 * fix-mapped?
47 */
48enum fixed_addresses {
49 FIX_HOLE,
50#ifdef CONFIG_HIGHMEM
51 FIX_KMAP_BEGIN,
52 FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
53#endif
54 __end_of_fixed_addresses
55};
56
57extern void __set_fixmap (enum fixed_addresses idx,
58 unsigned long phys, pgprot_t flags);
59
60#define set_fixmap(idx, phys) \
61 __set_fixmap(idx, phys, PAGE_KERNEL)
62/*
63 * Some hardware wants to get fixmapped without caching.
64 */
65#define set_fixmap_nocache(idx, phys) \
66 __set_fixmap(idx, phys, PAGE_KERNEL_NOCACHE)
67/*
68 * used by vmalloc.c.
69 *
70 * Leave one empty page between IO pages at 0xfd000000 and
71 * the start of the fixmap.
72 */
73#define FIXADDR_TOP (0xfcfff000UL)
74#define FIXADDR_SIZE ((__end_of_fixed_addresses) << PAGE_SHIFT)
75#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
76
77#define __fix_to_virt(x) (FIXADDR_TOP - ((x) << PAGE_SHIFT))
78#define __virt_to_fix(x) ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
79
80extern void __this_fixmap_does_not_exist(void);
81
82/*
83 * 'index to address' translation. If anyone tries to use the idx
84 * directly without tranlation, we catch the bug with a NULL-deference
85 * kernel oops. Illegal ranges of incoming indices are caught too.
86 */
87static inline unsigned long fix_to_virt(const unsigned int idx)
88{
89 /*
90 * this branch gets completely eliminated after inlining,
91 * except when someone tries to use fixaddr indices in an
92 * illegal way. (such as mixing up address types or using
93 * out-of-range indices).
94 *
95 * If it doesn't get removed, the linker will complain
96 * loudly with a reasonably clear error message..
97 */
98 if (idx >= __end_of_fixed_addresses)
99 __this_fixmap_does_not_exist();
100
101 return __fix_to_virt(idx);
102}
103
104static inline unsigned long virt_to_fix(const unsigned long vaddr)
105{
106 BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
107 return __virt_to_fix(vaddr);
108}
109
110#endif
diff --git a/include/asm-sparc/floppy.h b/include/asm-sparc/floppy.h
deleted file mode 100644
index 6c628ba15a8..00000000000
--- a/include/asm-sparc/floppy.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_FLOPPY_H
2#define ___ASM_SPARC_FLOPPY_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/floppy_64.h>
5#else
6#include <asm-sparc/floppy_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/floppy_32.h b/include/asm-sparc/floppy_32.h
deleted file mode 100644
index acdd06eafe5..00000000000
--- a/include/asm-sparc/floppy_32.h
+++ /dev/null
@@ -1,388 +0,0 @@
1/* asm-sparc/floppy.h: Sparc specific parts of the Floppy driver.
2 *
3 * Copyright (C) 1995 David S. Miller (davem@davemloft.net)
4 */
5
6#ifndef __ASM_SPARC_FLOPPY_H
7#define __ASM_SPARC_FLOPPY_H
8
9#include <asm/page.h>
10#include <asm/pgtable.h>
11#include <asm/system.h>
12#include <asm/idprom.h>
13#include <asm/machines.h>
14#include <asm/oplib.h>
15#include <asm/auxio.h>
16#include <asm/irq.h>
17
18/* We don't need no stinkin' I/O port allocation crap. */
19#undef release_region
20#undef request_region
21#define release_region(X, Y) do { } while(0)
22#define request_region(X, Y, Z) (1)
23
24/* References:
25 * 1) Netbsd Sun floppy driver.
26 * 2) NCR 82077 controller manual
27 * 3) Intel 82077 controller manual
28 */
29struct sun_flpy_controller {
30 volatile unsigned char status_82072; /* Main Status reg. */
31#define dcr_82072 status_82072 /* Digital Control reg. */
32#define status1_82077 status_82072 /* Auxiliary Status reg. 1 */
33
34 volatile unsigned char data_82072; /* Data fifo. */
35#define status2_82077 data_82072 /* Auxiliary Status reg. 2 */
36
37 volatile unsigned char dor_82077; /* Digital Output reg. */
38 volatile unsigned char tapectl_82077; /* What the? Tape control reg? */
39
40 volatile unsigned char status_82077; /* Main Status Register. */
41#define drs_82077 status_82077 /* Digital Rate Select reg. */
42
43 volatile unsigned char data_82077; /* Data fifo. */
44 volatile unsigned char ___unused;
45 volatile unsigned char dir_82077; /* Digital Input reg. */
46#define dcr_82077 dir_82077 /* Config Control reg. */
47};
48
49/* You'll only ever find one controller on a SparcStation anyways. */
50static struct sun_flpy_controller *sun_fdc = NULL;
51extern volatile unsigned char *fdc_status;
52
53struct sun_floppy_ops {
54 unsigned char (*fd_inb)(int port);
55 void (*fd_outb)(unsigned char value, int port);
56};
57
58static struct sun_floppy_ops sun_fdops;
59
60#define fd_inb(port) sun_fdops.fd_inb(port)
61#define fd_outb(value,port) sun_fdops.fd_outb(value,port)
62#define fd_enable_dma() sun_fd_enable_dma()
63#define fd_disable_dma() sun_fd_disable_dma()
64#define fd_request_dma() (0) /* nothing... */
65#define fd_free_dma() /* nothing... */
66#define fd_clear_dma_ff() /* nothing... */
67#define fd_set_dma_mode(mode) sun_fd_set_dma_mode(mode)
68#define fd_set_dma_addr(addr) sun_fd_set_dma_addr(addr)
69#define fd_set_dma_count(count) sun_fd_set_dma_count(count)
70#define fd_enable_irq() /* nothing... */
71#define fd_disable_irq() /* nothing... */
72#define fd_cacheflush(addr, size) /* nothing... */
73#define fd_request_irq() sun_fd_request_irq()
74#define fd_free_irq() /* nothing... */
75#if 0 /* P3: added by Alain, these cause a MMU corruption. 19960524 XXX */
76#define fd_dma_mem_alloc(size) ((unsigned long) vmalloc(size))
77#define fd_dma_mem_free(addr,size) (vfree((void *)(addr)))
78#endif
79
80/* XXX This isn't really correct. XXX */
81#define get_dma_residue(x) (0)
82
83#define FLOPPY0_TYPE 4
84#define FLOPPY1_TYPE 0
85
86/* Super paranoid... */
87#undef HAVE_DISABLE_HLT
88
89/* Here is where we catch the floppy driver trying to initialize,
90 * therefore this is where we call the PROM device tree probing
91 * routine etc. on the Sparc.
92 */
93#define FDC1 sun_floppy_init()
94
95#define N_FDC 1
96#define N_DRIVE 8
97
98/* No 64k boundary crossing problems on the Sparc. */
99#define CROSS_64KB(a,s) (0)
100
101/* Routines unique to each controller type on a Sun. */
102static void sun_set_dor(unsigned char value, int fdc_82077)
103{
104 if (sparc_cpu_model == sun4c) {
105 unsigned int bits = 0;
106 if (value & 0x10)
107 bits |= AUXIO_FLPY_DSEL;
108 if ((value & 0x80) == 0)
109 bits |= AUXIO_FLPY_EJCT;
110 set_auxio(bits, (~bits) & (AUXIO_FLPY_DSEL|AUXIO_FLPY_EJCT));
111 }
112 if (fdc_82077) {
113 sun_fdc->dor_82077 = value;
114 }
115}
116
117static unsigned char sun_read_dir(void)
118{
119 if (sparc_cpu_model == sun4c)
120 return (get_auxio() & AUXIO_FLPY_DCHG) ? 0x80 : 0;
121 else
122 return sun_fdc->dir_82077;
123}
124
125static unsigned char sun_82072_fd_inb(int port)
126{
127 udelay(5);
128 switch(port & 7) {
129 default:
130 printk("floppy: Asked to read unknown port %d\n", port);
131 panic("floppy: Port bolixed.");
132 case 4: /* FD_STATUS */
133 return sun_fdc->status_82072 & ~STATUS_DMA;
134 case 5: /* FD_DATA */
135 return sun_fdc->data_82072;
136 case 7: /* FD_DIR */
137 return sun_read_dir();
138 };
139 panic("sun_82072_fd_inb: How did I get here?");
140}
141
142static void sun_82072_fd_outb(unsigned char value, int port)
143{
144 udelay(5);
145 switch(port & 7) {
146 default:
147 printk("floppy: Asked to write to unknown port %d\n", port);
148 panic("floppy: Port bolixed.");
149 case 2: /* FD_DOR */
150 sun_set_dor(value, 0);
151 break;
152 case 5: /* FD_DATA */
153 sun_fdc->data_82072 = value;
154 break;
155 case 7: /* FD_DCR */
156 sun_fdc->dcr_82072 = value;
157 break;
158 case 4: /* FD_STATUS */
159 sun_fdc->status_82072 = value;
160 break;
161 };
162 return;
163}
164
165static unsigned char sun_82077_fd_inb(int port)
166{
167 udelay(5);
168 switch(port & 7) {
169 default:
170 printk("floppy: Asked to read unknown port %d\n", port);
171 panic("floppy: Port bolixed.");
172 case 0: /* FD_STATUS_0 */
173 return sun_fdc->status1_82077;
174 case 1: /* FD_STATUS_1 */
175 return sun_fdc->status2_82077;
176 case 2: /* FD_DOR */
177 return sun_fdc->dor_82077;
178 case 3: /* FD_TDR */
179 return sun_fdc->tapectl_82077;
180 case 4: /* FD_STATUS */
181 return sun_fdc->status_82077 & ~STATUS_DMA;
182 case 5: /* FD_DATA */
183 return sun_fdc->data_82077;
184 case 7: /* FD_DIR */
185 return sun_read_dir();
186 };
187 panic("sun_82077_fd_inb: How did I get here?");
188}
189
190static void sun_82077_fd_outb(unsigned char value, int port)
191{
192 udelay(5);
193 switch(port & 7) {
194 default:
195 printk("floppy: Asked to write to unknown port %d\n", port);
196 panic("floppy: Port bolixed.");
197 case 2: /* FD_DOR */
198 sun_set_dor(value, 1);
199 break;
200 case 5: /* FD_DATA */
201 sun_fdc->data_82077 = value;
202 break;
203 case 7: /* FD_DCR */
204 sun_fdc->dcr_82077 = value;
205 break;
206 case 4: /* FD_STATUS */
207 sun_fdc->status_82077 = value;
208 break;
209 case 3: /* FD_TDR */
210 sun_fdc->tapectl_82077 = value;
211 break;
212 };
213 return;
214}
215
216/* For pseudo-dma (Sun floppy drives have no real DMA available to
217 * them so we must eat the data fifo bytes directly ourselves) we have
218 * three state variables. doing_pdma tells our inline low-level
219 * assembly floppy interrupt entry point whether it should sit and eat
220 * bytes from the fifo or just transfer control up to the higher level
221 * floppy interrupt c-code. I tried very hard but I could not get the
222 * pseudo-dma to work in c-code without getting many overruns and
223 * underruns. If non-zero, doing_pdma encodes the direction of
224 * the transfer for debugging. 1=read 2=write
225 */
226extern char *pdma_vaddr;
227extern unsigned long pdma_size;
228extern volatile int doing_pdma;
229
230/* This is software state */
231extern char *pdma_base;
232extern unsigned long pdma_areasize;
233
234/* Common routines to all controller types on the Sparc. */
235static inline void virtual_dma_init(void)
236{
237 /* nothing... */
238}
239
240static inline void sun_fd_disable_dma(void)
241{
242 doing_pdma = 0;
243 if (pdma_base) {
244 mmu_unlockarea(pdma_base, pdma_areasize);
245 pdma_base = NULL;
246 }
247}
248
249static inline void sun_fd_set_dma_mode(int mode)
250{
251 switch(mode) {
252 case DMA_MODE_READ:
253 doing_pdma = 1;
254 break;
255 case DMA_MODE_WRITE:
256 doing_pdma = 2;
257 break;
258 default:
259 printk("Unknown dma mode %d\n", mode);
260 panic("floppy: Giving up...");
261 }
262}
263
264static inline void sun_fd_set_dma_addr(char *buffer)
265{
266 pdma_vaddr = buffer;
267}
268
269static inline void sun_fd_set_dma_count(int length)
270{
271 pdma_size = length;
272}
273
274static inline void sun_fd_enable_dma(void)
275{
276 pdma_vaddr = mmu_lockarea(pdma_vaddr, pdma_size);
277 pdma_base = pdma_vaddr;
278 pdma_areasize = pdma_size;
279}
280
281/* Our low-level entry point in arch/sparc/kernel/entry.S */
282extern int sparc_floppy_request_irq(int irq, unsigned long flags,
283 irq_handler_t irq_handler);
284
285static int sun_fd_request_irq(void)
286{
287 static int once = 0;
288 int error;
289
290 if(!once) {
291 once = 1;
292 error = sparc_floppy_request_irq(FLOPPY_IRQ,
293 IRQF_DISABLED,
294 floppy_interrupt);
295 return ((error == 0) ? 0 : -1);
296 } else return 0;
297}
298
299static struct linux_prom_registers fd_regs[2];
300
301static int sun_floppy_init(void)
302{
303 char state[128];
304 int tnode, fd_node, num_regs;
305 struct resource r;
306
307 use_virtual_dma = 1;
308
309 FLOPPY_IRQ = 11;
310 /* Forget it if we aren't on a machine that could possibly
311 * ever have a floppy drive.
312 */
313 if((sparc_cpu_model != sun4c && sparc_cpu_model != sun4m) ||
314 ((idprom->id_machtype == (SM_SUN4C | SM_4C_SLC)) ||
315 (idprom->id_machtype == (SM_SUN4C | SM_4C_ELC)))) {
316 /* We certainly don't have a floppy controller. */
317 goto no_sun_fdc;
318 }
319 /* Well, try to find one. */
320 tnode = prom_getchild(prom_root_node);
321 fd_node = prom_searchsiblings(tnode, "obio");
322 if(fd_node != 0) {
323 tnode = prom_getchild(fd_node);
324 fd_node = prom_searchsiblings(tnode, "SUNW,fdtwo");
325 } else {
326 fd_node = prom_searchsiblings(tnode, "fd");
327 }
328 if(fd_node == 0) {
329 goto no_sun_fdc;
330 }
331
332 /* The sun4m lets us know if the controller is actually usable. */
333 if(sparc_cpu_model == sun4m &&
334 prom_getproperty(fd_node, "status", state, sizeof(state)) != -1) {
335 if(!strcmp(state, "disabled")) {
336 goto no_sun_fdc;
337 }
338 }
339 num_regs = prom_getproperty(fd_node, "reg", (char *) fd_regs, sizeof(fd_regs));
340 num_regs = (num_regs / sizeof(fd_regs[0]));
341 prom_apply_obio_ranges(fd_regs, num_regs);
342 memset(&r, 0, sizeof(r));
343 r.flags = fd_regs[0].which_io;
344 r.start = fd_regs[0].phys_addr;
345 sun_fdc = (struct sun_flpy_controller *)
346 sbus_ioremap(&r, 0, fd_regs[0].reg_size, "floppy");
347
348 /* Last minute sanity check... */
349 if(sun_fdc->status_82072 == 0xff) {
350 sun_fdc = NULL;
351 goto no_sun_fdc;
352 }
353
354 sun_fdops.fd_inb = sun_82077_fd_inb;
355 sun_fdops.fd_outb = sun_82077_fd_outb;
356 fdc_status = &sun_fdc->status_82077;
357
358 if (sun_fdc->dor_82077 == 0x80) {
359 sun_fdc->dor_82077 = 0x02;
360 if (sun_fdc->dor_82077 == 0x80) {
361 sun_fdops.fd_inb = sun_82072_fd_inb;
362 sun_fdops.fd_outb = sun_82072_fd_outb;
363 fdc_status = &sun_fdc->status_82072;
364 }
365 }
366
367 /* Success... */
368 allowed_drive_mask = 0x01;
369 return (int) sun_fdc;
370
371no_sun_fdc:
372 return -1;
373}
374
375static int sparc_eject(void)
376{
377 set_dor(0x00, 0xff, 0x90);
378 udelay(500);
379 set_dor(0x00, 0x6f, 0x00);
380 udelay(500);
381 return 0;
382}
383
384#define fd_eject(drive) sparc_eject()
385
386#define EXTRA_FLOPPY_PARAMS
387
388#endif /* !(__ASM_SPARC_FLOPPY_H) */
diff --git a/include/asm-sparc/floppy_64.h b/include/asm-sparc/floppy_64.h
deleted file mode 100644
index c39db1060bc..00000000000
--- a/include/asm-sparc/floppy_64.h
+++ /dev/null
@@ -1,782 +0,0 @@
1/* floppy.h: Sparc specific parts of the Floppy driver.
2 *
3 * Copyright (C) 1996, 2007 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
5 *
6 * Ultra/PCI support added: Sep 1997 Eddie C. Dost (ecd@skynet.be)
7 */
8
9#ifndef __ASM_SPARC64_FLOPPY_H
10#define __ASM_SPARC64_FLOPPY_H
11
12#include <linux/init.h>
13#include <linux/pci.h>
14
15#include <asm/page.h>
16#include <asm/pgtable.h>
17#include <asm/system.h>
18#include <asm/idprom.h>
19#include <asm/oplib.h>
20#include <asm/auxio.h>
21#include <asm/sbus.h>
22#include <asm/irq.h>
23
24
25/*
26 * Define this to enable exchanging drive 0 and 1 if only drive 1 is
27 * probed on PCI machines.
28 */
29#undef PCI_FDC_SWAP_DRIVES
30
31
32/* References:
33 * 1) Netbsd Sun floppy driver.
34 * 2) NCR 82077 controller manual
35 * 3) Intel 82077 controller manual
36 */
37struct sun_flpy_controller {
38 volatile unsigned char status1_82077; /* Auxiliary Status reg. 1 */
39 volatile unsigned char status2_82077; /* Auxiliary Status reg. 2 */
40 volatile unsigned char dor_82077; /* Digital Output reg. */
41 volatile unsigned char tapectl_82077; /* Tape Control reg */
42 volatile unsigned char status_82077; /* Main Status Register. */
43#define drs_82077 status_82077 /* Digital Rate Select reg. */
44 volatile unsigned char data_82077; /* Data fifo. */
45 volatile unsigned char ___unused;
46 volatile unsigned char dir_82077; /* Digital Input reg. */
47#define dcr_82077 dir_82077 /* Config Control reg. */
48};
49
50/* You'll only ever find one controller on an Ultra anyways. */
51static struct sun_flpy_controller *sun_fdc = (struct sun_flpy_controller *)-1;
52unsigned long fdc_status;
53static struct sbus_dev *floppy_sdev = NULL;
54
55struct sun_floppy_ops {
56 unsigned char (*fd_inb) (unsigned long port);
57 void (*fd_outb) (unsigned char value, unsigned long port);
58 void (*fd_enable_dma) (void);
59 void (*fd_disable_dma) (void);
60 void (*fd_set_dma_mode) (int);
61 void (*fd_set_dma_addr) (char *);
62 void (*fd_set_dma_count) (int);
63 unsigned int (*get_dma_residue) (void);
64 int (*fd_request_irq) (void);
65 void (*fd_free_irq) (void);
66 int (*fd_eject) (int);
67};
68
69static struct sun_floppy_ops sun_fdops;
70
71#define fd_inb(port) sun_fdops.fd_inb(port)
72#define fd_outb(value,port) sun_fdops.fd_outb(value,port)
73#define fd_enable_dma() sun_fdops.fd_enable_dma()
74#define fd_disable_dma() sun_fdops.fd_disable_dma()
75#define fd_request_dma() (0) /* nothing... */
76#define fd_free_dma() /* nothing... */
77#define fd_clear_dma_ff() /* nothing... */
78#define fd_set_dma_mode(mode) sun_fdops.fd_set_dma_mode(mode)
79#define fd_set_dma_addr(addr) sun_fdops.fd_set_dma_addr(addr)
80#define fd_set_dma_count(count) sun_fdops.fd_set_dma_count(count)
81#define get_dma_residue(x) sun_fdops.get_dma_residue()
82#define fd_cacheflush(addr, size) /* nothing... */
83#define fd_request_irq() sun_fdops.fd_request_irq()
84#define fd_free_irq() sun_fdops.fd_free_irq()
85#define fd_eject(drive) sun_fdops.fd_eject(drive)
86
87/* Super paranoid... */
88#undef HAVE_DISABLE_HLT
89
90static int sun_floppy_types[2] = { 0, 0 };
91
92/* Here is where we catch the floppy driver trying to initialize,
93 * therefore this is where we call the PROM device tree probing
94 * routine etc. on the Sparc.
95 */
96#define FLOPPY0_TYPE sun_floppy_init()
97#define FLOPPY1_TYPE sun_floppy_types[1]
98
99#define FDC1 ((unsigned long)sun_fdc)
100
101#define N_FDC 1
102#define N_DRIVE 8
103
104/* No 64k boundary crossing problems on the Sparc. */
105#define CROSS_64KB(a,s) (0)
106
107static unsigned char sun_82077_fd_inb(unsigned long port)
108{
109 udelay(5);
110 switch(port & 7) {
111 default:
112 printk("floppy: Asked to read unknown port %lx\n", port);
113 panic("floppy: Port bolixed.");
114 case 4: /* FD_STATUS */
115 return sbus_readb(&sun_fdc->status_82077) & ~STATUS_DMA;
116 case 5: /* FD_DATA */
117 return sbus_readb(&sun_fdc->data_82077);
118 case 7: /* FD_DIR */
119 /* XXX: Is DCL on 0x80 in sun4m? */
120 return sbus_readb(&sun_fdc->dir_82077);
121 };
122 panic("sun_82072_fd_inb: How did I get here?");
123}
124
125static void sun_82077_fd_outb(unsigned char value, unsigned long port)
126{
127 udelay(5);
128 switch(port & 7) {
129 default:
130 printk("floppy: Asked to write to unknown port %lx\n", port);
131 panic("floppy: Port bolixed.");
132 case 2: /* FD_DOR */
133 /* Happily, the 82077 has a real DOR register. */
134 sbus_writeb(value, &sun_fdc->dor_82077);
135 break;
136 case 5: /* FD_DATA */
137 sbus_writeb(value, &sun_fdc->data_82077);
138 break;
139 case 7: /* FD_DCR */
140 sbus_writeb(value, &sun_fdc->dcr_82077);
141 break;
142 case 4: /* FD_STATUS */
143 sbus_writeb(value, &sun_fdc->status_82077);
144 break;
145 };
146 return;
147}
148
149/* For pseudo-dma (Sun floppy drives have no real DMA available to
150 * them so we must eat the data fifo bytes directly ourselves) we have
151 * three state variables. doing_pdma tells our inline low-level
152 * assembly floppy interrupt entry point whether it should sit and eat
153 * bytes from the fifo or just transfer control up to the higher level
154 * floppy interrupt c-code. I tried very hard but I could not get the
155 * pseudo-dma to work in c-code without getting many overruns and
156 * underruns. If non-zero, doing_pdma encodes the direction of
157 * the transfer for debugging. 1=read 2=write
158 */
159unsigned char *pdma_vaddr;
160unsigned long pdma_size;
161volatile int doing_pdma = 0;
162
163/* This is software state */
164char *pdma_base = NULL;
165unsigned long pdma_areasize;
166
167/* Common routines to all controller types on the Sparc. */
168static void sun_fd_disable_dma(void)
169{
170 doing_pdma = 0;
171 if (pdma_base) {
172 mmu_unlockarea(pdma_base, pdma_areasize);
173 pdma_base = NULL;
174 }
175}
176
177static void sun_fd_set_dma_mode(int mode)
178{
179 switch(mode) {
180 case DMA_MODE_READ:
181 doing_pdma = 1;
182 break;
183 case DMA_MODE_WRITE:
184 doing_pdma = 2;
185 break;
186 default:
187 printk("Unknown dma mode %d\n", mode);
188 panic("floppy: Giving up...");
189 }
190}
191
192static void sun_fd_set_dma_addr(char *buffer)
193{
194 pdma_vaddr = buffer;
195}
196
197static void sun_fd_set_dma_count(int length)
198{
199 pdma_size = length;
200}
201
202static void sun_fd_enable_dma(void)
203{
204 pdma_vaddr = mmu_lockarea(pdma_vaddr, pdma_size);
205 pdma_base = pdma_vaddr;
206 pdma_areasize = pdma_size;
207}
208
209irqreturn_t sparc_floppy_irq(int irq, void *dev_cookie)
210{
211 if (likely(doing_pdma)) {
212 void __iomem *stat = (void __iomem *) fdc_status;
213 unsigned char *vaddr = pdma_vaddr;
214 unsigned long size = pdma_size;
215 u8 val;
216
217 while (size) {
218 val = readb(stat);
219 if (unlikely(!(val & 0x80))) {
220 pdma_vaddr = vaddr;
221 pdma_size = size;
222 return IRQ_HANDLED;
223 }
224 if (unlikely(!(val & 0x20))) {
225 pdma_vaddr = vaddr;
226 pdma_size = size;
227 doing_pdma = 0;
228 goto main_interrupt;
229 }
230 if (val & 0x40) {
231 /* read */
232 *vaddr++ = readb(stat + 1);
233 } else {
234 unsigned char data = *vaddr++;
235
236 /* write */
237 writeb(data, stat + 1);
238 }
239 size--;
240 }
241
242 pdma_vaddr = vaddr;
243 pdma_size = size;
244
245 /* Send Terminal Count pulse to floppy controller. */
246 val = readb(auxio_register);
247 val |= AUXIO_AUX1_FTCNT;
248 writeb(val, auxio_register);
249 val &= ~AUXIO_AUX1_FTCNT;
250 writeb(val, auxio_register);
251
252 doing_pdma = 0;
253 }
254
255main_interrupt:
256 return floppy_interrupt(irq, dev_cookie);
257}
258
259static int sun_fd_request_irq(void)
260{
261 static int once = 0;
262 int error;
263
264 if(!once) {
265 once = 1;
266
267 error = request_irq(FLOPPY_IRQ, sparc_floppy_irq,
268 IRQF_DISABLED, "floppy", NULL);
269
270 return ((error == 0) ? 0 : -1);
271 }
272 return 0;
273}
274
275static void sun_fd_free_irq(void)
276{
277}
278
279static unsigned int sun_get_dma_residue(void)
280{
281 /* XXX This isn't really correct. XXX */
282 return 0;
283}
284
285static int sun_fd_eject(int drive)
286{
287 set_dor(0x00, 0xff, 0x90);
288 udelay(500);
289 set_dor(0x00, 0x6f, 0x00);
290 udelay(500);
291 return 0;
292}
293
294#ifdef CONFIG_PCI
295#include <asm/ebus.h>
296#include <asm/ns87303.h>
297
298static struct ebus_dma_info sun_pci_fd_ebus_dma;
299static struct pci_dev *sun_pci_ebus_dev;
300static int sun_pci_broken_drive = -1;
301
302struct sun_pci_dma_op {
303 unsigned int addr;
304 int len;
305 int direction;
306 char *buf;
307};
308static struct sun_pci_dma_op sun_pci_dma_current = { -1U, 0, 0, NULL};
309static struct sun_pci_dma_op sun_pci_dma_pending = { -1U, 0, 0, NULL};
310
311extern irqreturn_t floppy_interrupt(int irq, void *dev_id);
312
313static unsigned char sun_pci_fd_inb(unsigned long port)
314{
315 udelay(5);
316 return inb(port);
317}
318
319static void sun_pci_fd_outb(unsigned char val, unsigned long port)
320{
321 udelay(5);
322 outb(val, port);
323}
324
325static void sun_pci_fd_broken_outb(unsigned char val, unsigned long port)
326{
327 udelay(5);
328 /*
329 * XXX: Due to SUN's broken floppy connector on AX and AXi
330 * we need to turn on MOTOR_0 also, if the floppy is
331 * jumpered to DS1 (like most PC floppies are). I hope
332 * this does not hurt correct hardware like the AXmp.
333 * (Eddie, Sep 12 1998).
334 */
335 if (port == ((unsigned long)sun_fdc) + 2) {
336 if (((val & 0x03) == sun_pci_broken_drive) && (val & 0x20)) {
337 val |= 0x10;
338 }
339 }
340 outb(val, port);
341}
342
343#ifdef PCI_FDC_SWAP_DRIVES
344static void sun_pci_fd_lde_broken_outb(unsigned char val, unsigned long port)
345{
346 udelay(5);
347 /*
348 * XXX: Due to SUN's broken floppy connector on AX and AXi
349 * we need to turn on MOTOR_0 also, if the floppy is
350 * jumpered to DS1 (like most PC floppies are). I hope
351 * this does not hurt correct hardware like the AXmp.
352 * (Eddie, Sep 12 1998).
353 */
354 if (port == ((unsigned long)sun_fdc) + 2) {
355 if (((val & 0x03) == sun_pci_broken_drive) && (val & 0x10)) {
356 val &= ~(0x03);
357 val |= 0x21;
358 }
359 }
360 outb(val, port);
361}
362#endif /* PCI_FDC_SWAP_DRIVES */
363
364static void sun_pci_fd_enable_dma(void)
365{
366 BUG_ON((NULL == sun_pci_dma_pending.buf) ||
367 (0 == sun_pci_dma_pending.len) ||
368 (0 == sun_pci_dma_pending.direction));
369
370 sun_pci_dma_current.buf = sun_pci_dma_pending.buf;
371 sun_pci_dma_current.len = sun_pci_dma_pending.len;
372 sun_pci_dma_current.direction = sun_pci_dma_pending.direction;
373
374 sun_pci_dma_pending.buf = NULL;
375 sun_pci_dma_pending.len = 0;
376 sun_pci_dma_pending.direction = 0;
377 sun_pci_dma_pending.addr = -1U;
378
379 sun_pci_dma_current.addr =
380 pci_map_single(sun_pci_ebus_dev,
381 sun_pci_dma_current.buf,
382 sun_pci_dma_current.len,
383 sun_pci_dma_current.direction);
384
385 ebus_dma_enable(&sun_pci_fd_ebus_dma, 1);
386
387 if (ebus_dma_request(&sun_pci_fd_ebus_dma,
388 sun_pci_dma_current.addr,
389 sun_pci_dma_current.len))
390 BUG();
391}
392
393static void sun_pci_fd_disable_dma(void)
394{
395 ebus_dma_enable(&sun_pci_fd_ebus_dma, 0);
396 if (sun_pci_dma_current.addr != -1U)
397 pci_unmap_single(sun_pci_ebus_dev,
398 sun_pci_dma_current.addr,
399 sun_pci_dma_current.len,
400 sun_pci_dma_current.direction);
401 sun_pci_dma_current.addr = -1U;
402}
403
404static void sun_pci_fd_set_dma_mode(int mode)
405{
406 if (mode == DMA_MODE_WRITE)
407 sun_pci_dma_pending.direction = PCI_DMA_TODEVICE;
408 else
409 sun_pci_dma_pending.direction = PCI_DMA_FROMDEVICE;
410
411 ebus_dma_prepare(&sun_pci_fd_ebus_dma, mode != DMA_MODE_WRITE);
412}
413
414static void sun_pci_fd_set_dma_count(int length)
415{
416 sun_pci_dma_pending.len = length;
417}
418
419static void sun_pci_fd_set_dma_addr(char *buffer)
420{
421 sun_pci_dma_pending.buf = buffer;
422}
423
424static unsigned int sun_pci_get_dma_residue(void)
425{
426 return ebus_dma_residue(&sun_pci_fd_ebus_dma);
427}
428
429static int sun_pci_fd_request_irq(void)
430{
431 return ebus_dma_irq_enable(&sun_pci_fd_ebus_dma, 1);
432}
433
434static void sun_pci_fd_free_irq(void)
435{
436 ebus_dma_irq_enable(&sun_pci_fd_ebus_dma, 0);
437}
438
439static int sun_pci_fd_eject(int drive)
440{
441 return -EINVAL;
442}
443
444void sun_pci_fd_dma_callback(struct ebus_dma_info *p, int event, void *cookie)
445{
446 floppy_interrupt(0, NULL);
447}
448
449/*
450 * Floppy probing, we'd like to use /dev/fd0 for a single Floppy on PCI,
451 * even if this is configured using DS1, thus looks like /dev/fd1 with
452 * the cabling used in Ultras.
453 */
454#define DOR (port + 2)
455#define MSR (port + 4)
456#define FIFO (port + 5)
457
458static void sun_pci_fd_out_byte(unsigned long port, unsigned char val,
459 unsigned long reg)
460{
461 unsigned char status;
462 int timeout = 1000;
463
464 while (!((status = inb(MSR)) & 0x80) && --timeout)
465 udelay(100);
466 outb(val, reg);
467}
468
469static unsigned char sun_pci_fd_sensei(unsigned long port)
470{
471 unsigned char result[2] = { 0x70, 0x00 };
472 unsigned char status;
473 int i = 0;
474
475 sun_pci_fd_out_byte(port, 0x08, FIFO);
476 do {
477 int timeout = 1000;
478
479 while (!((status = inb(MSR)) & 0x80) && --timeout)
480 udelay(100);
481
482 if (!timeout)
483 break;
484
485 if ((status & 0xf0) == 0xd0)
486 result[i++] = inb(FIFO);
487 else
488 break;
489 } while (i < 2);
490
491 return result[0];
492}
493
494static void sun_pci_fd_reset(unsigned long port)
495{
496 unsigned char mask = 0x00;
497 unsigned char status;
498 int timeout = 10000;
499
500 outb(0x80, MSR);
501 do {
502 status = sun_pci_fd_sensei(port);
503 if ((status & 0xc0) == 0xc0)
504 mask |= 1 << (status & 0x03);
505 else
506 udelay(100);
507 } while ((mask != 0x0f) && --timeout);
508}
509
510static int sun_pci_fd_test_drive(unsigned long port, int drive)
511{
512 unsigned char status, data;
513 int timeout = 1000;
514 int ready;
515
516 sun_pci_fd_reset(port);
517
518 data = (0x10 << drive) | 0x0c | drive;
519 sun_pci_fd_out_byte(port, data, DOR);
520
521 sun_pci_fd_out_byte(port, 0x07, FIFO);
522 sun_pci_fd_out_byte(port, drive & 0x03, FIFO);
523
524 do {
525 udelay(100);
526 status = sun_pci_fd_sensei(port);
527 } while (((status & 0xc0) == 0x80) && --timeout);
528
529 if (!timeout)
530 ready = 0;
531 else
532 ready = (status & 0x10) ? 0 : 1;
533
534 sun_pci_fd_reset(port);
535 return ready;
536}
537#undef FIFO
538#undef MSR
539#undef DOR
540
541#endif /* CONFIG_PCI */
542
543#ifdef CONFIG_PCI
544static int __init ebus_fdthree_p(struct linux_ebus_device *edev)
545{
546 if (!strcmp(edev->prom_node->name, "fdthree"))
547 return 1;
548 if (!strcmp(edev->prom_node->name, "floppy")) {
549 const char *compat;
550
551 compat = of_get_property(edev->prom_node,
552 "compatible", NULL);
553 if (compat && !strcmp(compat, "fdthree"))
554 return 1;
555 }
556 return 0;
557}
558#endif
559
560static unsigned long __init sun_floppy_init(void)
561{
562 char state[128];
563 struct sbus_bus *bus;
564 struct sbus_dev *sdev = NULL;
565 static int initialized = 0;
566
567 if (initialized)
568 return sun_floppy_types[0];
569 initialized = 1;
570
571 for_all_sbusdev (sdev, bus) {
572 if (!strcmp(sdev->prom_name, "SUNW,fdtwo"))
573 break;
574 }
575 if(sdev) {
576 floppy_sdev = sdev;
577 FLOPPY_IRQ = sdev->irqs[0];
578 } else {
579#ifdef CONFIG_PCI
580 struct linux_ebus *ebus;
581 struct linux_ebus_device *edev = NULL;
582 unsigned long config = 0;
583 void __iomem *auxio_reg;
584 const char *state_prop;
585
586 for_each_ebus(ebus) {
587 for_each_ebusdev(edev, ebus) {
588 if (ebus_fdthree_p(edev))
589 goto ebus_done;
590 }
591 }
592 ebus_done:
593 if (!edev)
594 return 0;
595
596 state_prop = of_get_property(edev->prom_node, "status", NULL);
597 if (state_prop && !strncmp(state_prop, "disabled", 8))
598 return 0;
599
600 FLOPPY_IRQ = edev->irqs[0];
601
602 /* Make sure the high density bit is set, some systems
603 * (most notably Ultra5/Ultra10) come up with it clear.
604 */
605 auxio_reg = (void __iomem *) edev->resource[2].start;
606 writel(readl(auxio_reg)|0x2, auxio_reg);
607
608 sun_pci_ebus_dev = ebus->self;
609
610 spin_lock_init(&sun_pci_fd_ebus_dma.lock);
611
612 /* XXX ioremap */
613 sun_pci_fd_ebus_dma.regs = (void __iomem *)
614 edev->resource[1].start;
615 if (!sun_pci_fd_ebus_dma.regs)
616 return 0;
617
618 sun_pci_fd_ebus_dma.flags = (EBUS_DMA_FLAG_USE_EBDMA_HANDLER |
619 EBUS_DMA_FLAG_TCI_DISABLE);
620 sun_pci_fd_ebus_dma.callback = sun_pci_fd_dma_callback;
621 sun_pci_fd_ebus_dma.client_cookie = NULL;
622 sun_pci_fd_ebus_dma.irq = FLOPPY_IRQ;
623 strcpy(sun_pci_fd_ebus_dma.name, "floppy");
624 if (ebus_dma_register(&sun_pci_fd_ebus_dma))
625 return 0;
626
627 /* XXX ioremap */
628 sun_fdc = (struct sun_flpy_controller *)edev->resource[0].start;
629
630 sun_fdops.fd_inb = sun_pci_fd_inb;
631 sun_fdops.fd_outb = sun_pci_fd_outb;
632
633 can_use_virtual_dma = use_virtual_dma = 0;
634 sun_fdops.fd_enable_dma = sun_pci_fd_enable_dma;
635 sun_fdops.fd_disable_dma = sun_pci_fd_disable_dma;
636 sun_fdops.fd_set_dma_mode = sun_pci_fd_set_dma_mode;
637 sun_fdops.fd_set_dma_addr = sun_pci_fd_set_dma_addr;
638 sun_fdops.fd_set_dma_count = sun_pci_fd_set_dma_count;
639 sun_fdops.get_dma_residue = sun_pci_get_dma_residue;
640
641 sun_fdops.fd_request_irq = sun_pci_fd_request_irq;
642 sun_fdops.fd_free_irq = sun_pci_fd_free_irq;
643
644 sun_fdops.fd_eject = sun_pci_fd_eject;
645
646 fdc_status = (unsigned long) &sun_fdc->status_82077;
647
648 /*
649 * XXX: Find out on which machines this is really needed.
650 */
651 if (1) {
652 sun_pci_broken_drive = 1;
653 sun_fdops.fd_outb = sun_pci_fd_broken_outb;
654 }
655
656 allowed_drive_mask = 0;
657 if (sun_pci_fd_test_drive((unsigned long)sun_fdc, 0))
658 sun_floppy_types[0] = 4;
659 if (sun_pci_fd_test_drive((unsigned long)sun_fdc, 1))
660 sun_floppy_types[1] = 4;
661
662 /*
663 * Find NS87303 SuperIO config registers (through ecpp).
664 */
665 for_each_ebus(ebus) {
666 for_each_ebusdev(edev, ebus) {
667 if (!strcmp(edev->prom_node->name, "ecpp")) {
668 config = edev->resource[1].start;
669 goto config_done;
670 }
671 }
672 }
673 config_done:
674
675 /*
676 * Sanity check, is this really the NS87303?
677 */
678 switch (config & 0x3ff) {
679 case 0x02e:
680 case 0x15c:
681 case 0x26e:
682 case 0x398:
683 break;
684 default:
685 config = 0;
686 }
687
688 if (!config)
689 return sun_floppy_types[0];
690
691 /* Enable PC-AT mode. */
692 ns87303_modify(config, ASC, 0, 0xc0);
693
694#ifdef PCI_FDC_SWAP_DRIVES
695 /*
696 * If only Floppy 1 is present, swap drives.
697 */
698 if (!sun_floppy_types[0] && sun_floppy_types[1]) {
699 /*
700 * Set the drive exchange bit in FCR on NS87303,
701 * make sure other bits are sane before doing so.
702 */
703 ns87303_modify(config, FER, FER_EDM, 0);
704 ns87303_modify(config, ASC, ASC_DRV2_SEL, 0);
705 ns87303_modify(config, FCR, 0, FCR_LDE);
706
707 config = sun_floppy_types[0];
708 sun_floppy_types[0] = sun_floppy_types[1];
709 sun_floppy_types[1] = config;
710
711 if (sun_pci_broken_drive != -1) {
712 sun_pci_broken_drive = 1 - sun_pci_broken_drive;
713 sun_fdops.fd_outb = sun_pci_fd_lde_broken_outb;
714 }
715 }
716#endif /* PCI_FDC_SWAP_DRIVES */
717
718 return sun_floppy_types[0];
719#else
720 return 0;
721#endif
722 }
723 prom_getproperty(sdev->prom_node, "status", state, sizeof(state));
724 if(!strncmp(state, "disabled", 8))
725 return 0;
726
727 /*
728 * We cannot do sbus_ioremap here: it does request_region,
729 * which the generic floppy driver tries to do once again.
730 * But we must use the sdev resource values as they have
731 * had parent ranges applied.
732 */
733 sun_fdc = (struct sun_flpy_controller *)
734 (sdev->resource[0].start +
735 ((sdev->resource[0].flags & 0x1ffUL) << 32UL));
736
737 /* Last minute sanity check... */
738 if(sbus_readb(&sun_fdc->status1_82077) == 0xff) {
739 sun_fdc = (struct sun_flpy_controller *)-1;
740 return 0;
741 }
742
743 sun_fdops.fd_inb = sun_82077_fd_inb;
744 sun_fdops.fd_outb = sun_82077_fd_outb;
745
746 can_use_virtual_dma = use_virtual_dma = 1;
747 sun_fdops.fd_enable_dma = sun_fd_enable_dma;
748 sun_fdops.fd_disable_dma = sun_fd_disable_dma;
749 sun_fdops.fd_set_dma_mode = sun_fd_set_dma_mode;
750 sun_fdops.fd_set_dma_addr = sun_fd_set_dma_addr;
751 sun_fdops.fd_set_dma_count = sun_fd_set_dma_count;
752 sun_fdops.get_dma_residue = sun_get_dma_residue;
753
754 sun_fdops.fd_request_irq = sun_fd_request_irq;
755 sun_fdops.fd_free_irq = sun_fd_free_irq;
756
757 sun_fdops.fd_eject = sun_fd_eject;
758
759 fdc_status = (unsigned long) &sun_fdc->status_82077;
760
761 /* Success... */
762 allowed_drive_mask = 0x01;
763 sun_floppy_types[0] = 4;
764 sun_floppy_types[1] = 0;
765
766 return sun_floppy_types[0];
767}
768
769#define EXTRA_FLOPPY_PARAMS
770
771static DEFINE_SPINLOCK(dma_spin_lock);
772
773#define claim_dma_lock() \
774({ unsigned long flags; \
775 spin_lock_irqsave(&dma_spin_lock, flags); \
776 flags; \
777})
778
779#define release_dma_lock(__flags) \
780 spin_unlock_irqrestore(&dma_spin_lock, __flags);
781
782#endif /* !(__ASM_SPARC64_FLOPPY_H) */
diff --git a/include/asm-sparc/fpumacro.h b/include/asm-sparc/fpumacro.h
deleted file mode 100644
index cc463fec806..00000000000
--- a/include/asm-sparc/fpumacro.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/* fpumacro.h: FPU related macros.
2 *
3 * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
4 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
5 */
6
7#ifndef _SPARC64_FPUMACRO_H
8#define _SPARC64_FPUMACRO_H
9
10#include <asm/asi.h>
11#include <asm/visasm.h>
12
13struct fpustate {
14 u32 regs[64];
15};
16
17#define FPUSTATE (struct fpustate *)(current_thread_info()->fpregs)
18
19static inline unsigned long fprs_read(void)
20{
21 unsigned long retval;
22
23 __asm__ __volatile__("rd %%fprs, %0" : "=r" (retval));
24
25 return retval;
26}
27
28static inline void fprs_write(unsigned long val)
29{
30 __asm__ __volatile__("wr %0, 0x0, %%fprs" : : "r" (val));
31}
32
33#endif /* !(_SPARC64_FPUMACRO_H) */
diff --git a/include/asm-sparc/futex.h b/include/asm-sparc/futex.h
deleted file mode 100644
index c6a9f038c53..00000000000
--- a/include/asm-sparc/futex.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_FUTEX_H
2#define ___ASM_SPARC_FUTEX_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/futex_64.h>
5#else
6#include <asm-sparc/futex_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/futex_32.h b/include/asm-sparc/futex_32.h
deleted file mode 100644
index 6a332a9f099..00000000000
--- a/include/asm-sparc/futex_32.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _ASM_FUTEX_H
2#define _ASM_FUTEX_H
3
4#include <asm-generic/futex.h>
5
6#endif
diff --git a/include/asm-sparc/futex_64.h b/include/asm-sparc/futex_64.h
deleted file mode 100644
index d8378935ae9..00000000000
--- a/include/asm-sparc/futex_64.h
+++ /dev/null
@@ -1,110 +0,0 @@
1#ifndef _SPARC64_FUTEX_H
2#define _SPARC64_FUTEX_H
3
4#include <linux/futex.h>
5#include <linux/uaccess.h>
6#include <asm/errno.h>
7#include <asm/system.h>
8
9#define __futex_cas_op(insn, ret, oldval, uaddr, oparg) \
10 __asm__ __volatile__( \
11 "\n1: lduwa [%3] %%asi, %2\n" \
12 " " insn "\n" \
13 "2: casa [%3] %%asi, %2, %1\n" \
14 " cmp %2, %1\n" \
15 " bne,pn %%icc, 1b\n" \
16 " mov 0, %0\n" \
17 "3:\n" \
18 " .section .fixup,#alloc,#execinstr\n" \
19 " .align 4\n" \
20 "4: sethi %%hi(3b), %0\n" \
21 " jmpl %0 + %%lo(3b), %%g0\n" \
22 " mov %5, %0\n" \
23 " .previous\n" \
24 " .section __ex_table,\"a\"\n" \
25 " .align 4\n" \
26 " .word 1b, 4b\n" \
27 " .word 2b, 4b\n" \
28 " .previous\n" \
29 : "=&r" (ret), "=&r" (oldval), "=&r" (tem) \
30 : "r" (uaddr), "r" (oparg), "i" (-EFAULT) \
31 : "memory")
32
33static inline int futex_atomic_op_inuser(int encoded_op, int __user *uaddr)
34{
35 int op = (encoded_op >> 28) & 7;
36 int cmp = (encoded_op >> 24) & 15;
37 int oparg = (encoded_op << 8) >> 20;
38 int cmparg = (encoded_op << 20) >> 20;
39 int oldval = 0, ret, tem;
40
41 if (unlikely(!access_ok(VERIFY_WRITE, uaddr, sizeof(int))))
42 return -EFAULT;
43 if (unlikely((((unsigned long) uaddr) & 0x3UL)))
44 return -EINVAL;
45
46 if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
47 oparg = 1 << oparg;
48
49 pagefault_disable();
50
51 switch (op) {
52 case FUTEX_OP_SET:
53 __futex_cas_op("mov\t%4, %1", ret, oldval, uaddr, oparg);
54 break;
55 case FUTEX_OP_ADD:
56 __futex_cas_op("add\t%2, %4, %1", ret, oldval, uaddr, oparg);
57 break;
58 case FUTEX_OP_OR:
59 __futex_cas_op("or\t%2, %4, %1", ret, oldval, uaddr, oparg);
60 break;
61 case FUTEX_OP_ANDN:
62 __futex_cas_op("and\t%2, %4, %1", ret, oldval, uaddr, oparg);
63 break;
64 case FUTEX_OP_XOR:
65 __futex_cas_op("xor\t%2, %4, %1", ret, oldval, uaddr, oparg);
66 break;
67 default:
68 ret = -ENOSYS;
69 }
70
71 pagefault_enable();
72
73 if (!ret) {
74 switch (cmp) {
75 case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
76 case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
77 case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
78 case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
79 case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
80 case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
81 default: ret = -ENOSYS;
82 }
83 }
84 return ret;
85}
86
87static inline int
88futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
89{
90 __asm__ __volatile__(
91 "\n1: casa [%3] %%asi, %2, %0\n"
92 "2:\n"
93 " .section .fixup,#alloc,#execinstr\n"
94 " .align 4\n"
95 "3: sethi %%hi(2b), %0\n"
96 " jmpl %0 + %%lo(2b), %%g0\n"
97 " mov %4, %0\n"
98 " .previous\n"
99 " .section __ex_table,\"a\"\n"
100 " .align 4\n"
101 " .word 1b, 3b\n"
102 " .previous\n"
103 : "=r" (newval)
104 : "0" (newval), "r" (oldval), "r" (uaddr), "i" (-EFAULT)
105 : "memory");
106
107 return newval;
108}
109
110#endif /* !(_SPARC64_FUTEX_H) */
diff --git a/include/asm-sparc/hardirq.h b/include/asm-sparc/hardirq.h
deleted file mode 100644
index 15647877310..00000000000
--- a/include/asm-sparc/hardirq.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_HARDIRQ_H
2#define ___ASM_SPARC_HARDIRQ_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/hardirq_64.h>
5#else
6#include <asm-sparc/hardirq_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/hardirq_32.h b/include/asm-sparc/hardirq_32.h
deleted file mode 100644
index 4f63ed8df55..00000000000
--- a/include/asm-sparc/hardirq_32.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/* hardirq.h: 32-bit Sparc hard IRQ support.
2 *
3 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
4 * Copyright (C) 1998-2000 Anton Blanchard (anton@samba.org)
5 */
6
7#ifndef __SPARC_HARDIRQ_H
8#define __SPARC_HARDIRQ_H
9
10#include <linux/threads.h>
11#include <linux/spinlock.h>
12#include <linux/cache.h>
13
14/* entry.S is sensitive to the offsets of these fields */ /* XXX P3 Is it? */
15typedef struct {
16 unsigned int __softirq_pending;
17} ____cacheline_aligned irq_cpustat_t;
18
19#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
20
21#define HARDIRQ_BITS 8
22
23#endif /* __SPARC_HARDIRQ_H */
diff --git a/include/asm-sparc/hardirq_64.h b/include/asm-sparc/hardirq_64.h
deleted file mode 100644
index 7c29fd1a87a..00000000000
--- a/include/asm-sparc/hardirq_64.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/* hardirq.h: 64-bit Sparc hard IRQ support.
2 *
3 * Copyright (C) 1997, 1998, 2005 David S. Miller (davem@davemloft.net)
4 */
5
6#ifndef __SPARC64_HARDIRQ_H
7#define __SPARC64_HARDIRQ_H
8
9#include <asm/cpudata.h>
10
11#define __ARCH_IRQ_STAT
12#define local_softirq_pending() \
13 (local_cpu_data().__softirq_pending)
14
15void ack_bad_irq(unsigned int irq);
16
17#define HARDIRQ_BITS 8
18
19#endif /* !(__SPARC64_HARDIRQ_H) */
diff --git a/include/asm-sparc/head.h b/include/asm-sparc/head.h
deleted file mode 100644
index 14652abdea3..00000000000
--- a/include/asm-sparc/head.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_HEAD_H
2#define ___ASM_SPARC_HEAD_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/head_64.h>
5#else
6#include <asm-sparc/head_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/head_32.h b/include/asm-sparc/head_32.h
deleted file mode 100644
index 7c35491a8b5..00000000000
--- a/include/asm-sparc/head_32.h
+++ /dev/null
@@ -1,102 +0,0 @@
1#ifndef __SPARC_HEAD_H
2#define __SPARC_HEAD_H
3
4#define KERNBASE 0xf0000000 /* First address the kernel will eventually be */
5#define LOAD_ADDR 0x4000 /* prom jumps to us here unless this is elf /boot */
6#define SUN4C_SEGSZ (1 << 18)
7#define SRMMU_L1_KBASE_OFFSET ((KERNBASE>>24)<<2) /* Used in boot remapping. */
8#define INTS_ENAB 0x01 /* entry.S uses this. */
9
10#define SUN4_PROM_VECTOR 0xFFE81000 /* SUN4 PROM needs to be hardwired */
11
12#define WRITE_PAUSE nop; nop; nop; /* Have to do this after %wim/%psr chg */
13#define NOP_INSN 0x01000000 /* Used to patch sparc_save_state */
14
15/* Here are some trap goodies */
16
17/* Generic trap entry. */
18#define TRAP_ENTRY(type, label) \
19 rd %psr, %l0; b label; rd %wim, %l3; nop;
20
21/* Data/text faults. Defaults to sun4c version at boot time. */
22#define SPARC_TFAULT rd %psr, %l0; rd %wim, %l3; b sun4c_fault; mov 1, %l7;
23#define SPARC_DFAULT rd %psr, %l0; rd %wim, %l3; b sun4c_fault; mov 0, %l7;
24#define SRMMU_TFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 1, %l7;
25#define SRMMU_DFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 0, %l7;
26
27/* This is for traps we should NEVER get. */
28#define BAD_TRAP(num) \
29 rd %psr, %l0; mov num, %l7; b bad_trap_handler; rd %wim, %l3;
30
31/* This is for traps when we want just skip the instruction which caused it */
32#define SKIP_TRAP(type, name) \
33 jmpl %l2, %g0; rett %l2 + 4; nop; nop;
34
35/* Notice that for the system calls we pull a trick. We load up a
36 * different pointer to the system call vector table in %l7, but call
37 * the same generic system call low-level entry point. The trap table
38 * entry sequences are also HyperSparc pipeline friendly ;-)
39 */
40
41/* Software trap for Linux system calls. */
42#define LINUX_SYSCALL_TRAP \
43 sethi %hi(sys_call_table), %l7; \
44 or %l7, %lo(sys_call_table), %l7; \
45 b linux_sparc_syscall; \
46 rd %psr, %l0;
47
48#define BREAKPOINT_TRAP \
49 b breakpoint_trap; \
50 rd %psr,%l0; \
51 nop; \
52 nop;
53
54#ifdef CONFIG_KGDB
55#define KGDB_TRAP(num) \
56 b kgdb_trap_low; \
57 rd %psr,%l0; \
58 nop; \
59 nop;
60#else
61#define KGDB_TRAP(num) \
62 BAD_TRAP(num)
63#endif
64
65/* The Get Condition Codes software trap for userland. */
66#define GETCC_TRAP \
67 b getcc_trap_handler; mov %psr, %l0; nop; nop;
68
69/* The Set Condition Codes software trap for userland. */
70#define SETCC_TRAP \
71 b setcc_trap_handler; mov %psr, %l0; nop; nop;
72
73/* The Get PSR software trap for userland. */
74#define GETPSR_TRAP \
75 mov %psr, %i0; jmp %l2; rett %l2 + 4; nop;
76
77/* This is for hard interrupts from level 1-14, 15 is non-maskable (nmi) and
78 * gets handled with another macro.
79 */
80#define TRAP_ENTRY_INTERRUPT(int_level) \
81 mov int_level, %l7; rd %psr, %l0; b real_irq_entry; rd %wim, %l3;
82
83/* NMI's (Non Maskable Interrupts) are special, you can't keep them
84 * from coming in, and basically if you get one, the shows over. ;(
85 * On the sun4c they are usually asynchronous memory errors, on the
86 * the sun4m they could be either due to mem errors or a software
87 * initiated interrupt from the prom/kern on an SMP box saying "I
88 * command you to do CPU tricks, read your mailbox for more info."
89 */
90#define NMI_TRAP \
91 rd %wim, %l3; b linux_trap_nmi_sun4c; mov %psr, %l0; nop;
92
93/* Window overflows/underflows are special and we need to try to be as
94 * efficient as possible here....
95 */
96#define WINDOW_SPILL \
97 rd %psr, %l0; rd %wim, %l3; b spill_window_entry; andcc %l0, PSR_PS, %g0;
98
99#define WINDOW_FILL \
100 rd %psr, %l0; rd %wim, %l3; b fill_window_entry; andcc %l0, PSR_PS, %g0;
101
102#endif /* __SPARC_HEAD_H */
diff --git a/include/asm-sparc/head_64.h b/include/asm-sparc/head_64.h
deleted file mode 100644
index 10e9dabc4c4..00000000000
--- a/include/asm-sparc/head_64.h
+++ /dev/null
@@ -1,76 +0,0 @@
1#ifndef _SPARC64_HEAD_H
2#define _SPARC64_HEAD_H
3
4#include <asm/pstate.h>
5
6 /* wrpr %g0, val, %gl */
7#define SET_GL(val) \
8 .word 0xa1902000 | val
9
10 /* rdpr %gl, %gN */
11#define GET_GL_GLOBAL(N) \
12 .word 0x81540000 | (N << 25)
13
14#define KERNBASE 0x400000
15
16#define PTREGS_OFF (STACK_BIAS + STACKFRAME_SZ)
17
18#define __CHEETAH_ID 0x003e0014
19#define __JALAPENO_ID 0x003e0016
20#define __SERRANO_ID 0x003e0022
21
22#define CHEETAH_MANUF 0x003e
23#define CHEETAH_IMPL 0x0014 /* Ultra-III */
24#define CHEETAH_PLUS_IMPL 0x0015 /* Ultra-III+ */
25#define JALAPENO_IMPL 0x0016 /* Ultra-IIIi */
26#define JAGUAR_IMPL 0x0018 /* Ultra-IV */
27#define PANTHER_IMPL 0x0019 /* Ultra-IV+ */
28#define SERRANO_IMPL 0x0022 /* Ultra-IIIi+ */
29
30#define BRANCH_IF_SUN4V(tmp1,label) \
31 sethi %hi(is_sun4v), %tmp1; \
32 lduw [%tmp1 + %lo(is_sun4v)], %tmp1; \
33 brnz,pn %tmp1, label; \
34 nop
35
36#define BRANCH_IF_CHEETAH_BASE(tmp1,tmp2,label) \
37 rdpr %ver, %tmp1; \
38 sethi %hi(__CHEETAH_ID), %tmp2; \
39 srlx %tmp1, 32, %tmp1; \
40 or %tmp2, %lo(__CHEETAH_ID), %tmp2;\
41 cmp %tmp1, %tmp2; \
42 be,pn %icc, label; \
43 nop;
44
45#define BRANCH_IF_JALAPENO(tmp1,tmp2,label) \
46 rdpr %ver, %tmp1; \
47 sethi %hi(__JALAPENO_ID), %tmp2; \
48 srlx %tmp1, 32, %tmp1; \
49 or %tmp2, %lo(__JALAPENO_ID), %tmp2;\
50 cmp %tmp1, %tmp2; \
51 be,pn %icc, label; \
52 nop;
53
54#define BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(tmp1,tmp2,label) \
55 rdpr %ver, %tmp1; \
56 srlx %tmp1, (32 + 16), %tmp2; \
57 cmp %tmp2, CHEETAH_MANUF; \
58 bne,pt %xcc, 99f; \
59 sllx %tmp1, 16, %tmp1; \
60 srlx %tmp1, (32 + 16), %tmp2; \
61 cmp %tmp2, CHEETAH_PLUS_IMPL; \
62 bgeu,pt %xcc, label; \
6399: nop;
64
65#define BRANCH_IF_ANY_CHEETAH(tmp1,tmp2,label) \
66 rdpr %ver, %tmp1; \
67 srlx %tmp1, (32 + 16), %tmp2; \
68 cmp %tmp2, CHEETAH_MANUF; \
69 bne,pt %xcc, 99f; \
70 sllx %tmp1, 16, %tmp1; \
71 srlx %tmp1, (32 + 16), %tmp2; \
72 cmp %tmp2, CHEETAH_IMPL; \
73 bgeu,pt %xcc, label; \
7499: nop;
75
76#endif /* !(_SPARC64_HEAD_H) */
diff --git a/include/asm-sparc/highmem.h b/include/asm-sparc/highmem.h
deleted file mode 100644
index 3de42e77627..00000000000
--- a/include/asm-sparc/highmem.h
+++ /dev/null
@@ -1,81 +0,0 @@
1/*
2 * highmem.h: virtual kernel memory mappings for high memory
3 *
4 * Used in CONFIG_HIGHMEM systems for memory pages which
5 * are not addressable by direct kernel virtual addresses.
6 *
7 * Copyright (C) 1999 Gerhard Wichert, Siemens AG
8 * Gerhard.Wichert@pdb.siemens.de
9 *
10 *
11 * Redesigned the x86 32-bit VM architecture to deal with
12 * up to 16 Terrabyte physical memory. With current x86 CPUs
13 * we now support up to 64 Gigabytes physical RAM.
14 *
15 * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
16 */
17
18#ifndef _ASM_HIGHMEM_H
19#define _ASM_HIGHMEM_H
20
21#ifdef __KERNEL__
22
23#include <linux/interrupt.h>
24#include <asm/fixmap.h>
25#include <asm/vaddrs.h>
26#include <asm/kmap_types.h>
27#include <asm/pgtable.h>
28
29/* declarations for highmem.c */
30extern unsigned long highstart_pfn, highend_pfn;
31
32extern pte_t *kmap_pte;
33extern pgprot_t kmap_prot;
34extern pte_t *pkmap_page_table;
35
36extern void kmap_init(void) __init;
37
38/*
39 * Right now we initialize only a single pte table. It can be extended
40 * easily, subsequent pte tables have to be allocated in one physical
41 * chunk of RAM. Currently the simplest way to do this is to align the
42 * pkmap region on a pagetable boundary (4MB).
43 */
44#define LAST_PKMAP 1024
45#define PKMAP_SIZE (LAST_PKMAP << PAGE_SHIFT)
46#define PKMAP_BASE PMD_ALIGN(SRMMU_NOCACHE_VADDR + (SRMMU_MAX_NOCACHE_PAGES << PAGE_SHIFT))
47
48#define LAST_PKMAP_MASK (LAST_PKMAP - 1)
49#define PKMAP_NR(virt) ((virt - PKMAP_BASE) >> PAGE_SHIFT)
50#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
51
52#define PKMAP_END (PKMAP_ADDR(LAST_PKMAP))
53
54extern void *kmap_high(struct page *page);
55extern void kunmap_high(struct page *page);
56
57static inline void *kmap(struct page *page)
58{
59 BUG_ON(in_interrupt());
60 if (!PageHighMem(page))
61 return page_address(page);
62 return kmap_high(page);
63}
64
65static inline void kunmap(struct page *page)
66{
67 BUG_ON(in_interrupt());
68 if (!PageHighMem(page))
69 return;
70 kunmap_high(page);
71}
72
73extern void *kmap_atomic(struct page *page, enum km_type type);
74extern void kunmap_atomic(void *kvaddr, enum km_type type);
75extern struct page *kmap_atomic_to_page(void *vaddr);
76
77#define flush_cache_kmaps() flush_cache_all()
78
79#endif /* __KERNEL__ */
80
81#endif /* _ASM_HIGHMEM_H */
diff --git a/include/asm-sparc/hugetlb.h b/include/asm-sparc/hugetlb.h
deleted file mode 100644
index 177061064ee..00000000000
--- a/include/asm-sparc/hugetlb.h
+++ /dev/null
@@ -1,85 +0,0 @@
1#ifndef _ASM_SPARC64_HUGETLB_H
2#define _ASM_SPARC64_HUGETLB_H
3
4#include <asm/page.h>
5
6
7void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
8 pte_t *ptep, pte_t pte);
9
10pte_t huge_ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
11 pte_t *ptep);
12
13void hugetlb_prefault_arch_hook(struct mm_struct *mm);
14
15static inline int is_hugepage_only_range(struct mm_struct *mm,
16 unsigned long addr,
17 unsigned long len) {
18 return 0;
19}
20
21/*
22 * If the arch doesn't supply something else, assume that hugepage
23 * size aligned regions are ok without further preparation.
24 */
25static inline int prepare_hugepage_range(struct file *file,
26 unsigned long addr, unsigned long len)
27{
28 if (len & ~HPAGE_MASK)
29 return -EINVAL;
30 if (addr & ~HPAGE_MASK)
31 return -EINVAL;
32 return 0;
33}
34
35static inline void hugetlb_free_pgd_range(struct mmu_gather *tlb,
36 unsigned long addr, unsigned long end,
37 unsigned long floor,
38 unsigned long ceiling)
39{
40 free_pgd_range(tlb, addr, end, floor, ceiling);
41}
42
43static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
44 unsigned long addr, pte_t *ptep)
45{
46}
47
48static inline int huge_pte_none(pte_t pte)
49{
50 return pte_none(pte);
51}
52
53static inline pte_t huge_pte_wrprotect(pte_t pte)
54{
55 return pte_wrprotect(pte);
56}
57
58static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
59 unsigned long addr, pte_t *ptep)
60{
61 ptep_set_wrprotect(mm, addr, ptep);
62}
63
64static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
65 unsigned long addr, pte_t *ptep,
66 pte_t pte, int dirty)
67{
68 return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
69}
70
71static inline pte_t huge_ptep_get(pte_t *ptep)
72{
73 return *ptep;
74}
75
76static inline int arch_prepare_hugepage(struct page *page)
77{
78 return 0;
79}
80
81static inline void arch_release_hugepage(struct page *page)
82{
83}
84
85#endif /* _ASM_SPARC64_HUGETLB_H */
diff --git a/include/asm-sparc/hvtramp.h b/include/asm-sparc/hvtramp.h
deleted file mode 100644
index b2b9b947b3a..00000000000
--- a/include/asm-sparc/hvtramp.h
+++ /dev/null
@@ -1,37 +0,0 @@
1#ifndef _SPARC64_HVTRAP_H
2#define _SPARC64_HVTRAP_H
3
4#ifndef __ASSEMBLY__
5
6#include <linux/types.h>
7
8struct hvtramp_mapping {
9 __u64 vaddr;
10 __u64 tte;
11};
12
13struct hvtramp_descr {
14 __u32 cpu;
15 __u32 num_mappings;
16 __u64 fault_info_va;
17 __u64 fault_info_pa;
18 __u64 thread_reg;
19 struct hvtramp_mapping maps[1];
20};
21
22extern void hv_cpu_startup(unsigned long hvdescr_pa);
23
24#endif
25
26#define HVTRAMP_DESCR_CPU 0x00
27#define HVTRAMP_DESCR_NUM_MAPPINGS 0x04
28#define HVTRAMP_DESCR_FAULT_INFO_VA 0x08
29#define HVTRAMP_DESCR_FAULT_INFO_PA 0x10
30#define HVTRAMP_DESCR_THREAD_REG 0x18
31#define HVTRAMP_DESCR_MAPS 0x20
32
33#define HVTRAMP_MAPPING_VADDR 0x00
34#define HVTRAMP_MAPPING_TTE 0x08
35#define HVTRAMP_MAPPING_SIZE 0x10
36
37#endif /* _SPARC64_HVTRAP_H */
diff --git a/include/asm-sparc/hw_irq.h b/include/asm-sparc/hw_irq.h
deleted file mode 100644
index 8d30a7694be..00000000000
--- a/include/asm-sparc/hw_irq.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef __ASM_SPARC_HW_IRQ_H
2#define __ASM_SPARC_HW_IRQ_H
3
4/* Dummy include. */
5
6#endif
diff --git a/include/asm-sparc/hypervisor.h b/include/asm-sparc/hypervisor.h
deleted file mode 100644
index 109ae24ba24..00000000000
--- a/include/asm-sparc/hypervisor.h
+++ /dev/null
@@ -1,2949 +0,0 @@
1#ifndef _SPARC64_HYPERVISOR_H
2#define _SPARC64_HYPERVISOR_H
3
4/* Sun4v hypervisor interfaces and defines.
5 *
6 * Hypervisor calls are made via traps to software traps number 0x80
7 * and above. Registers %o0 to %o5 serve as argument, status, and
8 * return value registers.
9 *
10 * There are two kinds of these traps. First there are the normal
11 * "fast traps" which use software trap 0x80 and encode the function
12 * to invoke by number in register %o5. Argument and return value
13 * handling is as follows:
14 *
15 * -----------------------------------------------
16 * | %o5 | function number | undefined |
17 * | %o0 | argument 0 | return status |
18 * | %o1 | argument 1 | return value 1 |
19 * | %o2 | argument 2 | return value 2 |
20 * | %o3 | argument 3 | return value 3 |
21 * | %o4 | argument 4 | return value 4 |
22 * -----------------------------------------------
23 *
24 * The second type are "hyper-fast traps" which encode the function
25 * number in the software trap number itself. So these use trap
26 * numbers > 0x80. The register usage for hyper-fast traps is as
27 * follows:
28 *
29 * -----------------------------------------------
30 * | %o0 | argument 0 | return status |
31 * | %o1 | argument 1 | return value 1 |
32 * | %o2 | argument 2 | return value 2 |
33 * | %o3 | argument 3 | return value 3 |
34 * | %o4 | argument 4 | return value 4 |
35 * -----------------------------------------------
36 *
37 * Registers providing explicit arguments to the hypervisor calls
38 * are volatile across the call. Upon return their values are
39 * undefined unless explicitly specified as containing a particular
40 * return value by the specific call. The return status is always
41 * returned in register %o0, zero indicates a successful execution of
42 * the hypervisor call and other values indicate an error status as
43 * defined below. So, for example, if a hyper-fast trap takes
44 * arguments 0, 1, and 2, then %o0, %o1, and %o2 are volatile across
45 * the call and %o3, %o4, and %o5 would be preserved.
46 *
47 * If the hypervisor trap is invalid, or the fast trap function number
48 * is invalid, HV_EBADTRAP will be returned in %o0. Also, all 64-bits
49 * of the argument and return values are significant.
50 */
51
52/* Trap numbers. */
53#define HV_FAST_TRAP 0x80
54#define HV_MMU_MAP_ADDR_TRAP 0x83
55#define HV_MMU_UNMAP_ADDR_TRAP 0x84
56#define HV_TTRACE_ADDENTRY_TRAP 0x85
57#define HV_CORE_TRAP 0xff
58
59/* Error codes. */
60#define HV_EOK 0 /* Successful return */
61#define HV_ENOCPU 1 /* Invalid CPU id */
62#define HV_ENORADDR 2 /* Invalid real address */
63#define HV_ENOINTR 3 /* Invalid interrupt id */
64#define HV_EBADPGSZ 4 /* Invalid pagesize encoding */
65#define HV_EBADTSB 5 /* Invalid TSB description */
66#define HV_EINVAL 6 /* Invalid argument */
67#define HV_EBADTRAP 7 /* Invalid function number */
68#define HV_EBADALIGN 8 /* Invalid address alignment */
69#define HV_EWOULDBLOCK 9 /* Cannot complete w/o blocking */
70#define HV_ENOACCESS 10 /* No access to resource */
71#define HV_EIO 11 /* I/O error */
72#define HV_ECPUERROR 12 /* CPU in error state */
73#define HV_ENOTSUPPORTED 13 /* Function not supported */
74#define HV_ENOMAP 14 /* No mapping found */
75#define HV_ETOOMANY 15 /* Too many items specified */
76#define HV_ECHANNEL 16 /* Invalid LDC channel */
77#define HV_EBUSY 17 /* Resource busy */
78
79/* mach_exit()
80 * TRAP: HV_FAST_TRAP
81 * FUNCTION: HV_FAST_MACH_EXIT
82 * ARG0: exit code
83 * ERRORS: This service does not return.
84 *
85 * Stop all CPUs in the virtual domain and place them into the stopped
86 * state. The 64-bit exit code may be passed to a service entity as
87 * the domain's exit status. On systems without a service entity, the
88 * domain will undergo a reset, and the boot firmware will be
89 * reloaded.
90 *
91 * This function will never return to the guest that invokes it.
92 *
93 * Note: By convention an exit code of zero denotes a successful exit by
94 * the guest code. A non-zero exit code denotes a guest specific
95 * error indication.
96 *
97 */
98#define HV_FAST_MACH_EXIT 0x00
99
100#ifndef __ASSEMBLY__
101extern void sun4v_mach_exit(unsigned long exit_code);
102#endif
103
104/* Domain services. */
105
106/* mach_desc()
107 * TRAP: HV_FAST_TRAP
108 * FUNCTION: HV_FAST_MACH_DESC
109 * ARG0: buffer
110 * ARG1: length
111 * RET0: status
112 * RET1: length
113 * ERRORS: HV_EBADALIGN Buffer is badly aligned
114 * HV_ENORADDR Buffer is to an illegal real address.
115 * HV_EINVAL Buffer length is too small for complete
116 * machine description.
117 *
118 * Copy the most current machine description into the buffer indicated
119 * by the real address in ARG0. The buffer provided must be 16 byte
120 * aligned. Upon success or HV_EINVAL, this service returns the
121 * actual size of the machine description in the RET1 return value.
122 *
123 * Note: A method of determining the appropriate buffer size for the
124 * machine description is to first call this service with a buffer
125 * length of 0 bytes.
126 */
127#define HV_FAST_MACH_DESC 0x01
128
129#ifndef __ASSEMBLY__
130extern unsigned long sun4v_mach_desc(unsigned long buffer_pa,
131 unsigned long buf_len,
132 unsigned long *real_buf_len);
133#endif
134
135/* mach_sir()
136 * TRAP: HV_FAST_TRAP
137 * FUNCTION: HV_FAST_MACH_SIR
138 * ERRORS: This service does not return.
139 *
140 * Perform a software initiated reset of the virtual machine domain.
141 * All CPUs are captured as soon as possible, all hardware devices are
142 * returned to the entry default state, and the domain is restarted at
143 * the SIR (trap type 0x04) real trap table (RTBA) entry point on one
144 * of the CPUs. The single CPU restarted is selected as determined by
145 * platform specific policy. Memory is preserved across this
146 * operation.
147 */
148#define HV_FAST_MACH_SIR 0x02
149
150#ifndef __ASSEMBLY__
151extern void sun4v_mach_sir(void);
152#endif
153
154/* mach_set_watchdog()
155 * TRAP: HV_FAST_TRAP
156 * FUNCTION: HV_FAST_MACH_SET_WATCHDOG
157 * ARG0: timeout in milliseconds
158 * RET0: status
159 * RET1: time remaining in milliseconds
160 *
161 * A guest uses this API to set a watchdog timer. Once the gues has set
162 * the timer, it must call the timer service again either to disable or
163 * postpone the expiration. If the timer expires before being reset or
164 * disabled, then the hypervisor take a platform specific action leading
165 * to guest termination within a bounded time period. The platform action
166 * may include recovery actions such as reporting the expiration to a
167 * Service Processor, and/or automatically restarting the gues.
168 *
169 * The 'timeout' parameter is specified in milliseconds, however the
170 * implementated granularity is given by the 'watchdog-resolution'
171 * property in the 'platform' node of the guest's machine description.
172 * The largest allowed timeout value is specified by the
173 * 'watchdog-max-timeout' property of the 'platform' node.
174 *
175 * If the 'timeout' argument is not zero, the watchdog timer is set to
176 * expire after a minimum of 'timeout' milliseconds.
177 *
178 * If the 'timeout' argument is zero, the watchdog timer is disabled.
179 *
180 * If the 'timeout' value exceeds the value of the 'max-watchdog-timeout'
181 * property, the hypervisor leaves the watchdog timer state unchanged,
182 * and returns a status of EINVAL.
183 *
184 * The 'time remaining' return value is valid regardless of whether the
185 * return status is EOK or EINVAL. A non-zero return value indicates the
186 * number of milliseconds that were remaining until the timer was to expire.
187 * If less than one millisecond remains, the return value is '1'. If the
188 * watchdog timer was disabled at the time of the call, the return value is
189 * zero.
190 *
191 * If the hypervisor cannot support the exact timeout value requested, but
192 * can support a larger timeout value, the hypervisor may round the actual
193 * timeout to a value larger than the requested timeout, consequently the
194 * 'time remaining' return value may be larger than the previously requested
195 * timeout value.
196 *
197 * Any guest OS debugger should be aware that the watchdog service may be in
198 * use. Consequently, it is recommended that the watchdog service is
199 * disabled upon debugger entry (e.g. reaching a breakpoint), and then
200 * re-enabled upon returning to normal execution. The API has been designed
201 * with this in mind, and the 'time remaining' result of the disable call may
202 * be used directly as the timeout argument of the re-enable call.
203 */
204#define HV_FAST_MACH_SET_WATCHDOG 0x05
205
206#ifndef __ASSEMBLY__
207extern unsigned long sun4v_mach_set_watchdog(unsigned long timeout,
208 unsigned long *orig_timeout);
209#endif
210
211/* CPU services.
212 *
213 * CPUs represent devices that can execute software threads. A single
214 * chip that contains multiple cores or strands is represented as
215 * multiple CPUs with unique CPU identifiers. CPUs are exported to
216 * OBP via the machine description (and to the OS via the OBP device
217 * tree). CPUs are always in one of three states: stopped, running,
218 * or error.
219 *
220 * A CPU ID is a pre-assigned 16-bit value that uniquely identifies a
221 * CPU within a logical domain. Operations that are to be performed
222 * on multiple CPUs specify them via a CPU list. A CPU list is an
223 * array in real memory, of which each 16-bit word is a CPU ID. CPU
224 * lists are passed through the API as two arguments. The first is
225 * the number of entries (16-bit words) in the CPU list, and the
226 * second is the (real address) pointer to the CPU ID list.
227 */
228
229/* cpu_start()
230 * TRAP: HV_FAST_TRAP
231 * FUNCTION: HV_FAST_CPU_START
232 * ARG0: CPU ID
233 * ARG1: PC
234 * ARG2: RTBA
235 * ARG3: target ARG0
236 * RET0: status
237 * ERRORS: ENOCPU Invalid CPU ID
238 * EINVAL Target CPU ID is not in the stopped state
239 * ENORADDR Invalid PC or RTBA real address
240 * EBADALIGN Unaligned PC or unaligned RTBA
241 * EWOULDBLOCK Starting resources are not available
242 *
243 * Start CPU with given CPU ID with PC in %pc and with a real trap
244 * base address value of RTBA. The indicated CPU must be in the
245 * stopped state. The supplied RTBA must be aligned on a 256 byte
246 * boundary. On successful completion, the specified CPU will be in
247 * the running state and will be supplied with "target ARG0" in %o0
248 * and RTBA in %tba.
249 */
250#define HV_FAST_CPU_START 0x10
251
252#ifndef __ASSEMBLY__
253extern unsigned long sun4v_cpu_start(unsigned long cpuid,
254 unsigned long pc,
255 unsigned long rtba,
256 unsigned long arg0);
257#endif
258
259/* cpu_stop()
260 * TRAP: HV_FAST_TRAP
261 * FUNCTION: HV_FAST_CPU_STOP
262 * ARG0: CPU ID
263 * RET0: status
264 * ERRORS: ENOCPU Invalid CPU ID
265 * EINVAL Target CPU ID is the current cpu
266 * EINVAL Target CPU ID is not in the running state
267 * EWOULDBLOCK Stopping resources are not available
268 * ENOTSUPPORTED Not supported on this platform
269 *
270 * The specified CPU is stopped. The indicated CPU must be in the
271 * running state. On completion, it will be in the stopped state. It
272 * is not legal to stop the current CPU.
273 *
274 * Note: As this service cannot be used to stop the current cpu, this service
275 * may not be used to stop the last running CPU in a domain. To stop
276 * and exit a running domain, a guest must use the mach_exit() service.
277 */
278#define HV_FAST_CPU_STOP 0x11
279
280#ifndef __ASSEMBLY__
281extern unsigned long sun4v_cpu_stop(unsigned long cpuid);
282#endif
283
284/* cpu_yield()
285 * TRAP: HV_FAST_TRAP
286 * FUNCTION: HV_FAST_CPU_YIELD
287 * RET0: status
288 * ERRORS: No possible error.
289 *
290 * Suspend execution on the current CPU. Execution will resume when
291 * an interrupt (device, %stick_compare, or cross-call) is targeted to
292 * the CPU. On some CPUs, this API may be used by the hypervisor to
293 * save power by disabling hardware strands.
294 */
295#define HV_FAST_CPU_YIELD 0x12
296
297#ifndef __ASSEMBLY__
298extern unsigned long sun4v_cpu_yield(void);
299#endif
300
301/* cpu_qconf()
302 * TRAP: HV_FAST_TRAP
303 * FUNCTION: HV_FAST_CPU_QCONF
304 * ARG0: queue
305 * ARG1: base real address
306 * ARG2: number of entries
307 * RET0: status
308 * ERRORS: ENORADDR Invalid base real address
309 * EINVAL Invalid queue or number of entries is less
310 * than 2 or too large.
311 * EBADALIGN Base real address is not correctly aligned
312 * for size.
313 *
314 * Configure the given queue to be placed at the given base real
315 * address, with the given number of entries. The number of entries
316 * must be a power of 2. The base real address must be aligned
317 * exactly to match the queue size. Each queue entry is 64 bytes
318 * long, so for example a 32 entry queue must be aligned on a 2048
319 * byte real address boundary.
320 *
321 * The specified queue is unconfigured if the number of entries is given
322 * as zero.
323 *
324 * For the current version of this API service, the argument queue is defined
325 * as follows:
326 *
327 * queue description
328 * ----- -------------------------
329 * 0x3c cpu mondo queue
330 * 0x3d device mondo queue
331 * 0x3e resumable error queue
332 * 0x3f non-resumable error queue
333 *
334 * Note: The maximum number of entries for each queue for a specific cpu may
335 * be determined from the machine description.
336 */
337#define HV_FAST_CPU_QCONF 0x14
338#define HV_CPU_QUEUE_CPU_MONDO 0x3c
339#define HV_CPU_QUEUE_DEVICE_MONDO 0x3d
340#define HV_CPU_QUEUE_RES_ERROR 0x3e
341#define HV_CPU_QUEUE_NONRES_ERROR 0x3f
342
343#ifndef __ASSEMBLY__
344extern unsigned long sun4v_cpu_qconf(unsigned long type,
345 unsigned long queue_paddr,
346 unsigned long num_queue_entries);
347#endif
348
349/* cpu_qinfo()
350 * TRAP: HV_FAST_TRAP
351 * FUNCTION: HV_FAST_CPU_QINFO
352 * ARG0: queue
353 * RET0: status
354 * RET1: base real address
355 * RET1: number of entries
356 * ERRORS: EINVAL Invalid queue
357 *
358 * Return the configuration info for the given queue. The base real
359 * address and number of entries of the defined queue are returned.
360 * The queue argument values are the same as for cpu_qconf() above.
361 *
362 * If the specified queue is a valid queue number, but no queue has
363 * been defined, the number of entries will be set to zero and the
364 * base real address returned is undefined.
365 */
366#define HV_FAST_CPU_QINFO 0x15
367
368/* cpu_mondo_send()
369 * TRAP: HV_FAST_TRAP
370 * FUNCTION: HV_FAST_CPU_MONDO_SEND
371 * ARG0-1: CPU list
372 * ARG2: data real address
373 * RET0: status
374 * ERRORS: EBADALIGN Mondo data is not 64-byte aligned or CPU list
375 * is not 2-byte aligned.
376 * ENORADDR Invalid data mondo address, or invalid cpu list
377 * address.
378 * ENOCPU Invalid cpu in CPU list
379 * EWOULDBLOCK Some or all of the listed CPUs did not receive
380 * the mondo
381 * ECPUERROR One or more of the listed CPUs are in error
382 * state, use HV_FAST_CPU_STATE to see which ones
383 * EINVAL CPU list includes caller's CPU ID
384 *
385 * Send a mondo interrupt to the CPUs in the given CPU list with the
386 * 64-bytes at the given data real address. The data must be 64-byte
387 * aligned. The mondo data will be delivered to the cpu_mondo queues
388 * of the recipient CPUs.
389 *
390 * In all cases, error or not, the CPUs in the CPU list to which the
391 * mondo has been successfully delivered will be indicated by having
392 * their entry in CPU list updated with the value 0xffff.
393 */
394#define HV_FAST_CPU_MONDO_SEND 0x42
395
396#ifndef __ASSEMBLY__
397extern unsigned long sun4v_cpu_mondo_send(unsigned long cpu_count, unsigned long cpu_list_pa, unsigned long mondo_block_pa);
398#endif
399
400/* cpu_myid()
401 * TRAP: HV_FAST_TRAP
402 * FUNCTION: HV_FAST_CPU_MYID
403 * RET0: status
404 * RET1: CPU ID
405 * ERRORS: No errors defined.
406 *
407 * Return the hypervisor ID handle for the current CPU. Use by a
408 * virtual CPU to discover it's own identity.
409 */
410#define HV_FAST_CPU_MYID 0x16
411
412/* cpu_state()
413 * TRAP: HV_FAST_TRAP
414 * FUNCTION: HV_FAST_CPU_STATE
415 * ARG0: CPU ID
416 * RET0: status
417 * RET1: state
418 * ERRORS: ENOCPU Invalid CPU ID
419 *
420 * Retrieve the current state of the CPU with the given CPU ID.
421 */
422#define HV_FAST_CPU_STATE 0x17
423#define HV_CPU_STATE_STOPPED 0x01
424#define HV_CPU_STATE_RUNNING 0x02
425#define HV_CPU_STATE_ERROR 0x03
426
427#ifndef __ASSEMBLY__
428extern long sun4v_cpu_state(unsigned long cpuid);
429#endif
430
431/* cpu_set_rtba()
432 * TRAP: HV_FAST_TRAP
433 * FUNCTION: HV_FAST_CPU_SET_RTBA
434 * ARG0: RTBA
435 * RET0: status
436 * RET1: previous RTBA
437 * ERRORS: ENORADDR Invalid RTBA real address
438 * EBADALIGN RTBA is incorrectly aligned for a trap table
439 *
440 * Set the real trap base address of the local cpu to the given RTBA.
441 * The supplied RTBA must be aligned on a 256 byte boundary. Upon
442 * success the previous value of the RTBA is returned in RET1.
443 *
444 * Note: This service does not affect %tba
445 */
446#define HV_FAST_CPU_SET_RTBA 0x18
447
448/* cpu_set_rtba()
449 * TRAP: HV_FAST_TRAP
450 * FUNCTION: HV_FAST_CPU_GET_RTBA
451 * RET0: status
452 * RET1: previous RTBA
453 * ERRORS: No possible error.
454 *
455 * Returns the current value of RTBA in RET1.
456 */
457#define HV_FAST_CPU_GET_RTBA 0x19
458
459/* MMU services.
460 *
461 * Layout of a TSB description for mmu_tsb_ctx{,non}0() calls.
462 */
463#ifndef __ASSEMBLY__
464struct hv_tsb_descr {
465 unsigned short pgsz_idx;
466 unsigned short assoc;
467 unsigned int num_ttes; /* in TTEs */
468 unsigned int ctx_idx;
469 unsigned int pgsz_mask;
470 unsigned long tsb_base;
471 unsigned long resv;
472};
473#endif
474#define HV_TSB_DESCR_PGSZ_IDX_OFFSET 0x00
475#define HV_TSB_DESCR_ASSOC_OFFSET 0x02
476#define HV_TSB_DESCR_NUM_TTES_OFFSET 0x04
477#define HV_TSB_DESCR_CTX_IDX_OFFSET 0x08
478#define HV_TSB_DESCR_PGSZ_MASK_OFFSET 0x0c
479#define HV_TSB_DESCR_TSB_BASE_OFFSET 0x10
480#define HV_TSB_DESCR_RESV_OFFSET 0x18
481
482/* Page size bitmask. */
483#define HV_PGSZ_MASK_8K (1 << 0)
484#define HV_PGSZ_MASK_64K (1 << 1)
485#define HV_PGSZ_MASK_512K (1 << 2)
486#define HV_PGSZ_MASK_4MB (1 << 3)
487#define HV_PGSZ_MASK_32MB (1 << 4)
488#define HV_PGSZ_MASK_256MB (1 << 5)
489#define HV_PGSZ_MASK_2GB (1 << 6)
490#define HV_PGSZ_MASK_16GB (1 << 7)
491
492/* Page size index. The value given in the TSB descriptor must correspond
493 * to the smallest page size specified in the pgsz_mask page size bitmask.
494 */
495#define HV_PGSZ_IDX_8K 0
496#define HV_PGSZ_IDX_64K 1
497#define HV_PGSZ_IDX_512K 2
498#define HV_PGSZ_IDX_4MB 3
499#define HV_PGSZ_IDX_32MB 4
500#define HV_PGSZ_IDX_256MB 5
501#define HV_PGSZ_IDX_2GB 6
502#define HV_PGSZ_IDX_16GB 7
503
504/* MMU fault status area.
505 *
506 * MMU related faults have their status and fault address information
507 * placed into a memory region made available by privileged code. Each
508 * virtual processor must make a mmu_fault_area_conf() call to tell the
509 * hypervisor where that processor's fault status should be stored.
510 *
511 * The fault status block is a multiple of 64-bytes and must be aligned
512 * on a 64-byte boundary.
513 */
514#ifndef __ASSEMBLY__
515struct hv_fault_status {
516 unsigned long i_fault_type;
517 unsigned long i_fault_addr;
518 unsigned long i_fault_ctx;
519 unsigned long i_reserved[5];
520 unsigned long d_fault_type;
521 unsigned long d_fault_addr;
522 unsigned long d_fault_ctx;
523 unsigned long d_reserved[5];
524};
525#endif
526#define HV_FAULT_I_TYPE_OFFSET 0x00
527#define HV_FAULT_I_ADDR_OFFSET 0x08
528#define HV_FAULT_I_CTX_OFFSET 0x10
529#define HV_FAULT_D_TYPE_OFFSET 0x40
530#define HV_FAULT_D_ADDR_OFFSET 0x48
531#define HV_FAULT_D_CTX_OFFSET 0x50
532
533#define HV_FAULT_TYPE_FAST_MISS 1
534#define HV_FAULT_TYPE_FAST_PROT 2
535#define HV_FAULT_TYPE_MMU_MISS 3
536#define HV_FAULT_TYPE_INV_RA 4
537#define HV_FAULT_TYPE_PRIV_VIOL 5
538#define HV_FAULT_TYPE_PROT_VIOL 6
539#define HV_FAULT_TYPE_NFO 7
540#define HV_FAULT_TYPE_NFO_SEFF 8
541#define HV_FAULT_TYPE_INV_VA 9
542#define HV_FAULT_TYPE_INV_ASI 10
543#define HV_FAULT_TYPE_NC_ATOMIC 11
544#define HV_FAULT_TYPE_PRIV_ACT 12
545#define HV_FAULT_TYPE_RESV1 13
546#define HV_FAULT_TYPE_UNALIGNED 14
547#define HV_FAULT_TYPE_INV_PGSZ 15
548/* Values 16 --> -2 are reserved. */
549#define HV_FAULT_TYPE_MULTIPLE -1
550
551/* Flags argument for mmu_{map,unmap}_addr(), mmu_demap_{page,context,all}(),
552 * and mmu_{map,unmap}_perm_addr().
553 */
554#define HV_MMU_DMMU 0x01
555#define HV_MMU_IMMU 0x02
556#define HV_MMU_ALL (HV_MMU_DMMU | HV_MMU_IMMU)
557
558/* mmu_map_addr()
559 * TRAP: HV_MMU_MAP_ADDR_TRAP
560 * ARG0: virtual address
561 * ARG1: mmu context
562 * ARG2: TTE
563 * ARG3: flags (HV_MMU_{IMMU,DMMU})
564 * ERRORS: EINVAL Invalid virtual address, mmu context, or flags
565 * EBADPGSZ Invalid page size value
566 * ENORADDR Invalid real address in TTE
567 *
568 * Create a non-permanent mapping using the given TTE, virtual
569 * address, and mmu context. The flags argument determines which
570 * (data, or instruction, or both) TLB the mapping gets loaded into.
571 *
572 * The behavior is undefined if the valid bit is clear in the TTE.
573 *
574 * Note: This API call is for privileged code to specify temporary translation
575 * mappings without the need to create and manage a TSB.
576 */
577
578/* mmu_unmap_addr()
579 * TRAP: HV_MMU_UNMAP_ADDR_TRAP
580 * ARG0: virtual address
581 * ARG1: mmu context
582 * ARG2: flags (HV_MMU_{IMMU,DMMU})
583 * ERRORS: EINVAL Invalid virtual address, mmu context, or flags
584 *
585 * Demaps the given virtual address in the given mmu context on this
586 * CPU. This function is intended to be used to demap pages mapped
587 * with mmu_map_addr. This service is equivalent to invoking
588 * mmu_demap_page() with only the current CPU in the CPU list. The
589 * flags argument determines which (data, or instruction, or both) TLB
590 * the mapping gets unmapped from.
591 *
592 * Attempting to perform an unmap operation for a previously defined
593 * permanent mapping will have undefined results.
594 */
595
596/* mmu_tsb_ctx0()
597 * TRAP: HV_FAST_TRAP
598 * FUNCTION: HV_FAST_MMU_TSB_CTX0
599 * ARG0: number of TSB descriptions
600 * ARG1: TSB descriptions pointer
601 * RET0: status
602 * ERRORS: ENORADDR Invalid TSB descriptions pointer or
603 * TSB base within a descriptor
604 * EBADALIGN TSB descriptions pointer is not aligned
605 * to an 8-byte boundary, or TSB base
606 * within a descriptor is not aligned for
607 * the given TSB size
608 * EBADPGSZ Invalid page size in a TSB descriptor
609 * EBADTSB Invalid associativity or size in a TSB
610 * descriptor
611 * EINVAL Invalid number of TSB descriptions, or
612 * invalid context index in a TSB
613 * descriptor, or index page size not
614 * equal to smallest page size in page
615 * size bitmask field.
616 *
617 * Configures the TSBs for the current CPU for virtual addresses with
618 * context zero. The TSB descriptions pointer is a pointer to an
619 * array of the given number of TSB descriptions.
620 *
621 * Note: The maximum number of TSBs available to a virtual CPU is given by the
622 * mmu-max-#tsbs property of the cpu's corresponding "cpu" node in the
623 * machine description.
624 */
625#define HV_FAST_MMU_TSB_CTX0 0x20
626
627#ifndef __ASSEMBLY__
628extern unsigned long sun4v_mmu_tsb_ctx0(unsigned long num_descriptions,
629 unsigned long tsb_desc_ra);
630#endif
631
632/* mmu_tsb_ctxnon0()
633 * TRAP: HV_FAST_TRAP
634 * FUNCTION: HV_FAST_MMU_TSB_CTXNON0
635 * ARG0: number of TSB descriptions
636 * ARG1: TSB descriptions pointer
637 * RET0: status
638 * ERRORS: Same as for mmu_tsb_ctx0() above.
639 *
640 * Configures the TSBs for the current CPU for virtual addresses with
641 * non-zero contexts. The TSB descriptions pointer is a pointer to an
642 * array of the given number of TSB descriptions.
643 *
644 * Note: A maximum of 16 TSBs may be specified in the TSB description list.
645 */
646#define HV_FAST_MMU_TSB_CTXNON0 0x21
647
648/* mmu_demap_page()
649 * TRAP: HV_FAST_TRAP
650 * FUNCTION: HV_FAST_MMU_DEMAP_PAGE
651 * ARG0: reserved, must be zero
652 * ARG1: reserved, must be zero
653 * ARG2: virtual address
654 * ARG3: mmu context
655 * ARG4: flags (HV_MMU_{IMMU,DMMU})
656 * RET0: status
657 * ERRORS: EINVAL Invalid virutal address, context, or
658 * flags value
659 * ENOTSUPPORTED ARG0 or ARG1 is non-zero
660 *
661 * Demaps any page mapping of the given virtual address in the given
662 * mmu context for the current virtual CPU. Any virtually tagged
663 * caches are guaranteed to be kept consistent. The flags argument
664 * determines which TLB (instruction, or data, or both) participate in
665 * the operation.
666 *
667 * ARG0 and ARG1 are both reserved and must be set to zero.
668 */
669#define HV_FAST_MMU_DEMAP_PAGE 0x22
670
671/* mmu_demap_ctx()
672 * TRAP: HV_FAST_TRAP
673 * FUNCTION: HV_FAST_MMU_DEMAP_CTX
674 * ARG0: reserved, must be zero
675 * ARG1: reserved, must be zero
676 * ARG2: mmu context
677 * ARG3: flags (HV_MMU_{IMMU,DMMU})
678 * RET0: status
679 * ERRORS: EINVAL Invalid context or flags value
680 * ENOTSUPPORTED ARG0 or ARG1 is non-zero
681 *
682 * Demaps all non-permanent virtual page mappings previously specified
683 * for the given context for the current virtual CPU. Any virtual
684 * tagged caches are guaranteed to be kept consistent. The flags
685 * argument determines which TLB (instruction, or data, or both)
686 * participate in the operation.
687 *
688 * ARG0 and ARG1 are both reserved and must be set to zero.
689 */
690#define HV_FAST_MMU_DEMAP_CTX 0x23
691
692/* mmu_demap_all()
693 * TRAP: HV_FAST_TRAP
694 * FUNCTION: HV_FAST_MMU_DEMAP_ALL
695 * ARG0: reserved, must be zero
696 * ARG1: reserved, must be zero
697 * ARG2: flags (HV_MMU_{IMMU,DMMU})
698 * RET0: status
699 * ERRORS: EINVAL Invalid flags value
700 * ENOTSUPPORTED ARG0 or ARG1 is non-zero
701 *
702 * Demaps all non-permanent virtual page mappings previously specified
703 * for the current virtual CPU. Any virtual tagged caches are
704 * guaranteed to be kept consistent. The flags argument determines
705 * which TLB (instruction, or data, or both) participate in the
706 * operation.
707 *
708 * ARG0 and ARG1 are both reserved and must be set to zero.
709 */
710#define HV_FAST_MMU_DEMAP_ALL 0x24
711
712#ifndef __ASSEMBLY__
713extern void sun4v_mmu_demap_all(void);
714#endif
715
716/* mmu_map_perm_addr()
717 * TRAP: HV_FAST_TRAP
718 * FUNCTION: HV_FAST_MMU_MAP_PERM_ADDR
719 * ARG0: virtual address
720 * ARG1: reserved, must be zero
721 * ARG2: TTE
722 * ARG3: flags (HV_MMU_{IMMU,DMMU})
723 * RET0: status
724 * ERRORS: EINVAL Invalid virutal address or flags value
725 * EBADPGSZ Invalid page size value
726 * ENORADDR Invalid real address in TTE
727 * ETOOMANY Too many mappings (max of 8 reached)
728 *
729 * Create a permanent mapping using the given TTE and virtual address
730 * for context 0 on the calling virtual CPU. A maximum of 8 such
731 * permanent mappings may be specified by privileged code. Mappings
732 * may be removed with mmu_unmap_perm_addr().
733 *
734 * The behavior is undefined if a TTE with the valid bit clear is given.
735 *
736 * Note: This call is used to specify address space mappings for which
737 * privileged code does not expect to receive misses. For example,
738 * this mechanism can be used to map kernel nucleus code and data.
739 */
740#define HV_FAST_MMU_MAP_PERM_ADDR 0x25
741
742#ifndef __ASSEMBLY__
743extern unsigned long sun4v_mmu_map_perm_addr(unsigned long vaddr,
744 unsigned long set_to_zero,
745 unsigned long tte,
746 unsigned long flags);
747#endif
748
749/* mmu_fault_area_conf()
750 * TRAP: HV_FAST_TRAP
751 * FUNCTION: HV_FAST_MMU_FAULT_AREA_CONF
752 * ARG0: real address
753 * RET0: status
754 * RET1: previous mmu fault area real address
755 * ERRORS: ENORADDR Invalid real address
756 * EBADALIGN Invalid alignment for fault area
757 *
758 * Configure the MMU fault status area for the calling CPU. A 64-byte
759 * aligned real address specifies where MMU fault status information
760 * is placed. The return value is the previously specified area, or 0
761 * for the first invocation. Specifying a fault area at real address
762 * 0 is not allowed.
763 */
764#define HV_FAST_MMU_FAULT_AREA_CONF 0x26
765
766/* mmu_enable()
767 * TRAP: HV_FAST_TRAP
768 * FUNCTION: HV_FAST_MMU_ENABLE
769 * ARG0: enable flag
770 * ARG1: return target address
771 * RET0: status
772 * ERRORS: ENORADDR Invalid real address when disabling
773 * translation.
774 * EBADALIGN The return target address is not
775 * aligned to an instruction.
776 * EINVAL The enable flag request the current
777 * operating mode (e.g. disable if already
778 * disabled)
779 *
780 * Enable or disable virtual address translation for the calling CPU
781 * within the virtual machine domain. If the enable flag is zero,
782 * translation is disabled, any non-zero value will enable
783 * translation.
784 *
785 * When this function returns, the newly selected translation mode
786 * will be active. If the mmu is being enabled, then the return
787 * target address is a virtual address else it is a real address.
788 *
789 * Upon successful completion, control will be returned to the given
790 * return target address (ie. the cpu will jump to that address). On
791 * failure, the previous mmu mode remains and the trap simply returns
792 * as normal with the appropriate error code in RET0.
793 */
794#define HV_FAST_MMU_ENABLE 0x27
795
796/* mmu_unmap_perm_addr()
797 * TRAP: HV_FAST_TRAP
798 * FUNCTION: HV_FAST_MMU_UNMAP_PERM_ADDR
799 * ARG0: virtual address
800 * ARG1: reserved, must be zero
801 * ARG2: flags (HV_MMU_{IMMU,DMMU})
802 * RET0: status
803 * ERRORS: EINVAL Invalid virutal address or flags value
804 * ENOMAP Specified mapping was not found
805 *
806 * Demaps any permanent page mapping (established via
807 * mmu_map_perm_addr()) at the given virtual address for context 0 on
808 * the current virtual CPU. Any virtual tagged caches are guaranteed
809 * to be kept consistent.
810 */
811#define HV_FAST_MMU_UNMAP_PERM_ADDR 0x28
812
813/* mmu_tsb_ctx0_info()
814 * TRAP: HV_FAST_TRAP
815 * FUNCTION: HV_FAST_MMU_TSB_CTX0_INFO
816 * ARG0: max TSBs
817 * ARG1: buffer pointer
818 * RET0: status
819 * RET1: number of TSBs
820 * ERRORS: EINVAL Supplied buffer is too small
821 * EBADALIGN The buffer pointer is badly aligned
822 * ENORADDR Invalid real address for buffer pointer
823 *
824 * Return the TSB configuration as previous defined by mmu_tsb_ctx0()
825 * into the provided buffer. The size of the buffer is given in ARG1
826 * in terms of the number of TSB description entries.
827 *
828 * Upon return, RET1 always contains the number of TSB descriptions
829 * previously configured. If zero TSBs were configured, EOK is
830 * returned with RET1 containing 0.
831 */
832#define HV_FAST_MMU_TSB_CTX0_INFO 0x29
833
834/* mmu_tsb_ctxnon0_info()
835 * TRAP: HV_FAST_TRAP
836 * FUNCTION: HV_FAST_MMU_TSB_CTXNON0_INFO
837 * ARG0: max TSBs
838 * ARG1: buffer pointer
839 * RET0: status
840 * RET1: number of TSBs
841 * ERRORS: EINVAL Supplied buffer is too small
842 * EBADALIGN The buffer pointer is badly aligned
843 * ENORADDR Invalid real address for buffer pointer
844 *
845 * Return the TSB configuration as previous defined by
846 * mmu_tsb_ctxnon0() into the provided buffer. The size of the buffer
847 * is given in ARG1 in terms of the number of TSB description entries.
848 *
849 * Upon return, RET1 always contains the number of TSB descriptions
850 * previously configured. If zero TSBs were configured, EOK is
851 * returned with RET1 containing 0.
852 */
853#define HV_FAST_MMU_TSB_CTXNON0_INFO 0x2a
854
855/* mmu_fault_area_info()
856 * TRAP: HV_FAST_TRAP
857 * FUNCTION: HV_FAST_MMU_FAULT_AREA_INFO
858 * RET0: status
859 * RET1: fault area real address
860 * ERRORS: No errors defined.
861 *
862 * Return the currently defined MMU fault status area for the current
863 * CPU. The real address of the fault status area is returned in
864 * RET1, or 0 is returned in RET1 if no fault status area is defined.
865 *
866 * Note: mmu_fault_area_conf() may be called with the return value (RET1)
867 * from this service if there is a need to save and restore the fault
868 * area for a cpu.
869 */
870#define HV_FAST_MMU_FAULT_AREA_INFO 0x2b
871
872/* Cache and Memory services. */
873
874/* mem_scrub()
875 * TRAP: HV_FAST_TRAP
876 * FUNCTION: HV_FAST_MEM_SCRUB
877 * ARG0: real address
878 * ARG1: length
879 * RET0: status
880 * RET1: length scrubbed
881 * ERRORS: ENORADDR Invalid real address
882 * EBADALIGN Start address or length are not correctly
883 * aligned
884 * EINVAL Length is zero
885 *
886 * Zero the memory contents in the range real address to real address
887 * plus length minus 1. Also, valid ECC will be generated for that
888 * memory address range. Scrubbing is started at the given real
889 * address, but may not scrub the entire given length. The actual
890 * length scrubbed will be returned in RET1.
891 *
892 * The real address and length must be aligned on an 8K boundary, or
893 * contain the start address and length from a sun4v error report.
894 *
895 * Note: There are two uses for this function. The first use is to block clear
896 * and initialize memory and the second is to scrub an u ncorrectable
897 * error reported via a resumable or non-resumable trap. The second
898 * use requires the arguments to be equal to the real address and length
899 * provided in a sun4v memory error report.
900 */
901#define HV_FAST_MEM_SCRUB 0x31
902
903/* mem_sync()
904 * TRAP: HV_FAST_TRAP
905 * FUNCTION: HV_FAST_MEM_SYNC
906 * ARG0: real address
907 * ARG1: length
908 * RET0: status
909 * RET1: length synced
910 * ERRORS: ENORADDR Invalid real address
911 * EBADALIGN Start address or length are not correctly
912 * aligned
913 * EINVAL Length is zero
914 *
915 * Force the next access within the real address to real address plus
916 * length minus 1 to be fetches from main system memory. Less than
917 * the given length may be synced, the actual amount synced is
918 * returned in RET1. The real address and length must be aligned on
919 * an 8K boundary.
920 */
921#define HV_FAST_MEM_SYNC 0x32
922
923/* Time of day services.
924 *
925 * The hypervisor maintains the time of day on a per-domain basis.
926 * Changing the time of day in one domain does not affect the time of
927 * day on any other domain.
928 *
929 * Time is described by a single unsigned 64-bit word which is the
930 * number of seconds since the UNIX Epoch (00:00:00 UTC, January 1,
931 * 1970).
932 */
933
934/* tod_get()
935 * TRAP: HV_FAST_TRAP
936 * FUNCTION: HV_FAST_TOD_GET
937 * RET0: status
938 * RET1: TOD
939 * ERRORS: EWOULDBLOCK TOD resource is temporarily unavailable
940 * ENOTSUPPORTED If TOD not supported on this platform
941 *
942 * Return the current time of day. May block if TOD access is
943 * temporarily not possible.
944 */
945#define HV_FAST_TOD_GET 0x50
946
947#ifndef __ASSEMBLY__
948extern unsigned long sun4v_tod_get(unsigned long *time);
949#endif
950
951/* tod_set()
952 * TRAP: HV_FAST_TRAP
953 * FUNCTION: HV_FAST_TOD_SET
954 * ARG0: TOD
955 * RET0: status
956 * ERRORS: EWOULDBLOCK TOD resource is temporarily unavailable
957 * ENOTSUPPORTED If TOD not supported on this platform
958 *
959 * The current time of day is set to the value specified in ARG0. May
960 * block if TOD access is temporarily not possible.
961 */
962#define HV_FAST_TOD_SET 0x51
963
964#ifndef __ASSEMBLY__
965extern unsigned long sun4v_tod_set(unsigned long time);
966#endif
967
968/* Console services */
969
970/* con_getchar()
971 * TRAP: HV_FAST_TRAP
972 * FUNCTION: HV_FAST_CONS_GETCHAR
973 * RET0: status
974 * RET1: character
975 * ERRORS: EWOULDBLOCK No character available.
976 *
977 * Returns a character from the console device. If no character is
978 * available then an EWOULDBLOCK error is returned. If a character is
979 * available, then the returned status is EOK and the character value
980 * is in RET1.
981 *
982 * A virtual BREAK is represented by the 64-bit value -1.
983 *
984 * A virtual HUP signal is represented by the 64-bit value -2.
985 */
986#define HV_FAST_CONS_GETCHAR 0x60
987
988/* con_putchar()
989 * TRAP: HV_FAST_TRAP
990 * FUNCTION: HV_FAST_CONS_PUTCHAR
991 * ARG0: character
992 * RET0: status
993 * ERRORS: EINVAL Illegal character
994 * EWOULDBLOCK Output buffer currently full, would block
995 *
996 * Send a character to the console device. Only character values
997 * between 0 and 255 may be used. Values outside this range are
998 * invalid except for the 64-bit value -1 which is used to send a
999 * virtual BREAK.
1000 */
1001#define HV_FAST_CONS_PUTCHAR 0x61
1002
1003/* con_read()
1004 * TRAP: HV_FAST_TRAP
1005 * FUNCTION: HV_FAST_CONS_READ
1006 * ARG0: buffer real address
1007 * ARG1: buffer size in bytes
1008 * RET0: status
1009 * RET1: bytes read or BREAK or HUP
1010 * ERRORS: EWOULDBLOCK No character available.
1011 *
1012 * Reads characters into a buffer from the console device. If no
1013 * character is available then an EWOULDBLOCK error is returned.
1014 * If a character is available, then the returned status is EOK
1015 * and the number of bytes read into the given buffer is provided
1016 * in RET1.
1017 *
1018 * A virtual BREAK is represented by the 64-bit RET1 value -1.
1019 *
1020 * A virtual HUP signal is represented by the 64-bit RET1 value -2.
1021 *
1022 * If BREAK or HUP are indicated, no bytes were read into buffer.
1023 */
1024#define HV_FAST_CONS_READ 0x62
1025
1026/* con_write()
1027 * TRAP: HV_FAST_TRAP
1028 * FUNCTION: HV_FAST_CONS_WRITE
1029 * ARG0: buffer real address
1030 * ARG1: buffer size in bytes
1031 * RET0: status
1032 * RET1: bytes written
1033 * ERRORS: EWOULDBLOCK Output buffer currently full, would block
1034 *
1035 * Send a characters in buffer to the console device. Breaks must be
1036 * sent using con_putchar().
1037 */
1038#define HV_FAST_CONS_WRITE 0x63
1039
1040#ifndef __ASSEMBLY__
1041extern long sun4v_con_getchar(long *status);
1042extern long sun4v_con_putchar(long c);
1043extern long sun4v_con_read(unsigned long buffer,
1044 unsigned long size,
1045 unsigned long *bytes_read);
1046extern unsigned long sun4v_con_write(unsigned long buffer,
1047 unsigned long size,
1048 unsigned long *bytes_written);
1049#endif
1050
1051/* mach_set_soft_state()
1052 * TRAP: HV_FAST_TRAP
1053 * FUNCTION: HV_FAST_MACH_SET_SOFT_STATE
1054 * ARG0: software state
1055 * ARG1: software state description pointer
1056 * RET0: status
1057 * ERRORS: EINVAL software state not valid or software state
1058 * description is not NULL terminated
1059 * ENORADDR software state description pointer is not a
1060 * valid real address
1061 * EBADALIGNED software state description is not correctly
1062 * aligned
1063 *
1064 * This allows the guest to report it's soft state to the hypervisor. There
1065 * are two primary components to this state. The first part states whether
1066 * the guest software is running or not. The second containts optional
1067 * details specific to the software.
1068 *
1069 * The software state argument is defined below in HV_SOFT_STATE_*, and
1070 * indicates whether the guest is operating normally or in a transitional
1071 * state.
1072 *
1073 * The software state description argument is a real address of a data buffer
1074 * of size 32-bytes aligned on a 32-byte boundary. It is treated as a NULL
1075 * terminated 7-bit ASCII string of up to 31 characters not including the
1076 * NULL termination.
1077 */
1078#define HV_FAST_MACH_SET_SOFT_STATE 0x70
1079#define HV_SOFT_STATE_NORMAL 0x01
1080#define HV_SOFT_STATE_TRANSITION 0x02
1081
1082#ifndef __ASSEMBLY__
1083extern unsigned long sun4v_mach_set_soft_state(unsigned long soft_state,
1084 unsigned long msg_string_ra);
1085#endif
1086
1087/* mach_get_soft_state()
1088 * TRAP: HV_FAST_TRAP
1089 * FUNCTION: HV_FAST_MACH_GET_SOFT_STATE
1090 * ARG0: software state description pointer
1091 * RET0: status
1092 * RET1: software state
1093 * ERRORS: ENORADDR software state description pointer is not a
1094 * valid real address
1095 * EBADALIGNED software state description is not correctly
1096 * aligned
1097 *
1098 * Retrieve the current value of the guest's software state. The rules
1099 * for the software state pointer are the same as for mach_set_soft_state()
1100 * above.
1101 */
1102#define HV_FAST_MACH_GET_SOFT_STATE 0x71
1103
1104/* svc_send()
1105 * TRAP: HV_FAST_TRAP
1106 * FUNCTION: HV_FAST_SVC_SEND
1107 * ARG0: service ID
1108 * ARG1: buffer real address
1109 * ARG2: buffer size
1110 * RET0: STATUS
1111 * RET1: sent_bytes
1112 *
1113 * Be careful, all output registers are clobbered by this operation,
1114 * so for example it is not possible to save away a value in %o4
1115 * across the trap.
1116 */
1117#define HV_FAST_SVC_SEND 0x80
1118
1119/* svc_recv()
1120 * TRAP: HV_FAST_TRAP
1121 * FUNCTION: HV_FAST_SVC_RECV
1122 * ARG0: service ID
1123 * ARG1: buffer real address
1124 * ARG2: buffer size
1125 * RET0: STATUS
1126 * RET1: recv_bytes
1127 *
1128 * Be careful, all output registers are clobbered by this operation,
1129 * so for example it is not possible to save away a value in %o4
1130 * across the trap.
1131 */
1132#define HV_FAST_SVC_RECV 0x81
1133
1134/* svc_getstatus()
1135 * TRAP: HV_FAST_TRAP
1136 * FUNCTION: HV_FAST_SVC_GETSTATUS
1137 * ARG0: service ID
1138 * RET0: STATUS
1139 * RET1: status bits
1140 */
1141#define HV_FAST_SVC_GETSTATUS 0x82
1142
1143/* svc_setstatus()
1144 * TRAP: HV_FAST_TRAP
1145 * FUNCTION: HV_FAST_SVC_SETSTATUS
1146 * ARG0: service ID
1147 * ARG1: bits to set
1148 * RET0: STATUS
1149 */
1150#define HV_FAST_SVC_SETSTATUS 0x83
1151
1152/* svc_clrstatus()
1153 * TRAP: HV_FAST_TRAP
1154 * FUNCTION: HV_FAST_SVC_CLRSTATUS
1155 * ARG0: service ID
1156 * ARG1: bits to clear
1157 * RET0: STATUS
1158 */
1159#define HV_FAST_SVC_CLRSTATUS 0x84
1160
1161#ifndef __ASSEMBLY__
1162extern unsigned long sun4v_svc_send(unsigned long svc_id,
1163 unsigned long buffer,
1164 unsigned long buffer_size,
1165 unsigned long *sent_bytes);
1166extern unsigned long sun4v_svc_recv(unsigned long svc_id,
1167 unsigned long buffer,
1168 unsigned long buffer_size,
1169 unsigned long *recv_bytes);
1170extern unsigned long sun4v_svc_getstatus(unsigned long svc_id,
1171 unsigned long *status_bits);
1172extern unsigned long sun4v_svc_setstatus(unsigned long svc_id,
1173 unsigned long status_bits);
1174extern unsigned long sun4v_svc_clrstatus(unsigned long svc_id,
1175 unsigned long status_bits);
1176#endif
1177
1178/* Trap trace services.
1179 *
1180 * The hypervisor provides a trap tracing capability for privileged
1181 * code running on each virtual CPU. Privileged code provides a
1182 * round-robin trap trace queue within which the hypervisor writes
1183 * 64-byte entries detailing hyperprivileged traps taken n behalf of
1184 * privileged code. This is provided as a debugging capability for
1185 * privileged code.
1186 *
1187 * The trap trace control structure is 64-bytes long and placed at the
1188 * start (offset 0) of the trap trace buffer, and is described as
1189 * follows:
1190 */
1191#ifndef __ASSEMBLY__
1192struct hv_trap_trace_control {
1193 unsigned long head_offset;
1194 unsigned long tail_offset;
1195 unsigned long __reserved[0x30 / sizeof(unsigned long)];
1196};
1197#endif
1198#define HV_TRAP_TRACE_CTRL_HEAD_OFFSET 0x00
1199#define HV_TRAP_TRACE_CTRL_TAIL_OFFSET 0x08
1200
1201/* The head offset is the offset of the most recently completed entry
1202 * in the trap-trace buffer. The tail offset is the offset of the
1203 * next entry to be written. The control structure is owned and
1204 * modified by the hypervisor. A guest may not modify the control
1205 * structure contents. Attempts to do so will result in undefined
1206 * behavior for the guest.
1207 *
1208 * Each trap trace buffer entry is layed out as follows:
1209 */
1210#ifndef __ASSEMBLY__
1211struct hv_trap_trace_entry {
1212 unsigned char type; /* Hypervisor or guest entry? */
1213 unsigned char hpstate; /* Hyper-privileged state */
1214 unsigned char tl; /* Trap level */
1215 unsigned char gl; /* Global register level */
1216 unsigned short tt; /* Trap type */
1217 unsigned short tag; /* Extended trap identifier */
1218 unsigned long tstate; /* Trap state */
1219 unsigned long tick; /* Tick */
1220 unsigned long tpc; /* Trap PC */
1221 unsigned long f1; /* Entry specific */
1222 unsigned long f2; /* Entry specific */
1223 unsigned long f3; /* Entry specific */
1224 unsigned long f4; /* Entry specific */
1225};
1226#endif
1227#define HV_TRAP_TRACE_ENTRY_TYPE 0x00
1228#define HV_TRAP_TRACE_ENTRY_HPSTATE 0x01
1229#define HV_TRAP_TRACE_ENTRY_TL 0x02
1230#define HV_TRAP_TRACE_ENTRY_GL 0x03
1231#define HV_TRAP_TRACE_ENTRY_TT 0x04
1232#define HV_TRAP_TRACE_ENTRY_TAG 0x06
1233#define HV_TRAP_TRACE_ENTRY_TSTATE 0x08
1234#define HV_TRAP_TRACE_ENTRY_TICK 0x10
1235#define HV_TRAP_TRACE_ENTRY_TPC 0x18
1236#define HV_TRAP_TRACE_ENTRY_F1 0x20
1237#define HV_TRAP_TRACE_ENTRY_F2 0x28
1238#define HV_TRAP_TRACE_ENTRY_F3 0x30
1239#define HV_TRAP_TRACE_ENTRY_F4 0x38
1240
1241/* The type field is encoded as follows. */
1242#define HV_TRAP_TYPE_UNDEF 0x00 /* Entry content undefined */
1243#define HV_TRAP_TYPE_HV 0x01 /* Hypervisor trap entry */
1244#define HV_TRAP_TYPE_GUEST 0xff /* Added via ttrace_addentry() */
1245
1246/* ttrace_buf_conf()
1247 * TRAP: HV_FAST_TRAP
1248 * FUNCTION: HV_FAST_TTRACE_BUF_CONF
1249 * ARG0: real address
1250 * ARG1: number of entries
1251 * RET0: status
1252 * RET1: number of entries
1253 * ERRORS: ENORADDR Invalid real address
1254 * EINVAL Size is too small
1255 * EBADALIGN Real address not aligned on 64-byte boundary
1256 *
1257 * Requests hypervisor trap tracing and declares a virtual CPU's trap
1258 * trace buffer to the hypervisor. The real address supplies the real
1259 * base address of the trap trace queue and must be 64-byte aligned.
1260 * Specifying a value of 0 for the number of entries disables trap
1261 * tracing for the calling virtual CPU. The buffer allocated must be
1262 * sized for a power of two number of 64-byte trap trace entries plus
1263 * an initial 64-byte control structure.
1264 *
1265 * This may be invoked any number of times so that a virtual CPU may
1266 * relocate a trap trace buffer or create "snapshots" of information.
1267 *
1268 * If the real address is illegal or badly aligned, then trap tracing
1269 * is disabled and an error is returned.
1270 *
1271 * Upon failure with EINVAL, this service call returns in RET1 the
1272 * minimum number of buffer entries required. Upon other failures
1273 * RET1 is undefined.
1274 */
1275#define HV_FAST_TTRACE_BUF_CONF 0x90
1276
1277/* ttrace_buf_info()
1278 * TRAP: HV_FAST_TRAP
1279 * FUNCTION: HV_FAST_TTRACE_BUF_INFO
1280 * RET0: status
1281 * RET1: real address
1282 * RET2: size
1283 * ERRORS: None defined.
1284 *
1285 * Returns the size and location of the previously declared trap-trace
1286 * buffer. In the event that no buffer was previously defined, or the
1287 * buffer is disabled, this call will return a size of zero bytes.
1288 */
1289#define HV_FAST_TTRACE_BUF_INFO 0x91
1290
1291/* ttrace_enable()
1292 * TRAP: HV_FAST_TRAP
1293 * FUNCTION: HV_FAST_TTRACE_ENABLE
1294 * ARG0: enable
1295 * RET0: status
1296 * RET1: previous enable state
1297 * ERRORS: EINVAL No trap trace buffer currently defined
1298 *
1299 * Enable or disable trap tracing, and return the previous enabled
1300 * state in RET1. Future systems may define various flags for the
1301 * enable argument (ARG0), for the moment a guest should pass
1302 * "(uint64_t) -1" to enable, and "(uint64_t) 0" to disable all
1303 * tracing - which will ensure future compatability.
1304 */
1305#define HV_FAST_TTRACE_ENABLE 0x92
1306
1307/* ttrace_freeze()
1308 * TRAP: HV_FAST_TRAP
1309 * FUNCTION: HV_FAST_TTRACE_FREEZE
1310 * ARG0: freeze
1311 * RET0: status
1312 * RET1: previous freeze state
1313 * ERRORS: EINVAL No trap trace buffer currently defined
1314 *
1315 * Freeze or unfreeze trap tracing, returning the previous freeze
1316 * state in RET1. A guest should pass a non-zero value to freeze and
1317 * a zero value to unfreeze all tracing. The returned previous state
1318 * is 0 for not frozen and 1 for frozen.
1319 */
1320#define HV_FAST_TTRACE_FREEZE 0x93
1321
1322/* ttrace_addentry()
1323 * TRAP: HV_TTRACE_ADDENTRY_TRAP
1324 * ARG0: tag (16-bits)
1325 * ARG1: data word 0
1326 * ARG2: data word 1
1327 * ARG3: data word 2
1328 * ARG4: data word 3
1329 * RET0: status
1330 * ERRORS: EINVAL No trap trace buffer currently defined
1331 *
1332 * Add an entry to the trap trace buffer. Upon return only ARG0/RET0
1333 * is modified - none of the other registers holding arguments are
1334 * volatile across this hypervisor service.
1335 */
1336
1337/* Core dump services.
1338 *
1339 * Since the hypervisor viraulizes and thus obscures a lot of the
1340 * physical machine layout and state, traditional OS crash dumps can
1341 * be difficult to diagnose especially when the problem is a
1342 * configuration error of some sort.
1343 *
1344 * The dump services provide an opaque buffer into which the
1345 * hypervisor can place it's internal state in order to assist in
1346 * debugging such situations. The contents are opaque and extremely
1347 * platform and hypervisor implementation specific. The guest, during
1348 * a core dump, requests that the hypervisor update any information in
1349 * the dump buffer in preparation to being dumped as part of the
1350 * domain's memory image.
1351 */
1352
1353/* dump_buf_update()
1354 * TRAP: HV_FAST_TRAP
1355 * FUNCTION: HV_FAST_DUMP_BUF_UPDATE
1356 * ARG0: real address
1357 * ARG1: size
1358 * RET0: status
1359 * RET1: required size of dump buffer
1360 * ERRORS: ENORADDR Invalid real address
1361 * EBADALIGN Real address is not aligned on a 64-byte
1362 * boundary
1363 * EINVAL Size is non-zero but less than minimum size
1364 * required
1365 * ENOTSUPPORTED Operation not supported on current logical
1366 * domain
1367 *
1368 * Declare a domain dump buffer to the hypervisor. The real address
1369 * provided for the domain dump buffer must be 64-byte aligned. The
1370 * size specifies the size of the dump buffer and may be larger than
1371 * the minimum size specified in the machine description. The
1372 * hypervisor will fill the dump buffer with opaque data.
1373 *
1374 * Note: A guest may elect to include dump buffer contents as part of a crash
1375 * dump to assist with debugging. This function may be called any number
1376 * of times so that a guest may relocate a dump buffer, or create
1377 * "snapshots" of any dump-buffer information. Each call to
1378 * dump_buf_update() atomically declares the new dump buffer to the
1379 * hypervisor.
1380 *
1381 * A specified size of 0 unconfigures the dump buffer. If the real
1382 * address is illegal or badly aligned, then any currently active dump
1383 * buffer is disabled and an error is returned.
1384 *
1385 * In the event that the call fails with EINVAL, RET1 contains the
1386 * minimum size requires by the hypervisor for a valid dump buffer.
1387 */
1388#define HV_FAST_DUMP_BUF_UPDATE 0x94
1389
1390/* dump_buf_info()
1391 * TRAP: HV_FAST_TRAP
1392 * FUNCTION: HV_FAST_DUMP_BUF_INFO
1393 * RET0: status
1394 * RET1: real address of current dump buffer
1395 * RET2: size of current dump buffer
1396 * ERRORS: No errors defined.
1397 *
1398 * Return the currently configures dump buffer description. A
1399 * returned size of 0 bytes indicates an undefined dump buffer. In
1400 * this case the return address in RET1 is undefined.
1401 */
1402#define HV_FAST_DUMP_BUF_INFO 0x95
1403
1404/* Device interrupt services.
1405 *
1406 * Device interrupts are allocated to system bus bridges by the hypervisor,
1407 * and described to OBP in the machine description. OBP then describes
1408 * these interrupts to the OS via properties in the device tree.
1409 *
1410 * Terminology:
1411 *
1412 * cpuid Unique opaque value which represents a target cpu.
1413 *
1414 * devhandle Device handle. It uniquely identifies a device, and
1415 * consistes of the lower 28-bits of the hi-cell of the
1416 * first entry of the device's "reg" property in the
1417 * OBP device tree.
1418 *
1419 * devino Device interrupt number. Specifies the relative
1420 * interrupt number within the device. The unique
1421 * combination of devhandle and devino are used to
1422 * identify a specific device interrupt.
1423 *
1424 * Note: The devino value is the same as the values in the
1425 * "interrupts" property or "interrupt-map" property
1426 * in the OBP device tree for that device.
1427 *
1428 * sysino System interrupt number. A 64-bit unsigned interger
1429 * representing a unique interrupt within a virtual
1430 * machine.
1431 *
1432 * intr_state A flag representing the interrupt state for a given
1433 * sysino. The state values are defined below.
1434 *
1435 * intr_enabled A flag representing the 'enabled' state for a given
1436 * sysino. The enable values are defined below.
1437 */
1438
1439#define HV_INTR_STATE_IDLE 0 /* Nothing pending */
1440#define HV_INTR_STATE_RECEIVED 1 /* Interrupt received by hardware */
1441#define HV_INTR_STATE_DELIVERED 2 /* Interrupt delivered to queue */
1442
1443#define HV_INTR_DISABLED 0 /* sysino not enabled */
1444#define HV_INTR_ENABLED 1 /* sysino enabled */
1445
1446/* intr_devino_to_sysino()
1447 * TRAP: HV_FAST_TRAP
1448 * FUNCTION: HV_FAST_INTR_DEVINO2SYSINO
1449 * ARG0: devhandle
1450 * ARG1: devino
1451 * RET0: status
1452 * RET1: sysino
1453 * ERRORS: EINVAL Invalid devhandle/devino
1454 *
1455 * Converts a device specific interrupt number of the given
1456 * devhandle/devino into a system specific ino (sysino).
1457 */
1458#define HV_FAST_INTR_DEVINO2SYSINO 0xa0
1459
1460#ifndef __ASSEMBLY__
1461extern unsigned long sun4v_devino_to_sysino(unsigned long devhandle,
1462 unsigned long devino);
1463#endif
1464
1465/* intr_getenabled()
1466 * TRAP: HV_FAST_TRAP
1467 * FUNCTION: HV_FAST_INTR_GETENABLED
1468 * ARG0: sysino
1469 * RET0: status
1470 * RET1: intr_enabled (HV_INTR_{DISABLED,ENABLED})
1471 * ERRORS: EINVAL Invalid sysino
1472 *
1473 * Returns interrupt enabled state in RET1 for the interrupt defined
1474 * by the given sysino.
1475 */
1476#define HV_FAST_INTR_GETENABLED 0xa1
1477
1478#ifndef __ASSEMBLY__
1479extern unsigned long sun4v_intr_getenabled(unsigned long sysino);
1480#endif
1481
1482/* intr_setenabled()
1483 * TRAP: HV_FAST_TRAP
1484 * FUNCTION: HV_FAST_INTR_SETENABLED
1485 * ARG0: sysino
1486 * ARG1: intr_enabled (HV_INTR_{DISABLED,ENABLED})
1487 * RET0: status
1488 * ERRORS: EINVAL Invalid sysino or intr_enabled value
1489 *
1490 * Set the 'enabled' state of the interrupt sysino.
1491 */
1492#define HV_FAST_INTR_SETENABLED 0xa2
1493
1494#ifndef __ASSEMBLY__
1495extern unsigned long sun4v_intr_setenabled(unsigned long sysino, unsigned long intr_enabled);
1496#endif
1497
1498/* intr_getstate()
1499 * TRAP: HV_FAST_TRAP
1500 * FUNCTION: HV_FAST_INTR_GETSTATE
1501 * ARG0: sysino
1502 * RET0: status
1503 * RET1: intr_state (HV_INTR_STATE_*)
1504 * ERRORS: EINVAL Invalid sysino
1505 *
1506 * Returns current state of the interrupt defined by the given sysino.
1507 */
1508#define HV_FAST_INTR_GETSTATE 0xa3
1509
1510#ifndef __ASSEMBLY__
1511extern unsigned long sun4v_intr_getstate(unsigned long sysino);
1512#endif
1513
1514/* intr_setstate()
1515 * TRAP: HV_FAST_TRAP
1516 * FUNCTION: HV_FAST_INTR_SETSTATE
1517 * ARG0: sysino
1518 * ARG1: intr_state (HV_INTR_STATE_*)
1519 * RET0: status
1520 * ERRORS: EINVAL Invalid sysino or intr_state value
1521 *
1522 * Sets the current state of the interrupt described by the given sysino
1523 * value.
1524 *
1525 * Note: Setting the state to HV_INTR_STATE_IDLE clears any pending
1526 * interrupt for sysino.
1527 */
1528#define HV_FAST_INTR_SETSTATE 0xa4
1529
1530#ifndef __ASSEMBLY__
1531extern unsigned long sun4v_intr_setstate(unsigned long sysino, unsigned long intr_state);
1532#endif
1533
1534/* intr_gettarget()
1535 * TRAP: HV_FAST_TRAP
1536 * FUNCTION: HV_FAST_INTR_GETTARGET
1537 * ARG0: sysino
1538 * RET0: status
1539 * RET1: cpuid
1540 * ERRORS: EINVAL Invalid sysino
1541 *
1542 * Returns CPU that is the current target of the interrupt defined by
1543 * the given sysino. The CPU value returned is undefined if the target
1544 * has not been set via intr_settarget().
1545 */
1546#define HV_FAST_INTR_GETTARGET 0xa5
1547
1548#ifndef __ASSEMBLY__
1549extern unsigned long sun4v_intr_gettarget(unsigned long sysino);
1550#endif
1551
1552/* intr_settarget()
1553 * TRAP: HV_FAST_TRAP
1554 * FUNCTION: HV_FAST_INTR_SETTARGET
1555 * ARG0: sysino
1556 * ARG1: cpuid
1557 * RET0: status
1558 * ERRORS: EINVAL Invalid sysino
1559 * ENOCPU Invalid cpuid
1560 *
1561 * Set the target CPU for the interrupt defined by the given sysino.
1562 */
1563#define HV_FAST_INTR_SETTARGET 0xa6
1564
1565#ifndef __ASSEMBLY__
1566extern unsigned long sun4v_intr_settarget(unsigned long sysino, unsigned long cpuid);
1567#endif
1568
1569/* vintr_get_cookie()
1570 * TRAP: HV_FAST_TRAP
1571 * FUNCTION: HV_FAST_VINTR_GET_COOKIE
1572 * ARG0: device handle
1573 * ARG1: device ino
1574 * RET0: status
1575 * RET1: cookie
1576 */
1577#define HV_FAST_VINTR_GET_COOKIE 0xa7
1578
1579/* vintr_set_cookie()
1580 * TRAP: HV_FAST_TRAP
1581 * FUNCTION: HV_FAST_VINTR_SET_COOKIE
1582 * ARG0: device handle
1583 * ARG1: device ino
1584 * ARG2: cookie
1585 * RET0: status
1586 */
1587#define HV_FAST_VINTR_SET_COOKIE 0xa8
1588
1589/* vintr_get_valid()
1590 * TRAP: HV_FAST_TRAP
1591 * FUNCTION: HV_FAST_VINTR_GET_VALID
1592 * ARG0: device handle
1593 * ARG1: device ino
1594 * RET0: status
1595 * RET1: valid state
1596 */
1597#define HV_FAST_VINTR_GET_VALID 0xa9
1598
1599/* vintr_set_valid()
1600 * TRAP: HV_FAST_TRAP
1601 * FUNCTION: HV_FAST_VINTR_SET_VALID
1602 * ARG0: device handle
1603 * ARG1: device ino
1604 * ARG2: valid state
1605 * RET0: status
1606 */
1607#define HV_FAST_VINTR_SET_VALID 0xaa
1608
1609/* vintr_get_state()
1610 * TRAP: HV_FAST_TRAP
1611 * FUNCTION: HV_FAST_VINTR_GET_STATE
1612 * ARG0: device handle
1613 * ARG1: device ino
1614 * RET0: status
1615 * RET1: state
1616 */
1617#define HV_FAST_VINTR_GET_STATE 0xab
1618
1619/* vintr_set_state()
1620 * TRAP: HV_FAST_TRAP
1621 * FUNCTION: HV_FAST_VINTR_SET_STATE
1622 * ARG0: device handle
1623 * ARG1: device ino
1624 * ARG2: state
1625 * RET0: status
1626 */
1627#define HV_FAST_VINTR_SET_STATE 0xac
1628
1629/* vintr_get_target()
1630 * TRAP: HV_FAST_TRAP
1631 * FUNCTION: HV_FAST_VINTR_GET_TARGET
1632 * ARG0: device handle
1633 * ARG1: device ino
1634 * RET0: status
1635 * RET1: cpuid
1636 */
1637#define HV_FAST_VINTR_GET_TARGET 0xad
1638
1639/* vintr_set_target()
1640 * TRAP: HV_FAST_TRAP
1641 * FUNCTION: HV_FAST_VINTR_SET_TARGET
1642 * ARG0: device handle
1643 * ARG1: device ino
1644 * ARG2: cpuid
1645 * RET0: status
1646 */
1647#define HV_FAST_VINTR_SET_TARGET 0xae
1648
1649#ifndef __ASSEMBLY__
1650extern unsigned long sun4v_vintr_get_cookie(unsigned long dev_handle,
1651 unsigned long dev_ino,
1652 unsigned long *cookie);
1653extern unsigned long sun4v_vintr_set_cookie(unsigned long dev_handle,
1654 unsigned long dev_ino,
1655 unsigned long cookie);
1656extern unsigned long sun4v_vintr_get_valid(unsigned long dev_handle,
1657 unsigned long dev_ino,
1658 unsigned long *valid);
1659extern unsigned long sun4v_vintr_set_valid(unsigned long dev_handle,
1660 unsigned long dev_ino,
1661 unsigned long valid);
1662extern unsigned long sun4v_vintr_get_state(unsigned long dev_handle,
1663 unsigned long dev_ino,
1664 unsigned long *state);
1665extern unsigned long sun4v_vintr_set_state(unsigned long dev_handle,
1666 unsigned long dev_ino,
1667 unsigned long state);
1668extern unsigned long sun4v_vintr_get_target(unsigned long dev_handle,
1669 unsigned long dev_ino,
1670 unsigned long *cpuid);
1671extern unsigned long sun4v_vintr_set_target(unsigned long dev_handle,
1672 unsigned long dev_ino,
1673 unsigned long cpuid);
1674#endif
1675
1676/* PCI IO services.
1677 *
1678 * See the terminology descriptions in the device interrupt services
1679 * section above as those apply here too. Here are terminology
1680 * definitions specific to these PCI IO services:
1681 *
1682 * tsbnum TSB number. Indentifies which io-tsb is used.
1683 * For this version of the specification, tsbnum
1684 * must be zero.
1685 *
1686 * tsbindex TSB index. Identifies which entry in the TSB
1687 * is used. The first entry is zero.
1688 *
1689 * tsbid A 64-bit aligned data structure which contains
1690 * a tsbnum and a tsbindex. Bits 63:32 contain the
1691 * tsbnum and bits 31:00 contain the tsbindex.
1692 *
1693 * Use the HV_PCI_TSBID() macro to construct such
1694 * values.
1695 *
1696 * io_attributes IO attributes for IOMMU mappings. One of more
1697 * of the attritbute bits are stores in a 64-bit
1698 * value. The values are defined below.
1699 *
1700 * r_addr 64-bit real address
1701 *
1702 * pci_device PCI device address. A PCI device address identifies
1703 * a specific device on a specific PCI bus segment.
1704 * A PCI device address ia a 32-bit unsigned integer
1705 * with the following format:
1706 *
1707 * 00000000.bbbbbbbb.dddddfff.00000000
1708 *
1709 * Use the HV_PCI_DEVICE_BUILD() macro to construct
1710 * such values.
1711 *
1712 * pci_config_offset
1713 * PCI configureation space offset. For conventional
1714 * PCI a value between 0 and 255. For extended
1715 * configuration space, a value between 0 and 4095.
1716 *
1717 * Note: For PCI configuration space accesses, the offset
1718 * must be aligned to the access size.
1719 *
1720 * error_flag A return value which specifies if the action succeeded
1721 * or failed. 0 means no error, non-0 means some error
1722 * occurred while performing the service.
1723 *
1724 * io_sync_direction
1725 * Direction definition for pci_dma_sync(), defined
1726 * below in HV_PCI_SYNC_*.
1727 *
1728 * io_page_list A list of io_page_addresses, an io_page_address is
1729 * a real address.
1730 *
1731 * io_page_list_p A pointer to an io_page_list.
1732 *
1733 * "size based byte swap" - Some functions do size based byte swapping
1734 * which allows sw to access pointers and
1735 * counters in native form when the processor
1736 * operates in a different endianness than the
1737 * IO bus. Size-based byte swapping converts a
1738 * multi-byte field between big-endian and
1739 * little-endian format.
1740 */
1741
1742#define HV_PCI_MAP_ATTR_READ 0x01
1743#define HV_PCI_MAP_ATTR_WRITE 0x02
1744
1745#define HV_PCI_DEVICE_BUILD(b,d,f) \
1746 ((((b) & 0xff) << 16) | \
1747 (((d) & 0x1f) << 11) | \
1748 (((f) & 0x07) << 8))
1749
1750#define HV_PCI_TSBID(__tsb_num, __tsb_index) \
1751 ((((u64)(__tsb_num)) << 32UL) | ((u64)(__tsb_index)))
1752
1753#define HV_PCI_SYNC_FOR_DEVICE 0x01
1754#define HV_PCI_SYNC_FOR_CPU 0x02
1755
1756/* pci_iommu_map()
1757 * TRAP: HV_FAST_TRAP
1758 * FUNCTION: HV_FAST_PCI_IOMMU_MAP
1759 * ARG0: devhandle
1760 * ARG1: tsbid
1761 * ARG2: #ttes
1762 * ARG3: io_attributes
1763 * ARG4: io_page_list_p
1764 * RET0: status
1765 * RET1: #ttes mapped
1766 * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex/io_attributes
1767 * EBADALIGN Improperly aligned real address
1768 * ENORADDR Invalid real address
1769 *
1770 * Create IOMMU mappings in the sun4v device defined by the given
1771 * devhandle. The mappings are created in the TSB defined by the
1772 * tsbnum component of the given tsbid. The first mapping is created
1773 * in the TSB i ndex defined by the tsbindex component of the given tsbid.
1774 * The call creates up to #ttes mappings, the first one at tsbnum, tsbindex,
1775 * the second at tsbnum, tsbindex + 1, etc.
1776 *
1777 * All mappings are created with the attributes defined by the io_attributes
1778 * argument. The page mapping addresses are described in the io_page_list
1779 * defined by the given io_page_list_p, which is a pointer to the io_page_list.
1780 * The first entry in the io_page_list is the address for the first iotte, the
1781 * 2nd for the 2nd iotte, and so on.
1782 *
1783 * Each io_page_address in the io_page_list must be appropriately aligned.
1784 * #ttes must be greater than zero. For this version of the spec, the tsbnum
1785 * component of the given tsbid must be zero.
1786 *
1787 * Returns the actual number of mappings creates, which may be less than
1788 * or equal to the argument #ttes. If the function returns a value which
1789 * is less than the #ttes, the caller may continus to call the function with
1790 * an updated tsbid, #ttes, io_page_list_p arguments until all pages are
1791 * mapped.
1792 *
1793 * Note: This function does not imply an iotte cache flush. The guest must
1794 * demap an entry before re-mapping it.
1795 */
1796#define HV_FAST_PCI_IOMMU_MAP 0xb0
1797
1798/* pci_iommu_demap()
1799 * TRAP: HV_FAST_TRAP
1800 * FUNCTION: HV_FAST_PCI_IOMMU_DEMAP
1801 * ARG0: devhandle
1802 * ARG1: tsbid
1803 * ARG2: #ttes
1804 * RET0: status
1805 * RET1: #ttes demapped
1806 * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex
1807 *
1808 * Demap and flush IOMMU mappings in the device defined by the given
1809 * devhandle. Demaps up to #ttes entries in the TSB defined by the tsbnum
1810 * component of the given tsbid, starting at the TSB index defined by the
1811 * tsbindex component of the given tsbid.
1812 *
1813 * For this version of the spec, the tsbnum of the given tsbid must be zero.
1814 * #ttes must be greater than zero.
1815 *
1816 * Returns the actual number of ttes demapped, which may be less than or equal
1817 * to the argument #ttes. If #ttes demapped is less than #ttes, the caller
1818 * may continue to call this function with updated tsbid and #ttes arguments
1819 * until all pages are demapped.
1820 *
1821 * Note: Entries do not have to be mapped to be demapped. A demap of an
1822 * unmapped page will flush the entry from the tte cache.
1823 */
1824#define HV_FAST_PCI_IOMMU_DEMAP 0xb1
1825
1826/* pci_iommu_getmap()
1827 * TRAP: HV_FAST_TRAP
1828 * FUNCTION: HV_FAST_PCI_IOMMU_GETMAP
1829 * ARG0: devhandle
1830 * ARG1: tsbid
1831 * RET0: status
1832 * RET1: io_attributes
1833 * RET2: real address
1834 * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex
1835 * ENOMAP Mapping is not valid, no translation exists
1836 *
1837 * Read and return the mapping in the device described by the given devhandle
1838 * and tsbid. If successful, the io_attributes shall be returned in RET1
1839 * and the page address of the mapping shall be returned in RET2.
1840 *
1841 * For this version of the spec, the tsbnum component of the given tsbid
1842 * must be zero.
1843 */
1844#define HV_FAST_PCI_IOMMU_GETMAP 0xb2
1845
1846/* pci_iommu_getbypass()
1847 * TRAP: HV_FAST_TRAP
1848 * FUNCTION: HV_FAST_PCI_IOMMU_GETBYPASS
1849 * ARG0: devhandle
1850 * ARG1: real address
1851 * ARG2: io_attributes
1852 * RET0: status
1853 * RET1: io_addr
1854 * ERRORS: EINVAL Invalid devhandle/io_attributes
1855 * ENORADDR Invalid real address
1856 * ENOTSUPPORTED Function not supported in this implementation.
1857 *
1858 * Create a "special" mapping in the device described by the given devhandle,
1859 * for the given real address and attributes. Return the IO address in RET1
1860 * if successful.
1861 */
1862#define HV_FAST_PCI_IOMMU_GETBYPASS 0xb3
1863
1864/* pci_config_get()
1865 * TRAP: HV_FAST_TRAP
1866 * FUNCTION: HV_FAST_PCI_CONFIG_GET
1867 * ARG0: devhandle
1868 * ARG1: pci_device
1869 * ARG2: pci_config_offset
1870 * ARG3: size
1871 * RET0: status
1872 * RET1: error_flag
1873 * RET2: data
1874 * ERRORS: EINVAL Invalid devhandle/pci_device/offset/size
1875 * EBADALIGN pci_config_offset not size aligned
1876 * ENOACCESS Access to this offset is not permitted
1877 *
1878 * Read PCI configuration space for the adapter described by the given
1879 * devhandle. Read size (1, 2, or 4) bytes of data from the given
1880 * pci_device, at pci_config_offset from the beginning of the device's
1881 * configuration space. If there was no error, RET1 is set to zero and
1882 * RET2 is set to the data read. Insignificant bits in RET2 are not
1883 * guarenteed to have any specific value and therefore must be ignored.
1884 *
1885 * The data returned in RET2 is size based byte swapped.
1886 *
1887 * If an error occurs during the read, set RET1 to a non-zero value. The
1888 * given pci_config_offset must be 'size' aligned.
1889 */
1890#define HV_FAST_PCI_CONFIG_GET 0xb4
1891
1892/* pci_config_put()
1893 * TRAP: HV_FAST_TRAP
1894 * FUNCTION: HV_FAST_PCI_CONFIG_PUT
1895 * ARG0: devhandle
1896 * ARG1: pci_device
1897 * ARG2: pci_config_offset
1898 * ARG3: size
1899 * ARG4: data
1900 * RET0: status
1901 * RET1: error_flag
1902 * ERRORS: EINVAL Invalid devhandle/pci_device/offset/size
1903 * EBADALIGN pci_config_offset not size aligned
1904 * ENOACCESS Access to this offset is not permitted
1905 *
1906 * Write PCI configuration space for the adapter described by the given
1907 * devhandle. Write size (1, 2, or 4) bytes of data in a single operation,
1908 * at pci_config_offset from the beginning of the device's configuration
1909 * space. The data argument contains the data to be written to configuration
1910 * space. Prior to writing, the data is size based byte swapped.
1911 *
1912 * If an error occurs during the write access, do not generate an error
1913 * report, do set RET1 to a non-zero value. Otherwise RET1 is zero.
1914 * The given pci_config_offset must be 'size' aligned.
1915 *
1916 * This function is permitted to read from offset zero in the configuration
1917 * space described by the given pci_device if necessary to ensure that the
1918 * write access to config space completes.
1919 */
1920#define HV_FAST_PCI_CONFIG_PUT 0xb5
1921
1922/* pci_peek()
1923 * TRAP: HV_FAST_TRAP
1924 * FUNCTION: HV_FAST_PCI_PEEK
1925 * ARG0: devhandle
1926 * ARG1: real address
1927 * ARG2: size
1928 * RET0: status
1929 * RET1: error_flag
1930 * RET2: data
1931 * ERRORS: EINVAL Invalid devhandle or size
1932 * EBADALIGN Improperly aligned real address
1933 * ENORADDR Bad real address
1934 * ENOACCESS Guest access prohibited
1935 *
1936 * Attempt to read the IO address given by the given devhandle, real address,
1937 * and size. Size must be 1, 2, 4, or 8. The read is performed as a single
1938 * access operation using the given size. If an error occurs when reading
1939 * from the given location, do not generate an error report, but return a
1940 * non-zero value in RET1. If the read was successful, return zero in RET1
1941 * and return the actual data read in RET2. The data returned is size based
1942 * byte swapped.
1943 *
1944 * Non-significant bits in RET2 are not guarenteed to have any specific value
1945 * and therefore must be ignored. If RET1 is returned as non-zero, the data
1946 * value is not guarenteed to have any specific value and should be ignored.
1947 *
1948 * The caller must have permission to read from the given devhandle, real
1949 * address, which must be an IO address. The argument real address must be a
1950 * size aligned address.
1951 *
1952 * The hypervisor implementation of this function must block access to any
1953 * IO address that the guest does not have explicit permission to access.
1954 */
1955#define HV_FAST_PCI_PEEK 0xb6
1956
1957/* pci_poke()
1958 * TRAP: HV_FAST_TRAP
1959 * FUNCTION: HV_FAST_PCI_POKE
1960 * ARG0: devhandle
1961 * ARG1: real address
1962 * ARG2: size
1963 * ARG3: data
1964 * ARG4: pci_device
1965 * RET0: status
1966 * RET1: error_flag
1967 * ERRORS: EINVAL Invalid devhandle, size, or pci_device
1968 * EBADALIGN Improperly aligned real address
1969 * ENORADDR Bad real address
1970 * ENOACCESS Guest access prohibited
1971 * ENOTSUPPORTED Function is not supported by implementation
1972 *
1973 * Attempt to write data to the IO address given by the given devhandle,
1974 * real address, and size. Size must be 1, 2, 4, or 8. The write is
1975 * performed as a single access operation using the given size. Prior to
1976 * writing the data is size based swapped.
1977 *
1978 * If an error occurs when writing to the given location, do not generate an
1979 * error report, but return a non-zero value in RET1. If the write was
1980 * successful, return zero in RET1.
1981 *
1982 * pci_device describes the configuration address of the device being
1983 * written to. The implementation may safely read from offset 0 with
1984 * the configuration space of the device described by devhandle and
1985 * pci_device in order to guarantee that the write portion of the operation
1986 * completes
1987 *
1988 * Any error that occurs due to the read shall be reported using the normal
1989 * error reporting mechanisms .. the read error is not suppressed.
1990 *
1991 * The caller must have permission to write to the given devhandle, real
1992 * address, which must be an IO address. The argument real address must be a
1993 * size aligned address. The caller must have permission to read from
1994 * the given devhandle, pci_device cofiguration space offset 0.
1995 *
1996 * The hypervisor implementation of this function must block access to any
1997 * IO address that the guest does not have explicit permission to access.
1998 */
1999#define HV_FAST_PCI_POKE 0xb7
2000
2001/* pci_dma_sync()
2002 * TRAP: HV_FAST_TRAP
2003 * FUNCTION: HV_FAST_PCI_DMA_SYNC
2004 * ARG0: devhandle
2005 * ARG1: real address
2006 * ARG2: size
2007 * ARG3: io_sync_direction
2008 * RET0: status
2009 * RET1: #synced
2010 * ERRORS: EINVAL Invalid devhandle or io_sync_direction
2011 * ENORADDR Bad real address
2012 *
2013 * Synchronize a memory region described by the given real address and size,
2014 * for the device defined by the given devhandle using the direction(s)
2015 * defined by the given io_sync_direction. The argument size is the size of
2016 * the memory region in bytes.
2017 *
2018 * Return the actual number of bytes synchronized in the return value #synced,
2019 * which may be less than or equal to the argument size. If the return
2020 * value #synced is less than size, the caller must continue to call this
2021 * function with updated real address and size arguments until the entire
2022 * memory region is synchronized.
2023 */
2024#define HV_FAST_PCI_DMA_SYNC 0xb8
2025
2026/* PCI MSI services. */
2027
2028#define HV_MSITYPE_MSI32 0x00
2029#define HV_MSITYPE_MSI64 0x01
2030
2031#define HV_MSIQSTATE_IDLE 0x00
2032#define HV_MSIQSTATE_ERROR 0x01
2033
2034#define HV_MSIQ_INVALID 0x00
2035#define HV_MSIQ_VALID 0x01
2036
2037#define HV_MSISTATE_IDLE 0x00
2038#define HV_MSISTATE_DELIVERED 0x01
2039
2040#define HV_MSIVALID_INVALID 0x00
2041#define HV_MSIVALID_VALID 0x01
2042
2043#define HV_PCIE_MSGTYPE_PME_MSG 0x18
2044#define HV_PCIE_MSGTYPE_PME_ACK_MSG 0x1b
2045#define HV_PCIE_MSGTYPE_CORR_MSG 0x30
2046#define HV_PCIE_MSGTYPE_NONFATAL_MSG 0x31
2047#define HV_PCIE_MSGTYPE_FATAL_MSG 0x33
2048
2049#define HV_MSG_INVALID 0x00
2050#define HV_MSG_VALID 0x01
2051
2052/* pci_msiq_conf()
2053 * TRAP: HV_FAST_TRAP
2054 * FUNCTION: HV_FAST_PCI_MSIQ_CONF
2055 * ARG0: devhandle
2056 * ARG1: msiqid
2057 * ARG2: real address
2058 * ARG3: number of entries
2059 * RET0: status
2060 * ERRORS: EINVAL Invalid devhandle, msiqid or nentries
2061 * EBADALIGN Improperly aligned real address
2062 * ENORADDR Bad real address
2063 *
2064 * Configure the MSI queue given by the devhandle and msiqid arguments,
2065 * and to be placed at the given real address and be of the given
2066 * number of entries. The real address must be aligned exactly to match
2067 * the queue size. Each queue entry is 64-bytes long, so f.e. a 32 entry
2068 * queue must be aligned on a 2048 byte real address boundary. The MSI-EQ
2069 * Head and Tail are initialized so that the MSI-EQ is 'empty'.
2070 *
2071 * Implementation Note: Certain implementations have fixed sized queues. In
2072 * that case, number of entries must contain the correct
2073 * value.
2074 */
2075#define HV_FAST_PCI_MSIQ_CONF 0xc0
2076
2077/* pci_msiq_info()
2078 * TRAP: HV_FAST_TRAP
2079 * FUNCTION: HV_FAST_PCI_MSIQ_INFO
2080 * ARG0: devhandle
2081 * ARG1: msiqid
2082 * RET0: status
2083 * RET1: real address
2084 * RET2: number of entries
2085 * ERRORS: EINVAL Invalid devhandle or msiqid
2086 *
2087 * Return the configuration information for the MSI queue described
2088 * by the given devhandle and msiqid. The base address of the queue
2089 * is returned in ARG1 and the number of entries is returned in ARG2.
2090 * If the queue is unconfigured, the real address is undefined and the
2091 * number of entries will be returned as zero.
2092 */
2093#define HV_FAST_PCI_MSIQ_INFO 0xc1
2094
2095/* pci_msiq_getvalid()
2096 * TRAP: HV_FAST_TRAP
2097 * FUNCTION: HV_FAST_PCI_MSIQ_GETVALID
2098 * ARG0: devhandle
2099 * ARG1: msiqid
2100 * RET0: status
2101 * RET1: msiqvalid (HV_MSIQ_VALID or HV_MSIQ_INVALID)
2102 * ERRORS: EINVAL Invalid devhandle or msiqid
2103 *
2104 * Get the valid state of the MSI-EQ described by the given devhandle and
2105 * msiqid.
2106 */
2107#define HV_FAST_PCI_MSIQ_GETVALID 0xc2
2108
2109/* pci_msiq_setvalid()
2110 * TRAP: HV_FAST_TRAP
2111 * FUNCTION: HV_FAST_PCI_MSIQ_SETVALID
2112 * ARG0: devhandle
2113 * ARG1: msiqid
2114 * ARG2: msiqvalid (HV_MSIQ_VALID or HV_MSIQ_INVALID)
2115 * RET0: status
2116 * ERRORS: EINVAL Invalid devhandle or msiqid or msiqvalid
2117 * value or MSI EQ is uninitialized
2118 *
2119 * Set the valid state of the MSI-EQ described by the given devhandle and
2120 * msiqid to the given msiqvalid.
2121 */
2122#define HV_FAST_PCI_MSIQ_SETVALID 0xc3
2123
2124/* pci_msiq_getstate()
2125 * TRAP: HV_FAST_TRAP
2126 * FUNCTION: HV_FAST_PCI_MSIQ_GETSTATE
2127 * ARG0: devhandle
2128 * ARG1: msiqid
2129 * RET0: status
2130 * RET1: msiqstate (HV_MSIQSTATE_IDLE or HV_MSIQSTATE_ERROR)
2131 * ERRORS: EINVAL Invalid devhandle or msiqid
2132 *
2133 * Get the state of the MSI-EQ described by the given devhandle and
2134 * msiqid.
2135 */
2136#define HV_FAST_PCI_MSIQ_GETSTATE 0xc4
2137
2138/* pci_msiq_getvalid()
2139 * TRAP: HV_FAST_TRAP
2140 * FUNCTION: HV_FAST_PCI_MSIQ_GETVALID
2141 * ARG0: devhandle
2142 * ARG1: msiqid
2143 * ARG2: msiqstate (HV_MSIQSTATE_IDLE or HV_MSIQSTATE_ERROR)
2144 * RET0: status
2145 * ERRORS: EINVAL Invalid devhandle or msiqid or msiqstate
2146 * value or MSI EQ is uninitialized
2147 *
2148 * Set the state of the MSI-EQ described by the given devhandle and
2149 * msiqid to the given msiqvalid.
2150 */
2151#define HV_FAST_PCI_MSIQ_SETSTATE 0xc5
2152
2153/* pci_msiq_gethead()
2154 * TRAP: HV_FAST_TRAP
2155 * FUNCTION: HV_FAST_PCI_MSIQ_GETHEAD
2156 * ARG0: devhandle
2157 * ARG1: msiqid
2158 * RET0: status
2159 * RET1: msiqhead
2160 * ERRORS: EINVAL Invalid devhandle or msiqid
2161 *
2162 * Get the current MSI EQ queue head for the MSI-EQ described by the
2163 * given devhandle and msiqid.
2164 */
2165#define HV_FAST_PCI_MSIQ_GETHEAD 0xc6
2166
2167/* pci_msiq_sethead()
2168 * TRAP: HV_FAST_TRAP
2169 * FUNCTION: HV_FAST_PCI_MSIQ_SETHEAD
2170 * ARG0: devhandle
2171 * ARG1: msiqid
2172 * ARG2: msiqhead
2173 * RET0: status
2174 * ERRORS: EINVAL Invalid devhandle or msiqid or msiqhead,
2175 * or MSI EQ is uninitialized
2176 *
2177 * Set the current MSI EQ queue head for the MSI-EQ described by the
2178 * given devhandle and msiqid.
2179 */
2180#define HV_FAST_PCI_MSIQ_SETHEAD 0xc7
2181
2182/* pci_msiq_gettail()
2183 * TRAP: HV_FAST_TRAP
2184 * FUNCTION: HV_FAST_PCI_MSIQ_GETTAIL
2185 * ARG0: devhandle
2186 * ARG1: msiqid
2187 * RET0: status
2188 * RET1: msiqtail
2189 * ERRORS: EINVAL Invalid devhandle or msiqid
2190 *
2191 * Get the current MSI EQ queue tail for the MSI-EQ described by the
2192 * given devhandle and msiqid.
2193 */
2194#define HV_FAST_PCI_MSIQ_GETTAIL 0xc8
2195
2196/* pci_msi_getvalid()
2197 * TRAP: HV_FAST_TRAP
2198 * FUNCTION: HV_FAST_PCI_MSI_GETVALID
2199 * ARG0: devhandle
2200 * ARG1: msinum
2201 * RET0: status
2202 * RET1: msivalidstate
2203 * ERRORS: EINVAL Invalid devhandle or msinum
2204 *
2205 * Get the current valid/enabled state for the MSI defined by the
2206 * given devhandle and msinum.
2207 */
2208#define HV_FAST_PCI_MSI_GETVALID 0xc9
2209
2210/* pci_msi_setvalid()
2211 * TRAP: HV_FAST_TRAP
2212 * FUNCTION: HV_FAST_PCI_MSI_SETVALID
2213 * ARG0: devhandle
2214 * ARG1: msinum
2215 * ARG2: msivalidstate
2216 * RET0: status
2217 * ERRORS: EINVAL Invalid devhandle or msinum or msivalidstate
2218 *
2219 * Set the current valid/enabled state for the MSI defined by the
2220 * given devhandle and msinum.
2221 */
2222#define HV_FAST_PCI_MSI_SETVALID 0xca
2223
2224/* pci_msi_getmsiq()
2225 * TRAP: HV_FAST_TRAP
2226 * FUNCTION: HV_FAST_PCI_MSI_GETMSIQ
2227 * ARG0: devhandle
2228 * ARG1: msinum
2229 * RET0: status
2230 * RET1: msiqid
2231 * ERRORS: EINVAL Invalid devhandle or msinum or MSI is unbound
2232 *
2233 * Get the MSI EQ that the MSI defined by the given devhandle and
2234 * msinum is bound to.
2235 */
2236#define HV_FAST_PCI_MSI_GETMSIQ 0xcb
2237
2238/* pci_msi_setmsiq()
2239 * TRAP: HV_FAST_TRAP
2240 * FUNCTION: HV_FAST_PCI_MSI_SETMSIQ
2241 * ARG0: devhandle
2242 * ARG1: msinum
2243 * ARG2: msitype
2244 * ARG3: msiqid
2245 * RET0: status
2246 * ERRORS: EINVAL Invalid devhandle or msinum or msiqid
2247 *
2248 * Set the MSI EQ that the MSI defined by the given devhandle and
2249 * msinum is bound to.
2250 */
2251#define HV_FAST_PCI_MSI_SETMSIQ 0xcc
2252
2253/* pci_msi_getstate()
2254 * TRAP: HV_FAST_TRAP
2255 * FUNCTION: HV_FAST_PCI_MSI_GETSTATE
2256 * ARG0: devhandle
2257 * ARG1: msinum
2258 * RET0: status
2259 * RET1: msistate
2260 * ERRORS: EINVAL Invalid devhandle or msinum
2261 *
2262 * Get the state of the MSI defined by the given devhandle and msinum.
2263 * If not initialized, return HV_MSISTATE_IDLE.
2264 */
2265#define HV_FAST_PCI_MSI_GETSTATE 0xcd
2266
2267/* pci_msi_setstate()
2268 * TRAP: HV_FAST_TRAP
2269 * FUNCTION: HV_FAST_PCI_MSI_SETSTATE
2270 * ARG0: devhandle
2271 * ARG1: msinum
2272 * ARG2: msistate
2273 * RET0: status
2274 * ERRORS: EINVAL Invalid devhandle or msinum or msistate
2275 *
2276 * Set the state of the MSI defined by the given devhandle and msinum.
2277 */
2278#define HV_FAST_PCI_MSI_SETSTATE 0xce
2279
2280/* pci_msg_getmsiq()
2281 * TRAP: HV_FAST_TRAP
2282 * FUNCTION: HV_FAST_PCI_MSG_GETMSIQ
2283 * ARG0: devhandle
2284 * ARG1: msgtype
2285 * RET0: status
2286 * RET1: msiqid
2287 * ERRORS: EINVAL Invalid devhandle or msgtype
2288 *
2289 * Get the MSI EQ of the MSG defined by the given devhandle and msgtype.
2290 */
2291#define HV_FAST_PCI_MSG_GETMSIQ 0xd0
2292
2293/* pci_msg_setmsiq()
2294 * TRAP: HV_FAST_TRAP
2295 * FUNCTION: HV_FAST_PCI_MSG_SETMSIQ
2296 * ARG0: devhandle
2297 * ARG1: msgtype
2298 * ARG2: msiqid
2299 * RET0: status
2300 * ERRORS: EINVAL Invalid devhandle, msgtype, or msiqid
2301 *
2302 * Set the MSI EQ of the MSG defined by the given devhandle and msgtype.
2303 */
2304#define HV_FAST_PCI_MSG_SETMSIQ 0xd1
2305
2306/* pci_msg_getvalid()
2307 * TRAP: HV_FAST_TRAP
2308 * FUNCTION: HV_FAST_PCI_MSG_GETVALID
2309 * ARG0: devhandle
2310 * ARG1: msgtype
2311 * RET0: status
2312 * RET1: msgvalidstate
2313 * ERRORS: EINVAL Invalid devhandle or msgtype
2314 *
2315 * Get the valid/enabled state of the MSG defined by the given
2316 * devhandle and msgtype.
2317 */
2318#define HV_FAST_PCI_MSG_GETVALID 0xd2
2319
2320/* pci_msg_setvalid()
2321 * TRAP: HV_FAST_TRAP
2322 * FUNCTION: HV_FAST_PCI_MSG_SETVALID
2323 * ARG0: devhandle
2324 * ARG1: msgtype
2325 * ARG2: msgvalidstate
2326 * RET0: status
2327 * ERRORS: EINVAL Invalid devhandle or msgtype or msgvalidstate
2328 *
2329 * Set the valid/enabled state of the MSG defined by the given
2330 * devhandle and msgtype.
2331 */
2332#define HV_FAST_PCI_MSG_SETVALID 0xd3
2333
2334/* Logical Domain Channel services. */
2335
2336#define LDC_CHANNEL_DOWN 0
2337#define LDC_CHANNEL_UP 1
2338#define LDC_CHANNEL_RESETTING 2
2339
2340/* ldc_tx_qconf()
2341 * TRAP: HV_FAST_TRAP
2342 * FUNCTION: HV_FAST_LDC_TX_QCONF
2343 * ARG0: channel ID
2344 * ARG1: real address base of queue
2345 * ARG2: num entries in queue
2346 * RET0: status
2347 *
2348 * Configure transmit queue for the LDC endpoint specified by the
2349 * given channel ID, to be placed at the given real address, and
2350 * be of the given num entries. Num entries must be a power of two.
2351 * The real address base of the queue must be aligned on the queue
2352 * size. Each queue entry is 64-bytes, so for example, a 32 entry
2353 * queue must be aligned on a 2048 byte real address boundary.
2354 *
2355 * Upon configuration of a valid transmit queue the head and tail
2356 * pointers are set to a hypervisor specific identical value indicating
2357 * that the queue initially is empty.
2358 *
2359 * The endpoint's transmit queue is un-configured if num entries is zero.
2360 *
2361 * The maximum number of entries for each queue for a specific cpu may be
2362 * determined from the machine description. A transmit queue may be
2363 * specified even in the event that the LDC is down (peer endpoint has no
2364 * receive queue specified). Transmission will begin as soon as the peer
2365 * endpoint defines a receive queue.
2366 *
2367 * It is recommended that a guest wait for a transmit queue to empty prior
2368 * to reconfiguring it, or un-configuring it. Re or un-configuring of a
2369 * non-empty transmit queue behaves exactly as defined above, however it
2370 * is undefined as to how many of the pending entries in the original queue
2371 * will be delivered prior to the re-configuration taking effect.
2372 * Furthermore, as the queue configuration causes a reset of the head and
2373 * tail pointers there is no way for a guest to determine how many entries
2374 * have been sent after the configuration operation.
2375 */
2376#define HV_FAST_LDC_TX_QCONF 0xe0
2377
2378/* ldc_tx_qinfo()
2379 * TRAP: HV_FAST_TRAP
2380 * FUNCTION: HV_FAST_LDC_TX_QINFO
2381 * ARG0: channel ID
2382 * RET0: status
2383 * RET1: real address base of queue
2384 * RET2: num entries in queue
2385 *
2386 * Return the configuration info for the transmit queue of LDC endpoint
2387 * defined by the given channel ID. The real address is the currently
2388 * defined real address base of the defined queue, and num entries is the
2389 * size of the queue in terms of number of entries.
2390 *
2391 * If the specified channel ID is a valid endpoint number, but no transmit
2392 * queue has been defined this service will return success, but with num
2393 * entries set to zero and the real address will have an undefined value.
2394 */
2395#define HV_FAST_LDC_TX_QINFO 0xe1
2396
2397/* ldc_tx_get_state()
2398 * TRAP: HV_FAST_TRAP
2399 * FUNCTION: HV_FAST_LDC_TX_GET_STATE
2400 * ARG0: channel ID
2401 * RET0: status
2402 * RET1: head offset
2403 * RET2: tail offset
2404 * RET3: channel state
2405 *
2406 * Return the transmit state, and the head and tail queue pointers, for
2407 * the transmit queue of the LDC endpoint defined by the given channel ID.
2408 * The head and tail values are the byte offset of the head and tail
2409 * positions of the transmit queue for the specified endpoint.
2410 */
2411#define HV_FAST_LDC_TX_GET_STATE 0xe2
2412
2413/* ldc_tx_set_qtail()
2414 * TRAP: HV_FAST_TRAP
2415 * FUNCTION: HV_FAST_LDC_TX_SET_QTAIL
2416 * ARG0: channel ID
2417 * ARG1: tail offset
2418 * RET0: status
2419 *
2420 * Update the tail pointer for the transmit queue associated with the LDC
2421 * endpoint defined by the given channel ID. The tail offset specified
2422 * must be aligned on a 64 byte boundary, and calculated so as to increase
2423 * the number of pending entries on the transmit queue. Any attempt to
2424 * decrease the number of pending transmit queue entires is considered
2425 * an invalid tail offset and will result in an EINVAL error.
2426 *
2427 * Since the tail of the transmit queue may not be moved backwards, the
2428 * transmit queue may be flushed by configuring a new transmit queue,
2429 * whereupon the hypervisor will configure the initial transmit head and
2430 * tail pointers to be equal.
2431 */
2432#define HV_FAST_LDC_TX_SET_QTAIL 0xe3
2433
2434/* ldc_rx_qconf()
2435 * TRAP: HV_FAST_TRAP
2436 * FUNCTION: HV_FAST_LDC_RX_QCONF
2437 * ARG0: channel ID
2438 * ARG1: real address base of queue
2439 * ARG2: num entries in queue
2440 * RET0: status
2441 *
2442 * Configure receive queue for the LDC endpoint specified by the
2443 * given channel ID, to be placed at the given real address, and
2444 * be of the given num entries. Num entries must be a power of two.
2445 * The real address base of the queue must be aligned on the queue
2446 * size. Each queue entry is 64-bytes, so for example, a 32 entry
2447 * queue must be aligned on a 2048 byte real address boundary.
2448 *
2449 * The endpoint's transmit queue is un-configured if num entries is zero.
2450 *
2451 * If a valid receive queue is specified for a local endpoint the LDC is
2452 * in the up state for the purpose of transmission to this endpoint.
2453 *
2454 * The maximum number of entries for each queue for a specific cpu may be
2455 * determined from the machine description.
2456 *
2457 * As receive queue configuration causes a reset of the queue's head and
2458 * tail pointers there is no way for a gues to determine how many entries
2459 * have been received between a preceeding ldc_get_rx_state() API call
2460 * and the completion of the configuration operation. It should be noted
2461 * that datagram delivery is not guarenteed via domain channels anyway,
2462 * and therefore any higher protocol should be resilient to datagram
2463 * loss if necessary. However, to overcome this specific race potential
2464 * it is recommended, for example, that a higher level protocol be employed
2465 * to ensure either retransmission, or ensure that no datagrams are pending
2466 * on the peer endpoint's transmit queue prior to the configuration process.
2467 */
2468#define HV_FAST_LDC_RX_QCONF 0xe4
2469
2470/* ldc_rx_qinfo()
2471 * TRAP: HV_FAST_TRAP
2472 * FUNCTION: HV_FAST_LDC_RX_QINFO
2473 * ARG0: channel ID
2474 * RET0: status
2475 * RET1: real address base of queue
2476 * RET2: num entries in queue
2477 *
2478 * Return the configuration info for the receive queue of LDC endpoint
2479 * defined by the given channel ID. The real address is the currently
2480 * defined real address base of the defined queue, and num entries is the
2481 * size of the queue in terms of number of entries.
2482 *
2483 * If the specified channel ID is a valid endpoint number, but no receive
2484 * queue has been defined this service will return success, but with num
2485 * entries set to zero and the real address will have an undefined value.
2486 */
2487#define HV_FAST_LDC_RX_QINFO 0xe5
2488
2489/* ldc_rx_get_state()
2490 * TRAP: HV_FAST_TRAP
2491 * FUNCTION: HV_FAST_LDC_RX_GET_STATE
2492 * ARG0: channel ID
2493 * RET0: status
2494 * RET1: head offset
2495 * RET2: tail offset
2496 * RET3: channel state
2497 *
2498 * Return the receive state, and the head and tail queue pointers, for
2499 * the receive queue of the LDC endpoint defined by the given channel ID.
2500 * The head and tail values are the byte offset of the head and tail
2501 * positions of the receive queue for the specified endpoint.
2502 */
2503#define HV_FAST_LDC_RX_GET_STATE 0xe6
2504
2505/* ldc_rx_set_qhead()
2506 * TRAP: HV_FAST_TRAP
2507 * FUNCTION: HV_FAST_LDC_RX_SET_QHEAD
2508 * ARG0: channel ID
2509 * ARG1: head offset
2510 * RET0: status
2511 *
2512 * Update the head pointer for the receive queue associated with the LDC
2513 * endpoint defined by the given channel ID. The head offset specified
2514 * must be aligned on a 64 byte boundary, and calculated so as to decrease
2515 * the number of pending entries on the receive queue. Any attempt to
2516 * increase the number of pending receive queue entires is considered
2517 * an invalid head offset and will result in an EINVAL error.
2518 *
2519 * The receive queue may be flushed by setting the head offset equal
2520 * to the current tail offset.
2521 */
2522#define HV_FAST_LDC_RX_SET_QHEAD 0xe7
2523
2524/* LDC Map Table Entry. Each slot is defined by a translation table
2525 * entry, as specified by the LDC_MTE_* bits below, and a 64-bit
2526 * hypervisor invalidation cookie.
2527 */
2528#define LDC_MTE_PADDR 0x0fffffffffffe000 /* pa[55:13] */
2529#define LDC_MTE_COPY_W 0x0000000000000400 /* copy write access */
2530#define LDC_MTE_COPY_R 0x0000000000000200 /* copy read access */
2531#define LDC_MTE_IOMMU_W 0x0000000000000100 /* IOMMU write access */
2532#define LDC_MTE_IOMMU_R 0x0000000000000080 /* IOMMU read access */
2533#define LDC_MTE_EXEC 0x0000000000000040 /* execute */
2534#define LDC_MTE_WRITE 0x0000000000000020 /* read */
2535#define LDC_MTE_READ 0x0000000000000010 /* write */
2536#define LDC_MTE_SZALL 0x000000000000000f /* page size bits */
2537#define LDC_MTE_SZ16GB 0x0000000000000007 /* 16GB page */
2538#define LDC_MTE_SZ2GB 0x0000000000000006 /* 2GB page */
2539#define LDC_MTE_SZ256MB 0x0000000000000005 /* 256MB page */
2540#define LDC_MTE_SZ32MB 0x0000000000000004 /* 32MB page */
2541#define LDC_MTE_SZ4MB 0x0000000000000003 /* 4MB page */
2542#define LDC_MTE_SZ512K 0x0000000000000002 /* 512K page */
2543#define LDC_MTE_SZ64K 0x0000000000000001 /* 64K page */
2544#define LDC_MTE_SZ8K 0x0000000000000000 /* 8K page */
2545
2546#ifndef __ASSEMBLY__
2547struct ldc_mtable_entry {
2548 unsigned long mte;
2549 unsigned long cookie;
2550};
2551#endif
2552
2553/* ldc_set_map_table()
2554 * TRAP: HV_FAST_TRAP
2555 * FUNCTION: HV_FAST_LDC_SET_MAP_TABLE
2556 * ARG0: channel ID
2557 * ARG1: table real address
2558 * ARG2: num entries
2559 * RET0: status
2560 *
2561 * Register the MTE table at the given table real address, with the
2562 * specified num entries, for the LDC indicated by the given channel
2563 * ID.
2564 */
2565#define HV_FAST_LDC_SET_MAP_TABLE 0xea
2566
2567/* ldc_get_map_table()
2568 * TRAP: HV_FAST_TRAP
2569 * FUNCTION: HV_FAST_LDC_GET_MAP_TABLE
2570 * ARG0: channel ID
2571 * RET0: status
2572 * RET1: table real address
2573 * RET2: num entries
2574 *
2575 * Return the configuration of the current mapping table registered
2576 * for the given channel ID.
2577 */
2578#define HV_FAST_LDC_GET_MAP_TABLE 0xeb
2579
2580#define LDC_COPY_IN 0
2581#define LDC_COPY_OUT 1
2582
2583/* ldc_copy()
2584 * TRAP: HV_FAST_TRAP
2585 * FUNCTION: HV_FAST_LDC_COPY
2586 * ARG0: channel ID
2587 * ARG1: LDC_COPY_* direction code
2588 * ARG2: target real address
2589 * ARG3: local real address
2590 * ARG4: length in bytes
2591 * RET0: status
2592 * RET1: actual length in bytes
2593 */
2594#define HV_FAST_LDC_COPY 0xec
2595
2596#define LDC_MEM_READ 1
2597#define LDC_MEM_WRITE 2
2598#define LDC_MEM_EXEC 4
2599
2600/* ldc_mapin()
2601 * TRAP: HV_FAST_TRAP
2602 * FUNCTION: HV_FAST_LDC_MAPIN
2603 * ARG0: channel ID
2604 * ARG1: cookie
2605 * RET0: status
2606 * RET1: real address
2607 * RET2: LDC_MEM_* permissions
2608 */
2609#define HV_FAST_LDC_MAPIN 0xed
2610
2611/* ldc_unmap()
2612 * TRAP: HV_FAST_TRAP
2613 * FUNCTION: HV_FAST_LDC_UNMAP
2614 * ARG0: real address
2615 * RET0: status
2616 */
2617#define HV_FAST_LDC_UNMAP 0xee
2618
2619/* ldc_revoke()
2620 * TRAP: HV_FAST_TRAP
2621 * FUNCTION: HV_FAST_LDC_REVOKE
2622 * ARG0: channel ID
2623 * ARG1: cookie
2624 * ARG2: ldc_mtable_entry cookie
2625 * RET0: status
2626 */
2627#define HV_FAST_LDC_REVOKE 0xef
2628
2629#ifndef __ASSEMBLY__
2630extern unsigned long sun4v_ldc_tx_qconf(unsigned long channel,
2631 unsigned long ra,
2632 unsigned long num_entries);
2633extern unsigned long sun4v_ldc_tx_qinfo(unsigned long channel,
2634 unsigned long *ra,
2635 unsigned long *num_entries);
2636extern unsigned long sun4v_ldc_tx_get_state(unsigned long channel,
2637 unsigned long *head_off,
2638 unsigned long *tail_off,
2639 unsigned long *chan_state);
2640extern unsigned long sun4v_ldc_tx_set_qtail(unsigned long channel,
2641 unsigned long tail_off);
2642extern unsigned long sun4v_ldc_rx_qconf(unsigned long channel,
2643 unsigned long ra,
2644 unsigned long num_entries);
2645extern unsigned long sun4v_ldc_rx_qinfo(unsigned long channel,
2646 unsigned long *ra,
2647 unsigned long *num_entries);
2648extern unsigned long sun4v_ldc_rx_get_state(unsigned long channel,
2649 unsigned long *head_off,
2650 unsigned long *tail_off,
2651 unsigned long *chan_state);
2652extern unsigned long sun4v_ldc_rx_set_qhead(unsigned long channel,
2653 unsigned long head_off);
2654extern unsigned long sun4v_ldc_set_map_table(unsigned long channel,
2655 unsigned long ra,
2656 unsigned long num_entries);
2657extern unsigned long sun4v_ldc_get_map_table(unsigned long channel,
2658 unsigned long *ra,
2659 unsigned long *num_entries);
2660extern unsigned long sun4v_ldc_copy(unsigned long channel,
2661 unsigned long dir_code,
2662 unsigned long tgt_raddr,
2663 unsigned long lcl_raddr,
2664 unsigned long len,
2665 unsigned long *actual_len);
2666extern unsigned long sun4v_ldc_mapin(unsigned long channel,
2667 unsigned long cookie,
2668 unsigned long *ra,
2669 unsigned long *perm);
2670extern unsigned long sun4v_ldc_unmap(unsigned long ra);
2671extern unsigned long sun4v_ldc_revoke(unsigned long channel,
2672 unsigned long cookie,
2673 unsigned long mte_cookie);
2674#endif
2675
2676/* Performance counter services. */
2677
2678#define HV_PERF_JBUS_PERF_CTRL_REG 0x00
2679#define HV_PERF_JBUS_PERF_CNT_REG 0x01
2680#define HV_PERF_DRAM_PERF_CTRL_REG_0 0x02
2681#define HV_PERF_DRAM_PERF_CNT_REG_0 0x03
2682#define HV_PERF_DRAM_PERF_CTRL_REG_1 0x04
2683#define HV_PERF_DRAM_PERF_CNT_REG_1 0x05
2684#define HV_PERF_DRAM_PERF_CTRL_REG_2 0x06
2685#define HV_PERF_DRAM_PERF_CNT_REG_2 0x07
2686#define HV_PERF_DRAM_PERF_CTRL_REG_3 0x08
2687#define HV_PERF_DRAM_PERF_CNT_REG_3 0x09
2688
2689/* get_perfreg()
2690 * TRAP: HV_FAST_TRAP
2691 * FUNCTION: HV_FAST_GET_PERFREG
2692 * ARG0: performance reg number
2693 * RET0: status
2694 * RET1: performance reg value
2695 * ERRORS: EINVAL Invalid performance register number
2696 * ENOACCESS No access allowed to performance counters
2697 *
2698 * Read the value of the given DRAM/JBUS performance counter/control register.
2699 */
2700#define HV_FAST_GET_PERFREG 0x100
2701
2702/* set_perfreg()
2703 * TRAP: HV_FAST_TRAP
2704 * FUNCTION: HV_FAST_SET_PERFREG
2705 * ARG0: performance reg number
2706 * ARG1: performance reg value
2707 * RET0: status
2708 * ERRORS: EINVAL Invalid performance register number
2709 * ENOACCESS No access allowed to performance counters
2710 *
2711 * Write the given performance reg value to the given DRAM/JBUS
2712 * performance counter/control register.
2713 */
2714#define HV_FAST_SET_PERFREG 0x101
2715
2716/* MMU statistics services.
2717 *
2718 * The hypervisor maintains MMU statistics and privileged code provides
2719 * a buffer where these statistics can be collected. It is continually
2720 * updated once configured. The layout is as follows:
2721 */
2722#ifndef __ASSEMBLY__
2723struct hv_mmu_statistics {
2724 unsigned long immu_tsb_hits_ctx0_8k_tte;
2725 unsigned long immu_tsb_ticks_ctx0_8k_tte;
2726 unsigned long immu_tsb_hits_ctx0_64k_tte;
2727 unsigned long immu_tsb_ticks_ctx0_64k_tte;
2728 unsigned long __reserved1[2];
2729 unsigned long immu_tsb_hits_ctx0_4mb_tte;
2730 unsigned long immu_tsb_ticks_ctx0_4mb_tte;
2731 unsigned long __reserved2[2];
2732 unsigned long immu_tsb_hits_ctx0_256mb_tte;
2733 unsigned long immu_tsb_ticks_ctx0_256mb_tte;
2734 unsigned long __reserved3[4];
2735 unsigned long immu_tsb_hits_ctxnon0_8k_tte;
2736 unsigned long immu_tsb_ticks_ctxnon0_8k_tte;
2737 unsigned long immu_tsb_hits_ctxnon0_64k_tte;
2738 unsigned long immu_tsb_ticks_ctxnon0_64k_tte;
2739 unsigned long __reserved4[2];
2740 unsigned long immu_tsb_hits_ctxnon0_4mb_tte;
2741 unsigned long immu_tsb_ticks_ctxnon0_4mb_tte;
2742 unsigned long __reserved5[2];
2743 unsigned long immu_tsb_hits_ctxnon0_256mb_tte;
2744 unsigned long immu_tsb_ticks_ctxnon0_256mb_tte;
2745 unsigned long __reserved6[4];
2746 unsigned long dmmu_tsb_hits_ctx0_8k_tte;
2747 unsigned long dmmu_tsb_ticks_ctx0_8k_tte;
2748 unsigned long dmmu_tsb_hits_ctx0_64k_tte;
2749 unsigned long dmmu_tsb_ticks_ctx0_64k_tte;
2750 unsigned long __reserved7[2];
2751 unsigned long dmmu_tsb_hits_ctx0_4mb_tte;
2752 unsigned long dmmu_tsb_ticks_ctx0_4mb_tte;
2753 unsigned long __reserved8[2];
2754 unsigned long dmmu_tsb_hits_ctx0_256mb_tte;
2755 unsigned long dmmu_tsb_ticks_ctx0_256mb_tte;
2756 unsigned long __reserved9[4];
2757 unsigned long dmmu_tsb_hits_ctxnon0_8k_tte;
2758 unsigned long dmmu_tsb_ticks_ctxnon0_8k_tte;
2759 unsigned long dmmu_tsb_hits_ctxnon0_64k_tte;
2760 unsigned long dmmu_tsb_ticks_ctxnon0_64k_tte;
2761 unsigned long __reserved10[2];
2762 unsigned long dmmu_tsb_hits_ctxnon0_4mb_tte;
2763 unsigned long dmmu_tsb_ticks_ctxnon0_4mb_tte;
2764 unsigned long __reserved11[2];
2765 unsigned long dmmu_tsb_hits_ctxnon0_256mb_tte;
2766 unsigned long dmmu_tsb_ticks_ctxnon0_256mb_tte;
2767 unsigned long __reserved12[4];
2768};
2769#endif
2770
2771/* mmustat_conf()
2772 * TRAP: HV_FAST_TRAP
2773 * FUNCTION: HV_FAST_MMUSTAT_CONF
2774 * ARG0: real address
2775 * RET0: status
2776 * RET1: real address
2777 * ERRORS: ENORADDR Invalid real address
2778 * EBADALIGN Real address not aligned on 64-byte boundary
2779 * EBADTRAP API not supported on this processor
2780 *
2781 * Enable MMU statistic gathering using the buffer at the given real
2782 * address on the current virtual CPU. The new buffer real address
2783 * is given in ARG1, and the previously specified buffer real address
2784 * is returned in RET1, or is returned as zero for the first invocation.
2785 *
2786 * If the passed in real address argument is zero, this will disable
2787 * MMU statistic collection on the current virtual CPU. If an error is
2788 * returned then no statistics are collected.
2789 *
2790 * The buffer contents should be initialized to all zeros before being
2791 * given to the hypervisor or else the statistics will be meaningless.
2792 */
2793#define HV_FAST_MMUSTAT_CONF 0x102
2794
2795/* mmustat_info()
2796 * TRAP: HV_FAST_TRAP
2797 * FUNCTION: HV_FAST_MMUSTAT_INFO
2798 * RET0: status
2799 * RET1: real address
2800 * ERRORS: EBADTRAP API not supported on this processor
2801 *
2802 * Return the current state and real address of the currently configured
2803 * MMU statistics buffer on the current virtual CPU.
2804 */
2805#define HV_FAST_MMUSTAT_INFO 0x103
2806
2807#ifndef __ASSEMBLY__
2808extern unsigned long sun4v_mmustat_conf(unsigned long ra, unsigned long *orig_ra);
2809extern unsigned long sun4v_mmustat_info(unsigned long *ra);
2810#endif
2811
2812/* NCS crypto services */
2813
2814/* ncs_request() sub-function numbers */
2815#define HV_NCS_QCONF 0x01
2816#define HV_NCS_QTAIL_UPDATE 0x02
2817
2818#ifndef __ASSEMBLY__
2819struct hv_ncs_queue_entry {
2820 /* MAU Control Register */
2821 unsigned long mau_control;
2822#define MAU_CONTROL_INV_PARITY 0x0000000000002000
2823#define MAU_CONTROL_STRAND 0x0000000000001800
2824#define MAU_CONTROL_BUSY 0x0000000000000400
2825#define MAU_CONTROL_INT 0x0000000000000200
2826#define MAU_CONTROL_OP 0x00000000000001c0
2827#define MAU_CONTROL_OP_SHIFT 6
2828#define MAU_OP_LOAD_MA_MEMORY 0x0
2829#define MAU_OP_STORE_MA_MEMORY 0x1
2830#define MAU_OP_MODULAR_MULT 0x2
2831#define MAU_OP_MODULAR_REDUCE 0x3
2832#define MAU_OP_MODULAR_EXP_LOOP 0x4
2833#define MAU_CONTROL_LEN 0x000000000000003f
2834#define MAU_CONTROL_LEN_SHIFT 0
2835
2836 /* Real address of bytes to load or store bytes
2837 * into/out-of the MAU.
2838 */
2839 unsigned long mau_mpa;
2840
2841 /* Modular Arithmetic MA Offset Register. */
2842 unsigned long mau_ma;
2843
2844 /* Modular Arithmetic N Prime Register. */
2845 unsigned long mau_np;
2846};
2847
2848struct hv_ncs_qconf_arg {
2849 unsigned long mid; /* MAU ID, 1 per core on Niagara */
2850 unsigned long base; /* Real address base of queue */
2851 unsigned long end; /* Real address end of queue */
2852 unsigned long num_ents; /* Number of entries in queue */
2853};
2854
2855struct hv_ncs_qtail_update_arg {
2856 unsigned long mid; /* MAU ID, 1 per core on Niagara */
2857 unsigned long tail; /* New tail index to use */
2858 unsigned long syncflag; /* only SYNCFLAG_SYNC is implemented */
2859#define HV_NCS_SYNCFLAG_SYNC 0x00
2860#define HV_NCS_SYNCFLAG_ASYNC 0x01
2861};
2862#endif
2863
2864/* ncs_request()
2865 * TRAP: HV_FAST_TRAP
2866 * FUNCTION: HV_FAST_NCS_REQUEST
2867 * ARG0: NCS sub-function
2868 * ARG1: sub-function argument real address
2869 * ARG2: size in bytes of sub-function argument
2870 * RET0: status
2871 *
2872 * The MAU chip of the Niagara processor is not directly accessible
2873 * to privileged code, instead it is programmed indirectly via this
2874 * hypervisor API.
2875 *
2876 * The interfaces defines a queue of MAU operations to perform.
2877 * Privileged code registers a queue with the hypervisor by invoking
2878 * this HVAPI with the HV_NCS_QCONF sub-function, which defines the
2879 * base, end, and number of entries of the queue. Each queue entry
2880 * contains a MAU register struct block.
2881 *
2882 * The privileged code then proceeds to add entries to the queue and
2883 * then invoke the HV_NCS_QTAIL_UPDATE sub-function. Since only
2884 * synchronous operations are supported by the current hypervisor,
2885 * HV_NCS_QTAIL_UPDATE will run all the pending queue entries to
2886 * completion and return HV_EOK, or return an error code.
2887 *
2888 * The real address of the sub-function argument must be aligned on at
2889 * least an 8-byte boundary.
2890 *
2891 * The tail argument of HV_NCS_QTAIL_UPDATE is an index, not a byte
2892 * offset, into the queue and must be less than or equal the 'num_ents'
2893 * argument given in the HV_NCS_QCONF call.
2894 */
2895#define HV_FAST_NCS_REQUEST 0x110
2896
2897#ifndef __ASSEMBLY__
2898extern unsigned long sun4v_ncs_request(unsigned long request,
2899 unsigned long arg_ra,
2900 unsigned long arg_size);
2901#endif
2902
2903#define HV_FAST_FIRE_GET_PERFREG 0x120
2904#define HV_FAST_FIRE_SET_PERFREG 0x121
2905
2906/* Function numbers for HV_CORE_TRAP. */
2907#define HV_CORE_SET_VER 0x00
2908#define HV_CORE_PUTCHAR 0x01
2909#define HV_CORE_EXIT 0x02
2910#define HV_CORE_GET_VER 0x03
2911
2912/* Hypervisor API groups for use with HV_CORE_SET_VER and
2913 * HV_CORE_GET_VER.
2914 */
2915#define HV_GRP_SUN4V 0x0000
2916#define HV_GRP_CORE 0x0001
2917#define HV_GRP_INTR 0x0002
2918#define HV_GRP_SOFT_STATE 0x0003
2919#define HV_GRP_PCI 0x0100
2920#define HV_GRP_LDOM 0x0101
2921#define HV_GRP_SVC_CHAN 0x0102
2922#define HV_GRP_NCS 0x0103
2923#define HV_GRP_RNG 0x0104
2924#define HV_GRP_NIAG_PERF 0x0200
2925#define HV_GRP_FIRE_PERF 0x0201
2926#define HV_GRP_N2_CPU 0x0202
2927#define HV_GRP_NIU 0x0204
2928#define HV_GRP_VF_CPU 0x0205
2929#define HV_GRP_DIAG 0x0300
2930
2931#ifndef __ASSEMBLY__
2932extern unsigned long sun4v_get_version(unsigned long group,
2933 unsigned long *major,
2934 unsigned long *minor);
2935extern unsigned long sun4v_set_version(unsigned long group,
2936 unsigned long major,
2937 unsigned long minor,
2938 unsigned long *actual_minor);
2939
2940extern int sun4v_hvapi_register(unsigned long group, unsigned long major,
2941 unsigned long *minor);
2942extern void sun4v_hvapi_unregister(unsigned long group);
2943extern int sun4v_hvapi_get(unsigned long group,
2944 unsigned long *major,
2945 unsigned long *minor);
2946extern void sun4v_hvapi_init(void);
2947#endif
2948
2949#endif /* !(_SPARC64_HYPERVISOR_H) */
diff --git a/include/asm-sparc/ide.h b/include/asm-sparc/ide.h
deleted file mode 100644
index b7af3d65823..00000000000
--- a/include/asm-sparc/ide.h
+++ /dev/null
@@ -1,97 +0,0 @@
1/* ide.h: SPARC PCI specific IDE glue.
2 *
3 * Copyright (C) 1997 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
5 * Adaptation from sparc64 version to sparc by Pete Zaitcev.
6 */
7
8#ifndef _SPARC_IDE_H
9#define _SPARC_IDE_H
10
11#ifdef __KERNEL__
12
13#include <asm/io.h>
14#ifdef CONFIG_SPARC64
15#include <asm/pgalloc.h>
16#include <asm/spitfire.h>
17#include <asm/cacheflush.h>
18#include <asm/page.h>
19#else
20#include <asm/pgtable.h>
21#include <asm/psr.h>
22#endif
23
24#define __ide_insl(data_reg, buffer, wcount) \
25 __ide_insw(data_reg, buffer, (wcount)<<1)
26#define __ide_outsl(data_reg, buffer, wcount) \
27 __ide_outsw(data_reg, buffer, (wcount)<<1)
28
29/* On sparc, I/O ports and MMIO registers are accessed identically. */
30#define __ide_mm_insw __ide_insw
31#define __ide_mm_insl __ide_insl
32#define __ide_mm_outsw __ide_outsw
33#define __ide_mm_outsl __ide_outsl
34
35static inline void __ide_insw(void __iomem *port, void *dst, u32 count)
36{
37#if defined(CONFIG_SPARC64) && defined(DCACHE_ALIASING_POSSIBLE)
38 unsigned long end = (unsigned long)dst + (count << 1);
39#endif
40 u16 *ps = dst;
41 u32 *pi;
42
43 if(((unsigned long)ps) & 0x2) {
44 *ps++ = __raw_readw(port);
45 count--;
46 }
47 pi = (u32 *)ps;
48 while(count >= 2) {
49 u32 w;
50
51 w = __raw_readw(port) << 16;
52 w |= __raw_readw(port);
53 *pi++ = w;
54 count -= 2;
55 }
56 ps = (u16 *)pi;
57 if(count)
58 *ps++ = __raw_readw(port);
59
60#if defined(CONFIG_SPARC64) && defined(DCACHE_ALIASING_POSSIBLE)
61 __flush_dcache_range((unsigned long)dst, end);
62#endif
63}
64
65static inline void __ide_outsw(void __iomem *port, const void *src, u32 count)
66{
67#if defined(CONFIG_SPARC64) && defined(DCACHE_ALIASING_POSSIBLE)
68 unsigned long end = (unsigned long)src + (count << 1);
69#endif
70 const u16 *ps = src;
71 const u32 *pi;
72
73 if(((unsigned long)src) & 0x2) {
74 __raw_writew(*ps++, port);
75 count--;
76 }
77 pi = (const u32 *)ps;
78 while(count >= 2) {
79 u32 w;
80
81 w = *pi++;
82 __raw_writew((w >> 16), port);
83 __raw_writew(w, port);
84 count -= 2;
85 }
86 ps = (const u16 *)pi;
87 if(count)
88 __raw_writew(*ps, port);
89
90#if defined(CONFIG_SPARC64) && defined(DCACHE_ALIASING_POSSIBLE)
91 __flush_dcache_range((unsigned long)src, end);
92#endif
93}
94
95#endif /* __KERNEL__ */
96
97#endif /* _SPARC_IDE_H */
diff --git a/include/asm-sparc/idprom.h b/include/asm-sparc/idprom.h
deleted file mode 100644
index 6976aa2439c..00000000000
--- a/include/asm-sparc/idprom.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * idprom.h: Macros and defines for idprom routines
3 *
4 * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
5 */
6
7#ifndef _SPARC_IDPROM_H
8#define _SPARC_IDPROM_H
9
10#include <linux/types.h>
11
12struct idprom {
13 u8 id_format; /* Format identifier (always 0x01) */
14 u8 id_machtype; /* Machine type */
15 u8 id_ethaddr[6]; /* Hardware ethernet address */
16 s32 id_date; /* Date of manufacture */
17 u32 id_sernum:24; /* Unique serial number */
18 u8 id_cksum; /* Checksum - xor of the data bytes */
19 u8 reserved[16];
20};
21
22extern struct idprom *idprom;
23extern void idprom_init(void);
24
25#endif /* !(_SPARC_IDPROM_H) */
diff --git a/include/asm-sparc/intr_queue.h b/include/asm-sparc/intr_queue.h
deleted file mode 100644
index 206077dedc2..00000000000
--- a/include/asm-sparc/intr_queue.h
+++ /dev/null
@@ -1,15 +0,0 @@
1#ifndef _SPARC64_INTR_QUEUE_H
2#define _SPARC64_INTR_QUEUE_H
3
4/* Sun4v interrupt queue registers, accessed via ASI_QUEUE. */
5
6#define INTRQ_CPU_MONDO_HEAD 0x3c0 /* CPU mondo head */
7#define INTRQ_CPU_MONDO_TAIL 0x3c8 /* CPU mondo tail */
8#define INTRQ_DEVICE_MONDO_HEAD 0x3d0 /* Device mondo head */
9#define INTRQ_DEVICE_MONDO_TAIL 0x3d8 /* Device mondo tail */
10#define INTRQ_RESUM_MONDO_HEAD 0x3e0 /* Resumable error mondo head */
11#define INTRQ_RESUM_MONDO_TAIL 0x3e8 /* Resumable error mondo tail */
12#define INTRQ_NONRESUM_MONDO_HEAD 0x3f0 /* Non-resumable error mondo head */
13#define INTRQ_NONRESUM_MONDO_TAIL 0x3f8 /* Non-resumable error mondo head */
14
15#endif /* !(_SPARC64_INTR_QUEUE_H) */
diff --git a/include/asm-sparc/io-unit.h b/include/asm-sparc/io-unit.h
deleted file mode 100644
index 96823b47fd4..00000000000
--- a/include/asm-sparc/io-unit.h
+++ /dev/null
@@ -1,62 +0,0 @@
1/* io-unit.h: Definitions for the sun4d IO-UNIT.
2 *
3 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
4 */
5#ifndef _SPARC_IO_UNIT_H
6#define _SPARC_IO_UNIT_H
7
8#include <linux/spinlock.h>
9#include <asm/page.h>
10#include <asm/pgtable.h>
11
12/* The io-unit handles all virtual to physical address translations
13 * that occur between the SBUS and physical memory. Access by
14 * the cpu to IO registers and similar go over the xdbus so are
15 * translated by the on chip SRMMU. The io-unit and the srmmu do
16 * not need to have the same translations at all, in fact most
17 * of the time the translations they handle are a disjunct set.
18 * Basically the io-unit handles all dvma sbus activity.
19 */
20
21/* AIEEE, unlike the nice sun4m, these monsters have
22 fixed DMA range 64M */
23
24#define IOUNIT_DMA_BASE 0xfc000000 /* TOP - 64M */
25#define IOUNIT_DMA_SIZE 0x04000000 /* 64M */
26/* We use last 1M for sparc_dvma_malloc */
27#define IOUNIT_DVMA_SIZE 0x00100000 /* 1M */
28
29/* The format of an iopte in the external page tables */
30#define IOUPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */
31#define IOUPTE_CACHE 0x00000080 /* Cached (in Viking/MXCC) */
32/* XXX Jakub, find out how to program SBUS streaming cache on XDBUS/sun4d.
33 * XXX Actually, all you should need to do is find out where the registers
34 * XXX are and copy over the sparc64 implementation I wrote. There may be
35 * XXX some horrible hwbugs though, so be careful. -DaveM
36 */
37#define IOUPTE_STREAM 0x00000040 /* Translation can use streaming cache */
38#define IOUPTE_INTRA 0x00000008 /* SBUS direct slot->slot transfer */
39#define IOUPTE_WRITE 0x00000004 /* Writeable */
40#define IOUPTE_VALID 0x00000002 /* IOPTE is valid */
41#define IOUPTE_PARITY 0x00000001 /* Parity is checked during DVMA */
42
43struct iounit_struct {
44 unsigned long bmap[(IOUNIT_DMA_SIZE >> (PAGE_SHIFT + 3)) / sizeof(unsigned long)];
45 spinlock_t lock;
46 iopte_t *page_table;
47 unsigned long rotor[3];
48 unsigned long limit[4];
49};
50
51#define IOUNIT_BMAP1_START 0x00000000
52#define IOUNIT_BMAP1_END (IOUNIT_DMA_SIZE >> (PAGE_SHIFT + 1))
53#define IOUNIT_BMAP2_START IOUNIT_BMAP1_END
54#define IOUNIT_BMAP2_END IOUNIT_BMAP2_START + (IOUNIT_DMA_SIZE >> (PAGE_SHIFT + 2))
55#define IOUNIT_BMAPM_START IOUNIT_BMAP2_END
56#define IOUNIT_BMAPM_END ((IOUNIT_DMA_SIZE - IOUNIT_DVMA_SIZE) >> PAGE_SHIFT)
57
58extern __u32 iounit_map_dma_init(struct sbus_bus *, int);
59#define iounit_map_dma_finish(sbus, addr, len) mmu_release_scsi_one(addr, len, sbus)
60extern __u32 iounit_map_dma_page(__u32, void *, struct sbus_bus *);
61
62#endif /* !(_SPARC_IO_UNIT_H) */
diff --git a/include/asm-sparc/io.h b/include/asm-sparc/io.h
deleted file mode 100644
index fc9024d3dfc..00000000000
--- a/include/asm-sparc/io.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_IO_H
2#define ___ASM_SPARC_IO_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/io_64.h>
5#else
6#include <asm-sparc/io_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/io_32.h b/include/asm-sparc/io_32.h
deleted file mode 100644
index 10d7da45007..00000000000
--- a/include/asm-sparc/io_32.h
+++ /dev/null
@@ -1,326 +0,0 @@
1#ifndef __SPARC_IO_H
2#define __SPARC_IO_H
3
4#include <linux/kernel.h>
5#include <linux/types.h>
6#include <linux/ioport.h> /* struct resource */
7
8#include <asm/page.h> /* IO address mapping routines need this */
9#include <asm/system.h>
10
11#define page_to_phys(page) (((page) - mem_map) << PAGE_SHIFT)
12
13static inline u32 flip_dword (u32 l)
14{
15 return ((l&0xff)<<24) | (((l>>8)&0xff)<<16) | (((l>>16)&0xff)<<8)| ((l>>24)&0xff);
16}
17
18static inline u16 flip_word (u16 w)
19{
20 return ((w&0xff) << 8) | ((w>>8)&0xff);
21}
22
23#define mmiowb()
24
25/*
26 * Memory mapped I/O to PCI
27 */
28
29static inline u8 __raw_readb(const volatile void __iomem *addr)
30{
31 return *(__force volatile u8 *)addr;
32}
33
34static inline u16 __raw_readw(const volatile void __iomem *addr)
35{
36 return *(__force volatile u16 *)addr;
37}
38
39static inline u32 __raw_readl(const volatile void __iomem *addr)
40{
41 return *(__force volatile u32 *)addr;
42}
43
44static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
45{
46 *(__force volatile u8 *)addr = b;
47}
48
49static inline void __raw_writew(u16 w, volatile void __iomem *addr)
50{
51 *(__force volatile u16 *)addr = w;
52}
53
54static inline void __raw_writel(u32 l, volatile void __iomem *addr)
55{
56 *(__force volatile u32 *)addr = l;
57}
58
59static inline u8 __readb(const volatile void __iomem *addr)
60{
61 return *(__force volatile u8 *)addr;
62}
63
64static inline u16 __readw(const volatile void __iomem *addr)
65{
66 return flip_word(*(__force volatile u16 *)addr);
67}
68
69static inline u32 __readl(const volatile void __iomem *addr)
70{
71 return flip_dword(*(__force volatile u32 *)addr);
72}
73
74static inline void __writeb(u8 b, volatile void __iomem *addr)
75{
76 *(__force volatile u8 *)addr = b;
77}
78
79static inline void __writew(u16 w, volatile void __iomem *addr)
80{
81 *(__force volatile u16 *)addr = flip_word(w);
82}
83
84static inline void __writel(u32 l, volatile void __iomem *addr)
85{
86 *(__force volatile u32 *)addr = flip_dword(l);
87}
88
89#define readb(__addr) __readb(__addr)
90#define readw(__addr) __readw(__addr)
91#define readl(__addr) __readl(__addr)
92#define readb_relaxed(__addr) readb(__addr)
93#define readw_relaxed(__addr) readw(__addr)
94#define readl_relaxed(__addr) readl(__addr)
95
96#define writeb(__b, __addr) __writeb((__b),(__addr))
97#define writew(__w, __addr) __writew((__w),(__addr))
98#define writel(__l, __addr) __writel((__l),(__addr))
99
100/*
101 * I/O space operations
102 *
103 * Arrangement on a Sun is somewhat complicated.
104 *
105 * First of all, we want to use standard Linux drivers
106 * for keyboard, PC serial, etc. These drivers think
107 * they access I/O space and use inb/outb.
108 * On the other hand, EBus bridge accepts PCI *memory*
109 * cycles and converts them into ISA *I/O* cycles.
110 * Ergo, we want inb & outb to generate PCI memory cycles.
111 *
112 * If we want to issue PCI *I/O* cycles, we do this
113 * with a low 64K fixed window in PCIC. This window gets
114 * mapped somewhere into virtual kernel space and we
115 * can use inb/outb again.
116 */
117#define inb_local(__addr) __readb((void __iomem *)(unsigned long)(__addr))
118#define inb(__addr) __readb((void __iomem *)(unsigned long)(__addr))
119#define inw(__addr) __readw((void __iomem *)(unsigned long)(__addr))
120#define inl(__addr) __readl((void __iomem *)(unsigned long)(__addr))
121
122#define outb_local(__b, __addr) __writeb(__b, (void __iomem *)(unsigned long)(__addr))
123#define outb(__b, __addr) __writeb(__b, (void __iomem *)(unsigned long)(__addr))
124#define outw(__w, __addr) __writew(__w, (void __iomem *)(unsigned long)(__addr))
125#define outl(__l, __addr) __writel(__l, (void __iomem *)(unsigned long)(__addr))
126
127#define inb_p(__addr) inb(__addr)
128#define outb_p(__b, __addr) outb(__b, __addr)
129#define inw_p(__addr) inw(__addr)
130#define outw_p(__w, __addr) outw(__w, __addr)
131#define inl_p(__addr) inl(__addr)
132#define outl_p(__l, __addr) outl(__l, __addr)
133
134void outsb(unsigned long addr, const void *src, unsigned long cnt);
135void outsw(unsigned long addr, const void *src, unsigned long cnt);
136void outsl(unsigned long addr, const void *src, unsigned long cnt);
137void insb(unsigned long addr, void *dst, unsigned long count);
138void insw(unsigned long addr, void *dst, unsigned long count);
139void insl(unsigned long addr, void *dst, unsigned long count);
140
141#define IO_SPACE_LIMIT 0xffffffff
142
143/*
144 * SBus accessors.
145 *
146 * SBus has only one, memory mapped, I/O space.
147 * We do not need to flip bytes for SBus of course.
148 */
149static inline u8 _sbus_readb(const volatile void __iomem *addr)
150{
151 return *(__force volatile u8 *)addr;
152}
153
154static inline u16 _sbus_readw(const volatile void __iomem *addr)
155{
156 return *(__force volatile u16 *)addr;
157}
158
159static inline u32 _sbus_readl(const volatile void __iomem *addr)
160{
161 return *(__force volatile u32 *)addr;
162}
163
164static inline void _sbus_writeb(u8 b, volatile void __iomem *addr)
165{
166 *(__force volatile u8 *)addr = b;
167}
168
169static inline void _sbus_writew(u16 w, volatile void __iomem *addr)
170{
171 *(__force volatile u16 *)addr = w;
172}
173
174static inline void _sbus_writel(u32 l, volatile void __iomem *addr)
175{
176 *(__force volatile u32 *)addr = l;
177}
178
179/*
180 * The only reason for #define's is to hide casts to unsigned long.
181 */
182#define sbus_readb(__addr) _sbus_readb(__addr)
183#define sbus_readw(__addr) _sbus_readw(__addr)
184#define sbus_readl(__addr) _sbus_readl(__addr)
185#define sbus_writeb(__b, __addr) _sbus_writeb(__b, __addr)
186#define sbus_writew(__w, __addr) _sbus_writew(__w, __addr)
187#define sbus_writel(__l, __addr) _sbus_writel(__l, __addr)
188
189static inline void sbus_memset_io(volatile void __iomem *__dst, int c, __kernel_size_t n)
190{
191 while(n--) {
192 sbus_writeb(c, __dst);
193 __dst++;
194 }
195}
196
197static inline void
198_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
199{
200 volatile void __iomem *d = dst;
201
202 while (n--) {
203 writeb(c, d);
204 d++;
205 }
206}
207
208#define memset_io(d,c,sz) _memset_io(d,c,sz)
209
210static inline void
211_memcpy_fromio(void *dst, const volatile void __iomem *src, __kernel_size_t n)
212{
213 char *d = dst;
214
215 while (n--) {
216 char tmp = readb(src);
217 *d++ = tmp;
218 src++;
219 }
220}
221
222#define memcpy_fromio(d,s,sz) _memcpy_fromio(d,s,sz)
223
224static inline void
225_memcpy_toio(volatile void __iomem *dst, const void *src, __kernel_size_t n)
226{
227 const char *s = src;
228 volatile void __iomem *d = dst;
229
230 while (n--) {
231 char tmp = *s++;
232 writeb(tmp, d);
233 d++;
234 }
235}
236
237#define memcpy_toio(d,s,sz) _memcpy_toio(d,s,sz)
238
239#ifdef __KERNEL__
240
241/*
242 * Bus number may be embedded in the higher bits of the physical address.
243 * This is why we have no bus number argument to ioremap().
244 */
245extern void __iomem *ioremap(unsigned long offset, unsigned long size);
246#define ioremap_nocache(X,Y) ioremap((X),(Y))
247#define ioremap_wc(X,Y) ioremap((X),(Y))
248extern void iounmap(volatile void __iomem *addr);
249
250#define ioread8(X) readb(X)
251#define ioread16(X) readw(X)
252#define ioread32(X) readl(X)
253#define iowrite8(val,X) writeb(val,X)
254#define iowrite16(val,X) writew(val,X)
255#define iowrite32(val,X) writel(val,X)
256
257static inline void ioread8_rep(void __iomem *port, void *buf, unsigned long count)
258{
259 insb((unsigned long __force)port, buf, count);
260}
261static inline void ioread16_rep(void __iomem *port, void *buf, unsigned long count)
262{
263 insw((unsigned long __force)port, buf, count);
264}
265
266static inline void ioread32_rep(void __iomem *port, void *buf, unsigned long count)
267{
268 insl((unsigned long __force)port, buf, count);
269}
270
271static inline void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count)
272{
273 outsb((unsigned long __force)port, buf, count);
274}
275
276static inline void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count)
277{
278 outsw((unsigned long __force)port, buf, count);
279}
280
281static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count)
282{
283 outsl((unsigned long __force)port, buf, count);
284}
285
286/* Create a virtual mapping cookie for an IO port range */
287extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
288extern void ioport_unmap(void __iomem *);
289
290/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
291struct pci_dev;
292extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
293extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
294
295/*
296 * Bus number may be in res->flags... somewhere.
297 */
298extern void __iomem *sbus_ioremap(struct resource *res, unsigned long offset,
299 unsigned long size, char *name);
300extern void sbus_iounmap(volatile void __iomem *vaddr, unsigned long size);
301
302
303/*
304 * At the moment, we do not use CMOS_READ anywhere outside of rtc.c,
305 * so rtc_port is static in it. This should not change unless a new
306 * hardware pops up.
307 */
308#define RTC_PORT(x) (rtc_port + (x))
309#define RTC_ALWAYS_BCD 0
310
311#endif
312
313#define __ARCH_HAS_NO_PAGE_ZERO_MAPPED 1
314
315/*
316 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
317 * access
318 */
319#define xlate_dev_mem_ptr(p) __va(p)
320
321/*
322 * Convert a virtual cached pointer to an uncached pointer
323 */
324#define xlate_dev_kmem_ptr(p) p
325
326#endif /* !(__SPARC_IO_H) */
diff --git a/include/asm-sparc/io_64.h b/include/asm-sparc/io_64.h
deleted file mode 100644
index 0bff078ffdd..00000000000
--- a/include/asm-sparc/io_64.h
+++ /dev/null
@@ -1,511 +0,0 @@
1#ifndef __SPARC64_IO_H
2#define __SPARC64_IO_H
3
4#include <linux/kernel.h>
5#include <linux/compiler.h>
6#include <linux/types.h>
7
8#include <asm/page.h> /* IO address mapping routines need this */
9#include <asm/system.h>
10#include <asm/asi.h>
11
12/* PC crapola... */
13#define __SLOW_DOWN_IO do { } while (0)
14#define SLOW_DOWN_IO do { } while (0)
15
16/* BIO layer definitions. */
17extern unsigned long kern_base, kern_size;
18#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
19
20static inline u8 _inb(unsigned long addr)
21{
22 u8 ret;
23
24 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_inb */"
25 : "=r" (ret)
26 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
27 : "memory");
28
29 return ret;
30}
31
32static inline u16 _inw(unsigned long addr)
33{
34 u16 ret;
35
36 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_inw */"
37 : "=r" (ret)
38 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
39 : "memory");
40
41 return ret;
42}
43
44static inline u32 _inl(unsigned long addr)
45{
46 u32 ret;
47
48 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_inl */"
49 : "=r" (ret)
50 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
51 : "memory");
52
53 return ret;
54}
55
56static inline void _outb(u8 b, unsigned long addr)
57{
58 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_outb */"
59 : /* no outputs */
60 : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
61 : "memory");
62}
63
64static inline void _outw(u16 w, unsigned long addr)
65{
66 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_outw */"
67 : /* no outputs */
68 : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
69 : "memory");
70}
71
72static inline void _outl(u32 l, unsigned long addr)
73{
74 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_outl */"
75 : /* no outputs */
76 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
77 : "memory");
78}
79
80#define inb(__addr) (_inb((unsigned long)(__addr)))
81#define inw(__addr) (_inw((unsigned long)(__addr)))
82#define inl(__addr) (_inl((unsigned long)(__addr)))
83#define outb(__b, __addr) (_outb((u8)(__b), (unsigned long)(__addr)))
84#define outw(__w, __addr) (_outw((u16)(__w), (unsigned long)(__addr)))
85#define outl(__l, __addr) (_outl((u32)(__l), (unsigned long)(__addr)))
86
87#define inb_p(__addr) inb(__addr)
88#define outb_p(__b, __addr) outb(__b, __addr)
89#define inw_p(__addr) inw(__addr)
90#define outw_p(__w, __addr) outw(__w, __addr)
91#define inl_p(__addr) inl(__addr)
92#define outl_p(__l, __addr) outl(__l, __addr)
93
94extern void outsb(unsigned long, const void *, unsigned long);
95extern void outsw(unsigned long, const void *, unsigned long);
96extern void outsl(unsigned long, const void *, unsigned long);
97extern void insb(unsigned long, void *, unsigned long);
98extern void insw(unsigned long, void *, unsigned long);
99extern void insl(unsigned long, void *, unsigned long);
100
101static inline void ioread8_rep(void __iomem *port, void *buf, unsigned long count)
102{
103 insb((unsigned long __force)port, buf, count);
104}
105static inline void ioread16_rep(void __iomem *port, void *buf, unsigned long count)
106{
107 insw((unsigned long __force)port, buf, count);
108}
109
110static inline void ioread32_rep(void __iomem *port, void *buf, unsigned long count)
111{
112 insl((unsigned long __force)port, buf, count);
113}
114
115static inline void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count)
116{
117 outsb((unsigned long __force)port, buf, count);
118}
119
120static inline void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count)
121{
122 outsw((unsigned long __force)port, buf, count);
123}
124
125static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count)
126{
127 outsl((unsigned long __force)port, buf, count);
128}
129
130/* Memory functions, same as I/O accesses on Ultra. */
131static inline u8 _readb(const volatile void __iomem *addr)
132{ u8 ret;
133
134 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_readb */"
135 : "=r" (ret)
136 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
137 : "memory");
138 return ret;
139}
140
141static inline u16 _readw(const volatile void __iomem *addr)
142{ u16 ret;
143
144 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_readw */"
145 : "=r" (ret)
146 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
147 : "memory");
148
149 return ret;
150}
151
152static inline u32 _readl(const volatile void __iomem *addr)
153{ u32 ret;
154
155 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_readl */"
156 : "=r" (ret)
157 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
158 : "memory");
159
160 return ret;
161}
162
163static inline u64 _readq(const volatile void __iomem *addr)
164{ u64 ret;
165
166 __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_readq */"
167 : "=r" (ret)
168 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
169 : "memory");
170
171 return ret;
172}
173
174static inline void _writeb(u8 b, volatile void __iomem *addr)
175{
176 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */"
177 : /* no outputs */
178 : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
179 : "memory");
180}
181
182static inline void _writew(u16 w, volatile void __iomem *addr)
183{
184 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */"
185 : /* no outputs */
186 : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
187 : "memory");
188}
189
190static inline void _writel(u32 l, volatile void __iomem *addr)
191{
192 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */"
193 : /* no outputs */
194 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
195 : "memory");
196}
197
198static inline void _writeq(u64 q, volatile void __iomem *addr)
199{
200 __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */"
201 : /* no outputs */
202 : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
203 : "memory");
204}
205
206#define readb(__addr) _readb(__addr)
207#define readw(__addr) _readw(__addr)
208#define readl(__addr) _readl(__addr)
209#define readq(__addr) _readq(__addr)
210#define readb_relaxed(__addr) _readb(__addr)
211#define readw_relaxed(__addr) _readw(__addr)
212#define readl_relaxed(__addr) _readl(__addr)
213#define readq_relaxed(__addr) _readq(__addr)
214#define writeb(__b, __addr) _writeb(__b, __addr)
215#define writew(__w, __addr) _writew(__w, __addr)
216#define writel(__l, __addr) _writel(__l, __addr)
217#define writeq(__q, __addr) _writeq(__q, __addr)
218
219/* Now versions without byte-swapping. */
220static inline u8 _raw_readb(unsigned long addr)
221{
222 u8 ret;
223
224 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_raw_readb */"
225 : "=r" (ret)
226 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
227
228 return ret;
229}
230
231static inline u16 _raw_readw(unsigned long addr)
232{
233 u16 ret;
234
235 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_raw_readw */"
236 : "=r" (ret)
237 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
238
239 return ret;
240}
241
242static inline u32 _raw_readl(unsigned long addr)
243{
244 u32 ret;
245
246 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_raw_readl */"
247 : "=r" (ret)
248 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
249
250 return ret;
251}
252
253static inline u64 _raw_readq(unsigned long addr)
254{
255 u64 ret;
256
257 __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_raw_readq */"
258 : "=r" (ret)
259 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
260
261 return ret;
262}
263
264static inline void _raw_writeb(u8 b, unsigned long addr)
265{
266 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_raw_writeb */"
267 : /* no outputs */
268 : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
269}
270
271static inline void _raw_writew(u16 w, unsigned long addr)
272{
273 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_raw_writew */"
274 : /* no outputs */
275 : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
276}
277
278static inline void _raw_writel(u32 l, unsigned long addr)
279{
280 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_raw_writel */"
281 : /* no outputs */
282 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
283}
284
285static inline void _raw_writeq(u64 q, unsigned long addr)
286{
287 __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_raw_writeq */"
288 : /* no outputs */
289 : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
290}
291
292#define __raw_readb(__addr) (_raw_readb((unsigned long)(__addr)))
293#define __raw_readw(__addr) (_raw_readw((unsigned long)(__addr)))
294#define __raw_readl(__addr) (_raw_readl((unsigned long)(__addr)))
295#define __raw_readq(__addr) (_raw_readq((unsigned long)(__addr)))
296#define __raw_writeb(__b, __addr) (_raw_writeb((u8)(__b), (unsigned long)(__addr)))
297#define __raw_writew(__w, __addr) (_raw_writew((u16)(__w), (unsigned long)(__addr)))
298#define __raw_writel(__l, __addr) (_raw_writel((u32)(__l), (unsigned long)(__addr)))
299#define __raw_writeq(__q, __addr) (_raw_writeq((u64)(__q), (unsigned long)(__addr)))
300
301/* Valid I/O Space regions are anywhere, because each PCI bus supported
302 * can live in an arbitrary area of the physical address range.
303 */
304#define IO_SPACE_LIMIT 0xffffffffffffffffUL
305
306/* Now, SBUS variants, only difference from PCI is that we do
307 * not use little-endian ASIs.
308 */
309static inline u8 _sbus_readb(const volatile void __iomem *addr)
310{
311 u8 ret;
312
313 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* sbus_readb */"
314 : "=r" (ret)
315 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
316 : "memory");
317
318 return ret;
319}
320
321static inline u16 _sbus_readw(const volatile void __iomem *addr)
322{
323 u16 ret;
324
325 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* sbus_readw */"
326 : "=r" (ret)
327 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
328 : "memory");
329
330 return ret;
331}
332
333static inline u32 _sbus_readl(const volatile void __iomem *addr)
334{
335 u32 ret;
336
337 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* sbus_readl */"
338 : "=r" (ret)
339 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
340 : "memory");
341
342 return ret;
343}
344
345static inline u64 _sbus_readq(const volatile void __iomem *addr)
346{
347 u64 ret;
348
349 __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* sbus_readq */"
350 : "=r" (ret)
351 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
352 : "memory");
353
354 return ret;
355}
356
357static inline void _sbus_writeb(u8 b, volatile void __iomem *addr)
358{
359 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* sbus_writeb */"
360 : /* no outputs */
361 : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
362 : "memory");
363}
364
365static inline void _sbus_writew(u16 w, volatile void __iomem *addr)
366{
367 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* sbus_writew */"
368 : /* no outputs */
369 : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
370 : "memory");
371}
372
373static inline void _sbus_writel(u32 l, volatile void __iomem *addr)
374{
375 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* sbus_writel */"
376 : /* no outputs */
377 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
378 : "memory");
379}
380
381static inline void _sbus_writeq(u64 l, volatile void __iomem *addr)
382{
383 __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* sbus_writeq */"
384 : /* no outputs */
385 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
386 : "memory");
387}
388
389#define sbus_readb(__addr) _sbus_readb(__addr)
390#define sbus_readw(__addr) _sbus_readw(__addr)
391#define sbus_readl(__addr) _sbus_readl(__addr)
392#define sbus_readq(__addr) _sbus_readq(__addr)
393#define sbus_writeb(__b, __addr) _sbus_writeb(__b, __addr)
394#define sbus_writew(__w, __addr) _sbus_writew(__w, __addr)
395#define sbus_writel(__l, __addr) _sbus_writel(__l, __addr)
396#define sbus_writeq(__l, __addr) _sbus_writeq(__l, __addr)
397
398static inline void _sbus_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
399{
400 while(n--) {
401 sbus_writeb(c, dst);
402 dst++;
403 }
404}
405
406#define sbus_memset_io(d,c,sz) _sbus_memset_io(d,c,sz)
407
408static inline void
409_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
410{
411 volatile void __iomem *d = dst;
412
413 while (n--) {
414 writeb(c, d);
415 d++;
416 }
417}
418
419#define memset_io(d,c,sz) _memset_io(d,c,sz)
420
421static inline void
422_memcpy_fromio(void *dst, const volatile void __iomem *src, __kernel_size_t n)
423{
424 char *d = dst;
425
426 while (n--) {
427 char tmp = readb(src);
428 *d++ = tmp;
429 src++;
430 }
431}
432
433#define memcpy_fromio(d,s,sz) _memcpy_fromio(d,s,sz)
434
435static inline void
436_memcpy_toio(volatile void __iomem *dst, const void *src, __kernel_size_t n)
437{
438 const char *s = src;
439 volatile void __iomem *d = dst;
440
441 while (n--) {
442 char tmp = *s++;
443 writeb(tmp, d);
444 d++;
445 }
446}
447
448#define memcpy_toio(d,s,sz) _memcpy_toio(d,s,sz)
449
450#define mmiowb()
451
452#ifdef __KERNEL__
453
454/* On sparc64 we have the whole physical IO address space accessible
455 * using physically addressed loads and stores, so this does nothing.
456 */
457static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
458{
459 return (void __iomem *)offset;
460}
461
462#define ioremap_nocache(X,Y) ioremap((X),(Y))
463#define ioremap_wc(X,Y) ioremap((X),(Y))
464
465static inline void iounmap(volatile void __iomem *addr)
466{
467}
468
469#define ioread8(X) readb(X)
470#define ioread16(X) readw(X)
471#define ioread32(X) readl(X)
472#define iowrite8(val,X) writeb(val,X)
473#define iowrite16(val,X) writew(val,X)
474#define iowrite32(val,X) writel(val,X)
475
476/* Create a virtual mapping cookie for an IO port range */
477extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
478extern void ioport_unmap(void __iomem *);
479
480/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
481struct pci_dev;
482extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
483extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
484
485/* Similarly for SBUS. */
486#define sbus_ioremap(__res, __offset, __size, __name) \
487({ unsigned long __ret; \
488 __ret = (__res)->start + (((__res)->flags & 0x1ffUL) << 32UL); \
489 __ret += (unsigned long) (__offset); \
490 if (! request_region((__ret), (__size), (__name))) \
491 __ret = 0UL; \
492 (void __iomem *) __ret; \
493})
494
495#define sbus_iounmap(__addr, __size) \
496 release_region((unsigned long)(__addr), (__size))
497
498/*
499 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
500 * access
501 */
502#define xlate_dev_mem_ptr(p) __va(p)
503
504/*
505 * Convert a virtual cached pointer to an uncached pointer
506 */
507#define xlate_dev_kmem_ptr(p) p
508
509#endif
510
511#endif /* !(__SPARC64_IO_H) */
diff --git a/include/asm-sparc/ioctl.h b/include/asm-sparc/ioctl.h
deleted file mode 100644
index 7d6bd51321b..00000000000
--- a/include/asm-sparc/ioctl.h
+++ /dev/null
@@ -1,67 +0,0 @@
1#ifndef _SPARC_IOCTL_H
2#define _SPARC_IOCTL_H
3
4/*
5 * Our DIR and SIZE overlap in order to simulteneously provide
6 * a non-zero _IOC_NONE (for binary compatibility) and
7 * 14 bits of size as on i386. Here's the layout:
8 *
9 * 0xE0000000 DIR
10 * 0x80000000 DIR = WRITE
11 * 0x40000000 DIR = READ
12 * 0x20000000 DIR = NONE
13 * 0x3FFF0000 SIZE (overlaps NONE bit)
14 * 0x0000FF00 TYPE
15 * 0x000000FF NR (CMD)
16 */
17
18#define _IOC_NRBITS 8
19#define _IOC_TYPEBITS 8
20#define _IOC_SIZEBITS 13 /* Actually 14, see below. */
21#define _IOC_DIRBITS 3
22
23#define _IOC_NRMASK ((1 << _IOC_NRBITS)-1)
24#define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1)
25#define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1)
26#define _IOC_XSIZEMASK ((1 << (_IOC_SIZEBITS+1))-1)
27#define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1)
28
29#define _IOC_NRSHIFT 0
30#define _IOC_TYPESHIFT (_IOC_NRSHIFT + _IOC_NRBITS)
31#define _IOC_SIZESHIFT (_IOC_TYPESHIFT + _IOC_TYPEBITS)
32#define _IOC_DIRSHIFT (_IOC_SIZESHIFT + _IOC_SIZEBITS)
33
34#define _IOC_NONE 1U
35#define _IOC_READ 2U
36#define _IOC_WRITE 4U
37
38#define _IOC(dir,type,nr,size) \
39 (((dir) << _IOC_DIRSHIFT) | \
40 ((type) << _IOC_TYPESHIFT) | \
41 ((nr) << _IOC_NRSHIFT) | \
42 ((size) << _IOC_SIZESHIFT))
43
44#define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0)
45#define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size))
46#define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size))
47#define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size))
48
49/* Used to decode ioctl numbers in drivers despite the leading underscore... */
50#define _IOC_DIR(nr) \
51 ( (((((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) & (_IOC_WRITE|_IOC_READ)) != 0)? \
52 (((nr) >> _IOC_DIRSHIFT) & (_IOC_WRITE|_IOC_READ)): \
53 (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) )
54#define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
55#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
56#define _IOC_SIZE(nr) \
57 ((((((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) & (_IOC_WRITE|_IOC_READ)) == 0)? \
58 0: (((nr) >> _IOC_SIZESHIFT) & _IOC_XSIZEMASK))
59
60/* ...and for the PCMCIA and sound. */
61#define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT)
62#define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT)
63#define IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
64#define IOCSIZE_MASK (_IOC_XSIZEMASK << _IOC_SIZESHIFT)
65#define IOCSIZE_SHIFT (_IOC_SIZESHIFT)
66
67#endif /* !(_SPARC_IOCTL_H) */
diff --git a/include/asm-sparc/ioctls.h b/include/asm-sparc/ioctls.h
deleted file mode 100644
index 1fe6855c5c1..00000000000
--- a/include/asm-sparc/ioctls.h
+++ /dev/null
@@ -1,136 +0,0 @@
1#ifndef _ASM_SPARC_IOCTLS_H
2#define _ASM_SPARC_IOCTLS_H
3
4#include <asm/ioctl.h>
5
6/* Big T */
7#define TCGETA _IOR('T', 1, struct termio)
8#define TCSETA _IOW('T', 2, struct termio)
9#define TCSETAW _IOW('T', 3, struct termio)
10#define TCSETAF _IOW('T', 4, struct termio)
11#define TCSBRK _IO('T', 5)
12#define TCXONC _IO('T', 6)
13#define TCFLSH _IO('T', 7)
14#define TCGETS _IOR('T', 8, struct termios)
15#define TCSETS _IOW('T', 9, struct termios)
16#define TCSETSW _IOW('T', 10, struct termios)
17#define TCSETSF _IOW('T', 11, struct termios)
18#define TCGETS2 _IOR('T', 12, struct termios2)
19#define TCSETS2 _IOW('T', 13, struct termios2)
20#define TCSETSW2 _IOW('T', 14, struct termios2)
21#define TCSETSF2 _IOW('T', 15, struct termios2)
22
23/* Note that all the ioctls that are not available in Linux have a
24 * double underscore on the front to: a) avoid some programs to
25 * think we support some ioctls under Linux (autoconfiguration stuff)
26 */
27/* Little t */
28#define TIOCGETD _IOR('t', 0, int)
29#define TIOCSETD _IOW('t', 1, int)
30#define __TIOCHPCL _IO('t', 2) /* SunOS Specific */
31#define __TIOCMODG _IOR('t', 3, int) /* SunOS Specific */
32#define __TIOCMODS _IOW('t', 4, int) /* SunOS Specific */
33#define __TIOCGETP _IOR('t', 8, struct sgttyb) /* SunOS Specific */
34#define __TIOCSETP _IOW('t', 9, struct sgttyb) /* SunOS Specific */
35#define __TIOCSETN _IOW('t', 10, struct sgttyb) /* SunOS Specific */
36#define TIOCEXCL _IO('t', 13)
37#define TIOCNXCL _IO('t', 14)
38#define __TIOCFLUSH _IOW('t', 16, int) /* SunOS Specific */
39#define __TIOCSETC _IOW('t', 17, struct tchars) /* SunOS Specific */
40#define __TIOCGETC _IOR('t', 18, struct tchars) /* SunOS Specific */
41#define __TIOCTCNTL _IOW('t', 32, int) /* SunOS Specific */
42#define __TIOCSIGNAL _IOW('t', 33, int) /* SunOS Specific */
43#define __TIOCSETX _IOW('t', 34, int) /* SunOS Specific */
44#define __TIOCGETX _IOR('t', 35, int) /* SunOS Specific */
45#define TIOCCONS _IO('t', 36)
46#define TIOCGSOFTCAR _IOR('t', 100, int)
47#define TIOCSSOFTCAR _IOW('t', 101, int)
48#define __TIOCUCNTL _IOW('t', 102, int) /* SunOS Specific */
49#define TIOCSWINSZ _IOW('t', 103, struct winsize)
50#define TIOCGWINSZ _IOR('t', 104, struct winsize)
51#define __TIOCREMOTE _IOW('t', 105, int) /* SunOS Specific */
52#define TIOCMGET _IOR('t', 106, int)
53#define TIOCMBIC _IOW('t', 107, int)
54#define TIOCMBIS _IOW('t', 108, int)
55#define TIOCMSET _IOW('t', 109, int)
56#define TIOCSTART _IO('t', 110)
57#define TIOCSTOP _IO('t', 111)
58#define TIOCPKT _IOW('t', 112, int)
59#define TIOCNOTTY _IO('t', 113)
60#define TIOCSTI _IOW('t', 114, char)
61#define TIOCOUTQ _IOR('t', 115, int)
62#define __TIOCGLTC _IOR('t', 116, struct ltchars) /* SunOS Specific */
63#define __TIOCSLTC _IOW('t', 117, struct ltchars) /* SunOS Specific */
64/* 118 is the non-posix setpgrp tty ioctl */
65/* 119 is the non-posix getpgrp tty ioctl */
66#define __TIOCCDTR _IO('t', 120) /* SunOS Specific */
67#define __TIOCSDTR _IO('t', 121) /* SunOS Specific */
68#define TIOCCBRK _IO('t', 122)
69#define TIOCSBRK _IO('t', 123)
70#define __TIOCLGET _IOW('t', 124, int) /* SunOS Specific */
71#define __TIOCLSET _IOW('t', 125, int) /* SunOS Specific */
72#define __TIOCLBIC _IOW('t', 126, int) /* SunOS Specific */
73#define __TIOCLBIS _IOW('t', 127, int) /* SunOS Specific */
74#define __TIOCISPACE _IOR('t', 128, int) /* SunOS Specific */
75#define __TIOCISIZE _IOR('t', 129, int) /* SunOS Specific */
76#define TIOCSPGRP _IOW('t', 130, int)
77#define TIOCGPGRP _IOR('t', 131, int)
78#define TIOCSCTTY _IO('t', 132)
79#define TIOCGSID _IOR('t', 133, int)
80/* Get minor device of a pty master's FD -- Solaris equiv is ISPTM */
81#define TIOCGPTN _IOR('t', 134, unsigned int) /* Get Pty Number */
82#define TIOCSPTLCK _IOW('t', 135, int) /* Lock/unlock PTY */
83
84/* Little f */
85#define FIOCLEX _IO('f', 1)
86#define FIONCLEX _IO('f', 2)
87#define FIOASYNC _IOW('f', 125, int)
88#define FIONBIO _IOW('f', 126, int)
89#define FIONREAD _IOR('f', 127, int)
90#define TIOCINQ FIONREAD
91#define FIOQSIZE _IOR('f', 128, loff_t)
92
93/* SCARY Rutgers local SunOS kernel hackery, perhaps I will support it
94 * someday. This is completely bogus, I know...
95 */
96#define __TCGETSTAT _IO('T', 200) /* Rutgers specific */
97#define __TCSETSTAT _IO('T', 201) /* Rutgers specific */
98
99/* Linux specific, no SunOS equivalent. */
100#define TIOCLINUX 0x541C
101#define TIOCGSERIAL 0x541E
102#define TIOCSSERIAL 0x541F
103#define TCSBRKP 0x5425
104#define TIOCSERCONFIG 0x5453
105#define TIOCSERGWILD 0x5454
106#define TIOCSERSWILD 0x5455
107#define TIOCGLCKTRMIOS 0x5456
108#define TIOCSLCKTRMIOS 0x5457
109#define TIOCSERGSTRUCT 0x5458 /* For debugging only */
110#define TIOCSERGETLSR 0x5459 /* Get line status register */
111#define TIOCSERGETMULTI 0x545A /* Get multiport config */
112#define TIOCSERSETMULTI 0x545B /* Set multiport config */
113#define TIOCMIWAIT 0x545C /* Wait for change on serial input line(s) */
114#define TIOCGICOUNT 0x545D /* Read serial port inline interrupt counts */
115
116/* Kernel definitions */
117#ifdef __KERNEL__
118#define TIOCGETC __TIOCGETC
119#define TIOCGETP __TIOCGETP
120#define TIOCGLTC __TIOCGLTC
121#define TIOCSLTC __TIOCSLTC
122#define TIOCSETP __TIOCSETP
123#define TIOCSETN __TIOCSETN
124#define TIOCSETC __TIOCSETC
125#endif
126
127/* Used for packet mode */
128#define TIOCPKT_DATA 0
129#define TIOCPKT_FLUSHREAD 1
130#define TIOCPKT_FLUSHWRITE 2
131#define TIOCPKT_STOP 4
132#define TIOCPKT_START 8
133#define TIOCPKT_NOSTOP 16
134#define TIOCPKT_DOSTOP 32
135
136#endif /* !(_ASM_SPARC_IOCTLS_H) */
diff --git a/include/asm-sparc/iommu.h b/include/asm-sparc/iommu.h
deleted file mode 100644
index 91b072b0d7a..00000000000
--- a/include/asm-sparc/iommu.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_IOMMU_H
2#define ___ASM_SPARC_IOMMU_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/iommu_64.h>
5#else
6#include <asm-sparc/iommu_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/iommu_32.h b/include/asm-sparc/iommu_32.h
deleted file mode 100644
index 70c589c05a1..00000000000
--- a/include/asm-sparc/iommu_32.h
+++ /dev/null
@@ -1,121 +0,0 @@
1/* iommu.h: Definitions for the sun4m IOMMU.
2 *
3 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
4 */
5#ifndef _SPARC_IOMMU_H
6#define _SPARC_IOMMU_H
7
8#include <asm/page.h>
9#include <asm/bitext.h>
10
11/* The iommu handles all virtual to physical address translations
12 * that occur between the SBUS and physical memory. Access by
13 * the cpu to IO registers and similar go over the mbus so are
14 * translated by the on chip SRMMU. The iommu and the srmmu do
15 * not need to have the same translations at all, in fact most
16 * of the time the translations they handle are a disjunct set.
17 * Basically the iommu handles all dvma sbus activity.
18 */
19
20/* The IOMMU registers occupy three pages in IO space. */
21struct iommu_regs {
22 /* First page */
23 volatile unsigned long control; /* IOMMU control */
24 volatile unsigned long base; /* Physical base of iopte page table */
25 volatile unsigned long _unused1[3];
26 volatile unsigned long tlbflush; /* write only */
27 volatile unsigned long pageflush; /* write only */
28 volatile unsigned long _unused2[1017];
29 /* Second page */
30 volatile unsigned long afsr; /* Async-fault status register */
31 volatile unsigned long afar; /* Async-fault physical address */
32 volatile unsigned long _unused3[2];
33 volatile unsigned long sbuscfg0; /* SBUS configuration registers, per-slot */
34 volatile unsigned long sbuscfg1;
35 volatile unsigned long sbuscfg2;
36 volatile unsigned long sbuscfg3;
37 volatile unsigned long mfsr; /* Memory-fault status register */
38 volatile unsigned long mfar; /* Memory-fault physical address */
39 volatile unsigned long _unused4[1014];
40 /* Third page */
41 volatile unsigned long mid; /* IOMMU module-id */
42};
43
44#define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
45#define IOMMU_CTRL_VERS 0x0f000000 /* Version */
46#define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
47#define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
48#define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
49#define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
50#define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
51#define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
52#define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */
53#define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */
54#define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */
55#define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */
56
57#define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */
58#define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after transaction */
59#define IOMMU_AFSR_TO 0x20000000 /* Write access took more than 12.8 us. */
60#define IOMMU_AFSR_BE 0x10000000 /* Write access received error acknowledge */
61#define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */
62#define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
63#define IOMMU_AFSR_RESV 0x00f00000 /* Reserver, forced to 0x8 by hardware */
64#define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */
65#define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */
66#define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */
67
68#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when bypass enabled */
69#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
70#define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
71#define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
72 produced by this device as pure
73 physical. */
74
75#define IOMMU_MFSR_ERR 0x80000000 /* One or more of PERR1 or PERR0 */
76#define IOMMU_MFSR_S 0x01000000 /* Sparc was in supervisor mode */
77#define IOMMU_MFSR_CPU 0x00800000 /* CPU transaction caused parity error */
78#define IOMMU_MFSR_ME 0x00080000 /* Multiple parity errors occurred */
79#define IOMMU_MFSR_PERR 0x00006000 /* high bit indicates parity error occurred
80 on the even word of the access, low bit
81 indicated odd word caused the parity error */
82#define IOMMU_MFSR_BM 0x00001000 /* Error occurred while in boot mode */
83#define IOMMU_MFSR_C 0x00000800 /* Address causing error was marked cacheable */
84#define IOMMU_MFSR_RTYP 0x000000f0 /* Memory request transaction type */
85
86#define IOMMU_MID_SBAE 0x001f0000 /* SBus arbitration enable */
87#define IOMMU_MID_SE 0x00100000 /* Enables SCSI/ETHERNET arbitration */
88#define IOMMU_MID_SB3 0x00080000 /* Enable SBUS device 3 arbitration */
89#define IOMMU_MID_SB2 0x00040000 /* Enable SBUS device 2 arbitration */
90#define IOMMU_MID_SB1 0x00020000 /* Enable SBUS device 1 arbitration */
91#define IOMMU_MID_SB0 0x00010000 /* Enable SBUS device 0 arbitration */
92#define IOMMU_MID_MID 0x0000000f /* Module-id, hardcoded to 0x8 */
93
94/* The format of an iopte in the page tables */
95#define IOPTE_PAGE 0x07ffff00 /* Physical page number (PA[30:12]) */
96#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */
97#define IOPTE_WRITE 0x00000004 /* Writeable */
98#define IOPTE_VALID 0x00000002 /* IOPTE is valid */
99#define IOPTE_WAZ 0x00000001 /* Write as zeros */
100
101struct iommu_struct {
102 struct iommu_regs *regs;
103 iopte_t *page_table;
104 /* For convenience */
105 unsigned long start; /* First managed virtual address */
106 unsigned long end; /* Last managed virtual address */
107
108 struct bit_map usemap;
109};
110
111static inline void iommu_invalidate(struct iommu_regs *regs)
112{
113 regs->tlbflush = 0;
114}
115
116static inline void iommu_invalidate_page(struct iommu_regs *regs, unsigned long ba)
117{
118 regs->pageflush = (ba & PAGE_MASK);
119}
120
121#endif /* !(_SPARC_IOMMU_H) */
diff --git a/include/asm-sparc/iommu_64.h b/include/asm-sparc/iommu_64.h
deleted file mode 100644
index d7b9afcba08..00000000000
--- a/include/asm-sparc/iommu_64.h
+++ /dev/null
@@ -1,62 +0,0 @@
1/* iommu.h: Definitions for the sun5 IOMMU.
2 *
3 * Copyright (C) 1996, 1999, 2007 David S. Miller (davem@davemloft.net)
4 */
5#ifndef _SPARC64_IOMMU_H
6#define _SPARC64_IOMMU_H
7
8/* The format of an iopte in the page tables. */
9#define IOPTE_VALID 0x8000000000000000UL
10#define IOPTE_64K 0x2000000000000000UL
11#define IOPTE_STBUF 0x1000000000000000UL
12#define IOPTE_INTRA 0x0800000000000000UL
13#define IOPTE_CONTEXT 0x07ff800000000000UL
14#define IOPTE_PAGE 0x00007fffffffe000UL
15#define IOPTE_CACHE 0x0000000000000010UL
16#define IOPTE_WRITE 0x0000000000000002UL
17
18#define IOMMU_NUM_CTXS 4096
19
20struct iommu_arena {
21 unsigned long *map;
22 unsigned int hint;
23 unsigned int limit;
24};
25
26struct iommu {
27 spinlock_t lock;
28 struct iommu_arena arena;
29 void (*flush_all)(struct iommu *);
30 iopte_t *page_table;
31 u32 page_table_map_base;
32 unsigned long iommu_control;
33 unsigned long iommu_tsbbase;
34 unsigned long iommu_flush;
35 unsigned long iommu_flushinv;
36 unsigned long iommu_tags;
37 unsigned long iommu_ctxflush;
38 unsigned long write_complete_reg;
39 unsigned long dummy_page;
40 unsigned long dummy_page_pa;
41 unsigned long ctx_lowest_free;
42 DECLARE_BITMAP(ctx_bitmap, IOMMU_NUM_CTXS);
43 u32 dma_addr_mask;
44};
45
46struct strbuf {
47 int strbuf_enabled;
48 unsigned long strbuf_control;
49 unsigned long strbuf_pflush;
50 unsigned long strbuf_fsync;
51 unsigned long strbuf_ctxflush;
52 unsigned long strbuf_ctxmatch_base;
53 unsigned long strbuf_flushflag_pa;
54 volatile unsigned long *strbuf_flushflag;
55 volatile unsigned long __flushflag_buf[(64+(64-1)) / sizeof(long)];
56};
57
58extern int iommu_table_init(struct iommu *iommu, int tsbsize,
59 u32 dma_offset, u32 dma_addr_mask,
60 int numa_node);
61
62#endif /* !(_SPARC64_IOMMU_H) */
diff --git a/include/asm-sparc/ipcbuf.h b/include/asm-sparc/ipcbuf.h
deleted file mode 100644
index 037605d986e..00000000000
--- a/include/asm-sparc/ipcbuf.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_IPCBUF_H
2#define ___ASM_SPARC_IPCBUF_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/ipcbuf_64.h>
5#else
6#include <asm-sparc/ipcbuf_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/ipcbuf_32.h b/include/asm-sparc/ipcbuf_32.h
deleted file mode 100644
index 6387209518f..00000000000
--- a/include/asm-sparc/ipcbuf_32.h
+++ /dev/null
@@ -1,31 +0,0 @@
1#ifndef _SPARC_IPCBUF_H
2#define _SPARC_IPCBUF_H
3
4/*
5 * The ipc64_perm structure for sparc architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 32-bit mode
11 * - 32-bit seq
12 * - 2 miscellaneous 64-bit values (so that this structure matches
13 * sparc64 ipc64_perm)
14 */
15
16struct ipc64_perm
17{
18 __kernel_key_t key;
19 __kernel_uid32_t uid;
20 __kernel_gid32_t gid;
21 __kernel_uid32_t cuid;
22 __kernel_gid32_t cgid;
23 unsigned short __pad1;
24 __kernel_mode_t mode;
25 unsigned short __pad2;
26 unsigned short seq;
27 unsigned long long __unused1;
28 unsigned long long __unused2;
29};
30
31#endif /* _SPARC_IPCBUF_H */
diff --git a/include/asm-sparc/ipcbuf_64.h b/include/asm-sparc/ipcbuf_64.h
deleted file mode 100644
index a44b855b98d..00000000000
--- a/include/asm-sparc/ipcbuf_64.h
+++ /dev/null
@@ -1,28 +0,0 @@
1#ifndef _SPARC64_IPCBUF_H
2#define _SPARC64_IPCBUF_H
3
4/*
5 * The ipc64_perm structure for sparc64 architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 32-bit seq
11 * - 2 miscellaneous 64-bit values
12 */
13
14struct ipc64_perm
15{
16 __kernel_key_t key;
17 __kernel_uid_t uid;
18 __kernel_gid_t gid;
19 __kernel_uid_t cuid;
20 __kernel_gid_t cgid;
21 __kernel_mode_t mode;
22 unsigned short __pad1;
23 unsigned short seq;
24 unsigned long __unused1;
25 unsigned long __unused2;
26};
27
28#endif /* _SPARC64_IPCBUF_H */
diff --git a/include/asm-sparc/irq.h b/include/asm-sparc/irq.h
deleted file mode 100644
index 7af6bb4aa09..00000000000
--- a/include/asm-sparc/irq.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_IRQ_H
2#define ___ASM_SPARC_IRQ_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/irq_64.h>
5#else
6#include <asm-sparc/irq_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/irq_32.h b/include/asm-sparc/irq_32.h
deleted file mode 100644
index fe205cc444b..00000000000
--- a/include/asm-sparc/irq_32.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/* irq.h: IRQ registers on the Sparc.
2 *
3 * Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net)
4 */
5
6#ifndef _SPARC_IRQ_H
7#define _SPARC_IRQ_H
8
9#include <linux/interrupt.h>
10
11#define NR_IRQS 16
12
13#define irq_canonicalize(irq) (irq)
14
15#endif
diff --git a/include/asm-sparc/irq_64.h b/include/asm-sparc/irq_64.h
deleted file mode 100644
index 0bb9bf53174..00000000000
--- a/include/asm-sparc/irq_64.h
+++ /dev/null
@@ -1,93 +0,0 @@
1/* irq.h: IRQ registers on the 64-bit Sparc.
2 *
3 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
5 */
6
7#ifndef _SPARC64_IRQ_H
8#define _SPARC64_IRQ_H
9
10#include <linux/linkage.h>
11#include <linux/kernel.h>
12#include <linux/errno.h>
13#include <linux/interrupt.h>
14#include <asm/pil.h>
15#include <asm/ptrace.h>
16
17/* IMAP/ICLR register defines */
18#define IMAP_VALID 0x80000000UL /* IRQ Enabled */
19#define IMAP_TID_UPA 0x7c000000UL /* UPA TargetID */
20#define IMAP_TID_JBUS 0x7c000000UL /* JBUS TargetID */
21#define IMAP_TID_SHIFT 26
22#define IMAP_AID_SAFARI 0x7c000000UL /* Safari AgentID */
23#define IMAP_AID_SHIFT 26
24#define IMAP_NID_SAFARI 0x03e00000UL /* Safari NodeID */
25#define IMAP_NID_SHIFT 21
26#define IMAP_IGN 0x000007c0UL /* IRQ Group Number */
27#define IMAP_INO 0x0000003fUL /* IRQ Number */
28#define IMAP_INR 0x000007ffUL /* Full interrupt number*/
29
30#define ICLR_IDLE 0x00000000UL /* Idle state */
31#define ICLR_TRANSMIT 0x00000001UL /* Transmit state */
32#define ICLR_PENDING 0x00000003UL /* Pending state */
33
34/* The largest number of unique interrupt sources we support.
35 * If this needs to ever be larger than 255, you need to change
36 * the type of ino_bucket->virt_irq as appropriate.
37 *
38 * ino_bucket->virt_irq allocation is made during {sun4v_,}build_irq().
39 */
40#define NR_IRQS 255
41
42extern void irq_install_pre_handler(int virt_irq,
43 void (*func)(unsigned int, void *, void *),
44 void *arg1, void *arg2);
45#define irq_canonicalize(irq) (irq)
46extern unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap);
47extern unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino);
48extern unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino);
49extern unsigned int sun4v_build_msi(u32 devhandle, unsigned int *virt_irq_p,
50 unsigned int msi_devino_start,
51 unsigned int msi_devino_end);
52extern void sun4v_destroy_msi(unsigned int virt_irq);
53extern unsigned int sun4u_build_msi(u32 portid, unsigned int *virt_irq_p,
54 unsigned int msi_devino_start,
55 unsigned int msi_devino_end,
56 unsigned long imap_base,
57 unsigned long iclr_base);
58extern void sun4u_destroy_msi(unsigned int virt_irq);
59extern unsigned int sbus_build_irq(void *sbus, unsigned int ino);
60
61extern unsigned char virt_irq_alloc(unsigned int dev_handle,
62 unsigned int dev_ino);
63#ifdef CONFIG_PCI_MSI
64extern void virt_irq_free(unsigned int virt_irq);
65#endif
66
67extern void __init init_IRQ(void);
68extern void fixup_irqs(void);
69
70static inline void set_softint(unsigned long bits)
71{
72 __asm__ __volatile__("wr %0, 0x0, %%set_softint"
73 : /* No outputs */
74 : "r" (bits));
75}
76
77static inline void clear_softint(unsigned long bits)
78{
79 __asm__ __volatile__("wr %0, 0x0, %%clear_softint"
80 : /* No outputs */
81 : "r" (bits));
82}
83
84static inline unsigned long get_softint(void)
85{
86 unsigned long retval;
87
88 __asm__ __volatile__("rd %%softint, %0"
89 : "=r" (retval));
90 return retval;
91}
92
93#endif
diff --git a/include/asm-sparc/irq_regs.h b/include/asm-sparc/irq_regs.h
deleted file mode 100644
index 3dd9c0b7027..00000000000
--- a/include/asm-sparc/irq_regs.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/irq_regs.h>
diff --git a/include/asm-sparc/irqflags.h b/include/asm-sparc/irqflags.h
deleted file mode 100644
index c6402b187e2..00000000000
--- a/include/asm-sparc/irqflags.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_IRQFLAGS_H
2#define ___ASM_SPARC_IRQFLAGS_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/irqflags_64.h>
5#else
6#include <asm-sparc/irqflags_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/irqflags_32.h b/include/asm-sparc/irqflags_32.h
deleted file mode 100644
index db398fb3282..00000000000
--- a/include/asm-sparc/irqflags_32.h
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * include/asm-sparc/irqflags.h
3 *
4 * IRQ flags handling
5 *
6 * This file gets included from lowlevel asm headers too, to provide
7 * wrapped versions of the local_irq_*() APIs, based on the
8 * raw_local_irq_*() functions from the lowlevel headers.
9 */
10#ifndef _ASM_IRQFLAGS_H
11#define _ASM_IRQFLAGS_H
12
13#ifndef __ASSEMBLY__
14
15extern void raw_local_irq_restore(unsigned long);
16extern unsigned long __raw_local_irq_save(void);
17extern void raw_local_irq_enable(void);
18
19static inline unsigned long getipl(void)
20{
21 unsigned long retval;
22
23 __asm__ __volatile__("rd %%psr, %0" : "=r" (retval));
24 return retval;
25}
26
27#define raw_local_save_flags(flags) ((flags) = getipl())
28#define raw_local_irq_save(flags) ((flags) = __raw_local_irq_save())
29#define raw_local_irq_disable() ((void) __raw_local_irq_save())
30#define raw_irqs_disabled() ((getipl() & PSR_PIL) != 0)
31
32static inline int raw_irqs_disabled_flags(unsigned long flags)
33{
34 return ((flags & PSR_PIL) != 0);
35}
36
37#endif /* (__ASSEMBLY__) */
38
39#endif /* !(_ASM_IRQFLAGS_H) */
diff --git a/include/asm-sparc/irqflags_64.h b/include/asm-sparc/irqflags_64.h
deleted file mode 100644
index 024fc54d068..00000000000
--- a/include/asm-sparc/irqflags_64.h
+++ /dev/null
@@ -1,89 +0,0 @@
1/*
2 * include/asm-sparc64/irqflags.h
3 *
4 * IRQ flags handling
5 *
6 * This file gets included from lowlevel asm headers too, to provide
7 * wrapped versions of the local_irq_*() APIs, based on the
8 * raw_local_irq_*() functions from the lowlevel headers.
9 */
10#ifndef _ASM_IRQFLAGS_H
11#define _ASM_IRQFLAGS_H
12
13#ifndef __ASSEMBLY__
14
15static inline unsigned long __raw_local_save_flags(void)
16{
17 unsigned long flags;
18
19 __asm__ __volatile__(
20 "rdpr %%pil, %0"
21 : "=r" (flags)
22 );
23
24 return flags;
25}
26
27#define raw_local_save_flags(flags) \
28 do { (flags) = __raw_local_save_flags(); } while (0)
29
30static inline void raw_local_irq_restore(unsigned long flags)
31{
32 __asm__ __volatile__(
33 "wrpr %0, %%pil"
34 : /* no output */
35 : "r" (flags)
36 : "memory"
37 );
38}
39
40static inline void raw_local_irq_disable(void)
41{
42 __asm__ __volatile__(
43 "wrpr 15, %%pil"
44 : /* no outputs */
45 : /* no inputs */
46 : "memory"
47 );
48}
49
50static inline void raw_local_irq_enable(void)
51{
52 __asm__ __volatile__(
53 "wrpr 0, %%pil"
54 : /* no outputs */
55 : /* no inputs */
56 : "memory"
57 );
58}
59
60static inline int raw_irqs_disabled_flags(unsigned long flags)
61{
62 return (flags > 0);
63}
64
65static inline int raw_irqs_disabled(void)
66{
67 unsigned long flags = __raw_local_save_flags();
68
69 return raw_irqs_disabled_flags(flags);
70}
71
72/*
73 * For spinlocks, etc:
74 */
75static inline unsigned long __raw_local_irq_save(void)
76{
77 unsigned long flags = __raw_local_save_flags();
78
79 raw_local_irq_disable();
80
81 return flags;
82}
83
84#define raw_local_irq_save(flags) \
85 do { (flags) = __raw_local_irq_save(); } while (0)
86
87#endif /* (__ASSEMBLY__) */
88
89#endif /* !(_ASM_IRQFLAGS_H) */
diff --git a/include/asm-sparc/jsflash.h b/include/asm-sparc/jsflash.h
deleted file mode 100644
index 3457f29bd73..00000000000
--- a/include/asm-sparc/jsflash.h
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * jsflash.h: OS Flash SIMM support for JavaStations.
3 *
4 * Copyright (C) 1999 Pete Zaitcev
5 */
6
7#ifndef _SPARC_JSFLASH_H
8#define _SPARC_JSFLASH_H
9
10#ifndef _SPARC_TYPES_H
11#include <asm/types.h>
12#endif
13
14/*
15 * Semantics of the offset is a full address.
16 * Hardcode it or get it from probe ioctl.
17 *
18 * We use full bus address, so that we would be
19 * automatically compatible with possible future systems.
20 */
21
22#define JSFLASH_IDENT (('F'<<8)|54)
23struct jsflash_ident_arg {
24 __u64 off; /* 0x20000000 is included */
25 __u32 size;
26 char name[32]; /* With trailing zero */
27};
28
29#define JSFLASH_ERASE (('F'<<8)|55)
30/* Put 0 as argument, may be flags or sector number... */
31
32#define JSFLASH_PROGRAM (('F'<<8)|56)
33struct jsflash_program_arg {
34 __u64 data; /* char* for sparc and sparc64 */
35 __u64 off;
36 __u32 size;
37};
38
39#endif /* _SPARC_JSFLASH_H */
diff --git a/include/asm-sparc/kdebug.h b/include/asm-sparc/kdebug.h
deleted file mode 100644
index fe07d00d053..00000000000
--- a/include/asm-sparc/kdebug.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_KDEBUG_H
2#define ___ASM_SPARC_KDEBUG_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/kdebug_64.h>
5#else
6#include <asm-sparc/kdebug_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/kdebug_32.h b/include/asm-sparc/kdebug_32.h
deleted file mode 100644
index f69fe7d84b3..00000000000
--- a/include/asm-sparc/kdebug_32.h
+++ /dev/null
@@ -1,73 +0,0 @@
1/*
2 * kdebug.h: Defines and definitions for debugging the Linux kernel
3 * under various kernel debuggers.
4 *
5 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
6 */
7#ifndef _SPARC_KDEBUG_H
8#define _SPARC_KDEBUG_H
9
10#include <asm/openprom.h>
11#include <asm/vaddrs.h>
12
13/* Breakpoints are enter through trap table entry 126. So in sparc assembly
14 * if you want to drop into the debugger you do:
15 *
16 * t DEBUG_BP_TRAP
17 */
18
19#define DEBUG_BP_TRAP 126
20
21#ifndef __ASSEMBLY__
22/* The debug vector is passed in %o1 at boot time. It is a pointer to
23 * a structure in the debuggers address space. Here is its format.
24 */
25
26typedef unsigned int (*debugger_funct)(void);
27
28struct kernel_debug {
29 /* First the entry point into the debugger. You jump here
30 * to give control over to the debugger.
31 */
32 unsigned long kdebug_entry;
33 unsigned long kdebug_trapme; /* Figure out later... */
34 /* The following is the number of pages that the debugger has
35 * taken from to total pool.
36 */
37 unsigned long *kdebug_stolen_pages;
38 /* Ok, after you remap yourself and/or change the trap table
39 * from what you were left with at boot time you have to call
40 * this synchronization function so the debugger can check out
41 * what you have done.
42 */
43 debugger_funct teach_debugger;
44}; /* I think that is it... */
45
46extern struct kernel_debug *linux_dbvec;
47
48/* Use this macro in C-code to enter the debugger. */
49static inline void sp_enter_debugger(void)
50{
51 __asm__ __volatile__("jmpl %0, %%o7\n\t"
52 "nop\n\t" : :
53 "r" (linux_dbvec) : "o7", "memory");
54}
55
56#define SP_ENTER_DEBUGGER do { \
57 if((linux_dbvec!=0) && ((*(short *)linux_dbvec)!=-1)) \
58 sp_enter_debugger(); \
59 } while(0)
60
61enum die_val {
62 DIE_UNUSED,
63};
64
65#endif /* !(__ASSEMBLY__) */
66
67/* Some nice offset defines for assembler code. */
68#define KDEBUG_ENTRY_OFF 0x0
69#define KDEBUG_DUNNO_OFF 0x4
70#define KDEBUG_DUNNO2_OFF 0x8
71#define KDEBUG_TEACH_OFF 0xc
72
73#endif /* !(_SPARC_KDEBUG_H) */
diff --git a/include/asm-sparc/kdebug_64.h b/include/asm-sparc/kdebug_64.h
deleted file mode 100644
index f905b773235..00000000000
--- a/include/asm-sparc/kdebug_64.h
+++ /dev/null
@@ -1,19 +0,0 @@
1#ifndef _SPARC64_KDEBUG_H
2#define _SPARC64_KDEBUG_H
3
4struct pt_regs;
5
6extern void bad_trap(struct pt_regs *, long);
7
8/* Grossly misnamed. */
9enum die_val {
10 DIE_OOPS = 1,
11 DIE_DEBUG, /* ta 0x70 */
12 DIE_DEBUG_2, /* ta 0x71 */
13 DIE_DIE,
14 DIE_TRAP,
15 DIE_TRAP_TL1,
16 DIE_CALL,
17};
18
19#endif
diff --git a/include/asm-sparc/kgdb.h b/include/asm-sparc/kgdb.h
deleted file mode 100644
index b6ef301d05b..00000000000
--- a/include/asm-sparc/kgdb.h
+++ /dev/null
@@ -1,38 +0,0 @@
1#ifndef _SPARC_KGDB_H
2#define _SPARC_KGDB_H
3
4#ifdef CONFIG_SPARC32
5#define BUFMAX 2048
6#else
7#define BUFMAX 4096
8#endif
9
10enum regnames {
11 GDB_G0, GDB_G1, GDB_G2, GDB_G3, GDB_G4, GDB_G5, GDB_G6, GDB_G7,
12 GDB_O0, GDB_O1, GDB_O2, GDB_O3, GDB_O4, GDB_O5, GDB_SP, GDB_O7,
13 GDB_L0, GDB_L1, GDB_L2, GDB_L3, GDB_L4, GDB_L5, GDB_L6, GDB_L7,
14 GDB_I0, GDB_I1, GDB_I2, GDB_I3, GDB_I4, GDB_I5, GDB_FP, GDB_I7,
15 GDB_F0,
16 GDB_F31 = GDB_F0 + 31,
17#ifdef CONFIG_SPARC32
18 GDB_Y, GDB_PSR, GDB_WIM, GDB_TBR, GDB_PC, GDB_NPC,
19 GDB_FSR, GDB_CSR,
20#else
21 GDB_F32 = GDB_F0 + 32,
22 GDB_F62 = GDB_F32 + 15,
23 GDB_PC, GDB_NPC, GDB_STATE, GDB_FSR, GDB_FPRS, GDB_Y,
24#endif
25};
26
27#ifdef CONFIG_SPARC32
28#define NUMREGBYTES ((GDB_CSR + 1) * 4)
29#else
30#define NUMREGBYTES ((GDB_Y + 1) * 8)
31#endif
32
33extern void arch_kgdb_breakpoint(void);
34
35#define BREAK_INSTR_SIZE 4
36#define CACHE_FLUSH_IS_SAFE 1
37
38#endif /* _SPARC_KGDB_H */
diff --git a/include/asm-sparc/kmap_types.h b/include/asm-sparc/kmap_types.h
deleted file mode 100644
index 602f5e034f7..00000000000
--- a/include/asm-sparc/kmap_types.h
+++ /dev/null
@@ -1,25 +0,0 @@
1#ifndef _ASM_KMAP_TYPES_H
2#define _ASM_KMAP_TYPES_H
3
4/* Dummy header just to define km_type. None of this
5 * is actually used on sparc. -DaveM
6 */
7
8enum km_type {
9 KM_BOUNCE_READ,
10 KM_SKB_SUNRPC_DATA,
11 KM_SKB_DATA_SOFTIRQ,
12 KM_USER0,
13 KM_USER1,
14 KM_BIO_SRC_IRQ,
15 KM_BIO_DST_IRQ,
16 KM_PTE0,
17 KM_PTE1,
18 KM_IRQ0,
19 KM_IRQ1,
20 KM_SOFTIRQ0,
21 KM_SOFTIRQ1,
22 KM_TYPE_NR
23};
24
25#endif
diff --git a/include/asm-sparc/kprobes.h b/include/asm-sparc/kprobes.h
deleted file mode 100644
index 5879d71afda..00000000000
--- a/include/asm-sparc/kprobes.h
+++ /dev/null
@@ -1,49 +0,0 @@
1#ifndef _SPARC64_KPROBES_H
2#define _SPARC64_KPROBES_H
3
4#include <linux/types.h>
5#include <linux/percpu.h>
6
7typedef u32 kprobe_opcode_t;
8
9#define BREAKPOINT_INSTRUCTION 0x91d02070 /* ta 0x70 */
10#define BREAKPOINT_INSTRUCTION_2 0x91d02071 /* ta 0x71 */
11#define MAX_INSN_SIZE 2
12
13#define kretprobe_blacklist_size 0
14
15#define arch_remove_kprobe(p) do {} while (0)
16
17#define flush_insn_slot(p) \
18do { flushi(&(p)->ainsn.insn[0]); \
19 flushi(&(p)->ainsn.insn[1]); \
20} while (0)
21
22void kretprobe_trampoline(void);
23
24/* Architecture specific copy of original instruction*/
25struct arch_specific_insn {
26 /* copy of the original instruction */
27 kprobe_opcode_t insn[MAX_INSN_SIZE];
28};
29
30struct prev_kprobe {
31 struct kprobe *kp;
32 unsigned long status;
33 unsigned long orig_tnpc;
34 unsigned long orig_tstate_pil;
35};
36
37/* per-cpu kprobe control block */
38struct kprobe_ctlblk {
39 unsigned long kprobe_status;
40 unsigned long kprobe_orig_tnpc;
41 unsigned long kprobe_orig_tstate_pil;
42 struct pt_regs jprobe_saved_regs;
43 struct prev_kprobe prev_kprobe;
44};
45
46extern int kprobe_exceptions_notify(struct notifier_block *self,
47 unsigned long val, void *data);
48extern int kprobe_fault_handler(struct pt_regs *regs, int trapnr);
49#endif /* _SPARC64_KPROBES_H */
diff --git a/include/asm-sparc/ldc.h b/include/asm-sparc/ldc.h
deleted file mode 100644
index bdb524a7b81..00000000000
--- a/include/asm-sparc/ldc.h
+++ /dev/null
@@ -1,138 +0,0 @@
1#ifndef _SPARC64_LDC_H
2#define _SPARC64_LDC_H
3
4#include <asm/hypervisor.h>
5
6extern int ldom_domaining_enabled;
7extern void ldom_set_var(const char *var, const char *value);
8extern void ldom_reboot(const char *boot_command);
9extern void ldom_power_off(void);
10
11/* The event handler will be evoked when link state changes
12 * or data becomes available on the receive side.
13 *
14 * For non-RAW links, if the LDC_EVENT_RESET event arrives the
15 * driver should reset all of it's internal state and reinvoke
16 * ldc_connect() to try and bring the link up again.
17 *
18 * For RAW links, ldc_connect() is not used. Instead the driver
19 * just waits for the LDC_EVENT_UP event.
20 */
21struct ldc_channel_config {
22 void (*event)(void *arg, int event);
23
24 u32 mtu;
25 unsigned int rx_irq;
26 unsigned int tx_irq;
27 u8 mode;
28#define LDC_MODE_RAW 0x00
29#define LDC_MODE_UNRELIABLE 0x01
30#define LDC_MODE_RESERVED 0x02
31#define LDC_MODE_STREAM 0x03
32
33 u8 debug;
34#define LDC_DEBUG_HS 0x01
35#define LDC_DEBUG_STATE 0x02
36#define LDC_DEBUG_RX 0x04
37#define LDC_DEBUG_TX 0x08
38#define LDC_DEBUG_DATA 0x10
39};
40
41#define LDC_EVENT_RESET 0x01
42#define LDC_EVENT_UP 0x02
43#define LDC_EVENT_DATA_READY 0x04
44
45#define LDC_STATE_INVALID 0x00
46#define LDC_STATE_INIT 0x01
47#define LDC_STATE_BOUND 0x02
48#define LDC_STATE_READY 0x03
49#define LDC_STATE_CONNECTED 0x04
50
51struct ldc_channel;
52
53/* Allocate state for a channel. */
54extern struct ldc_channel *ldc_alloc(unsigned long id,
55 const struct ldc_channel_config *cfgp,
56 void *event_arg);
57
58/* Shut down and free state for a channel. */
59extern void ldc_free(struct ldc_channel *lp);
60
61/* Register TX and RX queues of the link with the hypervisor. */
62extern int ldc_bind(struct ldc_channel *lp, const char *name);
63
64/* For non-RAW protocols we need to complete a handshake before
65 * communication can proceed. ldc_connect() does that, if the
66 * handshake completes successfully, an LDC_EVENT_UP event will
67 * be sent up to the driver.
68 */
69extern int ldc_connect(struct ldc_channel *lp);
70extern int ldc_disconnect(struct ldc_channel *lp);
71
72extern int ldc_state(struct ldc_channel *lp);
73
74/* Read and write operations. Only valid when the link is up. */
75extern int ldc_write(struct ldc_channel *lp, const void *buf,
76 unsigned int size);
77extern int ldc_read(struct ldc_channel *lp, void *buf, unsigned int size);
78
79#define LDC_MAP_SHADOW 0x01
80#define LDC_MAP_DIRECT 0x02
81#define LDC_MAP_IO 0x04
82#define LDC_MAP_R 0x08
83#define LDC_MAP_W 0x10
84#define LDC_MAP_X 0x20
85#define LDC_MAP_RW (LDC_MAP_R | LDC_MAP_W)
86#define LDC_MAP_RWX (LDC_MAP_R | LDC_MAP_W | LDC_MAP_X)
87#define LDC_MAP_ALL 0x03f
88
89struct ldc_trans_cookie {
90 u64 cookie_addr;
91 u64 cookie_size;
92};
93
94struct scatterlist;
95extern int ldc_map_sg(struct ldc_channel *lp,
96 struct scatterlist *sg, int num_sg,
97 struct ldc_trans_cookie *cookies, int ncookies,
98 unsigned int map_perm);
99
100extern int ldc_map_single(struct ldc_channel *lp,
101 void *buf, unsigned int len,
102 struct ldc_trans_cookie *cookies, int ncookies,
103 unsigned int map_perm);
104
105extern void ldc_unmap(struct ldc_channel *lp, struct ldc_trans_cookie *cookies,
106 int ncookies);
107
108extern int ldc_copy(struct ldc_channel *lp, int copy_dir,
109 void *buf, unsigned int len, unsigned long offset,
110 struct ldc_trans_cookie *cookies, int ncookies);
111
112static inline int ldc_get_dring_entry(struct ldc_channel *lp,
113 void *buf, unsigned int len,
114 unsigned long offset,
115 struct ldc_trans_cookie *cookies,
116 int ncookies)
117{
118 return ldc_copy(lp, LDC_COPY_IN, buf, len, offset, cookies, ncookies);
119}
120
121static inline int ldc_put_dring_entry(struct ldc_channel *lp,
122 void *buf, unsigned int len,
123 unsigned long offset,
124 struct ldc_trans_cookie *cookies,
125 int ncookies)
126{
127 return ldc_copy(lp, LDC_COPY_OUT, buf, len, offset, cookies, ncookies);
128}
129
130extern void *ldc_alloc_exp_dring(struct ldc_channel *lp, unsigned int len,
131 struct ldc_trans_cookie *cookies,
132 int *ncookies, unsigned int map_perm);
133
134extern void ldc_free_exp_dring(struct ldc_channel *lp, void *buf,
135 unsigned int len,
136 struct ldc_trans_cookie *cookies, int ncookies);
137
138#endif /* _SPARC64_LDC_H */
diff --git a/include/asm-sparc/linkage.h b/include/asm-sparc/linkage.h
deleted file mode 100644
index 291c2d01c44..00000000000
--- a/include/asm-sparc/linkage.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef __ASM_LINKAGE_H
2#define __ASM_LINKAGE_H
3
4/* Nothing to see here... */
5
6#endif
diff --git a/include/asm-sparc/lmb.h b/include/asm-sparc/lmb.h
deleted file mode 100644
index 6a352cbcf52..00000000000
--- a/include/asm-sparc/lmb.h
+++ /dev/null
@@ -1,10 +0,0 @@
1#ifndef _SPARC64_LMB_H
2#define _SPARC64_LMB_H
3
4#include <asm/oplib.h>
5
6#define LMB_DBG(fmt...) prom_printf(fmt)
7
8#define LMB_REAL_LIMIT 0
9
10#endif /* !(_SPARC64_LMB_H) */
diff --git a/include/asm-sparc/local.h b/include/asm-sparc/local.h
deleted file mode 100644
index bc80815a435..00000000000
--- a/include/asm-sparc/local.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _SPARC_LOCAL_H
2#define _SPARC_LOCAL_H
3
4#include <asm-generic/local.h>
5
6#endif
diff --git a/include/asm-sparc/lsu.h b/include/asm-sparc/lsu.h
deleted file mode 100644
index 7190f8de90a..00000000000
--- a/include/asm-sparc/lsu.h
+++ /dev/null
@@ -1,19 +0,0 @@
1#ifndef _SPARC64_LSU_H
2#define _SPARC64_LSU_H
3
4#include <linux/const.h>
5
6/* LSU Control Register */
7#define LSU_CONTROL_PM _AC(0x000001fe00000000,UL) /* Phys-watchpoint byte mask*/
8#define LSU_CONTROL_VM _AC(0x00000001fe000000,UL) /* Virt-watchpoint byte mask*/
9#define LSU_CONTROL_PR _AC(0x0000000001000000,UL) /* Phys-rd watchpoint enable*/
10#define LSU_CONTROL_PW _AC(0x0000000000800000,UL) /* Phys-wr watchpoint enable*/
11#define LSU_CONTROL_VR _AC(0x0000000000400000,UL) /* Virt-rd watchpoint enable*/
12#define LSU_CONTROL_VW _AC(0x0000000000200000,UL) /* Virt-wr watchpoint enable*/
13#define LSU_CONTROL_FM _AC(0x00000000000ffff0,UL) /* Parity mask enables. */
14#define LSU_CONTROL_DM _AC(0x0000000000000008,UL) /* Data MMU enable. */
15#define LSU_CONTROL_IM _AC(0x0000000000000004,UL) /* Instruction MMU enable. */
16#define LSU_CONTROL_DC _AC(0x0000000000000002,UL) /* Data cache enable. */
17#define LSU_CONTROL_IC _AC(0x0000000000000001,UL) /* Instruction cache enable.*/
18
19#endif /* !(_SPARC64_LSU_H) */
diff --git a/include/asm-sparc/machines.h b/include/asm-sparc/machines.h
deleted file mode 100644
index c28c2f24879..00000000000
--- a/include/asm-sparc/machines.h
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * machines.h: Defines for taking apart the machine type value in the
3 * idprom and determining the kind of machine we are on.
4 *
5 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
6 */
7#ifndef _SPARC_MACHINES_H
8#define _SPARC_MACHINES_H
9
10struct Sun_Machine_Models {
11 char *name;
12 unsigned char id_machtype;
13};
14
15/* Current number of machines we know about that has an IDPROM
16 * machtype entry including one entry for the 0x80 OBP machines.
17 */
18#define NUM_SUN_MACHINES 15
19
20/* The machine type in the idprom area looks like this:
21 *
22 * ---------------
23 * | ARCH | MACH |
24 * ---------------
25 * 7 4 3 0
26 *
27 * The ARCH field determines the architecture line (sun4, sun4c, etc).
28 * The MACH field determines the machine make within that architecture.
29 */
30
31#define SM_ARCH_MASK 0xf0
32#define SM_SUN4 0x20
33#define SM_SUN4C 0x50
34#define SM_SUN4M 0x70
35#define SM_SUN4M_OBP 0x80
36
37#define SM_TYP_MASK 0x0f
38/* Sun4 machines */
39#define SM_4_260 0x01 /* Sun 4/200 series */
40#define SM_4_110 0x02 /* Sun 4/100 series */
41#define SM_4_330 0x03 /* Sun 4/300 series */
42#define SM_4_470 0x04 /* Sun 4/400 series */
43
44/* Sun4c machines Full Name - PROM NAME */
45#define SM_4C_SS1 0x01 /* Sun4c SparcStation 1 - Sun 4/60 */
46#define SM_4C_IPC 0x02 /* Sun4c SparcStation IPC - Sun 4/40 */
47#define SM_4C_SS1PLUS 0x03 /* Sun4c SparcStation 1+ - Sun 4/65 */
48#define SM_4C_SLC 0x04 /* Sun4c SparcStation SLC - Sun 4/20 */
49#define SM_4C_SS2 0x05 /* Sun4c SparcStation 2 - Sun 4/75 */
50#define SM_4C_ELC 0x06 /* Sun4c SparcStation ELC - Sun 4/25 */
51#define SM_4C_IPX 0x07 /* Sun4c SparcStation IPX - Sun 4/50 */
52
53/* Sun4m machines, these predate the OpenBoot. These values only mean
54 * something if the value in the ARCH field is SM_SUN4M, if it is
55 * SM_SUN4M_OBP then you have the following situation:
56 * 1) You either have a sun4d, a sun4e, or a recently made sun4m.
57 * 2) You have to consult OpenBoot to determine which machine this is.
58 */
59#define SM_4M_SS60 0x01 /* Sun4m SparcSystem 600 */
60#define SM_4M_SS50 0x02 /* Sun4m SparcStation 10 */
61#define SM_4M_SS40 0x03 /* Sun4m SparcStation 5 */
62
63/* Sun4d machines -- N/A */
64/* Sun4e machines -- N/A */
65/* Sun4u machines -- N/A */
66
67#endif /* !(_SPARC_MACHINES_H) */
diff --git a/include/asm-sparc/mbus.h b/include/asm-sparc/mbus.h
deleted file mode 100644
index 69f07a022ee..00000000000
--- a/include/asm-sparc/mbus.h
+++ /dev/null
@@ -1,100 +0,0 @@
1/*
2 * mbus.h: Various defines for MBUS modules.
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 */
6
7#ifndef _SPARC_MBUS_H
8#define _SPARC_MBUS_H
9
10#include <asm/ross.h> /* HyperSparc stuff */
11#include <asm/cypress.h> /* Cypress Chips */
12#include <asm/viking.h> /* Ugh, bug city... */
13
14enum mbus_module {
15 HyperSparc = 0,
16 Cypress = 1,
17 Cypress_vE = 2,
18 Cypress_vD = 3,
19 Swift_ok = 4,
20 Swift_bad_c = 5,
21 Swift_lots_o_bugs = 6,
22 Tsunami = 7,
23 Viking_12 = 8,
24 Viking_2x = 9,
25 Viking_30 = 10,
26 Viking_35 = 11,
27 Viking_new = 12,
28 TurboSparc = 13,
29 SRMMU_INVAL_MOD = 14,
30};
31
32extern enum mbus_module srmmu_modtype;
33extern unsigned int viking_rev, swift_rev, cypress_rev;
34
35/* HW Mbus module bugs we have to deal with */
36#define HWBUG_COPYBACK_BROKEN 0x00000001
37#define HWBUG_ASIFLUSH_BROKEN 0x00000002
38#define HWBUG_VACFLUSH_BITROT 0x00000004
39#define HWBUG_KERN_ACCBROKEN 0x00000008
40#define HWBUG_KERN_CBITBROKEN 0x00000010
41#define HWBUG_MODIFIED_BITROT 0x00000020
42#define HWBUG_PC_BADFAULT_ADDR 0x00000040
43#define HWBUG_SUPERSCALAR_BAD 0x00000080
44#define HWBUG_PACINIT_BITROT 0x00000100
45
46/* First the module type values. To find out which you have, just load
47 * the mmu control register from ASI_M_MMUREG alternate address space and
48 * shift the value right 28 bits.
49 */
50/* IMPL field means the company which produced the chip. */
51#define MBUS_VIKING 0x4 /* bleech, Texas Instruments Module */
52#define MBUS_LSI 0x3 /* LSI Logics */
53#define MBUS_ROSS 0x1 /* Ross is nice */
54#define MBUS_FMI 0x0 /* Fujitsu Microelectronics/Swift */
55
56/* Ross Module versions */
57#define ROSS_604_REV_CDE 0x0 /* revisions c, d, and e */
58#define ROSS_604_REV_F 0x1 /* revision f */
59#define ROSS_605 0xf /* revision a, a.1, and a.2 */
60#define ROSS_605_REV_B 0xe /* revision b */
61
62/* TI Viking Module versions */
63#define VIKING_REV_12 0x1 /* Version 1.2 or SPARCclassic's CPU */
64#define VIKING_REV_2 0x2 /* Version 2.1, 2.2, 2.3, and 2.4 */
65#define VIKING_REV_30 0x3 /* Version 3.0 */
66#define VIKING_REV_35 0x4 /* Version 3.5 */
67
68/* LSI Logics. */
69#define LSI_L64815 0x0
70
71/* Fujitsu */
72#define FMI_AURORA 0x4 /* MB8690x, a Swift module... */
73#define FMI_TURBO 0x5 /* MB86907, a TurboSparc module... */
74
75/* For multiprocessor support we need to be able to obtain the CPU id and
76 * the MBUS Module id.
77 */
78
79/* The CPU ID is encoded in the trap base register, 20 bits to the left of
80 * bit zero, with 2 bits being significant.
81 */
82#define TBR_ID_SHIFT 20
83
84static inline int get_cpuid(void)
85{
86 register int retval;
87 __asm__ __volatile__("rd %%tbr, %0\n\t"
88 "srl %0, %1, %0\n\t" :
89 "=r" (retval) :
90 "i" (TBR_ID_SHIFT));
91 return (retval & 3);
92}
93
94static inline int get_modid(void)
95{
96 return (get_cpuid() | 0x8);
97}
98
99
100#endif /* !(_SPARC_MBUS_H) */
diff --git a/include/asm-sparc/mc146818rtc.h b/include/asm-sparc/mc146818rtc.h
deleted file mode 100644
index 9ab65c21e9e..00000000000
--- a/include/asm-sparc/mc146818rtc.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_MC146818RTC_H
2#define ___ASM_SPARC_MC146818RTC_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/mc146818rtc_64.h>
5#else
6#include <asm-sparc/mc146818rtc_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/mc146818rtc_32.h b/include/asm-sparc/mc146818rtc_32.h
deleted file mode 100644
index fa7eac92658..00000000000
--- a/include/asm-sparc/mc146818rtc_32.h
+++ /dev/null
@@ -1,29 +0,0 @@
1/*
2 * Machine dependent access functions for RTC registers.
3 */
4#ifndef __ASM_SPARC_MC146818RTC_H
5#define __ASM_SPARC_MC146818RTC_H
6
7#include <asm/io.h>
8
9#ifndef RTC_PORT
10#define RTC_PORT(x) (0x70 + (x))
11#define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */
12#endif
13
14/*
15 * The yet supported machines all access the RTC index register via
16 * an ISA port access but the way to access the date register differs ...
17 */
18#define CMOS_READ(addr) ({ \
19outb_p((addr),RTC_PORT(0)); \
20inb_p(RTC_PORT(1)); \
21})
22#define CMOS_WRITE(val, addr) ({ \
23outb_p((addr),RTC_PORT(0)); \
24outb_p((val),RTC_PORT(1)); \
25})
26
27#define RTC_IRQ 8
28
29#endif /* __ASM_SPARC_MC146818RTC_H */
diff --git a/include/asm-sparc/mc146818rtc_64.h b/include/asm-sparc/mc146818rtc_64.h
deleted file mode 100644
index e9c0fcc25c6..00000000000
--- a/include/asm-sparc/mc146818rtc_64.h
+++ /dev/null
@@ -1,34 +0,0 @@
1/*
2 * Machine dependent access functions for RTC registers.
3 */
4#ifndef __ASM_SPARC64_MC146818RTC_H
5#define __ASM_SPARC64_MC146818RTC_H
6
7#include <asm/io.h>
8
9#ifndef RTC_PORT
10#ifdef CONFIG_PCI
11extern unsigned long ds1287_regs;
12#else
13#define ds1287_regs (0UL)
14#endif
15#define RTC_PORT(x) (ds1287_regs + (x))
16#define RTC_ALWAYS_BCD 0
17#endif
18
19/*
20 * The yet supported machines all access the RTC index register via
21 * an ISA port access but the way to access the date register differs ...
22 */
23#define CMOS_READ(addr) ({ \
24outb_p((addr),RTC_PORT(0)); \
25inb_p(RTC_PORT(1)); \
26})
27#define CMOS_WRITE(val, addr) ({ \
28outb_p((addr),RTC_PORT(0)); \
29outb_p((val),RTC_PORT(1)); \
30})
31
32#define RTC_IRQ 8
33
34#endif /* __ASM_SPARC64_MC146818RTC_H */
diff --git a/include/asm-sparc/mdesc.h b/include/asm-sparc/mdesc.h
deleted file mode 100644
index 1acc7272e53..00000000000
--- a/include/asm-sparc/mdesc.h
+++ /dev/null
@@ -1,78 +0,0 @@
1#ifndef _SPARC64_MDESC_H
2#define _SPARC64_MDESC_H
3
4#include <linux/types.h>
5#include <linux/cpumask.h>
6#include <asm/prom.h>
7
8struct mdesc_handle;
9
10/* Machine description operations are to be surrounded by grab and
11 * release calls. The mdesc_handle returned from the grab is
12 * the first argument to all of the operational calls that work
13 * on mdescs.
14 */
15extern struct mdesc_handle *mdesc_grab(void);
16extern void mdesc_release(struct mdesc_handle *);
17
18#define MDESC_NODE_NULL (~(u64)0)
19
20extern u64 mdesc_node_by_name(struct mdesc_handle *handle,
21 u64 from_node, const char *name);
22#define mdesc_for_each_node_by_name(__hdl, __node, __name) \
23 for (__node = mdesc_node_by_name(__hdl, MDESC_NODE_NULL, __name); \
24 (__node) != MDESC_NODE_NULL; \
25 __node = mdesc_node_by_name(__hdl, __node, __name))
26
27/* Access to property values returned from mdesc_get_property() are
28 * only valid inside of a mdesc_grab()/mdesc_release() sequence.
29 * Once mdesc_release() is called, the memory backed up by these
30 * pointers may reference freed up memory.
31 *
32 * Therefore callers must make copies of any property values
33 * they need.
34 *
35 * These same rules apply to mdesc_node_name().
36 */
37extern const void *mdesc_get_property(struct mdesc_handle *handle,
38 u64 node, const char *name, int *lenp);
39extern const char *mdesc_node_name(struct mdesc_handle *hp, u64 node);
40
41/* MD arc iteration, the standard sequence is:
42 *
43 * unsigned long arc;
44 * mdesc_for_each_arc(arc, handle, node, MDESC_ARC_TYPE_{FWD,BACK}) {
45 * unsigned long target = mdesc_arc_target(handle, arc);
46 * ...
47 * }
48 */
49
50#define MDESC_ARC_TYPE_FWD "fwd"
51#define MDESC_ARC_TYPE_BACK "back"
52
53extern u64 mdesc_next_arc(struct mdesc_handle *handle, u64 from,
54 const char *arc_type);
55#define mdesc_for_each_arc(__arc, __hdl, __node, __type) \
56 for (__arc = mdesc_next_arc(__hdl, __node, __type); \
57 (__arc) != MDESC_NODE_NULL; \
58 __arc = mdesc_next_arc(__hdl, __arc, __type))
59
60extern u64 mdesc_arc_target(struct mdesc_handle *hp, u64 arc);
61
62extern void mdesc_update(void);
63
64struct mdesc_notifier_client {
65 void (*add)(struct mdesc_handle *handle, u64 node);
66 void (*remove)(struct mdesc_handle *handle, u64 node);
67
68 const char *node_name;
69 struct mdesc_notifier_client *next;
70};
71
72extern void mdesc_register_notifier(struct mdesc_notifier_client *client);
73
74extern void mdesc_fill_in_cpu_data(cpumask_t mask);
75
76extern void sun4v_mdesc_init(void);
77
78#endif
diff --git a/include/asm-sparc/memreg.h b/include/asm-sparc/memreg.h
deleted file mode 100644
index 845ad2b3918..00000000000
--- a/include/asm-sparc/memreg.h
+++ /dev/null
@@ -1,51 +0,0 @@
1#ifndef _SPARC_MEMREG_H
2#define _SPARC_MEMREG_H
3/* memreg.h: Definitions of the values found in the synchronous
4 * and asynchronous memory error registers when a fault
5 * occurs on the sun4c.
6 *
7 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
8 */
9
10/* First the synchronous error codes, these are usually just
11 * normal page faults.
12 */
13
14#define SUN4C_SYNC_WDRESET 0x0001 /* watchdog reset */
15#define SUN4C_SYNC_SIZE 0x0002 /* bad access size? whuz this? */
16#define SUN4C_SYNC_PARITY 0x0008 /* bad ram chips caused a parity error */
17#define SUN4C_SYNC_SBUS 0x0010 /* the SBUS had some problems... */
18#define SUN4C_SYNC_NOMEM 0x0020 /* translation to non-existent ram */
19#define SUN4C_SYNC_PROT 0x0040 /* access violated pte protections */
20#define SUN4C_SYNC_NPRESENT 0x0080 /* pte said that page was not present */
21#define SUN4C_SYNC_BADWRITE 0x8000 /* while writing something went bogus */
22
23#define SUN4C_SYNC_BOLIXED \
24 (SUN4C_SYNC_WDRESET | SUN4C_SYNC_SIZE | SUN4C_SYNC_SBUS | \
25 SUN4C_SYNC_NOMEM | SUN4C_SYNC_PARITY)
26
27/* Now the asynchronous error codes, these are almost always produced
28 * by the cache writing things back to memory and getting a bad translation.
29 * Bad DVMA transactions can cause these faults too.
30 */
31
32#define SUN4C_ASYNC_BADDVMA 0x0010 /* error during DVMA access */
33#define SUN4C_ASYNC_NOMEM 0x0020 /* write back pointed to bad phys addr */
34#define SUN4C_ASYNC_BADWB 0x0080 /* write back points to non-present page */
35
36/* Memory parity error register with associated bit constants. */
37#ifndef __ASSEMBLY__
38extern __volatile__ unsigned long __iomem *sun4c_memerr_reg;
39#endif
40
41#define SUN4C_MPE_ERROR 0x80 /* Parity error detected. (ro) */
42#define SUN4C_MPE_MULTI 0x40 /* Multiple parity errors detected. (ro) */
43#define SUN4C_MPE_TEST 0x20 /* Write inverse parity. (rw) */
44#define SUN4C_MPE_CHECK 0x10 /* Enable parity checking. (rw) */
45#define SUN4C_MPE_ERR00 0x08 /* Parity error in bits 0-7. (ro) */
46#define SUN4C_MPE_ERR08 0x04 /* Parity error in bits 8-15. (ro) */
47#define SUN4C_MPE_ERR16 0x02 /* Parity error in bits 16-23. (ro) */
48#define SUN4C_MPE_ERR24 0x01 /* Parity error in bits 24-31. (ro) */
49#define SUN4C_MPE_ERRS 0x0F /* Bit mask for the error bits. (ro) */
50
51#endif /* !(_SPARC_MEMREG_H) */
diff --git a/include/asm-sparc/mman.h b/include/asm-sparc/mman.h
deleted file mode 100644
index fdfbbf0a473..00000000000
--- a/include/asm-sparc/mman.h
+++ /dev/null
@@ -1,31 +0,0 @@
1#ifndef __SPARC_MMAN_H__
2#define __SPARC_MMAN_H__
3
4#include <asm-generic/mman.h>
5
6/* SunOS'ified... */
7
8#define MAP_RENAME MAP_ANONYMOUS /* In SunOS terminology */
9#define MAP_NORESERVE 0x40 /* don't reserve swap pages */
10#define MAP_INHERIT 0x80 /* SunOS doesn't do this, but... */
11#define MAP_LOCKED 0x100 /* lock the mapping */
12#define _MAP_NEW 0x80000000 /* Binary compatibility is fun... */
13
14#define MAP_GROWSDOWN 0x0200 /* stack-like segment */
15#define MAP_DENYWRITE 0x0800 /* ETXTBSY */
16#define MAP_EXECUTABLE 0x1000 /* mark it as an executable */
17
18#define MCL_CURRENT 0x2000 /* lock all currently mapped pages */
19#define MCL_FUTURE 0x4000 /* lock all additions to address space */
20
21#define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */
22#define MAP_NONBLOCK 0x10000 /* do not block on IO */
23
24#ifdef __KERNEL__
25#ifndef __ASSEMBLY__
26#define arch_mmap_check(addr,len,flags) sparc_mmap_check(addr,len)
27int sparc_mmap_check(unsigned long addr, unsigned long len);
28#endif
29#endif
30
31#endif /* __SPARC_MMAN_H__ */
diff --git a/include/asm-sparc/mmu.h b/include/asm-sparc/mmu.h
deleted file mode 100644
index ee66bf6dcbd..00000000000
--- a/include/asm-sparc/mmu.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_MMU_H
2#define ___ASM_SPARC_MMU_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/mmu_64.h>
5#else
6#include <asm-sparc/mmu_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/mmu_32.h b/include/asm-sparc/mmu_32.h
deleted file mode 100644
index ccd36d26615..00000000000
--- a/include/asm-sparc/mmu_32.h
+++ /dev/null
@@ -1,7 +0,0 @@
1#ifndef __MMU_H
2#define __MMU_H
3
4/* Default "unsigned long" context */
5typedef unsigned long mm_context_t;
6
7#endif
diff --git a/include/asm-sparc/mmu_64.h b/include/asm-sparc/mmu_64.h
deleted file mode 100644
index 9067dc50053..00000000000
--- a/include/asm-sparc/mmu_64.h
+++ /dev/null
@@ -1,123 +0,0 @@
1#ifndef __MMU_H
2#define __MMU_H
3
4#include <linux/const.h>
5#include <asm/page.h>
6#include <asm/hypervisor.h>
7
8#define CTX_NR_BITS 13
9
10#define TAG_CONTEXT_BITS ((_AC(1,UL) << CTX_NR_BITS) - _AC(1,UL))
11
12/* UltraSPARC-III+ and later have a feature whereby you can
13 * select what page size the various Data-TLB instances in the
14 * chip. In order to gracefully support this, we put the version
15 * field in a spot outside of the areas of the context register
16 * where this parameter is specified.
17 */
18#define CTX_VERSION_SHIFT 22
19#define CTX_VERSION_MASK ((~0UL) << CTX_VERSION_SHIFT)
20
21#define CTX_PGSZ_8KB _AC(0x0,UL)
22#define CTX_PGSZ_64KB _AC(0x1,UL)
23#define CTX_PGSZ_512KB _AC(0x2,UL)
24#define CTX_PGSZ_4MB _AC(0x3,UL)
25#define CTX_PGSZ_BITS _AC(0x7,UL)
26#define CTX_PGSZ0_NUC_SHIFT 61
27#define CTX_PGSZ1_NUC_SHIFT 58
28#define CTX_PGSZ0_SHIFT 16
29#define CTX_PGSZ1_SHIFT 19
30#define CTX_PGSZ_MASK ((CTX_PGSZ_BITS << CTX_PGSZ0_SHIFT) | \
31 (CTX_PGSZ_BITS << CTX_PGSZ1_SHIFT))
32
33#if defined(CONFIG_SPARC64_PAGE_SIZE_8KB)
34#define CTX_PGSZ_BASE CTX_PGSZ_8KB
35#elif defined(CONFIG_SPARC64_PAGE_SIZE_64KB)
36#define CTX_PGSZ_BASE CTX_PGSZ_64KB
37#else
38#error No page size specified in kernel configuration
39#endif
40
41#if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
42#define CTX_PGSZ_HUGE CTX_PGSZ_4MB
43#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
44#define CTX_PGSZ_HUGE CTX_PGSZ_512KB
45#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
46#define CTX_PGSZ_HUGE CTX_PGSZ_64KB
47#endif
48
49#define CTX_PGSZ_KERN CTX_PGSZ_4MB
50
51/* Thus, when running on UltraSPARC-III+ and later, we use the following
52 * PRIMARY_CONTEXT register values for the kernel context.
53 */
54#define CTX_CHEETAH_PLUS_NUC \
55 ((CTX_PGSZ_KERN << CTX_PGSZ0_NUC_SHIFT) | \
56 (CTX_PGSZ_BASE << CTX_PGSZ1_NUC_SHIFT))
57
58#define CTX_CHEETAH_PLUS_CTX0 \
59 ((CTX_PGSZ_KERN << CTX_PGSZ0_SHIFT) | \
60 (CTX_PGSZ_BASE << CTX_PGSZ1_SHIFT))
61
62/* If you want "the TLB context number" use CTX_NR_MASK. If you
63 * want "the bits I program into the context registers" use
64 * CTX_HW_MASK.
65 */
66#define CTX_NR_MASK TAG_CONTEXT_BITS
67#define CTX_HW_MASK (CTX_NR_MASK | CTX_PGSZ_MASK)
68
69#define CTX_FIRST_VERSION ((_AC(1,UL) << CTX_VERSION_SHIFT) + _AC(1,UL))
70#define CTX_VALID(__ctx) \
71 (!(((__ctx.sparc64_ctx_val) ^ tlb_context_cache) & CTX_VERSION_MASK))
72#define CTX_HWBITS(__ctx) ((__ctx.sparc64_ctx_val) & CTX_HW_MASK)
73#define CTX_NRBITS(__ctx) ((__ctx.sparc64_ctx_val) & CTX_NR_MASK)
74
75#ifndef __ASSEMBLY__
76
77#define TSB_ENTRY_ALIGNMENT 16
78
79struct tsb {
80 unsigned long tag;
81 unsigned long pte;
82} __attribute__((aligned(TSB_ENTRY_ALIGNMENT)));
83
84extern void __tsb_insert(unsigned long ent, unsigned long tag, unsigned long pte);
85extern void tsb_flush(unsigned long ent, unsigned long tag);
86extern void tsb_init(struct tsb *tsb, unsigned long size);
87
88struct tsb_config {
89 struct tsb *tsb;
90 unsigned long tsb_rss_limit;
91 unsigned long tsb_nentries;
92 unsigned long tsb_reg_val;
93 unsigned long tsb_map_vaddr;
94 unsigned long tsb_map_pte;
95};
96
97#define MM_TSB_BASE 0
98
99#ifdef CONFIG_HUGETLB_PAGE
100#define MM_TSB_HUGE 1
101#define MM_NUM_TSBS 2
102#else
103#define MM_NUM_TSBS 1
104#endif
105
106typedef struct {
107 spinlock_t lock;
108 unsigned long sparc64_ctx_val;
109 unsigned long huge_pte_count;
110 struct tsb_config tsb_block[MM_NUM_TSBS];
111 struct hv_tsb_descr tsb_descr[MM_NUM_TSBS];
112} mm_context_t;
113
114#endif /* !__ASSEMBLY__ */
115
116#define TSB_CONFIG_TSB 0x00
117#define TSB_CONFIG_RSS_LIMIT 0x08
118#define TSB_CONFIG_NENTRIES 0x10
119#define TSB_CONFIG_REG_VAL 0x18
120#define TSB_CONFIG_MAP_VADDR 0x20
121#define TSB_CONFIG_MAP_PTE 0x28
122
123#endif /* __MMU_H */
diff --git a/include/asm-sparc/mmu_context.h b/include/asm-sparc/mmu_context.h
deleted file mode 100644
index e14efb9532f..00000000000
--- a/include/asm-sparc/mmu_context.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_MMU_CONTEXT_H
2#define ___ASM_SPARC_MMU_CONTEXT_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/mmu_context_64.h>
5#else
6#include <asm-sparc/mmu_context_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/mmu_context_32.h b/include/asm-sparc/mmu_context_32.h
deleted file mode 100644
index 671a997b9e6..00000000000
--- a/include/asm-sparc/mmu_context_32.h
+++ /dev/null
@@ -1,42 +0,0 @@
1#ifndef __SPARC_MMU_CONTEXT_H
2#define __SPARC_MMU_CONTEXT_H
3
4#include <asm/btfixup.h>
5
6#ifndef __ASSEMBLY__
7
8#include <asm-generic/mm_hooks.h>
9
10static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
11{
12}
13
14/*
15 * Initialize a new mmu context. This is invoked when a new
16 * address space instance (unique or shared) is instantiated.
17 */
18#define init_new_context(tsk, mm) (((mm)->context = NO_CONTEXT), 0)
19
20/*
21 * Destroy a dead context. This occurs when mmput drops the
22 * mm_users count to zero, the mmaps have been released, and
23 * all the page tables have been flushed. Our job is to destroy
24 * any remaining processor-specific state.
25 */
26BTFIXUPDEF_CALL(void, destroy_context, struct mm_struct *)
27
28#define destroy_context(mm) BTFIXUP_CALL(destroy_context)(mm)
29
30/* Switch the current MM context. */
31BTFIXUPDEF_CALL(void, switch_mm, struct mm_struct *, struct mm_struct *, struct task_struct *)
32
33#define switch_mm(old_mm, mm, tsk) BTFIXUP_CALL(switch_mm)(old_mm, mm, tsk)
34
35#define deactivate_mm(tsk,mm) do { } while (0)
36
37/* Activate a new MM instance for the current task. */
38#define activate_mm(active_mm, mm) switch_mm((active_mm), (mm), NULL)
39
40#endif /* !(__ASSEMBLY__) */
41
42#endif /* !(__SPARC_MMU_CONTEXT_H) */
diff --git a/include/asm-sparc/mmu_context_64.h b/include/asm-sparc/mmu_context_64.h
deleted file mode 100644
index 5693ab48260..00000000000
--- a/include/asm-sparc/mmu_context_64.h
+++ /dev/null
@@ -1,155 +0,0 @@
1#ifndef __SPARC64_MMU_CONTEXT_H
2#define __SPARC64_MMU_CONTEXT_H
3
4/* Derived heavily from Linus's Alpha/AXP ASN code... */
5
6#ifndef __ASSEMBLY__
7
8#include <linux/spinlock.h>
9#include <asm/system.h>
10#include <asm/spitfire.h>
11#include <asm-generic/mm_hooks.h>
12
13static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
14{
15}
16
17extern spinlock_t ctx_alloc_lock;
18extern unsigned long tlb_context_cache;
19extern unsigned long mmu_context_bmap[];
20
21extern void get_new_mmu_context(struct mm_struct *mm);
22#ifdef CONFIG_SMP
23extern void smp_new_mmu_context_version(void);
24#else
25#define smp_new_mmu_context_version() do { } while (0)
26#endif
27
28extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
29extern void destroy_context(struct mm_struct *mm);
30
31extern void __tsb_context_switch(unsigned long pgd_pa,
32 struct tsb_config *tsb_base,
33 struct tsb_config *tsb_huge,
34 unsigned long tsb_descr_pa);
35
36static inline void tsb_context_switch(struct mm_struct *mm)
37{
38 __tsb_context_switch(__pa(mm->pgd),
39 &mm->context.tsb_block[0],
40#ifdef CONFIG_HUGETLB_PAGE
41 (mm->context.tsb_block[1].tsb ?
42 &mm->context.tsb_block[1] :
43 NULL)
44#else
45 NULL
46#endif
47 , __pa(&mm->context.tsb_descr[0]));
48}
49
50extern void tsb_grow(struct mm_struct *mm, unsigned long tsb_index, unsigned long mm_rss);
51#ifdef CONFIG_SMP
52extern void smp_tsb_sync(struct mm_struct *mm);
53#else
54#define smp_tsb_sync(__mm) do { } while (0)
55#endif
56
57/* Set MMU context in the actual hardware. */
58#define load_secondary_context(__mm) \
59 __asm__ __volatile__( \
60 "\n661: stxa %0, [%1] %2\n" \
61 " .section .sun4v_1insn_patch, \"ax\"\n" \
62 " .word 661b\n" \
63 " stxa %0, [%1] %3\n" \
64 " .previous\n" \
65 " flush %%g6\n" \
66 : /* No outputs */ \
67 : "r" (CTX_HWBITS((__mm)->context)), \
68 "r" (SECONDARY_CONTEXT), "i" (ASI_DMMU), "i" (ASI_MMU))
69
70extern void __flush_tlb_mm(unsigned long, unsigned long);
71
72/* Switch the current MM context. Interrupts are disabled. */
73static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, struct task_struct *tsk)
74{
75 unsigned long ctx_valid, flags;
76 int cpu;
77
78 if (unlikely(mm == &init_mm))
79 return;
80
81 spin_lock_irqsave(&mm->context.lock, flags);
82 ctx_valid = CTX_VALID(mm->context);
83 if (!ctx_valid)
84 get_new_mmu_context(mm);
85
86 /* We have to be extremely careful here or else we will miss
87 * a TSB grow if we switch back and forth between a kernel
88 * thread and an address space which has it's TSB size increased
89 * on another processor.
90 *
91 * It is possible to play some games in order to optimize the
92 * switch, but the safest thing to do is to unconditionally
93 * perform the secondary context load and the TSB context switch.
94 *
95 * For reference the bad case is, for address space "A":
96 *
97 * CPU 0 CPU 1
98 * run address space A
99 * set cpu0's bits in cpu_vm_mask
100 * switch to kernel thread, borrow
101 * address space A via entry_lazy_tlb
102 * run address space A
103 * set cpu1's bit in cpu_vm_mask
104 * flush_tlb_pending()
105 * reset cpu_vm_mask to just cpu1
106 * TSB grow
107 * run address space A
108 * context was valid, so skip
109 * TSB context switch
110 *
111 * At that point cpu0 continues to use a stale TSB, the one from
112 * before the TSB grow performed on cpu1. cpu1 did not cross-call
113 * cpu0 to update it's TSB because at that point the cpu_vm_mask
114 * only had cpu1 set in it.
115 */
116 load_secondary_context(mm);
117 tsb_context_switch(mm);
118
119 /* Any time a processor runs a context on an address space
120 * for the first time, we must flush that context out of the
121 * local TLB.
122 */
123 cpu = smp_processor_id();
124 if (!ctx_valid || !cpu_isset(cpu, mm->cpu_vm_mask)) {
125 cpu_set(cpu, mm->cpu_vm_mask);
126 __flush_tlb_mm(CTX_HWBITS(mm->context),
127 SECONDARY_CONTEXT);
128 }
129 spin_unlock_irqrestore(&mm->context.lock, flags);
130}
131
132#define deactivate_mm(tsk,mm) do { } while (0)
133
134/* Activate a new MM instance for the current task. */
135static inline void activate_mm(struct mm_struct *active_mm, struct mm_struct *mm)
136{
137 unsigned long flags;
138 int cpu;
139
140 spin_lock_irqsave(&mm->context.lock, flags);
141 if (!CTX_VALID(mm->context))
142 get_new_mmu_context(mm);
143 cpu = smp_processor_id();
144 if (!cpu_isset(cpu, mm->cpu_vm_mask))
145 cpu_set(cpu, mm->cpu_vm_mask);
146
147 load_secondary_context(mm);
148 __flush_tlb_mm(CTX_HWBITS(mm->context), SECONDARY_CONTEXT);
149 tsb_context_switch(mm);
150 spin_unlock_irqrestore(&mm->context.lock, flags);
151}
152
153#endif /* !(__ASSEMBLY__) */
154
155#endif /* !(__SPARC64_MMU_CONTEXT_H) */
diff --git a/include/asm-sparc/mmzone.h b/include/asm-sparc/mmzone.h
deleted file mode 100644
index ebf5986c12e..00000000000
--- a/include/asm-sparc/mmzone.h
+++ /dev/null
@@ -1,17 +0,0 @@
1#ifndef _SPARC64_MMZONE_H
2#define _SPARC64_MMZONE_H
3
4#ifdef CONFIG_NEED_MULTIPLE_NODES
5
6extern struct pglist_data *node_data[];
7
8#define NODE_DATA(nid) (node_data[nid])
9#define node_start_pfn(nid) (NODE_DATA(nid)->node_start_pfn)
10#define node_end_pfn(nid) (NODE_DATA(nid)->node_end_pfn)
11
12extern int numa_cpu_lookup_table[];
13extern cpumask_t numa_cpumask_lookup_table[];
14
15#endif /* CONFIG_NEED_MULTIPLE_NODES */
16
17#endif /* _SPARC64_MMZONE_H */
diff --git a/include/asm-sparc/module.h b/include/asm-sparc/module.h
deleted file mode 100644
index 516138fe681..00000000000
--- a/include/asm-sparc/module.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_MODULE_H
2#define ___ASM_SPARC_MODULE_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/module_64.h>
5#else
6#include <asm-sparc/module_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/module_32.h b/include/asm-sparc/module_32.h
deleted file mode 100644
index cbd9e67b0c0..00000000000
--- a/include/asm-sparc/module_32.h
+++ /dev/null
@@ -1,7 +0,0 @@
1#ifndef _ASM_SPARC_MODULE_H
2#define _ASM_SPARC_MODULE_H
3struct mod_arch_specific { };
4#define Elf_Shdr Elf32_Shdr
5#define Elf_Sym Elf32_Sym
6#define Elf_Ehdr Elf32_Ehdr
7#endif /* _ASM_SPARC_MODULE_H */
diff --git a/include/asm-sparc/module_64.h b/include/asm-sparc/module_64.h
deleted file mode 100644
index 3d77ba46578..00000000000
--- a/include/asm-sparc/module_64.h
+++ /dev/null
@@ -1,7 +0,0 @@
1#ifndef _ASM_SPARC64_MODULE_H
2#define _ASM_SPARC64_MODULE_H
3struct mod_arch_specific { };
4#define Elf_Shdr Elf64_Shdr
5#define Elf_Sym Elf64_Sym
6#define Elf_Ehdr Elf64_Ehdr
7#endif /* _ASM_SPARC64_MODULE_H */
diff --git a/include/asm-sparc/mostek.h b/include/asm-sparc/mostek.h
deleted file mode 100644
index 5b9f7fec7ee..00000000000
--- a/include/asm-sparc/mostek.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_MOSTEK_H
2#define ___ASM_SPARC_MOSTEK_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/mostek_64.h>
5#else
6#include <asm-sparc/mostek_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/mostek_32.h b/include/asm-sparc/mostek_32.h
deleted file mode 100644
index a99590c4c50..00000000000
--- a/include/asm-sparc/mostek_32.h
+++ /dev/null
@@ -1,171 +0,0 @@
1/*
2 * mostek.h: Describes the various Mostek time of day clock registers.
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
6 * Added intersil code 05/25/98 Chris Davis (cdavis@cois.on.ca)
7 */
8
9#ifndef _SPARC_MOSTEK_H
10#define _SPARC_MOSTEK_H
11
12#include <asm/idprom.h>
13#include <asm/io.h>
14
15/* M48T02 Register Map (adapted from Sun NVRAM/Hostid FAQ)
16 *
17 * Data
18 * Address Function
19 * Bit 7 Bit 6 Bit 5 Bit 4Bit 3 Bit 2 Bit 1 Bit 0
20 * 7ff - - - - - - - - Year 00-99
21 * 7fe 0 0 0 - - - - - Month 01-12
22 * 7fd 0 0 - - - - - - Date 01-31
23 * 7fc 0 FT 0 0 0 - - - Day 01-07
24 * 7fb KS 0 - - - - - - Hours 00-23
25 * 7fa 0 - - - - - - - Minutes 00-59
26 * 7f9 ST - - - - - - - Seconds 00-59
27 * 7f8 W R S - - - - - Control
28 *
29 * * ST is STOP BIT
30 * * W is WRITE BIT
31 * * R is READ BIT
32 * * S is SIGN BIT
33 * * FT is FREQ TEST BIT
34 * * KS is KICK START BIT
35 */
36
37/* The Mostek 48t02 real time clock and NVRAM chip. The registers
38 * other than the control register are in binary coded decimal. Some
39 * control bits also live outside the control register.
40 */
41#define mostek_read(_addr) readb(_addr)
42#define mostek_write(_addr,_val) writeb(_val, _addr)
43#define MOSTEK_EEPROM 0x0000UL
44#define MOSTEK_IDPROM 0x07d8UL
45#define MOSTEK_CREG 0x07f8UL
46#define MOSTEK_SEC 0x07f9UL
47#define MOSTEK_MIN 0x07faUL
48#define MOSTEK_HOUR 0x07fbUL
49#define MOSTEK_DOW 0x07fcUL
50#define MOSTEK_DOM 0x07fdUL
51#define MOSTEK_MONTH 0x07feUL
52#define MOSTEK_YEAR 0x07ffUL
53
54struct mostek48t02 {
55 volatile char eeprom[2008]; /* This is the eeprom, don't touch! */
56 struct idprom idprom; /* The idprom lives here. */
57 volatile unsigned char creg; /* Control register */
58 volatile unsigned char sec; /* Seconds (0-59) */
59 volatile unsigned char min; /* Minutes (0-59) */
60 volatile unsigned char hour; /* Hour (0-23) */
61 volatile unsigned char dow; /* Day of the week (1-7) */
62 volatile unsigned char dom; /* Day of the month (1-31) */
63 volatile unsigned char month; /* Month of year (1-12) */
64 volatile unsigned char year; /* Year (0-99) */
65};
66
67extern spinlock_t mostek_lock;
68extern void __iomem *mstk48t02_regs;
69
70/* Control register values. */
71#define MSTK_CREG_WRITE 0x80 /* Must set this before placing values. */
72#define MSTK_CREG_READ 0x40 /* Stop updates to allow a clean read. */
73#define MSTK_CREG_SIGN 0x20 /* Slow/speed clock in calibration mode. */
74
75/* Control bits that live in the other registers. */
76#define MSTK_STOP 0x80 /* Stop the clock oscillator. (sec) */
77#define MSTK_KICK_START 0x80 /* Kick start the clock chip. (hour) */
78#define MSTK_FREQ_TEST 0x40 /* Frequency test mode. (day) */
79
80#define MSTK_YEAR_ZERO 1968 /* If year reg has zero, it is 1968. */
81#define MSTK_CVT_YEAR(yr) ((yr) + MSTK_YEAR_ZERO)
82
83/* Masks that define how much space each value takes up. */
84#define MSTK_SEC_MASK 0x7f
85#define MSTK_MIN_MASK 0x7f
86#define MSTK_HOUR_MASK 0x3f
87#define MSTK_DOW_MASK 0x07
88#define MSTK_DOM_MASK 0x3f
89#define MSTK_MONTH_MASK 0x1f
90#define MSTK_YEAR_MASK 0xffU
91
92/* Binary coded decimal conversion macros. */
93#define MSTK_REGVAL_TO_DECIMAL(x) (((x) & 0x0F) + 0x0A * ((x) >> 0x04))
94#define MSTK_DECIMAL_TO_REGVAL(x) ((((x) / 0x0A) << 0x04) + ((x) % 0x0A))
95
96/* Generic register set and get macros for internal use. */
97#define MSTK_GET(regs,var,mask) (MSTK_REGVAL_TO_DECIMAL(((struct mostek48t02 *)regs)->var & MSTK_ ## mask ## _MASK))
98#define MSTK_SET(regs,var,value,mask) do { ((struct mostek48t02 *)regs)->var &= ~(MSTK_ ## mask ## _MASK); ((struct mostek48t02 *)regs)->var |= MSTK_DECIMAL_TO_REGVAL(value) & (MSTK_ ## mask ## _MASK); } while (0)
99
100/* Macros to make register access easier on our fingers. These give you
101 * the decimal value of the register requested if applicable. You pass
102 * the a pointer to a 'struct mostek48t02'.
103 */
104#define MSTK_REG_CREG(regs) (((struct mostek48t02 *)regs)->creg)
105#define MSTK_REG_SEC(regs) MSTK_GET(regs,sec,SEC)
106#define MSTK_REG_MIN(regs) MSTK_GET(regs,min,MIN)
107#define MSTK_REG_HOUR(regs) MSTK_GET(regs,hour,HOUR)
108#define MSTK_REG_DOW(regs) MSTK_GET(regs,dow,DOW)
109#define MSTK_REG_DOM(regs) MSTK_GET(regs,dom,DOM)
110#define MSTK_REG_MONTH(regs) MSTK_GET(regs,month,MONTH)
111#define MSTK_REG_YEAR(regs) MSTK_GET(regs,year,YEAR)
112
113#define MSTK_SET_REG_SEC(regs,value) MSTK_SET(regs,sec,value,SEC)
114#define MSTK_SET_REG_MIN(regs,value) MSTK_SET(regs,min,value,MIN)
115#define MSTK_SET_REG_HOUR(regs,value) MSTK_SET(regs,hour,value,HOUR)
116#define MSTK_SET_REG_DOW(regs,value) MSTK_SET(regs,dow,value,DOW)
117#define MSTK_SET_REG_DOM(regs,value) MSTK_SET(regs,dom,value,DOM)
118#define MSTK_SET_REG_MONTH(regs,value) MSTK_SET(regs,month,value,MONTH)
119#define MSTK_SET_REG_YEAR(regs,value) MSTK_SET(regs,year,value,YEAR)
120
121
122/* The Mostek 48t08 clock chip. Found on Sun4m's I think. It has the
123 * same (basically) layout of the 48t02 chip except for the extra
124 * NVRAM on board (8 KB against the 48t02's 2 KB).
125 */
126struct mostek48t08 {
127 char offset[6*1024]; /* Magic things may be here, who knows? */
128 struct mostek48t02 regs; /* Here is what we are interested in. */
129};
130
131#ifdef CONFIG_SUN4
132enum sparc_clock_type { MSTK48T02, MSTK48T08, \
133INTERSIL, MSTK_INVALID };
134#else
135enum sparc_clock_type { MSTK48T02, MSTK48T08, \
136MSTK_INVALID };
137#endif
138
139#ifdef CONFIG_SUN4
140/* intersil on a sun 4/260 code data from harris doc */
141struct intersil_dt {
142 volatile unsigned char int_csec;
143 volatile unsigned char int_hour;
144 volatile unsigned char int_min;
145 volatile unsigned char int_sec;
146 volatile unsigned char int_month;
147 volatile unsigned char int_day;
148 volatile unsigned char int_year;
149 volatile unsigned char int_dow;
150};
151
152struct intersil {
153 struct intersil_dt clk;
154 struct intersil_dt cmp;
155 volatile unsigned char int_intr_reg;
156 volatile unsigned char int_cmd_reg;
157};
158
159#define INTERSIL_STOP 0x0
160#define INTERSIL_START 0x8
161#define INTERSIL_INTR_DISABLE 0x0
162#define INTERSIL_INTR_ENABLE 0x10
163#define INTERSIL_32K 0x0
164#define INTERSIL_NORMAL 0x0
165#define INTERSIL_24H 0x4
166#define INTERSIL_INT_100HZ 0x2
167
168/* end of intersil info */
169#endif
170
171#endif /* !(_SPARC_MOSTEK_H) */
diff --git a/include/asm-sparc/mostek_64.h b/include/asm-sparc/mostek_64.h
deleted file mode 100644
index c5652de2ace..00000000000
--- a/include/asm-sparc/mostek_64.h
+++ /dev/null
@@ -1,143 +0,0 @@
1/* mostek.h: Describes the various Mostek time of day clock registers.
2 *
3 * Copyright (C) 1995 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
5 */
6
7#ifndef _SPARC64_MOSTEK_H
8#define _SPARC64_MOSTEK_H
9
10#include <asm/idprom.h>
11
12/* M48T02 Register Map (adapted from Sun NVRAM/Hostid FAQ)
13 *
14 * Data
15 * Address Function
16 * Bit 7 Bit 6 Bit 5 Bit 4Bit 3 Bit 2 Bit 1 Bit 0
17 * 7ff - - - - - - - - Year 00-99
18 * 7fe 0 0 0 - - - - - Month 01-12
19 * 7fd 0 0 - - - - - - Date 01-31
20 * 7fc 0 FT 0 0 0 - - - Day 01-07
21 * 7fb KS 0 - - - - - - Hours 00-23
22 * 7fa 0 - - - - - - - Minutes 00-59
23 * 7f9 ST - - - - - - - Seconds 00-59
24 * 7f8 W R S - - - - - Control
25 *
26 * * ST is STOP BIT
27 * * W is WRITE BIT
28 * * R is READ BIT
29 * * S is SIGN BIT
30 * * FT is FREQ TEST BIT
31 * * KS is KICK START BIT
32 */
33
34/* The Mostek 48t02 real time clock and NVRAM chip. The registers
35 * other than the control register are in binary coded decimal. Some
36 * control bits also live outside the control register.
37 *
38 * We now deal with physical addresses for I/O to the chip. -DaveM
39 */
40static inline u8 mostek_read(void __iomem *addr)
41{
42 u8 ret;
43
44 __asm__ __volatile__("lduba [%1] %2, %0"
45 : "=r" (ret)
46 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
47 return ret;
48}
49
50static inline void mostek_write(void __iomem *addr, u8 val)
51{
52 __asm__ __volatile__("stba %0, [%1] %2"
53 : /* no outputs */
54 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
55}
56
57#define MOSTEK_EEPROM 0x0000UL
58#define MOSTEK_IDPROM 0x07d8UL
59#define MOSTEK_CREG 0x07f8UL
60#define MOSTEK_SEC 0x07f9UL
61#define MOSTEK_MIN 0x07faUL
62#define MOSTEK_HOUR 0x07fbUL
63#define MOSTEK_DOW 0x07fcUL
64#define MOSTEK_DOM 0x07fdUL
65#define MOSTEK_MONTH 0x07feUL
66#define MOSTEK_YEAR 0x07ffUL
67
68extern spinlock_t mostek_lock;
69extern void __iomem *mstk48t02_regs;
70
71/* Control register values. */
72#define MSTK_CREG_WRITE 0x80 /* Must set this before placing values. */
73#define MSTK_CREG_READ 0x40 /* Stop updates to allow a clean read. */
74#define MSTK_CREG_SIGN 0x20 /* Slow/speed clock in calibration mode. */
75
76/* Control bits that live in the other registers. */
77#define MSTK_STOP 0x80 /* Stop the clock oscillator. (sec) */
78#define MSTK_KICK_START 0x80 /* Kick start the clock chip. (hour) */
79#define MSTK_FREQ_TEST 0x40 /* Frequency test mode. (day) */
80
81#define MSTK_YEAR_ZERO 1968 /* If year reg has zero, it is 1968. */
82#define MSTK_CVT_YEAR(yr) ((yr) + MSTK_YEAR_ZERO)
83
84/* Masks that define how much space each value takes up. */
85#define MSTK_SEC_MASK 0x7f
86#define MSTK_MIN_MASK 0x7f
87#define MSTK_HOUR_MASK 0x3f
88#define MSTK_DOW_MASK 0x07
89#define MSTK_DOM_MASK 0x3f
90#define MSTK_MONTH_MASK 0x1f
91#define MSTK_YEAR_MASK 0xffU
92
93/* Binary coded decimal conversion macros. */
94#define MSTK_REGVAL_TO_DECIMAL(x) (((x) & 0x0F) + 0x0A * ((x) >> 0x04))
95#define MSTK_DECIMAL_TO_REGVAL(x) ((((x) / 0x0A) << 0x04) + ((x) % 0x0A))
96
97/* Generic register set and get macros for internal use. */
98#define MSTK_GET(regs,name) \
99 (MSTK_REGVAL_TO_DECIMAL(mostek_read(regs + MOSTEK_ ## name) & MSTK_ ## name ## _MASK))
100#define MSTK_SET(regs,name,value) \
101do { u8 __val = mostek_read(regs + MOSTEK_ ## name); \
102 __val &= ~(MSTK_ ## name ## _MASK); \
103 __val |= (MSTK_DECIMAL_TO_REGVAL(value) & \
104 (MSTK_ ## name ## _MASK)); \
105 mostek_write(regs + MOSTEK_ ## name, __val); \
106} while(0)
107
108/* Macros to make register access easier on our fingers. These give you
109 * the decimal value of the register requested if applicable. You pass
110 * the a pointer to a 'struct mostek48t02'.
111 */
112#define MSTK_REG_CREG(regs) (mostek_read((regs) + MOSTEK_CREG))
113#define MSTK_REG_SEC(regs) MSTK_GET(regs,SEC)
114#define MSTK_REG_MIN(regs) MSTK_GET(regs,MIN)
115#define MSTK_REG_HOUR(regs) MSTK_GET(regs,HOUR)
116#define MSTK_REG_DOW(regs) MSTK_GET(regs,DOW)
117#define MSTK_REG_DOM(regs) MSTK_GET(regs,DOM)
118#define MSTK_REG_MONTH(regs) MSTK_GET(regs,MONTH)
119#define MSTK_REG_YEAR(regs) MSTK_GET(regs,YEAR)
120
121#define MSTK_SET_REG_SEC(regs,value) MSTK_SET(regs,SEC,value)
122#define MSTK_SET_REG_MIN(regs,value) MSTK_SET(regs,MIN,value)
123#define MSTK_SET_REG_HOUR(regs,value) MSTK_SET(regs,HOUR,value)
124#define MSTK_SET_REG_DOW(regs,value) MSTK_SET(regs,DOW,value)
125#define MSTK_SET_REG_DOM(regs,value) MSTK_SET(regs,DOM,value)
126#define MSTK_SET_REG_MONTH(regs,value) MSTK_SET(regs,MONTH,value)
127#define MSTK_SET_REG_YEAR(regs,value) MSTK_SET(regs,YEAR,value)
128
129
130/* The Mostek 48t08 clock chip. Found on Sun4m's I think. It has the
131 * same (basically) layout of the 48t02 chip except for the extra
132 * NVRAM on board (8 KB against the 48t02's 2 KB).
133 */
134#define MOSTEK_48T08_OFFSET 0x0000UL /* Lower NVRAM portions */
135#define MOSTEK_48T08_48T02 0x1800UL /* Offset to 48T02 chip */
136
137/* SUN5 systems usually have 48t59 model clock chipsets. But we keep the older
138 * clock chip definitions around just in case.
139 */
140#define MOSTEK_48T59_OFFSET 0x0000UL /* Lower NVRAM portions */
141#define MOSTEK_48T59_48T02 0x1800UL /* Offset to 48T02 chip */
142
143#endif /* !(_SPARC64_MOSTEK_H) */
diff --git a/include/asm-sparc/mpmbox.h b/include/asm-sparc/mpmbox.h
deleted file mode 100644
index f8423039b24..00000000000
--- a/include/asm-sparc/mpmbox.h
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * mpmbox.h: Interface and defines for the OpenProm mailbox
3 * facilities for MP machines under Linux.
4 *
5 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
6 */
7
8#ifndef _SPARC_MPMBOX_H
9#define _SPARC_MPMBOX_H
10
11/* The prom allocates, for each CPU on the machine an unsigned
12 * byte in physical ram. You probe the device tree prom nodes
13 * for these values. The purpose of this byte is to be able to
14 * pass messages from one cpu to another.
15 */
16
17/* These are the main message types we have to look for in our
18 * Cpu mailboxes, based upon these values we decide what course
19 * of action to take.
20 */
21
22/* The CPU is executing code in the kernel. */
23#define MAILBOX_ISRUNNING 0xf0
24
25/* Another CPU called romvec->pv_exit(), you should call
26 * prom_stopcpu() when you see this in your mailbox.
27 */
28#define MAILBOX_EXIT 0xfb
29
30/* Another CPU called romvec->pv_enter(), you should call
31 * prom_cpuidle() when this is seen.
32 */
33#define MAILBOX_GOSPIN 0xfc
34
35/* Another CPU has hit a breakpoint either into kadb or the prom
36 * itself. Just like MAILBOX_GOSPIN, you should call prom_cpuidle()
37 * at this point.
38 */
39#define MAILBOX_BPT_SPIN 0xfd
40
41/* Oh geese, some other nitwit got a damn watchdog reset. The party's
42 * over so go call prom_stopcpu().
43 */
44#define MAILBOX_WDOG_STOP 0xfe
45
46#ifndef __ASSEMBLY__
47
48/* Handy macro's to determine a cpu's state. */
49
50/* Is the cpu still in Power On Self Test? */
51#define MBOX_POST_P(letter) ((letter) >= 0x00 && (letter) <= 0x7f)
52
53/* Is the cpu at the 'ok' prompt of the PROM? */
54#define MBOX_PROMPROMPT_P(letter) ((letter) >= 0x80 && (letter) <= 0x8f)
55
56/* Is the cpu spinning in the PROM? */
57#define MBOX_PROMSPIN_P(letter) ((letter) >= 0x90 && (letter) <= 0xef)
58
59/* Sanity check... This is junk mail, throw it out. */
60#define MBOX_BOGON_P(letter) ((letter) >= 0xf1 && (letter) <= 0xfa)
61
62/* Is the cpu actively running an application/kernel-code? */
63#define MBOX_RUNNING_P(letter) ((letter) == MAILBOX_ISRUNNING)
64
65#endif /* !(__ASSEMBLY__) */
66
67#endif /* !(_SPARC_MPMBOX_H) */
diff --git a/include/asm-sparc/msgbuf.h b/include/asm-sparc/msgbuf.h
deleted file mode 100644
index efc7cbe9788..00000000000
--- a/include/asm-sparc/msgbuf.h
+++ /dev/null
@@ -1,38 +0,0 @@
1#ifndef _SPARC_MSGBUF_H
2#define _SPARC_MSGBUF_H
3
4/*
5 * The msqid64_ds structure for sparc64 architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 64-bit time_t to solve y2038 problem
11 * - 2 miscellaneous 32-bit values
12 */
13
14#if defined(__sparc__) && defined(__arch64__)
15# define PADDING(x)
16#else
17# define PADDING(x) unsigned int x;
18#endif
19
20
21struct msqid64_ds {
22 struct ipc64_perm msg_perm;
23 PADDING(__pad1)
24 __kernel_time_t msg_stime; /* last msgsnd time */
25 PADDING(__pad2)
26 __kernel_time_t msg_rtime; /* last msgrcv time */
27 PADDING(__pad3)
28 __kernel_time_t msg_ctime; /* last change time */
29 unsigned long msg_cbytes; /* current number of bytes on queue */
30 unsigned long msg_qnum; /* number of messages in queue */
31 unsigned long msg_qbytes; /* max number of bytes on queue */
32 __kernel_pid_t msg_lspid; /* pid of last msgsnd */
33 __kernel_pid_t msg_lrpid; /* last receive pid */
34 unsigned long __unused1;
35 unsigned long __unused2;
36};
37#undef PADDING
38#endif /* _SPARC_MSGBUF_H */
diff --git a/include/asm-sparc/msi.h b/include/asm-sparc/msi.h
deleted file mode 100644
index 724ca566705..00000000000
--- a/include/asm-sparc/msi.h
+++ /dev/null
@@ -1,31 +0,0 @@
1/*
2 * msi.h: Defines specific to the MBus - Sbus - Interface.
3 *
4 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
6 */
7
8#ifndef _SPARC_MSI_H
9#define _SPARC_MSI_H
10
11/*
12 * Locations of MSI Registers.
13 */
14#define MSI_MBUS_ARBEN 0xe0001008 /* MBus Arbiter Enable register */
15
16/*
17 * Useful bits in the MSI Registers.
18 */
19#define MSI_ASYNC_MODE 0x80000000 /* Operate the MSI asynchronously */
20
21
22static inline void msi_set_sync(void)
23{
24 __asm__ __volatile__ ("lda [%0] %1, %%g3\n\t"
25 "andn %%g3, %2, %%g3\n\t"
26 "sta %%g3, [%0] %1\n\t" : :
27 "r" (MSI_MBUS_ARBEN),
28 "i" (ASI_M_CTL), "r" (MSI_ASYNC_MODE) : "g3");
29}
30
31#endif /* !(_SPARC_MSI_H) */
diff --git a/include/asm-sparc/mutex.h b/include/asm-sparc/mutex.h
deleted file mode 100644
index 458c1f7fbc1..00000000000
--- a/include/asm-sparc/mutex.h
+++ /dev/null
@@ -1,9 +0,0 @@
1/*
2 * Pull in the generic implementation for the mutex fastpath.
3 *
4 * TODO: implement optimized primitives instead, or leave the generic
5 * implementation in place, or pick the atomic_xchg() based generic
6 * implementation. (see asm-generic/mutex-xchg.h for details)
7 */
8
9#include <asm-generic/mutex-dec.h>
diff --git a/include/asm-sparc/mxcc.h b/include/asm-sparc/mxcc.h
deleted file mode 100644
index c0517bd05bd..00000000000
--- a/include/asm-sparc/mxcc.h
+++ /dev/null
@@ -1,137 +0,0 @@
1/*
2 * mxcc.h: Definitions of the Viking MXCC registers
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 */
6
7#ifndef _SPARC_MXCC_H
8#define _SPARC_MXCC_H
9
10/* These registers are accessed through ASI 0x2. */
11#define MXCC_DATSTREAM 0x1C00000 /* Data stream register */
12#define MXCC_SRCSTREAM 0x1C00100 /* Source stream register */
13#define MXCC_DESSTREAM 0x1C00200 /* Destination stream register */
14#define MXCC_RMCOUNT 0x1C00300 /* Count of references and misses */
15#define MXCC_STEST 0x1C00804 /* Internal self-test */
16#define MXCC_CREG 0x1C00A04 /* Control register */
17#define MXCC_SREG 0x1C00B00 /* Status register */
18#define MXCC_RREG 0x1C00C04 /* Reset register */
19#define MXCC_EREG 0x1C00E00 /* Error code register */
20#define MXCC_PREG 0x1C00F04 /* Address port register */
21
22/* Some MXCC constants. */
23#define MXCC_STREAM_SIZE 0x20 /* Size in bytes of one stream r/w */
24
25/* The MXCC Control Register:
26 *
27 * ----------------------------------------------------------------------
28 * | | RRC | RSV |PRE|MCE|PARE|ECE|RSV|
29 * ----------------------------------------------------------------------
30 * 31 10 9 8-6 5 4 3 2 1-0
31 *
32 * RRC: Controls what you read from MXCC_RMCOUNT reg.
33 * 0=Misses 1=References
34 * PRE: Prefetch enable
35 * MCE: Multiple Command Enable
36 * PARE: Parity enable
37 * ECE: External cache enable
38 */
39
40#define MXCC_CTL_RRC 0x00000200
41#define MXCC_CTL_PRE 0x00000020
42#define MXCC_CTL_MCE 0x00000010
43#define MXCC_CTL_PARE 0x00000008
44#define MXCC_CTL_ECE 0x00000004
45
46/* The MXCC Error Register:
47 *
48 * --------------------------------------------------------
49 * |ME| RSV|CE|PEW|PEE|ASE|EIV| MOPC|ECODE|PRIV|RSV|HPADDR|
50 * --------------------------------------------------------
51 * 31 30 29 28 27 26 25 24-15 14-7 6 5-3 2-0
52 *
53 * ME: Multiple Errors have occurred
54 * CE: Cache consistency Error
55 * PEW: Parity Error during a Write operation
56 * PEE: Parity Error involving the External cache
57 * ASE: ASynchronous Error
58 * EIV: This register is toast
59 * MOPC: MXCC Operation Code for instance causing error
60 * ECODE: The Error CODE
61 * PRIV: A privileged mode error? 0=no 1=yes
62 * HPADDR: High PhysicalADDRess bits (35-32)
63 */
64
65#define MXCC_ERR_ME 0x80000000
66#define MXCC_ERR_CE 0x20000000
67#define MXCC_ERR_PEW 0x10000000
68#define MXCC_ERR_PEE 0x08000000
69#define MXCC_ERR_ASE 0x04000000
70#define MXCC_ERR_EIV 0x02000000
71#define MXCC_ERR_MOPC 0x01FF8000
72#define MXCC_ERR_ECODE 0x00007F80
73#define MXCC_ERR_PRIV 0x00000040
74#define MXCC_ERR_HPADDR 0x0000000f
75
76/* The MXCC Port register:
77 *
78 * -----------------------------------------------------
79 * | | MID | |
80 * -----------------------------------------------------
81 * 31 21 20-18 17 0
82 *
83 * MID: The moduleID of the cpu your read this from.
84 */
85
86#ifndef __ASSEMBLY__
87
88static inline void mxcc_set_stream_src(unsigned long *paddr)
89{
90 unsigned long data0 = paddr[0];
91 unsigned long data1 = paddr[1];
92
93 __asm__ __volatile__ ("or %%g0, %0, %%g2\n\t"
94 "or %%g0, %1, %%g3\n\t"
95 "stda %%g2, [%2] %3\n\t" : :
96 "r" (data0), "r" (data1),
97 "r" (MXCC_SRCSTREAM),
98 "i" (ASI_M_MXCC) : "g2", "g3");
99}
100
101static inline void mxcc_set_stream_dst(unsigned long *paddr)
102{
103 unsigned long data0 = paddr[0];
104 unsigned long data1 = paddr[1];
105
106 __asm__ __volatile__ ("or %%g0, %0, %%g2\n\t"
107 "or %%g0, %1, %%g3\n\t"
108 "stda %%g2, [%2] %3\n\t" : :
109 "r" (data0), "r" (data1),
110 "r" (MXCC_DESSTREAM),
111 "i" (ASI_M_MXCC) : "g2", "g3");
112}
113
114static inline unsigned long mxcc_get_creg(void)
115{
116 unsigned long mxcc_control;
117
118 __asm__ __volatile__("set 0xffffffff, %%g2\n\t"
119 "set 0xffffffff, %%g3\n\t"
120 "stda %%g2, [%1] %2\n\t"
121 "lda [%3] %2, %0\n\t" :
122 "=r" (mxcc_control) :
123 "r" (MXCC_EREG), "i" (ASI_M_MXCC),
124 "r" (MXCC_CREG) : "g2", "g3");
125 return mxcc_control;
126}
127
128static inline void mxcc_set_creg(unsigned long mxcc_control)
129{
130 __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
131 "r" (mxcc_control), "r" (MXCC_CREG),
132 "i" (ASI_M_MXCC));
133}
134
135#endif /* !__ASSEMBLY__ */
136
137#endif /* !(_SPARC_MXCC_H) */
diff --git a/include/asm-sparc/ns87303.h b/include/asm-sparc/ns87303.h
deleted file mode 100644
index 686defe6aaa..00000000000
--- a/include/asm-sparc/ns87303.h
+++ /dev/null
@@ -1,118 +0,0 @@
1/* ns87303.h: Configuration Register Description for the
2 * National Semiconductor PC87303 (SuperIO).
3 *
4 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
5 */
6
7#ifndef _SPARC_NS87303_H
8#define _SPARC_NS87303_H 1
9
10/*
11 * Control Register Index Values
12 */
13#define FER 0x00
14#define FAR 0x01
15#define PTR 0x02
16#define FCR 0x03
17#define PCR 0x04
18#define KRR 0x05
19#define PMC 0x06
20#define TUP 0x07
21#define SID 0x08
22#define ASC 0x09
23#define CS0CF0 0x0a
24#define CS0CF1 0x0b
25#define CS1CF0 0x0c
26#define CS1CF1 0x0d
27
28/* Function Enable Register (FER) bits */
29#define FER_EDM 0x10 /* Encoded Drive and Motor pin information */
30
31/* Function Address Register (FAR) bits */
32#define FAR_LPT_MASK 0x03
33#define FAR_LPTB 0x00
34#define FAR_LPTA 0x01
35#define FAR_LPTC 0x02
36
37/* Power and Test Register (PTR) bits */
38#define PTR_LPTB_IRQ7 0x08
39#define PTR_LEVEL_IRQ 0x80 /* When not ECP/EPP: Use level IRQ */
40#define PTR_LPT_REG_DIR 0x80 /* When ECP/EPP: LPT CTR controlls direction */
41 /* of the parallel port */
42
43/* Function Control Register (FCR) bits */
44#define FCR_LDE 0x10 /* Logical Drive Exchange */
45#define FCR_ZWS_ENA 0x20 /* Enable short host read/write in ECP/EPP */
46
47/* Printer Control Register (PCR) bits */
48#define PCR_EPP_ENABLE 0x01
49#define PCR_EPP_IEEE 0x02 /* Enable EPP Version 1.9 (IEEE 1284) */
50#define PCR_ECP_ENABLE 0x04
51#define PCR_ECP_CLK_ENA 0x08 /* If 0 ECP Clock is stopped on Power down */
52#define PCR_IRQ_POLAR 0x20 /* If 0 IRQ is level high or negative pulse, */
53 /* if 1 polarity is inverted */
54#define PCR_IRQ_ODRAIN 0x40 /* If 1, IRQ is open drain */
55
56/* Tape UARTs and Parallel Port Config Register (TUP) bits */
57#define TUP_EPP_TIMO 0x02 /* Enable EPP timeout IRQ */
58
59/* Advanced SuperIO Config Register (ASC) bits */
60#define ASC_LPT_IRQ7 0x01 /* Always use IRQ7 for LPT */
61#define ASC_DRV2_SEL 0x02 /* Logical Drive Exchange controlled by TDR */
62
63#define FER_RESERVED 0x00
64#define FAR_RESERVED 0x00
65#define PTR_RESERVED 0x73
66#define FCR_RESERVED 0xc4
67#define PCR_RESERVED 0x10
68#define KRR_RESERVED 0x00
69#define PMC_RESERVED 0x98
70#define TUP_RESERVED 0xfb
71#define SIP_RESERVED 0x00
72#define ASC_RESERVED 0x18
73#define CS0CF0_RESERVED 0x00
74#define CS0CF1_RESERVED 0x08
75#define CS1CF0_RESERVED 0x00
76#define CS1CF1_RESERVED 0x08
77
78#ifdef __KERNEL__
79
80#include <linux/spinlock.h>
81
82#include <asm/system.h>
83#include <asm/io.h>
84
85extern spinlock_t ns87303_lock;
86
87static inline int ns87303_modify(unsigned long port, unsigned int index,
88 unsigned char clr, unsigned char set)
89{
90 static unsigned char reserved[] = {
91 FER_RESERVED, FAR_RESERVED, PTR_RESERVED, FCR_RESERVED,
92 PCR_RESERVED, KRR_RESERVED, PMC_RESERVED, TUP_RESERVED,
93 SIP_RESERVED, ASC_RESERVED, CS0CF0_RESERVED, CS0CF1_RESERVED,
94 CS1CF0_RESERVED, CS1CF1_RESERVED
95 };
96 unsigned long flags;
97 unsigned char value;
98
99 if (index > 0x0d)
100 return -EINVAL;
101
102 spin_lock_irqsave(&ns87303_lock, flags);
103
104 outb(index, port);
105 value = inb(port + 1);
106 value &= ~(reserved[index] | clr);
107 value |= set;
108 outb(value, port + 1);
109 outb(value, port + 1);
110
111 spin_unlock_irqrestore(&ns87303_lock, flags);
112
113 return 0;
114}
115
116#endif /* __KERNEL__ */
117
118#endif /* !(_SPARC_NS87303_H) */
diff --git a/include/asm-sparc/obio.h b/include/asm-sparc/obio.h
deleted file mode 100644
index 1a7544ceb57..00000000000
--- a/include/asm-sparc/obio.h
+++ /dev/null
@@ -1,249 +0,0 @@
1/*
2 * obio.h: Some useful locations in 0xFXXXXXXXX PA obio space on sun4d.
3 *
4 * Copyright (C) 1997 Jakub Jelinek <jj@sunsite.mff.cuni.cz>
5 */
6
7#ifndef _SPARC_OBIO_H
8#define _SPARC_OBIO_H
9
10#include <asm/asi.h>
11
12/* This weird monster likes to use the very upper parts of
13 36bit PA for these things :) */
14
15/* CSR space (for each XDBUS)
16 * ------------------------------------------------------------------------
17 * | 0xFE | DEVID | | XDBUS ID | |
18 * ------------------------------------------------------------------------
19 * 35 28 27 20 19 10 9 8 7 0
20 */
21
22#define CSR_BASE_ADDR 0xe0000000
23#define CSR_CPU_SHIFT (32 - 4 - 5)
24#define CSR_XDBUS_SHIFT 8
25
26#define CSR_BASE(cpu) (((CSR_BASE_ADDR >> CSR_CPU_SHIFT) + cpu) << CSR_CPU_SHIFT)
27
28/* ECSR space (not for each XDBUS)
29 * ------------------------------------------------------------------------
30 * | 0xF | DEVID[7:1] | |
31 * ------------------------------------------------------------------------
32 * 35 32 31 25 24 0
33 */
34
35#define ECSR_BASE_ADDR 0x00000000
36#define ECSR_CPU_SHIFT (32 - 5)
37#define ECSR_DEV_SHIFT (32 - 8)
38
39#define ECSR_BASE(cpu) ((cpu) << ECSR_CPU_SHIFT)
40#define ECSR_DEV_BASE(devid) ((devid) << ECSR_DEV_SHIFT)
41
42/* Bus Watcher */
43#define BW_LOCAL_BASE 0xfff00000
44
45#define BW_CID 0x00000000
46#define BW_DBUS_CTRL 0x00000008
47#define BW_DBUS_DATA 0x00000010
48#define BW_CTRL 0x00001000
49#define BW_INTR_TABLE 0x00001040
50#define BW_INTR_TABLE_CLEAR 0x00001080
51#define BW_PRESCALER 0x000010c0
52#define BW_PTIMER_LIMIT 0x00002000
53#define BW_PTIMER_COUNTER2 0x00002004
54#define BW_PTIMER_NDLIMIT 0x00002008
55#define BW_PTIMER_CTRL 0x0000200c
56#define BW_PTIMER_COUNTER 0x00002010
57#define BW_TIMER_LIMIT 0x00003000
58#define BW_TIMER_COUNTER2 0x00003004
59#define BW_TIMER_NDLIMIT 0x00003008
60#define BW_TIMER_CTRL 0x0000300c
61#define BW_TIMER_COUNTER 0x00003010
62
63/* BW Control */
64#define BW_CTRL_USER_TIMER 0x00000004 /* Is User Timer Free run enabled */
65
66/* Boot Bus */
67#define BB_LOCAL_BASE 0xf0000000
68
69#define BB_STAT1 0x00100000
70#define BB_STAT2 0x00120000
71#define BB_STAT3 0x00140000
72#define BB_LEDS 0x002e0000
73
74/* Bits in BB_STAT2 */
75#define BB_STAT2_AC_INTR 0x04 /* Aiee! 5ms and power is gone... */
76#define BB_STAT2_TMP_INTR 0x10 /* My Penguins are burning. Are you able to smell it? */
77#define BB_STAT2_FAN_INTR 0x20 /* My fan refuses to work */
78#define BB_STAT2_PWR_INTR 0x40 /* On SC2000, one of the two ACs died. Ok, we go on... */
79#define BB_STAT2_MASK (BB_STAT2_AC_INTR|BB_STAT2_TMP_INTR|BB_STAT2_FAN_INTR|BB_STAT2_PWR_INTR)
80
81/* Cache Controller */
82#define CC_BASE 0x1F00000
83#define CC_DATSTREAM 0x1F00000 /* Data stream register */
84#define CC_DATSIZE 0x1F0003F /* Size */
85#define CC_SRCSTREAM 0x1F00100 /* Source stream register */
86#define CC_DESSTREAM 0x1F00200 /* Destination stream register */
87#define CC_RMCOUNT 0x1F00300 /* Count of references and misses */
88#define CC_IPEN 0x1F00406 /* Pending Interrupts */
89#define CC_IMSK 0x1F00506 /* Interrupt Mask */
90#define CC_ICLR 0x1F00606 /* Clear pending Interrupts */
91#define CC_IGEN 0x1F00704 /* Generate Interrupt register */
92#define CC_STEST 0x1F00804 /* Internal self-test */
93#define CC_CREG 0x1F00A04 /* Control register */
94#define CC_SREG 0x1F00B00 /* Status register */
95#define CC_RREG 0x1F00C04 /* Reset register */
96#define CC_EREG 0x1F00E00 /* Error code register */
97#define CC_CID 0x1F00F04 /* Component ID */
98
99#ifndef __ASSEMBLY__
100
101static inline int bw_get_intr_mask(int sbus_level)
102{
103 int mask;
104
105 __asm__ __volatile__ ("lduha [%1] %2, %0" :
106 "=r" (mask) :
107 "r" (BW_LOCAL_BASE + BW_INTR_TABLE + (sbus_level << 3)),
108 "i" (ASI_M_CTL));
109 return mask;
110}
111
112static inline void bw_clear_intr_mask(int sbus_level, int mask)
113{
114 __asm__ __volatile__ ("stha %0, [%1] %2" : :
115 "r" (mask),
116 "r" (BW_LOCAL_BASE + BW_INTR_TABLE_CLEAR + (sbus_level << 3)),
117 "i" (ASI_M_CTL));
118}
119
120static inline unsigned bw_get_prof_limit(int cpu)
121{
122 unsigned limit;
123
124 __asm__ __volatile__ ("lda [%1] %2, %0" :
125 "=r" (limit) :
126 "r" (CSR_BASE(cpu) + BW_PTIMER_LIMIT),
127 "i" (ASI_M_CTL));
128 return limit;
129}
130
131static inline void bw_set_prof_limit(int cpu, unsigned limit)
132{
133 __asm__ __volatile__ ("sta %0, [%1] %2" : :
134 "r" (limit),
135 "r" (CSR_BASE(cpu) + BW_PTIMER_LIMIT),
136 "i" (ASI_M_CTL));
137}
138
139static inline unsigned bw_get_ctrl(int cpu)
140{
141 unsigned ctrl;
142
143 __asm__ __volatile__ ("lda [%1] %2, %0" :
144 "=r" (ctrl) :
145 "r" (CSR_BASE(cpu) + BW_CTRL),
146 "i" (ASI_M_CTL));
147 return ctrl;
148}
149
150static inline void bw_set_ctrl(int cpu, unsigned ctrl)
151{
152 __asm__ __volatile__ ("sta %0, [%1] %2" : :
153 "r" (ctrl),
154 "r" (CSR_BASE(cpu) + BW_CTRL),
155 "i" (ASI_M_CTL));
156}
157
158extern unsigned char cpu_leds[32];
159
160static inline void show_leds(int cpuid)
161{
162 cpuid &= 0x1e;
163 __asm__ __volatile__ ("stba %0, [%1] %2" : :
164 "r" ((cpu_leds[cpuid] << 4) | cpu_leds[cpuid+1]),
165 "r" (ECSR_BASE(cpuid) | BB_LEDS),
166 "i" (ASI_M_CTL));
167}
168
169static inline unsigned cc_get_ipen(void)
170{
171 unsigned pending;
172
173 __asm__ __volatile__ ("lduha [%1] %2, %0" :
174 "=r" (pending) :
175 "r" (CC_IPEN),
176 "i" (ASI_M_MXCC));
177 return pending;
178}
179
180static inline void cc_set_iclr(unsigned clear)
181{
182 __asm__ __volatile__ ("stha %0, [%1] %2" : :
183 "r" (clear),
184 "r" (CC_ICLR),
185 "i" (ASI_M_MXCC));
186}
187
188static inline unsigned cc_get_imsk(void)
189{
190 unsigned mask;
191
192 __asm__ __volatile__ ("lduha [%1] %2, %0" :
193 "=r" (mask) :
194 "r" (CC_IMSK),
195 "i" (ASI_M_MXCC));
196 return mask;
197}
198
199static inline void cc_set_imsk(unsigned mask)
200{
201 __asm__ __volatile__ ("stha %0, [%1] %2" : :
202 "r" (mask),
203 "r" (CC_IMSK),
204 "i" (ASI_M_MXCC));
205}
206
207static inline unsigned cc_get_imsk_other(int cpuid)
208{
209 unsigned mask;
210
211 __asm__ __volatile__ ("lduha [%1] %2, %0" :
212 "=r" (mask) :
213 "r" (ECSR_BASE(cpuid) | CC_IMSK),
214 "i" (ASI_M_CTL));
215 return mask;
216}
217
218static inline void cc_set_imsk_other(int cpuid, unsigned mask)
219{
220 __asm__ __volatile__ ("stha %0, [%1] %2" : :
221 "r" (mask),
222 "r" (ECSR_BASE(cpuid) | CC_IMSK),
223 "i" (ASI_M_CTL));
224}
225
226static inline void cc_set_igen(unsigned gen)
227{
228 __asm__ __volatile__ ("sta %0, [%1] %2" : :
229 "r" (gen),
230 "r" (CC_IGEN),
231 "i" (ASI_M_MXCC));
232}
233
234/* +-------+-------------+-----------+------------------------------------+
235 * | bcast | devid | sid | levels mask |
236 * +-------+-------------+-----------+------------------------------------+
237 * 31 30 23 22 15 14 0
238 */
239#define IGEN_MESSAGE(bcast, devid, sid, levels) \
240 (((bcast) << 31) | ((devid) << 23) | ((sid) << 15) | (levels))
241
242static inline void sun4d_send_ipi(int cpu, int level)
243{
244 cc_set_igen(IGEN_MESSAGE(0, cpu << 3, 6 + ((level >> 1) & 7), 1 << (level - 1)));
245}
246
247#endif /* !__ASSEMBLY__ */
248
249#endif /* !(_SPARC_OBIO_H) */
diff --git a/include/asm-sparc/of_device.h b/include/asm-sparc/of_device.h
deleted file mode 100644
index e5f5aedc229..00000000000
--- a/include/asm-sparc/of_device.h
+++ /dev/null
@@ -1,38 +0,0 @@
1#ifndef _ASM_SPARC_OF_DEVICE_H
2#define _ASM_SPARC_OF_DEVICE_H
3#ifdef __KERNEL__
4
5#include <linux/device.h>
6#include <linux/of.h>
7#include <linux/mod_devicetable.h>
8#include <asm/openprom.h>
9
10/*
11 * The of_device is a kind of "base class" that is a superset of
12 * struct device for use by devices attached to an OF node and
13 * probed using OF properties.
14 */
15struct of_device
16{
17 struct device_node *node;
18 struct device dev;
19 struct resource resource[PROMREG_MAX];
20 unsigned int irqs[PROMINTR_MAX];
21 int num_irqs;
22
23 void *sysdata;
24
25 int slot;
26 int portid;
27 int clock_freq;
28};
29
30extern void __iomem *of_ioremap(struct resource *res, unsigned long offset, unsigned long size, char *name);
31extern void of_iounmap(struct resource *res, void __iomem *base, unsigned long size);
32
33/* These are just here during the transition */
34#include <linux/of_device.h>
35#include <linux/of_platform.h>
36
37#endif /* __KERNEL__ */
38#endif /* _ASM_SPARC_OF_DEVICE_H */
diff --git a/include/asm-sparc/of_platform.h b/include/asm-sparc/of_platform.h
deleted file mode 100644
index 851eb84d737..00000000000
--- a/include/asm-sparc/of_platform.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_OF_PLATFORM_H
2#define ___ASM_SPARC_OF_PLATFORM_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/of_platform_64.h>
5#else
6#include <asm-sparc/of_platform_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/of_platform_32.h b/include/asm-sparc/of_platform_32.h
deleted file mode 100644
index 38334351c36..00000000000
--- a/include/asm-sparc/of_platform_32.h
+++ /dev/null
@@ -1,24 +0,0 @@
1#ifndef _ASM_SPARC_OF_PLATFORM_H
2#define _ASM_SPARC_OF_PLATFORM_H
3/*
4 * Copyright (C) 2006 Benjamin Herrenschmidt, IBM Corp.
5 * <benh@kernel.crashing.org>
6 * Modified for Sparc by merging parts of asm-sparc/of_device.h
7 * by Stephen Rothwell
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 *
14 */
15
16/* This is just here during the transition */
17#include <linux/of_platform.h>
18
19extern struct bus_type ebus_bus_type;
20extern struct bus_type sbus_bus_type;
21
22#define of_bus_type of_platform_bus_type /* for compatibility */
23
24#endif /* _ASM_SPARC_OF_PLATFORM_H */
diff --git a/include/asm-sparc/of_platform_64.h b/include/asm-sparc/of_platform_64.h
deleted file mode 100644
index 78aa032b674..00000000000
--- a/include/asm-sparc/of_platform_64.h
+++ /dev/null
@@ -1,25 +0,0 @@
1#ifndef _ASM_SPARC64_OF_PLATFORM_H
2#define _ASM_SPARC64_OF_PLATFORM_H
3/*
4 * Copyright (C) 2006 Benjamin Herrenschmidt, IBM Corp.
5 * <benh@kernel.crashing.org>
6 * Modified for Sparc by merging parts of asm-sparc/of_device.h
7 * by Stephen Rothwell
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 *
14 */
15
16/* This is just here during the transition */
17#include <linux/of_platform.h>
18
19extern struct bus_type isa_bus_type;
20extern struct bus_type ebus_bus_type;
21extern struct bus_type sbus_bus_type;
22
23#define of_bus_type of_platform_bus_type /* for compatibility */
24
25#endif /* _ASM_SPARC64_OF_PLATFORM_H */
diff --git a/include/asm-sparc/openprom.h b/include/asm-sparc/openprom.h
deleted file mode 100644
index 8c349f06199..00000000000
--- a/include/asm-sparc/openprom.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_OPENPROM_H
2#define ___ASM_SPARC_OPENPROM_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/openprom_64.h>
5#else
6#include <asm-sparc/openprom_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/openprom_32.h b/include/asm-sparc/openprom_32.h
deleted file mode 100644
index 8b1649f29ed..00000000000
--- a/include/asm-sparc/openprom_32.h
+++ /dev/null
@@ -1,255 +0,0 @@
1#ifndef __SPARC_OPENPROM_H
2#define __SPARC_OPENPROM_H
3
4/* openprom.h: Prom structures and defines for access to the OPENBOOT
5 * prom routines and data areas.
6 *
7 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
8 */
9
10/* Empirical constants... */
11#define LINUX_OPPROM_MAGIC 0x10010407
12
13#ifndef __ASSEMBLY__
14/* V0 prom device operations. */
15struct linux_dev_v0_funcs {
16 int (*v0_devopen)(char *device_str);
17 int (*v0_devclose)(int dev_desc);
18 int (*v0_rdblkdev)(int dev_desc, int num_blks, int blk_st, char *buf);
19 int (*v0_wrblkdev)(int dev_desc, int num_blks, int blk_st, char *buf);
20 int (*v0_wrnetdev)(int dev_desc, int num_bytes, char *buf);
21 int (*v0_rdnetdev)(int dev_desc, int num_bytes, char *buf);
22 int (*v0_rdchardev)(int dev_desc, int num_bytes, int dummy, char *buf);
23 int (*v0_wrchardev)(int dev_desc, int num_bytes, int dummy, char *buf);
24 int (*v0_seekdev)(int dev_desc, long logical_offst, int from);
25};
26
27/* V2 and later prom device operations. */
28struct linux_dev_v2_funcs {
29 int (*v2_inst2pkg)(int d); /* Convert ihandle to phandle */
30 char * (*v2_dumb_mem_alloc)(char *va, unsigned sz);
31 void (*v2_dumb_mem_free)(char *va, unsigned sz);
32
33 /* To map devices into virtual I/O space. */
34 char * (*v2_dumb_mmap)(char *virta, int which_io, unsigned paddr, unsigned sz);
35 void (*v2_dumb_munmap)(char *virta, unsigned size);
36
37 int (*v2_dev_open)(char *devpath);
38 void (*v2_dev_close)(int d);
39 int (*v2_dev_read)(int d, char *buf, int nbytes);
40 int (*v2_dev_write)(int d, char *buf, int nbytes);
41 int (*v2_dev_seek)(int d, int hi, int lo);
42
43 /* Never issued (multistage load support) */
44 void (*v2_wheee2)(void);
45 void (*v2_wheee3)(void);
46};
47
48struct linux_mlist_v0 {
49 struct linux_mlist_v0 *theres_more;
50 char *start_adr;
51 unsigned num_bytes;
52};
53
54struct linux_mem_v0 {
55 struct linux_mlist_v0 **v0_totphys;
56 struct linux_mlist_v0 **v0_prommap;
57 struct linux_mlist_v0 **v0_available; /* What we can use */
58};
59
60/* Arguments sent to the kernel from the boot prompt. */
61struct linux_arguments_v0 {
62 char *argv[8];
63 char args[100];
64 char boot_dev[2];
65 int boot_dev_ctrl;
66 int boot_dev_unit;
67 int dev_partition;
68 char *kernel_file_name;
69 void *aieee1; /* XXX */
70};
71
72/* V2 and up boot things. */
73struct linux_bootargs_v2 {
74 char **bootpath;
75 char **bootargs;
76 int *fd_stdin;
77 int *fd_stdout;
78};
79
80/* The top level PROM vector. */
81struct linux_romvec {
82 /* Version numbers. */
83 unsigned int pv_magic_cookie;
84 unsigned int pv_romvers;
85 unsigned int pv_plugin_revision;
86 unsigned int pv_printrev;
87
88 /* Version 0 memory descriptors. */
89 struct linux_mem_v0 pv_v0mem;
90
91 /* Node operations. */
92 struct linux_nodeops *pv_nodeops;
93
94 char **pv_bootstr;
95 struct linux_dev_v0_funcs pv_v0devops;
96
97 char *pv_stdin;
98 char *pv_stdout;
99#define PROMDEV_KBD 0 /* input from keyboard */
100#define PROMDEV_SCREEN 0 /* output to screen */
101#define PROMDEV_TTYA 1 /* in/out to ttya */
102#define PROMDEV_TTYB 2 /* in/out to ttyb */
103
104 /* Blocking getchar/putchar. NOT REENTRANT! (grr) */
105 int (*pv_getchar)(void);
106 void (*pv_putchar)(int ch);
107
108 /* Non-blocking variants. */
109 int (*pv_nbgetchar)(void);
110 int (*pv_nbputchar)(int ch);
111
112 void (*pv_putstr)(char *str, int len);
113
114 /* Miscellany. */
115 void (*pv_reboot)(char *bootstr);
116 void (*pv_printf)(__const__ char *fmt, ...);
117 void (*pv_abort)(void);
118 __volatile__ int *pv_ticks;
119 void (*pv_halt)(void);
120 void (**pv_synchook)(void);
121
122 /* Evaluate a forth string, not different proto for V0 and V2->up. */
123 union {
124 void (*v0_eval)(int len, char *str);
125 void (*v2_eval)(char *str);
126 } pv_fortheval;
127
128 struct linux_arguments_v0 **pv_v0bootargs;
129
130 /* Get ether address. */
131 unsigned int (*pv_enaddr)(int d, char *enaddr);
132
133 struct linux_bootargs_v2 pv_v2bootargs;
134 struct linux_dev_v2_funcs pv_v2devops;
135
136 int filler[15];
137
138 /* This one is sun4c/sun4 only. */
139 void (*pv_setctxt)(int ctxt, char *va, int pmeg);
140
141 /* Prom version 3 Multiprocessor routines. This stuff is crazy.
142 * No joke. Calling these when there is only one cpu probably
143 * crashes the machine, have to test this. :-)
144 */
145
146 /* v3_cpustart() will start the cpu 'whichcpu' in mmu-context
147 * 'thiscontext' executing at address 'prog_counter'
148 */
149 int (*v3_cpustart)(unsigned int whichcpu, int ctxtbl_ptr,
150 int thiscontext, char *prog_counter);
151
152 /* v3_cpustop() will cause cpu 'whichcpu' to stop executing
153 * until a resume cpu call is made.
154 */
155 int (*v3_cpustop)(unsigned int whichcpu);
156
157 /* v3_cpuidle() will idle cpu 'whichcpu' until a stop or
158 * resume cpu call is made.
159 */
160 int (*v3_cpuidle)(unsigned int whichcpu);
161
162 /* v3_cpuresume() will resume processor 'whichcpu' executing
163 * starting with whatever 'pc' and 'npc' were left at the
164 * last 'idle' or 'stop' call.
165 */
166 int (*v3_cpuresume)(unsigned int whichcpu);
167};
168
169/* Routines for traversing the prom device tree. */
170struct linux_nodeops {
171 int (*no_nextnode)(int node);
172 int (*no_child)(int node);
173 int (*no_proplen)(int node, char *name);
174 int (*no_getprop)(int node, char *name, char *val);
175 int (*no_setprop)(int node, char *name, char *val, int len);
176 char * (*no_nextprop)(int node, char *name);
177};
178
179/* More fun PROM structures for device probing. */
180#define PROMREG_MAX 16
181#define PROMVADDR_MAX 16
182#define PROMINTR_MAX 15
183
184struct linux_prom_registers {
185 unsigned int which_io; /* is this in OBIO space? */
186 unsigned int phys_addr; /* The physical address of this register */
187 unsigned int reg_size; /* How many bytes does this register take up? */
188};
189
190struct linux_prom_irqs {
191 int pri; /* IRQ priority */
192 int vector; /* This is foobar, what does it do? */
193};
194
195/* Element of the "ranges" vector */
196struct linux_prom_ranges {
197 unsigned int ot_child_space;
198 unsigned int ot_child_base; /* Bus feels this */
199 unsigned int ot_parent_space;
200 unsigned int ot_parent_base; /* CPU looks from here */
201 unsigned int or_size;
202};
203
204/* Ranges and reg properties are a bit different for PCI. */
205struct linux_prom_pci_registers {
206 /*
207 * We don't know what information this field contain.
208 * We guess, PCI device function is in bits 15:8
209 * So, ...
210 */
211 unsigned int which_io; /* Let it be which_io */
212
213 unsigned int phys_hi;
214 unsigned int phys_lo;
215
216 unsigned int size_hi;
217 unsigned int size_lo;
218};
219
220struct linux_prom_pci_ranges {
221 unsigned int child_phys_hi; /* Only certain bits are encoded here. */
222 unsigned int child_phys_mid;
223 unsigned int child_phys_lo;
224
225 unsigned int parent_phys_hi;
226 unsigned int parent_phys_lo;
227
228 unsigned int size_hi;
229 unsigned int size_lo;
230};
231
232struct linux_prom_pci_assigned_addresses {
233 unsigned int which_io;
234
235 unsigned int phys_hi;
236 unsigned int phys_lo;
237
238 unsigned int size_hi;
239 unsigned int size_lo;
240};
241
242struct linux_prom_ebus_ranges {
243 unsigned int child_phys_hi;
244 unsigned int child_phys_lo;
245
246 unsigned int parent_phys_hi;
247 unsigned int parent_phys_mid;
248 unsigned int parent_phys_lo;
249
250 unsigned int size;
251};
252
253#endif /* !(__ASSEMBLY__) */
254
255#endif /* !(__SPARC_OPENPROM_H) */
diff --git a/include/asm-sparc/openprom_64.h b/include/asm-sparc/openprom_64.h
deleted file mode 100644
index b69e4a8c917..00000000000
--- a/include/asm-sparc/openprom_64.h
+++ /dev/null
@@ -1,280 +0,0 @@
1#ifndef __SPARC64_OPENPROM_H
2#define __SPARC64_OPENPROM_H
3
4/* openprom.h: Prom structures and defines for access to the OPENBOOT
5 * prom routines and data areas.
6 *
7 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
8 */
9
10#ifndef __ASSEMBLY__
11/* V0 prom device operations. */
12struct linux_dev_v0_funcs {
13 int (*v0_devopen)(char *device_str);
14 int (*v0_devclose)(int dev_desc);
15 int (*v0_rdblkdev)(int dev_desc, int num_blks, int blk_st, char *buf);
16 int (*v0_wrblkdev)(int dev_desc, int num_blks, int blk_st, char *buf);
17 int (*v0_wrnetdev)(int dev_desc, int num_bytes, char *buf);
18 int (*v0_rdnetdev)(int dev_desc, int num_bytes, char *buf);
19 int (*v0_rdchardev)(int dev_desc, int num_bytes, int dummy, char *buf);
20 int (*v0_wrchardev)(int dev_desc, int num_bytes, int dummy, char *buf);
21 int (*v0_seekdev)(int dev_desc, long logical_offst, int from);
22};
23
24/* V2 and later prom device operations. */
25struct linux_dev_v2_funcs {
26 int (*v2_inst2pkg)(int d); /* Convert ihandle to phandle */
27 char * (*v2_dumb_mem_alloc)(char *va, unsigned sz);
28 void (*v2_dumb_mem_free)(char *va, unsigned sz);
29
30 /* To map devices into virtual I/O space. */
31 char * (*v2_dumb_mmap)(char *virta, int which_io, unsigned paddr, unsigned sz);
32 void (*v2_dumb_munmap)(char *virta, unsigned size);
33
34 int (*v2_dev_open)(char *devpath);
35 void (*v2_dev_close)(int d);
36 int (*v2_dev_read)(int d, char *buf, int nbytes);
37 int (*v2_dev_write)(int d, char *buf, int nbytes);
38 int (*v2_dev_seek)(int d, int hi, int lo);
39
40 /* Never issued (multistage load support) */
41 void (*v2_wheee2)(void);
42 void (*v2_wheee3)(void);
43};
44
45struct linux_mlist_v0 {
46 struct linux_mlist_v0 *theres_more;
47 unsigned start_adr;
48 unsigned num_bytes;
49};
50
51struct linux_mem_v0 {
52 struct linux_mlist_v0 **v0_totphys;
53 struct linux_mlist_v0 **v0_prommap;
54 struct linux_mlist_v0 **v0_available; /* What we can use */
55};
56
57/* Arguments sent to the kernel from the boot prompt. */
58struct linux_arguments_v0 {
59 char *argv[8];
60 char args[100];
61 char boot_dev[2];
62 int boot_dev_ctrl;
63 int boot_dev_unit;
64 int dev_partition;
65 char *kernel_file_name;
66 void *aieee1; /* XXX */
67};
68
69/* V2 and up boot things. */
70struct linux_bootargs_v2 {
71 char **bootpath;
72 char **bootargs;
73 int *fd_stdin;
74 int *fd_stdout;
75};
76
77/* The top level PROM vector. */
78struct linux_romvec {
79 /* Version numbers. */
80 unsigned int pv_magic_cookie;
81 unsigned int pv_romvers;
82 unsigned int pv_plugin_revision;
83 unsigned int pv_printrev;
84
85 /* Version 0 memory descriptors. */
86 struct linux_mem_v0 pv_v0mem;
87
88 /* Node operations. */
89 struct linux_nodeops *pv_nodeops;
90
91 char **pv_bootstr;
92 struct linux_dev_v0_funcs pv_v0devops;
93
94 char *pv_stdin;
95 char *pv_stdout;
96#define PROMDEV_KBD 0 /* input from keyboard */
97#define PROMDEV_SCREEN 0 /* output to screen */
98#define PROMDEV_TTYA 1 /* in/out to ttya */
99#define PROMDEV_TTYB 2 /* in/out to ttyb */
100
101 /* Blocking getchar/putchar. NOT REENTRANT! (grr) */
102 int (*pv_getchar)(void);
103 void (*pv_putchar)(int ch);
104
105 /* Non-blocking variants. */
106 int (*pv_nbgetchar)(void);
107 int (*pv_nbputchar)(int ch);
108
109 void (*pv_putstr)(char *str, int len);
110
111 /* Miscellany. */
112 void (*pv_reboot)(char *bootstr);
113 void (*pv_printf)(__const__ char *fmt, ...);
114 void (*pv_abort)(void);
115 __volatile__ int *pv_ticks;
116 void (*pv_halt)(void);
117 void (**pv_synchook)(void);
118
119 /* Evaluate a forth string, not different proto for V0 and V2->up. */
120 union {
121 void (*v0_eval)(int len, char *str);
122 void (*v2_eval)(char *str);
123 } pv_fortheval;
124
125 struct linux_arguments_v0 **pv_v0bootargs;
126
127 /* Get ether address. */
128 unsigned int (*pv_enaddr)(int d, char *enaddr);
129
130 struct linux_bootargs_v2 pv_v2bootargs;
131 struct linux_dev_v2_funcs pv_v2devops;
132
133 int filler[15];
134
135 /* This one is sun4c/sun4 only. */
136 void (*pv_setctxt)(int ctxt, char *va, int pmeg);
137
138 /* Prom version 3 Multiprocessor routines. This stuff is crazy.
139 * No joke. Calling these when there is only one cpu probably
140 * crashes the machine, have to test this. :-)
141 */
142
143 /* v3_cpustart() will start the cpu 'whichcpu' in mmu-context
144 * 'thiscontext' executing at address 'prog_counter'
145 */
146 int (*v3_cpustart)(unsigned int whichcpu, int ctxtbl_ptr,
147 int thiscontext, char *prog_counter);
148
149 /* v3_cpustop() will cause cpu 'whichcpu' to stop executing
150 * until a resume cpu call is made.
151 */
152 int (*v3_cpustop)(unsigned int whichcpu);
153
154 /* v3_cpuidle() will idle cpu 'whichcpu' until a stop or
155 * resume cpu call is made.
156 */
157 int (*v3_cpuidle)(unsigned int whichcpu);
158
159 /* v3_cpuresume() will resume processor 'whichcpu' executing
160 * starting with whatever 'pc' and 'npc' were left at the
161 * last 'idle' or 'stop' call.
162 */
163 int (*v3_cpuresume)(unsigned int whichcpu);
164};
165
166/* Routines for traversing the prom device tree. */
167struct linux_nodeops {
168 int (*no_nextnode)(int node);
169 int (*no_child)(int node);
170 int (*no_proplen)(int node, char *name);
171 int (*no_getprop)(int node, char *name, char *val);
172 int (*no_setprop)(int node, char *name, char *val, int len);
173 char * (*no_nextprop)(int node, char *name);
174};
175
176/* More fun PROM structures for device probing. */
177#define PROMREG_MAX 24
178#define PROMVADDR_MAX 16
179#define PROMINTR_MAX 32
180
181struct linux_prom_registers {
182 unsigned which_io; /* hi part of physical address */
183 unsigned phys_addr; /* The physical address of this register */
184 int reg_size; /* How many bytes does this register take up? */
185};
186
187struct linux_prom64_registers {
188 unsigned long phys_addr;
189 unsigned long reg_size;
190};
191
192struct linux_prom_irqs {
193 int pri; /* IRQ priority */
194 int vector; /* This is foobar, what does it do? */
195};
196
197/* Element of the "ranges" vector */
198struct linux_prom_ranges {
199 unsigned int ot_child_space;
200 unsigned int ot_child_base; /* Bus feels this */
201 unsigned int ot_parent_space;
202 unsigned int ot_parent_base; /* CPU looks from here */
203 unsigned int or_size;
204};
205
206struct linux_prom64_ranges {
207 unsigned long ot_child_base; /* Bus feels this */
208 unsigned long ot_parent_base; /* CPU looks from here */
209 unsigned long or_size;
210};
211
212/* Ranges and reg properties are a bit different for PCI. */
213struct linux_prom_pci_registers {
214 unsigned int phys_hi;
215 unsigned int phys_mid;
216 unsigned int phys_lo;
217
218 unsigned int size_hi;
219 unsigned int size_lo;
220};
221
222struct linux_prom_pci_ranges {
223 unsigned int child_phys_hi; /* Only certain bits are encoded here. */
224 unsigned int child_phys_mid;
225 unsigned int child_phys_lo;
226
227 unsigned int parent_phys_hi;
228 unsigned int parent_phys_lo;
229
230 unsigned int size_hi;
231 unsigned int size_lo;
232};
233
234struct linux_prom_pci_intmap {
235 unsigned int phys_hi;
236 unsigned int phys_mid;
237 unsigned int phys_lo;
238
239 unsigned int interrupt;
240
241 int cnode;
242 unsigned int cinterrupt;
243};
244
245struct linux_prom_pci_intmask {
246 unsigned int phys_hi;
247 unsigned int phys_mid;
248 unsigned int phys_lo;
249 unsigned int interrupt;
250};
251
252struct linux_prom_ebus_ranges {
253 unsigned int child_phys_hi;
254 unsigned int child_phys_lo;
255
256 unsigned int parent_phys_hi;
257 unsigned int parent_phys_mid;
258 unsigned int parent_phys_lo;
259
260 unsigned int size;
261};
262
263struct linux_prom_ebus_intmap {
264 unsigned int phys_hi;
265 unsigned int phys_lo;
266
267 unsigned int interrupt;
268
269 int cnode;
270 unsigned int cinterrupt;
271};
272
273struct linux_prom_ebus_intmask {
274 unsigned int phys_hi;
275 unsigned int phys_lo;
276 unsigned int interrupt;
277};
278#endif /* !(__ASSEMBLY__) */
279
280#endif /* !(__SPARC64_OPENPROM_H) */
diff --git a/include/asm-sparc/openpromio.h b/include/asm-sparc/openpromio.h
deleted file mode 100644
index 917fb8e9c63..00000000000
--- a/include/asm-sparc/openpromio.h
+++ /dev/null
@@ -1,69 +0,0 @@
1#ifndef _SPARC_OPENPROMIO_H
2#define _SPARC_OPENPROMIO_H
3
4#include <linux/compiler.h>
5#include <linux/ioctl.h>
6#include <linux/types.h>
7
8/*
9 * SunOS and Solaris /dev/openprom definitions. The ioctl values
10 * were chosen to be exactly equal to the SunOS equivalents.
11 */
12
13struct openpromio
14{
15 u_int oprom_size; /* Actual size of the oprom_array. */
16 char oprom_array[1]; /* Holds property names and values. */
17};
18
19#define OPROMMAXPARAM 4096 /* Maximum size of oprom_array. */
20
21#define OPROMGETOPT 0x20004F01
22#define OPROMSETOPT 0x20004F02
23#define OPROMNXTOPT 0x20004F03
24#define OPROMSETOPT2 0x20004F04
25#define OPROMNEXT 0x20004F05
26#define OPROMCHILD 0x20004F06
27#define OPROMGETPROP 0x20004F07
28#define OPROMNXTPROP 0x20004F08
29#define OPROMU2P 0x20004F09
30#define OPROMGETCONS 0x20004F0A
31#define OPROMGETFBNAME 0x20004F0B
32#define OPROMGETBOOTARGS 0x20004F0C
33/* Linux extensions */ /* Arguments in oprom_array: */
34#define OPROMSETCUR 0x20004FF0 /* int node - Sets current node */
35#define OPROMPCI2NODE 0x20004FF1 /* int pci_bus, pci_devfn - Sets current node to PCI device's node */
36#define OPROMPATH2NODE 0x20004FF2 /* char path[] - Set current node from fully qualified PROM path */
37
38/*
39 * Return values from OPROMGETCONS:
40 */
41
42#define OPROMCONS_NOT_WSCONS 0
43#define OPROMCONS_STDIN_IS_KBD 0x1 /* stdin device is kbd */
44#define OPROMCONS_STDOUT_IS_FB 0x2 /* stdout is a framebuffer */
45#define OPROMCONS_OPENPROM 0x4 /* supports openboot */
46
47
48/*
49 * NetBSD/OpenBSD /dev/openprom definitions.
50 */
51
52struct opiocdesc
53{
54 int op_nodeid; /* PROM Node ID (value-result) */
55 int op_namelen; /* Length of op_name. */
56 char __user *op_name; /* Pointer to the property name. */
57 int op_buflen; /* Length of op_buf (value-result) */
58 char __user *op_buf; /* Pointer to buffer. */
59};
60
61#define OPIOCGET _IOWR('O', 1, struct opiocdesc)
62#define OPIOCSET _IOW('O', 2, struct opiocdesc)
63#define OPIOCNEXTPROP _IOWR('O', 3, struct opiocdesc)
64#define OPIOCGETOPTNODE _IOR('O', 4, int)
65#define OPIOCGETNEXT _IOWR('O', 5, int)
66#define OPIOCGETCHILD _IOWR('O', 6, int)
67
68#endif /* _SPARC_OPENPROMIO_H */
69
diff --git a/include/asm-sparc/oplib.h b/include/asm-sparc/oplib.h
deleted file mode 100644
index e88d7c04a29..00000000000
--- a/include/asm-sparc/oplib.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_OPLIB_H
2#define ___ASM_SPARC_OPLIB_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/oplib_64.h>
5#else
6#include <asm-sparc/oplib_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/oplib_32.h b/include/asm-sparc/oplib_32.h
deleted file mode 100644
index b2631da259e..00000000000
--- a/include/asm-sparc/oplib_32.h
+++ /dev/null
@@ -1,272 +0,0 @@
1/*
2 * oplib.h: Describes the interface and available routines in the
3 * Linux Prom library.
4 *
5 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
6 */
7
8#ifndef __SPARC_OPLIB_H
9#define __SPARC_OPLIB_H
10
11#include <asm/openprom.h>
12#include <linux/spinlock.h>
13#include <linux/compiler.h>
14
15/* The master romvec pointer... */
16extern struct linux_romvec *romvec;
17
18/* Enumeration to describe the prom major version we have detected. */
19enum prom_major_version {
20 PROM_V0, /* Original sun4c V0 prom */
21 PROM_V2, /* sun4c and early sun4m V2 prom */
22 PROM_V3, /* sun4m and later, up to sun4d/sun4e machines V3 */
23 PROM_P1275, /* IEEE compliant ISA based Sun PROM, only sun4u */
24 PROM_SUN4, /* Old sun4 proms are totally different, but we'll shoehorn it to make it fit */
25};
26
27extern enum prom_major_version prom_vers;
28/* Revision, and firmware revision. */
29extern unsigned int prom_rev, prom_prev;
30
31/* Root node of the prom device tree, this stays constant after
32 * initialization is complete.
33 */
34extern int prom_root_node;
35
36/* Pointer to prom structure containing the device tree traversal
37 * and usage utility functions. Only prom-lib should use these,
38 * users use the interface defined by the library only!
39 */
40extern struct linux_nodeops *prom_nodeops;
41
42/* The functions... */
43
44/* You must call prom_init() before using any of the library services,
45 * preferably as early as possible. Pass it the romvec pointer.
46 */
47extern void prom_init(struct linux_romvec *rom_ptr);
48
49/* Boot argument acquisition, returns the boot command line string. */
50extern char *prom_getbootargs(void);
51
52/* Device utilities. */
53
54/* Map and unmap devices in IO space at virtual addresses. Note that the
55 * virtual address you pass is a request and the prom may put your mappings
56 * somewhere else, so check your return value as that is where your new
57 * mappings really are!
58 *
59 * Another note, these are only available on V2 or higher proms!
60 */
61extern char *prom_mapio(char *virt_hint, int io_space, unsigned int phys_addr, unsigned int num_bytes);
62extern void prom_unmapio(char *virt_addr, unsigned int num_bytes);
63
64/* Device operations. */
65
66/* Open the device described by the passed string. Note, that the format
67 * of the string is different on V0 vs. V2->higher proms. The caller must
68 * know what he/she is doing! Returns the device descriptor, an int.
69 */
70extern int prom_devopen(char *device_string);
71
72/* Close a previously opened device described by the passed integer
73 * descriptor.
74 */
75extern int prom_devclose(int device_handle);
76
77/* Do a seek operation on the device described by the passed integer
78 * descriptor.
79 */
80extern void prom_seek(int device_handle, unsigned int seek_hival,
81 unsigned int seek_lowval);
82
83/* Miscellaneous routines, don't really fit in any category per se. */
84
85/* Reboot the machine with the command line passed. */
86extern void prom_reboot(char *boot_command);
87
88/* Evaluate the forth string passed. */
89extern void prom_feval(char *forth_string);
90
91/* Enter the prom, with possibility of continuation with the 'go'
92 * command in newer proms.
93 */
94extern void prom_cmdline(void);
95
96/* Enter the prom, with no chance of continuation for the stand-alone
97 * which calls this.
98 */
99extern void prom_halt(void) __attribute__ ((noreturn));
100
101/* Set the PROM 'sync' callback function to the passed function pointer.
102 * When the user gives the 'sync' command at the prom prompt while the
103 * kernel is still active, the prom will call this routine.
104 *
105 * XXX The arguments are different on V0 vs. V2->higher proms, grrr! XXX
106 */
107typedef void (*sync_func_t)(void);
108extern void prom_setsync(sync_func_t func_ptr);
109
110/* Acquire the IDPROM of the root node in the prom device tree. This
111 * gets passed a buffer where you would like it stuffed. The return value
112 * is the format type of this idprom or 0xff on error.
113 */
114extern unsigned char prom_get_idprom(char *idp_buffer, int idpbuf_size);
115
116/* Get the prom major version. */
117extern int prom_version(void);
118
119/* Get the prom plugin revision. */
120extern int prom_getrev(void);
121
122/* Get the prom firmware revision. */
123extern int prom_getprev(void);
124
125/* Character operations to/from the console.... */
126
127/* Non-blocking get character from console. */
128extern int prom_nbgetchar(void);
129
130/* Non-blocking put character to console. */
131extern int prom_nbputchar(char character);
132
133/* Blocking get character from console. */
134extern char prom_getchar(void);
135
136/* Blocking put character to console. */
137extern void prom_putchar(char character);
138
139/* Prom's internal routines, don't use in kernel/boot code. */
140extern void prom_printf(char *fmt, ...);
141extern void prom_write(const char *buf, unsigned int len);
142
143/* Multiprocessor operations... */
144
145/* Start the CPU with the given device tree node, context table, and context
146 * at the passed program counter.
147 */
148extern int prom_startcpu(int cpunode, struct linux_prom_registers *context_table,
149 int context, char *program_counter);
150
151/* Stop the CPU with the passed device tree node. */
152extern int prom_stopcpu(int cpunode);
153
154/* Idle the CPU with the passed device tree node. */
155extern int prom_idlecpu(int cpunode);
156
157/* Re-Start the CPU with the passed device tree node. */
158extern int prom_restartcpu(int cpunode);
159
160/* PROM memory allocation facilities... */
161
162/* Allocated at possibly the given virtual address a chunk of the
163 * indicated size.
164 */
165extern char *prom_alloc(char *virt_hint, unsigned int size);
166
167/* Free a previously allocated chunk. */
168extern void prom_free(char *virt_addr, unsigned int size);
169
170/* Sun4/sun4c specific memory-management startup hook. */
171
172/* Map the passed segment in the given context at the passed
173 * virtual address.
174 */
175extern void prom_putsegment(int context, unsigned long virt_addr,
176 int physical_segment);
177
178
179/* PROM device tree traversal functions... */
180
181#ifdef PROMLIB_INTERNAL
182
183/* Internal version of prom_getchild. */
184extern int __prom_getchild(int parent_node);
185
186/* Internal version of prom_getsibling. */
187extern int __prom_getsibling(int node);
188
189#endif
190
191
192/* Get the child node of the given node, or zero if no child exists. */
193extern int prom_getchild(int parent_node);
194
195/* Get the next sibling node of the given node, or zero if no further
196 * siblings exist.
197 */
198extern int prom_getsibling(int node);
199
200/* Get the length, at the passed node, of the given property type.
201 * Returns -1 on error (ie. no such property at this node).
202 */
203extern int prom_getproplen(int thisnode, char *property);
204
205/* Fetch the requested property using the given buffer. Returns
206 * the number of bytes the prom put into your buffer or -1 on error.
207 */
208extern int __must_check prom_getproperty(int thisnode, char *property,
209 char *prop_buffer, int propbuf_size);
210
211/* Acquire an integer property. */
212extern int prom_getint(int node, char *property);
213
214/* Acquire an integer property, with a default value. */
215extern int prom_getintdefault(int node, char *property, int defval);
216
217/* Acquire a boolean property, 0=FALSE 1=TRUE. */
218extern int prom_getbool(int node, char *prop);
219
220/* Acquire a string property, null string on error. */
221extern void prom_getstring(int node, char *prop, char *buf, int bufsize);
222
223/* Does the passed node have the given "name"? YES=1 NO=0 */
224extern int prom_nodematch(int thisnode, char *name);
225
226/* Search all siblings starting at the passed node for "name" matching
227 * the given string. Returns the node on success, zero on failure.
228 */
229extern int prom_searchsiblings(int node_start, char *name);
230
231/* Return the first property type, as a string, for the given node.
232 * Returns a null string on error.
233 */
234extern char *prom_firstprop(int node, char *buffer);
235
236/* Returns the next property after the passed property for the given
237 * node. Returns null string on failure.
238 */
239extern char *prom_nextprop(int node, char *prev_property, char *buffer);
240
241/* Returns phandle of the path specified */
242extern int prom_finddevice(char *name);
243
244/* Returns 1 if the specified node has given property. */
245extern int prom_node_has_property(int node, char *property);
246
247/* Set the indicated property at the given node with the passed value.
248 * Returns the number of bytes of your value that the prom took.
249 */
250extern int prom_setprop(int node, char *prop_name, char *prop_value,
251 int value_size);
252
253extern int prom_pathtoinode(char *path);
254extern int prom_inst2pkg(int);
255
256/* Dorking with Bus ranges... */
257
258/* Apply promlib probes OBIO ranges to registers. */
259extern void prom_apply_obio_ranges(struct linux_prom_registers *obioregs, int nregs);
260
261/* Apply ranges of any prom node (and optionally parent node as well) to registers. */
262extern void prom_apply_generic_ranges(int node, int parent,
263 struct linux_prom_registers *sbusregs, int nregs);
264
265/* CPU probing helpers. */
266int cpu_find_by_instance(int instance, int *prom_node, int *mid);
267int cpu_find_by_mid(int mid, int *prom_node);
268int cpu_get_hwmid(int prom_node);
269
270extern spinlock_t prom_lock;
271
272#endif /* !(__SPARC_OPLIB_H) */
diff --git a/include/asm-sparc/oplib_64.h b/include/asm-sparc/oplib_64.h
deleted file mode 100644
index 6d2c2ca9803..00000000000
--- a/include/asm-sparc/oplib_64.h
+++ /dev/null
@@ -1,322 +0,0 @@
1/* oplib.h: Describes the interface and available routines in the
2 * Linux Prom library.
3 *
4 * Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net)
5 * Copyright (C) 1996 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8#ifndef __SPARC64_OPLIB_H
9#define __SPARC64_OPLIB_H
10
11#include <asm/openprom.h>
12
13/* OBP version string. */
14extern char prom_version[];
15
16/* Root node of the prom device tree, this stays constant after
17 * initialization is complete.
18 */
19extern int prom_root_node;
20
21/* PROM stdin and stdout */
22extern int prom_stdin, prom_stdout;
23
24/* /chosen node of the prom device tree, this stays constant after
25 * initialization is complete.
26 */
27extern int prom_chosen_node;
28
29/* Helper values and strings in arch/sparc64/kernel/head.S */
30extern const char prom_peer_name[];
31extern const char prom_compatible_name[];
32extern const char prom_root_compatible[];
33extern const char prom_cpu_compatible[];
34extern const char prom_finddev_name[];
35extern const char prom_chosen_path[];
36extern const char prom_cpu_path[];
37extern const char prom_getprop_name[];
38extern const char prom_mmu_name[];
39extern const char prom_callmethod_name[];
40extern const char prom_translate_name[];
41extern const char prom_map_name[];
42extern const char prom_unmap_name[];
43extern int prom_mmu_ihandle_cache;
44extern unsigned int prom_boot_mapped_pc;
45extern unsigned int prom_boot_mapping_mode;
46extern unsigned long prom_boot_mapping_phys_high, prom_boot_mapping_phys_low;
47
48struct linux_mlist_p1275 {
49 struct linux_mlist_p1275 *theres_more;
50 unsigned long start_adr;
51 unsigned long num_bytes;
52};
53
54struct linux_mem_p1275 {
55 struct linux_mlist_p1275 **p1275_totphys;
56 struct linux_mlist_p1275 **p1275_prommap;
57 struct linux_mlist_p1275 **p1275_available; /* What we can use */
58};
59
60/* The functions... */
61
62/* You must call prom_init() before using any of the library services,
63 * preferably as early as possible. Pass it the romvec pointer.
64 */
65extern void prom_init(void *cif_handler, void *cif_stack);
66
67/* Boot argument acquisition, returns the boot command line string. */
68extern char *prom_getbootargs(void);
69
70/* Device utilities. */
71
72/* Device operations. */
73
74/* Open the device described by the passed string. Note, that the format
75 * of the string is different on V0 vs. V2->higher proms. The caller must
76 * know what he/she is doing! Returns the device descriptor, an int.
77 */
78extern int prom_devopen(const char *device_string);
79
80/* Close a previously opened device described by the passed integer
81 * descriptor.
82 */
83extern int prom_devclose(int device_handle);
84
85/* Do a seek operation on the device described by the passed integer
86 * descriptor.
87 */
88extern void prom_seek(int device_handle, unsigned int seek_hival,
89 unsigned int seek_lowval);
90
91/* Miscellaneous routines, don't really fit in any category per se. */
92
93/* Reboot the machine with the command line passed. */
94extern void prom_reboot(const char *boot_command);
95
96/* Evaluate the forth string passed. */
97extern void prom_feval(const char *forth_string);
98
99/* Enter the prom, with possibility of continuation with the 'go'
100 * command in newer proms.
101 */
102extern void prom_cmdline(void);
103
104/* Enter the prom, with no chance of continuation for the stand-alone
105 * which calls this.
106 */
107extern void prom_halt(void) __attribute__ ((noreturn));
108
109/* Halt and power-off the machine. */
110extern void prom_halt_power_off(void) __attribute__ ((noreturn));
111
112/* Set the PROM 'sync' callback function to the passed function pointer.
113 * When the user gives the 'sync' command at the prom prompt while the
114 * kernel is still active, the prom will call this routine.
115 *
116 */
117typedef int (*callback_func_t)(long *cmd);
118extern void prom_setcallback(callback_func_t func_ptr);
119
120/* Acquire the IDPROM of the root node in the prom device tree. This
121 * gets passed a buffer where you would like it stuffed. The return value
122 * is the format type of this idprom or 0xff on error.
123 */
124extern unsigned char prom_get_idprom(char *idp_buffer, int idpbuf_size);
125
126/* Character operations to/from the console.... */
127
128/* Non-blocking get character from console. */
129extern int prom_nbgetchar(void);
130
131/* Non-blocking put character to console. */
132extern int prom_nbputchar(char character);
133
134/* Blocking get character from console. */
135extern char prom_getchar(void);
136
137/* Blocking put character to console. */
138extern void prom_putchar(char character);
139
140/* Prom's internal routines, don't use in kernel/boot code. */
141extern void prom_printf(const char *fmt, ...);
142extern void prom_write(const char *buf, unsigned int len);
143
144/* Multiprocessor operations... */
145#ifdef CONFIG_SMP
146/* Start the CPU with the given device tree node at the passed program
147 * counter with the given arg passed in via register %o0.
148 */
149extern void prom_startcpu(int cpunode, unsigned long pc, unsigned long arg);
150
151/* Start the CPU with the given cpu ID at the passed program
152 * counter with the given arg passed in via register %o0.
153 */
154extern void prom_startcpu_cpuid(int cpuid, unsigned long pc, unsigned long arg);
155
156/* Stop the CPU with the given cpu ID. */
157extern void prom_stopcpu_cpuid(int cpuid);
158
159/* Stop the current CPU. */
160extern void prom_stopself(void);
161
162/* Idle the current CPU. */
163extern void prom_idleself(void);
164
165/* Resume the CPU with the passed device tree node. */
166extern void prom_resumecpu(int cpunode);
167#endif
168
169/* Power management interfaces. */
170
171/* Put the current CPU to sleep. */
172extern void prom_sleepself(void);
173
174/* Put the entire system to sleep. */
175extern int prom_sleepsystem(void);
176
177/* Initiate a wakeup event. */
178extern int prom_wakeupsystem(void);
179
180/* MMU and memory related OBP interfaces. */
181
182/* Get unique string identifying SIMM at given physical address. */
183extern int prom_getunumber(int syndrome_code,
184 unsigned long phys_addr,
185 char *buf, int buflen);
186
187/* Retain physical memory to the caller across soft resets. */
188extern unsigned long prom_retain(const char *name,
189 unsigned long pa_low, unsigned long pa_high,
190 long size, long align);
191
192/* Load explicit I/D TLB entries into the calling processor. */
193extern long prom_itlb_load(unsigned long index,
194 unsigned long tte_data,
195 unsigned long vaddr);
196
197extern long prom_dtlb_load(unsigned long index,
198 unsigned long tte_data,
199 unsigned long vaddr);
200
201/* Map/Unmap client program address ranges. First the format of
202 * the mapping mode argument.
203 */
204#define PROM_MAP_WRITE 0x0001 /* Writable */
205#define PROM_MAP_READ 0x0002 /* Readable - sw */
206#define PROM_MAP_EXEC 0x0004 /* Executable - sw */
207#define PROM_MAP_LOCKED 0x0010 /* Locked, use i/dtlb load calls for this instead */
208#define PROM_MAP_CACHED 0x0020 /* Cacheable in both L1 and L2 caches */
209#define PROM_MAP_SE 0x0040 /* Side-Effects */
210#define PROM_MAP_GLOB 0x0080 /* Global */
211#define PROM_MAP_IE 0x0100 /* Invert-Endianness */
212#define PROM_MAP_DEFAULT (PROM_MAP_WRITE | PROM_MAP_READ | PROM_MAP_EXEC | PROM_MAP_CACHED)
213
214extern int prom_map(int mode, unsigned long size,
215 unsigned long vaddr, unsigned long paddr);
216extern void prom_unmap(unsigned long size, unsigned long vaddr);
217
218
219/* PROM device tree traversal functions... */
220
221#ifdef PROMLIB_INTERNAL
222
223/* Internal version of prom_getchild. */
224extern int __prom_getchild(int parent_node);
225
226/* Internal version of prom_getsibling. */
227extern int __prom_getsibling(int node);
228
229#endif
230
231/* Get the child node of the given node, or zero if no child exists. */
232extern int prom_getchild(int parent_node);
233
234/* Get the next sibling node of the given node, or zero if no further
235 * siblings exist.
236 */
237extern int prom_getsibling(int node);
238
239/* Get the length, at the passed node, of the given property type.
240 * Returns -1 on error (ie. no such property at this node).
241 */
242extern int prom_getproplen(int thisnode, const char *property);
243
244/* Fetch the requested property using the given buffer. Returns
245 * the number of bytes the prom put into your buffer or -1 on error.
246 */
247extern int prom_getproperty(int thisnode, const char *property,
248 char *prop_buffer, int propbuf_size);
249
250/* Acquire an integer property. */
251extern int prom_getint(int node, const char *property);
252
253/* Acquire an integer property, with a default value. */
254extern int prom_getintdefault(int node, const char *property, int defval);
255
256/* Acquire a boolean property, 0=FALSE 1=TRUE. */
257extern int prom_getbool(int node, const char *prop);
258
259/* Acquire a string property, null string on error. */
260extern void prom_getstring(int node, const char *prop, char *buf, int bufsize);
261
262/* Does the passed node have the given "name"? YES=1 NO=0 */
263extern int prom_nodematch(int thisnode, const char *name);
264
265/* Search all siblings starting at the passed node for "name" matching
266 * the given string. Returns the node on success, zero on failure.
267 */
268extern int prom_searchsiblings(int node_start, const char *name);
269
270/* Return the first property type, as a string, for the given node.
271 * Returns a null string on error. Buffer should be at least 32B long.
272 */
273extern char *prom_firstprop(int node, char *buffer);
274
275/* Returns the next property after the passed property for the given
276 * node. Returns null string on failure. Buffer should be at least 32B long.
277 */
278extern char *prom_nextprop(int node, const char *prev_property, char *buffer);
279
280/* Returns 1 if the specified node has given property. */
281extern int prom_node_has_property(int node, const char *property);
282
283/* Returns phandle of the path specified */
284extern int prom_finddevice(const char *name);
285
286/* Set the indicated property at the given node with the passed value.
287 * Returns the number of bytes of your value that the prom took.
288 */
289extern int prom_setprop(int node, const char *prop_name, char *prop_value,
290 int value_size);
291
292extern int prom_pathtoinode(const char *path);
293extern int prom_inst2pkg(int);
294extern int prom_service_exists(const char *service_name);
295extern void prom_sun4v_guest_soft_state(void);
296
297extern int prom_ihandle2path(int handle, char *buffer, int bufsize);
298
299/* Client interface level routines. */
300extern long p1275_cmd(const char *, long, ...);
301
302#if 0
303#define P1275_SIZE(x) ((((long)((x) / 32)) << 32) | (x))
304#else
305#define P1275_SIZE(x) x
306#endif
307
308/* We support at most 16 input and 1 output argument */
309#define P1275_ARG_NUMBER 0
310#define P1275_ARG_IN_STRING 1
311#define P1275_ARG_OUT_BUF 2
312#define P1275_ARG_OUT_32B 3
313#define P1275_ARG_IN_FUNCTION 4
314#define P1275_ARG_IN_BUF 5
315#define P1275_ARG_IN_64B 6
316
317#define P1275_IN(x) ((x) & 0xf)
318#define P1275_OUT(x) (((x) << 4) & 0xf0)
319#define P1275_INOUT(i,o) (P1275_IN(i)|P1275_OUT(o))
320#define P1275_ARG(n,x) ((x) << ((n)*3 + 8))
321
322#endif /* !(__SPARC64_OPLIB_H) */
diff --git a/include/asm-sparc/page.h b/include/asm-sparc/page.h
deleted file mode 100644
index f32f49fcf75..00000000000
--- a/include/asm-sparc/page.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_PAGE_H
2#define ___ASM_SPARC_PAGE_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/page_64.h>
5#else
6#include <asm-sparc/page_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/page_32.h b/include/asm-sparc/page_32.h
deleted file mode 100644
index cf5fb70ca1c..00000000000
--- a/include/asm-sparc/page_32.h
+++ /dev/null
@@ -1,160 +0,0 @@
1/*
2 * page.h: Various defines and such for MMU operations on the Sparc for
3 * the Linux kernel.
4 *
5 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
6 */
7
8#ifndef _SPARC_PAGE_H
9#define _SPARC_PAGE_H
10
11#ifdef CONFIG_SUN4
12#define PAGE_SHIFT 13
13#else
14#define PAGE_SHIFT 12
15#endif
16#ifndef __ASSEMBLY__
17/* I have my suspicions... -DaveM */
18#define PAGE_SIZE (1UL << PAGE_SHIFT)
19#else
20#define PAGE_SIZE (1 << PAGE_SHIFT)
21#endif
22#define PAGE_MASK (~(PAGE_SIZE-1))
23
24#include <asm/btfixup.h>
25
26#ifndef __ASSEMBLY__
27
28#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE)
29#define copy_page(to,from) memcpy((void *)(to), (void *)(from), PAGE_SIZE)
30#define clear_user_page(addr, vaddr, page) \
31 do { clear_page(addr); \
32 sparc_flush_page_to_ram(page); \
33 } while (0)
34#define copy_user_page(to, from, vaddr, page) \
35 do { copy_page(to, from); \
36 sparc_flush_page_to_ram(page); \
37 } while (0)
38
39/* The following structure is used to hold the physical
40 * memory configuration of the machine. This is filled in
41 * prom_meminit() and is later used by mem_init() to set up
42 * mem_map[]. We statically allocate SPARC_PHYS_BANKS+1 of
43 * these structs, this is arbitrary. The entry after the
44 * last valid one has num_bytes==0.
45 */
46struct sparc_phys_banks {
47 unsigned long base_addr;
48 unsigned long num_bytes;
49};
50
51#define SPARC_PHYS_BANKS 32
52
53extern struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS+1];
54
55/* Cache alias structure. Entry is valid if context != -1. */
56struct cache_palias {
57 unsigned long vaddr;
58 int context;
59};
60
61/* passing structs on the Sparc slow us down tremendously... */
62
63/* #define STRICT_MM_TYPECHECKS */
64
65#ifdef STRICT_MM_TYPECHECKS
66/*
67 * These are used to make use of C type-checking..
68 */
69typedef struct { unsigned long pte; } pte_t;
70typedef struct { unsigned long iopte; } iopte_t;
71typedef struct { unsigned long pmdv[16]; } pmd_t;
72typedef struct { unsigned long pgd; } pgd_t;
73typedef struct { unsigned long ctxd; } ctxd_t;
74typedef struct { unsigned long pgprot; } pgprot_t;
75typedef struct { unsigned long iopgprot; } iopgprot_t;
76
77#define pte_val(x) ((x).pte)
78#define iopte_val(x) ((x).iopte)
79#define pmd_val(x) ((x).pmdv[0])
80#define pgd_val(x) ((x).pgd)
81#define ctxd_val(x) ((x).ctxd)
82#define pgprot_val(x) ((x).pgprot)
83#define iopgprot_val(x) ((x).iopgprot)
84
85#define __pte(x) ((pte_t) { (x) } )
86#define __iopte(x) ((iopte_t) { (x) } )
87/* #define __pmd(x) ((pmd_t) { (x) } ) */ /* XXX procedure with loop */
88#define __pgd(x) ((pgd_t) { (x) } )
89#define __ctxd(x) ((ctxd_t) { (x) } )
90#define __pgprot(x) ((pgprot_t) { (x) } )
91#define __iopgprot(x) ((iopgprot_t) { (x) } )
92
93#else
94/*
95 * .. while these make it easier on the compiler
96 */
97typedef unsigned long pte_t;
98typedef unsigned long iopte_t;
99typedef struct { unsigned long pmdv[16]; } pmd_t;
100typedef unsigned long pgd_t;
101typedef unsigned long ctxd_t;
102typedef unsigned long pgprot_t;
103typedef unsigned long iopgprot_t;
104
105#define pte_val(x) (x)
106#define iopte_val(x) (x)
107#define pmd_val(x) ((x).pmdv[0])
108#define pgd_val(x) (x)
109#define ctxd_val(x) (x)
110#define pgprot_val(x) (x)
111#define iopgprot_val(x) (x)
112
113#define __pte(x) (x)
114#define __iopte(x) (x)
115/* #define __pmd(x) (x) */ /* XXX later */
116#define __pgd(x) (x)
117#define __ctxd(x) (x)
118#define __pgprot(x) (x)
119#define __iopgprot(x) (x)
120
121#endif
122
123typedef struct page *pgtable_t;
124
125extern unsigned long sparc_unmapped_base;
126
127BTFIXUPDEF_SETHI(sparc_unmapped_base)
128
129#define TASK_UNMAPPED_BASE BTFIXUP_SETHI(sparc_unmapped_base)
130
131#else /* !(__ASSEMBLY__) */
132
133#define __pgprot(x) (x)
134
135#endif /* !(__ASSEMBLY__) */
136
137#define PAGE_OFFSET 0xf0000000
138#ifndef __ASSEMBLY__
139extern unsigned long phys_base;
140extern unsigned long pfn_base;
141#endif
142#define __pa(x) ((unsigned long)(x) - PAGE_OFFSET + phys_base)
143#define __va(x) ((void *)((unsigned long) (x) - phys_base + PAGE_OFFSET))
144
145#define virt_to_phys __pa
146#define phys_to_virt __va
147
148#define ARCH_PFN_OFFSET (pfn_base)
149#define virt_to_page(kaddr) (mem_map + ((((unsigned long)(kaddr)-PAGE_OFFSET)>>PAGE_SHIFT)))
150
151#define pfn_valid(pfn) (((pfn) >= (pfn_base)) && (((pfn)-(pfn_base)) < max_mapnr))
152#define virt_addr_valid(kaddr) ((((unsigned long)(kaddr)-PAGE_OFFSET)>>PAGE_SHIFT) < max_mapnr)
153
154#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
155 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
156
157#include <asm-generic/memory_model.h>
158#include <asm-generic/page.h>
159
160#endif /* _SPARC_PAGE_H */
diff --git a/include/asm-sparc/page_64.h b/include/asm-sparc/page_64.h
deleted file mode 100644
index b579b910ef5..00000000000
--- a/include/asm-sparc/page_64.h
+++ /dev/null
@@ -1,135 +0,0 @@
1#ifndef _SPARC64_PAGE_H
2#define _SPARC64_PAGE_H
3
4#include <linux/const.h>
5
6#if defined(CONFIG_SPARC64_PAGE_SIZE_8KB)
7#define PAGE_SHIFT 13
8#elif defined(CONFIG_SPARC64_PAGE_SIZE_64KB)
9#define PAGE_SHIFT 16
10#else
11#error No page size specified in kernel configuration
12#endif
13
14#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT)
15#define PAGE_MASK (~(PAGE_SIZE-1))
16
17/* Flushing for D-cache alias handling is only needed if
18 * the page size is smaller than 16K.
19 */
20#if PAGE_SHIFT < 14
21#define DCACHE_ALIASING_POSSIBLE
22#endif
23
24#if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
25#define HPAGE_SHIFT 22
26#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
27#define HPAGE_SHIFT 19
28#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
29#define HPAGE_SHIFT 16
30#endif
31
32#ifdef CONFIG_HUGETLB_PAGE
33#define HPAGE_SIZE (_AC(1,UL) << HPAGE_SHIFT)
34#define HPAGE_MASK (~(HPAGE_SIZE - 1UL))
35#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
36#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
37#endif
38
39#ifndef __ASSEMBLY__
40
41extern void _clear_page(void *page);
42#define clear_page(X) _clear_page((void *)(X))
43struct page;
44extern void clear_user_page(void *addr, unsigned long vaddr, struct page *page);
45#define copy_page(X,Y) memcpy((void *)(X), (void *)(Y), PAGE_SIZE)
46extern void copy_user_page(void *to, void *from, unsigned long vaddr, struct page *topage);
47
48/* Unlike sparc32, sparc64's parameter passing API is more
49 * sane in that structures which as small enough are passed
50 * in registers instead of on the stack. Thus, setting
51 * STRICT_MM_TYPECHECKS does not generate worse code so
52 * let's enable it to get the type checking.
53 */
54
55#define STRICT_MM_TYPECHECKS
56
57#ifdef STRICT_MM_TYPECHECKS
58/* These are used to make use of C type-checking.. */
59typedef struct { unsigned long pte; } pte_t;
60typedef struct { unsigned long iopte; } iopte_t;
61typedef struct { unsigned int pmd; } pmd_t;
62typedef struct { unsigned int pgd; } pgd_t;
63typedef struct { unsigned long pgprot; } pgprot_t;
64
65#define pte_val(x) ((x).pte)
66#define iopte_val(x) ((x).iopte)
67#define pmd_val(x) ((x).pmd)
68#define pgd_val(x) ((x).pgd)
69#define pgprot_val(x) ((x).pgprot)
70
71#define __pte(x) ((pte_t) { (x) } )
72#define __iopte(x) ((iopte_t) { (x) } )
73#define __pmd(x) ((pmd_t) { (x) } )
74#define __pgd(x) ((pgd_t) { (x) } )
75#define __pgprot(x) ((pgprot_t) { (x) } )
76
77#else
78/* .. while these make it easier on the compiler */
79typedef unsigned long pte_t;
80typedef unsigned long iopte_t;
81typedef unsigned int pmd_t;
82typedef unsigned int pgd_t;
83typedef unsigned long pgprot_t;
84
85#define pte_val(x) (x)
86#define iopte_val(x) (x)
87#define pmd_val(x) (x)
88#define pgd_val(x) (x)
89#define pgprot_val(x) (x)
90
91#define __pte(x) (x)
92#define __iopte(x) (x)
93#define __pmd(x) (x)
94#define __pgd(x) (x)
95#define __pgprot(x) (x)
96
97#endif /* (STRICT_MM_TYPECHECKS) */
98
99typedef struct page *pgtable_t;
100
101#define TASK_UNMAPPED_BASE (test_thread_flag(TIF_32BIT) ? \
102 (_AC(0x0000000070000000,UL)) : \
103 (_AC(0xfffff80000000000,UL) + (1UL << 32UL)))
104
105#include <asm-generic/memory_model.h>
106
107#endif /* !(__ASSEMBLY__) */
108
109/* We used to stick this into a hard-coded global register (%g4)
110 * but that does not make sense anymore.
111 */
112#define PAGE_OFFSET _AC(0xFFFFF80000000000,UL)
113
114#ifndef __ASSEMBLY__
115
116#define __pa(x) ((unsigned long)(x) - PAGE_OFFSET)
117#define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET))
118
119#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
120
121#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr)>>PAGE_SHIFT)
122
123#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
124
125#define virt_to_phys __pa
126#define phys_to_virt __va
127
128#endif /* !(__ASSEMBLY__) */
129
130#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
131 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
132
133#include <asm-generic/page.h>
134
135#endif /* _SPARC64_PAGE_H */
diff --git a/include/asm-sparc/param.h b/include/asm-sparc/param.h
deleted file mode 100644
index 9836d9a3cb9..00000000000
--- a/include/asm-sparc/param.h
+++ /dev/null
@@ -1,22 +0,0 @@
1#ifndef _ASMSPARC_PARAM_H
2#define _ASMSPARC_PARAM_H
3
4#ifdef __KERNEL__
5# define HZ CONFIG_HZ /* Internal kernel timer frequency */
6# define USER_HZ 100 /* .. some user interfaces are in "ticks" */
7# define CLOCKS_PER_SEC (USER_HZ)
8#endif
9
10#ifndef HZ
11#define HZ 100
12#endif
13
14#define EXEC_PAGESIZE 8192 /* Thanks for sun4's we carry baggage... */
15
16#ifndef NOGROUP
17#define NOGROUP (-1)
18#endif
19
20#define MAXHOSTNAMELEN 64 /* max length of hostname */
21
22#endif
diff --git a/include/asm-sparc/parport.h b/include/asm-sparc/parport.h
deleted file mode 100644
index 7818b2523b8..00000000000
--- a/include/asm-sparc/parport.h
+++ /dev/null
@@ -1,246 +0,0 @@
1/* parport.h: sparc64 specific parport initialization and dma.
2 *
3 * Copyright (C) 1999 Eddie C. Dost (ecd@skynet.be)
4 */
5
6#ifndef _ASM_SPARC64_PARPORT_H
7#define _ASM_SPARC64_PARPORT_H 1
8
9#include <asm/ebus.h>
10#include <asm/ns87303.h>
11#include <asm/of_device.h>
12#include <asm/prom.h>
13
14#define PARPORT_PC_MAX_PORTS PARPORT_MAX
15
16/*
17 * While sparc64 doesn't have an ISA DMA API, we provide something that looks
18 * close enough to make parport_pc happy
19 */
20#define HAS_DMA
21
22static DEFINE_SPINLOCK(dma_spin_lock);
23
24#define claim_dma_lock() \
25({ unsigned long flags; \
26 spin_lock_irqsave(&dma_spin_lock, flags); \
27 flags; \
28})
29
30#define release_dma_lock(__flags) \
31 spin_unlock_irqrestore(&dma_spin_lock, __flags);
32
33static struct sparc_ebus_info {
34 struct ebus_dma_info info;
35 unsigned int addr;
36 unsigned int count;
37 int lock;
38
39 struct parport *port;
40} sparc_ebus_dmas[PARPORT_PC_MAX_PORTS];
41
42static DECLARE_BITMAP(dma_slot_map, PARPORT_PC_MAX_PORTS);
43
44static inline int request_dma(unsigned int dmanr, const char *device_id)
45{
46 if (dmanr >= PARPORT_PC_MAX_PORTS)
47 return -EINVAL;
48 if (xchg(&sparc_ebus_dmas[dmanr].lock, 1) != 0)
49 return -EBUSY;
50 return 0;
51}
52
53static inline void free_dma(unsigned int dmanr)
54{
55 if (dmanr >= PARPORT_PC_MAX_PORTS) {
56 printk(KERN_WARNING "Trying to free DMA%d\n", dmanr);
57 return;
58 }
59 if (xchg(&sparc_ebus_dmas[dmanr].lock, 0) == 0) {
60 printk(KERN_WARNING "Trying to free free DMA%d\n", dmanr);
61 return;
62 }
63}
64
65static inline void enable_dma(unsigned int dmanr)
66{
67 ebus_dma_enable(&sparc_ebus_dmas[dmanr].info, 1);
68
69 if (ebus_dma_request(&sparc_ebus_dmas[dmanr].info,
70 sparc_ebus_dmas[dmanr].addr,
71 sparc_ebus_dmas[dmanr].count))
72 BUG();
73}
74
75static inline void disable_dma(unsigned int dmanr)
76{
77 ebus_dma_enable(&sparc_ebus_dmas[dmanr].info, 0);
78}
79
80static inline void clear_dma_ff(unsigned int dmanr)
81{
82 /* nothing */
83}
84
85static inline void set_dma_mode(unsigned int dmanr, char mode)
86{
87 ebus_dma_prepare(&sparc_ebus_dmas[dmanr].info, (mode != DMA_MODE_WRITE));
88}
89
90static inline void set_dma_addr(unsigned int dmanr, unsigned int addr)
91{
92 sparc_ebus_dmas[dmanr].addr = addr;
93}
94
95static inline void set_dma_count(unsigned int dmanr, unsigned int count)
96{
97 sparc_ebus_dmas[dmanr].count = count;
98}
99
100static inline unsigned int get_dma_residue(unsigned int dmanr)
101{
102 return ebus_dma_residue(&sparc_ebus_dmas[dmanr].info);
103}
104
105static int __devinit ecpp_probe(struct of_device *op, const struct of_device_id *match)
106{
107 unsigned long base = op->resource[0].start;
108 unsigned long config = op->resource[1].start;
109 unsigned long d_base = op->resource[2].start;
110 unsigned long d_len;
111 struct device_node *parent;
112 struct parport *p;
113 int slot, err;
114
115 parent = op->node->parent;
116 if (!strcmp(parent->name, "dma")) {
117 p = parport_pc_probe_port(base, base + 0x400,
118 op->irqs[0], PARPORT_DMA_NOFIFO,
119 op->dev.parent->parent);
120 if (!p)
121 return -ENOMEM;
122 dev_set_drvdata(&op->dev, p);
123 return 0;
124 }
125
126 for (slot = 0; slot < PARPORT_PC_MAX_PORTS; slot++) {
127 if (!test_and_set_bit(slot, dma_slot_map))
128 break;
129 }
130 err = -ENODEV;
131 if (slot >= PARPORT_PC_MAX_PORTS)
132 goto out_err;
133
134 spin_lock_init(&sparc_ebus_dmas[slot].info.lock);
135
136 d_len = (op->resource[2].end - d_base) + 1UL;
137 sparc_ebus_dmas[slot].info.regs =
138 of_ioremap(&op->resource[2], 0, d_len, "ECPP DMA");
139
140 if (!sparc_ebus_dmas[slot].info.regs)
141 goto out_clear_map;
142
143 sparc_ebus_dmas[slot].info.flags = 0;
144 sparc_ebus_dmas[slot].info.callback = NULL;
145 sparc_ebus_dmas[slot].info.client_cookie = NULL;
146 sparc_ebus_dmas[slot].info.irq = 0xdeadbeef;
147 strcpy(sparc_ebus_dmas[slot].info.name, "parport");
148 if (ebus_dma_register(&sparc_ebus_dmas[slot].info))
149 goto out_unmap_regs;
150
151 ebus_dma_irq_enable(&sparc_ebus_dmas[slot].info, 1);
152
153 /* Configure IRQ to Push Pull, Level Low */
154 /* Enable ECP, set bit 2 of the CTR first */
155 outb(0x04, base + 0x02);
156 ns87303_modify(config, PCR,
157 PCR_EPP_ENABLE |
158 PCR_IRQ_ODRAIN,
159 PCR_ECP_ENABLE |
160 PCR_ECP_CLK_ENA |
161 PCR_IRQ_POLAR);
162
163 /* CTR bit 5 controls direction of port */
164 ns87303_modify(config, PTR,
165 0, PTR_LPT_REG_DIR);
166
167 p = parport_pc_probe_port(base, base + 0x400,
168 op->irqs[0],
169 slot,
170 op->dev.parent);
171 err = -ENOMEM;
172 if (!p)
173 goto out_disable_irq;
174
175 dev_set_drvdata(&op->dev, p);
176
177 return 0;
178
179out_disable_irq:
180 ebus_dma_irq_enable(&sparc_ebus_dmas[slot].info, 0);
181 ebus_dma_unregister(&sparc_ebus_dmas[slot].info);
182
183out_unmap_regs:
184 of_iounmap(&op->resource[2], sparc_ebus_dmas[slot].info.regs, d_len);
185
186out_clear_map:
187 clear_bit(slot, dma_slot_map);
188
189out_err:
190 return err;
191}
192
193static int __devexit ecpp_remove(struct of_device *op)
194{
195 struct parport *p = dev_get_drvdata(&op->dev);
196 int slot = p->dma;
197
198 parport_pc_unregister_port(p);
199
200 if (slot != PARPORT_DMA_NOFIFO) {
201 unsigned long d_base = op->resource[2].start;
202 unsigned long d_len;
203
204 d_len = (op->resource[2].end - d_base) + 1UL;
205
206 ebus_dma_irq_enable(&sparc_ebus_dmas[slot].info, 0);
207 ebus_dma_unregister(&sparc_ebus_dmas[slot].info);
208 of_iounmap(&op->resource[2],
209 sparc_ebus_dmas[slot].info.regs,
210 d_len);
211 clear_bit(slot, dma_slot_map);
212 }
213
214 return 0;
215}
216
217static struct of_device_id ecpp_match[] = {
218 {
219 .name = "ecpp",
220 },
221 {
222 .name = "parallel",
223 .compatible = "ecpp",
224 },
225 {
226 .name = "parallel",
227 .compatible = "ns87317-ecpp",
228 },
229 {},
230};
231
232static struct of_platform_driver ecpp_driver = {
233 .name = "ecpp",
234 .match_table = ecpp_match,
235 .probe = ecpp_probe,
236 .remove = __devexit_p(ecpp_remove),
237};
238
239static int parport_pc_find_nonpci_ports(int autoirq, int autodma)
240{
241 of_register_driver(&ecpp_driver, &of_bus_type);
242
243 return 0;
244}
245
246#endif /* !(_ASM_SPARC64_PARPORT_H */
diff --git a/include/asm-sparc/pbm.h b/include/asm-sparc/pbm.h
deleted file mode 100644
index 458a4916d14..00000000000
--- a/include/asm-sparc/pbm.h
+++ /dev/null
@@ -1,47 +0,0 @@
1/*
2 *
3 * pbm.h: PCI bus module pseudo driver software state
4 * Adopted from sparc64 by V. Roganov and G. Raiko
5 *
6 * Original header:
7 * pbm.h: U2P PCI bus module pseudo driver software state.
8 *
9 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
10 *
11 * To put things into perspective, consider sparc64 with a few PCI controllers.
12 * Each type would have an own structure, with instances related one to one.
13 * We have only pcic on sparc, but we want to be compatible with sparc64 pbm.h.
14 * All three represent different abstractions.
15 * pci_bus - Linux PCI subsystem view of a PCI bus (including bridged buses)
16 * pbm - Arch-specific view of a PCI bus (sparc or sparc64)
17 * pcic - Chip-specific information for PCIC.
18 */
19
20#ifndef __SPARC_PBM_H
21#define __SPARC_PBM_H
22
23#include <linux/pci.h>
24#include <asm/oplib.h>
25#include <asm/prom.h>
26
27struct linux_pbm_info {
28 int prom_node;
29 char prom_name[64];
30 /* struct linux_prom_pci_ranges pbm_ranges[PROMREG_MAX]; */
31 /* int num_pbm_ranges; */
32
33 /* Now things for the actual PCI bus probes. */
34 unsigned int pci_first_busno; /* Can it be nonzero? */
35 struct pci_bus *pci_bus; /* Was inline, MJ allocs now */
36};
37
38/* PCI devices which are not bridges have this placed in their pci_dev
39 * sysdata member. This makes OBP aware PCI device drivers easier to
40 * code.
41 */
42struct pcidev_cookie {
43 struct linux_pbm_info *pbm;
44 struct device_node *prom_node;
45};
46
47#endif /* !(__SPARC_PBM_H) */
diff --git a/include/asm-sparc/pci.h b/include/asm-sparc/pci.h
deleted file mode 100644
index b807d52a480..00000000000
--- a/include/asm-sparc/pci.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_PCI_H
2#define ___ASM_SPARC_PCI_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/pci_64.h>
5#else
6#include <asm-sparc/pci_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/pci_32.h b/include/asm-sparc/pci_32.h
deleted file mode 100644
index 0ee949d220c..00000000000
--- a/include/asm-sparc/pci_32.h
+++ /dev/null
@@ -1,171 +0,0 @@
1#ifndef __SPARC_PCI_H
2#define __SPARC_PCI_H
3
4#ifdef __KERNEL__
5
6/* Can be used to override the logic in pci_scan_bus for skipping
7 * already-configured bus numbers - to be used for buggy BIOSes
8 * or architectures with incomplete PCI setup by the loader.
9 */
10#define pcibios_assign_all_busses() 0
11#define pcibios_scan_all_fns(a, b) 0
12
13#define PCIBIOS_MIN_IO 0UL
14#define PCIBIOS_MIN_MEM 0UL
15
16#define PCI_IRQ_NONE 0xffffffff
17
18static inline void pcibios_set_master(struct pci_dev *dev)
19{
20 /* No special bus mastering setup handling */
21}
22
23static inline void pcibios_penalize_isa_irq(int irq, int active)
24{
25 /* We don't do dynamic PCI IRQ allocation */
26}
27
28/* Dynamic DMA mapping stuff.
29 */
30#define PCI_DMA_BUS_IS_PHYS (0)
31
32#include <asm/scatterlist.h>
33
34struct pci_dev;
35
36/* Allocate and map kernel buffer using consistent mode DMA for a device.
37 * hwdev should be valid struct pci_dev pointer for PCI devices.
38 */
39extern void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size, dma_addr_t *dma_handle);
40
41/* Free and unmap a consistent DMA buffer.
42 * cpu_addr is what was returned from pci_alloc_consistent,
43 * size must be the same as what as passed into pci_alloc_consistent,
44 * and likewise dma_addr must be the same as what *dma_addrp was set to.
45 *
46 * References to the memory and mappings assosciated with cpu_addr/dma_addr
47 * past this call are illegal.
48 */
49extern void pci_free_consistent(struct pci_dev *hwdev, size_t size, void *vaddr, dma_addr_t dma_handle);
50
51/* Map a single buffer of the indicated size for DMA in streaming mode.
52 * The 32-bit bus address to use is returned.
53 *
54 * Once the device is given the dma address, the device owns this memory
55 * until either pci_unmap_single or pci_dma_sync_single_for_cpu is performed.
56 */
57extern dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, int direction);
58
59/* Unmap a single streaming mode DMA translation. The dma_addr and size
60 * must match what was provided for in a previous pci_map_single call. All
61 * other usages are undefined.
62 *
63 * After this call, reads by the cpu to the buffer are guaranteed to see
64 * whatever the device wrote there.
65 */
66extern void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr, size_t size, int direction);
67
68/* pci_unmap_{single,page} is not a nop, thus... */
69#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
70 dma_addr_t ADDR_NAME;
71#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
72 __u32 LEN_NAME;
73#define pci_unmap_addr(PTR, ADDR_NAME) \
74 ((PTR)->ADDR_NAME)
75#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
76 (((PTR)->ADDR_NAME) = (VAL))
77#define pci_unmap_len(PTR, LEN_NAME) \
78 ((PTR)->LEN_NAME)
79#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
80 (((PTR)->LEN_NAME) = (VAL))
81
82/*
83 * Same as above, only with pages instead of mapped addresses.
84 */
85extern dma_addr_t pci_map_page(struct pci_dev *hwdev, struct page *page,
86 unsigned long offset, size_t size, int direction);
87extern void pci_unmap_page(struct pci_dev *hwdev,
88 dma_addr_t dma_address, size_t size, int direction);
89
90/* Map a set of buffers described by scatterlist in streaming
91 * mode for DMA. This is the scather-gather version of the
92 * above pci_map_single interface. Here the scatter gather list
93 * elements are each tagged with the appropriate dma address
94 * and length. They are obtained via sg_dma_{address,length}(SG).
95 *
96 * NOTE: An implementation may be able to use a smaller number of
97 * DMA address/length pairs than there are SG table elements.
98 * (for example via virtual mapping capabilities)
99 * The routine returns the number of addr/length pairs actually
100 * used, at most nents.
101 *
102 * Device ownership issues as mentioned above for pci_map_single are
103 * the same here.
104 */
105extern int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int direction);
106
107/* Unmap a set of streaming mode DMA translations.
108 * Again, cpu read rules concerning calls here are the same as for
109 * pci_unmap_single() above.
110 */
111extern void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nhwents, int direction);
112
113/* Make physical memory consistent for a single
114 * streaming mode DMA translation after a transfer.
115 *
116 * If you perform a pci_map_single() but wish to interrogate the
117 * buffer using the cpu, yet do not wish to teardown the PCI dma
118 * mapping, you must call this function before doing so. At the
119 * next point you give the PCI dma address back to the card, you
120 * must first perform a pci_dma_sync_for_device, and then the device
121 * again owns the buffer.
122 */
123extern void pci_dma_sync_single_for_cpu(struct pci_dev *hwdev, dma_addr_t dma_handle, size_t size, int direction);
124extern void pci_dma_sync_single_for_device(struct pci_dev *hwdev, dma_addr_t dma_handle, size_t size, int direction);
125
126/* Make physical memory consistent for a set of streaming
127 * mode DMA translations after a transfer.
128 *
129 * The same as pci_dma_sync_single_* but for a scatter-gather list,
130 * same rules and usage.
131 */
132extern void pci_dma_sync_sg_for_cpu(struct pci_dev *hwdev, struct scatterlist *sg, int nelems, int direction);
133extern void pci_dma_sync_sg_for_device(struct pci_dev *hwdev, struct scatterlist *sg, int nelems, int direction);
134
135/* Return whether the given PCI device DMA address mask can
136 * be supported properly. For example, if your device can
137 * only drive the low 24-bits during PCI bus mastering, then
138 * you would pass 0x00ffffff as the mask to this function.
139 */
140static inline int pci_dma_supported(struct pci_dev *hwdev, u64 mask)
141{
142 return 1;
143}
144
145#ifdef CONFIG_PCI
146static inline void pci_dma_burst_advice(struct pci_dev *pdev,
147 enum pci_dma_burst_strategy *strat,
148 unsigned long *strategy_parameter)
149{
150 *strat = PCI_DMA_BURST_INFINITY;
151 *strategy_parameter = ~0UL;
152}
153#endif
154
155#define PCI_DMA_ERROR_CODE (~(dma_addr_t)0x0)
156
157static inline int pci_dma_mapping_error(struct pci_dev *pdev,
158 dma_addr_t dma_addr)
159{
160 return (dma_addr == PCI_DMA_ERROR_CODE);
161}
162
163struct device_node;
164extern struct device_node *pci_device_to_OF_node(struct pci_dev *pdev);
165
166#endif /* __KERNEL__ */
167
168/* generic pci stuff */
169#include <asm-generic/pci.h>
170
171#endif /* __SPARC_PCI_H */
diff --git a/include/asm-sparc/pci_64.h b/include/asm-sparc/pci_64.h
deleted file mode 100644
index 4f79a54948f..00000000000
--- a/include/asm-sparc/pci_64.h
+++ /dev/null
@@ -1,210 +0,0 @@
1#ifndef __SPARC64_PCI_H
2#define __SPARC64_PCI_H
3
4#ifdef __KERNEL__
5
6#include <linux/dma-mapping.h>
7
8/* Can be used to override the logic in pci_scan_bus for skipping
9 * already-configured bus numbers - to be used for buggy BIOSes
10 * or architectures with incomplete PCI setup by the loader.
11 */
12#define pcibios_assign_all_busses() 0
13#define pcibios_scan_all_fns(a, b) 0
14
15#define PCIBIOS_MIN_IO 0UL
16#define PCIBIOS_MIN_MEM 0UL
17
18#define PCI_IRQ_NONE 0xffffffff
19
20#define PCI_CACHE_LINE_BYTES 64
21
22static inline void pcibios_set_master(struct pci_dev *dev)
23{
24 /* No special bus mastering setup handling */
25}
26
27static inline void pcibios_penalize_isa_irq(int irq, int active)
28{
29 /* We don't do dynamic PCI IRQ allocation */
30}
31
32/* The PCI address space does not equal the physical memory
33 * address space. The networking and block device layers use
34 * this boolean for bounce buffer decisions.
35 */
36#define PCI_DMA_BUS_IS_PHYS (0)
37
38static inline void *pci_alloc_consistent(struct pci_dev *pdev, size_t size,
39 dma_addr_t *dma_handle)
40{
41 return dma_alloc_coherent(&pdev->dev, size, dma_handle, GFP_ATOMIC);
42}
43
44static inline void pci_free_consistent(struct pci_dev *pdev, size_t size,
45 void *vaddr, dma_addr_t dma_handle)
46{
47 return dma_free_coherent(&pdev->dev, size, vaddr, dma_handle);
48}
49
50static inline dma_addr_t pci_map_single(struct pci_dev *pdev, void *ptr,
51 size_t size, int direction)
52{
53 return dma_map_single(&pdev->dev, ptr, size,
54 (enum dma_data_direction) direction);
55}
56
57static inline void pci_unmap_single(struct pci_dev *pdev, dma_addr_t dma_addr,
58 size_t size, int direction)
59{
60 dma_unmap_single(&pdev->dev, dma_addr, size,
61 (enum dma_data_direction) direction);
62}
63
64#define pci_map_page(dev, page, off, size, dir) \
65 pci_map_single(dev, (page_address(page) + (off)), size, dir)
66#define pci_unmap_page(dev,addr,sz,dir) \
67 pci_unmap_single(dev,addr,sz,dir)
68
69/* pci_unmap_{single,page} is not a nop, thus... */
70#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
71 dma_addr_t ADDR_NAME;
72#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
73 __u32 LEN_NAME;
74#define pci_unmap_addr(PTR, ADDR_NAME) \
75 ((PTR)->ADDR_NAME)
76#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
77 (((PTR)->ADDR_NAME) = (VAL))
78#define pci_unmap_len(PTR, LEN_NAME) \
79 ((PTR)->LEN_NAME)
80#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
81 (((PTR)->LEN_NAME) = (VAL))
82
83static inline int pci_map_sg(struct pci_dev *pdev, struct scatterlist *sg,
84 int nents, int direction)
85{
86 return dma_map_sg(&pdev->dev, sg, nents,
87 (enum dma_data_direction) direction);
88}
89
90static inline void pci_unmap_sg(struct pci_dev *pdev, struct scatterlist *sg,
91 int nents, int direction)
92{
93 dma_unmap_sg(&pdev->dev, sg, nents,
94 (enum dma_data_direction) direction);
95}
96
97static inline void pci_dma_sync_single_for_cpu(struct pci_dev *pdev,
98 dma_addr_t dma_handle,
99 size_t size, int direction)
100{
101 dma_sync_single_for_cpu(&pdev->dev, dma_handle, size,
102 (enum dma_data_direction) direction);
103}
104
105static inline void pci_dma_sync_single_for_device(struct pci_dev *pdev,
106 dma_addr_t dma_handle,
107 size_t size, int direction)
108{
109 /* No flushing needed to sync cpu writes to the device. */
110}
111
112static inline void pci_dma_sync_sg_for_cpu(struct pci_dev *pdev,
113 struct scatterlist *sg,
114 int nents, int direction)
115{
116 dma_sync_sg_for_cpu(&pdev->dev, sg, nents,
117 (enum dma_data_direction) direction);
118}
119
120static inline void pci_dma_sync_sg_for_device(struct pci_dev *pdev,
121 struct scatterlist *sg,
122 int nelems, int direction)
123{
124 /* No flushing needed to sync cpu writes to the device. */
125}
126
127/* Return whether the given PCI device DMA address mask can
128 * be supported properly. For example, if your device can
129 * only drive the low 24-bits during PCI bus mastering, then
130 * you would pass 0x00ffffff as the mask to this function.
131 */
132extern int pci_dma_supported(struct pci_dev *hwdev, u64 mask);
133
134/* PCI IOMMU mapping bypass support. */
135
136/* PCI 64-bit addressing works for all slots on all controller
137 * types on sparc64. However, it requires that the device
138 * can drive enough of the 64 bits.
139 */
140#define PCI64_REQUIRED_MASK (~(dma64_addr_t)0)
141#define PCI64_ADDR_BASE 0xfffc000000000000UL
142
143static inline int pci_dma_mapping_error(struct pci_dev *pdev,
144 dma_addr_t dma_addr)
145{
146 return dma_mapping_error(&pdev->dev, dma_addr);
147}
148
149#ifdef CONFIG_PCI
150static inline void pci_dma_burst_advice(struct pci_dev *pdev,
151 enum pci_dma_burst_strategy *strat,
152 unsigned long *strategy_parameter)
153{
154 unsigned long cacheline_size;
155 u8 byte;
156
157 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
158 if (byte == 0)
159 cacheline_size = 1024;
160 else
161 cacheline_size = (int) byte * 4;
162
163 *strat = PCI_DMA_BURST_BOUNDARY;
164 *strategy_parameter = cacheline_size;
165}
166#endif
167
168/* Return the index of the PCI controller for device PDEV. */
169
170extern int pci_domain_nr(struct pci_bus *bus);
171static inline int pci_proc_domain(struct pci_bus *bus)
172{
173 return 1;
174}
175
176/* Platform support for /proc/bus/pci/X/Y mmap()s. */
177
178#define HAVE_PCI_MMAP
179#define HAVE_ARCH_PCI_GET_UNMAPPED_AREA
180#define get_pci_unmapped_area get_fb_unmapped_area
181
182extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
183 enum pci_mmap_state mmap_state,
184 int write_combine);
185
186extern void
187pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
188 struct resource *res);
189
190extern void
191pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
192 struct pci_bus_region *region);
193
194extern struct resource *pcibios_select_root(struct pci_dev *, struct resource *);
195
196static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
197{
198 return PCI_IRQ_NONE;
199}
200
201struct device_node;
202extern struct device_node *pci_device_to_OF_node(struct pci_dev *pdev);
203
204#define HAVE_ARCH_PCI_RESOURCE_TO_USER
205extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
206 const struct resource *rsrc,
207 resource_size_t *start, resource_size_t *end);
208#endif /* __KERNEL__ */
209
210#endif /* __SPARC64_PCI_H */
diff --git a/include/asm-sparc/pcic.h b/include/asm-sparc/pcic.h
deleted file mode 100644
index f20ef562b26..00000000000
--- a/include/asm-sparc/pcic.h
+++ /dev/null
@@ -1,123 +0,0 @@
1/*
2 * pcic.h: JavaEngine 1 specific PCI definitions.
3 *
4 * Copyright (C) 1998 V. Roganov and G. Raiko
5 */
6
7#ifndef __SPARC_PCIC_H
8#define __SPARC_PCIC_H
9
10#ifndef __ASSEMBLY__
11
12#include <linux/types.h>
13#include <linux/smp.h>
14#include <linux/pci.h>
15#include <linux/ioport.h>
16#include <asm/pbm.h>
17
18struct linux_pcic {
19 void __iomem *pcic_regs;
20 unsigned long pcic_io;
21 void __iomem *pcic_config_space_addr;
22 void __iomem *pcic_config_space_data;
23 struct resource pcic_res_regs;
24 struct resource pcic_res_io;
25 struct resource pcic_res_cfg_addr;
26 struct resource pcic_res_cfg_data;
27 struct linux_pbm_info pbm;
28 struct pcic_ca2irq *pcic_imap;
29 int pcic_imdim;
30};
31
32extern int pcic_probe(void);
33/* Erm... MJ redefined pcibios_present() so that it does not work early. */
34extern int pcic_present(void);
35extern void sun4m_pci_init_IRQ(void);
36
37#endif
38
39/* Size of PCI I/O space which we relocate. */
40#define PCI_SPACE_SIZE 0x1000000 /* 16 MB */
41
42/* PCIC Register Set. */
43#define PCI_DIAGNOSTIC_0 0x40 /* 32 bits */
44#define PCI_SIZE_0 0x44 /* 32 bits */
45#define PCI_SIZE_1 0x48 /* 32 bits */
46#define PCI_SIZE_2 0x4c /* 32 bits */
47#define PCI_SIZE_3 0x50 /* 32 bits */
48#define PCI_SIZE_4 0x54 /* 32 bits */
49#define PCI_SIZE_5 0x58 /* 32 bits */
50#define PCI_PIO_CONTROL 0x60 /* 8 bits */
51#define PCI_DVMA_CONTROL 0x62 /* 8 bits */
52#define PCI_DVMA_CONTROL_INACTIVITY_REQ (1<<0)
53#define PCI_DVMA_CONTROL_IOTLB_ENABLE (1<<0)
54#define PCI_DVMA_CONTROL_IOTLB_DISABLE 0
55#define PCI_DVMA_CONTROL_INACTIVITY_ACK (1<<4)
56#define PCI_INTERRUPT_CONTROL 0x63 /* 8 bits */
57#define PCI_CPU_INTERRUPT_PENDING 0x64 /* 32 bits */
58#define PCI_DIAGNOSTIC_1 0x68 /* 16 bits */
59#define PCI_SOFTWARE_INT_CLEAR 0x6a /* 16 bits */
60#define PCI_SOFTWARE_INT_SET 0x6e /* 16 bits */
61#define PCI_SYS_INT_PENDING 0x70 /* 32 bits */
62#define PCI_SYS_INT_PENDING_PIO 0x40000000
63#define PCI_SYS_INT_PENDING_DMA 0x20000000
64#define PCI_SYS_INT_PENDING_PCI 0x10000000
65#define PCI_SYS_INT_PENDING_APSR 0x08000000
66#define PCI_SYS_INT_TARGET_MASK 0x74 /* 32 bits */
67#define PCI_SYS_INT_TARGET_MASK_CLEAR 0x78 /* 32 bits */
68#define PCI_SYS_INT_TARGET_MASK_SET 0x7c /* 32 bits */
69#define PCI_SYS_INT_PENDING_CLEAR 0x83 /* 8 bits */
70#define PCI_SYS_INT_PENDING_CLEAR_ALL 0x80
71#define PCI_SYS_INT_PENDING_CLEAR_PIO 0x40
72#define PCI_SYS_INT_PENDING_CLEAR_DMA 0x20
73#define PCI_SYS_INT_PENDING_CLEAR_PCI 0x10
74#define PCI_IOTLB_CONTROL 0x84 /* 8 bits */
75#define PCI_INT_SELECT_LO 0x88 /* 16 bits */
76#define PCI_ARBITRATION_SELECT 0x8a /* 16 bits */
77#define PCI_INT_SELECT_HI 0x8c /* 16 bits */
78#define PCI_HW_INT_OUTPUT 0x8e /* 16 bits */
79#define PCI_IOTLB_RAM_INPUT 0x90 /* 32 bits */
80#define PCI_IOTLB_CAM_INPUT 0x94 /* 32 bits */
81#define PCI_IOTLB_RAM_OUTPUT 0x98 /* 32 bits */
82#define PCI_IOTLB_CAM_OUTPUT 0x9c /* 32 bits */
83#define PCI_SMBAR0 0xa0 /* 8 bits */
84#define PCI_MSIZE0 0xa1 /* 8 bits */
85#define PCI_PMBAR0 0xa2 /* 8 bits */
86#define PCI_SMBAR1 0xa4 /* 8 bits */
87#define PCI_MSIZE1 0xa5 /* 8 bits */
88#define PCI_PMBAR1 0xa6 /* 8 bits */
89#define PCI_SIBAR 0xa8 /* 8 bits */
90#define PCI_SIBAR_ADDRESS_MASK 0xf
91#define PCI_ISIZE 0xa9 /* 8 bits */
92#define PCI_ISIZE_16M 0xf
93#define PCI_ISIZE_32M 0xe
94#define PCI_ISIZE_64M 0xc
95#define PCI_ISIZE_128M 0x8
96#define PCI_ISIZE_256M 0x0
97#define PCI_PIBAR 0xaa /* 8 bits */
98#define PCI_CPU_COUNTER_LIMIT_HI 0xac /* 32 bits */
99#define PCI_CPU_COUNTER_LIMIT_LO 0xb0 /* 32 bits */
100#define PCI_CPU_COUNTER_LIMIT 0xb4 /* 32 bits */
101#define PCI_SYS_LIMIT 0xb8 /* 32 bits */
102#define PCI_SYS_COUNTER 0xbc /* 32 bits */
103#define PCI_SYS_COUNTER_OVERFLOW (1<<31) /* Limit reached */
104#define PCI_SYS_LIMIT_PSEUDO 0xc0 /* 32 bits */
105#define PCI_USER_TIMER_CONTROL 0xc4 /* 8 bits */
106#define PCI_USER_TIMER_CONFIG 0xc5 /* 8 bits */
107#define PCI_COUNTER_IRQ 0xc6 /* 8 bits */
108#define PCI_COUNTER_IRQ_SET(sys_irq, cpu_irq) ((((sys_irq) & 0xf) << 4) | \
109 ((cpu_irq) & 0xf))
110#define PCI_COUNTER_IRQ_SYS(v) (((v) >> 4) & 0xf)
111#define PCI_COUNTER_IRQ_CPU(v) ((v) & 0xf)
112#define PCI_PIO_ERROR_COMMAND 0xc7 /* 8 bits */
113#define PCI_PIO_ERROR_ADDRESS 0xc8 /* 32 bits */
114#define PCI_IOTLB_ERROR_ADDRESS 0xcc /* 32 bits */
115#define PCI_SYS_STATUS 0xd0 /* 8 bits */
116#define PCI_SYS_STATUS_RESET_ENABLE (1<<0)
117#define PCI_SYS_STATUS_RESET (1<<1)
118#define PCI_SYS_STATUS_WATCHDOG_RESET (1<<4)
119#define PCI_SYS_STATUS_PCI_RESET (1<<5)
120#define PCI_SYS_STATUS_PCI_RESET_ENABLE (1<<6)
121#define PCI_SYS_STATUS_PCI_SATTELITE_MODE (1<<7)
122
123#endif /* !(__SPARC_PCIC_H) */
diff --git a/include/asm-sparc/percpu.h b/include/asm-sparc/percpu.h
deleted file mode 100644
index d98ed6cf2e3..00000000000
--- a/include/asm-sparc/percpu.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_PERCPU_H
2#define ___ASM_SPARC_PERCPU_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/percpu_64.h>
5#else
6#include <asm-sparc/percpu_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/percpu_32.h b/include/asm-sparc/percpu_32.h
deleted file mode 100644
index 06066a7aaec..00000000000
--- a/include/asm-sparc/percpu_32.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef __ARCH_SPARC_PERCPU__
2#define __ARCH_SPARC_PERCPU__
3
4#include <asm-generic/percpu.h>
5
6#endif /* __ARCH_SPARC_PERCPU__ */
diff --git a/include/asm-sparc/percpu_64.h b/include/asm-sparc/percpu_64.h
deleted file mode 100644
index bee64593023..00000000000
--- a/include/asm-sparc/percpu_64.h
+++ /dev/null
@@ -1,28 +0,0 @@
1#ifndef __ARCH_SPARC64_PERCPU__
2#define __ARCH_SPARC64_PERCPU__
3
4#include <linux/compiler.h>
5
6register unsigned long __local_per_cpu_offset asm("g5");
7
8#ifdef CONFIG_SMP
9
10extern void real_setup_per_cpu_areas(void);
11
12extern unsigned long __per_cpu_base;
13extern unsigned long __per_cpu_shift;
14#define __per_cpu_offset(__cpu) \
15 (__per_cpu_base + ((unsigned long)(__cpu) << __per_cpu_shift))
16#define per_cpu_offset(x) (__per_cpu_offset(x))
17
18#define __my_cpu_offset __local_per_cpu_offset
19
20#else /* ! SMP */
21
22#define real_setup_per_cpu_areas() do { } while (0)
23
24#endif /* SMP */
25
26#include <asm-generic/percpu.h>
27
28#endif /* __ARCH_SPARC64_PERCPU__ */
diff --git a/include/asm-sparc/perfctr.h b/include/asm-sparc/perfctr.h
deleted file mode 100644
index 836873002b7..00000000000
--- a/include/asm-sparc/perfctr.h
+++ /dev/null
@@ -1,173 +0,0 @@
1/*----------------------------------------
2 PERFORMANCE INSTRUMENTATION
3 Guillaume Thouvenin 08/10/98
4 David S. Miller 10/06/98
5 ---------------------------------------*/
6#ifndef PERF_COUNTER_API
7#define PERF_COUNTER_API
8
9/* sys_perfctr() interface. First arg is operation code
10 * from enumeration below. The meaning of further arguments
11 * are determined by the operation code.
12 *
13 * int sys_perfctr(int opcode, unsigned long arg0,
14 * unsigned long arg1, unsigned long arg2)
15 *
16 * Pointers which are passed by the user are pointers to 64-bit
17 * integers.
18 *
19 * Once enabled, performance counter state is retained until the
20 * process either exits or performs an exec. That is, performance
21 * counters remain enabled for fork/clone children.
22 */
23enum perfctr_opcode {
24 /* Enable UltraSparc performance counters, ARG0 is pointer
25 * to 64-bit accumulator for D0 counter in PIC, ARG1 is pointer
26 * to 64-bit accumulator for D1 counter. ARG2 is a pointer to
27 * the initial PCR register value to use.
28 */
29 PERFCTR_ON,
30
31 /* Disable UltraSparc performance counters. The PCR is written
32 * with zero and the user counter accumulator pointers and
33 * working PCR register value are forgotten.
34 */
35 PERFCTR_OFF,
36
37 /* Add current D0 and D1 PIC values into user pointers given
38 * in PERFCTR_ON operation. The PIC is cleared before returning.
39 */
40 PERFCTR_READ,
41
42 /* Clear the PIC register. */
43 PERFCTR_CLRPIC,
44
45 /* Begin using a new PCR value, the pointer to which is passed
46 * in ARG0. The PIC is also cleared after the new PCR value is
47 * written.
48 */
49 PERFCTR_SETPCR,
50
51 /* Store in pointer given in ARG0 the current PCR register value
52 * being used.
53 */
54 PERFCTR_GETPCR
55};
56
57/* I don't want the kernel's namespace to be polluted with this
58 * stuff when this file is included. --DaveM
59 */
60#ifndef __KERNEL__
61
62#define PRIV 0x00000001
63#define SYS 0x00000002
64#define USR 0x00000004
65
66/* Pic.S0 Selection Bit Field Encoding, Ultra-I/II */
67#define CYCLE_CNT 0x00000000
68#define INSTR_CNT 0x00000010
69#define DISPATCH0_IC_MISS 0x00000020
70#define DISPATCH0_STOREBUF 0x00000030
71#define IC_REF 0x00000080
72#define DC_RD 0x00000090
73#define DC_WR 0x000000A0
74#define LOAD_USE 0x000000B0
75#define EC_REF 0x000000C0
76#define EC_WRITE_HIT_RDO 0x000000D0
77#define EC_SNOOP_INV 0x000000E0
78#define EC_RD_HIT 0x000000F0
79
80/* Pic.S0 Selection Bit Field Encoding, Ultra-III */
81#define US3_CYCLE_CNT 0x00000000
82#define US3_INSTR_CNT 0x00000010
83#define US3_DISPATCH0_IC_MISS 0x00000020
84#define US3_DISPATCH0_BR_TGT 0x00000030
85#define US3_DISPATCH0_2ND_BR 0x00000040
86#define US3_RSTALL_STOREQ 0x00000050
87#define US3_RSTALL_IU_USE 0x00000060
88#define US3_IC_REF 0x00000080
89#define US3_DC_RD 0x00000090
90#define US3_DC_WR 0x000000a0
91#define US3_EC_REF 0x000000c0
92#define US3_EC_WR_HIT_RTO 0x000000d0
93#define US3_EC_SNOOP_INV 0x000000e0
94#define US3_EC_RD_MISS 0x000000f0
95#define US3_PC_PORT0_RD 0x00000100
96#define US3_SI_SNOOP 0x00000110
97#define US3_SI_CIQ_FLOW 0x00000120
98#define US3_SI_OWNED 0x00000130
99#define US3_SW_COUNT_0 0x00000140
100#define US3_IU_BR_MISS_TAKEN 0x00000150
101#define US3_IU_BR_COUNT_TAKEN 0x00000160
102#define US3_DISP_RS_MISPRED 0x00000170
103#define US3_FA_PIPE_COMPL 0x00000180
104#define US3_MC_READS_0 0x00000200
105#define US3_MC_READS_1 0x00000210
106#define US3_MC_READS_2 0x00000220
107#define US3_MC_READS_3 0x00000230
108#define US3_MC_STALLS_0 0x00000240
109#define US3_MC_STALLS_2 0x00000250
110
111/* Pic.S1 Selection Bit Field Encoding, Ultra-I/II */
112#define CYCLE_CNT_D1 0x00000000
113#define INSTR_CNT_D1 0x00000800
114#define DISPATCH0_IC_MISPRED 0x00001000
115#define DISPATCH0_FP_USE 0x00001800
116#define IC_HIT 0x00004000
117#define DC_RD_HIT 0x00004800
118#define DC_WR_HIT 0x00005000
119#define LOAD_USE_RAW 0x00005800
120#define EC_HIT 0x00006000
121#define EC_WB 0x00006800
122#define EC_SNOOP_CB 0x00007000
123#define EC_IT_HIT 0x00007800
124
125/* Pic.S1 Selection Bit Field Encoding, Ultra-III */
126#define US3_CYCLE_CNT_D1 0x00000000
127#define US3_INSTR_CNT_D1 0x00000800
128#define US3_DISPATCH0_MISPRED 0x00001000
129#define US3_IC_MISS_CANCELLED 0x00001800
130#define US3_RE_ENDIAN_MISS 0x00002000
131#define US3_RE_FPU_BYPASS 0x00002800
132#define US3_RE_DC_MISS 0x00003000
133#define US3_RE_EC_MISS 0x00003800
134#define US3_IC_MISS 0x00004000
135#define US3_DC_RD_MISS 0x00004800
136#define US3_DC_WR_MISS 0x00005000
137#define US3_RSTALL_FP_USE 0x00005800
138#define US3_EC_MISSES 0x00006000
139#define US3_EC_WB 0x00006800
140#define US3_EC_SNOOP_CB 0x00007000
141#define US3_EC_IC_MISS 0x00007800
142#define US3_RE_PC_MISS 0x00008000
143#define US3_ITLB_MISS 0x00008800
144#define US3_DTLB_MISS 0x00009000
145#define US3_WC_MISS 0x00009800
146#define US3_WC_SNOOP_CB 0x0000a000
147#define US3_WC_SCRUBBED 0x0000a800
148#define US3_WC_WB_WO_READ 0x0000b000
149#define US3_PC_SOFT_HIT 0x0000c000
150#define US3_PC_SNOOP_INV 0x0000c800
151#define US3_PC_HARD_HIT 0x0000d000
152#define US3_PC_PORT1_RD 0x0000d800
153#define US3_SW_COUNT_1 0x0000e000
154#define US3_IU_STAT_BR_MIS_UNTAKEN 0x0000e800
155#define US3_IU_STAT_BR_COUNT_UNTAKEN 0x0000f000
156#define US3_PC_MS_MISSES 0x0000f800
157#define US3_MC_WRITES_0 0x00010800
158#define US3_MC_WRITES_1 0x00011000
159#define US3_MC_WRITES_2 0x00011800
160#define US3_MC_WRITES_3 0x00012000
161#define US3_MC_STALLS_1 0x00012800
162#define US3_MC_STALLS_3 0x00013000
163#define US3_RE_RAW_MISS 0x00013800
164#define US3_FM_PIPE_COMPLETION 0x00014000
165
166struct vcounter_struct {
167 unsigned long long vcnt0;
168 unsigned long long vcnt1;
169};
170
171#endif /* !(__KERNEL__) */
172
173#endif /* !(PERF_COUNTER_API) */
diff --git a/include/asm-sparc/pgalloc.h b/include/asm-sparc/pgalloc.h
deleted file mode 100644
index 7fa02b53d39..00000000000
--- a/include/asm-sparc/pgalloc.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_PGALLOC_H
2#define ___ASM_SPARC_PGALLOC_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/pgalloc_64.h>
5#else
6#include <asm-sparc/pgalloc_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/pgalloc_32.h b/include/asm-sparc/pgalloc_32.h
deleted file mode 100644
index 681582d2696..00000000000
--- a/include/asm-sparc/pgalloc_32.h
+++ /dev/null
@@ -1,68 +0,0 @@
1#ifndef _SPARC_PGALLOC_H
2#define _SPARC_PGALLOC_H
3
4#include <linux/kernel.h>
5#include <linux/sched.h>
6
7#include <asm/page.h>
8#include <asm/btfixup.h>
9
10struct page;
11
12extern struct pgtable_cache_struct {
13 unsigned long *pgd_cache;
14 unsigned long *pte_cache;
15 unsigned long pgtable_cache_sz;
16 unsigned long pgd_cache_sz;
17} pgt_quicklists;
18#define pgd_quicklist (pgt_quicklists.pgd_cache)
19#define pmd_quicklist ((unsigned long *)0)
20#define pte_quicklist (pgt_quicklists.pte_cache)
21#define pgtable_cache_size (pgt_quicklists.pgtable_cache_sz)
22#define pgd_cache_size (pgt_quicklists.pgd_cache_sz)
23
24extern void check_pgt_cache(void);
25BTFIXUPDEF_CALL(void, do_check_pgt_cache, int, int)
26#define do_check_pgt_cache(low,high) BTFIXUP_CALL(do_check_pgt_cache)(low,high)
27
28BTFIXUPDEF_CALL(pgd_t *, get_pgd_fast, void)
29#define get_pgd_fast() BTFIXUP_CALL(get_pgd_fast)()
30
31BTFIXUPDEF_CALL(void, free_pgd_fast, pgd_t *)
32#define free_pgd_fast(pgd) BTFIXUP_CALL(free_pgd_fast)(pgd)
33
34#define pgd_free(mm, pgd) free_pgd_fast(pgd)
35#define pgd_alloc(mm) get_pgd_fast()
36
37BTFIXUPDEF_CALL(void, pgd_set, pgd_t *, pmd_t *)
38#define pgd_set(pgdp,pmdp) BTFIXUP_CALL(pgd_set)(pgdp,pmdp)
39#define pgd_populate(MM, PGD, PMD) pgd_set(PGD, PMD)
40
41BTFIXUPDEF_CALL(pmd_t *, pmd_alloc_one, struct mm_struct *, unsigned long)
42#define pmd_alloc_one(mm, address) BTFIXUP_CALL(pmd_alloc_one)(mm, address)
43
44BTFIXUPDEF_CALL(void, free_pmd_fast, pmd_t *)
45#define free_pmd_fast(pmd) BTFIXUP_CALL(free_pmd_fast)(pmd)
46
47#define pmd_free(mm, pmd) free_pmd_fast(pmd)
48#define __pmd_free_tlb(tlb, pmd) pmd_free((tlb)->mm, pmd)
49
50BTFIXUPDEF_CALL(void, pmd_populate, pmd_t *, struct page *)
51#define pmd_populate(MM, PMD, PTE) BTFIXUP_CALL(pmd_populate)(PMD, PTE)
52#define pmd_pgtable(pmd) pmd_page(pmd)
53BTFIXUPDEF_CALL(void, pmd_set, pmd_t *, pte_t *)
54#define pmd_populate_kernel(MM, PMD, PTE) BTFIXUP_CALL(pmd_set)(PMD, PTE)
55
56BTFIXUPDEF_CALL(pgtable_t , pte_alloc_one, struct mm_struct *, unsigned long)
57#define pte_alloc_one(mm, address) BTFIXUP_CALL(pte_alloc_one)(mm, address)
58BTFIXUPDEF_CALL(pte_t *, pte_alloc_one_kernel, struct mm_struct *, unsigned long)
59#define pte_alloc_one_kernel(mm, addr) BTFIXUP_CALL(pte_alloc_one_kernel)(mm, addr)
60
61BTFIXUPDEF_CALL(void, free_pte_fast, pte_t *)
62#define pte_free_kernel(mm, pte) BTFIXUP_CALL(free_pte_fast)(pte)
63
64BTFIXUPDEF_CALL(void, pte_free, pgtable_t )
65#define pte_free(mm, pte) BTFIXUP_CALL(pte_free)(pte)
66#define __pte_free_tlb(tlb, pte) pte_free((tlb)->mm, pte)
67
68#endif /* _SPARC_PGALLOC_H */
diff --git a/include/asm-sparc/pgalloc_64.h b/include/asm-sparc/pgalloc_64.h
deleted file mode 100644
index 5bdfa2c6e40..00000000000
--- a/include/asm-sparc/pgalloc_64.h
+++ /dev/null
@@ -1,81 +0,0 @@
1#ifndef _SPARC64_PGALLOC_H
2#define _SPARC64_PGALLOC_H
3
4#include <linux/kernel.h>
5#include <linux/sched.h>
6#include <linux/mm.h>
7#include <linux/slab.h>
8#include <linux/quicklist.h>
9
10#include <asm/spitfire.h>
11#include <asm/cpudata.h>
12#include <asm/cacheflush.h>
13#include <asm/page.h>
14
15/* Page table allocation/freeing. */
16
17static inline pgd_t *pgd_alloc(struct mm_struct *mm)
18{
19 return quicklist_alloc(0, GFP_KERNEL, NULL);
20}
21
22static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
23{
24 quicklist_free(0, NULL, pgd);
25}
26
27#define pud_populate(MM, PUD, PMD) pud_set(PUD, PMD)
28
29static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
30{
31 return quicklist_alloc(0, GFP_KERNEL, NULL);
32}
33
34static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
35{
36 quicklist_free(0, NULL, pmd);
37}
38
39static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
40 unsigned long address)
41{
42 return quicklist_alloc(0, GFP_KERNEL, NULL);
43}
44
45static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
46 unsigned long address)
47{
48 struct page *page;
49 void *pg;
50
51 pg = quicklist_alloc(0, GFP_KERNEL, NULL);
52 if (!pg)
53 return NULL;
54 page = virt_to_page(pg);
55 pgtable_page_ctor(page);
56 return page;
57}
58
59static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
60{
61 quicklist_free(0, NULL, pte);
62}
63
64static inline void pte_free(struct mm_struct *mm, pgtable_t ptepage)
65{
66 pgtable_page_dtor(ptepage);
67 quicklist_free_page(0, NULL, ptepage);
68}
69
70
71#define pmd_populate_kernel(MM, PMD, PTE) pmd_set(PMD, PTE)
72#define pmd_populate(MM,PMD,PTE_PAGE) \
73 pmd_populate_kernel(MM,PMD,page_address(PTE_PAGE))
74#define pmd_pgtable(pmd) pmd_page(pmd)
75
76static inline void check_pgt_cache(void)
77{
78 quicklist_trim(0, NULL, 25, 16);
79}
80
81#endif /* _SPARC64_PGALLOC_H */
diff --git a/include/asm-sparc/pgtable.h b/include/asm-sparc/pgtable.h
deleted file mode 100644
index 63cdef53bc5..00000000000
--- a/include/asm-sparc/pgtable.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_PGTABLE_H
2#define ___ASM_SPARC_PGTABLE_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/pgtable_64.h>
5#else
6#include <asm-sparc/pgtable_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/pgtable_32.h b/include/asm-sparc/pgtable_32.h
deleted file mode 100644
index 781bd4694a1..00000000000
--- a/include/asm-sparc/pgtable_32.h
+++ /dev/null
@@ -1,480 +0,0 @@
1#ifndef _SPARC_PGTABLE_H
2#define _SPARC_PGTABLE_H
3
4/* asm-sparc/pgtable.h: Defines and functions used to work
5 * with Sparc page tables.
6 *
7 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
8 * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
9 */
10
11#ifndef __ASSEMBLY__
12#include <asm-generic/4level-fixup.h>
13
14#include <linux/spinlock.h>
15#include <linux/swap.h>
16#include <asm/types.h>
17#ifdef CONFIG_SUN4
18#include <asm/pgtsun4.h>
19#else
20#include <asm/pgtsun4c.h>
21#endif
22#include <asm/pgtsrmmu.h>
23#include <asm/vac-ops.h>
24#include <asm/oplib.h>
25#include <asm/btfixup.h>
26#include <asm/system.h>
27
28
29struct vm_area_struct;
30struct page;
31
32extern void load_mmu(void);
33extern unsigned long calc_highpages(void);
34
35BTFIXUPDEF_SIMM13(pgdir_shift)
36BTFIXUPDEF_SETHI(pgdir_size)
37BTFIXUPDEF_SETHI(pgdir_mask)
38
39BTFIXUPDEF_SIMM13(ptrs_per_pmd)
40BTFIXUPDEF_SIMM13(ptrs_per_pgd)
41BTFIXUPDEF_SIMM13(user_ptrs_per_pgd)
42
43#define pte_ERROR(e) __builtin_trap()
44#define pmd_ERROR(e) __builtin_trap()
45#define pgd_ERROR(e) __builtin_trap()
46
47BTFIXUPDEF_INT(page_none)
48BTFIXUPDEF_INT(page_copy)
49BTFIXUPDEF_INT(page_readonly)
50BTFIXUPDEF_INT(page_kernel)
51
52#define PMD_SHIFT SUN4C_PMD_SHIFT
53#define PMD_SIZE (1UL << PMD_SHIFT)
54#define PMD_MASK (~(PMD_SIZE-1))
55#define PMD_ALIGN(__addr) (((__addr) + ~PMD_MASK) & PMD_MASK)
56#define PGDIR_SHIFT BTFIXUP_SIMM13(pgdir_shift)
57#define PGDIR_SIZE BTFIXUP_SETHI(pgdir_size)
58#define PGDIR_MASK BTFIXUP_SETHI(pgdir_mask)
59#define PTRS_PER_PTE 1024
60#define PTRS_PER_PMD BTFIXUP_SIMM13(ptrs_per_pmd)
61#define PTRS_PER_PGD BTFIXUP_SIMM13(ptrs_per_pgd)
62#define USER_PTRS_PER_PGD BTFIXUP_SIMM13(user_ptrs_per_pgd)
63#define FIRST_USER_ADDRESS 0
64#define PTE_SIZE (PTRS_PER_PTE*4)
65
66#define PAGE_NONE __pgprot(BTFIXUP_INT(page_none))
67extern pgprot_t PAGE_SHARED;
68#define PAGE_COPY __pgprot(BTFIXUP_INT(page_copy))
69#define PAGE_READONLY __pgprot(BTFIXUP_INT(page_readonly))
70
71extern unsigned long page_kernel;
72
73#ifdef MODULE
74#define PAGE_KERNEL page_kernel
75#else
76#define PAGE_KERNEL __pgprot(BTFIXUP_INT(page_kernel))
77#endif
78
79/* Top-level page directory */
80extern pgd_t swapper_pg_dir[1024];
81
82extern void paging_init(void);
83
84/* Page table for 0-4MB for everybody, on the Sparc this
85 * holds the same as on the i386.
86 */
87extern pte_t pg0[1024];
88extern pte_t pg1[1024];
89extern pte_t pg2[1024];
90extern pte_t pg3[1024];
91
92extern unsigned long ptr_in_current_pgd;
93
94/* Here is a trick, since mmap.c need the initializer elements for
95 * protection_map[] to be constant at compile time, I set the following
96 * to all zeros. I set it to the real values after I link in the
97 * appropriate MMU page table routines at boot time.
98 */
99#define __P000 __pgprot(0)
100#define __P001 __pgprot(0)
101#define __P010 __pgprot(0)
102#define __P011 __pgprot(0)
103#define __P100 __pgprot(0)
104#define __P101 __pgprot(0)
105#define __P110 __pgprot(0)
106#define __P111 __pgprot(0)
107
108#define __S000 __pgprot(0)
109#define __S001 __pgprot(0)
110#define __S010 __pgprot(0)
111#define __S011 __pgprot(0)
112#define __S100 __pgprot(0)
113#define __S101 __pgprot(0)
114#define __S110 __pgprot(0)
115#define __S111 __pgprot(0)
116
117extern int num_contexts;
118
119/* First physical page can be anywhere, the following is needed so that
120 * va-->pa and vice versa conversions work properly without performance
121 * hit for all __pa()/__va() operations.
122 */
123extern unsigned long phys_base;
124extern unsigned long pfn_base;
125
126/*
127 * BAD_PAGETABLE is used when we need a bogus page-table, while
128 * BAD_PAGE is used for a bogus page.
129 *
130 * ZERO_PAGE is a global shared page that is always zero: used
131 * for zero-mapped memory areas etc..
132 */
133extern pte_t * __bad_pagetable(void);
134extern pte_t __bad_page(void);
135extern unsigned long empty_zero_page;
136
137#define BAD_PAGETABLE __bad_pagetable()
138#define BAD_PAGE __bad_page()
139#define ZERO_PAGE(vaddr) (virt_to_page(&empty_zero_page))
140
141/*
142 */
143BTFIXUPDEF_CALL_CONST(struct page *, pmd_page, pmd_t)
144BTFIXUPDEF_CALL_CONST(unsigned long, pgd_page_vaddr, pgd_t)
145
146#define pmd_page(pmd) BTFIXUP_CALL(pmd_page)(pmd)
147#define pgd_page_vaddr(pgd) BTFIXUP_CALL(pgd_page_vaddr)(pgd)
148
149BTFIXUPDEF_SETHI(none_mask)
150BTFIXUPDEF_CALL_CONST(int, pte_present, pte_t)
151BTFIXUPDEF_CALL(void, pte_clear, pte_t *)
152
153static inline int pte_none(pte_t pte)
154{
155 return !(pte_val(pte) & ~BTFIXUP_SETHI(none_mask));
156}
157
158#define pte_present(pte) BTFIXUP_CALL(pte_present)(pte)
159#define pte_clear(mm,addr,pte) BTFIXUP_CALL(pte_clear)(pte)
160
161BTFIXUPDEF_CALL_CONST(int, pmd_bad, pmd_t)
162BTFIXUPDEF_CALL_CONST(int, pmd_present, pmd_t)
163BTFIXUPDEF_CALL(void, pmd_clear, pmd_t *)
164
165static inline int pmd_none(pmd_t pmd)
166{
167 return !(pmd_val(pmd) & ~BTFIXUP_SETHI(none_mask));
168}
169
170#define pmd_bad(pmd) BTFIXUP_CALL(pmd_bad)(pmd)
171#define pmd_present(pmd) BTFIXUP_CALL(pmd_present)(pmd)
172#define pmd_clear(pmd) BTFIXUP_CALL(pmd_clear)(pmd)
173
174BTFIXUPDEF_CALL_CONST(int, pgd_none, pgd_t)
175BTFIXUPDEF_CALL_CONST(int, pgd_bad, pgd_t)
176BTFIXUPDEF_CALL_CONST(int, pgd_present, pgd_t)
177BTFIXUPDEF_CALL(void, pgd_clear, pgd_t *)
178
179#define pgd_none(pgd) BTFIXUP_CALL(pgd_none)(pgd)
180#define pgd_bad(pgd) BTFIXUP_CALL(pgd_bad)(pgd)
181#define pgd_present(pgd) BTFIXUP_CALL(pgd_present)(pgd)
182#define pgd_clear(pgd) BTFIXUP_CALL(pgd_clear)(pgd)
183
184/*
185 * The following only work if pte_present() is true.
186 * Undefined behaviour if not..
187 */
188BTFIXUPDEF_HALF(pte_writei)
189BTFIXUPDEF_HALF(pte_dirtyi)
190BTFIXUPDEF_HALF(pte_youngi)
191
192static int pte_write(pte_t pte) __attribute_const__;
193static inline int pte_write(pte_t pte)
194{
195 return pte_val(pte) & BTFIXUP_HALF(pte_writei);
196}
197
198static int pte_dirty(pte_t pte) __attribute_const__;
199static inline int pte_dirty(pte_t pte)
200{
201 return pte_val(pte) & BTFIXUP_HALF(pte_dirtyi);
202}
203
204static int pte_young(pte_t pte) __attribute_const__;
205static inline int pte_young(pte_t pte)
206{
207 return pte_val(pte) & BTFIXUP_HALF(pte_youngi);
208}
209
210/*
211 * The following only work if pte_present() is not true.
212 */
213BTFIXUPDEF_HALF(pte_filei)
214
215static int pte_file(pte_t pte) __attribute_const__;
216static inline int pte_file(pte_t pte)
217{
218 return pte_val(pte) & BTFIXUP_HALF(pte_filei);
219}
220
221static inline int pte_special(pte_t pte)
222{
223 return 0;
224}
225
226/*
227 */
228BTFIXUPDEF_HALF(pte_wrprotecti)
229BTFIXUPDEF_HALF(pte_mkcleani)
230BTFIXUPDEF_HALF(pte_mkoldi)
231
232static pte_t pte_wrprotect(pte_t pte) __attribute_const__;
233static inline pte_t pte_wrprotect(pte_t pte)
234{
235 return __pte(pte_val(pte) & ~BTFIXUP_HALF(pte_wrprotecti));
236}
237
238static pte_t pte_mkclean(pte_t pte) __attribute_const__;
239static inline pte_t pte_mkclean(pte_t pte)
240{
241 return __pte(pte_val(pte) & ~BTFIXUP_HALF(pte_mkcleani));
242}
243
244static pte_t pte_mkold(pte_t pte) __attribute_const__;
245static inline pte_t pte_mkold(pte_t pte)
246{
247 return __pte(pte_val(pte) & ~BTFIXUP_HALF(pte_mkoldi));
248}
249
250BTFIXUPDEF_CALL_CONST(pte_t, pte_mkwrite, pte_t)
251BTFIXUPDEF_CALL_CONST(pte_t, pte_mkdirty, pte_t)
252BTFIXUPDEF_CALL_CONST(pte_t, pte_mkyoung, pte_t)
253
254#define pte_mkwrite(pte) BTFIXUP_CALL(pte_mkwrite)(pte)
255#define pte_mkdirty(pte) BTFIXUP_CALL(pte_mkdirty)(pte)
256#define pte_mkyoung(pte) BTFIXUP_CALL(pte_mkyoung)(pte)
257
258#define pte_mkspecial(pte) (pte)
259
260#define pfn_pte(pfn, prot) mk_pte(pfn_to_page(pfn), prot)
261
262BTFIXUPDEF_CALL(unsigned long, pte_pfn, pte_t)
263#define pte_pfn(pte) BTFIXUP_CALL(pte_pfn)(pte)
264#define pte_page(pte) pfn_to_page(pte_pfn(pte))
265
266/*
267 * Conversion functions: convert a page and protection to a page entry,
268 * and a page entry and page directory to the page they refer to.
269 */
270BTFIXUPDEF_CALL_CONST(pte_t, mk_pte, struct page *, pgprot_t)
271
272BTFIXUPDEF_CALL_CONST(pte_t, mk_pte_phys, unsigned long, pgprot_t)
273BTFIXUPDEF_CALL_CONST(pte_t, mk_pte_io, unsigned long, pgprot_t, int)
274BTFIXUPDEF_CALL_CONST(pgprot_t, pgprot_noncached, pgprot_t)
275
276#define mk_pte(page,pgprot) BTFIXUP_CALL(mk_pte)(page,pgprot)
277#define mk_pte_phys(page,pgprot) BTFIXUP_CALL(mk_pte_phys)(page,pgprot)
278#define mk_pte_io(page,pgprot,space) BTFIXUP_CALL(mk_pte_io)(page,pgprot,space)
279
280#define pgprot_noncached(pgprot) BTFIXUP_CALL(pgprot_noncached)(pgprot)
281
282BTFIXUPDEF_INT(pte_modify_mask)
283
284static pte_t pte_modify(pte_t pte, pgprot_t newprot) __attribute_const__;
285static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
286{
287 return __pte((pte_val(pte) & BTFIXUP_INT(pte_modify_mask)) |
288 pgprot_val(newprot));
289}
290
291#define pgd_index(address) ((address) >> PGDIR_SHIFT)
292
293/* to find an entry in a page-table-directory */
294#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
295
296/* to find an entry in a kernel page-table-directory */
297#define pgd_offset_k(address) pgd_offset(&init_mm, address)
298
299/* Find an entry in the second-level page table.. */
300BTFIXUPDEF_CALL(pmd_t *, pmd_offset, pgd_t *, unsigned long)
301#define pmd_offset(dir,addr) BTFIXUP_CALL(pmd_offset)(dir,addr)
302
303/* Find an entry in the third-level page table.. */
304BTFIXUPDEF_CALL(pte_t *, pte_offset_kernel, pmd_t *, unsigned long)
305#define pte_offset_kernel(dir,addr) BTFIXUP_CALL(pte_offset_kernel)(dir,addr)
306
307/*
308 * This shortcut works on sun4m (and sun4d) because the nocache area is static,
309 * and sun4c is guaranteed to have no highmem anyway.
310 */
311#define pte_offset_map(d, a) pte_offset_kernel(d,a)
312#define pte_offset_map_nested(d, a) pte_offset_kernel(d,a)
313
314#define pte_unmap(pte) do{}while(0)
315#define pte_unmap_nested(pte) do{}while(0)
316
317/* Certain architectures need to do special things when pte's
318 * within a page table are directly modified. Thus, the following
319 * hook is made available.
320 */
321
322BTFIXUPDEF_CALL(void, set_pte, pte_t *, pte_t)
323
324#define set_pte(ptep,pteval) BTFIXUP_CALL(set_pte)(ptep,pteval)
325#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
326
327struct seq_file;
328BTFIXUPDEF_CALL(void, mmu_info, struct seq_file *)
329
330#define mmu_info(p) BTFIXUP_CALL(mmu_info)(p)
331
332/* Fault handler stuff... */
333#define FAULT_CODE_PROT 0x1
334#define FAULT_CODE_WRITE 0x2
335#define FAULT_CODE_USER 0x4
336
337BTFIXUPDEF_CALL(void, update_mmu_cache, struct vm_area_struct *, unsigned long, pte_t)
338
339#define update_mmu_cache(vma,addr,pte) BTFIXUP_CALL(update_mmu_cache)(vma,addr,pte)
340
341BTFIXUPDEF_CALL(void, sparc_mapiorange, unsigned int, unsigned long,
342 unsigned long, unsigned int)
343BTFIXUPDEF_CALL(void, sparc_unmapiorange, unsigned long, unsigned int)
344#define sparc_mapiorange(bus,pa,va,len) BTFIXUP_CALL(sparc_mapiorange)(bus,pa,va,len)
345#define sparc_unmapiorange(va,len) BTFIXUP_CALL(sparc_unmapiorange)(va,len)
346
347extern int invalid_segment;
348
349/* Encode and de-code a swap entry */
350BTFIXUPDEF_CALL(unsigned long, __swp_type, swp_entry_t)
351BTFIXUPDEF_CALL(unsigned long, __swp_offset, swp_entry_t)
352BTFIXUPDEF_CALL(swp_entry_t, __swp_entry, unsigned long, unsigned long)
353
354#define __swp_type(__x) BTFIXUP_CALL(__swp_type)(__x)
355#define __swp_offset(__x) BTFIXUP_CALL(__swp_offset)(__x)
356#define __swp_entry(__type,__off) BTFIXUP_CALL(__swp_entry)(__type,__off)
357
358#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
359#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
360
361/* file-offset-in-pte helpers */
362BTFIXUPDEF_CALL(unsigned long, pte_to_pgoff, pte_t pte);
363BTFIXUPDEF_CALL(pte_t, pgoff_to_pte, unsigned long pgoff);
364
365#define pte_to_pgoff(pte) BTFIXUP_CALL(pte_to_pgoff)(pte)
366#define pgoff_to_pte(off) BTFIXUP_CALL(pgoff_to_pte)(off)
367
368/*
369 * This is made a constant because mm/fremap.c required a constant.
370 * Note that layout of these bits is different between sun4c.c and srmmu.c.
371 */
372#define PTE_FILE_MAX_BITS 24
373
374/*
375 */
376struct ctx_list {
377 struct ctx_list *next;
378 struct ctx_list *prev;
379 unsigned int ctx_number;
380 struct mm_struct *ctx_mm;
381};
382
383extern struct ctx_list *ctx_list_pool; /* Dynamically allocated */
384extern struct ctx_list ctx_free; /* Head of free list */
385extern struct ctx_list ctx_used; /* Head of used contexts list */
386
387#define NO_CONTEXT -1
388
389static inline void remove_from_ctx_list(struct ctx_list *entry)
390{
391 entry->next->prev = entry->prev;
392 entry->prev->next = entry->next;
393}
394
395static inline void add_to_ctx_list(struct ctx_list *head, struct ctx_list *entry)
396{
397 entry->next = head;
398 (entry->prev = head->prev)->next = entry;
399 head->prev = entry;
400}
401#define add_to_free_ctxlist(entry) add_to_ctx_list(&ctx_free, entry)
402#define add_to_used_ctxlist(entry) add_to_ctx_list(&ctx_used, entry)
403
404static inline unsigned long
405__get_phys (unsigned long addr)
406{
407 switch (sparc_cpu_model){
408 case sun4:
409 case sun4c:
410 return sun4c_get_pte (addr) << PAGE_SHIFT;
411 case sun4m:
412 case sun4d:
413 return ((srmmu_get_pte (addr) & 0xffffff00) << 4);
414 default:
415 return 0;
416 }
417}
418
419static inline int
420__get_iospace (unsigned long addr)
421{
422 switch (sparc_cpu_model){
423 case sun4:
424 case sun4c:
425 return -1; /* Don't check iospace on sun4c */
426 case sun4m:
427 case sun4d:
428 return (srmmu_get_pte (addr) >> 28);
429 default:
430 return -1;
431 }
432}
433
434extern unsigned long *sparc_valid_addr_bitmap;
435
436/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
437#define kern_addr_valid(addr) \
438 (test_bit(__pa((unsigned long)(addr))>>20, sparc_valid_addr_bitmap))
439
440extern int io_remap_pfn_range(struct vm_area_struct *vma,
441 unsigned long from, unsigned long pfn,
442 unsigned long size, pgprot_t prot);
443
444/*
445 * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
446 * its high 4 bits. These macros/functions put it there or get it from there.
447 */
448#define MK_IOSPACE_PFN(space, pfn) (pfn | (space << (BITS_PER_LONG - 4)))
449#define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4))
450#define GET_PFN(pfn) (pfn & 0x0fffffffUL)
451
452#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
453#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
454({ \
455 int __changed = !pte_same(*(__ptep), __entry); \
456 if (__changed) { \
457 set_pte_at((__vma)->vm_mm, (__address), __ptep, __entry); \
458 flush_tlb_page(__vma, __address); \
459 } \
460 (sparc_cpu_model == sun4c) || __changed; \
461})
462
463#include <asm-generic/pgtable.h>
464
465#endif /* !(__ASSEMBLY__) */
466
467#define VMALLOC_START 0xfe600000
468/* XXX Alter this when I get around to fixing sun4c - Anton */
469#define VMALLOC_END 0xffc00000
470
471
472/* We provide our own get_unmapped_area to cope with VA holes for userland */
473#define HAVE_ARCH_UNMAPPED_AREA
474
475/*
476 * No page table caches to initialise
477 */
478#define pgtable_cache_init() do { } while (0)
479
480#endif /* !(_SPARC_PGTABLE_H) */
diff --git a/include/asm-sparc/pgtable_64.h b/include/asm-sparc/pgtable_64.h
deleted file mode 100644
index bb9ec2cce35..00000000000
--- a/include/asm-sparc/pgtable_64.h
+++ /dev/null
@@ -1,775 +0,0 @@
1/*
2 * pgtable.h: SpitFire page table operations.
3 *
4 * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8#ifndef _SPARC64_PGTABLE_H
9#define _SPARC64_PGTABLE_H
10
11/* This file contains the functions and defines necessary to modify and use
12 * the SpitFire page tables.
13 */
14
15#include <asm-generic/pgtable-nopud.h>
16
17#include <linux/compiler.h>
18#include <linux/const.h>
19#include <asm/types.h>
20#include <asm/spitfire.h>
21#include <asm/asi.h>
22#include <asm/system.h>
23#include <asm/page.h>
24#include <asm/processor.h>
25
26/* The kernel image occupies 0x4000000 to 0x6000000 (4MB --> 96MB).
27 * The page copy blockops can use 0x6000000 to 0x8000000.
28 * The TSB is mapped in the 0x8000000 to 0xa000000 range.
29 * The PROM resides in an area spanning 0xf0000000 to 0x100000000.
30 * The vmalloc area spans 0x100000000 to 0x200000000.
31 * Since modules need to be in the lowest 32-bits of the address space,
32 * we place them right before the OBP area from 0x10000000 to 0xf0000000.
33 * There is a single static kernel PMD which maps from 0x0 to address
34 * 0x400000000.
35 */
36#define TLBTEMP_BASE _AC(0x0000000006000000,UL)
37#define TSBMAP_BASE _AC(0x0000000008000000,UL)
38#define MODULES_VADDR _AC(0x0000000010000000,UL)
39#define MODULES_LEN _AC(0x00000000e0000000,UL)
40#define MODULES_END _AC(0x00000000f0000000,UL)
41#define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL)
42#define HI_OBP_ADDRESS _AC(0x0000000100000000,UL)
43#define VMALLOC_START _AC(0x0000000100000000,UL)
44#define VMALLOC_END _AC(0x0000000200000000,UL)
45#define VMEMMAP_BASE _AC(0x0000000200000000,UL)
46
47#define vmemmap ((struct page *)VMEMMAP_BASE)
48
49/* XXX All of this needs to be rethought so we can take advantage
50 * XXX cheetah's full 64-bit virtual address space, ie. no more hole
51 * XXX in the middle like on spitfire. -DaveM
52 */
53/*
54 * Given a virtual address, the lowest PAGE_SHIFT bits determine offset
55 * into the page; the next higher PAGE_SHIFT-3 bits determine the pte#
56 * in the proper pagetable (the -3 is from the 8 byte ptes, and each page
57 * table is a single page long). The next higher PMD_BITS determine pmd#
58 * in the proper pmdtable (where we must have PMD_BITS <= (PAGE_SHIFT-2)
59 * since the pmd entries are 4 bytes, and each pmd page is a single page
60 * long). Finally, the higher few bits determine pgde#.
61 */
62
63/* PMD_SHIFT determines the size of the area a second-level page
64 * table can map
65 */
66#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3))
67#define PMD_SIZE (_AC(1,UL) << PMD_SHIFT)
68#define PMD_MASK (~(PMD_SIZE-1))
69#define PMD_BITS (PAGE_SHIFT - 2)
70
71/* PGDIR_SHIFT determines what a third-level page table entry can map */
72#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3) + PMD_BITS)
73#define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT)
74#define PGDIR_MASK (~(PGDIR_SIZE-1))
75#define PGDIR_BITS (PAGE_SHIFT - 2)
76
77#ifndef __ASSEMBLY__
78
79#include <linux/sched.h>
80
81/* Entries per page directory level. */
82#define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3))
83#define PTRS_PER_PMD (1UL << PMD_BITS)
84#define PTRS_PER_PGD (1UL << PGDIR_BITS)
85
86/* Kernel has a separate 44bit address space. */
87#define FIRST_USER_ADDRESS 0
88
89#define pte_ERROR(e) __builtin_trap()
90#define pmd_ERROR(e) __builtin_trap()
91#define pgd_ERROR(e) __builtin_trap()
92
93#endif /* !(__ASSEMBLY__) */
94
95/* PTE bits which are the same in SUN4U and SUN4V format. */
96#define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */
97#define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit uptodate*/
98
99/* SUN4U pte bits... */
100#define _PAGE_SZ4MB_4U _AC(0x6000000000000000,UL) /* 4MB Page */
101#define _PAGE_SZ512K_4U _AC(0x4000000000000000,UL) /* 512K Page */
102#define _PAGE_SZ64K_4U _AC(0x2000000000000000,UL) /* 64K Page */
103#define _PAGE_SZ8K_4U _AC(0x0000000000000000,UL) /* 8K Page */
104#define _PAGE_NFO_4U _AC(0x1000000000000000,UL) /* No Fault Only */
105#define _PAGE_IE_4U _AC(0x0800000000000000,UL) /* Invert Endianness */
106#define _PAGE_SOFT2_4U _AC(0x07FC000000000000,UL) /* Software bits, set 2 */
107#define _PAGE_RES1_4U _AC(0x0002000000000000,UL) /* Reserved */
108#define _PAGE_SZ32MB_4U _AC(0x0001000000000000,UL) /* (Panther) 32MB page */
109#define _PAGE_SZ256MB_4U _AC(0x2001000000000000,UL) /* (Panther) 256MB page */
110#define _PAGE_SZALL_4U _AC(0x6001000000000000,UL) /* All pgsz bits */
111#define _PAGE_SN_4U _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */
112#define _PAGE_RES2_4U _AC(0x0000780000000000,UL) /* Reserved */
113#define _PAGE_PADDR_4U _AC(0x000007FFFFFFE000,UL) /* (Cheetah) pa[42:13] */
114#define _PAGE_SOFT_4U _AC(0x0000000000001F80,UL) /* Software bits: */
115#define _PAGE_EXEC_4U _AC(0x0000000000001000,UL) /* Executable SW bit */
116#define _PAGE_MODIFIED_4U _AC(0x0000000000000800,UL) /* Modified (dirty) */
117#define _PAGE_FILE_4U _AC(0x0000000000000800,UL) /* Pagecache page */
118#define _PAGE_ACCESSED_4U _AC(0x0000000000000400,UL) /* Accessed (ref'd) */
119#define _PAGE_READ_4U _AC(0x0000000000000200,UL) /* Readable SW Bit */
120#define _PAGE_WRITE_4U _AC(0x0000000000000100,UL) /* Writable SW Bit */
121#define _PAGE_PRESENT_4U _AC(0x0000000000000080,UL) /* Present */
122#define _PAGE_L_4U _AC(0x0000000000000040,UL) /* Locked TTE */
123#define _PAGE_CP_4U _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */
124#define _PAGE_CV_4U _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */
125#define _PAGE_E_4U _AC(0x0000000000000008,UL) /* side-Effect */
126#define _PAGE_P_4U _AC(0x0000000000000004,UL) /* Privileged Page */
127#define _PAGE_W_4U _AC(0x0000000000000002,UL) /* Writable */
128
129/* SUN4V pte bits... */
130#define _PAGE_NFO_4V _AC(0x4000000000000000,UL) /* No Fault Only */
131#define _PAGE_SOFT2_4V _AC(0x3F00000000000000,UL) /* Software bits, set 2 */
132#define _PAGE_MODIFIED_4V _AC(0x2000000000000000,UL) /* Modified (dirty) */
133#define _PAGE_ACCESSED_4V _AC(0x1000000000000000,UL) /* Accessed (ref'd) */
134#define _PAGE_READ_4V _AC(0x0800000000000000,UL) /* Readable SW Bit */
135#define _PAGE_WRITE_4V _AC(0x0400000000000000,UL) /* Writable SW Bit */
136#define _PAGE_PADDR_4V _AC(0x00FFFFFFFFFFE000,UL) /* paddr[55:13] */
137#define _PAGE_IE_4V _AC(0x0000000000001000,UL) /* Invert Endianness */
138#define _PAGE_E_4V _AC(0x0000000000000800,UL) /* side-Effect */
139#define _PAGE_CP_4V _AC(0x0000000000000400,UL) /* Cacheable in P-Cache */
140#define _PAGE_CV_4V _AC(0x0000000000000200,UL) /* Cacheable in V-Cache */
141#define _PAGE_P_4V _AC(0x0000000000000100,UL) /* Privileged Page */
142#define _PAGE_EXEC_4V _AC(0x0000000000000080,UL) /* Executable Page */
143#define _PAGE_W_4V _AC(0x0000000000000040,UL) /* Writable */
144#define _PAGE_SOFT_4V _AC(0x0000000000000030,UL) /* Software bits */
145#define _PAGE_FILE_4V _AC(0x0000000000000020,UL) /* Pagecache page */
146#define _PAGE_PRESENT_4V _AC(0x0000000000000010,UL) /* Present */
147#define _PAGE_RESV_4V _AC(0x0000000000000008,UL) /* Reserved */
148#define _PAGE_SZ16GB_4V _AC(0x0000000000000007,UL) /* 16GB Page */
149#define _PAGE_SZ2GB_4V _AC(0x0000000000000006,UL) /* 2GB Page */
150#define _PAGE_SZ256MB_4V _AC(0x0000000000000005,UL) /* 256MB Page */
151#define _PAGE_SZ32MB_4V _AC(0x0000000000000004,UL) /* 32MB Page */
152#define _PAGE_SZ4MB_4V _AC(0x0000000000000003,UL) /* 4MB Page */
153#define _PAGE_SZ512K_4V _AC(0x0000000000000002,UL) /* 512K Page */
154#define _PAGE_SZ64K_4V _AC(0x0000000000000001,UL) /* 64K Page */
155#define _PAGE_SZ8K_4V _AC(0x0000000000000000,UL) /* 8K Page */
156#define _PAGE_SZALL_4V _AC(0x0000000000000007,UL) /* All pgsz bits */
157
158#if PAGE_SHIFT == 13
159#define _PAGE_SZBITS_4U _PAGE_SZ8K_4U
160#define _PAGE_SZBITS_4V _PAGE_SZ8K_4V
161#elif PAGE_SHIFT == 16
162#define _PAGE_SZBITS_4U _PAGE_SZ64K_4U
163#define _PAGE_SZBITS_4V _PAGE_SZ64K_4V
164#else
165#error Wrong PAGE_SHIFT specified
166#endif
167
168#if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
169#define _PAGE_SZHUGE_4U _PAGE_SZ4MB_4U
170#define _PAGE_SZHUGE_4V _PAGE_SZ4MB_4V
171#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
172#define _PAGE_SZHUGE_4U _PAGE_SZ512K_4U
173#define _PAGE_SZHUGE_4V _PAGE_SZ512K_4V
174#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
175#define _PAGE_SZHUGE_4U _PAGE_SZ64K_4U
176#define _PAGE_SZHUGE_4V _PAGE_SZ64K_4V
177#endif
178
179/* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */
180#define __P000 __pgprot(0)
181#define __P001 __pgprot(0)
182#define __P010 __pgprot(0)
183#define __P011 __pgprot(0)
184#define __P100 __pgprot(0)
185#define __P101 __pgprot(0)
186#define __P110 __pgprot(0)
187#define __P111 __pgprot(0)
188
189#define __S000 __pgprot(0)
190#define __S001 __pgprot(0)
191#define __S010 __pgprot(0)
192#define __S011 __pgprot(0)
193#define __S100 __pgprot(0)
194#define __S101 __pgprot(0)
195#define __S110 __pgprot(0)
196#define __S111 __pgprot(0)
197
198#ifndef __ASSEMBLY__
199
200extern pte_t mk_pte_io(unsigned long, pgprot_t, int, unsigned long);
201
202extern unsigned long pte_sz_bits(unsigned long size);
203
204extern pgprot_t PAGE_KERNEL;
205extern pgprot_t PAGE_KERNEL_LOCKED;
206extern pgprot_t PAGE_COPY;
207extern pgprot_t PAGE_SHARED;
208
209/* XXX This uglyness is for the atyfb driver's sparc mmap() support. XXX */
210extern unsigned long _PAGE_IE;
211extern unsigned long _PAGE_E;
212extern unsigned long _PAGE_CACHE;
213
214extern unsigned long pg_iobits;
215extern unsigned long _PAGE_ALL_SZ_BITS;
216extern unsigned long _PAGE_SZBITS;
217
218extern struct page *mem_map_zero;
219#define ZERO_PAGE(vaddr) (mem_map_zero)
220
221/* PFNs are real physical page numbers. However, mem_map only begins to record
222 * per-page information starting at pfn_base. This is to handle systems where
223 * the first physical page in the machine is at some huge physical address,
224 * such as 4GB. This is common on a partitioned E10000, for example.
225 */
226static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
227{
228 unsigned long paddr = pfn << PAGE_SHIFT;
229 unsigned long sz_bits;
230
231 sz_bits = 0UL;
232 if (_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL) {
233 __asm__ __volatile__(
234 "\n661: sethi %%uhi(%1), %0\n"
235 " sllx %0, 32, %0\n"
236 " .section .sun4v_2insn_patch, \"ax\"\n"
237 " .word 661b\n"
238 " mov %2, %0\n"
239 " nop\n"
240 " .previous\n"
241 : "=r" (sz_bits)
242 : "i" (_PAGE_SZBITS_4U), "i" (_PAGE_SZBITS_4V));
243 }
244 return __pte(paddr | sz_bits | pgprot_val(prot));
245}
246#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
247
248/* This one can be done with two shifts. */
249static inline unsigned long pte_pfn(pte_t pte)
250{
251 unsigned long ret;
252
253 __asm__ __volatile__(
254 "\n661: sllx %1, %2, %0\n"
255 " srlx %0, %3, %0\n"
256 " .section .sun4v_2insn_patch, \"ax\"\n"
257 " .word 661b\n"
258 " sllx %1, %4, %0\n"
259 " srlx %0, %5, %0\n"
260 " .previous\n"
261 : "=r" (ret)
262 : "r" (pte_val(pte)),
263 "i" (21), "i" (21 + PAGE_SHIFT),
264 "i" (8), "i" (8 + PAGE_SHIFT));
265
266 return ret;
267}
268#define pte_page(x) pfn_to_page(pte_pfn(x))
269
270static inline pte_t pte_modify(pte_t pte, pgprot_t prot)
271{
272 unsigned long mask, tmp;
273
274 /* SUN4U: 0x600307ffffffecb8 (negated == 0x9ffcf80000001347)
275 * SUN4V: 0x30ffffffffffee17 (negated == 0xcf000000000011e8)
276 *
277 * Even if we use negation tricks the result is still a 6
278 * instruction sequence, so don't try to play fancy and just
279 * do the most straightforward implementation.
280 *
281 * Note: We encode this into 3 sun4v 2-insn patch sequences.
282 */
283
284 __asm__ __volatile__(
285 "\n661: sethi %%uhi(%2), %1\n"
286 " sethi %%hi(%2), %0\n"
287 "\n662: or %1, %%ulo(%2), %1\n"
288 " or %0, %%lo(%2), %0\n"
289 "\n663: sllx %1, 32, %1\n"
290 " or %0, %1, %0\n"
291 " .section .sun4v_2insn_patch, \"ax\"\n"
292 " .word 661b\n"
293 " sethi %%uhi(%3), %1\n"
294 " sethi %%hi(%3), %0\n"
295 " .word 662b\n"
296 " or %1, %%ulo(%3), %1\n"
297 " or %0, %%lo(%3), %0\n"
298 " .word 663b\n"
299 " sllx %1, 32, %1\n"
300 " or %0, %1, %0\n"
301 " .previous\n"
302 : "=r" (mask), "=r" (tmp)
303 : "i" (_PAGE_PADDR_4U | _PAGE_MODIFIED_4U | _PAGE_ACCESSED_4U |
304 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_E_4U | _PAGE_PRESENT_4U |
305 _PAGE_SZBITS_4U),
306 "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V |
307 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_E_4V | _PAGE_PRESENT_4V |
308 _PAGE_SZBITS_4V));
309
310 return __pte((pte_val(pte) & mask) | (pgprot_val(prot) & ~mask));
311}
312
313static inline pte_t pgoff_to_pte(unsigned long off)
314{
315 off <<= PAGE_SHIFT;
316
317 __asm__ __volatile__(
318 "\n661: or %0, %2, %0\n"
319 " .section .sun4v_1insn_patch, \"ax\"\n"
320 " .word 661b\n"
321 " or %0, %3, %0\n"
322 " .previous\n"
323 : "=r" (off)
324 : "0" (off), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V));
325
326 return __pte(off);
327}
328
329static inline pgprot_t pgprot_noncached(pgprot_t prot)
330{
331 unsigned long val = pgprot_val(prot);
332
333 __asm__ __volatile__(
334 "\n661: andn %0, %2, %0\n"
335 " or %0, %3, %0\n"
336 " .section .sun4v_2insn_patch, \"ax\"\n"
337 " .word 661b\n"
338 " andn %0, %4, %0\n"
339 " or %0, %5, %0\n"
340 " .previous\n"
341 : "=r" (val)
342 : "0" (val), "i" (_PAGE_CP_4U | _PAGE_CV_4U), "i" (_PAGE_E_4U),
343 "i" (_PAGE_CP_4V | _PAGE_CV_4V), "i" (_PAGE_E_4V));
344
345 return __pgprot(val);
346}
347/* Various pieces of code check for platform support by ifdef testing
348 * on "pgprot_noncached". That's broken and should be fixed, but for
349 * now...
350 */
351#define pgprot_noncached pgprot_noncached
352
353#ifdef CONFIG_HUGETLB_PAGE
354static inline pte_t pte_mkhuge(pte_t pte)
355{
356 unsigned long mask;
357
358 __asm__ __volatile__(
359 "\n661: sethi %%uhi(%1), %0\n"
360 " sllx %0, 32, %0\n"
361 " .section .sun4v_2insn_patch, \"ax\"\n"
362 " .word 661b\n"
363 " mov %2, %0\n"
364 " nop\n"
365 " .previous\n"
366 : "=r" (mask)
367 : "i" (_PAGE_SZHUGE_4U), "i" (_PAGE_SZHUGE_4V));
368
369 return __pte(pte_val(pte) | mask);
370}
371#endif
372
373static inline pte_t pte_mkdirty(pte_t pte)
374{
375 unsigned long val = pte_val(pte), tmp;
376
377 __asm__ __volatile__(
378 "\n661: or %0, %3, %0\n"
379 " nop\n"
380 "\n662: nop\n"
381 " nop\n"
382 " .section .sun4v_2insn_patch, \"ax\"\n"
383 " .word 661b\n"
384 " sethi %%uhi(%4), %1\n"
385 " sllx %1, 32, %1\n"
386 " .word 662b\n"
387 " or %1, %%lo(%4), %1\n"
388 " or %0, %1, %0\n"
389 " .previous\n"
390 : "=r" (val), "=r" (tmp)
391 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U),
392 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V));
393
394 return __pte(val);
395}
396
397static inline pte_t pte_mkclean(pte_t pte)
398{
399 unsigned long val = pte_val(pte), tmp;
400
401 __asm__ __volatile__(
402 "\n661: andn %0, %3, %0\n"
403 " nop\n"
404 "\n662: nop\n"
405 " nop\n"
406 " .section .sun4v_2insn_patch, \"ax\"\n"
407 " .word 661b\n"
408 " sethi %%uhi(%4), %1\n"
409 " sllx %1, 32, %1\n"
410 " .word 662b\n"
411 " or %1, %%lo(%4), %1\n"
412 " andn %0, %1, %0\n"
413 " .previous\n"
414 : "=r" (val), "=r" (tmp)
415 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U),
416 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V));
417
418 return __pte(val);
419}
420
421static inline pte_t pte_mkwrite(pte_t pte)
422{
423 unsigned long val = pte_val(pte), mask;
424
425 __asm__ __volatile__(
426 "\n661: mov %1, %0\n"
427 " nop\n"
428 " .section .sun4v_2insn_patch, \"ax\"\n"
429 " .word 661b\n"
430 " sethi %%uhi(%2), %0\n"
431 " sllx %0, 32, %0\n"
432 " .previous\n"
433 : "=r" (mask)
434 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V));
435
436 return __pte(val | mask);
437}
438
439static inline pte_t pte_wrprotect(pte_t pte)
440{
441 unsigned long val = pte_val(pte), tmp;
442
443 __asm__ __volatile__(
444 "\n661: andn %0, %3, %0\n"
445 " nop\n"
446 "\n662: nop\n"
447 " nop\n"
448 " .section .sun4v_2insn_patch, \"ax\"\n"
449 " .word 661b\n"
450 " sethi %%uhi(%4), %1\n"
451 " sllx %1, 32, %1\n"
452 " .word 662b\n"
453 " or %1, %%lo(%4), %1\n"
454 " andn %0, %1, %0\n"
455 " .previous\n"
456 : "=r" (val), "=r" (tmp)
457 : "0" (val), "i" (_PAGE_WRITE_4U | _PAGE_W_4U),
458 "i" (_PAGE_WRITE_4V | _PAGE_W_4V));
459
460 return __pte(val);
461}
462
463static inline pte_t pte_mkold(pte_t pte)
464{
465 unsigned long mask;
466
467 __asm__ __volatile__(
468 "\n661: mov %1, %0\n"
469 " nop\n"
470 " .section .sun4v_2insn_patch, \"ax\"\n"
471 " .word 661b\n"
472 " sethi %%uhi(%2), %0\n"
473 " sllx %0, 32, %0\n"
474 " .previous\n"
475 : "=r" (mask)
476 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
477
478 mask |= _PAGE_R;
479
480 return __pte(pte_val(pte) & ~mask);
481}
482
483static inline pte_t pte_mkyoung(pte_t pte)
484{
485 unsigned long mask;
486
487 __asm__ __volatile__(
488 "\n661: mov %1, %0\n"
489 " nop\n"
490 " .section .sun4v_2insn_patch, \"ax\"\n"
491 " .word 661b\n"
492 " sethi %%uhi(%2), %0\n"
493 " sllx %0, 32, %0\n"
494 " .previous\n"
495 : "=r" (mask)
496 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
497
498 mask |= _PAGE_R;
499
500 return __pte(pte_val(pte) | mask);
501}
502
503static inline pte_t pte_mkspecial(pte_t pte)
504{
505 return pte;
506}
507
508static inline unsigned long pte_young(pte_t pte)
509{
510 unsigned long mask;
511
512 __asm__ __volatile__(
513 "\n661: mov %1, %0\n"
514 " nop\n"
515 " .section .sun4v_2insn_patch, \"ax\"\n"
516 " .word 661b\n"
517 " sethi %%uhi(%2), %0\n"
518 " sllx %0, 32, %0\n"
519 " .previous\n"
520 : "=r" (mask)
521 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
522
523 return (pte_val(pte) & mask);
524}
525
526static inline unsigned long pte_dirty(pte_t pte)
527{
528 unsigned long mask;
529
530 __asm__ __volatile__(
531 "\n661: mov %1, %0\n"
532 " nop\n"
533 " .section .sun4v_2insn_patch, \"ax\"\n"
534 " .word 661b\n"
535 " sethi %%uhi(%2), %0\n"
536 " sllx %0, 32, %0\n"
537 " .previous\n"
538 : "=r" (mask)
539 : "i" (_PAGE_MODIFIED_4U), "i" (_PAGE_MODIFIED_4V));
540
541 return (pte_val(pte) & mask);
542}
543
544static inline unsigned long pte_write(pte_t pte)
545{
546 unsigned long mask;
547
548 __asm__ __volatile__(
549 "\n661: mov %1, %0\n"
550 " nop\n"
551 " .section .sun4v_2insn_patch, \"ax\"\n"
552 " .word 661b\n"
553 " sethi %%uhi(%2), %0\n"
554 " sllx %0, 32, %0\n"
555 " .previous\n"
556 : "=r" (mask)
557 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V));
558
559 return (pte_val(pte) & mask);
560}
561
562static inline unsigned long pte_exec(pte_t pte)
563{
564 unsigned long mask;
565
566 __asm__ __volatile__(
567 "\n661: sethi %%hi(%1), %0\n"
568 " .section .sun4v_1insn_patch, \"ax\"\n"
569 " .word 661b\n"
570 " mov %2, %0\n"
571 " .previous\n"
572 : "=r" (mask)
573 : "i" (_PAGE_EXEC_4U), "i" (_PAGE_EXEC_4V));
574
575 return (pte_val(pte) & mask);
576}
577
578static inline unsigned long pte_file(pte_t pte)
579{
580 unsigned long val = pte_val(pte);
581
582 __asm__ __volatile__(
583 "\n661: and %0, %2, %0\n"
584 " .section .sun4v_1insn_patch, \"ax\"\n"
585 " .word 661b\n"
586 " and %0, %3, %0\n"
587 " .previous\n"
588 : "=r" (val)
589 : "0" (val), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V));
590
591 return val;
592}
593
594static inline unsigned long pte_present(pte_t pte)
595{
596 unsigned long val = pte_val(pte);
597
598 __asm__ __volatile__(
599 "\n661: and %0, %2, %0\n"
600 " .section .sun4v_1insn_patch, \"ax\"\n"
601 " .word 661b\n"
602 " and %0, %3, %0\n"
603 " .previous\n"
604 : "=r" (val)
605 : "0" (val), "i" (_PAGE_PRESENT_4U), "i" (_PAGE_PRESENT_4V));
606
607 return val;
608}
609
610static inline int pte_special(pte_t pte)
611{
612 return 0;
613}
614
615#define pmd_set(pmdp, ptep) \
616 (pmd_val(*(pmdp)) = (__pa((unsigned long) (ptep)) >> 11UL))
617#define pud_set(pudp, pmdp) \
618 (pud_val(*(pudp)) = (__pa((unsigned long) (pmdp)) >> 11UL))
619#define __pmd_page(pmd) \
620 ((unsigned long) __va((((unsigned long)pmd_val(pmd))<<11UL)))
621#define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd))
622#define pud_page_vaddr(pud) \
623 ((unsigned long) __va((((unsigned long)pud_val(pud))<<11UL)))
624#define pud_page(pud) virt_to_page((void *)pud_page_vaddr(pud))
625#define pmd_none(pmd) (!pmd_val(pmd))
626#define pmd_bad(pmd) (0)
627#define pmd_present(pmd) (pmd_val(pmd) != 0U)
628#define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0U)
629#define pud_none(pud) (!pud_val(pud))
630#define pud_bad(pud) (0)
631#define pud_present(pud) (pud_val(pud) != 0U)
632#define pud_clear(pudp) (pud_val(*(pudp)) = 0U)
633
634/* Same in both SUN4V and SUN4U. */
635#define pte_none(pte) (!pte_val(pte))
636
637/* to find an entry in a page-table-directory. */
638#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
639#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
640
641/* to find an entry in a kernel page-table-directory */
642#define pgd_offset_k(address) pgd_offset(&init_mm, address)
643
644/* Find an entry in the second-level page table.. */
645#define pmd_offset(pudp, address) \
646 ((pmd_t *) pud_page_vaddr(*(pudp)) + \
647 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)))
648
649/* Find an entry in the third-level page table.. */
650#define pte_index(dir, address) \
651 ((pte_t *) __pmd_page(*(dir)) + \
652 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
653#define pte_offset_kernel pte_index
654#define pte_offset_map pte_index
655#define pte_offset_map_nested pte_index
656#define pte_unmap(pte) do { } while (0)
657#define pte_unmap_nested(pte) do { } while (0)
658
659/* Actual page table PTE updates. */
660extern void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, pte_t *ptep, pte_t orig);
661
662static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte)
663{
664 pte_t orig = *ptep;
665
666 *ptep = pte;
667
668 /* It is more efficient to let flush_tlb_kernel_range()
669 * handle init_mm tlb flushes.
670 *
671 * SUN4V NOTE: _PAGE_VALID is the same value in both the SUN4U
672 * and SUN4V pte layout, so this inline test is fine.
673 */
674 if (likely(mm != &init_mm) && (pte_val(orig) & _PAGE_VALID))
675 tlb_batch_add(mm, addr, ptep, orig);
676}
677
678#define pte_clear(mm,addr,ptep) \
679 set_pte_at((mm), (addr), (ptep), __pte(0UL))
680
681#ifdef DCACHE_ALIASING_POSSIBLE
682#define __HAVE_ARCH_MOVE_PTE
683#define move_pte(pte, prot, old_addr, new_addr) \
684({ \
685 pte_t newpte = (pte); \
686 if (tlb_type != hypervisor && pte_present(pte)) { \
687 unsigned long this_pfn = pte_pfn(pte); \
688 \
689 if (pfn_valid(this_pfn) && \
690 (((old_addr) ^ (new_addr)) & (1 << 13))) \
691 flush_dcache_page_all(current->mm, \
692 pfn_to_page(this_pfn)); \
693 } \
694 newpte; \
695})
696#endif
697
698extern pgd_t swapper_pg_dir[2048];
699extern pmd_t swapper_low_pmd_dir[2048];
700
701extern void paging_init(void);
702extern unsigned long find_ecache_flush_span(unsigned long size);
703
704/* These do nothing with the way I have things setup. */
705#define mmu_lockarea(vaddr, len) (vaddr)
706#define mmu_unlockarea(vaddr, len) do { } while(0)
707
708struct vm_area_struct;
709extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
710
711/* Encode and de-code a swap entry */
712#define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0xffUL)
713#define __swp_offset(entry) ((entry).val >> (PAGE_SHIFT + 8UL))
714#define __swp_entry(type, offset) \
715 ( (swp_entry_t) \
716 { \
717 (((long)(type) << PAGE_SHIFT) | \
718 ((long)(offset) << (PAGE_SHIFT + 8UL))) \
719 } )
720#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
721#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
722
723/* File offset in PTE support. */
724extern unsigned long pte_file(pte_t);
725#define pte_to_pgoff(pte) (pte_val(pte) >> PAGE_SHIFT)
726extern pte_t pgoff_to_pte(unsigned long);
727#define PTE_FILE_MAX_BITS (64UL - PAGE_SHIFT - 1UL)
728
729extern unsigned long *sparc64_valid_addr_bitmap;
730
731/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
732#define kern_addr_valid(addr) \
733 (test_bit(__pa((unsigned long)(addr))>>22, sparc64_valid_addr_bitmap))
734
735extern int page_in_phys_avail(unsigned long paddr);
736
737extern int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from,
738 unsigned long pfn,
739 unsigned long size, pgprot_t prot);
740
741/*
742 * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
743 * its high 4 bits. These macros/functions put it there or get it from there.
744 */
745#define MK_IOSPACE_PFN(space, pfn) (pfn | (space << (BITS_PER_LONG - 4)))
746#define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4))
747#define GET_PFN(pfn) (pfn & 0x0fffffffffffffffUL)
748
749#include <asm-generic/pgtable.h>
750
751/* We provide our own get_unmapped_area to cope with VA holes and
752 * SHM area cache aliasing for userland.
753 */
754#define HAVE_ARCH_UNMAPPED_AREA
755#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
756
757/* We provide a special get_unmapped_area for framebuffer mmaps to try and use
758 * the largest alignment possible such that larget PTEs can be used.
759 */
760extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long,
761 unsigned long, unsigned long,
762 unsigned long);
763#define HAVE_ARCH_FB_UNMAPPED_AREA
764
765extern void pgtable_cache_init(void);
766extern void sun4v_register_fault_status(void);
767extern void sun4v_ktsb_register(void);
768extern void __init cheetah_ecache_flush_init(void);
769extern void sun4v_patch_tlb_handlers(void);
770
771extern unsigned long cmdline_memory_size;
772
773#endif /* !(__ASSEMBLY__) */
774
775#endif /* !(_SPARC64_PGTABLE_H) */
diff --git a/include/asm-sparc/pgtsrmmu.h b/include/asm-sparc/pgtsrmmu.h
deleted file mode 100644
index 808555fc1d5..00000000000
--- a/include/asm-sparc/pgtsrmmu.h
+++ /dev/null
@@ -1,298 +0,0 @@
1/*
2 * pgtsrmmu.h: SRMMU page table defines and code.
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 */
6
7#ifndef _SPARC_PGTSRMMU_H
8#define _SPARC_PGTSRMMU_H
9
10#include <asm/page.h>
11
12#ifdef __ASSEMBLY__
13#include <asm/thread_info.h> /* TI_UWINMASK for WINDOW_FLUSH */
14#endif
15
16/* Number of contexts is implementation-dependent; 64k is the most we support */
17#define SRMMU_MAX_CONTEXTS 65536
18
19/* PMD_SHIFT determines the size of the area a second-level page table entry can map */
20#define SRMMU_REAL_PMD_SHIFT 18
21#define SRMMU_REAL_PMD_SIZE (1UL << SRMMU_REAL_PMD_SHIFT)
22#define SRMMU_REAL_PMD_MASK (~(SRMMU_REAL_PMD_SIZE-1))
23#define SRMMU_REAL_PMD_ALIGN(__addr) (((__addr)+SRMMU_REAL_PMD_SIZE-1)&SRMMU_REAL_PMD_MASK)
24
25/* PGDIR_SHIFT determines what a third-level page table entry can map */
26#define SRMMU_PGDIR_SHIFT 24
27#define SRMMU_PGDIR_SIZE (1UL << SRMMU_PGDIR_SHIFT)
28#define SRMMU_PGDIR_MASK (~(SRMMU_PGDIR_SIZE-1))
29#define SRMMU_PGDIR_ALIGN(addr) (((addr)+SRMMU_PGDIR_SIZE-1)&SRMMU_PGDIR_MASK)
30
31#define SRMMU_REAL_PTRS_PER_PTE 64
32#define SRMMU_REAL_PTRS_PER_PMD 64
33#define SRMMU_PTRS_PER_PGD 256
34
35#define SRMMU_REAL_PTE_TABLE_SIZE (SRMMU_REAL_PTRS_PER_PTE*4)
36#define SRMMU_PMD_TABLE_SIZE (SRMMU_REAL_PTRS_PER_PMD*4)
37#define SRMMU_PGD_TABLE_SIZE (SRMMU_PTRS_PER_PGD*4)
38
39/*
40 * To support pagetables in highmem, Linux introduces APIs which
41 * return struct page* and generally manipulate page tables when
42 * they are not mapped into kernel space. Our hardware page tables
43 * are smaller than pages. We lump hardware tabes into big, page sized
44 * software tables.
45 *
46 * PMD_SHIFT determines the size of the area a second-level page table entry
47 * can map, and our pmd_t is 16 times larger than normal. The values which
48 * were once defined here are now generic for 4c and srmmu, so they're
49 * found in pgtable.h.
50 */
51#define SRMMU_PTRS_PER_PMD 4
52
53/* Definition of the values in the ET field of PTD's and PTE's */
54#define SRMMU_ET_MASK 0x3
55#define SRMMU_ET_INVALID 0x0
56#define SRMMU_ET_PTD 0x1
57#define SRMMU_ET_PTE 0x2
58#define SRMMU_ET_REPTE 0x3 /* AIEEE, SuperSparc II reverse endian page! */
59
60/* Physical page extraction from PTP's and PTE's. */
61#define SRMMU_CTX_PMASK 0xfffffff0
62#define SRMMU_PTD_PMASK 0xfffffff0
63#define SRMMU_PTE_PMASK 0xffffff00
64
65/* The pte non-page bits. Some notes:
66 * 1) cache, dirty, valid, and ref are frobbable
67 * for both supervisor and user pages.
68 * 2) exec and write will only give the desired effect
69 * on user pages
70 * 3) use priv and priv_readonly for changing the
71 * characteristics of supervisor ptes
72 */
73#define SRMMU_CACHE 0x80
74#define SRMMU_DIRTY 0x40
75#define SRMMU_REF 0x20
76#define SRMMU_NOREAD 0x10
77#define SRMMU_EXEC 0x08
78#define SRMMU_WRITE 0x04
79#define SRMMU_VALID 0x02 /* SRMMU_ET_PTE */
80#define SRMMU_PRIV 0x1c
81#define SRMMU_PRIV_RDONLY 0x18
82
83#define SRMMU_FILE 0x40 /* Implemented in software */
84
85#define SRMMU_PTE_FILE_SHIFT 8 /* == 32-PTE_FILE_MAX_BITS */
86
87#define SRMMU_CHG_MASK (0xffffff00 | SRMMU_REF | SRMMU_DIRTY)
88
89/* SRMMU swap entry encoding
90 *
91 * We use 5 bits for the type and 19 for the offset. This gives us
92 * 32 swapfiles of 4GB each. Encoding looks like:
93 *
94 * oooooooooooooooooootttttRRRRRRRR
95 * fedcba9876543210fedcba9876543210
96 *
97 * The bottom 8 bits are reserved for protection and status bits, especially
98 * FILE and PRESENT.
99 */
100#define SRMMU_SWP_TYPE_MASK 0x1f
101#define SRMMU_SWP_TYPE_SHIFT SRMMU_PTE_FILE_SHIFT
102#define SRMMU_SWP_OFF_MASK 0x7ffff
103#define SRMMU_SWP_OFF_SHIFT (SRMMU_PTE_FILE_SHIFT + 5)
104
105/* Some day I will implement true fine grained access bits for
106 * user pages because the SRMMU gives us the capabilities to
107 * enforce all the protection levels that vma's can have.
108 * XXX But for now...
109 */
110#define SRMMU_PAGE_NONE __pgprot(SRMMU_CACHE | \
111 SRMMU_PRIV | SRMMU_REF)
112#define SRMMU_PAGE_SHARED __pgprot(SRMMU_VALID | SRMMU_CACHE | \
113 SRMMU_EXEC | SRMMU_WRITE | SRMMU_REF)
114#define SRMMU_PAGE_COPY __pgprot(SRMMU_VALID | SRMMU_CACHE | \
115 SRMMU_EXEC | SRMMU_REF)
116#define SRMMU_PAGE_RDONLY __pgprot(SRMMU_VALID | SRMMU_CACHE | \
117 SRMMU_EXEC | SRMMU_REF)
118#define SRMMU_PAGE_KERNEL __pgprot(SRMMU_VALID | SRMMU_CACHE | SRMMU_PRIV | \
119 SRMMU_DIRTY | SRMMU_REF)
120
121/* SRMMU Register addresses in ASI 0x4. These are valid for all
122 * current SRMMU implementations that exist.
123 */
124#define SRMMU_CTRL_REG 0x00000000
125#define SRMMU_CTXTBL_PTR 0x00000100
126#define SRMMU_CTX_REG 0x00000200
127#define SRMMU_FAULT_STATUS 0x00000300
128#define SRMMU_FAULT_ADDR 0x00000400
129
130#define WINDOW_FLUSH(tmp1, tmp2) \
131 mov 0, tmp1; \
13298: ld [%g6 + TI_UWINMASK], tmp2; \
133 orcc %g0, tmp2, %g0; \
134 add tmp1, 1, tmp1; \
135 bne 98b; \
136 save %sp, -64, %sp; \
13799: subcc tmp1, 1, tmp1; \
138 bne 99b; \
139 restore %g0, %g0, %g0;
140
141#ifndef __ASSEMBLY__
142
143/* This makes sense. Honest it does - Anton */
144/* XXX Yes but it's ugly as sin. FIXME. -KMW */
145extern void *srmmu_nocache_pool;
146#define __nocache_pa(VADDR) (((unsigned long)VADDR) - SRMMU_NOCACHE_VADDR + __pa((unsigned long)srmmu_nocache_pool))
147#define __nocache_va(PADDR) (__va((unsigned long)PADDR) - (unsigned long)srmmu_nocache_pool + SRMMU_NOCACHE_VADDR)
148#define __nocache_fix(VADDR) __va(__nocache_pa(VADDR))
149
150/* Accessing the MMU control register. */
151static inline unsigned int srmmu_get_mmureg(void)
152{
153 unsigned int retval;
154 __asm__ __volatile__("lda [%%g0] %1, %0\n\t" :
155 "=r" (retval) :
156 "i" (ASI_M_MMUREGS));
157 return retval;
158}
159
160static inline void srmmu_set_mmureg(unsigned long regval)
161{
162 __asm__ __volatile__("sta %0, [%%g0] %1\n\t" : :
163 "r" (regval), "i" (ASI_M_MMUREGS) : "memory");
164
165}
166
167static inline void srmmu_set_ctable_ptr(unsigned long paddr)
168{
169 paddr = ((paddr >> 4) & SRMMU_CTX_PMASK);
170 __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
171 "r" (paddr), "r" (SRMMU_CTXTBL_PTR),
172 "i" (ASI_M_MMUREGS) :
173 "memory");
174}
175
176static inline unsigned long srmmu_get_ctable_ptr(void)
177{
178 unsigned int retval;
179
180 __asm__ __volatile__("lda [%1] %2, %0\n\t" :
181 "=r" (retval) :
182 "r" (SRMMU_CTXTBL_PTR),
183 "i" (ASI_M_MMUREGS));
184 return (retval & SRMMU_CTX_PMASK) << 4;
185}
186
187static inline void srmmu_set_context(int context)
188{
189 __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
190 "r" (context), "r" (SRMMU_CTX_REG),
191 "i" (ASI_M_MMUREGS) : "memory");
192}
193
194static inline int srmmu_get_context(void)
195{
196 register int retval;
197 __asm__ __volatile__("lda [%1] %2, %0\n\t" :
198 "=r" (retval) :
199 "r" (SRMMU_CTX_REG),
200 "i" (ASI_M_MMUREGS));
201 return retval;
202}
203
204static inline unsigned int srmmu_get_fstatus(void)
205{
206 unsigned int retval;
207
208 __asm__ __volatile__("lda [%1] %2, %0\n\t" :
209 "=r" (retval) :
210 "r" (SRMMU_FAULT_STATUS), "i" (ASI_M_MMUREGS));
211 return retval;
212}
213
214static inline unsigned int srmmu_get_faddr(void)
215{
216 unsigned int retval;
217
218 __asm__ __volatile__("lda [%1] %2, %0\n\t" :
219 "=r" (retval) :
220 "r" (SRMMU_FAULT_ADDR), "i" (ASI_M_MMUREGS));
221 return retval;
222}
223
224/* This is guaranteed on all SRMMU's. */
225static inline void srmmu_flush_whole_tlb(void)
226{
227 __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
228 "r" (0x400), /* Flush entire TLB!! */
229 "i" (ASI_M_FLUSH_PROBE) : "memory");
230
231}
232
233/* These flush types are not available on all chips... */
234static inline void srmmu_flush_tlb_ctx(void)
235{
236 __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
237 "r" (0x300), /* Flush TLB ctx.. */
238 "i" (ASI_M_FLUSH_PROBE) : "memory");
239
240}
241
242static inline void srmmu_flush_tlb_region(unsigned long addr)
243{
244 addr &= SRMMU_PGDIR_MASK;
245 __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
246 "r" (addr | 0x200), /* Flush TLB region.. */
247 "i" (ASI_M_FLUSH_PROBE) : "memory");
248
249}
250
251
252static inline void srmmu_flush_tlb_segment(unsigned long addr)
253{
254 addr &= SRMMU_REAL_PMD_MASK;
255 __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
256 "r" (addr | 0x100), /* Flush TLB segment.. */
257 "i" (ASI_M_FLUSH_PROBE) : "memory");
258
259}
260
261static inline void srmmu_flush_tlb_page(unsigned long page)
262{
263 page &= PAGE_MASK;
264 __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
265 "r" (page), /* Flush TLB page.. */
266 "i" (ASI_M_FLUSH_PROBE) : "memory");
267
268}
269
270static inline unsigned long srmmu_hwprobe(unsigned long vaddr)
271{
272 unsigned long retval;
273
274 vaddr &= PAGE_MASK;
275 __asm__ __volatile__("lda [%1] %2, %0\n\t" :
276 "=r" (retval) :
277 "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
278
279 return retval;
280}
281
282static inline int
283srmmu_get_pte (unsigned long addr)
284{
285 register unsigned long entry;
286
287 __asm__ __volatile__("\n\tlda [%1] %2,%0\n\t" :
288 "=r" (entry):
289 "r" ((addr & 0xfffff000) | 0x400), "i" (ASI_M_FLUSH_PROBE));
290 return entry;
291}
292
293extern unsigned long (*srmmu_read_physical)(unsigned long paddr);
294extern void (*srmmu_write_physical)(unsigned long paddr, unsigned long word);
295
296#endif /* !(__ASSEMBLY__) */
297
298#endif /* !(_SPARC_PGTSRMMU_H) */
diff --git a/include/asm-sparc/pgtsun4.h b/include/asm-sparc/pgtsun4.h
deleted file mode 100644
index 5a0d661fb82..00000000000
--- a/include/asm-sparc/pgtsun4.h
+++ /dev/null
@@ -1,171 +0,0 @@
1/*
2 * pgtsun4.h: Sun4 specific pgtable.h defines and code.
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7#ifndef _SPARC_PGTSUN4C_H
8#define _SPARC_PGTSUN4C_H
9
10#include <asm/contregs.h>
11
12/* PMD_SHIFT determines the size of the area a second-level page table can map */
13#define SUN4C_PMD_SHIFT 23
14
15/* PGDIR_SHIFT determines what a third-level page table entry can map */
16#define SUN4C_PGDIR_SHIFT 23
17#define SUN4C_PGDIR_SIZE (1UL << SUN4C_PGDIR_SHIFT)
18#define SUN4C_PGDIR_MASK (~(SUN4C_PGDIR_SIZE-1))
19#define SUN4C_PGDIR_ALIGN(addr) (((addr)+SUN4C_PGDIR_SIZE-1)&SUN4C_PGDIR_MASK)
20
21/* To represent how the sun4c mmu really lays things out. */
22#define SUN4C_REAL_PGDIR_SHIFT 18
23#define SUN4C_REAL_PGDIR_SIZE (1UL << SUN4C_REAL_PGDIR_SHIFT)
24#define SUN4C_REAL_PGDIR_MASK (~(SUN4C_REAL_PGDIR_SIZE-1))
25#define SUN4C_REAL_PGDIR_ALIGN(addr) (((addr)+SUN4C_REAL_PGDIR_SIZE-1)&SUN4C_REAL_PGDIR_MASK)
26
27/* 19 bit PFN on sun4 */
28#define SUN4C_PFN_MASK 0x7ffff
29
30/* Don't increase these unless the structures in sun4c.c are fixed */
31#define SUN4C_MAX_SEGMAPS 256
32#define SUN4C_MAX_CONTEXTS 16
33
34/*
35 * To be efficient, and not have to worry about allocating such
36 * a huge pgd, we make the kernel sun4c tables each hold 1024
37 * entries and the pgd similarly just like the i386 tables.
38 */
39#define SUN4C_PTRS_PER_PTE 1024
40#define SUN4C_PTRS_PER_PMD 1
41#define SUN4C_PTRS_PER_PGD 1024
42
43/*
44 * Sparc SUN4C pte fields.
45 */
46#define _SUN4C_PAGE_VALID 0x80000000
47#define _SUN4C_PAGE_SILENT_READ 0x80000000 /* synonym */
48#define _SUN4C_PAGE_DIRTY 0x40000000
49#define _SUN4C_PAGE_SILENT_WRITE 0x40000000 /* synonym */
50#define _SUN4C_PAGE_PRIV 0x20000000 /* privileged page */
51#define _SUN4C_PAGE_NOCACHE 0x10000000 /* non-cacheable page */
52#define _SUN4C_PAGE_PRESENT 0x08000000 /* implemented in software */
53#define _SUN4C_PAGE_IO 0x04000000 /* I/O page */
54#define _SUN4C_PAGE_FILE 0x02000000 /* implemented in software */
55#define _SUN4C_PAGE_READ 0x00800000 /* implemented in software */
56#define _SUN4C_PAGE_WRITE 0x00400000 /* implemented in software */
57#define _SUN4C_PAGE_ACCESSED 0x00200000 /* implemented in software */
58#define _SUN4C_PAGE_MODIFIED 0x00100000 /* implemented in software */
59
60#define _SUN4C_READABLE (_SUN4C_PAGE_READ|_SUN4C_PAGE_SILENT_READ|\
61 _SUN4C_PAGE_ACCESSED)
62#define _SUN4C_WRITEABLE (_SUN4C_PAGE_WRITE|_SUN4C_PAGE_SILENT_WRITE|\
63 _SUN4C_PAGE_MODIFIED)
64
65#define _SUN4C_PAGE_CHG_MASK (0xffff|_SUN4C_PAGE_ACCESSED|_SUN4C_PAGE_MODIFIED)
66
67#define SUN4C_PAGE_NONE __pgprot(_SUN4C_PAGE_PRESENT)
68#define SUN4C_PAGE_SHARED __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE|\
69 _SUN4C_PAGE_WRITE)
70#define SUN4C_PAGE_COPY __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE)
71#define SUN4C_PAGE_READONLY __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE)
72#define SUN4C_PAGE_KERNEL __pgprot(_SUN4C_READABLE|_SUN4C_WRITEABLE|\
73 _SUN4C_PAGE_DIRTY|_SUN4C_PAGE_PRIV)
74
75/* SUN4C swap entry encoding
76 *
77 * We use 5 bits for the type and 19 for the offset. This gives us
78 * 32 swapfiles of 4GB each. Encoding looks like:
79 *
80 * RRRRRRRRooooooooooooooooooottttt
81 * fedcba9876543210fedcba9876543210
82 *
83 * The top 8 bits are reserved for protection and status bits, especially
84 * FILE and PRESENT.
85 */
86#define SUN4C_SWP_TYPE_MASK 0x1f
87#define SUN4C_SWP_OFF_MASK 0x7ffff
88#define SUN4C_SWP_OFF_SHIFT 5
89
90#ifndef __ASSEMBLY__
91
92static inline unsigned long sun4c_get_synchronous_error(void)
93{
94 unsigned long sync_err;
95
96 __asm__ __volatile__("lda [%1] %2, %0\n\t" :
97 "=r" (sync_err) :
98 "r" (AC_SYNC_ERR), "i" (ASI_CONTROL));
99 return sync_err;
100}
101
102static inline unsigned long sun4c_get_synchronous_address(void)
103{
104 unsigned long sync_addr;
105
106 __asm__ __volatile__("lda [%1] %2, %0\n\t" :
107 "=r" (sync_addr) :
108 "r" (AC_SYNC_VA), "i" (ASI_CONTROL));
109 return sync_addr;
110}
111
112/* SUN4 pte, segmap, and context manipulation */
113static inline unsigned long sun4c_get_segmap(unsigned long addr)
114{
115 register unsigned long entry;
116
117 __asm__ __volatile__("\n\tlduha [%1] %2, %0\n\t" :
118 "=r" (entry) :
119 "r" (addr), "i" (ASI_SEGMAP));
120 return entry;
121}
122
123static inline void sun4c_put_segmap(unsigned long addr, unsigned long entry)
124{
125 __asm__ __volatile__("\n\tstha %1, [%0] %2; nop; nop; nop;\n\t" : :
126 "r" (addr), "r" (entry),
127 "i" (ASI_SEGMAP)
128 : "memory");
129}
130
131static inline unsigned long sun4c_get_pte(unsigned long addr)
132{
133 register unsigned long entry;
134
135 __asm__ __volatile__("\n\tlda [%1] %2, %0\n\t" :
136 "=r" (entry) :
137 "r" (addr), "i" (ASI_PTE));
138 return entry;
139}
140
141static inline void sun4c_put_pte(unsigned long addr, unsigned long entry)
142{
143 __asm__ __volatile__("\n\tsta %1, [%0] %2; nop; nop; nop;\n\t" : :
144 "r" (addr),
145 "r" ((entry & ~(_SUN4C_PAGE_PRESENT))), "i" (ASI_PTE)
146 : "memory");
147}
148
149static inline int sun4c_get_context(void)
150{
151 register int ctx;
152
153 __asm__ __volatile__("\n\tlduba [%1] %2, %0\n\t" :
154 "=r" (ctx) :
155 "r" (AC_CONTEXT), "i" (ASI_CONTROL));
156
157 return ctx;
158}
159
160static inline int sun4c_set_context(int ctx)
161{
162 __asm__ __volatile__("\n\tstba %0, [%1] %2; nop; nop; nop;\n\t" : :
163 "r" (ctx), "r" (AC_CONTEXT), "i" (ASI_CONTROL)
164 : "memory");
165
166 return ctx;
167}
168
169#endif /* !(__ASSEMBLY__) */
170
171#endif /* !(_SPARC_PGTSUN4_H) */
diff --git a/include/asm-sparc/pgtsun4c.h b/include/asm-sparc/pgtsun4c.h
deleted file mode 100644
index aeb25e91217..00000000000
--- a/include/asm-sparc/pgtsun4c.h
+++ /dev/null
@@ -1,172 +0,0 @@
1/*
2 * pgtsun4c.h: Sun4c specific pgtable.h defines and code.
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 */
6#ifndef _SPARC_PGTSUN4C_H
7#define _SPARC_PGTSUN4C_H
8
9#include <asm/contregs.h>
10
11/* PMD_SHIFT determines the size of the area a second-level page table can map */
12#define SUN4C_PMD_SHIFT 22
13
14/* PGDIR_SHIFT determines what a third-level page table entry can map */
15#define SUN4C_PGDIR_SHIFT 22
16#define SUN4C_PGDIR_SIZE (1UL << SUN4C_PGDIR_SHIFT)
17#define SUN4C_PGDIR_MASK (~(SUN4C_PGDIR_SIZE-1))
18#define SUN4C_PGDIR_ALIGN(addr) (((addr)+SUN4C_PGDIR_SIZE-1)&SUN4C_PGDIR_MASK)
19
20/* To represent how the sun4c mmu really lays things out. */
21#define SUN4C_REAL_PGDIR_SHIFT 18
22#define SUN4C_REAL_PGDIR_SIZE (1UL << SUN4C_REAL_PGDIR_SHIFT)
23#define SUN4C_REAL_PGDIR_MASK (~(SUN4C_REAL_PGDIR_SIZE-1))
24#define SUN4C_REAL_PGDIR_ALIGN(addr) (((addr)+SUN4C_REAL_PGDIR_SIZE-1)&SUN4C_REAL_PGDIR_MASK)
25
26/* 16 bit PFN on sun4c */
27#define SUN4C_PFN_MASK 0xffff
28
29/* Don't increase these unless the structures in sun4c.c are fixed */
30#define SUN4C_MAX_SEGMAPS 256
31#define SUN4C_MAX_CONTEXTS 16
32
33/*
34 * To be efficient, and not have to worry about allocating such
35 * a huge pgd, we make the kernel sun4c tables each hold 1024
36 * entries and the pgd similarly just like the i386 tables.
37 */
38#define SUN4C_PTRS_PER_PTE 1024
39#define SUN4C_PTRS_PER_PMD 1
40#define SUN4C_PTRS_PER_PGD 1024
41
42/*
43 * Sparc SUN4C pte fields.
44 */
45#define _SUN4C_PAGE_VALID 0x80000000
46#define _SUN4C_PAGE_SILENT_READ 0x80000000 /* synonym */
47#define _SUN4C_PAGE_DIRTY 0x40000000
48#define _SUN4C_PAGE_SILENT_WRITE 0x40000000 /* synonym */
49#define _SUN4C_PAGE_PRIV 0x20000000 /* privileged page */
50#define _SUN4C_PAGE_NOCACHE 0x10000000 /* non-cacheable page */
51#define _SUN4C_PAGE_PRESENT 0x08000000 /* implemented in software */
52#define _SUN4C_PAGE_IO 0x04000000 /* I/O page */
53#define _SUN4C_PAGE_FILE 0x02000000 /* implemented in software */
54#define _SUN4C_PAGE_READ 0x00800000 /* implemented in software */
55#define _SUN4C_PAGE_WRITE 0x00400000 /* implemented in software */
56#define _SUN4C_PAGE_ACCESSED 0x00200000 /* implemented in software */
57#define _SUN4C_PAGE_MODIFIED 0x00100000 /* implemented in software */
58
59#define _SUN4C_READABLE (_SUN4C_PAGE_READ|_SUN4C_PAGE_SILENT_READ|\
60 _SUN4C_PAGE_ACCESSED)
61#define _SUN4C_WRITEABLE (_SUN4C_PAGE_WRITE|_SUN4C_PAGE_SILENT_WRITE|\
62 _SUN4C_PAGE_MODIFIED)
63
64#define _SUN4C_PAGE_CHG_MASK (0xffff|_SUN4C_PAGE_ACCESSED|_SUN4C_PAGE_MODIFIED)
65
66#define SUN4C_PAGE_NONE __pgprot(_SUN4C_PAGE_PRESENT)
67#define SUN4C_PAGE_SHARED __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE|\
68 _SUN4C_PAGE_WRITE)
69#define SUN4C_PAGE_COPY __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE)
70#define SUN4C_PAGE_READONLY __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE)
71#define SUN4C_PAGE_KERNEL __pgprot(_SUN4C_READABLE|_SUN4C_WRITEABLE|\
72 _SUN4C_PAGE_DIRTY|_SUN4C_PAGE_PRIV)
73
74/* SUN4C swap entry encoding
75 *
76 * We use 5 bits for the type and 19 for the offset. This gives us
77 * 32 swapfiles of 4GB each. Encoding looks like:
78 *
79 * RRRRRRRRooooooooooooooooooottttt
80 * fedcba9876543210fedcba9876543210
81 *
82 * The top 8 bits are reserved for protection and status bits, especially
83 * FILE and PRESENT.
84 */
85#define SUN4C_SWP_TYPE_MASK 0x1f
86#define SUN4C_SWP_OFF_MASK 0x7ffff
87#define SUN4C_SWP_OFF_SHIFT 5
88
89#ifndef __ASSEMBLY__
90
91static inline unsigned long sun4c_get_synchronous_error(void)
92{
93 unsigned long sync_err;
94
95 __asm__ __volatile__("lda [%1] %2, %0\n\t" :
96 "=r" (sync_err) :
97 "r" (AC_SYNC_ERR), "i" (ASI_CONTROL));
98 return sync_err;
99}
100
101static inline unsigned long sun4c_get_synchronous_address(void)
102{
103 unsigned long sync_addr;
104
105 __asm__ __volatile__("lda [%1] %2, %0\n\t" :
106 "=r" (sync_addr) :
107 "r" (AC_SYNC_VA), "i" (ASI_CONTROL));
108 return sync_addr;
109}
110
111/* SUN4C pte, segmap, and context manipulation */
112static inline unsigned long sun4c_get_segmap(unsigned long addr)
113{
114 register unsigned long entry;
115
116 __asm__ __volatile__("\n\tlduba [%1] %2, %0\n\t" :
117 "=r" (entry) :
118 "r" (addr), "i" (ASI_SEGMAP));
119
120 return entry;
121}
122
123static inline void sun4c_put_segmap(unsigned long addr, unsigned long entry)
124{
125
126 __asm__ __volatile__("\n\tstba %1, [%0] %2; nop; nop; nop;\n\t" : :
127 "r" (addr), "r" (entry),
128 "i" (ASI_SEGMAP)
129 : "memory");
130}
131
132static inline unsigned long sun4c_get_pte(unsigned long addr)
133{
134 register unsigned long entry;
135
136 __asm__ __volatile__("\n\tlda [%1] %2, %0\n\t" :
137 "=r" (entry) :
138 "r" (addr), "i" (ASI_PTE));
139 return entry;
140}
141
142static inline void sun4c_put_pte(unsigned long addr, unsigned long entry)
143{
144 __asm__ __volatile__("\n\tsta %1, [%0] %2; nop; nop; nop;\n\t" : :
145 "r" (addr),
146 "r" ((entry & ~(_SUN4C_PAGE_PRESENT))), "i" (ASI_PTE)
147 : "memory");
148}
149
150static inline int sun4c_get_context(void)
151{
152 register int ctx;
153
154 __asm__ __volatile__("\n\tlduba [%1] %2, %0\n\t" :
155 "=r" (ctx) :
156 "r" (AC_CONTEXT), "i" (ASI_CONTROL));
157
158 return ctx;
159}
160
161static inline int sun4c_set_context(int ctx)
162{
163 __asm__ __volatile__("\n\tstba %0, [%1] %2; nop; nop; nop;\n\t" : :
164 "r" (ctx), "r" (AC_CONTEXT), "i" (ASI_CONTROL)
165 : "memory");
166
167 return ctx;
168}
169
170#endif /* !(__ASSEMBLY__) */
171
172#endif /* !(_SPARC_PGTSUN4C_H) */
diff --git a/include/asm-sparc/pil.h b/include/asm-sparc/pil.h
deleted file mode 100644
index 71819bb943f..00000000000
--- a/include/asm-sparc/pil.h
+++ /dev/null
@@ -1,22 +0,0 @@
1#ifndef _SPARC64_PIL_H
2#define _SPARC64_PIL_H
3
4/* To avoid some locking problems, we hard allocate certain PILs
5 * for SMP cross call messages that must do a etrap/rtrap.
6 *
7 * A local_irq_disable() does not block the cross call delivery, so
8 * when SMP locking is an issue we reschedule the event into a PIL
9 * interrupt which is blocked by local_irq_disable().
10 *
11 * In fact any XCALL which has to etrap/rtrap has a problem because
12 * it is difficult to prevent rtrap from running BH's, and that would
13 * need to be done if the XCALL arrived while %pil==15.
14 */
15#define PIL_SMP_CALL_FUNC 1
16#define PIL_SMP_RECEIVE_SIGNAL 2
17#define PIL_SMP_CAPTURE 3
18#define PIL_SMP_CTX_NEW_VERSION 4
19#define PIL_DEVICE_IRQ 5
20#define PIL_SMP_CALL_FUNC_SNGL 6
21
22#endif /* !(_SPARC64_PIL_H) */
diff --git a/include/asm-sparc/poll.h b/include/asm-sparc/poll.h
deleted file mode 100644
index 091d3ad2e83..00000000000
--- a/include/asm-sparc/poll.h
+++ /dev/null
@@ -1,12 +0,0 @@
1#ifndef __SPARC_POLL_H
2#define __SPARC_POLL_H
3
4#define POLLWRNORM POLLOUT
5#define POLLWRBAND 256
6#define POLLMSG 512
7#define POLLREMOVE 1024
8#define POLLRDHUP 2048
9
10#include <asm-generic/poll.h>
11
12#endif
diff --git a/include/asm-sparc/posix_types.h b/include/asm-sparc/posix_types.h
deleted file mode 100644
index 58c820d75e8..00000000000
--- a/include/asm-sparc/posix_types.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_POSIX_TYPES_H
2#define ___ASM_SPARC_POSIX_TYPES_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/posix_types_64.h>
5#else
6#include <asm-sparc/posix_types_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/posix_types_32.h b/include/asm-sparc/posix_types_32.h
deleted file mode 100644
index 6bb6eb1ca0f..00000000000
--- a/include/asm-sparc/posix_types_32.h
+++ /dev/null
@@ -1,118 +0,0 @@
1#ifndef __ARCH_SPARC_POSIX_TYPES_H
2#define __ARCH_SPARC_POSIX_TYPES_H
3
4/*
5 * This file is generally used by user-level software, so you need to
6 * be a little careful about namespace pollution etc. Also, we cannot
7 * assume GCC is being used.
8 */
9
10typedef unsigned int __kernel_size_t;
11typedef int __kernel_ssize_t;
12typedef long int __kernel_ptrdiff_t;
13typedef long __kernel_time_t;
14typedef long __kernel_suseconds_t;
15typedef long __kernel_clock_t;
16typedef int __kernel_pid_t;
17typedef unsigned short __kernel_ipc_pid_t;
18typedef unsigned short __kernel_uid_t;
19typedef unsigned short __kernel_gid_t;
20typedef unsigned long __kernel_ino_t;
21typedef unsigned short __kernel_mode_t;
22typedef unsigned short __kernel_umode_t;
23typedef short __kernel_nlink_t;
24typedef long __kernel_daddr_t;
25typedef long __kernel_off_t;
26typedef char * __kernel_caddr_t;
27typedef unsigned short __kernel_uid16_t;
28typedef unsigned short __kernel_gid16_t;
29typedef unsigned int __kernel_uid32_t;
30typedef unsigned int __kernel_gid32_t;
31typedef unsigned short __kernel_old_uid_t;
32typedef unsigned short __kernel_old_gid_t;
33typedef unsigned short __kernel_old_dev_t;
34typedef int __kernel_clockid_t;
35typedef int __kernel_timer_t;
36
37#ifdef __GNUC__
38typedef long long __kernel_loff_t;
39#endif
40
41typedef struct {
42 int val[2];
43} __kernel_fsid_t;
44
45#if defined(__KERNEL__)
46
47#undef __FD_SET
48static inline void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
49{
50 unsigned long _tmp = fd / __NFDBITS;
51 unsigned long _rem = fd % __NFDBITS;
52 fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
53}
54
55#undef __FD_CLR
56static inline void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
57{
58 unsigned long _tmp = fd / __NFDBITS;
59 unsigned long _rem = fd % __NFDBITS;
60 fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
61}
62
63#undef __FD_ISSET
64static inline int __FD_ISSET(unsigned long fd, __const__ __kernel_fd_set *p)
65{
66 unsigned long _tmp = fd / __NFDBITS;
67 unsigned long _rem = fd % __NFDBITS;
68 return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
69}
70
71/*
72 * This will unroll the loop for the normal constant cases (8 or 32 longs,
73 * for 256 and 1024-bit fd_sets respectively)
74 */
75#undef __FD_ZERO
76static inline void __FD_ZERO(__kernel_fd_set *p)
77{
78 unsigned long *tmp = p->fds_bits;
79 int i;
80
81 if (__builtin_constant_p(__FDSET_LONGS)) {
82 switch (__FDSET_LONGS) {
83 case 32:
84 tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
85 tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
86 tmp[ 8] = 0; tmp[ 9] = 0; tmp[10] = 0; tmp[11] = 0;
87 tmp[12] = 0; tmp[13] = 0; tmp[14] = 0; tmp[15] = 0;
88 tmp[16] = 0; tmp[17] = 0; tmp[18] = 0; tmp[19] = 0;
89 tmp[20] = 0; tmp[21] = 0; tmp[22] = 0; tmp[23] = 0;
90 tmp[24] = 0; tmp[25] = 0; tmp[26] = 0; tmp[27] = 0;
91 tmp[28] = 0; tmp[29] = 0; tmp[30] = 0; tmp[31] = 0;
92 return;
93 case 16:
94 tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
95 tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
96 tmp[ 8] = 0; tmp[ 9] = 0; tmp[10] = 0; tmp[11] = 0;
97 tmp[12] = 0; tmp[13] = 0; tmp[14] = 0; tmp[15] = 0;
98 return;
99 case 8:
100 tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
101 tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
102 return;
103 case 4:
104 tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
105 return;
106 }
107 }
108 i = __FDSET_LONGS;
109 while (i) {
110 i--;
111 *tmp = 0;
112 tmp++;
113 }
114}
115
116#endif /* defined(__KERNEL__) */
117
118#endif /* !(__ARCH_SPARC_POSIX_TYPES_H) */
diff --git a/include/asm-sparc/posix_types_64.h b/include/asm-sparc/posix_types_64.h
deleted file mode 100644
index ba8f9329576..00000000000
--- a/include/asm-sparc/posix_types_64.h
+++ /dev/null
@@ -1,122 +0,0 @@
1#ifndef __ARCH_SPARC64_POSIX_TYPES_H
2#define __ARCH_SPARC64_POSIX_TYPES_H
3
4/*
5 * This file is generally used by user-level software, so you need to
6 * be a little careful about namespace pollution etc. Also, we cannot
7 * assume GCC is being used.
8 */
9
10typedef unsigned long __kernel_size_t;
11typedef long __kernel_ssize_t;
12typedef long __kernel_ptrdiff_t;
13typedef long __kernel_time_t;
14typedef long __kernel_clock_t;
15typedef int __kernel_pid_t;
16typedef int __kernel_ipc_pid_t;
17typedef unsigned int __kernel_uid_t;
18typedef unsigned int __kernel_gid_t;
19typedef unsigned long __kernel_ino_t;
20typedef unsigned int __kernel_mode_t;
21typedef unsigned short __kernel_umode_t;
22typedef unsigned int __kernel_nlink_t;
23typedef int __kernel_daddr_t;
24typedef long __kernel_off_t;
25typedef char * __kernel_caddr_t;
26typedef unsigned short __kernel_uid16_t;
27typedef unsigned short __kernel_gid16_t;
28typedef int __kernel_clockid_t;
29typedef int __kernel_timer_t;
30
31typedef unsigned short __kernel_old_uid_t;
32typedef unsigned short __kernel_old_gid_t;
33typedef __kernel_uid_t __kernel_uid32_t;
34typedef __kernel_gid_t __kernel_gid32_t;
35
36typedef unsigned int __kernel_old_dev_t;
37
38/* Note this piece of asymmetry from the v9 ABI. */
39typedef int __kernel_suseconds_t;
40
41#ifdef __GNUC__
42typedef long long __kernel_loff_t;
43#endif
44
45typedef struct {
46 int val[2];
47} __kernel_fsid_t;
48
49#if defined(__KERNEL__)
50
51#undef __FD_SET
52static inline void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
53{
54 unsigned long _tmp = fd / __NFDBITS;
55 unsigned long _rem = fd % __NFDBITS;
56 fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
57}
58
59#undef __FD_CLR
60static inline void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
61{
62 unsigned long _tmp = fd / __NFDBITS;
63 unsigned long _rem = fd % __NFDBITS;
64 fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
65}
66
67#undef __FD_ISSET
68static inline int __FD_ISSET(unsigned long fd, __const__ __kernel_fd_set *p)
69{
70 unsigned long _tmp = fd / __NFDBITS;
71 unsigned long _rem = fd % __NFDBITS;
72 return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
73}
74
75/*
76 * This will unroll the loop for the normal constant cases (8 or 32 longs,
77 * for 256 and 1024-bit fd_sets respectively)
78 */
79#undef __FD_ZERO
80static inline void __FD_ZERO(__kernel_fd_set *p)
81{
82 unsigned long *tmp = p->fds_bits;
83 int i;
84
85 if (__builtin_constant_p(__FDSET_LONGS)) {
86 switch (__FDSET_LONGS) {
87 case 32:
88 tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
89 tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
90 tmp[ 8] = 0; tmp[ 9] = 0; tmp[10] = 0; tmp[11] = 0;
91 tmp[12] = 0; tmp[13] = 0; tmp[14] = 0; tmp[15] = 0;
92 tmp[16] = 0; tmp[17] = 0; tmp[18] = 0; tmp[19] = 0;
93 tmp[20] = 0; tmp[21] = 0; tmp[22] = 0; tmp[23] = 0;
94 tmp[24] = 0; tmp[25] = 0; tmp[26] = 0; tmp[27] = 0;
95 tmp[28] = 0; tmp[29] = 0; tmp[30] = 0; tmp[31] = 0;
96 return;
97 case 16:
98 tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
99 tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
100 tmp[ 8] = 0; tmp[ 9] = 0; tmp[10] = 0; tmp[11] = 0;
101 tmp[12] = 0; tmp[13] = 0; tmp[14] = 0; tmp[15] = 0;
102 return;
103 case 8:
104 tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
105 tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
106 return;
107 case 4:
108 tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
109 return;
110 }
111 }
112 i = __FDSET_LONGS;
113 while (i) {
114 i--;
115 *tmp = 0;
116 tmp++;
117 }
118}
119
120#endif /* defined(__KERNEL__) */
121
122#endif /* !(__ARCH_SPARC64_POSIX_TYPES_H) */
diff --git a/include/asm-sparc/processor.h b/include/asm-sparc/processor.h
deleted file mode 100644
index 11a66bb02ea..00000000000
--- a/include/asm-sparc/processor.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_PROCESSOR_H
2#define ___ASM_SPARC_PROCESSOR_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/processor_64.h>
5#else
6#include <asm-sparc/processor_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/processor_32.h b/include/asm-sparc/processor_32.h
deleted file mode 100644
index 562c0d69c53..00000000000
--- a/include/asm-sparc/processor_32.h
+++ /dev/null
@@ -1,128 +0,0 @@
1/* include/asm-sparc/processor.h
2 *
3 * Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu)
4 */
5
6#ifndef __ASM_SPARC_PROCESSOR_H
7#define __ASM_SPARC_PROCESSOR_H
8
9/*
10 * Sparc32 implementation of macro that returns current
11 * instruction pointer ("program counter").
12 */
13#define current_text_addr() ({ void *pc; __asm__("sethi %%hi(1f), %0; or %0, %%lo(1f), %0;\n1:" : "=r" (pc)); pc; })
14
15#include <asm/psr.h>
16#include <asm/ptrace.h>
17#include <asm/head.h>
18#include <asm/signal.h>
19#include <asm/btfixup.h>
20#include <asm/page.h>
21
22/*
23 * The sparc has no problems with write protection
24 */
25#define wp_works_ok 1
26#define wp_works_ok__is_a_macro /* for versions in ksyms.c */
27
28/* Whee, this is STACK_TOP + PAGE_SIZE and the lowest kernel address too...
29 * That one page is used to protect kernel from intruders, so that
30 * we can make our access_ok test faster
31 */
32#define TASK_SIZE PAGE_OFFSET
33#ifdef __KERNEL__
34#define STACK_TOP (PAGE_OFFSET - PAGE_SIZE)
35#define STACK_TOP_MAX STACK_TOP
36#endif /* __KERNEL__ */
37
38struct task_struct;
39
40#ifdef __KERNEL__
41struct fpq {
42 unsigned long *insn_addr;
43 unsigned long insn;
44};
45#endif
46
47typedef struct {
48 int seg;
49} mm_segment_t;
50
51/* The Sparc processor specific thread struct. */
52struct thread_struct {
53 struct pt_regs *kregs;
54 unsigned int _pad1;
55
56 /* Special child fork kpsr/kwim values. */
57 unsigned long fork_kpsr __attribute__ ((aligned (8)));
58 unsigned long fork_kwim;
59
60 /* Floating point regs */
61 unsigned long float_regs[32] __attribute__ ((aligned (8)));
62 unsigned long fsr;
63 unsigned long fpqdepth;
64 struct fpq fpqueue[16];
65 unsigned long flags;
66 mm_segment_t current_ds;
67};
68
69#define SPARC_FLAG_KTHREAD 0x1 /* task is a kernel thread */
70#define SPARC_FLAG_UNALIGNED 0x2 /* is allowed to do unaligned accesses */
71
72#define INIT_THREAD { \
73 .flags = SPARC_FLAG_KTHREAD, \
74 .current_ds = KERNEL_DS, \
75}
76
77/* Return saved PC of a blocked thread. */
78extern unsigned long thread_saved_pc(struct task_struct *t);
79
80/* Do necessary setup to start up a newly executed thread. */
81static inline void start_thread(struct pt_regs * regs, unsigned long pc,
82 unsigned long sp)
83{
84 register unsigned long zero asm("g1");
85
86 regs->psr = (regs->psr & (PSR_CWP)) | PSR_S;
87 regs->pc = ((pc & (~3)) - 4);
88 regs->npc = regs->pc + 4;
89 regs->y = 0;
90 zero = 0;
91 __asm__ __volatile__("std\t%%g0, [%0 + %3 + 0x00]\n\t"
92 "std\t%%g0, [%0 + %3 + 0x08]\n\t"
93 "std\t%%g0, [%0 + %3 + 0x10]\n\t"
94 "std\t%%g0, [%0 + %3 + 0x18]\n\t"
95 "std\t%%g0, [%0 + %3 + 0x20]\n\t"
96 "std\t%%g0, [%0 + %3 + 0x28]\n\t"
97 "std\t%%g0, [%0 + %3 + 0x30]\n\t"
98 "st\t%1, [%0 + %3 + 0x38]\n\t"
99 "st\t%%g0, [%0 + %3 + 0x3c]"
100 : /* no outputs */
101 : "r" (regs),
102 "r" (sp - sizeof(struct reg_window)),
103 "r" (zero),
104 "i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))
105 : "memory");
106}
107
108/* Free all resources held by a thread. */
109#define release_thread(tsk) do { } while(0)
110extern pid_t kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
111
112/* Prepare to copy thread state - unlazy all lazy status */
113#define prepare_to_copy(tsk) do { } while (0)
114
115extern unsigned long get_wchan(struct task_struct *);
116
117#define KSTK_EIP(tsk) ((tsk)->thread.kregs->pc)
118#define KSTK_ESP(tsk) ((tsk)->thread.kregs->u_regs[UREG_FP])
119
120#ifdef __KERNEL__
121
122extern struct task_struct *last_task_used_math;
123
124#define cpu_relax() barrier()
125
126#endif
127
128#endif /* __ASM_SPARC_PROCESSOR_H */
diff --git a/include/asm-sparc/processor_64.h b/include/asm-sparc/processor_64.h
deleted file mode 100644
index 70d42801a0d..00000000000
--- a/include/asm-sparc/processor_64.h
+++ /dev/null
@@ -1,237 +0,0 @@
1/*
2 * include/asm-sparc64/processor.h
3 *
4 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
5 */
6
7#ifndef __ASM_SPARC64_PROCESSOR_H
8#define __ASM_SPARC64_PROCESSOR_H
9
10/*
11 * Sparc64 implementation of macro that returns current
12 * instruction pointer ("program counter").
13 */
14#define current_text_addr() ({ void *pc; __asm__("rd %%pc, %0" : "=r" (pc)); pc; })
15
16#include <asm/asi.h>
17#include <asm/pstate.h>
18#include <asm/ptrace.h>
19#include <asm/page.h>
20
21/* The sparc has no problems with write protection */
22#define wp_works_ok 1
23#define wp_works_ok__is_a_macro /* for versions in ksyms.c */
24
25/*
26 * User lives in his very own context, and cannot reference us. Note
27 * that TASK_SIZE is a misnomer, it really gives maximum user virtual
28 * address that the kernel will allocate out.
29 *
30 * XXX No longer using virtual page tables, kill this upper limit...
31 */
32#define VA_BITS 44
33#ifndef __ASSEMBLY__
34#define VPTE_SIZE (1UL << (VA_BITS - PAGE_SHIFT + 3))
35#else
36#define VPTE_SIZE (1 << (VA_BITS - PAGE_SHIFT + 3))
37#endif
38
39#define TASK_SIZE ((unsigned long)-VPTE_SIZE)
40#define TASK_SIZE_OF(tsk) \
41 (test_tsk_thread_flag(tsk,TIF_32BIT) ? \
42 (1UL << 32UL) : TASK_SIZE)
43#ifdef __KERNEL__
44
45#define STACK_TOP32 ((1UL << 32UL) - PAGE_SIZE)
46#define STACK_TOP64 (0x0000080000000000UL - (1UL << 32UL))
47
48#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
49 STACK_TOP32 : STACK_TOP64)
50
51#define STACK_TOP_MAX STACK_TOP64
52
53#endif
54
55#ifndef __ASSEMBLY__
56
57typedef struct {
58 unsigned char seg;
59} mm_segment_t;
60
61/* The Sparc processor specific thread struct. */
62/* XXX This should die, everything can go into thread_info now. */
63struct thread_struct {
64#ifdef CONFIG_DEBUG_SPINLOCK
65 /* How many spinlocks held by this thread.
66 * Used with spin lock debugging to catch tasks
67 * sleeping illegally with locks held.
68 */
69 int smp_lock_count;
70 unsigned int smp_lock_pc;
71#else
72 int dummy; /* f'in gcc bug... */
73#endif
74};
75
76#endif /* !(__ASSEMBLY__) */
77
78#ifndef CONFIG_DEBUG_SPINLOCK
79#define INIT_THREAD { \
80 0, \
81}
82#else /* CONFIG_DEBUG_SPINLOCK */
83#define INIT_THREAD { \
84/* smp_lock_count, smp_lock_pc, */ \
85 0, 0, \
86}
87#endif /* !(CONFIG_DEBUG_SPINLOCK) */
88
89#ifndef __ASSEMBLY__
90
91#include <linux/types.h>
92
93/* Return saved PC of a blocked thread. */
94struct task_struct;
95extern unsigned long thread_saved_pc(struct task_struct *);
96
97/* On Uniprocessor, even in RMO processes see TSO semantics */
98#ifdef CONFIG_SMP
99#define TSTATE_INITIAL_MM TSTATE_TSO
100#else
101#define TSTATE_INITIAL_MM TSTATE_RMO
102#endif
103
104/* Do necessary setup to start up a newly executed thread. */
105#define start_thread(regs, pc, sp) \
106do { \
107 unsigned long __asi = ASI_PNF; \
108 regs->tstate = (regs->tstate & (TSTATE_CWP)) | (TSTATE_INITIAL_MM|TSTATE_IE) | (__asi << 24UL); \
109 regs->tpc = ((pc & (~3)) - 4); \
110 regs->tnpc = regs->tpc + 4; \
111 regs->y = 0; \
112 set_thread_wstate(1 << 3); \
113 if (current_thread_info()->utraps) { \
114 if (*(current_thread_info()->utraps) < 2) \
115 kfree(current_thread_info()->utraps); \
116 else \
117 (*(current_thread_info()->utraps))--; \
118 current_thread_info()->utraps = NULL; \
119 } \
120 __asm__ __volatile__( \
121 "stx %%g0, [%0 + %2 + 0x00]\n\t" \
122 "stx %%g0, [%0 + %2 + 0x08]\n\t" \
123 "stx %%g0, [%0 + %2 + 0x10]\n\t" \
124 "stx %%g0, [%0 + %2 + 0x18]\n\t" \
125 "stx %%g0, [%0 + %2 + 0x20]\n\t" \
126 "stx %%g0, [%0 + %2 + 0x28]\n\t" \
127 "stx %%g0, [%0 + %2 + 0x30]\n\t" \
128 "stx %%g0, [%0 + %2 + 0x38]\n\t" \
129 "stx %%g0, [%0 + %2 + 0x40]\n\t" \
130 "stx %%g0, [%0 + %2 + 0x48]\n\t" \
131 "stx %%g0, [%0 + %2 + 0x50]\n\t" \
132 "stx %%g0, [%0 + %2 + 0x58]\n\t" \
133 "stx %%g0, [%0 + %2 + 0x60]\n\t" \
134 "stx %%g0, [%0 + %2 + 0x68]\n\t" \
135 "stx %1, [%0 + %2 + 0x70]\n\t" \
136 "stx %%g0, [%0 + %2 + 0x78]\n\t" \
137 "wrpr %%g0, (1 << 3), %%wstate\n\t" \
138 : \
139 : "r" (regs), "r" (sp - sizeof(struct reg_window) - STACK_BIAS), \
140 "i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))); \
141} while (0)
142
143#define start_thread32(regs, pc, sp) \
144do { \
145 unsigned long __asi = ASI_PNF; \
146 pc &= 0x00000000ffffffffUL; \
147 sp &= 0x00000000ffffffffUL; \
148 regs->tstate = (regs->tstate & (TSTATE_CWP))|(TSTATE_INITIAL_MM|TSTATE_IE|TSTATE_AM) | (__asi << 24UL); \
149 regs->tpc = ((pc & (~3)) - 4); \
150 regs->tnpc = regs->tpc + 4; \
151 regs->y = 0; \
152 set_thread_wstate(2 << 3); \
153 if (current_thread_info()->utraps) { \
154 if (*(current_thread_info()->utraps) < 2) \
155 kfree(current_thread_info()->utraps); \
156 else \
157 (*(current_thread_info()->utraps))--; \
158 current_thread_info()->utraps = NULL; \
159 } \
160 __asm__ __volatile__( \
161 "stx %%g0, [%0 + %2 + 0x00]\n\t" \
162 "stx %%g0, [%0 + %2 + 0x08]\n\t" \
163 "stx %%g0, [%0 + %2 + 0x10]\n\t" \
164 "stx %%g0, [%0 + %2 + 0x18]\n\t" \
165 "stx %%g0, [%0 + %2 + 0x20]\n\t" \
166 "stx %%g0, [%0 + %2 + 0x28]\n\t" \
167 "stx %%g0, [%0 + %2 + 0x30]\n\t" \
168 "stx %%g0, [%0 + %2 + 0x38]\n\t" \
169 "stx %%g0, [%0 + %2 + 0x40]\n\t" \
170 "stx %%g0, [%0 + %2 + 0x48]\n\t" \
171 "stx %%g0, [%0 + %2 + 0x50]\n\t" \
172 "stx %%g0, [%0 + %2 + 0x58]\n\t" \
173 "stx %%g0, [%0 + %2 + 0x60]\n\t" \
174 "stx %%g0, [%0 + %2 + 0x68]\n\t" \
175 "stx %1, [%0 + %2 + 0x70]\n\t" \
176 "stx %%g0, [%0 + %2 + 0x78]\n\t" \
177 "wrpr %%g0, (2 << 3), %%wstate\n\t" \
178 : \
179 : "r" (regs), "r" (sp - sizeof(struct reg_window32)), \
180 "i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))); \
181} while (0)
182
183/* Free all resources held by a thread. */
184#define release_thread(tsk) do { } while (0)
185
186/* Prepare to copy thread state - unlazy all lazy status */
187#define prepare_to_copy(tsk) do { } while (0)
188
189extern pid_t kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
190
191extern unsigned long get_wchan(struct task_struct *task);
192
193#define task_pt_regs(tsk) (task_thread_info(tsk)->kregs)
194#define KSTK_EIP(tsk) (task_pt_regs(tsk)->tpc)
195#define KSTK_ESP(tsk) (task_pt_regs(tsk)->u_regs[UREG_FP])
196
197#define cpu_relax() barrier()
198
199/* Prefetch support. This is tuned for UltraSPARC-III and later.
200 * UltraSPARC-I will treat these as nops, and UltraSPARC-II has
201 * a shallower prefetch queue than later chips.
202 */
203#define ARCH_HAS_PREFETCH
204#define ARCH_HAS_PREFETCHW
205#define ARCH_HAS_SPINLOCK_PREFETCH
206
207static inline void prefetch(const void *x)
208{
209 /* We do not use the read prefetch mnemonic because that
210 * prefetches into the prefetch-cache which only is accessible
211 * by floating point operations in UltraSPARC-III and later.
212 * By contrast, "#one_write" prefetches into the L2 cache
213 * in shared state.
214 */
215 __asm__ __volatile__("prefetch [%0], #one_write"
216 : /* no outputs */
217 : "r" (x));
218}
219
220static inline void prefetchw(const void *x)
221{
222 /* The most optimal prefetch to use for writes is
223 * "#n_writes". This brings the cacheline into the
224 * L2 cache in "owned" state.
225 */
226 __asm__ __volatile__("prefetch [%0], #n_writes"
227 : /* no outputs */
228 : "r" (x));
229}
230
231#define spin_lock_prefetch(x) prefetchw(x)
232
233#define HAVE_ARCH_PICK_MMAP_LAYOUT
234
235#endif /* !(__ASSEMBLY__) */
236
237#endif /* !(__ASM_SPARC64_PROCESSOR_H) */
diff --git a/include/asm-sparc/prom.h b/include/asm-sparc/prom.h
deleted file mode 100644
index fd55522481c..00000000000
--- a/include/asm-sparc/prom.h
+++ /dev/null
@@ -1,108 +0,0 @@
1#ifndef _SPARC_PROM_H
2#define _SPARC_PROM_H
3#ifdef __KERNEL__
4
5/*
6 * Definitions for talking to the Open Firmware PROM on
7 * Power Macintosh computers.
8 *
9 * Copyright (C) 1996-2005 Paul Mackerras.
10 *
11 * Updates for PPC64 by Peter Bergner & David Engebretsen, IBM Corp.
12 * Updates for SPARC by David S. Miller
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
18 */
19#include <linux/types.h>
20#include <linux/proc_fs.h>
21#include <asm/atomic.h>
22
23#define OF_ROOT_NODE_ADDR_CELLS_DEFAULT 2
24#define OF_ROOT_NODE_SIZE_CELLS_DEFAULT 1
25
26#define of_compat_cmp(s1, s2, l) strncmp((s1), (s2), (l))
27#define of_prop_cmp(s1, s2) strcasecmp((s1), (s2))
28#define of_node_cmp(s1, s2) strcmp((s1), (s2))
29
30typedef u32 phandle;
31typedef u32 ihandle;
32
33struct property {
34 char *name;
35 int length;
36 void *value;
37 struct property *next;
38 unsigned long _flags;
39 unsigned int unique_id;
40};
41
42struct of_irq_controller;
43struct device_node {
44 const char *name;
45 const char *type;
46 phandle node;
47 char *path_component_name;
48 char *full_name;
49
50 struct property *properties;
51 struct property *deadprops; /* removed properties */
52 struct device_node *parent;
53 struct device_node *child;
54 struct device_node *sibling;
55 struct device_node *next; /* next device of same type */
56 struct device_node *allnext; /* next in list of all nodes */
57 struct proc_dir_entry *pde; /* this node's proc directory */
58 struct kref kref;
59 unsigned long _flags;
60 void *data;
61 unsigned int unique_id;
62
63 struct of_irq_controller *irq_trans;
64};
65
66struct of_irq_controller {
67 unsigned int (*irq_build)(struct device_node *, unsigned int, void *);
68 void *data;
69};
70
71#define OF_IS_DYNAMIC(x) test_bit(OF_DYNAMIC, &x->_flags)
72#define OF_MARK_DYNAMIC(x) set_bit(OF_DYNAMIC, &x->_flags)
73
74extern struct device_node *of_find_node_by_cpuid(int cpuid);
75extern int of_set_property(struct device_node *node, const char *name, void *val, int len);
76extern int of_getintprop_default(struct device_node *np,
77 const char *name,
78 int def);
79extern int of_find_in_proplist(const char *list, const char *match, int len);
80#ifdef CONFIG_NUMA
81extern int of_node_to_nid(struct device_node *dp);
82#else
83#define of_node_to_nid(dp) (-1)
84#endif
85
86extern void prom_build_devicetree(void);
87
88/* Dummy ref counting routines - to be implemented later */
89static inline struct device_node *of_node_get(struct device_node *node)
90{
91 return node;
92}
93static inline void of_node_put(struct device_node *node)
94{
95}
96
97/*
98 * NB: This is here while we transition from using asm/prom.h
99 * to linux/of.h
100 */
101#include <linux/of.h>
102
103extern struct device_node *of_console_device;
104extern char *of_console_path;
105extern char *of_console_options;
106
107#endif /* __KERNEL__ */
108#endif /* _SPARC_PROM_H */
diff --git a/include/asm-sparc/psr.h b/include/asm-sparc/psr.h
deleted file mode 100644
index b8c0e5f0a66..00000000000
--- a/include/asm-sparc/psr.h
+++ /dev/null
@@ -1,93 +0,0 @@
1/*
2 * psr.h: This file holds the macros for masking off various parts of
3 * the processor status register on the Sparc. This is valid
4 * for Version 8. On the V9 this is renamed to the PSTATE
5 * register and its members are accessed as fields like
6 * PSTATE.PRIV for the current CPU privilege level.
7 *
8 * Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu)
9 */
10
11#ifndef __LINUX_SPARC_PSR_H
12#define __LINUX_SPARC_PSR_H
13
14/* The Sparc PSR fields are laid out as the following:
15 *
16 * ------------------------------------------------------------------------
17 * | impl | vers | icc | resv | EC | EF | PIL | S | PS | ET | CWP |
18 * | 31-28 | 27-24 | 23-20 | 19-14 | 13 | 12 | 11-8 | 7 | 6 | 5 | 4-0 |
19 * ------------------------------------------------------------------------
20 */
21#define PSR_CWP 0x0000001f /* current window pointer */
22#define PSR_ET 0x00000020 /* enable traps field */
23#define PSR_PS 0x00000040 /* previous privilege level */
24#define PSR_S 0x00000080 /* current privilege level */
25#define PSR_PIL 0x00000f00 /* processor interrupt level */
26#define PSR_EF 0x00001000 /* enable floating point */
27#define PSR_EC 0x00002000 /* enable co-processor */
28#define PSR_SYSCALL 0x00004000 /* inside of a syscall */
29#define PSR_LE 0x00008000 /* SuperSparcII little-endian */
30#define PSR_ICC 0x00f00000 /* integer condition codes */
31#define PSR_C 0x00100000 /* carry bit */
32#define PSR_V 0x00200000 /* overflow bit */
33#define PSR_Z 0x00400000 /* zero bit */
34#define PSR_N 0x00800000 /* negative bit */
35#define PSR_VERS 0x0f000000 /* cpu-version field */
36#define PSR_IMPL 0xf0000000 /* cpu-implementation field */
37
38#ifdef __KERNEL__
39
40#ifndef __ASSEMBLY__
41/* Get the %psr register. */
42static inline unsigned int get_psr(void)
43{
44 unsigned int psr;
45 __asm__ __volatile__(
46 "rd %%psr, %0\n\t"
47 "nop\n\t"
48 "nop\n\t"
49 "nop\n\t"
50 : "=r" (psr)
51 : /* no inputs */
52 : "memory");
53
54 return psr;
55}
56
57static inline void put_psr(unsigned int new_psr)
58{
59 __asm__ __volatile__(
60 "wr %0, 0x0, %%psr\n\t"
61 "nop\n\t"
62 "nop\n\t"
63 "nop\n\t"
64 : /* no outputs */
65 : "r" (new_psr)
66 : "memory", "cc");
67}
68
69/* Get the %fsr register. Be careful, make sure the floating point
70 * enable bit is set in the %psr when you execute this or you will
71 * incur a trap.
72 */
73
74extern unsigned int fsr_storage;
75
76static inline unsigned int get_fsr(void)
77{
78 unsigned int fsr = 0;
79
80 __asm__ __volatile__(
81 "st %%fsr, %1\n\t"
82 "ld %1, %0\n\t"
83 : "=r" (fsr)
84 : "m" (fsr_storage));
85
86 return fsr;
87}
88
89#endif /* !(__ASSEMBLY__) */
90
91#endif /* (__KERNEL__) */
92
93#endif /* !(__LINUX_SPARC_PSR_H) */
diff --git a/include/asm-sparc/psrcompat.h b/include/asm-sparc/psrcompat.h
deleted file mode 100644
index 44b6327dbbf..00000000000
--- a/include/asm-sparc/psrcompat.h
+++ /dev/null
@@ -1,45 +0,0 @@
1#ifndef _SPARC64_PSRCOMPAT_H
2#define _SPARC64_PSRCOMPAT_H
3
4#include <asm/pstate.h>
5
6/* Old 32-bit PSR fields for the compatibility conversion code. */
7#define PSR_CWP 0x0000001f /* current window pointer */
8#define PSR_ET 0x00000020 /* enable traps field */
9#define PSR_PS 0x00000040 /* previous privilege level */
10#define PSR_S 0x00000080 /* current privilege level */
11#define PSR_PIL 0x00000f00 /* processor interrupt level */
12#define PSR_EF 0x00001000 /* enable floating point */
13#define PSR_EC 0x00002000 /* enable co-processor */
14#define PSR_SYSCALL 0x00004000 /* inside of a syscall */
15#define PSR_LE 0x00008000 /* SuperSparcII little-endian */
16#define PSR_ICC 0x00f00000 /* integer condition codes */
17#define PSR_C 0x00100000 /* carry bit */
18#define PSR_V 0x00200000 /* overflow bit */
19#define PSR_Z 0x00400000 /* zero bit */
20#define PSR_N 0x00800000 /* negative bit */
21#define PSR_VERS 0x0f000000 /* cpu-version field */
22#define PSR_IMPL 0xf0000000 /* cpu-implementation field */
23
24#define PSR_V8PLUS 0xff000000 /* fake impl/ver, meaning a 64bit CPU is present */
25#define PSR_XCC 0x000f0000 /* if PSR_V8PLUS, this is %xcc */
26
27static inline unsigned int tstate_to_psr(unsigned long tstate)
28{
29 return ((tstate & TSTATE_CWP) |
30 PSR_S |
31 ((tstate & TSTATE_ICC) >> 12) |
32 ((tstate & TSTATE_XCC) >> 20) |
33 ((tstate & TSTATE_SYSCALL) ? PSR_SYSCALL : 0) |
34 PSR_V8PLUS);
35}
36
37static inline unsigned long psr_to_tstate_icc(unsigned int psr)
38{
39 unsigned long tstate = ((unsigned long)(psr & PSR_ICC)) << 12;
40 if ((psr & (PSR_VERS|PSR_IMPL)) == PSR_V8PLUS)
41 tstate |= ((unsigned long)(psr & PSR_XCC)) << 20;
42 return tstate;
43}
44
45#endif /* !(_SPARC64_PSRCOMPAT_H) */
diff --git a/include/asm-sparc/pstate.h b/include/asm-sparc/pstate.h
deleted file mode 100644
index a26a53777bb..00000000000
--- a/include/asm-sparc/pstate.h
+++ /dev/null
@@ -1,91 +0,0 @@
1#ifndef _SPARC64_PSTATE_H
2#define _SPARC64_PSTATE_H
3
4#include <linux/const.h>
5
6/* The V9 PSTATE Register (with SpitFire extensions).
7 *
8 * -----------------------------------------------------------------------
9 * | Resv | IG | MG | CLE | TLE | MM | RED | PEF | AM | PRIV | IE | AG |
10 * -----------------------------------------------------------------------
11 * 63 12 11 10 9 8 7 6 5 4 3 2 1 0
12 */
13#define PSTATE_IG _AC(0x0000000000000800,UL) /* Interrupt Globals. */
14#define PSTATE_MG _AC(0x0000000000000400,UL) /* MMU Globals. */
15#define PSTATE_CLE _AC(0x0000000000000200,UL) /* Current Little Endian.*/
16#define PSTATE_TLE _AC(0x0000000000000100,UL) /* Trap Little Endian. */
17#define PSTATE_MM _AC(0x00000000000000c0,UL) /* Memory Model. */
18#define PSTATE_TSO _AC(0x0000000000000000,UL) /* MM: TotalStoreOrder */
19#define PSTATE_PSO _AC(0x0000000000000040,UL) /* MM: PartialStoreOrder */
20#define PSTATE_RMO _AC(0x0000000000000080,UL) /* MM: RelaxedMemoryOrder*/
21#define PSTATE_RED _AC(0x0000000000000020,UL) /* Reset Error Debug. */
22#define PSTATE_PEF _AC(0x0000000000000010,UL) /* Floating Point Enable.*/
23#define PSTATE_AM _AC(0x0000000000000008,UL) /* Address Mask. */
24#define PSTATE_PRIV _AC(0x0000000000000004,UL) /* Privilege. */
25#define PSTATE_IE _AC(0x0000000000000002,UL) /* Interrupt Enable. */
26#define PSTATE_AG _AC(0x0000000000000001,UL) /* Alternate Globals. */
27
28/* The V9 TSTATE Register (with SpitFire and Linux extensions).
29 *
30 * ---------------------------------------------------------------------
31 * | Resv | GL | CCR | ASI | %pil | PSTATE | Resv | CWP |
32 * ---------------------------------------------------------------------
33 * 63 43 42 40 39 32 31 24 23 20 19 8 7 5 4 0
34 */
35#define TSTATE_GL _AC(0x0000070000000000,UL) /* Global reg level */
36#define TSTATE_CCR _AC(0x000000ff00000000,UL) /* Condition Codes. */
37#define TSTATE_XCC _AC(0x000000f000000000,UL) /* Condition Codes. */
38#define TSTATE_XNEG _AC(0x0000008000000000,UL) /* %xcc Negative. */
39#define TSTATE_XZERO _AC(0x0000004000000000,UL) /* %xcc Zero. */
40#define TSTATE_XOVFL _AC(0x0000002000000000,UL) /* %xcc Overflow. */
41#define TSTATE_XCARRY _AC(0x0000001000000000,UL) /* %xcc Carry. */
42#define TSTATE_ICC _AC(0x0000000f00000000,UL) /* Condition Codes. */
43#define TSTATE_INEG _AC(0x0000000800000000,UL) /* %icc Negative. */
44#define TSTATE_IZERO _AC(0x0000000400000000,UL) /* %icc Zero. */
45#define TSTATE_IOVFL _AC(0x0000000200000000,UL) /* %icc Overflow. */
46#define TSTATE_ICARRY _AC(0x0000000100000000,UL) /* %icc Carry. */
47#define TSTATE_ASI _AC(0x00000000ff000000,UL) /* AddrSpace ID. */
48#define TSTATE_PIL _AC(0x0000000000f00000,UL) /* %pil (Linux traps)*/
49#define TSTATE_PSTATE _AC(0x00000000000fff00,UL) /* PSTATE. */
50#define TSTATE_IG _AC(0x0000000000080000,UL) /* Interrupt Globals.*/
51#define TSTATE_MG _AC(0x0000000000040000,UL) /* MMU Globals. */
52#define TSTATE_CLE _AC(0x0000000000020000,UL) /* CurrLittleEndian. */
53#define TSTATE_TLE _AC(0x0000000000010000,UL) /* TrapLittleEndian. */
54#define TSTATE_MM _AC(0x000000000000c000,UL) /* Memory Model. */
55#define TSTATE_TSO _AC(0x0000000000000000,UL) /* MM: TSO */
56#define TSTATE_PSO _AC(0x0000000000004000,UL) /* MM: PSO */
57#define TSTATE_RMO _AC(0x0000000000008000,UL) /* MM: RMO */
58#define TSTATE_RED _AC(0x0000000000002000,UL) /* Reset Error Debug.*/
59#define TSTATE_PEF _AC(0x0000000000001000,UL) /* FPU Enable. */
60#define TSTATE_AM _AC(0x0000000000000800,UL) /* Address Mask. */
61#define TSTATE_PRIV _AC(0x0000000000000400,UL) /* Privilege. */
62#define TSTATE_IE _AC(0x0000000000000200,UL) /* Interrupt Enable. */
63#define TSTATE_AG _AC(0x0000000000000100,UL) /* Alternate Globals.*/
64#define TSTATE_SYSCALL _AC(0x0000000000000020,UL) /* in syscall trap */
65#define TSTATE_CWP _AC(0x000000000000001f,UL) /* Curr Win-Pointer. */
66
67/* Floating-Point Registers State Register.
68 *
69 * --------------------------------
70 * | Resv | FEF | DU | DL |
71 * --------------------------------
72 * 63 3 2 1 0
73 */
74#define FPRS_FEF _AC(0x0000000000000004,UL) /* FPU Enable. */
75#define FPRS_DU _AC(0x0000000000000002,UL) /* Dirty Upper. */
76#define FPRS_DL _AC(0x0000000000000001,UL) /* Dirty Lower. */
77
78/* Version Register.
79 *
80 * ------------------------------------------------------
81 * | MANUF | IMPL | MASK | Resv | MAXTL | Resv | MAXWIN |
82 * ------------------------------------------------------
83 * 63 48 47 32 31 24 23 16 15 8 7 5 4 0
84 */
85#define VERS_MANUF _AC(0xffff000000000000,UL) /* Manufacturer. */
86#define VERS_IMPL _AC(0x0000ffff00000000,UL) /* Implementation. */
87#define VERS_MASK _AC(0x00000000ff000000,UL) /* Mask Set Revision.*/
88#define VERS_MAXTL _AC(0x000000000000ff00,UL) /* Max Trap Level. */
89#define VERS_MAXWIN _AC(0x000000000000001f,UL) /* Max RegWindow Idx.*/
90
91#endif /* !(_SPARC64_PSTATE_H) */
diff --git a/include/asm-sparc/ptrace.h b/include/asm-sparc/ptrace.h
deleted file mode 100644
index f36ab6c30ff..00000000000
--- a/include/asm-sparc/ptrace.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_PTRACE_H
2#define ___ASM_SPARC_PTRACE_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/ptrace_64.h>
5#else
6#include <asm-sparc/ptrace_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/ptrace_32.h b/include/asm-sparc/ptrace_32.h
deleted file mode 100644
index 0401cc7ec38..00000000000
--- a/include/asm-sparc/ptrace_32.h
+++ /dev/null
@@ -1,175 +0,0 @@
1#ifndef _SPARC_PTRACE_H
2#define _SPARC_PTRACE_H
3
4#include <asm/psr.h>
5
6/* This struct defines the way the registers are stored on the
7 * stack during a system call and basically all traps.
8 */
9
10#ifndef __ASSEMBLY__
11
12#include <linux/types.h>
13
14struct pt_regs {
15 unsigned long psr;
16 unsigned long pc;
17 unsigned long npc;
18 unsigned long y;
19 unsigned long u_regs[16]; /* globals and ins */
20};
21
22#define UREG_G0 0
23#define UREG_G1 1
24#define UREG_G2 2
25#define UREG_G3 3
26#define UREG_G4 4
27#define UREG_G5 5
28#define UREG_G6 6
29#define UREG_G7 7
30#define UREG_I0 8
31#define UREG_I1 9
32#define UREG_I2 10
33#define UREG_I3 11
34#define UREG_I4 12
35#define UREG_I5 13
36#define UREG_I6 14
37#define UREG_I7 15
38#define UREG_WIM UREG_G0
39#define UREG_FADDR UREG_G0
40#define UREG_FP UREG_I6
41#define UREG_RETPC UREG_I7
42
43static inline bool pt_regs_is_syscall(struct pt_regs *regs)
44{
45 return (regs->psr & PSR_SYSCALL);
46}
47
48static inline bool pt_regs_clear_syscall(struct pt_regs *regs)
49{
50 return (regs->psr &= ~PSR_SYSCALL);
51}
52
53/* A register window */
54struct reg_window {
55 unsigned long locals[8];
56 unsigned long ins[8];
57};
58
59/* A Sparc stack frame */
60struct sparc_stackf {
61 unsigned long locals[8];
62 unsigned long ins[6];
63 struct sparc_stackf *fp;
64 unsigned long callers_pc;
65 char *structptr;
66 unsigned long xargs[6];
67 unsigned long xxargs[1];
68};
69
70#define TRACEREG_SZ sizeof(struct pt_regs)
71#define STACKFRAME_SZ sizeof(struct sparc_stackf)
72
73#ifdef __KERNEL__
74
75#define user_mode(regs) (!((regs)->psr & PSR_PS))
76#define instruction_pointer(regs) ((regs)->pc)
77unsigned long profile_pc(struct pt_regs *);
78extern void show_regs(struct pt_regs *);
79#endif
80
81#else /* __ASSEMBLY__ */
82/* For assembly code. */
83#define TRACEREG_SZ 0x50
84#define STACKFRAME_SZ 0x60
85#endif
86
87/*
88 * The asm-offsets.h is a generated file, so we cannot include it.
89 * It may be OK for glibc headers, but it's utterly pointless for C code.
90 * The assembly code using those offsets has to include it explicitly.
91 */
92/* #include <asm/asm-offsets.h> */
93
94/* These are for pt_regs. */
95#define PT_PSR 0x0
96#define PT_PC 0x4
97#define PT_NPC 0x8
98#define PT_Y 0xc
99#define PT_G0 0x10
100#define PT_WIM PT_G0
101#define PT_G1 0x14
102#define PT_G2 0x18
103#define PT_G3 0x1c
104#define PT_G4 0x20
105#define PT_G5 0x24
106#define PT_G6 0x28
107#define PT_G7 0x2c
108#define PT_I0 0x30
109#define PT_I1 0x34
110#define PT_I2 0x38
111#define PT_I3 0x3c
112#define PT_I4 0x40
113#define PT_I5 0x44
114#define PT_I6 0x48
115#define PT_FP PT_I6
116#define PT_I7 0x4c
117
118/* Reg_window offsets */
119#define RW_L0 0x00
120#define RW_L1 0x04
121#define RW_L2 0x08
122#define RW_L3 0x0c
123#define RW_L4 0x10
124#define RW_L5 0x14
125#define RW_L6 0x18
126#define RW_L7 0x1c
127#define RW_I0 0x20
128#define RW_I1 0x24
129#define RW_I2 0x28
130#define RW_I3 0x2c
131#define RW_I4 0x30
132#define RW_I5 0x34
133#define RW_I6 0x38
134#define RW_I7 0x3c
135
136/* Stack_frame offsets */
137#define SF_L0 0x00
138#define SF_L1 0x04
139#define SF_L2 0x08
140#define SF_L3 0x0c
141#define SF_L4 0x10
142#define SF_L5 0x14
143#define SF_L6 0x18
144#define SF_L7 0x1c
145#define SF_I0 0x20
146#define SF_I1 0x24
147#define SF_I2 0x28
148#define SF_I3 0x2c
149#define SF_I4 0x30
150#define SF_I5 0x34
151#define SF_FP 0x38
152#define SF_PC 0x3c
153#define SF_RETP 0x40
154#define SF_XARG0 0x44
155#define SF_XARG1 0x48
156#define SF_XARG2 0x4c
157#define SF_XARG3 0x50
158#define SF_XARG4 0x54
159#define SF_XARG5 0x58
160#define SF_XXARG 0x5c
161
162/* Stuff for the ptrace system call */
163#define PTRACE_SPARC_DETACH 11
164#define PTRACE_GETREGS 12
165#define PTRACE_SETREGS 13
166#define PTRACE_GETFPREGS 14
167#define PTRACE_SETFPREGS 15
168#define PTRACE_READDATA 16
169#define PTRACE_WRITEDATA 17
170#define PTRACE_READTEXT 18
171#define PTRACE_WRITETEXT 19
172#define PTRACE_GETFPAREGS 20
173#define PTRACE_SETFPAREGS 21
174
175#endif /* !(_SPARC_PTRACE_H) */
diff --git a/include/asm-sparc/ptrace_64.h b/include/asm-sparc/ptrace_64.h
deleted file mode 100644
index a682e66d5c4..00000000000
--- a/include/asm-sparc/ptrace_64.h
+++ /dev/null
@@ -1,346 +0,0 @@
1#ifndef _SPARC64_PTRACE_H
2#define _SPARC64_PTRACE_H
3
4#include <asm/pstate.h>
5
6/* This struct defines the way the registers are stored on the
7 * stack during a system call and basically all traps.
8 */
9
10/* This magic value must have the low 9 bits clear,
11 * as that is where we encode the %tt value, see below.
12 */
13#define PT_REGS_MAGIC 0x57ac6c00
14
15#ifndef __ASSEMBLY__
16
17#include <linux/types.h>
18
19struct pt_regs {
20 unsigned long u_regs[16]; /* globals and ins */
21 unsigned long tstate;
22 unsigned long tpc;
23 unsigned long tnpc;
24 unsigned int y;
25
26 /* We encode a magic number, PT_REGS_MAGIC, along
27 * with the %tt (trap type) register value at trap
28 * entry time. The magic number allows us to identify
29 * accurately a trap stack frame in the stack
30 * unwinder, and the %tt value allows us to test
31 * things like "in a system call" etc. for an arbitray
32 * process.
33 *
34 * The PT_REGS_MAGIC is choosen such that it can be
35 * loaded completely using just a sethi instruction.
36 */
37 unsigned int magic;
38};
39
40static inline int pt_regs_trap_type(struct pt_regs *regs)
41{
42 return regs->magic & 0x1ff;
43}
44
45static inline bool pt_regs_is_syscall(struct pt_regs *regs)
46{
47 return (regs->tstate & TSTATE_SYSCALL);
48}
49
50static inline bool pt_regs_clear_syscall(struct pt_regs *regs)
51{
52 return (regs->tstate &= ~TSTATE_SYSCALL);
53}
54
55struct pt_regs32 {
56 unsigned int psr;
57 unsigned int pc;
58 unsigned int npc;
59 unsigned int y;
60 unsigned int u_regs[16]; /* globals and ins */
61};
62
63#define UREG_G0 0
64#define UREG_G1 1
65#define UREG_G2 2
66#define UREG_G3 3
67#define UREG_G4 4
68#define UREG_G5 5
69#define UREG_G6 6
70#define UREG_G7 7
71#define UREG_I0 8
72#define UREG_I1 9
73#define UREG_I2 10
74#define UREG_I3 11
75#define UREG_I4 12
76#define UREG_I5 13
77#define UREG_I6 14
78#define UREG_I7 15
79#define UREG_FP UREG_I6
80#define UREG_RETPC UREG_I7
81
82/* A V9 register window */
83struct reg_window {
84 unsigned long locals[8];
85 unsigned long ins[8];
86};
87
88/* A 32-bit register window. */
89struct reg_window32 {
90 unsigned int locals[8];
91 unsigned int ins[8];
92};
93
94/* A V9 Sparc stack frame */
95struct sparc_stackf {
96 unsigned long locals[8];
97 unsigned long ins[6];
98 struct sparc_stackf *fp;
99 unsigned long callers_pc;
100 char *structptr;
101 unsigned long xargs[6];
102 unsigned long xxargs[1];
103};
104
105/* A 32-bit Sparc stack frame */
106struct sparc_stackf32 {
107 unsigned int locals[8];
108 unsigned int ins[6];
109 unsigned int fp;
110 unsigned int callers_pc;
111 unsigned int structptr;
112 unsigned int xargs[6];
113 unsigned int xxargs[1];
114};
115
116struct sparc_trapf {
117 unsigned long locals[8];
118 unsigned long ins[8];
119 unsigned long _unused;
120 struct pt_regs *regs;
121};
122
123#define TRACEREG_SZ sizeof(struct pt_regs)
124#define STACKFRAME_SZ sizeof(struct sparc_stackf)
125
126#define TRACEREG32_SZ sizeof(struct pt_regs32)
127#define STACKFRAME32_SZ sizeof(struct sparc_stackf32)
128
129#ifdef __KERNEL__
130
131struct global_reg_snapshot {
132 unsigned long tstate;
133 unsigned long tpc;
134 unsigned long tnpc;
135 unsigned long o7;
136 unsigned long i7;
137 struct thread_info *thread;
138 unsigned long pad1;
139 unsigned long pad2;
140};
141
142#define __ARCH_WANT_COMPAT_SYS_PTRACE
143
144#define force_successful_syscall_return() \
145do { current_thread_info()->syscall_noerror = 1; \
146} while (0)
147#define user_mode(regs) (!((regs)->tstate & TSTATE_PRIV))
148#define instruction_pointer(regs) ((regs)->tpc)
149#define regs_return_value(regs) ((regs)->u_regs[UREG_I0])
150#ifdef CONFIG_SMP
151extern unsigned long profile_pc(struct pt_regs *);
152#else
153#define profile_pc(regs) instruction_pointer(regs)
154#endif
155extern void show_regs(struct pt_regs *);
156extern void __show_regs(struct pt_regs *);
157#endif
158
159#else /* __ASSEMBLY__ */
160/* For assembly code. */
161#define TRACEREG_SZ 0xa0
162#define STACKFRAME_SZ 0xc0
163
164#define TRACEREG32_SZ 0x50
165#define STACKFRAME32_SZ 0x60
166#endif
167
168#ifdef __KERNEL__
169#define STACK_BIAS 2047
170#endif
171
172/* These are for pt_regs. */
173#define PT_V9_G0 0x00
174#define PT_V9_G1 0x08
175#define PT_V9_G2 0x10
176#define PT_V9_G3 0x18
177#define PT_V9_G4 0x20
178#define PT_V9_G5 0x28
179#define PT_V9_G6 0x30
180#define PT_V9_G7 0x38
181#define PT_V9_I0 0x40
182#define PT_V9_I1 0x48
183#define PT_V9_I2 0x50
184#define PT_V9_I3 0x58
185#define PT_V9_I4 0x60
186#define PT_V9_I5 0x68
187#define PT_V9_I6 0x70
188#define PT_V9_FP PT_V9_I6
189#define PT_V9_I7 0x78
190#define PT_V9_TSTATE 0x80
191#define PT_V9_TPC 0x88
192#define PT_V9_TNPC 0x90
193#define PT_V9_Y 0x98
194#define PT_V9_MAGIC 0x9c
195#define PT_TSTATE PT_V9_TSTATE
196#define PT_TPC PT_V9_TPC
197#define PT_TNPC PT_V9_TNPC
198
199/* These for pt_regs32. */
200#define PT_PSR 0x0
201#define PT_PC 0x4
202#define PT_NPC 0x8
203#define PT_Y 0xc
204#define PT_G0 0x10
205#define PT_WIM PT_G0
206#define PT_G1 0x14
207#define PT_G2 0x18
208#define PT_G3 0x1c
209#define PT_G4 0x20
210#define PT_G5 0x24
211#define PT_G6 0x28
212#define PT_G7 0x2c
213#define PT_I0 0x30
214#define PT_I1 0x34
215#define PT_I2 0x38
216#define PT_I3 0x3c
217#define PT_I4 0x40
218#define PT_I5 0x44
219#define PT_I6 0x48
220#define PT_FP PT_I6
221#define PT_I7 0x4c
222
223/* Reg_window offsets */
224#define RW_V9_L0 0x00
225#define RW_V9_L1 0x08
226#define RW_V9_L2 0x10
227#define RW_V9_L3 0x18
228#define RW_V9_L4 0x20
229#define RW_V9_L5 0x28
230#define RW_V9_L6 0x30
231#define RW_V9_L7 0x38
232#define RW_V9_I0 0x40
233#define RW_V9_I1 0x48
234#define RW_V9_I2 0x50
235#define RW_V9_I3 0x58
236#define RW_V9_I4 0x60
237#define RW_V9_I5 0x68
238#define RW_V9_I6 0x70
239#define RW_V9_I7 0x78
240
241#define RW_L0 0x00
242#define RW_L1 0x04
243#define RW_L2 0x08
244#define RW_L3 0x0c
245#define RW_L4 0x10
246#define RW_L5 0x14
247#define RW_L6 0x18
248#define RW_L7 0x1c
249#define RW_I0 0x20
250#define RW_I1 0x24
251#define RW_I2 0x28
252#define RW_I3 0x2c
253#define RW_I4 0x30
254#define RW_I5 0x34
255#define RW_I6 0x38
256#define RW_I7 0x3c
257
258/* Stack_frame offsets */
259#define SF_V9_L0 0x00
260#define SF_V9_L1 0x08
261#define SF_V9_L2 0x10
262#define SF_V9_L3 0x18
263#define SF_V9_L4 0x20
264#define SF_V9_L5 0x28
265#define SF_V9_L6 0x30
266#define SF_V9_L7 0x38
267#define SF_V9_I0 0x40
268#define SF_V9_I1 0x48
269#define SF_V9_I2 0x50
270#define SF_V9_I3 0x58
271#define SF_V9_I4 0x60
272#define SF_V9_I5 0x68
273#define SF_V9_FP 0x70
274#define SF_V9_PC 0x78
275#define SF_V9_RETP 0x80
276#define SF_V9_XARG0 0x88
277#define SF_V9_XARG1 0x90
278#define SF_V9_XARG2 0x98
279#define SF_V9_XARG3 0xa0
280#define SF_V9_XARG4 0xa8
281#define SF_V9_XARG5 0xb0
282#define SF_V9_XXARG 0xb8
283
284#define SF_L0 0x00
285#define SF_L1 0x04
286#define SF_L2 0x08
287#define SF_L3 0x0c
288#define SF_L4 0x10
289#define SF_L5 0x14
290#define SF_L6 0x18
291#define SF_L7 0x1c
292#define SF_I0 0x20
293#define SF_I1 0x24
294#define SF_I2 0x28
295#define SF_I3 0x2c
296#define SF_I4 0x30
297#define SF_I5 0x34
298#define SF_FP 0x38
299#define SF_PC 0x3c
300#define SF_RETP 0x40
301#define SF_XARG0 0x44
302#define SF_XARG1 0x48
303#define SF_XARG2 0x4c
304#define SF_XARG3 0x50
305#define SF_XARG4 0x54
306#define SF_XARG5 0x58
307#define SF_XXARG 0x5c
308
309#ifdef __KERNEL__
310
311/* global_reg_snapshot offsets */
312#define GR_SNAP_TSTATE 0x00
313#define GR_SNAP_TPC 0x08
314#define GR_SNAP_TNPC 0x10
315#define GR_SNAP_O7 0x18
316#define GR_SNAP_I7 0x20
317#define GR_SNAP_THREAD 0x28
318#define GR_SNAP_PAD1 0x30
319#define GR_SNAP_PAD2 0x38
320
321#endif /* __KERNEL__ */
322
323/* Stuff for the ptrace system call */
324#define PTRACE_SPARC_DETACH 11
325#define PTRACE_GETREGS 12
326#define PTRACE_SETREGS 13
327#define PTRACE_GETFPREGS 14
328#define PTRACE_SETFPREGS 15
329#define PTRACE_READDATA 16
330#define PTRACE_WRITEDATA 17
331#define PTRACE_READTEXT 18
332#define PTRACE_WRITETEXT 19
333#define PTRACE_GETFPAREGS 20
334#define PTRACE_SETFPAREGS 21
335
336/* There are for debugging 64-bit processes, either from a 32 or 64 bit
337 * parent. Thus their complements are for debugging 32-bit processes only.
338 */
339
340#define PTRACE_GETREGS64 22
341#define PTRACE_SETREGS64 23
342/* PTRACE_SYSCALL is 24 */
343#define PTRACE_GETFPREGS64 25
344#define PTRACE_SETFPREGS64 26
345
346#endif /* !(_SPARC64_PTRACE_H) */
diff --git a/include/asm-sparc/reboot.h b/include/asm-sparc/reboot.h
deleted file mode 100644
index 3f3f43f5be5..00000000000
--- a/include/asm-sparc/reboot.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _SPARC64_REBOOT_H
2#define _SPARC64_REBOOT_H
3
4extern void machine_alt_power_off(void);
5
6#endif /* _SPARC64_REBOOT_H */
diff --git a/include/asm-sparc/reg.h b/include/asm-sparc/reg.h
deleted file mode 100644
index cb34b0a49aa..00000000000
--- a/include/asm-sparc/reg.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_REG_H
2#define ___ASM_SPARC_REG_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/reg_64.h>
5#else
6#include <asm-sparc/reg_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/reg_32.h b/include/asm-sparc/reg_32.h
deleted file mode 100644
index 42fecfcd97e..00000000000
--- a/include/asm-sparc/reg_32.h
+++ /dev/null
@@ -1,79 +0,0 @@
1/*
2 * linux/include/asm-sparc/reg.h
3 * Layout of the registers as expected by gdb on the Sparc
4 * we should replace the user.h definitions with those in
5 * this file, we don't even use the other
6 * -miguel
7 *
8 * The names of the structures, constants and aliases in this file
9 * have the same names as the sunos ones, some programs rely on these
10 * names (gdb for example).
11 *
12 */
13
14#ifndef __SPARC_REG_H
15#define __SPARC_REG_H
16
17struct regs {
18 int r_psr;
19#define r_ps r_psr
20 int r_pc;
21 int r_npc;
22 int r_y;
23 int r_g1;
24 int r_g2;
25 int r_g3;
26 int r_g4;
27 int r_g5;
28 int r_g6;
29 int r_g7;
30 int r_o0;
31 int r_o1;
32 int r_o2;
33 int r_o3;
34 int r_o4;
35 int r_o5;
36 int r_o6;
37 int r_o7;
38};
39
40struct fpq {
41 unsigned long *addr;
42 unsigned long instr;
43};
44
45struct fq {
46 union {
47 double whole;
48 struct fpq fpq;
49 } FQu;
50};
51
52#define FPU_REGS_TYPE unsigned int
53#define FPU_FSR_TYPE unsigned
54
55struct fp_status {
56 union {
57 FPU_REGS_TYPE Fpu_regs[32];
58 double Fpu_dregs[16];
59 } fpu_fr;
60 FPU_FSR_TYPE Fpu_fsr;
61 unsigned Fpu_flags;
62 unsigned Fpu_extra;
63 unsigned Fpu_qcnt;
64 struct fq Fpu_q[16];
65};
66
67#define fpu_regs f_fpstatus.fpu_fr.Fpu_regs
68#define fpu_dregs f_fpstatus.fpu_fr.Fpu_dregs
69#define fpu_fsr f_fpstatus.Fpu_fsr
70#define fpu_flags f_fpstatus.Fpu_flags
71#define fpu_extra f_fpstatus.Fpu_extra
72#define fpu_q f_fpstatus.Fpu_q
73#define fpu_qcnt f_fpstatus.Fpu_qcnt
74
75struct fpu {
76 struct fp_status f_fpstatus;
77};
78
79#endif /* __SPARC_REG_H */
diff --git a/include/asm-sparc/reg_64.h b/include/asm-sparc/reg_64.h
deleted file mode 100644
index eb24a07ff4d..00000000000
--- a/include/asm-sparc/reg_64.h
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * linux/asm-sparc64/reg.h
3 * Layout of the registers as expected by gdb on the Sparc
4 * we should replace the user.h definitions with those in
5 * this file, we don't even use the other
6 * -miguel
7 *
8 * The names of the structures, constants and aliases in this file
9 * have the same names as the sunos ones, some programs rely on these
10 * names (gdb for example).
11 *
12 */
13
14#ifndef __SPARC64_REG_H
15#define __SPARC64_REG_H
16
17struct regs {
18 unsigned long r_g1;
19 unsigned long r_g2;
20 unsigned long r_g3;
21 unsigned long r_g4;
22 unsigned long r_g5;
23 unsigned long r_g6;
24 unsigned long r_g7;
25 unsigned long r_o0;
26 unsigned long r_o1;
27 unsigned long r_o2;
28 unsigned long r_o3;
29 unsigned long r_o4;
30 unsigned long r_o5;
31 unsigned long r_o6;
32 unsigned long r_o7;
33 unsigned long __pad;
34 unsigned long r_tstate;
35 unsigned long r_tpc;
36 unsigned long r_tnpc;
37 unsigned int r_y;
38 unsigned int r_fprs;
39};
40
41#define FPU_REGS_TYPE unsigned int
42#define FPU_FSR_TYPE unsigned long
43
44struct fp_status {
45 unsigned long fpu_fr[32];
46 unsigned long Fpu_fsr;
47};
48
49struct fpu {
50 struct fp_status f_fpstatus;
51};
52
53#define fpu_regs f_fpstatus.fpu_fr
54#define fpu_fsr f_fpstatus.Fpu_fsr
55
56#endif /* __SPARC64_REG_H */
diff --git a/include/asm-sparc/resource.h b/include/asm-sparc/resource.h
deleted file mode 100644
index fe163cafb4c..00000000000
--- a/include/asm-sparc/resource.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * resource.h: Resource definitions.
3 *
4 * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
5 */
6
7#ifndef _SPARC_RESOURCE_H
8#define _SPARC_RESOURCE_H
9
10/*
11 * These two resource limit IDs have a Sparc/Linux-specific ordering,
12 * the rest comes from the generic header:
13 */
14#define RLIMIT_NOFILE 6 /* max number of open files */
15#define RLIMIT_NPROC 7 /* max number of processes */
16
17#if defined(__sparc__) && defined(__arch64__)
18/* Use generic version */
19#else
20/*
21 * SuS says limits have to be unsigned.
22 * We make this unsigned, but keep the
23 * old value for compatibility:
24 */
25#define RLIM_INFINITY 0x7fffffff
26#endif
27
28#include <asm-generic/resource.h>
29
30#endif /* !(_SPARC_RESOURCE_H) */
diff --git a/include/asm-sparc/ross.h b/include/asm-sparc/ross.h
deleted file mode 100644
index ecb6e81786a..00000000000
--- a/include/asm-sparc/ross.h
+++ /dev/null
@@ -1,191 +0,0 @@
1/*
2 * ross.h: Ross module specific definitions and defines.
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 */
6
7#ifndef _SPARC_ROSS_H
8#define _SPARC_ROSS_H
9
10#include <asm/asi.h>
11#include <asm/page.h>
12
13/* Ross made Hypersparcs have a %psr 'impl' field of '0001'. The 'vers'
14 * field has '1111'.
15 */
16
17/* The MMU control register fields on the HyperSparc.
18 *
19 * -----------------------------------------------------------------
20 * |implvers| RSV |CWR|SE|WBE| MID |BM| C|CS|MR|CM|RSV|CE|RSV|NF|ME|
21 * -----------------------------------------------------------------
22 * 31 24 23-22 21 20 19 18-15 14 13 12 11 10 9 8 7-2 1 0
23 *
24 * Phew, lots of fields there ;-)
25 *
26 * CWR: Cache Wrapping Enabled, if one cache wrapping is on.
27 * SE: Snoop Enable, turns on bus snooping for cache activity if one.
28 * WBE: Write Buffer Enable, one turns it on.
29 * MID: The ModuleID of the chip for MBus transactions.
30 * BM: Boot-Mode. One indicates the MMU is in boot mode.
31 * C: Indicates whether accesses are cachable while the MMU is
32 * disabled.
33 * CS: Cache Size -- 0 = 128k, 1 = 256k
34 * MR: Memory Reflection, one indicates that the memory bus connected
35 * to the MBus supports memory reflection.
36 * CM: Cache Mode -- 0 = write-through, 1 = copy-back
37 * CE: Cache Enable -- 0 = no caching, 1 = cache is on
38 * NF: No Fault -- 0 = faults trap the CPU from supervisor mode
39 * 1 = faults from supervisor mode do not generate traps
40 * ME: MMU Enable -- 0 = MMU is off, 1 = MMU is on
41 */
42
43#define HYPERSPARC_CWENABLE 0x00200000
44#define HYPERSPARC_SBENABLE 0x00100000
45#define HYPERSPARC_WBENABLE 0x00080000
46#define HYPERSPARC_MIDMASK 0x00078000
47#define HYPERSPARC_BMODE 0x00004000
48#define HYPERSPARC_ACENABLE 0x00002000
49#define HYPERSPARC_CSIZE 0x00001000
50#define HYPERSPARC_MRFLCT 0x00000800
51#define HYPERSPARC_CMODE 0x00000400
52#define HYPERSPARC_CENABLE 0x00000100
53#define HYPERSPARC_NFAULT 0x00000002
54#define HYPERSPARC_MENABLE 0x00000001
55
56
57/* The ICCR instruction cache register on the HyperSparc.
58 *
59 * -----------------------------------------------
60 * | | FTD | ICE |
61 * -----------------------------------------------
62 * 31 1 0
63 *
64 * This register is accessed using the V8 'wrasr' and 'rdasr'
65 * opcodes, since not all assemblers understand them and those
66 * that do use different semantics I will just hard code the
67 * instruction with a '.word' statement.
68 *
69 * FTD: If set to one flush instructions executed during an
70 * instruction cache hit occurs, the corresponding line
71 * for said cache-hit is invalidated. If FTD is zero,
72 * an unimplemented 'flush' trap will occur when any
73 * flush is executed by the processor.
74 *
75 * ICE: If set to one, the instruction cache is enabled. If
76 * zero, the cache will not be used for instruction fetches.
77 *
78 * All other bits are read as zeros, and writes to them have no
79 * effect.
80 *
81 * Wheee, not many assemblers understand the %iccr register nor
82 * the generic asr r/w instructions.
83 *
84 * 1000 0011 0100 0111 1100 0000 0000 0000 ! rd %iccr, %g1
85 *
86 * 0x 8 3 4 7 c 0 0 0 ! 0x8347c000
87 *
88 * 1011 1111 1000 0000 0110 0000 0000 0000 ! wr %g1, 0x0, %iccr
89 *
90 * 0x b f 8 0 6 0 0 0 ! 0xbf806000
91 *
92 */
93
94#define HYPERSPARC_ICCR_FTD 0x00000002
95#define HYPERSPARC_ICCR_ICE 0x00000001
96
97#ifndef __ASSEMBLY__
98
99static inline unsigned int get_ross_icr(void)
100{
101 unsigned int icreg;
102
103 __asm__ __volatile__(".word 0x8347c000\n\t" /* rd %iccr, %g1 */
104 "mov %%g1, %0\n\t"
105 : "=r" (icreg)
106 : /* no inputs */
107 : "g1", "memory");
108
109 return icreg;
110}
111
112static inline void put_ross_icr(unsigned int icreg)
113{
114 __asm__ __volatile__("or %%g0, %0, %%g1\n\t"
115 ".word 0xbf806000\n\t" /* wr %g1, 0x0, %iccr */
116 "nop\n\t"
117 "nop\n\t"
118 "nop\n\t"
119 : /* no outputs */
120 : "r" (icreg)
121 : "g1", "memory");
122
123 return;
124}
125
126/* HyperSparc specific cache flushing. */
127
128/* This is for the on-chip instruction cache. */
129static inline void hyper_flush_whole_icache(void)
130{
131 __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
132 : /* no outputs */
133 : "i" (ASI_M_FLUSH_IWHOLE)
134 : "memory");
135 return;
136}
137
138extern int vac_cache_size;
139extern int vac_line_size;
140
141static inline void hyper_clear_all_tags(void)
142{
143 unsigned long addr;
144
145 for(addr = 0; addr < vac_cache_size; addr += vac_line_size)
146 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
147 : /* no outputs */
148 : "r" (addr), "i" (ASI_M_DATAC_TAG)
149 : "memory");
150}
151
152static inline void hyper_flush_unconditional_combined(void)
153{
154 unsigned long addr;
155
156 for (addr = 0; addr < vac_cache_size; addr += vac_line_size)
157 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
158 : /* no outputs */
159 : "r" (addr), "i" (ASI_M_FLUSH_CTX)
160 : "memory");
161}
162
163static inline void hyper_flush_cache_user(void)
164{
165 unsigned long addr;
166
167 for (addr = 0; addr < vac_cache_size; addr += vac_line_size)
168 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
169 : /* no outputs */
170 : "r" (addr), "i" (ASI_M_FLUSH_USER)
171 : "memory");
172}
173
174static inline void hyper_flush_cache_page(unsigned long page)
175{
176 unsigned long end;
177
178 page &= PAGE_MASK;
179 end = page + PAGE_SIZE;
180 while (page < end) {
181 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
182 : /* no outputs */
183 : "r" (page), "i" (ASI_M_FLUSH_PAGE)
184 : "memory");
185 page += vac_line_size;
186 }
187}
188
189#endif /* !(__ASSEMBLY__) */
190
191#endif /* !(_SPARC_ROSS_H) */
diff --git a/include/asm-sparc/rtc.h b/include/asm-sparc/rtc.h
deleted file mode 100644
index f9ecb1fe2ec..00000000000
--- a/include/asm-sparc/rtc.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * rtc.h: Definitions for access to the Mostek real time clock
3 *
4 * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
5 */
6
7#ifndef _RTC_H
8#define _RTC_H
9
10#include <linux/ioctl.h>
11
12struct rtc_time
13{
14 int sec; /* Seconds (0-59) */
15 int min; /* Minutes (0-59) */
16 int hour; /* Hour (0-23) */
17 int dow; /* Day of the week (1-7) */
18 int dom; /* Day of the month (1-31) */
19 int month; /* Month of year (1-12) */
20 int year; /* Year (0-99) */
21};
22
23#define RTCGET _IOR('p', 20, struct rtc_time)
24#define RTCSET _IOW('p', 21, struct rtc_time)
25
26#endif
diff --git a/include/asm-sparc/rwsem-const.h b/include/asm-sparc/rwsem-const.h
deleted file mode 100644
index a303c9d64d8..00000000000
--- a/include/asm-sparc/rwsem-const.h
+++ /dev/null
@@ -1,12 +0,0 @@
1/* rwsem-const.h: RW semaphore counter constants. */
2#ifndef _SPARC64_RWSEM_CONST_H
3#define _SPARC64_RWSEM_CONST_H
4
5#define RWSEM_UNLOCKED_VALUE 0x00000000
6#define RWSEM_ACTIVE_BIAS 0x00000001
7#define RWSEM_ACTIVE_MASK 0x0000ffff
8#define RWSEM_WAITING_BIAS 0xffff0000
9#define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS
10#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
11
12#endif /* _SPARC64_RWSEM_CONST_H */
diff --git a/include/asm-sparc/rwsem.h b/include/asm-sparc/rwsem.h
deleted file mode 100644
index 1dc129ac2fe..00000000000
--- a/include/asm-sparc/rwsem.h
+++ /dev/null
@@ -1,84 +0,0 @@
1/*
2 * rwsem.h: R/W semaphores implemented using CAS
3 *
4 * Written by David S. Miller (davem@redhat.com), 2001.
5 * Derived from asm-i386/rwsem.h
6 */
7#ifndef _SPARC64_RWSEM_H
8#define _SPARC64_RWSEM_H
9
10#ifndef _LINUX_RWSEM_H
11#error "please don't include asm/rwsem.h directly, use linux/rwsem.h instead"
12#endif
13
14#ifdef __KERNEL__
15
16#include <linux/list.h>
17#include <linux/spinlock.h>
18#include <asm/rwsem-const.h>
19
20struct rwsem_waiter;
21
22struct rw_semaphore {
23 signed int count;
24 spinlock_t wait_lock;
25 struct list_head wait_list;
26#ifdef CONFIG_DEBUG_LOCK_ALLOC
27 struct lockdep_map dep_map;
28#endif
29};
30
31#ifdef CONFIG_DEBUG_LOCK_ALLOC
32# define __RWSEM_DEP_MAP_INIT(lockname) , .dep_map = { .name = #lockname }
33#else
34# define __RWSEM_DEP_MAP_INIT(lockname)
35#endif
36
37#define __RWSEM_INITIALIZER(name) \
38{ RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, LIST_HEAD_INIT((name).wait_list) \
39 __RWSEM_DEP_MAP_INIT(name) }
40
41#define DECLARE_RWSEM(name) \
42 struct rw_semaphore name = __RWSEM_INITIALIZER(name)
43
44extern void __init_rwsem(struct rw_semaphore *sem, const char *name,
45 struct lock_class_key *key);
46
47#define init_rwsem(sem) \
48do { \
49 static struct lock_class_key __key; \
50 \
51 __init_rwsem((sem), #sem, &__key); \
52} while (0)
53
54extern void __down_read(struct rw_semaphore *sem);
55extern int __down_read_trylock(struct rw_semaphore *sem);
56extern void __down_write(struct rw_semaphore *sem);
57extern int __down_write_trylock(struct rw_semaphore *sem);
58extern void __up_read(struct rw_semaphore *sem);
59extern void __up_write(struct rw_semaphore *sem);
60extern void __downgrade_write(struct rw_semaphore *sem);
61
62static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
63{
64 __down_write(sem);
65}
66
67static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
68{
69 return atomic_add_return(delta, (atomic_t *)(&sem->count));
70}
71
72static inline void rwsem_atomic_add(int delta, struct rw_semaphore *sem)
73{
74 atomic_add(delta, (atomic_t *)(&sem->count));
75}
76
77static inline int rwsem_is_locked(struct rw_semaphore *sem)
78{
79 return (sem->count != 0);
80}
81
82#endif /* __KERNEL__ */
83
84#endif /* _SPARC64_RWSEM_H */
diff --git a/include/asm-sparc/sbi.h b/include/asm-sparc/sbi.h
deleted file mode 100644
index 5eb7f1965d3..00000000000
--- a/include/asm-sparc/sbi.h
+++ /dev/null
@@ -1,115 +0,0 @@
1/*
2 * sbi.h: SBI (Sbus Interface on sun4d) definitions
3 *
4 * Copyright (C) 1997 Jakub Jelinek <jj@sunsite.mff.cuni.cz>
5 */
6
7#ifndef _SPARC_SBI_H
8#define _SPARC_SBI_H
9
10#include <asm/obio.h>
11
12/* SBI */
13struct sbi_regs {
14/* 0x0000 */ u32 cid; /* Component ID */
15/* 0x0004 */ u32 ctl; /* Control */
16/* 0x0008 */ u32 status; /* Status */
17 u32 _unused1;
18
19/* 0x0010 */ u32 cfg0; /* Slot0 config reg */
20/* 0x0014 */ u32 cfg1; /* Slot1 config reg */
21/* 0x0018 */ u32 cfg2; /* Slot2 config reg */
22/* 0x001c */ u32 cfg3; /* Slot3 config reg */
23
24/* 0x0020 */ u32 stb0; /* Streaming buf control for slot 0 */
25/* 0x0024 */ u32 stb1; /* Streaming buf control for slot 1 */
26/* 0x0028 */ u32 stb2; /* Streaming buf control for slot 2 */
27/* 0x002c */ u32 stb3; /* Streaming buf control for slot 3 */
28
29/* 0x0030 */ u32 intr_state; /* Interrupt state */
30/* 0x0034 */ u32 intr_tid; /* Interrupt target ID */
31/* 0x0038 */ u32 intr_diag; /* Interrupt diagnostics */
32};
33
34#define SBI_CID 0x02800000
35#define SBI_CTL 0x02800004
36#define SBI_STATUS 0x02800008
37#define SBI_CFG0 0x02800010
38#define SBI_CFG1 0x02800014
39#define SBI_CFG2 0x02800018
40#define SBI_CFG3 0x0280001c
41#define SBI_STB0 0x02800020
42#define SBI_STB1 0x02800024
43#define SBI_STB2 0x02800028
44#define SBI_STB3 0x0280002c
45#define SBI_INTR_STATE 0x02800030
46#define SBI_INTR_TID 0x02800034
47#define SBI_INTR_DIAG 0x02800038
48
49/* Burst bits for 8, 16, 32, 64 are in cfgX registers at bits 2, 3, 4, 5 respectively */
50#define SBI_CFG_BURST_MASK 0x0000001e
51
52/* How to make devid from sbi no */
53#define SBI2DEVID(sbino) ((sbino<<4)|2)
54
55/* intr_state has 4 bits for slots 0 .. 3 and these bits are repeated for each sbus irq level
56 *
57 * +-------+-------+-------+-------+-------+-------+-------+-------+
58 * SBUS IRQ LEVEL | 7 | 6 | 5 | 4 | 3 | 2 | 1 | |
59 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ Reser |
60 * SLOT # |3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0| ved |
61 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-------+
62 * Bits 31 27 23 19 15 11 7 3 0
63 */
64
65
66#ifndef __ASSEMBLY__
67
68static inline int acquire_sbi(int devid, int mask)
69{
70 __asm__ __volatile__ ("swapa [%2] %3, %0" :
71 "=r" (mask) :
72 "0" (mask),
73 "r" (ECSR_DEV_BASE(devid) | SBI_INTR_STATE),
74 "i" (ASI_M_CTL));
75 return mask;
76}
77
78static inline void release_sbi(int devid, int mask)
79{
80 __asm__ __volatile__ ("sta %0, [%1] %2" : :
81 "r" (mask),
82 "r" (ECSR_DEV_BASE(devid) | SBI_INTR_STATE),
83 "i" (ASI_M_CTL));
84}
85
86static inline void set_sbi_tid(int devid, int targetid)
87{
88 __asm__ __volatile__ ("sta %0, [%1] %2" : :
89 "r" (targetid),
90 "r" (ECSR_DEV_BASE(devid) | SBI_INTR_TID),
91 "i" (ASI_M_CTL));
92}
93
94static inline int get_sbi_ctl(int devid, int cfgno)
95{
96 int cfg;
97
98 __asm__ __volatile__ ("lda [%1] %2, %0" :
99 "=r" (cfg) :
100 "r" ((ECSR_DEV_BASE(devid) | SBI_CFG0) + (cfgno<<2)),
101 "i" (ASI_M_CTL));
102 return cfg;
103}
104
105static inline void set_sbi_ctl(int devid, int cfgno, int cfg)
106{
107 __asm__ __volatile__ ("sta %0, [%1] %2" : :
108 "r" (cfg),
109 "r" ((ECSR_DEV_BASE(devid) | SBI_CFG0) + (cfgno<<2)),
110 "i" (ASI_M_CTL));
111}
112
113#endif /* !__ASSEMBLY__ */
114
115#endif /* !(_SPARC_SBI_H) */
diff --git a/include/asm-sparc/sbus.h b/include/asm-sparc/sbus.h
deleted file mode 100644
index 8f29a197966..00000000000
--- a/include/asm-sparc/sbus.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_SBUS_H
2#define ___ASM_SPARC_SBUS_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/sbus_64.h>
5#else
6#include <asm-sparc/sbus_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/sbus_32.h b/include/asm-sparc/sbus_32.h
deleted file mode 100644
index 77b5d3aadc9..00000000000
--- a/include/asm-sparc/sbus_32.h
+++ /dev/null
@@ -1,153 +0,0 @@
1/*
2 * sbus.h: Defines for the Sun SBus.
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 */
6
7#ifndef _SPARC_SBUS_H
8#define _SPARC_SBUS_H
9
10#include <linux/dma-mapping.h>
11#include <linux/ioport.h>
12
13#include <asm/oplib.h>
14#include <asm/prom.h>
15#include <asm/of_device.h>
16#include <asm/scatterlist.h>
17
18/* We scan which devices are on the SBus using the PROM node device
19 * tree. SBus devices are described in two different ways. You can
20 * either get an absolute address at which to access the device, or
21 * you can get a SBus 'slot' number and an offset within that slot.
22 */
23
24/* The base address at which to calculate device OBIO addresses. */
25#define SUN_SBUS_BVADDR 0xf8000000
26#define SBUS_OFF_MASK 0x01ffffff
27
28/* These routines are used to calculate device address from slot
29 * numbers + offsets, and vice versa.
30 */
31
32static inline unsigned long sbus_devaddr(int slotnum, unsigned long offset)
33{
34 return (unsigned long) (SUN_SBUS_BVADDR+((slotnum)<<25)+(offset));
35}
36
37static inline int sbus_dev_slot(unsigned long dev_addr)
38{
39 return (int) (((dev_addr)-SUN_SBUS_BVADDR)>>25);
40}
41
42struct sbus_bus;
43
44/* Linux SBUS device tables */
45struct sbus_dev {
46 struct of_device ofdev;
47 struct sbus_bus *bus;
48 struct sbus_dev *next;
49 struct sbus_dev *child;
50 struct sbus_dev *parent;
51 int prom_node;
52 char prom_name[64];
53 int slot;
54
55 struct resource resource[PROMREG_MAX];
56
57 struct linux_prom_registers reg_addrs[PROMREG_MAX];
58 int num_registers;
59
60 struct linux_prom_ranges device_ranges[PROMREG_MAX];
61 int num_device_ranges;
62
63 unsigned int irqs[4];
64 int num_irqs;
65};
66#define to_sbus_device(d) container_of(d, struct sbus_dev, ofdev.dev)
67
68/* This struct describes the SBus(s) found on this machine. */
69struct sbus_bus {
70 struct of_device ofdev;
71 struct sbus_dev *devices; /* Link to devices on this SBus */
72 struct sbus_bus *next; /* next SBus, if more than one SBus */
73 int prom_node; /* PROM device tree node for this SBus */
74 char prom_name[64]; /* Usually "sbus" or "sbi" */
75 int clock_freq;
76
77 struct linux_prom_ranges sbus_ranges[PROMREG_MAX];
78 int num_sbus_ranges;
79
80 int devid;
81 int board;
82};
83#define to_sbus(d) container_of(d, struct sbus_bus, ofdev.dev)
84
85extern struct sbus_bus *sbus_root;
86
87static inline int
88sbus_is_slave(struct sbus_dev *dev)
89{
90 /* XXX Have to write this for sun4c's */
91 return 0;
92}
93
94/* Device probing routines could find these handy */
95#define for_each_sbus(bus) \
96 for((bus) = sbus_root; (bus); (bus)=(bus)->next)
97
98#define for_each_sbusdev(device, bus) \
99 for((device) = (bus)->devices; (device); (device)=(device)->next)
100
101#define for_all_sbusdev(device, bus) \
102 for ((bus) = sbus_root; (bus); (bus) = (bus)->next) \
103 for ((device) = (bus)->devices; (device); (device) = (device)->next)
104
105/* Driver DVMA interfaces. */
106#define sbus_can_dma_64bit(sdev) (0) /* actually, sparc_cpu_model==sun4d */
107#define sbus_can_burst64(sdev) (0) /* actually, sparc_cpu_model==sun4d */
108extern void sbus_set_sbus64(struct sbus_dev *, int);
109extern void sbus_fill_device_irq(struct sbus_dev *);
110
111/* These yield IOMMU mappings in consistent mode. */
112extern void *sbus_alloc_consistent(struct sbus_dev *, long, u32 *dma_addrp);
113extern void sbus_free_consistent(struct sbus_dev *, long, void *, u32);
114void prom_adjust_ranges(struct linux_prom_ranges *, int,
115 struct linux_prom_ranges *, int);
116
117#define SBUS_DMA_BIDIRECTIONAL DMA_BIDIRECTIONAL
118#define SBUS_DMA_TODEVICE DMA_TO_DEVICE
119#define SBUS_DMA_FROMDEVICE DMA_FROM_DEVICE
120#define SBUS_DMA_NONE DMA_NONE
121
122/* All the rest use streaming mode mappings. */
123extern dma_addr_t sbus_map_single(struct sbus_dev *, void *, size_t, int);
124extern void sbus_unmap_single(struct sbus_dev *, dma_addr_t, size_t, int);
125extern int sbus_map_sg(struct sbus_dev *, struct scatterlist *, int, int);
126extern void sbus_unmap_sg(struct sbus_dev *, struct scatterlist *, int, int);
127
128/* Finally, allow explicit synchronization of streamable mappings. */
129extern void sbus_dma_sync_single_for_cpu(struct sbus_dev *, dma_addr_t, size_t, int);
130#define sbus_dma_sync_single sbus_dma_sync_single_for_cpu
131extern void sbus_dma_sync_single_for_device(struct sbus_dev *, dma_addr_t, size_t, int);
132extern void sbus_dma_sync_sg_for_cpu(struct sbus_dev *, struct scatterlist *, int, int);
133#define sbus_dma_sync_sg sbus_dma_sync_sg_for_cpu
134extern void sbus_dma_sync_sg_for_device(struct sbus_dev *, struct scatterlist *, int, int);
135
136/* Eric Brower (ebrower@usa.net)
137 * Translate SBus interrupt levels to ino values--
138 * this is used when converting sbus "interrupts" OBP
139 * node values to "intr" node values, and is platform
140 * dependent. If only we could call OBP with
141 * "sbus-intr>cpu (sbint -- ino)" from kernel...
142 * See .../drivers/sbus/sbus.c for details.
143 */
144BTFIXUPDEF_CALL(unsigned int, sbint_to_irq, struct sbus_dev *sdev, unsigned int)
145#define sbint_to_irq(sdev, sbint) BTFIXUP_CALL(sbint_to_irq)(sdev, sbint)
146
147extern void sbus_arch_bus_ranges_init(struct device_node *, struct sbus_bus *);
148extern void sbus_setup_iommu(struct sbus_bus *, struct device_node *);
149extern void sbus_setup_arch_props(struct sbus_bus *, struct device_node *);
150extern int sbus_arch_preinit(void);
151extern void sbus_arch_postinit(void);
152
153#endif /* !(_SPARC_SBUS_H) */
diff --git a/include/asm-sparc/sbus_64.h b/include/asm-sparc/sbus_64.h
deleted file mode 100644
index 0e16b6dd7e9..00000000000
--- a/include/asm-sparc/sbus_64.h
+++ /dev/null
@@ -1,190 +0,0 @@
1/* sbus.h: Defines for the Sun SBus.
2 *
3 * Copyright (C) 1996, 1999, 2007 David S. Miller (davem@davemloft.net)
4 */
5
6#ifndef _SPARC64_SBUS_H
7#define _SPARC64_SBUS_H
8
9#include <linux/dma-mapping.h>
10#include <linux/ioport.h>
11
12#include <asm/oplib.h>
13#include <asm/prom.h>
14#include <asm/of_device.h>
15#include <asm/iommu.h>
16#include <asm/scatterlist.h>
17
18/* We scan which devices are on the SBus using the PROM node device
19 * tree. SBus devices are described in two different ways. You can
20 * either get an absolute address at which to access the device, or
21 * you can get a SBus 'slot' number and an offset within that slot.
22 */
23
24/* The base address at which to calculate device OBIO addresses. */
25#define SUN_SBUS_BVADDR 0x00000000
26#define SBUS_OFF_MASK 0x0fffffff
27
28/* These routines are used to calculate device address from slot
29 * numbers + offsets, and vice versa.
30 */
31
32static inline unsigned long sbus_devaddr(int slotnum, unsigned long offset)
33{
34 return (unsigned long) (SUN_SBUS_BVADDR+((slotnum)<<28)+(offset));
35}
36
37static inline int sbus_dev_slot(unsigned long dev_addr)
38{
39 return (int) (((dev_addr)-SUN_SBUS_BVADDR)>>28);
40}
41
42struct sbus_bus;
43
44/* Linux SBUS device tables */
45struct sbus_dev {
46 struct of_device ofdev;
47 struct sbus_bus *bus;
48 struct sbus_dev *next;
49 struct sbus_dev *child;
50 struct sbus_dev *parent;
51 int prom_node;
52 char prom_name[64];
53 int slot;
54
55 struct resource resource[PROMREG_MAX];
56
57 struct linux_prom_registers reg_addrs[PROMREG_MAX];
58 int num_registers;
59
60 struct linux_prom_ranges device_ranges[PROMREG_MAX];
61 int num_device_ranges;
62
63 unsigned int irqs[4];
64 int num_irqs;
65};
66#define to_sbus_device(d) container_of(d, struct sbus_dev, ofdev.dev)
67
68/* This struct describes the SBus(s) found on this machine. */
69struct sbus_bus {
70 struct of_device ofdev;
71 struct sbus_dev *devices; /* Tree of SBUS devices */
72 struct sbus_bus *next; /* Next SBUS in system */
73 int prom_node; /* OBP node of SBUS */
74 char prom_name[64]; /* Usually "sbus" or "sbi" */
75 int clock_freq;
76
77 struct linux_prom_ranges sbus_ranges[PROMREG_MAX];
78 int num_sbus_ranges;
79
80 int portid;
81};
82#define to_sbus(d) container_of(d, struct sbus_bus, ofdev.dev)
83
84extern struct sbus_bus *sbus_root;
85
86/* Device probing routines could find these handy */
87#define for_each_sbus(bus) \
88 for((bus) = sbus_root; (bus); (bus)=(bus)->next)
89
90#define for_each_sbusdev(device, bus) \
91 for((device) = (bus)->devices; (device); (device)=(device)->next)
92
93#define for_all_sbusdev(device, bus) \
94 for ((bus) = sbus_root; (bus); (bus) = (bus)->next) \
95 for ((device) = (bus)->devices; (device); (device) = (device)->next)
96
97/* Driver DVMA interfaces. */
98#define sbus_can_dma_64bit(sdev) (1)
99#define sbus_can_burst64(sdev) (1)
100extern void sbus_set_sbus64(struct sbus_dev *, int);
101extern void sbus_fill_device_irq(struct sbus_dev *);
102
103static inline void *sbus_alloc_consistent(struct sbus_dev *sdev , size_t size,
104 dma_addr_t *dma_handle)
105{
106 return dma_alloc_coherent(&sdev->ofdev.dev, size,
107 dma_handle, GFP_ATOMIC);
108}
109
110static inline void sbus_free_consistent(struct sbus_dev *sdev, size_t size,
111 void *vaddr, dma_addr_t dma_handle)
112{
113 return dma_free_coherent(&sdev->ofdev.dev, size, vaddr, dma_handle);
114}
115
116#define SBUS_DMA_BIDIRECTIONAL DMA_BIDIRECTIONAL
117#define SBUS_DMA_TODEVICE DMA_TO_DEVICE
118#define SBUS_DMA_FROMDEVICE DMA_FROM_DEVICE
119#define SBUS_DMA_NONE DMA_NONE
120
121/* All the rest use streaming mode mappings. */
122static inline dma_addr_t sbus_map_single(struct sbus_dev *sdev, void *ptr,
123 size_t size, int direction)
124{
125 return dma_map_single(&sdev->ofdev.dev, ptr, size,
126 (enum dma_data_direction) direction);
127}
128
129static inline void sbus_unmap_single(struct sbus_dev *sdev,
130 dma_addr_t dma_addr, size_t size,
131 int direction)
132{
133 dma_unmap_single(&sdev->ofdev.dev, dma_addr, size,
134 (enum dma_data_direction) direction);
135}
136
137static inline int sbus_map_sg(struct sbus_dev *sdev, struct scatterlist *sg,
138 int nents, int direction)
139{
140 return dma_map_sg(&sdev->ofdev.dev, sg, nents,
141 (enum dma_data_direction) direction);
142}
143
144static inline void sbus_unmap_sg(struct sbus_dev *sdev, struct scatterlist *sg,
145 int nents, int direction)
146{
147 dma_unmap_sg(&sdev->ofdev.dev, sg, nents,
148 (enum dma_data_direction) direction);
149}
150
151/* Finally, allow explicit synchronization of streamable mappings. */
152static inline void sbus_dma_sync_single_for_cpu(struct sbus_dev *sdev,
153 dma_addr_t dma_handle,
154 size_t size, int direction)
155{
156 dma_sync_single_for_cpu(&sdev->ofdev.dev, dma_handle, size,
157 (enum dma_data_direction) direction);
158}
159#define sbus_dma_sync_single sbus_dma_sync_single_for_cpu
160
161static inline void sbus_dma_sync_single_for_device(struct sbus_dev *sdev,
162 dma_addr_t dma_handle,
163 size_t size, int direction)
164{
165 /* No flushing needed to sync cpu writes to the device. */
166}
167
168static inline void sbus_dma_sync_sg_for_cpu(struct sbus_dev *sdev,
169 struct scatterlist *sg,
170 int nents, int direction)
171{
172 dma_sync_sg_for_cpu(&sdev->ofdev.dev, sg, nents,
173 (enum dma_data_direction) direction);
174}
175#define sbus_dma_sync_sg sbus_dma_sync_sg_for_cpu
176
177static inline void sbus_dma_sync_sg_for_device(struct sbus_dev *sdev,
178 struct scatterlist *sg,
179 int nents, int direction)
180{
181 /* No flushing needed to sync cpu writes to the device. */
182}
183
184extern void sbus_arch_bus_ranges_init(struct device_node *, struct sbus_bus *);
185extern void sbus_setup_iommu(struct sbus_bus *, struct device_node *);
186extern void sbus_setup_arch_props(struct sbus_bus *, struct device_node *);
187extern int sbus_arch_preinit(void);
188extern void sbus_arch_postinit(void);
189
190#endif /* !(_SPARC64_SBUS_H) */
diff --git a/include/asm-sparc/scatterlist.h b/include/asm-sparc/scatterlist.h
deleted file mode 100644
index b1a0e316c2b..00000000000
--- a/include/asm-sparc/scatterlist.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_SCATTERLIST_H
2#define ___ASM_SPARC_SCATTERLIST_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/scatterlist_64.h>
5#else
6#include <asm-sparc/scatterlist_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/scatterlist_32.h b/include/asm-sparc/scatterlist_32.h
deleted file mode 100644
index c82609ca1d0..00000000000
--- a/include/asm-sparc/scatterlist_32.h
+++ /dev/null
@@ -1,26 +0,0 @@
1#ifndef _SPARC_SCATTERLIST_H
2#define _SPARC_SCATTERLIST_H
3
4#include <linux/types.h>
5
6struct scatterlist {
7#ifdef CONFIG_DEBUG_SG
8 unsigned long sg_magic;
9#endif
10 unsigned long page_link;
11 unsigned int offset;
12
13 unsigned int length;
14
15 __u32 dvma_address; /* A place to hang host-specific addresses at. */
16 __u32 dvma_length;
17};
18
19#define sg_dma_address(sg) ((sg)->dvma_address)
20#define sg_dma_len(sg) ((sg)->dvma_length)
21
22#define ISA_DMA_THRESHOLD (~0UL)
23
24#define ARCH_HAS_SG_CHAIN
25
26#endif /* !(_SPARC_SCATTERLIST_H) */
diff --git a/include/asm-sparc/scatterlist_64.h b/include/asm-sparc/scatterlist_64.h
deleted file mode 100644
index 81bd058f938..00000000000
--- a/include/asm-sparc/scatterlist_64.h
+++ /dev/null
@@ -1,27 +0,0 @@
1#ifndef _SPARC64_SCATTERLIST_H
2#define _SPARC64_SCATTERLIST_H
3
4#include <asm/page.h>
5#include <asm/types.h>
6
7struct scatterlist {
8#ifdef CONFIG_DEBUG_SG
9 unsigned long sg_magic;
10#endif
11 unsigned long page_link;
12 unsigned int offset;
13
14 unsigned int length;
15
16 dma_addr_t dma_address;
17 __u32 dma_length;
18};
19
20#define sg_dma_address(sg) ((sg)->dma_address)
21#define sg_dma_len(sg) ((sg)->dma_length)
22
23#define ISA_DMA_THRESHOLD (~0UL)
24
25#define ARCH_HAS_SG_CHAIN
26
27#endif /* !(_SPARC64_SCATTERLIST_H) */
diff --git a/include/asm-sparc/scratchpad.h b/include/asm-sparc/scratchpad.h
deleted file mode 100644
index 5e8b01fb334..00000000000
--- a/include/asm-sparc/scratchpad.h
+++ /dev/null
@@ -1,14 +0,0 @@
1#ifndef _SPARC64_SCRATCHPAD_H
2#define _SPARC64_SCRATCHPAD_H
3
4/* Sun4v scratchpad registers, accessed via ASI_SCRATCHPAD. */
5
6#define SCRATCHPAD_MMU_MISS 0x00 /* Shared with OBP - set by OBP */
7#define SCRATCHPAD_CPUID 0x08 /* Shared with OBP - set by hypervisor */
8#define SCRATCHPAD_UTSBREG1 0x10
9#define SCRATCHPAD_UTSBREG2 0x18
10 /* 0x20 and 0x28, hypervisor only... */
11#define SCRATCHPAD_UNUSED1 0x30
12#define SCRATCHPAD_UNUSED2 0x38 /* Reserved for OBP */
13
14#endif /* !(_SPARC64_SCRATCHPAD_H) */
diff --git a/include/asm-sparc/seccomp.h b/include/asm-sparc/seccomp.h
deleted file mode 100644
index 7fcd9968192..00000000000
--- a/include/asm-sparc/seccomp.h
+++ /dev/null
@@ -1,21 +0,0 @@
1#ifndef _ASM_SECCOMP_H
2
3#include <linux/thread_info.h> /* already defines TIF_32BIT */
4
5#ifndef TIF_32BIT
6#error "unexpected TIF_32BIT on sparc64"
7#endif
8
9#include <linux/unistd.h>
10
11#define __NR_seccomp_read __NR_read
12#define __NR_seccomp_write __NR_write
13#define __NR_seccomp_exit __NR_exit
14#define __NR_seccomp_sigreturn __NR_rt_sigreturn
15
16#define __NR_seccomp_read_32 __NR_read
17#define __NR_seccomp_write_32 __NR_write
18#define __NR_seccomp_exit_32 __NR_exit
19#define __NR_seccomp_sigreturn_32 __NR_sigreturn
20
21#endif /* _ASM_SECCOMP_H */
diff --git a/include/asm-sparc/sections.h b/include/asm-sparc/sections.h
deleted file mode 100644
index cbd01916242..00000000000
--- a/include/asm-sparc/sections.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_SECTIONS_H
2#define ___ASM_SPARC_SECTIONS_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/sections_64.h>
5#else
6#include <asm-sparc/sections_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/sections_32.h b/include/asm-sparc/sections_32.h
deleted file mode 100644
index 6832841df05..00000000000
--- a/include/asm-sparc/sections_32.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _SPARC_SECTIONS_H
2#define _SPARC_SECTIONS_H
3
4#include <asm-generic/sections.h>
5
6#endif
diff --git a/include/asm-sparc/sections_64.h b/include/asm-sparc/sections_64.h
deleted file mode 100644
index 3f4b9fdc28d..00000000000
--- a/include/asm-sparc/sections_64.h
+++ /dev/null
@@ -1,9 +0,0 @@
1#ifndef _SPARC64_SECTIONS_H
2#define _SPARC64_SECTIONS_H
3
4/* nothing to see, move along */
5#include <asm-generic/sections.h>
6
7extern char _start[];
8
9#endif
diff --git a/include/asm-sparc/sembuf.h b/include/asm-sparc/sembuf.h
deleted file mode 100644
index faee1be08d6..00000000000
--- a/include/asm-sparc/sembuf.h
+++ /dev/null
@@ -1,31 +0,0 @@
1#ifndef _SPARC_SEMBUF_H
2#define _SPARC_SEMBUF_H
3
4/*
5 * The semid64_ds structure for sparc architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 64-bit time_t to solve y2038 problem
11 * - 2 miscellaneous 32-bit values
12 */
13#if defined(__sparc__) && defined(__arch64__)
14# define PADDING(x)
15#else
16# define PADDING(x) unsigned int x;
17#endif
18
19struct semid64_ds {
20 struct ipc64_perm sem_perm; /* permissions .. see ipc.h */
21 PADDING(__pad1)
22 __kernel_time_t sem_otime; /* last semop time */
23 PADDING(__pad2)
24 __kernel_time_t sem_ctime; /* last change time */
25 unsigned long sem_nsems; /* no. of semaphores in array */
26 unsigned long __unused1;
27 unsigned long __unused2;
28};
29#undef PADDING
30
31#endif /* _SPARC64_SEMBUF_H */
diff --git a/include/asm-sparc/setup.h b/include/asm-sparc/setup.h
deleted file mode 100644
index 2643c62f4ac..00000000000
--- a/include/asm-sparc/setup.h
+++ /dev/null
@@ -1,14 +0,0 @@
1/*
2 * Just a place holder.
3 */
4
5#ifndef _SPARC_SETUP_H
6#define _SPARC_SETUP_H
7
8#if defined(__sparc__) && defined(__arch64__)
9# define COMMAND_LINE_SIZE 2048
10#else
11# define COMMAND_LINE_SIZE 256
12#endif
13
14#endif /* _SPARC_SETUP_H */
diff --git a/include/asm-sparc/sfafsr.h b/include/asm-sparc/sfafsr.h
deleted file mode 100644
index e96137b04a4..00000000000
--- a/include/asm-sparc/sfafsr.h
+++ /dev/null
@@ -1,82 +0,0 @@
1#ifndef _SPARC64_SFAFSR_H
2#define _SPARC64_SFAFSR_H
3
4#include <linux/const.h>
5
6/* Spitfire Asynchronous Fault Status register, ASI=0x4C VA<63:0>=0x0 */
7
8#define SFAFSR_ME (_AC(1,UL) << SFAFSR_ME_SHIFT)
9#define SFAFSR_ME_SHIFT 32
10#define SFAFSR_PRIV (_AC(1,UL) << SFAFSR_PRIV_SHIFT)
11#define SFAFSR_PRIV_SHIFT 31
12#define SFAFSR_ISAP (_AC(1,UL) << SFAFSR_ISAP_SHIFT)
13#define SFAFSR_ISAP_SHIFT 30
14#define SFAFSR_ETP (_AC(1,UL) << SFAFSR_ETP_SHIFT)
15#define SFAFSR_ETP_SHIFT 29
16#define SFAFSR_IVUE (_AC(1,UL) << SFAFSR_IVUE_SHIFT)
17#define SFAFSR_IVUE_SHIFT 28
18#define SFAFSR_TO (_AC(1,UL) << SFAFSR_TO_SHIFT)
19#define SFAFSR_TO_SHIFT 27
20#define SFAFSR_BERR (_AC(1,UL) << SFAFSR_BERR_SHIFT)
21#define SFAFSR_BERR_SHIFT 26
22#define SFAFSR_LDP (_AC(1,UL) << SFAFSR_LDP_SHIFT)
23#define SFAFSR_LDP_SHIFT 25
24#define SFAFSR_CP (_AC(1,UL) << SFAFSR_CP_SHIFT)
25#define SFAFSR_CP_SHIFT 24
26#define SFAFSR_WP (_AC(1,UL) << SFAFSR_WP_SHIFT)
27#define SFAFSR_WP_SHIFT 23
28#define SFAFSR_EDP (_AC(1,UL) << SFAFSR_EDP_SHIFT)
29#define SFAFSR_EDP_SHIFT 22
30#define SFAFSR_UE (_AC(1,UL) << SFAFSR_UE_SHIFT)
31#define SFAFSR_UE_SHIFT 21
32#define SFAFSR_CE (_AC(1,UL) << SFAFSR_CE_SHIFT)
33#define SFAFSR_CE_SHIFT 20
34#define SFAFSR_ETS (_AC(0xf,UL) << SFAFSR_ETS_SHIFT)
35#define SFAFSR_ETS_SHIFT 16
36#define SFAFSR_PSYND (_AC(0xffff,UL) << SFAFSR_PSYND_SHIFT)
37#define SFAFSR_PSYND_SHIFT 0
38
39/* UDB Error Register, ASI=0x7f VA<63:0>=0x0(High),0x18(Low) for read
40 * ASI=0x77 VA<63:0>=0x0(High),0x18(Low) for write
41 */
42
43#define UDBE_UE (_AC(1,UL) << 9)
44#define UDBE_CE (_AC(1,UL) << 8)
45#define UDBE_E_SYNDR (_AC(0xff,UL) << 0)
46
47/* The trap handlers for asynchronous errors encode the AFSR and
48 * other pieces of information into a 64-bit argument for C code
49 * encoded as follows:
50 *
51 * -----------------------------------------------
52 * | UDB_H | UDB_L | TL>1 | TT | AFSR |
53 * -----------------------------------------------
54 * 63 54 53 44 42 41 33 32 0
55 *
56 * The AFAR is passed in unchanged.
57 */
58#define SFSTAT_UDBH_MASK (_AC(0x3ff,UL) << SFSTAT_UDBH_SHIFT)
59#define SFSTAT_UDBH_SHIFT 54
60#define SFSTAT_UDBL_MASK (_AC(0x3ff,UL) << SFSTAT_UDBH_SHIFT)
61#define SFSTAT_UDBL_SHIFT 44
62#define SFSTAT_TL_GT_ONE (_AC(1,UL) << SFSTAT_TL_GT_ONE_SHIFT)
63#define SFSTAT_TL_GT_ONE_SHIFT 42
64#define SFSTAT_TRAP_TYPE (_AC(0x1FF,UL) << SFSTAT_TRAP_TYPE_SHIFT)
65#define SFSTAT_TRAP_TYPE_SHIFT 33
66#define SFSTAT_AFSR_MASK (_AC(0x1ffffffff,UL) << SFSTAT_AFSR_SHIFT)
67#define SFSTAT_AFSR_SHIFT 0
68
69/* ESTATE Error Enable Register, ASI=0x4b VA<63:0>=0x0 */
70#define ESTATE_ERR_CE 0x1 /* Correctable errors */
71#define ESTATE_ERR_NCE 0x2 /* TO, BERR, LDP, ETP, EDP, WP, UE, IVUE */
72#define ESTATE_ERR_ISAP 0x4 /* System address parity error */
73#define ESTATE_ERR_ALL (ESTATE_ERR_CE | \
74 ESTATE_ERR_NCE | \
75 ESTATE_ERR_ISAP)
76
77/* The various trap types that report using the above state. */
78#define TRAP_TYPE_IAE 0x09 /* Instruction Access Error */
79#define TRAP_TYPE_DAE 0x32 /* Data Access Error */
80#define TRAP_TYPE_CEE 0x63 /* Correctable ECC Error */
81
82#endif /* _SPARC64_SFAFSR_H */
diff --git a/include/asm-sparc/sfp-machine.h b/include/asm-sparc/sfp-machine.h
deleted file mode 100644
index c676fcc2dd2..00000000000
--- a/include/asm-sparc/sfp-machine.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_SFP_MACHINE_H
2#define ___ASM_SPARC_SFP_MACHINE_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/sfp-machine_64.h>
5#else
6#include <asm-sparc/sfp-machine_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/sfp-machine_32.h b/include/asm-sparc/sfp-machine_32.h
deleted file mode 100644
index 01d9c3b5a73..00000000000
--- a/include/asm-sparc/sfp-machine_32.h
+++ /dev/null
@@ -1,212 +0,0 @@
1/* Machine-dependent software floating-point definitions.
2 Sparc userland (_Q_*) version.
3 Copyright (C) 1997,1998,1999 Free Software Foundation, Inc.
4 This file is part of the GNU C Library.
5 Contributed by Richard Henderson (rth@cygnus.com),
6 Jakub Jelinek (jj@ultra.linux.cz),
7 David S. Miller (davem@redhat.com) and
8 Peter Maydell (pmaydell@chiark.greenend.org.uk).
9
10 The GNU C Library is free software; you can redistribute it and/or
11 modify it under the terms of the GNU Library General Public License as
12 published by the Free Software Foundation; either version 2 of the
13 License, or (at your option) any later version.
14
15 The GNU C Library is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 Library General Public License for more details.
19
20 You should have received a copy of the GNU Library General Public
21 License along with the GNU C Library; see the file COPYING.LIB. If
22 not, write to the Free Software Foundation, Inc.,
23 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24
25#ifndef _SFP_MACHINE_H
26#define _SFP_MACHINE_H
27
28
29#define _FP_W_TYPE_SIZE 32
30#define _FP_W_TYPE unsigned long
31#define _FP_WS_TYPE signed long
32#define _FP_I_TYPE long
33
34#define _FP_MUL_MEAT_S(R,X,Y) \
35 _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm)
36#define _FP_MUL_MEAT_D(R,X,Y) \
37 _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
38#define _FP_MUL_MEAT_Q(R,X,Y) \
39 _FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
40
41#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_udiv(S,R,X,Y)
42#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y)
43#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y)
44
45#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1)
46#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1), -1
47#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1
48#define _FP_NANSIGN_S 0
49#define _FP_NANSIGN_D 0
50#define _FP_NANSIGN_Q 0
51
52#define _FP_KEEPNANFRACP 1
53
54/* If one NaN is signaling and the other is not,
55 * we choose that one, otherwise we choose X.
56 */
57/* For _Qp_* and _Q_*, this should prefer X, for
58 * CPU instruction emulation this should prefer Y.
59 * (see SPAMv9 B.2.2 section).
60 */
61#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
62 do { \
63 if ((_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs) \
64 && !(_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs)) \
65 { \
66 R##_s = X##_s; \
67 _FP_FRAC_COPY_##wc(R,X); \
68 } \
69 else \
70 { \
71 R##_s = Y##_s; \
72 _FP_FRAC_COPY_##wc(R,Y); \
73 } \
74 R##_c = FP_CLS_NAN; \
75 } while (0)
76
77/* Some assembly to speed things up. */
78#define __FP_FRAC_ADD_3(r2,r1,r0,x2,x1,x0,y2,y1,y0) \
79 __asm__ ("addcc %r7,%8,%2\n\t" \
80 "addxcc %r5,%6,%1\n\t" \
81 "addx %r3,%4,%0\n" \
82 : "=r" ((USItype)(r2)), \
83 "=&r" ((USItype)(r1)), \
84 "=&r" ((USItype)(r0)) \
85 : "%rJ" ((USItype)(x2)), \
86 "rI" ((USItype)(y2)), \
87 "%rJ" ((USItype)(x1)), \
88 "rI" ((USItype)(y1)), \
89 "%rJ" ((USItype)(x0)), \
90 "rI" ((USItype)(y0)) \
91 : "cc")
92
93#define __FP_FRAC_SUB_3(r2,r1,r0,x2,x1,x0,y2,y1,y0) \
94 __asm__ ("subcc %r7,%8,%2\n\t" \
95 "subxcc %r5,%6,%1\n\t" \
96 "subx %r3,%4,%0\n" \
97 : "=r" ((USItype)(r2)), \
98 "=&r" ((USItype)(r1)), \
99 "=&r" ((USItype)(r0)) \
100 : "%rJ" ((USItype)(x2)), \
101 "rI" ((USItype)(y2)), \
102 "%rJ" ((USItype)(x1)), \
103 "rI" ((USItype)(y1)), \
104 "%rJ" ((USItype)(x0)), \
105 "rI" ((USItype)(y0)) \
106 : "cc")
107
108#define __FP_FRAC_ADD_4(r3,r2,r1,r0,x3,x2,x1,x0,y3,y2,y1,y0) \
109 do { \
110 /* We need to fool gcc, as we need to pass more than 10 \
111 input/outputs. */ \
112 register USItype _t1 __asm__ ("g1"), _t2 __asm__ ("g2"); \
113 __asm__ __volatile__ ( \
114 "addcc %r8,%9,%1\n\t" \
115 "addxcc %r6,%7,%0\n\t" \
116 "addxcc %r4,%5,%%g2\n\t" \
117 "addx %r2,%3,%%g1\n\t" \
118 : "=&r" ((USItype)(r1)), \
119 "=&r" ((USItype)(r0)) \
120 : "%rJ" ((USItype)(x3)), \
121 "rI" ((USItype)(y3)), \
122 "%rJ" ((USItype)(x2)), \
123 "rI" ((USItype)(y2)), \
124 "%rJ" ((USItype)(x1)), \
125 "rI" ((USItype)(y1)), \
126 "%rJ" ((USItype)(x0)), \
127 "rI" ((USItype)(y0)) \
128 : "cc", "g1", "g2"); \
129 __asm__ __volatile__ ("" : "=r" (_t1), "=r" (_t2)); \
130 r3 = _t1; r2 = _t2; \
131 } while (0)
132
133#define __FP_FRAC_SUB_4(r3,r2,r1,r0,x3,x2,x1,x0,y3,y2,y1,y0) \
134 do { \
135 /* We need to fool gcc, as we need to pass more than 10 \
136 input/outputs. */ \
137 register USItype _t1 __asm__ ("g1"), _t2 __asm__ ("g2"); \
138 __asm__ __volatile__ ( \
139 "subcc %r8,%9,%1\n\t" \
140 "subxcc %r6,%7,%0\n\t" \
141 "subxcc %r4,%5,%%g2\n\t" \
142 "subx %r2,%3,%%g1\n\t" \
143 : "=&r" ((USItype)(r1)), \
144 "=&r" ((USItype)(r0)) \
145 : "%rJ" ((USItype)(x3)), \
146 "rI" ((USItype)(y3)), \
147 "%rJ" ((USItype)(x2)), \
148 "rI" ((USItype)(y2)), \
149 "%rJ" ((USItype)(x1)), \
150 "rI" ((USItype)(y1)), \
151 "%rJ" ((USItype)(x0)), \
152 "rI" ((USItype)(y0)) \
153 : "cc", "g1", "g2"); \
154 __asm__ __volatile__ ("" : "=r" (_t1), "=r" (_t2)); \
155 r3 = _t1; r2 = _t2; \
156 } while (0)
157
158#define __FP_FRAC_DEC_3(x2,x1,x0,y2,y1,y0) __FP_FRAC_SUB_3(x2,x1,x0,x2,x1,x0,y2,y1,y0)
159
160#define __FP_FRAC_DEC_4(x3,x2,x1,x0,y3,y2,y1,y0) __FP_FRAC_SUB_4(x3,x2,x1,x0,x3,x2,x1,x0,y3,y2,y1,y0)
161
162#define __FP_FRAC_ADDI_4(x3,x2,x1,x0,i) \
163 __asm__ ("addcc %3,%4,%3\n\t" \
164 "addxcc %2,%%g0,%2\n\t" \
165 "addxcc %1,%%g0,%1\n\t" \
166 "addx %0,%%g0,%0\n\t" \
167 : "=&r" ((USItype)(x3)), \
168 "=&r" ((USItype)(x2)), \
169 "=&r" ((USItype)(x1)), \
170 "=&r" ((USItype)(x0)) \
171 : "rI" ((USItype)(i)), \
172 "0" ((USItype)(x3)), \
173 "1" ((USItype)(x2)), \
174 "2" ((USItype)(x1)), \
175 "3" ((USItype)(x0)) \
176 : "cc")
177
178#ifndef CONFIG_SMP
179extern struct task_struct *last_task_used_math;
180#endif
181
182/* Obtain the current rounding mode. */
183#ifndef FP_ROUNDMODE
184#ifdef CONFIG_SMP
185#define FP_ROUNDMODE ((current->thread.fsr >> 30) & 0x3)
186#else
187#define FP_ROUNDMODE ((last_task_used_math->thread.fsr >> 30) & 0x3)
188#endif
189#endif
190
191/* Exception flags. */
192#define FP_EX_INVALID (1 << 4)
193#define FP_EX_OVERFLOW (1 << 3)
194#define FP_EX_UNDERFLOW (1 << 2)
195#define FP_EX_DIVZERO (1 << 1)
196#define FP_EX_INEXACT (1 << 0)
197
198#define FP_HANDLE_EXCEPTIONS return _fex
199
200#ifdef CONFIG_SMP
201#define FP_INHIBIT_RESULTS ((current->thread.fsr >> 23) & _fex)
202#else
203#define FP_INHIBIT_RESULTS ((last_task_used_math->thread.fsr >> 23) & _fex)
204#endif
205
206#ifdef CONFIG_SMP
207#define FP_TRAPPING_EXCEPTIONS ((current->thread.fsr >> 23) & 0x1f)
208#else
209#define FP_TRAPPING_EXCEPTIONS ((last_task_used_math->thread.fsr >> 23) & 0x1f)
210#endif
211
212#endif
diff --git a/include/asm-sparc/sfp-machine_64.h b/include/asm-sparc/sfp-machine_64.h
deleted file mode 100644
index ca913ef40bd..00000000000
--- a/include/asm-sparc/sfp-machine_64.h
+++ /dev/null
@@ -1,93 +0,0 @@
1/* Machine-dependent software floating-point definitions.
2 Sparc64 kernel version.
3 Copyright (C) 1997,1998,1999 Free Software Foundation, Inc.
4 This file is part of the GNU C Library.
5 Contributed by Richard Henderson (rth@cygnus.com),
6 Jakub Jelinek (jj@ultra.linux.cz) and
7 David S. Miller (davem@redhat.com).
8
9 The GNU C Library is free software; you can redistribute it and/or
10 modify it under the terms of the GNU Library General Public License as
11 published by the Free Software Foundation; either version 2 of the
12 License, or (at your option) any later version.
13
14 The GNU C Library is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 Library General Public License for more details.
18
19 You should have received a copy of the GNU Library General Public
20 License along with the GNU C Library; see the file COPYING.LIB. If
21 not, write to the Free Software Foundation, Inc.,
22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23
24#ifndef _SFP_MACHINE_H
25#define _SFP_MACHINE_H
26
27#define _FP_W_TYPE_SIZE 64
28#define _FP_W_TYPE unsigned long
29#define _FP_WS_TYPE signed long
30#define _FP_I_TYPE long
31
32#define _FP_MUL_MEAT_S(R,X,Y) \
33 _FP_MUL_MEAT_1_imm(_FP_WFRACBITS_S,R,X,Y)
34#define _FP_MUL_MEAT_D(R,X,Y) \
35 _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
36#define _FP_MUL_MEAT_Q(R,X,Y) \
37 _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
38
39#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_imm(S,R,X,Y,_FP_DIV_HELP_imm)
40#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_1_udiv_norm(D,R,X,Y)
41#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_2_udiv(Q,R,X,Y)
42
43#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1)
44#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1)
45#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1
46#define _FP_NANSIGN_S 0
47#define _FP_NANSIGN_D 0
48#define _FP_NANSIGN_Q 0
49
50#define _FP_KEEPNANFRACP 1
51
52/* If one NaN is signaling and the other is not,
53 * we choose that one, otherwise we choose X.
54 */
55/* For _Qp_* and _Q_*, this should prefer X, for
56 * CPU instruction emulation this should prefer Y.
57 * (see SPAMv9 B.2.2 section).
58 */
59#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
60 do { \
61 if ((_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs) \
62 && !(_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs)) \
63 { \
64 R##_s = X##_s; \
65 _FP_FRAC_COPY_##wc(R,X); \
66 } \
67 else \
68 { \
69 R##_s = Y##_s; \
70 _FP_FRAC_COPY_##wc(R,Y); \
71 } \
72 R##_c = FP_CLS_NAN; \
73 } while (0)
74
75/* Obtain the current rounding mode. */
76#ifndef FP_ROUNDMODE
77#define FP_ROUNDMODE ((current_thread_info()->xfsr[0] >> 30) & 0x3)
78#endif
79
80/* Exception flags. */
81#define FP_EX_INVALID (1 << 4)
82#define FP_EX_OVERFLOW (1 << 3)
83#define FP_EX_UNDERFLOW (1 << 2)
84#define FP_EX_DIVZERO (1 << 1)
85#define FP_EX_INEXACT (1 << 0)
86
87#define FP_HANDLE_EXCEPTIONS return _fex
88
89#define FP_INHIBIT_RESULTS ((current_thread_info()->xfsr[0] >> 23) & _fex)
90
91#define FP_TRAPPING_EXCEPTIONS ((current_thread_info()->xfsr[0] >> 23) & 0x1f)
92
93#endif
diff --git a/include/asm-sparc/shmbuf.h b/include/asm-sparc/shmbuf.h
deleted file mode 100644
index 83a16055363..00000000000
--- a/include/asm-sparc/shmbuf.h
+++ /dev/null
@@ -1,50 +0,0 @@
1#ifndef _SPARC_SHMBUF_H
2#define _SPARC_SHMBUF_H
3
4/*
5 * The shmid64_ds structure for sparc architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 64-bit time_t to solve y2038 problem
11 * - 2 miscellaneous 32-bit values
12 */
13
14#if defined(__sparc__) && defined(__arch64__)
15# define PADDING(x)
16#else
17# define PADDING(x) unsigned int x;
18#endif
19
20struct shmid64_ds {
21 struct ipc64_perm shm_perm; /* operation perms */
22 PADDING(__pad1)
23 __kernel_time_t shm_atime; /* last attach time */
24 PADDING(__pad2)
25 __kernel_time_t shm_dtime; /* last detach time */
26 PADDING(__pad3)
27 __kernel_time_t shm_ctime; /* last change time */
28 size_t shm_segsz; /* size of segment (bytes) */
29 __kernel_pid_t shm_cpid; /* pid of creator */
30 __kernel_pid_t shm_lpid; /* pid of last operator */
31 unsigned long shm_nattch; /* no. of current attaches */
32 unsigned long __unused1;
33 unsigned long __unused2;
34};
35
36struct shminfo64 {
37 unsigned long shmmax;
38 unsigned long shmmin;
39 unsigned long shmmni;
40 unsigned long shmseg;
41 unsigned long shmall;
42 unsigned long __unused1;
43 unsigned long __unused2;
44 unsigned long __unused3;
45 unsigned long __unused4;
46};
47
48#undef PADDING
49
50#endif /* _SPARC_SHMBUF_H */
diff --git a/include/asm-sparc/shmparam.h b/include/asm-sparc/shmparam.h
deleted file mode 100644
index 16fda7e9acc..00000000000
--- a/include/asm-sparc/shmparam.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_SHMPARAM_H
2#define ___ASM_SPARC_SHMPARAM_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/shmparam_64.h>
5#else
6#include <asm-sparc/shmparam_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/shmparam_32.h b/include/asm-sparc/shmparam_32.h
deleted file mode 100644
index 59a1243c12f..00000000000
--- a/include/asm-sparc/shmparam_32.h
+++ /dev/null
@@ -1,11 +0,0 @@
1#ifndef _ASMSPARC_SHMPARAM_H
2#define _ASMSPARC_SHMPARAM_H
3
4#define __ARCH_FORCE_SHMLBA 1
5
6extern int vac_cache_size;
7#define SHMLBA (vac_cache_size ? vac_cache_size : \
8 (sparc_cpu_model == sun4c ? (64 * 1024) : \
9 (sparc_cpu_model == sun4 ? (128 * 1024) : PAGE_SIZE)))
10
11#endif /* _ASMSPARC_SHMPARAM_H */
diff --git a/include/asm-sparc/shmparam_64.h b/include/asm-sparc/shmparam_64.h
deleted file mode 100644
index 1ed0d6701a9..00000000000
--- a/include/asm-sparc/shmparam_64.h
+++ /dev/null
@@ -1,10 +0,0 @@
1#ifndef _ASMSPARC64_SHMPARAM_H
2#define _ASMSPARC64_SHMPARAM_H
3
4#include <asm/spitfire.h>
5
6#define __ARCH_FORCE_SHMLBA 1
7/* attach addr a multiple of this */
8#define SHMLBA ((PAGE_SIZE > L1DCACHE_SIZE) ? PAGE_SIZE : L1DCACHE_SIZE)
9
10#endif /* _ASMSPARC64_SHMPARAM_H */
diff --git a/include/asm-sparc/sigcontext.h b/include/asm-sparc/sigcontext.h
deleted file mode 100644
index 82fc7d54a4f..00000000000
--- a/include/asm-sparc/sigcontext.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_SIGCONTEXT_H
2#define ___ASM_SPARC_SIGCONTEXT_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/sigcontext_64.h>
5#else
6#include <asm-sparc/sigcontext_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/sigcontext_32.h b/include/asm-sparc/sigcontext_32.h
deleted file mode 100644
index c5fb60dcbd7..00000000000
--- a/include/asm-sparc/sigcontext_32.h
+++ /dev/null
@@ -1,62 +0,0 @@
1#ifndef __SPARC_SIGCONTEXT_H
2#define __SPARC_SIGCONTEXT_H
3
4#ifdef __KERNEL__
5#include <asm/ptrace.h>
6
7#ifndef __ASSEMBLY__
8
9#define __SUNOS_MAXWIN 31
10
11/* This is what SunOS does, so shall I. */
12struct sigcontext {
13 int sigc_onstack; /* state to restore */
14 int sigc_mask; /* sigmask to restore */
15 int sigc_sp; /* stack pointer */
16 int sigc_pc; /* program counter */
17 int sigc_npc; /* next program counter */
18 int sigc_psr; /* for condition codes etc */
19 int sigc_g1; /* User uses these two registers */
20 int sigc_o0; /* within the trampoline code. */
21
22 /* Now comes information regarding the users window set
23 * at the time of the signal.
24 */
25 int sigc_oswins; /* outstanding windows */
26
27 /* stack ptrs for each regwin buf */
28 char *sigc_spbuf[__SUNOS_MAXWIN];
29
30 /* Windows to restore after signal */
31 struct {
32 unsigned long locals[8];
33 unsigned long ins[8];
34 } sigc_wbuf[__SUNOS_MAXWIN];
35};
36
37typedef struct {
38 struct {
39 unsigned long psr;
40 unsigned long pc;
41 unsigned long npc;
42 unsigned long y;
43 unsigned long u_regs[16]; /* globals and ins */
44 } si_regs;
45 int si_mask;
46} __siginfo_t;
47
48typedef struct {
49 unsigned long si_float_regs [32];
50 unsigned long si_fsr;
51 unsigned long si_fpqdepth;
52 struct {
53 unsigned long *insn_addr;
54 unsigned long insn;
55 } si_fpqueue [16];
56} __siginfo_fpu_t;
57
58#endif /* !(__ASSEMBLY__) */
59
60#endif /* (__KERNEL__) */
61
62#endif /* !(__SPARC_SIGCONTEXT_H) */
diff --git a/include/asm-sparc/sigcontext_64.h b/include/asm-sparc/sigcontext_64.h
deleted file mode 100644
index 1c868d680cf..00000000000
--- a/include/asm-sparc/sigcontext_64.h
+++ /dev/null
@@ -1,87 +0,0 @@
1#ifndef __SPARC64_SIGCONTEXT_H
2#define __SPARC64_SIGCONTEXT_H
3
4#ifdef __KERNEL__
5#include <asm/ptrace.h>
6#endif
7
8#ifndef __ASSEMBLY__
9
10#ifdef __KERNEL__
11
12#define __SUNOS_MAXWIN 31
13
14/* This is what SunOS does, so shall I unless we use new 32bit signals or rt signals. */
15struct sigcontext32 {
16 int sigc_onstack; /* state to restore */
17 int sigc_mask; /* sigmask to restore */
18 int sigc_sp; /* stack pointer */
19 int sigc_pc; /* program counter */
20 int sigc_npc; /* next program counter */
21 int sigc_psr; /* for condition codes etc */
22 int sigc_g1; /* User uses these two registers */
23 int sigc_o0; /* within the trampoline code. */
24
25 /* Now comes information regarding the users window set
26 * at the time of the signal.
27 */
28 int sigc_oswins; /* outstanding windows */
29
30 /* stack ptrs for each regwin buf */
31 unsigned sigc_spbuf[__SUNOS_MAXWIN];
32
33 /* Windows to restore after signal */
34 struct reg_window32 sigc_wbuf[__SUNOS_MAXWIN];
35};
36
37#endif
38
39#ifdef __KERNEL__
40
41/* This is what we use for 32bit new non-rt signals. */
42
43typedef struct {
44 struct {
45 unsigned int psr;
46 unsigned int pc;
47 unsigned int npc;
48 unsigned int y;
49 unsigned int u_regs[16]; /* globals and ins */
50 } si_regs;
51 int si_mask;
52} __siginfo32_t;
53
54#endif
55
56typedef struct {
57 unsigned int si_float_regs [64];
58 unsigned long si_fsr;
59 unsigned long si_gsr;
60 unsigned long si_fprs;
61} __siginfo_fpu_t;
62
63/* This is what SunOS doesn't, so we have to write this alone
64 and do it properly. */
65struct sigcontext {
66 /* The size of this array has to match SI_MAX_SIZE from siginfo.h */
67 char sigc_info[128];
68 struct {
69 unsigned long u_regs[16]; /* globals and ins */
70 unsigned long tstate;
71 unsigned long tpc;
72 unsigned long tnpc;
73 unsigned int y;
74 unsigned int fprs;
75 } sigc_regs;
76 __siginfo_fpu_t * sigc_fpu_save;
77 struct {
78 void * ss_sp;
79 int ss_flags;
80 unsigned long ss_size;
81 } sigc_stack;
82 unsigned long sigc_mask;
83};
84
85#endif /* !(__ASSEMBLY__) */
86
87#endif /* !(__SPARC64_SIGCONTEXT_H) */
diff --git a/include/asm-sparc/siginfo.h b/include/asm-sparc/siginfo.h
deleted file mode 100644
index 2c9fccf4ce1..00000000000
--- a/include/asm-sparc/siginfo.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_SIGINFO_H
2#define ___ASM_SPARC_SIGINFO_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/siginfo_64.h>
5#else
6#include <asm-sparc/siginfo_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/siginfo_32.h b/include/asm-sparc/siginfo_32.h
deleted file mode 100644
index 3c71af135c5..00000000000
--- a/include/asm-sparc/siginfo_32.h
+++ /dev/null
@@ -1,17 +0,0 @@
1#ifndef _SPARC_SIGINFO_H
2#define _SPARC_SIGINFO_H
3
4#define __ARCH_SI_UID_T unsigned int
5#define __ARCH_SI_TRAPNO
6
7#include <asm-generic/siginfo.h>
8
9#define SI_NOINFO 32767 /* no information in siginfo_t */
10
11/*
12 * SIGEMT si_codes
13 */
14#define EMT_TAGOVF (__SI_FAULT|1) /* tag overflow */
15#define NSIGEMT 1
16
17#endif /* !(_SPARC_SIGINFO_H) */
diff --git a/include/asm-sparc/siginfo_64.h b/include/asm-sparc/siginfo_64.h
deleted file mode 100644
index c96e6c30f8b..00000000000
--- a/include/asm-sparc/siginfo_64.h
+++ /dev/null
@@ -1,32 +0,0 @@
1#ifndef _SPARC64_SIGINFO_H
2#define _SPARC64_SIGINFO_H
3
4#define SI_PAD_SIZE32 ((SI_MAX_SIZE/sizeof(int)) - 3)
5
6#define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
7#define __ARCH_SI_TRAPNO
8#define __ARCH_SI_BAND_T int
9
10#include <asm-generic/siginfo.h>
11
12#ifdef __KERNEL__
13
14#include <linux/compat.h>
15
16#ifdef CONFIG_COMPAT
17
18struct compat_siginfo;
19
20#endif /* CONFIG_COMPAT */
21
22#endif /* __KERNEL__ */
23
24#define SI_NOINFO 32767 /* no information in siginfo_t */
25
26/*
27 * SIGEMT si_codes
28 */
29#define EMT_TAGOVF (__SI_FAULT|1) /* tag overflow */
30#define NSIGEMT 1
31
32#endif
diff --git a/include/asm-sparc/signal.h b/include/asm-sparc/signal.h
deleted file mode 100644
index 36f5f9e482f..00000000000
--- a/include/asm-sparc/signal.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_SIGNAL_H
2#define ___ASM_SPARC_SIGNAL_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/signal_64.h>
5#else
6#include <asm-sparc/signal_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/signal_32.h b/include/asm-sparc/signal_32.h
deleted file mode 100644
index 96a60ab03ca..00000000000
--- a/include/asm-sparc/signal_32.h
+++ /dev/null
@@ -1,207 +0,0 @@
1#ifndef _ASMSPARC_SIGNAL_H
2#define _ASMSPARC_SIGNAL_H
3
4#include <asm/sigcontext.h>
5#include <linux/compiler.h>
6
7#ifdef __KERNEL__
8#ifndef __ASSEMBLY__
9#include <linux/personality.h>
10#include <linux/types.h>
11#endif
12#endif
13
14/* On the Sparc the signal handlers get passed a 'sub-signal' code
15 * for certain signal types, which we document here.
16 */
17#define SIGHUP 1
18#define SIGINT 2
19#define SIGQUIT 3
20#define SIGILL 4
21#define SUBSIG_STACK 0
22#define SUBSIG_ILLINST 2
23#define SUBSIG_PRIVINST 3
24#define SUBSIG_BADTRAP(t) (0x80 + (t))
25
26#define SIGTRAP 5
27#define SIGABRT 6
28#define SIGIOT 6
29
30#define SIGEMT 7
31#define SUBSIG_TAG 10
32
33#define SIGFPE 8
34#define SUBSIG_FPDISABLED 0x400
35#define SUBSIG_FPERROR 0x404
36#define SUBSIG_FPINTOVFL 0x001
37#define SUBSIG_FPSTSIG 0x002
38#define SUBSIG_IDIVZERO 0x014
39#define SUBSIG_FPINEXACT 0x0c4
40#define SUBSIG_FPDIVZERO 0x0c8
41#define SUBSIG_FPUNFLOW 0x0cc
42#define SUBSIG_FPOPERROR 0x0d0
43#define SUBSIG_FPOVFLOW 0x0d4
44
45#define SIGKILL 9
46#define SIGBUS 10
47#define SUBSIG_BUSTIMEOUT 1
48#define SUBSIG_ALIGNMENT 2
49#define SUBSIG_MISCERROR 5
50
51#define SIGSEGV 11
52#define SUBSIG_NOMAPPING 3
53#define SUBSIG_PROTECTION 4
54#define SUBSIG_SEGERROR 5
55
56#define SIGSYS 12
57
58#define SIGPIPE 13
59#define SIGALRM 14
60#define SIGTERM 15
61#define SIGURG 16
62
63/* SunOS values which deviate from the Linux/i386 ones */
64#define SIGSTOP 17
65#define SIGTSTP 18
66#define SIGCONT 19
67#define SIGCHLD 20
68#define SIGTTIN 21
69#define SIGTTOU 22
70#define SIGIO 23
71#define SIGPOLL SIGIO /* SysV name for SIGIO */
72#define SIGXCPU 24
73#define SIGXFSZ 25
74#define SIGVTALRM 26
75#define SIGPROF 27
76#define SIGWINCH 28
77#define SIGLOST 29
78#define SIGPWR SIGLOST
79#define SIGUSR1 30
80#define SIGUSR2 31
81
82/* Most things should be clean enough to redefine this at will, if care
83 * is taken to make libc match.
84 */
85
86#define __OLD_NSIG 32
87#define __NEW_NSIG 64
88#define _NSIG_BPW 32
89#define _NSIG_WORDS (__NEW_NSIG / _NSIG_BPW)
90
91#define SIGRTMIN 32
92#define SIGRTMAX __NEW_NSIG
93
94#if defined(__KERNEL__) || defined(__WANT_POSIX1B_SIGNALS__)
95#define _NSIG __NEW_NSIG
96#define __new_sigset_t sigset_t
97#define __new_sigaction sigaction
98#define __old_sigset_t old_sigset_t
99#define __old_sigaction old_sigaction
100#else
101#define _NSIG __OLD_NSIG
102#define __old_sigset_t sigset_t
103#define __old_sigaction sigaction
104#endif
105
106#ifndef __ASSEMBLY__
107
108typedef unsigned long __old_sigset_t;
109
110typedef struct {
111 unsigned long sig[_NSIG_WORDS];
112} __new_sigset_t;
113
114
115#ifdef __KERNEL__
116/* A SunOS sigstack */
117struct sigstack {
118 char *the_stack;
119 int cur_status;
120};
121#endif
122
123/* Sigvec flags */
124#define _SV_SSTACK 1u /* This signal handler should use sig-stack */
125#define _SV_INTR 2u /* Sig return should not restart system call */
126#define _SV_RESET 4u /* Set handler to SIG_DFL upon taken signal */
127#define _SV_IGNCHILD 8u /* Do not send SIGCHLD */
128
129/*
130 * sa_flags values: SA_STACK is not currently supported, but will allow the
131 * usage of signal stacks by using the (now obsolete) sa_restorer field in
132 * the sigaction structure as a stack pointer. This is now possible due to
133 * the changes in signal handling. LBT 010493.
134 * SA_RESTART flag to get restarting signals (which were the default long ago)
135 */
136#define SA_NOCLDSTOP _SV_IGNCHILD
137#define SA_STACK _SV_SSTACK
138#define SA_ONSTACK _SV_SSTACK
139#define SA_RESTART _SV_INTR
140#define SA_ONESHOT _SV_RESET
141#define SA_NOMASK 0x20u
142#define SA_NOCLDWAIT 0x100u
143#define SA_SIGINFO 0x200u
144
145#define SIG_BLOCK 0x01 /* for blocking signals */
146#define SIG_UNBLOCK 0x02 /* for unblocking signals */
147#define SIG_SETMASK 0x04 /* for setting the signal mask */
148
149/*
150 * sigaltstack controls
151 */
152#define SS_ONSTACK 1
153#define SS_DISABLE 2
154
155#define MINSIGSTKSZ 4096
156#define SIGSTKSZ 16384
157
158#ifdef __KERNEL__
159/*
160 * DJHR
161 * SA_STATIC_ALLOC is used for the SPARC system to indicate that this
162 * interrupt handler's irq structure should be statically allocated
163 * by the request_irq routine.
164 * The alternative is that arch/sparc/kernel/irq.c has carnal knowledge
165 * of interrupt usage and that sucks. Also without a flag like this
166 * it may be possible for the free_irq routine to attempt to free
167 * statically allocated data.. which is NOT GOOD.
168 *
169 */
170#define SA_STATIC_ALLOC 0x8000
171#endif
172
173#include <asm-generic/signal.h>
174
175#ifdef __KERNEL__
176struct __new_sigaction {
177 __sighandler_t sa_handler;
178 unsigned long sa_flags;
179 void (*sa_restorer)(void); /* Not used by Linux/SPARC */
180 __new_sigset_t sa_mask;
181};
182
183struct k_sigaction {
184 struct __new_sigaction sa;
185 void __user *ka_restorer;
186};
187
188struct __old_sigaction {
189 __sighandler_t sa_handler;
190 __old_sigset_t sa_mask;
191 unsigned long sa_flags;
192 void (*sa_restorer) (void); /* not used by Linux/SPARC */
193};
194
195typedef struct sigaltstack {
196 void __user *ss_sp;
197 int ss_flags;
198 size_t ss_size;
199} stack_t;
200
201#define ptrace_signal_deliver(regs, cookie) do { } while (0)
202
203#endif /* !(__KERNEL__) */
204
205#endif /* !(__ASSEMBLY__) */
206
207#endif /* !(_ASMSPARC_SIGNAL_H) */
diff --git a/include/asm-sparc/signal_64.h b/include/asm-sparc/signal_64.h
deleted file mode 100644
index ab1509a101c..00000000000
--- a/include/asm-sparc/signal_64.h
+++ /dev/null
@@ -1,194 +0,0 @@
1#ifndef _ASMSPARC64_SIGNAL_H
2#define _ASMSPARC64_SIGNAL_H
3
4#include <asm/sigcontext.h>
5
6#ifdef __KERNEL__
7#ifndef __ASSEMBLY__
8#include <linux/personality.h>
9#include <linux/types.h>
10#endif
11#endif
12
13/* On the Sparc the signal handlers get passed a 'sub-signal' code
14 * for certain signal types, which we document here.
15 */
16#define SIGHUP 1
17#define SIGINT 2
18#define SIGQUIT 3
19#define SIGILL 4
20#define SUBSIG_STACK 0
21#define SUBSIG_ILLINST 2
22#define SUBSIG_PRIVINST 3
23#define SUBSIG_BADTRAP(t) (0x80 + (t))
24
25#define SIGTRAP 5
26#define SIGABRT 6
27#define SIGIOT 6
28
29#define SIGEMT 7
30#define SUBSIG_TAG 10
31
32#define SIGFPE 8
33#define SUBSIG_FPDISABLED 0x400
34#define SUBSIG_FPERROR 0x404
35#define SUBSIG_FPINTOVFL 0x001
36#define SUBSIG_FPSTSIG 0x002
37#define SUBSIG_IDIVZERO 0x014
38#define SUBSIG_FPINEXACT 0x0c4
39#define SUBSIG_FPDIVZERO 0x0c8
40#define SUBSIG_FPUNFLOW 0x0cc
41#define SUBSIG_FPOPERROR 0x0d0
42#define SUBSIG_FPOVFLOW 0x0d4
43
44#define SIGKILL 9
45#define SIGBUS 10
46#define SUBSIG_BUSTIMEOUT 1
47#define SUBSIG_ALIGNMENT 2
48#define SUBSIG_MISCERROR 5
49
50#define SIGSEGV 11
51#define SUBSIG_NOMAPPING 3
52#define SUBSIG_PROTECTION 4
53#define SUBSIG_SEGERROR 5
54
55#define SIGSYS 12
56
57#define SIGPIPE 13
58#define SIGALRM 14
59#define SIGTERM 15
60#define SIGURG 16
61
62/* SunOS values which deviate from the Linux/i386 ones */
63#define SIGSTOP 17
64#define SIGTSTP 18
65#define SIGCONT 19
66#define SIGCHLD 20
67#define SIGTTIN 21
68#define SIGTTOU 22
69#define SIGIO 23
70#define SIGPOLL SIGIO /* SysV name for SIGIO */
71#define SIGXCPU 24
72#define SIGXFSZ 25
73#define SIGVTALRM 26
74#define SIGPROF 27
75#define SIGWINCH 28
76#define SIGLOST 29
77#define SIGPWR SIGLOST
78#define SIGUSR1 30
79#define SIGUSR2 31
80
81/* Most things should be clean enough to redefine this at will, if care
82 is taken to make libc match. */
83
84#define __OLD_NSIG 32
85#define __NEW_NSIG 64
86#define _NSIG_BPW 64
87#define _NSIG_WORDS (__NEW_NSIG / _NSIG_BPW)
88
89#define SIGRTMIN 32
90#define SIGRTMAX __NEW_NSIG
91
92#if defined(__KERNEL__) || defined(__WANT_POSIX1B_SIGNALS__)
93#define _NSIG __NEW_NSIG
94#define __new_sigset_t sigset_t
95#define __new_sigaction sigaction
96#define __new_sigaction32 sigaction32
97#define __old_sigset_t old_sigset_t
98#define __old_sigaction old_sigaction
99#define __old_sigaction32 old_sigaction32
100#else
101#define _NSIG __OLD_NSIG
102#define NSIG _NSIG
103#define __old_sigset_t sigset_t
104#define __old_sigaction sigaction
105#define __old_sigaction32 sigaction32
106#endif
107
108#ifndef __ASSEMBLY__
109
110typedef unsigned long __old_sigset_t; /* at least 32 bits */
111
112typedef struct {
113 unsigned long sig[_NSIG_WORDS];
114} __new_sigset_t;
115
116/* A SunOS sigstack */
117struct sigstack {
118 /* XXX 32-bit pointers pinhead XXX */
119 char *the_stack;
120 int cur_status;
121};
122
123/* Sigvec flags */
124#define _SV_SSTACK 1u /* This signal handler should use sig-stack */
125#define _SV_INTR 2u /* Sig return should not restart system call */
126#define _SV_RESET 4u /* Set handler to SIG_DFL upon taken signal */
127#define _SV_IGNCHILD 8u /* Do not send SIGCHLD */
128
129/*
130 * sa_flags values: SA_STACK is not currently supported, but will allow the
131 * usage of signal stacks by using the (now obsolete) sa_restorer field in
132 * the sigaction structure as a stack pointer. This is now possible due to
133 * the changes in signal handling. LBT 010493.
134 * SA_RESTART flag to get restarting signals (which were the default long ago)
135 */
136#define SA_NOCLDSTOP _SV_IGNCHILD
137#define SA_STACK _SV_SSTACK
138#define SA_ONSTACK _SV_SSTACK
139#define SA_RESTART _SV_INTR
140#define SA_ONESHOT _SV_RESET
141#define SA_NOMASK 0x20u
142#define SA_NOCLDWAIT 0x100u
143#define SA_SIGINFO 0x200u
144
145
146#define SIG_BLOCK 0x01 /* for blocking signals */
147#define SIG_UNBLOCK 0x02 /* for unblocking signals */
148#define SIG_SETMASK 0x04 /* for setting the signal mask */
149
150/*
151 * sigaltstack controls
152 */
153#define SS_ONSTACK 1
154#define SS_DISABLE 2
155
156#define MINSIGSTKSZ 4096
157#define SIGSTKSZ 16384
158
159#include <asm-generic/signal.h>
160
161struct __new_sigaction {
162 __sighandler_t sa_handler;
163 unsigned long sa_flags;
164 __sigrestore_t sa_restorer; /* not used by Linux/SPARC yet */
165 __new_sigset_t sa_mask;
166};
167
168struct __old_sigaction {
169 __sighandler_t sa_handler;
170 __old_sigset_t sa_mask;
171 unsigned long sa_flags;
172 void (*sa_restorer)(void); /* not used by Linux/SPARC yet */
173};
174
175typedef struct sigaltstack {
176 void __user *ss_sp;
177 int ss_flags;
178 size_t ss_size;
179} stack_t;
180
181#ifdef __KERNEL__
182
183struct k_sigaction {
184 struct __new_sigaction sa;
185 void __user *ka_restorer;
186};
187
188#define ptrace_signal_deliver(regs, cookie) do { } while (0)
189
190#endif /* !(__KERNEL__) */
191
192#endif /* !(__ASSEMBLY__) */
193
194#endif /* !(_ASMSPARC64_SIGNAL_H) */
diff --git a/include/asm-sparc/smp.h b/include/asm-sparc/smp.h
deleted file mode 100644
index 1f9dedfbabd..00000000000
--- a/include/asm-sparc/smp.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_SMP_H
2#define ___ASM_SPARC_SMP_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/smp_64.h>
5#else
6#include <asm-sparc/smp_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/smp_32.h b/include/asm-sparc/smp_32.h
deleted file mode 100644
index 7201752cf93..00000000000
--- a/include/asm-sparc/smp_32.h
+++ /dev/null
@@ -1,173 +0,0 @@
1/* smp.h: Sparc specific SMP stuff.
2 *
3 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
4 */
5
6#ifndef _SPARC_SMP_H
7#define _SPARC_SMP_H
8
9#include <linux/threads.h>
10#include <asm/head.h>
11#include <asm/btfixup.h>
12
13#ifndef __ASSEMBLY__
14
15#include <linux/cpumask.h>
16
17#endif /* __ASSEMBLY__ */
18
19#ifdef CONFIG_SMP
20
21#ifndef __ASSEMBLY__
22
23#include <asm/ptrace.h>
24#include <asm/asi.h>
25#include <asm/atomic.h>
26
27/*
28 * Private routines/data
29 */
30
31extern unsigned char boot_cpu_id;
32extern cpumask_t phys_cpu_present_map;
33#define cpu_possible_map phys_cpu_present_map
34
35typedef void (*smpfunc_t)(unsigned long, unsigned long, unsigned long,
36 unsigned long, unsigned long);
37
38/*
39 * General functions that each host system must provide.
40 */
41
42void sun4m_init_smp(void);
43void sun4d_init_smp(void);
44
45void smp_callin(void);
46void smp_boot_cpus(void);
47void smp_store_cpu_info(int);
48
49struct seq_file;
50void smp_bogo(struct seq_file *);
51void smp_info(struct seq_file *);
52
53BTFIXUPDEF_CALL(void, smp_cross_call, smpfunc_t, unsigned long, unsigned long, unsigned long, unsigned long, unsigned long)
54BTFIXUPDEF_CALL(int, __hard_smp_processor_id, void)
55BTFIXUPDEF_BLACKBOX(hard_smp_processor_id)
56BTFIXUPDEF_BLACKBOX(load_current)
57
58#define smp_cross_call(func,arg1,arg2,arg3,arg4,arg5) BTFIXUP_CALL(smp_cross_call)(func,arg1,arg2,arg3,arg4,arg5)
59
60static inline void xc0(smpfunc_t func) { smp_cross_call(func, 0, 0, 0, 0, 0); }
61static inline void xc1(smpfunc_t func, unsigned long arg1)
62{ smp_cross_call(func, arg1, 0, 0, 0, 0); }
63static inline void xc2(smpfunc_t func, unsigned long arg1, unsigned long arg2)
64{ smp_cross_call(func, arg1, arg2, 0, 0, 0); }
65static inline void xc3(smpfunc_t func, unsigned long arg1, unsigned long arg2,
66 unsigned long arg3)
67{ smp_cross_call(func, arg1, arg2, arg3, 0, 0); }
68static inline void xc4(smpfunc_t func, unsigned long arg1, unsigned long arg2,
69 unsigned long arg3, unsigned long arg4)
70{ smp_cross_call(func, arg1, arg2, arg3, arg4, 0); }
71static inline void xc5(smpfunc_t func, unsigned long arg1, unsigned long arg2,
72 unsigned long arg3, unsigned long arg4, unsigned long arg5)
73{ smp_cross_call(func, arg1, arg2, arg3, arg4, arg5); }
74
75static inline int smp_call_function(void (*func)(void *info), void *info, int wait)
76{
77 xc1((smpfunc_t)func, (unsigned long)info);
78 return 0;
79}
80
81static inline int cpu_logical_map(int cpu)
82{
83 return cpu;
84}
85
86static inline int hard_smp4m_processor_id(void)
87{
88 int cpuid;
89
90 __asm__ __volatile__("rd %%tbr, %0\n\t"
91 "srl %0, 12, %0\n\t"
92 "and %0, 3, %0\n\t" :
93 "=&r" (cpuid));
94 return cpuid;
95}
96
97static inline int hard_smp4d_processor_id(void)
98{
99 int cpuid;
100
101 __asm__ __volatile__("lda [%%g0] %1, %0\n\t" :
102 "=&r" (cpuid) : "i" (ASI_M_VIKING_TMP1));
103 return cpuid;
104}
105
106#ifndef MODULE
107static inline int hard_smp_processor_id(void)
108{
109 int cpuid;
110
111 /* Black box - sun4m
112 __asm__ __volatile__("rd %%tbr, %0\n\t"
113 "srl %0, 12, %0\n\t"
114 "and %0, 3, %0\n\t" :
115 "=&r" (cpuid));
116 - sun4d
117 __asm__ __volatile__("lda [%g0] ASI_M_VIKING_TMP1, %0\n\t"
118 "nop; nop" :
119 "=&r" (cpuid));
120 See btfixup.h and btfixupprep.c to understand how a blackbox works.
121 */
122 __asm__ __volatile__("sethi %%hi(___b_hard_smp_processor_id), %0\n\t"
123 "sethi %%hi(boot_cpu_id), %0\n\t"
124 "ldub [%0 + %%lo(boot_cpu_id)], %0\n\t" :
125 "=&r" (cpuid));
126 return cpuid;
127}
128#else
129static inline int hard_smp_processor_id(void)
130{
131 int cpuid;
132
133 __asm__ __volatile__("mov %%o7, %%g1\n\t"
134 "call ___f___hard_smp_processor_id\n\t"
135 " nop\n\t"
136 "mov %%g2, %0\n\t" : "=r"(cpuid) : : "g1", "g2");
137 return cpuid;
138}
139#endif
140
141#define raw_smp_processor_id() (current_thread_info()->cpu)
142
143#define prof_multiplier(__cpu) cpu_data(__cpu).multiplier
144#define prof_counter(__cpu) cpu_data(__cpu).counter
145
146void smp_setup_cpu_possible_map(void);
147
148#endif /* !(__ASSEMBLY__) */
149
150/* Sparc specific messages. */
151#define MSG_CROSS_CALL 0x0005 /* run func on cpus */
152
153/* Empirical PROM processor mailbox constants. If the per-cpu mailbox
154 * contains something other than one of these then the ipi is from
155 * Linux's active_kernel_processor. This facility exists so that
156 * the boot monitor can capture all the other cpus when one catches
157 * a watchdog reset or the user enters the monitor using L1-A keys.
158 */
159#define MBOX_STOPCPU 0xFB
160#define MBOX_IDLECPU 0xFC
161#define MBOX_IDLECPU2 0xFD
162#define MBOX_STOPCPU2 0xFE
163
164#else /* SMP */
165
166#define hard_smp_processor_id() 0
167#define smp_setup_cpu_possible_map() do { } while (0)
168
169#endif /* !(SMP) */
170
171#define NO_PROC_ID 0xFF
172
173#endif /* !(_SPARC_SMP_H) */
diff --git a/include/asm-sparc/smp_64.h b/include/asm-sparc/smp_64.h
deleted file mode 100644
index 57224dd37b3..00000000000
--- a/include/asm-sparc/smp_64.h
+++ /dev/null
@@ -1,67 +0,0 @@
1/* smp.h: Sparc64 specific SMP stuff.
2 *
3 * Copyright (C) 1996, 2008 David S. Miller (davem@davemloft.net)
4 */
5
6#ifndef _SPARC64_SMP_H
7#define _SPARC64_SMP_H
8
9#include <linux/threads.h>
10#include <asm/asi.h>
11#include <asm/starfire.h>
12#include <asm/spitfire.h>
13
14#ifndef __ASSEMBLY__
15
16#include <linux/cpumask.h>
17#include <linux/cache.h>
18
19#endif /* !(__ASSEMBLY__) */
20
21#ifdef CONFIG_SMP
22
23#ifndef __ASSEMBLY__
24
25/*
26 * Private routines/data
27 */
28
29#include <linux/bitops.h>
30#include <asm/atomic.h>
31#include <asm/percpu.h>
32
33DECLARE_PER_CPU(cpumask_t, cpu_sibling_map);
34extern cpumask_t cpu_core_map[NR_CPUS];
35extern int sparc64_multi_core;
36
37extern void arch_send_call_function_single_ipi(int cpu);
38extern void arch_send_call_function_ipi(cpumask_t mask);
39
40/*
41 * General functions that each host system must provide.
42 */
43
44extern int hard_smp_processor_id(void);
45#define raw_smp_processor_id() (current_thread_info()->cpu)
46
47extern void smp_fill_in_sib_core_maps(void);
48extern void cpu_play_dead(void);
49
50extern void smp_fetch_global_regs(void);
51
52#ifdef CONFIG_HOTPLUG_CPU
53extern int __cpu_disable(void);
54extern void __cpu_die(unsigned int cpu);
55#endif
56
57#endif /* !(__ASSEMBLY__) */
58
59#else
60
61#define hard_smp_processor_id() 0
62#define smp_fill_in_sib_core_maps() do { } while (0)
63#define smp_fetch_global_regs() do { } while (0)
64
65#endif /* !(CONFIG_SMP) */
66
67#endif /* !(_SPARC64_SMP_H) */
diff --git a/include/asm-sparc/smpprim.h b/include/asm-sparc/smpprim.h
deleted file mode 100644
index eb849d862c6..00000000000
--- a/include/asm-sparc/smpprim.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * smpprim.h: SMP locking primitives on the Sparc
3 *
4 * God knows we won't be actually using this code for some time
5 * but I thought I'd write it since I knew how.
6 *
7 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
8 */
9
10#ifndef __SPARC_SMPPRIM_H
11#define __SPARC_SMPPRIM_H
12
13/* Test and set the unsigned byte at ADDR to 1. Returns the previous
14 * value. On the Sparc we use the ldstub instruction since it is
15 * atomic.
16 */
17
18static inline __volatile__ char test_and_set(void *addr)
19{
20 char state = 0;
21
22 __asm__ __volatile__("ldstub [%0], %1 ! test_and_set\n\t"
23 "=r" (addr), "=r" (state) :
24 "0" (addr), "1" (state) : "memory");
25
26 return state;
27}
28
29/* Initialize a spin-lock. */
30static inline __volatile__ smp_initlock(void *spinlock)
31{
32 /* Unset the lock. */
33 *((unsigned char *) spinlock) = 0;
34
35 return;
36}
37
38/* This routine spins until it acquires the lock at ADDR. */
39static inline __volatile__ smp_lock(void *addr)
40{
41 while(test_and_set(addr) == 0xff)
42 ;
43
44 /* We now have the lock */
45 return;
46}
47
48/* This routine releases the lock at ADDR. */
49static inline __volatile__ smp_unlock(void *addr)
50{
51 *((unsigned char *) addr) = 0;
52}
53
54#endif /* !(__SPARC_SMPPRIM_H) */
diff --git a/include/asm-sparc/socket.h b/include/asm-sparc/socket.h
deleted file mode 100644
index bf50d0c2d58..00000000000
--- a/include/asm-sparc/socket.h
+++ /dev/null
@@ -1,58 +0,0 @@
1#ifndef _ASM_SOCKET_H
2#define _ASM_SOCKET_H
3
4#include <asm/sockios.h>
5
6/* For setsockopt(2) */
7#define SOL_SOCKET 0xffff
8
9#define SO_DEBUG 0x0001
10#define SO_PASSCRED 0x0002
11#define SO_REUSEADDR 0x0004
12#define SO_KEEPALIVE 0x0008
13#define SO_DONTROUTE 0x0010
14#define SO_BROADCAST 0x0020
15#define SO_PEERCRED 0x0040
16#define SO_LINGER 0x0080
17#define SO_OOBINLINE 0x0100
18/* To add :#define SO_REUSEPORT 0x0200 */
19#define SO_BSDCOMPAT 0x0400
20#define SO_RCVLOWAT 0x0800
21#define SO_SNDLOWAT 0x1000
22#define SO_RCVTIMEO 0x2000
23#define SO_SNDTIMEO 0x4000
24#define SO_ACCEPTCONN 0x8000
25
26#define SO_SNDBUF 0x1001
27#define SO_RCVBUF 0x1002
28#define SO_SNDBUFFORCE 0x100a
29#define SO_RCVBUFFORCE 0x100b
30#define SO_ERROR 0x1007
31#define SO_TYPE 0x1008
32
33/* Linux specific, keep the same. */
34#define SO_NO_CHECK 0x000b
35#define SO_PRIORITY 0x000c
36
37#define SO_BINDTODEVICE 0x000d
38
39#define SO_ATTACH_FILTER 0x001a
40#define SO_DETACH_FILTER 0x001b
41
42#define SO_PEERNAME 0x001c
43#define SO_TIMESTAMP 0x001d
44#define SCM_TIMESTAMP SO_TIMESTAMP
45
46#define SO_PEERSEC 0x001e
47#define SO_PASSSEC 0x001f
48#define SO_TIMESTAMPNS 0x0021
49#define SCM_TIMESTAMPNS SO_TIMESTAMPNS
50
51#define SO_MARK 0x0022
52
53/* Security levels - as per NRL IPv6 - don't actually do anything */
54#define SO_SECURITY_AUTHENTICATION 0x5001
55#define SO_SECURITY_ENCRYPTION_TRANSPORT 0x5002
56#define SO_SECURITY_ENCRYPTION_NETWORK 0x5004
57
58#endif /* _ASM_SOCKET_H */
diff --git a/include/asm-sparc/sockios.h b/include/asm-sparc/sockios.h
deleted file mode 100644
index 990ea746486..00000000000
--- a/include/asm-sparc/sockios.h
+++ /dev/null
@@ -1,14 +0,0 @@
1#ifndef _ASM_SPARC_SOCKIOS_H
2#define _ASM_SPARC_SOCKIOS_H
3
4/* Socket-level I/O control calls. */
5#define FIOSETOWN 0x8901
6#define SIOCSPGRP 0x8902
7#define FIOGETOWN 0x8903
8#define SIOCGPGRP 0x8904
9#define SIOCATMARK 0x8905
10#define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */
11#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */
12
13#endif /* !(_ASM_SPARC_SOCKIOS_H) */
14
diff --git a/include/asm-sparc/sparsemem.h b/include/asm-sparc/sparsemem.h
deleted file mode 100644
index b99d4e4b6d2..00000000000
--- a/include/asm-sparc/sparsemem.h
+++ /dev/null
@@ -1,12 +0,0 @@
1#ifndef _SPARC64_SPARSEMEM_H
2#define _SPARC64_SPARSEMEM_H
3
4#ifdef __KERNEL__
5
6#define SECTION_SIZE_BITS 30
7#define MAX_PHYSADDR_BITS 42
8#define MAX_PHYSMEM_BITS 42
9
10#endif /* !(__KERNEL__) */
11
12#endif /* !(_SPARC64_SPARSEMEM_H) */
diff --git a/include/asm-sparc/spinlock.h b/include/asm-sparc/spinlock.h
deleted file mode 100644
index 3b71c50b72e..00000000000
--- a/include/asm-sparc/spinlock.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_SPINLOCK_H
2#define ___ASM_SPARC_SPINLOCK_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/spinlock_64.h>
5#else
6#include <asm-sparc/spinlock_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/spinlock_32.h b/include/asm-sparc/spinlock_32.h
deleted file mode 100644
index de2249b267c..00000000000
--- a/include/asm-sparc/spinlock_32.h
+++ /dev/null
@@ -1,192 +0,0 @@
1/* spinlock.h: 32-bit Sparc spinlock support.
2 *
3 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
4 */
5
6#ifndef __SPARC_SPINLOCK_H
7#define __SPARC_SPINLOCK_H
8
9#include <linux/threads.h> /* For NR_CPUS */
10
11#ifndef __ASSEMBLY__
12
13#include <asm/psr.h>
14
15#define __raw_spin_is_locked(lock) (*((volatile unsigned char *)(lock)) != 0)
16
17#define __raw_spin_unlock_wait(lock) \
18 do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
19
20static inline void __raw_spin_lock(raw_spinlock_t *lock)
21{
22 __asm__ __volatile__(
23 "\n1:\n\t"
24 "ldstub [%0], %%g2\n\t"
25 "orcc %%g2, 0x0, %%g0\n\t"
26 "bne,a 2f\n\t"
27 " ldub [%0], %%g2\n\t"
28 ".subsection 2\n"
29 "2:\n\t"
30 "orcc %%g2, 0x0, %%g0\n\t"
31 "bne,a 2b\n\t"
32 " ldub [%0], %%g2\n\t"
33 "b,a 1b\n\t"
34 ".previous\n"
35 : /* no outputs */
36 : "r" (lock)
37 : "g2", "memory", "cc");
38}
39
40static inline int __raw_spin_trylock(raw_spinlock_t *lock)
41{
42 unsigned int result;
43 __asm__ __volatile__("ldstub [%1], %0"
44 : "=r" (result)
45 : "r" (lock)
46 : "memory");
47 return (result == 0);
48}
49
50static inline void __raw_spin_unlock(raw_spinlock_t *lock)
51{
52 __asm__ __volatile__("stb %%g0, [%0]" : : "r" (lock) : "memory");
53}
54
55/* Read-write spinlocks, allowing multiple readers
56 * but only one writer.
57 *
58 * NOTE! it is quite common to have readers in interrupts
59 * but no interrupt writers. For those circumstances we
60 * can "mix" irq-safe locks - any writer needs to get a
61 * irq-safe write-lock, but readers can get non-irqsafe
62 * read-locks.
63 *
64 * XXX This might create some problems with my dual spinlock
65 * XXX scheme, deadlocks etc. -DaveM
66 *
67 * Sort of like atomic_t's on Sparc, but even more clever.
68 *
69 * ------------------------------------
70 * | 24-bit counter | wlock | raw_rwlock_t
71 * ------------------------------------
72 * 31 8 7 0
73 *
74 * wlock signifies the one writer is in or somebody is updating
75 * counter. For a writer, if he successfully acquires the wlock,
76 * but counter is non-zero, he has to release the lock and wait,
77 * till both counter and wlock are zero.
78 *
79 * Unfortunately this scheme limits us to ~16,000,000 cpus.
80 */
81static inline void __read_lock(raw_rwlock_t *rw)
82{
83 register raw_rwlock_t *lp asm("g1");
84 lp = rw;
85 __asm__ __volatile__(
86 "mov %%o7, %%g4\n\t"
87 "call ___rw_read_enter\n\t"
88 " ldstub [%%g1 + 3], %%g2\n"
89 : /* no outputs */
90 : "r" (lp)
91 : "g2", "g4", "memory", "cc");
92}
93
94#define __raw_read_lock(lock) \
95do { unsigned long flags; \
96 local_irq_save(flags); \
97 __read_lock(lock); \
98 local_irq_restore(flags); \
99} while(0)
100
101static inline void __read_unlock(raw_rwlock_t *rw)
102{
103 register raw_rwlock_t *lp asm("g1");
104 lp = rw;
105 __asm__ __volatile__(
106 "mov %%o7, %%g4\n\t"
107 "call ___rw_read_exit\n\t"
108 " ldstub [%%g1 + 3], %%g2\n"
109 : /* no outputs */
110 : "r" (lp)
111 : "g2", "g4", "memory", "cc");
112}
113
114#define __raw_read_unlock(lock) \
115do { unsigned long flags; \
116 local_irq_save(flags); \
117 __read_unlock(lock); \
118 local_irq_restore(flags); \
119} while(0)
120
121static inline void __raw_write_lock(raw_rwlock_t *rw)
122{
123 register raw_rwlock_t *lp asm("g1");
124 lp = rw;
125 __asm__ __volatile__(
126 "mov %%o7, %%g4\n\t"
127 "call ___rw_write_enter\n\t"
128 " ldstub [%%g1 + 3], %%g2\n"
129 : /* no outputs */
130 : "r" (lp)
131 : "g2", "g4", "memory", "cc");
132 *(volatile __u32 *)&lp->lock = ~0U;
133}
134
135static inline int __raw_write_trylock(raw_rwlock_t *rw)
136{
137 unsigned int val;
138
139 __asm__ __volatile__("ldstub [%1 + 3], %0"
140 : "=r" (val)
141 : "r" (&rw->lock)
142 : "memory");
143
144 if (val == 0) {
145 val = rw->lock & ~0xff;
146 if (val)
147 ((volatile u8*)&rw->lock)[3] = 0;
148 else
149 *(volatile u32*)&rw->lock = ~0U;
150 }
151
152 return (val == 0);
153}
154
155static inline int __read_trylock(raw_rwlock_t *rw)
156{
157 register raw_rwlock_t *lp asm("g1");
158 register int res asm("o0");
159 lp = rw;
160 __asm__ __volatile__(
161 "mov %%o7, %%g4\n\t"
162 "call ___rw_read_try\n\t"
163 " ldstub [%%g1 + 3], %%g2\n"
164 : "=r" (res)
165 : "r" (lp)
166 : "g2", "g4", "memory", "cc");
167 return res;
168}
169
170#define __raw_read_trylock(lock) \
171({ unsigned long flags; \
172 int res; \
173 local_irq_save(flags); \
174 res = __read_trylock(lock); \
175 local_irq_restore(flags); \
176 res; \
177})
178
179#define __raw_write_unlock(rw) do { (rw)->lock = 0; } while(0)
180
181#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
182
183#define _raw_spin_relax(lock) cpu_relax()
184#define _raw_read_relax(lock) cpu_relax()
185#define _raw_write_relax(lock) cpu_relax()
186
187#define __raw_read_can_lock(rw) (!((rw)->lock & 0xff))
188#define __raw_write_can_lock(rw) (!(rw)->lock)
189
190#endif /* !(__ASSEMBLY__) */
191
192#endif /* __SPARC_SPINLOCK_H */
diff --git a/include/asm-sparc/spinlock_64.h b/include/asm-sparc/spinlock_64.h
deleted file mode 100644
index 0006fe9f8c7..00000000000
--- a/include/asm-sparc/spinlock_64.h
+++ /dev/null
@@ -1,250 +0,0 @@
1/* spinlock.h: 64-bit Sparc spinlock support.
2 *
3 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
4 */
5
6#ifndef __SPARC64_SPINLOCK_H
7#define __SPARC64_SPINLOCK_H
8
9#include <linux/threads.h> /* For NR_CPUS */
10
11#ifndef __ASSEMBLY__
12
13/* To get debugging spinlocks which detect and catch
14 * deadlock situations, set CONFIG_DEBUG_SPINLOCK
15 * and rebuild your kernel.
16 */
17
18/* All of these locking primitives are expected to work properly
19 * even in an RMO memory model, which currently is what the kernel
20 * runs in.
21 *
22 * There is another issue. Because we play games to save cycles
23 * in the non-contention case, we need to be extra careful about
24 * branch targets into the "spinning" code. They live in their
25 * own section, but the newer V9 branches have a shorter range
26 * than the traditional 32-bit sparc branch variants. The rule
27 * is that the branches that go into and out of the spinner sections
28 * must be pre-V9 branches.
29 */
30
31#define __raw_spin_is_locked(lp) ((lp)->lock != 0)
32
33#define __raw_spin_unlock_wait(lp) \
34 do { rmb(); \
35 } while((lp)->lock)
36
37static inline void __raw_spin_lock(raw_spinlock_t *lock)
38{
39 unsigned long tmp;
40
41 __asm__ __volatile__(
42"1: ldstub [%1], %0\n"
43" membar #StoreLoad | #StoreStore\n"
44" brnz,pn %0, 2f\n"
45" nop\n"
46" .subsection 2\n"
47"2: ldub [%1], %0\n"
48" membar #LoadLoad\n"
49" brnz,pt %0, 2b\n"
50" nop\n"
51" ba,a,pt %%xcc, 1b\n"
52" .previous"
53 : "=&r" (tmp)
54 : "r" (lock)
55 : "memory");
56}
57
58static inline int __raw_spin_trylock(raw_spinlock_t *lock)
59{
60 unsigned long result;
61
62 __asm__ __volatile__(
63" ldstub [%1], %0\n"
64" membar #StoreLoad | #StoreStore"
65 : "=r" (result)
66 : "r" (lock)
67 : "memory");
68
69 return (result == 0UL);
70}
71
72static inline void __raw_spin_unlock(raw_spinlock_t *lock)
73{
74 __asm__ __volatile__(
75" membar #StoreStore | #LoadStore\n"
76" stb %%g0, [%0]"
77 : /* No outputs */
78 : "r" (lock)
79 : "memory");
80}
81
82static inline void __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags)
83{
84 unsigned long tmp1, tmp2;
85
86 __asm__ __volatile__(
87"1: ldstub [%2], %0\n"
88" membar #StoreLoad | #StoreStore\n"
89" brnz,pn %0, 2f\n"
90" nop\n"
91" .subsection 2\n"
92"2: rdpr %%pil, %1\n"
93" wrpr %3, %%pil\n"
94"3: ldub [%2], %0\n"
95" membar #LoadLoad\n"
96" brnz,pt %0, 3b\n"
97" nop\n"
98" ba,pt %%xcc, 1b\n"
99" wrpr %1, %%pil\n"
100" .previous"
101 : "=&r" (tmp1), "=&r" (tmp2)
102 : "r"(lock), "r"(flags)
103 : "memory");
104}
105
106/* Multi-reader locks, these are much saner than the 32-bit Sparc ones... */
107
108static void inline __read_lock(raw_rwlock_t *lock)
109{
110 unsigned long tmp1, tmp2;
111
112 __asm__ __volatile__ (
113"1: ldsw [%2], %0\n"
114" brlz,pn %0, 2f\n"
115"4: add %0, 1, %1\n"
116" cas [%2], %0, %1\n"
117" cmp %0, %1\n"
118" membar #StoreLoad | #StoreStore\n"
119" bne,pn %%icc, 1b\n"
120" nop\n"
121" .subsection 2\n"
122"2: ldsw [%2], %0\n"
123" membar #LoadLoad\n"
124" brlz,pt %0, 2b\n"
125" nop\n"
126" ba,a,pt %%xcc, 4b\n"
127" .previous"
128 : "=&r" (tmp1), "=&r" (tmp2)
129 : "r" (lock)
130 : "memory");
131}
132
133static int inline __read_trylock(raw_rwlock_t *lock)
134{
135 int tmp1, tmp2;
136
137 __asm__ __volatile__ (
138"1: ldsw [%2], %0\n"
139" brlz,a,pn %0, 2f\n"
140" mov 0, %0\n"
141" add %0, 1, %1\n"
142" cas [%2], %0, %1\n"
143" cmp %0, %1\n"
144" membar #StoreLoad | #StoreStore\n"
145" bne,pn %%icc, 1b\n"
146" mov 1, %0\n"
147"2:"
148 : "=&r" (tmp1), "=&r" (tmp2)
149 : "r" (lock)
150 : "memory");
151
152 return tmp1;
153}
154
155static void inline __read_unlock(raw_rwlock_t *lock)
156{
157 unsigned long tmp1, tmp2;
158
159 __asm__ __volatile__(
160" membar #StoreLoad | #LoadLoad\n"
161"1: lduw [%2], %0\n"
162" sub %0, 1, %1\n"
163" cas [%2], %0, %1\n"
164" cmp %0, %1\n"
165" bne,pn %%xcc, 1b\n"
166" nop"
167 : "=&r" (tmp1), "=&r" (tmp2)
168 : "r" (lock)
169 : "memory");
170}
171
172static void inline __write_lock(raw_rwlock_t *lock)
173{
174 unsigned long mask, tmp1, tmp2;
175
176 mask = 0x80000000UL;
177
178 __asm__ __volatile__(
179"1: lduw [%2], %0\n"
180" brnz,pn %0, 2f\n"
181"4: or %0, %3, %1\n"
182" cas [%2], %0, %1\n"
183" cmp %0, %1\n"
184" membar #StoreLoad | #StoreStore\n"
185" bne,pn %%icc, 1b\n"
186" nop\n"
187" .subsection 2\n"
188"2: lduw [%2], %0\n"
189" membar #LoadLoad\n"
190" brnz,pt %0, 2b\n"
191" nop\n"
192" ba,a,pt %%xcc, 4b\n"
193" .previous"
194 : "=&r" (tmp1), "=&r" (tmp2)
195 : "r" (lock), "r" (mask)
196 : "memory");
197}
198
199static void inline __write_unlock(raw_rwlock_t *lock)
200{
201 __asm__ __volatile__(
202" membar #LoadStore | #StoreStore\n"
203" stw %%g0, [%0]"
204 : /* no outputs */
205 : "r" (lock)
206 : "memory");
207}
208
209static int inline __write_trylock(raw_rwlock_t *lock)
210{
211 unsigned long mask, tmp1, tmp2, result;
212
213 mask = 0x80000000UL;
214
215 __asm__ __volatile__(
216" mov 0, %2\n"
217"1: lduw [%3], %0\n"
218" brnz,pn %0, 2f\n"
219" or %0, %4, %1\n"
220" cas [%3], %0, %1\n"
221" cmp %0, %1\n"
222" membar #StoreLoad | #StoreStore\n"
223" bne,pn %%icc, 1b\n"
224" nop\n"
225" mov 1, %2\n"
226"2:"
227 : "=&r" (tmp1), "=&r" (tmp2), "=&r" (result)
228 : "r" (lock), "r" (mask)
229 : "memory");
230
231 return result;
232}
233
234#define __raw_read_lock(p) __read_lock(p)
235#define __raw_read_trylock(p) __read_trylock(p)
236#define __raw_read_unlock(p) __read_unlock(p)
237#define __raw_write_lock(p) __write_lock(p)
238#define __raw_write_unlock(p) __write_unlock(p)
239#define __raw_write_trylock(p) __write_trylock(p)
240
241#define __raw_read_can_lock(rw) (!((rw)->lock & 0x80000000UL))
242#define __raw_write_can_lock(rw) (!(rw)->lock)
243
244#define _raw_spin_relax(lock) cpu_relax()
245#define _raw_read_relax(lock) cpu_relax()
246#define _raw_write_relax(lock) cpu_relax()
247
248#endif /* !(__ASSEMBLY__) */
249
250#endif /* !(__SPARC64_SPINLOCK_H) */
diff --git a/include/asm-sparc/spinlock_types.h b/include/asm-sparc/spinlock_types.h
deleted file mode 100644
index 37cbe01c585..00000000000
--- a/include/asm-sparc/spinlock_types.h
+++ /dev/null
@@ -1,20 +0,0 @@
1#ifndef __SPARC_SPINLOCK_TYPES_H
2#define __SPARC_SPINLOCK_TYPES_H
3
4#ifndef __LINUX_SPINLOCK_TYPES_H
5# error "please don't include this file directly"
6#endif
7
8typedef struct {
9 volatile unsigned char lock;
10} raw_spinlock_t;
11
12#define __RAW_SPIN_LOCK_UNLOCKED { 0 }
13
14typedef struct {
15 volatile unsigned int lock;
16} raw_rwlock_t;
17
18#define __RAW_RW_LOCK_UNLOCKED { 0 }
19
20#endif
diff --git a/include/asm-sparc/spitfire.h b/include/asm-sparc/spitfire.h
deleted file mode 100644
index 985ea7e3199..00000000000
--- a/include/asm-sparc/spitfire.h
+++ /dev/null
@@ -1,342 +0,0 @@
1/* spitfire.h: SpitFire/BlackBird/Cheetah inline MMU operations.
2 *
3 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
4 */
5
6#ifndef _SPARC64_SPITFIRE_H
7#define _SPARC64_SPITFIRE_H
8
9#include <asm/asi.h>
10
11/* The following register addresses are accessible via ASI_DMMU
12 * and ASI_IMMU, that is there is a distinct and unique copy of
13 * each these registers for each TLB.
14 */
15#define TSB_TAG_TARGET 0x0000000000000000 /* All chips */
16#define TLB_SFSR 0x0000000000000018 /* All chips */
17#define TSB_REG 0x0000000000000028 /* All chips */
18#define TLB_TAG_ACCESS 0x0000000000000030 /* All chips */
19#define VIRT_WATCHPOINT 0x0000000000000038 /* All chips */
20#define PHYS_WATCHPOINT 0x0000000000000040 /* All chips */
21#define TSB_EXTENSION_P 0x0000000000000048 /* Ultra-III and later */
22#define TSB_EXTENSION_S 0x0000000000000050 /* Ultra-III and later, D-TLB only */
23#define TSB_EXTENSION_N 0x0000000000000058 /* Ultra-III and later */
24#define TLB_TAG_ACCESS_EXT 0x0000000000000060 /* Ultra-III+ and later */
25
26/* These registers only exist as one entity, and are accessed
27 * via ASI_DMMU only.
28 */
29#define PRIMARY_CONTEXT 0x0000000000000008
30#define SECONDARY_CONTEXT 0x0000000000000010
31#define DMMU_SFAR 0x0000000000000020
32#define VIRT_WATCHPOINT 0x0000000000000038
33#define PHYS_WATCHPOINT 0x0000000000000040
34
35#define SPITFIRE_HIGHEST_LOCKED_TLBENT (64 - 1)
36#define CHEETAH_HIGHEST_LOCKED_TLBENT (16 - 1)
37
38#define L1DCACHE_SIZE 0x4000
39
40#define SUN4V_CHIP_INVALID 0x00
41#define SUN4V_CHIP_NIAGARA1 0x01
42#define SUN4V_CHIP_NIAGARA2 0x02
43#define SUN4V_CHIP_UNKNOWN 0xff
44
45#ifndef __ASSEMBLY__
46
47enum ultra_tlb_layout {
48 spitfire = 0,
49 cheetah = 1,
50 cheetah_plus = 2,
51 hypervisor = 3,
52};
53
54extern enum ultra_tlb_layout tlb_type;
55
56extern int sun4v_chip_type;
57
58extern int cheetah_pcache_forced_on;
59extern void cheetah_enable_pcache(void);
60
61#define sparc64_highest_locked_tlbent() \
62 (tlb_type == spitfire ? \
63 SPITFIRE_HIGHEST_LOCKED_TLBENT : \
64 CHEETAH_HIGHEST_LOCKED_TLBENT)
65
66extern int num_kernel_image_mappings;
67
68/* The data cache is write through, so this just invalidates the
69 * specified line.
70 */
71static inline void spitfire_put_dcache_tag(unsigned long addr, unsigned long tag)
72{
73 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
74 "membar #Sync"
75 : /* No outputs */
76 : "r" (tag), "r" (addr), "i" (ASI_DCACHE_TAG));
77}
78
79/* The instruction cache lines are flushed with this, but note that
80 * this does not flush the pipeline. It is possible for a line to
81 * get flushed but stale instructions to still be in the pipeline,
82 * a flush instruction (to any address) is sufficient to handle
83 * this issue after the line is invalidated.
84 */
85static inline void spitfire_put_icache_tag(unsigned long addr, unsigned long tag)
86{
87 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
88 "membar #Sync"
89 : /* No outputs */
90 : "r" (tag), "r" (addr), "i" (ASI_IC_TAG));
91}
92
93static inline unsigned long spitfire_get_dtlb_data(int entry)
94{
95 unsigned long data;
96
97 __asm__ __volatile__("ldxa [%1] %2, %0"
98 : "=r" (data)
99 : "r" (entry << 3), "i" (ASI_DTLB_DATA_ACCESS));
100
101 /* Clear TTE diag bits. */
102 data &= ~0x0003fe0000000000UL;
103
104 return data;
105}
106
107static inline unsigned long spitfire_get_dtlb_tag(int entry)
108{
109 unsigned long tag;
110
111 __asm__ __volatile__("ldxa [%1] %2, %0"
112 : "=r" (tag)
113 : "r" (entry << 3), "i" (ASI_DTLB_TAG_READ));
114 return tag;
115}
116
117static inline void spitfire_put_dtlb_data(int entry, unsigned long data)
118{
119 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
120 "membar #Sync"
121 : /* No outputs */
122 : "r" (data), "r" (entry << 3),
123 "i" (ASI_DTLB_DATA_ACCESS));
124}
125
126static inline unsigned long spitfire_get_itlb_data(int entry)
127{
128 unsigned long data;
129
130 __asm__ __volatile__("ldxa [%1] %2, %0"
131 : "=r" (data)
132 : "r" (entry << 3), "i" (ASI_ITLB_DATA_ACCESS));
133
134 /* Clear TTE diag bits. */
135 data &= ~0x0003fe0000000000UL;
136
137 return data;
138}
139
140static inline unsigned long spitfire_get_itlb_tag(int entry)
141{
142 unsigned long tag;
143
144 __asm__ __volatile__("ldxa [%1] %2, %0"
145 : "=r" (tag)
146 : "r" (entry << 3), "i" (ASI_ITLB_TAG_READ));
147 return tag;
148}
149
150static inline void spitfire_put_itlb_data(int entry, unsigned long data)
151{
152 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
153 "membar #Sync"
154 : /* No outputs */
155 : "r" (data), "r" (entry << 3),
156 "i" (ASI_ITLB_DATA_ACCESS));
157}
158
159static inline void spitfire_flush_dtlb_nucleus_page(unsigned long page)
160{
161 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
162 "membar #Sync"
163 : /* No outputs */
164 : "r" (page | 0x20), "i" (ASI_DMMU_DEMAP));
165}
166
167static inline void spitfire_flush_itlb_nucleus_page(unsigned long page)
168{
169 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
170 "membar #Sync"
171 : /* No outputs */
172 : "r" (page | 0x20), "i" (ASI_IMMU_DEMAP));
173}
174
175/* Cheetah has "all non-locked" tlb flushes. */
176static inline void cheetah_flush_dtlb_all(void)
177{
178 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
179 "membar #Sync"
180 : /* No outputs */
181 : "r" (0x80), "i" (ASI_DMMU_DEMAP));
182}
183
184static inline void cheetah_flush_itlb_all(void)
185{
186 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
187 "membar #Sync"
188 : /* No outputs */
189 : "r" (0x80), "i" (ASI_IMMU_DEMAP));
190}
191
192/* Cheetah has a 4-tlb layout so direct access is a bit different.
193 * The first two TLBs are fully assosciative, hold 16 entries, and are
194 * used only for locked and >8K sized translations. One exists for
195 * data accesses and one for instruction accesses.
196 *
197 * The third TLB is for data accesses to 8K non-locked translations, is
198 * 2 way assosciative, and holds 512 entries. The fourth TLB is for
199 * instruction accesses to 8K non-locked translations, is 2 way
200 * assosciative, and holds 128 entries.
201 *
202 * Cheetah has some bug where bogus data can be returned from
203 * ASI_{D,I}TLB_DATA_ACCESS loads, doing the load twice fixes
204 * the problem for me. -DaveM
205 */
206static inline unsigned long cheetah_get_ldtlb_data(int entry)
207{
208 unsigned long data;
209
210 __asm__ __volatile__("ldxa [%1] %2, %%g0\n\t"
211 "ldxa [%1] %2, %0"
212 : "=r" (data)
213 : "r" ((0 << 16) | (entry << 3)),
214 "i" (ASI_DTLB_DATA_ACCESS));
215
216 return data;
217}
218
219static inline unsigned long cheetah_get_litlb_data(int entry)
220{
221 unsigned long data;
222
223 __asm__ __volatile__("ldxa [%1] %2, %%g0\n\t"
224 "ldxa [%1] %2, %0"
225 : "=r" (data)
226 : "r" ((0 << 16) | (entry << 3)),
227 "i" (ASI_ITLB_DATA_ACCESS));
228
229 return data;
230}
231
232static inline unsigned long cheetah_get_ldtlb_tag(int entry)
233{
234 unsigned long tag;
235
236 __asm__ __volatile__("ldxa [%1] %2, %0"
237 : "=r" (tag)
238 : "r" ((0 << 16) | (entry << 3)),
239 "i" (ASI_DTLB_TAG_READ));
240
241 return tag;
242}
243
244static inline unsigned long cheetah_get_litlb_tag(int entry)
245{
246 unsigned long tag;
247
248 __asm__ __volatile__("ldxa [%1] %2, %0"
249 : "=r" (tag)
250 : "r" ((0 << 16) | (entry << 3)),
251 "i" (ASI_ITLB_TAG_READ));
252
253 return tag;
254}
255
256static inline void cheetah_put_ldtlb_data(int entry, unsigned long data)
257{
258 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
259 "membar #Sync"
260 : /* No outputs */
261 : "r" (data),
262 "r" ((0 << 16) | (entry << 3)),
263 "i" (ASI_DTLB_DATA_ACCESS));
264}
265
266static inline void cheetah_put_litlb_data(int entry, unsigned long data)
267{
268 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
269 "membar #Sync"
270 : /* No outputs */
271 : "r" (data),
272 "r" ((0 << 16) | (entry << 3)),
273 "i" (ASI_ITLB_DATA_ACCESS));
274}
275
276static inline unsigned long cheetah_get_dtlb_data(int entry, int tlb)
277{
278 unsigned long data;
279
280 __asm__ __volatile__("ldxa [%1] %2, %%g0\n\t"
281 "ldxa [%1] %2, %0"
282 : "=r" (data)
283 : "r" ((tlb << 16) | (entry << 3)), "i" (ASI_DTLB_DATA_ACCESS));
284
285 return data;
286}
287
288static inline unsigned long cheetah_get_dtlb_tag(int entry, int tlb)
289{
290 unsigned long tag;
291
292 __asm__ __volatile__("ldxa [%1] %2, %0"
293 : "=r" (tag)
294 : "r" ((tlb << 16) | (entry << 3)), "i" (ASI_DTLB_TAG_READ));
295 return tag;
296}
297
298static inline void cheetah_put_dtlb_data(int entry, unsigned long data, int tlb)
299{
300 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
301 "membar #Sync"
302 : /* No outputs */
303 : "r" (data),
304 "r" ((tlb << 16) | (entry << 3)),
305 "i" (ASI_DTLB_DATA_ACCESS));
306}
307
308static inline unsigned long cheetah_get_itlb_data(int entry)
309{
310 unsigned long data;
311
312 __asm__ __volatile__("ldxa [%1] %2, %%g0\n\t"
313 "ldxa [%1] %2, %0"
314 : "=r" (data)
315 : "r" ((2 << 16) | (entry << 3)),
316 "i" (ASI_ITLB_DATA_ACCESS));
317
318 return data;
319}
320
321static inline unsigned long cheetah_get_itlb_tag(int entry)
322{
323 unsigned long tag;
324
325 __asm__ __volatile__("ldxa [%1] %2, %0"
326 : "=r" (tag)
327 : "r" ((2 << 16) | (entry << 3)), "i" (ASI_ITLB_TAG_READ));
328 return tag;
329}
330
331static inline void cheetah_put_itlb_data(int entry, unsigned long data)
332{
333 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
334 "membar #Sync"
335 : /* No outputs */
336 : "r" (data), "r" ((2 << 16) | (entry << 3)),
337 "i" (ASI_ITLB_DATA_ACCESS));
338}
339
340#endif /* !(__ASSEMBLY__) */
341
342#endif /* !(_SPARC64_SPITFIRE_H) */
diff --git a/include/asm-sparc/sstate.h b/include/asm-sparc/sstate.h
deleted file mode 100644
index a7c35dbcb28..00000000000
--- a/include/asm-sparc/sstate.h
+++ /dev/null
@@ -1,13 +0,0 @@
1#ifndef _SPARC64_SSTATE_H
2#define _SPARC64_SSTATE_H
3
4extern void sstate_booting(void);
5extern void sstate_running(void);
6extern void sstate_halt(void);
7extern void sstate_poweroff(void);
8extern void sstate_panic(void);
9extern void sstate_reboot(void);
10
11extern void sun4v_sstate_init(void);
12
13#endif /* _SPARC64_SSTATE_H */
diff --git a/include/asm-sparc/stacktrace.h b/include/asm-sparc/stacktrace.h
deleted file mode 100644
index 6cee39adf6d..00000000000
--- a/include/asm-sparc/stacktrace.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _SPARC64_STACKTRACE_H
2#define _SPARC64_STACKTRACE_H
3
4extern void stack_trace_flush(void);
5
6#endif /* _SPARC64_STACKTRACE_H */
diff --git a/include/asm-sparc/starfire.h b/include/asm-sparc/starfire.h
deleted file mode 100644
index 07bafd31e33..00000000000
--- a/include/asm-sparc/starfire.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * starfire.h: Group all starfire specific code together.
3 *
4 * Copyright (C) 2000 Anton Blanchard (anton@samba.org)
5 */
6
7#ifndef _SPARC64_STARFIRE_H
8#define _SPARC64_STARFIRE_H
9
10#ifndef __ASSEMBLY__
11
12extern int this_is_starfire;
13
14extern void check_if_starfire(void);
15extern void starfire_cpu_setup(void);
16extern int starfire_hard_smp_processor_id(void);
17extern void starfire_hookup(int);
18extern unsigned int starfire_translate(unsigned long imap, unsigned int upaid);
19
20#endif
21#endif
diff --git a/include/asm-sparc/stat.h b/include/asm-sparc/stat.h
deleted file mode 100644
index 9fdcaf8c9cd..00000000000
--- a/include/asm-sparc/stat.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_STAT_H
2#define ___ASM_SPARC_STAT_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/stat_64.h>
5#else
6#include <asm-sparc/stat_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/stat_32.h b/include/asm-sparc/stat_32.h
deleted file mode 100644
index 2299e1d5d94..00000000000
--- a/include/asm-sparc/stat_32.h
+++ /dev/null
@@ -1,76 +0,0 @@
1#ifndef _SPARC_STAT_H
2#define _SPARC_STAT_H
3
4#include <linux/types.h>
5
6struct __old_kernel_stat {
7 unsigned short st_dev;
8 unsigned short st_ino;
9 unsigned short st_mode;
10 unsigned short st_nlink;
11 unsigned short st_uid;
12 unsigned short st_gid;
13 unsigned short st_rdev;
14 unsigned long st_size;
15 unsigned long st_atime;
16 unsigned long st_mtime;
17 unsigned long st_ctime;
18};
19
20struct stat {
21 unsigned short st_dev;
22 unsigned long st_ino;
23 unsigned short st_mode;
24 short st_nlink;
25 unsigned short st_uid;
26 unsigned short st_gid;
27 unsigned short st_rdev;
28 long st_size;
29 long st_atime;
30 unsigned long st_atime_nsec;
31 long st_mtime;
32 unsigned long st_mtime_nsec;
33 long st_ctime;
34 unsigned long st_ctime_nsec;
35 long st_blksize;
36 long st_blocks;
37 unsigned long __unused4[2];
38};
39
40#define STAT_HAVE_NSEC 1
41
42struct stat64 {
43 unsigned long long st_dev;
44
45 unsigned long long st_ino;
46
47 unsigned int st_mode;
48 unsigned int st_nlink;
49
50 unsigned int st_uid;
51 unsigned int st_gid;
52
53 unsigned long long st_rdev;
54
55 unsigned char __pad3[8];
56
57 long long st_size;
58 unsigned int st_blksize;
59
60 unsigned char __pad4[8];
61 unsigned int st_blocks;
62
63 unsigned int st_atime;
64 unsigned int st_atime_nsec;
65
66 unsigned int st_mtime;
67 unsigned int st_mtime_nsec;
68
69 unsigned int st_ctime;
70 unsigned int st_ctime_nsec;
71
72 unsigned int __unused4;
73 unsigned int __unused5;
74};
75
76#endif
diff --git a/include/asm-sparc/stat_64.h b/include/asm-sparc/stat_64.h
deleted file mode 100644
index 9650fdea847..00000000000
--- a/include/asm-sparc/stat_64.h
+++ /dev/null
@@ -1,47 +0,0 @@
1#ifndef _SPARC64_STAT_H
2#define _SPARC64_STAT_H
3
4#include <linux/types.h>
5
6struct stat {
7 unsigned st_dev;
8 ino_t st_ino;
9 mode_t st_mode;
10 short st_nlink;
11 uid_t st_uid;
12 gid_t st_gid;
13 unsigned st_rdev;
14 off_t st_size;
15 time_t st_atime;
16 time_t st_mtime;
17 time_t st_ctime;
18 off_t st_blksize;
19 off_t st_blocks;
20 unsigned long __unused4[2];
21};
22
23struct stat64 {
24 unsigned long st_dev;
25 unsigned long st_ino;
26 unsigned long st_nlink;
27
28 unsigned int st_mode;
29 unsigned int st_uid;
30 unsigned int st_gid;
31 unsigned int __pad0;
32
33 unsigned long st_rdev;
34 long st_size;
35 long st_blksize;
36 long st_blocks;
37
38 unsigned long st_atime;
39 unsigned long st_atime_nsec;
40 unsigned long st_mtime;
41 unsigned long st_mtime_nsec;
42 unsigned long st_ctime;
43 unsigned long st_ctime_nsec;
44 long __unused[3];
45};
46
47#endif
diff --git a/include/asm-sparc/statfs.h b/include/asm-sparc/statfs.h
deleted file mode 100644
index a70cc52e701..00000000000
--- a/include/asm-sparc/statfs.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_STATFS_H
2#define ___ASM_SPARC_STATFS_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/statfs_64.h>
5#else
6#include <asm-sparc/statfs_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/statfs_32.h b/include/asm-sparc/statfs_32.h
deleted file mode 100644
index 304520fa886..00000000000
--- a/include/asm-sparc/statfs_32.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _SPARC_STATFS_H
2#define _SPARC_STATFS_H
3
4#include <asm-generic/statfs.h>
5
6#endif
diff --git a/include/asm-sparc/statfs_64.h b/include/asm-sparc/statfs_64.h
deleted file mode 100644
index 79b3c890a5f..00000000000
--- a/include/asm-sparc/statfs_64.h
+++ /dev/null
@@ -1,54 +0,0 @@
1#ifndef _SPARC64_STATFS_H
2#define _SPARC64_STATFS_H
3
4#ifndef __KERNEL_STRICT_NAMES
5
6#include <linux/types.h>
7
8typedef __kernel_fsid_t fsid_t;
9
10#endif
11
12struct statfs {
13 long f_type;
14 long f_bsize;
15 long f_blocks;
16 long f_bfree;
17 long f_bavail;
18 long f_files;
19 long f_ffree;
20 __kernel_fsid_t f_fsid;
21 long f_namelen;
22 long f_frsize;
23 long f_spare[5];
24};
25
26struct statfs64 {
27 long f_type;
28 long f_bsize;
29 long f_blocks;
30 long f_bfree;
31 long f_bavail;
32 long f_files;
33 long f_ffree;
34 __kernel_fsid_t f_fsid;
35 long f_namelen;
36 long f_frsize;
37 long f_spare[5];
38};
39
40struct compat_statfs64 {
41 __u32 f_type;
42 __u32 f_bsize;
43 __u64 f_blocks;
44 __u64 f_bfree;
45 __u64 f_bavail;
46 __u64 f_files;
47 __u64 f_ffree;
48 __kernel_fsid_t f_fsid;
49 __u32 f_namelen;
50 __u32 f_frsize;
51 __u32 f_spare[5];
52};
53
54#endif
diff --git a/include/asm-sparc/string.h b/include/asm-sparc/string.h
deleted file mode 100644
index 14c04c7697a..00000000000
--- a/include/asm-sparc/string.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_STRING_H
2#define ___ASM_SPARC_STRING_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/string_64.h>
5#else
6#include <asm-sparc/string_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/string_32.h b/include/asm-sparc/string_32.h
deleted file mode 100644
index 6c5fddb7e6b..00000000000
--- a/include/asm-sparc/string_32.h
+++ /dev/null
@@ -1,205 +0,0 @@
1/*
2 * string.h: External definitions for optimized assembly string
3 * routines for the Linux Kernel.
4 *
5 * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
6 * Copyright (C) 1996,1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
7 */
8
9#ifndef __SPARC_STRING_H__
10#define __SPARC_STRING_H__
11
12#include <asm/page.h>
13
14/* Really, userland/ksyms should not see any of this stuff. */
15
16#ifdef __KERNEL__
17
18extern void __memmove(void *,const void *,__kernel_size_t);
19extern __kernel_size_t __memcpy(void *,const void *,__kernel_size_t);
20extern __kernel_size_t __memset(void *,int,__kernel_size_t);
21
22#ifndef EXPORT_SYMTAB_STROPS
23
24/* First the mem*() things. */
25#define __HAVE_ARCH_MEMMOVE
26#undef memmove
27#define memmove(_to, _from, _n) \
28({ \
29 void *_t = (_to); \
30 __memmove(_t, (_from), (_n)); \
31 _t; \
32})
33
34#define __HAVE_ARCH_MEMCPY
35
36static inline void *__constant_memcpy(void *to, const void *from, __kernel_size_t n)
37{
38 extern void __copy_1page(void *, const void *);
39
40 if(n <= 32) {
41 __builtin_memcpy(to, from, n);
42 } else if (((unsigned int) to & 7) != 0) {
43 /* Destination is not aligned on the double-word boundary */
44 __memcpy(to, from, n);
45 } else {
46 switch(n) {
47 case PAGE_SIZE:
48 __copy_1page(to, from);
49 break;
50 default:
51 __memcpy(to, from, n);
52 break;
53 }
54 }
55 return to;
56}
57
58static inline void *__nonconstant_memcpy(void *to, const void *from, __kernel_size_t n)
59{
60 __memcpy(to, from, n);
61 return to;
62}
63
64#undef memcpy
65#define memcpy(t, f, n) \
66(__builtin_constant_p(n) ? \
67 __constant_memcpy((t),(f),(n)) : \
68 __nonconstant_memcpy((t),(f),(n)))
69
70#define __HAVE_ARCH_MEMSET
71
72static inline void *__constant_c_and_count_memset(void *s, char c, __kernel_size_t count)
73{
74 extern void bzero_1page(void *);
75 extern __kernel_size_t __bzero(void *, __kernel_size_t);
76
77 if(!c) {
78 if(count == PAGE_SIZE)
79 bzero_1page(s);
80 else
81 __bzero(s, count);
82 } else {
83 __memset(s, c, count);
84 }
85 return s;
86}
87
88static inline void *__constant_c_memset(void *s, char c, __kernel_size_t count)
89{
90 extern __kernel_size_t __bzero(void *, __kernel_size_t);
91
92 if(!c)
93 __bzero(s, count);
94 else
95 __memset(s, c, count);
96 return s;
97}
98
99static inline void *__nonconstant_memset(void *s, char c, __kernel_size_t count)
100{
101 __memset(s, c, count);
102 return s;
103}
104
105#undef memset
106#define memset(s, c, count) \
107(__builtin_constant_p(c) ? (__builtin_constant_p(count) ? \
108 __constant_c_and_count_memset((s), (c), (count)) : \
109 __constant_c_memset((s), (c), (count))) \
110 : __nonconstant_memset((s), (c), (count)))
111
112#define __HAVE_ARCH_MEMSCAN
113
114#undef memscan
115#define memscan(__arg0, __char, __arg2) \
116({ \
117 extern void *__memscan_zero(void *, size_t); \
118 extern void *__memscan_generic(void *, int, size_t); \
119 void *__retval, *__addr = (__arg0); \
120 size_t __size = (__arg2); \
121 \
122 if(__builtin_constant_p(__char) && !(__char)) \
123 __retval = __memscan_zero(__addr, __size); \
124 else \
125 __retval = __memscan_generic(__addr, (__char), __size); \
126 \
127 __retval; \
128})
129
130#define __HAVE_ARCH_MEMCMP
131extern int memcmp(const void *,const void *,__kernel_size_t);
132
133/* Now the str*() stuff... */
134#define __HAVE_ARCH_STRLEN
135extern __kernel_size_t strlen(const char *);
136
137#define __HAVE_ARCH_STRNCMP
138
139extern int __strncmp(const char *, const char *, __kernel_size_t);
140
141static inline int __constant_strncmp(const char *src, const char *dest, __kernel_size_t count)
142{
143 register int retval;
144 switch(count) {
145 case 0: return 0;
146 case 1: return (src[0] - dest[0]);
147 case 2: retval = (src[0] - dest[0]);
148 if(!retval && src[0])
149 retval = (src[1] - dest[1]);
150 return retval;
151 case 3: retval = (src[0] - dest[0]);
152 if(!retval && src[0]) {
153 retval = (src[1] - dest[1]);
154 if(!retval && src[1])
155 retval = (src[2] - dest[2]);
156 }
157 return retval;
158 case 4: retval = (src[0] - dest[0]);
159 if(!retval && src[0]) {
160 retval = (src[1] - dest[1]);
161 if(!retval && src[1]) {
162 retval = (src[2] - dest[2]);
163 if (!retval && src[2])
164 retval = (src[3] - dest[3]);
165 }
166 }
167 return retval;
168 case 5: retval = (src[0] - dest[0]);
169 if(!retval && src[0]) {
170 retval = (src[1] - dest[1]);
171 if(!retval && src[1]) {
172 retval = (src[2] - dest[2]);
173 if (!retval && src[2]) {
174 retval = (src[3] - dest[3]);
175 if (!retval && src[3])
176 retval = (src[4] - dest[4]);
177 }
178 }
179 }
180 return retval;
181 default:
182 retval = (src[0] - dest[0]);
183 if(!retval && src[0]) {
184 retval = (src[1] - dest[1]);
185 if(!retval && src[1]) {
186 retval = (src[2] - dest[2]);
187 if(!retval && src[2])
188 retval = __strncmp(src+3,dest+3,count-3);
189 }
190 }
191 return retval;
192 }
193}
194
195#undef strncmp
196#define strncmp(__arg0, __arg1, __arg2) \
197(__builtin_constant_p(__arg2) ? \
198 __constant_strncmp(__arg0, __arg1, __arg2) : \
199 __strncmp(__arg0, __arg1, __arg2))
200
201#endif /* !EXPORT_SYMTAB_STROPS */
202
203#endif /* __KERNEL__ */
204
205#endif /* !(__SPARC_STRING_H__) */
diff --git a/include/asm-sparc/string_64.h b/include/asm-sparc/string_64.h
deleted file mode 100644
index 43161f2d17e..00000000000
--- a/include/asm-sparc/string_64.h
+++ /dev/null
@@ -1,83 +0,0 @@
1/*
2 * string.h: External definitions for optimized assembly string
3 * routines for the Linux Kernel.
4 *
5 * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
6 * Copyright (C) 1996,1997,1999 Jakub Jelinek (jakub@redhat.com)
7 */
8
9#ifndef __SPARC64_STRING_H__
10#define __SPARC64_STRING_H__
11
12/* Really, userland/ksyms should not see any of this stuff. */
13
14#ifdef __KERNEL__
15
16#include <asm/asi.h>
17
18extern void *__memset(void *,int,__kernel_size_t);
19
20#ifndef EXPORT_SYMTAB_STROPS
21
22/* First the mem*() things. */
23#define __HAVE_ARCH_MEMMOVE
24extern void *memmove(void *, const void *, __kernel_size_t);
25
26#define __HAVE_ARCH_MEMCPY
27extern void *memcpy(void *, const void *, __kernel_size_t);
28
29#define __HAVE_ARCH_MEMSET
30extern void *__builtin_memset(void *,int,__kernel_size_t);
31
32static inline void *__constant_memset(void *s, int c, __kernel_size_t count)
33{
34 extern __kernel_size_t __bzero(void *, __kernel_size_t);
35
36 if (!c) {
37 __bzero(s, count);
38 return s;
39 } else
40 return __memset(s, c, count);
41}
42
43#undef memset
44#define memset(s, c, count) \
45((__builtin_constant_p(count) && (count) <= 32) ? \
46 __builtin_memset((s), (c), (count)) : \
47 (__builtin_constant_p(c) ? \
48 __constant_memset((s), (c), (count)) : \
49 __memset((s), (c), (count))))
50
51#define __HAVE_ARCH_MEMSCAN
52
53#undef memscan
54#define memscan(__arg0, __char, __arg2) \
55({ \
56 extern void *__memscan_zero(void *, size_t); \
57 extern void *__memscan_generic(void *, int, size_t); \
58 void *__retval, *__addr = (__arg0); \
59 size_t __size = (__arg2); \
60 \
61 if(__builtin_constant_p(__char) && !(__char)) \
62 __retval = __memscan_zero(__addr, __size); \
63 else \
64 __retval = __memscan_generic(__addr, (__char), __size); \
65 \
66 __retval; \
67})
68
69#define __HAVE_ARCH_MEMCMP
70extern int memcmp(const void *,const void *,__kernel_size_t);
71
72/* Now the str*() stuff... */
73#define __HAVE_ARCH_STRLEN
74extern __kernel_size_t strlen(const char *);
75
76#define __HAVE_ARCH_STRNCMP
77extern int strncmp(const char *, const char *, __kernel_size_t);
78
79#endif /* !EXPORT_SYMTAB_STROPS */
80
81#endif /* __KERNEL__ */
82
83#endif /* !(__SPARC64_STRING_H__) */
diff --git a/include/asm-sparc/sun4paddr.h b/include/asm-sparc/sun4paddr.h
deleted file mode 100644
index d52985f19f4..00000000000
--- a/include/asm-sparc/sun4paddr.h
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * sun4paddr.h: Various physical addresses on sun4 machines
3 *
4 * Copyright (C) 1997 Anton Blanchard (anton@progsoc.uts.edu.au)
5 * Copyright (C) 1998 Chris Davis (cdavis@cois.on.ca)
6 *
7 * Now supports more sun4's
8 */
9
10#ifndef _SPARC_SUN4PADDR_H
11#define _SPARC_SUN4PADDR_H
12
13#define SUN4_IE_PHYSADDR 0xf5000000
14#define SUN4_UNUSED_PHYSADDR 0
15
16/* these work for me */
17#define SUN4_200_MEMREG_PHYSADDR 0xf4000000
18#define SUN4_200_CLOCK_PHYSADDR 0xf3000000
19#define SUN4_200_BWTWO_PHYSADDR 0xfd000000
20#define SUN4_200_ETH_PHYSADDR 0xf6000000
21#define SUN4_200_SI_PHYSADDR 0xff200000
22
23/* these were here before */
24#define SUN4_300_MEMREG_PHYSADDR 0xf4000000
25#define SUN4_300_CLOCK_PHYSADDR 0xf2000000
26#define SUN4_300_TIMER_PHYSADDR 0xef000000
27#define SUN4_300_ETH_PHYSADDR 0xf9000000
28#define SUN4_300_BWTWO_PHYSADDR 0xfb400000
29#define SUN4_300_DMA_PHYSADDR 0xfa001000
30#define SUN4_300_ESP_PHYSADDR 0xfa000000
31
32/* Are these right? */
33#define SUN4_400_MEMREG_PHYSADDR 0xf4000000
34#define SUN4_400_CLOCK_PHYSADDR 0xf2000000
35#define SUN4_400_TIMER_PHYSADDR 0xef000000
36#define SUN4_400_ETH_PHYSADDR 0xf9000000
37#define SUN4_400_BWTWO_PHYSADDR 0xfb400000
38#define SUN4_400_DMA_PHYSADDR 0xfa001000
39#define SUN4_400_ESP_PHYSADDR 0xfa000000
40
41/*
42 these are the actual values set and used in the code. Unused items set
43 to SUN_UNUSED_PHYSADDR
44 */
45
46extern int sun4_memreg_physaddr; /* memory register (ecc?) */
47extern int sun4_clock_physaddr; /* system clock */
48extern int sun4_timer_physaddr; /* timer, where applicable */
49extern int sun4_eth_physaddr; /* onboard ethernet (ie/le) */
50extern int sun4_si_physaddr; /* sun3 scsi adapter */
51extern int sun4_bwtwo_physaddr; /* onboard bw2 */
52extern int sun4_dma_physaddr; /* scsi dma */
53extern int sun4_esp_physaddr; /* esp scsi */
54extern int sun4_ie_physaddr; /* interrupt enable */
55
56#endif /* !(_SPARC_SUN4PADDR_H) */
diff --git a/include/asm-sparc/sun4prom.h b/include/asm-sparc/sun4prom.h
deleted file mode 100644
index 9c8b4cbf629..00000000000
--- a/include/asm-sparc/sun4prom.h
+++ /dev/null
@@ -1,83 +0,0 @@
1/*
2 * sun4prom.h -- interface to sun4 PROM monitor. We don't use most of this,
3 * so most of these are just placeholders.
4 */
5
6#ifndef _SUN4PROM_H_
7#define _SUN4PROM_H_
8
9/*
10 * Although this looks similar to an romvec for a OpenProm machine, it is
11 * actually closer to what was used in the Sun2 and Sun3.
12 *
13 * V2 entries exist only in version 2 PROMs and later, V3 in version 3 and later.
14 *
15 * Many of the function prototypes are guesses. Some are certainly wrong.
16 * Use with care.
17 */
18
19typedef struct {
20 char *initSP; /* Initial system stack ptr */
21 void (*startmon)(void); /* Initial PC for hardware */
22 int *diagberr; /* Bus err handler for diags */
23 struct linux_arguments_v0 **bootParam; /* Info for bootstrapped pgm */
24 unsigned int *memorysize; /* Usable memory in bytes */
25 unsigned char (*getchar)(void); /* Get char from input device */
26 void (*putchar)(char); /* Put char to output device */
27 int (*mayget)(void); /* Maybe get char, or -1 */
28 int (*mayput)(int); /* Maybe put char, or -1 */
29 unsigned char *echo; /* Should getchar echo? */
30 unsigned char *insource; /* Input source selector */
31 unsigned char *outsink; /* Output sink selector */
32 int (*getkey)(void); /* Get next key if one exists */
33 void (*initgetkey)(void); /* Initialize get key */
34 unsigned int *translation; /* Kbd translation selector */
35 unsigned char *keybid; /* Keyboard ID byte */
36 int *screen_x; /* V2: Screen x pos (r/o) */
37 int *screen_y; /* V2: Screen y pos (r/o) */
38 struct keybuf *keybuf; /* Up/down keycode buffer */
39 char *monid; /* Monitor version ID */
40 void (*fbwritechar)(char); /* Write a character to FB */
41 int *fbAddr; /* Address of frame buffer */
42 char **font; /* Font table for FB */
43 void (*fbwritestr)(char *); /* Write string to FB */
44 void (*reboot)(char *); /* e.g. reboot("sd()vmlinux") */
45 unsigned char *linebuf; /* The line input buffer */
46 unsigned char **lineptr; /* Cur pointer into linebuf */
47 int *linesize; /* length of line in linebuf */
48 void (*getline)(char *); /* Get line from user */
49 unsigned char (*getnextchar)(void); /* Get next char from linebuf */
50 unsigned char (*peeknextchar)(void); /* Peek at next char */
51 int *fbthere; /* =1 if frame buffer there */
52 int (*getnum)(void); /* Grab hex num from line */
53 int (*printf)(char *, ...); /* See prom_printf() instead */
54 void (*printhex)(int); /* Format N digits in hex */
55 unsigned char *leds; /* RAM copy of LED register */
56 void (*setLEDs)(unsigned char *); /* Sets LED's and RAM copy */
57 void (*NMIaddr)(void *); /* Addr for level 7 vector */
58 void (*abortentry)(void); /* Entry for keyboard abort */
59 int *nmiclock; /* Counts up in msec */
60 int *FBtype; /* Frame buffer type */
61 unsigned int romvecversion; /* Version number for this romvec */
62 struct globram *globram; /* monitor global variables ??? */
63 void * kbdaddr; /* Addr of keyboard in use */
64 int *keyrinit; /* ms before kbd repeat */
65 unsigned char *keyrtick; /* ms between repetitions */
66 unsigned int *memoryavail; /* V1: Main mem usable size */
67 long *resetaddr; /* where to jump on a reset */
68 long *resetmap; /* pgmap entry for resetaddr */
69 void (*exittomon)(void); /* Exit from user program */
70 unsigned char **memorybitmap; /* V1: &{0 or &bits} */
71 void (*setcxsegmap)(int ctxt, char *va, int pmeg); /* Set seg in any context */
72 void (**vector_cmd)(void *); /* V2: Handler for 'v' cmd */
73 unsigned long *expectedtrapsig; /* V3: Location of the expected trap signal */
74 unsigned long *trapvectorbasetable; /* V3: Address of the trap vector table */
75 int unused1;
76 int unused2;
77 int unused3;
78 int unused4;
79} linux_sun4_romvec;
80
81extern linux_sun4_romvec *sun4_romvec;
82
83#endif /* _SUN4PROM_H_ */
diff --git a/include/asm-sparc/sunbpp.h b/include/asm-sparc/sunbpp.h
deleted file mode 100644
index 92ee1a8ff3a..00000000000
--- a/include/asm-sparc/sunbpp.h
+++ /dev/null
@@ -1,80 +0,0 @@
1/*
2 * include/asm-sparc/sunbpp.h
3 */
4
5#ifndef _ASM_SPARC_SUNBPP_H
6#define _ASM_SPARC_SUNBPP_H
7
8struct bpp_regs {
9 /* DMA registers */
10 __volatile__ __u32 p_csr; /* DMA Control/Status Register */
11 __volatile__ __u32 p_addr; /* Address Register */
12 __volatile__ __u32 p_bcnt; /* Byte Count Register */
13 __volatile__ __u32 p_tst_csr; /* Test Control/Status (DMA2 only) */
14 /* Parallel Port registers */
15 __volatile__ __u16 p_hcr; /* Hardware Configuration Register */
16 __volatile__ __u16 p_ocr; /* Operation Configuration Register */
17 __volatile__ __u8 p_dr; /* Parallel Data Register */
18 __volatile__ __u8 p_tcr; /* Transfer Control Register */
19 __volatile__ __u8 p_or; /* Output Register */
20 __volatile__ __u8 p_ir; /* Input Register */
21 __volatile__ __u16 p_icr; /* Interrupt Control Register */
22};
23
24/* P_HCR. Time is in increments of SBus clock. */
25#define P_HCR_TEST 0x8000 /* Allows buried counters to be read */
26#define P_HCR_DSW 0x7f00 /* Data strobe width (in ticks) */
27#define P_HCR_DDS 0x007f /* Data setup before strobe (in ticks) */
28
29/* P_OCR. */
30#define P_OCR_MEM_CLR 0x8000
31#define P_OCR_DATA_SRC 0x4000 /* ) */
32#define P_OCR_DS_DSEL 0x2000 /* ) Bidirectional */
33#define P_OCR_BUSY_DSEL 0x1000 /* ) selects */
34#define P_OCR_ACK_DSEL 0x0800 /* ) */
35#define P_OCR_EN_DIAG 0x0400
36#define P_OCR_BUSY_OP 0x0200 /* Busy operation */
37#define P_OCR_ACK_OP 0x0100 /* Ack operation */
38#define P_OCR_SRST 0x0080 /* Reset state machines. Not selfcleaning. */
39#define P_OCR_IDLE 0x0008 /* PP data transfer state machine is idle */
40#define P_OCR_V_ILCK 0x0002 /* Versatec faded. Zebra only. */
41#define P_OCR_EN_VER 0x0001 /* Enable Versatec (0 - enable). Zebra only. */
42
43/* P_TCR */
44#define P_TCR_DIR 0x08
45#define P_TCR_BUSY 0x04
46#define P_TCR_ACK 0x02
47#define P_TCR_DS 0x01 /* Strobe */
48
49/* P_OR */
50#define P_OR_V3 0x20 /* ) */
51#define P_OR_V2 0x10 /* ) on Zebra only */
52#define P_OR_V1 0x08 /* ) */
53#define P_OR_INIT 0x04
54#define P_OR_AFXN 0x02 /* Auto Feed */
55#define P_OR_SLCT_IN 0x01
56
57/* P_IR */
58#define P_IR_PE 0x04
59#define P_IR_SLCT 0x02
60#define P_IR_ERR 0x01
61
62/* P_ICR */
63#define P_DS_IRQ 0x8000 /* RW1 */
64#define P_ACK_IRQ 0x4000 /* RW1 */
65#define P_BUSY_IRQ 0x2000 /* RW1 */
66#define P_PE_IRQ 0x1000 /* RW1 */
67#define P_SLCT_IRQ 0x0800 /* RW1 */
68#define P_ERR_IRQ 0x0400 /* RW1 */
69#define P_DS_IRQ_EN 0x0200 /* RW Always on rising edge */
70#define P_ACK_IRQ_EN 0x0100 /* RW Always on rising edge */
71#define P_BUSY_IRP 0x0080 /* RW 1= rising edge */
72#define P_BUSY_IRQ_EN 0x0040 /* RW */
73#define P_PE_IRP 0x0020 /* RW 1= rising edge */
74#define P_PE_IRQ_EN 0x0010 /* RW */
75#define P_SLCT_IRP 0x0008 /* RW 1= rising edge */
76#define P_SLCT_IRQ_EN 0x0004 /* RW */
77#define P_ERR_IRP 0x0002 /* RW1 1= rising edge */
78#define P_ERR_IRQ_EN 0x0001 /* RW */
79
80#endif /* !(_ASM_SPARC_SUNBPP_H) */
diff --git a/include/asm-sparc/swift.h b/include/asm-sparc/swift.h
deleted file mode 100644
index e535061bf75..00000000000
--- a/include/asm-sparc/swift.h
+++ /dev/null
@@ -1,106 +0,0 @@
1/* swift.h: Specific definitions for the _broken_ Swift SRMMU
2 * MMU module.
3 *
4 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
5 */
6
7#ifndef _SPARC_SWIFT_H
8#define _SPARC_SWIFT_H
9
10/* Swift is so brain damaged, here is the mmu control register. */
11#define SWIFT_ST 0x00800000 /* SW tablewalk enable */
12#define SWIFT_WP 0x00400000 /* Watchpoint enable */
13
14/* Branch folding (buggy, disable on production systems!) */
15#define SWIFT_BF 0x00200000
16#define SWIFT_PMC 0x00180000 /* Page mode control */
17#define SWIFT_PE 0x00040000 /* Parity enable */
18#define SWIFT_PC 0x00020000 /* Parity control */
19#define SWIFT_AP 0x00010000 /* Graphics page mode control (TCX/SX) */
20#define SWIFT_AC 0x00008000 /* Alternate Cacheability (see viking.h) */
21#define SWIFT_BM 0x00004000 /* Boot mode */
22#define SWIFT_RC 0x00003c00 /* DRAM refresh control */
23#define SWIFT_IE 0x00000200 /* Instruction cache enable */
24#define SWIFT_DE 0x00000100 /* Data cache enable */
25#define SWIFT_SA 0x00000080 /* Store Allocate */
26#define SWIFT_NF 0x00000002 /* No fault mode */
27#define SWIFT_EN 0x00000001 /* MMU enable */
28
29/* Bits [13:5] select one of 512 instruction cache tags */
30static inline void swift_inv_insn_tag(unsigned long addr)
31{
32 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
33 : /* no outputs */
34 : "r" (addr), "i" (ASI_M_TXTC_TAG)
35 : "memory");
36}
37
38/* Bits [12:4] select one of 512 data cache tags */
39static inline void swift_inv_data_tag(unsigned long addr)
40{
41 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
42 : /* no outputs */
43 : "r" (addr), "i" (ASI_M_DATAC_TAG)
44 : "memory");
45}
46
47static inline void swift_flush_dcache(void)
48{
49 unsigned long addr;
50
51 for (addr = 0; addr < 0x2000; addr += 0x10)
52 swift_inv_data_tag(addr);
53}
54
55static inline void swift_flush_icache(void)
56{
57 unsigned long addr;
58
59 for (addr = 0; addr < 0x4000; addr += 0x20)
60 swift_inv_insn_tag(addr);
61}
62
63static inline void swift_idflash_clear(void)
64{
65 unsigned long addr;
66
67 for (addr = 0; addr < 0x2000; addr += 0x10) {
68 swift_inv_insn_tag(addr<<1);
69 swift_inv_data_tag(addr);
70 }
71}
72
73/* Swift is so broken, it isn't even safe to use the following. */
74static inline void swift_flush_page(unsigned long page)
75{
76 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
77 : /* no outputs */
78 : "r" (page), "i" (ASI_M_FLUSH_PAGE)
79 : "memory");
80}
81
82static inline void swift_flush_segment(unsigned long addr)
83{
84 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
85 : /* no outputs */
86 : "r" (addr), "i" (ASI_M_FLUSH_SEG)
87 : "memory");
88}
89
90static inline void swift_flush_region(unsigned long addr)
91{
92 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
93 : /* no outputs */
94 : "r" (addr), "i" (ASI_M_FLUSH_REGION)
95 : "memory");
96}
97
98static inline void swift_flush_context(void)
99{
100 __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
101 : /* no outputs */
102 : "i" (ASI_M_FLUSH_CTX)
103 : "memory");
104}
105
106#endif /* !(_SPARC_SWIFT_H) */
diff --git a/include/asm-sparc/syscalls.h b/include/asm-sparc/syscalls.h
deleted file mode 100644
index 45a43f637a1..00000000000
--- a/include/asm-sparc/syscalls.h
+++ /dev/null
@@ -1,13 +0,0 @@
1#ifndef _SPARC64_SYSCALLS_H
2#define _SPARC64_SYSCALLS_H
3
4struct pt_regs;
5
6extern asmlinkage long sparc_do_fork(unsigned long clone_flags,
7 unsigned long stack_start,
8 struct pt_regs *regs,
9 unsigned long stack_size);
10
11extern asmlinkage int sparc_execve(struct pt_regs *regs);
12
13#endif /* _SPARC64_SYSCALLS_H */
diff --git a/include/asm-sparc/sysen.h b/include/asm-sparc/sysen.h
deleted file mode 100644
index 6af34abde6e..00000000000
--- a/include/asm-sparc/sysen.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/*
2 * sysen.h: Bit fields within the "System Enable" register accessed via
3 * the ASI_CONTROL address space at address AC_SYSENABLE.
4 *
5 * Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu)
6 */
7
8#ifndef _SPARC_SYSEN_H
9#define _SPARC_SYSEN_H
10
11#define SENABLE_DVMA 0x20 /* enable dvma transfers */
12#define SENABLE_CACHE 0x10 /* enable VAC cache */
13#define SENABLE_RESET 0x04 /* reset whole machine, danger Will Robinson */
14
15#endif /* _SPARC_SYSEN_H */
diff --git a/include/asm-sparc/system.h b/include/asm-sparc/system.h
deleted file mode 100644
index 15e2a3bc4f6..00000000000
--- a/include/asm-sparc/system.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_SYSTEM_H
2#define ___ASM_SPARC_SYSTEM_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/system_64.h>
5#else
6#include <asm-sparc/system_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/system_32.h b/include/asm-sparc/system_32.h
deleted file mode 100644
index b4b024445fc..00000000000
--- a/include/asm-sparc/system_32.h
+++ /dev/null
@@ -1,288 +0,0 @@
1#ifndef __SPARC_SYSTEM_H
2#define __SPARC_SYSTEM_H
3
4#include <linux/kernel.h>
5#include <linux/threads.h> /* NR_CPUS */
6#include <linux/thread_info.h>
7
8#include <asm/page.h>
9#include <asm/psr.h>
10#include <asm/ptrace.h>
11#include <asm/btfixup.h>
12#include <asm/smp.h>
13
14#ifndef __ASSEMBLY__
15
16#include <linux/irqflags.h>
17
18/*
19 * Sparc (general) CPU types
20 */
21enum sparc_cpu {
22 sun4 = 0x00,
23 sun4c = 0x01,
24 sun4m = 0x02,
25 sun4d = 0x03,
26 sun4e = 0x04,
27 sun4u = 0x05, /* V8 ploos ploos */
28 sun_unknown = 0x06,
29 ap1000 = 0x07, /* almost a sun4m */
30};
31
32/* Really, userland should not be looking at any of this... */
33#ifdef __KERNEL__
34
35extern enum sparc_cpu sparc_cpu_model;
36
37#ifndef CONFIG_SUN4
38#define ARCH_SUN4C_SUN4 (sparc_cpu_model==sun4c)
39#define ARCH_SUN4 0
40#else
41#define ARCH_SUN4C_SUN4 1
42#define ARCH_SUN4 1
43#endif
44
45#define SUN4M_NCPUS 4 /* Architectural limit of sun4m. */
46
47extern char reboot_command[];
48
49extern struct thread_info *current_set[NR_CPUS];
50
51extern unsigned long empty_bad_page;
52extern unsigned long empty_bad_page_table;
53extern unsigned long empty_zero_page;
54
55extern void sun_do_break(void);
56extern int serial_console;
57extern int stop_a_enabled;
58
59static inline int con_is_present(void)
60{
61 return serial_console ? 0 : 1;
62}
63
64/* When a context switch happens we must flush all user windows so that
65 * the windows of the current process are flushed onto its stack. This
66 * way the windows are all clean for the next process and the stack
67 * frames are up to date.
68 */
69extern void flush_user_windows(void);
70extern void kill_user_windows(void);
71extern void synchronize_user_stack(void);
72extern void fpsave(unsigned long *fpregs, unsigned long *fsr,
73 void *fpqueue, unsigned long *fpqdepth);
74
75#ifdef CONFIG_SMP
76#define SWITCH_ENTER(prv) \
77 do { \
78 if (test_tsk_thread_flag(prv, TIF_USEDFPU)) { \
79 put_psr(get_psr() | PSR_EF); \
80 fpsave(&(prv)->thread.float_regs[0], &(prv)->thread.fsr, \
81 &(prv)->thread.fpqueue[0], &(prv)->thread.fpqdepth); \
82 clear_tsk_thread_flag(prv, TIF_USEDFPU); \
83 (prv)->thread.kregs->psr &= ~PSR_EF; \
84 } \
85 } while(0)
86
87#define SWITCH_DO_LAZY_FPU(next) /* */
88#else
89#define SWITCH_ENTER(prv) /* */
90#define SWITCH_DO_LAZY_FPU(nxt) \
91 do { \
92 if (last_task_used_math != (nxt)) \
93 (nxt)->thread.kregs->psr&=~PSR_EF; \
94 } while(0)
95#endif
96
97extern void flushw_all(void);
98
99/*
100 * Flush windows so that the VM switch which follows
101 * would not pull the stack from under us.
102 *
103 * SWITCH_ENTER and SWITH_DO_LAZY_FPU do not work yet (e.g. SMP does not work)
104 * XXX WTF is the above comment? Found in late teen 2.4.x.
105 */
106#define prepare_arch_switch(next) do { \
107 __asm__ __volatile__( \
108 ".globl\tflush_patch_switch\nflush_patch_switch:\n\t" \
109 "save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
110 "save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
111 "save %sp, -0x40, %sp\n\t" \
112 "restore; restore; restore; restore; restore; restore; restore"); \
113} while(0)
114
115 /* Much care has gone into this code, do not touch it.
116 *
117 * We need to loadup regs l0/l1 for the newly forked child
118 * case because the trap return path relies on those registers
119 * holding certain values, gcc is told that they are clobbered.
120 * Gcc needs registers for 3 values in and 1 value out, so we
121 * clobber every non-fixed-usage register besides l2/l3/o4/o5. -DaveM
122 *
123 * Hey Dave, that do not touch sign is too much of an incentive
124 * - Anton & Pete
125 */
126#define switch_to(prev, next, last) do { \
127 SWITCH_ENTER(prev); \
128 SWITCH_DO_LAZY_FPU(next); \
129 cpu_set(smp_processor_id(), next->active_mm->cpu_vm_mask); \
130 __asm__ __volatile__( \
131 "sethi %%hi(here - 0x8), %%o7\n\t" \
132 "mov %%g6, %%g3\n\t" \
133 "or %%o7, %%lo(here - 0x8), %%o7\n\t" \
134 "rd %%psr, %%g4\n\t" \
135 "std %%sp, [%%g6 + %4]\n\t" \
136 "rd %%wim, %%g5\n\t" \
137 "wr %%g4, 0x20, %%psr\n\t" \
138 "nop\n\t" \
139 "std %%g4, [%%g6 + %3]\n\t" \
140 "ldd [%2 + %3], %%g4\n\t" \
141 "mov %2, %%g6\n\t" \
142 ".globl patchme_store_new_current\n" \
143"patchme_store_new_current:\n\t" \
144 "st %2, [%1]\n\t" \
145 "wr %%g4, 0x20, %%psr\n\t" \
146 "nop\n\t" \
147 "nop\n\t" \
148 "nop\n\t" /* LEON needs all 3 nops: load to %sp depends on CWP. */ \
149 "ldd [%%g6 + %4], %%sp\n\t" \
150 "wr %%g5, 0x0, %%wim\n\t" \
151 "ldd [%%sp + 0x00], %%l0\n\t" \
152 "ldd [%%sp + 0x38], %%i6\n\t" \
153 "wr %%g4, 0x0, %%psr\n\t" \
154 "nop\n\t" \
155 "nop\n\t" \
156 "jmpl %%o7 + 0x8, %%g0\n\t" \
157 " ld [%%g3 + %5], %0\n\t" \
158 "here:\n" \
159 : "=&r" (last) \
160 : "r" (&(current_set[hard_smp_processor_id()])), \
161 "r" (task_thread_info(next)), \
162 "i" (TI_KPSR), \
163 "i" (TI_KSP), \
164 "i" (TI_TASK) \
165 : "g1", "g2", "g3", "g4", "g5", "g7", \
166 "l0", "l1", "l3", "l4", "l5", "l6", "l7", \
167 "i0", "i1", "i2", "i3", "i4", "i5", \
168 "o0", "o1", "o2", "o3", "o7"); \
169 } while(0)
170
171/* XXX Change this if we ever use a PSO mode kernel. */
172#define mb() __asm__ __volatile__ ("" : : : "memory")
173#define rmb() mb()
174#define wmb() mb()
175#define read_barrier_depends() do { } while(0)
176#define set_mb(__var, __value) do { __var = __value; mb(); } while(0)
177#define smp_mb() __asm__ __volatile__("":::"memory")
178#define smp_rmb() __asm__ __volatile__("":::"memory")
179#define smp_wmb() __asm__ __volatile__("":::"memory")
180#define smp_read_barrier_depends() do { } while(0)
181
182#define nop() __asm__ __volatile__ ("nop")
183
184/* This has special calling conventions */
185#ifndef CONFIG_SMP
186BTFIXUPDEF_CALL(void, ___xchg32, void)
187#endif
188
189static inline unsigned long xchg_u32(__volatile__ unsigned long *m, unsigned long val)
190{
191#ifdef CONFIG_SMP
192 __asm__ __volatile__("swap [%2], %0"
193 : "=&r" (val)
194 : "0" (val), "r" (m)
195 : "memory");
196 return val;
197#else
198 register unsigned long *ptr asm("g1");
199 register unsigned long ret asm("g2");
200
201 ptr = (unsigned long *) m;
202 ret = val;
203
204 /* Note: this is magic and the nop there is
205 really needed. */
206 __asm__ __volatile__(
207 "mov %%o7, %%g4\n\t"
208 "call ___f____xchg32\n\t"
209 " nop\n\t"
210 : "=&r" (ret)
211 : "0" (ret), "r" (ptr)
212 : "g3", "g4", "g7", "memory", "cc");
213
214 return ret;
215#endif
216}
217
218#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
219
220extern void __xchg_called_with_bad_pointer(void);
221
222static inline unsigned long __xchg(unsigned long x, __volatile__ void * ptr, int size)
223{
224 switch (size) {
225 case 4:
226 return xchg_u32(ptr, x);
227 };
228 __xchg_called_with_bad_pointer();
229 return x;
230}
231
232/* Emulate cmpxchg() the same way we emulate atomics,
233 * by hashing the object address and indexing into an array
234 * of spinlocks to get a bit of performance...
235 *
236 * See arch/sparc/lib/atomic32.c for implementation.
237 *
238 * Cribbed from <asm-parisc/atomic.h>
239 */
240#define __HAVE_ARCH_CMPXCHG 1
241
242/* bug catcher for when unsupported size is used - won't link */
243extern void __cmpxchg_called_with_bad_pointer(void);
244/* we only need to support cmpxchg of a u32 on sparc */
245extern unsigned long __cmpxchg_u32(volatile u32 *m, u32 old, u32 new_);
246
247/* don't worry...optimizer will get rid of most of this */
248static inline unsigned long
249__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new_, int size)
250{
251 switch (size) {
252 case 4:
253 return __cmpxchg_u32((u32 *)ptr, (u32)old, (u32)new_);
254 default:
255 __cmpxchg_called_with_bad_pointer();
256 break;
257 }
258 return old;
259}
260
261#define cmpxchg(ptr, o, n) \
262({ \
263 __typeof__(*(ptr)) _o_ = (o); \
264 __typeof__(*(ptr)) _n_ = (n); \
265 (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
266 (unsigned long)_n_, sizeof(*(ptr))); \
267})
268
269#include <asm-generic/cmpxchg-local.h>
270
271/*
272 * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
273 * them available.
274 */
275#define cmpxchg_local(ptr, o, n) \
276 ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
277 (unsigned long)(n), sizeof(*(ptr))))
278#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
279
280extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noreturn));
281
282#endif /* __KERNEL__ */
283
284#endif /* __ASSEMBLY__ */
285
286#define arch_align_stack(x) (x)
287
288#endif /* !(__SPARC_SYSTEM_H) */
diff --git a/include/asm-sparc/system_64.h b/include/asm-sparc/system_64.h
deleted file mode 100644
index db9e742a406..00000000000
--- a/include/asm-sparc/system_64.h
+++ /dev/null
@@ -1,355 +0,0 @@
1#ifndef __SPARC64_SYSTEM_H
2#define __SPARC64_SYSTEM_H
3
4#include <asm/ptrace.h>
5#include <asm/processor.h>
6#include <asm/visasm.h>
7
8#ifndef __ASSEMBLY__
9
10#include <linux/irqflags.h>
11#include <asm-generic/cmpxchg-local.h>
12
13/*
14 * Sparc (general) CPU types
15 */
16enum sparc_cpu {
17 sun4 = 0x00,
18 sun4c = 0x01,
19 sun4m = 0x02,
20 sun4d = 0x03,
21 sun4e = 0x04,
22 sun4u = 0x05, /* V8 ploos ploos */
23 sun_unknown = 0x06,
24 ap1000 = 0x07, /* almost a sun4m */
25};
26
27#define sparc_cpu_model sun4u
28
29/* This cannot ever be a sun4c nor sun4 :) That's just history. */
30#define ARCH_SUN4C_SUN4 0
31#define ARCH_SUN4 0
32
33extern char reboot_command[];
34
35/* These are here in an effort to more fully work around Spitfire Errata
36 * #51. Essentially, if a memory barrier occurs soon after a mispredicted
37 * branch, the chip can stop executing instructions until a trap occurs.
38 * Therefore, if interrupts are disabled, the chip can hang forever.
39 *
40 * It used to be believed that the memory barrier had to be right in the
41 * delay slot, but a case has been traced recently wherein the memory barrier
42 * was one instruction after the branch delay slot and the chip still hung.
43 * The offending sequence was the following in sym_wakeup_done() of the
44 * sym53c8xx_2 driver:
45 *
46 * call sym_ccb_from_dsa, 0
47 * movge %icc, 0, %l0
48 * brz,pn %o0, .LL1303
49 * mov %o0, %l2
50 * membar #LoadLoad
51 *
52 * The branch has to be mispredicted for the bug to occur. Therefore, we put
53 * the memory barrier explicitly into a "branch always, predicted taken"
54 * delay slot to avoid the problem case.
55 */
56#define membar_safe(type) \
57do { __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \
58 " membar " type "\n" \
59 "1:\n" \
60 : : : "memory"); \
61} while (0)
62
63#define mb() \
64 membar_safe("#LoadLoad | #LoadStore | #StoreStore | #StoreLoad")
65#define rmb() \
66 membar_safe("#LoadLoad")
67#define wmb() \
68 membar_safe("#StoreStore")
69#define membar_storeload() \
70 membar_safe("#StoreLoad")
71#define membar_storeload_storestore() \
72 membar_safe("#StoreLoad | #StoreStore")
73#define membar_storeload_loadload() \
74 membar_safe("#StoreLoad | #LoadLoad")
75#define membar_storestore_loadstore() \
76 membar_safe("#StoreStore | #LoadStore")
77
78#endif
79
80#define nop() __asm__ __volatile__ ("nop")
81
82#define read_barrier_depends() do { } while(0)
83#define set_mb(__var, __value) \
84 do { __var = __value; membar_storeload_storestore(); } while(0)
85
86#ifdef CONFIG_SMP
87#define smp_mb() mb()
88#define smp_rmb() rmb()
89#define smp_wmb() wmb()
90#define smp_read_barrier_depends() read_barrier_depends()
91#else
92#define smp_mb() __asm__ __volatile__("":::"memory")
93#define smp_rmb() __asm__ __volatile__("":::"memory")
94#define smp_wmb() __asm__ __volatile__("":::"memory")
95#define smp_read_barrier_depends() do { } while(0)
96#endif
97
98#define flushi(addr) __asm__ __volatile__ ("flush %0" : : "r" (addr) : "memory")
99
100#define flushw_all() __asm__ __volatile__("flushw")
101
102/* Performance counter register access. */
103#define read_pcr(__p) __asm__ __volatile__("rd %%pcr, %0" : "=r" (__p))
104#define write_pcr(__p) __asm__ __volatile__("wr %0, 0x0, %%pcr" : : "r" (__p))
105#define read_pic(__p) __asm__ __volatile__("rd %%pic, %0" : "=r" (__p))
106
107/* Blackbird errata workaround. See commentary in
108 * arch/sparc64/kernel/smp.c:smp_percpu_timer_interrupt()
109 * for more information.
110 */
111#define reset_pic() \
112 __asm__ __volatile__("ba,pt %xcc, 99f\n\t" \
113 ".align 64\n" \
114 "99:wr %g0, 0x0, %pic\n\t" \
115 "rd %pic, %g0")
116
117#ifndef __ASSEMBLY__
118
119extern void sun_do_break(void);
120extern int stop_a_enabled;
121
122extern void fault_in_user_windows(void);
123extern void synchronize_user_stack(void);
124
125extern void __flushw_user(void);
126#define flushw_user() __flushw_user()
127
128#define flush_user_windows flushw_user
129#define flush_register_windows flushw_all
130
131/* Don't hold the runqueue lock over context switch */
132#define __ARCH_WANT_UNLOCKED_CTXSW
133#define prepare_arch_switch(next) \
134do { \
135 flushw_all(); \
136} while (0)
137
138 /* See what happens when you design the chip correctly?
139 *
140 * We tell gcc we clobber all non-fixed-usage registers except
141 * for l0/l1. It will use one for 'next' and the other to hold
142 * the output value of 'last'. 'next' is not referenced again
143 * past the invocation of switch_to in the scheduler, so we need
144 * not preserve it's value. Hairy, but it lets us remove 2 loads
145 * and 2 stores in this critical code path. -DaveM
146 */
147#define switch_to(prev, next, last) \
148do { if (test_thread_flag(TIF_PERFCTR)) { \
149 unsigned long __tmp; \
150 read_pcr(__tmp); \
151 current_thread_info()->pcr_reg = __tmp; \
152 read_pic(__tmp); \
153 current_thread_info()->kernel_cntd0 += (unsigned int)(__tmp);\
154 current_thread_info()->kernel_cntd1 += ((__tmp) >> 32); \
155 } \
156 flush_tlb_pending(); \
157 save_and_clear_fpu(); \
158 /* If you are tempted to conditionalize the following */ \
159 /* so that ASI is only written if it changes, think again. */ \
160 __asm__ __volatile__("wr %%g0, %0, %%asi" \
161 : : "r" (__thread_flag_byte_ptr(task_thread_info(next))[TI_FLAG_BYTE_CURRENT_DS]));\
162 trap_block[current_thread_info()->cpu].thread = \
163 task_thread_info(next); \
164 __asm__ __volatile__( \
165 "mov %%g4, %%g7\n\t" \
166 "stx %%i6, [%%sp + 2047 + 0x70]\n\t" \
167 "stx %%i7, [%%sp + 2047 + 0x78]\n\t" \
168 "rdpr %%wstate, %%o5\n\t" \
169 "stx %%o6, [%%g6 + %6]\n\t" \
170 "stb %%o5, [%%g6 + %5]\n\t" \
171 "rdpr %%cwp, %%o5\n\t" \
172 "stb %%o5, [%%g6 + %8]\n\t" \
173 "mov %4, %%g6\n\t" \
174 "ldub [%4 + %8], %%g1\n\t" \
175 "wrpr %%g1, %%cwp\n\t" \
176 "ldx [%%g6 + %6], %%o6\n\t" \
177 "ldub [%%g6 + %5], %%o5\n\t" \
178 "ldub [%%g6 + %7], %%o7\n\t" \
179 "wrpr %%o5, 0x0, %%wstate\n\t" \
180 "ldx [%%sp + 2047 + 0x70], %%i6\n\t" \
181 "ldx [%%sp + 2047 + 0x78], %%i7\n\t" \
182 "ldx [%%g6 + %9], %%g4\n\t" \
183 "brz,pt %%o7, switch_to_pc\n\t" \
184 " mov %%g7, %0\n\t" \
185 "sethi %%hi(ret_from_syscall), %%g1\n\t" \
186 "jmpl %%g1 + %%lo(ret_from_syscall), %%g0\n\t" \
187 " nop\n\t" \
188 ".globl switch_to_pc\n\t" \
189 "switch_to_pc:\n\t" \
190 : "=&r" (last), "=r" (current), "=r" (current_thread_info_reg), \
191 "=r" (__local_per_cpu_offset) \
192 : "0" (task_thread_info(next)), \
193 "i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_NEW_CHILD), \
194 "i" (TI_CWP), "i" (TI_TASK) \
195 : "cc", \
196 "g1", "g2", "g3", "g7", \
197 "l1", "l2", "l3", "l4", "l5", "l6", "l7", \
198 "i0", "i1", "i2", "i3", "i4", "i5", \
199 "o0", "o1", "o2", "o3", "o4", "o5", "o7"); \
200 /* If you fuck with this, update ret_from_syscall code too. */ \
201 if (test_thread_flag(TIF_PERFCTR)) { \
202 write_pcr(current_thread_info()->pcr_reg); \
203 reset_pic(); \
204 } \
205} while(0)
206
207static inline unsigned long xchg32(__volatile__ unsigned int *m, unsigned int val)
208{
209 unsigned long tmp1, tmp2;
210
211 __asm__ __volatile__(
212" membar #StoreLoad | #LoadLoad\n"
213" mov %0, %1\n"
214"1: lduw [%4], %2\n"
215" cas [%4], %2, %0\n"
216" cmp %2, %0\n"
217" bne,a,pn %%icc, 1b\n"
218" mov %1, %0\n"
219" membar #StoreLoad | #StoreStore\n"
220 : "=&r" (val), "=&r" (tmp1), "=&r" (tmp2)
221 : "0" (val), "r" (m)
222 : "cc", "memory");
223 return val;
224}
225
226static inline unsigned long xchg64(__volatile__ unsigned long *m, unsigned long val)
227{
228 unsigned long tmp1, tmp2;
229
230 __asm__ __volatile__(
231" membar #StoreLoad | #LoadLoad\n"
232" mov %0, %1\n"
233"1: ldx [%4], %2\n"
234" casx [%4], %2, %0\n"
235" cmp %2, %0\n"
236" bne,a,pn %%xcc, 1b\n"
237" mov %1, %0\n"
238" membar #StoreLoad | #StoreStore\n"
239 : "=&r" (val), "=&r" (tmp1), "=&r" (tmp2)
240 : "0" (val), "r" (m)
241 : "cc", "memory");
242 return val;
243}
244
245#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
246
247extern void __xchg_called_with_bad_pointer(void);
248
249static inline unsigned long __xchg(unsigned long x, __volatile__ void * ptr,
250 int size)
251{
252 switch (size) {
253 case 4:
254 return xchg32(ptr, x);
255 case 8:
256 return xchg64(ptr, x);
257 };
258 __xchg_called_with_bad_pointer();
259 return x;
260}
261
262extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noreturn));
263
264/*
265 * Atomic compare and exchange. Compare OLD with MEM, if identical,
266 * store NEW in MEM. Return the initial value in MEM. Success is
267 * indicated by comparing RETURN with OLD.
268 */
269
270#define __HAVE_ARCH_CMPXCHG 1
271
272static inline unsigned long
273__cmpxchg_u32(volatile int *m, int old, int new)
274{
275 __asm__ __volatile__("membar #StoreLoad | #LoadLoad\n"
276 "cas [%2], %3, %0\n\t"
277 "membar #StoreLoad | #StoreStore"
278 : "=&r" (new)
279 : "0" (new), "r" (m), "r" (old)
280 : "memory");
281
282 return new;
283}
284
285static inline unsigned long
286__cmpxchg_u64(volatile long *m, unsigned long old, unsigned long new)
287{
288 __asm__ __volatile__("membar #StoreLoad | #LoadLoad\n"
289 "casx [%2], %3, %0\n\t"
290 "membar #StoreLoad | #StoreStore"
291 : "=&r" (new)
292 : "0" (new), "r" (m), "r" (old)
293 : "memory");
294
295 return new;
296}
297
298/* This function doesn't exist, so you'll get a linker error
299 if something tries to do an invalid cmpxchg(). */
300extern void __cmpxchg_called_with_bad_pointer(void);
301
302static inline unsigned long
303__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
304{
305 switch (size) {
306 case 4:
307 return __cmpxchg_u32(ptr, old, new);
308 case 8:
309 return __cmpxchg_u64(ptr, old, new);
310 }
311 __cmpxchg_called_with_bad_pointer();
312 return old;
313}
314
315#define cmpxchg(ptr,o,n) \
316 ({ \
317 __typeof__(*(ptr)) _o_ = (o); \
318 __typeof__(*(ptr)) _n_ = (n); \
319 (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
320 (unsigned long)_n_, sizeof(*(ptr))); \
321 })
322
323/*
324 * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
325 * them available.
326 */
327
328static inline unsigned long __cmpxchg_local(volatile void *ptr,
329 unsigned long old,
330 unsigned long new, int size)
331{
332 switch (size) {
333 case 4:
334 case 8: return __cmpxchg(ptr, old, new, size);
335 default:
336 return __cmpxchg_local_generic(ptr, old, new, size);
337 }
338
339 return old;
340}
341
342#define cmpxchg_local(ptr, o, n) \
343 ((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \
344 (unsigned long)(n), sizeof(*(ptr))))
345#define cmpxchg64_local(ptr, o, n) \
346 ({ \
347 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
348 cmpxchg_local((ptr), (o), (n)); \
349 })
350
351#endif /* !(__ASSEMBLY__) */
352
353#define arch_align_stack(x) (x)
354
355#endif /* !(__SPARC64_SYSTEM_H) */
diff --git a/include/asm-sparc/termbits.h b/include/asm-sparc/termbits.h
deleted file mode 100644
index d6ca3e2754f..00000000000
--- a/include/asm-sparc/termbits.h
+++ /dev/null
@@ -1,266 +0,0 @@
1#ifndef _SPARC_TERMBITS_H
2#define _SPARC_TERMBITS_H
3
4#include <linux/posix_types.h>
5
6typedef unsigned char cc_t;
7typedef unsigned int speed_t;
8
9#if defined(__sparc__) && defined(__arch64__)
10typedef unsigned int tcflag_t;
11#else
12typedef unsigned long tcflag_t;
13#endif
14
15#define NCC 8
16struct termio {
17 unsigned short c_iflag; /* input mode flags */
18 unsigned short c_oflag; /* output mode flags */
19 unsigned short c_cflag; /* control mode flags */
20 unsigned short c_lflag; /* local mode flags */
21 unsigned char c_line; /* line discipline */
22 unsigned char c_cc[NCC]; /* control characters */
23};
24
25#define NCCS 17
26struct termios {
27 tcflag_t c_iflag; /* input mode flags */
28 tcflag_t c_oflag; /* output mode flags */
29 tcflag_t c_cflag; /* control mode flags */
30 tcflag_t c_lflag; /* local mode flags */
31 cc_t c_line; /* line discipline */
32 cc_t c_cc[NCCS]; /* control characters */
33#ifdef __KERNEL__
34#define SIZEOF_USER_TERMIOS sizeof (struct termios) - (2*sizeof (cc_t))
35 cc_t _x_cc[2]; /* We need them to hold vmin/vtime */
36#endif
37};
38
39struct termios2 {
40 tcflag_t c_iflag; /* input mode flags */
41 tcflag_t c_oflag; /* output mode flags */
42 tcflag_t c_cflag; /* control mode flags */
43 tcflag_t c_lflag; /* local mode flags */
44 cc_t c_line; /* line discipline */
45 cc_t c_cc[NCCS]; /* control characters */
46 cc_t _x_cc[2]; /* padding to match ktermios */
47 speed_t c_ispeed; /* input speed */
48 speed_t c_ospeed; /* output speed */
49};
50
51struct ktermios {
52 tcflag_t c_iflag; /* input mode flags */
53 tcflag_t c_oflag; /* output mode flags */
54 tcflag_t c_cflag; /* control mode flags */
55 tcflag_t c_lflag; /* local mode flags */
56 cc_t c_line; /* line discipline */
57 cc_t c_cc[NCCS]; /* control characters */
58 cc_t _x_cc[2]; /* We need them to hold vmin/vtime */
59 speed_t c_ispeed; /* input speed */
60 speed_t c_ospeed; /* output speed */
61};
62
63/* c_cc characters */
64#define VINTR 0
65#define VQUIT 1
66#define VERASE 2
67#define VKILL 3
68#define VEOF 4
69#define VEOL 5
70#define VEOL2 6
71#define VSWTC 7
72#define VSTART 8
73#define VSTOP 9
74
75
76
77#define VSUSP 10
78#define VDSUSP 11 /* SunOS POSIX nicety I do believe... */
79#define VREPRINT 12
80#define VDISCARD 13
81#define VWERASE 14
82#define VLNEXT 15
83
84/* Kernel keeps vmin/vtime separated, user apps assume vmin/vtime is
85 * shared with eof/eol
86 */
87#ifdef __KERNEL__
88#define VMIN 16
89#define VTIME 17
90#else
91#define VMIN VEOF
92#define VTIME VEOL
93#endif
94
95/* c_iflag bits */
96#define IGNBRK 0x00000001
97#define BRKINT 0x00000002
98#define IGNPAR 0x00000004
99#define PARMRK 0x00000008
100#define INPCK 0x00000010
101#define ISTRIP 0x00000020
102#define INLCR 0x00000040
103#define IGNCR 0x00000080
104#define ICRNL 0x00000100
105#define IUCLC 0x00000200
106#define IXON 0x00000400
107#define IXANY 0x00000800
108#define IXOFF 0x00001000
109#define IMAXBEL 0x00002000
110#define IUTF8 0x00004000
111
112/* c_oflag bits */
113#define OPOST 0x00000001
114#define OLCUC 0x00000002
115#define ONLCR 0x00000004
116#define OCRNL 0x00000008
117#define ONOCR 0x00000010
118#define ONLRET 0x00000020
119#define OFILL 0x00000040
120#define OFDEL 0x00000080
121#define NLDLY 0x00000100
122#define NL0 0x00000000
123#define NL1 0x00000100
124#define CRDLY 0x00000600
125#define CR0 0x00000000
126#define CR1 0x00000200
127#define CR2 0x00000400
128#define CR3 0x00000600
129#define TABDLY 0x00001800
130#define TAB0 0x00000000
131#define TAB1 0x00000800
132#define TAB2 0x00001000
133#define TAB3 0x00001800
134#define XTABS 0x00001800
135#define BSDLY 0x00002000
136#define BS0 0x00000000
137#define BS1 0x00002000
138#define VTDLY 0x00004000
139#define VT0 0x00000000
140#define VT1 0x00004000
141#define FFDLY 0x00008000
142#define FF0 0x00000000
143#define FF1 0x00008000
144#define PAGEOUT 0x00010000 /* SUNOS specific */
145#define WRAP 0x00020000 /* SUNOS specific */
146
147/* c_cflag bit meaning */
148#define CBAUD 0x0000100f
149#define B0 0x00000000 /* hang up */
150#define B50 0x00000001
151#define B75 0x00000002
152#define B110 0x00000003
153#define B134 0x00000004
154#define B150 0x00000005
155#define B200 0x00000006
156#define B300 0x00000007
157#define B600 0x00000008
158#define B1200 0x00000009
159#define B1800 0x0000000a
160#define B2400 0x0000000b
161#define B4800 0x0000000c
162#define B9600 0x0000000d
163#define B19200 0x0000000e
164#define B38400 0x0000000f
165#define EXTA B19200
166#define EXTB B38400
167#define CSIZE 0x00000030
168#define CS5 0x00000000
169#define CS6 0x00000010
170#define CS7 0x00000020
171#define CS8 0x00000030
172#define CSTOPB 0x00000040
173#define CREAD 0x00000080
174#define PARENB 0x00000100
175#define PARODD 0x00000200
176#define HUPCL 0x00000400
177#define CLOCAL 0x00000800
178#define CBAUDEX 0x00001000
179/* We'll never see these speeds with the Zilogs, but for completeness... */
180#define BOTHER 0x00001000
181#define B57600 0x00001001
182#define B115200 0x00001002
183#define B230400 0x00001003
184#define B460800 0x00001004
185/* This is what we can do with the Zilogs. */
186#define B76800 0x00001005
187/* This is what we can do with the SAB82532. */
188#define B153600 0x00001006
189#define B307200 0x00001007
190#define B614400 0x00001008
191#define B921600 0x00001009
192/* And these are the rest... */
193#define B500000 0x0000100a
194#define B576000 0x0000100b
195#define B1000000 0x0000100c
196#define B1152000 0x0000100d
197#define B1500000 0x0000100e
198#define B2000000 0x0000100f
199/* These have totally bogus values and nobody uses them
200 so far. Later on we'd have to use say 0x10000x and
201 adjust CBAUD constant and drivers accordingly.
202#define B2500000 0x00001010
203#define B3000000 0x00001011
204#define B3500000 0x00001012
205#define B4000000 0x00001013 */
206#define CIBAUD 0x100f0000 /* input baud rate (not used) */
207#define CMSPAR 0x40000000 /* mark or space (stick) parity */
208#define CRTSCTS 0x80000000 /* flow control */
209
210#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
211
212/* c_lflag bits */
213#define ISIG 0x00000001
214#define ICANON 0x00000002
215#define XCASE 0x00000004
216#define ECHO 0x00000008
217#define ECHOE 0x00000010
218#define ECHOK 0x00000020
219#define ECHONL 0x00000040
220#define NOFLSH 0x00000080
221#define TOSTOP 0x00000100
222#define ECHOCTL 0x00000200
223#define ECHOPRT 0x00000400
224#define ECHOKE 0x00000800
225#define DEFECHO 0x00001000 /* SUNOS thing, what is it? */
226#define FLUSHO 0x00002000
227#define PENDIN 0x00004000
228#define IEXTEN 0x00008000
229
230/* modem lines */
231#define TIOCM_LE 0x001
232#define TIOCM_DTR 0x002
233#define TIOCM_RTS 0x004
234#define TIOCM_ST 0x008
235#define TIOCM_SR 0x010
236#define TIOCM_CTS 0x020
237#define TIOCM_CAR 0x040
238#define TIOCM_RNG 0x080
239#define TIOCM_DSR 0x100
240#define TIOCM_CD TIOCM_CAR
241#define TIOCM_RI TIOCM_RNG
242#define TIOCM_OUT1 0x2000
243#define TIOCM_OUT2 0x4000
244#define TIOCM_LOOP 0x8000
245
246/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
247#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */
248
249
250/* tcflow() and TCXONC use these */
251#define TCOOFF 0
252#define TCOON 1
253#define TCIOFF 2
254#define TCION 3
255
256/* tcflush() and TCFLSH use these */
257#define TCIFLUSH 0
258#define TCOFLUSH 1
259#define TCIOFLUSH 2
260
261/* tcsetattr uses these */
262#define TCSANOW 0
263#define TCSADRAIN 1
264#define TCSAFLUSH 2
265
266#endif /* !(_SPARC_TERMBITS_H) */
diff --git a/include/asm-sparc/termios.h b/include/asm-sparc/termios.h
deleted file mode 100644
index e8ba9539964..00000000000
--- a/include/asm-sparc/termios.h
+++ /dev/null
@@ -1,186 +0,0 @@
1#ifndef _SPARC_TERMIOS_H
2#define _SPARC_TERMIOS_H
3
4#include <asm/ioctls.h>
5#include <asm/termbits.h>
6
7#if defined(__KERNEL__) || defined(__DEFINE_BSD_TERMIOS)
8struct sgttyb {
9 char sg_ispeed;
10 char sg_ospeed;
11 char sg_erase;
12 char sg_kill;
13 short sg_flags;
14};
15
16struct tchars {
17 char t_intrc;
18 char t_quitc;
19 char t_startc;
20 char t_stopc;
21 char t_eofc;
22 char t_brkc;
23};
24
25struct ltchars {
26 char t_suspc;
27 char t_dsuspc;
28 char t_rprntc;
29 char t_flushc;
30 char t_werasc;
31 char t_lnextc;
32};
33#endif /* __KERNEL__ */
34
35struct winsize {
36 unsigned short ws_row;
37 unsigned short ws_col;
38 unsigned short ws_xpixel;
39 unsigned short ws_ypixel;
40};
41
42#ifdef __KERNEL__
43#include <linux/module.h>
44
45/*
46 * c_cc characters in the termio structure. Oh, how I love being
47 * backwardly compatible. Notice that character 4 and 5 are
48 * interpreted differently depending on whether ICANON is set in
49 * c_lflag. If it's set, they are used as _VEOF and _VEOL, otherwise
50 * as _VMIN and V_TIME. This is for compatibility with OSF/1 (which
51 * is compatible with sysV)...
52 */
53#define _VMIN 4
54#define _VTIME 5
55
56/* intr=^C quit=^\ erase=del kill=^U
57 eof=^D eol=\0 eol2=\0 sxtc=\0
58 start=^Q stop=^S susp=^Z dsusp=^Y
59 reprint=^R discard=^U werase=^W lnext=^V
60 vmin=\1 vtime=\0
61*/
62#define INIT_C_CC "\003\034\177\025\004\000\000\000\021\023\032\031\022\025\027\026\001"
63
64/*
65 * Translate a "termio" structure into a "termios". Ugh.
66 */
67#define user_termio_to_kernel_termios(termios, termio) \
68({ \
69 unsigned short tmp; \
70 int err; \
71 err = get_user(tmp, &(termio)->c_iflag); \
72 (termios)->c_iflag = (0xffff0000 & ((termios)->c_iflag)) | tmp; \
73 err |= get_user(tmp, &(termio)->c_oflag); \
74 (termios)->c_oflag = (0xffff0000 & ((termios)->c_oflag)) | tmp; \
75 err |= get_user(tmp, &(termio)->c_cflag); \
76 (termios)->c_cflag = (0xffff0000 & ((termios)->c_cflag)) | tmp; \
77 err |= get_user(tmp, &(termio)->c_lflag); \
78 (termios)->c_lflag = (0xffff0000 & ((termios)->c_lflag)) | tmp; \
79 err |= copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
80 err; \
81})
82
83/*
84 * Translate a "termios" structure into a "termio". Ugh.
85 *
86 * Note the "fun" _VMIN overloading.
87 */
88#define kernel_termios_to_user_termio(termio, termios) \
89({ \
90 int err; \
91 err = put_user((termios)->c_iflag, &(termio)->c_iflag); \
92 err |= put_user((termios)->c_oflag, &(termio)->c_oflag); \
93 err |= put_user((termios)->c_cflag, &(termio)->c_cflag); \
94 err |= put_user((termios)->c_lflag, &(termio)->c_lflag); \
95 err |= put_user((termios)->c_line, &(termio)->c_line); \
96 err |= copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
97 if (!((termios)->c_lflag & ICANON)) { \
98 err |= put_user((termios)->c_cc[VMIN], &(termio)->c_cc[_VMIN]); \
99 err |= put_user((termios)->c_cc[VTIME], &(termio)->c_cc[_VTIME]); \
100 } \
101 err; \
102})
103
104#define user_termios_to_kernel_termios(k, u) \
105({ \
106 int err; \
107 err = get_user((k)->c_iflag, &(u)->c_iflag); \
108 err |= get_user((k)->c_oflag, &(u)->c_oflag); \
109 err |= get_user((k)->c_cflag, &(u)->c_cflag); \
110 err |= get_user((k)->c_lflag, &(u)->c_lflag); \
111 err |= get_user((k)->c_line, &(u)->c_line); \
112 err |= copy_from_user((k)->c_cc, (u)->c_cc, NCCS); \
113 if ((k)->c_lflag & ICANON) { \
114 err |= get_user((k)->c_cc[VEOF], &(u)->c_cc[VEOF]); \
115 err |= get_user((k)->c_cc[VEOL], &(u)->c_cc[VEOL]); \
116 } else { \
117 err |= get_user((k)->c_cc[VMIN], &(u)->c_cc[_VMIN]); \
118 err |= get_user((k)->c_cc[VTIME], &(u)->c_cc[_VTIME]); \
119 } \
120 err |= get_user((k)->c_ispeed, &(u)->c_ispeed); \
121 err |= get_user((k)->c_ospeed, &(u)->c_ospeed); \
122 err; \
123})
124
125#define kernel_termios_to_user_termios(u, k) \
126({ \
127 int err; \
128 err = put_user((k)->c_iflag, &(u)->c_iflag); \
129 err |= put_user((k)->c_oflag, &(u)->c_oflag); \
130 err |= put_user((k)->c_cflag, &(u)->c_cflag); \
131 err |= put_user((k)->c_lflag, &(u)->c_lflag); \
132 err |= put_user((k)->c_line, &(u)->c_line); \
133 err |= copy_to_user((u)->c_cc, (k)->c_cc, NCCS); \
134 if (!((k)->c_lflag & ICANON)) { \
135 err |= put_user((k)->c_cc[VMIN], &(u)->c_cc[_VMIN]); \
136 err |= put_user((k)->c_cc[VTIME], &(u)->c_cc[_VTIME]); \
137 } else { \
138 err |= put_user((k)->c_cc[VEOF], &(u)->c_cc[VEOF]); \
139 err |= put_user((k)->c_cc[VEOL], &(u)->c_cc[VEOL]); \
140 } \
141 err |= put_user((k)->c_ispeed, &(u)->c_ispeed); \
142 err |= put_user((k)->c_ospeed, &(u)->c_ospeed); \
143 err; \
144})
145
146#define user_termios_to_kernel_termios_1(k, u) \
147({ \
148 int err; \
149 err = get_user((k)->c_iflag, &(u)->c_iflag); \
150 err |= get_user((k)->c_oflag, &(u)->c_oflag); \
151 err |= get_user((k)->c_cflag, &(u)->c_cflag); \
152 err |= get_user((k)->c_lflag, &(u)->c_lflag); \
153 err |= get_user((k)->c_line, &(u)->c_line); \
154 err |= copy_from_user((k)->c_cc, (u)->c_cc, NCCS); \
155 if ((k)->c_lflag & ICANON) { \
156 err |= get_user((k)->c_cc[VEOF], &(u)->c_cc[VEOF]); \
157 err |= get_user((k)->c_cc[VEOL], &(u)->c_cc[VEOL]); \
158 } else { \
159 err |= get_user((k)->c_cc[VMIN], &(u)->c_cc[_VMIN]); \
160 err |= get_user((k)->c_cc[VTIME], &(u)->c_cc[_VTIME]); \
161 } \
162 err; \
163})
164
165#define kernel_termios_to_user_termios_1(u, k) \
166({ \
167 int err; \
168 err = put_user((k)->c_iflag, &(u)->c_iflag); \
169 err |= put_user((k)->c_oflag, &(u)->c_oflag); \
170 err |= put_user((k)->c_cflag, &(u)->c_cflag); \
171 err |= put_user((k)->c_lflag, &(u)->c_lflag); \
172 err |= put_user((k)->c_line, &(u)->c_line); \
173 err |= copy_to_user((u)->c_cc, (k)->c_cc, NCCS); \
174 if (!((k)->c_lflag & ICANON)) { \
175 err |= put_user((k)->c_cc[VMIN], &(u)->c_cc[_VMIN]); \
176 err |= put_user((k)->c_cc[VTIME], &(u)->c_cc[_VTIME]); \
177 } else { \
178 err |= put_user((k)->c_cc[VEOF], &(u)->c_cc[VEOF]); \
179 err |= put_user((k)->c_cc[VEOL], &(u)->c_cc[VEOL]); \
180 } \
181 err; \
182})
183
184#endif /* __KERNEL__ */
185
186#endif /* _SPARC_TERMIOS_H */
diff --git a/include/asm-sparc/thread_info.h b/include/asm-sparc/thread_info.h
deleted file mode 100644
index 64155cf89f3..00000000000
--- a/include/asm-sparc/thread_info.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_THREAD_INFO_H
2#define ___ASM_SPARC_THREAD_INFO_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/thread_info_64.h>
5#else
6#include <asm-sparc/thread_info_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/thread_info_32.h b/include/asm-sparc/thread_info_32.h
deleted file mode 100644
index 2cf9db04405..00000000000
--- a/include/asm-sparc/thread_info_32.h
+++ /dev/null
@@ -1,153 +0,0 @@
1/*
2 * thread_info.h: sparc low-level thread information
3 * adapted from the ppc version by Pete Zaitcev, which was
4 * adapted from the i386 version by Paul Mackerras
5 *
6 * Copyright (C) 2002 David Howells (dhowells@redhat.com)
7 * Copyright (c) 2002 Pete Zaitcev (zaitcev@yahoo.com)
8 * - Incorporating suggestions made by Linus Torvalds and Dave Miller
9 */
10
11#ifndef _ASM_THREAD_INFO_H
12#define _ASM_THREAD_INFO_H
13
14#ifdef __KERNEL__
15
16#ifndef __ASSEMBLY__
17
18#include <asm/btfixup.h>
19#include <asm/ptrace.h>
20#include <asm/page.h>
21
22/*
23 * Low level task data.
24 *
25 * If you change this, change the TI_* offsets below to match.
26 */
27#define NSWINS 8
28struct thread_info {
29 unsigned long uwinmask;
30 struct task_struct *task; /* main task structure */
31 struct exec_domain *exec_domain; /* execution domain */
32 unsigned long flags; /* low level flags */
33 int cpu; /* cpu we're on */
34 int preempt_count; /* 0 => preemptable,
35 <0 => BUG */
36 int softirq_count;
37 int hardirq_count;
38
39 /* Context switch saved kernel state. */
40 unsigned long ksp; /* ... ksp __attribute__ ((aligned (8))); */
41 unsigned long kpc;
42 unsigned long kpsr;
43 unsigned long kwim;
44
45 /* A place to store user windows and stack pointers
46 * when the stack needs inspection.
47 */
48 struct reg_window reg_window[NSWINS]; /* align for ldd! */
49 unsigned long rwbuf_stkptrs[NSWINS];
50 unsigned long w_saved;
51
52 struct restart_block restart_block;
53};
54
55/*
56 * macros/functions for gaining access to the thread information structure
57 *
58 * preempt_count needs to be 1 initially, until the scheduler is functional.
59 */
60#define INIT_THREAD_INFO(tsk) \
61{ \
62 .uwinmask = 0, \
63 .task = &tsk, \
64 .exec_domain = &default_exec_domain, \
65 .flags = 0, \
66 .cpu = 0, \
67 .preempt_count = 1, \
68 .restart_block = { \
69 .fn = do_no_restart_syscall, \
70 }, \
71}
72
73#define init_thread_info (init_thread_union.thread_info)
74#define init_stack (init_thread_union.stack)
75
76/* how to get the thread information struct from C */
77register struct thread_info *current_thread_info_reg asm("g6");
78#define current_thread_info() (current_thread_info_reg)
79
80/*
81 * thread information allocation
82 */
83#if PAGE_SHIFT == 13
84#define THREAD_INFO_ORDER 0
85#else /* PAGE_SHIFT */
86#define THREAD_INFO_ORDER 1
87#endif
88
89#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
90
91BTFIXUPDEF_CALL(struct thread_info *, alloc_thread_info, void)
92#define alloc_thread_info(tsk) BTFIXUP_CALL(alloc_thread_info)()
93
94BTFIXUPDEF_CALL(void, free_thread_info, struct thread_info *)
95#define free_thread_info(ti) BTFIXUP_CALL(free_thread_info)(ti)
96
97#endif /* __ASSEMBLY__ */
98
99/*
100 * Size of kernel stack for each process.
101 * Observe the order of get_free_pages() in alloc_thread_info().
102 * The sun4 has 8K stack too, because it's short on memory, and 16K is a waste.
103 */
104#define THREAD_SIZE 8192
105
106/*
107 * Offsets in thread_info structure, used in assembly code
108 * The "#define REGWIN_SZ 0x40" was abolished, so no multiplications.
109 */
110#define TI_UWINMASK 0x00 /* uwinmask */
111#define TI_TASK 0x04
112#define TI_EXECDOMAIN 0x08 /* exec_domain */
113#define TI_FLAGS 0x0c
114#define TI_CPU 0x10
115#define TI_PREEMPT 0x14 /* preempt_count */
116#define TI_SOFTIRQ 0x18 /* softirq_count */
117#define TI_HARDIRQ 0x1c /* hardirq_count */
118#define TI_KSP 0x20 /* ksp */
119#define TI_KPC 0x24 /* kpc (ldd'ed with kpc) */
120#define TI_KPSR 0x28 /* kpsr */
121#define TI_KWIM 0x2c /* kwim (ldd'ed with kpsr) */
122#define TI_REG_WINDOW 0x30
123#define TI_RWIN_SPTRS 0x230
124#define TI_W_SAVED 0x250
125/* #define TI_RESTART_BLOCK 0x25n */ /* Nobody cares */
126
127#define PREEMPT_ACTIVE 0x4000000
128
129/*
130 * thread information flag bit numbers
131 */
132#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
133/* flag bit 1 is available */
134#define TIF_SIGPENDING 2 /* signal pending */
135#define TIF_NEED_RESCHED 3 /* rescheduling necessary */
136#define TIF_RESTORE_SIGMASK 4 /* restore signal mask in do_signal() */
137#define TIF_USEDFPU 8 /* FPU was used by this task
138 * this quantum (SMP) */
139#define TIF_POLLING_NRFLAG 9 /* true if poll_idle() is polling
140 * TIF_NEED_RESCHED */
141#define TIF_MEMDIE 10
142
143/* as above, but as bit values */
144#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
145#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
146#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
147#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK)
148#define _TIF_USEDFPU (1<<TIF_USEDFPU)
149#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
150
151#endif /* __KERNEL__ */
152
153#endif /* _ASM_THREAD_INFO_H */
diff --git a/include/asm-sparc/thread_info_64.h b/include/asm-sparc/thread_info_64.h
deleted file mode 100644
index 960969d5ad0..00000000000
--- a/include/asm-sparc/thread_info_64.h
+++ /dev/null
@@ -1,279 +0,0 @@
1/* thread_info.h: sparc64 low-level thread information
2 *
3 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
4 */
5
6#ifndef _ASM_THREAD_INFO_H
7#define _ASM_THREAD_INFO_H
8
9#ifdef __KERNEL__
10
11#define NSWINS 7
12
13#define TI_FLAG_BYTE_FAULT_CODE 0
14#define TI_FLAG_FAULT_CODE_SHIFT 56
15#define TI_FLAG_BYTE_WSTATE 1
16#define TI_FLAG_WSTATE_SHIFT 48
17#define TI_FLAG_BYTE_CWP 2
18#define TI_FLAG_CWP_SHIFT 40
19#define TI_FLAG_BYTE_CURRENT_DS 3
20#define TI_FLAG_CURRENT_DS_SHIFT 32
21#define TI_FLAG_BYTE_FPDEPTH 4
22#define TI_FLAG_FPDEPTH_SHIFT 24
23#define TI_FLAG_BYTE_WSAVED 5
24#define TI_FLAG_WSAVED_SHIFT 16
25
26#include <asm/page.h>
27
28#ifndef __ASSEMBLY__
29
30#include <asm/ptrace.h>
31#include <asm/types.h>
32
33struct task_struct;
34struct exec_domain;
35
36struct thread_info {
37 /* D$ line 1 */
38 struct task_struct *task;
39 unsigned long flags;
40 __u8 fpsaved[7];
41 __u8 status;
42 unsigned long ksp;
43
44 /* D$ line 2 */
45 unsigned long fault_address;
46 struct pt_regs *kregs;
47 struct exec_domain *exec_domain;
48 int preempt_count; /* 0 => preemptable, <0 => BUG */
49 __u8 new_child;
50 __u8 syscall_noerror;
51 __u16 cpu;
52
53 unsigned long *utraps;
54
55 struct reg_window reg_window[NSWINS];
56 unsigned long rwbuf_stkptrs[NSWINS];
57
58 unsigned long gsr[7];
59 unsigned long xfsr[7];
60
61 __u64 __user *user_cntd0;
62 __u64 __user *user_cntd1;
63 __u64 kernel_cntd0, kernel_cntd1;
64 __u64 pcr_reg;
65
66 struct restart_block restart_block;
67
68 struct pt_regs *kern_una_regs;
69 unsigned int kern_una_insn;
70
71 unsigned long fpregs[0] __attribute__ ((aligned(64)));
72};
73
74#endif /* !(__ASSEMBLY__) */
75
76/* offsets into the thread_info struct for assembly code access */
77#define TI_TASK 0x00000000
78#define TI_FLAGS 0x00000008
79#define TI_FAULT_CODE (TI_FLAGS + TI_FLAG_BYTE_FAULT_CODE)
80#define TI_WSTATE (TI_FLAGS + TI_FLAG_BYTE_WSTATE)
81#define TI_CWP (TI_FLAGS + TI_FLAG_BYTE_CWP)
82#define TI_CURRENT_DS (TI_FLAGS + TI_FLAG_BYTE_CURRENT_DS)
83#define TI_FPDEPTH (TI_FLAGS + TI_FLAG_BYTE_FPDEPTH)
84#define TI_WSAVED (TI_FLAGS + TI_FLAG_BYTE_WSAVED)
85#define TI_FPSAVED 0x00000010
86#define TI_KSP 0x00000018
87#define TI_FAULT_ADDR 0x00000020
88#define TI_KREGS 0x00000028
89#define TI_EXEC_DOMAIN 0x00000030
90#define TI_PRE_COUNT 0x00000038
91#define TI_NEW_CHILD 0x0000003c
92#define TI_SYS_NOERROR 0x0000003d
93#define TI_CPU 0x0000003e
94#define TI_UTRAPS 0x00000040
95#define TI_REG_WINDOW 0x00000048
96#define TI_RWIN_SPTRS 0x000003c8
97#define TI_GSR 0x00000400
98#define TI_XFSR 0x00000438
99#define TI_USER_CNTD0 0x00000470
100#define TI_USER_CNTD1 0x00000478
101#define TI_KERN_CNTD0 0x00000480
102#define TI_KERN_CNTD1 0x00000488
103#define TI_PCR 0x00000490
104#define TI_RESTART_BLOCK 0x00000498
105#define TI_KUNA_REGS 0x000004c0
106#define TI_KUNA_INSN 0x000004c8
107#define TI_FPREGS 0x00000500
108
109/* We embed this in the uppermost byte of thread_info->flags */
110#define FAULT_CODE_WRITE 0x01 /* Write access, implies D-TLB */
111#define FAULT_CODE_DTLB 0x02 /* Miss happened in D-TLB */
112#define FAULT_CODE_ITLB 0x04 /* Miss happened in I-TLB */
113#define FAULT_CODE_WINFIXUP 0x08 /* Miss happened during spill/fill */
114#define FAULT_CODE_BLKCOMMIT 0x10 /* Use blk-commit ASI in copy_page */
115
116#if PAGE_SHIFT == 13
117#define THREAD_SIZE (2*PAGE_SIZE)
118#define THREAD_SHIFT (PAGE_SHIFT + 1)
119#else /* PAGE_SHIFT == 13 */
120#define THREAD_SIZE PAGE_SIZE
121#define THREAD_SHIFT PAGE_SHIFT
122#endif /* PAGE_SHIFT == 13 */
123
124#define PREEMPT_ACTIVE 0x4000000
125
126/*
127 * macros/functions for gaining access to the thread information structure
128 *
129 * preempt_count needs to be 1 initially, until the scheduler is functional.
130 */
131#ifndef __ASSEMBLY__
132
133#define INIT_THREAD_INFO(tsk) \
134{ \
135 .task = &tsk, \
136 .flags = ((unsigned long)ASI_P) << TI_FLAG_CURRENT_DS_SHIFT, \
137 .exec_domain = &default_exec_domain, \
138 .preempt_count = 1, \
139 .restart_block = { \
140 .fn = do_no_restart_syscall, \
141 }, \
142}
143
144#define init_thread_info (init_thread_union.thread_info)
145#define init_stack (init_thread_union.stack)
146
147/* how to get the thread information struct from C */
148register struct thread_info *current_thread_info_reg asm("g6");
149#define current_thread_info() (current_thread_info_reg)
150
151/* thread information allocation */
152#if PAGE_SHIFT == 13
153#define __THREAD_INFO_ORDER 1
154#else /* PAGE_SHIFT == 13 */
155#define __THREAD_INFO_ORDER 0
156#endif /* PAGE_SHIFT == 13 */
157
158#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
159
160#ifdef CONFIG_DEBUG_STACK_USAGE
161#define alloc_thread_info(tsk) \
162({ \
163 struct thread_info *ret; \
164 \
165 ret = (struct thread_info *) \
166 __get_free_pages(GFP_KERNEL, __THREAD_INFO_ORDER); \
167 if (ret) \
168 memset(ret, 0, PAGE_SIZE<<__THREAD_INFO_ORDER); \
169 ret; \
170})
171#else
172#define alloc_thread_info(tsk) \
173 ((struct thread_info *)__get_free_pages(GFP_KERNEL, __THREAD_INFO_ORDER))
174#endif
175
176#define free_thread_info(ti) \
177 free_pages((unsigned long)(ti),__THREAD_INFO_ORDER)
178
179#define __thread_flag_byte_ptr(ti) \
180 ((unsigned char *)(&((ti)->flags)))
181#define __cur_thread_flag_byte_ptr __thread_flag_byte_ptr(current_thread_info())
182
183#define get_thread_fault_code() (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_FAULT_CODE])
184#define set_thread_fault_code(val) (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_FAULT_CODE] = (val))
185#define get_thread_wstate() (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_WSTATE])
186#define set_thread_wstate(val) (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_WSTATE] = (val))
187#define get_thread_cwp() (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_CWP])
188#define set_thread_cwp(val) (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_CWP] = (val))
189#define get_thread_current_ds() (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_CURRENT_DS])
190#define set_thread_current_ds(val) (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_CURRENT_DS] = (val))
191#define get_thread_fpdepth() (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_FPDEPTH])
192#define set_thread_fpdepth(val) (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_FPDEPTH] = (val))
193#define get_thread_wsaved() (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_WSAVED])
194#define set_thread_wsaved(val) (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_WSAVED] = (val))
195
196#endif /* !(__ASSEMBLY__) */
197
198/*
199 * Thread information flags, only 16 bits are available as we encode
200 * other values into the upper 6 bytes.
201 *
202 * On trap return we need to test several values:
203 *
204 * user: need_resched, notify_resume, sigpending, wsaved, perfctr
205 * kernel: fpdepth
206 *
207 * So to check for work in the kernel case we simply load the fpdepth
208 * byte out of the flags and test it. For the user case we encode the
209 * lower 3 bytes of flags as follows:
210 * ----------------------------------------
211 * | wsaved | flags byte 1 | flags byte 2 |
212 * ----------------------------------------
213 * This optimizes the user test into:
214 * ldx [%g6 + TI_FLAGS], REG1
215 * sethi %hi(_TIF_USER_WORK_MASK), REG2
216 * or REG2, %lo(_TIF_USER_WORK_MASK), REG2
217 * andcc REG1, REG2, %g0
218 * be,pt no_work_to_do
219 * nop
220 */
221#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
222/* flags bit 1 is available */
223#define TIF_SIGPENDING 2 /* signal pending */
224#define TIF_NEED_RESCHED 3 /* rescheduling necessary */
225#define TIF_PERFCTR 4 /* performance counters active */
226#define TIF_UNALIGNED 5 /* allowed to do unaligned accesses */
227/* flag bit 6 is available */
228#define TIF_32BIT 7 /* 32-bit binary */
229/* flag bit 8 is available */
230#define TIF_SECCOMP 9 /* secure computing */
231#define TIF_SYSCALL_AUDIT 10 /* syscall auditing active */
232/* flag bit 11 is available */
233/* NOTE: Thread flags >= 12 should be ones we have no interest
234 * in using in assembly, else we can't use the mask as
235 * an immediate value in instructions such as andcc.
236 */
237#define TIF_ABI_PENDING 12
238#define TIF_MEMDIE 13
239#define TIF_POLLING_NRFLAG 14
240
241#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
242#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
243#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
244#define _TIF_PERFCTR (1<<TIF_PERFCTR)
245#define _TIF_UNALIGNED (1<<TIF_UNALIGNED)
246#define _TIF_32BIT (1<<TIF_32BIT)
247#define _TIF_SECCOMP (1<<TIF_SECCOMP)
248#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT)
249#define _TIF_ABI_PENDING (1<<TIF_ABI_PENDING)
250#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
251
252#define _TIF_USER_WORK_MASK ((0xff << TI_FLAG_WSAVED_SHIFT) | \
253 (_TIF_SIGPENDING | \
254 _TIF_NEED_RESCHED | _TIF_PERFCTR))
255
256/*
257 * Thread-synchronous status.
258 *
259 * This is different from the flags in that nobody else
260 * ever touches our thread-synchronous status, so we don't
261 * have to worry about atomic accesses.
262 *
263 * Note that there are only 8 bits available.
264 */
265#define TS_RESTORE_SIGMASK 0x0001 /* restore signal mask in do_signal() */
266
267#ifndef __ASSEMBLY__
268#define HAVE_SET_RESTORE_SIGMASK 1
269static inline void set_restore_sigmask(void)
270{
271 struct thread_info *ti = current_thread_info();
272 ti->status |= TS_RESTORE_SIGMASK;
273 set_bit(TIF_SIGPENDING, &ti->flags);
274}
275#endif /* !__ASSEMBLY__ */
276
277#endif /* __KERNEL__ */
278
279#endif /* _ASM_THREAD_INFO_H */
diff --git a/include/asm-sparc/timer.h b/include/asm-sparc/timer.h
deleted file mode 100644
index 475baa05a96..00000000000
--- a/include/asm-sparc/timer.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_TIMER_H
2#define ___ASM_SPARC_TIMER_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/timer_64.h>
5#else
6#include <asm-sparc/timer_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/timer_32.h b/include/asm-sparc/timer_32.h
deleted file mode 100644
index 361e53898dd..00000000000
--- a/include/asm-sparc/timer_32.h
+++ /dev/null
@@ -1,107 +0,0 @@
1/*
2 * timer.h: Definitions for the timer chips on the Sparc.
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 */
6
7
8#ifndef _SPARC_TIMER_H
9#define _SPARC_TIMER_H
10
11#include <asm/system.h> /* For SUN4M_NCPUS */
12#include <asm/sun4paddr.h>
13#include <asm/btfixup.h>
14
15/* Timer structures. The interrupt timer has two properties which
16 * are the counter (which is handled in do_timer in sched.c) and the limit.
17 * This limit is where the timer's counter 'wraps' around. Oddly enough,
18 * the sun4c timer when it hits the limit wraps back to 1 and not zero
19 * thus when calculating the value at which it will fire a microsecond you
20 * must adjust by one. Thanks SUN for designing such great hardware ;(
21 */
22
23/* Note that I am only going to use the timer that interrupts at
24 * Sparc IRQ 10. There is another one available that can fire at
25 * IRQ 14. Currently it is left untouched, we keep the PROM's limit
26 * register value and let the prom take these interrupts. This allows
27 * L1-A to work.
28 */
29
30struct sun4c_timer_info {
31 __volatile__ unsigned int cur_count10;
32 __volatile__ unsigned int timer_limit10;
33 __volatile__ unsigned int cur_count14;
34 __volatile__ unsigned int timer_limit14;
35};
36
37#define SUN4C_TIMER_PHYSADDR 0xf3000000
38#ifdef CONFIG_SUN4
39#define SUN_TIMER_PHYSADDR SUN4_300_TIMER_PHYSADDR
40#else
41#define SUN_TIMER_PHYSADDR SUN4C_TIMER_PHYSADDR
42#endif
43
44/* A sun4m has two blocks of registers which are probably of the same
45 * structure. LSI Logic's L64851 is told to _decrement_ from the limit
46 * value. Aurora behaves similarly but its limit value is compacted in
47 * other fashion (it's wider). Documented fields are defined here.
48 */
49
50/* As with the interrupt register, we have two classes of timer registers
51 * which are per-cpu and master. Per-cpu timers only hit that cpu and are
52 * only level 14 ticks, master timer hits all cpus and is level 10.
53 */
54
55#define SUN4M_PRM_CNT_L 0x80000000
56#define SUN4M_PRM_CNT_LVALUE 0x7FFFFC00
57
58struct sun4m_timer_percpu_info {
59 __volatile__ unsigned int l14_timer_limit; /* Initial value is 0x009c4000 */
60 __volatile__ unsigned int l14_cur_count;
61
62 /* This register appears to be write only and/or inaccessible
63 * on Uni-Processor sun4m machines.
64 */
65 __volatile__ unsigned int l14_limit_noclear; /* Data access error is here */
66
67 __volatile__ unsigned int cntrl; /* =1 after POST on Aurora */
68 __volatile__ unsigned char space[PAGE_SIZE - 16];
69};
70
71struct sun4m_timer_regs {
72 struct sun4m_timer_percpu_info cpu_timers[SUN4M_NCPUS];
73 volatile unsigned int l10_timer_limit;
74 volatile unsigned int l10_cur_count;
75
76 /* Again, this appears to be write only and/or inaccessible
77 * on uni-processor sun4m machines.
78 */
79 volatile unsigned int l10_limit_noclear;
80
81 /* This register too, it must be magic. */
82 volatile unsigned int foobar;
83
84 volatile unsigned int cfg; /* equals zero at boot time... */
85};
86
87#define SUN4D_PRM_CNT_L 0x80000000
88#define SUN4D_PRM_CNT_LVALUE 0x7FFFFC00
89
90struct sun4d_timer_regs {
91 volatile unsigned int l10_timer_limit;
92 volatile unsigned int l10_cur_countx;
93 volatile unsigned int l10_limit_noclear;
94 volatile unsigned int ctrl;
95 volatile unsigned int l10_cur_count;
96};
97
98extern struct sun4d_timer_regs *sun4d_timers;
99
100extern __volatile__ unsigned int *master_l10_counter;
101extern __volatile__ unsigned int *master_l10_limit;
102
103/* FIXME: Make do_[gs]ettimeofday btfixup calls */
104BTFIXUPDEF_CALL(int, bus_do_settimeofday, struct timespec *tv)
105#define bus_do_settimeofday(tv) BTFIXUP_CALL(bus_do_settimeofday)(tv)
106
107#endif /* !(_SPARC_TIMER_H) */
diff --git a/include/asm-sparc/timer_64.h b/include/asm-sparc/timer_64.h
deleted file mode 100644
index 5b779fd1f78..00000000000
--- a/include/asm-sparc/timer_64.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/* timer.h: System timer definitions for sun5.
2 *
3 * Copyright (C) 1997, 2008 David S. Miller (davem@davemloft.net)
4 */
5
6#ifndef _SPARC64_TIMER_H
7#define _SPARC64_TIMER_H
8
9#include <linux/types.h>
10#include <linux/init.h>
11
12struct sparc64_tick_ops {
13 unsigned long (*get_tick)(void);
14 int (*add_compare)(unsigned long);
15 unsigned long softint_mask;
16 void (*disable_irq)(void);
17
18 void (*init_tick)(void);
19 unsigned long (*add_tick)(unsigned long);
20
21 char *name;
22};
23
24extern struct sparc64_tick_ops *tick_ops;
25
26extern unsigned long sparc64_get_clock_tick(unsigned int cpu);
27extern void __devinit setup_sparc64_timer(void);
28extern void __init time_init(void);
29
30#endif /* _SPARC64_TIMER_H */
diff --git a/include/asm-sparc/timex.h b/include/asm-sparc/timex.h
deleted file mode 100644
index 01d9f199d45..00000000000
--- a/include/asm-sparc/timex.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_TIMEX_H
2#define ___ASM_SPARC_TIMEX_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/timex_64.h>
5#else
6#include <asm-sparc/timex_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/timex_32.h b/include/asm-sparc/timex_32.h
deleted file mode 100644
index 71b45c90cca..00000000000
--- a/include/asm-sparc/timex_32.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/*
2 * linux/include/asm-sparc/timex.h
3 *
4 * sparc architecture timex specifications
5 */
6#ifndef _ASMsparc_TIMEX_H
7#define _ASMsparc_TIMEX_H
8
9#define CLOCK_TICK_RATE 1193180 /* Underlying HZ */
10
11/* XXX Maybe do something better at some point... -DaveM */
12typedef unsigned long cycles_t;
13#define get_cycles() (0)
14
15#endif
diff --git a/include/asm-sparc/timex_64.h b/include/asm-sparc/timex_64.h
deleted file mode 100644
index c622535c456..00000000000
--- a/include/asm-sparc/timex_64.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * linux/include/asm-sparc64/timex.h
3 *
4 * sparc64 architecture timex specifications
5 */
6#ifndef _ASMsparc64_TIMEX_H
7#define _ASMsparc64_TIMEX_H
8
9#include <asm/timer.h>
10
11#define CLOCK_TICK_RATE 1193180 /* Underlying HZ */
12
13/* Getting on the cycle counter on sparc64. */
14typedef unsigned long cycles_t;
15#define get_cycles() tick_ops->get_tick()
16
17#define ARCH_HAS_READ_CURRENT_TIMER
18
19#endif
diff --git a/include/asm-sparc/tlb.h b/include/asm-sparc/tlb.h
deleted file mode 100644
index a821057327c..00000000000
--- a/include/asm-sparc/tlb.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_TLB_H
2#define ___ASM_SPARC_TLB_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/tlb_64.h>
5#else
6#include <asm-sparc/tlb_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/tlb_32.h b/include/asm-sparc/tlb_32.h
deleted file mode 100644
index 6d02d1ce53f..00000000000
--- a/include/asm-sparc/tlb_32.h
+++ /dev/null
@@ -1,24 +0,0 @@
1#ifndef _SPARC_TLB_H
2#define _SPARC_TLB_H
3
4#define tlb_start_vma(tlb, vma) \
5do { \
6 flush_cache_range(vma, vma->vm_start, vma->vm_end); \
7} while (0)
8
9#define tlb_end_vma(tlb, vma) \
10do { \
11 flush_tlb_range(vma, vma->vm_start, vma->vm_end); \
12} while (0)
13
14#define __tlb_remove_tlb_entry(tlb, pte, address) \
15 do { } while (0)
16
17#define tlb_flush(tlb) \
18do { \
19 flush_tlb_mm((tlb)->mm); \
20} while (0)
21
22#include <asm-generic/tlb.h>
23
24#endif /* _SPARC_TLB_H */
diff --git a/include/asm-sparc/tlb_64.h b/include/asm-sparc/tlb_64.h
deleted file mode 100644
index ec81cdedef2..00000000000
--- a/include/asm-sparc/tlb_64.h
+++ /dev/null
@@ -1,111 +0,0 @@
1#ifndef _SPARC64_TLB_H
2#define _SPARC64_TLB_H
3
4#include <linux/swap.h>
5#include <linux/pagemap.h>
6#include <asm/pgalloc.h>
7#include <asm/tlbflush.h>
8#include <asm/mmu_context.h>
9
10#define TLB_BATCH_NR 192
11
12/*
13 * For UP we don't need to worry about TLB flush
14 * and page free order so much..
15 */
16#ifdef CONFIG_SMP
17 #define FREE_PTE_NR 506
18 #define tlb_fast_mode(bp) ((bp)->pages_nr == ~0U)
19#else
20 #define FREE_PTE_NR 1
21 #define tlb_fast_mode(bp) 1
22#endif
23
24struct mmu_gather {
25 struct mm_struct *mm;
26 unsigned int pages_nr;
27 unsigned int need_flush;
28 unsigned int fullmm;
29 unsigned int tlb_nr;
30 unsigned long vaddrs[TLB_BATCH_NR];
31 struct page *pages[FREE_PTE_NR];
32};
33
34DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
35
36#ifdef CONFIG_SMP
37extern void smp_flush_tlb_pending(struct mm_struct *,
38 unsigned long, unsigned long *);
39#endif
40
41extern void __flush_tlb_pending(unsigned long, unsigned long, unsigned long *);
42extern void flush_tlb_pending(void);
43
44static inline struct mmu_gather *tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
45{
46 struct mmu_gather *mp = &get_cpu_var(mmu_gathers);
47
48 BUG_ON(mp->tlb_nr);
49
50 mp->mm = mm;
51 mp->pages_nr = num_online_cpus() > 1 ? 0U : ~0U;
52 mp->fullmm = full_mm_flush;
53
54 return mp;
55}
56
57
58static inline void tlb_flush_mmu(struct mmu_gather *mp)
59{
60 if (mp->need_flush) {
61 free_pages_and_swap_cache(mp->pages, mp->pages_nr);
62 mp->pages_nr = 0;
63 mp->need_flush = 0;
64 }
65
66}
67
68#ifdef CONFIG_SMP
69extern void smp_flush_tlb_mm(struct mm_struct *mm);
70#define do_flush_tlb_mm(mm) smp_flush_tlb_mm(mm)
71#else
72#define do_flush_tlb_mm(mm) __flush_tlb_mm(CTX_HWBITS(mm->context), SECONDARY_CONTEXT)
73#endif
74
75static inline void tlb_finish_mmu(struct mmu_gather *mp, unsigned long start, unsigned long end)
76{
77 tlb_flush_mmu(mp);
78
79 if (mp->fullmm)
80 mp->fullmm = 0;
81 else
82 flush_tlb_pending();
83
84 /* keep the page table cache within bounds */
85 check_pgt_cache();
86
87 put_cpu_var(mmu_gathers);
88}
89
90static inline void tlb_remove_page(struct mmu_gather *mp, struct page *page)
91{
92 if (tlb_fast_mode(mp)) {
93 free_page_and_swap_cache(page);
94 return;
95 }
96 mp->need_flush = 1;
97 mp->pages[mp->pages_nr++] = page;
98 if (mp->pages_nr >= FREE_PTE_NR)
99 tlb_flush_mmu(mp);
100}
101
102#define tlb_remove_tlb_entry(mp,ptep,addr) do { } while (0)
103#define pte_free_tlb(mp, ptepage) pte_free((mp)->mm, ptepage)
104#define pmd_free_tlb(mp, pmdp) pmd_free((mp)->mm, pmdp)
105#define pud_free_tlb(tlb,pudp) __pud_free_tlb(tlb,pudp)
106
107#define tlb_migrate_finish(mm) do { } while (0)
108#define tlb_start_vma(tlb, vma) do { } while (0)
109#define tlb_end_vma(tlb, vma) do { } while (0)
110
111#endif /* _SPARC64_TLB_H */
diff --git a/include/asm-sparc/tlbflush.h b/include/asm-sparc/tlbflush.h
deleted file mode 100644
index 6e6bc12227b..00000000000
--- a/include/asm-sparc/tlbflush.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_TLBFLUSH_H
2#define ___ASM_SPARC_TLBFLUSH_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/tlbflush_64.h>
5#else
6#include <asm-sparc/tlbflush_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/tlbflush_32.h b/include/asm-sparc/tlbflush_32.h
deleted file mode 100644
index fe0a71abc9b..00000000000
--- a/include/asm-sparc/tlbflush_32.h
+++ /dev/null
@@ -1,60 +0,0 @@
1#ifndef _SPARC_TLBFLUSH_H
2#define _SPARC_TLBFLUSH_H
3
4#include <linux/mm.h>
5// #include <asm/processor.h>
6
7/*
8 * TLB flushing:
9 *
10 * - flush_tlb() flushes the current mm struct TLBs XXX Exists?
11 * - flush_tlb_all() flushes all processes TLBs
12 * - flush_tlb_mm(mm) flushes the specified mm context TLB's
13 * - flush_tlb_page(vma, vmaddr) flushes one page
14 * - flush_tlb_range(vma, start, end) flushes a range of pages
15 * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
16 */
17
18#ifdef CONFIG_SMP
19
20BTFIXUPDEF_CALL(void, local_flush_tlb_all, void)
21BTFIXUPDEF_CALL(void, local_flush_tlb_mm, struct mm_struct *)
22BTFIXUPDEF_CALL(void, local_flush_tlb_range, struct vm_area_struct *, unsigned long, unsigned long)
23BTFIXUPDEF_CALL(void, local_flush_tlb_page, struct vm_area_struct *, unsigned long)
24
25#define local_flush_tlb_all() BTFIXUP_CALL(local_flush_tlb_all)()
26#define local_flush_tlb_mm(mm) BTFIXUP_CALL(local_flush_tlb_mm)(mm)
27#define local_flush_tlb_range(vma,start,end) BTFIXUP_CALL(local_flush_tlb_range)(vma,start,end)
28#define local_flush_tlb_page(vma,addr) BTFIXUP_CALL(local_flush_tlb_page)(vma,addr)
29
30extern void smp_flush_tlb_all(void);
31extern void smp_flush_tlb_mm(struct mm_struct *mm);
32extern void smp_flush_tlb_range(struct vm_area_struct *vma,
33 unsigned long start,
34 unsigned long end);
35extern void smp_flush_tlb_page(struct vm_area_struct *mm, unsigned long page);
36
37#endif /* CONFIG_SMP */
38
39BTFIXUPDEF_CALL(void, flush_tlb_all, void)
40BTFIXUPDEF_CALL(void, flush_tlb_mm, struct mm_struct *)
41BTFIXUPDEF_CALL(void, flush_tlb_range, struct vm_area_struct *, unsigned long, unsigned long)
42BTFIXUPDEF_CALL(void, flush_tlb_page, struct vm_area_struct *, unsigned long)
43
44#define flush_tlb_all() BTFIXUP_CALL(flush_tlb_all)()
45#define flush_tlb_mm(mm) BTFIXUP_CALL(flush_tlb_mm)(mm)
46#define flush_tlb_range(vma,start,end) BTFIXUP_CALL(flush_tlb_range)(vma,start,end)
47#define flush_tlb_page(vma,addr) BTFIXUP_CALL(flush_tlb_page)(vma,addr)
48
49// #define flush_tlb() flush_tlb_mm(current->active_mm) /* XXX Sure? */
50
51/*
52 * This is a kludge, until I know better. --zaitcev XXX
53 */
54static inline void flush_tlb_kernel_range(unsigned long start,
55 unsigned long end)
56{
57 flush_tlb_all();
58}
59
60#endif /* _SPARC_TLBFLUSH_H */
diff --git a/include/asm-sparc/tlbflush_64.h b/include/asm-sparc/tlbflush_64.h
deleted file mode 100644
index fbb675dbe0c..00000000000
--- a/include/asm-sparc/tlbflush_64.h
+++ /dev/null
@@ -1,44 +0,0 @@
1#ifndef _SPARC64_TLBFLUSH_H
2#define _SPARC64_TLBFLUSH_H
3
4#include <linux/mm.h>
5#include <asm/mmu_context.h>
6
7/* TSB flush operations. */
8struct mmu_gather;
9extern void flush_tsb_kernel_range(unsigned long start, unsigned long end);
10extern void flush_tsb_user(struct mmu_gather *mp);
11
12/* TLB flush operations. */
13
14extern void flush_tlb_pending(void);
15
16#define flush_tlb_range(vma,start,end) \
17 do { (void)(start); flush_tlb_pending(); } while (0)
18#define flush_tlb_page(vma,addr) flush_tlb_pending()
19#define flush_tlb_mm(mm) flush_tlb_pending()
20
21/* Local cpu only. */
22extern void __flush_tlb_all(void);
23
24extern void __flush_tlb_kernel_range(unsigned long start, unsigned long end);
25
26#ifndef CONFIG_SMP
27
28#define flush_tlb_kernel_range(start,end) \
29do { flush_tsb_kernel_range(start,end); \
30 __flush_tlb_kernel_range(start,end); \
31} while (0)
32
33#else /* CONFIG_SMP */
34
35extern void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end);
36
37#define flush_tlb_kernel_range(start, end) \
38do { flush_tsb_kernel_range(start,end); \
39 smp_flush_tlb_kernel_range(start, end); \
40} while (0)
41
42#endif /* ! CONFIG_SMP */
43
44#endif /* _SPARC64_TLBFLUSH_H */
diff --git a/include/asm-sparc/topology.h b/include/asm-sparc/topology.h
deleted file mode 100644
index ed13630f32e..00000000000
--- a/include/asm-sparc/topology.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_TOPOLOGY_H
2#define ___ASM_SPARC_TOPOLOGY_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/topology_64.h>
5#else
6#include <asm-sparc/topology_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/topology_32.h b/include/asm-sparc/topology_32.h
deleted file mode 100644
index ee5ac9c9da2..00000000000
--- a/include/asm-sparc/topology_32.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _ASM_SPARC_TOPOLOGY_H
2#define _ASM_SPARC_TOPOLOGY_H
3
4#include <asm-generic/topology.h>
5
6#endif /* _ASM_SPARC_TOPOLOGY_H */
diff --git a/include/asm-sparc/topology_64.h b/include/asm-sparc/topology_64.h
deleted file mode 100644
index 001c04027c8..00000000000
--- a/include/asm-sparc/topology_64.h
+++ /dev/null
@@ -1,86 +0,0 @@
1#ifndef _ASM_SPARC64_TOPOLOGY_H
2#define _ASM_SPARC64_TOPOLOGY_H
3
4#ifdef CONFIG_NUMA
5
6#include <asm/mmzone.h>
7
8static inline int cpu_to_node(int cpu)
9{
10 return numa_cpu_lookup_table[cpu];
11}
12
13#define parent_node(node) (node)
14
15static inline cpumask_t node_to_cpumask(int node)
16{
17 return numa_cpumask_lookup_table[node];
18}
19
20/* Returns a pointer to the cpumask of CPUs on Node 'node'. */
21#define node_to_cpumask_ptr(v, node) \
22 cpumask_t *v = &(numa_cpumask_lookup_table[node])
23
24#define node_to_cpumask_ptr_next(v, node) \
25 v = &(numa_cpumask_lookup_table[node])
26
27static inline int node_to_first_cpu(int node)
28{
29 cpumask_t tmp;
30 tmp = node_to_cpumask(node);
31 return first_cpu(tmp);
32}
33
34struct pci_bus;
35#ifdef CONFIG_PCI
36extern int pcibus_to_node(struct pci_bus *pbus);
37#else
38static inline int pcibus_to_node(struct pci_bus *pbus)
39{
40 return -1;
41}
42#endif
43
44#define pcibus_to_cpumask(bus) \
45 (pcibus_to_node(bus) == -1 ? \
46 CPU_MASK_ALL : \
47 node_to_cpumask(pcibus_to_node(bus)))
48
49#define SD_NODE_INIT (struct sched_domain) { \
50 .min_interval = 8, \
51 .max_interval = 32, \
52 .busy_factor = 32, \
53 .imbalance_pct = 125, \
54 .cache_nice_tries = 2, \
55 .busy_idx = 3, \
56 .idle_idx = 2, \
57 .newidle_idx = 0, \
58 .wake_idx = 1, \
59 .forkexec_idx = 1, \
60 .flags = SD_LOAD_BALANCE \
61 | SD_BALANCE_FORK \
62 | SD_BALANCE_EXEC \
63 | SD_SERIALIZE \
64 | SD_WAKE_BALANCE, \
65 .last_balance = jiffies, \
66 .balance_interval = 1, \
67}
68
69#else /* CONFIG_NUMA */
70
71#include <asm-generic/topology.h>
72
73#endif /* !(CONFIG_NUMA) */
74
75#ifdef CONFIG_SMP
76#define topology_physical_package_id(cpu) (cpu_data(cpu).proc_id)
77#define topology_core_id(cpu) (cpu_data(cpu).core_id)
78#define topology_core_siblings(cpu) (cpu_core_map[cpu])
79#define topology_thread_siblings(cpu) (per_cpu(cpu_sibling_map, cpu))
80#define mc_capable() (sparc64_multi_core)
81#define smt_capable() (sparc64_multi_core)
82#endif /* CONFIG_SMP */
83
84#define cpu_coregroup_map(cpu) (cpu_core_map[cpu])
85
86#endif /* _ASM_SPARC64_TOPOLOGY_H */
diff --git a/include/asm-sparc/traps.h b/include/asm-sparc/traps.h
deleted file mode 100644
index bebdbf8f43a..00000000000
--- a/include/asm-sparc/traps.h
+++ /dev/null
@@ -1,140 +0,0 @@
1/*
2 * traps.h: Format of entries for the Sparc trap table.
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 */
6
7#ifndef _SPARC_TRAPS_H
8#define _SPARC_TRAPS_H
9
10#define NUM_SPARC_TRAPS 255
11
12#ifndef __ASSEMBLY__
13
14/* This is for V8 compliant Sparc CPUS */
15struct tt_entry {
16 unsigned long inst_one;
17 unsigned long inst_two;
18 unsigned long inst_three;
19 unsigned long inst_four;
20};
21
22/* We set this to _start in system setup. */
23extern struct tt_entry *sparc_ttable;
24
25static inline unsigned long get_tbr(void)
26{
27 unsigned long tbr;
28
29 __asm__ __volatile__("rd %%tbr, %0\n\t" : "=r" (tbr));
30 return tbr;
31}
32
33#endif /* !(__ASSEMBLY__) */
34
35/* For patching the trap table at boot time, we need to know how to
36 * form various common Sparc instructions. Thus these macros...
37 */
38
39#define SPARC_MOV_CONST_L3(const) (0xa6102000 | (const&0xfff))
40
41/* The following assumes that the branch lies before the place we
42 * are branching to. This is the case for a trap vector...
43 * You have been warned.
44 */
45#define SPARC_BRANCH(dest_addr, inst_addr) \
46 (0x10800000 | (((dest_addr-inst_addr)>>2)&0x3fffff))
47
48#define SPARC_RD_PSR_L0 (0xa1480000)
49#define SPARC_RD_WIM_L3 (0xa7500000)
50#define SPARC_NOP (0x01000000)
51
52/* Various interesting trap levels. */
53/* First, hardware traps. */
54#define SP_TRAP_TFLT 0x1 /* Text fault */
55#define SP_TRAP_II 0x2 /* Illegal Instruction */
56#define SP_TRAP_PI 0x3 /* Privileged Instruction */
57#define SP_TRAP_FPD 0x4 /* Floating Point Disabled */
58#define SP_TRAP_WOVF 0x5 /* Window Overflow */
59#define SP_TRAP_WUNF 0x6 /* Window Underflow */
60#define SP_TRAP_MNA 0x7 /* Memory Address Unaligned */
61#define SP_TRAP_FPE 0x8 /* Floating Point Exception */
62#define SP_TRAP_DFLT 0x9 /* Data Fault */
63#define SP_TRAP_TOF 0xa /* Tag Overflow */
64#define SP_TRAP_WDOG 0xb /* Watchpoint Detected */
65#define SP_TRAP_IRQ1 0x11 /* IRQ level 1 */
66#define SP_TRAP_IRQ2 0x12 /* IRQ level 2 */
67#define SP_TRAP_IRQ3 0x13 /* IRQ level 3 */
68#define SP_TRAP_IRQ4 0x14 /* IRQ level 4 */
69#define SP_TRAP_IRQ5 0x15 /* IRQ level 5 */
70#define SP_TRAP_IRQ6 0x16 /* IRQ level 6 */
71#define SP_TRAP_IRQ7 0x17 /* IRQ level 7 */
72#define SP_TRAP_IRQ8 0x18 /* IRQ level 8 */
73#define SP_TRAP_IRQ9 0x19 /* IRQ level 9 */
74#define SP_TRAP_IRQ10 0x1a /* IRQ level 10 */
75#define SP_TRAP_IRQ11 0x1b /* IRQ level 11 */
76#define SP_TRAP_IRQ12 0x1c /* IRQ level 12 */
77#define SP_TRAP_IRQ13 0x1d /* IRQ level 13 */
78#define SP_TRAP_IRQ14 0x1e /* IRQ level 14 */
79#define SP_TRAP_IRQ15 0x1f /* IRQ level 15 Non-maskable */
80#define SP_TRAP_RACC 0x20 /* Register Access Error ??? */
81#define SP_TRAP_IACC 0x21 /* Instruction Access Error */
82#define SP_TRAP_CPDIS 0x24 /* Co-Processor Disabled */
83#define SP_TRAP_BADFL 0x25 /* Unimplemented Flush Instruction */
84#define SP_TRAP_CPEXP 0x28 /* Co-Processor Exception */
85#define SP_TRAP_DACC 0x29 /* Data Access Error */
86#define SP_TRAP_DIVZ 0x2a /* Divide By Zero */
87#define SP_TRAP_DSTORE 0x2b /* Data Store Error ??? */
88#define SP_TRAP_DMM 0x2c /* Data Access MMU Miss ??? */
89#define SP_TRAP_IMM 0x3c /* Instruction Access MMU Miss ??? */
90
91/* Now the Software Traps... */
92#define SP_TRAP_SUNOS 0x80 /* SunOS System Call */
93#define SP_TRAP_SBPT 0x81 /* Software Breakpoint */
94#define SP_TRAP_SDIVZ 0x82 /* Software Divide-by-Zero trap */
95#define SP_TRAP_FWIN 0x83 /* Flush Windows */
96#define SP_TRAP_CWIN 0x84 /* Clean Windows */
97#define SP_TRAP_RCHK 0x85 /* Range Check */
98#define SP_TRAP_FUNA 0x86 /* Fix Unaligned Access */
99#define SP_TRAP_IOWFL 0x87 /* Integer Overflow */
100#define SP_TRAP_SOLARIS 0x88 /* Solaris System Call */
101#define SP_TRAP_NETBSD 0x89 /* NetBSD System Call */
102#define SP_TRAP_LINUX 0x90 /* Linux System Call */
103
104/* Names used for compatibility with SunOS */
105#define ST_SYSCALL 0x00
106#define ST_BREAKPOINT 0x01
107#define ST_DIV0 0x02
108#define ST_FLUSH_WINDOWS 0x03
109#define ST_CLEAN_WINDOWS 0x04
110#define ST_RANGE_CHECK 0x05
111#define ST_FIX_ALIGN 0x06
112#define ST_INT_OVERFLOW 0x07
113
114/* Special traps... */
115#define SP_TRAP_KBPT1 0xfe /* KADB/PROM Breakpoint one */
116#define SP_TRAP_KBPT2 0xff /* KADB/PROM Breakpoint two */
117
118/* Handy Macros */
119/* Is this a trap we never expect to get? */
120#define BAD_TRAP_P(level) \
121 ((level > SP_TRAP_WDOG && level < SP_TRAP_IRQ1) || \
122 (level > SP_TRAP_IACC && level < SP_TRAP_CPDIS) || \
123 (level > SP_TRAP_BADFL && level < SP_TRAP_CPEXP) || \
124 (level > SP_TRAP_DMM && level < SP_TRAP_IMM) || \
125 (level > SP_TRAP_IMM && level < SP_TRAP_SUNOS) || \
126 (level > SP_TRAP_LINUX && level < SP_TRAP_KBPT1))
127
128/* Is this a Hardware trap? */
129#define HW_TRAP_P(level) ((level > 0) && (level < SP_TRAP_SUNOS))
130
131/* Is this a Software trap? */
132#define SW_TRAP_P(level) ((level >= SP_TRAP_SUNOS) && (level <= SP_TRAP_KBPT2))
133
134/* Is this a system call for some OS we know about? */
135#define SCALL_TRAP_P(level) ((level == SP_TRAP_SUNOS) || \
136 (level == SP_TRAP_SOLARIS) || \
137 (level == SP_TRAP_NETBSD) || \
138 (level == SP_TRAP_LINUX))
139
140#endif /* !(_SPARC_TRAPS_H) */
diff --git a/include/asm-sparc/tsb.h b/include/asm-sparc/tsb.h
deleted file mode 100644
index 76e4299dd9b..00000000000
--- a/include/asm-sparc/tsb.h
+++ /dev/null
@@ -1,283 +0,0 @@
1#ifndef _SPARC64_TSB_H
2#define _SPARC64_TSB_H
3
4/* The sparc64 TSB is similar to the powerpc hashtables. It's a
5 * power-of-2 sized table of TAG/PTE pairs. The cpu precomputes
6 * pointers into this table for 8K and 64K page sizes, and also a
7 * comparison TAG based upon the virtual address and context which
8 * faults.
9 *
10 * TLB miss trap handler software does the actual lookup via something
11 * of the form:
12 *
13 * ldxa [%g0] ASI_{D,I}MMU_TSB_8KB_PTR, %g1
14 * ldxa [%g0] ASI_{D,I}MMU, %g6
15 * sllx %g6, 22, %g6
16 * srlx %g6, 22, %g6
17 * ldda [%g1] ASI_NUCLEUS_QUAD_LDD, %g4
18 * cmp %g4, %g6
19 * bne,pn %xcc, tsb_miss_{d,i}tlb
20 * mov FAULT_CODE_{D,I}TLB, %g3
21 * stxa %g5, [%g0] ASI_{D,I}TLB_DATA_IN
22 * retry
23 *
24 *
25 * Each 16-byte slot of the TSB is the 8-byte tag and then the 8-byte
26 * PTE. The TAG is of the same layout as the TLB TAG TARGET mmu
27 * register which is:
28 *
29 * -------------------------------------------------
30 * | - | CONTEXT | - | VADDR bits 63:22 |
31 * -------------------------------------------------
32 * 63 61 60 48 47 42 41 0
33 *
34 * But actually, since we use per-mm TSB's, we zero out the CONTEXT
35 * field.
36 *
37 * Like the powerpc hashtables we need to use locking in order to
38 * synchronize while we update the entries. PTE updates need locking
39 * as well.
40 *
41 * We need to carefully choose a lock bits for the TSB entry. We
42 * choose to use bit 47 in the tag. Also, since we never map anything
43 * at page zero in context zero, we use zero as an invalid tag entry.
44 * When the lock bit is set, this forces a tag comparison failure.
45 */
46
47#define TSB_TAG_LOCK_BIT 47
48#define TSB_TAG_LOCK_HIGH (1 << (TSB_TAG_LOCK_BIT - 32))
49
50#define TSB_TAG_INVALID_BIT 46
51#define TSB_TAG_INVALID_HIGH (1 << (TSB_TAG_INVALID_BIT - 32))
52
53#define TSB_MEMBAR membar #StoreStore
54
55/* Some cpus support physical address quad loads. We want to use
56 * those if possible so we don't need to hard-lock the TSB mapping
57 * into the TLB. We encode some instruction patching in order to
58 * support this.
59 *
60 * The kernel TSB is locked into the TLB by virtue of being in the
61 * kernel image, so we don't play these games for swapper_tsb access.
62 */
63#ifndef __ASSEMBLY__
64struct tsb_ldquad_phys_patch_entry {
65 unsigned int addr;
66 unsigned int sun4u_insn;
67 unsigned int sun4v_insn;
68};
69extern struct tsb_ldquad_phys_patch_entry __tsb_ldquad_phys_patch,
70 __tsb_ldquad_phys_patch_end;
71
72struct tsb_phys_patch_entry {
73 unsigned int addr;
74 unsigned int insn;
75};
76extern struct tsb_phys_patch_entry __tsb_phys_patch, __tsb_phys_patch_end;
77#endif
78#define TSB_LOAD_QUAD(TSB, REG) \
79661: ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG; \
80 .section .tsb_ldquad_phys_patch, "ax"; \
81 .word 661b; \
82 ldda [TSB] ASI_QUAD_LDD_PHYS, REG; \
83 ldda [TSB] ASI_QUAD_LDD_PHYS_4V, REG; \
84 .previous
85
86#define TSB_LOAD_TAG_HIGH(TSB, REG) \
87661: lduwa [TSB] ASI_N, REG; \
88 .section .tsb_phys_patch, "ax"; \
89 .word 661b; \
90 lduwa [TSB] ASI_PHYS_USE_EC, REG; \
91 .previous
92
93#define TSB_LOAD_TAG(TSB, REG) \
94661: ldxa [TSB] ASI_N, REG; \
95 .section .tsb_phys_patch, "ax"; \
96 .word 661b; \
97 ldxa [TSB] ASI_PHYS_USE_EC, REG; \
98 .previous
99
100#define TSB_CAS_TAG_HIGH(TSB, REG1, REG2) \
101661: casa [TSB] ASI_N, REG1, REG2; \
102 .section .tsb_phys_patch, "ax"; \
103 .word 661b; \
104 casa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
105 .previous
106
107#define TSB_CAS_TAG(TSB, REG1, REG2) \
108661: casxa [TSB] ASI_N, REG1, REG2; \
109 .section .tsb_phys_patch, "ax"; \
110 .word 661b; \
111 casxa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
112 .previous
113
114#define TSB_STORE(ADDR, VAL) \
115661: stxa VAL, [ADDR] ASI_N; \
116 .section .tsb_phys_patch, "ax"; \
117 .word 661b; \
118 stxa VAL, [ADDR] ASI_PHYS_USE_EC; \
119 .previous
120
121#define TSB_LOCK_TAG(TSB, REG1, REG2) \
12299: TSB_LOAD_TAG_HIGH(TSB, REG1); \
123 sethi %hi(TSB_TAG_LOCK_HIGH), REG2;\
124 andcc REG1, REG2, %g0; \
125 bne,pn %icc, 99b; \
126 nop; \
127 TSB_CAS_TAG_HIGH(TSB, REG1, REG2); \
128 cmp REG1, REG2; \
129 bne,pn %icc, 99b; \
130 nop; \
131 TSB_MEMBAR
132
133#define TSB_WRITE(TSB, TTE, TAG) \
134 add TSB, 0x8, TSB; \
135 TSB_STORE(TSB, TTE); \
136 sub TSB, 0x8, TSB; \
137 TSB_MEMBAR; \
138 TSB_STORE(TSB, TAG);
139
140#define KTSB_LOAD_QUAD(TSB, REG) \
141 ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG;
142
143#define KTSB_STORE(ADDR, VAL) \
144 stxa VAL, [ADDR] ASI_N;
145
146#define KTSB_LOCK_TAG(TSB, REG1, REG2) \
14799: lduwa [TSB] ASI_N, REG1; \
148 sethi %hi(TSB_TAG_LOCK_HIGH), REG2;\
149 andcc REG1, REG2, %g0; \
150 bne,pn %icc, 99b; \
151 nop; \
152 casa [TSB] ASI_N, REG1, REG2;\
153 cmp REG1, REG2; \
154 bne,pn %icc, 99b; \
155 nop; \
156 TSB_MEMBAR
157
158#define KTSB_WRITE(TSB, TTE, TAG) \
159 add TSB, 0x8, TSB; \
160 stxa TTE, [TSB] ASI_N; \
161 sub TSB, 0x8, TSB; \
162 TSB_MEMBAR; \
163 stxa TAG, [TSB] ASI_N;
164
165 /* Do a kernel page table walk. Leaves physical PTE pointer in
166 * REG1. Jumps to FAIL_LABEL on early page table walk termination.
167 * VADDR will not be clobbered, but REG2 will.
168 */
169#define KERN_PGTABLE_WALK(VADDR, REG1, REG2, FAIL_LABEL) \
170 sethi %hi(swapper_pg_dir), REG1; \
171 or REG1, %lo(swapper_pg_dir), REG1; \
172 sllx VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
173 srlx REG2, 64 - PAGE_SHIFT, REG2; \
174 andn REG2, 0x3, REG2; \
175 lduw [REG1 + REG2], REG1; \
176 brz,pn REG1, FAIL_LABEL; \
177 sllx VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
178 srlx REG2, 64 - PAGE_SHIFT, REG2; \
179 sllx REG1, 11, REG1; \
180 andn REG2, 0x3, REG2; \
181 lduwa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
182 brz,pn REG1, FAIL_LABEL; \
183 sllx VADDR, 64 - PMD_SHIFT, REG2; \
184 srlx REG2, 64 - PAGE_SHIFT, REG2; \
185 sllx REG1, 11, REG1; \
186 andn REG2, 0x7, REG2; \
187 add REG1, REG2, REG1;
188
189 /* Do a user page table walk in MMU globals. Leaves physical PTE
190 * pointer in REG1. Jumps to FAIL_LABEL on early page table walk
191 * termination. Physical base of page tables is in PHYS_PGD which
192 * will not be modified.
193 *
194 * VADDR will not be clobbered, but REG1 and REG2 will.
195 */
196#define USER_PGTABLE_WALK_TL1(VADDR, PHYS_PGD, REG1, REG2, FAIL_LABEL) \
197 sllx VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
198 srlx REG2, 64 - PAGE_SHIFT, REG2; \
199 andn REG2, 0x3, REG2; \
200 lduwa [PHYS_PGD + REG2] ASI_PHYS_USE_EC, REG1; \
201 brz,pn REG1, FAIL_LABEL; \
202 sllx VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
203 srlx REG2, 64 - PAGE_SHIFT, REG2; \
204 sllx REG1, 11, REG1; \
205 andn REG2, 0x3, REG2; \
206 lduwa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
207 brz,pn REG1, FAIL_LABEL; \
208 sllx VADDR, 64 - PMD_SHIFT, REG2; \
209 srlx REG2, 64 - PAGE_SHIFT, REG2; \
210 sllx REG1, 11, REG1; \
211 andn REG2, 0x7, REG2; \
212 add REG1, REG2, REG1;
213
214/* Lookup a OBP mapping on VADDR in the prom_trans[] table at TL>0.
215 * If no entry is found, FAIL_LABEL will be branched to. On success
216 * the resulting PTE value will be left in REG1. VADDR is preserved
217 * by this routine.
218 */
219#define OBP_TRANS_LOOKUP(VADDR, REG1, REG2, REG3, FAIL_LABEL) \
220 sethi %hi(prom_trans), REG1; \
221 or REG1, %lo(prom_trans), REG1; \
22297: ldx [REG1 + 0x00], REG2; \
223 brz,pn REG2, FAIL_LABEL; \
224 nop; \
225 ldx [REG1 + 0x08], REG3; \
226 add REG2, REG3, REG3; \
227 cmp REG2, VADDR; \
228 bgu,pt %xcc, 98f; \
229 cmp VADDR, REG3; \
230 bgeu,pt %xcc, 98f; \
231 ldx [REG1 + 0x10], REG3; \
232 sub VADDR, REG2, REG2; \
233 ba,pt %xcc, 99f; \
234 add REG3, REG2, REG1; \
23598: ba,pt %xcc, 97b; \
236 add REG1, (3 * 8), REG1; \
23799:
238
239 /* We use a 32K TSB for the whole kernel, this allows to
240 * handle about 16MB of modules and vmalloc mappings without
241 * incurring many hash conflicts.
242 */
243#define KERNEL_TSB_SIZE_BYTES (32 * 1024)
244#define KERNEL_TSB_NENTRIES \
245 (KERNEL_TSB_SIZE_BYTES / 16)
246#define KERNEL_TSB4M_NENTRIES 4096
247
248 /* Do a kernel TSB lookup at tl>0 on VADDR+TAG, branch to OK_LABEL
249 * on TSB hit. REG1, REG2, REG3, and REG4 are used as temporaries
250 * and the found TTE will be left in REG1. REG3 and REG4 must
251 * be an even/odd pair of registers.
252 *
253 * VADDR and TAG will be preserved and not clobbered by this macro.
254 */
255#define KERN_TSB_LOOKUP_TL1(VADDR, TAG, REG1, REG2, REG3, REG4, OK_LABEL) \
256 sethi %hi(swapper_tsb), REG1; \
257 or REG1, %lo(swapper_tsb), REG1; \
258 srlx VADDR, PAGE_SHIFT, REG2; \
259 and REG2, (KERNEL_TSB_NENTRIES - 1), REG2; \
260 sllx REG2, 4, REG2; \
261 add REG1, REG2, REG2; \
262 KTSB_LOAD_QUAD(REG2, REG3); \
263 cmp REG3, TAG; \
264 be,a,pt %xcc, OK_LABEL; \
265 mov REG4, REG1;
266
267#ifndef CONFIG_DEBUG_PAGEALLOC
268 /* This version uses a trick, the TAG is already (VADDR >> 22) so
269 * we can make use of that for the index computation.
270 */
271#define KERN_TSB4M_LOOKUP_TL1(TAG, REG1, REG2, REG3, REG4, OK_LABEL) \
272 sethi %hi(swapper_4m_tsb), REG1; \
273 or REG1, %lo(swapper_4m_tsb), REG1; \
274 and TAG, (KERNEL_TSB4M_NENTRIES - 1), REG2; \
275 sllx REG2, 4, REG2; \
276 add REG1, REG2, REG2; \
277 KTSB_LOAD_QUAD(REG2, REG3); \
278 cmp REG3, TAG; \
279 be,a,pt %xcc, OK_LABEL; \
280 mov REG4, REG1;
281#endif
282
283#endif /* !(_SPARC64_TSB_H) */
diff --git a/include/asm-sparc/tsunami.h b/include/asm-sparc/tsunami.h
deleted file mode 100644
index 5bbd1d523ba..00000000000
--- a/include/asm-sparc/tsunami.h
+++ /dev/null
@@ -1,64 +0,0 @@
1/*
2 * tsunami.h: Module specific definitions for Tsunami V8 Sparcs
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 */
6
7#ifndef _SPARC_TSUNAMI_H
8#define _SPARC_TSUNAMI_H
9
10#include <asm/asi.h>
11
12/* The MMU control register on the Tsunami:
13 *
14 * -----------------------------------------------------------------------
15 * | implvers |SW|AV|DV|MV| RSV |PC|ITD|ALC| RSV |PE| RC |IE|DE|RSV|NF|ME|
16 * -----------------------------------------------------------------------
17 * 31 24 23 22 21 20 19-18 17 16 14 13-12 11 10-9 8 7 6-2 1 0
18 *
19 * SW: Enable Software Table Walks 0=off 1=on
20 * AV: Address View bit
21 * DV: Data View bit
22 * MV: Memory View bit
23 * PC: Parity Control
24 * ITD: ITBR disable
25 * ALC: Alternate Cacheable
26 * PE: Parity Enable 0=off 1=on
27 * RC: Refresh Control
28 * IE: Instruction cache Enable 0=off 1=on
29 * DE: Data cache Enable 0=off 1=on
30 * NF: No Fault, same as all other SRMMUs
31 * ME: MMU Enable, same as all other SRMMUs
32 */
33
34#define TSUNAMI_SW 0x00800000
35#define TSUNAMI_AV 0x00400000
36#define TSUNAMI_DV 0x00200000
37#define TSUNAMI_MV 0x00100000
38#define TSUNAMI_PC 0x00020000
39#define TSUNAMI_ITD 0x00010000
40#define TSUNAMI_ALC 0x00008000
41#define TSUNAMI_PE 0x00001000
42#define TSUNAMI_RCMASK 0x00000C00
43#define TSUNAMI_IENAB 0x00000200
44#define TSUNAMI_DENAB 0x00000100
45#define TSUNAMI_NF 0x00000002
46#define TSUNAMI_ME 0x00000001
47
48static inline void tsunami_flush_icache(void)
49{
50 __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
51 : /* no outputs */
52 : "i" (ASI_M_IC_FLCLEAR)
53 : "memory");
54}
55
56static inline void tsunami_flush_dcache(void)
57{
58 __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
59 : /* no outputs */
60 : "i" (ASI_M_DC_FLCLEAR)
61 : "memory");
62}
63
64#endif /* !(_SPARC_TSUNAMI_H) */
diff --git a/include/asm-sparc/ttable.h b/include/asm-sparc/ttable.h
deleted file mode 100644
index 5708ba2719f..00000000000
--- a/include/asm-sparc/ttable.h
+++ /dev/null
@@ -1,658 +0,0 @@
1#ifndef _SPARC64_TTABLE_H
2#define _SPARC64_TTABLE_H
3
4#include <asm/utrap.h>
5
6#ifdef __ASSEMBLY__
7#include <asm/thread_info.h>
8#endif
9
10#define BOOT_KERNEL b sparc64_boot; nop; nop; nop; nop; nop; nop; nop;
11
12/* We need a "cleaned" instruction... */
13#define CLEAN_WINDOW \
14 rdpr %cleanwin, %l0; add %l0, 1, %l0; \
15 wrpr %l0, 0x0, %cleanwin; \
16 clr %o0; clr %o1; clr %o2; clr %o3; \
17 clr %o4; clr %o5; clr %o6; clr %o7; \
18 clr %l0; clr %l1; clr %l2; clr %l3; \
19 clr %l4; clr %l5; clr %l6; clr %l7; \
20 retry; \
21 nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;
22
23#define TRAP(routine) \
24 sethi %hi(109f), %g7; \
25 ba,pt %xcc, etrap; \
26109: or %g7, %lo(109b), %g7; \
27 call routine; \
28 add %sp, PTREGS_OFF, %o0; \
29 ba,pt %xcc, rtrap; \
30 nop; \
31 nop;
32
33#define TRAP_7INSNS(routine) \
34 sethi %hi(109f), %g7; \
35 ba,pt %xcc, etrap; \
36109: or %g7, %lo(109b), %g7; \
37 call routine; \
38 add %sp, PTREGS_OFF, %o0; \
39 ba,pt %xcc, rtrap; \
40 nop;
41
42#define TRAP_SAVEFPU(routine) \
43 sethi %hi(109f), %g7; \
44 ba,pt %xcc, do_fptrap; \
45109: or %g7, %lo(109b), %g7; \
46 call routine; \
47 add %sp, PTREGS_OFF, %o0; \
48 ba,pt %xcc, rtrap; \
49 nop; \
50 nop;
51
52#define TRAP_NOSAVE(routine) \
53 ba,pt %xcc, routine; \
54 nop; \
55 nop; nop; nop; nop; nop; nop;
56
57#define TRAP_NOSAVE_7INSNS(routine) \
58 ba,pt %xcc, routine; \
59 nop; \
60 nop; nop; nop; nop; nop;
61
62#define TRAPTL1(routine) \
63 sethi %hi(109f), %g7; \
64 ba,pt %xcc, etraptl1; \
65109: or %g7, %lo(109b), %g7; \
66 call routine; \
67 add %sp, PTREGS_OFF, %o0; \
68 ba,pt %xcc, rtrap; \
69 nop; \
70 nop;
71
72#define TRAP_ARG(routine, arg) \
73 sethi %hi(109f), %g7; \
74 ba,pt %xcc, etrap; \
75109: or %g7, %lo(109b), %g7; \
76 add %sp, PTREGS_OFF, %o0; \
77 call routine; \
78 mov arg, %o1; \
79 ba,pt %xcc, rtrap; \
80 nop;
81
82#define TRAPTL1_ARG(routine, arg) \
83 sethi %hi(109f), %g7; \
84 ba,pt %xcc, etraptl1; \
85109: or %g7, %lo(109b), %g7; \
86 add %sp, PTREGS_OFF, %o0; \
87 call routine; \
88 mov arg, %o1; \
89 ba,pt %xcc, rtrap; \
90 nop;
91
92#define SYSCALL_TRAP(routine, systbl) \
93 rdpr %pil, %g2; \
94 mov TSTATE_SYSCALL, %g3; \
95 sethi %hi(109f), %g7; \
96 ba,pt %xcc, etrap_syscall; \
97109: or %g7, %lo(109b), %g7; \
98 sethi %hi(systbl), %l7; \
99 ba,pt %xcc, routine; \
100 or %l7, %lo(systbl), %l7;
101
102#define TRAP_UTRAP(handler,lvl) \
103 mov handler, %g3; \
104 ba,pt %xcc, utrap_trap; \
105 mov lvl, %g4; \
106 nop; \
107 nop; \
108 nop; \
109 nop; \
110 nop;
111
112#ifdef CONFIG_COMPAT
113#define LINUX_32BIT_SYSCALL_TRAP SYSCALL_TRAP(linux_sparc_syscall32, sys_call_table32)
114#else
115#define LINUX_32BIT_SYSCALL_TRAP BTRAP(0x110)
116#endif
117#define LINUX_64BIT_SYSCALL_TRAP SYSCALL_TRAP(linux_sparc_syscall, sys_call_table64)
118#define GETCC_TRAP TRAP(getcc)
119#define SETCC_TRAP TRAP(setcc)
120#define BREAKPOINT_TRAP TRAP(breakpoint_trap)
121
122#ifdef CONFIG_TRACE_IRQFLAGS
123
124#define TRAP_IRQ(routine, level) \
125 rdpr %pil, %g2; \
126 wrpr %g0, 15, %pil; \
127 sethi %hi(1f-4), %g7; \
128 ba,pt %xcc, etrap_irq; \
129 or %g7, %lo(1f-4), %g7; \
130 nop; \
131 nop; \
132 nop; \
133 .subsection 2; \
1341: call trace_hardirqs_off; \
135 nop; \
136 mov level, %o0; \
137 call routine; \
138 add %sp, PTREGS_OFF, %o1; \
139 ba,a,pt %xcc, rtrap_irq; \
140 .previous;
141
142#else
143
144#define TRAP_IRQ(routine, level) \
145 rdpr %pil, %g2; \
146 wrpr %g0, 15, %pil; \
147 ba,pt %xcc, etrap_irq; \
148 rd %pc, %g7; \
149 mov level, %o0; \
150 call routine; \
151 add %sp, PTREGS_OFF, %o1; \
152 ba,a,pt %xcc, rtrap_irq;
153
154#endif
155
156#define TRAP_IVEC TRAP_NOSAVE(do_ivec)
157
158#define BTRAP(lvl) TRAP_ARG(bad_trap, lvl)
159
160#define BTRAPTL1(lvl) TRAPTL1_ARG(bad_trap_tl1, lvl)
161
162#define FLUSH_WINDOW_TRAP \
163 ba,pt %xcc, etrap; \
164 rd %pc, %g7; \
165 flushw; \
166 ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %l1; \
167 add %l1, 4, %l2; \
168 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]; \
169 ba,pt %xcc, rtrap; \
170 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC];
171
172#ifdef CONFIG_KPROBES
173#define KPROBES_TRAP(lvl) TRAP_IRQ(kprobe_trap, lvl)
174#else
175#define KPROBES_TRAP(lvl) TRAP_ARG(bad_trap, lvl)
176#endif
177
178#ifdef CONFIG_KGDB
179#define KGDB_TRAP(lvl) TRAP_IRQ(kgdb_trap, lvl)
180#else
181#define KGDB_TRAP(lvl) TRAP_ARG(bad_trap, lvl)
182#endif
183
184#define SUN4V_ITSB_MISS \
185 ldxa [%g0] ASI_SCRATCHPAD, %g2; \
186 ldx [%g2 + HV_FAULT_I_ADDR_OFFSET], %g4; \
187 ldx [%g2 + HV_FAULT_I_CTX_OFFSET], %g5; \
188 srlx %g4, 22, %g6; \
189 ba,pt %xcc, sun4v_itsb_miss; \
190 nop; \
191 nop; \
192 nop;
193
194#define SUN4V_DTSB_MISS \
195 ldxa [%g0] ASI_SCRATCHPAD, %g2; \
196 ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4; \
197 ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5; \
198 srlx %g4, 22, %g6; \
199 ba,pt %xcc, sun4v_dtsb_miss; \
200 nop; \
201 nop; \
202 nop;
203
204/* Before touching these macros, you owe it to yourself to go and
205 * see how arch/sparc64/kernel/winfixup.S works... -DaveM
206 *
207 * For the user cases we used to use the %asi register, but
208 * it turns out that the "wr xxx, %asi" costs ~5 cycles, so
209 * now we use immediate ASI loads and stores instead. Kudos
210 * to Greg Onufer for pointing out this performance anomaly.
211 *
212 * Further note that we cannot use the g2, g4, g5, and g7 alternate
213 * globals in the spill routines, check out the save instruction in
214 * arch/sparc64/kernel/etrap.S to see what I mean about g2, and
215 * g4/g5 are the globals which are preserved by etrap processing
216 * for the caller of it. The g7 register is the return pc for
217 * etrap. Finally, g6 is the current thread register so we cannot
218 * us it in the spill handlers either. Most of these rules do not
219 * apply to fill processing, only g6 is not usable.
220 */
221
222/* Normal kernel spill */
223#define SPILL_0_NORMAL \
224 stx %l0, [%sp + STACK_BIAS + 0x00]; \
225 stx %l1, [%sp + STACK_BIAS + 0x08]; \
226 stx %l2, [%sp + STACK_BIAS + 0x10]; \
227 stx %l3, [%sp + STACK_BIAS + 0x18]; \
228 stx %l4, [%sp + STACK_BIAS + 0x20]; \
229 stx %l5, [%sp + STACK_BIAS + 0x28]; \
230 stx %l6, [%sp + STACK_BIAS + 0x30]; \
231 stx %l7, [%sp + STACK_BIAS + 0x38]; \
232 stx %i0, [%sp + STACK_BIAS + 0x40]; \
233 stx %i1, [%sp + STACK_BIAS + 0x48]; \
234 stx %i2, [%sp + STACK_BIAS + 0x50]; \
235 stx %i3, [%sp + STACK_BIAS + 0x58]; \
236 stx %i4, [%sp + STACK_BIAS + 0x60]; \
237 stx %i5, [%sp + STACK_BIAS + 0x68]; \
238 stx %i6, [%sp + STACK_BIAS + 0x70]; \
239 stx %i7, [%sp + STACK_BIAS + 0x78]; \
240 saved; retry; nop; nop; nop; nop; nop; nop; \
241 nop; nop; nop; nop; nop; nop; nop; nop;
242
243#define SPILL_0_NORMAL_ETRAP \
244etrap_kernel_spill: \
245 stx %l0, [%sp + STACK_BIAS + 0x00]; \
246 stx %l1, [%sp + STACK_BIAS + 0x08]; \
247 stx %l2, [%sp + STACK_BIAS + 0x10]; \
248 stx %l3, [%sp + STACK_BIAS + 0x18]; \
249 stx %l4, [%sp + STACK_BIAS + 0x20]; \
250 stx %l5, [%sp + STACK_BIAS + 0x28]; \
251 stx %l6, [%sp + STACK_BIAS + 0x30]; \
252 stx %l7, [%sp + STACK_BIAS + 0x38]; \
253 stx %i0, [%sp + STACK_BIAS + 0x40]; \
254 stx %i1, [%sp + STACK_BIAS + 0x48]; \
255 stx %i2, [%sp + STACK_BIAS + 0x50]; \
256 stx %i3, [%sp + STACK_BIAS + 0x58]; \
257 stx %i4, [%sp + STACK_BIAS + 0x60]; \
258 stx %i5, [%sp + STACK_BIAS + 0x68]; \
259 stx %i6, [%sp + STACK_BIAS + 0x70]; \
260 stx %i7, [%sp + STACK_BIAS + 0x78]; \
261 saved; \
262 sub %g1, 2, %g1; \
263 ba,pt %xcc, etrap_save; \
264 wrpr %g1, %cwp; \
265 nop; nop; nop; nop; nop; nop; nop; nop; \
266 nop; nop; nop; nop;
267
268/* Normal 64bit spill */
269#define SPILL_1_GENERIC(ASI) \
270 add %sp, STACK_BIAS + 0x00, %g1; \
271 stxa %l0, [%g1 + %g0] ASI; \
272 mov 0x08, %g3; \
273 stxa %l1, [%g1 + %g3] ASI; \
274 add %g1, 0x10, %g1; \
275 stxa %l2, [%g1 + %g0] ASI; \
276 stxa %l3, [%g1 + %g3] ASI; \
277 add %g1, 0x10, %g1; \
278 stxa %l4, [%g1 + %g0] ASI; \
279 stxa %l5, [%g1 + %g3] ASI; \
280 add %g1, 0x10, %g1; \
281 stxa %l6, [%g1 + %g0] ASI; \
282 stxa %l7, [%g1 + %g3] ASI; \
283 add %g1, 0x10, %g1; \
284 stxa %i0, [%g1 + %g0] ASI; \
285 stxa %i1, [%g1 + %g3] ASI; \
286 add %g1, 0x10, %g1; \
287 stxa %i2, [%g1 + %g0] ASI; \
288 stxa %i3, [%g1 + %g3] ASI; \
289 add %g1, 0x10, %g1; \
290 stxa %i4, [%g1 + %g0] ASI; \
291 stxa %i5, [%g1 + %g3] ASI; \
292 add %g1, 0x10, %g1; \
293 stxa %i6, [%g1 + %g0] ASI; \
294 stxa %i7, [%g1 + %g3] ASI; \
295 saved; \
296 retry; nop; nop; \
297 b,a,pt %xcc, spill_fixup_dax; \
298 b,a,pt %xcc, spill_fixup_mna; \
299 b,a,pt %xcc, spill_fixup;
300
301#define SPILL_1_GENERIC_ETRAP \
302etrap_user_spill_64bit: \
303 stxa %l0, [%sp + STACK_BIAS + 0x00] %asi; \
304 stxa %l1, [%sp + STACK_BIAS + 0x08] %asi; \
305 stxa %l2, [%sp + STACK_BIAS + 0x10] %asi; \
306 stxa %l3, [%sp + STACK_BIAS + 0x18] %asi; \
307 stxa %l4, [%sp + STACK_BIAS + 0x20] %asi; \
308 stxa %l5, [%sp + STACK_BIAS + 0x28] %asi; \
309 stxa %l6, [%sp + STACK_BIAS + 0x30] %asi; \
310 stxa %l7, [%sp + STACK_BIAS + 0x38] %asi; \
311 stxa %i0, [%sp + STACK_BIAS + 0x40] %asi; \
312 stxa %i1, [%sp + STACK_BIAS + 0x48] %asi; \
313 stxa %i2, [%sp + STACK_BIAS + 0x50] %asi; \
314 stxa %i3, [%sp + STACK_BIAS + 0x58] %asi; \
315 stxa %i4, [%sp + STACK_BIAS + 0x60] %asi; \
316 stxa %i5, [%sp + STACK_BIAS + 0x68] %asi; \
317 stxa %i6, [%sp + STACK_BIAS + 0x70] %asi; \
318 stxa %i7, [%sp + STACK_BIAS + 0x78] %asi; \
319 saved; \
320 sub %g1, 2, %g1; \
321 ba,pt %xcc, etrap_save; \
322 wrpr %g1, %cwp; \
323 nop; nop; nop; nop; nop; \
324 nop; nop; nop; nop; \
325 ba,a,pt %xcc, etrap_spill_fixup_64bit; \
326 ba,a,pt %xcc, etrap_spill_fixup_64bit; \
327 ba,a,pt %xcc, etrap_spill_fixup_64bit;
328
329#define SPILL_1_GENERIC_ETRAP_FIXUP \
330etrap_spill_fixup_64bit: \
331 ldub [%g6 + TI_WSAVED], %g1; \
332 sll %g1, 3, %g3; \
333 add %g6, %g3, %g3; \
334 stx %sp, [%g3 + TI_RWIN_SPTRS]; \
335 sll %g1, 7, %g3; \
336 add %g6, %g3, %g3; \
337 stx %l0, [%g3 + TI_REG_WINDOW + 0x00]; \
338 stx %l1, [%g3 + TI_REG_WINDOW + 0x08]; \
339 stx %l2, [%g3 + TI_REG_WINDOW + 0x10]; \
340 stx %l3, [%g3 + TI_REG_WINDOW + 0x18]; \
341 stx %l4, [%g3 + TI_REG_WINDOW + 0x20]; \
342 stx %l5, [%g3 + TI_REG_WINDOW + 0x28]; \
343 stx %l6, [%g3 + TI_REG_WINDOW + 0x30]; \
344 stx %l7, [%g3 + TI_REG_WINDOW + 0x38]; \
345 stx %i0, [%g3 + TI_REG_WINDOW + 0x40]; \
346 stx %i1, [%g3 + TI_REG_WINDOW + 0x48]; \
347 stx %i2, [%g3 + TI_REG_WINDOW + 0x50]; \
348 stx %i3, [%g3 + TI_REG_WINDOW + 0x58]; \
349 stx %i4, [%g3 + TI_REG_WINDOW + 0x60]; \
350 stx %i5, [%g3 + TI_REG_WINDOW + 0x68]; \
351 stx %i6, [%g3 + TI_REG_WINDOW + 0x70]; \
352 stx %i7, [%g3 + TI_REG_WINDOW + 0x78]; \
353 add %g1, 1, %g1; \
354 stb %g1, [%g6 + TI_WSAVED]; \
355 saved; \
356 rdpr %cwp, %g1; \
357 sub %g1, 2, %g1; \
358 ba,pt %xcc, etrap_save; \
359 wrpr %g1, %cwp; \
360 nop; nop; nop
361
362/* Normal 32bit spill */
363#define SPILL_2_GENERIC(ASI) \
364 srl %sp, 0, %sp; \
365 stwa %l0, [%sp + %g0] ASI; \
366 mov 0x04, %g3; \
367 stwa %l1, [%sp + %g3] ASI; \
368 add %sp, 0x08, %g1; \
369 stwa %l2, [%g1 + %g0] ASI; \
370 stwa %l3, [%g1 + %g3] ASI; \
371 add %g1, 0x08, %g1; \
372 stwa %l4, [%g1 + %g0] ASI; \
373 stwa %l5, [%g1 + %g3] ASI; \
374 add %g1, 0x08, %g1; \
375 stwa %l6, [%g1 + %g0] ASI; \
376 stwa %l7, [%g1 + %g3] ASI; \
377 add %g1, 0x08, %g1; \
378 stwa %i0, [%g1 + %g0] ASI; \
379 stwa %i1, [%g1 + %g3] ASI; \
380 add %g1, 0x08, %g1; \
381 stwa %i2, [%g1 + %g0] ASI; \
382 stwa %i3, [%g1 + %g3] ASI; \
383 add %g1, 0x08, %g1; \
384 stwa %i4, [%g1 + %g0] ASI; \
385 stwa %i5, [%g1 + %g3] ASI; \
386 add %g1, 0x08, %g1; \
387 stwa %i6, [%g1 + %g0] ASI; \
388 stwa %i7, [%g1 + %g3] ASI; \
389 saved; \
390 retry; nop; nop; \
391 b,a,pt %xcc, spill_fixup_dax; \
392 b,a,pt %xcc, spill_fixup_mna; \
393 b,a,pt %xcc, spill_fixup;
394
395#define SPILL_2_GENERIC_ETRAP \
396etrap_user_spill_32bit: \
397 srl %sp, 0, %sp; \
398 stwa %l0, [%sp + 0x00] %asi; \
399 stwa %l1, [%sp + 0x04] %asi; \
400 stwa %l2, [%sp + 0x08] %asi; \
401 stwa %l3, [%sp + 0x0c] %asi; \
402 stwa %l4, [%sp + 0x10] %asi; \
403 stwa %l5, [%sp + 0x14] %asi; \
404 stwa %l6, [%sp + 0x18] %asi; \
405 stwa %l7, [%sp + 0x1c] %asi; \
406 stwa %i0, [%sp + 0x20] %asi; \
407 stwa %i1, [%sp + 0x24] %asi; \
408 stwa %i2, [%sp + 0x28] %asi; \
409 stwa %i3, [%sp + 0x2c] %asi; \
410 stwa %i4, [%sp + 0x30] %asi; \
411 stwa %i5, [%sp + 0x34] %asi; \
412 stwa %i6, [%sp + 0x38] %asi; \
413 stwa %i7, [%sp + 0x3c] %asi; \
414 saved; \
415 sub %g1, 2, %g1; \
416 ba,pt %xcc, etrap_save; \
417 wrpr %g1, %cwp; \
418 nop; nop; nop; nop; \
419 nop; nop; nop; nop; \
420 ba,a,pt %xcc, etrap_spill_fixup_32bit; \
421 ba,a,pt %xcc, etrap_spill_fixup_32bit; \
422 ba,a,pt %xcc, etrap_spill_fixup_32bit;
423
424#define SPILL_2_GENERIC_ETRAP_FIXUP \
425etrap_spill_fixup_32bit: \
426 ldub [%g6 + TI_WSAVED], %g1; \
427 sll %g1, 3, %g3; \
428 add %g6, %g3, %g3; \
429 stx %sp, [%g3 + TI_RWIN_SPTRS]; \
430 sll %g1, 7, %g3; \
431 add %g6, %g3, %g3; \
432 stw %l0, [%g3 + TI_REG_WINDOW + 0x00]; \
433 stw %l1, [%g3 + TI_REG_WINDOW + 0x04]; \
434 stw %l2, [%g3 + TI_REG_WINDOW + 0x08]; \
435 stw %l3, [%g3 + TI_REG_WINDOW + 0x0c]; \
436 stw %l4, [%g3 + TI_REG_WINDOW + 0x10]; \
437 stw %l5, [%g3 + TI_REG_WINDOW + 0x14]; \
438 stw %l6, [%g3 + TI_REG_WINDOW + 0x18]; \
439 stw %l7, [%g3 + TI_REG_WINDOW + 0x1c]; \
440 stw %i0, [%g3 + TI_REG_WINDOW + 0x20]; \
441 stw %i1, [%g3 + TI_REG_WINDOW + 0x24]; \
442 stw %i2, [%g3 + TI_REG_WINDOW + 0x28]; \
443 stw %i3, [%g3 + TI_REG_WINDOW + 0x2c]; \
444 stw %i4, [%g3 + TI_REG_WINDOW + 0x30]; \
445 stw %i5, [%g3 + TI_REG_WINDOW + 0x34]; \
446 stw %i6, [%g3 + TI_REG_WINDOW + 0x38]; \
447 stw %i7, [%g3 + TI_REG_WINDOW + 0x3c]; \
448 add %g1, 1, %g1; \
449 stb %g1, [%g6 + TI_WSAVED]; \
450 saved; \
451 rdpr %cwp, %g1; \
452 sub %g1, 2, %g1; \
453 ba,pt %xcc, etrap_save; \
454 wrpr %g1, %cwp; \
455 nop; nop; nop
456
457#define SPILL_1_NORMAL SPILL_1_GENERIC(ASI_AIUP)
458#define SPILL_2_NORMAL SPILL_2_GENERIC(ASI_AIUP)
459#define SPILL_3_NORMAL SPILL_0_NORMAL
460#define SPILL_4_NORMAL SPILL_0_NORMAL
461#define SPILL_5_NORMAL SPILL_0_NORMAL
462#define SPILL_6_NORMAL SPILL_0_NORMAL
463#define SPILL_7_NORMAL SPILL_0_NORMAL
464
465#define SPILL_0_OTHER SPILL_0_NORMAL
466#define SPILL_1_OTHER SPILL_1_GENERIC(ASI_AIUS)
467#define SPILL_2_OTHER SPILL_2_GENERIC(ASI_AIUS)
468#define SPILL_3_OTHER SPILL_3_NORMAL
469#define SPILL_4_OTHER SPILL_4_NORMAL
470#define SPILL_5_OTHER SPILL_5_NORMAL
471#define SPILL_6_OTHER SPILL_6_NORMAL
472#define SPILL_7_OTHER SPILL_7_NORMAL
473
474/* Normal kernel fill */
475#define FILL_0_NORMAL \
476 ldx [%sp + STACK_BIAS + 0x00], %l0; \
477 ldx [%sp + STACK_BIAS + 0x08], %l1; \
478 ldx [%sp + STACK_BIAS + 0x10], %l2; \
479 ldx [%sp + STACK_BIAS + 0x18], %l3; \
480 ldx [%sp + STACK_BIAS + 0x20], %l4; \
481 ldx [%sp + STACK_BIAS + 0x28], %l5; \
482 ldx [%sp + STACK_BIAS + 0x30], %l6; \
483 ldx [%sp + STACK_BIAS + 0x38], %l7; \
484 ldx [%sp + STACK_BIAS + 0x40], %i0; \
485 ldx [%sp + STACK_BIAS + 0x48], %i1; \
486 ldx [%sp + STACK_BIAS + 0x50], %i2; \
487 ldx [%sp + STACK_BIAS + 0x58], %i3; \
488 ldx [%sp + STACK_BIAS + 0x60], %i4; \
489 ldx [%sp + STACK_BIAS + 0x68], %i5; \
490 ldx [%sp + STACK_BIAS + 0x70], %i6; \
491 ldx [%sp + STACK_BIAS + 0x78], %i7; \
492 restored; retry; nop; nop; nop; nop; nop; nop; \
493 nop; nop; nop; nop; nop; nop; nop; nop;
494
495#define FILL_0_NORMAL_RTRAP \
496kern_rtt_fill: \
497 rdpr %cwp, %g1; \
498 sub %g1, 1, %g1; \
499 wrpr %g1, %cwp; \
500 ldx [%sp + STACK_BIAS + 0x00], %l0; \
501 ldx [%sp + STACK_BIAS + 0x08], %l1; \
502 ldx [%sp + STACK_BIAS + 0x10], %l2; \
503 ldx [%sp + STACK_BIAS + 0x18], %l3; \
504 ldx [%sp + STACK_BIAS + 0x20], %l4; \
505 ldx [%sp + STACK_BIAS + 0x28], %l5; \
506 ldx [%sp + STACK_BIAS + 0x30], %l6; \
507 ldx [%sp + STACK_BIAS + 0x38], %l7; \
508 ldx [%sp + STACK_BIAS + 0x40], %i0; \
509 ldx [%sp + STACK_BIAS + 0x48], %i1; \
510 ldx [%sp + STACK_BIAS + 0x50], %i2; \
511 ldx [%sp + STACK_BIAS + 0x58], %i3; \
512 ldx [%sp + STACK_BIAS + 0x60], %i4; \
513 ldx [%sp + STACK_BIAS + 0x68], %i5; \
514 ldx [%sp + STACK_BIAS + 0x70], %i6; \
515 ldx [%sp + STACK_BIAS + 0x78], %i7; \
516 restored; \
517 add %g1, 1, %g1; \
518 ba,pt %xcc, kern_rtt_restore; \
519 wrpr %g1, %cwp; \
520 nop; nop; nop; nop; nop; \
521 nop; nop; nop; nop;
522
523
524/* Normal 64bit fill */
525#define FILL_1_GENERIC(ASI) \
526 add %sp, STACK_BIAS + 0x00, %g1; \
527 ldxa [%g1 + %g0] ASI, %l0; \
528 mov 0x08, %g2; \
529 mov 0x10, %g3; \
530 ldxa [%g1 + %g2] ASI, %l1; \
531 mov 0x18, %g5; \
532 ldxa [%g1 + %g3] ASI, %l2; \
533 ldxa [%g1 + %g5] ASI, %l3; \
534 add %g1, 0x20, %g1; \
535 ldxa [%g1 + %g0] ASI, %l4; \
536 ldxa [%g1 + %g2] ASI, %l5; \
537 ldxa [%g1 + %g3] ASI, %l6; \
538 ldxa [%g1 + %g5] ASI, %l7; \
539 add %g1, 0x20, %g1; \
540 ldxa [%g1 + %g0] ASI, %i0; \
541 ldxa [%g1 + %g2] ASI, %i1; \
542 ldxa [%g1 + %g3] ASI, %i2; \
543 ldxa [%g1 + %g5] ASI, %i3; \
544 add %g1, 0x20, %g1; \
545 ldxa [%g1 + %g0] ASI, %i4; \
546 ldxa [%g1 + %g2] ASI, %i5; \
547 ldxa [%g1 + %g3] ASI, %i6; \
548 ldxa [%g1 + %g5] ASI, %i7; \
549 restored; \
550 retry; nop; nop; nop; nop; \
551 b,a,pt %xcc, fill_fixup_dax; \
552 b,a,pt %xcc, fill_fixup_mna; \
553 b,a,pt %xcc, fill_fixup;
554
555#define FILL_1_GENERIC_RTRAP \
556user_rtt_fill_64bit: \
557 ldxa [%sp + STACK_BIAS + 0x00] %asi, %l0; \
558 ldxa [%sp + STACK_BIAS + 0x08] %asi, %l1; \
559 ldxa [%sp + STACK_BIAS + 0x10] %asi, %l2; \
560 ldxa [%sp + STACK_BIAS + 0x18] %asi, %l3; \
561 ldxa [%sp + STACK_BIAS + 0x20] %asi, %l4; \
562 ldxa [%sp + STACK_BIAS + 0x28] %asi, %l5; \
563 ldxa [%sp + STACK_BIAS + 0x30] %asi, %l6; \
564 ldxa [%sp + STACK_BIAS + 0x38] %asi, %l7; \
565 ldxa [%sp + STACK_BIAS + 0x40] %asi, %i0; \
566 ldxa [%sp + STACK_BIAS + 0x48] %asi, %i1; \
567 ldxa [%sp + STACK_BIAS + 0x50] %asi, %i2; \
568 ldxa [%sp + STACK_BIAS + 0x58] %asi, %i3; \
569 ldxa [%sp + STACK_BIAS + 0x60] %asi, %i4; \
570 ldxa [%sp + STACK_BIAS + 0x68] %asi, %i5; \
571 ldxa [%sp + STACK_BIAS + 0x70] %asi, %i6; \
572 ldxa [%sp + STACK_BIAS + 0x78] %asi, %i7; \
573 ba,pt %xcc, user_rtt_pre_restore; \
574 restored; \
575 nop; nop; nop; nop; nop; nop; \
576 nop; nop; nop; nop; nop; \
577 ba,a,pt %xcc, user_rtt_fill_fixup; \
578 ba,a,pt %xcc, user_rtt_fill_fixup; \
579 ba,a,pt %xcc, user_rtt_fill_fixup;
580
581
582/* Normal 32bit fill */
583#define FILL_2_GENERIC(ASI) \
584 srl %sp, 0, %sp; \
585 lduwa [%sp + %g0] ASI, %l0; \
586 mov 0x04, %g2; \
587 mov 0x08, %g3; \
588 lduwa [%sp + %g2] ASI, %l1; \
589 mov 0x0c, %g5; \
590 lduwa [%sp + %g3] ASI, %l2; \
591 lduwa [%sp + %g5] ASI, %l3; \
592 add %sp, 0x10, %g1; \
593 lduwa [%g1 + %g0] ASI, %l4; \
594 lduwa [%g1 + %g2] ASI, %l5; \
595 lduwa [%g1 + %g3] ASI, %l6; \
596 lduwa [%g1 + %g5] ASI, %l7; \
597 add %g1, 0x10, %g1; \
598 lduwa [%g1 + %g0] ASI, %i0; \
599 lduwa [%g1 + %g2] ASI, %i1; \
600 lduwa [%g1 + %g3] ASI, %i2; \
601 lduwa [%g1 + %g5] ASI, %i3; \
602 add %g1, 0x10, %g1; \
603 lduwa [%g1 + %g0] ASI, %i4; \
604 lduwa [%g1 + %g2] ASI, %i5; \
605 lduwa [%g1 + %g3] ASI, %i6; \
606 lduwa [%g1 + %g5] ASI, %i7; \
607 restored; \
608 retry; nop; nop; nop; nop; \
609 b,a,pt %xcc, fill_fixup_dax; \
610 b,a,pt %xcc, fill_fixup_mna; \
611 b,a,pt %xcc, fill_fixup;
612
613#define FILL_2_GENERIC_RTRAP \
614user_rtt_fill_32bit: \
615 srl %sp, 0, %sp; \
616 lduwa [%sp + 0x00] %asi, %l0; \
617 lduwa [%sp + 0x04] %asi, %l1; \
618 lduwa [%sp + 0x08] %asi, %l2; \
619 lduwa [%sp + 0x0c] %asi, %l3; \
620 lduwa [%sp + 0x10] %asi, %l4; \
621 lduwa [%sp + 0x14] %asi, %l5; \
622 lduwa [%sp + 0x18] %asi, %l6; \
623 lduwa [%sp + 0x1c] %asi, %l7; \
624 lduwa [%sp + 0x20] %asi, %i0; \
625 lduwa [%sp + 0x24] %asi, %i1; \
626 lduwa [%sp + 0x28] %asi, %i2; \
627 lduwa [%sp + 0x2c] %asi, %i3; \
628 lduwa [%sp + 0x30] %asi, %i4; \
629 lduwa [%sp + 0x34] %asi, %i5; \
630 lduwa [%sp + 0x38] %asi, %i6; \
631 lduwa [%sp + 0x3c] %asi, %i7; \
632 ba,pt %xcc, user_rtt_pre_restore; \
633 restored; \
634 nop; nop; nop; nop; nop; \
635 nop; nop; nop; nop; nop; \
636 ba,a,pt %xcc, user_rtt_fill_fixup; \
637 ba,a,pt %xcc, user_rtt_fill_fixup; \
638 ba,a,pt %xcc, user_rtt_fill_fixup;
639
640
641#define FILL_1_NORMAL FILL_1_GENERIC(ASI_AIUP)
642#define FILL_2_NORMAL FILL_2_GENERIC(ASI_AIUP)
643#define FILL_3_NORMAL FILL_0_NORMAL
644#define FILL_4_NORMAL FILL_0_NORMAL
645#define FILL_5_NORMAL FILL_0_NORMAL
646#define FILL_6_NORMAL FILL_0_NORMAL
647#define FILL_7_NORMAL FILL_0_NORMAL
648
649#define FILL_0_OTHER FILL_0_NORMAL
650#define FILL_1_OTHER FILL_1_GENERIC(ASI_AIUS)
651#define FILL_2_OTHER FILL_2_GENERIC(ASI_AIUS)
652#define FILL_3_OTHER FILL_3_NORMAL
653#define FILL_4_OTHER FILL_4_NORMAL
654#define FILL_5_OTHER FILL_5_NORMAL
655#define FILL_6_OTHER FILL_6_NORMAL
656#define FILL_7_OTHER FILL_7_NORMAL
657
658#endif /* !(_SPARC64_TTABLE_H) */
diff --git a/include/asm-sparc/turbosparc.h b/include/asm-sparc/turbosparc.h
deleted file mode 100644
index 17c73282db0..00000000000
--- a/include/asm-sparc/turbosparc.h
+++ /dev/null
@@ -1,125 +0,0 @@
1/*
2 * turbosparc.h: Defines specific to the TurboSparc module.
3 * This is SRMMU stuff.
4 *
5 * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7#ifndef _SPARC_TURBOSPARC_H
8#define _SPARC_TURBOSPARC_H
9
10#include <asm/asi.h>
11#include <asm/pgtsrmmu.h>
12
13/* Bits in the SRMMU control register for TurboSparc modules.
14 *
15 * -------------------------------------------------------------------
16 * |impl-vers| RSV| PMC |PE|PC| RSV |BM| RFR |IC|DC|PSO|RSV|ICS|NF|ME|
17 * -------------------------------------------------------------------
18 * 31 24 23-21 20-19 18 17 16-15 14 13-10 9 8 7 6-3 2 1 0
19 *
20 * BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode
21 *
22 * This indicates whether the TurboSparc is in boot-mode or not.
23 *
24 * IC: Instruction Cache -- 0 = off, 1 = on
25 * DC: Data Cache -- 0 = off, 1 = 0n
26 *
27 * These bits enable the on-cpu TurboSparc split I/D caches.
28 *
29 * ICS: ICache Snooping -- 0 = disable, 1 = enable snooping of icache
30 * NF: No Fault -- 0 = faults generate traps, 1 = faults don't trap
31 * ME: MMU enable -- 0 = mmu not translating, 1 = mmu translating
32 *
33 */
34
35#define TURBOSPARC_MMUENABLE 0x00000001
36#define TURBOSPARC_NOFAULT 0x00000002
37#define TURBOSPARC_ICSNOOP 0x00000004
38#define TURBOSPARC_PSO 0x00000080
39#define TURBOSPARC_DCENABLE 0x00000100 /* Enable data cache */
40#define TURBOSPARC_ICENABLE 0x00000200 /* Enable instruction cache */
41#define TURBOSPARC_BMODE 0x00004000
42#define TURBOSPARC_PARITYODD 0x00020000 /* Parity odd, if enabled */
43#define TURBOSPARC_PCENABLE 0x00040000 /* Enable parity checking */
44
45/* Bits in the CPU configuration register for TurboSparc modules.
46 *
47 * -------------------------------------------------------
48 * |IOClk|SNP|AXClk| RAH | WS | RSV |SBC|WT|uS2|SE|SCC|
49 * -------------------------------------------------------
50 * 31 30 29-28 27-26 25-23 22-8 7-6 5 4 3 2-0
51 *
52 */
53
54#define TURBOSPARC_SCENABLE 0x00000008 /* Secondary cache enable */
55#define TURBOSPARC_uS2 0x00000010 /* Swift compatibility mode */
56#define TURBOSPARC_WTENABLE 0x00000020 /* Write thru for dcache */
57#define TURBOSPARC_SNENABLE 0x40000000 /* DVMA snoop enable */
58
59#ifndef __ASSEMBLY__
60
61/* Bits [13:5] select one of 512 instruction cache tags */
62static inline void turbosparc_inv_insn_tag(unsigned long addr)
63{
64 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
65 : /* no outputs */
66 : "r" (addr), "i" (ASI_M_TXTC_TAG)
67 : "memory");
68}
69
70/* Bits [13:5] select one of 512 data cache tags */
71static inline void turbosparc_inv_data_tag(unsigned long addr)
72{
73 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
74 : /* no outputs */
75 : "r" (addr), "i" (ASI_M_DATAC_TAG)
76 : "memory");
77}
78
79static inline void turbosparc_flush_icache(void)
80{
81 unsigned long addr;
82
83 for (addr = 0; addr < 0x4000; addr += 0x20)
84 turbosparc_inv_insn_tag(addr);
85}
86
87static inline void turbosparc_flush_dcache(void)
88{
89 unsigned long addr;
90
91 for (addr = 0; addr < 0x4000; addr += 0x20)
92 turbosparc_inv_data_tag(addr);
93}
94
95static inline void turbosparc_idflash_clear(void)
96{
97 unsigned long addr;
98
99 for (addr = 0; addr < 0x4000; addr += 0x20) {
100 turbosparc_inv_insn_tag(addr);
101 turbosparc_inv_data_tag(addr);
102 }
103}
104
105static inline void turbosparc_set_ccreg(unsigned long regval)
106{
107 __asm__ __volatile__("sta %0, [%1] %2\n\t"
108 : /* no outputs */
109 : "r" (regval), "r" (0x600), "i" (ASI_M_MMUREGS)
110 : "memory");
111}
112
113static inline unsigned long turbosparc_get_ccreg(void)
114{
115 unsigned long regval;
116
117 __asm__ __volatile__("lda [%1] %2, %0\n\t"
118 : "=r" (regval)
119 : "r" (0x600), "i" (ASI_M_MMUREGS));
120 return regval;
121}
122
123#endif /* !__ASSEMBLY__ */
124
125#endif /* !(_SPARC_TURBOSPARC_H) */
diff --git a/include/asm-sparc/types.h b/include/asm-sparc/types.h
deleted file mode 100644
index 8c28fde5eaa..00000000000
--- a/include/asm-sparc/types.h
+++ /dev/null
@@ -1,62 +0,0 @@
1#ifndef _SPARC_TYPES_H
2#define _SPARC_TYPES_H
3/*
4 * This file is never included by application software unless
5 * explicitly requested (e.g., via linux/types.h) in which case the
6 * application is Linux specific so (user-) name space pollution is
7 * not a major issue. However, for interoperability, libraries still
8 * need to be careful to avoid a name clashes.
9 */
10
11#if defined(__sparc__) && defined(__arch64__)
12
13/*** SPARC 64 bit ***/
14#include <asm-generic/int-l64.h>
15
16#ifndef __ASSEMBLY__
17
18typedef unsigned short umode_t;
19
20#endif /* __ASSEMBLY__ */
21
22#ifdef __KERNEL__
23
24#define BITS_PER_LONG 64
25
26#ifndef __ASSEMBLY__
27
28/* Dma addresses come in generic and 64-bit flavours. */
29
30typedef u32 dma_addr_t;
31typedef u64 dma64_addr_t;
32
33#endif /* __ASSEMBLY__ */
34
35#endif /* __KERNEL__ */
36#else
37
38/*** SPARC 32 bit ***/
39#include <asm-generic/int-ll64.h>
40
41#ifndef __ASSEMBLY__
42
43typedef unsigned short umode_t;
44
45#endif /* __ASSEMBLY__ */
46
47#ifdef __KERNEL__
48
49#define BITS_PER_LONG 32
50
51#ifndef __ASSEMBLY__
52
53typedef u32 dma_addr_t;
54typedef u32 dma64_addr_t;
55
56#endif /* __ASSEMBLY__ */
57
58#endif /* __KERNEL__ */
59
60#endif /* defined(__sparc__) && defined(__arch64__) */
61
62#endif /* defined(_SPARC_TYPES_H) */
diff --git a/include/asm-sparc/uaccess.h b/include/asm-sparc/uaccess.h
deleted file mode 100644
index 424facce523..00000000000
--- a/include/asm-sparc/uaccess.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_UACCESS_H
2#define ___ASM_SPARC_UACCESS_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/uaccess_64.h>
5#else
6#include <asm-sparc/uaccess_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/uaccess_32.h b/include/asm-sparc/uaccess_32.h
deleted file mode 100644
index 47d5619d43f..00000000000
--- a/include/asm-sparc/uaccess_32.h
+++ /dev/null
@@ -1,336 +0,0 @@
1/*
2 * uaccess.h: User space memore access functions.
3 *
4 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1996,1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7#ifndef _ASM_UACCESS_H
8#define _ASM_UACCESS_H
9
10#ifdef __KERNEL__
11#include <linux/compiler.h>
12#include <linux/sched.h>
13#include <linux/string.h>
14#include <linux/errno.h>
15#include <asm/vac-ops.h>
16#endif
17
18#ifndef __ASSEMBLY__
19
20/* Sparc is not segmented, however we need to be able to fool access_ok()
21 * when doing system calls from kernel mode legitimately.
22 *
23 * "For historical reasons, these macros are grossly misnamed." -Linus
24 */
25
26#define KERNEL_DS ((mm_segment_t) { 0 })
27#define USER_DS ((mm_segment_t) { -1 })
28
29#define VERIFY_READ 0
30#define VERIFY_WRITE 1
31
32#define get_ds() (KERNEL_DS)
33#define get_fs() (current->thread.current_ds)
34#define set_fs(val) ((current->thread.current_ds) = (val))
35
36#define segment_eq(a,b) ((a).seg == (b).seg)
37
38/* We have there a nice not-mapped page at PAGE_OFFSET - PAGE_SIZE, so that this test
39 * can be fairly lightweight.
40 * No one can read/write anything from userland in the kernel space by setting
41 * large size and address near to PAGE_OFFSET - a fault will break his intentions.
42 */
43#define __user_ok(addr, size) ({ (void)(size); (addr) < STACK_TOP; })
44#define __kernel_ok (segment_eq(get_fs(), KERNEL_DS))
45#define __access_ok(addr,size) (__user_ok((addr) & get_fs().seg,(size)))
46#define access_ok(type, addr, size) \
47 ({ (void)(type); __access_ok((unsigned long)(addr), size); })
48
49/*
50 * The exception table consists of pairs of addresses: the first is the
51 * address of an instruction that is allowed to fault, and the second is
52 * the address at which the program should continue. No registers are
53 * modified, so it is entirely up to the continuation code to figure out
54 * what to do.
55 *
56 * All the routines below use bits of fixup code that are out of line
57 * with the main instruction path. This means when everything is well,
58 * we don't even have to jump over them. Further, they do not intrude
59 * on our cache or tlb entries.
60 *
61 * There is a special way how to put a range of potentially faulting
62 * insns (like twenty ldd/std's with now intervening other instructions)
63 * You specify address of first in insn and 0 in fixup and in the next
64 * exception_table_entry you specify last potentially faulting insn + 1
65 * and in fixup the routine which should handle the fault.
66 * That fixup code will get
67 * (faulting_insn_address - first_insn_in_the_range_address)/4
68 * in %g2 (ie. index of the faulting instruction in the range).
69 */
70
71struct exception_table_entry
72{
73 unsigned long insn, fixup;
74};
75
76/* Returns 0 if exception not found and fixup otherwise. */
77extern unsigned long search_extables_range(unsigned long addr, unsigned long *g2);
78
79extern void __ret_efault(void);
80
81/* Uh, these should become the main single-value transfer routines..
82 * They automatically use the right size if we just have the right
83 * pointer type..
84 *
85 * This gets kind of ugly. We want to return _two_ values in "get_user()"
86 * and yet we don't want to do any pointers, because that is too much
87 * of a performance impact. Thus we have a few rather ugly macros here,
88 * and hide all the ugliness from the user.
89 */
90#define put_user(x,ptr) ({ \
91unsigned long __pu_addr = (unsigned long)(ptr); \
92__chk_user_ptr(ptr); \
93__put_user_check((__typeof__(*(ptr)))(x),__pu_addr,sizeof(*(ptr))); })
94
95#define get_user(x,ptr) ({ \
96unsigned long __gu_addr = (unsigned long)(ptr); \
97__chk_user_ptr(ptr); \
98__get_user_check((x),__gu_addr,sizeof(*(ptr)),__typeof__(*(ptr))); })
99
100/*
101 * The "__xxx" versions do not do address space checking, useful when
102 * doing multiple accesses to the same area (the user has to do the
103 * checks by hand with "access_ok()")
104 */
105#define __put_user(x,ptr) __put_user_nocheck((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr)))
106#define __get_user(x,ptr) __get_user_nocheck((x),(ptr),sizeof(*(ptr)),__typeof__(*(ptr)))
107
108struct __large_struct { unsigned long buf[100]; };
109#define __m(x) ((struct __large_struct __user *)(x))
110
111#define __put_user_check(x,addr,size) ({ \
112register int __pu_ret; \
113if (__access_ok(addr,size)) { \
114switch (size) { \
115case 1: __put_user_asm(x,b,addr,__pu_ret); break; \
116case 2: __put_user_asm(x,h,addr,__pu_ret); break; \
117case 4: __put_user_asm(x,,addr,__pu_ret); break; \
118case 8: __put_user_asm(x,d,addr,__pu_ret); break; \
119default: __pu_ret = __put_user_bad(); break; \
120} } else { __pu_ret = -EFAULT; } __pu_ret; })
121
122#define __put_user_nocheck(x,addr,size) ({ \
123register int __pu_ret; \
124switch (size) { \
125case 1: __put_user_asm(x,b,addr,__pu_ret); break; \
126case 2: __put_user_asm(x,h,addr,__pu_ret); break; \
127case 4: __put_user_asm(x,,addr,__pu_ret); break; \
128case 8: __put_user_asm(x,d,addr,__pu_ret); break; \
129default: __pu_ret = __put_user_bad(); break; \
130} __pu_ret; })
131
132#define __put_user_asm(x,size,addr,ret) \
133__asm__ __volatile__( \
134 "/* Put user asm, inline. */\n" \
135"1:\t" "st"#size " %1, %2\n\t" \
136 "clr %0\n" \
137"2:\n\n\t" \
138 ".section .fixup,#alloc,#execinstr\n\t" \
139 ".align 4\n" \
140"3:\n\t" \
141 "b 2b\n\t" \
142 " mov %3, %0\n\t" \
143 ".previous\n\n\t" \
144 ".section __ex_table,#alloc\n\t" \
145 ".align 4\n\t" \
146 ".word 1b, 3b\n\t" \
147 ".previous\n\n\t" \
148 : "=&r" (ret) : "r" (x), "m" (*__m(addr)), \
149 "i" (-EFAULT))
150
151extern int __put_user_bad(void);
152
153#define __get_user_check(x,addr,size,type) ({ \
154register int __gu_ret; \
155register unsigned long __gu_val; \
156if (__access_ok(addr,size)) { \
157switch (size) { \
158case 1: __get_user_asm(__gu_val,ub,addr,__gu_ret); break; \
159case 2: __get_user_asm(__gu_val,uh,addr,__gu_ret); break; \
160case 4: __get_user_asm(__gu_val,,addr,__gu_ret); break; \
161case 8: __get_user_asm(__gu_val,d,addr,__gu_ret); break; \
162default: __gu_val = 0; __gu_ret = __get_user_bad(); break; \
163} } else { __gu_val = 0; __gu_ret = -EFAULT; } x = (type) __gu_val; __gu_ret; })
164
165#define __get_user_check_ret(x,addr,size,type,retval) ({ \
166register unsigned long __gu_val __asm__ ("l1"); \
167if (__access_ok(addr,size)) { \
168switch (size) { \
169case 1: __get_user_asm_ret(__gu_val,ub,addr,retval); break; \
170case 2: __get_user_asm_ret(__gu_val,uh,addr,retval); break; \
171case 4: __get_user_asm_ret(__gu_val,,addr,retval); break; \
172case 8: __get_user_asm_ret(__gu_val,d,addr,retval); break; \
173default: if (__get_user_bad()) return retval; \
174} x = (type) __gu_val; } else return retval; })
175
176#define __get_user_nocheck(x,addr,size,type) ({ \
177register int __gu_ret; \
178register unsigned long __gu_val; \
179switch (size) { \
180case 1: __get_user_asm(__gu_val,ub,addr,__gu_ret); break; \
181case 2: __get_user_asm(__gu_val,uh,addr,__gu_ret); break; \
182case 4: __get_user_asm(__gu_val,,addr,__gu_ret); break; \
183case 8: __get_user_asm(__gu_val,d,addr,__gu_ret); break; \
184default: __gu_val = 0; __gu_ret = __get_user_bad(); break; \
185} x = (type) __gu_val; __gu_ret; })
186
187#define __get_user_nocheck_ret(x,addr,size,type,retval) ({ \
188register unsigned long __gu_val __asm__ ("l1"); \
189switch (size) { \
190case 1: __get_user_asm_ret(__gu_val,ub,addr,retval); break; \
191case 2: __get_user_asm_ret(__gu_val,uh,addr,retval); break; \
192case 4: __get_user_asm_ret(__gu_val,,addr,retval); break; \
193case 8: __get_user_asm_ret(__gu_val,d,addr,retval); break; \
194default: if (__get_user_bad()) return retval; \
195} x = (type) __gu_val; })
196
197#define __get_user_asm(x,size,addr,ret) \
198__asm__ __volatile__( \
199 "/* Get user asm, inline. */\n" \
200"1:\t" "ld"#size " %2, %1\n\t" \
201 "clr %0\n" \
202"2:\n\n\t" \
203 ".section .fixup,#alloc,#execinstr\n\t" \
204 ".align 4\n" \
205"3:\n\t" \
206 "clr %1\n\t" \
207 "b 2b\n\t" \
208 " mov %3, %0\n\n\t" \
209 ".previous\n\t" \
210 ".section __ex_table,#alloc\n\t" \
211 ".align 4\n\t" \
212 ".word 1b, 3b\n\n\t" \
213 ".previous\n\t" \
214 : "=&r" (ret), "=&r" (x) : "m" (*__m(addr)), \
215 "i" (-EFAULT))
216
217#define __get_user_asm_ret(x,size,addr,retval) \
218if (__builtin_constant_p(retval) && retval == -EFAULT) \
219__asm__ __volatile__( \
220 "/* Get user asm ret, inline. */\n" \
221"1:\t" "ld"#size " %1, %0\n\n\t" \
222 ".section __ex_table,#alloc\n\t" \
223 ".align 4\n\t" \
224 ".word 1b,__ret_efault\n\n\t" \
225 ".previous\n\t" \
226 : "=&r" (x) : "m" (*__m(addr))); \
227else \
228__asm__ __volatile__( \
229 "/* Get user asm ret, inline. */\n" \
230"1:\t" "ld"#size " %1, %0\n\n\t" \
231 ".section .fixup,#alloc,#execinstr\n\t" \
232 ".align 4\n" \
233"3:\n\t" \
234 "ret\n\t" \
235 " restore %%g0, %2, %%o0\n\n\t" \
236 ".previous\n\t" \
237 ".section __ex_table,#alloc\n\t" \
238 ".align 4\n\t" \
239 ".word 1b, 3b\n\n\t" \
240 ".previous\n\t" \
241 : "=&r" (x) : "m" (*__m(addr)), "i" (retval))
242
243extern int __get_user_bad(void);
244
245extern unsigned long __copy_user(void __user *to, const void __user *from, unsigned long size);
246
247static inline unsigned long copy_to_user(void __user *to, const void *from, unsigned long n)
248{
249 if (n && __access_ok((unsigned long) to, n))
250 return __copy_user(to, (__force void __user *) from, n);
251 else
252 return n;
253}
254
255static inline unsigned long __copy_to_user(void __user *to, const void *from, unsigned long n)
256{
257 return __copy_user(to, (__force void __user *) from, n);
258}
259
260static inline unsigned long copy_from_user(void *to, const void __user *from, unsigned long n)
261{
262 if (n && __access_ok((unsigned long) from, n))
263 return __copy_user((__force void __user *) to, from, n);
264 else
265 return n;
266}
267
268static inline unsigned long __copy_from_user(void *to, const void __user *from, unsigned long n)
269{
270 return __copy_user((__force void __user *) to, from, n);
271}
272
273#define __copy_to_user_inatomic __copy_to_user
274#define __copy_from_user_inatomic __copy_from_user
275
276static inline unsigned long __clear_user(void __user *addr, unsigned long size)
277{
278 unsigned long ret;
279
280 __asm__ __volatile__ (
281 ".section __ex_table,#alloc\n\t"
282 ".align 4\n\t"
283 ".word 1f,3\n\t"
284 ".previous\n\t"
285 "mov %2, %%o1\n"
286 "1:\n\t"
287 "call __bzero\n\t"
288 " mov %1, %%o0\n\t"
289 "mov %%o0, %0\n"
290 : "=r" (ret) : "r" (addr), "r" (size) :
291 "o0", "o1", "o2", "o3", "o4", "o5", "o7",
292 "g1", "g2", "g3", "g4", "g5", "g7", "cc");
293
294 return ret;
295}
296
297static inline unsigned long clear_user(void __user *addr, unsigned long n)
298{
299 if (n && __access_ok((unsigned long) addr, n))
300 return __clear_user(addr, n);
301 else
302 return n;
303}
304
305extern long __strncpy_from_user(char *dest, const char __user *src, long count);
306
307static inline long strncpy_from_user(char *dest, const char __user *src, long count)
308{
309 if (__access_ok((unsigned long) src, count))
310 return __strncpy_from_user(dest, src, count);
311 else
312 return -EFAULT;
313}
314
315extern long __strlen_user(const char __user *);
316extern long __strnlen_user(const char __user *, long len);
317
318static inline long strlen_user(const char __user *str)
319{
320 if (!access_ok(VERIFY_READ, str, 0))
321 return 0;
322 else
323 return __strlen_user(str);
324}
325
326static inline long strnlen_user(const char __user *str, long len)
327{
328 if (!access_ok(VERIFY_READ, str, 0))
329 return 0;
330 else
331 return __strnlen_user(str, len);
332}
333
334#endif /* __ASSEMBLY__ */
335
336#endif /* _ASM_UACCESS_H */
diff --git a/include/asm-sparc/uaccess_64.h b/include/asm-sparc/uaccess_64.h
deleted file mode 100644
index 296ef30e05c..00000000000
--- a/include/asm-sparc/uaccess_64.h
+++ /dev/null
@@ -1,273 +0,0 @@
1#ifndef _ASM_UACCESS_H
2#define _ASM_UACCESS_H
3
4/*
5 * User space memory access functions
6 */
7
8#ifdef __KERNEL__
9#include <linux/compiler.h>
10#include <linux/sched.h>
11#include <linux/string.h>
12#include <asm/asi.h>
13#include <asm/system.h>
14#include <asm/spitfire.h>
15#include <asm-generic/uaccess.h>
16#endif
17
18#ifndef __ASSEMBLY__
19
20/*
21 * Sparc64 is segmented, though more like the M68K than the I386.
22 * We use the secondary ASI to address user memory, which references a
23 * completely different VM map, thus there is zero chance of the user
24 * doing something queer and tricking us into poking kernel memory.
25 *
26 * What is left here is basically what is needed for the other parts of
27 * the kernel that expect to be able to manipulate, erum, "segments".
28 * Or perhaps more properly, permissions.
29 *
30 * "For historical reasons, these macros are grossly misnamed." -Linus
31 */
32
33#define KERNEL_DS ((mm_segment_t) { ASI_P })
34#define USER_DS ((mm_segment_t) { ASI_AIUS }) /* har har har */
35
36#define VERIFY_READ 0
37#define VERIFY_WRITE 1
38
39#define get_fs() ((mm_segment_t) { get_thread_current_ds() })
40#define get_ds() (KERNEL_DS)
41
42#define segment_eq(a,b) ((a).seg == (b).seg)
43
44#define set_fs(val) \
45do { \
46 set_thread_current_ds((val).seg); \
47 __asm__ __volatile__ ("wr %%g0, %0, %%asi" : : "r" ((val).seg)); \
48} while(0)
49
50static inline int __access_ok(const void __user * addr, unsigned long size)
51{
52 return 1;
53}
54
55static inline int access_ok(int type, const void __user * addr, unsigned long size)
56{
57 return 1;
58}
59
60/*
61 * The exception table consists of pairs of addresses: the first is the
62 * address of an instruction that is allowed to fault, and the second is
63 * the address at which the program should continue. No registers are
64 * modified, so it is entirely up to the continuation code to figure out
65 * what to do.
66 *
67 * All the routines below use bits of fixup code that are out of line
68 * with the main instruction path. This means when everything is well,
69 * we don't even have to jump over them. Further, they do not intrude
70 * on our cache or tlb entries.
71 */
72
73struct exception_table_entry {
74 unsigned int insn, fixup;
75};
76
77extern void __ret_efault(void);
78extern void __retl_efault(void);
79
80/* Uh, these should become the main single-value transfer routines..
81 * They automatically use the right size if we just have the right
82 * pointer type..
83 *
84 * This gets kind of ugly. We want to return _two_ values in "get_user()"
85 * and yet we don't want to do any pointers, because that is too much
86 * of a performance impact. Thus we have a few rather ugly macros here,
87 * and hide all the ugliness from the user.
88 */
89#define put_user(x,ptr) ({ \
90unsigned long __pu_addr = (unsigned long)(ptr); \
91__chk_user_ptr(ptr); \
92__put_user_nocheck((__typeof__(*(ptr)))(x),__pu_addr,sizeof(*(ptr))); })
93
94#define get_user(x,ptr) ({ \
95unsigned long __gu_addr = (unsigned long)(ptr); \
96__chk_user_ptr(ptr); \
97__get_user_nocheck((x),__gu_addr,sizeof(*(ptr)),__typeof__(*(ptr))); })
98
99#define __put_user(x,ptr) put_user(x,ptr)
100#define __get_user(x,ptr) get_user(x,ptr)
101
102struct __large_struct { unsigned long buf[100]; };
103#define __m(x) ((struct __large_struct *)(x))
104
105#define __put_user_nocheck(data,addr,size) ({ \
106register int __pu_ret; \
107switch (size) { \
108case 1: __put_user_asm(data,b,addr,__pu_ret); break; \
109case 2: __put_user_asm(data,h,addr,__pu_ret); break; \
110case 4: __put_user_asm(data,w,addr,__pu_ret); break; \
111case 8: __put_user_asm(data,x,addr,__pu_ret); break; \
112default: __pu_ret = __put_user_bad(); break; \
113} __pu_ret; })
114
115#define __put_user_asm(x,size,addr,ret) \
116__asm__ __volatile__( \
117 "/* Put user asm, inline. */\n" \
118"1:\t" "st"#size "a %1, [%2] %%asi\n\t" \
119 "clr %0\n" \
120"2:\n\n\t" \
121 ".section .fixup,#alloc,#execinstr\n\t" \
122 ".align 4\n" \
123"3:\n\t" \
124 "sethi %%hi(2b), %0\n\t" \
125 "jmpl %0 + %%lo(2b), %%g0\n\t" \
126 " mov %3, %0\n\n\t" \
127 ".previous\n\t" \
128 ".section __ex_table,\"a\"\n\t" \
129 ".align 4\n\t" \
130 ".word 1b, 3b\n\t" \
131 ".previous\n\n\t" \
132 : "=r" (ret) : "r" (x), "r" (__m(addr)), \
133 "i" (-EFAULT))
134
135extern int __put_user_bad(void);
136
137#define __get_user_nocheck(data,addr,size,type) ({ \
138register int __gu_ret; \
139register unsigned long __gu_val; \
140switch (size) { \
141case 1: __get_user_asm(__gu_val,ub,addr,__gu_ret); break; \
142case 2: __get_user_asm(__gu_val,uh,addr,__gu_ret); break; \
143case 4: __get_user_asm(__gu_val,uw,addr,__gu_ret); break; \
144case 8: __get_user_asm(__gu_val,x,addr,__gu_ret); break; \
145default: __gu_val = 0; __gu_ret = __get_user_bad(); break; \
146} data = (type) __gu_val; __gu_ret; })
147
148#define __get_user_nocheck_ret(data,addr,size,type,retval) ({ \
149register unsigned long __gu_val __asm__ ("l1"); \
150switch (size) { \
151case 1: __get_user_asm_ret(__gu_val,ub,addr,retval); break; \
152case 2: __get_user_asm_ret(__gu_val,uh,addr,retval); break; \
153case 4: __get_user_asm_ret(__gu_val,uw,addr,retval); break; \
154case 8: __get_user_asm_ret(__gu_val,x,addr,retval); break; \
155default: if (__get_user_bad()) return retval; \
156} data = (type) __gu_val; })
157
158#define __get_user_asm(x,size,addr,ret) \
159__asm__ __volatile__( \
160 "/* Get user asm, inline. */\n" \
161"1:\t" "ld"#size "a [%2] %%asi, %1\n\t" \
162 "clr %0\n" \
163"2:\n\n\t" \
164 ".section .fixup,#alloc,#execinstr\n\t" \
165 ".align 4\n" \
166"3:\n\t" \
167 "sethi %%hi(2b), %0\n\t" \
168 "clr %1\n\t" \
169 "jmpl %0 + %%lo(2b), %%g0\n\t" \
170 " mov %3, %0\n\n\t" \
171 ".previous\n\t" \
172 ".section __ex_table,\"a\"\n\t" \
173 ".align 4\n\t" \
174 ".word 1b, 3b\n\n\t" \
175 ".previous\n\t" \
176 : "=r" (ret), "=r" (x) : "r" (__m(addr)), \
177 "i" (-EFAULT))
178
179#define __get_user_asm_ret(x,size,addr,retval) \
180if (__builtin_constant_p(retval) && retval == -EFAULT) \
181__asm__ __volatile__( \
182 "/* Get user asm ret, inline. */\n" \
183"1:\t" "ld"#size "a [%1] %%asi, %0\n\n\t" \
184 ".section __ex_table,\"a\"\n\t" \
185 ".align 4\n\t" \
186 ".word 1b,__ret_efault\n\n\t" \
187 ".previous\n\t" \
188 : "=r" (x) : "r" (__m(addr))); \
189else \
190__asm__ __volatile__( \
191 "/* Get user asm ret, inline. */\n" \
192"1:\t" "ld"#size "a [%1] %%asi, %0\n\n\t" \
193 ".section .fixup,#alloc,#execinstr\n\t" \
194 ".align 4\n" \
195"3:\n\t" \
196 "ret\n\t" \
197 " restore %%g0, %2, %%o0\n\n\t" \
198 ".previous\n\t" \
199 ".section __ex_table,\"a\"\n\t" \
200 ".align 4\n\t" \
201 ".word 1b, 3b\n\n\t" \
202 ".previous\n\t" \
203 : "=r" (x) : "r" (__m(addr)), "i" (retval))
204
205extern int __get_user_bad(void);
206
207extern unsigned long __must_check ___copy_from_user(void *to,
208 const void __user *from,
209 unsigned long size);
210extern unsigned long copy_from_user_fixup(void *to, const void __user *from,
211 unsigned long size);
212static inline unsigned long __must_check
213copy_from_user(void *to, const void __user *from, unsigned long size)
214{
215 unsigned long ret = ___copy_from_user(to, from, size);
216
217 if (unlikely(ret))
218 ret = copy_from_user_fixup(to, from, size);
219 return ret;
220}
221#define __copy_from_user copy_from_user
222
223extern unsigned long __must_check ___copy_to_user(void __user *to,
224 const void *from,
225 unsigned long size);
226extern unsigned long copy_to_user_fixup(void __user *to, const void *from,
227 unsigned long size);
228static inline unsigned long __must_check
229copy_to_user(void __user *to, const void *from, unsigned long size)
230{
231 unsigned long ret = ___copy_to_user(to, from, size);
232
233 if (unlikely(ret))
234 ret = copy_to_user_fixup(to, from, size);
235 return ret;
236}
237#define __copy_to_user copy_to_user
238
239extern unsigned long __must_check ___copy_in_user(void __user *to,
240 const void __user *from,
241 unsigned long size);
242extern unsigned long copy_in_user_fixup(void __user *to, void __user *from,
243 unsigned long size);
244static inline unsigned long __must_check
245copy_in_user(void __user *to, void __user *from, unsigned long size)
246{
247 unsigned long ret = ___copy_in_user(to, from, size);
248
249 if (unlikely(ret))
250 ret = copy_in_user_fixup(to, from, size);
251 return ret;
252}
253#define __copy_in_user copy_in_user
254
255extern unsigned long __must_check __clear_user(void __user *, unsigned long);
256
257#define clear_user __clear_user
258
259extern long __must_check __strncpy_from_user(char *dest, const char __user *src, long count);
260
261#define strncpy_from_user __strncpy_from_user
262
263extern long __strlen_user(const char __user *);
264extern long __strnlen_user(const char __user *, long len);
265
266#define strlen_user __strlen_user
267#define strnlen_user __strnlen_user
268#define __copy_to_user_inatomic __copy_to_user
269#define __copy_from_user_inatomic __copy_from_user
270
271#endif /* __ASSEMBLY__ */
272
273#endif /* _ASM_UACCESS_H */
diff --git a/include/asm-sparc/uctx.h b/include/asm-sparc/uctx.h
deleted file mode 100644
index dc937c75ffd..00000000000
--- a/include/asm-sparc/uctx.h
+++ /dev/null
@@ -1,71 +0,0 @@
1/*
2 * uctx.h: Sparc64 {set,get}context() register state layouts.
3 *
4 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
5 */
6
7#ifndef __SPARC64_UCTX_H
8#define __SPARC64_UCTX_H
9
10#define MC_TSTATE 0
11#define MC_PC 1
12#define MC_NPC 2
13#define MC_Y 3
14#define MC_G1 4
15#define MC_G2 5
16#define MC_G3 6
17#define MC_G4 7
18#define MC_G5 8
19#define MC_G6 9
20#define MC_G7 10
21#define MC_O0 11
22#define MC_O1 12
23#define MC_O2 13
24#define MC_O3 14
25#define MC_O4 15
26#define MC_O5 16
27#define MC_O6 17
28#define MC_O7 18
29#define MC_NGREG 19
30
31typedef unsigned long mc_greg_t;
32typedef mc_greg_t mc_gregset_t[MC_NGREG];
33
34#define MC_MAXFPQ 16
35struct mc_fq {
36 unsigned long *mcfq_addr;
37 unsigned int mcfq_insn;
38};
39
40struct mc_fpu {
41 union {
42 unsigned int sregs[32];
43 unsigned long dregs[32];
44 long double qregs[16];
45 } mcfpu_fregs;
46 unsigned long mcfpu_fsr;
47 unsigned long mcfpu_fprs;
48 unsigned long mcfpu_gsr;
49 struct mc_fq *mcfpu_fq;
50 unsigned char mcfpu_qcnt;
51 unsigned char mcfpu_qentsz;
52 unsigned char mcfpu_enab;
53};
54typedef struct mc_fpu mc_fpu_t;
55
56typedef struct {
57 mc_gregset_t mc_gregs;
58 mc_greg_t mc_fp;
59 mc_greg_t mc_i7;
60 mc_fpu_t mc_fpregs;
61} mcontext_t;
62
63struct ucontext {
64 struct ucontext *uc_link;
65 unsigned long uc_flags;
66 sigset_t uc_sigmask;
67 mcontext_t uc_mcontext;
68};
69typedef struct ucontext ucontext_t;
70
71#endif /* __SPARC64_UCTX_H */
diff --git a/include/asm-sparc/unaligned.h b/include/asm-sparc/unaligned.h
deleted file mode 100644
index 11d2d5fb590..00000000000
--- a/include/asm-sparc/unaligned.h
+++ /dev/null
@@ -1,10 +0,0 @@
1#ifndef _ASM_SPARC_UNALIGNED_H
2#define _ASM_SPARC_UNALIGNED_H
3
4#include <linux/unaligned/be_struct.h>
5#include <linux/unaligned/le_byteshift.h>
6#include <linux/unaligned/generic.h>
7#define get_unaligned __get_unaligned_be
8#define put_unaligned __put_unaligned_be
9
10#endif /* _ASM_SPARC_UNALIGNED_H */
diff --git a/include/asm-sparc/unistd.h b/include/asm-sparc/unistd.h
deleted file mode 100644
index 3c2609618a0..00000000000
--- a/include/asm-sparc/unistd.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_UNISTD_H
2#define ___ASM_SPARC_UNISTD_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/unistd_64.h>
5#else
6#include <asm-sparc/unistd_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/unistd_32.h b/include/asm-sparc/unistd_32.h
deleted file mode 100644
index 648643a9f13..00000000000
--- a/include/asm-sparc/unistd_32.h
+++ /dev/null
@@ -1,384 +0,0 @@
1#ifndef _SPARC_UNISTD_H
2#define _SPARC_UNISTD_H
3
4/*
5 * System calls under the Sparc.
6 *
7 * Don't be scared by the ugly clobbers, it is the only way I can
8 * think of right now to force the arguments into fixed registers
9 * before the trap into the system call with gcc 'asm' statements.
10 *
11 * Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net)
12 *
13 * SunOS compatibility based upon preliminary work which is:
14 *
15 * Copyright (C) 1995 Adrian M. Rodriguez (adrian@remus.rutgers.edu)
16 */
17
18#define __NR_restart_syscall 0 /* Linux Specific */
19#define __NR_exit 1 /* Common */
20#define __NR_fork 2 /* Common */
21#define __NR_read 3 /* Common */
22#define __NR_write 4 /* Common */
23#define __NR_open 5 /* Common */
24#define __NR_close 6 /* Common */
25#define __NR_wait4 7 /* Common */
26#define __NR_creat 8 /* Common */
27#define __NR_link 9 /* Common */
28#define __NR_unlink 10 /* Common */
29#define __NR_execv 11 /* SunOS Specific */
30#define __NR_chdir 12 /* Common */
31#define __NR_chown 13 /* Common */
32#define __NR_mknod 14 /* Common */
33#define __NR_chmod 15 /* Common */
34#define __NR_lchown 16 /* Common */
35#define __NR_brk 17 /* Common */
36#define __NR_perfctr 18 /* Performance counter operations */
37#define __NR_lseek 19 /* Common */
38#define __NR_getpid 20 /* Common */
39#define __NR_capget 21 /* Linux Specific */
40#define __NR_capset 22 /* Linux Specific */
41#define __NR_setuid 23 /* Implemented via setreuid in SunOS */
42#define __NR_getuid 24 /* Common */
43#define __NR_vmsplice 25 /* ENOSYS under SunOS */
44#define __NR_ptrace 26 /* Common */
45#define __NR_alarm 27 /* Implemented via setitimer in SunOS */
46#define __NR_sigaltstack 28 /* Common */
47#define __NR_pause 29 /* Is sigblock(0)->sigpause() in SunOS */
48#define __NR_utime 30 /* Implemented via utimes() under SunOS */
49#define __NR_lchown32 31 /* Linux sparc32 specific */
50#define __NR_fchown32 32 /* Linux sparc32 specific */
51#define __NR_access 33 /* Common */
52#define __NR_nice 34 /* Implemented via get/setpriority() in SunOS */
53#define __NR_chown32 35 /* Linux sparc32 specific */
54#define __NR_sync 36 /* Common */
55#define __NR_kill 37 /* Common */
56#define __NR_stat 38 /* Common */
57#define __NR_sendfile 39 /* Linux Specific */
58#define __NR_lstat 40 /* Common */
59#define __NR_dup 41 /* Common */
60#define __NR_pipe 42 /* Common */
61#define __NR_times 43 /* Implemented via getrusage() in SunOS */
62#define __NR_getuid32 44 /* Linux sparc32 specific */
63#define __NR_umount2 45 /* Linux Specific */
64#define __NR_setgid 46 /* Implemented via setregid() in SunOS */
65#define __NR_getgid 47 /* Common */
66#define __NR_signal 48 /* Implemented via sigvec() in SunOS */
67#define __NR_geteuid 49 /* SunOS calls getuid() */
68#define __NR_getegid 50 /* SunOS calls getgid() */
69#define __NR_acct 51 /* Common */
70/* #define __NR_memory_ordering 52 Linux sparc64 specific */
71#define __NR_getgid32 53 /* Linux sparc32 specific */
72#define __NR_ioctl 54 /* Common */
73#define __NR_reboot 55 /* Common */
74#define __NR_mmap2 56 /* Linux sparc32 Specific */
75#define __NR_symlink 57 /* Common */
76#define __NR_readlink 58 /* Common */
77#define __NR_execve 59 /* Common */
78#define __NR_umask 60 /* Common */
79#define __NR_chroot 61 /* Common */
80#define __NR_fstat 62 /* Common */
81#define __NR_fstat64 63 /* Linux Specific */
82#define __NR_getpagesize 64 /* Common */
83#define __NR_msync 65 /* Common in newer 1.3.x revs... */
84#define __NR_vfork 66 /* Common */
85#define __NR_pread64 67 /* Linux Specific */
86#define __NR_pwrite64 68 /* Linux Specific */
87#define __NR_geteuid32 69 /* Linux sparc32, sbrk under SunOS */
88#define __NR_getegid32 70 /* Linux sparc32, sstk under SunOS */
89#define __NR_mmap 71 /* Common */
90#define __NR_setreuid32 72 /* Linux sparc32, vadvise under SunOS */
91#define __NR_munmap 73 /* Common */
92#define __NR_mprotect 74 /* Common */
93#define __NR_madvise 75 /* Common */
94#define __NR_vhangup 76 /* Common */
95#define __NR_truncate64 77 /* Linux sparc32 Specific */
96#define __NR_mincore 78 /* Common */
97#define __NR_getgroups 79 /* Common */
98#define __NR_setgroups 80 /* Common */
99#define __NR_getpgrp 81 /* Common */
100#define __NR_setgroups32 82 /* Linux sparc32, setpgrp under SunOS */
101#define __NR_setitimer 83 /* Common */
102#define __NR_ftruncate64 84 /* Linux sparc32 Specific */
103#define __NR_swapon 85 /* Common */
104#define __NR_getitimer 86 /* Common */
105#define __NR_setuid32 87 /* Linux sparc32, gethostname under SunOS */
106#define __NR_sethostname 88 /* Common */
107#define __NR_setgid32 89 /* Linux sparc32, getdtablesize under SunOS */
108#define __NR_dup2 90 /* Common */
109#define __NR_setfsuid32 91 /* Linux sparc32, getdopt under SunOS */
110#define __NR_fcntl 92 /* Common */
111#define __NR_select 93 /* Common */
112#define __NR_setfsgid32 94 /* Linux sparc32, setdopt under SunOS */
113#define __NR_fsync 95 /* Common */
114#define __NR_setpriority 96 /* Common */
115#define __NR_socket 97 /* Common */
116#define __NR_connect 98 /* Common */
117#define __NR_accept 99 /* Common */
118#define __NR_getpriority 100 /* Common */
119#define __NR_rt_sigreturn 101 /* Linux Specific */
120#define __NR_rt_sigaction 102 /* Linux Specific */
121#define __NR_rt_sigprocmask 103 /* Linux Specific */
122#define __NR_rt_sigpending 104 /* Linux Specific */
123#define __NR_rt_sigtimedwait 105 /* Linux Specific */
124#define __NR_rt_sigqueueinfo 106 /* Linux Specific */
125#define __NR_rt_sigsuspend 107 /* Linux Specific */
126#define __NR_setresuid32 108 /* Linux Specific, sigvec under SunOS */
127#define __NR_getresuid32 109 /* Linux Specific, sigblock under SunOS */
128#define __NR_setresgid32 110 /* Linux Specific, sigsetmask under SunOS */
129#define __NR_getresgid32 111 /* Linux Specific, sigpause under SunOS */
130#define __NR_setregid32 112 /* Linux sparc32, sigstack under SunOS */
131#define __NR_recvmsg 113 /* Common */
132#define __NR_sendmsg 114 /* Common */
133#define __NR_getgroups32 115 /* Linux sparc32, vtrace under SunOS */
134#define __NR_gettimeofday 116 /* Common */
135#define __NR_getrusage 117 /* Common */
136#define __NR_getsockopt 118 /* Common */
137#define __NR_getcwd 119 /* Linux Specific */
138#define __NR_readv 120 /* Common */
139#define __NR_writev 121 /* Common */
140#define __NR_settimeofday 122 /* Common */
141#define __NR_fchown 123 /* Common */
142#define __NR_fchmod 124 /* Common */
143#define __NR_recvfrom 125 /* Common */
144#define __NR_setreuid 126 /* Common */
145#define __NR_setregid 127 /* Common */
146#define __NR_rename 128 /* Common */
147#define __NR_truncate 129 /* Common */
148#define __NR_ftruncate 130 /* Common */
149#define __NR_flock 131 /* Common */
150#define __NR_lstat64 132 /* Linux Specific */
151#define __NR_sendto 133 /* Common */
152#define __NR_shutdown 134 /* Common */
153#define __NR_socketpair 135 /* Common */
154#define __NR_mkdir 136 /* Common */
155#define __NR_rmdir 137 /* Common */
156#define __NR_utimes 138 /* SunOS Specific */
157#define __NR_stat64 139 /* Linux Specific */
158#define __NR_sendfile64 140 /* adjtime under SunOS */
159#define __NR_getpeername 141 /* Common */
160#define __NR_futex 142 /* gethostid under SunOS */
161#define __NR_gettid 143 /* ENOSYS under SunOS */
162#define __NR_getrlimit 144 /* Common */
163#define __NR_setrlimit 145 /* Common */
164#define __NR_pivot_root 146 /* Linux Specific, killpg under SunOS */
165#define __NR_prctl 147 /* ENOSYS under SunOS */
166#define __NR_pciconfig_read 148 /* ENOSYS under SunOS */
167#define __NR_pciconfig_write 149 /* ENOSYS under SunOS */
168#define __NR_getsockname 150 /* Common */
169#define __NR_inotify_init 151 /* Linux specific */
170#define __NR_inotify_add_watch 152 /* Linux specific */
171#define __NR_poll 153 /* Common */
172#define __NR_getdents64 154 /* Linux specific */
173#define __NR_fcntl64 155 /* Linux sparc32 Specific */
174#define __NR_inotify_rm_watch 156 /* Linux specific */
175#define __NR_statfs 157 /* Common */
176#define __NR_fstatfs 158 /* Common */
177#define __NR_umount 159 /* Common */
178#define __NR_sched_set_affinity 160 /* Linux specific, async_daemon under SunOS */
179#define __NR_sched_get_affinity 161 /* Linux specific, getfh under SunOS */
180#define __NR_getdomainname 162 /* SunOS Specific */
181#define __NR_setdomainname 163 /* Common */
182/* #define __NR_utrap_install 164 Linux sparc64 specific */
183#define __NR_quotactl 165 /* Common */
184#define __NR_set_tid_address 166 /* Linux specific, exportfs under SunOS */
185#define __NR_mount 167 /* Common */
186#define __NR_ustat 168 /* Common */
187#define __NR_setxattr 169 /* SunOS: semsys */
188#define __NR_lsetxattr 170 /* SunOS: msgsys */
189#define __NR_fsetxattr 171 /* SunOS: shmsys */
190#define __NR_getxattr 172 /* SunOS: auditsys */
191#define __NR_lgetxattr 173 /* SunOS: rfssys */
192#define __NR_getdents 174 /* Common */
193#define __NR_setsid 175 /* Common */
194#define __NR_fchdir 176 /* Common */
195#define __NR_fgetxattr 177 /* SunOS: fchroot */
196#define __NR_listxattr 178 /* SunOS: vpixsys */
197#define __NR_llistxattr 179 /* SunOS: aioread */
198#define __NR_flistxattr 180 /* SunOS: aiowrite */
199#define __NR_removexattr 181 /* SunOS: aiowait */
200#define __NR_lremovexattr 182 /* SunOS: aiocancel */
201#define __NR_sigpending 183 /* Common */
202#define __NR_query_module 184 /* Linux Specific */
203#define __NR_setpgid 185 /* Common */
204#define __NR_fremovexattr 186 /* SunOS: pathconf */
205#define __NR_tkill 187 /* SunOS: fpathconf */
206#define __NR_exit_group 188 /* Linux specific, sysconf undef SunOS */
207#define __NR_uname 189 /* Linux Specific */
208#define __NR_init_module 190 /* Linux Specific */
209#define __NR_personality 191 /* Linux Specific */
210#define __NR_remap_file_pages 192 /* Linux Specific */
211#define __NR_epoll_create 193 /* Linux Specific */
212#define __NR_epoll_ctl 194 /* Linux Specific */
213#define __NR_epoll_wait 195 /* Linux Specific */
214#define __NR_ioprio_set 196 /* Linux Specific */
215#define __NR_getppid 197 /* Linux Specific */
216#define __NR_sigaction 198 /* Linux Specific */
217#define __NR_sgetmask 199 /* Linux Specific */
218#define __NR_ssetmask 200 /* Linux Specific */
219#define __NR_sigsuspend 201 /* Linux Specific */
220#define __NR_oldlstat 202 /* Linux Specific */
221#define __NR_uselib 203 /* Linux Specific */
222#define __NR_readdir 204 /* Linux Specific */
223#define __NR_readahead 205 /* Linux Specific */
224#define __NR_socketcall 206 /* Linux Specific */
225#define __NR_syslog 207 /* Linux Specific */
226#define __NR_lookup_dcookie 208 /* Linux Specific */
227#define __NR_fadvise64 209 /* Linux Specific */
228#define __NR_fadvise64_64 210 /* Linux Specific */
229#define __NR_tgkill 211 /* Linux Specific */
230#define __NR_waitpid 212 /* Linux Specific */
231#define __NR_swapoff 213 /* Linux Specific */
232#define __NR_sysinfo 214 /* Linux Specific */
233#define __NR_ipc 215 /* Linux Specific */
234#define __NR_sigreturn 216 /* Linux Specific */
235#define __NR_clone 217 /* Linux Specific */
236#define __NR_ioprio_get 218 /* Linux Specific */
237#define __NR_adjtimex 219 /* Linux Specific */
238#define __NR_sigprocmask 220 /* Linux Specific */
239#define __NR_create_module 221 /* Linux Specific */
240#define __NR_delete_module 222 /* Linux Specific */
241#define __NR_get_kernel_syms 223 /* Linux Specific */
242#define __NR_getpgid 224 /* Linux Specific */
243#define __NR_bdflush 225 /* Linux Specific */
244#define __NR_sysfs 226 /* Linux Specific */
245#define __NR_afs_syscall 227 /* Linux Specific */
246#define __NR_setfsuid 228 /* Linux Specific */
247#define __NR_setfsgid 229 /* Linux Specific */
248#define __NR__newselect 230 /* Linux Specific */
249#define __NR_time 231 /* Linux Specific */
250#define __NR_splice 232 /* Linux Specific */
251#define __NR_stime 233 /* Linux Specific */
252#define __NR_statfs64 234 /* Linux Specific */
253#define __NR_fstatfs64 235 /* Linux Specific */
254#define __NR__llseek 236 /* Linux Specific */
255#define __NR_mlock 237
256#define __NR_munlock 238
257#define __NR_mlockall 239
258#define __NR_munlockall 240
259#define __NR_sched_setparam 241
260#define __NR_sched_getparam 242
261#define __NR_sched_setscheduler 243
262#define __NR_sched_getscheduler 244
263#define __NR_sched_yield 245
264#define __NR_sched_get_priority_max 246
265#define __NR_sched_get_priority_min 247
266#define __NR_sched_rr_get_interval 248
267#define __NR_nanosleep 249
268#define __NR_mremap 250
269#define __NR__sysctl 251
270#define __NR_getsid 252
271#define __NR_fdatasync 253
272#define __NR_nfsservctl 254
273#define __NR_sync_file_range 255
274#define __NR_clock_settime 256
275#define __NR_clock_gettime 257
276#define __NR_clock_getres 258
277#define __NR_clock_nanosleep 259
278#define __NR_sched_getaffinity 260
279#define __NR_sched_setaffinity 261
280#define __NR_timer_settime 262
281#define __NR_timer_gettime 263
282#define __NR_timer_getoverrun 264
283#define __NR_timer_delete 265
284#define __NR_timer_create 266
285/* #define __NR_vserver 267 Reserved for VSERVER */
286#define __NR_io_setup 268
287#define __NR_io_destroy 269
288#define __NR_io_submit 270
289#define __NR_io_cancel 271
290#define __NR_io_getevents 272
291#define __NR_mq_open 273
292#define __NR_mq_unlink 274
293#define __NR_mq_timedsend 275
294#define __NR_mq_timedreceive 276
295#define __NR_mq_notify 277
296#define __NR_mq_getsetattr 278
297#define __NR_waitid 279
298#define __NR_tee 280
299#define __NR_add_key 281
300#define __NR_request_key 282
301#define __NR_keyctl 283
302#define __NR_openat 284
303#define __NR_mkdirat 285
304#define __NR_mknodat 286
305#define __NR_fchownat 287
306#define __NR_futimesat 288
307#define __NR_fstatat64 289
308#define __NR_unlinkat 290
309#define __NR_renameat 291
310#define __NR_linkat 292
311#define __NR_symlinkat 293
312#define __NR_readlinkat 294
313#define __NR_fchmodat 295
314#define __NR_faccessat 296
315#define __NR_pselect6 297
316#define __NR_ppoll 298
317#define __NR_unshare 299
318#define __NR_set_robust_list 300
319#define __NR_get_robust_list 301
320#define __NR_migrate_pages 302
321#define __NR_mbind 303
322#define __NR_get_mempolicy 304
323#define __NR_set_mempolicy 305
324#define __NR_kexec_load 306
325#define __NR_move_pages 307
326#define __NR_getcpu 308
327#define __NR_epoll_pwait 309
328#define __NR_utimensat 310
329#define __NR_signalfd 311
330#define __NR_timerfd_create 312
331#define __NR_eventfd 313
332#define __NR_fallocate 314
333#define __NR_timerfd_settime 315
334#define __NR_timerfd_gettime 316
335#define __NR_signalfd4 317
336#define __NR_eventfd2 318
337#define __NR_epoll_create1 319
338#define __NR_dup3 320
339#define __NR_pipe2 321
340#define __NR_inotify_init1 322
341
342#define NR_SYSCALLS 323
343
344/* Sparc 32-bit only has the "setresuid32", "getresuid32" variants,
345 * it never had the plain ones and there is no value to adding those
346 * old versions into the syscall table.
347 */
348#define __IGNORE_setresuid
349#define __IGNORE_getresuid
350#define __IGNORE_setresgid
351#define __IGNORE_getresgid
352
353#ifdef __KERNEL__
354#define __ARCH_WANT_IPC_PARSE_VERSION
355#define __ARCH_WANT_OLD_READDIR
356#define __ARCH_WANT_STAT64
357#define __ARCH_WANT_SYS_ALARM
358#define __ARCH_WANT_SYS_GETHOSTNAME
359#define __ARCH_WANT_SYS_PAUSE
360#define __ARCH_WANT_SYS_SGETMASK
361#define __ARCH_WANT_SYS_SIGNAL
362#define __ARCH_WANT_SYS_TIME
363#define __ARCH_WANT_SYS_UTIME
364#define __ARCH_WANT_SYS_WAITPID
365#define __ARCH_WANT_SYS_SOCKETCALL
366#define __ARCH_WANT_SYS_FADVISE64
367#define __ARCH_WANT_SYS_GETPGRP
368#define __ARCH_WANT_SYS_LLSEEK
369#define __ARCH_WANT_SYS_NICE
370#define __ARCH_WANT_SYS_OLDUMOUNT
371#define __ARCH_WANT_SYS_SIGPENDING
372#define __ARCH_WANT_SYS_SIGPROCMASK
373#define __ARCH_WANT_SYS_RT_SIGSUSPEND
374
375/*
376 * "Conditional" syscalls
377 *
378 * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
379 * but it doesn't work on all toolchains, so we just do it by hand
380 */
381#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
382
383#endif /* __KERNEL__ */
384#endif /* _SPARC_UNISTD_H */
diff --git a/include/asm-sparc/unistd_64.h b/include/asm-sparc/unistd_64.h
deleted file mode 100644
index c5cc0e05232..00000000000
--- a/include/asm-sparc/unistd_64.h
+++ /dev/null
@@ -1,379 +0,0 @@
1#ifndef _SPARC64_UNISTD_H
2#define _SPARC64_UNISTD_H
3
4/*
5 * System calls under the Sparc.
6 *
7 * Don't be scared by the ugly clobbers, it is the only way I can
8 * think of right now to force the arguments into fixed registers
9 * before the trap into the system call with gcc 'asm' statements.
10 *
11 * Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net)
12 *
13 * SunOS compatibility based upon preliminary work which is:
14 *
15 * Copyright (C) 1995 Adrian M. Rodriguez (adrian@remus.rutgers.edu)
16 */
17
18#define __NR_restart_syscall 0 /* Linux Specific */
19#define __NR_exit 1 /* Common */
20#define __NR_fork 2 /* Common */
21#define __NR_read 3 /* Common */
22#define __NR_write 4 /* Common */
23#define __NR_open 5 /* Common */
24#define __NR_close 6 /* Common */
25#define __NR_wait4 7 /* Common */
26#define __NR_creat 8 /* Common */
27#define __NR_link 9 /* Common */
28#define __NR_unlink 10 /* Common */
29#define __NR_execv 11 /* SunOS Specific */
30#define __NR_chdir 12 /* Common */
31#define __NR_chown 13 /* Common */
32#define __NR_mknod 14 /* Common */
33#define __NR_chmod 15 /* Common */
34#define __NR_lchown 16 /* Common */
35#define __NR_brk 17 /* Common */
36#define __NR_perfctr 18 /* Performance counter operations */
37#define __NR_lseek 19 /* Common */
38#define __NR_getpid 20 /* Common */
39#define __NR_capget 21 /* Linux Specific */
40#define __NR_capset 22 /* Linux Specific */
41#define __NR_setuid 23 /* Implemented via setreuid in SunOS */
42#define __NR_getuid 24 /* Common */
43#define __NR_vmsplice 25 /* ENOSYS under SunOS */
44#define __NR_ptrace 26 /* Common */
45#define __NR_alarm 27 /* Implemented via setitimer in SunOS */
46#define __NR_sigaltstack 28 /* Common */
47#define __NR_pause 29 /* Is sigblock(0)->sigpause() in SunOS */
48#define __NR_utime 30 /* Implemented via utimes() under SunOS */
49/* #define __NR_lchown32 31 Linux sparc32 specific */
50/* #define __NR_fchown32 32 Linux sparc32 specific */
51#define __NR_access 33 /* Common */
52#define __NR_nice 34 /* Implemented via get/setpriority() in SunOS */
53/* #define __NR_chown32 35 Linux sparc32 specific */
54#define __NR_sync 36 /* Common */
55#define __NR_kill 37 /* Common */
56#define __NR_stat 38 /* Common */
57#define __NR_sendfile 39 /* Linux Specific */
58#define __NR_lstat 40 /* Common */
59#define __NR_dup 41 /* Common */
60#define __NR_pipe 42 /* Common */
61#define __NR_times 43 /* Implemented via getrusage() in SunOS */
62/* #define __NR_getuid32 44 Linux sparc32 specific */
63#define __NR_umount2 45 /* Linux Specific */
64#define __NR_setgid 46 /* Implemented via setregid() in SunOS */
65#define __NR_getgid 47 /* Common */
66#define __NR_signal 48 /* Implemented via sigvec() in SunOS */
67#define __NR_geteuid 49 /* SunOS calls getuid() */
68#define __NR_getegid 50 /* SunOS calls getgid() */
69#define __NR_acct 51 /* Common */
70#define __NR_memory_ordering 52 /* Linux Specific */
71/* #define __NR_getgid32 53 Linux sparc32 specific */
72#define __NR_ioctl 54 /* Common */
73#define __NR_reboot 55 /* Common */
74/* #define __NR_mmap2 56 Linux sparc32 Specific */
75#define __NR_symlink 57 /* Common */
76#define __NR_readlink 58 /* Common */
77#define __NR_execve 59 /* Common */
78#define __NR_umask 60 /* Common */
79#define __NR_chroot 61 /* Common */
80#define __NR_fstat 62 /* Common */
81#define __NR_fstat64 63 /* Linux Specific */
82#define __NR_getpagesize 64 /* Common */
83#define __NR_msync 65 /* Common in newer 1.3.x revs... */
84#define __NR_vfork 66 /* Common */
85#define __NR_pread64 67 /* Linux Specific */
86#define __NR_pwrite64 68 /* Linux Specific */
87/* #define __NR_geteuid32 69 Linux sparc32, sbrk under SunOS */
88/* #define __NR_getegid32 70 Linux sparc32, sstk under SunOS */
89#define __NR_mmap 71 /* Common */
90/* #define __NR_setreuid32 72 Linux sparc32, vadvise under SunOS */
91#define __NR_munmap 73 /* Common */
92#define __NR_mprotect 74 /* Common */
93#define __NR_madvise 75 /* Common */
94#define __NR_vhangup 76 /* Common */
95/* #define __NR_truncate64 77 Linux sparc32 Specific */
96#define __NR_mincore 78 /* Common */
97#define __NR_getgroups 79 /* Common */
98#define __NR_setgroups 80 /* Common */
99#define __NR_getpgrp 81 /* Common */
100/* #define __NR_setgroups32 82 Linux sparc32, setpgrp under SunOS */
101#define __NR_setitimer 83 /* Common */
102/* #define __NR_ftruncate64 84 Linux sparc32 Specific */
103#define __NR_swapon 85 /* Common */
104#define __NR_getitimer 86 /* Common */
105/* #define __NR_setuid32 87 Linux sparc32, gethostname under SunOS */
106#define __NR_sethostname 88 /* Common */
107/* #define __NR_setgid32 89 Linux sparc32, getdtablesize under SunOS */
108#define __NR_dup2 90 /* Common */
109/* #define __NR_setfsuid32 91 Linux sparc32, getdopt under SunOS */
110#define __NR_fcntl 92 /* Common */
111#define __NR_select 93 /* Common */
112/* #define __NR_setfsgid32 94 Linux sparc32, setdopt under SunOS */
113#define __NR_fsync 95 /* Common */
114#define __NR_setpriority 96 /* Common */
115#define __NR_socket 97 /* Common */
116#define __NR_connect 98 /* Common */
117#define __NR_accept 99 /* Common */
118#define __NR_getpriority 100 /* Common */
119#define __NR_rt_sigreturn 101 /* Linux Specific */
120#define __NR_rt_sigaction 102 /* Linux Specific */
121#define __NR_rt_sigprocmask 103 /* Linux Specific */
122#define __NR_rt_sigpending 104 /* Linux Specific */
123#define __NR_rt_sigtimedwait 105 /* Linux Specific */
124#define __NR_rt_sigqueueinfo 106 /* Linux Specific */
125#define __NR_rt_sigsuspend 107 /* Linux Specific */
126#define __NR_setresuid 108 /* Linux Specific, sigvec under SunOS */
127#define __NR_getresuid 109 /* Linux Specific, sigblock under SunOS */
128#define __NR_setresgid 110 /* Linux Specific, sigsetmask under SunOS */
129#define __NR_getresgid 111 /* Linux Specific, sigpause under SunOS */
130/* #define __NR_setregid32 75 Linux sparc32, sigstack under SunOS */
131#define __NR_recvmsg 113 /* Common */
132#define __NR_sendmsg 114 /* Common */
133/* #define __NR_getgroups32 115 Linux sparc32, vtrace under SunOS */
134#define __NR_gettimeofday 116 /* Common */
135#define __NR_getrusage 117 /* Common */
136#define __NR_getsockopt 118 /* Common */
137#define __NR_getcwd 119 /* Linux Specific */
138#define __NR_readv 120 /* Common */
139#define __NR_writev 121 /* Common */
140#define __NR_settimeofday 122 /* Common */
141#define __NR_fchown 123 /* Common */
142#define __NR_fchmod 124 /* Common */
143#define __NR_recvfrom 125 /* Common */
144#define __NR_setreuid 126 /* Common */
145#define __NR_setregid 127 /* Common */
146#define __NR_rename 128 /* Common */
147#define __NR_truncate 129 /* Common */
148#define __NR_ftruncate 130 /* Common */
149#define __NR_flock 131 /* Common */
150#define __NR_lstat64 132 /* Linux Specific */
151#define __NR_sendto 133 /* Common */
152#define __NR_shutdown 134 /* Common */
153#define __NR_socketpair 135 /* Common */
154#define __NR_mkdir 136 /* Common */
155#define __NR_rmdir 137 /* Common */
156#define __NR_utimes 138 /* SunOS Specific */
157#define __NR_stat64 139 /* Linux Specific */
158#define __NR_sendfile64 140 /* adjtime under SunOS */
159#define __NR_getpeername 141 /* Common */
160#define __NR_futex 142 /* gethostid under SunOS */
161#define __NR_gettid 143 /* ENOSYS under SunOS */
162#define __NR_getrlimit 144 /* Common */
163#define __NR_setrlimit 145 /* Common */
164#define __NR_pivot_root 146 /* Linux Specific, killpg under SunOS */
165#define __NR_prctl 147 /* ENOSYS under SunOS */
166#define __NR_pciconfig_read 148 /* ENOSYS under SunOS */
167#define __NR_pciconfig_write 149 /* ENOSYS under SunOS */
168#define __NR_getsockname 150 /* Common */
169#define __NR_inotify_init 151 /* Linux specific */
170#define __NR_inotify_add_watch 152 /* Linux specific */
171#define __NR_poll 153 /* Common */
172#define __NR_getdents64 154 /* Linux specific */
173/* #define __NR_fcntl64 155 Linux sparc32 Specific */
174#define __NR_inotify_rm_watch 156 /* Linux specific */
175#define __NR_statfs 157 /* Common */
176#define __NR_fstatfs 158 /* Common */
177#define __NR_umount 159 /* Common */
178#define __NR_sched_set_affinity 160 /* Linux specific, async_daemon under SunOS */
179#define __NR_sched_get_affinity 161 /* Linux specific, getfh under SunOS */
180#define __NR_getdomainname 162 /* SunOS Specific */
181#define __NR_setdomainname 163 /* Common */
182#define __NR_utrap_install 164 /* SYSV ABI/v9 required */
183#define __NR_quotactl 165 /* Common */
184#define __NR_set_tid_address 166 /* Linux specific, exportfs under SunOS */
185#define __NR_mount 167 /* Common */
186#define __NR_ustat 168 /* Common */
187#define __NR_setxattr 169 /* SunOS: semsys */
188#define __NR_lsetxattr 170 /* SunOS: msgsys */
189#define __NR_fsetxattr 171 /* SunOS: shmsys */
190#define __NR_getxattr 172 /* SunOS: auditsys */
191#define __NR_lgetxattr 173 /* SunOS: rfssys */
192#define __NR_getdents 174 /* Common */
193#define __NR_setsid 175 /* Common */
194#define __NR_fchdir 176 /* Common */
195#define __NR_fgetxattr 177 /* SunOS: fchroot */
196#define __NR_listxattr 178 /* SunOS: vpixsys */
197#define __NR_llistxattr 179 /* SunOS: aioread */
198#define __NR_flistxattr 180 /* SunOS: aiowrite */
199#define __NR_removexattr 181 /* SunOS: aiowait */
200#define __NR_lremovexattr 182 /* SunOS: aiocancel */
201#define __NR_sigpending 183 /* Common */
202#define __NR_query_module 184 /* Linux Specific */
203#define __NR_setpgid 185 /* Common */
204#define __NR_fremovexattr 186 /* SunOS: pathconf */
205#define __NR_tkill 187 /* SunOS: fpathconf */
206#define __NR_exit_group 188 /* Linux specific, sysconf undef SunOS */
207#define __NR_uname 189 /* Linux Specific */
208#define __NR_init_module 190 /* Linux Specific */
209#define __NR_personality 191 /* Linux Specific */
210#define __NR_remap_file_pages 192 /* Linux Specific */
211#define __NR_epoll_create 193 /* Linux Specific */
212#define __NR_epoll_ctl 194 /* Linux Specific */
213#define __NR_epoll_wait 195 /* Linux Specific */
214#define __NR_ioprio_set 196 /* Linux Specific */
215#define __NR_getppid 197 /* Linux Specific */
216#define __NR_sigaction 198 /* Linux Specific */
217#define __NR_sgetmask 199 /* Linux Specific */
218#define __NR_ssetmask 200 /* Linux Specific */
219#define __NR_sigsuspend 201 /* Linux Specific */
220#define __NR_oldlstat 202 /* Linux Specific */
221#define __NR_uselib 203 /* Linux Specific */
222#define __NR_readdir 204 /* Linux Specific */
223#define __NR_readahead 205 /* Linux Specific */
224#define __NR_socketcall 206 /* Linux Specific */
225#define __NR_syslog 207 /* Linux Specific */
226#define __NR_lookup_dcookie 208 /* Linux Specific */
227#define __NR_fadvise64 209 /* Linux Specific */
228#define __NR_fadvise64_64 210 /* Linux Specific */
229#define __NR_tgkill 211 /* Linux Specific */
230#define __NR_waitpid 212 /* Linux Specific */
231#define __NR_swapoff 213 /* Linux Specific */
232#define __NR_sysinfo 214 /* Linux Specific */
233#define __NR_ipc 215 /* Linux Specific */
234#define __NR_sigreturn 216 /* Linux Specific */
235#define __NR_clone 217 /* Linux Specific */
236#define __NR_ioprio_get 218 /* Linux Specific */
237#define __NR_adjtimex 219 /* Linux Specific */
238#define __NR_sigprocmask 220 /* Linux Specific */
239#define __NR_create_module 221 /* Linux Specific */
240#define __NR_delete_module 222 /* Linux Specific */
241#define __NR_get_kernel_syms 223 /* Linux Specific */
242#define __NR_getpgid 224 /* Linux Specific */
243#define __NR_bdflush 225 /* Linux Specific */
244#define __NR_sysfs 226 /* Linux Specific */
245#define __NR_afs_syscall 227 /* Linux Specific */
246#define __NR_setfsuid 228 /* Linux Specific */
247#define __NR_setfsgid 229 /* Linux Specific */
248#define __NR__newselect 230 /* Linux Specific */
249#ifdef __KERNEL__
250#define __NR_time 231 /* Linux sparc32 */
251#endif
252#define __NR_splice 232 /* Linux Specific */
253#define __NR_stime 233 /* Linux Specific */
254#define __NR_statfs64 234 /* Linux Specific */
255#define __NR_fstatfs64 235 /* Linux Specific */
256#define __NR__llseek 236 /* Linux Specific */
257#define __NR_mlock 237
258#define __NR_munlock 238
259#define __NR_mlockall 239
260#define __NR_munlockall 240
261#define __NR_sched_setparam 241
262#define __NR_sched_getparam 242
263#define __NR_sched_setscheduler 243
264#define __NR_sched_getscheduler 244
265#define __NR_sched_yield 245
266#define __NR_sched_get_priority_max 246
267#define __NR_sched_get_priority_min 247
268#define __NR_sched_rr_get_interval 248
269#define __NR_nanosleep 249
270#define __NR_mremap 250
271#define __NR__sysctl 251
272#define __NR_getsid 252
273#define __NR_fdatasync 253
274#define __NR_nfsservctl 254
275#define __NR_sync_file_range 255
276#define __NR_clock_settime 256
277#define __NR_clock_gettime 257
278#define __NR_clock_getres 258
279#define __NR_clock_nanosleep 259
280#define __NR_sched_getaffinity 260
281#define __NR_sched_setaffinity 261
282#define __NR_timer_settime 262
283#define __NR_timer_gettime 263
284#define __NR_timer_getoverrun 264
285#define __NR_timer_delete 265
286#define __NR_timer_create 266
287/* #define __NR_vserver 267 Reserved for VSERVER */
288#define __NR_io_setup 268
289#define __NR_io_destroy 269
290#define __NR_io_submit 270
291#define __NR_io_cancel 271
292#define __NR_io_getevents 272
293#define __NR_mq_open 273
294#define __NR_mq_unlink 274
295#define __NR_mq_timedsend 275
296#define __NR_mq_timedreceive 276
297#define __NR_mq_notify 277
298#define __NR_mq_getsetattr 278
299#define __NR_waitid 279
300#define __NR_tee 280
301#define __NR_add_key 281
302#define __NR_request_key 282
303#define __NR_keyctl 283
304#define __NR_openat 284
305#define __NR_mkdirat 285
306#define __NR_mknodat 286
307#define __NR_fchownat 287
308#define __NR_futimesat 288
309#define __NR_fstatat64 289
310#define __NR_unlinkat 290
311#define __NR_renameat 291
312#define __NR_linkat 292
313#define __NR_symlinkat 293
314#define __NR_readlinkat 294
315#define __NR_fchmodat 295
316#define __NR_faccessat 296
317#define __NR_pselect6 297
318#define __NR_ppoll 298
319#define __NR_unshare 299
320#define __NR_set_robust_list 300
321#define __NR_get_robust_list 301
322#define __NR_migrate_pages 302
323#define __NR_mbind 303
324#define __NR_get_mempolicy 304
325#define __NR_set_mempolicy 305
326#define __NR_kexec_load 306
327#define __NR_move_pages 307
328#define __NR_getcpu 308
329#define __NR_epoll_pwait 309
330#define __NR_utimensat 310
331#define __NR_signalfd 311
332#define __NR_timerfd_create 312
333#define __NR_eventfd 313
334#define __NR_fallocate 314
335#define __NR_timerfd_settime 315
336#define __NR_timerfd_gettime 316
337#define __NR_signalfd4 317
338#define __NR_eventfd2 318
339#define __NR_epoll_create1 319
340#define __NR_dup3 320
341#define __NR_pipe2 321
342#define __NR_inotify_init1 322
343
344#define NR_SYSCALLS 323
345
346#ifdef __KERNEL__
347#define __ARCH_WANT_IPC_PARSE_VERSION
348#define __ARCH_WANT_OLD_READDIR
349#define __ARCH_WANT_STAT64
350#define __ARCH_WANT_SYS_ALARM
351#define __ARCH_WANT_SYS_GETHOSTNAME
352#define __ARCH_WANT_SYS_PAUSE
353#define __ARCH_WANT_SYS_SGETMASK
354#define __ARCH_WANT_SYS_SIGNAL
355#define __ARCH_WANT_SYS_TIME
356#define __ARCH_WANT_COMPAT_SYS_TIME
357#define __ARCH_WANT_SYS_UTIME
358#define __ARCH_WANT_SYS_WAITPID
359#define __ARCH_WANT_SYS_SOCKETCALL
360#define __ARCH_WANT_SYS_FADVISE64
361#define __ARCH_WANT_SYS_GETPGRP
362#define __ARCH_WANT_SYS_LLSEEK
363#define __ARCH_WANT_SYS_NICE
364#define __ARCH_WANT_SYS_OLDUMOUNT
365#define __ARCH_WANT_SYS_SIGPENDING
366#define __ARCH_WANT_SYS_SIGPROCMASK
367#define __ARCH_WANT_SYS_RT_SIGSUSPEND
368#define __ARCH_WANT_COMPAT_SYS_RT_SIGSUSPEND
369
370/*
371 * "Conditional" syscalls
372 *
373 * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
374 * but it doesn't work on all toolchains, so we just do it by hand
375 */
376#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
377
378#endif /* __KERNEL__ */
379#endif /* _SPARC64_UNISTD_H */
diff --git a/include/asm-sparc/upa.h b/include/asm-sparc/upa.h
deleted file mode 100644
index 5b1633223f9..00000000000
--- a/include/asm-sparc/upa.h
+++ /dev/null
@@ -1,109 +0,0 @@
1#ifndef _SPARC64_UPA_H
2#define _SPARC64_UPA_H
3
4#include <asm/asi.h>
5
6/* UPA level registers and defines. */
7
8/* UPA Config Register */
9#define UPA_CONFIG_RESV 0xffffffffc0000000 /* Reserved. */
10#define UPA_CONFIG_PCON 0x000000003fc00000 /* Depth of various sys queues. */
11#define UPA_CONFIG_MID 0x00000000003e0000 /* Module ID. */
12#define UPA_CONFIG_PCAP 0x000000000001ffff /* Port Capabilities. */
13
14/* UPA Port ID Register */
15#define UPA_PORTID_FNP 0xff00000000000000 /* Hardcoded to 0xfc on ultra. */
16#define UPA_PORTID_RESV 0x00fffff800000000 /* Reserved. */
17#define UPA_PORTID_ECCVALID 0x0000000400000000 /* Zero if mod can generate ECC */
18#define UPA_PORTID_ONEREAD 0x0000000200000000 /* Set if mod generates P_RASB */
19#define UPA_PORTID_PINTRDQ 0x0000000180000000 /* # outstanding P_INT_REQ's */
20#define UPA_PORTID_PREQDQ 0x000000007e000000 /* slave-wr's to mod supported */
21#define UPA_PORTID_PREQRD 0x0000000001e00000 /* # incoming P_REQ's supported */
22#define UPA_PORTID_UPACAP 0x00000000001f0000 /* UPA capabilities of mod */
23#define UPA_PORTID_ID 0x000000000000ffff /* Module Identification bits */
24
25/* UPA I/O space accessors */
26#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
27static inline unsigned char _upa_readb(unsigned long addr)
28{
29 unsigned char ret;
30
31 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* upa_readb */"
32 : "=r" (ret)
33 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
34
35 return ret;
36}
37
38static inline unsigned short _upa_readw(unsigned long addr)
39{
40 unsigned short ret;
41
42 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* upa_readw */"
43 : "=r" (ret)
44 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
45
46 return ret;
47}
48
49static inline unsigned int _upa_readl(unsigned long addr)
50{
51 unsigned int ret;
52
53 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* upa_readl */"
54 : "=r" (ret)
55 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
56
57 return ret;
58}
59
60static inline unsigned long _upa_readq(unsigned long addr)
61{
62 unsigned long ret;
63
64 __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* upa_readq */"
65 : "=r" (ret)
66 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
67
68 return ret;
69}
70
71static inline void _upa_writeb(unsigned char b, unsigned long addr)
72{
73 __asm__ __volatile__("stba\t%0, [%1] %2\t/* upa_writeb */"
74 : /* no outputs */
75 : "r" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
76}
77
78static inline void _upa_writew(unsigned short w, unsigned long addr)
79{
80 __asm__ __volatile__("stha\t%0, [%1] %2\t/* upa_writew */"
81 : /* no outputs */
82 : "r" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
83}
84
85static inline void _upa_writel(unsigned int l, unsigned long addr)
86{
87 __asm__ __volatile__("stwa\t%0, [%1] %2\t/* upa_writel */"
88 : /* no outputs */
89 : "r" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
90}
91
92static inline void _upa_writeq(unsigned long q, unsigned long addr)
93{
94 __asm__ __volatile__("stxa\t%0, [%1] %2\t/* upa_writeq */"
95 : /* no outputs */
96 : "r" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
97}
98
99#define upa_readb(__addr) (_upa_readb((unsigned long)(__addr)))
100#define upa_readw(__addr) (_upa_readw((unsigned long)(__addr)))
101#define upa_readl(__addr) (_upa_readl((unsigned long)(__addr)))
102#define upa_readq(__addr) (_upa_readq((unsigned long)(__addr)))
103#define upa_writeb(__b, __addr) (_upa_writeb((__b), (unsigned long)(__addr)))
104#define upa_writew(__w, __addr) (_upa_writew((__w), (unsigned long)(__addr)))
105#define upa_writel(__l, __addr) (_upa_writel((__l), (unsigned long)(__addr)))
106#define upa_writeq(__q, __addr) (_upa_writeq((__q), (unsigned long)(__addr)))
107#endif /* __KERNEL__ && !__ASSEMBLY__ */
108
109#endif /* !(_SPARC64_UPA_H) */
diff --git a/include/asm-sparc/user.h b/include/asm-sparc/user.h
deleted file mode 100644
index 3400ea87f14..00000000000
--- a/include/asm-sparc/user.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _SPARC_USER_H
2#define _SPARC_USER_H
3
4/* Nothing to define. */
5
6#endif /* !(_SPARC_USER_H) */
diff --git a/include/asm-sparc/utrap.h b/include/asm-sparc/utrap.h
deleted file mode 100644
index 9da37babbe5..00000000000
--- a/include/asm-sparc/utrap.h
+++ /dev/null
@@ -1,51 +0,0 @@
1/*
2 * include/asm-sparc64/utrap.h
3 *
4 * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
5 */
6
7#ifndef __ASM_SPARC64_UTRAP_H
8#define __ASM_SPARC64_UTRAP_H
9
10#define UT_INSTRUCTION_EXCEPTION 1
11#define UT_INSTRUCTION_ERROR 2
12#define UT_INSTRUCTION_PROTECTION 3
13#define UT_ILLTRAP_INSTRUCTION 4
14#define UT_ILLEGAL_INSTRUCTION 5
15#define UT_PRIVILEGED_OPCODE 6
16#define UT_FP_DISABLED 7
17#define UT_FP_EXCEPTION_IEEE_754 8
18#define UT_FP_EXCEPTION_OTHER 9
19#define UT_TAG_OVERVIEW 10
20#define UT_DIVISION_BY_ZERO 11
21#define UT_DATA_EXCEPTION 12
22#define UT_DATA_ERROR 13
23#define UT_DATA_PROTECTION 14
24#define UT_MEM_ADDRESS_NOT_ALIGNED 15
25#define UT_PRIVILEGED_ACTION 16
26#define UT_ASYNC_DATA_ERROR 17
27#define UT_TRAP_INSTRUCTION_16 18
28#define UT_TRAP_INSTRUCTION_17 19
29#define UT_TRAP_INSTRUCTION_18 20
30#define UT_TRAP_INSTRUCTION_19 21
31#define UT_TRAP_INSTRUCTION_20 22
32#define UT_TRAP_INSTRUCTION_21 23
33#define UT_TRAP_INSTRUCTION_22 24
34#define UT_TRAP_INSTRUCTION_23 25
35#define UT_TRAP_INSTRUCTION_24 26
36#define UT_TRAP_INSTRUCTION_25 27
37#define UT_TRAP_INSTRUCTION_26 28
38#define UT_TRAP_INSTRUCTION_27 29
39#define UT_TRAP_INSTRUCTION_28 30
40#define UT_TRAP_INSTRUCTION_29 31
41#define UT_TRAP_INSTRUCTION_30 32
42#define UT_TRAP_INSTRUCTION_31 33
43
44#define UTH_NOCHANGE (-1)
45
46#ifndef __ASSEMBLY__
47typedef int utrap_entry_t;
48typedef void *utrap_handler_t;
49#endif /* __ASSEMBLY__ */
50
51#endif /* !(__ASM_SPARC64_PROCESSOR_H) */
diff --git a/include/asm-sparc/vac-ops.h b/include/asm-sparc/vac-ops.h
deleted file mode 100644
index d10527611f1..00000000000
--- a/include/asm-sparc/vac-ops.h
+++ /dev/null
@@ -1,134 +0,0 @@
1#ifndef _SPARC_VAC_OPS_H
2#define _SPARC_VAC_OPS_H
3
4/* vac-ops.h: Inline assembly routines to do operations on the Sparc
5 * VAC (virtual address cache) for the sun4c.
6 *
7 * Copyright (C) 1994, David S. Miller (davem@caip.rutgers.edu)
8 */
9
10#include <asm/sysen.h>
11#include <asm/contregs.h>
12#include <asm/asi.h>
13
14/* The SUN4C models have a virtually addressed write-through
15 * cache.
16 *
17 * The cache tags are directly accessible through an ASI and
18 * each have the form:
19 *
20 * ------------------------------------------------------------
21 * | MBZ | CONTEXT | WRITE | PRIV | VALID | MBZ | TagID | MBZ |
22 * ------------------------------------------------------------
23 * 31 25 24 22 21 20 19 18 16 15 2 1 0
24 *
25 * MBZ: These bits are either unused and/or reserved and should
26 * be written as zeroes.
27 *
28 * CONTEXT: Records the context to which this cache line belongs.
29 *
30 * WRITE: A copy of the writable bit from the mmu pte access bits.
31 *
32 * PRIV: A copy of the privileged bit from the pte access bits.
33 *
34 * VALID: If set, this line is valid, else invalid.
35 *
36 * TagID: Fourteen bits of tag ID.
37 *
38 * Every virtual address is seen by the cache like this:
39 *
40 * ----------------------------------------
41 * | RESV | TagID | LINE | BYTE-in-LINE |
42 * ----------------------------------------
43 * 31 30 29 16 15 4 3 0
44 *
45 * RESV: Unused/reserved.
46 *
47 * TagID: Used to match the Tag-ID in that vac tags.
48 *
49 * LINE: Which line within the cache
50 *
51 * BYTE-in-LINE: Which byte within the cache line.
52 */
53
54/* Sun4c VAC Tags */
55#define S4CVACTAG_CID 0x01c00000
56#define S4CVACTAG_W 0x00200000
57#define S4CVACTAG_P 0x00100000
58#define S4CVACTAG_V 0x00080000
59#define S4CVACTAG_TID 0x0000fffc
60
61/* Sun4c VAC Virtual Address */
62/* These aren't used, why bother? (Anton) */
63#if 0
64#define S4CVACVA_TID 0x3fff0000
65#define S4CVACVA_LINE 0x0000fff0
66#define S4CVACVA_BIL 0x0000000f
67#endif
68
69/* The indexing of cache lines creates a problem. Because the line
70 * field of a virtual address extends past the page offset within
71 * the virtual address it is possible to have what are called
72 * 'bad aliases' which will create inconsistencies. So we must make
73 * sure that within a context that if a physical page is mapped
74 * more than once, that 'extra' line bits are the same. If this is
75 * not the case, and thus is a 'bad alias' we must turn off the
76 * cacheable bit in the pte's of all such pages.
77 */
78
79#ifdef CONFIG_SUN4
80#define S4CVAC_BADBITS 0x0001e000
81#else
82#define S4CVAC_BADBITS 0x0000f000
83#endif
84
85/* The following is true if vaddr1 and vaddr2 would cause
86 * a 'bad alias'.
87 */
88#define S4CVAC_BADALIAS(vaddr1, vaddr2) \
89 ((((unsigned long) (vaddr1)) ^ ((unsigned long) (vaddr2))) & \
90 (S4CVAC_BADBITS))
91
92/* The following structure describes the characteristics of a sun4c
93 * VAC as probed from the prom during boot time.
94 */
95struct sun4c_vac_props {
96 unsigned int num_bytes; /* Size of the cache */
97 unsigned int num_lines; /* Number of cache lines */
98 unsigned int do_hwflushes; /* Hardware flushing available? */
99 enum { VAC_NONE, VAC_WRITE_THROUGH,
100 VAC_WRITE_BACK } type; /* What type of VAC? */
101 unsigned int linesize; /* Size of each line in bytes */
102 unsigned int log2lsize; /* log2(linesize) */
103 unsigned int on; /* VAC is enabled */
104};
105
106extern struct sun4c_vac_props sun4c_vacinfo;
107
108/* sun4c_enable_vac() enables the sun4c virtual address cache. */
109static inline void sun4c_enable_vac(void)
110{
111 __asm__ __volatile__("lduba [%0] %1, %%g1\n\t"
112 "or %%g1, %2, %%g1\n\t"
113 "stba %%g1, [%0] %1\n\t"
114 : /* no outputs */
115 : "r" ((unsigned int) AC_SENABLE),
116 "i" (ASI_CONTROL), "i" (SENABLE_CACHE)
117 : "g1", "memory");
118 sun4c_vacinfo.on = 1;
119}
120
121/* sun4c_disable_vac() disables the virtual address cache. */
122static inline void sun4c_disable_vac(void)
123{
124 __asm__ __volatile__("lduba [%0] %1, %%g1\n\t"
125 "andn %%g1, %2, %%g1\n\t"
126 "stba %%g1, [%0] %1\n\t"
127 : /* no outputs */
128 : "r" ((unsigned int) AC_SENABLE),
129 "i" (ASI_CONTROL), "i" (SENABLE_CACHE)
130 : "g1", "memory");
131 sun4c_vacinfo.on = 0;
132}
133
134#endif /* !(_SPARC_VAC_OPS_H) */
diff --git a/include/asm-sparc/vaddrs.h b/include/asm-sparc/vaddrs.h
deleted file mode 100644
index a22fed5a3c6..00000000000
--- a/include/asm-sparc/vaddrs.h
+++ /dev/null
@@ -1,64 +0,0 @@
1#ifndef _SPARC_VADDRS_H
2#define _SPARC_VADDRS_H
3
4#include <asm/head.h>
5
6/*
7 * asm-sparc/vaddrs.h: Here we define the virtual addresses at
8 * which important things will be mapped.
9 *
10 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
11 * Copyright (C) 2000 Anton Blanchard (anton@samba.org)
12 */
13
14#define SRMMU_MAXMEM 0x0c000000
15
16#define SRMMU_NOCACHE_VADDR (KERNBASE + SRMMU_MAXMEM)
17 /* = 0x0fc000000 */
18/* XXX Empiricals - this needs to go away - KMW */
19#define SRMMU_MIN_NOCACHE_PAGES (550)
20#define SRMMU_MAX_NOCACHE_PAGES (1280)
21
22/* The following constant is used in mm/srmmu.c::srmmu_nocache_calcsize()
23 * to determine the amount of memory that will be reserved as nocache:
24 *
25 * 256 pages will be taken as nocache per each
26 * SRMMU_NOCACHE_ALCRATIO MB of system memory.
27 *
28 * limits enforced: nocache minimum = 256 pages
29 * nocache maximum = 1280 pages
30 */
31#define SRMMU_NOCACHE_ALCRATIO 64 /* 256 pages per 64MB of system RAM */
32
33#define SUN4M_IOBASE_VADDR 0xfd000000 /* Base for mapping pages */
34#define IOBASE_VADDR 0xfe000000
35#define IOBASE_END 0xfe600000
36
37/*
38 * On the sun4/4c we need a place
39 * to reliably map locked down kernel data. This includes the
40 * task_struct and kernel stack pages of each process plus the
41 * scsi buffers during dvma IO transfers, also the floppy buffers
42 * during pseudo dma which runs with traps off (no faults allowed).
43 * Some quick calculations yield:
44 * NR_TASKS <512> * (3 * PAGE_SIZE) == 0x600000
45 * Subtract this from 0xc00000 and you get 0x927C0 of vm left
46 * over to map SCSI dvma + floppy pseudo-dma buffers. So be
47 * careful if you change NR_TASKS or else there won't be enough
48 * room for it all.
49 */
50#define SUN4C_LOCK_VADDR 0xff000000
51#define SUN4C_LOCK_END 0xffc00000
52
53#define KADB_DEBUGGER_BEGVM 0xffc00000 /* Where kern debugger is in virt-mem */
54#define KADB_DEBUGGER_ENDVM 0xffd00000
55#define DEBUG_FIRSTVADDR KADB_DEBUGGER_BEGVM
56#define DEBUG_LASTVADDR KADB_DEBUGGER_ENDVM
57
58#define LINUX_OPPROM_BEGVM 0xffd00000
59#define LINUX_OPPROM_ENDVM 0xfff00000
60
61#define DVMA_VADDR 0xfff00000 /* Base area of the DVMA on suns */
62#define DVMA_END 0xfffc0000
63
64#endif /* !(_SPARC_VADDRS_H) */
diff --git a/include/asm-sparc/vfc_ioctls.h b/include/asm-sparc/vfc_ioctls.h
deleted file mode 100644
index af8b69007b2..00000000000
--- a/include/asm-sparc/vfc_ioctls.h
+++ /dev/null
@@ -1,58 +0,0 @@
1/* Copyright (c) 1996 by Manish Vachharajani */
2
3#ifndef _LINUX_VFC_IOCTLS_H_
4#define _LINUX_VFC_IOCTLS_H_
5
6 /* IOCTLs */
7#define VFC_IOCTL(a) (('j' << 8) | a)
8#define VFCGCTRL (VFC_IOCTL (0)) /* get vfc attributes */
9#define VFCSCTRL (VFC_IOCTL (1)) /* set vfc attributes */
10#define VFCGVID (VFC_IOCTL (2)) /* get video decoder attributes */
11#define VFCSVID (VFC_IOCTL (3)) /* set video decoder attributes */
12#define VFCHUE (VFC_IOCTL (4)) /* set hue */
13#define VFCPORTCHG (VFC_IOCTL (5)) /* change port */
14#define VFCRDINFO (VFC_IOCTL (6)) /* read info */
15
16 /* Options for setting the vfc attributes and status */
17#define MEMPRST 0x1 /* reset FIFO ptr. */
18#define CAPTRCMD 0x2 /* start capture and wait */
19#define DIAGMODE 0x3 /* diag mode */
20#define NORMMODE 0x4 /* normal mode */
21#define CAPTRSTR 0x5 /* start capture */
22#define CAPTRWAIT 0x6 /* wait for capture to finish */
23
24
25 /* Options for the decoder */
26#define STD_NTSC 0x1 /* NTSC mode */
27#define STD_PAL 0x2 /* PAL mode */
28#define COLOR_ON 0x3 /* force color ON */
29#define MONO 0x4 /* force color OFF */
30
31 /* Values returned by ioctl 2 */
32
33#define NO_LOCK 1
34#define NTSC_COLOR 2
35#define NTSC_NOCOLOR 3
36#define PAL_COLOR 4
37#define PAL_NOCOLOR 5
38
39/* Not too sure what this does yet */
40 /* Options for setting Field number */
41#define ODD_FIELD 0x1
42#define EVEN_FIELD 0x0
43#define ACTIVE_ONLY 0x2
44#define NON_ACTIVE 0x0
45
46/* Debug options */
47#define VFC_I2C_SEND 0
48#define VFC_I2C_RECV 1
49
50struct vfc_debug_inout
51{
52 unsigned long addr;
53 unsigned long ret;
54 unsigned long len;
55 unsigned char __user *buffer;
56};
57
58#endif /* _LINUX_VFC_IOCTLS_H_ */
diff --git a/include/asm-sparc/vga.h b/include/asm-sparc/vga.h
deleted file mode 100644
index c69d5b2ba19..00000000000
--- a/include/asm-sparc/vga.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * Access to VGA videoram
3 *
4 * (c) 1998 Martin Mares <mj@ucw.cz>
5 */
6
7#ifndef _LINUX_ASM_VGA_H_
8#define _LINUX_ASM_VGA_H_
9
10#include <asm/types.h>
11
12#define VT_BUF_HAVE_RW
13
14#undef scr_writew
15#undef scr_readw
16
17static inline void scr_writew(u16 val, u16 *addr)
18{
19 BUG_ON((long) addr >= 0);
20
21 *addr = val;
22}
23
24static inline u16 scr_readw(const u16 *addr)
25{
26 BUG_ON((long) addr >= 0);
27
28 return *addr;
29}
30
31#define VGA_MAP_MEM(x,s) (x)
32
33#endif
diff --git a/include/asm-sparc/viking.h b/include/asm-sparc/viking.h
deleted file mode 100644
index 989930aeb09..00000000000
--- a/include/asm-sparc/viking.h
+++ /dev/null
@@ -1,253 +0,0 @@
1/*
2 * viking.h: Defines specific to the GNU/Viking MBUS module.
3 * This is SRMMU stuff.
4 *
5 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
6 */
7#ifndef _SPARC_VIKING_H
8#define _SPARC_VIKING_H
9
10#include <asm/asi.h>
11#include <asm/mxcc.h>
12#include <asm/pgtsrmmu.h>
13
14/* Bits in the SRMMU control register for GNU/Viking modules.
15 *
16 * -----------------------------------------------------------
17 * |impl-vers| RSV |TC|AC|SP|BM|PC|MBM|SB|IC|DC|PSO|RSV|NF|ME|
18 * -----------------------------------------------------------
19 * 31 24 23-17 16 15 14 13 12 11 10 9 8 7 6-2 1 0
20 *
21 * TC: Tablewalk Cacheable -- 0 = Twalks are not cacheable in E-cache
22 * 1 = Twalks are cacheable in E-cache
23 *
24 * GNU/Viking will only cache tablewalks in the E-cache (mxcc) if present
25 * and never caches them internally (or so states the docs). Therefore
26 * for machines lacking an E-cache (ie. in MBUS mode) this bit must
27 * remain cleared.
28 *
29 * AC: Alternate Cacheable -- 0 = Passthru physical accesses not cacheable
30 * 1 = Passthru physical accesses cacheable
31 *
32 * This indicates whether accesses are cacheable when no cachable bit
33 * is present in the pte when the processor is in boot-mode or the
34 * access does not need pte's for translation (ie. pass-thru ASI's).
35 * "Cachable" is only referring to E-cache (if present) and not the
36 * on chip split I/D caches of the GNU/Viking.
37 *
38 * SP: SnooP Enable -- 0 = bus snooping off, 1 = bus snooping on
39 *
40 * This enables snooping on the GNU/Viking bus. This must be on
41 * for the hardware cache consistency mechanisms of the GNU/Viking
42 * to work at all. On non-mxcc GNU/Viking modules the split I/D
43 * caches will snoop regardless of whether they are enabled, this
44 * takes care of the case where the I or D or both caches are turned
45 * off yet still contain valid data. Note also that this bit does
46 * not affect GNU/Viking store-buffer snoops, those happen if the
47 * store-buffer is enabled no matter what.
48 *
49 * BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode
50 *
51 * This indicates whether the GNU/Viking is in boot-mode or not,
52 * if it is then all instruction fetch physical addresses are
53 * computed as 0xff0000000 + low 28 bits of requested address.
54 * GNU/Viking boot-mode does not affect data accesses. Also,
55 * in boot mode instruction accesses bypass the split on chip I/D
56 * caches, they may be cached by the GNU/MXCC if present and enabled.
57 *
58 * MBM: MBus Mode -- 0 = not in MBus mode, 1 = in MBus mode
59 *
60 * This indicated the GNU/Viking configuration present. If in
61 * MBUS mode, the GNU/Viking lacks a GNU/MXCC E-cache. If it is
62 * not then the GNU/Viking is on a module VBUS connected directly
63 * to a GNU/MXCC cache controller. The GNU/MXCC can be thus connected
64 * to either an GNU/MBUS (sun4m) or the packet-switched GNU/XBus (sun4d).
65 *
66 * SB: StoreBuffer enable -- 0 = store buffer off, 1 = store buffer on
67 *
68 * The GNU/Viking store buffer allows the chip to continue execution
69 * after a store even if the data cannot be placed in one of the
70 * caches during that cycle. If disabled, all stores operations
71 * occur synchronously.
72 *
73 * IC: Instruction Cache -- 0 = off, 1 = on
74 * DC: Data Cache -- 0 = off, 1 = 0n
75 *
76 * These bits enable the on-cpu GNU/Viking split I/D caches. Note,
77 * as mentioned above, these caches will snoop the bus in GNU/MBUS
78 * configurations even when disabled to avoid data corruption.
79 *
80 * NF: No Fault -- 0 = faults generate traps, 1 = faults don't trap
81 * ME: MMU enable -- 0 = mmu not translating, 1 = mmu translating
82 *
83 */
84
85#define VIKING_MMUENABLE 0x00000001
86#define VIKING_NOFAULT 0x00000002
87#define VIKING_PSO 0x00000080
88#define VIKING_DCENABLE 0x00000100 /* Enable data cache */
89#define VIKING_ICENABLE 0x00000200 /* Enable instruction cache */
90#define VIKING_SBENABLE 0x00000400 /* Enable store buffer */
91#define VIKING_MMODE 0x00000800 /* MBUS mode */
92#define VIKING_PCENABLE 0x00001000 /* Enable parity checking */
93#define VIKING_BMODE 0x00002000
94#define VIKING_SPENABLE 0x00004000 /* Enable bus cache snooping */
95#define VIKING_ACENABLE 0x00008000 /* Enable alternate caching */
96#define VIKING_TCENABLE 0x00010000 /* Enable table-walks to be cached */
97#define VIKING_DPENABLE 0x00040000 /* Enable the data prefetcher */
98
99/*
100 * GNU/Viking Breakpoint Action Register fields.
101 */
102#define VIKING_ACTION_MIX 0x00001000 /* Enable multiple instructions */
103
104/*
105 * GNU/Viking Cache Tags.
106 */
107#define VIKING_PTAG_VALID 0x01000000 /* Cache block is valid */
108#define VIKING_PTAG_DIRTY 0x00010000 /* Block has been modified */
109#define VIKING_PTAG_SHARED 0x00000100 /* Shared with some other cache */
110
111#ifndef __ASSEMBLY__
112
113static inline void viking_flush_icache(void)
114{
115 __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
116 : /* no outputs */
117 : "i" (ASI_M_IC_FLCLEAR)
118 : "memory");
119}
120
121static inline void viking_flush_dcache(void)
122{
123 __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
124 : /* no outputs */
125 : "i" (ASI_M_DC_FLCLEAR)
126 : "memory");
127}
128
129static inline void viking_unlock_icache(void)
130{
131 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
132 : /* no outputs */
133 : "r" (0x80000000), "i" (ASI_M_IC_FLCLEAR)
134 : "memory");
135}
136
137static inline void viking_unlock_dcache(void)
138{
139 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
140 : /* no outputs */
141 : "r" (0x80000000), "i" (ASI_M_DC_FLCLEAR)
142 : "memory");
143}
144
145static inline void viking_set_bpreg(unsigned long regval)
146{
147 __asm__ __volatile__("sta %0, [%%g0] %1\n\t"
148 : /* no outputs */
149 : "r" (regval), "i" (ASI_M_ACTION)
150 : "memory");
151}
152
153static inline unsigned long viking_get_bpreg(void)
154{
155 unsigned long regval;
156
157 __asm__ __volatile__("lda [%%g0] %1, %0\n\t"
158 : "=r" (regval)
159 : "i" (ASI_M_ACTION));
160 return regval;
161}
162
163static inline void viking_get_dcache_ptag(int set, int block,
164 unsigned long *data)
165{
166 unsigned long ptag = ((set & 0x7f) << 5) | ((block & 0x3) << 26) |
167 0x80000000;
168 unsigned long info, page;
169
170 __asm__ __volatile__ ("ldda [%2] %3, %%g2\n\t"
171 "or %%g0, %%g2, %0\n\t"
172 "or %%g0, %%g3, %1\n\t"
173 : "=r" (info), "=r" (page)
174 : "r" (ptag), "i" (ASI_M_DATAC_TAG)
175 : "g2", "g3");
176 data[0] = info;
177 data[1] = page;
178}
179
180static inline void viking_mxcc_turn_off_parity(unsigned long *mregp,
181 unsigned long *mxcc_cregp)
182{
183 unsigned long mreg = *mregp;
184 unsigned long mxcc_creg = *mxcc_cregp;
185
186 mreg &= ~(VIKING_PCENABLE);
187 mxcc_creg &= ~(MXCC_CTL_PARE);
188
189 __asm__ __volatile__ ("set 1f, %%g2\n\t"
190 "andcc %%g2, 4, %%g0\n\t"
191 "bne 2f\n\t"
192 " nop\n"
193 "1:\n\t"
194 "sta %0, [%%g0] %3\n\t"
195 "sta %1, [%2] %4\n\t"
196 "b 1f\n\t"
197 " nop\n\t"
198 "nop\n"
199 "2:\n\t"
200 "sta %0, [%%g0] %3\n\t"
201 "sta %1, [%2] %4\n"
202 "1:\n\t"
203 : /* no output */
204 : "r" (mreg), "r" (mxcc_creg),
205 "r" (MXCC_CREG), "i" (ASI_M_MMUREGS),
206 "i" (ASI_M_MXCC)
207 : "g2", "memory", "cc");
208 *mregp = mreg;
209 *mxcc_cregp = mxcc_creg;
210}
211
212static inline unsigned long viking_hwprobe(unsigned long vaddr)
213{
214 unsigned long val;
215
216 vaddr &= PAGE_MASK;
217 /* Probe all MMU entries. */
218 __asm__ __volatile__("lda [%1] %2, %0\n\t"
219 : "=r" (val)
220 : "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
221 if (!val)
222 return 0;
223
224 /* Probe region. */
225 __asm__ __volatile__("lda [%1] %2, %0\n\t"
226 : "=r" (val)
227 : "r" (vaddr | 0x200), "i" (ASI_M_FLUSH_PROBE));
228 if ((val & SRMMU_ET_MASK) == SRMMU_ET_PTE) {
229 vaddr &= ~SRMMU_PGDIR_MASK;
230 vaddr >>= PAGE_SHIFT;
231 return val | (vaddr << 8);
232 }
233
234 /* Probe segment. */
235 __asm__ __volatile__("lda [%1] %2, %0\n\t"
236 : "=r" (val)
237 : "r" (vaddr | 0x100), "i" (ASI_M_FLUSH_PROBE));
238 if ((val & SRMMU_ET_MASK) == SRMMU_ET_PTE) {
239 vaddr &= ~SRMMU_REAL_PMD_MASK;
240 vaddr >>= PAGE_SHIFT;
241 return val | (vaddr << 8);
242 }
243
244 /* Probe page. */
245 __asm__ __volatile__("lda [%1] %2, %0\n\t"
246 : "=r" (val)
247 : "r" (vaddr), "i" (ASI_M_FLUSH_PROBE));
248 return val;
249}
250
251#endif /* !__ASSEMBLY__ */
252
253#endif /* !(_SPARC_VIKING_H) */
diff --git a/include/asm-sparc/vio.h b/include/asm-sparc/vio.h
deleted file mode 100644
index d4de32f0f8a..00000000000
--- a/include/asm-sparc/vio.h
+++ /dev/null
@@ -1,406 +0,0 @@
1#ifndef _SPARC64_VIO_H
2#define _SPARC64_VIO_H
3
4#include <linux/kernel.h>
5#include <linux/device.h>
6#include <linux/mod_devicetable.h>
7#include <linux/timer.h>
8#include <linux/spinlock.h>
9#include <linux/completion.h>
10#include <linux/list.h>
11#include <linux/log2.h>
12
13#include <asm/ldc.h>
14#include <asm/mdesc.h>
15
16struct vio_msg_tag {
17 u8 type;
18#define VIO_TYPE_CTRL 0x01
19#define VIO_TYPE_DATA 0x02
20#define VIO_TYPE_ERR 0x04
21
22 u8 stype;
23#define VIO_SUBTYPE_INFO 0x01
24#define VIO_SUBTYPE_ACK 0x02
25#define VIO_SUBTYPE_NACK 0x04
26
27 u16 stype_env;
28#define VIO_VER_INFO 0x0001
29#define VIO_ATTR_INFO 0x0002
30#define VIO_DRING_REG 0x0003
31#define VIO_DRING_UNREG 0x0004
32#define VIO_RDX 0x0005
33#define VIO_PKT_DATA 0x0040
34#define VIO_DESC_DATA 0x0041
35#define VIO_DRING_DATA 0x0042
36#define VNET_MCAST_INFO 0x0101
37
38 u32 sid;
39};
40
41struct vio_rdx {
42 struct vio_msg_tag tag;
43 u64 resv[6];
44};
45
46struct vio_ver_info {
47 struct vio_msg_tag tag;
48 u16 major;
49 u16 minor;
50 u8 dev_class;
51#define VDEV_NETWORK 0x01
52#define VDEV_NETWORK_SWITCH 0x02
53#define VDEV_DISK 0x03
54#define VDEV_DISK_SERVER 0x04
55
56 u8 resv1[3];
57 u64 resv2[5];
58};
59
60struct vio_dring_register {
61 struct vio_msg_tag tag;
62 u64 dring_ident;
63 u32 num_descr;
64 u32 descr_size;
65 u16 options;
66#define VIO_TX_DRING 0x0001
67#define VIO_RX_DRING 0x0002
68 u16 resv;
69 u32 num_cookies;
70 struct ldc_trans_cookie cookies[0];
71};
72
73struct vio_dring_unregister {
74 struct vio_msg_tag tag;
75 u64 dring_ident;
76 u64 resv[5];
77};
78
79/* Data transfer modes */
80#define VIO_PKT_MODE 0x01 /* Packet based transfer */
81#define VIO_DESC_MODE 0x02 /* In-band descriptors */
82#define VIO_DRING_MODE 0x03 /* Descriptor rings */
83
84struct vio_dring_data {
85 struct vio_msg_tag tag;
86 u64 seq;
87 u64 dring_ident;
88 u32 start_idx;
89 u32 end_idx;
90 u8 state;
91#define VIO_DRING_ACTIVE 0x01
92#define VIO_DRING_STOPPED 0x02
93
94 u8 __pad1;
95 u16 __pad2;
96 u32 __pad3;
97 u64 __par4[2];
98};
99
100struct vio_dring_hdr {
101 u8 state;
102#define VIO_DESC_FREE 0x01
103#define VIO_DESC_READY 0x02
104#define VIO_DESC_ACCEPTED 0x03
105#define VIO_DESC_DONE 0x04
106 u8 ack;
107#define VIO_ACK_ENABLE 0x01
108#define VIO_ACK_DISABLE 0x00
109
110 u16 __pad1;
111 u32 __pad2;
112};
113
114/* VIO disk specific structures and defines */
115struct vio_disk_attr_info {
116 struct vio_msg_tag tag;
117 u8 xfer_mode;
118 u8 vdisk_type;
119#define VD_DISK_TYPE_SLICE 0x01 /* Slice in block device */
120#define VD_DISK_TYPE_DISK 0x02 /* Entire block device */
121 u16 resv1;
122 u32 vdisk_block_size;
123 u64 operations;
124 u64 vdisk_size;
125 u64 max_xfer_size;
126 u64 resv2[2];
127};
128
129struct vio_disk_desc {
130 struct vio_dring_hdr hdr;
131 u64 req_id;
132 u8 operation;
133#define VD_OP_BREAD 0x01 /* Block read */
134#define VD_OP_BWRITE 0x02 /* Block write */
135#define VD_OP_FLUSH 0x03 /* Flush disk contents */
136#define VD_OP_GET_WCE 0x04 /* Get write-cache status */
137#define VD_OP_SET_WCE 0x05 /* Enable/disable write-cache */
138#define VD_OP_GET_VTOC 0x06 /* Get VTOC */
139#define VD_OP_SET_VTOC 0x07 /* Set VTOC */
140#define VD_OP_GET_DISKGEOM 0x08 /* Get disk geometry */
141#define VD_OP_SET_DISKGEOM 0x09 /* Set disk geometry */
142#define VD_OP_SCSICMD 0x0a /* SCSI control command */
143#define VD_OP_GET_DEVID 0x0b /* Get device ID */
144#define VD_OP_GET_EFI 0x0c /* Get EFI */
145#define VD_OP_SET_EFI 0x0d /* Set EFI */
146 u8 slice;
147 u16 resv1;
148 u32 status;
149 u64 offset;
150 u64 size;
151 u32 ncookies;
152 u32 resv2;
153 struct ldc_trans_cookie cookies[0];
154};
155
156#define VIO_DISK_VNAME_LEN 8
157#define VIO_DISK_ALABEL_LEN 128
158#define VIO_DISK_NUM_PART 8
159
160struct vio_disk_vtoc {
161 u8 volume_name[VIO_DISK_VNAME_LEN];
162 u16 sector_size;
163 u16 num_partitions;
164 u8 ascii_label[VIO_DISK_ALABEL_LEN];
165 struct {
166 u16 id;
167 u16 perm_flags;
168 u32 resv;
169 u64 start_block;
170 u64 num_blocks;
171 } partitions[VIO_DISK_NUM_PART];
172};
173
174struct vio_disk_geom {
175 u16 num_cyl; /* Num data cylinders */
176 u16 alt_cyl; /* Num alternate cylinders */
177 u16 beg_cyl; /* Cyl off of fixed head area */
178 u16 num_hd; /* Num heads */
179 u16 num_sec; /* Num sectors */
180 u16 ifact; /* Interleave factor */
181 u16 apc; /* Alts per cylinder (SCSI) */
182 u16 rpm; /* Revolutions per minute */
183 u16 phy_cyl; /* Num physical cylinders */
184 u16 wr_skip; /* Num sects to skip, writes */
185 u16 rd_skip; /* Num sects to skip, writes */
186};
187
188struct vio_disk_devid {
189 u16 resv;
190 u16 type;
191 u32 len;
192 char id[0];
193};
194
195struct vio_disk_efi {
196 u64 lba;
197 u64 len;
198 char data[0];
199};
200
201/* VIO net specific structures and defines */
202struct vio_net_attr_info {
203 struct vio_msg_tag tag;
204 u8 xfer_mode;
205 u8 addr_type;
206#define VNET_ADDR_ETHERMAC 0x01
207 u16 ack_freq;
208 u32 resv1;
209 u64 addr;
210 u64 mtu;
211 u64 resv2[3];
212};
213
214#define VNET_NUM_MCAST 7
215
216struct vio_net_mcast_info {
217 struct vio_msg_tag tag;
218 u8 set;
219 u8 count;
220 u8 mcast_addr[VNET_NUM_MCAST * 6];
221 u32 resv;
222};
223
224struct vio_net_desc {
225 struct vio_dring_hdr hdr;
226 u32 size;
227 u32 ncookies;
228 struct ldc_trans_cookie cookies[0];
229};
230
231#define VIO_MAX_RING_COOKIES 24
232
233struct vio_dring_state {
234 u64 ident;
235 void *base;
236 u64 snd_nxt;
237 u64 rcv_nxt;
238 u32 entry_size;
239 u32 num_entries;
240 u32 prod;
241 u32 cons;
242 u32 pending;
243 int ncookies;
244 struct ldc_trans_cookie cookies[VIO_MAX_RING_COOKIES];
245};
246
247static inline void *vio_dring_cur(struct vio_dring_state *dr)
248{
249 return dr->base + (dr->entry_size * dr->prod);
250}
251
252static inline void *vio_dring_entry(struct vio_dring_state *dr,
253 unsigned int index)
254{
255 return dr->base + (dr->entry_size * index);
256}
257
258static inline u32 vio_dring_avail(struct vio_dring_state *dr,
259 unsigned int ring_size)
260{
261 BUILD_BUG_ON(!is_power_of_2(ring_size));
262
263 return (dr->pending -
264 ((dr->prod - dr->cons) & (ring_size - 1)));
265}
266
267#define VIO_MAX_TYPE_LEN 32
268#define VIO_MAX_COMPAT_LEN 64
269
270struct vio_dev {
271 u64 mp;
272 struct device_node *dp;
273
274 char type[VIO_MAX_TYPE_LEN];
275 char compat[VIO_MAX_COMPAT_LEN];
276 int compat_len;
277
278 u64 dev_no;
279
280 unsigned long channel_id;
281
282 unsigned int tx_irq;
283 unsigned int rx_irq;
284
285 struct device dev;
286};
287
288struct vio_driver {
289 struct list_head node;
290 const struct vio_device_id *id_table;
291 int (*probe)(struct vio_dev *dev, const struct vio_device_id *id);
292 int (*remove)(struct vio_dev *dev);
293 void (*shutdown)(struct vio_dev *dev);
294 unsigned long driver_data;
295 struct device_driver driver;
296};
297
298struct vio_version {
299 u16 major;
300 u16 minor;
301};
302
303struct vio_driver_state;
304struct vio_driver_ops {
305 int (*send_attr)(struct vio_driver_state *vio);
306 int (*handle_attr)(struct vio_driver_state *vio, void *pkt);
307 void (*handshake_complete)(struct vio_driver_state *vio);
308};
309
310struct vio_completion {
311 struct completion com;
312 int err;
313 int waiting_for;
314};
315
316struct vio_driver_state {
317 /* Protects VIO handshake and, optionally, driver private state. */
318 spinlock_t lock;
319
320 struct ldc_channel *lp;
321
322 u32 _peer_sid;
323 u32 _local_sid;
324 struct vio_dring_state drings[2];
325#define VIO_DRIVER_TX_RING 0
326#define VIO_DRIVER_RX_RING 1
327
328 u8 hs_state;
329#define VIO_HS_INVALID 0x00
330#define VIO_HS_GOTVERS 0x01
331#define VIO_HS_GOT_ATTR 0x04
332#define VIO_HS_SENT_DREG 0x08
333#define VIO_HS_SENT_RDX 0x10
334#define VIO_HS_GOT_RDX_ACK 0x20
335#define VIO_HS_GOT_RDX 0x40
336#define VIO_HS_SENT_RDX_ACK 0x80
337#define VIO_HS_COMPLETE (VIO_HS_GOT_RDX_ACK | VIO_HS_SENT_RDX_ACK)
338
339 u8 dev_class;
340
341 u8 dr_state;
342#define VIO_DR_STATE_TXREG 0x01
343#define VIO_DR_STATE_RXREG 0x02
344#define VIO_DR_STATE_TXREQ 0x10
345#define VIO_DR_STATE_RXREQ 0x20
346
347 u8 debug;
348#define VIO_DEBUG_HS 0x01
349#define VIO_DEBUG_DATA 0x02
350
351 void *desc_buf;
352 unsigned int desc_buf_len;
353
354 struct vio_completion *cmp;
355
356 struct vio_dev *vdev;
357
358 struct timer_list timer;
359
360 struct vio_version ver;
361
362 struct vio_version *ver_table;
363 int ver_table_entries;
364
365 char *name;
366
367 struct vio_driver_ops *ops;
368};
369
370#define viodbg(TYPE, f, a...) \
371do { if (vio->debug & VIO_DEBUG_##TYPE) \
372 printk(KERN_INFO "vio: ID[%lu] " f, \
373 vio->vdev->channel_id, ## a); \
374} while (0)
375
376extern int vio_register_driver(struct vio_driver *drv);
377extern void vio_unregister_driver(struct vio_driver *drv);
378
379static inline struct vio_driver *to_vio_driver(struct device_driver *drv)
380{
381 return container_of(drv, struct vio_driver, driver);
382}
383
384static inline struct vio_dev *to_vio_dev(struct device *dev)
385{
386 return container_of(dev, struct vio_dev, dev);
387}
388
389extern int vio_ldc_send(struct vio_driver_state *vio, void *data, int len);
390extern void vio_link_state_change(struct vio_driver_state *vio, int event);
391extern void vio_conn_reset(struct vio_driver_state *vio);
392extern int vio_control_pkt_engine(struct vio_driver_state *vio, void *pkt);
393extern int vio_validate_sid(struct vio_driver_state *vio,
394 struct vio_msg_tag *tp);
395extern u32 vio_send_sid(struct vio_driver_state *vio);
396extern int vio_ldc_alloc(struct vio_driver_state *vio,
397 struct ldc_channel_config *base_cfg, void *event_arg);
398extern void vio_ldc_free(struct vio_driver_state *vio);
399extern int vio_driver_init(struct vio_driver_state *vio, struct vio_dev *vdev,
400 u8 dev_class, struct vio_version *ver_table,
401 int ver_table_size, struct vio_driver_ops *ops,
402 char *name);
403
404extern void vio_port_up(struct vio_driver_state *vio);
405
406#endif /* _SPARC64_VIO_H */
diff --git a/include/asm-sparc/visasm.h b/include/asm-sparc/visasm.h
deleted file mode 100644
index de797b9bf55..00000000000
--- a/include/asm-sparc/visasm.h
+++ /dev/null
@@ -1,62 +0,0 @@
1#ifndef _SPARC64_VISASM_H
2#define _SPARC64_VISASM_H
3
4/* visasm.h: FPU saving macros for VIS routines
5 *
6 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
7 */
8
9#include <asm/pstate.h>
10#include <asm/ptrace.h>
11
12/* Clobbers %o5, %g1, %g2, %g3, %g7, %icc, %xcc */
13
14#define VISEntry \
15 rd %fprs, %o5; \
16 andcc %o5, (FPRS_FEF|FPRS_DU), %g0; \
17 be,pt %icc, 297f; \
18 sethi %hi(297f), %g7; \
19 sethi %hi(VISenter), %g1; \
20 jmpl %g1 + %lo(VISenter), %g0; \
21 or %g7, %lo(297f), %g7; \
22297: wr %g0, FPRS_FEF, %fprs; \
23
24#define VISExit \
25 wr %g0, 0, %fprs;
26
27/* Clobbers %o5, %g1, %g2, %g3, %g7, %icc, %xcc.
28 * Must preserve %o5 between VISEntryHalf and VISExitHalf */
29
30#define VISEntryHalf \
31 rd %fprs, %o5; \
32 andcc %o5, FPRS_FEF, %g0; \
33 be,pt %icc, 297f; \
34 sethi %hi(298f), %g7; \
35 sethi %hi(VISenterhalf), %g1; \
36 jmpl %g1 + %lo(VISenterhalf), %g0; \
37 or %g7, %lo(298f), %g7; \
38 clr %o5; \
39297: wr %o5, FPRS_FEF, %fprs; \
40298:
41
42#define VISExitHalf \
43 wr %o5, 0, %fprs;
44
45#ifndef __ASSEMBLY__
46static inline void save_and_clear_fpu(void) {
47 __asm__ __volatile__ (
48" rd %%fprs, %%o5\n"
49" andcc %%o5, %0, %%g0\n"
50" be,pt %%icc, 299f\n"
51" sethi %%hi(298f), %%g7\n"
52" sethi %%hi(VISenter), %%g1\n"
53" jmpl %%g1 + %%lo(VISenter), %%g0\n"
54" or %%g7, %%lo(298f), %%g7\n"
55" 298: wr %%g0, 0, %%fprs\n"
56" 299:\n"
57" " : : "i" (FPRS_FEF|FPRS_DU) :
58 "o5", "g1", "g2", "g3", "g7", "cc");
59}
60#endif
61
62#endif /* _SPARC64_ASI_H */
diff --git a/include/asm-sparc/watchdog.h b/include/asm-sparc/watchdog.h
deleted file mode 100644
index 5baf2d3919c..00000000000
--- a/include/asm-sparc/watchdog.h
+++ /dev/null
@@ -1,31 +0,0 @@
1/*
2 *
3 * watchdog - Driver interface for the hardware watchdog timers
4 * present on Sun Microsystems boardsets
5 *
6 * Copyright (c) 2000 Eric Brower <ebrower@usa.net>
7 *
8 */
9
10#ifndef _SPARC64_WATCHDOG_H
11#define _SPARC64_WATCHDOG_H
12
13#include <linux/watchdog.h>
14
15/* Solaris compatibility ioctls--
16 * Ref. <linux/watchdog.h> for standard linux watchdog ioctls
17 */
18#define WIOCSTART _IO (WATCHDOG_IOCTL_BASE, 10) /* Start Timer */
19#define WIOCSTOP _IO (WATCHDOG_IOCTL_BASE, 11) /* Stop Timer */
20#define WIOCGSTAT _IOR(WATCHDOG_IOCTL_BASE, 12, int)/* Get Timer Status */
21
22/* Status flags from WIOCGSTAT ioctl
23 */
24#define WD_FREERUN 0x01 /* timer is running, interrupts disabled */
25#define WD_EXPIRED 0x02 /* timer has expired */
26#define WD_RUNNING 0x04 /* timer is running, interrupts enabled */
27#define WD_STOPPED 0x08 /* timer has not been started */
28#define WD_SERVICED 0x10 /* timer interrupt was serviced */
29
30#endif /* ifndef _SPARC64_WATCHDOG_H */
31
diff --git a/include/asm-sparc/winmacro.h b/include/asm-sparc/winmacro.h
deleted file mode 100644
index 5b0a06dc3bc..00000000000
--- a/include/asm-sparc/winmacro.h
+++ /dev/null
@@ -1,135 +0,0 @@
1/*
2 * winmacro.h: Window loading-unloading macros.
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 */
6
7#ifndef _SPARC_WINMACRO_H
8#define _SPARC_WINMACRO_H
9
10#include <asm/ptrace.h>
11
12/* Store the register window onto the 8-byte aligned area starting
13 * at %reg. It might be %sp, it might not, we don't care.
14 */
15#define STORE_WINDOW(reg) \
16 std %l0, [%reg + RW_L0]; \
17 std %l2, [%reg + RW_L2]; \
18 std %l4, [%reg + RW_L4]; \
19 std %l6, [%reg + RW_L6]; \
20 std %i0, [%reg + RW_I0]; \
21 std %i2, [%reg + RW_I2]; \
22 std %i4, [%reg + RW_I4]; \
23 std %i6, [%reg + RW_I6];
24
25/* Load a register window from the area beginning at %reg. */
26#define LOAD_WINDOW(reg) \
27 ldd [%reg + RW_L0], %l0; \
28 ldd [%reg + RW_L2], %l2; \
29 ldd [%reg + RW_L4], %l4; \
30 ldd [%reg + RW_L6], %l6; \
31 ldd [%reg + RW_I0], %i0; \
32 ldd [%reg + RW_I2], %i2; \
33 ldd [%reg + RW_I4], %i4; \
34 ldd [%reg + RW_I6], %i6;
35
36/* Loading and storing struct pt_reg trap frames. */
37#define LOAD_PT_INS(base_reg) \
38 ldd [%base_reg + STACKFRAME_SZ + PT_I0], %i0; \
39 ldd [%base_reg + STACKFRAME_SZ + PT_I2], %i2; \
40 ldd [%base_reg + STACKFRAME_SZ + PT_I4], %i4; \
41 ldd [%base_reg + STACKFRAME_SZ + PT_I6], %i6;
42
43#define LOAD_PT_GLOBALS(base_reg) \
44 ld [%base_reg + STACKFRAME_SZ + PT_G1], %g1; \
45 ldd [%base_reg + STACKFRAME_SZ + PT_G2], %g2; \
46 ldd [%base_reg + STACKFRAME_SZ + PT_G4], %g4; \
47 ldd [%base_reg + STACKFRAME_SZ + PT_G6], %g6;
48
49#define LOAD_PT_YREG(base_reg, scratch) \
50 ld [%base_reg + STACKFRAME_SZ + PT_Y], %scratch; \
51 wr %scratch, 0x0, %y;
52
53#define LOAD_PT_PRIV(base_reg, pt_psr, pt_pc, pt_npc) \
54 ld [%base_reg + STACKFRAME_SZ + PT_PSR], %pt_psr; \
55 ld [%base_reg + STACKFRAME_SZ + PT_PC], %pt_pc; \
56 ld [%base_reg + STACKFRAME_SZ + PT_NPC], %pt_npc;
57
58#define LOAD_PT_ALL(base_reg, pt_psr, pt_pc, pt_npc, scratch) \
59 LOAD_PT_YREG(base_reg, scratch) \
60 LOAD_PT_INS(base_reg) \
61 LOAD_PT_GLOBALS(base_reg) \
62 LOAD_PT_PRIV(base_reg, pt_psr, pt_pc, pt_npc)
63
64#define STORE_PT_INS(base_reg) \
65 std %i0, [%base_reg + STACKFRAME_SZ + PT_I0]; \
66 std %i2, [%base_reg + STACKFRAME_SZ + PT_I2]; \
67 std %i4, [%base_reg + STACKFRAME_SZ + PT_I4]; \
68 std %i6, [%base_reg + STACKFRAME_SZ + PT_I6];
69
70#define STORE_PT_GLOBALS(base_reg) \
71 st %g1, [%base_reg + STACKFRAME_SZ + PT_G1]; \
72 std %g2, [%base_reg + STACKFRAME_SZ + PT_G2]; \
73 std %g4, [%base_reg + STACKFRAME_SZ + PT_G4]; \
74 std %g6, [%base_reg + STACKFRAME_SZ + PT_G6];
75
76#define STORE_PT_YREG(base_reg, scratch) \
77 rd %y, %scratch; \
78 st %scratch, [%base_reg + STACKFRAME_SZ + PT_Y];
79
80#define STORE_PT_PRIV(base_reg, pt_psr, pt_pc, pt_npc) \
81 st %pt_psr, [%base_reg + STACKFRAME_SZ + PT_PSR]; \
82 st %pt_pc, [%base_reg + STACKFRAME_SZ + PT_PC]; \
83 st %pt_npc, [%base_reg + STACKFRAME_SZ + PT_NPC];
84
85#define STORE_PT_ALL(base_reg, reg_psr, reg_pc, reg_npc, g_scratch) \
86 STORE_PT_PRIV(base_reg, reg_psr, reg_pc, reg_npc) \
87 STORE_PT_GLOBALS(base_reg) \
88 STORE_PT_YREG(base_reg, g_scratch) \
89 STORE_PT_INS(base_reg)
90
91#define SAVE_BOLIXED_USER_STACK(cur_reg, scratch) \
92 ld [%cur_reg + TI_W_SAVED], %scratch; \
93 sll %scratch, 2, %scratch; \
94 add %scratch, %cur_reg, %scratch; \
95 st %sp, [%scratch + TI_RWIN_SPTRS]; \
96 sub %scratch, %cur_reg, %scratch; \
97 sll %scratch, 4, %scratch; \
98 add %scratch, %cur_reg, %scratch; \
99 STORE_WINDOW(scratch + TI_REG_WINDOW); \
100 sub %scratch, %cur_reg, %scratch; \
101 srl %scratch, 6, %scratch; \
102 add %scratch, 1, %scratch; \
103 st %scratch, [%cur_reg + TI_W_SAVED];
104
105#ifdef CONFIG_SMP
106#define LOAD_CURRENT4M(dest_reg, idreg) \
107 rd %tbr, %idreg; \
108 sethi %hi(current_set), %dest_reg; \
109 srl %idreg, 10, %idreg; \
110 or %dest_reg, %lo(current_set), %dest_reg; \
111 and %idreg, 0xc, %idreg; \
112 ld [%idreg + %dest_reg], %dest_reg;
113
114#define LOAD_CURRENT4D(dest_reg, idreg) \
115 lda [%g0] ASI_M_VIKING_TMP1, %idreg; \
116 sethi %hi(C_LABEL(current_set)), %dest_reg; \
117 sll %idreg, 2, %idreg; \
118 or %dest_reg, %lo(C_LABEL(current_set)), %dest_reg; \
119 ld [%idreg + %dest_reg], %dest_reg;
120
121/* Blackbox - take care with this... - check smp4m and smp4d before changing this. */
122#define LOAD_CURRENT(dest_reg, idreg) \
123 sethi %hi(___b_load_current), %idreg; \
124 sethi %hi(current_set), %dest_reg; \
125 sethi %hi(boot_cpu_id4), %idreg; \
126 or %dest_reg, %lo(current_set), %dest_reg; \
127 ldub [%idreg + %lo(boot_cpu_id4)], %idreg; \
128 ld [%idreg + %dest_reg], %dest_reg;
129#else
130#define LOAD_CURRENT(dest_reg, idreg) \
131 sethi %hi(current_set), %idreg; \
132 ld [%idreg + %lo(current_set)], %dest_reg;
133#endif
134
135#endif /* !(_SPARC_WINMACRO_H) */
diff --git a/include/asm-sparc/xor.h b/include/asm-sparc/xor.h
deleted file mode 100644
index 35089a838c3..00000000000
--- a/include/asm-sparc/xor.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef ___ASM_SPARC_XOR_H
2#define ___ASM_SPARC_XOR_H
3#if defined(__sparc__) && defined(__arch64__)
4#include <asm-sparc/xor_64.h>
5#else
6#include <asm-sparc/xor_32.h>
7#endif
8#endif
diff --git a/include/asm-sparc/xor_32.h b/include/asm-sparc/xor_32.h
deleted file mode 100644
index f34b2cfa820..00000000000
--- a/include/asm-sparc/xor_32.h
+++ /dev/null
@@ -1,269 +0,0 @@
1/*
2 * include/asm-sparc/xor.h
3 *
4 * Optimized RAID-5 checksumming functions for 32-bit Sparc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2, or (at your option)
9 * any later version.
10 *
11 * You should have received a copy of the GNU General Public License
12 * (for example /usr/src/linux/COPYING); if not, write to the Free
13 * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
14 */
15
16/*
17 * High speed xor_block operation for RAID4/5 utilizing the
18 * ldd/std SPARC instructions.
19 *
20 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
21 */
22
23static void
24sparc_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
25{
26 int lines = bytes / (sizeof (long)) / 8;
27
28 do {
29 __asm__ __volatile__(
30 "ldd [%0 + 0x00], %%g2\n\t"
31 "ldd [%0 + 0x08], %%g4\n\t"
32 "ldd [%0 + 0x10], %%o0\n\t"
33 "ldd [%0 + 0x18], %%o2\n\t"
34 "ldd [%1 + 0x00], %%o4\n\t"
35 "ldd [%1 + 0x08], %%l0\n\t"
36 "ldd [%1 + 0x10], %%l2\n\t"
37 "ldd [%1 + 0x18], %%l4\n\t"
38 "xor %%g2, %%o4, %%g2\n\t"
39 "xor %%g3, %%o5, %%g3\n\t"
40 "xor %%g4, %%l0, %%g4\n\t"
41 "xor %%g5, %%l1, %%g5\n\t"
42 "xor %%o0, %%l2, %%o0\n\t"
43 "xor %%o1, %%l3, %%o1\n\t"
44 "xor %%o2, %%l4, %%o2\n\t"
45 "xor %%o3, %%l5, %%o3\n\t"
46 "std %%g2, [%0 + 0x00]\n\t"
47 "std %%g4, [%0 + 0x08]\n\t"
48 "std %%o0, [%0 + 0x10]\n\t"
49 "std %%o2, [%0 + 0x18]\n"
50 :
51 : "r" (p1), "r" (p2)
52 : "g2", "g3", "g4", "g5",
53 "o0", "o1", "o2", "o3", "o4", "o5",
54 "l0", "l1", "l2", "l3", "l4", "l5");
55 p1 += 8;
56 p2 += 8;
57 } while (--lines > 0);
58}
59
60static void
61sparc_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
62 unsigned long *p3)
63{
64 int lines = bytes / (sizeof (long)) / 8;
65
66 do {
67 __asm__ __volatile__(
68 "ldd [%0 + 0x00], %%g2\n\t"
69 "ldd [%0 + 0x08], %%g4\n\t"
70 "ldd [%0 + 0x10], %%o0\n\t"
71 "ldd [%0 + 0x18], %%o2\n\t"
72 "ldd [%1 + 0x00], %%o4\n\t"
73 "ldd [%1 + 0x08], %%l0\n\t"
74 "ldd [%1 + 0x10], %%l2\n\t"
75 "ldd [%1 + 0x18], %%l4\n\t"
76 "xor %%g2, %%o4, %%g2\n\t"
77 "xor %%g3, %%o5, %%g3\n\t"
78 "ldd [%2 + 0x00], %%o4\n\t"
79 "xor %%g4, %%l0, %%g4\n\t"
80 "xor %%g5, %%l1, %%g5\n\t"
81 "ldd [%2 + 0x08], %%l0\n\t"
82 "xor %%o0, %%l2, %%o0\n\t"
83 "xor %%o1, %%l3, %%o1\n\t"
84 "ldd [%2 + 0x10], %%l2\n\t"
85 "xor %%o2, %%l4, %%o2\n\t"
86 "xor %%o3, %%l5, %%o3\n\t"
87 "ldd [%2 + 0x18], %%l4\n\t"
88 "xor %%g2, %%o4, %%g2\n\t"
89 "xor %%g3, %%o5, %%g3\n\t"
90 "xor %%g4, %%l0, %%g4\n\t"
91 "xor %%g5, %%l1, %%g5\n\t"
92 "xor %%o0, %%l2, %%o0\n\t"
93 "xor %%o1, %%l3, %%o1\n\t"
94 "xor %%o2, %%l4, %%o2\n\t"
95 "xor %%o3, %%l5, %%o3\n\t"
96 "std %%g2, [%0 + 0x00]\n\t"
97 "std %%g4, [%0 + 0x08]\n\t"
98 "std %%o0, [%0 + 0x10]\n\t"
99 "std %%o2, [%0 + 0x18]\n"
100 :
101 : "r" (p1), "r" (p2), "r" (p3)
102 : "g2", "g3", "g4", "g5",
103 "o0", "o1", "o2", "o3", "o4", "o5",
104 "l0", "l1", "l2", "l3", "l4", "l5");
105 p1 += 8;
106 p2 += 8;
107 p3 += 8;
108 } while (--lines > 0);
109}
110
111static void
112sparc_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
113 unsigned long *p3, unsigned long *p4)
114{
115 int lines = bytes / (sizeof (long)) / 8;
116
117 do {
118 __asm__ __volatile__(
119 "ldd [%0 + 0x00], %%g2\n\t"
120 "ldd [%0 + 0x08], %%g4\n\t"
121 "ldd [%0 + 0x10], %%o0\n\t"
122 "ldd [%0 + 0x18], %%o2\n\t"
123 "ldd [%1 + 0x00], %%o4\n\t"
124 "ldd [%1 + 0x08], %%l0\n\t"
125 "ldd [%1 + 0x10], %%l2\n\t"
126 "ldd [%1 + 0x18], %%l4\n\t"
127 "xor %%g2, %%o4, %%g2\n\t"
128 "xor %%g3, %%o5, %%g3\n\t"
129 "ldd [%2 + 0x00], %%o4\n\t"
130 "xor %%g4, %%l0, %%g4\n\t"
131 "xor %%g5, %%l1, %%g5\n\t"
132 "ldd [%2 + 0x08], %%l0\n\t"
133 "xor %%o0, %%l2, %%o0\n\t"
134 "xor %%o1, %%l3, %%o1\n\t"
135 "ldd [%2 + 0x10], %%l2\n\t"
136 "xor %%o2, %%l4, %%o2\n\t"
137 "xor %%o3, %%l5, %%o3\n\t"
138 "ldd [%2 + 0x18], %%l4\n\t"
139 "xor %%g2, %%o4, %%g2\n\t"
140 "xor %%g3, %%o5, %%g3\n\t"
141 "ldd [%3 + 0x00], %%o4\n\t"
142 "xor %%g4, %%l0, %%g4\n\t"
143 "xor %%g5, %%l1, %%g5\n\t"
144 "ldd [%3 + 0x08], %%l0\n\t"
145 "xor %%o0, %%l2, %%o0\n\t"
146 "xor %%o1, %%l3, %%o1\n\t"
147 "ldd [%3 + 0x10], %%l2\n\t"
148 "xor %%o2, %%l4, %%o2\n\t"
149 "xor %%o3, %%l5, %%o3\n\t"
150 "ldd [%3 + 0x18], %%l4\n\t"
151 "xor %%g2, %%o4, %%g2\n\t"
152 "xor %%g3, %%o5, %%g3\n\t"
153 "xor %%g4, %%l0, %%g4\n\t"
154 "xor %%g5, %%l1, %%g5\n\t"
155 "xor %%o0, %%l2, %%o0\n\t"
156 "xor %%o1, %%l3, %%o1\n\t"
157 "xor %%o2, %%l4, %%o2\n\t"
158 "xor %%o3, %%l5, %%o3\n\t"
159 "std %%g2, [%0 + 0x00]\n\t"
160 "std %%g4, [%0 + 0x08]\n\t"
161 "std %%o0, [%0 + 0x10]\n\t"
162 "std %%o2, [%0 + 0x18]\n"
163 :
164 : "r" (p1), "r" (p2), "r" (p3), "r" (p4)
165 : "g2", "g3", "g4", "g5",
166 "o0", "o1", "o2", "o3", "o4", "o5",
167 "l0", "l1", "l2", "l3", "l4", "l5");
168 p1 += 8;
169 p2 += 8;
170 p3 += 8;
171 p4 += 8;
172 } while (--lines > 0);
173}
174
175static void
176sparc_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
177 unsigned long *p3, unsigned long *p4, unsigned long *p5)
178{
179 int lines = bytes / (sizeof (long)) / 8;
180
181 do {
182 __asm__ __volatile__(
183 "ldd [%0 + 0x00], %%g2\n\t"
184 "ldd [%0 + 0x08], %%g4\n\t"
185 "ldd [%0 + 0x10], %%o0\n\t"
186 "ldd [%0 + 0x18], %%o2\n\t"
187 "ldd [%1 + 0x00], %%o4\n\t"
188 "ldd [%1 + 0x08], %%l0\n\t"
189 "ldd [%1 + 0x10], %%l2\n\t"
190 "ldd [%1 + 0x18], %%l4\n\t"
191 "xor %%g2, %%o4, %%g2\n\t"
192 "xor %%g3, %%o5, %%g3\n\t"
193 "ldd [%2 + 0x00], %%o4\n\t"
194 "xor %%g4, %%l0, %%g4\n\t"
195 "xor %%g5, %%l1, %%g5\n\t"
196 "ldd [%2 + 0x08], %%l0\n\t"
197 "xor %%o0, %%l2, %%o0\n\t"
198 "xor %%o1, %%l3, %%o1\n\t"
199 "ldd [%2 + 0x10], %%l2\n\t"
200 "xor %%o2, %%l4, %%o2\n\t"
201 "xor %%o3, %%l5, %%o3\n\t"
202 "ldd [%2 + 0x18], %%l4\n\t"
203 "xor %%g2, %%o4, %%g2\n\t"
204 "xor %%g3, %%o5, %%g3\n\t"
205 "ldd [%3 + 0x00], %%o4\n\t"
206 "xor %%g4, %%l0, %%g4\n\t"
207 "xor %%g5, %%l1, %%g5\n\t"
208 "ldd [%3 + 0x08], %%l0\n\t"
209 "xor %%o0, %%l2, %%o0\n\t"
210 "xor %%o1, %%l3, %%o1\n\t"
211 "ldd [%3 + 0x10], %%l2\n\t"
212 "xor %%o2, %%l4, %%o2\n\t"
213 "xor %%o3, %%l5, %%o3\n\t"
214 "ldd [%3 + 0x18], %%l4\n\t"
215 "xor %%g2, %%o4, %%g2\n\t"
216 "xor %%g3, %%o5, %%g3\n\t"
217 "ldd [%4 + 0x00], %%o4\n\t"
218 "xor %%g4, %%l0, %%g4\n\t"
219 "xor %%g5, %%l1, %%g5\n\t"
220 "ldd [%4 + 0x08], %%l0\n\t"
221 "xor %%o0, %%l2, %%o0\n\t"
222 "xor %%o1, %%l3, %%o1\n\t"
223 "ldd [%4 + 0x10], %%l2\n\t"
224 "xor %%o2, %%l4, %%o2\n\t"
225 "xor %%o3, %%l5, %%o3\n\t"
226 "ldd [%4 + 0x18], %%l4\n\t"
227 "xor %%g2, %%o4, %%g2\n\t"
228 "xor %%g3, %%o5, %%g3\n\t"
229 "xor %%g4, %%l0, %%g4\n\t"
230 "xor %%g5, %%l1, %%g5\n\t"
231 "xor %%o0, %%l2, %%o0\n\t"
232 "xor %%o1, %%l3, %%o1\n\t"
233 "xor %%o2, %%l4, %%o2\n\t"
234 "xor %%o3, %%l5, %%o3\n\t"
235 "std %%g2, [%0 + 0x00]\n\t"
236 "std %%g4, [%0 + 0x08]\n\t"
237 "std %%o0, [%0 + 0x10]\n\t"
238 "std %%o2, [%0 + 0x18]\n"
239 :
240 : "r" (p1), "r" (p2), "r" (p3), "r" (p4), "r" (p5)
241 : "g2", "g3", "g4", "g5",
242 "o0", "o1", "o2", "o3", "o4", "o5",
243 "l0", "l1", "l2", "l3", "l4", "l5");
244 p1 += 8;
245 p2 += 8;
246 p3 += 8;
247 p4 += 8;
248 p5 += 8;
249 } while (--lines > 0);
250}
251
252static struct xor_block_template xor_block_SPARC = {
253 .name = "SPARC",
254 .do_2 = sparc_2,
255 .do_3 = sparc_3,
256 .do_4 = sparc_4,
257 .do_5 = sparc_5,
258};
259
260/* For grins, also test the generic routines. */
261#include <asm-generic/xor.h>
262
263#undef XOR_TRY_TEMPLATES
264#define XOR_TRY_TEMPLATES \
265 do { \
266 xor_speed(&xor_block_8regs); \
267 xor_speed(&xor_block_32regs); \
268 xor_speed(&xor_block_SPARC); \
269 } while (0)
diff --git a/include/asm-sparc/xor_64.h b/include/asm-sparc/xor_64.h
deleted file mode 100644
index a0233884fc9..00000000000
--- a/include/asm-sparc/xor_64.h
+++ /dev/null
@@ -1,70 +0,0 @@
1/*
2 * include/asm-sparc64/xor.h
3 *
4 * High speed xor_block operation for RAID4/5 utilizing the
5 * UltraSparc Visual Instruction Set and Niagara block-init
6 * twin-load instructions.
7 *
8 * Copyright (C) 1997, 1999 Jakub Jelinek (jj@ultra.linux.cz)
9 * Copyright (C) 2006 David S. Miller <davem@davemloft.net>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * You should have received a copy of the GNU General Public License
17 * (for example /usr/src/linux/COPYING); if not, write to the Free
18 * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21#include <asm/spitfire.h>
22
23extern void xor_vis_2(unsigned long, unsigned long *, unsigned long *);
24extern void xor_vis_3(unsigned long, unsigned long *, unsigned long *,
25 unsigned long *);
26extern void xor_vis_4(unsigned long, unsigned long *, unsigned long *,
27 unsigned long *, unsigned long *);
28extern void xor_vis_5(unsigned long, unsigned long *, unsigned long *,
29 unsigned long *, unsigned long *, unsigned long *);
30
31/* XXX Ugh, write cheetah versions... -DaveM */
32
33static struct xor_block_template xor_block_VIS = {
34 .name = "VIS",
35 .do_2 = xor_vis_2,
36 .do_3 = xor_vis_3,
37 .do_4 = xor_vis_4,
38 .do_5 = xor_vis_5,
39};
40
41extern void xor_niagara_2(unsigned long, unsigned long *, unsigned long *);
42extern void xor_niagara_3(unsigned long, unsigned long *, unsigned long *,
43 unsigned long *);
44extern void xor_niagara_4(unsigned long, unsigned long *, unsigned long *,
45 unsigned long *, unsigned long *);
46extern void xor_niagara_5(unsigned long, unsigned long *, unsigned long *,
47 unsigned long *, unsigned long *, unsigned long *);
48
49static struct xor_block_template xor_block_niagara = {
50 .name = "Niagara",
51 .do_2 = xor_niagara_2,
52 .do_3 = xor_niagara_3,
53 .do_4 = xor_niagara_4,
54 .do_5 = xor_niagara_5,
55};
56
57#undef XOR_TRY_TEMPLATES
58#define XOR_TRY_TEMPLATES \
59 do { \
60 xor_speed(&xor_block_VIS); \
61 xor_speed(&xor_block_niagara); \
62 } while (0)
63
64/* For VIS for everything except Niagara. */
65#define XOR_SELECT_TEMPLATE(FASTEST) \
66 ((tlb_type == hypervisor && \
67 (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 || \
68 sun4v_chip_type == SUN4V_CHIP_NIAGARA2)) ? \
69 &xor_block_niagara : \
70 &xor_block_VIS)
diff --git a/include/asm-sparc64/Kbuild b/include/asm-sparc64/Kbuild
deleted file mode 100644
index 6cdaf9d33b3..00000000000
--- a/include/asm-sparc64/Kbuild
+++ /dev/null
@@ -1 +0,0 @@
1# dummy file to avoid breaking make headers_install
diff --git a/include/asm-sparc64/agp.h b/include/asm-sparc64/agp.h
deleted file mode 100644
index eb8d4b3f516..00000000000
--- a/include/asm-sparc64/agp.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/agp.h>
diff --git a/include/asm-sparc64/apb.h b/include/asm-sparc64/apb.h
deleted file mode 100644
index 5e236ca6e49..00000000000
--- a/include/asm-sparc64/apb.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/apb.h>
diff --git a/include/asm-sparc64/asi.h b/include/asm-sparc64/asi.h
deleted file mode 100644
index 9b7110c516e..00000000000
--- a/include/asm-sparc64/asi.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/asi.h>
diff --git a/include/asm-sparc64/atomic.h b/include/asm-sparc64/atomic.h
deleted file mode 100644
index f5126826ba3..00000000000
--- a/include/asm-sparc64/atomic.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/atomic.h>
diff --git a/include/asm-sparc64/auxio.h b/include/asm-sparc64/auxio.h
deleted file mode 100644
index 46c9042f30b..00000000000
--- a/include/asm-sparc64/auxio.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/auxio.h>
diff --git a/include/asm-sparc64/auxvec.h b/include/asm-sparc64/auxvec.h
deleted file mode 100644
index 1f45c67d731..00000000000
--- a/include/asm-sparc64/auxvec.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/auxvec.h>
diff --git a/include/asm-sparc64/backoff.h b/include/asm-sparc64/backoff.h
deleted file mode 100644
index 8ee26d947e0..00000000000
--- a/include/asm-sparc64/backoff.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/backoff.h>
diff --git a/include/asm-sparc64/bbc.h b/include/asm-sparc64/bbc.h
deleted file mode 100644
index 06e8b630651..00000000000
--- a/include/asm-sparc64/bbc.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/bbc.h>
diff --git a/include/asm-sparc64/bitops.h b/include/asm-sparc64/bitops.h
deleted file mode 100644
index 204404355bd..00000000000
--- a/include/asm-sparc64/bitops.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/bitops.h>
diff --git a/include/asm-sparc64/bpp.h b/include/asm-sparc64/bpp.h
deleted file mode 100644
index 514eee20272..00000000000
--- a/include/asm-sparc64/bpp.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/bpp.h>
diff --git a/include/asm-sparc64/bug.h b/include/asm-sparc64/bug.h
deleted file mode 100644
index 3433737c7a6..00000000000
--- a/include/asm-sparc64/bug.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/bug.h>
diff --git a/include/asm-sparc64/bugs.h b/include/asm-sparc64/bugs.h
deleted file mode 100644
index 04ae9e2818c..00000000000
--- a/include/asm-sparc64/bugs.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/bugs.h>
diff --git a/include/asm-sparc64/byteorder.h b/include/asm-sparc64/byteorder.h
deleted file mode 100644
index f672855bee1..00000000000
--- a/include/asm-sparc64/byteorder.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/byteorder.h>
diff --git a/include/asm-sparc64/cache.h b/include/asm-sparc64/cache.h
deleted file mode 100644
index fa9de5cadbf..00000000000
--- a/include/asm-sparc64/cache.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/cache.h>
diff --git a/include/asm-sparc64/cacheflush.h b/include/asm-sparc64/cacheflush.h
deleted file mode 100644
index cf5b6b3e8a5..00000000000
--- a/include/asm-sparc64/cacheflush.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/cacheflush.h>
diff --git a/include/asm-sparc64/chafsr.h b/include/asm-sparc64/chafsr.h
deleted file mode 100644
index aaab97562a3..00000000000
--- a/include/asm-sparc64/chafsr.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/chafsr.h>
diff --git a/include/asm-sparc64/checksum.h b/include/asm-sparc64/checksum.h
deleted file mode 100644
index c3966c5e29d..00000000000
--- a/include/asm-sparc64/checksum.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/checksum.h>
diff --git a/include/asm-sparc64/chmctrl.h b/include/asm-sparc64/chmctrl.h
deleted file mode 100644
index eb757b483b3..00000000000
--- a/include/asm-sparc64/chmctrl.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/chmctrl.h>
diff --git a/include/asm-sparc64/cmt.h b/include/asm-sparc64/cmt.h
deleted file mode 100644
index b19b445cb81..00000000000
--- a/include/asm-sparc64/cmt.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/cmt.h>
diff --git a/include/asm-sparc64/compat.h b/include/asm-sparc64/compat.h
deleted file mode 100644
index 8c155d22195..00000000000
--- a/include/asm-sparc64/compat.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/compat.h>
diff --git a/include/asm-sparc64/compat_signal.h b/include/asm-sparc64/compat_signal.h
deleted file mode 100644
index 7187dcc8cac..00000000000
--- a/include/asm-sparc64/compat_signal.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/compat_signal.h>
diff --git a/include/asm-sparc64/cpudata.h b/include/asm-sparc64/cpudata.h
deleted file mode 100644
index 3220e134a57..00000000000
--- a/include/asm-sparc64/cpudata.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/cpudata.h>
diff --git a/include/asm-sparc64/cputime.h b/include/asm-sparc64/cputime.h
deleted file mode 100644
index 435f37a92f7..00000000000
--- a/include/asm-sparc64/cputime.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/cputime.h>
diff --git a/include/asm-sparc64/current.h b/include/asm-sparc64/current.h
deleted file mode 100644
index a7904a7f53a..00000000000
--- a/include/asm-sparc64/current.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/current.h>
diff --git a/include/asm-sparc64/dcr.h b/include/asm-sparc64/dcr.h
deleted file mode 100644
index d67613b1f5f..00000000000
--- a/include/asm-sparc64/dcr.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/dcr.h>
diff --git a/include/asm-sparc64/dcu.h b/include/asm-sparc64/dcu.h
deleted file mode 100644
index 28853f4968d..00000000000
--- a/include/asm-sparc64/dcu.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/dcu.h>
diff --git a/include/asm-sparc64/delay.h b/include/asm-sparc64/delay.h
deleted file mode 100644
index 33dc5589d84..00000000000
--- a/include/asm-sparc64/delay.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/delay.h>
diff --git a/include/asm-sparc64/device.h b/include/asm-sparc64/device.h
deleted file mode 100644
index 4145c47097e..00000000000
--- a/include/asm-sparc64/device.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/device.h>
diff --git a/include/asm-sparc64/display7seg.h b/include/asm-sparc64/display7seg.h
deleted file mode 100644
index e74f046b41d..00000000000
--- a/include/asm-sparc64/display7seg.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/display7seg.h>
diff --git a/include/asm-sparc64/div64.h b/include/asm-sparc64/div64.h
deleted file mode 100644
index 928c94f99ec..00000000000
--- a/include/asm-sparc64/div64.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/div64.h>
diff --git a/include/asm-sparc64/dma-mapping.h b/include/asm-sparc64/dma-mapping.h
deleted file mode 100644
index 380b7b63147..00000000000
--- a/include/asm-sparc64/dma-mapping.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/dma-mapping.h>
diff --git a/include/asm-sparc64/dma.h b/include/asm-sparc64/dma.h
deleted file mode 100644
index 2e36248e6b5..00000000000
--- a/include/asm-sparc64/dma.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/dma.h>
diff --git a/include/asm-sparc64/ebus.h b/include/asm-sparc64/ebus.h
deleted file mode 100644
index d7d476158bd..00000000000
--- a/include/asm-sparc64/ebus.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/ebus.h>
diff --git a/include/asm-sparc64/elf.h b/include/asm-sparc64/elf.h
deleted file mode 100644
index f256d9472c8..00000000000
--- a/include/asm-sparc64/elf.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/elf.h>
diff --git a/include/asm-sparc64/emergency-restart.h b/include/asm-sparc64/emergency-restart.h
deleted file mode 100644
index 2cac7b644da..00000000000
--- a/include/asm-sparc64/emergency-restart.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/emergency-restart.h>
diff --git a/include/asm-sparc64/envctrl.h b/include/asm-sparc64/envctrl.h
deleted file mode 100644
index a2cc0ca334b..00000000000
--- a/include/asm-sparc64/envctrl.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/envctrl.h>
diff --git a/include/asm-sparc64/errno.h b/include/asm-sparc64/errno.h
deleted file mode 100644
index 9701fe01cc5..00000000000
--- a/include/asm-sparc64/errno.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/errno.h>
diff --git a/include/asm-sparc64/estate.h b/include/asm-sparc64/estate.h
deleted file mode 100644
index bedd0ef5f19..00000000000
--- a/include/asm-sparc64/estate.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/estate.h>
diff --git a/include/asm-sparc64/fb.h b/include/asm-sparc64/fb.h
deleted file mode 100644
index 1c2ac5832f3..00000000000
--- a/include/asm-sparc64/fb.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/fb.h>
diff --git a/include/asm-sparc64/fbio.h b/include/asm-sparc64/fbio.h
deleted file mode 100644
index c17edf8c7bc..00000000000
--- a/include/asm-sparc64/fbio.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/fbio.h>
diff --git a/include/asm-sparc64/fcntl.h b/include/asm-sparc64/fcntl.h
deleted file mode 100644
index 8b1beae48cd..00000000000
--- a/include/asm-sparc64/fcntl.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/fcntl.h>
diff --git a/include/asm-sparc64/fhc.h b/include/asm-sparc64/fhc.h
deleted file mode 100644
index 73eb04c19c4..00000000000
--- a/include/asm-sparc64/fhc.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/fhc.h>
diff --git a/include/asm-sparc64/floppy.h b/include/asm-sparc64/floppy.h
deleted file mode 100644
index 21487811443..00000000000
--- a/include/asm-sparc64/floppy.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/floppy.h>
diff --git a/include/asm-sparc64/fpumacro.h b/include/asm-sparc64/fpumacro.h
deleted file mode 100644
index 30d6d0f68bc..00000000000
--- a/include/asm-sparc64/fpumacro.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/fpumacro.h>
diff --git a/include/asm-sparc64/ftrace.h b/include/asm-sparc64/ftrace.h
deleted file mode 100644
index d27716cd38c..00000000000
--- a/include/asm-sparc64/ftrace.h
+++ /dev/null
@@ -1,14 +0,0 @@
1#ifndef _ASM_SPARC64_FTRACE
2#define _ASM_SPARC64_FTRACE
3
4#ifdef CONFIG_MCOUNT
5#define MCOUNT_ADDR ((long)(_mcount))
6#define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */
7
8#ifndef __ASSEMBLY__
9extern void _mcount(void);
10#endif
11
12#endif
13
14#endif /* _ASM_SPARC64_FTRACE */
diff --git a/include/asm-sparc64/futex.h b/include/asm-sparc64/futex.h
deleted file mode 100644
index 1ceb0bb2fe5..00000000000
--- a/include/asm-sparc64/futex.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/futex.h>
diff --git a/include/asm-sparc64/hardirq.h b/include/asm-sparc64/hardirq.h
deleted file mode 100644
index 63dca3db11f..00000000000
--- a/include/asm-sparc64/hardirq.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/hardirq.h>
diff --git a/include/asm-sparc64/head.h b/include/asm-sparc64/head.h
deleted file mode 100644
index 2254c09e53f..00000000000
--- a/include/asm-sparc64/head.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/head.h>
diff --git a/include/asm-sparc64/hugetlb.h b/include/asm-sparc64/hugetlb.h
deleted file mode 100644
index 21d8f0a9c24..00000000000
--- a/include/asm-sparc64/hugetlb.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/hugetlb.h>
diff --git a/include/asm-sparc64/hvtramp.h b/include/asm-sparc64/hvtramp.h
deleted file mode 100644
index fb46bfe934a..00000000000
--- a/include/asm-sparc64/hvtramp.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/hvtramp.h>
diff --git a/include/asm-sparc64/hw_irq.h b/include/asm-sparc64/hw_irq.h
deleted file mode 100644
index 16920a291f5..00000000000
--- a/include/asm-sparc64/hw_irq.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/hw_irq.h>
diff --git a/include/asm-sparc64/hypervisor.h b/include/asm-sparc64/hypervisor.h
deleted file mode 100644
index fe7e51a9e42..00000000000
--- a/include/asm-sparc64/hypervisor.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/hypervisor.h>
diff --git a/include/asm-sparc64/ide.h b/include/asm-sparc64/ide.h
deleted file mode 100644
index 7125317a428..00000000000
--- a/include/asm-sparc64/ide.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/ide.h>
diff --git a/include/asm-sparc64/idprom.h b/include/asm-sparc64/idprom.h
deleted file mode 100644
index c22f9c30bc7..00000000000
--- a/include/asm-sparc64/idprom.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/idprom.h>
diff --git a/include/asm-sparc64/intr_queue.h b/include/asm-sparc64/intr_queue.h
deleted file mode 100644
index f7225015b3d..00000000000
--- a/include/asm-sparc64/intr_queue.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/intr_queue.h>
diff --git a/include/asm-sparc64/io.h b/include/asm-sparc64/io.h
deleted file mode 100644
index 25ff258dfd3..00000000000
--- a/include/asm-sparc64/io.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/io.h>
diff --git a/include/asm-sparc64/ioctl.h b/include/asm-sparc64/ioctl.h
deleted file mode 100644
index 18fc5623ff5..00000000000
--- a/include/asm-sparc64/ioctl.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/ioctl.h>
diff --git a/include/asm-sparc64/ioctls.h b/include/asm-sparc64/ioctls.h
deleted file mode 100644
index dcd5540ec10..00000000000
--- a/include/asm-sparc64/ioctls.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/ioctls.h>
diff --git a/include/asm-sparc64/iommu.h b/include/asm-sparc64/iommu.h
deleted file mode 100644
index 76252bb85e9..00000000000
--- a/include/asm-sparc64/iommu.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/iommu.h>
diff --git a/include/asm-sparc64/ipcbuf.h b/include/asm-sparc64/ipcbuf.h
deleted file mode 100644
index 41dfaf1149b..00000000000
--- a/include/asm-sparc64/ipcbuf.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/ipcbuf.h>
diff --git a/include/asm-sparc64/irq.h b/include/asm-sparc64/irq.h
deleted file mode 100644
index b2102e65947..00000000000
--- a/include/asm-sparc64/irq.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/irq.h>
diff --git a/include/asm-sparc64/irq_regs.h b/include/asm-sparc64/irq_regs.h
deleted file mode 100644
index 1e2b8a1e745..00000000000
--- a/include/asm-sparc64/irq_regs.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/irq_regs.h>
diff --git a/include/asm-sparc64/irqflags.h b/include/asm-sparc64/irqflags.h
deleted file mode 100644
index 27b091fc3fa..00000000000
--- a/include/asm-sparc64/irqflags.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/irqflags.h>
diff --git a/include/asm-sparc64/kdebug.h b/include/asm-sparc64/kdebug.h
deleted file mode 100644
index 78cfd5d2749..00000000000
--- a/include/asm-sparc64/kdebug.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/kdebug.h>
diff --git a/include/asm-sparc64/kgdb.h b/include/asm-sparc64/kgdb.h
deleted file mode 100644
index aa6532fd3a1..00000000000
--- a/include/asm-sparc64/kgdb.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/kgdb.h>
diff --git a/include/asm-sparc64/kmap_types.h b/include/asm-sparc64/kmap_types.h
deleted file mode 100644
index 276530cf539..00000000000
--- a/include/asm-sparc64/kmap_types.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/kmap_types.h>
diff --git a/include/asm-sparc64/kprobes.h b/include/asm-sparc64/kprobes.h
deleted file mode 100644
index c55e43e4d2a..00000000000
--- a/include/asm-sparc64/kprobes.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/kprobes.h>
diff --git a/include/asm-sparc64/ldc.h b/include/asm-sparc64/ldc.h
deleted file mode 100644
index 40f3f231c45..00000000000
--- a/include/asm-sparc64/ldc.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/ldc.h>
diff --git a/include/asm-sparc64/linkage.h b/include/asm-sparc64/linkage.h
deleted file mode 100644
index 3ea4fd13f19..00000000000
--- a/include/asm-sparc64/linkage.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/linkage.h>
diff --git a/include/asm-sparc64/lmb.h b/include/asm-sparc64/lmb.h
deleted file mode 100644
index 3d04981701e..00000000000
--- a/include/asm-sparc64/lmb.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/lmb.h>
diff --git a/include/asm-sparc64/local.h b/include/asm-sparc64/local.h
deleted file mode 100644
index c11c530f74d..00000000000
--- a/include/asm-sparc64/local.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/local.h>
diff --git a/include/asm-sparc64/lsu.h b/include/asm-sparc64/lsu.h
deleted file mode 100644
index 4e3d8b128a5..00000000000
--- a/include/asm-sparc64/lsu.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/lsu.h>
diff --git a/include/asm-sparc64/mc146818rtc.h b/include/asm-sparc64/mc146818rtc.h
deleted file mode 100644
index 97842e6ed1c..00000000000
--- a/include/asm-sparc64/mc146818rtc.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/mc146818rtc.h>
diff --git a/include/asm-sparc64/mdesc.h b/include/asm-sparc64/mdesc.h
deleted file mode 100644
index 165a1934728..00000000000
--- a/include/asm-sparc64/mdesc.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/mdesc.h>
diff --git a/include/asm-sparc64/mman.h b/include/asm-sparc64/mman.h
deleted file mode 100644
index 17ddb1724f5..00000000000
--- a/include/asm-sparc64/mman.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/mman.h>
diff --git a/include/asm-sparc64/mmu.h b/include/asm-sparc64/mmu.h
deleted file mode 100644
index e677a64d8db..00000000000
--- a/include/asm-sparc64/mmu.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/mmu.h>
diff --git a/include/asm-sparc64/mmu_context.h b/include/asm-sparc64/mmu_context.h
deleted file mode 100644
index 877fee94bd4..00000000000
--- a/include/asm-sparc64/mmu_context.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/mmu_context.h>
diff --git a/include/asm-sparc64/mmzone.h b/include/asm-sparc64/mmzone.h
deleted file mode 100644
index 43a710f7892..00000000000
--- a/include/asm-sparc64/mmzone.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/mmzone.h>
diff --git a/include/asm-sparc64/module.h b/include/asm-sparc64/module.h
deleted file mode 100644
index a9606db55e4..00000000000
--- a/include/asm-sparc64/module.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/module.h>
diff --git a/include/asm-sparc64/mostek.h b/include/asm-sparc64/mostek.h
deleted file mode 100644
index 95a752f7e87..00000000000
--- a/include/asm-sparc64/mostek.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/mostek.h>
diff --git a/include/asm-sparc64/msgbuf.h b/include/asm-sparc64/msgbuf.h
deleted file mode 100644
index 5b33cc9d9bf..00000000000
--- a/include/asm-sparc64/msgbuf.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/msgbuf.h>
diff --git a/include/asm-sparc64/mutex.h b/include/asm-sparc64/mutex.h
deleted file mode 100644
index c0c0f8f260d..00000000000
--- a/include/asm-sparc64/mutex.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/mutex.h>
diff --git a/include/asm-sparc64/ns87303.h b/include/asm-sparc64/ns87303.h
deleted file mode 100644
index 5f369d4df3d..00000000000
--- a/include/asm-sparc64/ns87303.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/ns87303.h>
diff --git a/include/asm-sparc64/of_device.h b/include/asm-sparc64/of_device.h
deleted file mode 100644
index a769fdbe164..00000000000
--- a/include/asm-sparc64/of_device.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/of_device.h>
diff --git a/include/asm-sparc64/of_platform.h b/include/asm-sparc64/of_platform.h
deleted file mode 100644
index f7c427b8bc6..00000000000
--- a/include/asm-sparc64/of_platform.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/of_platform.h>
diff --git a/include/asm-sparc64/openprom.h b/include/asm-sparc64/openprom.h
deleted file mode 100644
index acf4b234fae..00000000000
--- a/include/asm-sparc64/openprom.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/openprom.h>
diff --git a/include/asm-sparc64/openpromio.h b/include/asm-sparc64/openpromio.h
deleted file mode 100644
index 122fabda21f..00000000000
--- a/include/asm-sparc64/openpromio.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/openpromio.h>
diff --git a/include/asm-sparc64/oplib.h b/include/asm-sparc64/oplib.h
deleted file mode 100644
index d93e44e6351..00000000000
--- a/include/asm-sparc64/oplib.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/oplib.h>
diff --git a/include/asm-sparc64/page.h b/include/asm-sparc64/page.h
deleted file mode 100644
index f46c1fb5302..00000000000
--- a/include/asm-sparc64/page.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/page.h>
diff --git a/include/asm-sparc64/param.h b/include/asm-sparc64/param.h
deleted file mode 100644
index 40c6dc11082..00000000000
--- a/include/asm-sparc64/param.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/param.h>
diff --git a/include/asm-sparc64/parport.h b/include/asm-sparc64/parport.h
deleted file mode 100644
index b4e4ca812eb..00000000000
--- a/include/asm-sparc64/parport.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/parport.h>
diff --git a/include/asm-sparc64/pci.h b/include/asm-sparc64/pci.h
deleted file mode 100644
index da54c4d1f39..00000000000
--- a/include/asm-sparc64/pci.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/pci.h>
diff --git a/include/asm-sparc64/percpu.h b/include/asm-sparc64/percpu.h
deleted file mode 100644
index 292729bb350..00000000000
--- a/include/asm-sparc64/percpu.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/percpu.h>
diff --git a/include/asm-sparc64/perfctr.h b/include/asm-sparc64/perfctr.h
deleted file mode 100644
index 52073a9f8e3..00000000000
--- a/include/asm-sparc64/perfctr.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/perfctr.h>
diff --git a/include/asm-sparc64/pgalloc.h b/include/asm-sparc64/pgalloc.h
deleted file mode 100644
index bec31641011..00000000000
--- a/include/asm-sparc64/pgalloc.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/pgalloc.h>
diff --git a/include/asm-sparc64/pgtable.h b/include/asm-sparc64/pgtable.h
deleted file mode 100644
index 9decbd99aef..00000000000
--- a/include/asm-sparc64/pgtable.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/pgtable.h>
diff --git a/include/asm-sparc64/pil.h b/include/asm-sparc64/pil.h
deleted file mode 100644
index d805f33f1e0..00000000000
--- a/include/asm-sparc64/pil.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/pil.h>
diff --git a/include/asm-sparc64/poll.h b/include/asm-sparc64/poll.h
deleted file mode 100644
index 8e2f31b4641..00000000000
--- a/include/asm-sparc64/poll.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/poll.h>
diff --git a/include/asm-sparc64/posix_types.h b/include/asm-sparc64/posix_types.h
deleted file mode 100644
index 8cee9920023..00000000000
--- a/include/asm-sparc64/posix_types.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/posix_types.h>
diff --git a/include/asm-sparc64/processor.h b/include/asm-sparc64/processor.h
deleted file mode 100644
index 21de6cc182e..00000000000
--- a/include/asm-sparc64/processor.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/processor.h>
diff --git a/include/asm-sparc64/prom.h b/include/asm-sparc64/prom.h
deleted file mode 100644
index 5fa166ee3ff..00000000000
--- a/include/asm-sparc64/prom.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/prom.h>
diff --git a/include/asm-sparc64/psrcompat.h b/include/asm-sparc64/psrcompat.h
deleted file mode 100644
index 587846f4835..00000000000
--- a/include/asm-sparc64/psrcompat.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/psrcompat.h>
diff --git a/include/asm-sparc64/pstate.h b/include/asm-sparc64/pstate.h
deleted file mode 100644
index 3ccf0be2536..00000000000
--- a/include/asm-sparc64/pstate.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/pstate.h>
diff --git a/include/asm-sparc64/ptrace.h b/include/asm-sparc64/ptrace.h
deleted file mode 100644
index 1a55b9fb3b0..00000000000
--- a/include/asm-sparc64/ptrace.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/ptrace.h>
diff --git a/include/asm-sparc64/reboot.h b/include/asm-sparc64/reboot.h
deleted file mode 100644
index 0d72eb811cc..00000000000
--- a/include/asm-sparc64/reboot.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/reboot.h>
diff --git a/include/asm-sparc64/reg.h b/include/asm-sparc64/reg.h
deleted file mode 100644
index 495bab27da0..00000000000
--- a/include/asm-sparc64/reg.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/reg.h>
diff --git a/include/asm-sparc64/resource.h b/include/asm-sparc64/resource.h
deleted file mode 100644
index 46e3bc0de47..00000000000
--- a/include/asm-sparc64/resource.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/resource.h>
diff --git a/include/asm-sparc64/rtc.h b/include/asm-sparc64/rtc.h
deleted file mode 100644
index e49a9685aea..00000000000
--- a/include/asm-sparc64/rtc.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/rtc.h>
diff --git a/include/asm-sparc64/rwsem-const.h b/include/asm-sparc64/rwsem-const.h
deleted file mode 100644
index 2a1de315c86..00000000000
--- a/include/asm-sparc64/rwsem-const.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/rwsem-const.h>
diff --git a/include/asm-sparc64/rwsem.h b/include/asm-sparc64/rwsem.h
deleted file mode 100644
index 6943c56ed08..00000000000
--- a/include/asm-sparc64/rwsem.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/rwsem.h>
diff --git a/include/asm-sparc64/sbus.h b/include/asm-sparc64/sbus.h
deleted file mode 100644
index 0cab0e89b87..00000000000
--- a/include/asm-sparc64/sbus.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/sbus.h>
diff --git a/include/asm-sparc64/scatterlist.h b/include/asm-sparc64/scatterlist.h
deleted file mode 100644
index b7fef95953c..00000000000
--- a/include/asm-sparc64/scatterlist.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/scatterlist.h>
diff --git a/include/asm-sparc64/scratchpad.h b/include/asm-sparc64/scratchpad.h
deleted file mode 100644
index 23675f6a915..00000000000
--- a/include/asm-sparc64/scratchpad.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/scratchpad.h>
diff --git a/include/asm-sparc64/seccomp.h b/include/asm-sparc64/seccomp.h
deleted file mode 100644
index f22f02a08a6..00000000000
--- a/include/asm-sparc64/seccomp.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/seccomp.h>
diff --git a/include/asm-sparc64/sections.h b/include/asm-sparc64/sections.h
deleted file mode 100644
index 721496f8b2b..00000000000
--- a/include/asm-sparc64/sections.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/sections.h>
diff --git a/include/asm-sparc64/sembuf.h b/include/asm-sparc64/sembuf.h
deleted file mode 100644
index c55b9521413..00000000000
--- a/include/asm-sparc64/sembuf.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/sembuf.h>
diff --git a/include/asm-sparc64/setup.h b/include/asm-sparc64/setup.h
deleted file mode 100644
index 7143d06b2c5..00000000000
--- a/include/asm-sparc64/setup.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/setup.h>
diff --git a/include/asm-sparc64/sfafsr.h b/include/asm-sparc64/sfafsr.h
deleted file mode 100644
index 8036fc377a4..00000000000
--- a/include/asm-sparc64/sfafsr.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/sfafsr.h>
diff --git a/include/asm-sparc64/sfp-machine.h b/include/asm-sparc64/sfp-machine.h
deleted file mode 100644
index 7bbc4fecdc7..00000000000
--- a/include/asm-sparc64/sfp-machine.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/sfp-machine.h>
diff --git a/include/asm-sparc64/shmbuf.h b/include/asm-sparc64/shmbuf.h
deleted file mode 100644
index 0c54a2d6868..00000000000
--- a/include/asm-sparc64/shmbuf.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/shmbuf.h>
diff --git a/include/asm-sparc64/shmparam.h b/include/asm-sparc64/shmparam.h
deleted file mode 100644
index 5fa3a9b05e7..00000000000
--- a/include/asm-sparc64/shmparam.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/shmparam.h>
diff --git a/include/asm-sparc64/sigcontext.h b/include/asm-sparc64/sigcontext.h
deleted file mode 100644
index 5b16dcce44f..00000000000
--- a/include/asm-sparc64/sigcontext.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/sigcontext.h>
diff --git a/include/asm-sparc64/siginfo.h b/include/asm-sparc64/siginfo.h
deleted file mode 100644
index 8ffd6ebabc7..00000000000
--- a/include/asm-sparc64/siginfo.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/siginfo.h>
diff --git a/include/asm-sparc64/signal.h b/include/asm-sparc64/signal.h
deleted file mode 100644
index 79705e5d49c..00000000000
--- a/include/asm-sparc64/signal.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/signal.h>
diff --git a/include/asm-sparc64/smp.h b/include/asm-sparc64/smp.h
deleted file mode 100644
index 5095a2cbea5..00000000000
--- a/include/asm-sparc64/smp.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/smp.h>
diff --git a/include/asm-sparc64/socket.h b/include/asm-sparc64/socket.h
deleted file mode 100644
index 13e0d5d94bb..00000000000
--- a/include/asm-sparc64/socket.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/socket.h>
diff --git a/include/asm-sparc64/sockios.h b/include/asm-sparc64/sockios.h
deleted file mode 100644
index 2cb4b641482..00000000000
--- a/include/asm-sparc64/sockios.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/sockios.h>
diff --git a/include/asm-sparc64/sparsemem.h b/include/asm-sparc64/sparsemem.h
deleted file mode 100644
index e681f22a97a..00000000000
--- a/include/asm-sparc64/sparsemem.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/sparsemem.h>
diff --git a/include/asm-sparc64/spinlock.h b/include/asm-sparc64/spinlock.h
deleted file mode 100644
index 0115b8156eb..00000000000
--- a/include/asm-sparc64/spinlock.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/spinlock.h>
diff --git a/include/asm-sparc64/spinlock_types.h b/include/asm-sparc64/spinlock_types.h
deleted file mode 100644
index 48d81c8734b..00000000000
--- a/include/asm-sparc64/spinlock_types.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/spinlock_types.h>
diff --git a/include/asm-sparc64/spitfire.h b/include/asm-sparc64/spitfire.h
deleted file mode 100644
index 4430d2fbb0d..00000000000
--- a/include/asm-sparc64/spitfire.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/spitfire.h>
diff --git a/include/asm-sparc64/sstate.h b/include/asm-sparc64/sstate.h
deleted file mode 100644
index 97720ce2fd4..00000000000
--- a/include/asm-sparc64/sstate.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/sstate.h>
diff --git a/include/asm-sparc64/stacktrace.h b/include/asm-sparc64/stacktrace.h
deleted file mode 100644
index adc9b92c0ef..00000000000
--- a/include/asm-sparc64/stacktrace.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/stacktrace.h>
diff --git a/include/asm-sparc64/starfire.h b/include/asm-sparc64/starfire.h
deleted file mode 100644
index db97daa3bed..00000000000
--- a/include/asm-sparc64/starfire.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/starfire.h>
diff --git a/include/asm-sparc64/stat.h b/include/asm-sparc64/stat.h
deleted file mode 100644
index b108a866256..00000000000
--- a/include/asm-sparc64/stat.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/stat.h>
diff --git a/include/asm-sparc64/statfs.h b/include/asm-sparc64/statfs.h
deleted file mode 100644
index 5503d6a4c67..00000000000
--- a/include/asm-sparc64/statfs.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/statfs.h>
diff --git a/include/asm-sparc64/string.h b/include/asm-sparc64/string.h
deleted file mode 100644
index 5018cd8b6ad..00000000000
--- a/include/asm-sparc64/string.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/string.h>
diff --git a/include/asm-sparc64/sunbpp.h b/include/asm-sparc64/sunbpp.h
deleted file mode 100644
index 9632be290eb..00000000000
--- a/include/asm-sparc64/sunbpp.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/sunbpp.h>
diff --git a/include/asm-sparc64/syscalls.h b/include/asm-sparc64/syscalls.h
deleted file mode 100644
index 3477b16e30c..00000000000
--- a/include/asm-sparc64/syscalls.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/syscalls.h>
diff --git a/include/asm-sparc64/system.h b/include/asm-sparc64/system.h
deleted file mode 100644
index be2603c2e52..00000000000
--- a/include/asm-sparc64/system.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/system.h>
diff --git a/include/asm-sparc64/termbits.h b/include/asm-sparc64/termbits.h
deleted file mode 100644
index e03f97592c7..00000000000
--- a/include/asm-sparc64/termbits.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/termbits.h>
diff --git a/include/asm-sparc64/termios.h b/include/asm-sparc64/termios.h
deleted file mode 100644
index 940495eb05c..00000000000
--- a/include/asm-sparc64/termios.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/termios.h>
diff --git a/include/asm-sparc64/thread_info.h b/include/asm-sparc64/thread_info.h
deleted file mode 100644
index 92bed791339..00000000000
--- a/include/asm-sparc64/thread_info.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/thread_info.h>
diff --git a/include/asm-sparc64/timer.h b/include/asm-sparc64/timer.h
deleted file mode 100644
index 88026d83cc9..00000000000
--- a/include/asm-sparc64/timer.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/timer.h>
diff --git a/include/asm-sparc64/timex.h b/include/asm-sparc64/timex.h
deleted file mode 100644
index 8dd59ee24b4..00000000000
--- a/include/asm-sparc64/timex.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/timex.h>
diff --git a/include/asm-sparc64/tlb.h b/include/asm-sparc64/tlb.h
deleted file mode 100644
index ae92fce1093..00000000000
--- a/include/asm-sparc64/tlb.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/tlb.h>
diff --git a/include/asm-sparc64/tlbflush.h b/include/asm-sparc64/tlbflush.h
deleted file mode 100644
index a43979a06cd..00000000000
--- a/include/asm-sparc64/tlbflush.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/tlbflush.h>
diff --git a/include/asm-sparc64/topology.h b/include/asm-sparc64/topology.h
deleted file mode 100644
index 46999b60fbb..00000000000
--- a/include/asm-sparc64/topology.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/topology.h>
diff --git a/include/asm-sparc64/tsb.h b/include/asm-sparc64/tsb.h
deleted file mode 100644
index 3677a302ea3..00000000000
--- a/include/asm-sparc64/tsb.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/tsb.h>
diff --git a/include/asm-sparc64/ttable.h b/include/asm-sparc64/ttable.h
deleted file mode 100644
index a550f1bf6f9..00000000000
--- a/include/asm-sparc64/ttable.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/ttable.h>
diff --git a/include/asm-sparc64/types.h b/include/asm-sparc64/types.h
deleted file mode 100644
index cfbfad5043e..00000000000
--- a/include/asm-sparc64/types.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/types.h>
diff --git a/include/asm-sparc64/uaccess.h b/include/asm-sparc64/uaccess.h
deleted file mode 100644
index 2872d22844f..00000000000
--- a/include/asm-sparc64/uaccess.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/uaccess.h>
diff --git a/include/asm-sparc64/uctx.h b/include/asm-sparc64/uctx.h
deleted file mode 100644
index 9e1b5794b07..00000000000
--- a/include/asm-sparc64/uctx.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/uctx.h>
diff --git a/include/asm-sparc64/unaligned.h b/include/asm-sparc64/unaligned.h
deleted file mode 100644
index 19fbf9508ac..00000000000
--- a/include/asm-sparc64/unaligned.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/unaligned.h>
diff --git a/include/asm-sparc64/unistd.h b/include/asm-sparc64/unistd.h
deleted file mode 100644
index ad86e0b7a45..00000000000
--- a/include/asm-sparc64/unistd.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/unistd.h>
diff --git a/include/asm-sparc64/upa.h b/include/asm-sparc64/upa.h
deleted file mode 100644
index aab72930815..00000000000
--- a/include/asm-sparc64/upa.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/upa.h>
diff --git a/include/asm-sparc64/user.h b/include/asm-sparc64/user.h
deleted file mode 100644
index 29fc6e906c2..00000000000
--- a/include/asm-sparc64/user.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/user.h>
diff --git a/include/asm-sparc64/utrap.h b/include/asm-sparc64/utrap.h
deleted file mode 100644
index b030a41f189..00000000000
--- a/include/asm-sparc64/utrap.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/utrap.h>
diff --git a/include/asm-sparc64/vga.h b/include/asm-sparc64/vga.h
deleted file mode 100644
index fbf4d58a56f..00000000000
--- a/include/asm-sparc64/vga.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/vga.h>
diff --git a/include/asm-sparc64/vio.h b/include/asm-sparc64/vio.h
deleted file mode 100644
index 299b26ab81a..00000000000
--- a/include/asm-sparc64/vio.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/vio.h>
diff --git a/include/asm-sparc64/visasm.h b/include/asm-sparc64/visasm.h
deleted file mode 100644
index 837a12278f4..00000000000
--- a/include/asm-sparc64/visasm.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/visasm.h>
diff --git a/include/asm-sparc64/watchdog.h b/include/asm-sparc64/watchdog.h
deleted file mode 100644
index b0f2857145f..00000000000
--- a/include/asm-sparc64/watchdog.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/watchdog.h>
diff --git a/include/asm-sparc64/xor.h b/include/asm-sparc64/xor.h
deleted file mode 100644
index ef187cc07ed..00000000000
--- a/include/asm-sparc64/xor.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-sparc/xor.h>
diff --git a/include/asm-x86/dma-mapping.h b/include/asm-x86/dma-mapping.h
index 0eaa9bf6011..ad9cd6d49bf 100644
--- a/include/asm-x86/dma-mapping.h
+++ b/include/asm-x86/dma-mapping.h
@@ -249,25 +249,5 @@ static inline int dma_get_cache_alignment(void)
249 249
250#define dma_is_consistent(d, h) (1) 250#define dma_is_consistent(d, h) (1)
251 251
252#ifdef CONFIG_X86_32 252#include <asm-generic/dma-coherent.h>
253# define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
254struct dma_coherent_mem {
255 void *virt_base;
256 u32 device_base;
257 int size;
258 int flags;
259 unsigned long *bitmap;
260};
261
262extern int
263dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
264 dma_addr_t device_addr, size_t size, int flags);
265
266extern void
267dma_release_declared_memory(struct device *dev);
268
269extern void *
270dma_mark_declared_memory_occupied(struct device *dev,
271 dma_addr_t device_addr, size_t size);
272#endif /* CONFIG_X86_32 */
273#endif 253#endif
diff --git a/include/asm-x86/iommu.h b/include/asm-x86/iommu.h
index ecc8061904a..5f888cc5be4 100644
--- a/include/asm-x86/iommu.h
+++ b/include/asm-x86/iommu.h
@@ -7,6 +7,8 @@ extern struct dma_mapping_ops nommu_dma_ops;
7extern int force_iommu, no_iommu; 7extern int force_iommu, no_iommu;
8extern int iommu_detected; 8extern int iommu_detected;
9 9
10extern unsigned long iommu_num_pages(unsigned long addr, unsigned long len);
11
10#ifdef CONFIG_GART_IOMMU 12#ifdef CONFIG_GART_IOMMU
11extern int gart_iommu_aperture; 13extern int gart_iommu_aperture;
12extern int gart_iommu_aperture_allowed; 14extern int gart_iommu_aperture_allowed;
diff --git a/include/asm-x86/kvm_host.h b/include/asm-x86/kvm_host.h
index bc34dc21f17..0f3c5311461 100644
--- a/include/asm-x86/kvm_host.h
+++ b/include/asm-x86/kvm_host.h
@@ -13,6 +13,7 @@
13 13
14#include <linux/types.h> 14#include <linux/types.h>
15#include <linux/mm.h> 15#include <linux/mm.h>
16#include <linux/mmu_notifier.h>
16 17
17#include <linux/kvm.h> 18#include <linux/kvm.h>
18#include <linux/kvm_para.h> 19#include <linux/kvm_para.h>
@@ -251,6 +252,7 @@ struct kvm_vcpu_arch {
251 gfn_t gfn; /* presumed gfn during guest pte update */ 252 gfn_t gfn; /* presumed gfn during guest pte update */
252 pfn_t pfn; /* pfn corresponding to that gfn */ 253 pfn_t pfn; /* pfn corresponding to that gfn */
253 int largepage; 254 int largepage;
255 unsigned long mmu_seq;
254 } update_pte; 256 } update_pte;
255 257
256 struct i387_fxsave_struct host_fx_image; 258 struct i387_fxsave_struct host_fx_image;
@@ -729,4 +731,8 @@ asmlinkage void kvm_handle_fault_on_reboot(void);
729 KVM_EX_ENTRY " 666b, 667b \n\t" \ 731 KVM_EX_ENTRY " 666b, 667b \n\t" \
730 ".popsection" 732 ".popsection"
731 733
734#define KVM_ARCH_WANT_MMU_NOTIFIER
735int kvm_unmap_hva(struct kvm *kvm, unsigned long hva);
736int kvm_age_hva(struct kvm *kvm, unsigned long hva);
737
732#endif 738#endif
diff --git a/include/linux/Kbuild b/include/linux/Kbuild
index 4c4142c5aa6..a26f565e818 100644
--- a/include/linux/Kbuild
+++ b/include/linux/Kbuild
@@ -97,6 +97,7 @@ header-y += ioctl.h
97header-y += ip6_tunnel.h 97header-y += ip6_tunnel.h
98header-y += ipmi_msgdefs.h 98header-y += ipmi_msgdefs.h
99header-y += ipsec.h 99header-y += ipsec.h
100header-y += ip_vs.h
100header-y += ipx.h 101header-y += ipx.h
101header-y += irda.h 102header-y += irda.h
102header-y += iso_fs.h 103header-y += iso_fs.h
diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h
index 88d68081a0f..e61f22be4d0 100644
--- a/include/linux/blkdev.h
+++ b/include/linux/blkdev.h
@@ -655,6 +655,7 @@ extern struct request *blk_get_request(struct request_queue *, int, gfp_t);
655extern void blk_insert_request(struct request_queue *, struct request *, int, void *); 655extern void blk_insert_request(struct request_queue *, struct request *, int, void *);
656extern void blk_requeue_request(struct request_queue *, struct request *); 656extern void blk_requeue_request(struct request_queue *, struct request *);
657extern void blk_plug_device(struct request_queue *); 657extern void blk_plug_device(struct request_queue *);
658extern void blk_plug_device_unlocked(struct request_queue *);
658extern int blk_remove_plug(struct request_queue *); 659extern int blk_remove_plug(struct request_queue *);
659extern void blk_recount_segments(struct request_queue *, struct bio *); 660extern void blk_recount_segments(struct request_queue *, struct bio *);
660extern int scsi_cmd_ioctl(struct file *, struct request_queue *, 661extern int scsi_cmd_ioctl(struct file *, struct request_queue *,
diff --git a/include/linux/buffer_head.h b/include/linux/buffer_head.h
index 82aa36c53ea..eadaab44015 100644
--- a/include/linux/buffer_head.h
+++ b/include/linux/buffer_head.h
@@ -115,7 +115,6 @@ BUFFER_FNS(Uptodate, uptodate)
115BUFFER_FNS(Dirty, dirty) 115BUFFER_FNS(Dirty, dirty)
116TAS_BUFFER_FNS(Dirty, dirty) 116TAS_BUFFER_FNS(Dirty, dirty)
117BUFFER_FNS(Lock, locked) 117BUFFER_FNS(Lock, locked)
118TAS_BUFFER_FNS(Lock, locked)
119BUFFER_FNS(Req, req) 118BUFFER_FNS(Req, req)
120TAS_BUFFER_FNS(Req, req) 119TAS_BUFFER_FNS(Req, req)
121BUFFER_FNS(Mapped, mapped) 120BUFFER_FNS(Mapped, mapped)
@@ -205,6 +204,8 @@ void block_invalidatepage(struct page *page, unsigned long offset);
205int block_write_full_page(struct page *page, get_block_t *get_block, 204int block_write_full_page(struct page *page, get_block_t *get_block,
206 struct writeback_control *wbc); 205 struct writeback_control *wbc);
207int block_read_full_page(struct page*, get_block_t*); 206int block_read_full_page(struct page*, get_block_t*);
207int block_is_partially_uptodate(struct page *page, read_descriptor_t *desc,
208 unsigned long from);
208int block_write_begin(struct file *, struct address_space *, 209int block_write_begin(struct file *, struct address_space *,
209 loff_t, unsigned, unsigned, 210 loff_t, unsigned, unsigned,
210 struct page **, void **, get_block_t*); 211 struct page **, void **, get_block_t*);
@@ -319,10 +320,15 @@ static inline void wait_on_buffer(struct buffer_head *bh)
319 __wait_on_buffer(bh); 320 __wait_on_buffer(bh);
320} 321}
321 322
323static inline int trylock_buffer(struct buffer_head *bh)
324{
325 return likely(!test_and_set_bit(BH_Lock, &bh->b_state));
326}
327
322static inline void lock_buffer(struct buffer_head *bh) 328static inline void lock_buffer(struct buffer_head *bh)
323{ 329{
324 might_sleep(); 330 might_sleep();
325 if (test_set_buffer_locked(bh)) 331 if (!trylock_buffer(bh))
326 __lock_buffer(bh); 332 __lock_buffer(bh);
327} 333}
328 334
diff --git a/include/linux/configfs.h b/include/linux/configfs.h
index d62c19ff041..7f627775c94 100644
--- a/include/linux/configfs.h
+++ b/include/linux/configfs.h
@@ -40,6 +40,7 @@
40#include <linux/list.h> 40#include <linux/list.h>
41#include <linux/kref.h> 41#include <linux/kref.h>
42#include <linux/mutex.h> 42#include <linux/mutex.h>
43#include <linux/err.h>
43 44
44#include <asm/atomic.h> 45#include <asm/atomic.h>
45 46
@@ -129,8 +130,25 @@ struct configfs_attribute {
129/* 130/*
130 * Users often need to create attribute structures for their configurable 131 * Users often need to create attribute structures for their configurable
131 * attributes, containing a configfs_attribute member and function pointers 132 * attributes, containing a configfs_attribute member and function pointers
132 * for the show() and store() operations on that attribute. They can use 133 * for the show() and store() operations on that attribute. If they don't
133 * this macro (similar to sysfs' __ATTR) to make defining attributes easier. 134 * need anything else on the extended attribute structure, they can use
135 * this macro to define it The argument _item is the name of the
136 * config_item structure.
137 */
138#define CONFIGFS_ATTR_STRUCT(_item) \
139struct _item##_attribute { \
140 struct configfs_attribute attr; \
141 ssize_t (*show)(struct _item *, char *); \
142 ssize_t (*store)(struct _item *, const char *, size_t); \
143}
144
145/*
146 * With the extended attribute structure, users can use this macro
147 * (similar to sysfs' __ATTR) to make defining attributes easier.
148 * An example:
149 * #define MYITEM_ATTR(_name, _mode, _show, _store) \
150 * struct myitem_attribute childless_attr_##_name = \
151 * __CONFIGFS_ATTR(_name, _mode, _show, _store)
134 */ 152 */
135#define __CONFIGFS_ATTR(_name, _mode, _show, _store) \ 153#define __CONFIGFS_ATTR(_name, _mode, _show, _store) \
136{ \ 154{ \
@@ -142,6 +160,52 @@ struct configfs_attribute {
142 .show = _show, \ 160 .show = _show, \
143 .store = _store, \ 161 .store = _store, \
144} 162}
163/* Here is a readonly version, only requiring a show() operation */
164#define __CONFIGFS_ATTR_RO(_name, _show) \
165{ \
166 .attr = { \
167 .ca_name = __stringify(_name), \
168 .ca_mode = 0444, \
169 .ca_owner = THIS_MODULE, \
170 }, \
171 .show = _show, \
172}
173
174/*
175 * With these extended attributes, the simple show_attribute() and
176 * store_attribute() operations need to call the show() and store() of the
177 * attributes. This is a common pattern, so we provide a macro to define
178 * them. The argument _item is the name of the config_item structure.
179 * This macro expects the attributes to be named "struct <name>_attribute"
180 * and the function to_<name>() to exist;
181 */
182#define CONFIGFS_ATTR_OPS(_item) \
183static ssize_t _item##_attr_show(struct config_item *item, \
184 struct configfs_attribute *attr, \
185 char *page) \
186{ \
187 struct _item *_item = to_##_item(item); \
188 struct _item##_attribute *_item##_attr = \
189 container_of(attr, struct _item##_attribute, attr); \
190 ssize_t ret = 0; \
191 \
192 if (_item##_attr->show) \
193 ret = _item##_attr->show(_item, page); \
194 return ret; \
195} \
196static ssize_t _item##_attr_store(struct config_item *item, \
197 struct configfs_attribute *attr, \
198 const char *page, size_t count) \
199{ \
200 struct _item *_item = to_##_item(item); \
201 struct _item##_attribute *_item##_attr = \
202 container_of(attr, struct _item##_attribute, attr); \
203 ssize_t ret = -EINVAL; \
204 \
205 if (_item##_attr->store) \
206 ret = _item##_attr->store(_item, page, count); \
207 return ret; \
208}
145 209
146/* 210/*
147 * If allow_link() exists, the item can symlink(2) out to other 211 * If allow_link() exists, the item can symlink(2) out to other
diff --git a/include/linux/connector.h b/include/linux/connector.h
index 96a89d3d672..5c7f9468f75 100644
--- a/include/linux/connector.h
+++ b/include/linux/connector.h
@@ -38,8 +38,9 @@
38#define CN_W1_VAL 0x1 38#define CN_W1_VAL 0x1
39#define CN_IDX_V86D 0x4 39#define CN_IDX_V86D 0x4
40#define CN_VAL_V86D_UVESAFB 0x1 40#define CN_VAL_V86D_UVESAFB 0x1
41#define CN_IDX_BB 0x5 /* BlackBoard, from the TSP GPL sampling framework */
41 42
42#define CN_NETLINK_USERS 5 43#define CN_NETLINK_USERS 6
43 44
44/* 45/*
45 * Maximum connector's message size. 46 * Maximum connector's message size.
diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h
index 2270ca5ec63..6fd5668aa57 100644
--- a/include/linux/cpufreq.h
+++ b/include/linux/cpufreq.h
@@ -106,6 +106,7 @@ struct cpufreq_policy {
106#define CPUFREQ_ADJUST (0) 106#define CPUFREQ_ADJUST (0)
107#define CPUFREQ_INCOMPATIBLE (1) 107#define CPUFREQ_INCOMPATIBLE (1)
108#define CPUFREQ_NOTIFY (2) 108#define CPUFREQ_NOTIFY (2)
109#define CPUFREQ_START (3)
109 110
110#define CPUFREQ_SHARED_TYPE_NONE (0) /* None */ 111#define CPUFREQ_SHARED_TYPE_NONE (0) /* None */
111#define CPUFREQ_SHARED_TYPE_HW (1) /* HW does needed coordination */ 112#define CPUFREQ_SHARED_TYPE_HW (1) /* HW does needed coordination */
diff --git a/include/linux/cpumask.h b/include/linux/cpumask.h
index 1b5c98e7fef..d3219d73f8e 100644
--- a/include/linux/cpumask.h
+++ b/include/linux/cpumask.h
@@ -62,15 +62,7 @@
62 * int next_cpu_nr(cpu, mask) Next cpu past 'cpu', or nr_cpu_ids 62 * int next_cpu_nr(cpu, mask) Next cpu past 'cpu', or nr_cpu_ids
63 * 63 *
64 * cpumask_t cpumask_of_cpu(cpu) Return cpumask with bit 'cpu' set 64 * cpumask_t cpumask_of_cpu(cpu) Return cpumask with bit 'cpu' set
65 *ifdef CONFIG_HAS_CPUMASK_OF_CPU 65 * (can be used as an lvalue)
66 * cpumask_of_cpu_ptr_declare(v) Declares cpumask_t *v
67 * cpumask_of_cpu_ptr_next(v, cpu) Sets v = &cpumask_of_cpu_map[cpu]
68 * cpumask_of_cpu_ptr(v, cpu) Combines above two operations
69 *else
70 * cpumask_of_cpu_ptr_declare(v) Declares cpumask_t _v and *v = &_v
71 * cpumask_of_cpu_ptr_next(v, cpu) Sets _v = cpumask_of_cpu(cpu)
72 * cpumask_of_cpu_ptr(v, cpu) Combines above two operations
73 *endif
74 * CPU_MASK_ALL Initializer - all bits set 66 * CPU_MASK_ALL Initializer - all bits set
75 * CPU_MASK_NONE Initializer - no bits set 67 * CPU_MASK_NONE Initializer - no bits set
76 * unsigned long *cpus_addr(mask) Array of unsigned long's in mask 68 * unsigned long *cpus_addr(mask) Array of unsigned long's in mask
@@ -273,37 +265,30 @@ static inline void __cpus_shift_left(cpumask_t *dstp,
273 bitmap_shift_left(dstp->bits, srcp->bits, n, nbits); 265 bitmap_shift_left(dstp->bits, srcp->bits, n, nbits);
274} 266}
275 267
268/*
269 * Special-case data structure for "single bit set only" constant CPU masks.
270 *
271 * We pre-generate all the 64 (or 32) possible bit positions, with enough
272 * padding to the left and the right, and return the constant pointer
273 * appropriately offset.
274 */
275extern const unsigned long
276 cpu_bit_bitmap[BITS_PER_LONG+1][BITS_TO_LONGS(NR_CPUS)];
277
278static inline const cpumask_t *get_cpu_mask(unsigned int cpu)
279{
280 const unsigned long *p = cpu_bit_bitmap[1 + cpu % BITS_PER_LONG];
281 p -= cpu / BITS_PER_LONG;
282 return (const cpumask_t *)p;
283}
284
285/*
286 * In cases where we take the address of the cpumask immediately,
287 * gcc optimizes it out (it's a constant) and there's no huge stack
288 * variable created:
289 */
290#define cpumask_of_cpu(cpu) (*get_cpu_mask(cpu))
276 291
277#ifdef CONFIG_HAVE_CPUMASK_OF_CPU_MAP
278extern cpumask_t *cpumask_of_cpu_map;
279#define cpumask_of_cpu(cpu) (cpumask_of_cpu_map[cpu])
280#define cpumask_of_cpu_ptr(v, cpu) \
281 const cpumask_t *v = &cpumask_of_cpu(cpu)
282#define cpumask_of_cpu_ptr_declare(v) \
283 const cpumask_t *v
284#define cpumask_of_cpu_ptr_next(v, cpu) \
285 v = &cpumask_of_cpu(cpu)
286#else
287#define cpumask_of_cpu(cpu) \
288({ \
289 typeof(_unused_cpumask_arg_) m; \
290 if (sizeof(m) == sizeof(unsigned long)) { \
291 m.bits[0] = 1UL<<(cpu); \
292 } else { \
293 cpus_clear(m); \
294 cpu_set((cpu), m); \
295 } \
296 m; \
297})
298#define cpumask_of_cpu_ptr(v, cpu) \
299 cpumask_t _##v = cpumask_of_cpu(cpu); \
300 const cpumask_t *v = &_##v
301#define cpumask_of_cpu_ptr_declare(v) \
302 cpumask_t _##v; \
303 const cpumask_t *v = &_##v
304#define cpumask_of_cpu_ptr_next(v, cpu) \
305 _##v = cpumask_of_cpu(cpu)
306#endif
307 292
308#define CPU_MASK_LAST_WORD BITMAP_LAST_WORD_MASK(NR_CPUS) 293#define CPU_MASK_LAST_WORD BITMAP_LAST_WORD_MASK(NR_CPUS)
309 294
diff --git a/include/linux/dcache.h b/include/linux/dcache.h
index 98202c672fd..07aa198f19e 100644
--- a/include/linux/dcache.h
+++ b/include/linux/dcache.h
@@ -230,6 +230,7 @@ extern void d_delete(struct dentry *);
230extern struct dentry * d_alloc(struct dentry *, const struct qstr *); 230extern struct dentry * d_alloc(struct dentry *, const struct qstr *);
231extern struct dentry * d_alloc_anon(struct inode *); 231extern struct dentry * d_alloc_anon(struct inode *);
232extern struct dentry * d_splice_alias(struct inode *, struct dentry *); 232extern struct dentry * d_splice_alias(struct inode *, struct dentry *);
233extern struct dentry * d_add_ci(struct inode *, struct dentry *, struct qstr *);
233extern void shrink_dcache_sb(struct super_block *); 234extern void shrink_dcache_sb(struct super_block *);
234extern void shrink_dcache_parent(struct dentry *); 235extern void shrink_dcache_parent(struct dentry *);
235extern void shrink_dcache_for_umount(struct super_block *); 236extern void shrink_dcache_for_umount(struct super_block *);
diff --git a/include/linux/file.h b/include/linux/file.h
index 27c64bdc68c..a20259e248a 100644
--- a/include/linux/file.h
+++ b/include/linux/file.h
@@ -34,8 +34,9 @@ extern struct file *fget(unsigned int fd);
34extern struct file *fget_light(unsigned int fd, int *fput_needed); 34extern struct file *fget_light(unsigned int fd, int *fput_needed);
35extern void set_close_on_exec(unsigned int fd, int flag); 35extern void set_close_on_exec(unsigned int fd, int flag);
36extern void put_filp(struct file *); 36extern void put_filp(struct file *);
37extern int alloc_fd(unsigned start, unsigned flags);
37extern int get_unused_fd(void); 38extern int get_unused_fd(void);
38extern int get_unused_fd_flags(int flags); 39#define get_unused_fd_flags(flags) alloc_fd(0, (flags))
39extern void put_unused_fd(unsigned int fd); 40extern void put_unused_fd(unsigned int fd);
40 41
41extern void fd_install(unsigned int fd, struct file *file); 42extern void fd_install(unsigned int fd, struct file *file);
diff --git a/include/linux/fs.h b/include/linux/fs.h
index 8252b045e62..580b513668f 100644
--- a/include/linux/fs.h
+++ b/include/linux/fs.h
@@ -443,6 +443,27 @@ static inline size_t iov_iter_count(struct iov_iter *i)
443 return i->count; 443 return i->count;
444} 444}
445 445
446/*
447 * "descriptor" for what we're up to with a read.
448 * This allows us to use the same read code yet
449 * have multiple different users of the data that
450 * we read from a file.
451 *
452 * The simplest case just copies the data to user
453 * mode.
454 */
455typedef struct {
456 size_t written;
457 size_t count;
458 union {
459 char __user *buf;
460 void *data;
461 } arg;
462 int error;
463} read_descriptor_t;
464
465typedef int (*read_actor_t)(read_descriptor_t *, struct page *,
466 unsigned long, unsigned long);
446 467
447struct address_space_operations { 468struct address_space_operations {
448 int (*writepage)(struct page *page, struct writeback_control *wbc); 469 int (*writepage)(struct page *page, struct writeback_control *wbc);
@@ -484,6 +505,8 @@ struct address_space_operations {
484 int (*migratepage) (struct address_space *, 505 int (*migratepage) (struct address_space *,
485 struct page *, struct page *); 506 struct page *, struct page *);
486 int (*launder_page) (struct page *); 507 int (*launder_page) (struct page *);
508 int (*is_partially_uptodate) (struct page *, read_descriptor_t *,
509 unsigned long);
487}; 510};
488 511
489/* 512/*
@@ -1198,27 +1221,6 @@ struct block_device_operations {
1198 struct module *owner; 1221 struct module *owner;
1199}; 1222};
1200 1223
1201/*
1202 * "descriptor" for what we're up to with a read.
1203 * This allows us to use the same read code yet
1204 * have multiple different users of the data that
1205 * we read from a file.
1206 *
1207 * The simplest case just copies the data to user
1208 * mode.
1209 */
1210typedef struct {
1211 size_t written;
1212 size_t count;
1213 union {
1214 char __user * buf;
1215 void *data;
1216 } arg;
1217 int error;
1218} read_descriptor_t;
1219
1220typedef int (*read_actor_t)(read_descriptor_t *, struct page *, unsigned long, unsigned long);
1221
1222/* These macros are for out of kernel modules to test that 1224/* These macros are for out of kernel modules to test that
1223 * the kernel supports the unlocked_ioctl and compat_ioctl 1225 * the kernel supports the unlocked_ioctl and compat_ioctl
1224 * fields in struct file_operations. */ 1226 * fields in struct file_operations. */
diff --git a/include/linux/ide.h b/include/linux/ide.h
index b846bc44a27..87c12ed9695 100644
--- a/include/linux/ide.h
+++ b/include/linux/ide.h
@@ -219,18 +219,7 @@ static inline int __ide_default_irq(unsigned long base)
219#include <asm-generic/ide_iops.h> 219#include <asm-generic/ide_iops.h>
220#endif 220#endif
221 221
222#ifndef MAX_HWIFS 222#define MAX_HWIFS 10
223#if defined(CONFIG_BLACKFIN) || defined(CONFIG_H8300) || defined(CONFIG_XTENSA)
224# define MAX_HWIFS 1
225#else
226# define MAX_HWIFS 10
227#endif
228#endif
229
230#if !defined(MAX_HWIFS) || defined(CONFIG_EMBEDDED)
231#undef MAX_HWIFS
232#define MAX_HWIFS CONFIG_IDE_MAX_HWIFS
233#endif
234 223
235/* Currently only m68k, apus and m8xx need it */ 224/* Currently only m68k, apus and m8xx need it */
236#ifndef IDE_ARCH_ACK_INTR 225#ifndef IDE_ARCH_ACK_INTR
@@ -509,24 +498,33 @@ struct ide_tp_ops {
509 498
510extern const struct ide_tp_ops default_tp_ops; 499extern const struct ide_tp_ops default_tp_ops;
511 500
501/**
502 * struct ide_port_ops - IDE port operations
503 *
504 * @init_dev: host specific initialization of a device
505 * @set_pio_mode: routine to program host for PIO mode
506 * @set_dma_mode: routine to program host for DMA mode
507 * @selectproc: tweaks hardware to select drive
508 * @reset_poll: chipset polling based on hba specifics
509 * @pre_reset: chipset specific changes to default for device-hba resets
510 * @resetproc: routine to reset controller after a disk reset
511 * @maskproc: special host masking for drive selection
512 * @quirkproc: check host's drive quirk list
513 *
514 * @mdma_filter: filter MDMA modes
515 * @udma_filter: filter UDMA modes
516 *
517 * @cable_detect: detect cable type
518 */
512struct ide_port_ops { 519struct ide_port_ops {
513 /* host specific initialization of a device */
514 void (*init_dev)(ide_drive_t *); 520 void (*init_dev)(ide_drive_t *);
515 /* routine to program host for PIO mode */
516 void (*set_pio_mode)(ide_drive_t *, const u8); 521 void (*set_pio_mode)(ide_drive_t *, const u8);
517 /* routine to program host for DMA mode */
518 void (*set_dma_mode)(ide_drive_t *, const u8); 522 void (*set_dma_mode)(ide_drive_t *, const u8);
519 /* tweaks hardware to select drive */
520 void (*selectproc)(ide_drive_t *); 523 void (*selectproc)(ide_drive_t *);
521 /* chipset polling based on hba specifics */
522 int (*reset_poll)(ide_drive_t *); 524 int (*reset_poll)(ide_drive_t *);
523 /* chipset specific changes to default for device-hba resets */
524 void (*pre_reset)(ide_drive_t *); 525 void (*pre_reset)(ide_drive_t *);
525 /* routine to reset controller after a disk reset */
526 void (*resetproc)(ide_drive_t *); 526 void (*resetproc)(ide_drive_t *);
527 /* special host masking for drive selection */
528 void (*maskproc)(ide_drive_t *, int); 527 void (*maskproc)(ide_drive_t *, int);
529 /* check host's drive quirk list */
530 void (*quirkproc)(ide_drive_t *); 528 void (*quirkproc)(ide_drive_t *);
531 529
532 u8 (*mdma_filter)(ide_drive_t *); 530 u8 (*mdma_filter)(ide_drive_t *);
diff --git a/include/linux/ieee80211.h b/include/linux/ieee80211.h
index a1630ba0b87..7f4df7c7659 100644
--- a/include/linux/ieee80211.h
+++ b/include/linux/ieee80211.h
@@ -506,6 +506,19 @@ struct ieee80211_channel_sw_ie {
506 u8 count; 506 u8 count;
507} __attribute__ ((packed)); 507} __attribute__ ((packed));
508 508
509/**
510 * struct ieee80211_tim
511 *
512 * This structure refers to "Traffic Indication Map information element"
513 */
514struct ieee80211_tim_ie {
515 u8 dtim_count;
516 u8 dtim_period;
517 u8 bitmap_ctrl;
518 /* variable size: 1 - 251 bytes */
519 u8 virtual_map[0];
520} __attribute__ ((packed));
521
509struct ieee80211_mgmt { 522struct ieee80211_mgmt {
510 __le16 frame_control; 523 __le16 frame_control;
511 __le16 duration; 524 __le16 duration;
diff --git a/include/linux/ihex.h b/include/linux/ihex.h
index 2baace2788a..31d8629e75a 100644
--- a/include/linux/ihex.h
+++ b/include/linux/ihex.h
@@ -18,7 +18,7 @@ struct ihex_binrec {
18 __be32 addr; 18 __be32 addr;
19 __be16 len; 19 __be16 len;
20 uint8_t data[0]; 20 uint8_t data[0];
21} __attribute__((aligned(4))); 21} __attribute__((packed));
22 22
23/* Find the next record, taking into account the 4-byte alignment */ 23/* Find the next record, taking into account the 4-byte alignment */
24static inline const struct ihex_binrec * 24static inline const struct ihex_binrec *
diff --git a/include/linux/interrupt.h b/include/linux/interrupt.h
index 62aa4f895ab..58ff4e74b2f 100644
--- a/include/linux/interrupt.h
+++ b/include/linux/interrupt.h
@@ -223,35 +223,6 @@ static inline int disable_irq_wake(unsigned int irq)
223#define or_softirq_pending(x) (local_softirq_pending() |= (x)) 223#define or_softirq_pending(x) (local_softirq_pending() |= (x))
224#endif 224#endif
225 225
226/*
227 * Temporary defines for UP kernels, until all code gets fixed.
228 */
229#ifndef CONFIG_SMP
230static inline void __deprecated cli(void)
231{
232 local_irq_disable();
233}
234static inline void __deprecated sti(void)
235{
236 local_irq_enable();
237}
238static inline void __deprecated save_flags(unsigned long *x)
239{
240 local_save_flags(*x);
241}
242#define save_flags(x) save_flags(&x)
243static inline void __deprecated restore_flags(unsigned long x)
244{
245 local_irq_restore(x);
246}
247
248static inline void __deprecated save_and_cli(unsigned long *x)
249{
250 local_irq_save(*x);
251}
252#define save_and_cli(x) save_and_cli(&x)
253#endif /* CONFIG_SMP */
254
255/* Some architectures might implement lazy enabling/disabling of 226/* Some architectures might implement lazy enabling/disabling of
256 * interrupts. In some cases, such as stop_machine, we might want 227 * interrupts. In some cases, such as stop_machine, we might want
257 * to ensure that after a local_irq_disable(), interrupts have 228 * to ensure that after a local_irq_disable(), interrupts have
diff --git a/include/linux/ioport.h b/include/linux/ioport.h
index 2cd07cc2968..22d2115458c 100644
--- a/include/linux/ioport.h
+++ b/include/linux/ioport.h
@@ -118,6 +118,10 @@ extern int allocate_resource(struct resource *root, struct resource *new,
118int adjust_resource(struct resource *res, resource_size_t start, 118int adjust_resource(struct resource *res, resource_size_t start,
119 resource_size_t size); 119 resource_size_t size);
120resource_size_t resource_alignment(struct resource *res); 120resource_size_t resource_alignment(struct resource *res);
121static inline resource_size_t resource_size(struct resource *res)
122{
123 return res->end - res->start + 1;
124}
121 125
122/* Convenience shorthand with allocation */ 126/* Convenience shorthand with allocation */
123#define request_region(start,n,name) __request_region(&ioport_resource, (start), (n), (name)) 127#define request_region(start,n,name) __request_region(&ioport_resource, (start), (n), (name))
diff --git a/include/linux/ip_vs.h b/include/linux/ip_vs.h
new file mode 100644
index 00000000000..ec6eb49af2d
--- /dev/null
+++ b/include/linux/ip_vs.h
@@ -0,0 +1,245 @@
1/*
2 * IP Virtual Server
3 * data structure and functionality definitions
4 */
5
6#ifndef _IP_VS_H
7#define _IP_VS_H
8
9#include <linux/types.h> /* For __beXX types in userland */
10
11#define IP_VS_VERSION_CODE 0x010201
12#define NVERSION(version) \
13 (version >> 16) & 0xFF, \
14 (version >> 8) & 0xFF, \
15 version & 0xFF
16
17/*
18 * Virtual Service Flags
19 */
20#define IP_VS_SVC_F_PERSISTENT 0x0001 /* persistent port */
21#define IP_VS_SVC_F_HASHED 0x0002 /* hashed entry */
22
23/*
24 * Destination Server Flags
25 */
26#define IP_VS_DEST_F_AVAILABLE 0x0001 /* server is available */
27#define IP_VS_DEST_F_OVERLOAD 0x0002 /* server is overloaded */
28
29/*
30 * IPVS sync daemon states
31 */
32#define IP_VS_STATE_NONE 0x0000 /* daemon is stopped */
33#define IP_VS_STATE_MASTER 0x0001 /* started as master */
34#define IP_VS_STATE_BACKUP 0x0002 /* started as backup */
35
36/*
37 * IPVS socket options
38 */
39#define IP_VS_BASE_CTL (64+1024+64) /* base */
40
41#define IP_VS_SO_SET_NONE IP_VS_BASE_CTL /* just peek */
42#define IP_VS_SO_SET_INSERT (IP_VS_BASE_CTL+1)
43#define IP_VS_SO_SET_ADD (IP_VS_BASE_CTL+2)
44#define IP_VS_SO_SET_EDIT (IP_VS_BASE_CTL+3)
45#define IP_VS_SO_SET_DEL (IP_VS_BASE_CTL+4)
46#define IP_VS_SO_SET_FLUSH (IP_VS_BASE_CTL+5)
47#define IP_VS_SO_SET_LIST (IP_VS_BASE_CTL+6)
48#define IP_VS_SO_SET_ADDDEST (IP_VS_BASE_CTL+7)
49#define IP_VS_SO_SET_DELDEST (IP_VS_BASE_CTL+8)
50#define IP_VS_SO_SET_EDITDEST (IP_VS_BASE_CTL+9)
51#define IP_VS_SO_SET_TIMEOUT (IP_VS_BASE_CTL+10)
52#define IP_VS_SO_SET_STARTDAEMON (IP_VS_BASE_CTL+11)
53#define IP_VS_SO_SET_STOPDAEMON (IP_VS_BASE_CTL+12)
54#define IP_VS_SO_SET_RESTORE (IP_VS_BASE_CTL+13)
55#define IP_VS_SO_SET_SAVE (IP_VS_BASE_CTL+14)
56#define IP_VS_SO_SET_ZERO (IP_VS_BASE_CTL+15)
57#define IP_VS_SO_SET_MAX IP_VS_SO_SET_ZERO
58
59#define IP_VS_SO_GET_VERSION IP_VS_BASE_CTL
60#define IP_VS_SO_GET_INFO (IP_VS_BASE_CTL+1)
61#define IP_VS_SO_GET_SERVICES (IP_VS_BASE_CTL+2)
62#define IP_VS_SO_GET_SERVICE (IP_VS_BASE_CTL+3)
63#define IP_VS_SO_GET_DESTS (IP_VS_BASE_CTL+4)
64#define IP_VS_SO_GET_DEST (IP_VS_BASE_CTL+5) /* not used now */
65#define IP_VS_SO_GET_TIMEOUT (IP_VS_BASE_CTL+6)
66#define IP_VS_SO_GET_DAEMON (IP_VS_BASE_CTL+7)
67#define IP_VS_SO_GET_MAX IP_VS_SO_GET_DAEMON
68
69
70/*
71 * IPVS Connection Flags
72 */
73#define IP_VS_CONN_F_FWD_MASK 0x0007 /* mask for the fwd methods */
74#define IP_VS_CONN_F_MASQ 0x0000 /* masquerading/NAT */
75#define IP_VS_CONN_F_LOCALNODE 0x0001 /* local node */
76#define IP_VS_CONN_F_TUNNEL 0x0002 /* tunneling */
77#define IP_VS_CONN_F_DROUTE 0x0003 /* direct routing */
78#define IP_VS_CONN_F_BYPASS 0x0004 /* cache bypass */
79#define IP_VS_CONN_F_SYNC 0x0020 /* entry created by sync */
80#define IP_VS_CONN_F_HASHED 0x0040 /* hashed entry */
81#define IP_VS_CONN_F_NOOUTPUT 0x0080 /* no output packets */
82#define IP_VS_CONN_F_INACTIVE 0x0100 /* not established */
83#define IP_VS_CONN_F_OUT_SEQ 0x0200 /* must do output seq adjust */
84#define IP_VS_CONN_F_IN_SEQ 0x0400 /* must do input seq adjust */
85#define IP_VS_CONN_F_SEQ_MASK 0x0600 /* in/out sequence mask */
86#define IP_VS_CONN_F_NO_CPORT 0x0800 /* no client port set yet */
87#define IP_VS_CONN_F_TEMPLATE 0x1000 /* template, not connection */
88
89#define IP_VS_SCHEDNAME_MAXLEN 16
90#define IP_VS_IFNAME_MAXLEN 16
91
92
93/*
94 * The struct ip_vs_service_user and struct ip_vs_dest_user are
95 * used to set IPVS rules through setsockopt.
96 */
97struct ip_vs_service_user {
98 /* virtual service addresses */
99 u_int16_t protocol;
100 __be32 addr; /* virtual ip address */
101 __be16 port;
102 u_int32_t fwmark; /* firwall mark of service */
103
104 /* virtual service options */
105 char sched_name[IP_VS_SCHEDNAME_MAXLEN];
106 unsigned flags; /* virtual service flags */
107 unsigned timeout; /* persistent timeout in sec */
108 __be32 netmask; /* persistent netmask */
109};
110
111
112struct ip_vs_dest_user {
113 /* destination server address */
114 __be32 addr;
115 __be16 port;
116
117 /* real server options */
118 unsigned conn_flags; /* connection flags */
119 int weight; /* destination weight */
120
121 /* thresholds for active connections */
122 u_int32_t u_threshold; /* upper threshold */
123 u_int32_t l_threshold; /* lower threshold */
124};
125
126
127/*
128 * IPVS statistics object (for user space)
129 */
130struct ip_vs_stats_user
131{
132 __u32 conns; /* connections scheduled */
133 __u32 inpkts; /* incoming packets */
134 __u32 outpkts; /* outgoing packets */
135 __u64 inbytes; /* incoming bytes */
136 __u64 outbytes; /* outgoing bytes */
137
138 __u32 cps; /* current connection rate */
139 __u32 inpps; /* current in packet rate */
140 __u32 outpps; /* current out packet rate */
141 __u32 inbps; /* current in byte rate */
142 __u32 outbps; /* current out byte rate */
143};
144
145
146/* The argument to IP_VS_SO_GET_INFO */
147struct ip_vs_getinfo {
148 /* version number */
149 unsigned int version;
150
151 /* size of connection hash table */
152 unsigned int size;
153
154 /* number of virtual services */
155 unsigned int num_services;
156};
157
158
159/* The argument to IP_VS_SO_GET_SERVICE */
160struct ip_vs_service_entry {
161 /* which service: user fills in these */
162 u_int16_t protocol;
163 __be32 addr; /* virtual address */
164 __be16 port;
165 u_int32_t fwmark; /* firwall mark of service */
166
167 /* service options */
168 char sched_name[IP_VS_SCHEDNAME_MAXLEN];
169 unsigned flags; /* virtual service flags */
170 unsigned timeout; /* persistent timeout */
171 __be32 netmask; /* persistent netmask */
172
173 /* number of real servers */
174 unsigned int num_dests;
175
176 /* statistics */
177 struct ip_vs_stats_user stats;
178};
179
180
181struct ip_vs_dest_entry {
182 __be32 addr; /* destination address */
183 __be16 port;
184 unsigned conn_flags; /* connection flags */
185 int weight; /* destination weight */
186
187 u_int32_t u_threshold; /* upper threshold */
188 u_int32_t l_threshold; /* lower threshold */
189
190 u_int32_t activeconns; /* active connections */
191 u_int32_t inactconns; /* inactive connections */
192 u_int32_t persistconns; /* persistent connections */
193
194 /* statistics */
195 struct ip_vs_stats_user stats;
196};
197
198
199/* The argument to IP_VS_SO_GET_DESTS */
200struct ip_vs_get_dests {
201 /* which service: user fills in these */
202 u_int16_t protocol;
203 __be32 addr; /* virtual address */
204 __be16 port;
205 u_int32_t fwmark; /* firwall mark of service */
206
207 /* number of real servers */
208 unsigned int num_dests;
209
210 /* the real servers */
211 struct ip_vs_dest_entry entrytable[0];
212};
213
214
215/* The argument to IP_VS_SO_GET_SERVICES */
216struct ip_vs_get_services {
217 /* number of virtual services */
218 unsigned int num_services;
219
220 /* service table */
221 struct ip_vs_service_entry entrytable[0];
222};
223
224
225/* The argument to IP_VS_SO_GET_TIMEOUT */
226struct ip_vs_timeout_user {
227 int tcp_timeout;
228 int tcp_fin_timeout;
229 int udp_timeout;
230};
231
232
233/* The argument to IP_VS_SO_GET_DAEMON */
234struct ip_vs_daemon_user {
235 /* sync daemon state (master/backup) */
236 int state;
237
238 /* multicast interface name */
239 char mcast_ifn[IP_VS_IFNAME_MAXLEN];
240
241 /* SyncID we belong to */
242 int syncid;
243};
244
245#endif /* _IP_VS_H */
diff --git a/include/linux/kallsyms.h b/include/linux/kallsyms.h
index 57aefa160a9..b9614488744 100644
--- a/include/linux/kallsyms.h
+++ b/include/linux/kallsyms.h
@@ -108,8 +108,7 @@ static inline void print_fn_descriptor_symbol(const char *fmt, void *addr)
108 108
109static inline void print_ip_sym(unsigned long ip) 109static inline void print_ip_sym(unsigned long ip)
110{ 110{
111 printk("[<%p>]", (void *) ip); 111 printk("[<%p>] %pS\n", (void *) ip, (void *) ip);
112 print_symbol(" %s\n", ip);
113} 112}
114 113
115#endif /*_LINUX_KALLSYMS_H*/ 114#endif /*_LINUX_KALLSYMS_H*/
diff --git a/include/linux/kernel.h b/include/linux/kernel.h
index fdbbf72ca2e..aaa998f65c7 100644
--- a/include/linux/kernel.h
+++ b/include/linux/kernel.h
@@ -75,6 +75,12 @@ extern const char linux_proc_banner[];
75 */ 75 */
76#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16)) 76#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))
77 77
78/**
79 * lower_32_bits - return bits 0-31 of a number
80 * @n: the number we're accessing
81 */
82#define lower_32_bits(n) ((u32)(n))
83
78#define KERN_EMERG "<0>" /* system is unusable */ 84#define KERN_EMERG "<0>" /* system is unusable */
79#define KERN_ALERT "<1>" /* action must be taken immediately */ 85#define KERN_ALERT "<1>" /* action must be taken immediately */
80#define KERN_CRIT "<2>" /* critical conditions */ 86#define KERN_CRIT "<2>" /* critical conditions */
diff --git a/include/linux/kexec.h b/include/linux/kexec.h
index 82f88a8a827..32110cede64 100644
--- a/include/linux/kexec.h
+++ b/include/linux/kexec.h
@@ -130,8 +130,8 @@ void vmcoreinfo_append_str(const char *fmt, ...)
130 __attribute__ ((format (printf, 1, 2))); 130 __attribute__ ((format (printf, 1, 2)));
131unsigned long paddr_vmcoreinfo_note(void); 131unsigned long paddr_vmcoreinfo_note(void);
132 132
133#define VMCOREINFO_OSRELEASE(name) \ 133#define VMCOREINFO_OSRELEASE(value) \
134 vmcoreinfo_append_str("OSRELEASE=%s\n", #name) 134 vmcoreinfo_append_str("OSRELEASE=%s\n", value)
135#define VMCOREINFO_PAGESIZE(value) \ 135#define VMCOREINFO_PAGESIZE(value) \
136 vmcoreinfo_append_str("PAGESIZE=%ld\n", value) 136 vmcoreinfo_append_str("PAGESIZE=%ld\n", value)
137#define VMCOREINFO_SYMBOL(name) \ 137#define VMCOREINFO_SYMBOL(name) \
diff --git a/include/linux/kvm.h b/include/linux/kvm.h
index 0ea064cbfbc..69511f74f91 100644
--- a/include/linux/kvm.h
+++ b/include/linux/kvm.h
@@ -371,6 +371,7 @@ struct kvm_trace_rec {
371#define KVM_CAP_PV_MMU 13 371#define KVM_CAP_PV_MMU 13
372#define KVM_CAP_MP_STATE 14 372#define KVM_CAP_MP_STATE 14
373#define KVM_CAP_COALESCED_MMIO 15 373#define KVM_CAP_COALESCED_MMIO 15
374#define KVM_CAP_SYNC_MMU 16 /* Changes to host mmap are reflected in guest */
374 375
375/* 376/*
376 * ioctls for VM fds 377 * ioctls for VM fds
diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h
index 07d68a8ae8e..8525afc5310 100644
--- a/include/linux/kvm_host.h
+++ b/include/linux/kvm_host.h
@@ -121,6 +121,12 @@ struct kvm {
121 struct kvm_coalesced_mmio_dev *coalesced_mmio_dev; 121 struct kvm_coalesced_mmio_dev *coalesced_mmio_dev;
122 struct kvm_coalesced_mmio_ring *coalesced_mmio_ring; 122 struct kvm_coalesced_mmio_ring *coalesced_mmio_ring;
123#endif 123#endif
124
125#ifdef KVM_ARCH_WANT_MMU_NOTIFIER
126 struct mmu_notifier mmu_notifier;
127 unsigned long mmu_notifier_seq;
128 long mmu_notifier_count;
129#endif
124}; 130};
125 131
126/* The guest did something we don't support. */ 132/* The guest did something we don't support. */
@@ -332,4 +338,22 @@ int kvm_trace_ioctl(unsigned int ioctl, unsigned long arg)
332#define kvm_trace_cleanup() ((void)0) 338#define kvm_trace_cleanup() ((void)0)
333#endif 339#endif
334 340
341#ifdef KVM_ARCH_WANT_MMU_NOTIFIER
342static inline int mmu_notifier_retry(struct kvm_vcpu *vcpu, unsigned long mmu_seq)
343{
344 if (unlikely(vcpu->kvm->mmu_notifier_count))
345 return 1;
346 /*
347 * Both reads happen under the mmu_lock and both values are
348 * modified under mmu_lock, so there's no need of smb_rmb()
349 * here in between, otherwise mmu_notifier_count should be
350 * read before mmu_notifier_seq, see
351 * mmu_notifier_invalidate_range_end write side.
352 */
353 if (vcpu->kvm->mmu_notifier_seq != mmu_seq)
354 return 1;
355 return 0;
356}
357#endif
358
335#endif 359#endif
diff --git a/include/linux/libata.h b/include/linux/libata.h
index 5b247b8a6b3..06b80337303 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -60,9 +60,9 @@
60 60
61/* note: prints function name for you */ 61/* note: prints function name for you */
62#ifdef ATA_DEBUG 62#ifdef ATA_DEBUG
63#define DPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args) 63#define DPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
64#ifdef ATA_VERBOSE_DEBUG 64#ifdef ATA_VERBOSE_DEBUG
65#define VPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args) 65#define VPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
66#else 66#else
67#define VPRINTK(fmt, args...) 67#define VPRINTK(fmt, args...)
68#endif /* ATA_VERBOSE_DEBUG */ 68#endif /* ATA_VERBOSE_DEBUG */
@@ -71,7 +71,7 @@
71#define VPRINTK(fmt, args...) 71#define VPRINTK(fmt, args...)
72#endif /* ATA_DEBUG */ 72#endif /* ATA_DEBUG */
73 73
74#define BPRINTK(fmt, args...) if (ap->flags & ATA_FLAG_DEBUGMSG) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args) 74#define BPRINTK(fmt, args...) if (ap->flags & ATA_FLAG_DEBUGMSG) printk(KERN_ERR "%s: " fmt, __func__, ## args)
75 75
76/* NEW: debug levels */ 76/* NEW: debug levels */
77#define HAVE_LIBATA_MSG 1 77#define HAVE_LIBATA_MSG 1
@@ -750,6 +750,7 @@ struct ata_port_operations {
750 void (*set_piomode)(struct ata_port *ap, struct ata_device *dev); 750 void (*set_piomode)(struct ata_port *ap, struct ata_device *dev);
751 void (*set_dmamode)(struct ata_port *ap, struct ata_device *dev); 751 void (*set_dmamode)(struct ata_port *ap, struct ata_device *dev);
752 int (*set_mode)(struct ata_link *link, struct ata_device **r_failed_dev); 752 int (*set_mode)(struct ata_link *link, struct ata_device **r_failed_dev);
753 unsigned int (*read_id)(struct ata_device *dev, struct ata_taskfile *tf, u16 *id);
753 754
754 void (*dev_config)(struct ata_device *dev); 755 void (*dev_config)(struct ata_device *dev);
755 756
@@ -951,6 +952,8 @@ extern void ata_id_string(const u16 *id, unsigned char *s,
951 unsigned int ofs, unsigned int len); 952 unsigned int ofs, unsigned int len);
952extern void ata_id_c_string(const u16 *id, unsigned char *s, 953extern void ata_id_c_string(const u16 *id, unsigned char *s,
953 unsigned int ofs, unsigned int len); 954 unsigned int ofs, unsigned int len);
955extern unsigned int ata_do_dev_read_id(struct ata_device *dev,
956 struct ata_taskfile *tf, u16 *id);
954extern void ata_qc_complete(struct ata_queued_cmd *qc); 957extern void ata_qc_complete(struct ata_queued_cmd *qc);
955extern int ata_qc_complete_multiple(struct ata_port *ap, u32 qc_active); 958extern int ata_qc_complete_multiple(struct ata_port *ap, u32 qc_active);
956extern void ata_scsi_simulate(struct ata_device *dev, struct scsi_cmnd *cmd, 959extern void ata_scsi_simulate(struct ata_device *dev, struct scsi_cmnd *cmd,
diff --git a/include/linux/mISDNif.h b/include/linux/mISDNif.h
index 5c948f33781..8f2d60da04e 100644
--- a/include/linux/mISDNif.h
+++ b/include/linux/mISDNif.h
@@ -37,7 +37,7 @@
37 */ 37 */
38#define MISDN_MAJOR_VERSION 1 38#define MISDN_MAJOR_VERSION 1
39#define MISDN_MINOR_VERSION 0 39#define MISDN_MINOR_VERSION 0
40#define MISDN_RELEASE 18 40#define MISDN_RELEASE 19
41 41
42/* primitives for information exchange 42/* primitives for information exchange
43 * generell format 43 * generell format
@@ -242,7 +242,8 @@ struct mISDNhead {
242#define TEI_SAPI 63 242#define TEI_SAPI 63
243#define CTRL_SAPI 0 243#define CTRL_SAPI 0
244 244
245#define MISDN_CHMAP_SIZE 4 245#define MISDN_MAX_CHANNEL 127
246#define MISDN_CHMAP_SIZE ((MISDN_MAX_CHANNEL + 1) >> 3)
246 247
247#define SOL_MISDN 0 248#define SOL_MISDN 0
248 249
@@ -275,11 +276,32 @@ struct mISDN_devinfo {
275 u_int Dprotocols; 276 u_int Dprotocols;
276 u_int Bprotocols; 277 u_int Bprotocols;
277 u_int protocol; 278 u_int protocol;
278 u_long channelmap[MISDN_CHMAP_SIZE]; 279 u_char channelmap[MISDN_CHMAP_SIZE];
279 u_int nrbchan; 280 u_int nrbchan;
280 char name[MISDN_MAX_IDLEN]; 281 char name[MISDN_MAX_IDLEN];
281}; 282};
282 283
284static inline int
285test_channelmap(u_int nr, u_char *map)
286{
287 if (nr <= MISDN_MAX_CHANNEL)
288 return map[nr >> 3] & (1 << (nr & 7));
289 else
290 return 0;
291}
292
293static inline void
294set_channelmap(u_int nr, u_char *map)
295{
296 map[nr >> 3] |= (1 << (nr & 7));
297}
298
299static inline void
300clear_channelmap(u_int nr, u_char *map)
301{
302 map[nr >> 3] &= ~(1 << (nr & 7));
303}
304
283/* CONTROL_CHANNEL parameters */ 305/* CONTROL_CHANNEL parameters */
284#define MISDN_CTRL_GETOP 0x0000 306#define MISDN_CTRL_GETOP 0x0000
285#define MISDN_CTRL_LOOP 0x0001 307#define MISDN_CTRL_LOOP 0x0001
@@ -405,7 +427,7 @@ struct mISDNdevice {
405 u_int Dprotocols; 427 u_int Dprotocols;
406 u_int Bprotocols; 428 u_int Bprotocols;
407 u_int nrbchan; 429 u_int nrbchan;
408 u_long channelmap[MISDN_CHMAP_SIZE]; 430 u_char channelmap[MISDN_CHMAP_SIZE];
409 struct list_head bchannels; 431 struct list_head bchannels;
410 struct mISDNchannel *teimgr; 432 struct mISDNchannel *teimgr;
411 struct device dev; 433 struct device dev;
@@ -430,7 +452,7 @@ struct mISDNstack {
430#endif 452#endif
431}; 453};
432 454
433/* global alloc/queue dunctions */ 455/* global alloc/queue functions */
434 456
435static inline struct sk_buff * 457static inline struct sk_buff *
436mI_alloc_skb(unsigned int len, gfp_t gfp_mask) 458mI_alloc_skb(unsigned int len, gfp_t gfp_mask)
diff --git a/include/linux/maple.h b/include/linux/maple.h
index d31e36ebb43..c23d3f51ba4 100644
--- a/include/linux/maple.h
+++ b/include/linux/maple.h
@@ -2,6 +2,7 @@
2#define __LINUX_MAPLE_H 2#define __LINUX_MAPLE_H
3 3
4#include <linux/device.h> 4#include <linux/device.h>
5#include <mach/maple.h>
5 6
6extern struct bus_type maple_bus_type; 7extern struct bus_type maple_bus_type;
7 8
@@ -33,6 +34,7 @@ struct mapleq {
33 void *sendbuf, *recvbuf, *recvbufdcsp; 34 void *sendbuf, *recvbuf, *recvbufdcsp;
34 unsigned char length; 35 unsigned char length;
35 enum maple_code command; 36 enum maple_code command;
37 struct mutex mutex;
36}; 38};
37 39
38struct maple_devinfo { 40struct maple_devinfo {
@@ -49,7 +51,6 @@ struct maple_devinfo {
49struct maple_device { 51struct maple_device {
50 struct maple_driver *driver; 52 struct maple_driver *driver;
51 struct mapleq *mq; 53 struct mapleq *mq;
52 void *private_data;
53 void (*callback) (struct mapleq * mq); 54 void (*callback) (struct mapleq * mq);
54 unsigned long when, interval, function; 55 unsigned long when, interval, function;
55 struct maple_devinfo devinfo; 56 struct maple_devinfo devinfo;
@@ -61,8 +62,6 @@ struct maple_device {
61 62
62struct maple_driver { 63struct maple_driver {
63 unsigned long function; 64 unsigned long function;
64 int (*connect) (struct maple_device * dev);
65 void (*disconnect) (struct maple_device * dev);
66 struct device_driver drv; 65 struct device_driver drv;
67}; 66};
68 67
@@ -70,10 +69,17 @@ void maple_getcond_callback(struct maple_device *dev,
70 void (*callback) (struct mapleq * mq), 69 void (*callback) (struct mapleq * mq),
71 unsigned long interval, 70 unsigned long interval,
72 unsigned long function); 71 unsigned long function);
73int maple_driver_register(struct device_driver *drv); 72int maple_driver_register(struct maple_driver *);
74void maple_add_packet(struct mapleq *mq); 73void maple_driver_unregister(struct maple_driver *);
74
75int maple_add_packet_sleeps(struct maple_device *mdev, u32 function,
76 u32 command, u32 length, void *data);
77void maple_clear_dev(struct maple_device *mdev);
75 78
76#define to_maple_dev(n) container_of(n, struct maple_device, dev) 79#define to_maple_dev(n) container_of(n, struct maple_device, dev)
77#define to_maple_driver(n) container_of(n, struct maple_driver, drv) 80#define to_maple_driver(n) container_of(n, struct maple_driver, drv)
78 81
82#define maple_get_drvdata(d) dev_get_drvdata(&(d)->dev)
83#define maple_set_drvdata(d,p) dev_set_drvdata(&(d)->dev, (p))
84
79#endif /* __LINUX_MAPLE_H */ 85#endif /* __LINUX_MAPLE_H */
diff --git a/include/linux/mfd/core.h b/include/linux/mfd/core.h
index bb3dd054592..49ef857cdb2 100644
--- a/include/linux/mfd/core.h
+++ b/include/linux/mfd/core.h
@@ -1,5 +1,3 @@
1#ifndef MFD_CORE_H
2#define MFD_CORE_H
3/* 1/*
4 * drivers/mfd/mfd-core.h 2 * drivers/mfd/mfd-core.h
5 * 3 *
@@ -13,6 +11,9 @@
13 * 11 *
14 */ 12 */
15 13
14#ifndef MFD_CORE_H
15#define MFD_CORE_H
16
16#include <linux/platform_device.h> 17#include <linux/platform_device.h>
17 18
18/* 19/*
@@ -28,7 +29,13 @@ struct mfd_cell {
28 int (*suspend)(struct platform_device *dev); 29 int (*suspend)(struct platform_device *dev);
29 int (*resume)(struct platform_device *dev); 30 int (*resume)(struct platform_device *dev);
30 31
31 void *driver_data; /* driver-specific data */ 32 /* driver-specific data for MFD-aware "cell" drivers */
33 void *driver_data;
34
35 /* platform_data can be used to either pass data to "generic"
36 driver or as a hook to mfd_cell for the "cell" drivers */
37 void *platform_data;
38 size_t data_size;
32 39
33 /* 40 /*
34 * This resources can be specified relatievly to the parent device. 41 * This resources can be specified relatievly to the parent device.
@@ -38,18 +45,11 @@ struct mfd_cell {
38 const struct resource *resources; 45 const struct resource *resources;
39}; 46};
40 47
41static inline struct mfd_cell * 48extern int mfd_add_devices(struct device *parent, int id,
42mfd_get_cell(struct platform_device *pdev) 49 const struct mfd_cell *cells, int n_devs,
43{ 50 struct resource *mem_base,
44 return (struct mfd_cell *)pdev->dev.platform_data; 51 int irq_base);
45}
46
47extern int mfd_add_devices(
48 struct platform_device *parent,
49 const struct mfd_cell *cells, int n_devs,
50 struct resource *mem_base,
51 int irq_base);
52 52
53extern void mfd_remove_devices(struct platform_device *parent); 53extern void mfd_remove_devices(struct device *parent);
54 54
55#endif 55#endif
diff --git a/include/linux/mm.h b/include/linux/mm.h
index 6e695eaab4c..335288bff1b 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -744,6 +744,8 @@ struct zap_details {
744struct page *vm_normal_page(struct vm_area_struct *vma, unsigned long addr, 744struct page *vm_normal_page(struct vm_area_struct *vma, unsigned long addr,
745 pte_t pte); 745 pte_t pte);
746 746
747int zap_vma_ptes(struct vm_area_struct *vma, unsigned long address,
748 unsigned long size);
747unsigned long zap_page_range(struct vm_area_struct *vma, unsigned long address, 749unsigned long zap_page_range(struct vm_area_struct *vma, unsigned long address,
748 unsigned long size, struct zap_details *); 750 unsigned long size, struct zap_details *);
749unsigned long unmap_vmas(struct mmu_gather **tlb, 751unsigned long unmap_vmas(struct mmu_gather **tlb,
@@ -1041,7 +1043,6 @@ extern unsigned long absent_pages_in_range(unsigned long start_pfn,
1041extern void get_pfn_range_for_nid(unsigned int nid, 1043extern void get_pfn_range_for_nid(unsigned int nid,
1042 unsigned long *start_pfn, unsigned long *end_pfn); 1044 unsigned long *start_pfn, unsigned long *end_pfn);
1043extern unsigned long find_min_pfn_with_active_regions(void); 1045extern unsigned long find_min_pfn_with_active_regions(void);
1044extern unsigned long find_max_pfn_with_active_regions(void);
1045extern void free_bootmem_with_active_regions(int nid, 1046extern void free_bootmem_with_active_regions(int nid,
1046 unsigned long max_low_pfn); 1047 unsigned long max_low_pfn);
1047typedef int (*work_fn_t)(unsigned long, unsigned long, void *); 1048typedef int (*work_fn_t)(unsigned long, unsigned long, void *);
@@ -1104,6 +1105,9 @@ extern struct vm_area_struct *copy_vma(struct vm_area_struct **,
1104 unsigned long addr, unsigned long len, pgoff_t pgoff); 1105 unsigned long addr, unsigned long len, pgoff_t pgoff);
1105extern void exit_mmap(struct mm_struct *); 1106extern void exit_mmap(struct mm_struct *);
1106 1107
1108extern int mm_take_all_locks(struct mm_struct *mm);
1109extern void mm_drop_all_locks(struct mm_struct *mm);
1110
1107#ifdef CONFIG_PROC_FS 1111#ifdef CONFIG_PROC_FS
1108/* From fs/proc/base.c. callers must _not_ hold the mm's exe_file_lock */ 1112/* From fs/proc/base.c. callers must _not_ hold the mm's exe_file_lock */
1109extern void added_exe_file_vma(struct mm_struct *mm); 1113extern void added_exe_file_vma(struct mm_struct *mm);
diff --git a/include/linux/mm_types.h b/include/linux/mm_types.h
index 746f975b58e..386edbe2cb4 100644
--- a/include/linux/mm_types.h
+++ b/include/linux/mm_types.h
@@ -10,6 +10,7 @@
10#include <linux/rbtree.h> 10#include <linux/rbtree.h>
11#include <linux/rwsem.h> 11#include <linux/rwsem.h>
12#include <linux/completion.h> 12#include <linux/completion.h>
13#include <linux/cpumask.h>
13#include <asm/page.h> 14#include <asm/page.h>
14#include <asm/mmu.h> 15#include <asm/mmu.h>
15 16
@@ -253,6 +254,9 @@ struct mm_struct {
253 struct file *exe_file; 254 struct file *exe_file;
254 unsigned long num_exe_file_vmas; 255 unsigned long num_exe_file_vmas;
255#endif 256#endif
257#ifdef CONFIG_MMU_NOTIFIER
258 struct mmu_notifier_mm *mmu_notifier_mm;
259#endif
256}; 260};
257 261
258#endif /* _LINUX_MM_TYPES_H */ 262#endif /* _LINUX_MM_TYPES_H */
diff --git a/include/linux/mmu_notifier.h b/include/linux/mmu_notifier.h
new file mode 100644
index 00000000000..b77486d152c
--- /dev/null
+++ b/include/linux/mmu_notifier.h
@@ -0,0 +1,279 @@
1#ifndef _LINUX_MMU_NOTIFIER_H
2#define _LINUX_MMU_NOTIFIER_H
3
4#include <linux/list.h>
5#include <linux/spinlock.h>
6#include <linux/mm_types.h>
7
8struct mmu_notifier;
9struct mmu_notifier_ops;
10
11#ifdef CONFIG_MMU_NOTIFIER
12
13/*
14 * The mmu notifier_mm structure is allocated and installed in
15 * mm->mmu_notifier_mm inside the mm_take_all_locks() protected
16 * critical section and it's released only when mm_count reaches zero
17 * in mmdrop().
18 */
19struct mmu_notifier_mm {
20 /* all mmu notifiers registerd in this mm are queued in this list */
21 struct hlist_head list;
22 /* to serialize the list modifications and hlist_unhashed */
23 spinlock_t lock;
24};
25
26struct mmu_notifier_ops {
27 /*
28 * Called either by mmu_notifier_unregister or when the mm is
29 * being destroyed by exit_mmap, always before all pages are
30 * freed. This can run concurrently with other mmu notifier
31 * methods (the ones invoked outside the mm context) and it
32 * should tear down all secondary mmu mappings and freeze the
33 * secondary mmu. If this method isn't implemented you've to
34 * be sure that nothing could possibly write to the pages
35 * through the secondary mmu by the time the last thread with
36 * tsk->mm == mm exits.
37 *
38 * As side note: the pages freed after ->release returns could
39 * be immediately reallocated by the gart at an alias physical
40 * address with a different cache model, so if ->release isn't
41 * implemented because all _software_ driven memory accesses
42 * through the secondary mmu are terminated by the time the
43 * last thread of this mm quits, you've also to be sure that
44 * speculative _hardware_ operations can't allocate dirty
45 * cachelines in the cpu that could not be snooped and made
46 * coherent with the other read and write operations happening
47 * through the gart alias address, so leading to memory
48 * corruption.
49 */
50 void (*release)(struct mmu_notifier *mn,
51 struct mm_struct *mm);
52
53 /*
54 * clear_flush_young is called after the VM is
55 * test-and-clearing the young/accessed bitflag in the
56 * pte. This way the VM will provide proper aging to the
57 * accesses to the page through the secondary MMUs and not
58 * only to the ones through the Linux pte.
59 */
60 int (*clear_flush_young)(struct mmu_notifier *mn,
61 struct mm_struct *mm,
62 unsigned long address);
63
64 /*
65 * Before this is invoked any secondary MMU is still ok to
66 * read/write to the page previously pointed to by the Linux
67 * pte because the page hasn't been freed yet and it won't be
68 * freed until this returns. If required set_page_dirty has to
69 * be called internally to this method.
70 */
71 void (*invalidate_page)(struct mmu_notifier *mn,
72 struct mm_struct *mm,
73 unsigned long address);
74
75 /*
76 * invalidate_range_start() and invalidate_range_end() must be
77 * paired and are called only when the mmap_sem and/or the
78 * locks protecting the reverse maps are held. The subsystem
79 * must guarantee that no additional references are taken to
80 * the pages in the range established between the call to
81 * invalidate_range_start() and the matching call to
82 * invalidate_range_end().
83 *
84 * Invalidation of multiple concurrent ranges may be
85 * optionally permitted by the driver. Either way the
86 * establishment of sptes is forbidden in the range passed to
87 * invalidate_range_begin/end for the whole duration of the
88 * invalidate_range_begin/end critical section.
89 *
90 * invalidate_range_start() is called when all pages in the
91 * range are still mapped and have at least a refcount of one.
92 *
93 * invalidate_range_end() is called when all pages in the
94 * range have been unmapped and the pages have been freed by
95 * the VM.
96 *
97 * The VM will remove the page table entries and potentially
98 * the page between invalidate_range_start() and
99 * invalidate_range_end(). If the page must not be freed
100 * because of pending I/O or other circumstances then the
101 * invalidate_range_start() callback (or the initial mapping
102 * by the driver) must make sure that the refcount is kept
103 * elevated.
104 *
105 * If the driver increases the refcount when the pages are
106 * initially mapped into an address space then either
107 * invalidate_range_start() or invalidate_range_end() may
108 * decrease the refcount. If the refcount is decreased on
109 * invalidate_range_start() then the VM can free pages as page
110 * table entries are removed. If the refcount is only
111 * droppped on invalidate_range_end() then the driver itself
112 * will drop the last refcount but it must take care to flush
113 * any secondary tlb before doing the final free on the
114 * page. Pages will no longer be referenced by the linux
115 * address space but may still be referenced by sptes until
116 * the last refcount is dropped.
117 */
118 void (*invalidate_range_start)(struct mmu_notifier *mn,
119 struct mm_struct *mm,
120 unsigned long start, unsigned long end);
121 void (*invalidate_range_end)(struct mmu_notifier *mn,
122 struct mm_struct *mm,
123 unsigned long start, unsigned long end);
124};
125
126/*
127 * The notifier chains are protected by mmap_sem and/or the reverse map
128 * semaphores. Notifier chains are only changed when all reverse maps and
129 * the mmap_sem locks are taken.
130 *
131 * Therefore notifier chains can only be traversed when either
132 *
133 * 1. mmap_sem is held.
134 * 2. One of the reverse map locks is held (i_mmap_lock or anon_vma->lock).
135 * 3. No other concurrent thread can access the list (release)
136 */
137struct mmu_notifier {
138 struct hlist_node hlist;
139 const struct mmu_notifier_ops *ops;
140};
141
142static inline int mm_has_notifiers(struct mm_struct *mm)
143{
144 return unlikely(mm->mmu_notifier_mm);
145}
146
147extern int mmu_notifier_register(struct mmu_notifier *mn,
148 struct mm_struct *mm);
149extern int __mmu_notifier_register(struct mmu_notifier *mn,
150 struct mm_struct *mm);
151extern void mmu_notifier_unregister(struct mmu_notifier *mn,
152 struct mm_struct *mm);
153extern void __mmu_notifier_mm_destroy(struct mm_struct *mm);
154extern void __mmu_notifier_release(struct mm_struct *mm);
155extern int __mmu_notifier_clear_flush_young(struct mm_struct *mm,
156 unsigned long address);
157extern void __mmu_notifier_invalidate_page(struct mm_struct *mm,
158 unsigned long address);
159extern void __mmu_notifier_invalidate_range_start(struct mm_struct *mm,
160 unsigned long start, unsigned long end);
161extern void __mmu_notifier_invalidate_range_end(struct mm_struct *mm,
162 unsigned long start, unsigned long end);
163
164static inline void mmu_notifier_release(struct mm_struct *mm)
165{
166 if (mm_has_notifiers(mm))
167 __mmu_notifier_release(mm);
168}
169
170static inline int mmu_notifier_clear_flush_young(struct mm_struct *mm,
171 unsigned long address)
172{
173 if (mm_has_notifiers(mm))
174 return __mmu_notifier_clear_flush_young(mm, address);
175 return 0;
176}
177
178static inline void mmu_notifier_invalidate_page(struct mm_struct *mm,
179 unsigned long address)
180{
181 if (mm_has_notifiers(mm))
182 __mmu_notifier_invalidate_page(mm, address);
183}
184
185static inline void mmu_notifier_invalidate_range_start(struct mm_struct *mm,
186 unsigned long start, unsigned long end)
187{
188 if (mm_has_notifiers(mm))
189 __mmu_notifier_invalidate_range_start(mm, start, end);
190}
191
192static inline void mmu_notifier_invalidate_range_end(struct mm_struct *mm,
193 unsigned long start, unsigned long end)
194{
195 if (mm_has_notifiers(mm))
196 __mmu_notifier_invalidate_range_end(mm, start, end);
197}
198
199static inline void mmu_notifier_mm_init(struct mm_struct *mm)
200{
201 mm->mmu_notifier_mm = NULL;
202}
203
204static inline void mmu_notifier_mm_destroy(struct mm_struct *mm)
205{
206 if (mm_has_notifiers(mm))
207 __mmu_notifier_mm_destroy(mm);
208}
209
210/*
211 * These two macros will sometime replace ptep_clear_flush.
212 * ptep_clear_flush is impleemnted as macro itself, so this also is
213 * implemented as a macro until ptep_clear_flush will converted to an
214 * inline function, to diminish the risk of compilation failure. The
215 * invalidate_page method over time can be moved outside the PT lock
216 * and these two macros can be later removed.
217 */
218#define ptep_clear_flush_notify(__vma, __address, __ptep) \
219({ \
220 pte_t __pte; \
221 struct vm_area_struct *___vma = __vma; \
222 unsigned long ___address = __address; \
223 __pte = ptep_clear_flush(___vma, ___address, __ptep); \
224 mmu_notifier_invalidate_page(___vma->vm_mm, ___address); \
225 __pte; \
226})
227
228#define ptep_clear_flush_young_notify(__vma, __address, __ptep) \
229({ \
230 int __young; \
231 struct vm_area_struct *___vma = __vma; \
232 unsigned long ___address = __address; \
233 __young = ptep_clear_flush_young(___vma, ___address, __ptep); \
234 __young |= mmu_notifier_clear_flush_young(___vma->vm_mm, \
235 ___address); \
236 __young; \
237})
238
239#else /* CONFIG_MMU_NOTIFIER */
240
241static inline void mmu_notifier_release(struct mm_struct *mm)
242{
243}
244
245static inline int mmu_notifier_clear_flush_young(struct mm_struct *mm,
246 unsigned long address)
247{
248 return 0;
249}
250
251static inline void mmu_notifier_invalidate_page(struct mm_struct *mm,
252 unsigned long address)
253{
254}
255
256static inline void mmu_notifier_invalidate_range_start(struct mm_struct *mm,
257 unsigned long start, unsigned long end)
258{
259}
260
261static inline void mmu_notifier_invalidate_range_end(struct mm_struct *mm,
262 unsigned long start, unsigned long end)
263{
264}
265
266static inline void mmu_notifier_mm_init(struct mm_struct *mm)
267{
268}
269
270static inline void mmu_notifier_mm_destroy(struct mm_struct *mm)
271{
272}
273
274#define ptep_clear_flush_young_notify ptep_clear_flush_young
275#define ptep_clear_flush_notify ptep_clear_flush
276
277#endif /* CONFIG_MMU_NOTIFIER */
278
279#endif /* _LINUX_MMU_NOTIFIER_H */
diff --git a/include/linux/mount.h b/include/linux/mount.h
index b5efaa2132a..30a1d63b6fb 100644
--- a/include/linux/mount.h
+++ b/include/linux/mount.h
@@ -105,7 +105,8 @@ extern struct vfsmount *vfs_kern_mount(struct file_system_type *type,
105 105
106struct nameidata; 106struct nameidata;
107 107
108extern int do_add_mount(struct vfsmount *newmnt, struct nameidata *nd, 108struct path;
109extern int do_add_mount(struct vfsmount *newmnt, struct path *path,
109 int mnt_flags, struct list_head *fslist); 110 int mnt_flags, struct list_head *fslist);
110 111
111extern void mark_mounts_for_expiry(struct list_head *mounts); 112extern void mark_mounts_for_expiry(struct list_head *mounts);
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 4ed40caff4e..92263654855 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -272,7 +272,11 @@ static inline void mtd_erase_callback(struct erase_info *instr)
272 printk(KERN_INFO args); \ 272 printk(KERN_INFO args); \
273 } while(0) 273 } while(0)
274#else /* CONFIG_MTD_DEBUG */ 274#else /* CONFIG_MTD_DEBUG */
275#define DEBUG(n, args...) do { } while(0) 275#define DEBUG(n, args...) \
276 do { \
277 if (0) \
278 printk(KERN_INFO args); \
279 } while(0)
276 280
277#endif /* CONFIG_MTD_DEBUG */ 281#endif /* CONFIG_MTD_DEBUG */
278 282
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 83f678702df..81774e5facf 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -177,7 +177,9 @@ typedef enum {
177#define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING)) 177#define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
178#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) 178#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
179#define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK)) 179#define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
180#define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT)) 180/* Large page NAND with SOFT_ECC should support subpage reads */
181#define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \
182 && (chip->page_shift > 9))
181 183
182/* Mask to zero out the chip options, which come from the id table */ 184/* Mask to zero out the chip options, which come from the id table */
183#define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR) 185#define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h
index b4d056ceab9..488c56e649b 100644
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -61,9 +61,7 @@ struct wireless_dev;
61#define NET_XMIT_DROP 1 /* skb dropped */ 61#define NET_XMIT_DROP 1 /* skb dropped */
62#define NET_XMIT_CN 2 /* congestion notification */ 62#define NET_XMIT_CN 2 /* congestion notification */
63#define NET_XMIT_POLICED 3 /* skb is shot by police */ 63#define NET_XMIT_POLICED 3 /* skb is shot by police */
64#define NET_XMIT_BYPASS 4 /* packet does not leave via dequeue; 64#define NET_XMIT_MASK 0xFFFF /* qdisc flags in net/sch_generic.h */
65 (TC use only - dev_queue_xmit
66 returns this as NET_XMIT_SUCCESS) */
67 65
68/* Backlog congestion levels */ 66/* Backlog congestion levels */
69#define NET_RX_SUCCESS 0 /* keep 'em coming, baby */ 67#define NET_RX_SUCCESS 0 /* keep 'em coming, baby */
@@ -440,6 +438,7 @@ static inline void napi_synchronize(const struct napi_struct *n)
440enum netdev_queue_state_t 438enum netdev_queue_state_t
441{ 439{
442 __QUEUE_STATE_XOFF, 440 __QUEUE_STATE_XOFF,
441 __QUEUE_STATE_FROZEN,
443}; 442};
444 443
445struct netdev_queue { 444struct netdev_queue {
@@ -636,7 +635,7 @@ struct net_device
636 unsigned int real_num_tx_queues; 635 unsigned int real_num_tx_queues;
637 636
638 unsigned long tx_queue_len; /* Max frames per queue allowed */ 637 unsigned long tx_queue_len; /* Max frames per queue allowed */
639 638 spinlock_t tx_global_lock;
640/* 639/*
641 * One part is mostly used on xmit path (device) 640 * One part is mostly used on xmit path (device)
642 */ 641 */
@@ -1099,6 +1098,11 @@ static inline int netif_queue_stopped(const struct net_device *dev)
1099 return netif_tx_queue_stopped(netdev_get_tx_queue(dev, 0)); 1098 return netif_tx_queue_stopped(netdev_get_tx_queue(dev, 0));
1100} 1099}
1101 1100
1101static inline int netif_tx_queue_frozen(const struct netdev_queue *dev_queue)
1102{
1103 return test_bit(__QUEUE_STATE_FROZEN, &dev_queue->state);
1104}
1105
1102/** 1106/**
1103 * netif_running - test if up 1107 * netif_running - test if up
1104 * @dev: network device 1108 * @dev: network device
@@ -1475,6 +1479,26 @@ static inline void __netif_tx_lock_bh(struct netdev_queue *txq)
1475 txq->xmit_lock_owner = smp_processor_id(); 1479 txq->xmit_lock_owner = smp_processor_id();
1476} 1480}
1477 1481
1482static inline int __netif_tx_trylock(struct netdev_queue *txq)
1483{
1484 int ok = spin_trylock(&txq->_xmit_lock);
1485 if (likely(ok))
1486 txq->xmit_lock_owner = smp_processor_id();
1487 return ok;
1488}
1489
1490static inline void __netif_tx_unlock(struct netdev_queue *txq)
1491{
1492 txq->xmit_lock_owner = -1;
1493 spin_unlock(&txq->_xmit_lock);
1494}
1495
1496static inline void __netif_tx_unlock_bh(struct netdev_queue *txq)
1497{
1498 txq->xmit_lock_owner = -1;
1499 spin_unlock_bh(&txq->_xmit_lock);
1500}
1501
1478/** 1502/**
1479 * netif_tx_lock - grab network device transmit lock 1503 * netif_tx_lock - grab network device transmit lock
1480 * @dev: network device 1504 * @dev: network device
@@ -1484,12 +1508,23 @@ static inline void __netif_tx_lock_bh(struct netdev_queue *txq)
1484 */ 1508 */
1485static inline void netif_tx_lock(struct net_device *dev) 1509static inline void netif_tx_lock(struct net_device *dev)
1486{ 1510{
1487 int cpu = smp_processor_id();
1488 unsigned int i; 1511 unsigned int i;
1512 int cpu;
1489 1513
1514 spin_lock(&dev->tx_global_lock);
1515 cpu = smp_processor_id();
1490 for (i = 0; i < dev->num_tx_queues; i++) { 1516 for (i = 0; i < dev->num_tx_queues; i++) {
1491 struct netdev_queue *txq = netdev_get_tx_queue(dev, i); 1517 struct netdev_queue *txq = netdev_get_tx_queue(dev, i);
1518
1519 /* We are the only thread of execution doing a
1520 * freeze, but we have to grab the _xmit_lock in
1521 * order to synchronize with threads which are in
1522 * the ->hard_start_xmit() handler and already
1523 * checked the frozen bit.
1524 */
1492 __netif_tx_lock(txq, cpu); 1525 __netif_tx_lock(txq, cpu);
1526 set_bit(__QUEUE_STATE_FROZEN, &txq->state);
1527 __netif_tx_unlock(txq);
1493 } 1528 }
1494} 1529}
1495 1530
@@ -1499,40 +1534,22 @@ static inline void netif_tx_lock_bh(struct net_device *dev)
1499 netif_tx_lock(dev); 1534 netif_tx_lock(dev);
1500} 1535}
1501 1536
1502static inline int __netif_tx_trylock(struct netdev_queue *txq)
1503{
1504 int ok = spin_trylock(&txq->_xmit_lock);
1505 if (likely(ok))
1506 txq->xmit_lock_owner = smp_processor_id();
1507 return ok;
1508}
1509
1510static inline int netif_tx_trylock(struct net_device *dev)
1511{
1512 return __netif_tx_trylock(netdev_get_tx_queue(dev, 0));
1513}
1514
1515static inline void __netif_tx_unlock(struct netdev_queue *txq)
1516{
1517 txq->xmit_lock_owner = -1;
1518 spin_unlock(&txq->_xmit_lock);
1519}
1520
1521static inline void __netif_tx_unlock_bh(struct netdev_queue *txq)
1522{
1523 txq->xmit_lock_owner = -1;
1524 spin_unlock_bh(&txq->_xmit_lock);
1525}
1526
1527static inline void netif_tx_unlock(struct net_device *dev) 1537static inline void netif_tx_unlock(struct net_device *dev)
1528{ 1538{
1529 unsigned int i; 1539 unsigned int i;
1530 1540
1531 for (i = 0; i < dev->num_tx_queues; i++) { 1541 for (i = 0; i < dev->num_tx_queues; i++) {
1532 struct netdev_queue *txq = netdev_get_tx_queue(dev, i); 1542 struct netdev_queue *txq = netdev_get_tx_queue(dev, i);
1533 __netif_tx_unlock(txq);
1534 }
1535 1543
1544 /* No need to grab the _xmit_lock here. If the
1545 * queue is not stopped for another reason, we
1546 * force a schedule.
1547 */
1548 clear_bit(__QUEUE_STATE_FROZEN, &txq->state);
1549 if (!test_bit(__QUEUE_STATE_XOFF, &txq->state))
1550 __netif_schedule(txq->qdisc);
1551 }
1552 spin_unlock(&dev->tx_global_lock);
1536} 1553}
1537 1554
1538static inline void netif_tx_unlock_bh(struct net_device *dev) 1555static inline void netif_tx_unlock_bh(struct net_device *dev)
@@ -1556,13 +1573,18 @@ static inline void netif_tx_unlock_bh(struct net_device *dev)
1556static inline void netif_tx_disable(struct net_device *dev) 1573static inline void netif_tx_disable(struct net_device *dev)
1557{ 1574{
1558 unsigned int i; 1575 unsigned int i;
1576 int cpu;
1559 1577
1560 netif_tx_lock_bh(dev); 1578 local_bh_disable();
1579 cpu = smp_processor_id();
1561 for (i = 0; i < dev->num_tx_queues; i++) { 1580 for (i = 0; i < dev->num_tx_queues; i++) {
1562 struct netdev_queue *txq = netdev_get_tx_queue(dev, i); 1581 struct netdev_queue *txq = netdev_get_tx_queue(dev, i);
1582
1583 __netif_tx_lock(txq, cpu);
1563 netif_tx_stop_queue(txq); 1584 netif_tx_stop_queue(txq);
1585 __netif_tx_unlock(txq);
1564 } 1586 }
1565 netif_tx_unlock_bh(dev); 1587 local_bh_enable();
1566} 1588}
1567 1589
1568static inline void netif_addr_lock(struct net_device *dev) 1590static inline void netif_addr_lock(struct net_device *dev)
diff --git a/include/linux/netfilter/nf_conntrack_tcp.h b/include/linux/netfilter/nf_conntrack_tcp.h
index 22ce29995f1..a049df4f223 100644
--- a/include/linux/netfilter/nf_conntrack_tcp.h
+++ b/include/linux/netfilter/nf_conntrack_tcp.h
@@ -30,6 +30,9 @@ enum tcp_conntrack {
30/* Be liberal in window checking */ 30/* Be liberal in window checking */
31#define IP_CT_TCP_FLAG_BE_LIBERAL 0x08 31#define IP_CT_TCP_FLAG_BE_LIBERAL 0x08
32 32
33/* Has unacknowledged data */
34#define IP_CT_TCP_FLAG_DATA_UNACKNOWLEDGED 0x10
35
33struct nf_ct_tcp_flags { 36struct nf_ct_tcp_flags {
34 u_int8_t flags; 37 u_int8_t flags;
35 u_int8_t mask; 38 u_int8_t mask;
diff --git a/include/linux/of.h b/include/linux/of.h
index 59a61bdc98b..79886ade070 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -70,5 +70,6 @@ extern int of_n_addr_cells(struct device_node *np);
70extern int of_n_size_cells(struct device_node *np); 70extern int of_n_size_cells(struct device_node *np);
71extern const struct of_device_id *of_match_node( 71extern const struct of_device_id *of_match_node(
72 const struct of_device_id *matches, const struct device_node *node); 72 const struct of_device_id *matches, const struct device_node *node);
73extern int of_modalias_node(struct device_node *node, char *modalias, int len);
73 74
74#endif /* _LINUX_OF_H */ 75#endif /* _LINUX_OF_H */
diff --git a/include/linux/of_spi.h b/include/linux/of_spi.h
new file mode 100644
index 00000000000..5f71ee8c086
--- /dev/null
+++ b/include/linux/of_spi.h
@@ -0,0 +1,18 @@
1/*
2 * OpenFirmware SPI support routines
3 * Copyright (C) 2008 Secret Lab Technologies Ltd.
4 *
5 * Support routines for deriving SPI device attachments from the device
6 * tree.
7 */
8
9#ifndef __LINUX_OF_SPI_H
10#define __LINUX_OF_SPI_H
11
12#include <linux/of.h>
13#include <linux/spi/spi.h>
14
15extern void of_register_spi_devices(struct spi_master *master,
16 struct device_node *np);
17
18#endif /* __LINUX_OF_SPI */
diff --git a/include/linux/page-flags.h b/include/linux/page-flags.h
index 54590a9a103..c74d3e87531 100644
--- a/include/linux/page-flags.h
+++ b/include/linux/page-flags.h
@@ -163,7 +163,7 @@ static inline int Page##uname(struct page *page) \
163 163
164struct page; /* forward declaration */ 164struct page; /* forward declaration */
165 165
166PAGEFLAG(Locked, locked) TESTSCFLAG(Locked, locked) 166TESTPAGEFLAG(Locked, locked)
167PAGEFLAG(Error, error) 167PAGEFLAG(Error, error)
168PAGEFLAG(Referenced, referenced) TESTCLEARFLAG(Referenced, referenced) 168PAGEFLAG(Referenced, referenced) TESTCLEARFLAG(Referenced, referenced)
169PAGEFLAG(Dirty, dirty) TESTSCFLAG(Dirty, dirty) __CLEARPAGEFLAG(Dirty, dirty) 169PAGEFLAG(Dirty, dirty) TESTSCFLAG(Dirty, dirty) __CLEARPAGEFLAG(Dirty, dirty)
@@ -239,9 +239,6 @@ static inline void __SetPageUptodate(struct page *page)
239{ 239{
240 smp_wmb(); 240 smp_wmb();
241 __set_bit(PG_uptodate, &(page)->flags); 241 __set_bit(PG_uptodate, &(page)->flags);
242#ifdef CONFIG_S390
243 page_clear_dirty(page);
244#endif
245} 242}
246 243
247static inline void SetPageUptodate(struct page *page) 244static inline void SetPageUptodate(struct page *page)
diff --git a/include/linux/pagemap.h b/include/linux/pagemap.h
index a81d8189042..5da31c12101 100644
--- a/include/linux/pagemap.h
+++ b/include/linux/pagemap.h
@@ -20,6 +20,7 @@
20 */ 20 */
21#define AS_EIO (__GFP_BITS_SHIFT + 0) /* IO error on async write */ 21#define AS_EIO (__GFP_BITS_SHIFT + 0) /* IO error on async write */
22#define AS_ENOSPC (__GFP_BITS_SHIFT + 1) /* ENOSPC on async write */ 22#define AS_ENOSPC (__GFP_BITS_SHIFT + 1) /* ENOSPC on async write */
23#define AS_MM_ALL_LOCKS (__GFP_BITS_SHIFT + 2) /* under mm_take_all_locks() */
23 24
24static inline void mapping_set_error(struct address_space *mapping, int error) 25static inline void mapping_set_error(struct address_space *mapping, int error)
25{ 26{
@@ -142,6 +143,29 @@ static inline int page_cache_get_speculative(struct page *page)
142 return 1; 143 return 1;
143} 144}
144 145
146/*
147 * Same as above, but add instead of inc (could just be merged)
148 */
149static inline int page_cache_add_speculative(struct page *page, int count)
150{
151 VM_BUG_ON(in_interrupt());
152
153#if !defined(CONFIG_SMP) && defined(CONFIG_CLASSIC_RCU)
154# ifdef CONFIG_PREEMPT
155 VM_BUG_ON(!in_atomic());
156# endif
157 VM_BUG_ON(page_count(page) == 0);
158 atomic_add(count, &page->_count);
159
160#else
161 if (unlikely(!atomic_add_unless(&page->_count, count, 0)))
162 return 0;
163#endif
164 VM_BUG_ON(PageCompound(page) && page != compound_head(page));
165
166 return 1;
167}
168
145static inline int page_freeze_refs(struct page *page, int count) 169static inline int page_freeze_refs(struct page *page, int count)
146{ 170{
147 return likely(atomic_cmpxchg(&page->_count, count, 0) == count); 171 return likely(atomic_cmpxchg(&page->_count, count, 0) == count);
@@ -226,29 +250,6 @@ static inline struct page *read_mapping_page(struct address_space *mapping,
226 return read_cache_page(mapping, index, filler, data); 250 return read_cache_page(mapping, index, filler, data);
227} 251}
228 252
229int add_to_page_cache_locked(struct page *page, struct address_space *mapping,
230 pgoff_t index, gfp_t gfp_mask);
231int add_to_page_cache_lru(struct page *page, struct address_space *mapping,
232 pgoff_t index, gfp_t gfp_mask);
233extern void remove_from_page_cache(struct page *page);
234extern void __remove_from_page_cache(struct page *page);
235
236/*
237 * Like add_to_page_cache_locked, but used to add newly allocated pages:
238 * the page is new, so we can just run SetPageLocked() against it.
239 */
240static inline int add_to_page_cache(struct page *page,
241 struct address_space *mapping, pgoff_t offset, gfp_t gfp_mask)
242{
243 int error;
244
245 SetPageLocked(page);
246 error = add_to_page_cache_locked(page, mapping, offset, gfp_mask);
247 if (unlikely(error))
248 ClearPageLocked(page);
249 return error;
250}
251
252/* 253/*
253 * Return byte-offset into filesystem object for page. 254 * Return byte-offset into filesystem object for page.
254 */ 255 */
@@ -270,13 +271,28 @@ extern int __lock_page_killable(struct page *page);
270extern void __lock_page_nosync(struct page *page); 271extern void __lock_page_nosync(struct page *page);
271extern void unlock_page(struct page *page); 272extern void unlock_page(struct page *page);
272 273
274static inline void set_page_locked(struct page *page)
275{
276 set_bit(PG_locked, &page->flags);
277}
278
279static inline void clear_page_locked(struct page *page)
280{
281 clear_bit(PG_locked, &page->flags);
282}
283
284static inline int trylock_page(struct page *page)
285{
286 return !test_and_set_bit(PG_locked, &page->flags);
287}
288
273/* 289/*
274 * lock_page may only be called if we have the page's inode pinned. 290 * lock_page may only be called if we have the page's inode pinned.
275 */ 291 */
276static inline void lock_page(struct page *page) 292static inline void lock_page(struct page *page)
277{ 293{
278 might_sleep(); 294 might_sleep();
279 if (TestSetPageLocked(page)) 295 if (!trylock_page(page))
280 __lock_page(page); 296 __lock_page(page);
281} 297}
282 298
@@ -288,7 +304,7 @@ static inline void lock_page(struct page *page)
288static inline int lock_page_killable(struct page *page) 304static inline int lock_page_killable(struct page *page)
289{ 305{
290 might_sleep(); 306 might_sleep();
291 if (TestSetPageLocked(page)) 307 if (!trylock_page(page))
292 return __lock_page_killable(page); 308 return __lock_page_killable(page);
293 return 0; 309 return 0;
294} 310}
@@ -300,7 +316,7 @@ static inline int lock_page_killable(struct page *page)
300static inline void lock_page_nosync(struct page *page) 316static inline void lock_page_nosync(struct page *page)
301{ 317{
302 might_sleep(); 318 might_sleep();
303 if (TestSetPageLocked(page)) 319 if (!trylock_page(page))
304 __lock_page_nosync(page); 320 __lock_page_nosync(page);
305} 321}
306 322
@@ -385,4 +401,27 @@ static inline int fault_in_pages_readable(const char __user *uaddr, int size)
385 return ret; 401 return ret;
386} 402}
387 403
404int add_to_page_cache_locked(struct page *page, struct address_space *mapping,
405 pgoff_t index, gfp_t gfp_mask);
406int add_to_page_cache_lru(struct page *page, struct address_space *mapping,
407 pgoff_t index, gfp_t gfp_mask);
408extern void remove_from_page_cache(struct page *page);
409extern void __remove_from_page_cache(struct page *page);
410
411/*
412 * Like add_to_page_cache_locked, but used to add newly allocated pages:
413 * the page is new, so we can just run set_page_locked() against it.
414 */
415static inline int add_to_page_cache(struct page *page,
416 struct address_space *mapping, pgoff_t offset, gfp_t gfp_mask)
417{
418 int error;
419
420 set_page_locked(page);
421 error = add_to_page_cache_locked(page, mapping, offset, gfp_mask);
422 if (unlikely(error))
423 clear_page_locked(page);
424 return error;
425}
426
388#endif /* _LINUX_PAGEMAP_H */ 427#endif /* _LINUX_PAGEMAP_H */
diff --git a/include/linux/parser.h b/include/linux/parser.h
index cc554ca8bc7..7dcd0507575 100644
--- a/include/linux/parser.h
+++ b/include/linux/parser.h
@@ -14,7 +14,7 @@ struct match_token {
14 const char *pattern; 14 const char *pattern;
15}; 15};
16 16
17typedef const struct match_token match_table_t[]; 17typedef struct match_token match_table_t[];
18 18
19/* Maximum number of arguments that match_token will find in a pattern */ 19/* Maximum number of arguments that match_token will find in a pattern */
20enum {MAX_OPT_ARGS = 3}; 20enum {MAX_OPT_ARGS = 3};
diff --git a/include/linux/pci-aspm.h b/include/linux/pci-aspm.h
index a1a1e618e99..91ba0b338b4 100644
--- a/include/linux/pci-aspm.h
+++ b/include/linux/pci-aspm.h
@@ -27,6 +27,7 @@ extern void pcie_aspm_init_link_state(struct pci_dev *pdev);
27extern void pcie_aspm_exit_link_state(struct pci_dev *pdev); 27extern void pcie_aspm_exit_link_state(struct pci_dev *pdev);
28extern void pcie_aspm_pm_state_change(struct pci_dev *pdev); 28extern void pcie_aspm_pm_state_change(struct pci_dev *pdev);
29extern void pci_disable_link_state(struct pci_dev *pdev, int state); 29extern void pci_disable_link_state(struct pci_dev *pdev, int state);
30extern void pcie_no_aspm(void);
30#else 31#else
31static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) 32static inline void pcie_aspm_init_link_state(struct pci_dev *pdev)
32{ 33{
@@ -40,6 +41,10 @@ static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev)
40static inline void pci_disable_link_state(struct pci_dev *pdev, int state) 41static inline void pci_disable_link_state(struct pci_dev *pdev, int state)
41{ 42{
42} 43}
44
45static inline void pcie_no_aspm(void)
46{
47}
43#endif 48#endif
44 49
45#ifdef CONFIG_PCIEASPM_DEBUG /* this depends on CONFIG_PCIEASPM */ 50#ifdef CONFIG_PCIEASPM_DEBUG /* this depends on CONFIG_PCIEASPM */
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 1d296d31abe..825be3878f6 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -124,6 +124,8 @@ enum pci_dev_flags {
124 * generation too. 124 * generation too.
125 */ 125 */
126 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1, 126 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
127 /* Device configuration is irrevocably lost if disabled into D3 */
128 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
127}; 129};
128 130
129typedef unsigned short __bitwise pci_bus_flags_t; 131typedef unsigned short __bitwise pci_bus_flags_t;
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index 19958b92990..450684f7eaa 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -374,6 +374,7 @@
374#define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */ 374#define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
375#define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */ 375#define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
376#define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */ 376#define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
377#define PCI_EXP_DEVCAP_RBER 0x8000 /* Role-Based Error Reporting */
377#define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */ 378#define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
378#define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */ 379#define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
379#define PCI_EXP_DEVCTL 8 /* Device Control */ 380#define PCI_EXP_DEVCTL 8 /* Device Control */
diff --git a/include/linux/pm_qos_params.h b/include/linux/pm_qos_params.h
index 2e4e97bd19f..d74f75ed1e4 100644
--- a/include/linux/pm_qos_params.h
+++ b/include/linux/pm_qos_params.h
@@ -1,6 +1,6 @@
1/* interface for the pm_qos_power infrastructure of the linux kernel. 1/* interface for the pm_qos_power infrastructure of the linux kernel.
2 * 2 *
3 * Mark Gross 3 * Mark Gross <mgross@linux.intel.com>
4 */ 4 */
5#include <linux/list.h> 5#include <linux/list.h>
6#include <linux/notifier.h> 6#include <linux/notifier.h>
diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h
index 68ed19ccf1f..ea96ead1d39 100644
--- a/include/linux/power_supply.h
+++ b/include/linux/power_supply.h
@@ -78,6 +78,7 @@ enum power_supply_property {
78 POWER_SUPPLY_PROP_CHARGE_EMPTY, 78 POWER_SUPPLY_PROP_CHARGE_EMPTY,
79 POWER_SUPPLY_PROP_CHARGE_NOW, 79 POWER_SUPPLY_PROP_CHARGE_NOW,
80 POWER_SUPPLY_PROP_CHARGE_AVG, 80 POWER_SUPPLY_PROP_CHARGE_AVG,
81 POWER_SUPPLY_PROP_CHARGE_COUNTER,
81 POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN, 82 POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN,
82 POWER_SUPPLY_PROP_ENERGY_EMPTY_DESIGN, 83 POWER_SUPPLY_PROP_ENERGY_EMPTY_DESIGN,
83 POWER_SUPPLY_PROP_ENERGY_FULL, 84 POWER_SUPPLY_PROP_ENERGY_FULL,
diff --git a/include/linux/quotaops.h b/include/linux/quotaops.h
index 742187f7a05..ca6b9b5c8d5 100644
--- a/include/linux/quotaops.h
+++ b/include/linux/quotaops.h
@@ -43,6 +43,8 @@ int dquot_mark_dquot_dirty(struct dquot *dquot);
43 43
44int vfs_quota_on(struct super_block *sb, int type, int format_id, 44int vfs_quota_on(struct super_block *sb, int type, int format_id,
45 char *path, int remount); 45 char *path, int remount);
46int vfs_quota_on_path(struct super_block *sb, int type, int format_id,
47 struct path *path);
46int vfs_quota_on_mount(struct super_block *sb, char *qf_name, 48int vfs_quota_on_mount(struct super_block *sb, char *qf_name,
47 int format_id, int type); 49 int format_id, int type);
48int vfs_quota_off(struct super_block *sb, int type, int remount); 50int vfs_quota_off(struct super_block *sb, int type, int remount);
diff --git a/include/linux/raid/md_k.h b/include/linux/raid/md_k.h
index 9f2549ac0e2..c200b9a34af 100644
--- a/include/linux/raid/md_k.h
+++ b/include/linux/raid/md_k.h
@@ -128,6 +128,7 @@ struct mddev_s
128#define MD_CHANGE_DEVS 0 /* Some device status has changed */ 128#define MD_CHANGE_DEVS 0 /* Some device status has changed */
129#define MD_CHANGE_CLEAN 1 /* transition to or from 'clean' */ 129#define MD_CHANGE_CLEAN 1 /* transition to or from 'clean' */
130#define MD_CHANGE_PENDING 2 /* superblock update in progress */ 130#define MD_CHANGE_PENDING 2 /* superblock update in progress */
131#define MD_NOTIFY_ARRAY_STATE 3 /* atomic context wants to notify userspace */
131 132
132 int ro; 133 int ro;
133 134
diff --git a/include/linux/rculist.h b/include/linux/rculist.h
index b0f39be08b6..eb4443c7e05 100644
--- a/include/linux/rculist.h
+++ b/include/linux/rculist.h
@@ -98,6 +98,34 @@ static inline void list_del_rcu(struct list_head *entry)
98} 98}
99 99
100/** 100/**
101 * hlist_del_init_rcu - deletes entry from hash list with re-initialization
102 * @n: the element to delete from the hash list.
103 *
104 * Note: list_unhashed() on the node return true after this. It is
105 * useful for RCU based read lockfree traversal if the writer side
106 * must know if the list entry is still hashed or already unhashed.
107 *
108 * In particular, it means that we can not poison the forward pointers
109 * that may still be used for walking the hash list and we can only
110 * zero the pprev pointer so list_unhashed() will return true after
111 * this.
112 *
113 * The caller must take whatever precautions are necessary (such as
114 * holding appropriate locks) to avoid racing with another
115 * list-mutation primitive, such as hlist_add_head_rcu() or
116 * hlist_del_rcu(), running on this same list. However, it is
117 * perfectly legal to run concurrently with the _rcu list-traversal
118 * primitives, such as hlist_for_each_entry_rcu().
119 */
120static inline void hlist_del_init_rcu(struct hlist_node *n)
121{
122 if (!hlist_unhashed(n)) {
123 __hlist_del(n);
124 n->pprev = NULL;
125 }
126}
127
128/**
101 * list_replace_rcu - replace old entry by new one 129 * list_replace_rcu - replace old entry by new one
102 * @old : the element to be replaced 130 * @old : the element to be replaced
103 * @new : the new element to insert 131 * @new : the new element to insert
diff --git a/include/linux/regulator/bq24022.h b/include/linux/regulator/bq24022.h
new file mode 100644
index 00000000000..e84b0a9feda
--- /dev/null
+++ b/include/linux/regulator/bq24022.h
@@ -0,0 +1,21 @@
1/*
2 * Support for TI bq24022 (bqTINY-II) Dual Input (USB/AC Adpater)
3 * 1-Cell Li-Ion Charger connected via GPIOs.
4 *
5 * Copyright (c) 2008 Philipp Zabel
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 */
12
13/**
14 * bq24022_mach_info - platform data for bq24022
15 * @gpio_nce: GPIO line connected to the nCE pin, used to enable / disable charging
16 * @gpio_iset2: GPIO line connected to the ISET2 pin, used to limit charging current to 100 mA / 500 mA
17 */
18struct bq24022_mach_info {
19 int gpio_nce;
20 int gpio_iset2;
21};
diff --git a/include/linux/regulator/consumer.h b/include/linux/regulator/consumer.h
new file mode 100644
index 00000000000..afdc4558bb9
--- /dev/null
+++ b/include/linux/regulator/consumer.h
@@ -0,0 +1,284 @@
1/*
2 * consumer.h -- SoC Regulator consumer support.
3 *
4 * Copyright (C) 2007, 2008 Wolfson Microelectronics PLC.
5 *
6 * Author: Liam Girdwood <lg@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Regulator Consumer Interface.
13 *
14 * A Power Management Regulator framework for SoC based devices.
15 * Features:-
16 * o Voltage and current level control.
17 * o Operating mode control.
18 * o Regulator status.
19 * o sysfs entries for showing client devices and status
20 *
21 * EXPERIMENTAL FEATURES:
22 * Dynamic Regulator operating Mode Switching (DRMS) - allows regulators
23 * to use most efficient operating mode depending upon voltage and load and
24 * is transparent to client drivers.
25 *
26 * e.g. Devices x,y,z share regulator r. Device x and y draw 20mA each during
27 * IO and 1mA at idle. Device z draws 100mA when under load and 5mA when
28 * idling. Regulator r has > 90% efficiency in NORMAL mode at loads > 100mA
29 * but this drops rapidly to 60% when below 100mA. Regulator r has > 90%
30 * efficiency in IDLE mode at loads < 10mA. Thus regulator r will operate
31 * in normal mode for loads > 10mA and in IDLE mode for load <= 10mA.
32 *
33 */
34
35#ifndef __LINUX_REGULATOR_CONSUMER_H_
36#define __LINUX_REGULATOR_CONSUMER_H_
37
38/*
39 * Regulator operating modes.
40 *
41 * Regulators can run in a variety of different operating modes depending on
42 * output load. This allows further system power savings by selecting the
43 * best (and most efficient) regulator mode for a desired load.
44 *
45 * Most drivers will only care about NORMAL. The modes below are generic and
46 * will probably not match the naming convention of your regulator data sheet
47 * but should match the use cases in the datasheet.
48 *
49 * In order of power efficiency (least efficient at top).
50 *
51 * Mode Description
52 * FAST Regulator can handle fast changes in it's load.
53 * e.g. useful in CPU voltage & frequency scaling where
54 * load can quickly increase with CPU frequency increases.
55 *
56 * NORMAL Normal regulator power supply mode. Most drivers will
57 * use this mode.
58 *
59 * IDLE Regulator runs in a more efficient mode for light
60 * loads. Can be used for devices that have a low power
61 * requirement during periods of inactivity. This mode
62 * may be more noisy than NORMAL and may not be able
63 * to handle fast load switching.
64 *
65 * STANDBY Regulator runs in the most efficient mode for very
66 * light loads. Can be used by devices when they are
67 * in a sleep/standby state. This mode is likely to be
68 * the most noisy and may not be able to handle fast load
69 * switching.
70 *
71 * NOTE: Most regulators will only support a subset of these modes. Some
72 * will only just support NORMAL.
73 *
74 * These modes can be OR'ed together to make up a mask of valid register modes.
75 */
76
77#define REGULATOR_MODE_FAST 0x1
78#define REGULATOR_MODE_NORMAL 0x2
79#define REGULATOR_MODE_IDLE 0x4
80#define REGULATOR_MODE_STANDBY 0x8
81
82/*
83 * Regulator notifier events.
84 *
85 * UNDER_VOLTAGE Regulator output is under voltage.
86 * OVER_CURRENT Regulator output current is too high.
87 * REGULATION_OUT Regulator output is out of regulation.
88 * FAIL Regulator output has failed.
89 * OVER_TEMP Regulator over temp.
90 * FORCE_DISABLE Regulator shut down by software.
91 *
92 * NOTE: These events can be OR'ed together when passed into handler.
93 */
94
95#define REGULATOR_EVENT_UNDER_VOLTAGE 0x01
96#define REGULATOR_EVENT_OVER_CURRENT 0x02
97#define REGULATOR_EVENT_REGULATION_OUT 0x04
98#define REGULATOR_EVENT_FAIL 0x08
99#define REGULATOR_EVENT_OVER_TEMP 0x10
100#define REGULATOR_EVENT_FORCE_DISABLE 0x20
101
102struct regulator;
103
104/**
105 * struct regulator_bulk_data - Data used for bulk regulator operations.
106 *
107 * @supply The name of the supply. Initialised by the user before
108 * using the bulk regulator APIs.
109 * @consumer The regulator consumer for the supply. This will be managed
110 * by the bulk API.
111 *
112 * The regulator APIs provide a series of regulator_bulk_() API calls as
113 * a convenience to consumers which require multiple supplies. This
114 * structure is used to manage data for these calls.
115 */
116struct regulator_bulk_data {
117 const char *supply;
118 struct regulator *consumer;
119};
120
121#if defined(CONFIG_REGULATOR)
122
123/* regulator get and put */
124struct regulator *__must_check regulator_get(struct device *dev,
125 const char *id);
126void regulator_put(struct regulator *regulator);
127
128/* regulator output control and status */
129int regulator_enable(struct regulator *regulator);
130int regulator_disable(struct regulator *regulator);
131int regulator_force_disable(struct regulator *regulator);
132int regulator_is_enabled(struct regulator *regulator);
133
134int regulator_bulk_get(struct device *dev, int num_consumers,
135 struct regulator_bulk_data *consumers);
136int regulator_bulk_enable(int num_consumers,
137 struct regulator_bulk_data *consumers);
138int regulator_bulk_disable(int num_consumers,
139 struct regulator_bulk_data *consumers);
140void regulator_bulk_free(int num_consumers,
141 struct regulator_bulk_data *consumers);
142
143int regulator_set_voltage(struct regulator *regulator, int min_uV, int max_uV);
144int regulator_get_voltage(struct regulator *regulator);
145int regulator_set_current_limit(struct regulator *regulator,
146 int min_uA, int max_uA);
147int regulator_get_current_limit(struct regulator *regulator);
148
149int regulator_set_mode(struct regulator *regulator, unsigned int mode);
150unsigned int regulator_get_mode(struct regulator *regulator);
151int regulator_set_optimum_mode(struct regulator *regulator, int load_uA);
152
153/* regulator notifier block */
154int regulator_register_notifier(struct regulator *regulator,
155 struct notifier_block *nb);
156int regulator_unregister_notifier(struct regulator *regulator,
157 struct notifier_block *nb);
158
159/* driver data - core doesn't touch */
160void *regulator_get_drvdata(struct regulator *regulator);
161void regulator_set_drvdata(struct regulator *regulator, void *data);
162
163#else
164
165/*
166 * Make sure client drivers will still build on systems with no software
167 * controllable voltage or current regulators.
168 */
169static inline struct regulator *__must_check regulator_get(struct device *dev,
170 const char *id)
171{
172 /* Nothing except the stubbed out regulator API should be
173 * looking at the value except to check if it is an error
174 * value so the actual return value doesn't matter.
175 */
176 return (struct regulator *)id;
177}
178static inline void regulator_put(struct regulator *regulator)
179{
180}
181
182static inline int regulator_enable(struct regulator *regulator)
183{
184 return 0;
185}
186
187static inline int regulator_disable(struct regulator *regulator)
188{
189 return 0;
190}
191
192static inline int regulator_is_enabled(struct regulator *regulator)
193{
194 return 1;
195}
196
197static inline int regulator_bulk_get(struct device *dev,
198 int num_consumers,
199 struct regulator_bulk_data *consumers)
200{
201 return 0;
202}
203
204static inline int regulator_bulk_enable(int num_consumers,
205 struct regulator_bulk_data *consumers)
206{
207 return 0;
208}
209
210static inline int regulator_bulk_disable(int num_consumers,
211 struct regulator_bulk_data *consumers)
212{
213 return 0;
214}
215
216static inline void regulator_bulk_free(int num_consumers,
217 struct regulator_bulk_data *consumers)
218{
219}
220
221static inline int regulator_set_voltage(struct regulator *regulator,
222 int min_uV, int max_uV)
223{
224 return 0;
225}
226
227static inline int regulator_get_voltage(struct regulator *regulator)
228{
229 return 0;
230}
231
232static inline int regulator_set_current_limit(struct regulator *regulator,
233 int min_uA, int max_uA)
234{
235 return 0;
236}
237
238static inline int regulator_get_current_limit(struct regulator *regulator)
239{
240 return 0;
241}
242
243static inline int regulator_set_mode(struct regulator *regulator,
244 unsigned int mode)
245{
246 return 0;
247}
248
249static inline unsigned int regulator_get_mode(struct regulator *regulator)
250{
251 return REGULATOR_MODE_NORMAL;
252}
253
254static inline int regulator_set_optimum_mode(struct regulator *regulator,
255 int load_uA)
256{
257 return REGULATOR_MODE_NORMAL;
258}
259
260static inline int regulator_register_notifier(struct regulator *regulator,
261 struct notifier_block *nb)
262{
263 return 0;
264}
265
266static inline int regulator_unregister_notifier(struct regulator *regulator,
267 struct notifier_block *nb)
268{
269 return 0;
270}
271
272static inline void *regulator_get_drvdata(struct regulator *regulator)
273{
274 return NULL;
275}
276
277static inline void regulator_set_drvdata(struct regulator *regulator,
278 void *data)
279{
280}
281
282#endif
283
284#endif
diff --git a/include/linux/regulator/driver.h b/include/linux/regulator/driver.h
new file mode 100644
index 00000000000..1d712c7172a
--- /dev/null
+++ b/include/linux/regulator/driver.h
@@ -0,0 +1,99 @@
1/*
2 * driver.h -- SoC Regulator driver support.
3 *
4 * Copyright (C) 2007, 2008 Wolfson Microelectronics PLC.
5 *
6 * Author: Liam Girdwood <lg@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Regulator Driver Interface.
13 */
14
15#ifndef __LINUX_REGULATOR_DRIVER_H_
16#define __LINUX_REGULATOR_DRIVER_H_
17
18#include <linux/device.h>
19#include <linux/regulator/consumer.h>
20
21struct regulator_constraints;
22struct regulator_dev;
23
24/**
25 * struct regulator_ops - regulator operations.
26 *
27 * This struct describes regulator operations.
28 */
29struct regulator_ops {
30
31 /* get/set regulator voltage */
32 int (*set_voltage) (struct regulator_dev *, int min_uV, int max_uV);
33 int (*get_voltage) (struct regulator_dev *);
34
35 /* get/set regulator current */
36 int (*set_current_limit) (struct regulator_dev *,
37 int min_uA, int max_uA);
38 int (*get_current_limit) (struct regulator_dev *);
39
40 /* enable/disable regulator */
41 int (*enable) (struct regulator_dev *);
42 int (*disable) (struct regulator_dev *);
43 int (*is_enabled) (struct regulator_dev *);
44
45 /* get/set regulator operating mode (defined in regulator.h) */
46 int (*set_mode) (struct regulator_dev *, unsigned int mode);
47 unsigned int (*get_mode) (struct regulator_dev *);
48
49 /* get most efficient regulator operating mode for load */
50 unsigned int (*get_optimum_mode) (struct regulator_dev *, int input_uV,
51 int output_uV, int load_uA);
52
53 /* the operations below are for configuration of regulator state when
54 * it's parent PMIC enters a global STANBY/HIBERNATE state */
55
56 /* set regulator suspend voltage */
57 int (*set_suspend_voltage) (struct regulator_dev *, int uV);
58
59 /* enable/disable regulator in suspend state */
60 int (*set_suspend_enable) (struct regulator_dev *);
61 int (*set_suspend_disable) (struct regulator_dev *);
62
63 /* set regulator suspend operating mode (defined in regulator.h) */
64 int (*set_suspend_mode) (struct regulator_dev *, unsigned int mode);
65};
66
67/*
68 * Regulators can either control voltage or current.
69 */
70enum regulator_type {
71 REGULATOR_VOLTAGE,
72 REGULATOR_CURRENT,
73};
74
75/**
76 * struct regulator_desc - Regulator descriptor
77 *
78 */
79struct regulator_desc {
80 const char *name;
81 int id;
82 struct regulator_ops *ops;
83 int irq;
84 enum regulator_type type;
85 struct module *owner;
86};
87
88
89struct regulator_dev *regulator_register(struct regulator_desc *regulator_desc,
90 void *reg_data);
91void regulator_unregister(struct regulator_dev *rdev);
92
93int regulator_notifier_call_chain(struct regulator_dev *rdev,
94 unsigned long event, void *data);
95
96void *rdev_get_drvdata(struct regulator_dev *rdev);
97int rdev_get_id(struct regulator_dev *rdev);
98
99#endif
diff --git a/include/linux/regulator/fixed.h b/include/linux/regulator/fixed.h
new file mode 100644
index 00000000000..1387a5d2190
--- /dev/null
+++ b/include/linux/regulator/fixed.h
@@ -0,0 +1,22 @@
1/*
2 * fixed.h
3 *
4 * Copyright 2008 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or (at your option) any later version.
12 */
13
14#ifndef __REGULATOR_FIXED_H
15#define __REGULATOR_FIXED_H
16
17struct fixed_voltage_config {
18 const char *supply_name;
19 int microvolts;
20};
21
22#endif
diff --git a/include/linux/regulator/machine.h b/include/linux/regulator/machine.h
new file mode 100644
index 00000000000..11e737dbfcf
--- /dev/null
+++ b/include/linux/regulator/machine.h
@@ -0,0 +1,104 @@
1/*
2 * machine.h -- SoC Regulator support, machine/board driver API.
3 *
4 * Copyright (C) 2007, 2008 Wolfson Microelectronics PLC.
5 *
6 * Author: Liam Girdwood <lg@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Regulator Machine/Board Interface.
13 */
14
15#ifndef __LINUX_REGULATOR_MACHINE_H_
16#define __LINUX_REGULATOR_MACHINE_H_
17
18#include <linux/regulator/consumer.h>
19#include <linux/suspend.h>
20
21struct regulator;
22
23/*
24 * Regulator operation constraint flags. These flags are used to enable
25 * certain regulator operations and can be OR'ed together.
26 *
27 * VOLTAGE: Regulator output voltage can be changed by software on this
28 * board/machine.
29 * CURRENT: Regulator output current can be changed by software on this
30 * board/machine.
31 * MODE: Regulator operating mode can be changed by software on this
32 * board/machine.
33 * STATUS: Regulator can be enabled and disabled.
34 * DRMS: Dynamic Regulator Mode Switching is enabled for this regulator.
35 */
36
37#define REGULATOR_CHANGE_VOLTAGE 0x1
38#define REGULATOR_CHANGE_CURRENT 0x2
39#define REGULATOR_CHANGE_MODE 0x4
40#define REGULATOR_CHANGE_STATUS 0x8
41#define REGULATOR_CHANGE_DRMS 0x10
42
43/**
44 * struct regulator_state - regulator state during low power syatem states
45 *
46 * This describes a regulators state during a system wide low power state.
47 */
48struct regulator_state {
49 int uV; /* suspend voltage */
50 unsigned int mode; /* suspend regulator operating mode */
51 int enabled; /* is regulator enabled in this suspend state */
52};
53
54/**
55 * struct regulation_constraints - regulator operating constraints.
56 *
57 * This struct describes regulator and board/machine specific constraints.
58 */
59struct regulation_constraints {
60
61 char *name;
62
63 /* voltage output range (inclusive) - for voltage control */
64 int min_uV;
65 int max_uV;
66
67 /* current output range (inclusive) - for current control */
68 int min_uA;
69 int max_uA;
70
71 /* valid regulator operating modes for this machine */
72 unsigned int valid_modes_mask;
73
74 /* valid operations for regulator on this machine */
75 unsigned int valid_ops_mask;
76
77 /* regulator input voltage - only if supply is another regulator */
78 int input_uV;
79
80 /* regulator suspend states for global PMIC STANDBY/HIBERNATE */
81 struct regulator_state state_disk;
82 struct regulator_state state_mem;
83 struct regulator_state state_standby;
84 suspend_state_t initial_state; /* suspend state to set at init */
85
86 /* constriant flags */
87 unsigned always_on:1; /* regulator never off when system is on */
88 unsigned boot_on:1; /* bootloader/firmware enabled regulator */
89 unsigned apply_uV:1; /* apply uV constraint iff min == max */
90};
91
92int regulator_set_supply(const char *regulator, const char *regulator_supply);
93
94const char *regulator_get_supply(const char *regulator);
95
96int regulator_set_machine_constraints(const char *regulator,
97 struct regulation_constraints *constraints);
98
99int regulator_set_device_supply(const char *regulator, struct device *dev,
100 const char *supply);
101
102int regulator_suspend_prepare(suspend_state_t state);
103
104#endif
diff --git a/include/linux/rfkill.h b/include/linux/rfkill.h
index c5f6e54ec6a..741d1a62cc3 100644
--- a/include/linux/rfkill.h
+++ b/include/linux/rfkill.h
@@ -68,7 +68,8 @@ enum rfkill_state {
68 * @user_claim_unsupported: Whether the hardware supports exclusive 68 * @user_claim_unsupported: Whether the hardware supports exclusive
69 * RF-kill control by userspace. Set this before registering. 69 * RF-kill control by userspace. Set this before registering.
70 * @user_claim: Set when the switch is controlled exlusively by userspace. 70 * @user_claim: Set when the switch is controlled exlusively by userspace.
71 * @mutex: Guards switch state transitions 71 * @mutex: Guards switch state transitions. It serializes callbacks
72 * and also protects the state.
72 * @data: Pointer to the RF button drivers private data which will be 73 * @data: Pointer to the RF button drivers private data which will be
73 * passed along when toggling radio state. 74 * passed along when toggling radio state.
74 * @toggle_radio(): Mandatory handler to control state of the radio. 75 * @toggle_radio(): Mandatory handler to control state of the radio.
@@ -89,12 +90,13 @@ struct rfkill {
89 const char *name; 90 const char *name;
90 enum rfkill_type type; 91 enum rfkill_type type;
91 92
92 enum rfkill_state state;
93 bool user_claim_unsupported; 93 bool user_claim_unsupported;
94 bool user_claim; 94 bool user_claim;
95 95
96 /* the mutex serializes callbacks and also protects
97 * the state */
96 struct mutex mutex; 98 struct mutex mutex;
97 99 enum rfkill_state state;
98 void *data; 100 void *data;
99 int (*toggle_radio)(void *data, enum rfkill_state state); 101 int (*toggle_radio)(void *data, enum rfkill_state state);
100 int (*get_state)(void *data, enum rfkill_state *state); 102 int (*get_state)(void *data, enum rfkill_state *state);
diff --git a/include/linux/rmap.h b/include/linux/rmap.h
index 1383692ac5b..69407f85e10 100644
--- a/include/linux/rmap.h
+++ b/include/linux/rmap.h
@@ -26,6 +26,14 @@
26 */ 26 */
27struct anon_vma { 27struct anon_vma {
28 spinlock_t lock; /* Serialize access to vma list */ 28 spinlock_t lock; /* Serialize access to vma list */
29 /*
30 * NOTE: the LSB of the head.next is set by
31 * mm_take_all_locks() _after_ taking the above lock. So the
32 * head must only be read/written after taking the above lock
33 * to be sure to see a valid next pointer. The LSB bit itself
34 * is serialized by a system wide lock only visible to
35 * mm_take_all_locks() (mm_all_locks_mutex).
36 */
29 struct list_head head; /* List of private "related" vmas */ 37 struct list_head head; /* List of private "related" vmas */
30}; 38};
31 39
diff --git a/include/linux/serio.h b/include/linux/serio.h
index e72716cca57..25641d9e0ea 100644
--- a/include/linux/serio.h
+++ b/include/linux/serio.h
@@ -87,11 +87,10 @@ void serio_unregister_port(struct serio *serio);
87void serio_unregister_child_port(struct serio *serio); 87void serio_unregister_child_port(struct serio *serio);
88 88
89int __serio_register_driver(struct serio_driver *drv, struct module *owner, const char *mod_name); 89int __serio_register_driver(struct serio_driver *drv, struct module *owner, const char *mod_name);
90static inline int serio_register_driver(struct serio_driver *drv) 90static inline int __must_check serio_register_driver(struct serio_driver *drv)
91{ 91{
92 return __serio_register_driver(drv, THIS_MODULE, KBUILD_MODNAME); 92 return __serio_register_driver(drv, THIS_MODULE, KBUILD_MODNAME);
93} 93}
94int serio_register_driver(struct serio_driver *drv);
95void serio_unregister_driver(struct serio_driver *drv); 94void serio_unregister_driver(struct serio_driver *drv);
96 95
97static inline int serio_write(struct serio *serio, unsigned char data) 96static inline int serio_write(struct serio *serio, unsigned char data)
diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h
index 7ea44f6621f..cfcc45b3bef 100644
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
@@ -243,6 +243,7 @@ typedef unsigned char *sk_buff_data_t;
243 * @tc_index: Traffic control index 243 * @tc_index: Traffic control index
244 * @tc_verd: traffic control verdict 244 * @tc_verd: traffic control verdict
245 * @ndisc_nodetype: router type (from link layer) 245 * @ndisc_nodetype: router type (from link layer)
246 * @do_not_encrypt: set to prevent encryption of this frame
246 * @dma_cookie: a cookie to one of several possible DMA operations 247 * @dma_cookie: a cookie to one of several possible DMA operations
247 * done by skb DMA functions 248 * done by skb DMA functions
248 * @secmark: security marking 249 * @secmark: security marking
@@ -316,7 +317,10 @@ struct sk_buff {
316#ifdef CONFIG_IPV6_NDISC_NODETYPE 317#ifdef CONFIG_IPV6_NDISC_NODETYPE
317 __u8 ndisc_nodetype:2; 318 __u8 ndisc_nodetype:2;
318#endif 319#endif
319 /* 14 bit hole */ 320#if defined(CONFIG_MAC80211) || defined(CONFIG_MAC80211_MODULE)
321 __u8 do_not_encrypt:1;
322#endif
323 /* 0/13/14 bit hole */
320 324
321#ifdef CONFIG_NET_DMA 325#ifdef CONFIG_NET_DMA
322 dma_cookie_t dma_cookie; 326 dma_cookie_t dma_cookie;
diff --git a/include/linux/snmp.h b/include/linux/snmp.h
index 5df62ef1280..7a6e6bba4a7 100644
--- a/include/linux/snmp.h
+++ b/include/linux/snmp.h
@@ -214,6 +214,8 @@ enum
214 LINUX_MIB_TCPDSACKIGNOREDOLD, /* TCPSACKIgnoredOld */ 214 LINUX_MIB_TCPDSACKIGNOREDOLD, /* TCPSACKIgnoredOld */
215 LINUX_MIB_TCPDSACKIGNOREDNOUNDO, /* TCPSACKIgnoredNoUndo */ 215 LINUX_MIB_TCPDSACKIGNOREDNOUNDO, /* TCPSACKIgnoredNoUndo */
216 LINUX_MIB_TCPSPURIOUSRTOS, /* TCPSpuriousRTOs */ 216 LINUX_MIB_TCPSPURIOUSRTOS, /* TCPSpuriousRTOs */
217 LINUX_MIB_TCPMD5NOTFOUND, /* TCPMD5NotFound */
218 LINUX_MIB_TCPMD5UNEXPECTED, /* TCPMD5Unexpected */
217 __LINUX_MIB_MAX 219 __LINUX_MIB_MAX
218}; 220};
219 221
diff --git a/include/linux/spi/orion_spi.h b/include/linux/spi/orion_spi.h
new file mode 100644
index 00000000000..b4d9fa6f797
--- /dev/null
+++ b/include/linux/spi/orion_spi.h
@@ -0,0 +1,17 @@
1/*
2 * orion_spi.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __LINUX_SPI_ORION_SPI_H
10#define __LINUX_SPI_ORION_SPI_H
11
12struct orion_spi_info {
13 u32 tclk; /* no <linux/clk.h> support yet */
14};
15
16
17#endif
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index a9cc29d4665..4be01bb4437 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -778,8 +778,20 @@ spi_register_board_info(struct spi_board_info const *info, unsigned n)
778 * use spi_new_device() to describe each device. You can also call 778 * use spi_new_device() to describe each device. You can also call
779 * spi_unregister_device() to start making that device vanish, but 779 * spi_unregister_device() to start making that device vanish, but
780 * normally that would be handled by spi_unregister_master(). 780 * normally that would be handled by spi_unregister_master().
781 *
782 * You can also use spi_alloc_device() and spi_add_device() to use a two
783 * stage registration sequence for each spi_device. This gives the caller
784 * some more control over the spi_device structure before it is registered,
785 * but requires that caller to initialize fields that would otherwise
786 * be defined using the board info.
781 */ 787 */
782extern struct spi_device * 788extern struct spi_device *
789spi_alloc_device(struct spi_master *master);
790
791extern int
792spi_add_device(struct spi_device *spi);
793
794extern struct spi_device *
783spi_new_device(struct spi_master *, struct spi_board_info *); 795spi_new_device(struct spi_master *, struct spi_board_info *);
784 796
785static inline void 797static inline void
diff --git a/include/linux/stop_machine.h b/include/linux/stop_machine.h
index 5bfc553bdb2..f1cb0ba6d71 100644
--- a/include/linux/stop_machine.h
+++ b/include/linux/stop_machine.h
@@ -5,41 +5,43 @@
5 (and more). So the "read" side to such a lock is anything which 5 (and more). So the "read" side to such a lock is anything which
6 diables preeempt. */ 6 diables preeempt. */
7#include <linux/cpu.h> 7#include <linux/cpu.h>
8#include <linux/cpumask.h>
8#include <asm/system.h> 9#include <asm/system.h>
9 10
10#if defined(CONFIG_STOP_MACHINE) && defined(CONFIG_SMP) 11#if defined(CONFIG_STOP_MACHINE) && defined(CONFIG_SMP)
12
13/* Deprecated, but useful for transition. */
14#define ALL_CPUS ~0U
15
11/** 16/**
12 * stop_machine_run: freeze the machine on all CPUs and run this function 17 * stop_machine: freeze the machine on all CPUs and run this function
13 * @fn: the function to run 18 * @fn: the function to run
14 * @data: the data ptr for the @fn() 19 * @data: the data ptr for the @fn()
15 * @cpu: the cpu to run @fn() on (or any, if @cpu == NR_CPUS. 20 * @cpus: the cpus to run the @fn() on (NULL = any online cpu)
16 * 21 *
17 * Description: This causes a thread to be scheduled on every other cpu, 22 * Description: This causes a thread to be scheduled on every cpu,
18 * each of which disables interrupts, and finally interrupts are disabled 23 * each of which disables interrupts. The result is that noone is
19 * on the current CPU. The result is that noone is holding a spinlock 24 * holding a spinlock or inside any other preempt-disabled region when
20 * or inside any other preempt-disabled region when @fn() runs. 25 * @fn() runs.
21 * 26 *
22 * This can be thought of as a very heavy write lock, equivalent to 27 * This can be thought of as a very heavy write lock, equivalent to
23 * grabbing every spinlock in the kernel. */ 28 * grabbing every spinlock in the kernel. */
24int stop_machine_run(int (*fn)(void *), void *data, unsigned int cpu); 29int stop_machine(int (*fn)(void *), void *data, const cpumask_t *cpus);
25 30
26/** 31/**
27 * __stop_machine_run: freeze the machine on all CPUs and run this function 32 * __stop_machine: freeze the machine on all CPUs and run this function
28 * @fn: the function to run 33 * @fn: the function to run
29 * @data: the data ptr for the @fn 34 * @data: the data ptr for the @fn
30 * @cpu: the cpu to run @fn on (or any, if @cpu == NR_CPUS. 35 * @cpus: the cpus to run the @fn() on (NULL = any online cpu)
31 * 36 *
32 * Description: This is a special version of the above, which returns the 37 * Description: This is a special version of the above, which assumes cpus
33 * thread which has run @fn(): kthread_stop will return the return value 38 * won't come or go while it's being called. Used by hotplug cpu.
34 * of @fn(). Used by hotplug cpu.
35 */ 39 */
36struct task_struct *__stop_machine_run(int (*fn)(void *), void *data, 40int __stop_machine(int (*fn)(void *), void *data, const cpumask_t *cpus);
37 unsigned int cpu);
38
39#else 41#else
40 42
41static inline int stop_machine_run(int (*fn)(void *), void *data, 43static inline int stop_machine(int (*fn)(void *), void *data,
42 unsigned int cpu) 44 const cpumask_t *cpus)
43{ 45{
44 int ret; 46 int ret;
45 local_irq_disable(); 47 local_irq_disable();
@@ -48,4 +50,18 @@ static inline int stop_machine_run(int (*fn)(void *), void *data,
48 return ret; 50 return ret;
49} 51}
50#endif /* CONFIG_SMP */ 52#endif /* CONFIG_SMP */
53
54static inline int __deprecated stop_machine_run(int (*fn)(void *), void *data,
55 unsigned int cpu)
56{
57 /* If they don't care which cpu fn runs on, just pick one. */
58 if (cpu == NR_CPUS)
59 return stop_machine(fn, data, NULL);
60 else if (cpu == ~0U)
61 return stop_machine(fn, data, &cpu_possible_map);
62 else {
63 cpumask_t cpus = cpumask_of_cpu(cpu);
64 return stop_machine(fn, data, &cpus);
65 }
66}
51#endif /* _LINUX_STOP_MACHINE */ 67#endif /* _LINUX_STOP_MACHINE */
diff --git a/include/linux/tracehook.h b/include/linux/tracehook.h
index b1875582c1a..ab3ef7aefa9 100644
--- a/include/linux/tracehook.h
+++ b/include/linux/tracehook.h
@@ -487,14 +487,20 @@ static inline int tracehook_notify_jctl(int notify, int why)
487 return notify || (current->ptrace & PT_PTRACED); 487 return notify || (current->ptrace & PT_PTRACED);
488} 488}
489 489
490#define DEATH_REAP -1
491#define DEATH_DELAYED_GROUP_LEADER -2
492
490/** 493/**
491 * tracehook_notify_death - task is dead, ready to notify parent 494 * tracehook_notify_death - task is dead, ready to notify parent
492 * @task: @current task now exiting 495 * @task: @current task now exiting
493 * @death_cookie: value to pass to tracehook_report_death() 496 * @death_cookie: value to pass to tracehook_report_death()
494 * @group_dead: nonzero if this was the last thread in the group to die 497 * @group_dead: nonzero if this was the last thread in the group to die
495 * 498 *
496 * Return the signal number to send our parent with do_notify_parent(), or 499 * A return value >= 0 means call do_notify_parent() with that signal
497 * zero to send no signal and leave a zombie, or -1 to self-reap right now. 500 * number. Negative return value can be %DEATH_REAP to self-reap right
501 * now, or %DEATH_DELAYED_GROUP_LEADER to a zombie without notifying our
502 * parent. Note that a return value of 0 means a do_notify_parent() call
503 * that sends no signal, but still wakes up a parent blocked in wait*().
498 * 504 *
499 * Called with write_lock_irq(&tasklist_lock) held. 505 * Called with write_lock_irq(&tasklist_lock) held.
500 */ 506 */
@@ -502,7 +508,7 @@ static inline int tracehook_notify_death(struct task_struct *task,
502 void **death_cookie, int group_dead) 508 void **death_cookie, int group_dead)
503{ 509{
504 if (task->exit_signal == -1) 510 if (task->exit_signal == -1)
505 return task->ptrace ? SIGCHLD : -1; 511 return task->ptrace ? SIGCHLD : DEATH_REAP;
506 512
507 /* 513 /*
508 * If something other than our normal parent is ptracing us, then 514 * If something other than our normal parent is ptracing us, then
@@ -512,21 +518,21 @@ static inline int tracehook_notify_death(struct task_struct *task,
512 if (thread_group_empty(task) && !ptrace_reparented(task)) 518 if (thread_group_empty(task) && !ptrace_reparented(task))
513 return task->exit_signal; 519 return task->exit_signal;
514 520
515 return task->ptrace ? SIGCHLD : 0; 521 return task->ptrace ? SIGCHLD : DEATH_DELAYED_GROUP_LEADER;
516} 522}
517 523
518/** 524/**
519 * tracehook_report_death - task is dead and ready to be reaped 525 * tracehook_report_death - task is dead and ready to be reaped
520 * @task: @current task now exiting 526 * @task: @current task now exiting
521 * @signal: signal number sent to parent, or 0 or -1 527 * @signal: return value from tracheook_notify_death()
522 * @death_cookie: value passed back from tracehook_notify_death() 528 * @death_cookie: value passed back from tracehook_notify_death()
523 * @group_dead: nonzero if this was the last thread in the group to die 529 * @group_dead: nonzero if this was the last thread in the group to die
524 * 530 *
525 * Thread has just become a zombie or is about to self-reap. If positive, 531 * Thread has just become a zombie or is about to self-reap. If positive,
526 * @signal is the signal number just sent to the parent (usually %SIGCHLD). 532 * @signal is the signal number just sent to the parent (usually %SIGCHLD).
527 * If @signal is -1, this thread will self-reap. If @signal is 0, this is 533 * If @signal is %DEATH_REAP, this thread will self-reap. If @signal is
528 * a delayed_group_leader() zombie. The @death_cookie was passed back by 534 * %DEATH_DELAYED_GROUP_LEADER, this is a delayed_group_leader() zombie.
529 * tracehook_notify_death(). 535 * The @death_cookie was passed back by tracehook_notify_death().
530 * 536 *
531 * If normal reaping is not inhibited, @task->exit_state might be changing 537 * If normal reaping is not inhibited, @task->exit_state might be changing
532 * in parallel. 538 * in parallel.
diff --git a/include/linux/videodev.h b/include/linux/videodev.h
index 9385a566aed..15a653d4113 100644
--- a/include/linux/videodev.h
+++ b/include/linux/videodev.h
@@ -17,6 +17,21 @@
17 17
18#if defined(CONFIG_VIDEO_V4L1_COMPAT) || !defined (__KERNEL__) 18#if defined(CONFIG_VIDEO_V4L1_COMPAT) || !defined (__KERNEL__)
19 19
20#define VID_TYPE_CAPTURE 1 /* Can capture */
21#define VID_TYPE_TUNER 2 /* Can tune */
22#define VID_TYPE_TELETEXT 4 /* Does teletext */
23#define VID_TYPE_OVERLAY 8 /* Overlay onto frame buffer */
24#define VID_TYPE_CHROMAKEY 16 /* Overlay by chromakey */
25#define VID_TYPE_CLIPPING 32 /* Can clip */
26#define VID_TYPE_FRAMERAM 64 /* Uses the frame buffer memory */
27#define VID_TYPE_SCALES 128 /* Scalable */
28#define VID_TYPE_MONOCHROME 256 /* Monochrome only */
29#define VID_TYPE_SUBCAPTURE 512 /* Can capture subareas of the image */
30#define VID_TYPE_MPEG_DECODER 1024 /* Can decode MPEG streams */
31#define VID_TYPE_MPEG_ENCODER 2048 /* Can encode MPEG streams */
32#define VID_TYPE_MJPEG_DECODER 4096 /* Can decode MJPEG streams */
33#define VID_TYPE_MJPEG_ENCODER 8192 /* Can encode MJPEG streams */
34
20struct video_capability 35struct video_capability
21{ 36{
22 char name[32]; 37 char name[32];
diff --git a/include/linux/videodev2.h b/include/linux/videodev2.h
index 2e66a95e8d3..e466bd54a50 100644
--- a/include/linux/videodev2.h
+++ b/include/linux/videodev2.h
@@ -71,6 +71,11 @@
71 */ 71 */
72#define VIDEO_MAX_FRAME 32 72#define VIDEO_MAX_FRAME 32
73 73
74#ifndef __KERNEL__
75
76/* These defines are V4L1 specific and should not be used with the V4L2 API!
77 They will be removed from this header in the future. */
78
74#define VID_TYPE_CAPTURE 1 /* Can capture */ 79#define VID_TYPE_CAPTURE 1 /* Can capture */
75#define VID_TYPE_TUNER 2 /* Can tune */ 80#define VID_TYPE_TUNER 2 /* Can tune */
76#define VID_TYPE_TELETEXT 4 /* Does teletext */ 81#define VID_TYPE_TELETEXT 4 /* Does teletext */
@@ -85,14 +90,15 @@
85#define VID_TYPE_MPEG_ENCODER 2048 /* Can encode MPEG streams */ 90#define VID_TYPE_MPEG_ENCODER 2048 /* Can encode MPEG streams */
86#define VID_TYPE_MJPEG_DECODER 4096 /* Can decode MJPEG streams */ 91#define VID_TYPE_MJPEG_DECODER 4096 /* Can decode MJPEG streams */
87#define VID_TYPE_MJPEG_ENCODER 8192 /* Can encode MJPEG streams */ 92#define VID_TYPE_MJPEG_ENCODER 8192 /* Can encode MJPEG streams */
93#endif
88 94
89/* 95/*
90 * M I S C E L L A N E O U S 96 * M I S C E L L A N E O U S
91 */ 97 */
92 98
93/* Four-character-code (FOURCC) */ 99/* Four-character-code (FOURCC) */
94#define v4l2_fourcc(a,b,c,d)\ 100#define v4l2_fourcc(a, b, c, d)\
95 (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24)) 101 ((__u32)(a) | ((__u32)(b) << 8) | ((__u32)(c) << 16) | ((__u32)(d) << 24))
96 102
97/* 103/*
98 * E N U M S 104 * E N U M S
@@ -226,8 +232,7 @@ struct v4l2_fract {
226/* 232/*
227 * D R I V E R C A P A B I L I T I E S 233 * D R I V E R C A P A B I L I T I E S
228 */ 234 */
229struct v4l2_capability 235struct v4l2_capability {
230{
231 __u8 driver[16]; /* i.e. "bttv" */ 236 __u8 driver[16]; /* i.e. "bttv" */
232 __u8 card[32]; /* i.e. "Hauppauge WinTV" */ 237 __u8 card[32]; /* i.e. "Hauppauge WinTV" */
233 __u8 bus_info[32]; /* "PCI:" + pci_name(pci_dev) */ 238 __u8 bus_info[32]; /* "PCI:" + pci_name(pci_dev) */
@@ -259,8 +264,7 @@ struct v4l2_capability
259/* 264/*
260 * V I D E O I M A G E F O R M A T 265 * V I D E O I M A G E F O R M A T
261 */ 266 */
262struct v4l2_pix_format 267struct v4l2_pix_format {
263{
264 __u32 width; 268 __u32 width;
265 __u32 height; 269 __u32 height;
266 __u32 pixelformat; 270 __u32 pixelformat;
@@ -272,68 +276,69 @@ struct v4l2_pix_format
272}; 276};
273 277
274/* Pixel format FOURCC depth Description */ 278/* Pixel format FOURCC depth Description */
275#define V4L2_PIX_FMT_RGB332 v4l2_fourcc('R','G','B','1') /* 8 RGB-3-3-2 */ 279#define V4L2_PIX_FMT_RGB332 v4l2_fourcc('R', 'G', 'B', '1') /* 8 RGB-3-3-2 */
276#define V4L2_PIX_FMT_RGB444 v4l2_fourcc('R','4','4','4') /* 16 xxxxrrrr ggggbbbb */ 280#define V4L2_PIX_FMT_RGB444 v4l2_fourcc('R', '4', '4', '4') /* 16 xxxxrrrr ggggbbbb */
277#define V4L2_PIX_FMT_RGB555 v4l2_fourcc('R','G','B','O') /* 16 RGB-5-5-5 */ 281#define V4L2_PIX_FMT_RGB555 v4l2_fourcc('R', 'G', 'B', 'O') /* 16 RGB-5-5-5 */
278#define V4L2_PIX_FMT_RGB565 v4l2_fourcc('R','G','B','P') /* 16 RGB-5-6-5 */ 282#define V4L2_PIX_FMT_RGB565 v4l2_fourcc('R', 'G', 'B', 'P') /* 16 RGB-5-6-5 */
279#define V4L2_PIX_FMT_RGB555X v4l2_fourcc('R','G','B','Q') /* 16 RGB-5-5-5 BE */ 283#define V4L2_PIX_FMT_RGB555X v4l2_fourcc('R', 'G', 'B', 'Q') /* 16 RGB-5-5-5 BE */
280#define V4L2_PIX_FMT_RGB565X v4l2_fourcc('R','G','B','R') /* 16 RGB-5-6-5 BE */ 284#define V4L2_PIX_FMT_RGB565X v4l2_fourcc('R', 'G', 'B', 'R') /* 16 RGB-5-6-5 BE */
281#define V4L2_PIX_FMT_BGR24 v4l2_fourcc('B','G','R','3') /* 24 BGR-8-8-8 */ 285#define V4L2_PIX_FMT_BGR24 v4l2_fourcc('B', 'G', 'R', '3') /* 24 BGR-8-8-8 */
282#define V4L2_PIX_FMT_RGB24 v4l2_fourcc('R','G','B','3') /* 24 RGB-8-8-8 */ 286#define V4L2_PIX_FMT_RGB24 v4l2_fourcc('R', 'G', 'B', '3') /* 24 RGB-8-8-8 */
283#define V4L2_PIX_FMT_BGR32 v4l2_fourcc('B','G','R','4') /* 32 BGR-8-8-8-8 */ 287#define V4L2_PIX_FMT_BGR32 v4l2_fourcc('B', 'G', 'R', '4') /* 32 BGR-8-8-8-8 */
284#define V4L2_PIX_FMT_RGB32 v4l2_fourcc('R','G','B','4') /* 32 RGB-8-8-8-8 */ 288#define V4L2_PIX_FMT_RGB32 v4l2_fourcc('R', 'G', 'B', '4') /* 32 RGB-8-8-8-8 */
285#define V4L2_PIX_FMT_GREY v4l2_fourcc('G','R','E','Y') /* 8 Greyscale */ 289#define V4L2_PIX_FMT_GREY v4l2_fourcc('G', 'R', 'E', 'Y') /* 8 Greyscale */
286#define V4L2_PIX_FMT_Y16 v4l2_fourcc('Y','1','6',' ') /* 16 Greyscale */ 290#define V4L2_PIX_FMT_Y16 v4l2_fourcc('Y', '1', '6', ' ') /* 16 Greyscale */
287#define V4L2_PIX_FMT_PAL8 v4l2_fourcc('P','A','L','8') /* 8 8-bit palette */ 291#define V4L2_PIX_FMT_PAL8 v4l2_fourcc('P', 'A', 'L', '8') /* 8 8-bit palette */
288#define V4L2_PIX_FMT_YVU410 v4l2_fourcc('Y','V','U','9') /* 9 YVU 4:1:0 */ 292#define V4L2_PIX_FMT_YVU410 v4l2_fourcc('Y', 'V', 'U', '9') /* 9 YVU 4:1:0 */
289#define V4L2_PIX_FMT_YVU420 v4l2_fourcc('Y','V','1','2') /* 12 YVU 4:2:0 */ 293#define V4L2_PIX_FMT_YVU420 v4l2_fourcc('Y', 'V', '1', '2') /* 12 YVU 4:2:0 */
290#define V4L2_PIX_FMT_YUYV v4l2_fourcc('Y','U','Y','V') /* 16 YUV 4:2:2 */ 294#define V4L2_PIX_FMT_YUYV v4l2_fourcc('Y', 'U', 'Y', 'V') /* 16 YUV 4:2:2 */
291#define V4L2_PIX_FMT_UYVY v4l2_fourcc('U','Y','V','Y') /* 16 YUV 4:2:2 */ 295#define V4L2_PIX_FMT_UYVY v4l2_fourcc('U', 'Y', 'V', 'Y') /* 16 YUV 4:2:2 */
292#define V4L2_PIX_FMT_YUV422P v4l2_fourcc('4','2','2','P') /* 16 YVU422 planar */ 296#define V4L2_PIX_FMT_YUV422P v4l2_fourcc('4', '2', '2', 'P') /* 16 YVU422 planar */
293#define V4L2_PIX_FMT_YUV411P v4l2_fourcc('4','1','1','P') /* 16 YVU411 planar */ 297#define V4L2_PIX_FMT_YUV411P v4l2_fourcc('4', '1', '1', 'P') /* 16 YVU411 planar */
294#define V4L2_PIX_FMT_Y41P v4l2_fourcc('Y','4','1','P') /* 12 YUV 4:1:1 */ 298#define V4L2_PIX_FMT_Y41P v4l2_fourcc('Y', '4', '1', 'P') /* 12 YUV 4:1:1 */
295#define V4L2_PIX_FMT_YUV444 v4l2_fourcc('Y','4','4','4') /* 16 xxxxyyyy uuuuvvvv */ 299#define V4L2_PIX_FMT_YUV444 v4l2_fourcc('Y', '4', '4', '4') /* 16 xxxxyyyy uuuuvvvv */
296#define V4L2_PIX_FMT_YUV555 v4l2_fourcc('Y','U','V','O') /* 16 YUV-5-5-5 */ 300#define V4L2_PIX_FMT_YUV555 v4l2_fourcc('Y', 'U', 'V', 'O') /* 16 YUV-5-5-5 */
297#define V4L2_PIX_FMT_YUV565 v4l2_fourcc('Y','U','V','P') /* 16 YUV-5-6-5 */ 301#define V4L2_PIX_FMT_YUV565 v4l2_fourcc('Y', 'U', 'V', 'P') /* 16 YUV-5-6-5 */
298#define V4L2_PIX_FMT_YUV32 v4l2_fourcc('Y','U','V','4') /* 32 YUV-8-8-8-8 */ 302#define V4L2_PIX_FMT_YUV32 v4l2_fourcc('Y', 'U', 'V', '4') /* 32 YUV-8-8-8-8 */
299 303
300/* two planes -- one Y, one Cr + Cb interleaved */ 304/* two planes -- one Y, one Cr + Cb interleaved */
301#define V4L2_PIX_FMT_NV12 v4l2_fourcc('N','V','1','2') /* 12 Y/CbCr 4:2:0 */ 305#define V4L2_PIX_FMT_NV12 v4l2_fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */
302#define V4L2_PIX_FMT_NV21 v4l2_fourcc('N','V','2','1') /* 12 Y/CrCb 4:2:0 */ 306#define V4L2_PIX_FMT_NV21 v4l2_fourcc('N', 'V', '2', '1') /* 12 Y/CrCb 4:2:0 */
303 307
304/* The following formats are not defined in the V4L2 specification */ 308/* The following formats are not defined in the V4L2 specification */
305#define V4L2_PIX_FMT_YUV410 v4l2_fourcc('Y','U','V','9') /* 9 YUV 4:1:0 */ 309#define V4L2_PIX_FMT_YUV410 v4l2_fourcc('Y', 'U', 'V', '9') /* 9 YUV 4:1:0 */
306#define V4L2_PIX_FMT_YUV420 v4l2_fourcc('Y','U','1','2') /* 12 YUV 4:2:0 */ 310#define V4L2_PIX_FMT_YUV420 v4l2_fourcc('Y', 'U', '1', '2') /* 12 YUV 4:2:0 */
307#define V4L2_PIX_FMT_YYUV v4l2_fourcc('Y','Y','U','V') /* 16 YUV 4:2:2 */ 311#define V4L2_PIX_FMT_YYUV v4l2_fourcc('Y', 'Y', 'U', 'V') /* 16 YUV 4:2:2 */
308#define V4L2_PIX_FMT_HI240 v4l2_fourcc('H','I','2','4') /* 8 8-bit color */ 312#define V4L2_PIX_FMT_HI240 v4l2_fourcc('H', 'I', '2', '4') /* 8 8-bit color */
309#define V4L2_PIX_FMT_HM12 v4l2_fourcc('H','M','1','2') /* 8 YUV 4:2:0 16x16 macroblocks */ 313#define V4L2_PIX_FMT_HM12 v4l2_fourcc('H', 'M', '1', '2') /* 8 YUV 4:2:0 16x16 macroblocks */
310 314
311/* see http://www.siliconimaging.com/RGB%20Bayer.htm */ 315/* see http://www.siliconimaging.com/RGB%20Bayer.htm */
312#define V4L2_PIX_FMT_SBGGR8 v4l2_fourcc('B','A','8','1') /* 8 BGBG.. GRGR.. */ 316#define V4L2_PIX_FMT_SBGGR8 v4l2_fourcc('B', 'A', '8', '1') /* 8 BGBG.. GRGR.. */
313#define V4L2_PIX_FMT_SGBRG8 v4l2_fourcc('G','B','R','G') /* 8 GBGB.. RGRG.. */ 317#define V4L2_PIX_FMT_SGBRG8 v4l2_fourcc('G', 'B', 'R', 'G') /* 8 GBGB.. RGRG.. */
314#define V4L2_PIX_FMT_SBGGR16 v4l2_fourcc('B','Y','R','2') /* 16 BGBG.. GRGR.. */ 318#define V4L2_PIX_FMT_SBGGR16 v4l2_fourcc('B', 'Y', 'R', '2') /* 16 BGBG.. GRGR.. */
315 319
316/* compressed formats */ 320/* compressed formats */
317#define V4L2_PIX_FMT_MJPEG v4l2_fourcc('M','J','P','G') /* Motion-JPEG */ 321#define V4L2_PIX_FMT_MJPEG v4l2_fourcc('M', 'J', 'P', 'G') /* Motion-JPEG */
318#define V4L2_PIX_FMT_JPEG v4l2_fourcc('J','P','E','G') /* JFIF JPEG */ 322#define V4L2_PIX_FMT_JPEG v4l2_fourcc('J', 'P', 'E', 'G') /* JFIF JPEG */
319#define V4L2_PIX_FMT_DV v4l2_fourcc('d','v','s','d') /* 1394 */ 323#define V4L2_PIX_FMT_DV v4l2_fourcc('d', 'v', 's', 'd') /* 1394 */
320#define V4L2_PIX_FMT_MPEG v4l2_fourcc('M','P','E','G') /* MPEG-1/2/4 */ 324#define V4L2_PIX_FMT_MPEG v4l2_fourcc('M', 'P', 'E', 'G') /* MPEG-1/2/4 */
321 325
322/* Vendor-specific formats */ 326/* Vendor-specific formats */
323#define V4L2_PIX_FMT_WNVA v4l2_fourcc('W','N','V','A') /* Winnov hw compress */ 327#define V4L2_PIX_FMT_WNVA v4l2_fourcc('W', 'N', 'V', 'A') /* Winnov hw compress */
324#define V4L2_PIX_FMT_SN9C10X v4l2_fourcc('S','9','1','0') /* SN9C10x compression */ 328#define V4L2_PIX_FMT_SN9C10X v4l2_fourcc('S', '9', '1', '0') /* SN9C10x compression */
325#define V4L2_PIX_FMT_PWC1 v4l2_fourcc('P','W','C','1') /* pwc older webcam */ 329#define V4L2_PIX_FMT_PWC1 v4l2_fourcc('P', 'W', 'C', '1') /* pwc older webcam */
326#define V4L2_PIX_FMT_PWC2 v4l2_fourcc('P','W','C','2') /* pwc newer webcam */ 330#define V4L2_PIX_FMT_PWC2 v4l2_fourcc('P', 'W', 'C', '2') /* pwc newer webcam */
327#define V4L2_PIX_FMT_ET61X251 v4l2_fourcc('E','6','2','5') /* ET61X251 compression */ 331#define V4L2_PIX_FMT_ET61X251 v4l2_fourcc('E', '6', '2', '5') /* ET61X251 compression */
328#define V4L2_PIX_FMT_SPCA501 v4l2_fourcc('S','5','0','1') /* YUYV per line */ 332#define V4L2_PIX_FMT_SPCA501 v4l2_fourcc('S', '5', '0', '1') /* YUYV per line */
329#define V4L2_PIX_FMT_SPCA561 v4l2_fourcc('S','5','6','1') /* compressed GBRG bayer */ 333#define V4L2_PIX_FMT_SPCA505 v4l2_fourcc('S', '5', '0', '5') /* YYUV per line */
330#define V4L2_PIX_FMT_PAC207 v4l2_fourcc('P','2','0','7') /* compressed BGGR bayer */ 334#define V4L2_PIX_FMT_SPCA508 v4l2_fourcc('S', '5', '0', '8') /* YUVY per line */
335#define V4L2_PIX_FMT_SPCA561 v4l2_fourcc('S', '5', '6', '1') /* compressed GBRG bayer */
336#define V4L2_PIX_FMT_PAC207 v4l2_fourcc('P', '2', '0', '7') /* compressed BGGR bayer */
331 337
332/* 338/*
333 * F O R M A T E N U M E R A T I O N 339 * F O R M A T E N U M E R A T I O N
334 */ 340 */
335struct v4l2_fmtdesc 341struct v4l2_fmtdesc {
336{
337 __u32 index; /* Format number */ 342 __u32 index; /* Format number */
338 enum v4l2_buf_type type; /* buffer type */ 343 enum v4l2_buf_type type; /* buffer type */
339 __u32 flags; 344 __u32 flags;
@@ -349,21 +354,18 @@ struct v4l2_fmtdesc
349/* 354/*
350 * F R A M E S I Z E E N U M E R A T I O N 355 * F R A M E S I Z E E N U M E R A T I O N
351 */ 356 */
352enum v4l2_frmsizetypes 357enum v4l2_frmsizetypes {
353{
354 V4L2_FRMSIZE_TYPE_DISCRETE = 1, 358 V4L2_FRMSIZE_TYPE_DISCRETE = 1,
355 V4L2_FRMSIZE_TYPE_CONTINUOUS = 2, 359 V4L2_FRMSIZE_TYPE_CONTINUOUS = 2,
356 V4L2_FRMSIZE_TYPE_STEPWISE = 3, 360 V4L2_FRMSIZE_TYPE_STEPWISE = 3,
357}; 361};
358 362
359struct v4l2_frmsize_discrete 363struct v4l2_frmsize_discrete {
360{
361 __u32 width; /* Frame width [pixel] */ 364 __u32 width; /* Frame width [pixel] */
362 __u32 height; /* Frame height [pixel] */ 365 __u32 height; /* Frame height [pixel] */
363}; 366};
364 367
365struct v4l2_frmsize_stepwise 368struct v4l2_frmsize_stepwise {
366{
367 __u32 min_width; /* Minimum frame width [pixel] */ 369 __u32 min_width; /* Minimum frame width [pixel] */
368 __u32 max_width; /* Maximum frame width [pixel] */ 370 __u32 max_width; /* Maximum frame width [pixel] */
369 __u32 step_width; /* Frame width step size [pixel] */ 371 __u32 step_width; /* Frame width step size [pixel] */
@@ -372,8 +374,7 @@ struct v4l2_frmsize_stepwise
372 __u32 step_height; /* Frame height step size [pixel] */ 374 __u32 step_height; /* Frame height step size [pixel] */
373}; 375};
374 376
375struct v4l2_frmsizeenum 377struct v4l2_frmsizeenum {
376{
377 __u32 index; /* Frame size number */ 378 __u32 index; /* Frame size number */
378 __u32 pixel_format; /* Pixel format */ 379 __u32 pixel_format; /* Pixel format */
379 __u32 type; /* Frame size type the device supports. */ 380 __u32 type; /* Frame size type the device supports. */
@@ -389,22 +390,19 @@ struct v4l2_frmsizeenum
389/* 390/*
390 * F R A M E R A T E E N U M E R A T I O N 391 * F R A M E R A T E E N U M E R A T I O N
391 */ 392 */
392enum v4l2_frmivaltypes 393enum v4l2_frmivaltypes {
393{
394 V4L2_FRMIVAL_TYPE_DISCRETE = 1, 394 V4L2_FRMIVAL_TYPE_DISCRETE = 1,
395 V4L2_FRMIVAL_TYPE_CONTINUOUS = 2, 395 V4L2_FRMIVAL_TYPE_CONTINUOUS = 2,
396 V4L2_FRMIVAL_TYPE_STEPWISE = 3, 396 V4L2_FRMIVAL_TYPE_STEPWISE = 3,
397}; 397};
398 398
399struct v4l2_frmival_stepwise 399struct v4l2_frmival_stepwise {
400{
401 struct v4l2_fract min; /* Minimum frame interval [s] */ 400 struct v4l2_fract min; /* Minimum frame interval [s] */
402 struct v4l2_fract max; /* Maximum frame interval [s] */ 401 struct v4l2_fract max; /* Maximum frame interval [s] */
403 struct v4l2_fract step; /* Frame interval step size [s] */ 402 struct v4l2_fract step; /* Frame interval step size [s] */
404}; 403};
405 404
406struct v4l2_frmivalenum 405struct v4l2_frmivalenum {
407{
408 __u32 index; /* Frame format index */ 406 __u32 index; /* Frame format index */
409 __u32 pixel_format; /* Pixel format */ 407 __u32 pixel_format; /* Pixel format */
410 __u32 width; /* Frame width */ 408 __u32 width; /* Frame width */
@@ -423,8 +421,7 @@ struct v4l2_frmivalenum
423/* 421/*
424 * T I M E C O D E 422 * T I M E C O D E
425 */ 423 */
426struct v4l2_timecode 424struct v4l2_timecode {
427{
428 __u32 type; 425 __u32 type;
429 __u32 flags; 426 __u32 flags;
430 __u8 frames; 427 __u8 frames;
@@ -449,8 +446,7 @@ struct v4l2_timecode
449#define V4L2_TC_USERBITS_8BITCHARS 0x0008 446#define V4L2_TC_USERBITS_8BITCHARS 0x0008
450/* The above is based on SMPTE timecodes */ 447/* The above is based on SMPTE timecodes */
451 448
452struct v4l2_jpegcompression 449struct v4l2_jpegcompression {
453{
454 int quality; 450 int quality;
455 451
456 int APPn; /* Number of APP segment to be written, 452 int APPn; /* Number of APP segment to be written,
@@ -482,16 +478,14 @@ struct v4l2_jpegcompression
482/* 478/*
483 * M E M O R Y - M A P P I N G B U F F E R S 479 * M E M O R Y - M A P P I N G B U F F E R S
484 */ 480 */
485struct v4l2_requestbuffers 481struct v4l2_requestbuffers {
486{
487 __u32 count; 482 __u32 count;
488 enum v4l2_buf_type type; 483 enum v4l2_buf_type type;
489 enum v4l2_memory memory; 484 enum v4l2_memory memory;
490 __u32 reserved[2]; 485 __u32 reserved[2];
491}; 486};
492 487
493struct v4l2_buffer 488struct v4l2_buffer {
494{
495 __u32 index; 489 __u32 index;
496 enum v4l2_buf_type type; 490 enum v4l2_buf_type type;
497 __u32 bytesused; 491 __u32 bytesused;
@@ -525,13 +519,12 @@ struct v4l2_buffer
525/* 519/*
526 * O V E R L A Y P R E V I E W 520 * O V E R L A Y P R E V I E W
527 */ 521 */
528struct v4l2_framebuffer 522struct v4l2_framebuffer {
529{
530 __u32 capability; 523 __u32 capability;
531 __u32 flags; 524 __u32 flags;
532/* FIXME: in theory we should pass something like PCI device + memory 525/* FIXME: in theory we should pass something like PCI device + memory
533 * region + offset instead of some physical address */ 526 * region + offset instead of some physical address */
534 void* base; 527 void *base;
535 struct v4l2_pix_format fmt; 528 struct v4l2_pix_format fmt;
536}; 529};
537/* Flags for the 'capability' field. Read only */ 530/* Flags for the 'capability' field. Read only */
@@ -550,14 +543,12 @@ struct v4l2_framebuffer
550#define V4L2_FBUF_FLAG_GLOBAL_ALPHA 0x0010 543#define V4L2_FBUF_FLAG_GLOBAL_ALPHA 0x0010
551#define V4L2_FBUF_FLAG_LOCAL_INV_ALPHA 0x0020 544#define V4L2_FBUF_FLAG_LOCAL_INV_ALPHA 0x0020
552 545
553struct v4l2_clip 546struct v4l2_clip {
554{
555 struct v4l2_rect c; 547 struct v4l2_rect c;
556 struct v4l2_clip __user *next; 548 struct v4l2_clip __user *next;
557}; 549};
558 550
559struct v4l2_window 551struct v4l2_window {
560{
561 struct v4l2_rect w; 552 struct v4l2_rect w;
562 enum v4l2_field field; 553 enum v4l2_field field;
563 __u32 chromakey; 554 __u32 chromakey;
@@ -570,8 +561,7 @@ struct v4l2_window
570/* 561/*
571 * C A P T U R E P A R A M E T E R S 562 * C A P T U R E P A R A M E T E R S
572 */ 563 */
573struct v4l2_captureparm 564struct v4l2_captureparm {
574{
575 __u32 capability; /* Supported modes */ 565 __u32 capability; /* Supported modes */
576 __u32 capturemode; /* Current mode */ 566 __u32 capturemode; /* Current mode */
577 struct v4l2_fract timeperframe; /* Time per frame in .1us units */ 567 struct v4l2_fract timeperframe; /* Time per frame in .1us units */
@@ -584,8 +574,7 @@ struct v4l2_captureparm
584#define V4L2_MODE_HIGHQUALITY 0x0001 /* High quality imaging mode */ 574#define V4L2_MODE_HIGHQUALITY 0x0001 /* High quality imaging mode */
585#define V4L2_CAP_TIMEPERFRAME 0x1000 /* timeperframe field is supported */ 575#define V4L2_CAP_TIMEPERFRAME 0x1000 /* timeperframe field is supported */
586 576
587struct v4l2_outputparm 577struct v4l2_outputparm {
588{
589 __u32 capability; /* Supported modes */ 578 __u32 capability; /* Supported modes */
590 __u32 outputmode; /* Current mode */ 579 __u32 outputmode; /* Current mode */
591 struct v4l2_fract timeperframe; /* Time per frame in seconds */ 580 struct v4l2_fract timeperframe; /* Time per frame in seconds */
@@ -702,8 +691,7 @@ typedef __u64 v4l2_std_id;
702#define V4L2_STD_ALL (V4L2_STD_525_60 |\ 691#define V4L2_STD_ALL (V4L2_STD_525_60 |\
703 V4L2_STD_625_50) 692 V4L2_STD_625_50)
704 693
705struct v4l2_standard 694struct v4l2_standard {
706{
707 __u32 index; 695 __u32 index;
708 v4l2_std_id id; 696 v4l2_std_id id;
709 __u8 name[24]; 697 __u8 name[24];
@@ -715,8 +703,7 @@ struct v4l2_standard
715/* 703/*
716 * V I D E O I N P U T S 704 * V I D E O I N P U T S
717 */ 705 */
718struct v4l2_input 706struct v4l2_input {
719{
720 __u32 index; /* Which input */ 707 __u32 index; /* Which input */
721 __u8 name[32]; /* Label */ 708 __u8 name[32]; /* Label */
722 __u32 type; /* Type of input */ 709 __u32 type; /* Type of input */
@@ -753,8 +740,7 @@ struct v4l2_input
753/* 740/*
754 * V I D E O O U T P U T S 741 * V I D E O O U T P U T S
755 */ 742 */
756struct v4l2_output 743struct v4l2_output {
757{
758 __u32 index; /* Which output */ 744 __u32 index; /* Which output */
759 __u8 name[32]; /* Label */ 745 __u8 name[32]; /* Label */
760 __u32 type; /* Type of output */ 746 __u32 type; /* Type of output */
@@ -771,14 +757,12 @@ struct v4l2_output
771/* 757/*
772 * C O N T R O L S 758 * C O N T R O L S
773 */ 759 */
774struct v4l2_control 760struct v4l2_control {
775{
776 __u32 id; 761 __u32 id;
777 __s32 value; 762 __s32 value;
778}; 763};
779 764
780struct v4l2_ext_control 765struct v4l2_ext_control {
781{
782 __u32 id; 766 __u32 id;
783 __u32 reserved2[2]; 767 __u32 reserved2[2];
784 union { 768 union {
@@ -788,8 +772,7 @@ struct v4l2_ext_control
788 }; 772 };
789} __attribute__ ((packed)); 773} __attribute__ ((packed));
790 774
791struct v4l2_ext_controls 775struct v4l2_ext_controls {
792{
793 __u32 ctrl_class; 776 __u32 ctrl_class;
794 __u32 count; 777 __u32 count;
795 __u32 error_idx; 778 __u32 error_idx;
@@ -807,8 +790,7 @@ struct v4l2_ext_controls
807#define V4L2_CTRL_DRIVER_PRIV(id) (((id) & 0xffff) >= 0x1000) 790#define V4L2_CTRL_DRIVER_PRIV(id) (((id) & 0xffff) >= 0x1000)
808 791
809/* Used in the VIDIOC_QUERYCTRL ioctl for querying controls */ 792/* Used in the VIDIOC_QUERYCTRL ioctl for querying controls */
810struct v4l2_queryctrl 793struct v4l2_queryctrl {
811{
812 __u32 id; 794 __u32 id;
813 enum v4l2_ctrl_type type; 795 enum v4l2_ctrl_type type;
814 __u8 name[32]; /* Whatever */ 796 __u8 name[32]; /* Whatever */
@@ -821,8 +803,7 @@ struct v4l2_queryctrl
821}; 803};
822 804
823/* Used in the VIDIOC_QUERYMENU ioctl for querying menu items */ 805/* Used in the VIDIOC_QUERYMENU ioctl for querying menu items */
824struct v4l2_querymenu 806struct v4l2_querymenu {
825{
826 __u32 id; 807 __u32 id;
827 __u32 index; 808 __u32 index;
828 __u8 name[32]; /* Whatever */ 809 __u8 name[32]; /* Whatever */
@@ -1104,8 +1085,7 @@ enum v4l2_exposure_auto_type {
1104/* 1085/*
1105 * T U N I N G 1086 * T U N I N G
1106 */ 1087 */
1107struct v4l2_tuner 1088struct v4l2_tuner {
1108{
1109 __u32 index; 1089 __u32 index;
1110 __u8 name[32]; 1090 __u8 name[32];
1111 enum v4l2_tuner_type type; 1091 enum v4l2_tuner_type type;
@@ -1119,8 +1099,7 @@ struct v4l2_tuner
1119 __u32 reserved[4]; 1099 __u32 reserved[4];
1120}; 1100};
1121 1101
1122struct v4l2_modulator 1102struct v4l2_modulator {
1123{
1124 __u32 index; 1103 __u32 index;
1125 __u8 name[32]; 1104 __u8 name[32];
1126 __u32 capability; 1105 __u32 capability;
@@ -1153,8 +1132,7 @@ struct v4l2_modulator
1153#define V4L2_TUNER_MODE_LANG1 0x0003 1132#define V4L2_TUNER_MODE_LANG1 0x0003
1154#define V4L2_TUNER_MODE_LANG1_LANG2 0x0004 1133#define V4L2_TUNER_MODE_LANG1_LANG2 0x0004
1155 1134
1156struct v4l2_frequency 1135struct v4l2_frequency {
1157{
1158 __u32 tuner; 1136 __u32 tuner;
1159 enum v4l2_tuner_type type; 1137 enum v4l2_tuner_type type;
1160 __u32 frequency; 1138 __u32 frequency;
@@ -1172,8 +1150,7 @@ struct v4l2_hw_freq_seek {
1172/* 1150/*
1173 * A U D I O 1151 * A U D I O
1174 */ 1152 */
1175struct v4l2_audio 1153struct v4l2_audio {
1176{
1177 __u32 index; 1154 __u32 index;
1178 __u8 name[32]; 1155 __u8 name[32];
1179 __u32 capability; 1156 __u32 capability;
@@ -1188,8 +1165,7 @@ struct v4l2_audio
1188/* Flags for the 'mode' field */ 1165/* Flags for the 'mode' field */
1189#define V4L2_AUDMODE_AVL 0x00001 1166#define V4L2_AUDMODE_AVL 0x00001
1190 1167
1191struct v4l2_audioout 1168struct v4l2_audioout {
1192{
1193 __u32 index; 1169 __u32 index;
1194 __u8 name[32]; 1170 __u8 name[32];
1195 __u32 capability; 1171 __u32 capability;
@@ -1253,8 +1229,7 @@ struct v4l2_encoder_cmd {
1253 */ 1229 */
1254 1230
1255/* Raw VBI */ 1231/* Raw VBI */
1256struct v4l2_vbi_format 1232struct v4l2_vbi_format {
1257{
1258 __u32 sampling_rate; /* in 1 Hz */ 1233 __u32 sampling_rate; /* in 1 Hz */
1259 __u32 offset; 1234 __u32 offset;
1260 __u32 samples_per_line; 1235 __u32 samples_per_line;
@@ -1266,8 +1241,8 @@ struct v4l2_vbi_format
1266}; 1241};
1267 1242
1268/* VBI flags */ 1243/* VBI flags */
1269#define V4L2_VBI_UNSYNC (1<< 0) 1244#define V4L2_VBI_UNSYNC (1 << 0)
1270#define V4L2_VBI_INTERLACED (1<< 1) 1245#define V4L2_VBI_INTERLACED (1 << 1)
1271 1246
1272/* Sliced VBI 1247/* Sliced VBI
1273 * 1248 *
@@ -1276,8 +1251,7 @@ struct v4l2_vbi_format
1276 * notice in the definitive implementation. 1251 * notice in the definitive implementation.
1277 */ 1252 */
1278 1253
1279struct v4l2_sliced_vbi_format 1254struct v4l2_sliced_vbi_format {
1280{
1281 __u16 service_set; 1255 __u16 service_set;
1282 /* service_lines[0][...] specifies lines 0-23 (1-23 used) of the first field 1256 /* service_lines[0][...] specifies lines 0-23 (1-23 used) of the first field
1283 service_lines[1][...] specifies lines 0-23 (1-23 used) of the second field 1257 service_lines[1][...] specifies lines 0-23 (1-23 used) of the second field
@@ -1301,8 +1275,7 @@ struct v4l2_sliced_vbi_format
1301#define V4L2_SLICED_VBI_525 (V4L2_SLICED_CAPTION_525) 1275#define V4L2_SLICED_VBI_525 (V4L2_SLICED_CAPTION_525)
1302#define V4L2_SLICED_VBI_625 (V4L2_SLICED_TELETEXT_B | V4L2_SLICED_VPS | V4L2_SLICED_WSS_625) 1276#define V4L2_SLICED_VBI_625 (V4L2_SLICED_TELETEXT_B | V4L2_SLICED_VPS | V4L2_SLICED_WSS_625)
1303 1277
1304struct v4l2_sliced_vbi_cap 1278struct v4l2_sliced_vbi_cap {
1305{
1306 __u16 service_set; 1279 __u16 service_set;
1307 /* service_lines[0][...] specifies lines 0-23 (1-23 used) of the first field 1280 /* service_lines[0][...] specifies lines 0-23 (1-23 used) of the first field
1308 service_lines[1][...] specifies lines 0-23 (1-23 used) of the second field 1281 service_lines[1][...] specifies lines 0-23 (1-23 used) of the second field
@@ -1313,8 +1286,7 @@ struct v4l2_sliced_vbi_cap
1313 __u32 reserved[3]; /* must be 0 */ 1286 __u32 reserved[3]; /* must be 0 */
1314}; 1287};
1315 1288
1316struct v4l2_sliced_vbi_data 1289struct v4l2_sliced_vbi_data {
1317{
1318 __u32 id; 1290 __u32 id;
1319 __u32 field; /* 0: first field, 1: second field */ 1291 __u32 field; /* 0: first field, 1: second field */
1320 __u32 line; /* 1-23 */ 1292 __u32 line; /* 1-23 */
@@ -1328,27 +1300,23 @@ struct v4l2_sliced_vbi_data
1328 1300
1329/* Stream data format 1301/* Stream data format
1330 */ 1302 */
1331struct v4l2_format 1303struct v4l2_format {
1332{
1333 enum v4l2_buf_type type; 1304 enum v4l2_buf_type type;
1334 union 1305 union {
1335 { 1306 struct v4l2_pix_format pix; /* V4L2_BUF_TYPE_VIDEO_CAPTURE */
1336 struct v4l2_pix_format pix; // V4L2_BUF_TYPE_VIDEO_CAPTURE 1307 struct v4l2_window win; /* V4L2_BUF_TYPE_VIDEO_OVERLAY */
1337 struct v4l2_window win; // V4L2_BUF_TYPE_VIDEO_OVERLAY 1308 struct v4l2_vbi_format vbi; /* V4L2_BUF_TYPE_VBI_CAPTURE */
1338 struct v4l2_vbi_format vbi; // V4L2_BUF_TYPE_VBI_CAPTURE 1309 struct v4l2_sliced_vbi_format sliced; /* V4L2_BUF_TYPE_SLICED_VBI_CAPTURE */
1339 struct v4l2_sliced_vbi_format sliced; // V4L2_BUF_TYPE_SLICED_VBI_CAPTURE 1310 __u8 raw_data[200]; /* user-defined */
1340 __u8 raw_data[200]; // user-defined
1341 } fmt; 1311 } fmt;
1342}; 1312};
1343 1313
1344 1314
1345/* Stream type-dependent parameters 1315/* Stream type-dependent parameters
1346 */ 1316 */
1347struct v4l2_streamparm 1317struct v4l2_streamparm {
1348{
1349 enum v4l2_buf_type type; 1318 enum v4l2_buf_type type;
1350 union 1319 union {
1351 {
1352 struct v4l2_captureparm capture; 1320 struct v4l2_captureparm capture;
1353 struct v4l2_outputparm output; 1321 struct v4l2_outputparm output;
1354 __u8 raw_data[200]; /* user-defined */ 1322 __u8 raw_data[200]; /* user-defined */
@@ -1386,92 +1354,86 @@ struct v4l2_chip_ident {
1386 * I O C T L C O D E S F O R V I D E O D E V I C E S 1354 * I O C T L C O D E S F O R V I D E O D E V I C E S
1387 * 1355 *
1388 */ 1356 */
1389#define VIDIOC_QUERYCAP _IOR ('V', 0, struct v4l2_capability) 1357#define VIDIOC_QUERYCAP _IOR('V', 0, struct v4l2_capability)
1390#define VIDIOC_RESERVED _IO ('V', 1) 1358#define VIDIOC_RESERVED _IO('V', 1)
1391#define VIDIOC_ENUM_FMT _IOWR ('V', 2, struct v4l2_fmtdesc) 1359#define VIDIOC_ENUM_FMT _IOWR('V', 2, struct v4l2_fmtdesc)
1392#define VIDIOC_G_FMT _IOWR ('V', 4, struct v4l2_format) 1360#define VIDIOC_G_FMT _IOWR('V', 4, struct v4l2_format)
1393#define VIDIOC_S_FMT _IOWR ('V', 5, struct v4l2_format) 1361#define VIDIOC_S_FMT _IOWR('V', 5, struct v4l2_format)
1394#define VIDIOC_REQBUFS _IOWR ('V', 8, struct v4l2_requestbuffers) 1362#define VIDIOC_REQBUFS _IOWR('V', 8, struct v4l2_requestbuffers)
1395#define VIDIOC_QUERYBUF _IOWR ('V', 9, struct v4l2_buffer) 1363#define VIDIOC_QUERYBUF _IOWR('V', 9, struct v4l2_buffer)
1396#define VIDIOC_G_FBUF _IOR ('V', 10, struct v4l2_framebuffer) 1364#define VIDIOC_G_FBUF _IOR('V', 10, struct v4l2_framebuffer)
1397#define VIDIOC_S_FBUF _IOW ('V', 11, struct v4l2_framebuffer) 1365#define VIDIOC_S_FBUF _IOW('V', 11, struct v4l2_framebuffer)
1398#define VIDIOC_OVERLAY _IOW ('V', 14, int) 1366#define VIDIOC_OVERLAY _IOW('V', 14, int)
1399#define VIDIOC_QBUF _IOWR ('V', 15, struct v4l2_buffer) 1367#define VIDIOC_QBUF _IOWR('V', 15, struct v4l2_buffer)
1400#define VIDIOC_DQBUF _IOWR ('V', 17, struct v4l2_buffer) 1368#define VIDIOC_DQBUF _IOWR('V', 17, struct v4l2_buffer)
1401#define VIDIOC_STREAMON _IOW ('V', 18, int) 1369#define VIDIOC_STREAMON _IOW('V', 18, int)
1402#define VIDIOC_STREAMOFF _IOW ('V', 19, int) 1370#define VIDIOC_STREAMOFF _IOW('V', 19, int)
1403#define VIDIOC_G_PARM _IOWR ('V', 21, struct v4l2_streamparm) 1371#define VIDIOC_G_PARM _IOWR('V', 21, struct v4l2_streamparm)
1404#define VIDIOC_S_PARM _IOWR ('V', 22, struct v4l2_streamparm) 1372#define VIDIOC_S_PARM _IOWR('V', 22, struct v4l2_streamparm)
1405#define VIDIOC_G_STD _IOR ('V', 23, v4l2_std_id) 1373#define VIDIOC_G_STD _IOR('V', 23, v4l2_std_id)
1406#define VIDIOC_S_STD _IOW ('V', 24, v4l2_std_id) 1374#define VIDIOC_S_STD _IOW('V', 24, v4l2_std_id)
1407#define VIDIOC_ENUMSTD _IOWR ('V', 25, struct v4l2_standard) 1375#define VIDIOC_ENUMSTD _IOWR('V', 25, struct v4l2_standard)
1408#define VIDIOC_ENUMINPUT _IOWR ('V', 26, struct v4l2_input) 1376#define VIDIOC_ENUMINPUT _IOWR('V', 26, struct v4l2_input)
1409#define VIDIOC_G_CTRL _IOWR ('V', 27, struct v4l2_control) 1377#define VIDIOC_G_CTRL _IOWR('V', 27, struct v4l2_control)
1410#define VIDIOC_S_CTRL _IOWR ('V', 28, struct v4l2_control) 1378#define VIDIOC_S_CTRL _IOWR('V', 28, struct v4l2_control)
1411#define VIDIOC_G_TUNER _IOWR ('V', 29, struct v4l2_tuner) 1379#define VIDIOC_G_TUNER _IOWR('V', 29, struct v4l2_tuner)
1412#define VIDIOC_S_TUNER _IOW ('V', 30, struct v4l2_tuner) 1380#define VIDIOC_S_TUNER _IOW('V', 30, struct v4l2_tuner)
1413#define VIDIOC_G_AUDIO _IOR ('V', 33, struct v4l2_audio) 1381#define VIDIOC_G_AUDIO _IOR('V', 33, struct v4l2_audio)
1414#define VIDIOC_S_AUDIO _IOW ('V', 34, struct v4l2_audio) 1382#define VIDIOC_S_AUDIO _IOW('V', 34, struct v4l2_audio)
1415#define VIDIOC_QUERYCTRL _IOWR ('V', 36, struct v4l2_queryctrl) 1383#define VIDIOC_QUERYCTRL _IOWR('V', 36, struct v4l2_queryctrl)
1416#define VIDIOC_QUERYMENU _IOWR ('V', 37, struct v4l2_querymenu) 1384#define VIDIOC_QUERYMENU _IOWR('V', 37, struct v4l2_querymenu)
1417#define VIDIOC_G_INPUT _IOR ('V', 38, int) 1385#define VIDIOC_G_INPUT _IOR('V', 38, int)
1418#define VIDIOC_S_INPUT _IOWR ('V', 39, int) 1386#define VIDIOC_S_INPUT _IOWR('V', 39, int)
1419#define VIDIOC_G_OUTPUT _IOR ('V', 46, int) 1387#define VIDIOC_G_OUTPUT _IOR('V', 46, int)
1420#define VIDIOC_S_OUTPUT _IOWR ('V', 47, int) 1388#define VIDIOC_S_OUTPUT _IOWR('V', 47, int)
1421#define VIDIOC_ENUMOUTPUT _IOWR ('V', 48, struct v4l2_output) 1389#define VIDIOC_ENUMOUTPUT _IOWR('V', 48, struct v4l2_output)
1422#define VIDIOC_G_AUDOUT _IOR ('V', 49, struct v4l2_audioout) 1390#define VIDIOC_G_AUDOUT _IOR('V', 49, struct v4l2_audioout)
1423#define VIDIOC_S_AUDOUT _IOW ('V', 50, struct v4l2_audioout) 1391#define VIDIOC_S_AUDOUT _IOW('V', 50, struct v4l2_audioout)
1424#define VIDIOC_G_MODULATOR _IOWR ('V', 54, struct v4l2_modulator) 1392#define VIDIOC_G_MODULATOR _IOWR('V', 54, struct v4l2_modulator)
1425#define VIDIOC_S_MODULATOR _IOW ('V', 55, struct v4l2_modulator) 1393#define VIDIOC_S_MODULATOR _IOW('V', 55, struct v4l2_modulator)
1426#define VIDIOC_G_FREQUENCY _IOWR ('V', 56, struct v4l2_frequency) 1394#define VIDIOC_G_FREQUENCY _IOWR('V', 56, struct v4l2_frequency)
1427#define VIDIOC_S_FREQUENCY _IOW ('V', 57, struct v4l2_frequency) 1395#define VIDIOC_S_FREQUENCY _IOW('V', 57, struct v4l2_frequency)
1428#define VIDIOC_CROPCAP _IOWR ('V', 58, struct v4l2_cropcap) 1396#define VIDIOC_CROPCAP _IOWR('V', 58, struct v4l2_cropcap)
1429#define VIDIOC_G_CROP _IOWR ('V', 59, struct v4l2_crop) 1397#define VIDIOC_G_CROP _IOWR('V', 59, struct v4l2_crop)
1430#define VIDIOC_S_CROP _IOW ('V', 60, struct v4l2_crop) 1398#define VIDIOC_S_CROP _IOW('V', 60, struct v4l2_crop)
1431#define VIDIOC_G_JPEGCOMP _IOR ('V', 61, struct v4l2_jpegcompression) 1399#define VIDIOC_G_JPEGCOMP _IOR('V', 61, struct v4l2_jpegcompression)
1432#define VIDIOC_S_JPEGCOMP _IOW ('V', 62, struct v4l2_jpegcompression) 1400#define VIDIOC_S_JPEGCOMP _IOW('V', 62, struct v4l2_jpegcompression)
1433#define VIDIOC_QUERYSTD _IOR ('V', 63, v4l2_std_id) 1401#define VIDIOC_QUERYSTD _IOR('V', 63, v4l2_std_id)
1434#define VIDIOC_TRY_FMT _IOWR ('V', 64, struct v4l2_format) 1402#define VIDIOC_TRY_FMT _IOWR('V', 64, struct v4l2_format)
1435#define VIDIOC_ENUMAUDIO _IOWR ('V', 65, struct v4l2_audio) 1403#define VIDIOC_ENUMAUDIO _IOWR('V', 65, struct v4l2_audio)
1436#define VIDIOC_ENUMAUDOUT _IOWR ('V', 66, struct v4l2_audioout) 1404#define VIDIOC_ENUMAUDOUT _IOWR('V', 66, struct v4l2_audioout)
1437#define VIDIOC_G_PRIORITY _IOR ('V', 67, enum v4l2_priority) 1405#define VIDIOC_G_PRIORITY _IOR('V', 67, enum v4l2_priority)
1438#define VIDIOC_S_PRIORITY _IOW ('V', 68, enum v4l2_priority) 1406#define VIDIOC_S_PRIORITY _IOW('V', 68, enum v4l2_priority)
1439#define VIDIOC_G_SLICED_VBI_CAP _IOWR ('V', 69, struct v4l2_sliced_vbi_cap) 1407#define VIDIOC_G_SLICED_VBI_CAP _IOWR('V', 69, struct v4l2_sliced_vbi_cap)
1440#define VIDIOC_LOG_STATUS _IO ('V', 70) 1408#define VIDIOC_LOG_STATUS _IO('V', 70)
1441#define VIDIOC_G_EXT_CTRLS _IOWR ('V', 71, struct v4l2_ext_controls) 1409#define VIDIOC_G_EXT_CTRLS _IOWR('V', 71, struct v4l2_ext_controls)
1442#define VIDIOC_S_EXT_CTRLS _IOWR ('V', 72, struct v4l2_ext_controls) 1410#define VIDIOC_S_EXT_CTRLS _IOWR('V', 72, struct v4l2_ext_controls)
1443#define VIDIOC_TRY_EXT_CTRLS _IOWR ('V', 73, struct v4l2_ext_controls) 1411#define VIDIOC_TRY_EXT_CTRLS _IOWR('V', 73, struct v4l2_ext_controls)
1444#if 1 1412#if 1
1445#define VIDIOC_ENUM_FRAMESIZES _IOWR ('V', 74, struct v4l2_frmsizeenum) 1413#define VIDIOC_ENUM_FRAMESIZES _IOWR('V', 74, struct v4l2_frmsizeenum)
1446#define VIDIOC_ENUM_FRAMEINTERVALS _IOWR ('V', 75, struct v4l2_frmivalenum) 1414#define VIDIOC_ENUM_FRAMEINTERVALS _IOWR('V', 75, struct v4l2_frmivalenum)
1447#define VIDIOC_G_ENC_INDEX _IOR ('V', 76, struct v4l2_enc_idx) 1415#define VIDIOC_G_ENC_INDEX _IOR('V', 76, struct v4l2_enc_idx)
1448#define VIDIOC_ENCODER_CMD _IOWR ('V', 77, struct v4l2_encoder_cmd) 1416#define VIDIOC_ENCODER_CMD _IOWR('V', 77, struct v4l2_encoder_cmd)
1449#define VIDIOC_TRY_ENCODER_CMD _IOWR ('V', 78, struct v4l2_encoder_cmd) 1417#define VIDIOC_TRY_ENCODER_CMD _IOWR('V', 78, struct v4l2_encoder_cmd)
1450 1418
1451/* Experimental, only implemented if CONFIG_VIDEO_ADV_DEBUG is defined */ 1419/* Experimental, only implemented if CONFIG_VIDEO_ADV_DEBUG is defined */
1452#define VIDIOC_DBG_S_REGISTER _IOW ('V', 79, struct v4l2_register) 1420#define VIDIOC_DBG_S_REGISTER _IOW('V', 79, struct v4l2_register)
1453#define VIDIOC_DBG_G_REGISTER _IOWR ('V', 80, struct v4l2_register) 1421#define VIDIOC_DBG_G_REGISTER _IOWR('V', 80, struct v4l2_register)
1454 1422
1455#define VIDIOC_G_CHIP_IDENT _IOWR ('V', 81, struct v4l2_chip_ident) 1423#define VIDIOC_G_CHIP_IDENT _IOWR('V', 81, struct v4l2_chip_ident)
1456#endif 1424#endif
1457#define VIDIOC_S_HW_FREQ_SEEK _IOW ('V', 82, struct v4l2_hw_freq_seek) 1425#define VIDIOC_S_HW_FREQ_SEEK _IOW('V', 82, struct v4l2_hw_freq_seek)
1458 1426
1459#ifdef __OLD_VIDIOC_ 1427#ifdef __OLD_VIDIOC_
1460/* for compatibility, will go away some day */ 1428/* for compatibility, will go away some day */
1461#define VIDIOC_OVERLAY_OLD _IOWR ('V', 14, int) 1429#define VIDIOC_OVERLAY_OLD _IOWR('V', 14, int)
1462#define VIDIOC_S_PARM_OLD _IOW ('V', 22, struct v4l2_streamparm) 1430#define VIDIOC_S_PARM_OLD _IOW('V', 22, struct v4l2_streamparm)
1463#define VIDIOC_S_CTRL_OLD _IOW ('V', 28, struct v4l2_control) 1431#define VIDIOC_S_CTRL_OLD _IOW('V', 28, struct v4l2_control)
1464#define VIDIOC_G_AUDIO_OLD _IOWR ('V', 33, struct v4l2_audio) 1432#define VIDIOC_G_AUDIO_OLD _IOWR('V', 33, struct v4l2_audio)
1465#define VIDIOC_G_AUDOUT_OLD _IOWR ('V', 49, struct v4l2_audioout) 1433#define VIDIOC_G_AUDOUT_OLD _IOWR('V', 49, struct v4l2_audioout)
1466#define VIDIOC_CROPCAP_OLD _IOR ('V', 58, struct v4l2_cropcap) 1434#define VIDIOC_CROPCAP_OLD _IOR('V', 58, struct v4l2_cropcap)
1467#endif 1435#endif
1468 1436
1469#define BASE_VIDIOC_PRIVATE 192 /* 192-255 are private */ 1437#define BASE_VIDIOC_PRIVATE 192 /* 192-255 are private */
1470 1438
1471#endif /* __LINUX_VIDEODEV2_H */ 1439#endif /* __LINUX_VIDEODEV2_H */
1472
1473/*
1474 * Local variables:
1475 * c-basic-offset: 8
1476 * End:
1477 */
diff --git a/include/linux/videotext.h b/include/linux/videotext.h
index 018f92047ff..3e68c8d1c7f 100644
--- a/include/linux/videotext.h
+++ b/include/linux/videotext.h
@@ -45,10 +45,10 @@
45#define VTXIOCCLRCACHE_OLD 0x710b /* clear cache on VTX-interface (if avail.) */ 45#define VTXIOCCLRCACHE_OLD 0x710b /* clear cache on VTX-interface (if avail.) */
46#define VTXIOCSETVIRT_OLD 0x710c /* turn on virtual mode (this disables TV-display) */ 46#define VTXIOCSETVIRT_OLD 0x710c /* turn on virtual mode (this disables TV-display) */
47 47
48/* 48/*
49 * Definitions for VTXIOCGETINFO 49 * Definitions for VTXIOCGETINFO
50 */ 50 */
51 51
52#define SAA5243 0 52#define SAA5243 0
53#define SAA5246 1 53#define SAA5246 1
54#define SAA5249 2 54#define SAA5249 2
@@ -57,10 +57,10 @@
57 57
58typedef struct { 58typedef struct {
59 int version_major, version_minor; /* version of driver; if version_major changes, driver */ 59 int version_major, version_minor; /* version of driver; if version_major changes, driver */
60 /* is not backward compatible!!! CHECK THIS!!! */ 60 /* is not backward compatible!!! CHECK THIS!!! */
61 int numpages; /* number of page-buffers of vtx-chipset */ 61 int numpages; /* number of page-buffers of vtx-chipset */
62 int cct_type; /* type of vtx-chipset (SAA5243, SAA5246, SAA5248 or 62 int cct_type; /* type of vtx-chipset (SAA5243, SAA5246, SAA5248 or
63 * SAA5249) */ 63 * SAA5249) */
64} 64}
65vtx_info_t; 65vtx_info_t;
66 66
@@ -81,7 +81,7 @@ vtx_info_t;
81#define PGMASK_HOUR (HR_TEN | HR_UNIT) 81#define PGMASK_HOUR (HR_TEN | HR_UNIT)
82#define PGMASK_MINUTE (MIN_TEN | MIN_UNIT) 82#define PGMASK_MINUTE (MIN_TEN | MIN_UNIT)
83 83
84typedef struct 84typedef struct
85{ 85{
86 int page; /* number of requested page (hexadecimal) */ 86 int page; /* number of requested page (hexadecimal) */
87 int hour; /* requested hour (hexadecimal) */ 87 int hour; /* requested hour (hexadecimal) */
@@ -98,11 +98,11 @@ vtx_pagereq_t;
98/* 98/*
99 * Definitions for VTXIOC{GETSTAT,PUTSTAT} 99 * Definitions for VTXIOC{GETSTAT,PUTSTAT}
100 */ 100 */
101 101
102#define VTX_PAGESIZE (40 * 24) 102#define VTX_PAGESIZE (40 * 24)
103#define VTX_VIRTUALSIZE (40 * 49) 103#define VTX_VIRTUALSIZE (40 * 49)
104 104
105typedef struct 105typedef struct
106{ 106{
107 int pagenum; /* number of page (hexadecimal) */ 107 int pagenum; /* number of page (hexadecimal) */
108 int hour; /* hour (hexadecimal) */ 108 int hour; /* hour (hexadecimal) */
@@ -121,5 +121,5 @@ typedef struct
121 unsigned hamming : 1; /* hamming-error occurred */ 121 unsigned hamming : 1; /* hamming-error occurred */
122} 122}
123vtx_pageinfo_t; 123vtx_pageinfo_t;
124 124
125#endif /* _VTX_H */ 125#endif /* _VTX_H */
diff --git a/include/linux/vt_kern.h b/include/linux/vt_kern.h
index 14c0e91be9b..1c78d56c57e 100644
--- a/include/linux/vt_kern.h
+++ b/include/linux/vt_kern.h
@@ -74,7 +74,7 @@ void con_protect_unimap(struct vc_data *vc, int rdonly);
74int con_copy_unimap(struct vc_data *dst_vc, struct vc_data *src_vc); 74int con_copy_unimap(struct vc_data *dst_vc, struct vc_data *src_vc);
75 75
76#define vc_translate(vc, c) ((vc)->vc_translate[(c) | \ 76#define vc_translate(vc, c) ((vc)->vc_translate[(c) | \
77 (vc)->vc_toggle_meta ? 0x80 : 0]) 77 ((vc)->vc_toggle_meta ? 0x80 : 0)])
78#else 78#else
79#define con_set_trans_old(arg) (0) 79#define con_set_trans_old(arg) (0)
80#define con_get_trans_old(arg) (-EINVAL) 80#define con_get_trans_old(arg) (-EINVAL)
@@ -86,6 +86,7 @@ int con_copy_unimap(struct vc_data *dst_vc, struct vc_data *src_vc);
86#define con_copy_unimap(d, s) (0) 86#define con_copy_unimap(d, s) (0)
87#define con_get_unimap(vc, ct, uct, list) (-EINVAL) 87#define con_get_unimap(vc, ct, uct, list) (-EINVAL)
88#define con_free_unimap(vc) do { ; } while (0) 88#define con_free_unimap(vc) do { ; } while (0)
89#define con_protect_unimap(vc, rdonly) do { ; } while (0)
89 90
90#define vc_translate(vc, c) (c) 91#define vc_translate(vc, c) (c)
91#endif 92#endif
diff --git a/include/media/audiochip.h b/include/media/audiochip.h
deleted file mode 100644
index db8823d45a7..00000000000
--- a/include/media/audiochip.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 */
3
4#ifndef AUDIOCHIP_H
5#define AUDIOCHIP_H
6
7enum audiochip {
8 AUDIO_CHIP_NONE,
9 AUDIO_CHIP_UNKNOWN,
10 /* Provided by video chip */
11 AUDIO_CHIP_INTERNAL,
12 /* Provided by tvaudio.c */
13 AUDIO_CHIP_TDA8425,
14 AUDIO_CHIP_TEA6300,
15 AUDIO_CHIP_TEA6420,
16 AUDIO_CHIP_TDA9840,
17 AUDIO_CHIP_TDA985X,
18 AUDIO_CHIP_TDA9874,
19 AUDIO_CHIP_PIC16C54,
20 /* Provided by msp3400.c */
21 AUDIO_CHIP_MSP34XX,
22 /* Provided by wm8775.c */
23 AUDIO_CHIP_WM8775
24};
25
26#endif /* AUDIOCHIP_H */
diff --git a/include/media/saa7146_vv.h b/include/media/saa7146_vv.h
index 89c442eb884..1d104096619 100644
--- a/include/media/saa7146_vv.h
+++ b/include/media/saa7146_vv.h
@@ -2,6 +2,7 @@
2#define __SAA7146_VV__ 2#define __SAA7146_VV__
3 3
4#include <media/v4l2-common.h> 4#include <media/v4l2-common.h>
5#include <media/v4l2-ioctl.h>
5#include <media/saa7146.h> 6#include <media/saa7146.h>
6#include <media/videobuf-dma-sg.h> 7#include <media/videobuf-dma-sg.h>
7 8
diff --git a/include/media/tveeprom.h b/include/media/tveeprom.h
index 5660ea24996..a8ad75a9152 100644
--- a/include/media/tveeprom.h
+++ b/include/media/tveeprom.h
@@ -3,7 +3,12 @@
3 3
4struct tveeprom { 4struct tveeprom {
5 u32 has_radio; 5 u32 has_radio;
6 u32 has_ir; /* bit 0: IR receiver present, bit 1: IR transmitter (blaster) present. -1 == unknown */ 6 /* If has_ir == 0, then it is unknown what the IR capabilities are,
7 otherwise:
8 bit 0: 1 (= IR capabilities are known)
9 bit 1: IR receiver present
10 bit 2: IR transmitter (blaster) present */
11 u32 has_ir;
7 u32 has_MAC_address; /* 0: no MAC, 1: MAC present, 2: unknown */ 12 u32 has_MAC_address; /* 0: no MAC, 1: MAC present, 2: unknown */
8 13
9 u32 tuner_type; 14 u32 tuner_type;
diff --git a/include/media/v4l2-chip-ident.h b/include/media/v4l2-chip-ident.h
index 2a527742701..41b509babf3 100644
--- a/include/media/v4l2-chip-ident.h
+++ b/include/media/v4l2-chip-ident.h
@@ -90,7 +90,10 @@ enum {
90 /* module m52790: just ident 52790 */ 90 /* module m52790: just ident 52790 */
91 V4L2_IDENT_M52790 = 52790, 91 V4L2_IDENT_M52790 = 52790,
92 92
93 /* module msp34xx: reserved range 34000-34999 */ 93 /* module msp3400: reserved range 34000-34999 and 44000-44999 */
94 V4L2_IDENT_MSPX4XX = 34000, /* generic MSPX4XX identifier, only
95 use internally (tveeprom.c). */
96
94 V4L2_IDENT_MSP3400B = 34002, 97 V4L2_IDENT_MSP3400B = 34002,
95 V4L2_IDENT_MSP3410B = 34102, 98 V4L2_IDENT_MSP3410B = 34102,
96 99
@@ -142,7 +145,7 @@ enum {
142 V4L2_IDENT_MSP3457G = 34577, 145 V4L2_IDENT_MSP3457G = 34577,
143 V4L2_IDENT_MSP3467G = 34677, 146 V4L2_IDENT_MSP3467G = 34677,
144 147
145 /* module msp44xx: reserved range 44000-44999 */ 148 /* module msp3400: reserved range 34000-34999 and 44000-44999 */
146 V4L2_IDENT_MSP4400G = 44007, 149 V4L2_IDENT_MSP4400G = 44007,
147 V4L2_IDENT_MSP4410G = 44107, 150 V4L2_IDENT_MSP4410G = 44107,
148 V4L2_IDENT_MSP4420G = 44207, 151 V4L2_IDENT_MSP4420G = 44207,
diff --git a/include/media/v4l2-common.h b/include/media/v4l2-common.h
index 020d05758bd..07d3a9a575d 100644
--- a/include/media/v4l2-common.h
+++ b/include/media/v4l2-common.h
@@ -28,12 +28,6 @@
28 28
29#include <media/v4l2-dev.h> 29#include <media/v4l2-dev.h>
30 30
31/* v4l debugging and diagnostics */
32
33/* Debug bitmask flags to be used on V4L2 */
34#define V4L2_DEBUG_IOCTL 0x01
35#define V4L2_DEBUG_IOCTL_ARG 0x02
36
37/* Common printk constucts for v4l-i2c drivers. These macros create a unique 31/* Common printk constucts for v4l-i2c drivers. These macros create a unique
38 prefix consisting of the driver name, the adapter number and the i2c 32 prefix consisting of the driver name, the adapter number and the i2c
39 address. */ 33 address. */
@@ -61,21 +55,20 @@
61 v4l_client_printk(KERN_DEBUG, client, fmt , ## arg); \ 55 v4l_client_printk(KERN_DEBUG, client, fmt , ## arg); \
62 } while (0) 56 } while (0)
63 57
58/* ------------------------------------------------------------------------- */
64 59
65/* Use this macro for non-I2C drivers. Pass the driver name as the first arg. */ 60/* Priority helper functions */
66#define v4l_print_ioctl(name, cmd) \
67 do { \
68 printk(KERN_DEBUG "%s: ", name); \
69 v4l_printk_ioctl(cmd); \
70 } while (0)
71 61
72/* Use this macro in I2C drivers where 'client' is the struct i2c_client 62struct v4l2_prio_state {
73 pointer */ 63 atomic_t prios[4];
74#define v4l_i2c_print_ioctl(client, cmd) \ 64};
75 do { \ 65int v4l2_prio_init(struct v4l2_prio_state *global);
76 v4l_client_printk(KERN_DEBUG, client, ""); \ 66int v4l2_prio_change(struct v4l2_prio_state *global, enum v4l2_priority *local,
77 v4l_printk_ioctl(cmd); \ 67 enum v4l2_priority new);
78 } while (0) 68int v4l2_prio_open(struct v4l2_prio_state *global, enum v4l2_priority *local);
69int v4l2_prio_close(struct v4l2_prio_state *global, enum v4l2_priority *local);
70enum v4l2_priority v4l2_prio_max(struct v4l2_prio_state *global);
71int v4l2_prio_check(struct v4l2_prio_state *global, enum v4l2_priority *local);
79 72
80/* ------------------------------------------------------------------------- */ 73/* ------------------------------------------------------------------------- */
81 74
diff --git a/include/media/v4l2-dev.h b/include/media/v4l2-dev.h
index 33f379b1ecf..2745e1afc72 100644
--- a/include/media/v4l2-dev.h
+++ b/include/media/v4l2-dev.h
@@ -9,7 +9,6 @@
9#ifndef _V4L2_DEV_H 9#ifndef _V4L2_DEV_H
10#define _V4L2_DEV_H 10#define _V4L2_DEV_H
11 11
12#define OBSOLETE_OWNER 1 /* to be removed soon */
13#define OBSOLETE_DEVDATA 1 /* to be removed soon */ 12#define OBSOLETE_DEVDATA 1 /* to be removed soon */
14 13
15#include <linux/poll.h> 14#include <linux/poll.h>
@@ -17,11 +16,7 @@
17#include <linux/device.h> 16#include <linux/device.h>
18#include <linux/mutex.h> 17#include <linux/mutex.h>
19#include <linux/compiler.h> /* need __user */ 18#include <linux/compiler.h> /* need __user */
20#ifdef CONFIG_VIDEO_V4L1_COMPAT
21#include <linux/videodev.h>
22#else
23#include <linux/videodev2.h> 19#include <linux/videodev2.h>
24#endif
25 20
26#define VIDEO_MAJOR 81 21#define VIDEO_MAJOR 81
27/* Minor device allocation */ 22/* Minor device allocation */
@@ -39,42 +34,7 @@
39#define VFL_TYPE_RADIO 2 34#define VFL_TYPE_RADIO 2
40#define VFL_TYPE_VTX 3 35#define VFL_TYPE_VTX 3
41 36
42/* Video standard functions */ 37struct v4l2_ioctl_callbacks;
43extern const char *v4l2_norm_to_name(v4l2_std_id id);
44extern int v4l2_video_std_construct(struct v4l2_standard *vs,
45 int id, const char *name);
46/* Prints the ioctl in a human-readable format */
47extern void v4l_printk_ioctl(unsigned int cmd);
48
49/* prority handling */
50struct v4l2_prio_state {
51 atomic_t prios[4];
52};
53int v4l2_prio_init(struct v4l2_prio_state *global);
54int v4l2_prio_change(struct v4l2_prio_state *global, enum v4l2_priority *local,
55 enum v4l2_priority new);
56int v4l2_prio_open(struct v4l2_prio_state *global, enum v4l2_priority *local);
57int v4l2_prio_close(struct v4l2_prio_state *global, enum v4l2_priority *local);
58enum v4l2_priority v4l2_prio_max(struct v4l2_prio_state *global);
59int v4l2_prio_check(struct v4l2_prio_state *global, enum v4l2_priority *local);
60
61/* names for fancy debug output */
62extern const char *v4l2_field_names[];
63extern const char *v4l2_type_names[];
64
65/* Compatibility layer interface -- v4l1-compat module */
66typedef int (*v4l2_kioctl)(struct inode *inode, struct file *file,
67 unsigned int cmd, void *arg);
68#ifdef CONFIG_VIDEO_V4L1_COMPAT
69int v4l_compat_translate_ioctl(struct inode *inode, struct file *file,
70 int cmd, void *arg, v4l2_kioctl driver_ioctl);
71#else
72#define v4l_compat_translate_ioctl(inode,file,cmd,arg,ioctl) -EINVAL
73#endif
74
75/* 32 Bits compatibility layer for 64 bits processors */
76extern long v4l_compat_ioctl32(struct file *file, unsigned int cmd,
77 unsigned long arg);
78 38
79/* 39/*
80 * Newer version of video_device, handled by videodev2.c 40 * Newer version of video_device, handled by videodev2.c
@@ -88,18 +48,17 @@ struct video_device
88 const struct file_operations *fops; 48 const struct file_operations *fops;
89 49
90 /* sysfs */ 50 /* sysfs */
91 struct device class_dev; /* v4l device */ 51 struct device dev; /* v4l device */
92 struct device *dev; /* device parent */ 52 struct device *parent; /* device parent */
93 53
94 /* device info */ 54 /* device info */
95 char name[32]; 55 char name[32];
96 int type; /* v4l1 */ 56 int vfl_type;
97 int type2; /* v4l2 */
98 int minor; 57 int minor;
99 /* attribute to diferentiate multiple indexs on one physical device */ 58 /* attribute to differentiate multiple indices on one physical device */
100 int index; 59 int index;
101 60
102 int debug; /* Activates debug level*/ 61 int debug; /* Activates debug level*/
103 62
104 /* Video standard vars */ 63 /* Video standard vars */
105 v4l2_std_id tvnorms; /* Supported tv norms */ 64 v4l2_std_id tvnorms; /* Supported tv norms */
@@ -109,285 +68,36 @@ struct video_device
109 void (*release)(struct video_device *vfd); 68 void (*release)(struct video_device *vfd);
110 69
111 /* ioctl callbacks */ 70 /* ioctl callbacks */
71 const struct v4l2_ioctl_ops *ioctl_ops;
112 72
113 /* VIDIOC_QUERYCAP handler */ 73#ifdef OBSOLETE_DEVDATA /* to be removed soon */
114 int (*vidioc_querycap)(struct file *file, void *fh, struct v4l2_capability *cap); 74 /* dev->driver_data will be used instead some day.
115 75 * Use the video_{get|set}_drvdata() helper functions,
116 /* Priority handling */ 76 * so the switch over will be transparent for you.
117 int (*vidioc_g_priority) (struct file *file, void *fh, 77 * Or use {pci|usb}_{get|set}_drvdata() directly. */
118 enum v4l2_priority *p); 78 void *priv;
119 int (*vidioc_s_priority) (struct file *file, void *fh,
120 enum v4l2_priority p);
121
122 /* VIDIOC_ENUM_FMT handlers */
123 int (*vidioc_enum_fmt_vid_cap) (struct file *file, void *fh,
124 struct v4l2_fmtdesc *f);
125 int (*vidioc_enum_fmt_vid_overlay) (struct file *file, void *fh,
126 struct v4l2_fmtdesc *f);
127 int (*vidioc_enum_fmt_vid_out) (struct file *file, void *fh,
128 struct v4l2_fmtdesc *f);
129#if 1
130 /* deprecated, will be removed in 2.6.28 */
131 int (*vidioc_enum_fmt_vbi_cap) (struct file *file, void *fh,
132 struct v4l2_fmtdesc *f);
133#endif
134 int (*vidioc_enum_fmt_type_private)(struct file *file, void *fh,
135 struct v4l2_fmtdesc *f);
136
137 /* VIDIOC_G_FMT handlers */
138 int (*vidioc_g_fmt_vid_cap) (struct file *file, void *fh,
139 struct v4l2_format *f);
140 int (*vidioc_g_fmt_vid_overlay)(struct file *file, void *fh,
141 struct v4l2_format *f);
142 int (*vidioc_g_fmt_vid_out) (struct file *file, void *fh,
143 struct v4l2_format *f);
144 int (*vidioc_g_fmt_vid_out_overlay)(struct file *file, void *fh,
145 struct v4l2_format *f);
146 int (*vidioc_g_fmt_vbi_cap) (struct file *file, void *fh,
147 struct v4l2_format *f);
148 int (*vidioc_g_fmt_vbi_out) (struct file *file, void *fh,
149 struct v4l2_format *f);
150 int (*vidioc_g_fmt_sliced_vbi_cap)(struct file *file, void *fh,
151 struct v4l2_format *f);
152 int (*vidioc_g_fmt_sliced_vbi_out)(struct file *file, void *fh,
153 struct v4l2_format *f);
154 int (*vidioc_g_fmt_type_private)(struct file *file, void *fh,
155 struct v4l2_format *f);
156
157 /* VIDIOC_S_FMT handlers */
158 int (*vidioc_s_fmt_vid_cap) (struct file *file, void *fh,
159 struct v4l2_format *f);
160 int (*vidioc_s_fmt_vid_overlay)(struct file *file, void *fh,
161 struct v4l2_format *f);
162 int (*vidioc_s_fmt_vid_out) (struct file *file, void *fh,
163 struct v4l2_format *f);
164 int (*vidioc_s_fmt_vid_out_overlay)(struct file *file, void *fh,
165 struct v4l2_format *f);
166 int (*vidioc_s_fmt_vbi_cap) (struct file *file, void *fh,
167 struct v4l2_format *f);
168 int (*vidioc_s_fmt_vbi_out) (struct file *file, void *fh,
169 struct v4l2_format *f);
170 int (*vidioc_s_fmt_sliced_vbi_cap)(struct file *file, void *fh,
171 struct v4l2_format *f);
172 int (*vidioc_s_fmt_sliced_vbi_out)(struct file *file, void *fh,
173 struct v4l2_format *f);
174 int (*vidioc_s_fmt_type_private)(struct file *file, void *fh,
175 struct v4l2_format *f);
176
177 /* VIDIOC_TRY_FMT handlers */
178 int (*vidioc_try_fmt_vid_cap) (struct file *file, void *fh,
179 struct v4l2_format *f);
180 int (*vidioc_try_fmt_vid_overlay)(struct file *file, void *fh,
181 struct v4l2_format *f);
182 int (*vidioc_try_fmt_vid_out) (struct file *file, void *fh,
183 struct v4l2_format *f);
184 int (*vidioc_try_fmt_vid_out_overlay)(struct file *file, void *fh,
185 struct v4l2_format *f);
186 int (*vidioc_try_fmt_vbi_cap) (struct file *file, void *fh,
187 struct v4l2_format *f);
188 int (*vidioc_try_fmt_vbi_out) (struct file *file, void *fh,
189 struct v4l2_format *f);
190 int (*vidioc_try_fmt_sliced_vbi_cap)(struct file *file, void *fh,
191 struct v4l2_format *f);
192 int (*vidioc_try_fmt_sliced_vbi_out)(struct file *file, void *fh,
193 struct v4l2_format *f);
194 int (*vidioc_try_fmt_type_private)(struct file *file, void *fh,
195 struct v4l2_format *f);
196
197 /* Buffer handlers */
198 int (*vidioc_reqbufs) (struct file *file, void *fh, struct v4l2_requestbuffers *b);
199 int (*vidioc_querybuf)(struct file *file, void *fh, struct v4l2_buffer *b);
200 int (*vidioc_qbuf) (struct file *file, void *fh, struct v4l2_buffer *b);
201 int (*vidioc_dqbuf) (struct file *file, void *fh, struct v4l2_buffer *b);
202
203
204 int (*vidioc_overlay) (struct file *file, void *fh, unsigned int i);
205#ifdef CONFIG_VIDEO_V4L1_COMPAT
206 /* buffer type is struct vidio_mbuf * */
207 int (*vidiocgmbuf) (struct file *file, void *fh, struct video_mbuf *p);
208#endif
209 int (*vidioc_g_fbuf) (struct file *file, void *fh,
210 struct v4l2_framebuffer *a);
211 int (*vidioc_s_fbuf) (struct file *file, void *fh,
212 struct v4l2_framebuffer *a);
213
214 /* Stream on/off */
215 int (*vidioc_streamon) (struct file *file, void *fh, enum v4l2_buf_type i);
216 int (*vidioc_streamoff)(struct file *file, void *fh, enum v4l2_buf_type i);
217
218 /* Standard handling
219 ENUMSTD is handled by videodev.c
220 */
221 int (*vidioc_g_std) (struct file *file, void *fh, v4l2_std_id *norm);
222 int (*vidioc_s_std) (struct file *file, void *fh, v4l2_std_id *norm);
223 int (*vidioc_querystd) (struct file *file, void *fh, v4l2_std_id *a);
224
225 /* Input handling */
226 int (*vidioc_enum_input)(struct file *file, void *fh,
227 struct v4l2_input *inp);
228 int (*vidioc_g_input) (struct file *file, void *fh, unsigned int *i);
229 int (*vidioc_s_input) (struct file *file, void *fh, unsigned int i);
230
231 /* Output handling */
232 int (*vidioc_enum_output) (struct file *file, void *fh,
233 struct v4l2_output *a);
234 int (*vidioc_g_output) (struct file *file, void *fh, unsigned int *i);
235 int (*vidioc_s_output) (struct file *file, void *fh, unsigned int i);
236
237 /* Control handling */
238 int (*vidioc_queryctrl) (struct file *file, void *fh,
239 struct v4l2_queryctrl *a);
240 int (*vidioc_g_ctrl) (struct file *file, void *fh,
241 struct v4l2_control *a);
242 int (*vidioc_s_ctrl) (struct file *file, void *fh,
243 struct v4l2_control *a);
244 int (*vidioc_g_ext_ctrls) (struct file *file, void *fh,
245 struct v4l2_ext_controls *a);
246 int (*vidioc_s_ext_ctrls) (struct file *file, void *fh,
247 struct v4l2_ext_controls *a);
248 int (*vidioc_try_ext_ctrls) (struct file *file, void *fh,
249 struct v4l2_ext_controls *a);
250 int (*vidioc_querymenu) (struct file *file, void *fh,
251 struct v4l2_querymenu *a);
252
253 /* Audio ioctls */
254 int (*vidioc_enumaudio) (struct file *file, void *fh,
255 struct v4l2_audio *a);
256 int (*vidioc_g_audio) (struct file *file, void *fh,
257 struct v4l2_audio *a);
258 int (*vidioc_s_audio) (struct file *file, void *fh,
259 struct v4l2_audio *a);
260
261 /* Audio out ioctls */
262 int (*vidioc_enumaudout) (struct file *file, void *fh,
263 struct v4l2_audioout *a);
264 int (*vidioc_g_audout) (struct file *file, void *fh,
265 struct v4l2_audioout *a);
266 int (*vidioc_s_audout) (struct file *file, void *fh,
267 struct v4l2_audioout *a);
268 int (*vidioc_g_modulator) (struct file *file, void *fh,
269 struct v4l2_modulator *a);
270 int (*vidioc_s_modulator) (struct file *file, void *fh,
271 struct v4l2_modulator *a);
272 /* Crop ioctls */
273 int (*vidioc_cropcap) (struct file *file, void *fh,
274 struct v4l2_cropcap *a);
275 int (*vidioc_g_crop) (struct file *file, void *fh,
276 struct v4l2_crop *a);
277 int (*vidioc_s_crop) (struct file *file, void *fh,
278 struct v4l2_crop *a);
279 /* Compression ioctls */
280 int (*vidioc_g_jpegcomp) (struct file *file, void *fh,
281 struct v4l2_jpegcompression *a);
282 int (*vidioc_s_jpegcomp) (struct file *file, void *fh,
283 struct v4l2_jpegcompression *a);
284 int (*vidioc_g_enc_index) (struct file *file, void *fh,
285 struct v4l2_enc_idx *a);
286 int (*vidioc_encoder_cmd) (struct file *file, void *fh,
287 struct v4l2_encoder_cmd *a);
288 int (*vidioc_try_encoder_cmd) (struct file *file, void *fh,
289 struct v4l2_encoder_cmd *a);
290
291 /* Stream type-dependent parameter ioctls */
292 int (*vidioc_g_parm) (struct file *file, void *fh,
293 struct v4l2_streamparm *a);
294 int (*vidioc_s_parm) (struct file *file, void *fh,
295 struct v4l2_streamparm *a);
296
297 /* Tuner ioctls */
298 int (*vidioc_g_tuner) (struct file *file, void *fh,
299 struct v4l2_tuner *a);
300 int (*vidioc_s_tuner) (struct file *file, void *fh,
301 struct v4l2_tuner *a);
302 int (*vidioc_g_frequency) (struct file *file, void *fh,
303 struct v4l2_frequency *a);
304 int (*vidioc_s_frequency) (struct file *file, void *fh,
305 struct v4l2_frequency *a);
306
307 /* Sliced VBI cap */
308 int (*vidioc_g_sliced_vbi_cap) (struct file *file, void *fh,
309 struct v4l2_sliced_vbi_cap *a);
310
311 /* Log status ioctl */
312 int (*vidioc_log_status) (struct file *file, void *fh);
313
314 int (*vidioc_s_hw_freq_seek) (struct file *file, void *fh,
315 struct v4l2_hw_freq_seek *a);
316
317 /* Debugging ioctls */
318#ifdef CONFIG_VIDEO_ADV_DEBUG
319 int (*vidioc_g_register) (struct file *file, void *fh,
320 struct v4l2_register *reg);
321 int (*vidioc_s_register) (struct file *file, void *fh,
322 struct v4l2_register *reg);
323#endif
324 int (*vidioc_g_chip_ident) (struct file *file, void *fh,
325 struct v4l2_chip_ident *chip);
326
327 /* For other private ioctls */
328 int (*vidioc_default) (struct file *file, void *fh,
329 int cmd, void *arg);
330
331
332#ifdef OBSOLETE_OWNER /* to be removed soon */
333/* obsolete -- fops->owner is used instead */
334struct module *owner;
335/* dev->driver_data will be used instead some day.
336 * Use the video_{get|set}_drvdata() helper functions,
337 * so the switch over will be transparent for you.
338 * Or use {pci|usb}_{get|set}_drvdata() directly. */
339void *priv;
340#endif 79#endif
341 80
342 /* for videodev.c intenal usage -- please don't touch */ 81 /* for videodev.c internal usage -- please don't touch */
343 int users; /* video_exclusive_{open|close} ... */ 82 int users; /* video_exclusive_{open|close} ... */
344 struct mutex lock; /* ... helper function uses these */ 83 struct mutex lock; /* ... helper function uses these */
345}; 84};
346 85
347/* Class-dev to video-device */ 86/* Class-dev to video-device */
348#define to_video_device(cd) container_of(cd, struct video_device, class_dev) 87#define to_video_device(cd) container_of(cd, struct video_device, dev)
349 88
350/* Version 2 functions */ 89/* Version 2 functions */
351extern int video_register_device(struct video_device *vfd, int type, int nr); 90extern int video_register_device(struct video_device *vfd, int type, int nr);
352int video_register_device_index(struct video_device *vfd, int type, int nr, 91int video_register_device_index(struct video_device *vfd, int type, int nr,
353 int index); 92 int index);
354void video_unregister_device(struct video_device *); 93void video_unregister_device(struct video_device *);
355extern int video_ioctl2(struct inode *inode, struct file *file,
356 unsigned int cmd, unsigned long arg);
357 94
358/* helper functions to alloc / release struct video_device, the 95/* helper functions to alloc / release struct video_device, the
359 later can be used for video_device->release() */ 96 later can be used for video_device->release() */
360struct video_device *video_device_alloc(void); 97struct video_device *video_device_alloc(void);
361void video_device_release(struct video_device *vfd); 98void video_device_release(struct video_device *vfd);
362 99
363/* Include support for obsoleted stuff */ 100#ifdef OBSOLETE_DEVDATA /* to be removed soon */
364extern int video_usercopy(struct inode *inode, struct file *file,
365 unsigned int cmd, unsigned long arg,
366 int (*func)(struct inode *inode, struct file *file,
367 unsigned int cmd, void *arg));
368
369#ifdef CONFIG_VIDEO_V4L1_COMPAT
370#include <linux/mm.h>
371
372static inline int __must_check
373video_device_create_file(struct video_device *vfd,
374 struct device_attribute *attr)
375{
376 int ret = device_create_file(&vfd->class_dev, attr);
377 if (ret < 0)
378 printk(KERN_WARNING "%s error: %d\n", __func__, ret);
379 return ret;
380}
381static inline void
382video_device_remove_file(struct video_device *vfd,
383 struct device_attribute *attr)
384{
385 device_remove_file(&vfd->class_dev, attr);
386}
387
388#endif /* CONFIG_VIDEO_V4L1_COMPAT */
389
390#ifdef OBSOLETE_OWNER /* to be removed soon */
391/* helper functions to access driver private data. */ 101/* helper functions to access driver private data. */
392static inline void *video_get_drvdata(struct video_device *dev) 102static inline void *video_get_drvdata(struct video_device *dev)
393{ 103{
@@ -399,9 +109,6 @@ static inline void video_set_drvdata(struct video_device *dev, void *data)
399 dev->priv = data; 109 dev->priv = data;
400} 110}
401 111
402#endif
403
404#ifdef OBSOLETE_DEVDATA /* to be removed soon */
405/* Obsolete stuff - Still needed for radio devices and obsolete drivers */ 112/* Obsolete stuff - Still needed for radio devices and obsolete drivers */
406extern struct video_device* video_devdata(struct file*); 113extern struct video_device* video_devdata(struct file*);
407extern int video_exclusive_open(struct inode *inode, struct file *file); 114extern int video_exclusive_open(struct inode *inode, struct file *file);
diff --git a/include/media/v4l2-ioctl.h b/include/media/v4l2-ioctl.h
new file mode 100644
index 00000000000..dc640461855
--- /dev/null
+++ b/include/media/v4l2-ioctl.h
@@ -0,0 +1,301 @@
1/*
2 *
3 * V 4 L 2 D R I V E R H E L P E R A P I
4 *
5 * Moved from videodev2.h
6 *
7 * Some commonly needed functions for drivers (v4l2-common.o module)
8 */
9#ifndef _V4L2_IOCTL_H
10#define _V4L2_IOCTL_H
11
12#include <linux/poll.h>
13#include <linux/fs.h>
14#include <linux/device.h>
15#include <linux/mutex.h>
16#include <linux/compiler.h> /* need __user */
17#ifdef CONFIG_VIDEO_V4L1_COMPAT
18#include <linux/videodev.h>
19#else
20#include <linux/videodev2.h>
21#endif
22
23struct v4l2_ioctl_ops {
24 /* ioctl callbacks */
25
26 /* VIDIOC_QUERYCAP handler */
27 int (*vidioc_querycap)(struct file *file, void *fh, struct v4l2_capability *cap);
28
29 /* Priority handling */
30 int (*vidioc_g_priority) (struct file *file, void *fh,
31 enum v4l2_priority *p);
32 int (*vidioc_s_priority) (struct file *file, void *fh,
33 enum v4l2_priority p);
34
35 /* VIDIOC_ENUM_FMT handlers */
36 int (*vidioc_enum_fmt_vid_cap) (struct file *file, void *fh,
37 struct v4l2_fmtdesc *f);
38 int (*vidioc_enum_fmt_vid_overlay) (struct file *file, void *fh,
39 struct v4l2_fmtdesc *f);
40 int (*vidioc_enum_fmt_vid_out) (struct file *file, void *fh,
41 struct v4l2_fmtdesc *f);
42#if 1
43 /* deprecated, will be removed in 2.6.28 */
44 int (*vidioc_enum_fmt_vbi_cap) (struct file *file, void *fh,
45 struct v4l2_fmtdesc *f);
46#endif
47 int (*vidioc_enum_fmt_type_private)(struct file *file, void *fh,
48 struct v4l2_fmtdesc *f);
49
50 /* VIDIOC_G_FMT handlers */
51 int (*vidioc_g_fmt_vid_cap) (struct file *file, void *fh,
52 struct v4l2_format *f);
53 int (*vidioc_g_fmt_vid_overlay)(struct file *file, void *fh,
54 struct v4l2_format *f);
55 int (*vidioc_g_fmt_vid_out) (struct file *file, void *fh,
56 struct v4l2_format *f);
57 int (*vidioc_g_fmt_vid_out_overlay)(struct file *file, void *fh,
58 struct v4l2_format *f);
59 int (*vidioc_g_fmt_vbi_cap) (struct file *file, void *fh,
60 struct v4l2_format *f);
61 int (*vidioc_g_fmt_vbi_out) (struct file *file, void *fh,
62 struct v4l2_format *f);
63 int (*vidioc_g_fmt_sliced_vbi_cap)(struct file *file, void *fh,
64 struct v4l2_format *f);
65 int (*vidioc_g_fmt_sliced_vbi_out)(struct file *file, void *fh,
66 struct v4l2_format *f);
67 int (*vidioc_g_fmt_type_private)(struct file *file, void *fh,
68 struct v4l2_format *f);
69
70 /* VIDIOC_S_FMT handlers */
71 int (*vidioc_s_fmt_vid_cap) (struct file *file, void *fh,
72 struct v4l2_format *f);
73 int (*vidioc_s_fmt_vid_overlay)(struct file *file, void *fh,
74 struct v4l2_format *f);
75 int (*vidioc_s_fmt_vid_out) (struct file *file, void *fh,
76 struct v4l2_format *f);
77 int (*vidioc_s_fmt_vid_out_overlay)(struct file *file, void *fh,
78 struct v4l2_format *f);
79 int (*vidioc_s_fmt_vbi_cap) (struct file *file, void *fh,
80 struct v4l2_format *f);
81 int (*vidioc_s_fmt_vbi_out) (struct file *file, void *fh,
82 struct v4l2_format *f);
83 int (*vidioc_s_fmt_sliced_vbi_cap)(struct file *file, void *fh,
84 struct v4l2_format *f);
85 int (*vidioc_s_fmt_sliced_vbi_out)(struct file *file, void *fh,
86 struct v4l2_format *f);
87 int (*vidioc_s_fmt_type_private)(struct file *file, void *fh,
88 struct v4l2_format *f);
89
90 /* VIDIOC_TRY_FMT handlers */
91 int (*vidioc_try_fmt_vid_cap) (struct file *file, void *fh,
92 struct v4l2_format *f);
93 int (*vidioc_try_fmt_vid_overlay)(struct file *file, void *fh,
94 struct v4l2_format *f);
95 int (*vidioc_try_fmt_vid_out) (struct file *file, void *fh,
96 struct v4l2_format *f);
97 int (*vidioc_try_fmt_vid_out_overlay)(struct file *file, void *fh,
98 struct v4l2_format *f);
99 int (*vidioc_try_fmt_vbi_cap) (struct file *file, void *fh,
100 struct v4l2_format *f);
101 int (*vidioc_try_fmt_vbi_out) (struct file *file, void *fh,
102 struct v4l2_format *f);
103 int (*vidioc_try_fmt_sliced_vbi_cap)(struct file *file, void *fh,
104 struct v4l2_format *f);
105 int (*vidioc_try_fmt_sliced_vbi_out)(struct file *file, void *fh,
106 struct v4l2_format *f);
107 int (*vidioc_try_fmt_type_private)(struct file *file, void *fh,
108 struct v4l2_format *f);
109
110 /* Buffer handlers */
111 int (*vidioc_reqbufs) (struct file *file, void *fh, struct v4l2_requestbuffers *b);
112 int (*vidioc_querybuf)(struct file *file, void *fh, struct v4l2_buffer *b);
113 int (*vidioc_qbuf) (struct file *file, void *fh, struct v4l2_buffer *b);
114 int (*vidioc_dqbuf) (struct file *file, void *fh, struct v4l2_buffer *b);
115
116
117 int (*vidioc_overlay) (struct file *file, void *fh, unsigned int i);
118#ifdef CONFIG_VIDEO_V4L1_COMPAT
119 /* buffer type is struct vidio_mbuf * */
120 int (*vidiocgmbuf) (struct file *file, void *fh, struct video_mbuf *p);
121#endif
122 int (*vidioc_g_fbuf) (struct file *file, void *fh,
123 struct v4l2_framebuffer *a);
124 int (*vidioc_s_fbuf) (struct file *file, void *fh,
125 struct v4l2_framebuffer *a);
126
127 /* Stream on/off */
128 int (*vidioc_streamon) (struct file *file, void *fh, enum v4l2_buf_type i);
129 int (*vidioc_streamoff)(struct file *file, void *fh, enum v4l2_buf_type i);
130
131 /* Standard handling
132 ENUMSTD is handled by videodev.c
133 */
134 int (*vidioc_g_std) (struct file *file, void *fh, v4l2_std_id *norm);
135 int (*vidioc_s_std) (struct file *file, void *fh, v4l2_std_id *norm);
136 int (*vidioc_querystd) (struct file *file, void *fh, v4l2_std_id *a);
137
138 /* Input handling */
139 int (*vidioc_enum_input)(struct file *file, void *fh,
140 struct v4l2_input *inp);
141 int (*vidioc_g_input) (struct file *file, void *fh, unsigned int *i);
142 int (*vidioc_s_input) (struct file *file, void *fh, unsigned int i);
143
144 /* Output handling */
145 int (*vidioc_enum_output) (struct file *file, void *fh,
146 struct v4l2_output *a);
147 int (*vidioc_g_output) (struct file *file, void *fh, unsigned int *i);
148 int (*vidioc_s_output) (struct file *file, void *fh, unsigned int i);
149
150 /* Control handling */
151 int (*vidioc_queryctrl) (struct file *file, void *fh,
152 struct v4l2_queryctrl *a);
153 int (*vidioc_g_ctrl) (struct file *file, void *fh,
154 struct v4l2_control *a);
155 int (*vidioc_s_ctrl) (struct file *file, void *fh,
156 struct v4l2_control *a);
157 int (*vidioc_g_ext_ctrls) (struct file *file, void *fh,
158 struct v4l2_ext_controls *a);
159 int (*vidioc_s_ext_ctrls) (struct file *file, void *fh,
160 struct v4l2_ext_controls *a);
161 int (*vidioc_try_ext_ctrls) (struct file *file, void *fh,
162 struct v4l2_ext_controls *a);
163 int (*vidioc_querymenu) (struct file *file, void *fh,
164 struct v4l2_querymenu *a);
165
166 /* Audio ioctls */
167 int (*vidioc_enumaudio) (struct file *file, void *fh,
168 struct v4l2_audio *a);
169 int (*vidioc_g_audio) (struct file *file, void *fh,
170 struct v4l2_audio *a);
171 int (*vidioc_s_audio) (struct file *file, void *fh,
172 struct v4l2_audio *a);
173
174 /* Audio out ioctls */
175 int (*vidioc_enumaudout) (struct file *file, void *fh,
176 struct v4l2_audioout *a);
177 int (*vidioc_g_audout) (struct file *file, void *fh,
178 struct v4l2_audioout *a);
179 int (*vidioc_s_audout) (struct file *file, void *fh,
180 struct v4l2_audioout *a);
181 int (*vidioc_g_modulator) (struct file *file, void *fh,
182 struct v4l2_modulator *a);
183 int (*vidioc_s_modulator) (struct file *file, void *fh,
184 struct v4l2_modulator *a);
185 /* Crop ioctls */
186 int (*vidioc_cropcap) (struct file *file, void *fh,
187 struct v4l2_cropcap *a);
188 int (*vidioc_g_crop) (struct file *file, void *fh,
189 struct v4l2_crop *a);
190 int (*vidioc_s_crop) (struct file *file, void *fh,
191 struct v4l2_crop *a);
192 /* Compression ioctls */
193 int (*vidioc_g_jpegcomp) (struct file *file, void *fh,
194 struct v4l2_jpegcompression *a);
195 int (*vidioc_s_jpegcomp) (struct file *file, void *fh,
196 struct v4l2_jpegcompression *a);
197 int (*vidioc_g_enc_index) (struct file *file, void *fh,
198 struct v4l2_enc_idx *a);
199 int (*vidioc_encoder_cmd) (struct file *file, void *fh,
200 struct v4l2_encoder_cmd *a);
201 int (*vidioc_try_encoder_cmd) (struct file *file, void *fh,
202 struct v4l2_encoder_cmd *a);
203
204 /* Stream type-dependent parameter ioctls */
205 int (*vidioc_g_parm) (struct file *file, void *fh,
206 struct v4l2_streamparm *a);
207 int (*vidioc_s_parm) (struct file *file, void *fh,
208 struct v4l2_streamparm *a);
209
210 /* Tuner ioctls */
211 int (*vidioc_g_tuner) (struct file *file, void *fh,
212 struct v4l2_tuner *a);
213 int (*vidioc_s_tuner) (struct file *file, void *fh,
214 struct v4l2_tuner *a);
215 int (*vidioc_g_frequency) (struct file *file, void *fh,
216 struct v4l2_frequency *a);
217 int (*vidioc_s_frequency) (struct file *file, void *fh,
218 struct v4l2_frequency *a);
219
220 /* Sliced VBI cap */
221 int (*vidioc_g_sliced_vbi_cap) (struct file *file, void *fh,
222 struct v4l2_sliced_vbi_cap *a);
223
224 /* Log status ioctl */
225 int (*vidioc_log_status) (struct file *file, void *fh);
226
227 int (*vidioc_s_hw_freq_seek) (struct file *file, void *fh,
228 struct v4l2_hw_freq_seek *a);
229
230 /* Debugging ioctls */
231#ifdef CONFIG_VIDEO_ADV_DEBUG
232 int (*vidioc_g_register) (struct file *file, void *fh,
233 struct v4l2_register *reg);
234 int (*vidioc_s_register) (struct file *file, void *fh,
235 struct v4l2_register *reg);
236#endif
237 int (*vidioc_g_chip_ident) (struct file *file, void *fh,
238 struct v4l2_chip_ident *chip);
239
240 /* For other private ioctls */
241 int (*vidioc_default) (struct file *file, void *fh,
242 int cmd, void *arg);
243};
244
245
246/* v4l debugging and diagnostics */
247
248/* Debug bitmask flags to be used on V4L2 */
249#define V4L2_DEBUG_IOCTL 0x01
250#define V4L2_DEBUG_IOCTL_ARG 0x02
251
252/* Use this macro for non-I2C drivers. Pass the driver name as the first arg. */
253#define v4l_print_ioctl(name, cmd) \
254 do { \
255 printk(KERN_DEBUG "%s: ", name); \
256 v4l_printk_ioctl(cmd); \
257 } while (0)
258
259/* Use this macro in I2C drivers where 'client' is the struct i2c_client
260 pointer */
261#define v4l_i2c_print_ioctl(client, cmd) \
262 do { \
263 v4l_client_printk(KERN_DEBUG, client, ""); \
264 v4l_printk_ioctl(cmd); \
265 } while (0)
266
267/* Video standard functions */
268extern const char *v4l2_norm_to_name(v4l2_std_id id);
269extern int v4l2_video_std_construct(struct v4l2_standard *vs,
270 int id, const char *name);
271/* Prints the ioctl in a human-readable format */
272extern void v4l_printk_ioctl(unsigned int cmd);
273
274/* names for fancy debug output */
275extern const char *v4l2_field_names[];
276extern const char *v4l2_type_names[];
277
278/* Compatibility layer interface -- v4l1-compat module */
279typedef int (*v4l2_kioctl)(struct inode *inode, struct file *file,
280 unsigned int cmd, void *arg);
281#ifdef CONFIG_VIDEO_V4L1_COMPAT
282int v4l_compat_translate_ioctl(struct inode *inode, struct file *file,
283 int cmd, void *arg, v4l2_kioctl driver_ioctl);
284#else
285#define v4l_compat_translate_ioctl(inode, file, cmd, arg, ioctl) (-EINVAL)
286#endif
287
288/* 32 Bits compatibility layer for 64 bits processors */
289extern long v4l_compat_ioctl32(struct file *file, unsigned int cmd,
290 unsigned long arg);
291
292extern int video_ioctl2(struct inode *inode, struct file *file,
293 unsigned int cmd, unsigned long arg);
294
295/* Include support for obsoleted stuff */
296extern int video_usercopy(struct inode *inode, struct file *file,
297 unsigned int cmd, unsigned long arg,
298 int (*func)(struct inode *inode, struct file *file,
299 unsigned int cmd, void *arg));
300
301#endif /* _V4L2_IOCTL_H */
diff --git a/include/net/dst.h b/include/net/dst.h
index c5c318a628f..8a8b71e5f3f 100644
--- a/include/net/dst.h
+++ b/include/net/dst.h
@@ -252,17 +252,7 @@ static inline int dst_output(struct sk_buff *skb)
252/* Input packet from network to transport. */ 252/* Input packet from network to transport. */
253static inline int dst_input(struct sk_buff *skb) 253static inline int dst_input(struct sk_buff *skb)
254{ 254{
255 int err; 255 return skb->dst->input(skb);
256
257 for (;;) {
258 err = skb->dst->input(skb);
259
260 if (likely(err == 0))
261 return err;
262 /* Oh, Jamal... Seems, I will not forgive you this mess. :-) */
263 if (unlikely(err != NET_XMIT_BYPASS))
264 return err;
265 }
266} 256}
267 257
268static inline struct dst_entry *dst_check(struct dst_entry *dst, u32 cookie) 258static inline struct dst_entry *dst_check(struct dst_entry *dst, u32 cookie)
diff --git a/include/net/flow.h b/include/net/flow.h
index ad16e0076c8..228b2477cee 100644
--- a/include/net/flow.h
+++ b/include/net/flow.h
@@ -47,7 +47,6 @@ struct flowi {
47#define fl4_scope nl_u.ip4_u.scope 47#define fl4_scope nl_u.ip4_u.scope
48 48
49 __u8 proto; 49 __u8 proto;
50 __u8 flags;
51 union { 50 union {
52 struct { 51 struct {
53 __be16 sport; 52 __be16 sport;
diff --git a/include/net/ip_vs.h b/include/net/ip_vs.h
index 9a51ebad3f1..cbb59ebed4a 100644
--- a/include/net/ip_vs.h
+++ b/include/net/ip_vs.h
@@ -3,254 +3,17 @@
3 * data structure and functionality definitions 3 * data structure and functionality definitions
4 */ 4 */
5 5
6#ifndef _IP_VS_H 6#ifndef _NET_IP_VS_H
7#define _IP_VS_H 7#define _NET_IP_VS_H
8
9#include <asm/types.h> /* For __uXX types */
10#include <linux/types.h> /* For __beXX types in userland */
11
12#include <linux/sysctl.h> /* For ctl_path */
13
14#define IP_VS_VERSION_CODE 0x010201
15#define NVERSION(version) \
16 (version >> 16) & 0xFF, \
17 (version >> 8) & 0xFF, \
18 version & 0xFF
19
20/*
21 * Virtual Service Flags
22 */
23#define IP_VS_SVC_F_PERSISTENT 0x0001 /* persistent port */
24#define IP_VS_SVC_F_HASHED 0x0002 /* hashed entry */
25
26/*
27 * Destination Server Flags
28 */
29#define IP_VS_DEST_F_AVAILABLE 0x0001 /* server is available */
30#define IP_VS_DEST_F_OVERLOAD 0x0002 /* server is overloaded */
31
32/*
33 * IPVS sync daemon states
34 */
35#define IP_VS_STATE_NONE 0x0000 /* daemon is stopped */
36#define IP_VS_STATE_MASTER 0x0001 /* started as master */
37#define IP_VS_STATE_BACKUP 0x0002 /* started as backup */
38
39/*
40 * IPVS socket options
41 */
42#define IP_VS_BASE_CTL (64+1024+64) /* base */
43
44#define IP_VS_SO_SET_NONE IP_VS_BASE_CTL /* just peek */
45#define IP_VS_SO_SET_INSERT (IP_VS_BASE_CTL+1)
46#define IP_VS_SO_SET_ADD (IP_VS_BASE_CTL+2)
47#define IP_VS_SO_SET_EDIT (IP_VS_BASE_CTL+3)
48#define IP_VS_SO_SET_DEL (IP_VS_BASE_CTL+4)
49#define IP_VS_SO_SET_FLUSH (IP_VS_BASE_CTL+5)
50#define IP_VS_SO_SET_LIST (IP_VS_BASE_CTL+6)
51#define IP_VS_SO_SET_ADDDEST (IP_VS_BASE_CTL+7)
52#define IP_VS_SO_SET_DELDEST (IP_VS_BASE_CTL+8)
53#define IP_VS_SO_SET_EDITDEST (IP_VS_BASE_CTL+9)
54#define IP_VS_SO_SET_TIMEOUT (IP_VS_BASE_CTL+10)
55#define IP_VS_SO_SET_STARTDAEMON (IP_VS_BASE_CTL+11)
56#define IP_VS_SO_SET_STOPDAEMON (IP_VS_BASE_CTL+12)
57#define IP_VS_SO_SET_RESTORE (IP_VS_BASE_CTL+13)
58#define IP_VS_SO_SET_SAVE (IP_VS_BASE_CTL+14)
59#define IP_VS_SO_SET_ZERO (IP_VS_BASE_CTL+15)
60#define IP_VS_SO_SET_MAX IP_VS_SO_SET_ZERO
61
62#define IP_VS_SO_GET_VERSION IP_VS_BASE_CTL
63#define IP_VS_SO_GET_INFO (IP_VS_BASE_CTL+1)
64#define IP_VS_SO_GET_SERVICES (IP_VS_BASE_CTL+2)
65#define IP_VS_SO_GET_SERVICE (IP_VS_BASE_CTL+3)
66#define IP_VS_SO_GET_DESTS (IP_VS_BASE_CTL+4)
67#define IP_VS_SO_GET_DEST (IP_VS_BASE_CTL+5) /* not used now */
68#define IP_VS_SO_GET_TIMEOUT (IP_VS_BASE_CTL+6)
69#define IP_VS_SO_GET_DAEMON (IP_VS_BASE_CTL+7)
70#define IP_VS_SO_GET_MAX IP_VS_SO_GET_DAEMON
71
72
73/*
74 * IPVS Connection Flags
75 */
76#define IP_VS_CONN_F_FWD_MASK 0x0007 /* mask for the fwd methods */
77#define IP_VS_CONN_F_MASQ 0x0000 /* masquerading/NAT */
78#define IP_VS_CONN_F_LOCALNODE 0x0001 /* local node */
79#define IP_VS_CONN_F_TUNNEL 0x0002 /* tunneling */
80#define IP_VS_CONN_F_DROUTE 0x0003 /* direct routing */
81#define IP_VS_CONN_F_BYPASS 0x0004 /* cache bypass */
82#define IP_VS_CONN_F_SYNC 0x0020 /* entry created by sync */
83#define IP_VS_CONN_F_HASHED 0x0040 /* hashed entry */
84#define IP_VS_CONN_F_NOOUTPUT 0x0080 /* no output packets */
85#define IP_VS_CONN_F_INACTIVE 0x0100 /* not established */
86#define IP_VS_CONN_F_OUT_SEQ 0x0200 /* must do output seq adjust */
87#define IP_VS_CONN_F_IN_SEQ 0x0400 /* must do input seq adjust */
88#define IP_VS_CONN_F_SEQ_MASK 0x0600 /* in/out sequence mask */
89#define IP_VS_CONN_F_NO_CPORT 0x0800 /* no client port set yet */
90#define IP_VS_CONN_F_TEMPLATE 0x1000 /* template, not connection */
91
92/* Move it to better place one day, for now keep it unique */
93#define NFC_IPVS_PROPERTY 0x10000
94
95#define IP_VS_SCHEDNAME_MAXLEN 16
96#define IP_VS_IFNAME_MAXLEN 16
97
98
99/*
100 * The struct ip_vs_service_user and struct ip_vs_dest_user are
101 * used to set IPVS rules through setsockopt.
102 */
103struct ip_vs_service_user {
104 /* virtual service addresses */
105 u_int16_t protocol;
106 __be32 addr; /* virtual ip address */
107 __be16 port;
108 u_int32_t fwmark; /* firwall mark of service */
109
110 /* virtual service options */
111 char sched_name[IP_VS_SCHEDNAME_MAXLEN];
112 unsigned flags; /* virtual service flags */
113 unsigned timeout; /* persistent timeout in sec */
114 __be32 netmask; /* persistent netmask */
115};
116
117
118struct ip_vs_dest_user {
119 /* destination server address */
120 __be32 addr;
121 __be16 port;
122
123 /* real server options */
124 unsigned conn_flags; /* connection flags */
125 int weight; /* destination weight */
126
127 /* thresholds for active connections */
128 u_int32_t u_threshold; /* upper threshold */
129 u_int32_t l_threshold; /* lower threshold */
130};
131
132
133/*
134 * IPVS statistics object (for user space)
135 */
136struct ip_vs_stats_user
137{
138 __u32 conns; /* connections scheduled */
139 __u32 inpkts; /* incoming packets */
140 __u32 outpkts; /* outgoing packets */
141 __u64 inbytes; /* incoming bytes */
142 __u64 outbytes; /* outgoing bytes */
143
144 __u32 cps; /* current connection rate */
145 __u32 inpps; /* current in packet rate */
146 __u32 outpps; /* current out packet rate */
147 __u32 inbps; /* current in byte rate */
148 __u32 outbps; /* current out byte rate */
149};
150
151
152/* The argument to IP_VS_SO_GET_INFO */
153struct ip_vs_getinfo {
154 /* version number */
155 unsigned int version;
156
157 /* size of connection hash table */
158 unsigned int size;
159
160 /* number of virtual services */
161 unsigned int num_services;
162};
163
164
165/* The argument to IP_VS_SO_GET_SERVICE */
166struct ip_vs_service_entry {
167 /* which service: user fills in these */
168 u_int16_t protocol;
169 __be32 addr; /* virtual address */
170 __be16 port;
171 u_int32_t fwmark; /* firwall mark of service */
172
173 /* service options */
174 char sched_name[IP_VS_SCHEDNAME_MAXLEN];
175 unsigned flags; /* virtual service flags */
176 unsigned timeout; /* persistent timeout */
177 __be32 netmask; /* persistent netmask */
178
179 /* number of real servers */
180 unsigned int num_dests;
181
182 /* statistics */
183 struct ip_vs_stats_user stats;
184};
185
186
187struct ip_vs_dest_entry {
188 __be32 addr; /* destination address */
189 __be16 port;
190 unsigned conn_flags; /* connection flags */
191 int weight; /* destination weight */
192
193 u_int32_t u_threshold; /* upper threshold */
194 u_int32_t l_threshold; /* lower threshold */
195
196 u_int32_t activeconns; /* active connections */
197 u_int32_t inactconns; /* inactive connections */
198 u_int32_t persistconns; /* persistent connections */
199
200 /* statistics */
201 struct ip_vs_stats_user stats;
202};
203
204
205/* The argument to IP_VS_SO_GET_DESTS */
206struct ip_vs_get_dests {
207 /* which service: user fills in these */
208 u_int16_t protocol;
209 __be32 addr; /* virtual address */
210 __be16 port;
211 u_int32_t fwmark; /* firwall mark of service */
212
213 /* number of real servers */
214 unsigned int num_dests;
215
216 /* the real servers */
217 struct ip_vs_dest_entry entrytable[0];
218};
219
220
221/* The argument to IP_VS_SO_GET_SERVICES */
222struct ip_vs_get_services {
223 /* number of virtual services */
224 unsigned int num_services;
225
226 /* service table */
227 struct ip_vs_service_entry entrytable[0];
228};
229
230
231/* The argument to IP_VS_SO_GET_TIMEOUT */
232struct ip_vs_timeout_user {
233 int tcp_timeout;
234 int tcp_fin_timeout;
235 int udp_timeout;
236};
237
238
239/* The argument to IP_VS_SO_GET_DAEMON */
240struct ip_vs_daemon_user {
241 /* sync daemon state (master/backup) */
242 int state;
243
244 /* multicast interface name */
245 char mcast_ifn[IP_VS_IFNAME_MAXLEN];
246
247 /* SyncID we belong to */
248 int syncid;
249};
250 8
9#include <linux/ip_vs.h> /* definitions shared with userland */
251 10
11/* old ipvsadm versions still include this file directly */
252#ifdef __KERNEL__ 12#ifdef __KERNEL__
253 13
14#include <asm/types.h> /* for __uXX types */
15
16#include <linux/sysctl.h> /* for ctl_path */
254#include <linux/list.h> /* for struct list_head */ 17#include <linux/list.h> /* for struct list_head */
255#include <linux/spinlock.h> /* for struct rwlock_t */ 18#include <linux/spinlock.h> /* for struct rwlock_t */
256#include <asm/atomic.h> /* for struct atomic_t */ 19#include <asm/atomic.h> /* for struct atomic_t */
@@ -981,4 +744,4 @@ static inline __wsum ip_vs_check_diff2(__be16 old, __be16 new, __wsum oldsum)
981 744
982#endif /* __KERNEL__ */ 745#endif /* __KERNEL__ */
983 746
984#endif /* _IP_VS_H */ 747#endif /* _NET_IP_VS_H */
diff --git a/include/net/mac80211.h b/include/net/mac80211.h
index 4dd3d93e196..b397e4d984c 100644
--- a/include/net/mac80211.h
+++ b/include/net/mac80211.h
@@ -177,9 +177,10 @@ enum ieee80211_bss_change {
177 * @aid: association ID number, valid only when @assoc is true 177 * @aid: association ID number, valid only when @assoc is true
178 * @use_cts_prot: use CTS protection 178 * @use_cts_prot: use CTS protection
179 * @use_short_preamble: use 802.11b short preamble 179 * @use_short_preamble: use 802.11b short preamble
180 * @dtim_period: num of beacons before the next DTIM, for PSM
180 * @timestamp: beacon timestamp 181 * @timestamp: beacon timestamp
181 * @beacon_int: beacon interval 182 * @beacon_int: beacon interval
182 * @assoc_capability: capabbilities taken from assoc resp 183 * @assoc_capability: capabilities taken from assoc resp
183 * @assoc_ht: association in HT mode 184 * @assoc_ht: association in HT mode
184 * @ht_conf: ht capabilities 185 * @ht_conf: ht capabilities
185 * @ht_bss_conf: ht extended capabilities 186 * @ht_bss_conf: ht extended capabilities
@@ -191,6 +192,7 @@ struct ieee80211_bss_conf {
191 /* erp related data */ 192 /* erp related data */
192 bool use_cts_prot; 193 bool use_cts_prot;
193 bool use_short_preamble; 194 bool use_short_preamble;
195 u8 dtim_period;
194 u16 beacon_int; 196 u16 beacon_int;
195 u16 assoc_capability; 197 u16 assoc_capability;
196 u64 timestamp; 198 u64 timestamp;
@@ -206,8 +208,6 @@ struct ieee80211_bss_conf {
206 * These flags are used with the @flags member of &ieee80211_tx_info. 208 * These flags are used with the @flags member of &ieee80211_tx_info.
207 * 209 *
208 * @IEEE80211_TX_CTL_REQ_TX_STATUS: request TX status callback for this frame. 210 * @IEEE80211_TX_CTL_REQ_TX_STATUS: request TX status callback for this frame.
209 * @IEEE80211_TX_CTL_DO_NOT_ENCRYPT: send this frame without encryption;
210 * e.g., for EAPOL frame
211 * @IEEE80211_TX_CTL_USE_RTS_CTS: use RTS-CTS before sending frame 211 * @IEEE80211_TX_CTL_USE_RTS_CTS: use RTS-CTS before sending frame
212 * @IEEE80211_TX_CTL_USE_CTS_PROTECT: use CTS protection for the frame (e.g., 212 * @IEEE80211_TX_CTL_USE_CTS_PROTECT: use CTS protection for the frame (e.g.,
213 * for combined 802.11g / 802.11b networks) 213 * for combined 802.11g / 802.11b networks)
@@ -220,7 +220,6 @@ struct ieee80211_bss_conf {
220 * @IEEE80211_TX_CTL_SHORT_PREAMBLE: TBD 220 * @IEEE80211_TX_CTL_SHORT_PREAMBLE: TBD
221 * @IEEE80211_TX_CTL_LONG_RETRY_LIMIT: this frame should be send using the 221 * @IEEE80211_TX_CTL_LONG_RETRY_LIMIT: this frame should be send using the
222 * through set_retry_limit configured long retry value 222 * through set_retry_limit configured long retry value
223 * @IEEE80211_TX_CTL_EAPOL_FRAME: internal to mac80211
224 * @IEEE80211_TX_CTL_SEND_AFTER_DTIM: send this frame after DTIM beacon 223 * @IEEE80211_TX_CTL_SEND_AFTER_DTIM: send this frame after DTIM beacon
225 * @IEEE80211_TX_CTL_AMPDU: this frame should be sent as part of an A-MPDU 224 * @IEEE80211_TX_CTL_AMPDU: this frame should be sent as part of an A-MPDU
226 * @IEEE80211_TX_CTL_OFDM_HT: this frame can be sent in HT OFDM rates. number 225 * @IEEE80211_TX_CTL_OFDM_HT: this frame can be sent in HT OFDM rates. number
@@ -253,7 +252,6 @@ struct ieee80211_bss_conf {
253 */ 252 */
254enum mac80211_tx_control_flags { 253enum mac80211_tx_control_flags {
255 IEEE80211_TX_CTL_REQ_TX_STATUS = BIT(0), 254 IEEE80211_TX_CTL_REQ_TX_STATUS = BIT(0),
256 IEEE80211_TX_CTL_DO_NOT_ENCRYPT = BIT(1),
257 IEEE80211_TX_CTL_USE_RTS_CTS = BIT(2), 255 IEEE80211_TX_CTL_USE_RTS_CTS = BIT(2),
258 IEEE80211_TX_CTL_USE_CTS_PROTECT = BIT(3), 256 IEEE80211_TX_CTL_USE_CTS_PROTECT = BIT(3),
259 IEEE80211_TX_CTL_NO_ACK = BIT(4), 257 IEEE80211_TX_CTL_NO_ACK = BIT(4),
@@ -263,7 +261,6 @@ enum mac80211_tx_control_flags {
263 IEEE80211_TX_CTL_FIRST_FRAGMENT = BIT(8), 261 IEEE80211_TX_CTL_FIRST_FRAGMENT = BIT(8),
264 IEEE80211_TX_CTL_SHORT_PREAMBLE = BIT(9), 262 IEEE80211_TX_CTL_SHORT_PREAMBLE = BIT(9),
265 IEEE80211_TX_CTL_LONG_RETRY_LIMIT = BIT(10), 263 IEEE80211_TX_CTL_LONG_RETRY_LIMIT = BIT(10),
266 IEEE80211_TX_CTL_EAPOL_FRAME = BIT(11),
267 IEEE80211_TX_CTL_SEND_AFTER_DTIM = BIT(12), 264 IEEE80211_TX_CTL_SEND_AFTER_DTIM = BIT(12),
268 IEEE80211_TX_CTL_AMPDU = BIT(13), 265 IEEE80211_TX_CTL_AMPDU = BIT(13),
269 IEEE80211_TX_CTL_OFDM_HT = BIT(14), 266 IEEE80211_TX_CTL_OFDM_HT = BIT(14),
@@ -323,7 +320,6 @@ struct ieee80211_tx_info {
323 struct ieee80211_vif *vif; 320 struct ieee80211_vif *vif;
324 struct ieee80211_key_conf *hw_key; 321 struct ieee80211_key_conf *hw_key;
325 unsigned long jiffies; 322 unsigned long jiffies;
326 int ifindex;
327 u16 aid; 323 u16 aid;
328 s8 rts_cts_rate_idx, alt_retry_rate_idx; 324 s8 rts_cts_rate_idx, alt_retry_rate_idx;
329 u8 retry_limit; 325 u8 retry_limit;
@@ -436,6 +432,7 @@ enum ieee80211_conf_flags {
436 * @radio_enabled: when zero, driver is required to switch off the radio. 432 * @radio_enabled: when zero, driver is required to switch off the radio.
437 * TODO make a flag 433 * TODO make a flag
438 * @beacon_int: beacon interval (TODO make interface config) 434 * @beacon_int: beacon interval (TODO make interface config)
435 * @listen_interval: listen interval in units of beacon interval
439 * @flags: configuration flags defined above 436 * @flags: configuration flags defined above
440 * @power_level: requested transmit power (in dBm) 437 * @power_level: requested transmit power (in dBm)
441 * @max_antenna_gain: maximum antenna gain (in dBi) 438 * @max_antenna_gain: maximum antenna gain (in dBi)
@@ -450,6 +447,7 @@ struct ieee80211_conf {
450 int radio_enabled; 447 int radio_enabled;
451 448
452 int beacon_int; 449 int beacon_int;
450 u16 listen_interval;
453 u32 flags; 451 u32 flags;
454 int power_level; 452 int power_level;
455 int max_antenna_gain; 453 int max_antenna_gain;
@@ -746,7 +744,6 @@ enum ieee80211_tkip_key_type {
746 * Measurement, Channel Switch, Quieting, TPC 744 * Measurement, Channel Switch, Quieting, TPC
747 */ 745 */
748enum ieee80211_hw_flags { 746enum ieee80211_hw_flags {
749 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE = 1<<0,
750 IEEE80211_HW_RX_INCLUDES_FCS = 1<<1, 747 IEEE80211_HW_RX_INCLUDES_FCS = 1<<1,
751 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING = 1<<2, 748 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING = 1<<2,
752 IEEE80211_HW_2GHZ_SHORT_SLOT_INCAPABLE = 1<<3, 749 IEEE80211_HW_2GHZ_SHORT_SLOT_INCAPABLE = 1<<3,
@@ -792,6 +789,9 @@ enum ieee80211_hw_flags {
792 * @max_signal: Maximum value for signal (rssi) in RX information, used 789 * @max_signal: Maximum value for signal (rssi) in RX information, used
793 * only when @IEEE80211_HW_SIGNAL_UNSPEC or @IEEE80211_HW_SIGNAL_DB 790 * only when @IEEE80211_HW_SIGNAL_UNSPEC or @IEEE80211_HW_SIGNAL_DB
794 * 791 *
792 * @max_listen_interval: max listen interval in units of beacon interval
793 * that HW supports
794 *
795 * @queues: number of available hardware transmit queues for 795 * @queues: number of available hardware transmit queues for
796 * data packets. WMM/QoS requires at least four, these 796 * data packets. WMM/QoS requires at least four, these
797 * queues need to have configurable access parameters. 797 * queues need to have configurable access parameters.
@@ -819,7 +819,9 @@ struct ieee80211_hw {
819 unsigned int extra_tx_headroom; 819 unsigned int extra_tx_headroom;
820 int channel_change_time; 820 int channel_change_time;
821 int vif_data_size; 821 int vif_data_size;
822 u16 queues, ampdu_queues; 822 u16 queues;
823 u16 ampdu_queues;
824 u16 max_listen_interval;
823 s8 max_signal; 825 s8 max_signal;
824}; 826};
825 827
diff --git a/include/net/sch_generic.h b/include/net/sch_generic.h
index b5f40d7ef72..a7abfda3e44 100644
--- a/include/net/sch_generic.h
+++ b/include/net/sch_generic.h
@@ -193,10 +193,22 @@ static inline struct Qdisc *qdisc_root(struct Qdisc *qdisc)
193 return qdisc->dev_queue->qdisc; 193 return qdisc->dev_queue->qdisc;
194} 194}
195 195
196/* The qdisc root lock is a mechanism by which to top level
197 * of a qdisc tree can be locked from any qdisc node in the
198 * forest. This allows changing the configuration of some
199 * aspect of the qdisc tree while blocking out asynchronous
200 * qdisc access in the packet processing paths.
201 *
202 * It is only legal to do this when the root will not change
203 * on us. Otherwise we'll potentially lock the wrong qdisc
204 * root. This is enforced by holding the RTNL semaphore, which
205 * all users of this lock accessor must do.
206 */
196static inline spinlock_t *qdisc_root_lock(struct Qdisc *qdisc) 207static inline spinlock_t *qdisc_root_lock(struct Qdisc *qdisc)
197{ 208{
198 struct Qdisc *root = qdisc_root(qdisc); 209 struct Qdisc *root = qdisc_root(qdisc);
199 210
211 ASSERT_RTNL();
200 return qdisc_lock(root); 212 return qdisc_lock(root);
201} 213}
202 214
@@ -331,6 +343,18 @@ static inline unsigned int qdisc_pkt_len(struct sk_buff *skb)
331 return qdisc_skb_cb(skb)->pkt_len; 343 return qdisc_skb_cb(skb)->pkt_len;
332} 344}
333 345
346/* additional qdisc xmit flags (NET_XMIT_MASK in linux/netdevice.h) */
347enum net_xmit_qdisc_t {
348 __NET_XMIT_STOLEN = 0x00010000,
349 __NET_XMIT_BYPASS = 0x00020000,
350};
351
352#ifdef CONFIG_NET_CLS_ACT
353#define net_xmit_drop_count(e) ((e) & __NET_XMIT_STOLEN ? 0 : 1)
354#else
355#define net_xmit_drop_count(e) (1)
356#endif
357
334static inline int qdisc_enqueue(struct sk_buff *skb, struct Qdisc *sch) 358static inline int qdisc_enqueue(struct sk_buff *skb, struct Qdisc *sch)
335{ 359{
336#ifdef CONFIG_NET_SCHED 360#ifdef CONFIG_NET_SCHED
@@ -343,7 +367,7 @@ static inline int qdisc_enqueue(struct sk_buff *skb, struct Qdisc *sch)
343static inline int qdisc_enqueue_root(struct sk_buff *skb, struct Qdisc *sch) 367static inline int qdisc_enqueue_root(struct sk_buff *skb, struct Qdisc *sch)
344{ 368{
345 qdisc_skb_cb(skb)->pkt_len = skb->len; 369 qdisc_skb_cb(skb)->pkt_len = skb->len;
346 return qdisc_enqueue(skb, sch); 370 return qdisc_enqueue(skb, sch) & NET_XMIT_MASK;
347} 371}
348 372
349static inline int __qdisc_enqueue_tail(struct sk_buff *skb, struct Qdisc *sch, 373static inline int __qdisc_enqueue_tail(struct sk_buff *skb, struct Qdisc *sch,
diff --git a/include/net/sctp/structs.h b/include/net/sctp/structs.h
index 535a18f57a1..ab1c472ea75 100644
--- a/include/net/sctp/structs.h
+++ b/include/net/sctp/structs.h
@@ -524,8 +524,7 @@ static inline void sctp_ssn_skip(struct sctp_stream *stream, __u16 id,
524 */ 524 */
525struct sctp_af { 525struct sctp_af {
526 int (*sctp_xmit) (struct sk_buff *skb, 526 int (*sctp_xmit) (struct sk_buff *skb,
527 struct sctp_transport *, 527 struct sctp_transport *);
528 int ipfragok);
529 int (*setsockopt) (struct sock *sk, 528 int (*setsockopt) (struct sock *sk,
530 int level, 529 int level,
531 int optname, 530 int optname,
diff --git a/include/sound/soc-dapm.h b/include/sound/soc-dapm.h
index 3030fdc6981..c1b26fcc0b5 100644
--- a/include/sound/soc-dapm.h
+++ b/include/sound/soc-dapm.h
@@ -202,6 +202,9 @@ struct snd_soc_dapm_path;
202struct snd_soc_dapm_pin; 202struct snd_soc_dapm_pin;
203struct snd_soc_dapm_route; 203struct snd_soc_dapm_route;
204 204
205int dapm_reg_event(struct snd_soc_dapm_widget *w,
206 struct snd_kcontrol *kcontrol, int event);
207
205/* dapm controls */ 208/* dapm controls */
206int snd_soc_dapm_put_volsw(struct snd_kcontrol *kcontrol, 209int snd_soc_dapm_put_volsw(struct snd_kcontrol *kcontrol,
207 struct snd_ctl_elem_value *ucontrol); 210 struct snd_ctl_elem_value *ucontrol);
diff --git a/include/video/radeon.h b/include/video/radeon.h
index 83467e18f5e..95a1f2038b1 100644
--- a/include/video/radeon.h
+++ b/include/video/radeon.h
@@ -527,8 +527,9 @@
527 527
528 528
529/* DSTCACHE_CTLSTAT bit constants */ 529/* DSTCACHE_CTLSTAT bit constants */
530#define RB2D_DC_FLUSH (3 << 0) 530#define RB2D_DC_FLUSH_2D (1 << 0)
531#define RB2D_DC_FLUSH_ALL 0xf 531#define RB2D_DC_FREE_2D (1 << 2)
532#define RB2D_DC_FLUSH_ALL (RB2D_DC_FLUSH_2D | RB2D_DC_FREE_2D)
532#define RB2D_DC_BUSY (1 << 31) 533#define RB2D_DC_BUSY (1 << 31)
533 534
534 535