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authorPeter Korsgaard <jacmet@sunsite.dk>2011-03-09 11:56:30 -0500
committerGrant Likely <grant.likely@secretlab.ca>2011-03-12 03:26:34 -0500
commit0b7bb77fd55903ff9dc7c0474c49002aa6b9c78c (patch)
treed6f20011adc132700bc3e98d8686cbe838d7c86d /include
parent9c3c8afccb6a163fd2be739f511e863eab668702 (diff)
gpio/mcp23s08: support mcp23s17 variant
mpc23s17 is very similar to the mcp23s08, except that registers are 16bit wide, so extend the interface to work with both variants. The s17 variant also has an additional address pin, so adjust platform data structure to support up to 8 devices per SPI chipselect. Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'include')
-rw-r--r--include/linux/spi/mcp23s08.h15
1 files changed, 9 insertions, 6 deletions
diff --git a/include/linux/spi/mcp23s08.h b/include/linux/spi/mcp23s08.h
index 22ef107d770..c42cff8ca19 100644
--- a/include/linux/spi/mcp23s08.h
+++ b/include/linux/spi/mcp23s08.h
@@ -2,21 +2,24 @@
2/* FIXME driver should be able to handle IRQs... */ 2/* FIXME driver should be able to handle IRQs... */
3 3
4struct mcp23s08_chip_info { 4struct mcp23s08_chip_info {
5 bool is_present; /* true iff populated */ 5 bool is_present; /* true if populated */
6 u8 pullups; /* BIT(x) means enable pullup x */ 6 unsigned pullups; /* BIT(x) means enable pullup x */
7}; 7};
8 8
9struct mcp23s08_platform_data { 9struct mcp23s08_platform_data {
10 /* Four slaves (numbered 0..3) can share one SPI chipselect, and 10 /* For mcp23s08, up to 4 slaves (numbered 0..3) can share one SPI
11 * will provide 8..32 GPIOs using 1..4 gpio_chip instances. 11 * chipselect, each providing 1 gpio_chip instance with 8 gpios.
12 * For mpc23s17, up to 8 slaves (numbered 0..7) can share one SPI
13 * chipselect, each providing 1 gpio_chip (port A + port B) with
14 * 16 gpios.
12 */ 15 */
13 struct mcp23s08_chip_info chip[4]; 16 struct mcp23s08_chip_info chip[8];
14 17
15 /* "base" is the number of the first GPIO. Dynamic assignment is 18 /* "base" is the number of the first GPIO. Dynamic assignment is
16 * not currently supported, and even if there are gaps in chip 19 * not currently supported, and even if there are gaps in chip
17 * addressing the GPIO numbers are sequential .. so for example 20 * addressing the GPIO numbers are sequential .. so for example
18 * if only slaves 0 and 3 are present, their GPIOs range from 21 * if only slaves 0 and 3 are present, their GPIOs range from
19 * base to base+15. 22 * base to base+15 (or base+31 for s17 variant).
20 */ 23 */
21 unsigned base; 24 unsigned base;
22 25