diff options
author | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
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committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
commit | 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch) | |
tree | 0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/asm-x86_64/mpspec.h |
Linux-2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
Diffstat (limited to 'include/asm-x86_64/mpspec.h')
-rw-r--r-- | include/asm-x86_64/mpspec.h | 241 |
1 files changed, 241 insertions, 0 deletions
diff --git a/include/asm-x86_64/mpspec.h b/include/asm-x86_64/mpspec.h new file mode 100644 index 00000000000..331f6a3c72a --- /dev/null +++ b/include/asm-x86_64/mpspec.h | |||
@@ -0,0 +1,241 @@ | |||
1 | #ifndef __ASM_MPSPEC_H | ||
2 | #define __ASM_MPSPEC_H | ||
3 | |||
4 | /* | ||
5 | * Structure definitions for SMP machines following the | ||
6 | * Intel Multiprocessing Specification 1.1 and 1.4. | ||
7 | */ | ||
8 | |||
9 | /* | ||
10 | * This tag identifies where the SMP configuration | ||
11 | * information is. | ||
12 | */ | ||
13 | |||
14 | #define SMP_MAGIC_IDENT (('_'<<24)|('P'<<16)|('M'<<8)|'_') | ||
15 | |||
16 | /* | ||
17 | * A maximum of 255 APICs with the current APIC ID architecture. | ||
18 | */ | ||
19 | #define MAX_APICS 128 | ||
20 | |||
21 | struct intel_mp_floating | ||
22 | { | ||
23 | char mpf_signature[4]; /* "_MP_" */ | ||
24 | unsigned int mpf_physptr; /* Configuration table address */ | ||
25 | unsigned char mpf_length; /* Our length (paragraphs) */ | ||
26 | unsigned char mpf_specification;/* Specification version */ | ||
27 | unsigned char mpf_checksum; /* Checksum (makes sum 0) */ | ||
28 | unsigned char mpf_feature1; /* Standard or configuration ? */ | ||
29 | unsigned char mpf_feature2; /* Bit7 set for IMCR|PIC */ | ||
30 | unsigned char mpf_feature3; /* Unused (0) */ | ||
31 | unsigned char mpf_feature4; /* Unused (0) */ | ||
32 | unsigned char mpf_feature5; /* Unused (0) */ | ||
33 | }; | ||
34 | |||
35 | struct mp_config_table | ||
36 | { | ||
37 | char mpc_signature[4]; | ||
38 | #define MPC_SIGNATURE "PCMP" | ||
39 | unsigned short mpc_length; /* Size of table */ | ||
40 | char mpc_spec; /* 0x01 */ | ||
41 | char mpc_checksum; | ||
42 | char mpc_oem[8]; | ||
43 | char mpc_productid[12]; | ||
44 | unsigned int mpc_oemptr; /* 0 if not present */ | ||
45 | unsigned short mpc_oemsize; /* 0 if not present */ | ||
46 | unsigned short mpc_oemcount; | ||
47 | unsigned int mpc_lapic; /* APIC address */ | ||
48 | unsigned int reserved; | ||
49 | }; | ||
50 | |||
51 | /* Followed by entries */ | ||
52 | |||
53 | #define MP_PROCESSOR 0 | ||
54 | #define MP_BUS 1 | ||
55 | #define MP_IOAPIC 2 | ||
56 | #define MP_INTSRC 3 | ||
57 | #define MP_LINTSRC 4 | ||
58 | |||
59 | struct mpc_config_processor | ||
60 | { | ||
61 | unsigned char mpc_type; | ||
62 | unsigned char mpc_apicid; /* Local APIC number */ | ||
63 | unsigned char mpc_apicver; /* Its versions */ | ||
64 | unsigned char mpc_cpuflag; | ||
65 | #define CPU_ENABLED 1 /* Processor is available */ | ||
66 | #define CPU_BOOTPROCESSOR 2 /* Processor is the BP */ | ||
67 | unsigned int mpc_cpufeature; | ||
68 | #define CPU_STEPPING_MASK 0x0F | ||
69 | #define CPU_MODEL_MASK 0xF0 | ||
70 | #define CPU_FAMILY_MASK 0xF00 | ||
71 | unsigned int mpc_featureflag; /* CPUID feature value */ | ||
72 | unsigned int mpc_reserved[2]; | ||
73 | }; | ||
74 | |||
75 | struct mpc_config_bus | ||
76 | { | ||
77 | unsigned char mpc_type; | ||
78 | unsigned char mpc_busid; | ||
79 | unsigned char mpc_bustype[6] __attribute((packed)); | ||
80 | }; | ||
81 | |||
82 | /* List of Bus Type string values, Intel MP Spec. */ | ||
83 | #define BUSTYPE_EISA "EISA" | ||
84 | #define BUSTYPE_ISA "ISA" | ||
85 | #define BUSTYPE_INTERN "INTERN" /* Internal BUS */ | ||
86 | #define BUSTYPE_MCA "MCA" | ||
87 | #define BUSTYPE_VL "VL" /* Local bus */ | ||
88 | #define BUSTYPE_PCI "PCI" | ||
89 | #define BUSTYPE_PCMCIA "PCMCIA" | ||
90 | #define BUSTYPE_CBUS "CBUS" | ||
91 | #define BUSTYPE_CBUSII "CBUSII" | ||
92 | #define BUSTYPE_FUTURE "FUTURE" | ||
93 | #define BUSTYPE_MBI "MBI" | ||
94 | #define BUSTYPE_MBII "MBII" | ||
95 | #define BUSTYPE_MPI "MPI" | ||
96 | #define BUSTYPE_MPSA "MPSA" | ||
97 | #define BUSTYPE_NUBUS "NUBUS" | ||
98 | #define BUSTYPE_TC "TC" | ||
99 | #define BUSTYPE_VME "VME" | ||
100 | #define BUSTYPE_XPRESS "XPRESS" | ||
101 | |||
102 | struct mpc_config_ioapic | ||
103 | { | ||
104 | unsigned char mpc_type; | ||
105 | unsigned char mpc_apicid; | ||
106 | unsigned char mpc_apicver; | ||
107 | unsigned char mpc_flags; | ||
108 | #define MPC_APIC_USABLE 0x01 | ||
109 | unsigned int mpc_apicaddr; | ||
110 | }; | ||
111 | |||
112 | struct mpc_config_intsrc | ||
113 | { | ||
114 | unsigned char mpc_type; | ||
115 | unsigned char mpc_irqtype; | ||
116 | unsigned short mpc_irqflag; | ||
117 | unsigned char mpc_srcbus; | ||
118 | unsigned char mpc_srcbusirq; | ||
119 | unsigned char mpc_dstapic; | ||
120 | unsigned char mpc_dstirq; | ||
121 | }; | ||
122 | |||
123 | enum mp_irq_source_types { | ||
124 | mp_INT = 0, | ||
125 | mp_NMI = 1, | ||
126 | mp_SMI = 2, | ||
127 | mp_ExtINT = 3 | ||
128 | }; | ||
129 | |||
130 | #define MP_IRQDIR_DEFAULT 0 | ||
131 | #define MP_IRQDIR_HIGH 1 | ||
132 | #define MP_IRQDIR_LOW 3 | ||
133 | |||
134 | |||
135 | struct mpc_config_lintsrc | ||
136 | { | ||
137 | unsigned char mpc_type; | ||
138 | unsigned char mpc_irqtype; | ||
139 | unsigned short mpc_irqflag; | ||
140 | unsigned char mpc_srcbusid; | ||
141 | unsigned char mpc_srcbusirq; | ||
142 | unsigned char mpc_destapic; | ||
143 | #define MP_APIC_ALL 0xFF | ||
144 | unsigned char mpc_destapiclint; | ||
145 | }; | ||
146 | |||
147 | /* | ||
148 | * Default configurations | ||
149 | * | ||
150 | * 1 2 CPU ISA 82489DX | ||
151 | * 2 2 CPU EISA 82489DX neither IRQ 0 timer nor IRQ 13 DMA chaining | ||
152 | * 3 2 CPU EISA 82489DX | ||
153 | * 4 2 CPU MCA 82489DX | ||
154 | * 5 2 CPU ISA+PCI | ||
155 | * 6 2 CPU EISA+PCI | ||
156 | * 7 2 CPU MCA+PCI | ||
157 | */ | ||
158 | |||
159 | #define MAX_MP_BUSSES 256 | ||
160 | #define MAX_IRQ_SOURCES 256 | ||
161 | enum mp_bustype { | ||
162 | MP_BUS_ISA = 1, | ||
163 | MP_BUS_EISA, | ||
164 | MP_BUS_PCI, | ||
165 | MP_BUS_MCA | ||
166 | }; | ||
167 | extern unsigned char mp_bus_id_to_type [MAX_MP_BUSSES]; | ||
168 | extern int mp_bus_id_to_pci_bus [MAX_MP_BUSSES]; | ||
169 | |||
170 | extern unsigned int boot_cpu_physical_apicid; | ||
171 | extern int smp_found_config; | ||
172 | extern void find_smp_config (void); | ||
173 | extern void get_smp_config (void); | ||
174 | extern int nr_ioapics; | ||
175 | extern int apic_version [MAX_APICS]; | ||
176 | extern int mp_irq_entries; | ||
177 | extern struct mpc_config_intsrc mp_irqs [MAX_IRQ_SOURCES]; | ||
178 | extern int mpc_default_type; | ||
179 | extern unsigned long mp_lapic_addr; | ||
180 | extern int pic_mode; | ||
181 | |||
182 | #ifdef CONFIG_ACPI_BOOT | ||
183 | extern void mp_register_lapic (u8 id, u8 enabled); | ||
184 | extern void mp_register_lapic_address (u64 address); | ||
185 | |||
186 | #ifdef CONFIG_X86_IO_APIC | ||
187 | extern void mp_register_ioapic (u8 id, u32 address, u32 gsi_base); | ||
188 | extern void mp_override_legacy_irq (u8 bus_irq, u8 polarity, u8 trigger, u32 gsi); | ||
189 | extern void mp_config_acpi_legacy_irqs (void); | ||
190 | extern int mp_register_gsi (u32 gsi, int edge_level, int active_high_low); | ||
191 | #endif /*CONFIG_X86_IO_APIC*/ | ||
192 | #endif | ||
193 | |||
194 | extern int using_apic_timer; | ||
195 | |||
196 | #define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS) | ||
197 | |||
198 | struct physid_mask | ||
199 | { | ||
200 | unsigned long mask[PHYSID_ARRAY_SIZE]; | ||
201 | }; | ||
202 | |||
203 | typedef struct physid_mask physid_mask_t; | ||
204 | |||
205 | #define physid_set(physid, map) set_bit(physid, (map).mask) | ||
206 | #define physid_clear(physid, map) clear_bit(physid, (map).mask) | ||
207 | #define physid_isset(physid, map) test_bit(physid, (map).mask) | ||
208 | #define physid_test_and_set(physid, map) test_and_set_bit(physid, (map).mask) | ||
209 | |||
210 | #define physids_and(dst, src1, src2) bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS) | ||
211 | #define physids_or(dst, src1, src2) bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS) | ||
212 | #define physids_clear(map) bitmap_zero((map).mask, MAX_APICS) | ||
213 | #define physids_complement(dst, src) bitmap_complement((dst).mask, (src).mask, MAX_APICS) | ||
214 | #define physids_empty(map) bitmap_empty((map).mask, MAX_APICS) | ||
215 | #define physids_equal(map1, map2) bitmap_equal((map1).mask, (map2).mask, MAX_APICS) | ||
216 | #define physids_weight(map) bitmap_weight((map).mask, MAX_APICS) | ||
217 | #define physids_shift_right(d, s, n) bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS) | ||
218 | #define physids_shift_left(d, s, n) bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS) | ||
219 | #define physids_coerce(map) ((map).mask[0]) | ||
220 | |||
221 | #define physids_promote(physids) \ | ||
222 | ({ \ | ||
223 | physid_mask_t __physid_mask = PHYSID_MASK_NONE; \ | ||
224 | __physid_mask.mask[0] = physids; \ | ||
225 | __physid_mask; \ | ||
226 | }) | ||
227 | |||
228 | #define physid_mask_of_physid(physid) \ | ||
229 | ({ \ | ||
230 | physid_mask_t __physid_mask = PHYSID_MASK_NONE; \ | ||
231 | physid_set(physid, __physid_mask); \ | ||
232 | __physid_mask; \ | ||
233 | }) | ||
234 | |||
235 | #define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} } | ||
236 | #define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} } | ||
237 | |||
238 | extern physid_mask_t phys_cpu_present_map; | ||
239 | |||
240 | #endif | ||
241 | |||