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authorPaul Mackerras <paulus@samba.org>2005-10-20 06:53:39 -0400
committerPaul Mackerras <paulus@samba.org>2005-10-20 06:53:39 -0400
commitff065ddd96c233d27322de493fa023357939c888 (patch)
treeb60d8a362dea386d1cec91422fd18f92da244ffd /include/asm-ppc/keylargo.h
parent0dd194d02d2584c34e06ddd26c7a7896a5fa1974 (diff)
powerpc: Merge various powermac-related header files.
Except for smu.h, which moved from asm-ppc64 to asm-powerpc, all of these moved from asm-ppc to asm-powerpc. In each case the asm-ppc64 version (if there was one) was just a single line including the asm-ppc version. Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include/asm-ppc/keylargo.h')
-rw-r--r--include/asm-ppc/keylargo.h248
1 files changed, 0 insertions, 248 deletions
diff --git a/include/asm-ppc/keylargo.h b/include/asm-ppc/keylargo.h
deleted file mode 100644
index a669a3f0f5a..00000000000
--- a/include/asm-ppc/keylargo.h
+++ /dev/null
@@ -1,248 +0,0 @@
1/*
2 * keylargo.h: definitions for using the "KeyLargo" I/O controller chip.
3 *
4 */
5
6/* "Pangea" chipset has keylargo device-id 0x25 while core99
7 * has device-id 0x22. The rev. of the pangea one is 0, so we
8 * fake an artificial rev. in keylargo_rev by oring 0x100
9 */
10#define KL_PANGEA_REV 0x100
11
12/* offset from base for feature control registers */
13#define KEYLARGO_MBCR 0x34 /* KL Only, Media bay control/status */
14#define KEYLARGO_FCR0 0x38
15#define KEYLARGO_FCR1 0x3c
16#define KEYLARGO_FCR2 0x40
17#define KEYLARGO_FCR3 0x44
18#define KEYLARGO_FCR4 0x48
19#define KEYLARGO_FCR5 0x4c /* Pangea only */
20
21/* K2 aditional FCRs */
22#define K2_FCR6 0x34
23#define K2_FCR7 0x30
24#define K2_FCR8 0x2c
25#define K2_FCR9 0x28
26#define K2_FCR10 0x24
27
28/* GPIO registers */
29#define KEYLARGO_GPIO_LEVELS0 0x50
30#define KEYLARGO_GPIO_LEVELS1 0x54
31#define KEYLARGO_GPIO_EXTINT_0 0x58
32#define KEYLARGO_GPIO_EXTINT_CNT 18
33#define KEYLARGO_GPIO_0 0x6A
34#define KEYLARGO_GPIO_CNT 17
35#define KEYLARGO_GPIO_EXTINT_DUAL_EDGE 0x80
36#define KEYLARGO_GPIO_OUTPUT_ENABLE 0x04
37#define KEYLARGO_GPIO_OUTOUT_DATA 0x01
38#define KEYLARGO_GPIO_INPUT_DATA 0x02
39
40/* K2 does only extint GPIOs and does 51 of them */
41#define K2_GPIO_EXTINT_0 0x58
42#define K2_GPIO_EXTINT_CNT 51
43
44/* Specific GPIO regs */
45
46#define KL_GPIO_MODEM_RESET (KEYLARGO_GPIO_0+0x03)
47#define KL_GPIO_MODEM_POWER (KEYLARGO_GPIO_0+0x02) /* Pangea */
48
49#define KL_GPIO_SOUND_POWER (KEYLARGO_GPIO_0+0x05)
50
51/* Hrm... this one is only to be used on Pismo. It seeem to also
52 * control the timebase enable on other machines. Still to be
53 * experimented... --BenH.
54 */
55#define KL_GPIO_FW_CABLE_POWER (KEYLARGO_GPIO_0+0x09)
56#define KL_GPIO_TB_ENABLE (KEYLARGO_GPIO_0+0x09)
57
58#define KL_GPIO_ETH_PHY_RESET (KEYLARGO_GPIO_0+0x10)
59
60#define KL_GPIO_EXTINT_CPU1 (KEYLARGO_GPIO_0+0x0a)
61#define KL_GPIO_EXTINT_CPU1_ASSERT 0x04
62#define KL_GPIO_EXTINT_CPU1_RELEASE 0x38
63
64#define KL_GPIO_RESET_CPU0 (KEYLARGO_GPIO_EXTINT_0+0x03)
65#define KL_GPIO_RESET_CPU1 (KEYLARGO_GPIO_EXTINT_0+0x04)
66#define KL_GPIO_RESET_CPU2 (KEYLARGO_GPIO_EXTINT_0+0x0f)
67#define KL_GPIO_RESET_CPU3 (KEYLARGO_GPIO_EXTINT_0+0x10)
68
69#define KL_GPIO_PMU_MESSAGE_IRQ (KEYLARGO_GPIO_EXTINT_0+0x09)
70#define KL_GPIO_PMU_MESSAGE_BIT KEYLARGO_GPIO_INPUT_DATA
71
72#define KL_GPIO_MEDIABAY_IRQ (KEYLARGO_GPIO_EXTINT_0+0x0e)
73
74#define KL_GPIO_AIRPORT_0 (KEYLARGO_GPIO_EXTINT_0+0x0a)
75#define KL_GPIO_AIRPORT_1 (KEYLARGO_GPIO_EXTINT_0+0x0d)
76#define KL_GPIO_AIRPORT_2 (KEYLARGO_GPIO_0+0x0d)
77#define KL_GPIO_AIRPORT_3 (KEYLARGO_GPIO_0+0x0e)
78#define KL_GPIO_AIRPORT_4 (KEYLARGO_GPIO_0+0x0f)
79
80/*
81 * Bits in feature control register. Those bits different for K2 are
82 * listed separately
83 */
84#define KL_MBCR_MB0_PCI_ENABLE 0x00000800 /* exist ? */
85#define KL_MBCR_MB0_IDE_ENABLE 0x00001000
86#define KL_MBCR_MB0_FLOPPY_ENABLE 0x00002000 /* exist ? */
87#define KL_MBCR_MB0_SOUND_ENABLE 0x00004000 /* hrm... */
88#define KL_MBCR_MB0_DEV_MASK 0x00007800
89#define KL_MBCR_MB0_DEV_POWER 0x00000400
90#define KL_MBCR_MB0_DEV_RESET 0x00000200
91#define KL_MBCR_MB0_ENABLE 0x00000100
92#define KL_MBCR_MB1_PCI_ENABLE 0x08000000 /* exist ? */
93#define KL_MBCR_MB1_IDE_ENABLE 0x10000000
94#define KL_MBCR_MB1_FLOPPY_ENABLE 0x20000000 /* exist ? */
95#define KL_MBCR_MB1_SOUND_ENABLE 0x40000000 /* hrm... */
96#define KL_MBCR_MB1_DEV_MASK 0x78000000
97#define KL_MBCR_MB1_DEV_POWER 0x04000000
98#define KL_MBCR_MB1_DEV_RESET 0x02000000
99#define KL_MBCR_MB1_ENABLE 0x01000000
100
101#define KL0_SCC_B_INTF_ENABLE 0x00000001 /* (KL Only) */
102#define KL0_SCC_A_INTF_ENABLE 0x00000002
103#define KL0_SCC_SLOWPCLK 0x00000004
104#define KL0_SCC_RESET 0x00000008
105#define KL0_SCCA_ENABLE 0x00000010
106#define KL0_SCCB_ENABLE 0x00000020
107#define KL0_SCC_CELL_ENABLE 0x00000040
108#define KL0_IRDA_HIGH_BAND 0x00000100 /* (KL Only) */
109#define KL0_IRDA_SOURCE2_SEL 0x00000200 /* (KL Only) */
110#define KL0_IRDA_SOURCE1_SEL 0x00000400 /* (KL Only) */
111#define KL0_PG_USB0_PMI_ENABLE 0x00000400 /* (Pangea/Intrepid Only) */
112#define KL0_IRDA_RESET 0x00000800 /* (KL Only) */
113#define KL0_PG_USB0_REF_SUSPEND_SEL 0x00000800 /* (Pangea/Intrepid Only) */
114#define KL0_IRDA_DEFAULT1 0x00001000 /* (KL Only) */
115#define KL0_PG_USB0_REF_SUSPEND 0x00001000 /* (Pangea/Intrepid Only) */
116#define KL0_IRDA_DEFAULT0 0x00002000 /* (KL Only) */
117#define KL0_PG_USB0_PAD_SUSPEND 0x00002000 /* (Pangea/Intrepid Only) */
118#define KL0_IRDA_FAST_CONNECT 0x00004000 /* (KL Only) */
119#define KL0_PG_USB1_PMI_ENABLE 0x00004000 /* (Pangea/Intrepid Only) */
120#define KL0_IRDA_ENABLE 0x00008000 /* (KL Only) */
121#define KL0_PG_USB1_REF_SUSPEND_SEL 0x00008000 /* (Pangea/Intrepid Only) */
122#define KL0_IRDA_CLK32_ENABLE 0x00010000 /* (KL Only) */
123#define KL0_PG_USB1_REF_SUSPEND 0x00010000 /* (Pangea/Intrepid Only) */
124#define KL0_IRDA_CLK19_ENABLE 0x00020000 /* (KL Only) */
125#define KL0_PG_USB1_PAD_SUSPEND 0x00020000 /* (Pangea/Intrepid Only) */
126#define KL0_USB0_PAD_SUSPEND0 0x00040000
127#define KL0_USB0_PAD_SUSPEND1 0x00080000
128#define KL0_USB0_CELL_ENABLE 0x00100000
129#define KL0_USB1_PAD_SUSPEND0 0x00400000
130#define KL0_USB1_PAD_SUSPEND1 0x00800000
131#define KL0_USB1_CELL_ENABLE 0x01000000
132#define KL0_USB_REF_SUSPEND 0x10000000 /* (KL Only) */
133
134#define KL0_SERIAL_ENABLE (KL0_SCC_B_INTF_ENABLE | \
135 KL0_SCC_SLOWPCLK | \
136 KL0_SCC_CELL_ENABLE | KL0_SCCA_ENABLE)
137
138#define KL1_USB2_PMI_ENABLE 0x00000001 /* Intrepid only */
139#define KL1_AUDIO_SEL_22MCLK 0x00000002 /* KL/Pangea only */
140#define KL1_USB2_REF_SUSPEND_SEL 0x00000002 /* Intrepid only */
141#define KL1_USB2_REF_SUSPEND 0x00000004 /* Intrepid only */
142#define KL1_AUDIO_CLK_ENABLE_BIT 0x00000008 /* KL/Pangea only */
143#define KL1_USB2_PAD_SUSPEND_SEL 0x00000008 /* Intrepid only */
144#define KL1_USB2_PAD_SUSPEND0 0x00000010 /* Intrepid only */
145#define KL1_AUDIO_CLK_OUT_ENABLE 0x00000020 /* KL/Pangea only */
146#define KL1_USB2_PAD_SUSPEND1 0x00000020 /* Intrepid only */
147#define KL1_AUDIO_CELL_ENABLE 0x00000040 /* KL/Pangea only */
148#define KL1_USB2_CELL_ENABLE 0x00000040 /* Intrepid only */
149#define KL1_AUDIO_CHOOSE 0x00000080 /* KL/Pangea only */
150#define KL1_I2S0_CHOOSE 0x00000200 /* KL Only */
151#define KL1_I2S0_CELL_ENABLE 0x00000400
152#define KL1_I2S0_CLK_ENABLE_BIT 0x00001000
153#define KL1_I2S0_ENABLE 0x00002000
154#define KL1_I2S1_CELL_ENABLE 0x00020000
155#define KL1_I2S1_CLK_ENABLE_BIT 0x00080000
156#define KL1_I2S1_ENABLE 0x00100000
157#define KL1_EIDE0_ENABLE 0x00800000 /* KL/Intrepid Only */
158#define KL1_EIDE0_RESET_N 0x01000000 /* KL/Intrepid Only */
159#define KL1_EIDE1_ENABLE 0x04000000 /* KL Only */
160#define KL1_EIDE1_RESET_N 0x08000000 /* KL Only */
161#define KL1_UIDE_ENABLE 0x20000000 /* KL/Pangea Only */
162#define KL1_UIDE_RESET_N 0x40000000 /* KL/Pangea Only */
163
164#define KL2_IOBUS_ENABLE 0x00000002
165#define KL2_SLEEP_STATE_BIT 0x00000100 /* KL Only */
166#define KL2_PG_STOP_ALL_CLOCKS 0x00000100 /* Pangea Only */
167#define KL2_MPIC_ENABLE 0x00020000
168#define KL2_CARDSLOT_RESET 0x00040000 /* Pangea/Intrepid Only */
169#define KL2_ALT_DATA_OUT 0x02000000 /* KL Only ??? */
170#define KL2_MEM_IS_BIG 0x04000000
171#define KL2_CARDSEL_16 0x08000000
172
173#define KL3_SHUTDOWN_PLL_TOTAL 0x00000001 /* KL/Pangea only */
174#define KL3_SHUTDOWN_PLLKW6 0x00000002 /* KL/Pangea only */
175#define KL3_IT_SHUTDOWN_PLL3 0x00000002 /* Intrepid only */
176#define KL3_SHUTDOWN_PLLKW4 0x00000004 /* KL/Pangea only */
177#define KL3_IT_SHUTDOWN_PLL2 0x00000004 /* Intrepid only */
178#define KL3_SHUTDOWN_PLLKW35 0x00000008 /* KL/Pangea only */
179#define KL3_IT_SHUTDOWN_PLL1 0x00000008 /* Intrepid only */
180#define KL3_SHUTDOWN_PLLKW12 0x00000010 /* KL Only */
181#define KL3_IT_ENABLE_PLL3_SHUTDOWN 0x00000010 /* Intrepid only */
182#define KL3_PLL_RESET 0x00000020 /* KL/Pangea only */
183#define KL3_IT_ENABLE_PLL2_SHUTDOWN 0x00000020 /* Intrepid only */
184#define KL3_IT_ENABLE_PLL1_SHUTDOWN 0x00000010 /* Intrepid only */
185#define KL3_SHUTDOWN_PLL2X 0x00000080 /* KL Only */
186#define KL3_CLK66_ENABLE 0x00000100 /* KL Only */
187#define KL3_CLK49_ENABLE 0x00000200
188#define KL3_CLK45_ENABLE 0x00000400
189#define KL3_CLK31_ENABLE 0x00000800 /* KL/Pangea only */
190#define KL3_TIMER_CLK18_ENABLE 0x00001000
191#define KL3_I2S1_CLK18_ENABLE 0x00002000
192#define KL3_I2S0_CLK18_ENABLE 0x00004000
193#define KL3_VIA_CLK16_ENABLE 0x00008000 /* KL/Pangea only */
194#define KL3_IT_VIA_CLK32_ENABLE 0x00008000 /* Intrepid only */
195#define KL3_STOPPING33_ENABLED 0x00080000 /* KL Only */
196#define KL3_PG_PLL_ENABLE_TEST 0x00080000 /* Pangea Only */
197
198/* Intrepid USB bus 2, port 0,1 */
199#define KL3_IT_PORT_WAKEUP_ENABLE(p) (0x00080000 << ((p)<<3))
200#define KL3_IT_PORT_RESUME_WAKE_EN(p) (0x00040000 << ((p)<<3))
201#define KL3_IT_PORT_CONNECT_WAKE_EN(p) (0x00020000 << ((p)<<3))
202#define KL3_IT_PORT_DISCONNECT_WAKE_EN(p) (0x00010000 << ((p)<<3))
203#define KL3_IT_PORT_RESUME_STAT(p) (0x00300000 << ((p)<<3))
204#define KL3_IT_PORT_CONNECT_STAT(p) (0x00200000 << ((p)<<3))
205#define KL3_IT_PORT_DISCONNECT_STAT(p) (0x00100000 << ((p)<<3))
206
207/* Port 0,1 : bus 0, port 2,3 : bus 1 */
208#define KL4_PORT_WAKEUP_ENABLE(p) (0x00000008 << ((p)<<3))
209#define KL4_PORT_RESUME_WAKE_EN(p) (0x00000004 << ((p)<<3))
210#define KL4_PORT_CONNECT_WAKE_EN(p) (0x00000002 << ((p)<<3))
211#define KL4_PORT_DISCONNECT_WAKE_EN(p) (0x00000001 << ((p)<<3))
212#define KL4_PORT_RESUME_STAT(p) (0x00000040 << ((p)<<3))
213#define KL4_PORT_CONNECT_STAT(p) (0x00000020 << ((p)<<3))
214#define KL4_PORT_DISCONNECT_STAT(p) (0x00000010 << ((p)<<3))
215
216/* Pangea and Intrepid only */
217#define KL5_VIA_USE_CLK31 0000000001 /* Pangea Only */
218#define KL5_SCC_USE_CLK31 0x00000002 /* Pangea Only */
219#define KL5_PWM_CLK32_EN 0x00000004
220#define KL5_CLK3_68_EN 0x00000010
221#define KL5_CLK32_EN 0x00000020
222
223
224/* K2 definitions */
225#define K2_FCR0_USB0_SWRESET 0x00200000
226#define K2_FCR0_USB1_SWRESET 0x02000000
227#define K2_FCR0_RING_PME_DISABLE 0x08000000
228
229#define K2_FCR1_PCI1_BUS_RESET_N 0x00000010
230#define K2_FCR1_PCI1_SLEEP_RESET_EN 0x00000020
231#define K2_FCR1_I2S0_CELL_ENABLE 0x00000400
232#define K2_FCR1_I2S0_RESET 0x00000800
233#define K2_FCR1_I2S0_CLK_ENABLE_BIT 0x00001000
234#define K2_FCR1_I2S0_ENABLE 0x00002000
235
236#define K2_FCR1_PCI1_CLK_ENABLE 0x00004000
237#define K2_FCR1_FW_CLK_ENABLE 0x00008000
238#define K2_FCR1_FW_RESET_N 0x00010000
239#define K2_FCR1_GMAC_CLK_ENABLE 0x00400000
240#define K2_FCR1_GMAC_POWER_DOWN 0x00800000
241#define K2_FCR1_GMAC_RESET_N 0x01000000
242#define K2_FCR1_SATA_CLK_ENABLE 0x02000000
243#define K2_FCR1_SATA_POWER_DOWN 0x04000000
244#define K2_FCR1_SATA_RESET_N 0x08000000
245#define K2_FCR1_UATA_CLK_ENABLE 0x10000000
246#define K2_FCR1_UATA_RESET_N 0x40000000
247#define K2_FCR1_UATA_CHOOSE_CLK66 0x80000000
248
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