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authorPaul Mackerras <paulus@samba.org>2007-07-10 23:28:26 -0400
committerPaul Mackerras <paulus@samba.org>2007-07-10 23:28:26 -0400
commitbf22f6fe2d72b4d7e9035be8ceb340414cf490e3 (patch)
tree14085d90de0428316479fe6de8a0c6d32e6e65e2 /include/asm-powerpc
parent4eb6bf6bfb580afaf1e1a1d30cba17a078530cf4 (diff)
parent93ab471889c6662b42ce7da257f31f24c08d7d9e (diff)
Merge branch 'for-2.6.23' into merge
Diffstat (limited to 'include/asm-powerpc')
-rw-r--r--include/asm-powerpc/cache.h4
-rw-r--r--include/asm-powerpc/cputable.h111
-rw-r--r--include/asm-powerpc/floppy.h6
-rw-r--r--include/asm-powerpc/hvcall.h1
-rw-r--r--include/asm-powerpc/io.h26
-rw-r--r--include/asm-powerpc/irq.h9
-rw-r--r--include/asm-powerpc/lppaca.h2
-rw-r--r--include/asm-powerpc/lv1call.h3
-rw-r--r--include/asm-powerpc/machdep.h2
-rw-r--r--include/asm-powerpc/mmu-8xx.h147
-rw-r--r--include/asm-powerpc/mmu-fsl-booke.h88
-rw-r--r--include/asm-powerpc/mmu-hash32.h91
-rw-r--r--include/asm-powerpc/mmu-hash64.h9
-rw-r--r--include/asm-powerpc/mmu.h13
-rw-r--r--include/asm-powerpc/mmu_context.h202
-rw-r--r--include/asm-powerpc/mpc86xx.h6
-rw-r--r--include/asm-powerpc/mpc8xx.h4
-rw-r--r--include/asm-powerpc/pci-bridge.h148
-rw-r--r--include/asm-powerpc/pci.h11
-rw-r--r--include/asm-powerpc/pgtable-ppc32.h50
-rw-r--r--include/asm-powerpc/pgtable-ppc64.h50
-rw-r--r--include/asm-powerpc/pgtable.h28
-rw-r--r--include/asm-powerpc/ppc-pci.h9
-rw-r--r--include/asm-powerpc/processor.h8
-rw-r--r--include/asm-powerpc/prom.h18
-rw-r--r--include/asm-powerpc/ps3.h182
-rw-r--r--include/asm-powerpc/ps3av.h48
-rw-r--r--include/asm-powerpc/ps3fb.h12
-rw-r--r--include/asm-powerpc/ps3stor.h71
-rw-r--r--include/asm-powerpc/ptrace.h22
-rw-r--r--include/asm-powerpc/reg.h2
-rw-r--r--include/asm-powerpc/spu.h24
-rw-r--r--include/asm-powerpc/syscalls.h7
-rw-r--r--include/asm-powerpc/system.h4
-rw-r--r--include/asm-powerpc/termbits.h4
-rw-r--r--include/asm-powerpc/thread_info.h12
-rw-r--r--include/asm-powerpc/time.h4
-rw-r--r--include/asm-powerpc/tlbflush.h5
38 files changed, 1082 insertions, 361 deletions
diff --git a/include/asm-powerpc/cache.h b/include/asm-powerpc/cache.h
index 642be62cf39..53507046a1b 100644
--- a/include/asm-powerpc/cache.h
+++ b/include/asm-powerpc/cache.h
@@ -34,5 +34,9 @@ struct ppc64_caches {
34extern struct ppc64_caches ppc64_caches; 34extern struct ppc64_caches ppc64_caches;
35#endif /* __powerpc64__ && ! __ASSEMBLY__ */ 35#endif /* __powerpc64__ && ! __ASSEMBLY__ */
36 36
37#if !defined(__ASSEMBLY__)
38#define __read_mostly __attribute__((__section__(".data.read_mostly")))
39#endif
40
37#endif /* __KERNEL__ */ 41#endif /* __KERNEL__ */
38#endif /* _ASM_POWERPC_CACHE_H */ 42#endif /* _ASM_POWERPC_CACHE_H */
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h
index 82d595a5210..3dc8e2dfca8 100644
--- a/include/asm-powerpc/cputable.h
+++ b/include/asm-powerpc/cputable.h
@@ -111,7 +111,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
111/* CPU kernel features */ 111/* CPU kernel features */
112 112
113/* Retain the 32b definitions all use bottom half of word */ 113/* Retain the 32b definitions all use bottom half of word */
114#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001) 114#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000000000000001)
115#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002) 115#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
116#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004) 116#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
117#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008) 117#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
@@ -135,6 +135,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
135#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000) 135#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
136#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000) 136#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
137#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000) 137#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000)
138#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000)
138 139
139/* 140/*
140 * Add the 64-bit processor unique features in the top half of the word; 141 * Add the 64-bit processor unique features in the top half of the word;
@@ -154,7 +155,6 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
154#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000) 155#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
155#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000) 156#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
156#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000) 157#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
157#define CPU_FTR_COHERENT_ICACHE LONG_ASM_CONST(0x0000020000000000)
158#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000) 158#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
159#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000) 159#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
160#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000) 160#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
@@ -206,164 +206,149 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
206 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \ 206 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
207 !defined(CONFIG_BOOKE)) 207 !defined(CONFIG_BOOKE))
208 208
209#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE) 209#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE | \
210#define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 210 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
211#define CPU_FTRS_603 (CPU_FTR_COMMON | \
211 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ 212 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
212 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 213 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
213#define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 214#define CPU_FTRS_604 (CPU_FTR_COMMON | \
214 CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \ 215 CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \
215 CPU_FTR_PPC_LE) 216 CPU_FTR_PPC_LE)
216#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 217#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
217 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 218 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
218 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 219 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
219#define CPU_FTRS_740 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 220#define CPU_FTRS_740 (CPU_FTR_COMMON | \
220 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 221 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
221 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ 222 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
222 CPU_FTR_PPC_LE) 223 CPU_FTR_PPC_LE)
223#define CPU_FTRS_750 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 224#define CPU_FTRS_750 (CPU_FTR_COMMON | \
224 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 225 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
225 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ 226 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
226 CPU_FTR_PPC_LE) 227 CPU_FTR_PPC_LE)
227#define CPU_FTRS_750CL (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 228#define CPU_FTRS_750CL (CPU_FTRS_750 | CPU_FTR_HAS_HIGH_BATS)
228 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 229#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
229 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ 230#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
230 CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE) 231#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | \
231#define CPU_FTRS_750FX1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 232 CPU_FTR_HAS_HIGH_BATS)
232 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 233#define CPU_FTRS_750GX (CPU_FTRS_750FX)
233 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ 234#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
234 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
235#define CPU_FTRS_750FX2 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
236 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
237 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
238 CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
239#define CPU_FTRS_750FX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
240 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
241 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
242 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
243#define CPU_FTRS_750GX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
244 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
245 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
246 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
247#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
248 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 235 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
249 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \ 236 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
250 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 237 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
251#define CPU_FTRS_7400 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 238#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
252 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 239 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
253 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \ 240 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
254 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 241 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
255#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 242#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
256 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 243 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
257 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ 244 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
258 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 245 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
259#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 246#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
260 CPU_FTR_USE_TB | \ 247 CPU_FTR_USE_TB | \
261 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 248 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
262 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ 249 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
263 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ 250 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
264 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 251 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
265#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 252#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
266 CPU_FTR_USE_TB | \ 253 CPU_FTR_USE_TB | \
267 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 254 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
268 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ 255 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
269 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 256 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
270#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 257#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
271 CPU_FTR_USE_TB | \ 258 CPU_FTR_USE_TB | \
272 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \ 259 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
273 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \ 260 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
274 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 261 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
275#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 262#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
276 CPU_FTR_USE_TB | \ 263 CPU_FTR_USE_TB | \
277 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 264 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
278 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ 265 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
279 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ 266 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
280 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE) 267 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
281#define CPU_FTRS_7455 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 268#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
282 CPU_FTR_USE_TB | \ 269 CPU_FTR_USE_TB | \
283 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 270 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
284 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ 271 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
285 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ 272 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
286 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 273 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
287#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 274#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
288 CPU_FTR_USE_TB | \ 275 CPU_FTR_USE_TB | \
289 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 276 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
290 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ 277 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
291 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ 278 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
292 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE) 279 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE)
293#define CPU_FTRS_7447 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 280#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
294 CPU_FTR_USE_TB | \ 281 CPU_FTR_USE_TB | \
295 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 282 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
296 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ 283 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
297 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ 284 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
298 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 285 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
299#define CPU_FTRS_7447A (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 286#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
300 CPU_FTR_USE_TB | \ 287 CPU_FTR_USE_TB | \
301 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 288 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
302 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ 289 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
303 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ 290 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
304 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 291 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
305#define CPU_FTRS_7448 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 292#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
306 CPU_FTR_USE_TB | \ 293 CPU_FTR_USE_TB | \
307 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 294 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
308 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ 295 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
309 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ 296 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
310 CPU_FTR_PPC_LE) 297 CPU_FTR_PPC_LE)
311#define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 298#define CPU_FTRS_82XX (CPU_FTR_COMMON | \
312 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB) 299 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
313#define CPU_FTRS_G2_LE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \ 300#define CPU_FTRS_G2_LE (CPU_FTR_MAYBE_CAN_DOZE | \
314 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS) 301 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
315#define CPU_FTRS_E300 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \ 302#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
316 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \ 303 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
317 CPU_FTR_COMMON) 304 CPU_FTR_COMMON)
318#define CPU_FTRS_E300C2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \ 305#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
319 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \ 306 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
320 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE) 307 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
321#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ 308#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | \
322 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE) 309 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
323#define CPU_FTRS_8XX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB) 310#define CPU_FTRS_8XX (CPU_FTR_USE_TB)
324#define CPU_FTRS_40X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 311#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
325 CPU_FTR_NODSISRALIGN) 312#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
326#define CPU_FTRS_44X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 313#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
327 CPU_FTR_NODSISRALIGN) 314 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
328#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN) 315#define CPU_FTRS_E500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
329#define CPU_FTRS_E500 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 316#define CPU_FTRS_E500_2 (CPU_FTR_USE_TB | \
330 CPU_FTR_NODSISRALIGN)
331#define CPU_FTRS_E500_2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
332 CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN) 317 CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
333#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) 318#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
334 319
335/* 64-bit CPUs */ 320/* 64-bit CPUs */
336#define CPU_FTRS_POWER3 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 321#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \
337 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE) 322 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
338#define CPU_FTRS_RS64 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 323#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | \
339 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \ 324 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
340 CPU_FTR_MMCRA | CPU_FTR_CTRL) 325 CPU_FTR_MMCRA | CPU_FTR_CTRL)
341#define CPU_FTRS_POWER4 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 326#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | \
342 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 327 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
343 CPU_FTR_MMCRA) 328 CPU_FTR_MMCRA)
344#define CPU_FTRS_PPC970 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 329#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | \
345 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 330 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
346 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA) 331 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
347#define CPU_FTRS_POWER5 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 332#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | \
348 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 333 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
349 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 334 CPU_FTR_MMCRA | CPU_FTR_SMT | \
350 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ 335 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
351 CPU_FTR_PURR) 336 CPU_FTR_PURR)
352#define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 337#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | \
353 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 338 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
354 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 339 CPU_FTR_MMCRA | CPU_FTR_SMT | \
355 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ 340 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
356 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 341 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
357 CPU_FTR_DSCR) 342 CPU_FTR_DSCR)
358#define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 343#define CPU_FTRS_CELL (CPU_FTR_USE_TB | \
359 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 344 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
360 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ 345 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
361 CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG) 346 CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG)
362#define CPU_FTRS_PA6T (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 347#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | \
363 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \ 348 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
364 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \ 349 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
365 CPU_FTR_PURR | CPU_FTR_REAL_LE) 350 CPU_FTR_PURR | CPU_FTR_REAL_LE)
366#define CPU_FTRS_COMPATIBLE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 351#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | \
367 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2) 352 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
368 353
369#ifdef __powerpc64__ 354#ifdef __powerpc64__
diff --git a/include/asm-powerpc/floppy.h b/include/asm-powerpc/floppy.h
index afa700ded87..34146f0eea6 100644
--- a/include/asm-powerpc/floppy.h
+++ b/include/asm-powerpc/floppy.h
@@ -29,7 +29,7 @@
29#define fd_free_irq() free_irq(FLOPPY_IRQ, NULL); 29#define fd_free_irq() free_irq(FLOPPY_IRQ, NULL);
30 30
31#include <linux/pci.h> 31#include <linux/pci.h>
32#include <asm/ppc-pci.h> /* for ppc64_isabridge_dev */ 32#include <asm/ppc-pci.h> /* for isa_bridge_pcidev */
33 33
34#define fd_dma_setup(addr,size,mode,io) fd_ops->_dma_setup(addr,size,mode,io) 34#define fd_dma_setup(addr,size,mode,io) fd_ops->_dma_setup(addr,size,mode,io)
35 35
@@ -139,12 +139,12 @@ static int hard_dma_setup(char *addr, unsigned long size, int mode, int io)
139 if (bus_addr 139 if (bus_addr
140 && (addr != prev_addr || size != prev_size || dir != prev_dir)) { 140 && (addr != prev_addr || size != prev_size || dir != prev_dir)) {
141 /* different from last time -- unmap prev */ 141 /* different from last time -- unmap prev */
142 pci_unmap_single(ppc64_isabridge_dev, bus_addr, prev_size, prev_dir); 142 pci_unmap_single(isa_bridge_pcidev, bus_addr, prev_size, prev_dir);
143 bus_addr = 0; 143 bus_addr = 0;
144 } 144 }
145 145
146 if (!bus_addr) /* need to map it */ 146 if (!bus_addr) /* need to map it */
147 bus_addr = pci_map_single(ppc64_isabridge_dev, addr, size, dir); 147 bus_addr = pci_map_single(isa_bridge_pcidev, addr, size, dir);
148 148
149 /* remember this one as prev */ 149 /* remember this one as prev */
150 prev_addr = addr; 150 prev_addr = addr;
diff --git a/include/asm-powerpc/hvcall.h b/include/asm-powerpc/hvcall.h
index 62efd9d7a43..bf6cd7cb996 100644
--- a/include/asm-powerpc/hvcall.h
+++ b/include/asm-powerpc/hvcall.h
@@ -206,6 +206,7 @@
206#define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 206#define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
207#define H_QUERY_INT_STATE 0x1E4 207#define H_QUERY_INT_STATE 0x1E4
208#define H_POLL_PENDING 0x1D8 208#define H_POLL_PENDING 0x1D8
209#define H_ILLAN_ATTRIBUTES 0x244
209#define H_JOIN 0x298 210#define H_JOIN 0x298
210#define H_VASI_STATE 0x2A4 211#define H_VASI_STATE 0x2A4
211#define H_ENABLE_CRQ 0x2B0 212#define H_ENABLE_CRQ 0x2B0
diff --git a/include/asm-powerpc/io.h b/include/asm-powerpc/io.h
index 350c9bdb31d..bb8d965f96c 100644
--- a/include/asm-powerpc/io.h
+++ b/include/asm-powerpc/io.h
@@ -607,9 +607,9 @@ static inline void iosync(void)
607 * 607 *
608 * * iounmap undoes such a mapping and can be hooked 608 * * iounmap undoes such a mapping and can be hooked
609 * 609 *
610 * * __ioremap_explicit (and the pending __iounmap_explicit) are low level 610 * * __ioremap_at (and the pending __iounmap_at) are low level functions to
611 * functions to create hand-made mappings for use only by the PCI code 611 * create hand-made mappings for use only by the PCI code and cannot
612 * and cannot currently be hooked. 612 * currently be hooked. Must be page aligned.
613 * 613 *
614 * * __ioremap is the low level implementation used by ioremap and 614 * * __ioremap is the low level implementation used by ioremap and
615 * ioremap_flags and cannot be hooked (but can be used by a hook on one 615 * ioremap_flags and cannot be hooked (but can be used by a hook on one
@@ -629,19 +629,9 @@ extern void __iomem *__ioremap(phys_addr_t, unsigned long size,
629 unsigned long flags); 629 unsigned long flags);
630extern void __iounmap(volatile void __iomem *addr); 630extern void __iounmap(volatile void __iomem *addr);
631 631
632extern int __ioremap_explicit(phys_addr_t p_addr, unsigned long v_addr, 632extern void __iomem * __ioremap_at(phys_addr_t pa, void *ea,
633 unsigned long size, unsigned long flags); 633 unsigned long size, unsigned long flags);
634extern int __iounmap_explicit(volatile void __iomem *start, 634extern void __iounmap_at(void *ea, unsigned long size);
635 unsigned long size);
636
637extern void __iomem * reserve_phb_iospace(unsigned long size);
638
639/* Those are more 32 bits only functions */
640extern unsigned long iopa(unsigned long addr);
641extern unsigned long mm_ptov(unsigned long addr) __attribute_const__;
642extern void io_block_mapping(unsigned long virt, phys_addr_t phys,
643 unsigned int size, int flags);
644
645 635
646/* 636/*
647 * When CONFIG_PPC_INDIRECT_IO is set, we use the generic iomap implementation 637 * When CONFIG_PPC_INDIRECT_IO is set, we use the generic iomap implementation
@@ -651,8 +641,8 @@ extern void io_block_mapping(unsigned long virt, phys_addr_t phys,
651 */ 641 */
652#define HAVE_ARCH_PIO_SIZE 1 642#define HAVE_ARCH_PIO_SIZE 1
653#define PIO_OFFSET 0x00000000UL 643#define PIO_OFFSET 0x00000000UL
654#define PIO_MASK 0x3fffffffUL 644#define PIO_MASK (FULL_IO_SIZE - 1)
655#define PIO_RESERVED 0x40000000UL 645#define PIO_RESERVED (FULL_IO_SIZE)
656 646
657#define mmio_read16be(addr) readw_be(addr) 647#define mmio_read16be(addr) readw_be(addr)
658#define mmio_read32be(addr) readl_be(addr) 648#define mmio_read32be(addr) readl_be(addr)
diff --git a/include/asm-powerpc/irq.h b/include/asm-powerpc/irq.h
index 05dd5a3eb3a..0485c53db2b 100644
--- a/include/asm-powerpc/irq.h
+++ b/include/asm-powerpc/irq.h
@@ -223,6 +223,15 @@ extern void irq_dispose_mapping(unsigned int virq);
223extern unsigned int irq_find_mapping(struct irq_host *host, 223extern unsigned int irq_find_mapping(struct irq_host *host,
224 irq_hw_number_t hwirq); 224 irq_hw_number_t hwirq);
225 225
226/**
227 * irq_create_direct_mapping - Allocate a virq for direct mapping
228 * @host: host to allocate the virq for or NULL for default host
229 *
230 * This routine is used for irq controllers which can choose the hardware
231 * interrupt numbers they generate. In such a case it's simplest to use
232 * the linux virq as the hardware interrupt number.
233 */
234extern unsigned int irq_create_direct_mapping(struct irq_host *host);
226 235
227/** 236/**
228 * irq_radix_revmap - Find a linux virq from a hw irq number. 237 * irq_radix_revmap - Find a linux virq from a hw irq number.
diff --git a/include/asm-powerpc/lppaca.h b/include/asm-powerpc/lppaca.h
index 821ea0c512b..567ed92cd91 100644
--- a/include/asm-powerpc/lppaca.h
+++ b/include/asm-powerpc/lppaca.h
@@ -98,7 +98,7 @@ struct lppaca {
98 u64 saved_gpr5; // Saved GPR5 x30-x37 98 u64 saved_gpr5; // Saved GPR5 x30-x37
99 99
100 u8 reserved4; // Reserved x38-x38 100 u8 reserved4; // Reserved x38-x38
101 u8 cpuctls_task_attrs; // Task attributes for cpuctls x39-x39 101 u8 donate_dedicated_cpu; // Donate dedicated CPU cycles x39-x39
102 u8 fpregs_in_use; // FP regs in use x3A-x3A 102 u8 fpregs_in_use; // FP regs in use x3A-x3A
103 u8 pmcregs_in_use; // PMC regs in use x3B-x3B 103 u8 pmcregs_in_use; // PMC regs in use x3B-x3B
104 volatile u32 saved_decr; // Saved Decr Value x3C-x3F 104 volatile u32 saved_decr; // Saved Decr Value x3C-x3F
diff --git a/include/asm-powerpc/lv1call.h b/include/asm-powerpc/lv1call.h
index f733beeea63..81713acf752 100644
--- a/include/asm-powerpc/lv1call.h
+++ b/include/asm-powerpc/lv1call.h
@@ -238,6 +238,7 @@ LV1_CALL(destruct_virtual_address_space, 1, 0, 10 )
238LV1_CALL(configure_irq_state_bitmap, 3, 0, 11 ) 238LV1_CALL(configure_irq_state_bitmap, 3, 0, 11 )
239LV1_CALL(connect_irq_plug_ext, 5, 0, 12 ) 239LV1_CALL(connect_irq_plug_ext, 5, 0, 12 )
240LV1_CALL(release_memory, 1, 0, 13 ) 240LV1_CALL(release_memory, 1, 0, 13 )
241LV1_CALL(put_iopte, 5, 0, 15 )
241LV1_CALL(disconnect_irq_plug_ext, 3, 0, 17 ) 242LV1_CALL(disconnect_irq_plug_ext, 3, 0, 17 )
242LV1_CALL(construct_event_receive_port, 0, 1, 18 ) 243LV1_CALL(construct_event_receive_port, 0, 1, 18 )
243LV1_CALL(destruct_event_receive_port, 1, 0, 19 ) 244LV1_CALL(destruct_event_receive_port, 1, 0, 19 )
@@ -268,6 +269,8 @@ LV1_CALL(remove_repository_node, 4, 0, 93 )
268LV1_CALL(read_htab_entries, 2, 5, 95 ) 269LV1_CALL(read_htab_entries, 2, 5, 95 )
269LV1_CALL(set_dabr, 2, 0, 96 ) 270LV1_CALL(set_dabr, 2, 0, 96 )
270LV1_CALL(get_total_execution_time, 2, 1, 103 ) 271LV1_CALL(get_total_execution_time, 2, 1, 103 )
272LV1_CALL(allocate_io_segment, 3, 1, 116 )
273LV1_CALL(release_io_segment, 2, 0, 117 )
271LV1_CALL(construct_io_irq_outlet, 1, 1, 120 ) 274LV1_CALL(construct_io_irq_outlet, 1, 1, 120 )
272LV1_CALL(destruct_io_irq_outlet, 1, 0, 121 ) 275LV1_CALL(destruct_io_irq_outlet, 1, 0, 121 )
273LV1_CALL(map_htab, 1, 1, 122 ) 276LV1_CALL(map_htab, 1, 1, 122 )
diff --git a/include/asm-powerpc/machdep.h b/include/asm-powerpc/machdep.h
index 6cf1a831f55..71c6e7eb2a2 100644
--- a/include/asm-powerpc/machdep.h
+++ b/include/asm-powerpc/machdep.h
@@ -218,7 +218,7 @@ struct machdep_calls {
218 int (*pcibios_enable_device_hook)(struct pci_dev *, int initial); 218 int (*pcibios_enable_device_hook)(struct pci_dev *, int initial);
219 219
220 /* Called in indirect_* to avoid touching devices */ 220 /* Called in indirect_* to avoid touching devices */
221 int (*pci_exclude_device)(unsigned char, unsigned char); 221 int (*pci_exclude_device)(struct pci_controller *, unsigned char, unsigned char);
222 222
223 /* Called at then very end of pcibios_init() */ 223 /* Called at then very end of pcibios_init() */
224 void (*pcibios_after_init)(void); 224 void (*pcibios_after_init)(void);
diff --git a/include/asm-powerpc/mmu-8xx.h b/include/asm-powerpc/mmu-8xx.h
new file mode 100644
index 00000000000..952bd8899f2
--- /dev/null
+++ b/include/asm-powerpc/mmu-8xx.h
@@ -0,0 +1,147 @@
1#ifndef _ASM_POWERPC_MMU_8XX_H_
2#define _ASM_POWERPC_MMU_8XX_H_
3/*
4 * PPC8xx support
5 */
6
7/* Control/status registers for the MPC8xx.
8 * A write operation to these registers causes serialized access.
9 * During software tablewalk, the registers used perform mask/shift-add
10 * operations when written/read. A TLB entry is created when the Mx_RPN
11 * is written, and the contents of several registers are used to
12 * create the entry.
13 */
14#define SPRN_MI_CTR 784 /* Instruction TLB control register */
15#define MI_GPM 0x80000000 /* Set domain manager mode */
16#define MI_PPM 0x40000000 /* Set subpage protection */
17#define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
18#define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */
19#define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
20#define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */
21#define MI_RESETVAL 0x00000000 /* Value of register at reset */
22
23/* These are the Ks and Kp from the PowerPC books. For proper operation,
24 * Ks = 0, Kp = 1.
25 */
26#define SPRN_MI_AP 786
27#define MI_Ks 0x80000000 /* Should not be set */
28#define MI_Kp 0x40000000 /* Should always be set */
29
30/* The effective page number register. When read, contains the information
31 * about the last instruction TLB miss. When MI_RPN is written, bits in
32 * this register are used to create the TLB entry.
33 */
34#define SPRN_MI_EPN 787
35#define MI_EPNMASK 0xfffff000 /* Effective page number for entry */
36#define MI_EVALID 0x00000200 /* Entry is valid */
37#define MI_ASIDMASK 0x0000000f /* ASID match value */
38 /* Reset value is undefined */
39
40/* A "level 1" or "segment" or whatever you want to call it register.
41 * For the instruction TLB, it contains bits that get loaded into the
42 * TLB entry when the MI_RPN is written.
43 */
44#define SPRN_MI_TWC 789
45#define MI_APG 0x000001e0 /* Access protection group (0) */
46#define MI_GUARDED 0x00000010 /* Guarded storage */
47#define MI_PSMASK 0x0000000c /* Mask of page size bits */
48#define MI_PS8MEG 0x0000000c /* 8M page size */
49#define MI_PS512K 0x00000004 /* 512K page size */
50#define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */
51#define MI_SVALID 0x00000001 /* Segment entry is valid */
52 /* Reset value is undefined */
53
54/* Real page number. Defined by the pte. Writing this register
55 * causes a TLB entry to be created for the instruction TLB, using
56 * additional information from the MI_EPN, and MI_TWC registers.
57 */
58#define SPRN_MI_RPN 790
59
60/* Define an RPN value for mapping kernel memory to large virtual
61 * pages for boot initialization. This has real page number of 0,
62 * large page size, shared page, cache enabled, and valid.
63 * Also mark all subpages valid and write access.
64 */
65#define MI_BOOTINIT 0x000001fd
66
67#define SPRN_MD_CTR 792 /* Data TLB control register */
68#define MD_GPM 0x80000000 /* Set domain manager mode */
69#define MD_PPM 0x40000000 /* Set subpage protection */
70#define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
71#define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */
72#define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */
73#define MD_TWAM 0x04000000 /* Use 4K page hardware assist */
74#define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
75#define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */
76#define MD_RESETVAL 0x04000000 /* Value of register at reset */
77
78#define SPRN_M_CASID 793 /* Address space ID (context) to match */
79#define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */
80
81
82/* These are the Ks and Kp from the PowerPC books. For proper operation,
83 * Ks = 0, Kp = 1.
84 */
85#define SPRN_MD_AP 794
86#define MD_Ks 0x80000000 /* Should not be set */
87#define MD_Kp 0x40000000 /* Should always be set */
88
89/* The effective page number register. When read, contains the information
90 * about the last instruction TLB miss. When MD_RPN is written, bits in
91 * this register are used to create the TLB entry.
92 */
93#define SPRN_MD_EPN 795
94#define MD_EPNMASK 0xfffff000 /* Effective page number for entry */
95#define MD_EVALID 0x00000200 /* Entry is valid */
96#define MD_ASIDMASK 0x0000000f /* ASID match value */
97 /* Reset value is undefined */
98
99/* The pointer to the base address of the first level page table.
100 * During a software tablewalk, reading this register provides the address
101 * of the entry associated with MD_EPN.
102 */
103#define SPRN_M_TWB 796
104#define M_L1TB 0xfffff000 /* Level 1 table base address */
105#define M_L1INDX 0x00000ffc /* Level 1 index, when read */
106 /* Reset value is undefined */
107
108/* A "level 1" or "segment" or whatever you want to call it register.
109 * For the data TLB, it contains bits that get loaded into the TLB entry
110 * when the MD_RPN is written. It is also provides the hardware assist
111 * for finding the PTE address during software tablewalk.
112 */
113#define SPRN_MD_TWC 797
114#define MD_L2TB 0xfffff000 /* Level 2 table base address */
115#define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */
116#define MD_APG 0x000001e0 /* Access protection group (0) */
117#define MD_GUARDED 0x00000010 /* Guarded storage */
118#define MD_PSMASK 0x0000000c /* Mask of page size bits */
119#define MD_PS8MEG 0x0000000c /* 8M page size */
120#define MD_PS512K 0x00000004 /* 512K page size */
121#define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */
122#define MD_WT 0x00000002 /* Use writethrough page attribute */
123#define MD_SVALID 0x00000001 /* Segment entry is valid */
124 /* Reset value is undefined */
125
126
127/* Real page number. Defined by the pte. Writing this register
128 * causes a TLB entry to be created for the data TLB, using
129 * additional information from the MD_EPN, and MD_TWC registers.
130 */
131#define SPRN_MD_RPN 798
132
133/* This is a temporary storage register that could be used to save
134 * a processor working register during a tablewalk.
135 */
136#define SPRN_M_TW 799
137
138#ifndef __ASSEMBLY__
139typedef unsigned long phys_addr_t;
140
141typedef struct {
142 unsigned long id;
143 unsigned long vdso_base;
144} mm_context_t;
145#endif /* !__ASSEMBLY__ */
146
147#endif /* _ASM_POWERPC_MMU_8XX_H_ */
diff --git a/include/asm-powerpc/mmu-fsl-booke.h b/include/asm-powerpc/mmu-fsl-booke.h
new file mode 100644
index 00000000000..37580004cd7
--- /dev/null
+++ b/include/asm-powerpc/mmu-fsl-booke.h
@@ -0,0 +1,88 @@
1#ifndef _ASM_POWERPC_MMU_FSL_BOOKE_H_
2#define _ASM_POWERPC_MMU_FSL_BOOKE_H_
3/*
4 * Freescale Book-E MMU support
5 */
6
7/* Book-E defined page sizes */
8#define BOOKE_PAGESZ_1K 0
9#define BOOKE_PAGESZ_4K 1
10#define BOOKE_PAGESZ_16K 2
11#define BOOKE_PAGESZ_64K 3
12#define BOOKE_PAGESZ_256K 4
13#define BOOKE_PAGESZ_1M 5
14#define BOOKE_PAGESZ_4M 6
15#define BOOKE_PAGESZ_16M 7
16#define BOOKE_PAGESZ_64M 8
17#define BOOKE_PAGESZ_256M 9
18#define BOOKE_PAGESZ_1GB 10
19#define BOOKE_PAGESZ_4GB 11
20#define BOOKE_PAGESZ_16GB 12
21#define BOOKE_PAGESZ_64GB 13
22#define BOOKE_PAGESZ_256GB 14
23#define BOOKE_PAGESZ_1TB 15
24
25#define MAS0_TLBSEL(x) ((x << 28) & 0x30000000)
26#define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000)
27#define MAS0_NV(x) ((x) & 0x00000FFF)
28
29#define MAS1_VALID 0x80000000
30#define MAS1_IPROT 0x40000000
31#define MAS1_TID(x) ((x << 16) & 0x3FFF0000)
32#define MAS1_TS 0x00001000
33#define MAS1_TSIZE(x) ((x << 8) & 0x00000F00)
34
35#define MAS2_EPN 0xFFFFF000
36#define MAS2_X0 0x00000040
37#define MAS2_X1 0x00000020
38#define MAS2_W 0x00000010
39#define MAS2_I 0x00000008
40#define MAS2_M 0x00000004
41#define MAS2_G 0x00000002
42#define MAS2_E 0x00000001
43
44#define MAS3_RPN 0xFFFFF000
45#define MAS3_U0 0x00000200
46#define MAS3_U1 0x00000100
47#define MAS3_U2 0x00000080
48#define MAS3_U3 0x00000040
49#define MAS3_UX 0x00000020
50#define MAS3_SX 0x00000010
51#define MAS3_UW 0x00000008
52#define MAS3_SW 0x00000004
53#define MAS3_UR 0x00000002
54#define MAS3_SR 0x00000001
55
56#define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
57#define MAS4_TIDDSEL 0x000F0000
58#define MAS4_TSIZED(x) MAS1_TSIZE(x)
59#define MAS4_X0D 0x00000040
60#define MAS4_X1D 0x00000020
61#define MAS4_WD 0x00000010
62#define MAS4_ID 0x00000008
63#define MAS4_MD 0x00000004
64#define MAS4_GD 0x00000002
65#define MAS4_ED 0x00000001
66
67#define MAS6_SPID0 0x3FFF0000
68#define MAS6_SPID1 0x00007FFE
69#define MAS6_SAS 0x00000001
70#define MAS6_SPID MAS6_SPID0
71
72#define MAS7_RPN 0xFFFFFFFF
73
74#ifndef __ASSEMBLY__
75
76#ifndef CONFIG_PHYS_64BIT
77typedef unsigned long phys_addr_t;
78#else
79typedef unsigned long long phys_addr_t;
80#endif
81
82typedef struct {
83 unsigned long id;
84 unsigned long vdso_base;
85} mm_context_t;
86#endif /* !__ASSEMBLY__ */
87
88#endif /* _ASM_POWERPC_MMU_FSL_BOOKE_H_ */
diff --git a/include/asm-powerpc/mmu-hash32.h b/include/asm-powerpc/mmu-hash32.h
new file mode 100644
index 00000000000..4bd735be383
--- /dev/null
+++ b/include/asm-powerpc/mmu-hash32.h
@@ -0,0 +1,91 @@
1#ifndef _ASM_POWERPC_MMU_HASH32_H_
2#define _ASM_POWERPC_MMU_HASH32_H_
3/*
4 * 32-bit hash table MMU support
5 */
6
7/*
8 * BATs
9 */
10
11/* Block size masks */
12#define BL_128K 0x000
13#define BL_256K 0x001
14#define BL_512K 0x003
15#define BL_1M 0x007
16#define BL_2M 0x00F
17#define BL_4M 0x01F
18#define BL_8M 0x03F
19#define BL_16M 0x07F
20#define BL_32M 0x0FF
21#define BL_64M 0x1FF
22#define BL_128M 0x3FF
23#define BL_256M 0x7FF
24
25/* BAT Access Protection */
26#define BPP_XX 0x00 /* No access */
27#define BPP_RX 0x01 /* Read only */
28#define BPP_RW 0x02 /* Read/write */
29
30#ifndef __ASSEMBLY__
31struct ppc_bat {
32 struct {
33 unsigned long bepi:15; /* Effective page index (virtual address) */
34 unsigned long :4; /* Unused */
35 unsigned long bl:11; /* Block size mask */
36 unsigned long vs:1; /* Supervisor valid */
37 unsigned long vp:1; /* User valid */
38 } batu; /* Upper register */
39 struct {
40 unsigned long brpn:15; /* Real page index (physical address) */
41 unsigned long :10; /* Unused */
42 unsigned long w:1; /* Write-thru cache */
43 unsigned long i:1; /* Cache inhibit */
44 unsigned long m:1; /* Memory coherence */
45 unsigned long g:1; /* Guarded (MBZ in IBAT) */
46 unsigned long :1; /* Unused */
47 unsigned long pp:2; /* Page access protections */
48 } batl; /* Lower register */
49};
50#endif /* !__ASSEMBLY__ */
51
52/*
53 * Hash table
54 */
55
56/* Values for PP (assumes Ks=0, Kp=1) */
57#define PP_RWXX 0 /* Supervisor read/write, User none */
58#define PP_RWRX 1 /* Supervisor read/write, User read */
59#define PP_RWRW 2 /* Supervisor read/write, User read/write */
60#define PP_RXRX 3 /* Supervisor read, User read */
61
62#ifndef __ASSEMBLY__
63
64/* Hardware Page Table Entry */
65struct hash_pte {
66 unsigned long v:1; /* Entry is valid */
67 unsigned long vsid:24; /* Virtual segment identifier */
68 unsigned long h:1; /* Hash algorithm indicator */
69 unsigned long api:6; /* Abbreviated page index */
70 unsigned long rpn:20; /* Real (physical) page number */
71 unsigned long :3; /* Unused */
72 unsigned long r:1; /* Referenced */
73 unsigned long c:1; /* Changed */
74 unsigned long w:1; /* Write-thru cache mode */
75 unsigned long i:1; /* Cache inhibited */
76 unsigned long m:1; /* Memory coherence */
77 unsigned long g:1; /* Guarded */
78 unsigned long :1; /* Unused */
79 unsigned long pp:2; /* Page protection */
80};
81
82typedef struct {
83 unsigned long id;
84 unsigned long vdso_base;
85} mm_context_t;
86
87typedef unsigned long phys_addr_t;
88
89#endif /* !__ASSEMBLY__ */
90
91#endif /* _ASM_POWERPC_MMU_HASH32_H_ */
diff --git a/include/asm-powerpc/mmu-hash64.h b/include/asm-powerpc/mmu-hash64.h
index b8dca30bd0b..695962f0205 100644
--- a/include/asm-powerpc/mmu-hash64.h
+++ b/include/asm-powerpc/mmu-hash64.h
@@ -94,6 +94,9 @@ extern char initial_stab[];
94#define HPTE_R_C ASM_CONST(0x0000000000000080) 94#define HPTE_R_C ASM_CONST(0x0000000000000080)
95#define HPTE_R_R ASM_CONST(0x0000000000000100) 95#define HPTE_R_R ASM_CONST(0x0000000000000100)
96 96
97#define HPTE_V_1TB_SEG ASM_CONST(0x4000000000000000)
98#define HPTE_V_VRMA_MASK ASM_CONST(0x4001ffffff000000)
99
97/* Values for PP (assumes Ks=0, Kp=1) */ 100/* Values for PP (assumes Ks=0, Kp=1) */
98/* pp0 will always be 0 for linux */ 101/* pp0 will always be 0 for linux */
99#define PP_RWXX 0 /* Supervisor read/write, User none */ 102#define PP_RWXX 0 /* Supervisor read/write, User none */
@@ -103,12 +106,12 @@ extern char initial_stab[];
103 106
104#ifndef __ASSEMBLY__ 107#ifndef __ASSEMBLY__
105 108
106typedef struct { 109struct hash_pte {
107 unsigned long v; 110 unsigned long v;
108 unsigned long r; 111 unsigned long r;
109} hpte_t; 112};
110 113
111extern hpte_t *htab_address; 114extern struct hash_pte *htab_address;
112extern unsigned long htab_size_bytes; 115extern unsigned long htab_size_bytes;
113extern unsigned long htab_hash_mask; 116extern unsigned long htab_hash_mask;
114 117
diff --git a/include/asm-powerpc/mmu.h b/include/asm-powerpc/mmu.h
index fe510fff890..d44d211e758 100644
--- a/include/asm-powerpc/mmu.h
+++ b/include/asm-powerpc/mmu.h
@@ -5,13 +5,18 @@
5#ifdef CONFIG_PPC64 5#ifdef CONFIG_PPC64
6/* 64-bit classic hash table MMU */ 6/* 64-bit classic hash table MMU */
7# include <asm/mmu-hash64.h> 7# include <asm/mmu-hash64.h>
8#elif defined(CONFIG_PPC_STD_MMU)
9/* 32-bit classic hash table MMU */
10# include <asm/mmu-hash32.h>
8#elif defined(CONFIG_44x) 11#elif defined(CONFIG_44x)
9/* 44x-style software loaded TLB */ 12/* 44x-style software loaded TLB */
10# include <asm/mmu-44x.h> 13# include <asm/mmu-44x.h>
11#else 14#elif defined(CONFIG_FSL_BOOKE)
12/* Other 32-bit. FIXME: split up the other 32-bit MMU types, and 15/* Freescale Book-E software loaded TLB */
13 * revise for arch/powerpc */ 16# include <asm/mmu-fsl-booke.h>
14# include <asm-ppc/mmu.h> 17#elif defined (CONFIG_PPC_8xx)
18/* Motorola/Freescale 8xx software loaded TLB */
19# include <asm/mmu-8xx.h>
15#endif 20#endif
16 21
17#endif /* __KERNEL__ */ 22#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/mmu_context.h b/include/asm-powerpc/mmu_context.h
index 40c9e5a13ff..f863ac21409 100644
--- a/include/asm-powerpc/mmu_context.h
+++ b/include/asm-powerpc/mmu_context.h
@@ -2,16 +2,210 @@
2#define __ASM_POWERPC_MMU_CONTEXT_H 2#define __ASM_POWERPC_MMU_CONTEXT_H
3#ifdef __KERNEL__ 3#ifdef __KERNEL__
4 4
5#include <asm/mmu.h>
6#include <asm/cputable.h>
7#include <asm-generic/mm_hooks.h>
8
5#ifndef CONFIG_PPC64 9#ifndef CONFIG_PPC64
6#include <asm-ppc/mmu_context.h> 10#include <asm/atomic.h>
11#include <asm/bitops.h>
12
13/*
14 * On 32-bit PowerPC 6xx/7xx/7xxx CPUs, we use a set of 16 VSIDs
15 * (virtual segment identifiers) for each context. Although the
16 * hardware supports 24-bit VSIDs, and thus >1 million contexts,
17 * we only use 32,768 of them. That is ample, since there can be
18 * at most around 30,000 tasks in the system anyway, and it means
19 * that we can use a bitmap to indicate which contexts are in use.
20 * Using a bitmap means that we entirely avoid all of the problems
21 * that we used to have when the context number overflowed,
22 * particularly on SMP systems.
23 * -- paulus.
24 */
25
26/*
27 * This function defines the mapping from contexts to VSIDs (virtual
28 * segment IDs). We use a skew on both the context and the high 4 bits
29 * of the 32-bit virtual address (the "effective segment ID") in order
30 * to spread out the entries in the MMU hash table. Note, if this
31 * function is changed then arch/ppc/mm/hashtable.S will have to be
32 * changed to correspond.
33 */
34#define CTX_TO_VSID(ctx, va) (((ctx) * (897 * 16) + ((va) >> 28) * 0x111) \
35 & 0xffffff)
36
37/*
38 The MPC8xx has only 16 contexts. We rotate through them on each
39 task switch. A better way would be to keep track of tasks that
40 own contexts, and implement an LRU usage. That way very active
41 tasks don't always have to pay the TLB reload overhead. The
42 kernel pages are mapped shared, so the kernel can run on behalf
43 of any task that makes a kernel entry. Shared does not mean they
44 are not protected, just that the ASID comparison is not performed.
45 -- Dan
46
47 The IBM4xx has 256 contexts, so we can just rotate through these
48 as a way of "switching" contexts. If the TID of the TLB is zero,
49 the PID/TID comparison is disabled, so we can use a TID of zero
50 to represent all kernel pages as shared among all contexts.
51 -- Dan
52 */
53
54static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
55{
56}
57
58#ifdef CONFIG_8xx
59#define NO_CONTEXT 16
60#define LAST_CONTEXT 15
61#define FIRST_CONTEXT 0
62
63#elif defined(CONFIG_4xx)
64#define NO_CONTEXT 256
65#define LAST_CONTEXT 255
66#define FIRST_CONTEXT 1
67
68#elif defined(CONFIG_E200) || defined(CONFIG_E500)
69#define NO_CONTEXT 256
70#define LAST_CONTEXT 255
71#define FIRST_CONTEXT 1
72
73#else
74
75/* PPC 6xx, 7xx CPUs */
76#define NO_CONTEXT ((unsigned long) -1)
77#define LAST_CONTEXT 32767
78#define FIRST_CONTEXT 1
79#endif
80
81/*
82 * Set the current MMU context.
83 * On 32-bit PowerPCs (other than the 8xx embedded chips), this is done by
84 * loading up the segment registers for the user part of the address space.
85 *
86 * Since the PGD is immediately available, it is much faster to simply
87 * pass this along as a second parameter, which is required for 8xx and
88 * can be used for debugging on all processors (if you happen to have
89 * an Abatron).
90 */
91extern void set_context(unsigned long contextid, pgd_t *pgd);
92
93/*
94 * Bitmap of contexts in use.
95 * The size of this bitmap is LAST_CONTEXT + 1 bits.
96 */
97extern unsigned long context_map[];
98
99/*
100 * This caches the next context number that we expect to be free.
101 * Its use is an optimization only, we can't rely on this context
102 * number to be free, but it usually will be.
103 */
104extern unsigned long next_mmu_context;
105
106/*
107 * If we don't have sufficient contexts to give one to every task
108 * that could be in the system, we need to be able to steal contexts.
109 * These variables support that.
110 */
111#if LAST_CONTEXT < 30000
112#define FEW_CONTEXTS 1
113extern atomic_t nr_free_contexts;
114extern struct mm_struct *context_mm[LAST_CONTEXT+1];
115extern void steal_context(void);
116#endif
117
118/*
119 * Get a new mmu context for the address space described by `mm'.
120 */
121static inline void get_mmu_context(struct mm_struct *mm)
122{
123 unsigned long ctx;
124
125 if (mm->context.id != NO_CONTEXT)
126 return;
127#ifdef FEW_CONTEXTS
128 while (atomic_dec_if_positive(&nr_free_contexts) < 0)
129 steal_context();
130#endif
131 ctx = next_mmu_context;
132 while (test_and_set_bit(ctx, context_map)) {
133 ctx = find_next_zero_bit(context_map, LAST_CONTEXT+1, ctx);
134 if (ctx > LAST_CONTEXT)
135 ctx = 0;
136 }
137 next_mmu_context = (ctx + 1) & LAST_CONTEXT;
138 mm->context.id = ctx;
139#ifdef FEW_CONTEXTS
140 context_mm[ctx] = mm;
141#endif
142}
143
144/*
145 * Set up the context for a new address space.
146 */
147static inline int init_new_context(struct task_struct *t, struct mm_struct *mm)
148{
149 mm->context.id = NO_CONTEXT;
150 mm->context.vdso_base = 0;
151 return 0;
152}
153
154/*
155 * We're finished using the context for an address space.
156 */
157static inline void destroy_context(struct mm_struct *mm)
158{
159 preempt_disable();
160 if (mm->context.id != NO_CONTEXT) {
161 clear_bit(mm->context.id, context_map);
162 mm->context.id = NO_CONTEXT;
163#ifdef FEW_CONTEXTS
164 atomic_inc(&nr_free_contexts);
165#endif
166 }
167 preempt_enable();
168}
169
170static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
171 struct task_struct *tsk)
172{
173#ifdef CONFIG_ALTIVEC
174 if (cpu_has_feature(CPU_FTR_ALTIVEC))
175 asm volatile ("dssall;\n"
176#ifndef CONFIG_POWER4
177 "sync;\n" /* G4 needs a sync here, G5 apparently not */
178#endif
179 : : );
180#endif /* CONFIG_ALTIVEC */
181
182 tsk->thread.pgdir = next->pgd;
183
184 /* No need to flush userspace segments if the mm doesnt change */
185 if (prev == next)
186 return;
187
188 /* Setup new userspace context */
189 get_mmu_context(next);
190 set_context(next->context.id, next->pgd);
191}
192
193#define deactivate_mm(tsk,mm) do { } while (0)
194
195/*
196 * After we have set current->mm to a new value, this activates
197 * the context for the new mm so we see the new mappings.
198 */
199#define activate_mm(active_mm, mm) switch_mm(active_mm, mm, current)
200
201extern void mmu_context_init(void);
202
203
7#else 204#else
8 205
9#include <linux/kernel.h> 206#include <linux/kernel.h>
10#include <linux/mm.h> 207#include <linux/mm.h>
11#include <linux/sched.h> 208#include <linux/sched.h>
12#include <asm/mmu.h>
13#include <asm/cputable.h>
14#include <asm-generic/mm_hooks.h>
15 209
16/* 210/*
17 * Copyright (C) 2001 PPC 64 Team, IBM Corp 211 * Copyright (C) 2001 PPC 64 Team, IBM Corp
diff --git a/include/asm-powerpc/mpc86xx.h b/include/asm-powerpc/mpc86xx.h
index b85df45b1a8..15f650f987e 100644
--- a/include/asm-powerpc/mpc86xx.h
+++ b/include/asm-powerpc/mpc86xx.h
@@ -19,12 +19,6 @@
19 19
20#ifdef CONFIG_PPC_86xx 20#ifdef CONFIG_PPC_86xx
21 21
22#define _IO_BASE isa_io_base
23#define _ISA_MEM_BASE isa_mem_base
24#ifdef CONFIG_PCI
25#define PCI_DRAM_OFFSET pci_dram_offset
26#endif
27
28#define CPU0_BOOT_RELEASE 0x01000000 22#define CPU0_BOOT_RELEASE 0x01000000
29#define CPU1_BOOT_RELEASE 0x02000000 23#define CPU1_BOOT_RELEASE 0x02000000
30#define CPU_ALL_RELEASED (CPU0_BOOT_RELEASE | CPU1_BOOT_RELEASE) 24#define CPU_ALL_RELEASED (CPU0_BOOT_RELEASE | CPU1_BOOT_RELEASE)
diff --git a/include/asm-powerpc/mpc8xx.h b/include/asm-powerpc/mpc8xx.h
index 580371120e1..2be014b6f57 100644
--- a/include/asm-powerpc/mpc8xx.h
+++ b/include/asm-powerpc/mpc8xx.h
@@ -23,6 +23,10 @@
23#include <platforms/8xx/mpc885ads.h> 23#include <platforms/8xx/mpc885ads.h>
24#endif 24#endif
25 25
26#ifdef CONFIG_PCMCIA_M8XX
27extern struct mpc8xx_pcmcia_ops m8xx_pcmcia_ops;
28#endif
29
26#endif /* CONFIG_8xx */ 30#endif /* CONFIG_8xx */
27#endif /* __CONFIG_8xx_DEFS */ 31#endif /* __CONFIG_8xx_DEFS */
28#endif /* __KERNEL__ */ 32#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h
index d9bf5aba96c..e72c2a60853 100644
--- a/include/asm-powerpc/pci-bridge.h
+++ b/include/asm-powerpc/pci-bridge.h
@@ -2,12 +2,91 @@
2#define _ASM_POWERPC_PCI_BRIDGE_H 2#define _ASM_POWERPC_PCI_BRIDGE_H
3#ifdef __KERNEL__ 3#ifdef __KERNEL__
4 4
5#include <linux/pci.h>
6#include <linux/list.h>
7#include <linux/ioport.h>
8
5#ifndef CONFIG_PPC64 9#ifndef CONFIG_PPC64
6#include <asm-ppc/pci-bridge.h> 10
11struct device_node;
12struct pci_controller;
13
14/*
15 * Structure of a PCI controller (host bridge)
16 */
17struct pci_controller {
18 struct pci_bus *bus;
19 char is_dynamic;
20 void *arch_data;
21 struct list_head list_node;
22 struct device *parent;
23
24 int first_busno;
25 int last_busno;
26 int self_busno;
27
28 void __iomem *io_base_virt;
29 resource_size_t io_base_phys;
30
31 /* Some machines (PReP) have a non 1:1 mapping of
32 * the PCI memory space in the CPU bus space
33 */
34 resource_size_t pci_mem_offset;
35
36 struct pci_ops *ops;
37 volatile unsigned int __iomem *cfg_addr;
38 volatile void __iomem *cfg_data;
39
40 /*
41 * Used for variants of PCI indirect handling and possible quirks:
42 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
43 * EXT_REG - provides access to PCI-e extended registers
44 * SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS
45 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
46 * to determine which bus number to match on when generating type0
47 * config cycles
48 */
49#define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001)
50#define PPC_INDIRECT_TYPE_EXT_REG (0x00000002)
51#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004)
52 u32 indirect_type;
53
54 /* Currently, we limit ourselves to 1 IO range and 3 mem
55 * ranges since the common pci_bus structure can't handle more
56 */
57 struct resource io_resource;
58 struct resource mem_resources[3];
59 int global_number; /* PCI domain number */
60};
61
62static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
63{
64 return bus->sysdata;
65}
66
67/* These are used for config access before all the PCI probing
68 has been done. */
69int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn,
70 int where, u8 *val);
71int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn,
72 int where, u16 *val);
73int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn,
74 int where, u32 *val);
75int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn,
76 int where, u8 val);
77int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn,
78 int where, u16 val);
79int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn,
80 int where, u32 val);
81
82extern void setup_indirect_pci_nomap(struct pci_controller* hose,
83 void __iomem *cfg_addr, void __iomem *cfg_data);
84extern void setup_indirect_pci(struct pci_controller* hose,
85 u32 cfg_addr, u32 cfg_data);
86extern void setup_grackle(struct pci_controller *hose);
87
7#else 88#else
8 89
9#include <linux/pci.h>
10#include <linux/list.h>
11 90
12/* 91/*
13 * This program is free software; you can redistribute it and/or 92 * This program is free software; you can redistribute it and/or
@@ -31,6 +110,7 @@ struct pci_controller {
31 int last_busno; 110 int last_busno;
32 111
33 void __iomem *io_base_virt; 112 void __iomem *io_base_virt;
113 void *io_base_alloc;
34 resource_size_t io_base_phys; 114 resource_size_t io_base_phys;
35 115
36 /* Some machines have a non 1:1 mapping of 116 /* Some machines have a non 1:1 mapping of
@@ -48,8 +128,7 @@ struct pci_controller {
48 */ 128 */
49 struct resource io_resource; 129 struct resource io_resource;
50 struct resource mem_resources[3]; 130 struct resource mem_resources[3];
51 int global_number; 131 int global_number;
52 int local_number;
53 unsigned long buid; 132 unsigned long buid;
54 unsigned long dma_window_base_cur; 133 unsigned long dma_window_base_cur;
55 unsigned long dma_window_size; 134 unsigned long dma_window_size;
@@ -70,19 +149,22 @@ struct pci_dn {
70 int devfn; /* pci device and function number */ 149 int devfn; /* pci device and function number */
71 int class_code; /* pci device class */ 150 int class_code; /* pci device class */
72 151
73#ifdef CONFIG_PPC_PSERIES 152 struct pci_controller *phb; /* for pci devices */
153 struct iommu_table *iommu_table; /* for phb's or bridges */
154 struct pci_dev *pcidev; /* back-pointer to the pci device */
155 struct device_node *node; /* back-pointer to the device_node */
156
157 int pci_ext_config_space; /* for pci devices */
158
159#ifdef CONFIG_EEH
74 int eeh_mode; /* See eeh.h for possible EEH_MODEs */ 160 int eeh_mode; /* See eeh.h for possible EEH_MODEs */
75 int eeh_config_addr; 161 int eeh_config_addr;
76 int eeh_pe_config_addr; /* new-style partition endpoint address */ 162 int eeh_pe_config_addr; /* new-style partition endpoint address */
77 int eeh_check_count; /* # times driver ignored error */ 163 int eeh_check_count; /* # times driver ignored error */
78 int eeh_freeze_count; /* # times this device froze up. */ 164 int eeh_freeze_count; /* # times this device froze up. */
79#endif 165 int eeh_false_positives; /* # times this device reported #ff's */
80 int pci_ext_config_space; /* for pci devices */
81 struct pci_controller *phb; /* for pci devices */
82 struct iommu_table *iommu_table; /* for phb's or bridges */
83 struct pci_dev *pcidev; /* back-pointer to the pci device */
84 struct device_node *node; /* back-pointer to the device_node */
85 u32 config_space[16]; /* saved PCI config space */ 166 u32 config_space[16]; /* saved PCI config space */
167#endif
86}; 168};
87 169
88/* Get the pointer to a device_node's pci_dn */ 170/* Get the pointer to a device_node's pci_dn */
@@ -128,9 +210,6 @@ static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
128/** Find the bus corresponding to the indicated device node */ 210/** Find the bus corresponding to the indicated device node */
129struct pci_bus * pcibios_find_pci_bus(struct device_node *dn); 211struct pci_bus * pcibios_find_pci_bus(struct device_node *dn);
130 212
131extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
132 struct device_node *dev, int primary);
133
134/** Remove all of the PCI devices under this bus */ 213/** Remove all of the PCI devices under this bus */
135void pcibios_remove_pci_devices(struct pci_bus *bus); 214void pcibios_remove_pci_devices(struct pci_bus *bus);
136 215
@@ -148,13 +227,38 @@ static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
148 return PCI_DN(busdn)->phb; 227 return PCI_DN(busdn)->phb;
149} 228}
150 229
230extern void pcibios_free_controller(struct pci_controller *phb);
231
232extern void isa_bridge_find_early(struct pci_controller *hose);
233
234extern int pcibios_unmap_io_space(struct pci_bus *bus);
235extern int pcibios_map_io_space(struct pci_bus *bus);
236
237/* Return values for ppc_md.pci_probe_mode function */
238#define PCI_PROBE_NONE -1 /* Don't look at this bus at all */
239#define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */
240#define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */
241
242#ifdef CONFIG_NUMA
243#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
244#else
245#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
246#endif
247
248#endif /* CONFIG_PPC64 */
249
250/* Get the PCI host controller for an OF device */
151extern struct pci_controller* 251extern struct pci_controller*
152pci_find_hose_for_OF_device(struct device_node* node); 252pci_find_hose_for_OF_device(struct device_node* node);
153 253
254/* Fill up host controller resources from the OF node */
255extern void
256pci_process_bridge_OF_ranges(struct pci_controller *hose,
257 struct device_node *dev, int primary);
258
259/* Allocate a new PCI host bridge structure */
154extern struct pci_controller * 260extern struct pci_controller *
155pcibios_alloc_controller(struct device_node *dev); 261pcibios_alloc_controller(struct device_node *dev);
156extern void pcibios_free_controller(struct pci_controller *phb);
157
158#ifdef CONFIG_PCI 262#ifdef CONFIG_PCI
159extern unsigned long pci_address_to_pio(phys_addr_t address); 263extern unsigned long pci_address_to_pio(phys_addr_t address);
160#else 264#else
@@ -164,17 +268,7 @@ static inline unsigned long pci_address_to_pio(phys_addr_t address)
164} 268}
165#endif 269#endif
166 270
167/* Return values for ppc_md.pci_probe_mode function */
168#define PCI_PROBE_NONE -1 /* Don't look at this bus at all */
169#define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */
170#define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */
171 271
172#ifdef CONFIG_NUMA
173#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
174#else
175#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
176#endif
177 272
178#endif /* CONFIG_PPC64 */
179#endif /* __KERNEL__ */ 273#endif /* __KERNEL__ */
180#endif 274#endif
diff --git a/include/asm-powerpc/pci.h b/include/asm-powerpc/pci.h
index ce0f13e8eb1..0cd3e77efd2 100644
--- a/include/asm-powerpc/pci.h
+++ b/include/asm-powerpc/pci.h
@@ -107,8 +107,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
107#define get_pci_dma_ops() NULL 107#define get_pci_dma_ops() NULL
108#endif 108#endif
109 109
110extern int pci_domain_nr(struct pci_bus *bus);
111
112/* Decide whether to display the domain number in /proc */ 110/* Decide whether to display the domain number in /proc */
113extern int pci_proc_domain(struct pci_bus *bus); 111extern int pci_proc_domain(struct pci_bus *bus);
114 112
@@ -130,9 +128,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
130 */ 128 */
131#define pci_dac_dma_supported(pci_dev, mask) (0) 129#define pci_dac_dma_supported(pci_dev, mask) (0)
132 130
133/* Return the index of the PCI controller for device PDEV. */
134#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
135
136/* Set the name of the bus as it appears in /proc/bus/pci */ 131/* Set the name of the bus as it appears in /proc/bus/pci */
137static inline int pci_proc_domain(struct pci_bus *bus) 132static inline int pci_proc_domain(struct pci_bus *bus)
138{ 133{
@@ -141,6 +136,8 @@ static inline int pci_proc_domain(struct pci_bus *bus)
141 136
142#endif /* CONFIG_PPC64 */ 137#endif /* CONFIG_PPC64 */
143 138
139extern int pci_domain_nr(struct pci_bus *bus);
140
144struct vm_area_struct; 141struct vm_area_struct;
145/* Map a range of PCI memory or I/O space for a device into user space */ 142/* Map a range of PCI memory or I/O space for a device into user space */
146int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma, 143int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
@@ -220,10 +217,6 @@ static inline struct resource *pcibios_select_root(struct pci_dev *pdev,
220 return root; 217 return root;
221} 218}
222 219
223extern int unmap_bus_range(struct pci_bus *bus);
224
225extern int remap_bus_range(struct pci_bus *bus);
226
227extern void pcibios_fixup_device_resources(struct pci_dev *dev, 220extern void pcibios_fixup_device_resources(struct pci_dev *dev,
228 struct pci_bus *bus); 221 struct pci_bus *bus);
229 222
diff --git a/include/asm-powerpc/pgtable-ppc32.h b/include/asm-powerpc/pgtable-ppc32.h
index 7fb730c62f8..b2b880a6f63 100644
--- a/include/asm-powerpc/pgtable-ppc32.h
+++ b/include/asm-powerpc/pgtable-ppc32.h
@@ -6,11 +6,7 @@
6#ifndef __ASSEMBLY__ 6#ifndef __ASSEMBLY__
7#include <linux/sched.h> 7#include <linux/sched.h>
8#include <linux/threads.h> 8#include <linux/threads.h>
9#include <asm/processor.h> /* For TASK_SIZE */
10#include <asm/mmu.h>
11#include <asm/page.h>
12#include <asm/io.h> /* For sub-arch specific PPC_PIN_SIZE */ 9#include <asm/io.h> /* For sub-arch specific PPC_PIN_SIZE */
13struct mm_struct;
14 10
15extern unsigned long va_to_phys(unsigned long address); 11extern unsigned long va_to_phys(unsigned long address);
16extern pte_t *va_to_pte(unsigned long address); 12extern pte_t *va_to_pte(unsigned long address);
@@ -488,14 +484,6 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
488#define pfn_pte(pfn, prot) __pte(((pte_basic_t)(pfn) << PFN_SHIFT_OFFSET) |\ 484#define pfn_pte(pfn, prot) __pte(((pte_basic_t)(pfn) << PFN_SHIFT_OFFSET) |\
489 pgprot_val(prot)) 485 pgprot_val(prot))
490#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot) 486#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
491
492/*
493 * ZERO_PAGE is a global shared page that is always zero: used
494 * for zero-mapped memory areas etc..
495 */
496extern unsigned long empty_zero_page[1024];
497#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
498
499#endif /* __ASSEMBLY__ */ 487#endif /* __ASSEMBLY__ */
500 488
501#define pte_none(pte) ((pte_val(pte) & ~_PTE_NONE_MASK) == 0) 489#define pte_none(pte) ((pte_val(pte) & ~_PTE_NONE_MASK) == 0)
@@ -734,10 +722,6 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
734#define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0) 722#define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0)
735#define pte_unmap_nested(pte) kunmap_atomic(pte, KM_PTE1) 723#define pte_unmap_nested(pte) kunmap_atomic(pte, KM_PTE1)
736 724
737extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
738
739extern void paging_init(void);
740
741/* 725/*
742 * Encode and decode a swap entry. 726 * Encode and decode a swap entry.
743 * Note that the bits we use in a PTE for representing a swap entry 727 * Note that the bits we use in a PTE for representing a swap entry
@@ -755,40 +739,6 @@ extern void paging_init(void);
755#define pte_to_pgoff(pte) (pte_val(pte) >> 3) 739#define pte_to_pgoff(pte) (pte_val(pte) >> 3)
756#define pgoff_to_pte(off) ((pte_t) { ((off) << 3) | _PAGE_FILE }) 740#define pgoff_to_pte(off) ((pte_t) { ((off) << 3) | _PAGE_FILE })
757 741
758/* CONFIG_APUS */
759/* For virtual address to physical address conversion */
760extern void cache_clear(__u32 addr, int length);
761extern void cache_push(__u32 addr, int length);
762extern int mm_end_of_chunk (unsigned long addr, int len);
763extern unsigned long iopa(unsigned long addr);
764extern unsigned long mm_ptov(unsigned long addr) __attribute_const__;
765
766/* Values for nocacheflag and cmode */
767/* These are not used by the APUS kernel_map, but prevents
768 compilation errors. */
769#define KERNELMAP_FULL_CACHING 0
770#define KERNELMAP_NOCACHE_SER 1
771#define KERNELMAP_NOCACHE_NONSER 2
772#define KERNELMAP_NO_COPYBACK 3
773
774/*
775 * Map some physical address range into the kernel address space.
776 */
777extern unsigned long kernel_map(unsigned long paddr, unsigned long size,
778 int nocacheflag, unsigned long *memavailp );
779
780/*
781 * Set cache mode of (kernel space) address range.
782 */
783extern void kernel_set_cachemode (unsigned long address, unsigned long size,
784 unsigned int cmode);
785
786/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
787#define kern_addr_valid(addr) (1)
788
789#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
790 remap_pfn_range(vma, vaddr, pfn, size, prot)
791
792/* 742/*
793 * No page table caches to initialise 743 * No page table caches to initialise
794 */ 744 */
diff --git a/include/asm-powerpc/pgtable-ppc64.h b/include/asm-powerpc/pgtable-ppc64.h
index 3cfd98f44bf..4ea99922a75 100644
--- a/include/asm-powerpc/pgtable-ppc64.h
+++ b/include/asm-powerpc/pgtable-ppc64.h
@@ -7,11 +7,7 @@
7 7
8#ifndef __ASSEMBLY__ 8#ifndef __ASSEMBLY__
9#include <linux/stddef.h> 9#include <linux/stddef.h>
10#include <asm/processor.h> /* For TASK_SIZE */
11#include <asm/mmu.h>
12#include <asm/page.h>
13#include <asm/tlbflush.h> 10#include <asm/tlbflush.h>
14struct mm_struct;
15#endif /* __ASSEMBLY__ */ 11#endif /* __ASSEMBLY__ */
16 12
17#ifdef CONFIG_PPC_64K_PAGES 13#ifdef CONFIG_PPC_64K_PAGES
@@ -27,7 +23,7 @@ struct mm_struct;
27 */ 23 */
28#define PGTABLE_EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \ 24#define PGTABLE_EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \
29 PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT) 25 PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT)
30#define PGTABLE_RANGE (1UL << PGTABLE_EADDR_SIZE) 26#define PGTABLE_RANGE (ASM_CONST(1) << PGTABLE_EADDR_SIZE)
31 27
32#if TASK_SIZE_USER64 > PGTABLE_RANGE 28#if TASK_SIZE_USER64 > PGTABLE_RANGE
33#error TASK_SIZE_USER64 exceeds pagetable range 29#error TASK_SIZE_USER64 exceeds pagetable range
@@ -37,19 +33,28 @@ struct mm_struct;
37#error TASK_SIZE_USER64 exceeds user VSID range 33#error TASK_SIZE_USER64 exceeds user VSID range
38#endif 34#endif
39 35
36
40/* 37/*
41 * Define the address range of the vmalloc VM area. 38 * Define the address range of the vmalloc VM area.
42 */ 39 */
43#define VMALLOC_START ASM_CONST(0xD000000000000000) 40#define VMALLOC_START ASM_CONST(0xD000000000000000)
44#define VMALLOC_SIZE ASM_CONST(0x80000000000) 41#define VMALLOC_SIZE (PGTABLE_RANGE >> 1)
45#define VMALLOC_END (VMALLOC_START + VMALLOC_SIZE) 42#define VMALLOC_END (VMALLOC_START + VMALLOC_SIZE)
46 43
47/* 44/*
48 * Define the address range of the imalloc VM area. 45 * Define the address ranges for MMIO and IO space :
46 *
47 * ISA_IO_BASE = VMALLOC_END, 64K reserved area
48 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
49 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
49 */ 50 */
50#define PHBS_IO_BASE VMALLOC_END 51#define FULL_IO_SIZE 0x80000000ul
51#define IMALLOC_BASE (PHBS_IO_BASE + 0x80000000ul) /* Reserve 2 gigs for PHBs */ 52#define ISA_IO_BASE (VMALLOC_END)
52#define IMALLOC_END (VMALLOC_START + PGTABLE_RANGE) 53#define ISA_IO_END (VMALLOC_END + 0x10000ul)
54#define PHB_IO_BASE (ISA_IO_END)
55#define PHB_IO_END (VMALLOC_END + FULL_IO_SIZE)
56#define IOREMAP_BASE (PHB_IO_END)
57#define IOREMAP_END (VMALLOC_START + PGTABLE_RANGE)
53 58
54/* 59/*
55 * Region IDs 60 * Region IDs
@@ -134,16 +139,6 @@ struct mm_struct;
134#define __S110 PAGE_SHARED_X 139#define __S110 PAGE_SHARED_X
135#define __S111 PAGE_SHARED_X 140#define __S111 PAGE_SHARED_X
136 141
137#ifndef __ASSEMBLY__
138
139/*
140 * ZERO_PAGE is a global shared page that is always zero: used
141 * for zero-mapped memory areas etc..
142 */
143extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)];
144#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
145#endif /* __ASSEMBLY__ */
146
147#ifdef CONFIG_HUGETLB_PAGE 142#ifdef CONFIG_HUGETLB_PAGE
148 143
149#define HAVE_ARCH_UNMAPPED_AREA 144#define HAVE_ARCH_UNMAPPED_AREA
@@ -442,10 +437,6 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
442#define pgd_ERROR(e) \ 437#define pgd_ERROR(e) \
443 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 438 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
444 439
445extern pgd_t swapper_pg_dir[];
446
447extern void paging_init(void);
448
449/* Encode and de-code a swap entry */ 440/* Encode and de-code a swap entry */
450#define __swp_type(entry) (((entry).val >> 1) & 0x3f) 441#define __swp_type(entry) (((entry).val >> 1) & 0x3f)
451#define __swp_offset(entry) ((entry).val >> 8) 442#define __swp_offset(entry) ((entry).val >> 8)
@@ -456,17 +447,6 @@ extern void paging_init(void);
456#define pgoff_to_pte(off) ((pte_t) {((off) << PTE_RPN_SHIFT)|_PAGE_FILE}) 447#define pgoff_to_pte(off) ((pte_t) {((off) << PTE_RPN_SHIFT)|_PAGE_FILE})
457#define PTE_FILE_MAX_BITS (BITS_PER_LONG - PTE_RPN_SHIFT) 448#define PTE_FILE_MAX_BITS (BITS_PER_LONG - PTE_RPN_SHIFT)
458 449
459/*
460 * kern_addr_valid is intended to indicate whether an address is a valid
461 * kernel address. Most 32-bit archs define it as always true (like this)
462 * but most 64-bit archs actually perform a test. What should we do here?
463 * The only use is in fs/ncpfs/dir.c
464 */
465#define kern_addr_valid(addr) (1)
466
467#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
468 remap_pfn_range(vma, vaddr, pfn, size, prot)
469
470void pgtable_cache_init(void); 450void pgtable_cache_init(void);
471 451
472/* 452/*
diff --git a/include/asm-powerpc/pgtable.h b/include/asm-powerpc/pgtable.h
index 78bf4ae712a..d18ffe7bc7c 100644
--- a/include/asm-powerpc/pgtable.h
+++ b/include/asm-powerpc/pgtable.h
@@ -2,6 +2,13 @@
2#define _ASM_POWERPC_PGTABLE_H 2#define _ASM_POWERPC_PGTABLE_H
3#ifdef __KERNEL__ 3#ifdef __KERNEL__
4 4
5#ifndef __ASSEMBLY__
6#include <asm/processor.h> /* For TASK_SIZE */
7#include <asm/mmu.h>
8#include <asm/page.h>
9struct mm_struct;
10#endif /* !__ASSEMBLY__ */
11
5#if defined(CONFIG_PPC64) 12#if defined(CONFIG_PPC64)
6# include <asm/pgtable-ppc64.h> 13# include <asm/pgtable-ppc64.h>
7#else 14#else
@@ -9,6 +16,27 @@
9#endif 16#endif
10 17
11#ifndef __ASSEMBLY__ 18#ifndef __ASSEMBLY__
19/*
20 * ZERO_PAGE is a global shared page that is always zero: used
21 * for zero-mapped memory areas etc..
22 */
23extern unsigned long empty_zero_page[];
24#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
25
26extern pgd_t swapper_pg_dir[];
27
28extern void paging_init(void);
29
30/*
31 * kern_addr_valid is intended to indicate whether an address is a valid
32 * kernel address. Most 32-bit archs define it as always true (like this)
33 * but most 64-bit archs actually perform a test. What should we do here?
34 */
35#define kern_addr_valid(addr) (1)
36
37#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
38 remap_pfn_range(vma, vaddr, pfn, size, prot)
39
12#include <asm-generic/pgtable.h> 40#include <asm-generic/pgtable.h>
13#endif /* __ASSEMBLY__ */ 41#endif /* __ASSEMBLY__ */
14 42
diff --git a/include/asm-powerpc/ppc-pci.h b/include/asm-powerpc/ppc-pci.h
index 8e2005159ff..b847aa10074 100644
--- a/include/asm-powerpc/ppc-pci.h
+++ b/include/asm-powerpc/ppc-pci.h
@@ -26,7 +26,7 @@ extern int global_phb_number;
26 26
27extern void find_and_init_phbs(void); 27extern void find_and_init_phbs(void);
28 28
29extern struct pci_dev *ppc64_isabridge_dev; /* may be NULL if no ISA bus */ 29extern struct pci_dev *isa_bridge_pcidev; /* may be NULL if no ISA bus */
30 30
31/** Bus Unit ID macros; get low and hi 32-bits of the 64-bit BUID */ 31/** Bus Unit ID macros; get low and hi 32-bits of the 64-bit BUID */
32#define BUID_HI(buid) ((buid) >> 32) 32#define BUID_HI(buid) ((buid) >> 32)
@@ -47,8 +47,8 @@ extern void init_pci_config_tokens (void);
47extern unsigned long get_phb_buid (struct device_node *); 47extern unsigned long get_phb_buid (struct device_node *);
48extern int rtas_setup_phb(struct pci_controller *phb); 48extern int rtas_setup_phb(struct pci_controller *phb);
49 49
50/* From pSeries_pci.h */ 50/* From iSeries PCI */
51extern void pSeries_final_fixup(void); 51extern void iSeries_pcibios_init(void);
52 52
53extern unsigned long pci_probe_only; 53extern unsigned long pci_probe_only;
54 54
@@ -139,6 +139,9 @@ void eeh_clear_slot (struct device_node *dn, int mode_flag);
139 */ 139 */
140struct device_node * find_device_pe(struct device_node *dn); 140struct device_node * find_device_pe(struct device_node *dn);
141 141
142void eeh_sysfs_add_device(struct pci_dev *pdev);
143void eeh_sysfs_remove_device(struct pci_dev *pdev);
144
142#endif /* CONFIG_EEH */ 145#endif /* CONFIG_EEH */
143 146
144#else /* CONFIG_PCI */ 147#else /* CONFIG_PCI */
diff --git a/include/asm-powerpc/processor.h b/include/asm-powerpc/processor.h
index d947b160949..e28b1080515 100644
--- a/include/asm-powerpc/processor.h
+++ b/include/asm-powerpc/processor.h
@@ -43,14 +43,6 @@ extern int _chrp_type;
43/* what kind of prep workstation we are */ 43/* what kind of prep workstation we are */
44extern int _prep_type; 44extern int _prep_type;
45 45
46/*
47 * This is used to identify the board type from a given PReP board
48 * vendor. Board revision is also made available. This will be moved
49 * elsewhere soon
50 */
51extern unsigned char ucBoardRev;
52extern unsigned char ucBoardRevMaj, ucBoardRevMin;
53
54#endif /* CONFIG_PPC_PREP */ 46#endif /* CONFIG_PPC_PREP */
55 47
56#endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */ 48#endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
diff --git a/include/asm-powerpc/prom.h b/include/asm-powerpc/prom.h
index 6845af93ba9..1632baa17dc 100644
--- a/include/asm-powerpc/prom.h
+++ b/include/asm-powerpc/prom.h
@@ -98,10 +98,19 @@ struct device_node {
98extern struct device_node *of_chosen; 98extern struct device_node *of_chosen;
99 99
100/* flag descriptions */ 100/* flag descriptions */
101#define OF_DYNAMIC 1 /* node and properties were allocated via kmalloc */ 101#define OF_DYNAMIC 1 /* node and properties were allocated via kmalloc */
102#define OF_DETACHED 2 /* node has been detached from the device tree */
103
104static inline int of_node_check_flag(struct device_node *n, unsigned long flag)
105{
106 return test_bit(flag, &n->_flags);
107}
108
109static inline void of_node_set_flag(struct device_node *n, unsigned long flag)
110{
111 set_bit(flag, &n->_flags);
112}
102 113
103#define OF_IS_DYNAMIC(x) test_bit(OF_DYNAMIC, &x->_flags)
104#define OF_MARK_DYNAMIC(x) set_bit(OF_DYNAMIC, &x->_flags)
105 114
106#define HAVE_ARCH_DEVTREE_FIXUPS 115#define HAVE_ARCH_DEVTREE_FIXUPS
107 116
@@ -124,6 +133,9 @@ extern struct device_node *of_find_node_by_type(struct device_node *from,
124 dn = of_find_node_by_type(dn, type)) 133 dn = of_find_node_by_type(dn, type))
125extern struct device_node *of_find_compatible_node(struct device_node *from, 134extern struct device_node *of_find_compatible_node(struct device_node *from,
126 const char *type, const char *compat); 135 const char *type, const char *compat);
136#define for_each_compatible_node(dn, type, compatible) \
137 for (dn = of_find_compatible_node(NULL, type, compatible); dn; \
138 dn = of_find_compatible_node(dn, type, compatible))
127extern struct device_node *of_find_node_by_path(const char *path); 139extern struct device_node *of_find_node_by_path(const char *path);
128extern struct device_node *of_find_node_by_phandle(phandle handle); 140extern struct device_node *of_find_node_by_phandle(phandle handle);
129extern struct device_node *of_find_all_nodes(struct device_node *prev); 141extern struct device_node *of_find_all_nodes(struct device_node *prev);
diff --git a/include/asm-powerpc/ps3.h b/include/asm-powerpc/ps3.h
index 1e04651eedc..a6f3f5ee7ca 100644
--- a/include/asm-powerpc/ps3.h
+++ b/include/asm-powerpc/ps3.h
@@ -35,7 +35,8 @@ union ps3_firmware_version {
35 }; 35 };
36}; 36};
37 37
38int ps3_get_firmware_version(union ps3_firmware_version *v); 38void ps3_get_firmware_version(union ps3_firmware_version *v);
39int ps3_compare_firmware_version(u16 major, u16 minor, u16 rev);
39 40
40/* 'Other OS' area */ 41/* 'Other OS' area */
41 42
@@ -48,18 +49,6 @@ enum ps3_param_av_multi_out {
48 49
49enum ps3_param_av_multi_out ps3_os_area_get_av_multi_out(void); 50enum ps3_param_av_multi_out ps3_os_area_get_av_multi_out(void);
50 51
51/**
52 * struct ps3_device_id - HV bus device identifier from the system repository
53 * @bus_id: HV bus id, {1..} (zero invalid)
54 * @dev_id: HV device id, {0..}
55 */
56
57struct ps3_device_id {
58 unsigned int bus_id;
59 unsigned int dev_id;
60};
61
62
63/* dma routines */ 52/* dma routines */
64 53
65enum ps3_dma_page_size { 54enum ps3_dma_page_size {
@@ -74,6 +63,8 @@ enum ps3_dma_region_type {
74 PS3_DMA_INTERNAL = 2, 63 PS3_DMA_INTERNAL = 2,
75}; 64};
76 65
66struct ps3_dma_region_ops;
67
77/** 68/**
78 * struct ps3_dma_region - A per device dma state variables structure 69 * struct ps3_dma_region - A per device dma state variables structure
79 * @did: The HV device id. 70 * @did: The HV device id.
@@ -81,21 +72,42 @@ enum ps3_dma_region_type {
81 * @region_type: The HV region type. 72 * @region_type: The HV region type.
82 * @bus_addr: The 'translated' bus address of the region. 73 * @bus_addr: The 'translated' bus address of the region.
83 * @len: The length in bytes of the region. 74 * @len: The length in bytes of the region.
75 * @offset: The offset from the start of memory of the region.
76 * @ioid: The IOID of the device who owns this region
84 * @chunk_list: Opaque variable used by the ioc page manager. 77 * @chunk_list: Opaque variable used by the ioc page manager.
78 * @region_ops: struct ps3_dma_region_ops - dma region operations
85 */ 79 */
86 80
87struct ps3_dma_region { 81struct ps3_dma_region {
88 struct ps3_device_id did; 82 struct ps3_system_bus_device *dev;
83 /* device variables */
84 const struct ps3_dma_region_ops *region_ops;
85 unsigned char ioid;
89 enum ps3_dma_page_size page_size; 86 enum ps3_dma_page_size page_size;
90 enum ps3_dma_region_type region_type; 87 enum ps3_dma_region_type region_type;
91 unsigned long bus_addr;
92 unsigned long len; 88 unsigned long len;
89 unsigned long offset;
90
91 /* driver variables (set by ps3_dma_region_create) */
92 unsigned long bus_addr;
93 struct { 93 struct {
94 spinlock_t lock; 94 spinlock_t lock;
95 struct list_head head; 95 struct list_head head;
96 } chunk_list; 96 } chunk_list;
97}; 97};
98 98
99struct ps3_dma_region_ops {
100 int (*create)(struct ps3_dma_region *);
101 int (*free)(struct ps3_dma_region *);
102 int (*map)(struct ps3_dma_region *,
103 unsigned long virt_addr,
104 unsigned long len,
105 unsigned long *bus_addr,
106 u64 iopte_pp);
107 int (*unmap)(struct ps3_dma_region *,
108 unsigned long bus_addr,
109 unsigned long len);
110};
99/** 111/**
100 * struct ps3_dma_region_init - Helper to initialize structure variables 112 * struct ps3_dma_region_init - Helper to initialize structure variables
101 * 113 *
@@ -103,18 +115,16 @@ struct ps3_dma_region {
103 * ps3_system_bus_device_register. 115 * ps3_system_bus_device_register.
104 */ 116 */
105 117
106static inline void ps3_dma_region_init(struct ps3_dma_region *r, 118struct ps3_system_bus_device;
107 const struct ps3_device_id* did, enum ps3_dma_page_size page_size, 119
108 enum ps3_dma_region_type region_type) 120int ps3_dma_region_init(struct ps3_system_bus_device *dev,
109{ 121 struct ps3_dma_region *r, enum ps3_dma_page_size page_size,
110 r->did = *did; 122 enum ps3_dma_region_type region_type, void *addr, unsigned long len);
111 r->page_size = page_size;
112 r->region_type = region_type;
113}
114int ps3_dma_region_create(struct ps3_dma_region *r); 123int ps3_dma_region_create(struct ps3_dma_region *r);
115int ps3_dma_region_free(struct ps3_dma_region *r); 124int ps3_dma_region_free(struct ps3_dma_region *r);
116int ps3_dma_map(struct ps3_dma_region *r, unsigned long virt_addr, 125int ps3_dma_map(struct ps3_dma_region *r, unsigned long virt_addr,
117 unsigned long len, unsigned long *bus_addr); 126 unsigned long len, unsigned long *bus_addr,
127 u64 iopte_pp);
118int ps3_dma_unmap(struct ps3_dma_region *r, unsigned long bus_addr, 128int ps3_dma_unmap(struct ps3_dma_region *r, unsigned long bus_addr,
119 unsigned long len); 129 unsigned long len);
120 130
@@ -125,6 +135,7 @@ enum ps3_mmio_page_size {
125 PS3_MMIO_64K = 16U 135 PS3_MMIO_64K = 16U
126}; 136};
127 137
138struct ps3_mmio_region_ops;
128/** 139/**
129 * struct ps3_mmio_region - a per device mmio state variables structure 140 * struct ps3_mmio_region - a per device mmio state variables structure
130 * 141 *
@@ -132,13 +143,18 @@ enum ps3_mmio_page_size {
132 */ 143 */
133 144
134struct ps3_mmio_region { 145struct ps3_mmio_region {
135 struct ps3_device_id did; 146 struct ps3_system_bus_device *dev;
147 const struct ps3_mmio_region_ops *mmio_ops;
136 unsigned long bus_addr; 148 unsigned long bus_addr;
137 unsigned long len; 149 unsigned long len;
138 enum ps3_mmio_page_size page_size; 150 enum ps3_mmio_page_size page_size;
139 unsigned long lpar_addr; 151 unsigned long lpar_addr;
140}; 152};
141 153
154struct ps3_mmio_region_ops {
155 int (*create)(struct ps3_mmio_region *);
156 int (*free)(struct ps3_mmio_region *);
157};
142/** 158/**
143 * struct ps3_mmio_region_init - Helper to initialize structure variables 159 * struct ps3_mmio_region_init - Helper to initialize structure variables
144 * 160 *
@@ -146,15 +162,9 @@ struct ps3_mmio_region {
146 * ps3_system_bus_device_register. 162 * ps3_system_bus_device_register.
147 */ 163 */
148 164
149static inline void ps3_mmio_region_init(struct ps3_mmio_region *r, 165int ps3_mmio_region_init(struct ps3_system_bus_device *dev,
150 const struct ps3_device_id* did, unsigned long bus_addr, 166 struct ps3_mmio_region *r, unsigned long bus_addr, unsigned long len,
151 unsigned long len, enum ps3_mmio_page_size page_size) 167 enum ps3_mmio_page_size page_size);
152{
153 r->did = *did;
154 r->bus_addr = bus_addr;
155 r->len = len;
156 r->page_size = page_size;
157}
158int ps3_mmio_region_create(struct ps3_mmio_region *r); 168int ps3_mmio_region_create(struct ps3_mmio_region *r);
159int ps3_free_mmio_region(struct ps3_mmio_region *r); 169int ps3_free_mmio_region(struct ps3_mmio_region *r);
160unsigned long ps3_mm_phys_to_lpar(unsigned long phys_addr); 170unsigned long ps3_mm_phys_to_lpar(unsigned long phys_addr);
@@ -187,11 +197,10 @@ int ps3_spe_irq_setup(enum ps3_cpu_binding cpu, unsigned long spe_id,
187 unsigned int class, unsigned int *virq); 197 unsigned int class, unsigned int *virq);
188int ps3_spe_irq_destroy(unsigned int virq); 198int ps3_spe_irq_destroy(unsigned int virq);
189 199
190int ps3_sb_event_receive_port_setup(enum ps3_cpu_binding cpu, 200int ps3_sb_event_receive_port_setup(struct ps3_system_bus_device *dev,
191 const struct ps3_device_id *did, unsigned int interrupt_id, 201 enum ps3_cpu_binding cpu, unsigned int *virq);
192 unsigned int *virq); 202int ps3_sb_event_receive_port_destroy(struct ps3_system_bus_device *dev,
193int ps3_sb_event_receive_port_destroy(const struct ps3_device_id *did, 203 unsigned int virq);
194 unsigned int interrupt_id, unsigned int virq);
195 204
196/* lv1 result codes */ 205/* lv1 result codes */
197 206
@@ -289,11 +298,33 @@ static inline const char* ps3_result(int result)
289/* system bus routines */ 298/* system bus routines */
290 299
291enum ps3_match_id { 300enum ps3_match_id {
292 PS3_MATCH_ID_EHCI = 1, 301 PS3_MATCH_ID_EHCI = 1,
293 PS3_MATCH_ID_OHCI, 302 PS3_MATCH_ID_OHCI = 2,
294 PS3_MATCH_ID_GELIC, 303 PS3_MATCH_ID_GELIC = 3,
295 PS3_MATCH_ID_AV_SETTINGS, 304 PS3_MATCH_ID_AV_SETTINGS = 4,
296 PS3_MATCH_ID_SYSTEM_MANAGER, 305 PS3_MATCH_ID_SYSTEM_MANAGER = 5,
306 PS3_MATCH_ID_STOR_DISK = 6,
307 PS3_MATCH_ID_STOR_ROM = 7,
308 PS3_MATCH_ID_STOR_FLASH = 8,
309 PS3_MATCH_ID_SOUND = 9,
310 PS3_MATCH_ID_GRAPHICS = 10,
311};
312
313#define PS3_MODULE_ALIAS_EHCI "ps3:1"
314#define PS3_MODULE_ALIAS_OHCI "ps3:2"
315#define PS3_MODULE_ALIAS_GELIC "ps3:3"
316#define PS3_MODULE_ALIAS_AV_SETTINGS "ps3:4"
317#define PS3_MODULE_ALIAS_SYSTEM_MANAGER "ps3:5"
318#define PS3_MODULE_ALIAS_STOR_DISK "ps3:6"
319#define PS3_MODULE_ALIAS_STOR_ROM "ps3:7"
320#define PS3_MODULE_ALIAS_STOR_FLASH "ps3:8"
321#define PS3_MODULE_ALIAS_SOUND "ps3:9"
322#define PS3_MODULE_ALIAS_GRAPHICS "ps3:10"
323
324enum ps3_system_bus_device_type {
325 PS3_DEVICE_TYPE_IOC0 = 1,
326 PS3_DEVICE_TYPE_SB,
327 PS3_DEVICE_TYPE_VUART,
297}; 328};
298 329
299/** 330/**
@@ -302,14 +333,23 @@ enum ps3_match_id {
302 333
303struct ps3_system_bus_device { 334struct ps3_system_bus_device {
304 enum ps3_match_id match_id; 335 enum ps3_match_id match_id;
305 struct ps3_device_id did; 336 enum ps3_system_bus_device_type dev_type;
306 unsigned int interrupt_id; 337
307/* struct iommu_table *iommu_table; -- waiting for Ben's cleanups */ 338 unsigned int bus_id; /* SB */
308 struct ps3_dma_region *d_region; 339 unsigned int dev_id; /* SB */
309 struct ps3_mmio_region *m_region; 340 unsigned int interrupt_id; /* SB */
341 struct ps3_dma_region *d_region; /* SB, IOC0 */
342 struct ps3_mmio_region *m_region; /* SB, IOC0*/
343 unsigned int port_number; /* VUART */
344
345/* struct iommu_table *iommu_table; -- waiting for BenH's cleanups */
310 struct device core; 346 struct device core;
347 void *driver_priv; /* private driver variables */
311}; 348};
312 349
350int ps3_open_hv_device(struct ps3_system_bus_device *dev);
351int ps3_close_hv_device(struct ps3_system_bus_device *dev);
352
313/** 353/**
314 * struct ps3_system_bus_driver - a driver for a device on the system bus 354 * struct ps3_system_bus_driver - a driver for a device on the system bus
315 */ 355 */
@@ -319,6 +359,7 @@ struct ps3_system_bus_driver {
319 struct device_driver core; 359 struct device_driver core;
320 int (*probe)(struct ps3_system_bus_device *); 360 int (*probe)(struct ps3_system_bus_device *);
321 int (*remove)(struct ps3_system_bus_device *); 361 int (*remove)(struct ps3_system_bus_device *);
362 int (*shutdown)(struct ps3_system_bus_device *);
322/* int (*suspend)(struct ps3_system_bus_device *, pm_message_t); */ 363/* int (*suspend)(struct ps3_system_bus_device *, pm_message_t); */
323/* int (*resume)(struct ps3_system_bus_device *); */ 364/* int (*resume)(struct ps3_system_bus_device *); */
324}; 365};
@@ -326,16 +367,24 @@ struct ps3_system_bus_driver {
326int ps3_system_bus_device_register(struct ps3_system_bus_device *dev); 367int ps3_system_bus_device_register(struct ps3_system_bus_device *dev);
327int ps3_system_bus_driver_register(struct ps3_system_bus_driver *drv); 368int ps3_system_bus_driver_register(struct ps3_system_bus_driver *drv);
328void ps3_system_bus_driver_unregister(struct ps3_system_bus_driver *drv); 369void ps3_system_bus_driver_unregister(struct ps3_system_bus_driver *drv);
329static inline struct ps3_system_bus_driver *to_ps3_system_bus_driver( 370
371static inline struct ps3_system_bus_driver *ps3_drv_to_system_bus_drv(
330 struct device_driver *_drv) 372 struct device_driver *_drv)
331{ 373{
332 return container_of(_drv, struct ps3_system_bus_driver, core); 374 return container_of(_drv, struct ps3_system_bus_driver, core);
333} 375}
334static inline struct ps3_system_bus_device *to_ps3_system_bus_device( 376static inline struct ps3_system_bus_device *ps3_dev_to_system_bus_dev(
335 struct device *_dev) 377 struct device *_dev)
336{ 378{
337 return container_of(_dev, struct ps3_system_bus_device, core); 379 return container_of(_dev, struct ps3_system_bus_device, core);
338} 380}
381static inline struct ps3_system_bus_driver *
382 ps3_system_bus_dev_to_system_bus_drv(struct ps3_system_bus_device *_dev)
383{
384 BUG_ON(!_dev);
385 BUG_ON(!_dev->core.driver);
386 return ps3_drv_to_system_bus_drv(_dev->core.driver);
387}
339 388
340/** 389/**
341 * ps3_system_bus_set_drvdata - 390 * ps3_system_bus_set_drvdata -
@@ -358,32 +407,17 @@ static inline void *ps3_system_bus_get_driver_data(
358 407
359extern struct bus_type ps3_system_bus_type; 408extern struct bus_type ps3_system_bus_type;
360 409
361/* vuart routines */ 410/* system manager */
362
363struct ps3_vuart_port_priv;
364
365/**
366 * struct ps3_vuart_port_device - a device on a vuart port
367 */
368
369struct ps3_vuart_port_device {
370 enum ps3_match_id match_id;
371 struct device core;
372 struct ps3_vuart_port_priv* priv; /* private driver variables */
373 411
412struct ps3_sys_manager_ops {
413 struct ps3_system_bus_device *dev;
414 void (*power_off)(struct ps3_system_bus_device *dev);
415 void (*restart)(struct ps3_system_bus_device *dev);
374}; 416};
375 417
376int ps3_vuart_port_device_register(struct ps3_vuart_port_device *dev); 418void ps3_sys_manager_register_ops(const struct ps3_sys_manager_ops *ops);
377
378/* system manager */
379
380#ifdef CONFIG_PS3_SYS_MANAGER
381void ps3_sys_manager_restart(void);
382void ps3_sys_manager_power_off(void); 419void ps3_sys_manager_power_off(void);
383#else 420void ps3_sys_manager_restart(void);
384static inline void ps3_sys_manager_restart(void) {}
385static inline void ps3_sys_manager_power_off(void) {}
386#endif
387 421
388struct ps3_prealloc { 422struct ps3_prealloc {
389 const char *name; 423 const char *name;
@@ -393,5 +427,7 @@ struct ps3_prealloc {
393}; 427};
394 428
395extern struct ps3_prealloc ps3fb_videomemory; 429extern struct ps3_prealloc ps3fb_videomemory;
430extern struct ps3_prealloc ps3flash_bounce_buffer;
431
396 432
397#endif 433#endif
diff --git a/include/asm-powerpc/ps3av.h b/include/asm-powerpc/ps3av.h
index 9efc40f1c77..7df4250802d 100644
--- a/include/asm-powerpc/ps3av.h
+++ b/include/asm-powerpc/ps3av.h
@@ -1,20 +1,23 @@
1/* 1/*
2 * Copyright (C) 2006 Sony Computer Entertainment Inc. 2 * PS3 AV backend support.
3 * Copyright 2006, 2007 Sony Corporation
4 * 3 *
5 * This program is free software; you can redistribute it and/or modify it 4 * Copyright (C) 2007 Sony Computer Entertainment Inc.
6 * under the terms of the GNU General Public License as published 5 * Copyright 2007 Sony Corp.
7 * by the Free Software Foundation; version 2 of the License.
8 * 6 *
9 * This program is distributed in the hope that it will be useful, but 7 * This program is free software; you can redistribute it and/or modify
10 * WITHOUT ANY WARRANTY; without even the implied warranty of 8 * it under the terms of the GNU General Public License as published by
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 9 * the Free Software Foundation; version 2 of the License.
12 * General Public License for more details.
13 * 10 *
14 * You should have received a copy of the GNU General Public License along 11 * This program is distributed in the hope that it will be useful,
15 * with this program; if not, write to the Free Software Foundation, Inc., 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */ 19 */
20
18#ifndef _ASM_POWERPC_PS3AV_H_ 21#ifndef _ASM_POWERPC_PS3AV_H_
19#define _ASM_POWERPC_PS3AV_H_ 22#define _ASM_POWERPC_PS3AV_H_
20 23
@@ -159,6 +162,9 @@
159#define PS3AV_CMD_VIDEO_FMT_X8R8G8B8 0x0000 162#define PS3AV_CMD_VIDEO_FMT_X8R8G8B8 0x0000
160/* video_out_format */ 163/* video_out_format */
161#define PS3AV_CMD_VIDEO_OUT_FORMAT_RGB_12BIT 0x0000 164#define PS3AV_CMD_VIDEO_OUT_FORMAT_RGB_12BIT 0x0000
165/* video_cl_cnv */
166#define PS3AV_CMD_VIDEO_CL_CNV_ENABLE_LUT 0x0000
167#define PS3AV_CMD_VIDEO_CL_CNV_DISABLE_LUT 0x0010
162/* video_sync */ 168/* video_sync */
163#define PS3AV_CMD_VIDEO_SYNC_VSYNC 0x0001 169#define PS3AV_CMD_VIDEO_SYNC_VSYNC 0x0001
164#define PS3AV_CMD_VIDEO_SYNC_CSYNC 0x0004 170#define PS3AV_CMD_VIDEO_SYNC_CSYNC 0x0004
@@ -311,6 +317,8 @@
311#define PS3AV_MODE_MASK 0x000F 317#define PS3AV_MODE_MASK 0x000F
312#define PS3AV_MODE_HDCP_OFF 0x1000 /* Retail PS3 product doesn't support this */ 318#define PS3AV_MODE_HDCP_OFF 0x1000 /* Retail PS3 product doesn't support this */
313#define PS3AV_MODE_DITHER 0x0800 319#define PS3AV_MODE_DITHER 0x0800
320#define PS3AV_MODE_COLOR 0x0400
321#define PS3AV_MODE_WHITE 0x0200
314#define PS3AV_MODE_FULL 0x0080 322#define PS3AV_MODE_FULL 0x0080
315#define PS3AV_MODE_DVI 0x0040 323#define PS3AV_MODE_DVI 0x0040
316#define PS3AV_MODE_RGB 0x0020 324#define PS3AV_MODE_RGB 0x0020
@@ -529,9 +537,9 @@ struct ps3av_pkt_video_mode {
529 u32 video_out_format; /* in: out format */ 537 u32 video_out_format; /* in: out format */
530 u32 video_format; /* in: input frame buffer format */ 538 u32 video_format; /* in: input frame buffer format */
531 u8 reserved3; 539 u8 reserved3;
532 u8 reserved4; 540 u8 video_cl_cnv; /* in: color conversion */
533 u16 video_order; /* in: input RGB order */ 541 u16 video_order; /* in: input RGB order */
534 u32 reserved5; 542 u32 reserved4;
535}; 543};
536 544
537/* video: format */ 545/* video: format */
@@ -539,7 +547,8 @@ struct ps3av_pkt_video_format {
539 struct ps3av_send_hdr send_hdr; 547 struct ps3av_send_hdr send_hdr;
540 u32 video_head; /* in: head */ 548 u32 video_head; /* in: head */
541 u32 video_format; /* in: frame buffer format */ 549 u32 video_format; /* in: frame buffer format */
542 u16 reserved; 550 u8 reserved;
551 u8 video_cl_cnv; /* in: color conversion */
543 u16 video_order; /* in: input RGB order */ 552 u16 video_order; /* in: input RGB order */
544}; 553};
545 554
@@ -698,12 +707,6 @@ static inline void ps3av_cmd_av_monitor_info_dump(const struct ps3av_pkt_av_get_
698extern int ps3av_cmd_video_get_monitor_info(struct ps3av_pkt_av_get_monitor_info *, 707extern int ps3av_cmd_video_get_monitor_info(struct ps3av_pkt_av_get_monitor_info *,
699 u32); 708 u32);
700 709
701struct ps3_vuart_port_device;
702extern int ps3av_vuart_write(struct ps3_vuart_port_device *dev,
703 const void *buf, unsigned long size);
704extern int ps3av_vuart_read(struct ps3_vuart_port_device *dev, void *buf,
705 unsigned long size, int timeout);
706
707extern int ps3av_set_video_mode(u32, int); 710extern int ps3av_set_video_mode(u32, int);
708extern int ps3av_set_audio_mode(u32, u32, u32, u32, u32); 711extern int ps3av_set_audio_mode(u32, u32, u32, u32, u32);
709extern int ps3av_get_auto_mode(int); 712extern int ps3av_get_auto_mode(int);
@@ -716,5 +719,8 @@ extern int ps3av_video_mute(int);
716extern int ps3av_audio_mute(int); 719extern int ps3av_audio_mute(int);
717extern int ps3av_dev_open(void); 720extern int ps3av_dev_open(void);
718extern int ps3av_dev_close(void); 721extern int ps3av_dev_close(void);
722extern void ps3av_register_flip_ctl(void (*flip_ctl)(int on, void *data),
723 void *flip_data);
724extern void ps3av_flip_ctl(int on);
719 725
720#endif /* _ASM_POWERPC_PS3AV_H_ */ 726#endif /* _ASM_POWERPC_PS3AV_H_ */
diff --git a/include/asm-powerpc/ps3fb.h b/include/asm-powerpc/ps3fb.h
index ad81cf43196..3f121fe4010 100644
--- a/include/asm-powerpc/ps3fb.h
+++ b/include/asm-powerpc/ps3fb.h
@@ -41,16 +41,4 @@ struct ps3fb_ioctl_res {
41 __u32 num_frames; /* num of frame buffers */ 41 __u32 num_frames; /* num of frame buffers */
42}; 42};
43 43
44#ifdef __KERNEL__
45
46#ifdef CONFIG_FB_PS3
47extern void ps3fb_flip_ctl(int on);
48extern void ps3fb_cleanup(void);
49#else
50static inline void ps3fb_flip_ctl(int on) {}
51static inline void ps3fb_cleanup(void) {}
52#endif
53
54#endif /* __KERNEL__ */
55
56#endif /* _ASM_POWERPC_PS3FB_H_ */ 44#endif /* _ASM_POWERPC_PS3FB_H_ */
diff --git a/include/asm-powerpc/ps3stor.h b/include/asm-powerpc/ps3stor.h
new file mode 100644
index 00000000000..6fcaf714fa5
--- /dev/null
+++ b/include/asm-powerpc/ps3stor.h
@@ -0,0 +1,71 @@
1/*
2 * PS3 Storage Devices
3 *
4 * Copyright (C) 2007 Sony Computer Entertainment Inc.
5 * Copyright 2007 Sony Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published
9 * by the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#ifndef _ASM_POWERPC_PS3STOR_H_
22#define _ASM_POWERPC_PS3STOR_H_
23
24#include <linux/interrupt.h>
25
26#include <asm/ps3.h>
27
28
29struct ps3_storage_region {
30 unsigned int id;
31 u64 start;
32 u64 size;
33};
34
35struct ps3_storage_device {
36 struct ps3_system_bus_device sbd;
37
38 struct ps3_dma_region dma_region;
39 unsigned int irq;
40 u64 blk_size;
41
42 u64 tag;
43 u64 lv1_status;
44 struct completion done;
45
46 unsigned long bounce_size;
47 void *bounce_buf;
48 u64 bounce_lpar;
49 dma_addr_t bounce_dma;
50
51 unsigned int num_regions;
52 unsigned long accessible_regions;
53 unsigned int region_idx; /* first accessible region */
54 struct ps3_storage_region regions[0]; /* Must be last */
55};
56
57static inline struct ps3_storage_device *to_ps3_storage_device(struct device *dev)
58{
59 return container_of(dev, struct ps3_storage_device, sbd.core);
60}
61
62extern int ps3stor_setup(struct ps3_storage_device *dev,
63 irq_handler_t handler);
64extern void ps3stor_teardown(struct ps3_storage_device *dev);
65extern u64 ps3stor_read_write_sectors(struct ps3_storage_device *dev, u64 lpar,
66 u64 start_sector, u64 sectors,
67 int write);
68extern u64 ps3stor_send_command(struct ps3_storage_device *dev, u64 cmd,
69 u64 arg1, u64 arg2, u64 arg3, u64 arg4);
70
71#endif /* _ASM_POWERPC_PS3STOR_H_ */
diff --git a/include/asm-powerpc/ptrace.h b/include/asm-powerpc/ptrace.h
index 4ad77a13f86..13fccc5a411 100644
--- a/include/asm-powerpc/ptrace.h
+++ b/include/asm-powerpc/ptrace.h
@@ -92,6 +92,11 @@ extern unsigned long profile_pc(struct pt_regs *regs);
92 set_thread_flag(TIF_NOERROR); \ 92 set_thread_flag(TIF_NOERROR); \
93 } while(0) 93 } while(0)
94 94
95struct task_struct;
96extern unsigned long ptrace_get_reg(struct task_struct *task, int regno);
97extern int ptrace_put_reg(struct task_struct *task, int regno,
98 unsigned long data);
99
95/* 100/*
96 * We use the least-significant bit of the trap field to indicate 101 * We use the least-significant bit of the trap field to indicate
97 * whether we have saved the full set of registers, or only a 102 * whether we have saved the full set of registers, or only a
@@ -158,9 +163,7 @@ do { \
158 163
159#define PT_NIP 32 164#define PT_NIP 32
160#define PT_MSR 33 165#define PT_MSR 33
161#ifdef __KERNEL__
162#define PT_ORIG_R3 34 166#define PT_ORIG_R3 34
163#endif
164#define PT_CTR 35 167#define PT_CTR 35
165#define PT_LNK 36 168#define PT_LNK 36
166#define PT_XER 37 169#define PT_XER 37
@@ -169,11 +172,12 @@ do { \
169#define PT_MQ 39 172#define PT_MQ 39
170#else 173#else
171#define PT_SOFTE 39 174#define PT_SOFTE 39
175#endif
172#define PT_TRAP 40 176#define PT_TRAP 40
173#define PT_DAR 41 177#define PT_DAR 41
174#define PT_DSISR 42 178#define PT_DSISR 42
175#define PT_RESULT 43 179#define PT_RESULT 43
176#endif 180#define PT_REGS_COUNT 44
177 181
178#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */ 182#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */
179 183
@@ -229,7 +233,17 @@ do { \
229#define PTRACE_GET_DEBUGREG 25 233#define PTRACE_GET_DEBUGREG 25
230#define PTRACE_SET_DEBUGREG 26 234#define PTRACE_SET_DEBUGREG 26
231 235
232/* Additional PTRACE requests implemented on PowerPC. */ 236/* (new) PTRACE requests using the same numbers as x86 and the same
237 * argument ordering. Additionally, they support more registers too
238 */
239#define PTRACE_GETREGS 12
240#define PTRACE_SETREGS 13
241#define PTRACE_GETFPREGS 14
242#define PTRACE_SETFPREGS 15
243#define PTRACE_GETREGS64 22
244#define PTRACE_SETREGS64 23
245
246/* (old) PTRACE requests with inverted arguments */
233#define PPC_PTRACE_GETREGS 0x99 /* Get GPRs 0 - 31 */ 247#define PPC_PTRACE_GETREGS 0x99 /* Get GPRs 0 - 31 */
234#define PPC_PTRACE_SETREGS 0x98 /* Set GPRs 0 - 31 */ 248#define PPC_PTRACE_SETREGS 0x98 /* Set GPRs 0 - 31 */
235#define PPC_PTRACE_GETFPREGS 0x97 /* Get FPRs 0 - 31 */ 249#define PPC_PTRACE_GETFPREGS 0x97 /* Get FPRs 0 - 31 */
diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h
index 749c7f953b5..281011e953e 100644
--- a/include/asm-powerpc/reg.h
+++ b/include/asm-powerpc/reg.h
@@ -453,6 +453,8 @@
453#define SPRN_MMCRA 0x312 453#define SPRN_MMCRA 0x312
454#define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */ 454#define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */
455#define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */ 455#define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */
456#define MMCRA_SLOT 0x07000000UL /* SLOT bits (37-39) */
457#define MMCRA_SLOT_SHIFT 24
456#define MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */ 458#define MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
457#define POWER6_MMCRA_SIHV 0x0000040000000000ULL 459#define POWER6_MMCRA_SIHV 0x0000040000000000ULL
458#define POWER6_MMCRA_SIPR 0x0000020000000000ULL 460#define POWER6_MMCRA_SIPR 0x0000020000000000ULL
diff --git a/include/asm-powerpc/spu.h b/include/asm-powerpc/spu.h
index 31d5054be20..eedc828cef2 100644
--- a/include/asm-powerpc/spu.h
+++ b/include/asm-powerpc/spu.h
@@ -106,6 +106,14 @@ struct spu_context;
106struct spu_runqueue; 106struct spu_runqueue;
107struct device_node; 107struct device_node;
108 108
109enum spu_utilization_state {
110 SPU_UTIL_SYSTEM,
111 SPU_UTIL_USER,
112 SPU_UTIL_IOWAIT,
113 SPU_UTIL_IDLE,
114 SPU_UTIL_MAX
115};
116
109struct spu { 117struct spu {
110 const char *name; 118 const char *name;
111 unsigned long local_store_phys; 119 unsigned long local_store_phys;
@@ -156,6 +164,21 @@ struct spu {
156 u64 shadow_int_mask_RW[3]; 164 u64 shadow_int_mask_RW[3];
157 165
158 struct sys_device sysdev; 166 struct sys_device sysdev;
167
168 struct {
169 /* protected by interrupt reentrancy */
170 enum spu_utilization_state utilization_state;
171 unsigned long tstamp; /* time of last ctx switch */
172 unsigned long times[SPU_UTIL_MAX];
173 unsigned long long vol_ctx_switch;
174 unsigned long long invol_ctx_switch;
175 unsigned long long min_flt;
176 unsigned long long maj_flt;
177 unsigned long long hash_flt;
178 unsigned long long slb_flt;
179 unsigned long long class2_intr;
180 unsigned long long libassist;
181 } stats;
159}; 182};
160 183
161struct spu *spu_alloc(void); 184struct spu *spu_alloc(void);
@@ -448,6 +471,7 @@ struct spu_priv1 {
448#define MFC_STATE1_PROBLEM_STATE_MASK 0x08ull 471#define MFC_STATE1_PROBLEM_STATE_MASK 0x08ull
449#define MFC_STATE1_RELOCATE_MASK 0x10ull 472#define MFC_STATE1_RELOCATE_MASK 0x10ull
450#define MFC_STATE1_MASTER_RUN_CONTROL_MASK 0x20ull 473#define MFC_STATE1_MASTER_RUN_CONTROL_MASK 0x20ull
474#define MFC_STATE1_TABLE_SEARCH_MASK 0x40ull
451 u64 mfc_lpid_RW; /* 0x008 */ 475 u64 mfc_lpid_RW; /* 0x008 */
452 u64 spu_idr_RW; /* 0x010 */ 476 u64 spu_idr_RW; /* 0x010 */
453 u64 mfc_vr_RO; /* 0x018 */ 477 u64 mfc_vr_RO; /* 0x018 */
diff --git a/include/asm-powerpc/syscalls.h b/include/asm-powerpc/syscalls.h
index c2fe79d4f90..b3ca41fc8bb 100644
--- a/include/asm-powerpc/syscalls.h
+++ b/include/asm-powerpc/syscalls.h
@@ -43,16 +43,9 @@ asmlinkage long ppc_newuname(struct new_utsname __user * name);
43 43
44asmlinkage long sys_rt_sigsuspend(sigset_t __user *unewset, 44asmlinkage long sys_rt_sigsuspend(sigset_t __user *unewset,
45 size_t sigsetsize); 45 size_t sigsetsize);
46
47#ifndef __powerpc64__
48asmlinkage long sys_sigaltstack(const stack_t __user *uss,
49 stack_t __user *uoss, int r5, int r6, int r7, int r8,
50 struct pt_regs *regs);
51#else /* __powerpc64__ */
52asmlinkage long sys_sigaltstack(const stack_t __user *uss, 46asmlinkage long sys_sigaltstack(const stack_t __user *uss,
53 stack_t __user *uoss, unsigned long r5, unsigned long r6, 47 stack_t __user *uoss, unsigned long r5, unsigned long r6,
54 unsigned long r7, unsigned long r8, struct pt_regs *regs); 48 unsigned long r7, unsigned long r8, struct pt_regs *regs);
55#endif /* __powerpc64__ */
56 49
57#endif /* __KERNEL__ */ 50#endif /* __KERNEL__ */
58#endif /* __ASM_POWERPC_SYSCALLS_H */ 51#endif /* __ASM_POWERPC_SYSCALLS_H */
diff --git a/include/asm-powerpc/system.h b/include/asm-powerpc/system.h
index 09621f611db..32aa42b748b 100644
--- a/include/asm-powerpc/system.h
+++ b/include/asm-powerpc/system.h
@@ -43,7 +43,7 @@
43#ifdef CONFIG_SMP 43#ifdef CONFIG_SMP
44#define smp_mb() mb() 44#define smp_mb() mb()
45#define smp_rmb() rmb() 45#define smp_rmb() rmb()
46#define smp_wmb() __asm__ __volatile__ ("eieio" : : : "memory") 46#define smp_wmb() eieio()
47#define smp_read_barrier_depends() read_barrier_depends() 47#define smp_read_barrier_depends() read_barrier_depends()
48#else 48#else
49#define smp_mb() barrier() 49#define smp_mb() barrier()
@@ -559,5 +559,7 @@ static inline void create_function_call(unsigned long addr, void * func)
559extern void account_system_vtime(struct task_struct *); 559extern void account_system_vtime(struct task_struct *);
560#endif 560#endif
561 561
562extern struct dentry *powerpc_debugfs_root;
563
562#endif /* __KERNEL__ */ 564#endif /* __KERNEL__ */
563#endif /* _ASM_POWERPC_SYSTEM_H */ 565#endif /* _ASM_POWERPC_SYSTEM_H */
diff --git a/include/asm-powerpc/termbits.h b/include/asm-powerpc/termbits.h
index 5e79198f7d1..6698188ca55 100644
--- a/include/asm-powerpc/termbits.h
+++ b/include/asm-powerpc/termbits.h
@@ -152,6 +152,10 @@ struct ktermios {
152#define B3000000 00034 152#define B3000000 00034
153#define B3500000 00035 153#define B3500000 00035
154#define B4000000 00036 154#define B4000000 00036
155#define BOTHER 00037
156
157#define CIBAUD 077600000
158#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
155 159
156#define CSIZE 00001400 160#define CSIZE 00001400
157#define CS5 00000000 161#define CS5 00000000
diff --git a/include/asm-powerpc/thread_info.h b/include/asm-powerpc/thread_info.h
index 3f32ca8bfec..9d9aeca8ad2 100644
--- a/include/asm-powerpc/thread_info.h
+++ b/include/asm-powerpc/thread_info.h
@@ -113,8 +113,8 @@ static inline struct thread_info *current_thread_info(void)
113#define TIF_POLLING_NRFLAG 4 /* true if poll_idle() is polling 113#define TIF_POLLING_NRFLAG 4 /* true if poll_idle() is polling
114 TIF_NEED_RESCHED */ 114 TIF_NEED_RESCHED */
115#define TIF_32BIT 5 /* 32 bit binary */ 115#define TIF_32BIT 5 /* 32 bit binary */
116#define TIF_RUNLATCH 6 /* Is the runlatch enabled? */ 116#define TIF_PERFMON_WORK 6 /* work for pfm_handle_work() */
117#define TIF_ABI_PENDING 7 /* 32/64 bit switch needed */ 117#define TIF_PERFMON_CTXSW 7 /* perfmon needs ctxsw calls */
118#define TIF_SYSCALL_AUDIT 8 /* syscall auditing active */ 118#define TIF_SYSCALL_AUDIT 8 /* syscall auditing active */
119#define TIF_SINGLESTEP 9 /* singlestepping active */ 119#define TIF_SINGLESTEP 9 /* singlestepping active */
120#define TIF_MEMDIE 10 120#define TIF_MEMDIE 10
@@ -123,6 +123,8 @@ static inline struct thread_info *current_thread_info(void)
123#define TIF_NOERROR 14 /* Force successful syscall return */ 123#define TIF_NOERROR 14 /* Force successful syscall return */
124#define TIF_RESTORE_SIGMASK 15 /* Restore signal mask in do_signal */ 124#define TIF_RESTORE_SIGMASK 15 /* Restore signal mask in do_signal */
125#define TIF_FREEZE 16 /* Freezing for suspend */ 125#define TIF_FREEZE 16 /* Freezing for suspend */
126#define TIF_RUNLATCH 17 /* Is the runlatch enabled? */
127#define TIF_ABI_PENDING 18 /* 32/64 bit switch needed */
126 128
127/* as above, but as bit values */ 129/* as above, but as bit values */
128#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) 130#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
@@ -131,8 +133,8 @@ static inline struct thread_info *current_thread_info(void)
131#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) 133#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
132#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) 134#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
133#define _TIF_32BIT (1<<TIF_32BIT) 135#define _TIF_32BIT (1<<TIF_32BIT)
134#define _TIF_RUNLATCH (1<<TIF_RUNLATCH) 136#define _TIF_PERFMON_WORK (1<<TIF_PERFMON_WORK)
135#define _TIF_ABI_PENDING (1<<TIF_ABI_PENDING) 137#define _TIF_PERFMON_CTXSW (1<<TIF_PERFMON_CTXSW)
136#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT) 138#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT)
137#define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP) 139#define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP)
138#define _TIF_SECCOMP (1<<TIF_SECCOMP) 140#define _TIF_SECCOMP (1<<TIF_SECCOMP)
@@ -140,6 +142,8 @@ static inline struct thread_info *current_thread_info(void)
140#define _TIF_NOERROR (1<<TIF_NOERROR) 142#define _TIF_NOERROR (1<<TIF_NOERROR)
141#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK) 143#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK)
142#define _TIF_FREEZE (1<<TIF_FREEZE) 144#define _TIF_FREEZE (1<<TIF_FREEZE)
145#define _TIF_RUNLATCH (1<<TIF_RUNLATCH)
146#define _TIF_ABI_PENDING (1<<TIF_ABI_PENDING)
143#define _TIF_SYSCALL_T_OR_A (_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SECCOMP) 147#define _TIF_SYSCALL_T_OR_A (_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SECCOMP)
144 148
145#define _TIF_USER_WORK_MASK (_TIF_NOTIFY_RESUME | _TIF_SIGPENDING | \ 149#define _TIF_USER_WORK_MASK (_TIF_NOTIFY_RESUME | _TIF_SIGPENDING | \
diff --git a/include/asm-powerpc/time.h b/include/asm-powerpc/time.h
index 3fd57c048f5..d7f5ddfbaac 100644
--- a/include/asm-powerpc/time.h
+++ b/include/asm-powerpc/time.h
@@ -232,7 +232,7 @@ extern void account_process_vtime(struct task_struct *tsk);
232#define account_process_vtime(tsk) do { } while (0) 232#define account_process_vtime(tsk) do { } while (0)
233#endif 233#endif
234 234
235#if defined(CONFIG_VIRT_CPU_ACCOUNTING) && defined(CONFIG_PPC_SPLPAR) 235#if defined(CONFIG_VIRT_CPU_ACCOUNTING)
236extern void calculate_steal_time(void); 236extern void calculate_steal_time(void);
237extern void snapshot_timebases(void); 237extern void snapshot_timebases(void);
238#else 238#else
@@ -240,5 +240,7 @@ extern void snapshot_timebases(void);
240#define snapshot_timebases() do { } while (0) 240#define snapshot_timebases() do { } while (0)
241#endif 241#endif
242 242
243extern void iSeries_time_init_early(void);
244
243#endif /* __KERNEL__ */ 245#endif /* __KERNEL__ */
244#endif /* __POWERPC_TIME_H */ 246#endif /* __POWERPC_TIME_H */
diff --git a/include/asm-powerpc/tlbflush.h b/include/asm-powerpc/tlbflush.h
index 86e6266a028..99a0439baa5 100644
--- a/include/asm-powerpc/tlbflush.h
+++ b/include/asm-powerpc/tlbflush.h
@@ -155,6 +155,11 @@ static inline void flush_tlb_kernel_range(unsigned long start,
155{ 155{
156} 156}
157 157
158/* Private function for use by PCI IO mapping code */
159extern void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
160 unsigned long end);
161
162
158#endif 163#endif
159 164
160/* 165/*