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authorLinus Torvalds <torvalds@linux-foundation.org>2008-01-30 21:37:27 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2008-01-30 21:37:27 -0500
commit8af03e782cae1e0a0f530ddd22301cdd12cf9dc0 (patch)
treec4af13a38bd3cc1a811a37f2358491f171052070 /include/asm-powerpc
parent6232665040f9a23fafd9d94d4ae8d5a2dc850f65 (diff)
parent99e139126ab2e84be67969650f92eb37c12ab5cd (diff)
Merge branch 'for-2.6.25' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc
* 'for-2.6.25' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: (454 commits) [POWERPC] Cell IOMMU fixed mapping support [POWERPC] Split out the ioid fetching/checking logic [POWERPC] Add support to cell_iommu_setup_page_tables() for multiple windows [POWERPC] Split out the IOMMU logic from cell_dma_dev_setup() [POWERPC] Split cell_iommu_setup_hardware() into two parts [POWERPC] Split out the logic that allocates struct iommus [POWERPC] Allocate the hash table under 1G on cell [POWERPC] Add set_dma_ops() to match get_dma_ops() [POWERPC] 83xx: Clean up / convert mpc83xx board DTS files to v1 format. [POWERPC] 85xx: Only invalidate TLB0 and TLB1 [POWERPC] 83xx: Fix typo in mpc837x compatible entries [POWERPC] 85xx: convert sbc85* boards to use machine_device_initcall [POWERPC] 83xx: rework platform Kconfig [POWERPC] 85xx: rework platform Kconfig [POWERPC] 86xx: Remove unused IRQ defines [POWERPC] QE: Explicitly set address-cells and size cells for muram [POWERPC] Convert StorCenter DTS file to /dts-v1/ format. [POWERPC] 86xx: Convert all 86xx DTS files to /dts-v1/ format. [PPC] Remove 85xx from arch/ppc [PPC] Remove 83xx from arch/ppc ...
Diffstat (limited to 'include/asm-powerpc')
-rw-r--r--include/asm-powerpc/8xx_immap.h2
-rw-r--r--include/asm-powerpc/cpm.h74
-rw-r--r--include/asm-powerpc/cpm1.h (renamed from include/asm-powerpc/commproc.h)79
-rw-r--r--include/asm-powerpc/cpm2.h64
-rw-r--r--include/asm-powerpc/cputable.h13
-rw-r--r--include/asm-powerpc/cputhreads.h71
-rw-r--r--include/asm-powerpc/dcr-native.h30
-rw-r--r--include/asm-powerpc/dcr-regs.h71
-rw-r--r--include/asm-powerpc/dma-mapping.h10
-rw-r--r--include/asm-powerpc/firmware.h2
-rw-r--r--include/asm-powerpc/immap_86xx.h25
-rw-r--r--include/asm-powerpc/immap_qe.h34
-rw-r--r--include/asm-powerpc/io.h5
-rw-r--r--include/asm-powerpc/iommu.h3
-rw-r--r--include/asm-powerpc/ipic.h12
-rw-r--r--include/asm-powerpc/irq.h212
-rw-r--r--include/asm-powerpc/iseries/hv_lp_event.h2
-rw-r--r--include/asm-powerpc/kexec.h3
-rw-r--r--include/asm-powerpc/lmb.h1
-rw-r--r--include/asm-powerpc/machdep.h58
-rw-r--r--include/asm-powerpc/mmu-hash64.h7
-rw-r--r--include/asm-powerpc/mpc52xx.h16
-rw-r--r--include/asm-powerpc/mpc52xx_psc.h3
-rw-r--r--include/asm-powerpc/mpc8260.h1
-rw-r--r--include/asm-powerpc/mpc8xx.h20
-rw-r--r--include/asm-powerpc/mpic.h20
-rw-r--r--include/asm-powerpc/nvram.h11
-rw-r--r--include/asm-powerpc/of_platform.h14
-rw-r--r--include/asm-powerpc/pci-bridge.h199
-rw-r--r--include/asm-powerpc/pci.h29
-rw-r--r--include/asm-powerpc/pgalloc-64.h5
-rw-r--r--include/asm-powerpc/pgtable-64k.h39
-rw-r--r--include/asm-powerpc/ppc-pci.h4
-rw-r--r--include/asm-powerpc/prom.h4
-rw-r--r--include/asm-powerpc/ps3.h74
-rw-r--r--include/asm-powerpc/ptrace.h3
-rw-r--r--include/asm-powerpc/qe.h156
-rw-r--r--include/asm-powerpc/reg.h7
-rw-r--r--include/asm-powerpc/reg_booke.h18
-rw-r--r--include/asm-powerpc/setjmp.h18
-rw-r--r--include/asm-powerpc/smu.h142
-rw-r--r--include/asm-powerpc/sparsemem.h5
-rw-r--r--include/asm-powerpc/spu.h28
-rw-r--r--include/asm-powerpc/spu_csa.h13
-rw-r--r--include/asm-powerpc/spu_priv1.h15
-rw-r--r--include/asm-powerpc/systbl.h1
-rw-r--r--include/asm-powerpc/system.h2
-rw-r--r--include/asm-powerpc/udbg.h1
-rw-r--r--include/asm-powerpc/unistd.h3
49 files changed, 994 insertions, 635 deletions
diff --git a/include/asm-powerpc/8xx_immap.h b/include/asm-powerpc/8xx_immap.h
index 1311cefdfd3..4b0e1520600 100644
--- a/include/asm-powerpc/8xx_immap.h
+++ b/include/asm-powerpc/8xx_immap.h
@@ -123,7 +123,7 @@ typedef struct mem_ctlr {
123#define OR_G5LA 0x00000400 /* Output #GPL5 on #GPL_A5 */ 123#define OR_G5LA 0x00000400 /* Output #GPL5 on #GPL_A5 */
124#define OR_G5LS 0x00000200 /* Drive #GPL high on falling edge of...*/ 124#define OR_G5LS 0x00000200 /* Drive #GPL high on falling edge of...*/
125#define OR_BI 0x00000100 /* Burst inhibit */ 125#define OR_BI 0x00000100 /* Burst inhibit */
126#define OR_SCY_MSK 0x000000f0 /* Cycle Lenght in Clocks */ 126#define OR_SCY_MSK 0x000000f0 /* Cycle Length in Clocks */
127#define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */ 127#define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */
128#define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */ 128#define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */
129#define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */ 129#define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */
diff --git a/include/asm-powerpc/cpm.h b/include/asm-powerpc/cpm.h
index 48df9f330e7..77e39dad972 100644
--- a/include/asm-powerpc/cpm.h
+++ b/include/asm-powerpc/cpm.h
@@ -4,11 +4,85 @@
4#include <linux/compiler.h> 4#include <linux/compiler.h>
5#include <linux/types.h> 5#include <linux/types.h>
6 6
7/* Buffer descriptors used by many of the CPM protocols. */
8typedef struct cpm_buf_desc {
9 ushort cbd_sc; /* Status and Control */
10 ushort cbd_datlen; /* Data length in buffer */
11 uint cbd_bufaddr; /* Buffer address in host memory */
12} cbd_t;
13
14/* Buffer descriptor control/status used by serial
15 */
16
17#define BD_SC_EMPTY (0x8000) /* Receive is empty */
18#define BD_SC_READY (0x8000) /* Transmit is ready */
19#define BD_SC_WRAP (0x2000) /* Last buffer descriptor */
20#define BD_SC_INTRPT (0x1000) /* Interrupt on change */
21#define BD_SC_LAST (0x0800) /* Last buffer in frame */
22#define BD_SC_TC (0x0400) /* Transmit CRC */
23#define BD_SC_CM (0x0200) /* Continous mode */
24#define BD_SC_ID (0x0100) /* Rec'd too many idles */
25#define BD_SC_P (0x0100) /* xmt preamble */
26#define BD_SC_BR (0x0020) /* Break received */
27#define BD_SC_FR (0x0010) /* Framing error */
28#define BD_SC_PR (0x0008) /* Parity error */
29#define BD_SC_NAK (0x0004) /* NAK - did not respond */
30#define BD_SC_OV (0x0002) /* Overrun */
31#define BD_SC_UN (0x0002) /* Underrun */
32#define BD_SC_CD (0x0001) /* */
33#define BD_SC_CL (0x0001) /* Collision */
34
35/* Buffer descriptor control/status used by Ethernet receive.
36 * Common to SCC and FCC.
37 */
38#define BD_ENET_RX_EMPTY (0x8000)
39#define BD_ENET_RX_WRAP (0x2000)
40#define BD_ENET_RX_INTR (0x1000)
41#define BD_ENET_RX_LAST (0x0800)
42#define BD_ENET_RX_FIRST (0x0400)
43#define BD_ENET_RX_MISS (0x0100)
44#define BD_ENET_RX_BC (0x0080) /* FCC Only */
45#define BD_ENET_RX_MC (0x0040) /* FCC Only */
46#define BD_ENET_RX_LG (0x0020)
47#define BD_ENET_RX_NO (0x0010)
48#define BD_ENET_RX_SH (0x0008)
49#define BD_ENET_RX_CR (0x0004)
50#define BD_ENET_RX_OV (0x0002)
51#define BD_ENET_RX_CL (0x0001)
52#define BD_ENET_RX_STATS (0x01ff) /* All status bits */
53
54/* Buffer descriptor control/status used by Ethernet transmit.
55 * Common to SCC and FCC.
56 */
57#define BD_ENET_TX_READY (0x8000)
58#define BD_ENET_TX_PAD (0x4000)
59#define BD_ENET_TX_WRAP (0x2000)
60#define BD_ENET_TX_INTR (0x1000)
61#define BD_ENET_TX_LAST (0x0800)
62#define BD_ENET_TX_TC (0x0400)
63#define BD_ENET_TX_DEF (0x0200)
64#define BD_ENET_TX_HB (0x0100)
65#define BD_ENET_TX_LC (0x0080)
66#define BD_ENET_TX_RL (0x0040)
67#define BD_ENET_TX_RCMASK (0x003c)
68#define BD_ENET_TX_UN (0x0002)
69#define BD_ENET_TX_CSL (0x0001)
70#define BD_ENET_TX_STATS (0x03ff) /* All status bits */
71
72/* Buffer descriptor control/status used by Transparent mode SCC.
73 */
74#define BD_SCC_TX_LAST (0x0800)
75
76/* Buffer descriptor control/status used by I2C.
77 */
78#define BD_I2C_START (0x0400)
79
7int cpm_muram_init(void); 80int cpm_muram_init(void);
8unsigned long cpm_muram_alloc(unsigned long size, unsigned long align); 81unsigned long cpm_muram_alloc(unsigned long size, unsigned long align);
9int cpm_muram_free(unsigned long offset); 82int cpm_muram_free(unsigned long offset);
10unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size); 83unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size);
11void __iomem *cpm_muram_addr(unsigned long offset); 84void __iomem *cpm_muram_addr(unsigned long offset);
12dma_addr_t cpm_muram_dma(void __iomem *addr); 85dma_addr_t cpm_muram_dma(void __iomem *addr);
86int cpm_command(u32 command, u8 opcode);
13 87
14#endif 88#endif
diff --git a/include/asm-powerpc/commproc.h b/include/asm-powerpc/cpm1.h
index 2ee59d7b335..b2ebd6ac6da 100644
--- a/include/asm-powerpc/commproc.h
+++ b/include/asm-powerpc/cpm1.h
@@ -14,8 +14,8 @@
14 * IDMA1 space. The remaining DP RAM is available for buffer descriptors 14 * IDMA1 space. The remaining DP RAM is available for buffer descriptors
15 * or other use. 15 * or other use.
16 */ 16 */
17#ifndef __CPM_8XX__ 17#ifndef __CPM1__
18#define __CPM_8XX__ 18#define __CPM1__
19 19
20#include <asm/8xx_immap.h> 20#include <asm/8xx_immap.h>
21#include <asm/ptrace.h> 21#include <asm/ptrace.h>
@@ -82,42 +82,14 @@ extern int cpm_dpfree(unsigned long offset);
82extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align); 82extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align);
83extern void cpm_dpdump(void); 83extern void cpm_dpdump(void);
84extern void *cpm_dpram_addr(unsigned long offset); 84extern void *cpm_dpram_addr(unsigned long offset);
85extern uint cpm_dpram_phys(u8* addr); 85extern uint cpm_dpram_phys(u8 *addr);
86#endif 86#endif
87 87
88extern void cpm_setbrg(uint brg, uint rate); 88extern void cpm_setbrg(uint brg, uint rate);
89 89
90extern uint m8xx_cpm_hostalloc(uint size);
91extern int m8xx_cpm_hostfree(uint start);
92extern void m8xx_cpm_hostdump(void);
93
94extern void cpm_load_patch(cpm8xx_t *cp); 90extern void cpm_load_patch(cpm8xx_t *cp);
95 91
96/* Buffer descriptors used by many of the CPM protocols. 92extern void cpm_reset(void);
97*/
98typedef struct cpm_buf_desc {
99 ushort cbd_sc; /* Status and Control */
100 ushort cbd_datlen; /* Data length in buffer */
101 uint cbd_bufaddr; /* Buffer address in host memory */
102} cbd_t;
103
104#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
105#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
106#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
107#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
108#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
109#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
110#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
111#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
112#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
113#define BD_SC_BR ((ushort)0x0020) /* Break received */
114#define BD_SC_FR ((ushort)0x0010) /* Framing error */
115#define BD_SC_PR ((ushort)0x0008) /* Parity error */
116#define BD_SC_NAK ((ushort)0x0004) /* NAK - did not respond */
117#define BD_SC_OV ((ushort)0x0002) /* Overrun */
118#define BD_SC_UN ((ushort)0x0002) /* Underrun */
119#define BD_SC_CD ((ushort)0x0001) /* ?? */
120#define BD_SC_CL ((ushort)0x0001) /* Collision */
121 93
122/* Parameter RAM offsets. 94/* Parameter RAM offsets.
123*/ 95*/
@@ -448,41 +420,6 @@ typedef struct scc_enet {
448#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ 420#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
449#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ 421#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
450 422
451/* Buffer descriptor control/status used by Ethernet receive.
452*/
453#define BD_ENET_RX_EMPTY ((ushort)0x8000)
454#define BD_ENET_RX_WRAP ((ushort)0x2000)
455#define BD_ENET_RX_INTR ((ushort)0x1000)
456#define BD_ENET_RX_LAST ((ushort)0x0800)
457#define BD_ENET_RX_FIRST ((ushort)0x0400)
458#define BD_ENET_RX_MISS ((ushort)0x0100)
459#define BD_ENET_RX_LG ((ushort)0x0020)
460#define BD_ENET_RX_NO ((ushort)0x0010)
461#define BD_ENET_RX_SH ((ushort)0x0008)
462#define BD_ENET_RX_CR ((ushort)0x0004)
463#define BD_ENET_RX_OV ((ushort)0x0002)
464#define BD_ENET_RX_CL ((ushort)0x0001)
465#define BD_ENET_RX_BC ((ushort)0x0080) /* DA is Broadcast */
466#define BD_ENET_RX_MC ((ushort)0x0040) /* DA is Multicast */
467#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
468
469/* Buffer descriptor control/status used by Ethernet transmit.
470*/
471#define BD_ENET_TX_READY ((ushort)0x8000)
472#define BD_ENET_TX_PAD ((ushort)0x4000)
473#define BD_ENET_TX_WRAP ((ushort)0x2000)
474#define BD_ENET_TX_INTR ((ushort)0x1000)
475#define BD_ENET_TX_LAST ((ushort)0x0800)
476#define BD_ENET_TX_TC ((ushort)0x0400)
477#define BD_ENET_TX_DEF ((ushort)0x0200)
478#define BD_ENET_TX_HB ((ushort)0x0100)
479#define BD_ENET_TX_LC ((ushort)0x0080)
480#define BD_ENET_TX_RL ((ushort)0x0040)
481#define BD_ENET_TX_RCMASK ((ushort)0x003c)
482#define BD_ENET_TX_UN ((ushort)0x0002)
483#define BD_ENET_TX_CSL ((ushort)0x0001)
484#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
485
486/* SCC as UART 423/* SCC as UART
487*/ 424*/
488typedef struct scc_uart { 425typedef struct scc_uart {
@@ -551,8 +488,6 @@ typedef struct scc_trans {
551 uint st_cmask; /* Constant mask for CRC */ 488 uint st_cmask; /* Constant mask for CRC */
552} scc_trans_t; 489} scc_trans_t;
553 490
554#define BD_SCC_TX_LAST ((ushort)0x0800)
555
556/* IIC parameter RAM. 491/* IIC parameter RAM.
557*/ 492*/
558typedef struct iic { 493typedef struct iic {
@@ -576,8 +511,6 @@ typedef struct iic {
576 char res2[2]; /* Reserved */ 511 char res2[2]; /* Reserved */
577} iic_t; 512} iic_t;
578 513
579#define BD_IIC_START ((ushort)0x0400)
580
581/* SPI parameter RAM. 514/* SPI parameter RAM.
582*/ 515*/
583typedef struct spi { 516typedef struct spi {
@@ -693,7 +626,7 @@ typedef struct risc_timer_pram {
693#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ 626#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
694#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ 627#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
695#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ 628#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
696#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */ 629#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */
697#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ 630#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
698#define CICR_IEN ((uint)0x00000080) /* Int. enable */ 631#define CICR_IEN ((uint)0x00000080) /* Int. enable */
699#define CICR_SPS ((uint)0x00000001) /* SCC Spread */ 632#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
@@ -749,4 +682,4 @@ enum cpm_clk {
749 682
750int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode); 683int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode);
751 684
752#endif /* __CPM_8XX__ */ 685#endif /* __CPM1__ */
diff --git a/include/asm-powerpc/cpm2.h b/include/asm-powerpc/cpm2.h
index f1112c15ef9..b93a53eb55c 100644
--- a/include/asm-powerpc/cpm2.h
+++ b/include/asm-powerpc/cpm2.h
@@ -132,29 +132,6 @@ extern void cpm_setbrg(uint brg, uint rate);
132extern void cpm2_fastbrg(uint brg, uint rate, int div16); 132extern void cpm2_fastbrg(uint brg, uint rate, int div16);
133extern void cpm2_reset(void); 133extern void cpm2_reset(void);
134 134
135
136/* Buffer descriptors used by many of the CPM protocols.
137*/
138typedef struct cpm_buf_desc {
139 ushort cbd_sc; /* Status and Control */
140 ushort cbd_datlen; /* Data length in buffer */
141 uint cbd_bufaddr; /* Buffer address in host memory */
142} cbd_t;
143
144#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
145#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
146#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
147#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
148#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
149#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
150#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
151#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
152#define BD_SC_BR ((ushort)0x0020) /* Break received */
153#define BD_SC_FR ((ushort)0x0010) /* Framing error */
154#define BD_SC_PR ((ushort)0x0008) /* Parity error */
155#define BD_SC_OV ((ushort)0x0002) /* Overrun */
156#define BD_SC_CD ((ushort)0x0001) /* ?? */
157
158/* Function code bits, usually generic to devices. 135/* Function code bits, usually generic to devices.
159*/ 136*/
160#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */ 137#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
@@ -456,43 +433,6 @@ typedef struct scc_enet {
456#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ 433#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
457#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ 434#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
458 435
459/* Buffer descriptor control/status used by Ethernet receive.
460 * Common to SCC and FCC.
461 */
462#define BD_ENET_RX_EMPTY ((ushort)0x8000)
463#define BD_ENET_RX_WRAP ((ushort)0x2000)
464#define BD_ENET_RX_INTR ((ushort)0x1000)
465#define BD_ENET_RX_LAST ((ushort)0x0800)
466#define BD_ENET_RX_FIRST ((ushort)0x0400)
467#define BD_ENET_RX_MISS ((ushort)0x0100)
468#define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */
469#define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */
470#define BD_ENET_RX_LG ((ushort)0x0020)
471#define BD_ENET_RX_NO ((ushort)0x0010)
472#define BD_ENET_RX_SH ((ushort)0x0008)
473#define BD_ENET_RX_CR ((ushort)0x0004)
474#define BD_ENET_RX_OV ((ushort)0x0002)
475#define BD_ENET_RX_CL ((ushort)0x0001)
476#define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */
477
478/* Buffer descriptor control/status used by Ethernet transmit.
479 * Common to SCC and FCC.
480 */
481#define BD_ENET_TX_READY ((ushort)0x8000)
482#define BD_ENET_TX_PAD ((ushort)0x4000)
483#define BD_ENET_TX_WRAP ((ushort)0x2000)
484#define BD_ENET_TX_INTR ((ushort)0x1000)
485#define BD_ENET_TX_LAST ((ushort)0x0800)
486#define BD_ENET_TX_TC ((ushort)0x0400)
487#define BD_ENET_TX_DEF ((ushort)0x0200)
488#define BD_ENET_TX_HB ((ushort)0x0100)
489#define BD_ENET_TX_LC ((ushort)0x0080)
490#define BD_ENET_TX_RL ((ushort)0x0040)
491#define BD_ENET_TX_RCMASK ((ushort)0x003c)
492#define BD_ENET_TX_UN ((ushort)0x0002)
493#define BD_ENET_TX_CSL ((ushort)0x0001)
494#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
495
496/* SCC as UART 436/* SCC as UART
497*/ 437*/
498typedef struct scc_uart { 438typedef struct scc_uart {
@@ -562,8 +502,6 @@ typedef struct scc_trans {
562 uint st_cmask; /* Constant mask for CRC */ 502 uint st_cmask; /* Constant mask for CRC */
563} scc_trans_t; 503} scc_trans_t;
564 504
565#define BD_SCC_TX_LAST ((ushort)0x0800)
566
567/* How about some FCCs..... 505/* How about some FCCs.....
568*/ 506*/
569#define FCC_GFMR_DIAG_NORM ((uint)0x00000000) 507#define FCC_GFMR_DIAG_NORM ((uint)0x00000000)
@@ -769,8 +707,6 @@ typedef struct spi {
769 707
770#define SPI_EB ((u_char)0x10) /* big endian byte order */ 708#define SPI_EB ((u_char)0x10) /* big endian byte order */
771 709
772#define BD_IIC_START ((ushort)0x0400)
773
774/* IDMA parameter RAM 710/* IDMA parameter RAM
775*/ 711*/
776typedef struct idma { 712typedef struct idma {
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h
index 4525c784dfd..528ef183c22 100644
--- a/include/asm-powerpc/cputable.h
+++ b/include/asm-powerpc/cputable.h
@@ -57,6 +57,14 @@ enum powerpc_pmc_type {
57 PPC_PMC_PA6T = 2, 57 PPC_PMC_PA6T = 2,
58}; 58};
59 59
60struct pt_regs;
61
62extern int machine_check_generic(struct pt_regs *regs);
63extern int machine_check_4xx(struct pt_regs *regs);
64extern int machine_check_440A(struct pt_regs *regs);
65extern int machine_check_e500(struct pt_regs *regs);
66extern int machine_check_e200(struct pt_regs *regs);
67
60/* NOTE WELL: Update identify_cpu() if fields are added or removed! */ 68/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
61struct cpu_spec { 69struct cpu_spec {
62 /* CPU is matched via (PVR & pvr_mask) == pvr_value */ 70 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
@@ -97,6 +105,11 @@ struct cpu_spec {
97 105
98 /* Name of processor class, for the ELF AT_PLATFORM entry */ 106 /* Name of processor class, for the ELF AT_PLATFORM entry */
99 char *platform; 107 char *platform;
108
109 /* Processor specific machine check handling. Return negative
110 * if the error is fatal, 1 if it was fully recovered and 0 to
111 * pass up (not CPU originated) */
112 int (*machine_check)(struct pt_regs *regs);
100}; 113};
101 114
102extern struct cpu_spec *cur_cpu_spec; 115extern struct cpu_spec *cur_cpu_spec;
diff --git a/include/asm-powerpc/cputhreads.h b/include/asm-powerpc/cputhreads.h
new file mode 100644
index 00000000000..8485c28b5f4
--- /dev/null
+++ b/include/asm-powerpc/cputhreads.h
@@ -0,0 +1,71 @@
1#ifndef _ASM_POWERPC_CPUTHREADS_H
2#define _ASM_POWERPC_CPUTHREADS_H
3
4#include <linux/cpumask.h>
5
6/*
7 * Mapping of threads to cores
8 */
9
10#ifdef CONFIG_SMP
11extern int threads_per_core;
12extern int threads_shift;
13extern cpumask_t threads_core_mask;
14#else
15#define threads_per_core 1
16#define threads_shift 0
17#define threads_core_mask (CPU_MASK_CPU0)
18#endif
19
20/* cpu_thread_mask_to_cores - Return a cpumask of one per cores
21 * hit by the argument
22 *
23 * @threads: a cpumask of threads
24 *
25 * This function returns a cpumask which will have one "cpu" (or thread)
26 * bit set for each core that has at least one thread set in the argument.
27 *
28 * This can typically be used for things like IPI for tlb invalidations
29 * since those need to be done only once per core/TLB
30 */
31static inline cpumask_t cpu_thread_mask_to_cores(cpumask_t threads)
32{
33 cpumask_t tmp, res;
34 int i;
35
36 res = CPU_MASK_NONE;
37 for (i = 0; i < NR_CPUS; i += threads_per_core) {
38 cpus_shift_right(tmp, threads_core_mask, i);
39 if (cpus_intersects(threads, tmp))
40 cpu_set(i, res);
41 }
42 return res;
43}
44
45static inline int cpu_nr_cores(void)
46{
47 return NR_CPUS >> threads_shift;
48}
49
50static inline cpumask_t cpu_online_cores_map(void)
51{
52 return cpu_thread_mask_to_cores(cpu_online_map);
53}
54
55static inline int cpu_thread_to_core(int cpu)
56{
57 return cpu >> threads_shift;
58}
59
60static inline int cpu_thread_in_core(int cpu)
61{
62 return cpu & (threads_per_core - 1);
63}
64
65static inline int cpu_first_thread_in_core(int cpu)
66{
67 return cpu & ~(threads_per_core - 1);
68}
69
70#endif /* _ASM_POWERPC_CPUTHREADS_H */
71
diff --git a/include/asm-powerpc/dcr-native.h b/include/asm-powerpc/dcr-native.h
index 8dbb1ab0aa0..af5fb31af55 100644
--- a/include/asm-powerpc/dcr-native.h
+++ b/include/asm-powerpc/dcr-native.h
@@ -22,6 +22,8 @@
22#ifdef __KERNEL__ 22#ifdef __KERNEL__
23#ifndef __ASSEMBLY__ 23#ifndef __ASSEMBLY__
24 24
25#include <linux/spinlock.h>
26
25typedef struct { 27typedef struct {
26 unsigned int base; 28 unsigned int base;
27} dcr_host_t; 29} dcr_host_t;
@@ -55,20 +57,28 @@ do { \
55} while (0) 57} while (0)
56 58
57/* R/W of indirect DCRs make use of standard naming conventions for DCRs */ 59/* R/W of indirect DCRs make use of standard naming conventions for DCRs */
58#define mfdcri(base, reg) \ 60extern spinlock_t dcr_ind_lock;
59({ \ 61
60 mtdcr(base ## _CFGADDR, base ## _ ## reg); \ 62#define mfdcri(base, reg) \
61 mfdcr(base ## _CFGDATA); \ 63({ \
64 unsigned long flags; \
65 unsigned int val; \
66 spin_lock_irqsave(&dcr_ind_lock, flags); \
67 mtdcr(DCRN_ ## base ## _CONFIG_ADDR, reg); \
68 val = mfdcr(DCRN_ ## base ## _CONFIG_DATA); \
69 spin_unlock_irqrestore(&dcr_ind_lock, flags); \
70 val; \
62}) 71})
63 72
64#define mtdcri(base, reg, data) \ 73#define mtdcri(base, reg, data) \
65do { \ 74do { \
66 mtdcr(base ## _CFGADDR, base ## _ ## reg); \ 75 unsigned long flags; \
67 mtdcr(base ## _CFGDATA, data); \ 76 spin_lock_irqsave(&dcr_ind_lock, flags); \
77 mtdcr(DCRN_ ## base ## _CONFIG_ADDR, reg); \
78 mtdcr(DCRN_ ## base ## _CONFIG_DATA, data); \
79 spin_unlock_irqrestore(&dcr_ind_lock, flags); \
68} while (0) 80} while (0)
69 81
70#endif /* __ASSEMBLY__ */ 82#endif /* __ASSEMBLY__ */
71#endif /* __KERNEL__ */ 83#endif /* __KERNEL__ */
72#endif /* _ASM_POWERPC_DCR_NATIVE_H */ 84#endif /* _ASM_POWERPC_DCR_NATIVE_H */
73
74
diff --git a/include/asm-powerpc/dcr-regs.h b/include/asm-powerpc/dcr-regs.h
new file mode 100644
index 00000000000..9f1fb98fcdc
--- /dev/null
+++ b/include/asm-powerpc/dcr-regs.h
@@ -0,0 +1,71 @@
1/*
2 * Common DCR / SDR / CPR register definitions used on various IBM/AMCC
3 * 4xx processors
4 *
5 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp
6 * <benh@kernel.crashing.org>
7 *
8 * Mostly lifted from asm-ppc/ibm4xx.h by
9 *
10 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
11 *
12 */
13
14#ifndef __DCR_REGS_H__
15#define __DCR_REGS_H__
16
17/*
18 * Most DCRs used for controlling devices such as the MAL, DMA engine,
19 * etc... are obtained for the device tree.
20 *
21 * The definitions in this files are fixed DCRs and indirect DCRs that
22 * are commonly used outside of specific drivers or refer to core
23 * common registers that may occasionally have to be tweaked outside
24 * of the driver main register set
25 */
26
27/* CPRs (440GX and 440SP/440SPe) */
28#define DCRN_CPR0_CONFIG_ADDR 0xc
29#define DCRN_CPR0_CONFIG_DATA 0xd
30
31/* SDRs (440GX and 440SP/440SPe) */
32#define DCRN_SDR0_CONFIG_ADDR 0xe
33#define DCRN_SDR0_CONFIG_DATA 0xf
34
35#define SDR0_PFC0 0x4100
36#define SDR0_PFC1 0x4101
37#define SDR0_PFC1_EPS 0x1c00000
38#define SDR0_PFC1_EPS_SHIFT 22
39#define SDR0_PFC1_RMII 0x02000000
40#define SDR0_MFR 0x4300
41#define SDR0_MFR_TAH0 0x80000000 /* TAHOE0 Enable */
42#define SDR0_MFR_TAH1 0x40000000 /* TAHOE1 Enable */
43#define SDR0_MFR_PCM 0x10000000 /* PPC440GP irq compat mode */
44#define SDR0_MFR_ECS 0x08000000 /* EMAC int clk */
45#define SDR0_MFR_T0TXFL 0x00080000
46#define SDR0_MFR_T0TXFH 0x00040000
47#define SDR0_MFR_T1TXFL 0x00020000
48#define SDR0_MFR_T1TXFH 0x00010000
49#define SDR0_MFR_E0TXFL 0x00008000
50#define SDR0_MFR_E0TXFH 0x00004000
51#define SDR0_MFR_E0RXFL 0x00002000
52#define SDR0_MFR_E0RXFH 0x00001000
53#define SDR0_MFR_E1TXFL 0x00000800
54#define SDR0_MFR_E1TXFH 0x00000400
55#define SDR0_MFR_E1RXFL 0x00000200
56#define SDR0_MFR_E1RXFH 0x00000100
57#define SDR0_MFR_E2TXFL 0x00000080
58#define SDR0_MFR_E2TXFH 0x00000040
59#define SDR0_MFR_E2RXFL 0x00000020
60#define SDR0_MFR_E2RXFH 0x00000010
61#define SDR0_MFR_E3TXFL 0x00000008
62#define SDR0_MFR_E3TXFH 0x00000004
63#define SDR0_MFR_E3RXFL 0x00000002
64#define SDR0_MFR_E3RXFH 0x00000001
65#define SDR0_UART0 0x0120
66#define SDR0_UART1 0x0121
67#define SDR0_UART2 0x0122
68#define SDR0_UART3 0x0123
69#define SDR0_CUST0 0x4000
70
71#endif /* __DCR_REGS_H__ */
diff --git a/include/asm-powerpc/dma-mapping.h b/include/asm-powerpc/dma-mapping.h
index ff52013c0e2..bbefb69bfb6 100644
--- a/include/asm-powerpc/dma-mapping.h
+++ b/include/asm-powerpc/dma-mapping.h
@@ -76,6 +76,11 @@ static inline struct dma_mapping_ops *get_dma_ops(struct device *dev)
76 return dev->archdata.dma_ops; 76 return dev->archdata.dma_ops;
77} 77}
78 78
79static inline void set_dma_ops(struct device *dev, struct dma_mapping_ops *ops)
80{
81 dev->archdata.dma_ops = ops;
82}
83
79static inline int dma_supported(struct device *dev, u64 mask) 84static inline int dma_supported(struct device *dev, u64 mask)
80{ 85{
81 struct dma_mapping_ops *dma_ops = get_dma_ops(dev); 86 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
@@ -87,6 +92,9 @@ static inline int dma_supported(struct device *dev, u64 mask)
87 return dma_ops->dma_supported(dev, mask); 92 return dma_ops->dma_supported(dev, mask);
88} 93}
89 94
95/* We have our own implementation of pci_set_dma_mask() */
96#define HAVE_ARCH_PCI_SET_DMA_MASK
97
90static inline int dma_set_mask(struct device *dev, u64 dma_mask) 98static inline int dma_set_mask(struct device *dev, u64 dma_mask)
91{ 99{
92 struct dma_mapping_ops *dma_ops = get_dma_ops(dev); 100 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
@@ -186,8 +194,6 @@ static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
186extern struct dma_mapping_ops dma_iommu_ops; 194extern struct dma_mapping_ops dma_iommu_ops;
187extern struct dma_mapping_ops dma_direct_ops; 195extern struct dma_mapping_ops dma_direct_ops;
188 196
189extern unsigned long dma_direct_offset;
190
191#else /* CONFIG_PPC64 */ 197#else /* CONFIG_PPC64 */
192 198
193#define dma_supported(dev, mask) (1) 199#define dma_supported(dev, mask) (1)
diff --git a/include/asm-powerpc/firmware.h b/include/asm-powerpc/firmware.h
index 3671c128f27..1e41bd1c850 100644
--- a/include/asm-powerpc/firmware.h
+++ b/include/asm-powerpc/firmware.h
@@ -64,7 +64,7 @@ enum {
64 FW_FEATURE_PS3_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1, 64 FW_FEATURE_PS3_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1,
65 FW_FEATURE_PS3_ALWAYS = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1, 65 FW_FEATURE_PS3_ALWAYS = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1,
66 FW_FEATURE_CELLEB_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_BEAT, 66 FW_FEATURE_CELLEB_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_BEAT,
67 FW_FEATURE_CELLEB_ALWAYS = FW_FEATURE_LPAR | FW_FEATURE_BEAT, 67 FW_FEATURE_CELLEB_ALWAYS = 0,
68 FW_FEATURE_NATIVE_POSSIBLE = 0, 68 FW_FEATURE_NATIVE_POSSIBLE = 0,
69 FW_FEATURE_NATIVE_ALWAYS = 0, 69 FW_FEATURE_NATIVE_ALWAYS = 0,
70 FW_FEATURE_POSSIBLE = 70 FW_FEATURE_POSSIBLE =
diff --git a/include/asm-powerpc/immap_86xx.h b/include/asm-powerpc/immap_86xx.h
index 0ad4e653d46..0f165e59c32 100644
--- a/include/asm-powerpc/immap_86xx.h
+++ b/include/asm-powerpc/immap_86xx.h
@@ -89,14 +89,14 @@ struct ccsr_guts {
89 * them. 89 * them.
90 * 90 *
91 * guts: Pointer to GUTS structure 91 * guts: Pointer to GUTS structure
92 * co: The DMA controller (1 or 2) 92 * co: The DMA controller (0 or 1)
93 * ch: The channel on the DMA controller (0, 1, 2, or 3) 93 * ch: The channel on the DMA controller (0, 1, 2, or 3)
94 * device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx) 94 * device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx)
95 */ 95 */
96static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts, 96static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts,
97 unsigned int co, unsigned int ch, unsigned int device) 97 unsigned int co, unsigned int ch, unsigned int device)
98{ 98{
99 unsigned int shift = 16 + (8 * (2 - co) + 2 * (3 - ch)); 99 unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch));
100 100
101 clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift); 101 clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift);
102} 102}
@@ -118,6 +118,27 @@ static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts,
118#define CCSR_GUTS_PMUXCR_DMA1_0 0x00000002 118#define CCSR_GUTS_PMUXCR_DMA1_0 0x00000002
119#define CCSR_GUTS_PMUXCR_DMA1_3 0x00000001 119#define CCSR_GUTS_PMUXCR_DMA1_3 0x00000001
120 120
121/*
122 * Set the DMA external control bits in the GUTS
123 *
124 * The DMA external control bits in the PMUXCR are only meaningful for
125 * channels 0 and 3. Any other channels are ignored.
126 *
127 * guts: Pointer to GUTS structure
128 * co: The DMA controller (0 or 1)
129 * ch: The channel on the DMA controller (0, 1, 2, or 3)
130 * value: the new value for the bit (0 or 1)
131 */
132static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts,
133 unsigned int co, unsigned int ch, unsigned int value)
134{
135 if ((ch == 0) || (ch == 3)) {
136 unsigned int shift = 2 * (co + 1) - (ch & 1) - 1;
137
138 clrsetbits_be32(&guts->pmuxcr, 1 << shift, value << shift);
139 }
140}
141
121#define CCSR_GUTS_CLKDVDR_PXCKEN 0x80000000 142#define CCSR_GUTS_CLKDVDR_PXCKEN 0x80000000
122#define CCSR_GUTS_CLKDVDR_SSICKEN 0x20000000 143#define CCSR_GUTS_CLKDVDR_SSICKEN 0x20000000
123#define CCSR_GUTS_CLKDVDR_PXCKINV 0x10000000 144#define CCSR_GUTS_CLKDVDR_PXCKINV 0x10000000
diff --git a/include/asm-powerpc/immap_qe.h b/include/asm-powerpc/immap_qe.h
index aba9806b31c..82a45261509 100644
--- a/include/asm-powerpc/immap_qe.h
+++ b/include/asm-powerpc/immap_qe.h
@@ -393,9 +393,39 @@ struct dbg {
393 u8 res2[0x48]; 393 u8 res2[0x48];
394} __attribute__ ((packed)); 394} __attribute__ ((packed));
395 395
396/* RISC Special Registers (Trap and Breakpoint) */ 396/*
397 * RISC Special Registers (Trap and Breakpoint). These are described in
398 * the QE Developer's Handbook.
399 */
397struct rsp { 400struct rsp {
398 u32 reg[0x40]; /* 64 32-bit registers */ 401 __be32 tibcr[16]; /* Trap/instruction breakpoint control regs */
402 u8 res0[64];
403 __be32 ibcr0;
404 __be32 ibs0;
405 __be32 ibcnr0;
406 u8 res1[4];
407 __be32 ibcr1;
408 __be32 ibs1;
409 __be32 ibcnr1;
410 __be32 npcr;
411 __be32 dbcr;
412 __be32 dbar;
413 __be32 dbamr;
414 __be32 dbsr;
415 __be32 dbcnr;
416 u8 res2[12];
417 __be32 dbdr_h;
418 __be32 dbdr_l;
419 __be32 dbdmr_h;
420 __be32 dbdmr_l;
421 __be32 bsr;
422 __be32 bor;
423 __be32 bior;
424 u8 res3[4];
425 __be32 iatr[4];
426 __be32 eccr; /* Exception control configuration register */
427 __be32 eicr;
428 u8 res4[0x100-0xf8];
399} __attribute__ ((packed)); 429} __attribute__ ((packed));
400 430
401struct qe_immap { 431struct qe_immap {
diff --git a/include/asm-powerpc/io.h b/include/asm-powerpc/io.h
index e44cdfc8493..7be26f61575 100644
--- a/include/asm-powerpc/io.h
+++ b/include/asm-powerpc/io.h
@@ -50,15 +50,16 @@ extern int check_legacy_ioport(unsigned long base_port);
50#define PCI_DRAM_OFFSET pci_dram_offset 50#define PCI_DRAM_OFFSET pci_dram_offset
51#else 51#else
52#define _IO_BASE pci_io_base 52#define _IO_BASE pci_io_base
53#define _ISA_MEM_BASE 0 53#define _ISA_MEM_BASE isa_mem_base
54#define PCI_DRAM_OFFSET 0 54#define PCI_DRAM_OFFSET 0
55#endif 55#endif
56 56
57extern unsigned long isa_io_base; 57extern unsigned long isa_io_base;
58extern unsigned long isa_mem_base;
59extern unsigned long pci_io_base; 58extern unsigned long pci_io_base;
60extern unsigned long pci_dram_offset; 59extern unsigned long pci_dram_offset;
61 60
61extern resource_size_t isa_mem_base;
62
62#if defined(CONFIG_PPC32) && defined(CONFIG_PPC_INDIRECT_IO) 63#if defined(CONFIG_PPC32) && defined(CONFIG_PPC_INDIRECT_IO)
63#error CONFIG_PPC_INDIRECT_IO is not yet supported on 32 bits 64#error CONFIG_PPC_INDIRECT_IO is not yet supported on 32 bits
64#endif 65#endif
diff --git a/include/asm-powerpc/iommu.h b/include/asm-powerpc/iommu.h
index 4a82fdccee9..7a3cef785ab 100644
--- a/include/asm-powerpc/iommu.h
+++ b/include/asm-powerpc/iommu.h
@@ -69,10 +69,9 @@ struct iommu_table {
69}; 69};
70 70
71struct scatterlist; 71struct scatterlist;
72struct device_node;
73 72
74/* Frees table for an individual device node */ 73/* Frees table for an individual device node */
75extern void iommu_free_table(struct device_node *dn); 74extern void iommu_free_table(struct iommu_table *tbl, const char *node_name);
76 75
77/* Initializes an iommu_table based in values set in the passed-in 76/* Initializes an iommu_table based in values set in the passed-in
78 * structure 77 * structure
diff --git a/include/asm-powerpc/ipic.h b/include/asm-powerpc/ipic.h
index edec79dcb7c..8ff08be0014 100644
--- a/include/asm-powerpc/ipic.h
+++ b/include/asm-powerpc/ipic.h
@@ -20,11 +20,13 @@
20 20
21/* Flags when we init the IPIC */ 21/* Flags when we init the IPIC */
22#define IPIC_SPREADMODE_GRP_A 0x00000001 22#define IPIC_SPREADMODE_GRP_A 0x00000001
23#define IPIC_SPREADMODE_GRP_D 0x00000002 23#define IPIC_SPREADMODE_GRP_B 0x00000002
24#define IPIC_SPREADMODE_MIX_A 0x00000004 24#define IPIC_SPREADMODE_GRP_C 0x00000004
25#define IPIC_SPREADMODE_MIX_B 0x00000008 25#define IPIC_SPREADMODE_GRP_D 0x00000008
26#define IPIC_DISABLE_MCP_OUT 0x00000010 26#define IPIC_SPREADMODE_MIX_A 0x00000010
27#define IPIC_IRQ0_MCP 0x00000020 27#define IPIC_SPREADMODE_MIX_B 0x00000020
28#define IPIC_DISABLE_MCP_OUT 0x00000040
29#define IPIC_IRQ0_MCP 0x00000080
28 30
29/* IPIC registers offsets */ 31/* IPIC registers offsets */
30#define IPIC_SICFR 0x00 /* System Global Interrupt Configuration Register */ 32#define IPIC_SICFR 0x00 /* System Global Interrupt Configuration Register */
diff --git a/include/asm-powerpc/irq.h b/include/asm-powerpc/irq.h
index 1392db45652..b5c03127a9b 100644
--- a/include/asm-powerpc/irq.h
+++ b/include/asm-powerpc/irq.h
@@ -483,218 +483,6 @@ static __inline__ int irq_canonicalize(int irq)
483 */ 483 */
484#define mk_int_int_mask(IL) (1 << (7 - (IL/2))) 484#define mk_int_int_mask(IL) (1 << (7 - (IL/2)))
485 485
486#elif defined(CONFIG_83xx)
487#include <asm/mpc83xx.h>
488
489#define NR_IRQS (NR_IPIC_INTS)
490
491#elif defined(CONFIG_85xx)
492/* Now include the board configuration specific associations.
493*/
494#include <asm/mpc85xx.h>
495
496/* The MPC8548 openpic has 48 internal interrupts and 12 external
497 * interrupts.
498 *
499 * We are "flattening" the interrupt vectors of the cascaded CPM
500 * so that we can uniquely identify any interrupt source with a
501 * single integer.
502 */
503#define NR_CPM_INTS 64
504#define NR_EPIC_INTS 60
505#ifndef NR_8259_INTS
506#define NR_8259_INTS 0
507#endif
508#define NUM_8259_INTERRUPTS NR_8259_INTS
509
510#ifndef CPM_IRQ_OFFSET
511#define CPM_IRQ_OFFSET 0
512#endif
513
514#define NR_IRQS (NR_EPIC_INTS + NR_CPM_INTS + NR_8259_INTS)
515
516/* Internal IRQs on MPC85xx OpenPIC */
517
518#ifndef MPC85xx_OPENPIC_IRQ_OFFSET
519#ifdef CONFIG_CPM2
520#define MPC85xx_OPENPIC_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS)
521#else
522#define MPC85xx_OPENPIC_IRQ_OFFSET 0
523#endif
524#endif
525
526/* Not all of these exist on all MPC85xx implementations */
527#define MPC85xx_IRQ_L2CACHE ( 0 + MPC85xx_OPENPIC_IRQ_OFFSET)
528#define MPC85xx_IRQ_ECM ( 1 + MPC85xx_OPENPIC_IRQ_OFFSET)
529#define MPC85xx_IRQ_DDR ( 2 + MPC85xx_OPENPIC_IRQ_OFFSET)
530#define MPC85xx_IRQ_LBIU ( 3 + MPC85xx_OPENPIC_IRQ_OFFSET)
531#define MPC85xx_IRQ_DMA0 ( 4 + MPC85xx_OPENPIC_IRQ_OFFSET)
532#define MPC85xx_IRQ_DMA1 ( 5 + MPC85xx_OPENPIC_IRQ_OFFSET)
533#define MPC85xx_IRQ_DMA2 ( 6 + MPC85xx_OPENPIC_IRQ_OFFSET)
534#define MPC85xx_IRQ_DMA3 ( 7 + MPC85xx_OPENPIC_IRQ_OFFSET)
535#define MPC85xx_IRQ_PCI1 ( 8 + MPC85xx_OPENPIC_IRQ_OFFSET)
536#define MPC85xx_IRQ_PCI2 ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET)
537#define MPC85xx_IRQ_RIO_ERROR ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET)
538#define MPC85xx_IRQ_RIO_BELL (10 + MPC85xx_OPENPIC_IRQ_OFFSET)
539#define MPC85xx_IRQ_RIO_TX (11 + MPC85xx_OPENPIC_IRQ_OFFSET)
540#define MPC85xx_IRQ_RIO_RX (12 + MPC85xx_OPENPIC_IRQ_OFFSET)
541#define MPC85xx_IRQ_TSEC1_TX (13 + MPC85xx_OPENPIC_IRQ_OFFSET)
542#define MPC85xx_IRQ_TSEC1_RX (14 + MPC85xx_OPENPIC_IRQ_OFFSET)
543#define MPC85xx_IRQ_TSEC3_TX (15 + MPC85xx_OPENPIC_IRQ_OFFSET)
544#define MPC85xx_IRQ_TSEC3_RX (16 + MPC85xx_OPENPIC_IRQ_OFFSET)
545#define MPC85xx_IRQ_TSEC3_ERROR (17 + MPC85xx_OPENPIC_IRQ_OFFSET)
546#define MPC85xx_IRQ_TSEC1_ERROR (18 + MPC85xx_OPENPIC_IRQ_OFFSET)
547#define MPC85xx_IRQ_TSEC2_TX (19 + MPC85xx_OPENPIC_IRQ_OFFSET)
548#define MPC85xx_IRQ_TSEC2_RX (20 + MPC85xx_OPENPIC_IRQ_OFFSET)
549#define MPC85xx_IRQ_TSEC4_TX (21 + MPC85xx_OPENPIC_IRQ_OFFSET)
550#define MPC85xx_IRQ_TSEC4_RX (22 + MPC85xx_OPENPIC_IRQ_OFFSET)
551#define MPC85xx_IRQ_TSEC4_ERROR (23 + MPC85xx_OPENPIC_IRQ_OFFSET)
552#define MPC85xx_IRQ_TSEC2_ERROR (24 + MPC85xx_OPENPIC_IRQ_OFFSET)
553#define MPC85xx_IRQ_FEC (25 + MPC85xx_OPENPIC_IRQ_OFFSET)
554#define MPC85xx_IRQ_DUART (26 + MPC85xx_OPENPIC_IRQ_OFFSET)
555#define MPC85xx_IRQ_IIC1 (27 + MPC85xx_OPENPIC_IRQ_OFFSET)
556#define MPC85xx_IRQ_PERFMON (28 + MPC85xx_OPENPIC_IRQ_OFFSET)
557#define MPC85xx_IRQ_SEC2 (29 + MPC85xx_OPENPIC_IRQ_OFFSET)
558#define MPC85xx_IRQ_CPM (30 + MPC85xx_OPENPIC_IRQ_OFFSET)
559
560/* The 12 external interrupt lines */
561#define MPC85xx_IRQ_EXT0 (48 + MPC85xx_OPENPIC_IRQ_OFFSET)
562#define MPC85xx_IRQ_EXT1 (49 + MPC85xx_OPENPIC_IRQ_OFFSET)
563#define MPC85xx_IRQ_EXT2 (50 + MPC85xx_OPENPIC_IRQ_OFFSET)
564#define MPC85xx_IRQ_EXT3 (51 + MPC85xx_OPENPIC_IRQ_OFFSET)
565#define MPC85xx_IRQ_EXT4 (52 + MPC85xx_OPENPIC_IRQ_OFFSET)
566#define MPC85xx_IRQ_EXT5 (53 + MPC85xx_OPENPIC_IRQ_OFFSET)
567#define MPC85xx_IRQ_EXT6 (54 + MPC85xx_OPENPIC_IRQ_OFFSET)
568#define MPC85xx_IRQ_EXT7 (55 + MPC85xx_OPENPIC_IRQ_OFFSET)
569#define MPC85xx_IRQ_EXT8 (56 + MPC85xx_OPENPIC_IRQ_OFFSET)
570#define MPC85xx_IRQ_EXT9 (57 + MPC85xx_OPENPIC_IRQ_OFFSET)
571#define MPC85xx_IRQ_EXT10 (58 + MPC85xx_OPENPIC_IRQ_OFFSET)
572#define MPC85xx_IRQ_EXT11 (59 + MPC85xx_OPENPIC_IRQ_OFFSET)
573
574/* CPM related interrupts */
575#define SIU_INT_ERROR ((uint)0x00+CPM_IRQ_OFFSET)
576#define SIU_INT_I2C ((uint)0x01+CPM_IRQ_OFFSET)
577#define SIU_INT_SPI ((uint)0x02+CPM_IRQ_OFFSET)
578#define SIU_INT_RISC ((uint)0x03+CPM_IRQ_OFFSET)
579#define SIU_INT_SMC1 ((uint)0x04+CPM_IRQ_OFFSET)
580#define SIU_INT_SMC2 ((uint)0x05+CPM_IRQ_OFFSET)
581#define SIU_INT_USB ((uint)0x0b+CPM_IRQ_OFFSET)
582#define SIU_INT_TIMER1 ((uint)0x0c+CPM_IRQ_OFFSET)
583#define SIU_INT_TIMER2 ((uint)0x0d+CPM_IRQ_OFFSET)
584#define SIU_INT_TIMER3 ((uint)0x0e+CPM_IRQ_OFFSET)
585#define SIU_INT_TIMER4 ((uint)0x0f+CPM_IRQ_OFFSET)
586#define SIU_INT_FCC1 ((uint)0x20+CPM_IRQ_OFFSET)
587#define SIU_INT_FCC2 ((uint)0x21+CPM_IRQ_OFFSET)
588#define SIU_INT_FCC3 ((uint)0x22+CPM_IRQ_OFFSET)
589#define SIU_INT_MCC1 ((uint)0x24+CPM_IRQ_OFFSET)
590#define SIU_INT_MCC2 ((uint)0x25+CPM_IRQ_OFFSET)
591#define SIU_INT_SCC1 ((uint)0x28+CPM_IRQ_OFFSET)
592#define SIU_INT_SCC2 ((uint)0x29+CPM_IRQ_OFFSET)
593#define SIU_INT_SCC3 ((uint)0x2a+CPM_IRQ_OFFSET)
594#define SIU_INT_SCC4 ((uint)0x2b+CPM_IRQ_OFFSET)
595#define SIU_INT_PC15 ((uint)0x30+CPM_IRQ_OFFSET)
596#define SIU_INT_PC14 ((uint)0x31+CPM_IRQ_OFFSET)
597#define SIU_INT_PC13 ((uint)0x32+CPM_IRQ_OFFSET)
598#define SIU_INT_PC12 ((uint)0x33+CPM_IRQ_OFFSET)
599#define SIU_INT_PC11 ((uint)0x34+CPM_IRQ_OFFSET)
600#define SIU_INT_PC10 ((uint)0x35+CPM_IRQ_OFFSET)
601#define SIU_INT_PC9 ((uint)0x36+CPM_IRQ_OFFSET)
602#define SIU_INT_PC8 ((uint)0x37+CPM_IRQ_OFFSET)
603#define SIU_INT_PC7 ((uint)0x38+CPM_IRQ_OFFSET)
604#define SIU_INT_PC6 ((uint)0x39+CPM_IRQ_OFFSET)
605#define SIU_INT_PC5 ((uint)0x3a+CPM_IRQ_OFFSET)
606#define SIU_INT_PC4 ((uint)0x3b+CPM_IRQ_OFFSET)
607#define SIU_INT_PC3 ((uint)0x3c+CPM_IRQ_OFFSET)
608#define SIU_INT_PC2 ((uint)0x3d+CPM_IRQ_OFFSET)
609#define SIU_INT_PC1 ((uint)0x3e+CPM_IRQ_OFFSET)
610#define SIU_INT_PC0 ((uint)0x3f+CPM_IRQ_OFFSET)
611
612#elif defined(CONFIG_PPC_86xx)
613#include <asm/mpc86xx.h>
614
615#define NR_EPIC_INTS 48
616#ifndef NR_8259_INTS
617#define NR_8259_INTS 16 /*ULI 1575 can route 12 interrupts */
618#endif
619#define NUM_8259_INTERRUPTS NR_8259_INTS
620
621#ifndef I8259_OFFSET
622#define I8259_OFFSET 0
623#endif
624
625#define NR_IRQS 256
626
627/* Internal IRQs on MPC86xx OpenPIC */
628
629#ifndef MPC86xx_OPENPIC_IRQ_OFFSET
630#define MPC86xx_OPENPIC_IRQ_OFFSET NR_8259_INTS
631#endif
632
633/* The 48 internal sources */
634#define MPC86xx_IRQ_NULL ( 0 + MPC86xx_OPENPIC_IRQ_OFFSET)
635#define MPC86xx_IRQ_MCM ( 1 + MPC86xx_OPENPIC_IRQ_OFFSET)
636#define MPC86xx_IRQ_DDR ( 2 + MPC86xx_OPENPIC_IRQ_OFFSET)
637#define MPC86xx_IRQ_LBC ( 3 + MPC86xx_OPENPIC_IRQ_OFFSET)
638#define MPC86xx_IRQ_DMA0 ( 4 + MPC86xx_OPENPIC_IRQ_OFFSET)
639#define MPC86xx_IRQ_DMA1 ( 5 + MPC86xx_OPENPIC_IRQ_OFFSET)
640#define MPC86xx_IRQ_DMA2 ( 6 + MPC86xx_OPENPIC_IRQ_OFFSET)
641#define MPC86xx_IRQ_DMA3 ( 7 + MPC86xx_OPENPIC_IRQ_OFFSET)
642
643/* no 10,11 */
644#define MPC86xx_IRQ_UART2 (12 + MPC86xx_OPENPIC_IRQ_OFFSET)
645#define MPC86xx_IRQ_TSEC1_TX (13 + MPC86xx_OPENPIC_IRQ_OFFSET)
646#define MPC86xx_IRQ_TSEC1_RX (14 + MPC86xx_OPENPIC_IRQ_OFFSET)
647#define MPC86xx_IRQ_TSEC3_TX (15 + MPC86xx_OPENPIC_IRQ_OFFSET)
648#define MPC86xx_IRQ_TSEC3_RX (16 + MPC86xx_OPENPIC_IRQ_OFFSET)
649#define MPC86xx_IRQ_TSEC3_ERROR (17 + MPC86xx_OPENPIC_IRQ_OFFSET)
650#define MPC86xx_IRQ_TSEC1_ERROR (18 + MPC86xx_OPENPIC_IRQ_OFFSET)
651#define MPC86xx_IRQ_TSEC2_TX (19 + MPC86xx_OPENPIC_IRQ_OFFSET)
652#define MPC86xx_IRQ_TSEC2_RX (20 + MPC86xx_OPENPIC_IRQ_OFFSET)
653#define MPC86xx_IRQ_TSEC4_TX (21 + MPC86xx_OPENPIC_IRQ_OFFSET)
654#define MPC86xx_IRQ_TSEC4_RX (22 + MPC86xx_OPENPIC_IRQ_OFFSET)
655#define MPC86xx_IRQ_TSEC4_ERROR (23 + MPC86xx_OPENPIC_IRQ_OFFSET)
656#define MPC86xx_IRQ_TSEC2_ERROR (24 + MPC86xx_OPENPIC_IRQ_OFFSET)
657/* no 25 */
658#define MPC86xx_IRQ_UART1 (26 + MPC86xx_OPENPIC_IRQ_OFFSET)
659#define MPC86xx_IRQ_IIC (27 + MPC86xx_OPENPIC_IRQ_OFFSET)
660#define MPC86xx_IRQ_PERFMON (28 + MPC86xx_OPENPIC_IRQ_OFFSET)
661/* no 29,30,31 */
662#define MPC86xx_IRQ_SRIO_ERROR (32 + MPC86xx_OPENPIC_IRQ_OFFSET)
663#define MPC86xx_IRQ_SRIO_OUT_BELL (33 + MPC86xx_OPENPIC_IRQ_OFFSET)
664#define MPC86xx_IRQ_SRIO_IN_BELL (34 + MPC86xx_OPENPIC_IRQ_OFFSET)
665/* no 35,36 */
666#define MPC86xx_IRQ_SRIO_OUT_MSG1 (37 + MPC86xx_OPENPIC_IRQ_OFFSET)
667#define MPC86xx_IRQ_SRIO_IN_MSG1 (38 + MPC86xx_OPENPIC_IRQ_OFFSET)
668#define MPC86xx_IRQ_SRIO_OUT_MSG2 (39 + MPC86xx_OPENPIC_IRQ_OFFSET)
669#define MPC86xx_IRQ_SRIO_IN_MSG2 (40 + MPC86xx_OPENPIC_IRQ_OFFSET)
670
671/* The 12 external interrupt lines */
672#define MPC86xx_IRQ_EXT_BASE 48
673#define MPC86xx_IRQ_EXT0 (0 + MPC86xx_IRQ_EXT_BASE \
674 + MPC86xx_OPENPIC_IRQ_OFFSET)
675#define MPC86xx_IRQ_EXT1 (1 + MPC86xx_IRQ_EXT_BASE \
676 + MPC86xx_OPENPIC_IRQ_OFFSET)
677#define MPC86xx_IRQ_EXT2 (2 + MPC86xx_IRQ_EXT_BASE \
678 + MPC86xx_OPENPIC_IRQ_OFFSET)
679#define MPC86xx_IRQ_EXT3 (3 + MPC86xx_IRQ_EXT_BASE \
680 + MPC86xx_OPENPIC_IRQ_OFFSET)
681#define MPC86xx_IRQ_EXT4 (4 + MPC86xx_IRQ_EXT_BASE \
682 + MPC86xx_OPENPIC_IRQ_OFFSET)
683#define MPC86xx_IRQ_EXT5 (5 + MPC86xx_IRQ_EXT_BASE \
684 + MPC86xx_OPENPIC_IRQ_OFFSET)
685#define MPC86xx_IRQ_EXT6 (6 + MPC86xx_IRQ_EXT_BASE \
686 + MPC86xx_OPENPIC_IRQ_OFFSET)
687#define MPC86xx_IRQ_EXT7 (7 + MPC86xx_IRQ_EXT_BASE \
688 + MPC86xx_OPENPIC_IRQ_OFFSET)
689#define MPC86xx_IRQ_EXT8 (8 + MPC86xx_IRQ_EXT_BASE \
690 + MPC86xx_OPENPIC_IRQ_OFFSET)
691#define MPC86xx_IRQ_EXT9 (9 + MPC86xx_IRQ_EXT_BASE \
692 + MPC86xx_OPENPIC_IRQ_OFFSET)
693#define MPC86xx_IRQ_EXT10 (10 + MPC86xx_IRQ_EXT_BASE \
694 + MPC86xx_OPENPIC_IRQ_OFFSET)
695#define MPC86xx_IRQ_EXT11 (11 + MPC86xx_IRQ_EXT_BASE \
696 + MPC86xx_OPENPIC_IRQ_OFFSET)
697
698#else /* CONFIG_40x + CONFIG_8xx */ 486#else /* CONFIG_40x + CONFIG_8xx */
699/* 487/*
700 * this is the # irq's for all ppc arch's (pmac/chrp/prep) 488 * this is the # irq's for all ppc arch's (pmac/chrp/prep)
diff --git a/include/asm-powerpc/iseries/hv_lp_event.h b/include/asm-powerpc/iseries/hv_lp_event.h
index 6ce2ce1e269..8f5da7d7720 100644
--- a/include/asm-powerpc/iseries/hv_lp_event.h
+++ b/include/asm-powerpc/iseries/hv_lp_event.h
@@ -78,7 +78,7 @@ extern int HvLpEvent_openPath(HvLpEvent_Type eventType, HvLpIndex lpIndex);
78 78
79/* 79/*
80 * Close an Lp Event Path for a type and partition 80 * Close an Lp Event Path for a type and partition
81 * returns 0 on sucess 81 * returns 0 on success
82 */ 82 */
83extern int HvLpEvent_closePath(HvLpEvent_Type eventType, HvLpIndex lpIndex); 83extern int HvLpEvent_closePath(HvLpEvent_Type eventType, HvLpIndex lpIndex);
84 84
diff --git a/include/asm-powerpc/kexec.h b/include/asm-powerpc/kexec.h
index b6f817b8ba3..701857bc8e2 100644
--- a/include/asm-powerpc/kexec.h
+++ b/include/asm-powerpc/kexec.h
@@ -123,6 +123,9 @@ struct pt_regs;
123extern void default_machine_kexec(struct kimage *image); 123extern void default_machine_kexec(struct kimage *image);
124extern int default_machine_kexec_prepare(struct kimage *image); 124extern int default_machine_kexec_prepare(struct kimage *image);
125extern void default_machine_crash_shutdown(struct pt_regs *regs); 125extern void default_machine_crash_shutdown(struct pt_regs *regs);
126typedef void (*crash_shutdown_t)(void);
127extern int crash_shutdown_register(crash_shutdown_t handler);
128extern int crash_shutdown_unregister(crash_shutdown_t handler);
126 129
127extern void machine_kexec_simple(struct kimage *image); 130extern void machine_kexec_simple(struct kimage *image);
128extern void crash_kexec_secondary(struct pt_regs *regs); 131extern void crash_kexec_secondary(struct pt_regs *regs);
diff --git a/include/asm-powerpc/lmb.h b/include/asm-powerpc/lmb.h
index b5f9f4c9c29..5d1dc48a0bb 100644
--- a/include/asm-powerpc/lmb.h
+++ b/include/asm-powerpc/lmb.h
@@ -51,6 +51,7 @@ extern unsigned long __init __lmb_alloc_base(unsigned long size,
51extern unsigned long __init lmb_phys_mem_size(void); 51extern unsigned long __init lmb_phys_mem_size(void);
52extern unsigned long __init lmb_end_of_DRAM(void); 52extern unsigned long __init lmb_end_of_DRAM(void);
53extern void __init lmb_enforce_memory_limit(unsigned long memory_limit); 53extern void __init lmb_enforce_memory_limit(unsigned long memory_limit);
54extern int __init lmb_is_reserved(unsigned long addr);
54 55
55extern void lmb_dump_all(void); 56extern void lmb_dump_all(void);
56 57
diff --git a/include/asm-powerpc/machdep.h b/include/asm-powerpc/machdep.h
index 6968f4300dc..0872ec228c1 100644
--- a/include/asm-powerpc/machdep.h
+++ b/include/asm-powerpc/machdep.h
@@ -204,6 +204,13 @@ struct machdep_calls {
204 /* 204 /*
205 * optional PCI "hooks" 205 * optional PCI "hooks"
206 */ 206 */
207 /* Called in indirect_* to avoid touching devices */
208 int (*pci_exclude_device)(struct pci_controller *, unsigned char, unsigned char);
209
210 /* Called at then very end of pcibios_init() */
211 void (*pcibios_after_init)(void);
212
213#endif /* CONFIG_PPC32 */
207 214
208 /* Called after PPC generic resource fixup to perform 215 /* Called after PPC generic resource fixup to perform
209 machine specific fixups */ 216 machine specific fixups */
@@ -212,18 +219,9 @@ struct machdep_calls {
212 /* Called for each PCI bus in the system when it's probed */ 219 /* Called for each PCI bus in the system when it's probed */
213 void (*pcibios_fixup_bus)(struct pci_bus *); 220 void (*pcibios_fixup_bus)(struct pci_bus *);
214 221
215 /* Called when pci_enable_device() is called (initial=0) or 222 /* Called when pci_enable_device() is called. Returns 0 to
216 * when a device with no assigned resource is found (initial=1). 223 * allow assignment/enabling of the device. */
217 * Returns 0 to allow assignment/enabling of the device. */ 224 int (*pcibios_enable_device_hook)(struct pci_dev *);
218 int (*pcibios_enable_device_hook)(struct pci_dev *, int initial);
219
220 /* Called in indirect_* to avoid touching devices */
221 int (*pci_exclude_device)(struct pci_controller *, unsigned char, unsigned char);
222
223 /* Called at then very end of pcibios_init() */
224 void (*pcibios_after_init)(void);
225
226#endif /* CONFIG_PPC32 */
227 225
228 /* Called to shutdown machine specific hardware not already controlled 226 /* Called to shutdown machine specific hardware not already controlled
229 * by other drivers. 227 * by other drivers.
@@ -253,6 +251,16 @@ struct machdep_calls {
253 */ 251 */
254 void (*machine_kexec)(struct kimage *image); 252 void (*machine_kexec)(struct kimage *image);
255#endif /* CONFIG_KEXEC */ 253#endif /* CONFIG_KEXEC */
254
255#ifdef CONFIG_SUSPEND
256 /* These are called to disable and enable, respectively, IRQs when
257 * entering a suspend state. If NULL, then the generic versions
258 * will be called. The generic versions disable/enable the
259 * decrementer along with interrupts.
260 */
261 void (*suspend_disable_irqs)(void);
262 void (*suspend_enable_irqs)(void);
263#endif
256}; 264};
257 265
258extern void power4_idle(void); 266extern void power4_idle(void);
@@ -326,5 +334,31 @@ static inline void log_error(char *buf, unsigned int err_type, int fatal)
326 ppc_md.log_error(buf, err_type, fatal); 334 ppc_md.log_error(buf, err_type, fatal);
327} 335}
328 336
337#define __define_machine_initcall(mach,level,fn,id) \
338 static int __init __machine_initcall_##mach##_##fn(void) { \
339 if (machine_is(mach)) return fn(); \
340 return 0; \
341 } \
342 __define_initcall(level,__machine_initcall_##mach##_##fn,id);
343
344#define machine_core_initcall(mach,fn) __define_machine_initcall(mach,"1",fn,1)
345#define machine_core_initcall_sync(mach,fn) __define_machine_initcall(mach,"1s",fn,1s)
346#define machine_postcore_initcall(mach,fn) __define_machine_initcall(mach,"2",fn,2)
347#define machine_postcore_initcall_sync(mach,fn) __define_machine_initcall(mach,"2s",fn,2s)
348#define machine_arch_initcall(mach,fn) __define_machine_initcall(mach,"3",fn,3)
349#define machine_arch_initcall_sync(mach,fn) __define_machine_initcall(mach,"3s",fn,3s)
350#define machine_subsys_initcall(mach,fn) __define_machine_initcall(mach,"4",fn,4)
351#define machine_subsys_initcall_sync(mach,fn) __define_machine_initcall(mach,"4s",fn,4s)
352#define machine_fs_initcall(mach,fn) __define_machine_initcall(mach,"5",fn,5)
353#define machine_fs_initcall_sync(mach,fn) __define_machine_initcall(mach,"5s",fn,5s)
354#define machine_rootfs_initcall(mach,fn) __define_machine_initcall(mach,"rootfs",fn,rootfs)
355#define machine_device_initcall(mach,fn) __define_machine_initcall(mach,"6",fn,6)
356#define machine_device_initcall_sync(mach,fn) __define_machine_initcall(mach,"6s",fn,6s)
357#define machine_late_initcall(mach,fn) __define_machine_initcall(mach,"7",fn,7)
358#define machine_late_initcall_sync(mach,fn) __define_machine_initcall(mach,"7s",fn,7s)
359
360void generic_suspend_disable_irqs(void);
361void generic_suspend_enable_irqs(void);
362
329#endif /* __KERNEL__ */ 363#endif /* __KERNEL__ */
330#endif /* _ASM_POWERPC_MACHDEP_H */ 364#endif /* _ASM_POWERPC_MACHDEP_H */
diff --git a/include/asm-powerpc/mmu-hash64.h b/include/asm-powerpc/mmu-hash64.h
index 82328dec2b5..2864fa3989e 100644
--- a/include/asm-powerpc/mmu-hash64.h
+++ b/include/asm-powerpc/mmu-hash64.h
@@ -80,7 +80,7 @@ extern char initial_stab[];
80#define HPTE_V_AVPN_SHIFT 7 80#define HPTE_V_AVPN_SHIFT 7
81#define HPTE_V_AVPN ASM_CONST(0x3fffffffffffff80) 81#define HPTE_V_AVPN ASM_CONST(0x3fffffffffffff80)
82#define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT) 82#define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
83#define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & 0xffffffffffffff80)) 83#define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & 0xffffffffffffff80UL))
84#define HPTE_V_BOLTED ASM_CONST(0x0000000000000010) 84#define HPTE_V_BOLTED ASM_CONST(0x0000000000000010)
85#define HPTE_V_LOCK ASM_CONST(0x0000000000000008) 85#define HPTE_V_LOCK ASM_CONST(0x0000000000000008)
86#define HPTE_V_LARGE ASM_CONST(0x0000000000000004) 86#define HPTE_V_LARGE ASM_CONST(0x0000000000000004)
@@ -180,6 +180,7 @@ extern int mmu_vmalloc_psize;
180extern int mmu_io_psize; 180extern int mmu_io_psize;
181extern int mmu_kernel_ssize; 181extern int mmu_kernel_ssize;
182extern int mmu_highuser_ssize; 182extern int mmu_highuser_ssize;
183extern u16 mmu_slb_size;
183 184
184/* 185/*
185 * If the processor supports 64k normal pages but not 64k cache 186 * If the processor supports 64k normal pages but not 64k cache
@@ -264,7 +265,7 @@ static inline unsigned long hpt_hash(unsigned long va, unsigned int shift,
264 265
265extern int __hash_page_4K(unsigned long ea, unsigned long access, 266extern int __hash_page_4K(unsigned long ea, unsigned long access,
266 unsigned long vsid, pte_t *ptep, unsigned long trap, 267 unsigned long vsid, pte_t *ptep, unsigned long trap,
267 unsigned int local, int ssize); 268 unsigned int local, int ssize, int subpage_prot);
268extern int __hash_page_64K(unsigned long ea, unsigned long access, 269extern int __hash_page_64K(unsigned long ea, unsigned long access,
269 unsigned long vsid, pte_t *ptep, unsigned long trap, 270 unsigned long vsid, pte_t *ptep, unsigned long trap,
270 unsigned int local, int ssize); 271 unsigned int local, int ssize);
@@ -277,6 +278,8 @@ extern int hash_huge_page(struct mm_struct *mm, unsigned long access,
277extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend, 278extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
278 unsigned long pstart, unsigned long mode, 279 unsigned long pstart, unsigned long mode,
279 int psize, int ssize); 280 int psize, int ssize);
281extern void set_huge_psize(int psize);
282extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr);
280 283
281extern void htab_initialize(void); 284extern void htab_initialize(void);
282extern void htab_initialize_secondary(void); 285extern void htab_initialize_secondary(void);
diff --git a/include/asm-powerpc/mpc52xx.h b/include/asm-powerpc/mpc52xx.h
index fcb2ebbfddb..81ef10b6b67 100644
--- a/include/asm-powerpc/mpc52xx.h
+++ b/include/asm-powerpc/mpc52xx.h
@@ -248,19 +248,25 @@ struct mpc52xx_cdm {
248 248
249#ifndef __ASSEMBLY__ 249#ifndef __ASSEMBLY__
250 250
251extern void __iomem * mpc52xx_find_and_map(const char *); 251/* mpc52xx_common.c */
252extern void __iomem * mpc52xx_find_and_map_path(const char *path);
253extern unsigned int mpc52xx_find_ipb_freq(struct device_node *node); 252extern unsigned int mpc52xx_find_ipb_freq(struct device_node *node);
254extern void mpc5200_setup_xlb_arbiter(void); 253extern void mpc5200_setup_xlb_arbiter(void);
255extern void mpc52xx_declare_of_platform_devices(void); 254extern void mpc52xx_declare_of_platform_devices(void);
255extern void mpc52xx_map_common_devices(void);
256extern int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv);
257extern void mpc52xx_restart(char *cmd);
256 258
259/* mpc52xx_pic.c */
257extern void mpc52xx_init_irq(void); 260extern void mpc52xx_init_irq(void);
258extern unsigned int mpc52xx_get_irq(void); 261extern unsigned int mpc52xx_get_irq(void);
259 262
263/* mpc52xx_pci.c */
264#ifdef CONFIG_PCI
260extern int __init mpc52xx_add_bridge(struct device_node *node); 265extern int __init mpc52xx_add_bridge(struct device_node *node);
261 266extern void __init mpc52xx_setup_pci(void);
262extern void __init mpc52xx_map_wdt(void); 267#else
263extern void mpc52xx_restart(char *cmd); 268static inline void mpc52xx_setup_pci(void) { }
269#endif
264 270
265#endif /* __ASSEMBLY__ */ 271#endif /* __ASSEMBLY__ */
266 272
diff --git a/include/asm-powerpc/mpc52xx_psc.h b/include/asm-powerpc/mpc52xx_psc.h
index 26690d2b32f..bea42b95390 100644
--- a/include/asm-powerpc/mpc52xx_psc.h
+++ b/include/asm-powerpc/mpc52xx_psc.h
@@ -153,6 +153,9 @@ struct mpc52xx_psc {
153 u8 reserved16[3]; 153 u8 reserved16[3];
154 u8 irfdr; /* PSC + 0x54 */ 154 u8 irfdr; /* PSC + 0x54 */
155 u8 reserved17[3]; 155 u8 reserved17[3];
156};
157
158struct mpc52xx_psc_fifo {
156 u16 rfnum; /* PSC + 0x58 */ 159 u16 rfnum; /* PSC + 0x58 */
157 u16 reserved18; 160 u16 reserved18;
158 u16 tfnum; /* PSC + 0x5c */ 161 u16 tfnum; /* PSC + 0x5c */
diff --git a/include/asm-powerpc/mpc8260.h b/include/asm-powerpc/mpc8260.h
index e0d480790e1..03317e1e618 100644
--- a/include/asm-powerpc/mpc8260.h
+++ b/include/asm-powerpc/mpc8260.h
@@ -8,6 +8,7 @@
8#ifndef __ASM_POWERPC_MPC8260_H__ 8#ifndef __ASM_POWERPC_MPC8260_H__
9#define __ASM_POWERPC_MPC8260_H__ 9#define __ASM_POWERPC_MPC8260_H__
10 10
11#define MPC82XX_BCR_PLDP 0x00800000 /* Pipeline Maximum Depth */
11 12
12#ifdef CONFIG_8260 13#ifdef CONFIG_8260
13 14
diff --git a/include/asm-powerpc/mpc8xx.h b/include/asm-powerpc/mpc8xx.h
index 2be014b6f57..98f3c4f1732 100644
--- a/include/asm-powerpc/mpc8xx.h
+++ b/include/asm-powerpc/mpc8xx.h
@@ -4,29 +4,9 @@
4 * file that has to include MPC8xx configuration, they all include 4 * file that has to include MPC8xx configuration, they all include
5 * this one and the configuration switching is done here. 5 * this one and the configuration switching is done here.
6 */ 6 */
7#ifdef __KERNEL__
8#ifndef __CONFIG_8xx_DEFS 7#ifndef __CONFIG_8xx_DEFS
9#define __CONFIG_8xx_DEFS 8#define __CONFIG_8xx_DEFS
10 9
11
12#ifdef CONFIG_8xx
13
14#ifdef CONFIG_FADS
15#include <platforms/fads.h>
16#endif
17
18#if defined(CONFIG_MPC86XADS)
19#include <platforms/8xx/mpc86xads.h>
20#endif
21
22#if defined(CONFIG_MPC885ADS)
23#include <platforms/8xx/mpc885ads.h>
24#endif
25
26#ifdef CONFIG_PCMCIA_M8XX
27extern struct mpc8xx_pcmcia_ops m8xx_pcmcia_ops; 10extern struct mpc8xx_pcmcia_ops m8xx_pcmcia_ops;
28#endif
29 11
30#endif /* CONFIG_8xx */
31#endif /* __CONFIG_8xx_DEFS */ 12#endif /* __CONFIG_8xx_DEFS */
32#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/mpic.h b/include/asm-powerpc/mpic.h
index ae84dde3bc7..943c5a3fac8 100644
--- a/include/asm-powerpc/mpic.h
+++ b/include/asm-powerpc/mpic.h
@@ -22,7 +22,9 @@
22#define MPIC_GREG_GLOBAL_CONF_0 0x00020 22#define MPIC_GREG_GLOBAL_CONF_0 0x00020
23#define MPIC_GREG_GCONF_RESET 0x80000000 23#define MPIC_GREG_GCONF_RESET 0x80000000
24#define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000 24#define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000
25#define MPIC_GREG_GCONF_NO_BIAS 0x10000000
25#define MPIC_GREG_GCONF_BASE_MASK 0x000fffff 26#define MPIC_GREG_GCONF_BASE_MASK 0x000fffff
27#define MPIC_GREG_GCONF_MCK 0x08000000
26#define MPIC_GREG_GLOBAL_CONF_1 0x00030 28#define MPIC_GREG_GLOBAL_CONF_1 0x00030
27#define MPIC_GREG_GLOBAL_CONF_1_SIE 0x08000000 29#define MPIC_GREG_GLOBAL_CONF_1_SIE 0x08000000
28#define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK 0x70000000 30#define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK 0x70000000
@@ -78,6 +80,7 @@
78#define MPIC_CPU_WHOAMI_MASK 0x0000001f 80#define MPIC_CPU_WHOAMI_MASK 0x0000001f
79#define MPIC_CPU_INTACK 0x000a0 81#define MPIC_CPU_INTACK 0x000a0
80#define MPIC_CPU_EOI 0x000b0 82#define MPIC_CPU_EOI 0x000b0
83#define MPIC_CPU_MCACK 0x000c0
81 84
82/* 85/*
83 * Per-source registers 86 * Per-source registers
@@ -141,6 +144,7 @@
141#define TSI108_CPU_WHOAMI 0xffffffff 144#define TSI108_CPU_WHOAMI 0xffffffff
142#define TSI108_CPU_INTACK 0x00004 145#define TSI108_CPU_INTACK 0x00004
143#define TSI108_CPU_EOI 0x00008 146#define TSI108_CPU_EOI 0x00008
147#define TSI108_CPU_MCACK 0x00004 /* Doesn't really exist here */
144 148
145/* 149/*
146 * Per-source registers 150 * Per-source registers
@@ -183,6 +187,7 @@ enum {
183 MPIC_IDX_CPU_WHOAMI, 187 MPIC_IDX_CPU_WHOAMI,
184 MPIC_IDX_CPU_INTACK, 188 MPIC_IDX_CPU_INTACK,
185 MPIC_IDX_CPU_EOI, 189 MPIC_IDX_CPU_EOI,
190 MPIC_IDX_CPU_MCACK,
186 191
187 MPIC_IDX_IRQ_BASE, 192 MPIC_IDX_IRQ_BASE,
188 MPIC_IDX_IRQ_STRIDE, 193 MPIC_IDX_IRQ_STRIDE,
@@ -344,6 +349,10 @@ struct mpic
344#define MPIC_USES_DCR 0x00000080 349#define MPIC_USES_DCR 0x00000080
345/* MPIC has 11-bit vector fields (or larger) */ 350/* MPIC has 11-bit vector fields (or larger) */
346#define MPIC_LARGE_VECTORS 0x00000100 351#define MPIC_LARGE_VECTORS 0x00000100
352/* Enable delivery of prio 15 interrupts as MCK instead of EE */
353#define MPIC_ENABLE_MCK 0x00000200
354/* Disable bias among target selection, spread interrupts evenly */
355#define MPIC_NO_BIAS 0x00000400
347 356
348/* MPIC HW modification ID */ 357/* MPIC HW modification ID */
349#define MPIC_REGSET_MASK 0xf0000000 358#define MPIC_REGSET_MASK 0xf0000000
@@ -447,10 +456,19 @@ extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask);
447/* Send a message (IPI) to a given target (cpu number or MSG_*) */ 456/* Send a message (IPI) to a given target (cpu number or MSG_*) */
448void smp_mpic_message_pass(int target, int msg); 457void smp_mpic_message_pass(int target, int msg);
449 458
459/* Unmask a specific virq */
460extern void mpic_unmask_irq(unsigned int irq);
461/* Mask a specific virq */
462extern void mpic_mask_irq(unsigned int irq);
463/* EOI a specific virq */
464extern void mpic_end_irq(unsigned int irq);
465
450/* Fetch interrupt from a given mpic */ 466/* Fetch interrupt from a given mpic */
451extern unsigned int mpic_get_one_irq(struct mpic *mpic); 467extern unsigned int mpic_get_one_irq(struct mpic *mpic);
452/* This one gets to the primary mpic */ 468/* This one gets from the primary mpic */
453extern unsigned int mpic_get_irq(void); 469extern unsigned int mpic_get_irq(void);
470/* Fetch Machine Check interrupt from primary mpic */
471extern unsigned int mpic_get_mcirq(void);
454 472
455/* Set the EPIC clock ratio */ 473/* Set the EPIC clock ratio */
456void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio); 474void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio);
diff --git a/include/asm-powerpc/nvram.h b/include/asm-powerpc/nvram.h
index 9877982508b..4e7059cc611 100644
--- a/include/asm-powerpc/nvram.h
+++ b/include/asm-powerpc/nvram.h
@@ -10,6 +10,8 @@
10#ifndef _ASM_POWERPC_NVRAM_H 10#ifndef _ASM_POWERPC_NVRAM_H
11#define _ASM_POWERPC_NVRAM_H 11#define _ASM_POWERPC_NVRAM_H
12 12
13#include <linux/errno.h>
14
13#define NVRW_CNT 0x20 15#define NVRW_CNT 0x20
14#define NVRAM_HEADER_LEN 16 /* sizeof(struct nvram_header) */ 16#define NVRAM_HEADER_LEN 16 /* sizeof(struct nvram_header) */
15#define NVRAM_BLOCK_LEN 16 17#define NVRAM_BLOCK_LEN 16
@@ -71,7 +73,16 @@ extern int nvram_clear_error_log(void);
71extern struct nvram_partition *nvram_find_partition(int sig, const char *name); 73extern struct nvram_partition *nvram_find_partition(int sig, const char *name);
72 74
73extern int pSeries_nvram_init(void); 75extern int pSeries_nvram_init(void);
76
77#ifdef CONFIG_MMIO_NVRAM
74extern int mmio_nvram_init(void); 78extern int mmio_nvram_init(void);
79#else
80static inline int mmio_nvram_init(void)
81{
82 return -ENODEV;
83}
84#endif
85
75#endif /* __KERNEL__ */ 86#endif /* __KERNEL__ */
76 87
77/* PowerMac specific nvram stuffs */ 88/* PowerMac specific nvram stuffs */
diff --git a/include/asm-powerpc/of_platform.h b/include/asm-powerpc/of_platform.h
index 80e6fad28b4..18659ef7213 100644
--- a/include/asm-powerpc/of_platform.h
+++ b/include/asm-powerpc/of_platform.h
@@ -15,8 +15,14 @@
15#include <linux/of_platform.h> 15#include <linux/of_platform.h>
16 16
17/* Platform drivers register/unregister */ 17/* Platform drivers register/unregister */
18extern int of_register_platform_driver(struct of_platform_driver *drv); 18static inline int of_register_platform_driver(struct of_platform_driver *drv)
19extern void of_unregister_platform_driver(struct of_platform_driver *drv); 19{
20 return of_register_driver(drv, &of_platform_bus_type);
21}
22static inline void of_unregister_platform_driver(struct of_platform_driver *drv)
23{
24 of_unregister_driver(drv);
25}
20 26
21/* Platform devices and busses creation */ 27/* Platform devices and busses creation */
22extern struct of_device *of_platform_device_create(struct device_node *np, 28extern struct of_device *of_platform_device_create(struct device_node *np,
@@ -26,9 +32,11 @@ extern struct of_device *of_platform_device_create(struct device_node *np,
26#define OF_NO_DEEP_PROBE ((struct of_device_id *)-1) 32#define OF_NO_DEEP_PROBE ((struct of_device_id *)-1)
27 33
28extern int of_platform_bus_probe(struct device_node *root, 34extern int of_platform_bus_probe(struct device_node *root,
29 struct of_device_id *matches, 35 const struct of_device_id *matches,
30 struct device *parent); 36 struct device *parent);
31 37
32extern struct of_device *of_find_device_by_phandle(phandle ph); 38extern struct of_device *of_find_device_by_phandle(phandle ph);
33 39
40extern void of_instantiate_rtc(void);
41
34#endif /* _ASM_POWERPC_OF_PLATFORM_H */ 42#endif /* _ASM_POWERPC_OF_PLATFORM_H */
diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h
index d8bdc79db12..e5802c62f42 100644
--- a/include/asm-powerpc/pci-bridge.h
+++ b/include/asm-powerpc/pci-bridge.h
@@ -1,15 +1,42 @@
1#ifndef _ASM_POWERPC_PCI_BRIDGE_H 1#ifndef _ASM_POWERPC_PCI_BRIDGE_H
2#define _ASM_POWERPC_PCI_BRIDGE_H 2#define _ASM_POWERPC_PCI_BRIDGE_H
3#ifdef __KERNEL__ 3#ifdef __KERNEL__
4 4/*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
5#include <linux/pci.h> 10#include <linux/pci.h>
6#include <linux/list.h> 11#include <linux/list.h>
7#include <linux/ioport.h> 12#include <linux/ioport.h>
8 13
9#ifndef CONFIG_PPC64
10
11struct device_node; 14struct device_node;
12struct pci_controller; 15
16extern unsigned int ppc_pci_flags;
17enum {
18 /* Force re-assigning all resources (ignore firmware
19 * setup completely)
20 */
21 PPC_PCI_REASSIGN_ALL_RSRC = 0x00000001,
22
23 /* Re-assign all bus numbers */
24 PPC_PCI_REASSIGN_ALL_BUS = 0x00000002,
25
26 /* Do not try to assign, just use existing setup */
27 PPC_PCI_PROBE_ONLY = 0x00000004,
28
29 /* Don't bother with ISA alignment unless the bridge has
30 * ISA forwarding enabled
31 */
32 PPC_PCI_CAN_SKIP_ISA_ALIGN = 0x00000008,
33
34 /* Enable domain numbers in /proc */
35 PPC_PCI_ENABLE_PROC_DOMAINS = 0x00000010,
36 /* ... except for domain 0 */
37 PPC_PCI_COMPAT_DOMAIN_0 = 0x00000020,
38};
39
13 40
14/* 41/*
15 * Structure of a PCI controller (host bridge) 42 * Structure of a PCI controller (host bridge)
@@ -17,26 +44,41 @@ struct pci_controller;
17struct pci_controller { 44struct pci_controller {
18 struct pci_bus *bus; 45 struct pci_bus *bus;
19 char is_dynamic; 46 char is_dynamic;
20 void *arch_data; 47#ifdef CONFIG_PPC64
48 int node;
49#endif
50 struct device_node *dn;
21 struct list_head list_node; 51 struct list_head list_node;
22 struct device *parent; 52 struct device *parent;
23 53
24 int first_busno; 54 int first_busno;
25 int last_busno; 55 int last_busno;
56#ifndef CONFIG_PPC64
26 int self_busno; 57 int self_busno;
58#endif
27 59
28 void __iomem *io_base_virt; 60 void __iomem *io_base_virt;
61#ifdef CONFIG_PPC64
62 void *io_base_alloc;
63#endif
29 resource_size_t io_base_phys; 64 resource_size_t io_base_phys;
65#ifndef CONFIG_PPC64
66 resource_size_t pci_io_size;
67#endif
30 68
31 /* Some machines (PReP) have a non 1:1 mapping of 69 /* Some machines (PReP) have a non 1:1 mapping of
32 * the PCI memory space in the CPU bus space 70 * the PCI memory space in the CPU bus space
33 */ 71 */
34 resource_size_t pci_mem_offset; 72 resource_size_t pci_mem_offset;
73#ifdef CONFIG_PPC64
74 unsigned long pci_io_size;
75#endif
35 76
36 struct pci_ops *ops; 77 struct pci_ops *ops;
37 volatile unsigned int __iomem *cfg_addr; 78 unsigned int __iomem *cfg_addr;
38 volatile void __iomem *cfg_data; 79 void __iomem *cfg_data;
39 80
81#ifndef CONFIG_PPC64
40 /* 82 /*
41 * Used for variants of PCI indirect handling and possible quirks: 83 * Used for variants of PCI indirect handling and possible quirks:
42 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1 84 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
@@ -51,21 +93,30 @@ struct pci_controller {
51 * set. 93 * set.
52 * BIG_ENDIAN - cfg_addr is a big endian register 94 * BIG_ENDIAN - cfg_addr is a big endian register
53 */ 95 */
54#define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001) 96#define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
55#define PPC_INDIRECT_TYPE_EXT_REG (0x00000002) 97#define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
56#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004) 98#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
57#define PPC_INDIRECT_TYPE_NO_PCIE_LINK (0x00000008) 99#define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
58#define PPC_INDIRECT_TYPE_BIG_ENDIAN (0x00000010) 100#define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
59 u32 indirect_type; 101 u32 indirect_type;
60 102#endif /* !CONFIG_PPC64 */
61 /* Currently, we limit ourselves to 1 IO range and 3 mem 103 /* Currently, we limit ourselves to 1 IO range and 3 mem
62 * ranges since the common pci_bus structure can't handle more 104 * ranges since the common pci_bus structure can't handle more
63 */ 105 */
64 struct resource io_resource; 106 struct resource io_resource;
65 struct resource mem_resources[3]; 107 struct resource mem_resources[3];
66 int global_number; /* PCI domain number */ 108 int global_number; /* PCI domain number */
109#ifdef CONFIG_PPC64
110 unsigned long buid;
111 unsigned long dma_window_base_cur;
112 unsigned long dma_window_size;
113
114 void *private_data;
115#endif /* CONFIG_PPC64 */
67}; 116};
68 117
118#ifndef CONFIG_PPC64
119
69static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus) 120static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
70{ 121{
71 return bus->sysdata; 122 return bus->sysdata;
@@ -81,18 +132,18 @@ static inline int isa_vaddr_is_ioport(void __iomem *address)
81 132
82/* These are used for config access before all the PCI probing 133/* These are used for config access before all the PCI probing
83 has been done. */ 134 has been done. */
84int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn, 135extern int early_read_config_byte(struct pci_controller *hose, int bus,
85 int where, u8 *val); 136 int dev_fn, int where, u8 *val);
86int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn, 137extern int early_read_config_word(struct pci_controller *hose, int bus,
87 int where, u16 *val); 138 int dev_fn, int where, u16 *val);
88int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn, 139extern int early_read_config_dword(struct pci_controller *hose, int bus,
89 int where, u32 *val); 140 int dev_fn, int where, u32 *val);
90int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn, 141extern int early_write_config_byte(struct pci_controller *hose, int bus,
91 int where, u8 val); 142 int dev_fn, int where, u8 val);
92int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn, 143extern int early_write_config_word(struct pci_controller *hose, int bus,
93 int where, u16 val); 144 int dev_fn, int where, u16 val);
94int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn, 145extern int early_write_config_dword(struct pci_controller *hose, int bus,
95 int where, u32 val); 146 int dev_fn, int where, u32 val);
96 147
97extern int early_find_capability(struct pci_controller *hose, int bus, 148extern int early_find_capability(struct pci_controller *hose, int bus,
98 int dev_fn, int cap); 149 int dev_fn, int cap);
@@ -101,87 +152,33 @@ extern void setup_indirect_pci(struct pci_controller* hose,
101 resource_size_t cfg_addr, 152 resource_size_t cfg_addr,
102 resource_size_t cfg_data, u32 flags); 153 resource_size_t cfg_data, u32 flags);
103extern void setup_grackle(struct pci_controller *hose); 154extern void setup_grackle(struct pci_controller *hose);
104extern void __init update_bridge_resource(struct pci_dev *dev, 155#else /* CONFIG_PPC64 */
105 struct resource *res);
106
107#else
108
109
110/*
111 * This program is free software; you can redistribute it and/or
112 * modify it under the terms of the GNU General Public License
113 * as published by the Free Software Foundation; either version
114 * 2 of the License, or (at your option) any later version.
115 */
116
117/*
118 * Structure of a PCI controller (host bridge)
119 */
120struct pci_controller {
121 struct pci_bus *bus;
122 char is_dynamic;
123 int node;
124 void *arch_data;
125 struct list_head list_node;
126 struct device *parent;
127
128 int first_busno;
129 int last_busno;
130
131 void __iomem *io_base_virt;
132 void *io_base_alloc;
133 resource_size_t io_base_phys;
134
135 /* Some machines have a non 1:1 mapping of
136 * the PCI memory space in the CPU bus space
137 */
138 resource_size_t pci_mem_offset;
139 unsigned long pci_io_size;
140
141 struct pci_ops *ops;
142 volatile unsigned int __iomem *cfg_addr;
143 volatile void __iomem *cfg_data;
144
145 /* Currently, we limit ourselves to 1 IO range and 3 mem
146 * ranges since the common pci_bus structure can't handle more
147 */
148 struct resource io_resource;
149 struct resource mem_resources[3];
150 int global_number;
151 unsigned long buid;
152 unsigned long dma_window_base_cur;
153 unsigned long dma_window_size;
154
155 void *private_data;
156};
157 156
158/* 157/*
159 * PCI stuff, for nodes representing PCI devices, pointed to 158 * PCI stuff, for nodes representing PCI devices, pointed to
160 * by device_node->data. 159 * by device_node->data.
161 */ 160 */
162struct pci_controller;
163struct iommu_table; 161struct iommu_table;
164 162
165struct pci_dn { 163struct pci_dn {
166 int busno; /* pci bus number */ 164 int busno; /* pci bus number */
167 int bussubno; /* pci subordinate bus number */
168 int devfn; /* pci device and function number */ 165 int devfn; /* pci device and function number */
169 int class_code; /* pci device class */
170 166
171 struct pci_controller *phb; /* for pci devices */ 167 struct pci_controller *phb; /* for pci devices */
172 struct iommu_table *iommu_table; /* for phb's or bridges */ 168 struct iommu_table *iommu_table; /* for phb's or bridges */
173 struct pci_dev *pcidev; /* back-pointer to the pci device */
174 struct device_node *node; /* back-pointer to the device_node */ 169 struct device_node *node; /* back-pointer to the device_node */
175 170
176 int pci_ext_config_space; /* for pci devices */ 171 int pci_ext_config_space; /* for pci devices */
177 172
178#ifdef CONFIG_EEH 173#ifdef CONFIG_EEH
174 struct pci_dev *pcidev; /* back-pointer to the pci device */
175 int class_code; /* pci device class */
179 int eeh_mode; /* See eeh.h for possible EEH_MODEs */ 176 int eeh_mode; /* See eeh.h for possible EEH_MODEs */
180 int eeh_config_addr; 177 int eeh_config_addr;
181 int eeh_pe_config_addr; /* new-style partition endpoint address */ 178 int eeh_pe_config_addr; /* new-style partition endpoint address */
182 int eeh_check_count; /* # times driver ignored error */ 179 int eeh_check_count; /* # times driver ignored error */
183 int eeh_freeze_count; /* # times this device froze up. */ 180 int eeh_freeze_count; /* # times this device froze up. */
184 int eeh_false_positives; /* # times this device reported #ff's */ 181 int eeh_false_positives; /* # times this device reported #ff's */
185 u32 config_space[16]; /* saved PCI config space */ 182 u32 config_space[16]; /* saved PCI config space */
186#endif 183#endif
187}; 184};
@@ -189,7 +186,7 @@ struct pci_dn {
189/* Get the pointer to a device_node's pci_dn */ 186/* Get the pointer to a device_node's pci_dn */
190#define PCI_DN(dn) ((struct pci_dn *) (dn)->data) 187#define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
191 188
192struct device_node *fetch_dev_dn(struct pci_dev *dev); 189extern struct device_node *fetch_dev_dn(struct pci_dev *dev);
193 190
194/* Get a device_node from a pci_dev. This code must be fast except 191/* Get a device_node from a pci_dev. This code must be fast except
195 * in the case where the sysdata is incorrect and needs to be fixed 192 * in the case where the sysdata is incorrect and needs to be fixed
@@ -227,14 +224,14 @@ static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
227} 224}
228 225
229/** Find the bus corresponding to the indicated device node */ 226/** Find the bus corresponding to the indicated device node */
230struct pci_bus * pcibios_find_pci_bus(struct device_node *dn); 227extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);
231 228
232/** Remove all of the PCI devices under this bus */ 229/** Remove all of the PCI devices under this bus */
233void pcibios_remove_pci_devices(struct pci_bus *bus); 230extern void pcibios_remove_pci_devices(struct pci_bus *bus);
234 231
235/** Discover new pci devices under this bus, and add them */ 232/** Discover new pci devices under this bus, and add them */
236void pcibios_add_pci_devices(struct pci_bus * bus); 233extern void pcibios_add_pci_devices(struct pci_bus *bus);
237void pcibios_fixup_new_pci_devices(struct pci_bus *bus, int fix_bus); 234extern void pcibios_fixup_new_pci_devices(struct pci_bus *bus);
238 235
239extern int pcibios_remove_root_bus(struct pci_controller *phb); 236extern int pcibios_remove_root_bus(struct pci_controller *phb);
240 237
@@ -270,20 +267,18 @@ extern int pcibios_map_io_space(struct pci_bus *bus);
270#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1) 267#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
271#endif 268#endif
272 269
273#endif /* CONFIG_PPC64 */ 270#endif /* CONFIG_PPC64 */
274 271
275/* Get the PCI host controller for an OF device */ 272/* Get the PCI host controller for an OF device */
276extern struct pci_controller* 273extern struct pci_controller *pci_find_hose_for_OF_device(
277pci_find_hose_for_OF_device(struct device_node* node); 274 struct device_node* node);
278 275
279/* Fill up host controller resources from the OF node */ 276/* Fill up host controller resources from the OF node */
280extern void 277extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
281pci_process_bridge_OF_ranges(struct pci_controller *hose, 278 struct device_node *dev, int primary);
282 struct device_node *dev, int primary);
283 279
284/* Allocate & free a PCI host bridge structure */ 280/* Allocate & free a PCI host bridge structure */
285extern struct pci_controller * 281extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
286pcibios_alloc_controller(struct device_node *dev);
287extern void pcibios_free_controller(struct pci_controller *phb); 282extern void pcibios_free_controller(struct pci_controller *phb);
288 283
289#ifdef CONFIG_PCI 284#ifdef CONFIG_PCI
@@ -298,9 +293,7 @@ static inline int pcibios_vaddr_is_ioport(void __iomem *address)
298{ 293{
299 return 0; 294 return 0;
300} 295}
301#endif 296#endif /* CONFIG_PCI */
302
303 297
304 298#endif /* __KERNEL__ */
305#endif /* __KERNEL__ */ 299#endif /* _ASM_POWERPC_PCI_BRIDGE_H */
306#endif
diff --git a/include/asm-powerpc/pci.h b/include/asm-powerpc/pci.h
index 7b11765c686..a05a942b1c2 100644
--- a/include/asm-powerpc/pci.h
+++ b/include/asm-powerpc/pci.h
@@ -36,11 +36,10 @@ struct pci_dev;
36 36
37/* 37/*
38 * Set this to 1 if you want the kernel to re-assign all PCI 38 * Set this to 1 if you want the kernel to re-assign all PCI
39 * bus numbers 39 * bus numbers (don't do that on ppc64 yet !)
40 */ 40 */
41extern int pci_assign_all_buses; 41#define pcibios_assign_all_busses() (ppc_pci_flags & \
42#define pcibios_assign_all_busses() (pci_assign_all_buses) 42 PPC_PCI_REASSIGN_ALL_BUS)
43
44#define pcibios_scan_all_fns(a, b) 0 43#define pcibios_scan_all_fns(a, b) 0
45 44
46static inline void pcibios_set_master(struct pci_dev *dev) 45static inline void pcibios_set_master(struct pci_dev *dev)
@@ -95,9 +94,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
95#define get_pci_dma_ops() NULL 94#define get_pci_dma_ops() NULL
96#endif 95#endif
97 96
98/* Decide whether to display the domain number in /proc */
99extern int pci_proc_domain(struct pci_bus *bus);
100
101#else /* 32-bit */ 97#else /* 32-bit */
102 98
103#ifdef CONFIG_PCI 99#ifdef CONFIG_PCI
@@ -109,17 +105,14 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
109 *strategy_parameter = ~0UL; 105 *strategy_parameter = ~0UL;
110} 106}
111#endif 107#endif
112
113/* Set the name of the bus as it appears in /proc/bus/pci */
114static inline int pci_proc_domain(struct pci_bus *bus)
115{
116 return 0;
117}
118
119#endif /* CONFIG_PPC64 */ 108#endif /* CONFIG_PPC64 */
120 109
121extern int pci_domain_nr(struct pci_bus *bus); 110extern int pci_domain_nr(struct pci_bus *bus);
122 111
112/* Decide whether to display the domain number in /proc */
113extern int pci_proc_domain(struct pci_bus *bus);
114
115
123struct vm_area_struct; 116struct vm_area_struct;
124/* Map a range of PCI memory or I/O space for a device into user space */ 117/* Map a range of PCI memory or I/O space for a device into user space */
125int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma, 118int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
@@ -199,13 +192,12 @@ static inline struct resource *pcibios_select_root(struct pci_dev *pdev,
199 return root; 192 return root;
200} 193}
201 194
202extern void pcibios_fixup_device_resources(struct pci_dev *dev,
203 struct pci_bus *bus);
204
205extern void pcibios_setup_new_device(struct pci_dev *dev); 195extern void pcibios_setup_new_device(struct pci_dev *dev);
206 196
207extern void pcibios_claim_one_bus(struct pci_bus *b); 197extern void pcibios_claim_one_bus(struct pci_bus *b);
208 198
199extern void pcibios_resource_survey(void);
200
209extern struct pci_controller *init_phb_dynamic(struct device_node *dn); 201extern struct pci_controller *init_phb_dynamic(struct device_node *dn);
210 202
211extern struct pci_dev *of_create_pci_dev(struct device_node *node, 203extern struct pci_dev *of_create_pci_dev(struct device_node *node,
@@ -229,5 +221,8 @@ extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
229 const struct resource *rsrc, 221 const struct resource *rsrc,
230 resource_size_t *start, resource_size_t *end); 222 resource_size_t *start, resource_size_t *end);
231 223
224extern void pcibios_do_bus_setup(struct pci_bus *bus);
225extern void pcibios_fixup_of_probed_bus(struct pci_bus *bus);
226
232#endif /* __KERNEL__ */ 227#endif /* __KERNEL__ */
233#endif /* __ASM_POWERPC_PCI_H */ 228#endif /* __ASM_POWERPC_PCI_H */
diff --git a/include/asm-powerpc/pgalloc-64.h b/include/asm-powerpc/pgalloc-64.h
index 94d0294341d..43214c8085b 100644
--- a/include/asm-powerpc/pgalloc-64.h
+++ b/include/asm-powerpc/pgalloc-64.h
@@ -12,6 +12,10 @@
12#include <linux/cpumask.h> 12#include <linux/cpumask.h>
13#include <linux/percpu.h> 13#include <linux/percpu.h>
14 14
15#ifndef CONFIG_PPC_SUBPAGE_PROT
16static inline void subpage_prot_free(pgd_t *pgd) {}
17#endif
18
15extern struct kmem_cache *pgtable_cache[]; 19extern struct kmem_cache *pgtable_cache[];
16 20
17#define PGD_CACHE_NUM 0 21#define PGD_CACHE_NUM 0
@@ -27,6 +31,7 @@ static inline pgd_t *pgd_alloc(struct mm_struct *mm)
27 31
28static inline void pgd_free(pgd_t *pgd) 32static inline void pgd_free(pgd_t *pgd)
29{ 33{
34 subpage_prot_free(pgd);
30 kmem_cache_free(pgtable_cache[PGD_CACHE_NUM], pgd); 35 kmem_cache_free(pgtable_cache[PGD_CACHE_NUM], pgd);
31} 36}
32 37
diff --git a/include/asm-powerpc/pgtable-64k.h b/include/asm-powerpc/pgtable-64k.h
index bd54b772fbc..1cbd6b377ee 100644
--- a/include/asm-powerpc/pgtable-64k.h
+++ b/include/asm-powerpc/pgtable-64k.h
@@ -13,12 +13,49 @@
13#define PTE_TABLE_SIZE (sizeof(real_pte_t) << PTE_INDEX_SIZE) 13#define PTE_TABLE_SIZE (sizeof(real_pte_t) << PTE_INDEX_SIZE)
14#define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE) 14#define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE)
15#define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE) 15#define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE)
16#endif /* __ASSEMBLY__ */
17 16
18#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 17#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
19#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) 18#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
20#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 19#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
21 20
21#ifdef CONFIG_PPC_SUBPAGE_PROT
22/*
23 * For the sub-page protection option, we extend the PGD with one of
24 * these. Basically we have a 3-level tree, with the top level being
25 * the protptrs array. To optimize speed and memory consumption when
26 * only addresses < 4GB are being protected, pointers to the first
27 * four pages of sub-page protection words are stored in the low_prot
28 * array.
29 * Each page of sub-page protection words protects 1GB (4 bytes
30 * protects 64k). For the 3-level tree, each page of pointers then
31 * protects 8TB.
32 */
33struct subpage_prot_table {
34 unsigned long maxaddr; /* only addresses < this are protected */
35 unsigned int **protptrs[2];
36 unsigned int *low_prot[4];
37};
38
39#undef PGD_TABLE_SIZE
40#define PGD_TABLE_SIZE ((sizeof(pgd_t) << PGD_INDEX_SIZE) + \
41 sizeof(struct subpage_prot_table))
42
43#define SBP_L1_BITS (PAGE_SHIFT - 2)
44#define SBP_L2_BITS (PAGE_SHIFT - 3)
45#define SBP_L1_COUNT (1 << SBP_L1_BITS)
46#define SBP_L2_COUNT (1 << SBP_L2_BITS)
47#define SBP_L2_SHIFT (PAGE_SHIFT + SBP_L1_BITS)
48#define SBP_L3_SHIFT (SBP_L2_SHIFT + SBP_L2_BITS)
49
50extern void subpage_prot_free(pgd_t *pgd);
51
52static inline struct subpage_prot_table *pgd_subpage_prot(pgd_t *pgd)
53{
54 return (struct subpage_prot_table *)(pgd + PTRS_PER_PGD);
55}
56#endif /* CONFIG_PPC_SUBPAGE_PROT */
57#endif /* __ASSEMBLY__ */
58
22/* With 4k base page size, hugepage PTEs go at the PMD level */ 59/* With 4k base page size, hugepage PTEs go at the PMD level */
23#define MIN_HUGEPTE_SHIFT PAGE_SHIFT 60#define MIN_HUGEPTE_SHIFT PAGE_SHIFT
24 61
diff --git a/include/asm-powerpc/ppc-pci.h b/include/asm-powerpc/ppc-pci.h
index b847aa10074..854ab713f56 100644
--- a/include/asm-powerpc/ppc-pci.h
+++ b/include/asm-powerpc/ppc-pci.h
@@ -22,7 +22,6 @@ extern void pci_setup_phb_io_dynamic(struct pci_controller *hose, int primary);
22 22
23 23
24extern struct list_head hose_list; 24extern struct list_head hose_list;
25extern int global_phb_number;
26 25
27extern void find_and_init_phbs(void); 26extern void find_and_init_phbs(void);
28 27
@@ -47,9 +46,6 @@ extern void init_pci_config_tokens (void);
47extern unsigned long get_phb_buid (struct device_node *); 46extern unsigned long get_phb_buid (struct device_node *);
48extern int rtas_setup_phb(struct pci_controller *phb); 47extern int rtas_setup_phb(struct pci_controller *phb);
49 48
50/* From iSeries PCI */
51extern void iSeries_pcibios_init(void);
52
53extern unsigned long pci_probe_only; 49extern unsigned long pci_probe_only;
54 50
55/* ---- EEH internal-use-only related routines ---- */ 51/* ---- EEH internal-use-only related routines ---- */
diff --git a/include/asm-powerpc/prom.h b/include/asm-powerpc/prom.h
index 925e2d384bb..78b7b0d494c 100644
--- a/include/asm-powerpc/prom.h
+++ b/include/asm-powerpc/prom.h
@@ -202,6 +202,10 @@ static inline unsigned long of_read_ulong(const u32 *cell, int size)
202 */ 202 */
203extern u64 of_translate_address(struct device_node *np, const u32 *addr); 203extern u64 of_translate_address(struct device_node *np, const u32 *addr);
204 204
205/* Translate a DMA address from device space to CPU space */
206extern u64 of_translate_dma_address(struct device_node *dev,
207 const u32 *in_addr);
208
205/* Extract an address from a device, returns the region size and 209/* Extract an address from a device, returns the region size and
206 * the address space flags too. The PCI version uses a BAR number 210 * the address space flags too. The PCI version uses a BAR number
207 * instead of an absolute index 211 * instead of an absolute index
diff --git a/include/asm-powerpc/ps3.h b/include/asm-powerpc/ps3.h
index f577a16c672..2b693673eff 100644
--- a/include/asm-powerpc/ps3.h
+++ b/include/asm-powerpc/ps3.h
@@ -24,6 +24,7 @@
24#include <linux/init.h> 24#include <linux/init.h>
25#include <linux/types.h> 25#include <linux/types.h>
26#include <linux/device.h> 26#include <linux/device.h>
27#include "cell-pmu.h"
27 28
28union ps3_firmware_version { 29union ps3_firmware_version {
29 u64 raw; 30 u64 raw;
@@ -317,6 +318,7 @@ enum ps3_match_id {
317 PS3_MATCH_ID_STOR_FLASH = 8, 318 PS3_MATCH_ID_STOR_FLASH = 8,
318 PS3_MATCH_ID_SOUND = 9, 319 PS3_MATCH_ID_SOUND = 9,
319 PS3_MATCH_ID_GRAPHICS = 10, 320 PS3_MATCH_ID_GRAPHICS = 10,
321 PS3_MATCH_ID_LPM = 11,
320}; 322};
321 323
322#define PS3_MODULE_ALIAS_EHCI "ps3:1" 324#define PS3_MODULE_ALIAS_EHCI "ps3:1"
@@ -329,11 +331,13 @@ enum ps3_match_id {
329#define PS3_MODULE_ALIAS_STOR_FLASH "ps3:8" 331#define PS3_MODULE_ALIAS_STOR_FLASH "ps3:8"
330#define PS3_MODULE_ALIAS_SOUND "ps3:9" 332#define PS3_MODULE_ALIAS_SOUND "ps3:9"
331#define PS3_MODULE_ALIAS_GRAPHICS "ps3:10" 333#define PS3_MODULE_ALIAS_GRAPHICS "ps3:10"
334#define PS3_MODULE_ALIAS_LPM "ps3:11"
332 335
333enum ps3_system_bus_device_type { 336enum ps3_system_bus_device_type {
334 PS3_DEVICE_TYPE_IOC0 = 1, 337 PS3_DEVICE_TYPE_IOC0 = 1,
335 PS3_DEVICE_TYPE_SB, 338 PS3_DEVICE_TYPE_SB,
336 PS3_DEVICE_TYPE_VUART, 339 PS3_DEVICE_TYPE_VUART,
340 PS3_DEVICE_TYPE_LPM,
337}; 341};
338 342
339/** 343/**
@@ -344,12 +348,17 @@ struct ps3_system_bus_device {
344 enum ps3_match_id match_id; 348 enum ps3_match_id match_id;
345 enum ps3_system_bus_device_type dev_type; 349 enum ps3_system_bus_device_type dev_type;
346 350
347 unsigned int bus_id; /* SB */ 351 u64 bus_id; /* SB */
348 unsigned int dev_id; /* SB */ 352 u64 dev_id; /* SB */
349 unsigned int interrupt_id; /* SB */ 353 unsigned int interrupt_id; /* SB */
350 struct ps3_dma_region *d_region; /* SB, IOC0 */ 354 struct ps3_dma_region *d_region; /* SB, IOC0 */
351 struct ps3_mmio_region *m_region; /* SB, IOC0*/ 355 struct ps3_mmio_region *m_region; /* SB, IOC0*/
352 unsigned int port_number; /* VUART */ 356 unsigned int port_number; /* VUART */
357 struct { /* LPM */
358 u64 node_id;
359 u64 pu_id;
360 u64 rights;
361 } lpm;
353 362
354/* struct iommu_table *iommu_table; -- waiting for BenH's cleanups */ 363/* struct iommu_table *iommu_table; -- waiting for BenH's cleanups */
355 struct device core; 364 struct device core;
@@ -438,5 +447,66 @@ struct ps3_prealloc {
438extern struct ps3_prealloc ps3fb_videomemory; 447extern struct ps3_prealloc ps3fb_videomemory;
439extern struct ps3_prealloc ps3flash_bounce_buffer; 448extern struct ps3_prealloc ps3flash_bounce_buffer;
440 449
450/* logical performance monitor */
451
452/**
453 * enum ps3_lpm_rights - Rigths granted by the system policy module.
454 *
455 * @PS3_LPM_RIGHTS_USE_LPM: The right to use the lpm.
456 * @PS3_LPM_RIGHTS_USE_TB: The right to use the internal trace buffer.
457 */
458
459enum ps3_lpm_rights {
460 PS3_LPM_RIGHTS_USE_LPM = 0x001,
461 PS3_LPM_RIGHTS_USE_TB = 0x100,
462};
463
464/**
465 * enum ps3_lpm_tb_type - Type of trace buffer lv1 should use.
466 *
467 * @PS3_LPM_TB_TYPE_NONE: Do not use a trace buffer.
468 * @PS3_LPM_RIGHTS_USE_TB: Use the lv1 internal trace buffer. Must have
469 * rights @PS3_LPM_RIGHTS_USE_TB.
470 */
471
472enum ps3_lpm_tb_type {
473 PS3_LPM_TB_TYPE_NONE = 0,
474 PS3_LPM_TB_TYPE_INTERNAL = 1,
475};
476
477int ps3_lpm_open(enum ps3_lpm_tb_type tb_type, void *tb_cache,
478 u64 tb_cache_size);
479int ps3_lpm_close(void);
480int ps3_lpm_copy_tb(unsigned long offset, void *buf, unsigned long count,
481 unsigned long *bytes_copied);
482int ps3_lpm_copy_tb_to_user(unsigned long offset, void __user *buf,
483 unsigned long count, unsigned long *bytes_copied);
484void ps3_set_bookmark(u64 bookmark);
485void ps3_set_pm_bookmark(u64 tag, u64 incident, u64 th_id);
486int ps3_set_signal(u64 rtas_signal_group, u8 signal_bit, u16 sub_unit,
487 u8 bus_word);
488
489u32 ps3_read_phys_ctr(u32 cpu, u32 phys_ctr);
490void ps3_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val);
491u32 ps3_read_ctr(u32 cpu, u32 ctr);
492void ps3_write_ctr(u32 cpu, u32 ctr, u32 val);
493
494u32 ps3_read_pm07_control(u32 cpu, u32 ctr);
495void ps3_write_pm07_control(u32 cpu, u32 ctr, u32 val);
496u32 ps3_read_pm(u32 cpu, enum pm_reg_name reg);
497void ps3_write_pm(u32 cpu, enum pm_reg_name reg, u32 val);
498
499u32 ps3_get_ctr_size(u32 cpu, u32 phys_ctr);
500void ps3_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size);
501
502void ps3_enable_pm(u32 cpu);
503void ps3_disable_pm(u32 cpu);
504void ps3_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask);
505void ps3_disable_pm_interrupts(u32 cpu);
506
507u32 ps3_get_and_clear_pm_interrupts(u32 cpu);
508void ps3_sync_irq(int node);
509u32 ps3_get_hw_thread_id(int cpu);
510u64 ps3_get_spe_id(void *arg);
441 511
442#endif 512#endif
diff --git a/include/asm-powerpc/ptrace.h b/include/asm-powerpc/ptrace.h
index 3063363f679..ffc150f602b 100644
--- a/include/asm-powerpc/ptrace.h
+++ b/include/asm-powerpc/ptrace.h
@@ -106,7 +106,8 @@ extern int ptrace_put_reg(struct task_struct *task, int regno,
106 */ 106 */
107#define FULL_REGS(regs) (((regs)->trap & 1) == 0) 107#define FULL_REGS(regs) (((regs)->trap & 1) == 0)
108#ifndef __powerpc64__ 108#ifndef __powerpc64__
109#define IS_CRITICAL_EXC(regs) (((regs)->trap & 2) == 0) 109#define IS_CRITICAL_EXC(regs) (((regs)->trap & 2) != 0)
110#define IS_MCHECK_EXC(regs) (((regs)->trap & 4) != 0)
110#endif /* ! __powerpc64__ */ 111#endif /* ! __powerpc64__ */
111#define TRAP(regs) ((regs)->trap & ~0xF) 112#define TRAP(regs) ((regs)->trap & ~0xF)
112#ifdef __powerpc64__ 113#ifdef __powerpc64__
diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h
index 0dabe46a29d..430dc77b35f 100644
--- a/include/asm-powerpc/qe.h
+++ b/include/asm-powerpc/qe.h
@@ -28,6 +28,52 @@
28#define MEM_PART_SECONDARY 1 28#define MEM_PART_SECONDARY 1
29#define MEM_PART_MURAM 2 29#define MEM_PART_MURAM 2
30 30
31/* Clocks and BRGs */
32enum qe_clock {
33 QE_CLK_NONE = 0,
34 QE_BRG1, /* Baud Rate Generator 1 */
35 QE_BRG2, /* Baud Rate Generator 2 */
36 QE_BRG3, /* Baud Rate Generator 3 */
37 QE_BRG4, /* Baud Rate Generator 4 */
38 QE_BRG5, /* Baud Rate Generator 5 */
39 QE_BRG6, /* Baud Rate Generator 6 */
40 QE_BRG7, /* Baud Rate Generator 7 */
41 QE_BRG8, /* Baud Rate Generator 8 */
42 QE_BRG9, /* Baud Rate Generator 9 */
43 QE_BRG10, /* Baud Rate Generator 10 */
44 QE_BRG11, /* Baud Rate Generator 11 */
45 QE_BRG12, /* Baud Rate Generator 12 */
46 QE_BRG13, /* Baud Rate Generator 13 */
47 QE_BRG14, /* Baud Rate Generator 14 */
48 QE_BRG15, /* Baud Rate Generator 15 */
49 QE_BRG16, /* Baud Rate Generator 16 */
50 QE_CLK1, /* Clock 1 */
51 QE_CLK2, /* Clock 2 */
52 QE_CLK3, /* Clock 3 */
53 QE_CLK4, /* Clock 4 */
54 QE_CLK5, /* Clock 5 */
55 QE_CLK6, /* Clock 6 */
56 QE_CLK7, /* Clock 7 */
57 QE_CLK8, /* Clock 8 */
58 QE_CLK9, /* Clock 9 */
59 QE_CLK10, /* Clock 10 */
60 QE_CLK11, /* Clock 11 */
61 QE_CLK12, /* Clock 12 */
62 QE_CLK13, /* Clock 13 */
63 QE_CLK14, /* Clock 14 */
64 QE_CLK15, /* Clock 15 */
65 QE_CLK16, /* Clock 16 */
66 QE_CLK17, /* Clock 17 */
67 QE_CLK18, /* Clock 18 */
68 QE_CLK19, /* Clock 19 */
69 QE_CLK20, /* Clock 20 */
70 QE_CLK21, /* Clock 21 */
71 QE_CLK22, /* Clock 22 */
72 QE_CLK23, /* Clock 23 */
73 QE_CLK24, /* Clock 24 */
74 QE_CLK_DUMMY
75};
76
31/* Export QE common operations */ 77/* Export QE common operations */
32extern void qe_reset(void); 78extern void qe_reset(void);
33extern int par_io_init(struct device_node *np); 79extern int par_io_init(struct device_node *np);
@@ -38,7 +84,8 @@ extern int par_io_data_set(u8 port, u8 pin, u8 val);
38 84
39/* QE internal API */ 85/* QE internal API */
40int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input); 86int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
41void qe_setbrg(unsigned int brg, unsigned int rate, unsigned int multiplier); 87enum qe_clock qe_clock_source(const char *source);
88int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
42int qe_get_snum(void); 89int qe_get_snum(void);
43void qe_put_snum(u8 snum); 90void qe_put_snum(u8 snum);
44unsigned long qe_muram_alloc(int size, int align); 91unsigned long qe_muram_alloc(int size, int align);
@@ -47,6 +94,58 @@ unsigned long qe_muram_alloc_fixed(unsigned long offset, int size);
47void qe_muram_dump(void); 94void qe_muram_dump(void);
48void *qe_muram_addr(unsigned long offset); 95void *qe_muram_addr(unsigned long offset);
49 96
97/* Structure that defines QE firmware binary files.
98 *
99 * See Documentation/powerpc/qe-firmware.txt for a description of these
100 * fields.
101 */
102struct qe_firmware {
103 struct qe_header {
104 __be32 length; /* Length of the entire structure, in bytes */
105 u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */
106 u8 version; /* Version of this layout. First ver is '1' */
107 } header;
108 u8 id[62]; /* Null-terminated identifier string */
109 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
110 u8 count; /* Number of microcode[] structures */
111 struct {
112 __be16 model; /* The SOC model */
113 u8 major; /* The SOC revision major */
114 u8 minor; /* The SOC revision minor */
115 } __attribute__ ((packed)) soc;
116 u8 padding[4]; /* Reserved, for alignment */
117 __be64 extended_modes; /* Extended modes */
118 __be32 vtraps[8]; /* Virtual trap addresses */
119 u8 reserved[4]; /* Reserved, for future expansion */
120 struct qe_microcode {
121 u8 id[32]; /* Null-terminated identifier */
122 __be32 traps[16]; /* Trap addresses, 0 == ignore */
123 __be32 eccr; /* The value for the ECCR register */
124 __be32 iram_offset; /* Offset into I-RAM for the code */
125 __be32 count; /* Number of 32-bit words of the code */
126 __be32 code_offset; /* Offset of the actual microcode */
127 u8 major; /* The microcode version major */
128 u8 minor; /* The microcode version minor */
129 u8 revision; /* The microcode version revision */
130 u8 padding; /* Reserved, for alignment */
131 u8 reserved[4]; /* Reserved, for future expansion */
132 } __attribute__ ((packed)) microcode[1];
133 /* All microcode binaries should be located here */
134 /* CRC32 should be located here, after the microcode binaries */
135} __attribute__ ((packed));
136
137struct qe_firmware_info {
138 char id[64]; /* Firmware name */
139 u32 vtraps[8]; /* Virtual trap addresses */
140 u64 extended_modes; /* Extended modes */
141};
142
143/* Upload a firmware to the QE */
144int qe_upload_firmware(const struct qe_firmware *firmware);
145
146/* Obtain information on the uploaded firmware */
147struct qe_firmware_info *qe_get_firmware_info(void);
148
50/* Buffer descriptors */ 149/* Buffer descriptors */
51struct qe_bd { 150struct qe_bd {
52 __be16 status; 151 __be16 status;
@@ -129,52 +228,6 @@ enum comm_dir {
129 COMM_DIR_RX_AND_TX = 3 228 COMM_DIR_RX_AND_TX = 3
130}; 229};
131 230
132/* Clocks and BRGs */
133enum qe_clock {
134 QE_CLK_NONE = 0,
135 QE_BRG1, /* Baud Rate Generator 1 */
136 QE_BRG2, /* Baud Rate Generator 2 */
137 QE_BRG3, /* Baud Rate Generator 3 */
138 QE_BRG4, /* Baud Rate Generator 4 */
139 QE_BRG5, /* Baud Rate Generator 5 */
140 QE_BRG6, /* Baud Rate Generator 6 */
141 QE_BRG7, /* Baud Rate Generator 7 */
142 QE_BRG8, /* Baud Rate Generator 8 */
143 QE_BRG9, /* Baud Rate Generator 9 */
144 QE_BRG10, /* Baud Rate Generator 10 */
145 QE_BRG11, /* Baud Rate Generator 11 */
146 QE_BRG12, /* Baud Rate Generator 12 */
147 QE_BRG13, /* Baud Rate Generator 13 */
148 QE_BRG14, /* Baud Rate Generator 14 */
149 QE_BRG15, /* Baud Rate Generator 15 */
150 QE_BRG16, /* Baud Rate Generator 16 */
151 QE_CLK1, /* Clock 1 */
152 QE_CLK2, /* Clock 2 */
153 QE_CLK3, /* Clock 3 */
154 QE_CLK4, /* Clock 4 */
155 QE_CLK5, /* Clock 5 */
156 QE_CLK6, /* Clock 6 */
157 QE_CLK7, /* Clock 7 */
158 QE_CLK8, /* Clock 8 */
159 QE_CLK9, /* Clock 9 */
160 QE_CLK10, /* Clock 10 */
161 QE_CLK11, /* Clock 11 */
162 QE_CLK12, /* Clock 12 */
163 QE_CLK13, /* Clock 13 */
164 QE_CLK14, /* Clock 14 */
165 QE_CLK15, /* Clock 15 */
166 QE_CLK16, /* Clock 16 */
167 QE_CLK17, /* Clock 17 */
168 QE_CLK18, /* Clock 18 */
169 QE_CLK19, /* Clock 19 */
170 QE_CLK20, /* Clock 20 */
171 QE_CLK21, /* Clock 21 */
172 QE_CLK22, /* Clock 22 */
173 QE_CLK23, /* Clock 23 */
174 QE_CLK24, /* Clock 24 */
175 QE_CLK_DUMMY,
176};
177
178/* QE CMXUCR Registers. 231/* QE CMXUCR Registers.
179 * There are two UCCs represented in each of the four CMXUCR registers. 232 * There are two UCCs represented in each of the four CMXUCR registers.
180 * These values are for the UCC in the LSBs 233 * These values are for the UCC in the LSBs
@@ -328,6 +381,15 @@ enum qe_clock {
328 381
329#define QE_SDEBCR_BA_MASK 0x01FFFFFF 382#define QE_SDEBCR_BA_MASK 0x01FFFFFF
330 383
384/* Communication Processor */
385#define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */
386#define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */
387#define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */
388
389/* I-RAM */
390#define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */
391#define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */
392
331/* UPC */ 393/* UPC */
332#define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */ 394#define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */
333#define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */ 395#define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */
diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h
index e775ff1ca41..2408a29507e 100644
--- a/include/asm-powerpc/reg.h
+++ b/include/asm-powerpc/reg.h
@@ -553,6 +553,7 @@
553#define SPRN_PA6T_BTCR 978 /* Breakpoint and Tagging Control Register */ 553#define SPRN_PA6T_BTCR 978 /* Breakpoint and Tagging Control Register */
554#define SPRN_PA6T_IMAAT 979 /* Instruction Match Array Action Table */ 554#define SPRN_PA6T_IMAAT 979 /* Instruction Match Array Action Table */
555#define SPRN_PA6T_PCCR 1019 /* Power Counter Control Register */ 555#define SPRN_PA6T_PCCR 1019 /* Power Counter Control Register */
556#define SPRN_BKMK 1020 /* Cell Bookmark Register */
556#define SPRN_PA6T_RPCCR 1021 /* Retire PC Trace Control Register */ 557#define SPRN_PA6T_RPCCR 1021 /* Retire PC Trace Control Register */
557 558
558 559
@@ -691,12 +692,6 @@
691#define PV_BE 0x0070 692#define PV_BE 0x0070
692#define PV_PA6T 0x0090 693#define PV_PA6T 0x0090
693 694
694/*
695 * Number of entries in the SLB. If this ever changes we should handle
696 * it with a use a cpu feature fixup.
697 */
698#define SLB_NUM_ENTRIES 64
699
700/* Macros for setting and retrieving special purpose registers */ 695/* Macros for setting and retrieving special purpose registers */
701#ifndef __ASSEMBLY__ 696#ifndef __ASSEMBLY__
702#define mfmsr() ({unsigned long rval; \ 697#define mfmsr() ({unsigned long rval; \
diff --git a/include/asm-powerpc/reg_booke.h b/include/asm-powerpc/reg_booke.h
index 8fdc2b47afb..0405ef47981 100644
--- a/include/asm-powerpc/reg_booke.h
+++ b/include/asm-powerpc/reg_booke.h
@@ -123,16 +123,23 @@
123#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */ 123#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
124#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ 124#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
125#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ 125#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
126#define SPRN_ATB 0x20E /* Alternate Time Base */
127#define SPRN_ATBL 0x20E /* Alternate Time Base Lower */
128#define SPRN_ATBU 0x20F /* Alternate Time Base Upper */
126#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */ 129#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
127#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */ 130#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
128#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */ 131#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */
129#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */ 132#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
133#define SPRN_IVOR36 0x214 /* Interrupt Vector Offset Register 36 */
134#define SPRN_IVOR37 0x215 /* Interrupt Vector Offset Register 37 */
130#define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */ 135#define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */
131#define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */ 136#define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */
132#define SPRN_MCSR 0x23C /* Machine Check Status Register */ 137#define SPRN_MCSR 0x23C /* Machine Check Status Register */
133#define SPRN_MCAR 0x23D /* Machine Check Address Register */ 138#define SPRN_MCAR 0x23D /* Machine Check Address Register */
134#define SPRN_DSRR0 0x23E /* Debug Save and Restore Register 0 */ 139#define SPRN_DSRR0 0x23E /* Debug Save and Restore Register 0 */
135#define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */ 140#define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */
141#define SPRN_SPRG8 0x25C /* Special Purpose Register General 8 */
142#define SPRN_SPRG9 0x25D /* Special Purpose Register General 9 */
136#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ 143#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
137#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ 144#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
138#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ 145#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
@@ -140,15 +147,18 @@
140#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */ 147#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
141#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */ 148#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */
142#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ 149#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
143#define SPRN_MAS7 0x3b0 /* MMU Assist Register 7 */
144#define SPRN_PID1 0x279 /* Process ID Register 1 */ 150#define SPRN_PID1 0x279 /* Process ID Register 1 */
145#define SPRN_PID2 0x27A /* Process ID Register 2 */ 151#define SPRN_PID2 0x27A /* Process ID Register 2 */
146#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */ 152#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
147#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */ 153#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */
154#define SPRN_EPR 0x2BE /* External Proxy Register */
148#define SPRN_CCR1 0x378 /* Core Configuration Register 1 */ 155#define SPRN_CCR1 0x378 /* Core Configuration Register 1 */
149#define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */ 156#define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */
157#define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */
150#define SPRN_MMUCR 0x3B2 /* MMU Control Register */ 158#define SPRN_MMUCR 0x3B2 /* MMU Control Register */
151#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */ 159#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */
160#define SPRN_EPLC 0x3B3 /* External Process ID Load Context */
161#define SPRN_EPSC 0x3B4 /* External Process ID Store Context */
152#define SPRN_SGR 0x3B9 /* Storage Guarded Register */ 162#define SPRN_SGR 0x3B9 /* Storage Guarded Register */
153#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ 163#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
154#define SPRN_SLER 0x3BB /* Little-endian real mode */ 164#define SPRN_SLER 0x3BB /* Little-endian real mode */
@@ -159,6 +169,7 @@
159#define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */ 169#define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */
160#define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */ 170#define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */
161#define SPRN_PIT 0x3DB /* Programmable Interval Timer */ 171#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
172#define SPRN_BUCSR 0x3F5 /* Branch Unit Control and Status */
162#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ 173#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
163#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ 174#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
164#define SPRN_SVR 0x3FF /* System Version Register */ 175#define SPRN_SVR 0x3FF /* System Version Register */
@@ -207,7 +218,6 @@
207#define CCR1_TCS 0x00000080 /* Timer Clock Select */ 218#define CCR1_TCS 0x00000080 /* Timer Clock Select */
208 219
209/* Bit definitions for the MCSR. */ 220/* Bit definitions for the MCSR. */
210#ifdef CONFIG_440A
211#define MCSR_MCS 0x80000000 /* Machine Check Summary */ 221#define MCSR_MCS 0x80000000 /* Machine Check Summary */
212#define MCSR_IB 0x40000000 /* Instruction PLB Error */ 222#define MCSR_IB 0x40000000 /* Instruction PLB Error */
213#define MCSR_DRB 0x20000000 /* Data Read PLB Error */ 223#define MCSR_DRB 0x20000000 /* Data Read PLB Error */
@@ -217,7 +227,7 @@
217#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */ 227#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
218#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */ 228#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
219#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */ 229#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
220#endif 230
221#ifdef CONFIG_E500 231#ifdef CONFIG_E500
222#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */ 232#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */
223#define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */ 233#define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */
@@ -293,7 +303,7 @@
293#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ 303#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
294#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ 304#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
295#define ESR_PIL 0x08000000 /* Program Exception - Illegal */ 305#define ESR_PIL 0x08000000 /* Program Exception - Illegal */
296#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */ 306#define ESR_PPR 0x04000000 /* Program Exception - Privileged */
297#define ESR_PTR 0x02000000 /* Program Exception - Trap */ 307#define ESR_PTR 0x02000000 /* Program Exception - Trap */
298#define ESR_FP 0x01000000 /* Floating Point Operation */ 308#define ESR_FP 0x01000000 /* Floating Point Operation */
299#define ESR_DST 0x00800000 /* Storage Exception - Data miss */ 309#define ESR_DST 0x00800000 /* Storage Exception - Data miss */
diff --git a/include/asm-powerpc/setjmp.h b/include/asm-powerpc/setjmp.h
new file mode 100644
index 00000000000..279d03a1eec
--- /dev/null
+++ b/include/asm-powerpc/setjmp.h
@@ -0,0 +1,18 @@
1/*
2 * Copyright © 2008 Michael Neuling IBM Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 */
10#ifndef _ASM_POWERPC_SETJMP_H
11#define _ASM_POWERPC_SETJMP_H
12
13#define JMP_BUF_LEN 23
14
15extern long setjmp(long *);
16extern void longjmp(long *, long);
17
18#endif /* _ASM_POWERPC_SETJMP_H */
diff --git a/include/asm-powerpc/smu.h b/include/asm-powerpc/smu.h
index e49f644ca63..7ae2753da56 100644
--- a/include/asm-powerpc/smu.h
+++ b/include/asm-powerpc/smu.h
@@ -22,7 +22,7 @@
22 * Partition info commands 22 * Partition info commands
23 * 23 *
24 * These commands are used to retrieve the sdb-partition-XX datas from 24 * These commands are used to retrieve the sdb-partition-XX datas from
25 * the SMU. The lenght is always 2. First byte is the subcommand code 25 * the SMU. The length is always 2. First byte is the subcommand code
26 * and second byte is the partition ID. 26 * and second byte is the partition ID.
27 * 27 *
28 * The reply is 6 bytes: 28 * The reply is 6 bytes:
@@ -173,12 +173,12 @@
173 * Power supply control 173 * Power supply control
174 * 174 *
175 * The "sub" command is an ASCII string in the data, the 175 * The "sub" command is an ASCII string in the data, the
176 * data lenght is that of the string. 176 * data length is that of the string.
177 * 177 *
178 * The VSLEW command can be used to get or set the voltage slewing. 178 * The VSLEW command can be used to get or set the voltage slewing.
179 * - lenght 5 (only "VSLEW") : it returns "DONE" and 3 bytes of 179 * - length 5 (only "VSLEW") : it returns "DONE" and 3 bytes of
180 * reply at data offset 6, 7 and 8. 180 * reply at data offset 6, 7 and 8.
181 * - lenght 8 ("VSLEWxyz") has 3 additional bytes appended, and is 181 * - length 8 ("VSLEWxyz") has 3 additional bytes appended, and is
182 * used to set the voltage slewing point. The SMU replies with "DONE" 182 * used to set the voltage slewing point. The SMU replies with "DONE"
183 * I yet have to figure out their exact meaning of those 3 bytes in 183 * I yet have to figure out their exact meaning of those 3 bytes in
184 * both cases. They seem to be: 184 * both cases. They seem to be:
@@ -201,20 +201,90 @@
201 */ 201 */
202#define SMU_CMD_READ_ADC 0xd8 202#define SMU_CMD_READ_ADC 0xd8
203 203
204
204/* Misc commands 205/* Misc commands
205 * 206 *
206 * This command seem to be a grab bag of various things 207 * This command seem to be a grab bag of various things
208 *
209 * Parameters:
210 * 1: subcommand
207 */ 211 */
208#define SMU_CMD_MISC_df_COMMAND 0xdf 212#define SMU_CMD_MISC_df_COMMAND 0xdf
209#define SMU_CMD_MISC_df_SET_DISPLAY_LIT 0x02 /* i: 1 byte */ 213
214/*
215 * Sets "system ready" status
216 *
217 * I did not yet understand how it exactly works or what it does.
218 *
219 * Guessing from OF code, 0x02 activates the display backlight. Apple uses/used
220 * the same codebase for all OF versions. On PowerBooks, this command would
221 * enable the backlight. For the G5s, it only activates the front LED. However,
222 * don't take this for granted.
223 *
224 * Parameters:
225 * 2: status [0x00, 0x01 or 0x02]
226 */
227#define SMU_CMD_MISC_df_SET_DISPLAY_LIT 0x02
228
229/*
230 * Sets mode of power switch.
231 *
232 * What this actually does is not yet known. Maybe it enables some interrupt.
233 *
234 * Parameters:
235 * 2: enable power switch? [0x00 or 0x01]
236 * 3 (optional): enable nmi? [0x00 or 0x01]
237 *
238 * Returns:
239 * If parameter 2 is 0x00 and parameter 3 is not specified, returns wether
240 * NMI is enabled. Otherwise unknown.
241 */
210#define SMU_CMD_MISC_df_NMI_OPTION 0x04 242#define SMU_CMD_MISC_df_NMI_OPTION 0x04
211 243
244/* Sets LED dimm offset.
245 *
246 * The front LED dimms itself during sleep. Its brightness (or, well, the PWM
247 * frequency) depends on current time. Therefore, the SMU needs to know the
248 * timezone.
249 *
250 * Parameters:
251 * 2-8: unknown (BCD coding)
252 */
253#define SMU_CMD_MISC_df_DIMM_OFFSET 0x99
254
255
212/* 256/*
213 * Version info commands 257 * Version info commands
214 * 258 *
215 * I haven't quite tried to figure out how these work 259 * Parameters:
260 * 1 (optional): Specifies version part to retrieve
261 *
262 * Returns:
263 * Version value
216 */ 264 */
217#define SMU_CMD_VERSION_COMMAND 0xea 265#define SMU_CMD_VERSION_COMMAND 0xea
266#define SMU_VERSION_RUNNING 0x00
267#define SMU_VERSION_BASE 0x01
268#define SMU_VERSION_UPDATE 0x02
269
270
271/*
272 * Switches
273 *
274 * These are switches whose status seems to be known to the SMU.
275 *
276 * Parameters:
277 * none
278 *
279 * Result:
280 * Switch bits (ORed, see below)
281 */
282#define SMU_CMD_SWITCHES 0xdc
283
284/* Switches bits */
285#define SMU_SWITCH_CASE_CLOSED 0x01
286#define SMU_SWITCH_AC_POWER 0x04
287#define SMU_SWITCH_POWER_SWITCH 0x08
218 288
219 289
220/* 290/*
@@ -243,10 +313,64 @@
243 */ 313 */
244#define SMU_CMD_MISC_ee_COMMAND 0xee 314#define SMU_CMD_MISC_ee_COMMAND 0xee
245#define SMU_CMD_MISC_ee_GET_DATABLOCK_REC 0x02 315#define SMU_CMD_MISC_ee_GET_DATABLOCK_REC 0x02
246#define SMU_CMD_MISC_ee_LEDS_CTRL 0x04 /* i: 00 (00,01) [00] */ 316
317/* Retrieves currently used watts.
318 *
319 * Parameters:
320 * 1: 0x03 (Meaning unknown)
321 */
322#define SMU_CMD_MISC_ee_GET_WATTS 0x03
323
324#define SMU_CMD_MISC_ee_LEDS_CTRL 0x04 /* i: 00 (00,01) [00] */
247#define SMU_CMD_MISC_ee_GET_DATA 0x05 /* i: 00 , o: ?? */ 325#define SMU_CMD_MISC_ee_GET_DATA 0x05 /* i: 00 , o: ?? */
248 326
249 327
328/*
329 * Power related commands
330 *
331 * Parameters:
332 * 1: subcommand
333 */
334#define SMU_CMD_POWER_EVENTS_COMMAND 0x8f
335
336/* SMU_POWER_EVENTS subcommands */
337enum {
338 SMU_PWR_GET_POWERUP_EVENTS = 0x00,
339 SMU_PWR_SET_POWERUP_EVENTS = 0x01,
340 SMU_PWR_CLR_POWERUP_EVENTS = 0x02,
341 SMU_PWR_GET_WAKEUP_EVENTS = 0x03,
342 SMU_PWR_SET_WAKEUP_EVENTS = 0x04,
343 SMU_PWR_CLR_WAKEUP_EVENTS = 0x05,
344
345 /*
346 * Get last shutdown cause
347 *
348 * Returns:
349 * 1 byte (signed char): Last shutdown cause. Exact meaning unknown.
350 */
351 SMU_PWR_LAST_SHUTDOWN_CAUSE = 0x07,
352
353 /*
354 * Sets or gets server ID. Meaning or use is unknown.
355 *
356 * Parameters:
357 * 2 (optional): Set server ID (1 byte)
358 *
359 * Returns:
360 * 1 byte (server ID?)
361 */
362 SMU_PWR_SERVER_ID = 0x08,
363};
364
365/* Power events wakeup bits */
366enum {
367 SMU_PWR_WAKEUP_KEY = 0x01, /* Wake on key press */
368 SMU_PWR_WAKEUP_AC_INSERT = 0x02, /* Wake on AC adapter plug */
369 SMU_PWR_WAKEUP_AC_CHANGE = 0x04,
370 SMU_PWR_WAKEUP_LID_OPEN = 0x08,
371 SMU_PWR_WAKEUP_RING = 0x10,
372};
373
250 374
251/* 375/*
252 * - Kernel side interface - 376 * - Kernel side interface -
@@ -564,13 +688,13 @@ struct smu_user_cmd_hdr
564 688
565 __u8 cmd; /* SMU command byte */ 689 __u8 cmd; /* SMU command byte */
566 __u8 pad[3]; /* padding */ 690 __u8 pad[3]; /* padding */
567 __u32 data_len; /* Lenght of data following */ 691 __u32 data_len; /* Length of data following */
568}; 692};
569 693
570struct smu_user_reply_hdr 694struct smu_user_reply_hdr
571{ 695{
572 __u32 status; /* Command status */ 696 __u32 status; /* Command status */
573 __u32 reply_len; /* Lenght of data follwing */ 697 __u32 reply_len; /* Length of data follwing */
574}; 698};
575 699
576#endif /* _SMU_H */ 700#endif /* _SMU_H */
diff --git a/include/asm-powerpc/sparsemem.h b/include/asm-powerpc/sparsemem.h
index 48ad807a0b8..e8b493d52b4 100644
--- a/include/asm-powerpc/sparsemem.h
+++ b/include/asm-powerpc/sparsemem.h
@@ -10,13 +10,8 @@
10 */ 10 */
11#define SECTION_SIZE_BITS 24 11#define SECTION_SIZE_BITS 24
12 12
13#if defined(CONFIG_PS3_USE_LPAR_ADDR)
14#define MAX_PHYSADDR_BITS 47
15#define MAX_PHYSMEM_BITS 47
16#else
17#define MAX_PHYSADDR_BITS 44 13#define MAX_PHYSADDR_BITS 44
18#define MAX_PHYSMEM_BITS 44 14#define MAX_PHYSMEM_BITS 44
19#endif
20 15
21#ifdef CONFIG_MEMORY_HOTPLUG 16#ifdef CONFIG_MEMORY_HOTPLUG
22extern void create_section_mapping(unsigned long start, unsigned long end); 17extern void create_section_mapping(unsigned long start, unsigned long end);
diff --git a/include/asm-powerpc/spu.h b/include/asm-powerpc/spu.h
index 34b7807f068..f07c99ba5d1 100644
--- a/include/asm-powerpc/spu.h
+++ b/include/asm-powerpc/spu.h
@@ -104,6 +104,7 @@
104 104
105struct spu_context; 105struct spu_context;
106struct spu_runqueue; 106struct spu_runqueue;
107struct spu_lscsa;
107struct device_node; 108struct device_node;
108 109
109enum spu_utilization_state { 110enum spu_utilization_state {
@@ -145,7 +146,6 @@ struct spu {
145 void (* ibox_callback)(struct spu *spu); 146 void (* ibox_callback)(struct spu *spu);
146 void (* stop_callback)(struct spu *spu); 147 void (* stop_callback)(struct spu *spu);
147 void (* mfc_callback)(struct spu *spu); 148 void (* mfc_callback)(struct spu *spu);
148 void (* dma_callback)(struct spu *spu, int type);
149 149
150 char irq_c0[8]; 150 char irq_c0[8];
151 char irq_c1[8]; 151 char irq_c1[8];
@@ -196,10 +196,11 @@ struct cbe_spu_info {
196extern struct cbe_spu_info cbe_spu_info[]; 196extern struct cbe_spu_info cbe_spu_info[];
197 197
198void spu_init_channels(struct spu *spu); 198void spu_init_channels(struct spu *spu);
199int spu_irq_class_0_bottom(struct spu *spu);
200int spu_irq_class_1_bottom(struct spu *spu);
201void spu_irq_setaffinity(struct spu *spu, int cpu); 199void spu_irq_setaffinity(struct spu *spu, int cpu);
202 200
201void spu_setup_kernel_slbs(struct spu *spu, struct spu_lscsa *lscsa,
202 void *code, int code_size);
203
203#ifdef CONFIG_KEXEC 204#ifdef CONFIG_KEXEC
204void crash_register_spus(struct list_head *list); 205void crash_register_spus(struct list_head *list);
205#else 206#else
@@ -210,6 +211,7 @@ static inline void crash_register_spus(struct list_head *list)
210 211
211extern void spu_invalidate_slbs(struct spu *spu); 212extern void spu_invalidate_slbs(struct spu *spu);
212extern void spu_associate_mm(struct spu *spu, struct mm_struct *mm); 213extern void spu_associate_mm(struct spu *spu, struct mm_struct *mm);
214int spu_64k_pages_available(void);
213 215
214/* Calls from the memory management to the SPU */ 216/* Calls from the memory management to the SPU */
215struct mm_struct; 217struct mm_struct;
@@ -279,6 +281,8 @@ void spu_remove_sysdev_attr(struct sysdev_attribute *attr);
279int spu_add_sysdev_attr_group(struct attribute_group *attrs); 281int spu_add_sysdev_attr_group(struct attribute_group *attrs);
280void spu_remove_sysdev_attr_group(struct attribute_group *attrs); 282void spu_remove_sysdev_attr_group(struct attribute_group *attrs);
281 283
284int spu_handle_mm_fault(struct mm_struct *mm, unsigned long ea,
285 unsigned long dsisr, unsigned *flt);
282 286
283/* 287/*
284 * Notifier blocks: 288 * Notifier blocks:
@@ -303,7 +307,7 @@ extern void notify_spus_active(void);
303extern void do_notify_spus_active(void); 307extern void do_notify_spus_active(void);
304 308
305/* 309/*
306 * This defines the Local Store, Problem Area and Privlege Area of an SPU. 310 * This defines the Local Store, Problem Area and Privilege Area of an SPU.
307 */ 311 */
308 312
309union mfc_tag_size_class_cmd { 313union mfc_tag_size_class_cmd {
@@ -524,8 +528,24 @@ struct spu_priv1 {
524#define CLASS2_ENABLE_SPU_STOP_INTR 0x2L 528#define CLASS2_ENABLE_SPU_STOP_INTR 0x2L
525#define CLASS2_ENABLE_SPU_HALT_INTR 0x4L 529#define CLASS2_ENABLE_SPU_HALT_INTR 0x4L
526#define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L 530#define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L
531#define CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR 0x10L
527 u8 pad_0x118_0x140[0x28]; /* 0x118 */ 532 u8 pad_0x118_0x140[0x28]; /* 0x118 */
528 u64 int_stat_RW[3]; /* 0x140 */ 533 u64 int_stat_RW[3]; /* 0x140 */
534#define CLASS0_DMA_ALIGNMENT_INTR 0x1L
535#define CLASS0_INVALID_DMA_COMMAND_INTR 0x2L
536#define CLASS0_SPU_ERROR_INTR 0x4L
537#define CLASS0_INTR_MASK 0x7L
538#define CLASS1_SEGMENT_FAULT_INTR 0x1L
539#define CLASS1_STORAGE_FAULT_INTR 0x2L
540#define CLASS1_LS_COMPARE_SUSPEND_ON_GET_INTR 0x4L
541#define CLASS1_LS_COMPARE_SUSPEND_ON_PUT_INTR 0x8L
542#define CLASS1_INTR_MASK 0xfL
543#define CLASS2_MAILBOX_INTR 0x1L
544#define CLASS2_SPU_STOP_INTR 0x2L
545#define CLASS2_SPU_HALT_INTR 0x4L
546#define CLASS2_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L
547#define CLASS2_MAILBOX_THRESHOLD_INTR 0x10L
548#define CLASS2_INTR_MASK 0x1fL
529 u8 pad_0x158_0x180[0x28]; /* 0x158 */ 549 u8 pad_0x158_0x180[0x28]; /* 0x158 */
530 u64 int_route_RW; /* 0x180 */ 550 u64 int_route_RW; /* 0x180 */
531 551
diff --git a/include/asm-powerpc/spu_csa.h b/include/asm-powerpc/spu_csa.h
index e87794d5d4e..0ab6bff8607 100644
--- a/include/asm-powerpc/spu_csa.h
+++ b/include/asm-powerpc/spu_csa.h
@@ -194,7 +194,7 @@ struct spu_priv1_collapsed {
194}; 194};
195 195
196/* 196/*
197 * struct spu_priv2_collapsed - condensed priviliged 2 area, w/o pads. 197 * struct spu_priv2_collapsed - condensed privileged 2 area, w/o pads.
198 */ 198 */
199struct spu_priv2_collapsed { 199struct spu_priv2_collapsed {
200 u64 slb_index_W; 200 u64 slb_index_W;
@@ -254,20 +254,11 @@ struct spu_state {
254 u64 spu_chnldata_RW[32]; 254 u64 spu_chnldata_RW[32];
255 u32 spu_mailbox_data[4]; 255 u32 spu_mailbox_data[4];
256 u32 pu_mailbox_data[1]; 256 u32 pu_mailbox_data[1];
257 u64 dar, dsisr; 257 u64 dar, dsisr, class_0_pending;
258 unsigned long suspend_time; 258 unsigned long suspend_time;
259 spinlock_t register_lock; 259 spinlock_t register_lock;
260}; 260};
261 261
262extern int spu_init_csa(struct spu_state *csa);
263extern void spu_fini_csa(struct spu_state *csa);
264extern int spu_save(struct spu_state *prev, struct spu *spu);
265extern int spu_restore(struct spu_state *new, struct spu *spu);
266extern int spu_switch(struct spu_state *prev, struct spu_state *new,
267 struct spu *spu);
268extern int spu_alloc_lscsa(struct spu_state *csa);
269extern void spu_free_lscsa(struct spu_state *csa);
270
271#endif /* !__SPU__ */ 262#endif /* !__SPU__ */
272#endif /* __KERNEL__ */ 263#endif /* __KERNEL__ */
273#endif /* !__ASSEMBLY__ */ 264#endif /* !__ASSEMBLY__ */
diff --git a/include/asm-powerpc/spu_priv1.h b/include/asm-powerpc/spu_priv1.h
index 0f37c7c9082..25020a34ce7 100644
--- a/include/asm-powerpc/spu_priv1.h
+++ b/include/asm-powerpc/spu_priv1.h
@@ -24,6 +24,7 @@
24#include <linux/types.h> 24#include <linux/types.h>
25 25
26struct spu; 26struct spu;
27struct spu_context;
27 28
28/* access to priv1 registers */ 29/* access to priv1 registers */
29 30
@@ -178,6 +179,8 @@ struct spu_management_ops {
178 int (*enumerate_spus)(int (*fn)(void *data)); 179 int (*enumerate_spus)(int (*fn)(void *data));
179 int (*create_spu)(struct spu *spu, void *data); 180 int (*create_spu)(struct spu *spu, void *data);
180 int (*destroy_spu)(struct spu *spu); 181 int (*destroy_spu)(struct spu *spu);
182 void (*enable_spu)(struct spu_context *ctx);
183 void (*disable_spu)(struct spu_context *ctx);
181 int (*init_affinity)(void); 184 int (*init_affinity)(void);
182}; 185};
183 186
@@ -207,6 +210,18 @@ spu_init_affinity (void)
207 return spu_management_ops->init_affinity(); 210 return spu_management_ops->init_affinity();
208} 211}
209 212
213static inline void
214spu_enable_spu (struct spu_context *ctx)
215{
216 spu_management_ops->enable_spu(ctx);
217}
218
219static inline void
220spu_disable_spu (struct spu_context *ctx)
221{
222 spu_management_ops->disable_spu(ctx);
223}
224
210/* 225/*
211 * The declarations folowing are put here for convenience 226 * The declarations folowing are put here for convenience
212 * and only intended to be used by the platform setup code. 227 * and only intended to be used by the platform setup code.
diff --git a/include/asm-powerpc/systbl.h b/include/asm-powerpc/systbl.h
index 11d5383b2f0..0c8b0d67913 100644
--- a/include/asm-powerpc/systbl.h
+++ b/include/asm-powerpc/systbl.h
@@ -313,3 +313,4 @@ COMPAT_SYS_SPU(timerfd)
313SYSCALL_SPU(eventfd) 313SYSCALL_SPU(eventfd)
314COMPAT_SYS_SPU(sync_file_range2) 314COMPAT_SYS_SPU(sync_file_range2)
315COMPAT_SYS(fallocate) 315COMPAT_SYS(fallocate)
316SYSCALL(subpage_prot)
diff --git a/include/asm-powerpc/system.h b/include/asm-powerpc/system.h
index 87be8c3bc9c..bc9739dff5e 100644
--- a/include/asm-powerpc/system.h
+++ b/include/asm-powerpc/system.h
@@ -169,6 +169,8 @@ extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
169extern void bad_page_fault(struct pt_regs *, unsigned long, int); 169extern void bad_page_fault(struct pt_regs *, unsigned long, int);
170extern int die(const char *, struct pt_regs *, long); 170extern int die(const char *, struct pt_regs *, long);
171extern void _exception(int, struct pt_regs *, int, unsigned long); 171extern void _exception(int, struct pt_regs *, int, unsigned long);
172extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
173
172#ifdef CONFIG_BOOKE_WDT 174#ifdef CONFIG_BOOKE_WDT
173extern u32 booke_wdt_enabled; 175extern u32 booke_wdt_enabled;
174extern u32 booke_wdt_period; 176extern u32 booke_wdt_period;
diff --git a/include/asm-powerpc/udbg.h b/include/asm-powerpc/udbg.h
index a9e0b0ebcb0..6418ceea44b 100644
--- a/include/asm-powerpc/udbg.h
+++ b/include/asm-powerpc/udbg.h
@@ -48,6 +48,7 @@ extern void __init udbg_init_rtas_console(void);
48extern void __init udbg_init_debug_beat(void); 48extern void __init udbg_init_debug_beat(void);
49extern void __init udbg_init_btext(void); 49extern void __init udbg_init_btext(void);
50extern void __init udbg_init_44x_as1(void); 50extern void __init udbg_init_44x_as1(void);
51extern void __init udbg_init_40x_realmode(void);
51extern void __init udbg_init_cpm(void); 52extern void __init udbg_init_cpm(void);
52 53
53#endif /* __KERNEL__ */ 54#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/unistd.h b/include/asm-powerpc/unistd.h
index 97d82b6a940..fedc4b8e49e 100644
--- a/include/asm-powerpc/unistd.h
+++ b/include/asm-powerpc/unistd.h
@@ -332,10 +332,11 @@
332#define __NR_eventfd 307 332#define __NR_eventfd 307
333#define __NR_sync_file_range2 308 333#define __NR_sync_file_range2 308
334#define __NR_fallocate 309 334#define __NR_fallocate 309
335#define __NR_subpage_prot 310
335 336
336#ifdef __KERNEL__ 337#ifdef __KERNEL__
337 338
338#define __NR_syscalls 310 339#define __NR_syscalls 311
339 340
340#define __NR__exit __NR_exit 341#define __NR__exit __NR_exit
341#define NR_syscalls __NR_syscalls 342#define NR_syscalls __NR_syscalls
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-17 04:16:15 -0500