diff options
author | Marc St-Jean <stjeanma@pmc-sierra.com> | 2007-06-14 17:55:31 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2007-07-10 12:33:03 -0400 |
commit | 9267a30d1dc7dcd7cadb5eb6a5bbfed703feeefa (patch) | |
tree | 91fa5a1a4605cdf0a1f1db21e22073b87735ce7a /include/asm-mips | |
parent | 35832e26f95ba14a6b6f0519441c5cb64cca6bf9 (diff) |
[MIPS] PMC MSP71xx mips common
Patch to add mips common support for the PMC-Sierra MSP71xx devices.
Signed-off-by: Marc St-Jean <Marc_St-Jean@pmc-sierra.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips')
-rw-r--r-- | include/asm-mips/bootinfo.h | 12 | ||||
-rw-r--r-- | include/asm-mips/cpu.h | 2 | ||||
-rw-r--r-- | include/asm-mips/mipsregs.h | 33 | ||||
-rw-r--r-- | include/asm-mips/war.h | 11 |
4 files changed, 58 insertions, 0 deletions
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h index 12f9d7139eb..94fc9be1aab 100644 --- a/include/asm-mips/bootinfo.h +++ b/include/asm-mips/bootinfo.h | |||
@@ -213,6 +213,18 @@ | |||
213 | #define MACH_GROUP_LEMOTE 27 | 213 | #define MACH_GROUP_LEMOTE 27 |
214 | #define MACH_LEMOTE_FULONG 0 | 214 | #define MACH_LEMOTE_FULONG 0 |
215 | 215 | ||
216 | /* | ||
217 | * Valid machtype for group PMC-MSP | ||
218 | */ | ||
219 | #define MACH_GROUP_MSP 26 /* PMC-Sierra MSP boards/CPUs */ | ||
220 | #define MACH_MSP4200_EVAL 0 /* PMC-Sierra MSP4200 Evaluation */ | ||
221 | #define MACH_MSP4200_GW 1 /* PMC-Sierra MSP4200 Gateway demo */ | ||
222 | #define MACH_MSP4200_FPGA 2 /* PMC-Sierra MSP4200 Emulation */ | ||
223 | #define MACH_MSP7120_EVAL 3 /* PMC-Sierra MSP7120 Evaluation */ | ||
224 | #define MACH_MSP7120_GW 4 /* PMC-Sierra MSP7120 Residential GW */ | ||
225 | #define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */ | ||
226 | #define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */ | ||
227 | |||
216 | #define CL_SIZE COMMAND_LINE_SIZE | 228 | #define CL_SIZE COMMAND_LINE_SIZE |
217 | 229 | ||
218 | const char *get_system_type(void); | 230 | const char *get_system_type(void); |
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index a3623954dad..3857358fb6d 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h | |||
@@ -109,6 +109,7 @@ | |||
109 | * Definitions for 7:0 on legacy processors | 109 | * Definitions for 7:0 on legacy processors |
110 | */ | 110 | */ |
111 | 111 | ||
112 | #define PRID_REV_MASK 0x00ff | ||
112 | 113 | ||
113 | #define PRID_REV_TX4927 0x0022 | 114 | #define PRID_REV_TX4927 0x0022 |
114 | #define PRID_REV_TX4937 0x0030 | 115 | #define PRID_REV_TX4937 0x0030 |
@@ -125,6 +126,7 @@ | |||
125 | #define PRID_REV_VR4122 0x0070 | 126 | #define PRID_REV_VR4122 0x0070 |
126 | #define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ | 127 | #define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ |
127 | #define PRID_REV_VR4130 0x0080 | 128 | #define PRID_REV_VR4130 0x0080 |
129 | #define PRID_REV_34K_V1_0_2 0x0022 | ||
128 | 130 | ||
129 | /* | 131 | /* |
130 | * Older processors used to encode processor version and revision in two | 132 | * Older processors used to encode processor version and revision in two |
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h index 668db02c280..706b3691f57 100644 --- a/include/asm-mips/mipsregs.h +++ b/include/asm-mips/mipsregs.h | |||
@@ -15,6 +15,7 @@ | |||
15 | 15 | ||
16 | #include <linux/linkage.h> | 16 | #include <linux/linkage.h> |
17 | #include <asm/hazards.h> | 17 | #include <asm/hazards.h> |
18 | #include <asm/war.h> | ||
18 | 19 | ||
19 | /* | 20 | /* |
20 | * The following macros are especially useful for __asm__ | 21 | * The following macros are especially useful for __asm__ |
@@ -537,6 +538,9 @@ | |||
537 | 538 | ||
538 | #define MIPS_CONF7_WII (_ULCAST_(1) << 31) | 539 | #define MIPS_CONF7_WII (_ULCAST_(1) << 31) |
539 | 540 | ||
541 | #define MIPS_CONF7_RPS (_ULCAST_(1) << 2) | ||
542 | |||
543 | |||
540 | /* | 544 | /* |
541 | * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. | 545 | * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. |
542 | */ | 546 | */ |
@@ -1298,10 +1302,39 @@ static inline void tlb_probe(void) | |||
1298 | 1302 | ||
1299 | static inline void tlb_read(void) | 1303 | static inline void tlb_read(void) |
1300 | { | 1304 | { |
1305 | #if MIPS34K_MISSED_ITLB_WAR | ||
1306 | int res = 0; | ||
1307 | |||
1308 | __asm__ __volatile__( | ||
1309 | " .set push \n" | ||
1310 | " .set noreorder \n" | ||
1311 | " .set noat \n" | ||
1312 | " .set mips32r2 \n" | ||
1313 | " .word 0x41610001 # dvpe $1 \n" | ||
1314 | " move %0, $1 \n" | ||
1315 | " ehb \n" | ||
1316 | " .set pop \n" | ||
1317 | : "=r" (res)); | ||
1318 | |||
1319 | instruction_hazard(); | ||
1320 | #endif | ||
1321 | |||
1301 | __asm__ __volatile__( | 1322 | __asm__ __volatile__( |
1302 | ".set noreorder\n\t" | 1323 | ".set noreorder\n\t" |
1303 | "tlbr\n\t" | 1324 | "tlbr\n\t" |
1304 | ".set reorder"); | 1325 | ".set reorder"); |
1326 | |||
1327 | #if MIPS34K_MISSED_ITLB_WAR | ||
1328 | if ((res & _ULCAST_(1))) | ||
1329 | __asm__ __volatile__( | ||
1330 | " .set push \n" | ||
1331 | " .set noreorder \n" | ||
1332 | " .set noat \n" | ||
1333 | " .set mips32r2 \n" | ||
1334 | " .word 0x41600021 # evpe \n" | ||
1335 | " ehb \n" | ||
1336 | " .set pop \n"); | ||
1337 | #endif | ||
1305 | } | 1338 | } |
1306 | 1339 | ||
1307 | static inline void tlb_write_indexed(void) | 1340 | static inline void tlb_write_indexed(void) |
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index c507f1b8014..45cb8272483 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h | |||
@@ -198,6 +198,14 @@ | |||
198 | #endif | 198 | #endif |
199 | 199 | ||
200 | /* | 200 | /* |
201 | * 34K core erratum: "Problems Executing the TLBR Instruction" | ||
202 | */ | ||
203 | #if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \ | ||
204 | defined(CONFIG_PMC_MSP7120_FPGA) | ||
205 | #define MIPS34K_MISSED_ITLB_WAR 1 | ||
206 | #endif | ||
207 | |||
208 | /* | ||
201 | * Workarounds default to off | 209 | * Workarounds default to off |
202 | */ | 210 | */ |
203 | #ifndef ICACHE_REFILLS_WORKAROUND_WAR | 211 | #ifndef ICACHE_REFILLS_WORKAROUND_WAR |
@@ -236,5 +244,8 @@ | |||
236 | #ifndef R10000_LLSC_WAR | 244 | #ifndef R10000_LLSC_WAR |
237 | #define R10000_LLSC_WAR 0 | 245 | #define R10000_LLSC_WAR 0 |
238 | #endif | 246 | #endif |
247 | #ifndef MIPS34K_MISSED_ITLB_WAR | ||
248 | #define MIPS34K_MISSED_ITLB_WAR 0 | ||
249 | #endif | ||
239 | 250 | ||
240 | #endif /* _ASM_WAR_H */ | 251 | #endif /* _ASM_WAR_H */ |