diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2005-09-03 18:56:17 -0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@evo.osdl.org> | 2005-09-05 03:06:07 -0400 |
| commit | 42a3b4f25af8f8d77feddf27f839fa0628dbff1a (patch) | |
| tree | 332370ff3889fabb66a45fb5dcf605b142de77c8 /include/asm-mips/war.h | |
| parent | 875d43e72b5bf22161a81de7554f88eccf8a51ae (diff) | |
[PATCH] mips: nuke trailing whitespace
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-mips/war.h')
| -rw-r--r-- | include/asm-mips/war.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index c4a70412134..04ee53b34c2 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h | |||
| @@ -113,7 +113,7 @@ | |||
| 113 | */ | 113 | */ |
| 114 | #define BCM1250_M3_WAR 1 | 114 | #define BCM1250_M3_WAR 1 |
| 115 | 115 | ||
| 116 | /* | 116 | /* |
| 117 | * This is a DUART workaround related to glitches around register accesses | 117 | * This is a DUART workaround related to glitches around register accesses |
| 118 | */ | 118 | */ |
| 119 | #define SIBYTE_1956_WAR 1 | 119 | #define SIBYTE_1956_WAR 1 |
| @@ -122,7 +122,7 @@ | |||
| 122 | 122 | ||
| 123 | /* | 123 | /* |
| 124 | * Fill buffers not flushed on CACHE instructions | 124 | * Fill buffers not flushed on CACHE instructions |
| 125 | * | 125 | * |
| 126 | * Hit_Invalidate_I cacheops invalidate an icache line but the refill | 126 | * Hit_Invalidate_I cacheops invalidate an icache line but the refill |
| 127 | * for that line can get stale data from the fill buffer instead of | 127 | * for that line can get stale data from the fill buffer instead of |
| 128 | * accessing memory if the previous icache miss was also to that line. | 128 | * accessing memory if the previous icache miss was also to that line. |