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authorAndrew Isaacson <adi@broadcom.com>2005-10-20 02:55:11 -0400
committerRalf Baechle <ralf@linux-mips.org>2005-10-29 14:32:45 -0400
commit4cbf2beac2265b3619be9c8e88ff4ff45b49d7c2 (patch)
treefa7701264e60759b080b7953bcfad081a51e63d2 /include/asm-mips/sibyte/sb1250_dma.h
parentd121ced21d79eab7726bfe6b1e33da4ae86072c0 (diff)
BCM1480 headers
Add header files for BCM1480/1280/1455/1255 family of chips, and update sb1250 headers which are shared by BCM1480 family. Signed-Off-By: Andy Isaacson <adi@broadcom.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> diff --git a/include/asm-mips/sibyte/bcm1480_int.h b/include/asm-mips/sibyte/bcm1480_int.h new file mode 100644
Diffstat (limited to 'include/asm-mips/sibyte/sb1250_dma.h')
-rw-r--r--include/asm-mips/sibyte/sb1250_dma.h65
1 files changed, 33 insertions, 32 deletions
diff --git a/include/asm-mips/sibyte/sb1250_dma.h b/include/asm-mips/sibyte/sb1250_dma.h
index 3cdb48f50ed..4b092b9dfe0 100644
--- a/include/asm-mips/sibyte/sb1250_dma.h
+++ b/include/asm-mips/sibyte/sb1250_dma.h
@@ -58,17 +58,17 @@
58#define M_DMA_RESERVED1 _SB_MAKEMASK1(2) 58#define M_DMA_RESERVED1 _SB_MAKEMASK1(2)
59 59
60#define S_DMA_DESC_TYPE _SB_MAKE64(1) 60#define S_DMA_DESC_TYPE _SB_MAKE64(1)
61#define M_DMA_DESC_TYPE _SB_MAKE64(2,S_DMA_DESC_TYPE) 61#define M_DMA_DESC_TYPE _SB_MAKEMASK(2,S_DMA_DESC_TYPE)
62#define V_DMA_DESC_TYPE(x) _SB_MAKEVALUE(x,S_DMA_DESC_TYPE) 62#define V_DMA_DESC_TYPE(x) _SB_MAKEVALUE(x,S_DMA_DESC_TYPE)
63#define G_DMA_DESC_TYPE(x) _SB_GETVALUE(x,S_DMA_DESC_TYPE,M_DMA_DESC_TYPE) 63#define G_DMA_DESC_TYPE(x) _SB_GETVALUE(x,S_DMA_DESC_TYPE,M_DMA_DESC_TYPE)
64 64
65#define K_DMA_DESC_TYPE_RING_AL 0 65#define K_DMA_DESC_TYPE_RING_AL 0
66#define K_DMA_DESC_TYPE_CHAIN_AL 1 66#define K_DMA_DESC_TYPE_CHAIN_AL 1
67 67
68#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 68#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
69#define K_DMA_DESC_TYPE_RING_UAL_WI 2 69#define K_DMA_DESC_TYPE_RING_UAL_WI 2
70#define K_DMA_DESC_TYPE_RING_UAL_RMW 3 70#define K_DMA_DESC_TYPE_RING_UAL_RMW 3
71#endif /* 1250 PASS3 || 112x PASS1 */ 71#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
72 72
73#define M_DMA_EOP_INT_EN _SB_MAKEMASK1(3) 73#define M_DMA_EOP_INT_EN _SB_MAKEMASK1(3)
74#define M_DMA_HWM_INT_EN _SB_MAKEMASK1(4) 74#define M_DMA_HWM_INT_EN _SB_MAKEMASK1(4)
@@ -111,11 +111,11 @@
111#define M_DMA_NO_DSCR_UPDT _SB_MAKEMASK1(4) 111#define M_DMA_NO_DSCR_UPDT _SB_MAKEMASK1(4)
112#define M_DMA_L2CA _SB_MAKEMASK1(5) 112#define M_DMA_L2CA _SB_MAKEMASK1(5)
113 113
114#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 114#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
115#define M_DMA_RX_XTRA_STATUS _SB_MAKEMASK1(6) 115#define M_DMA_RX_XTRA_STATUS _SB_MAKEMASK1(6)
116#define M_DMA_TX_CPU_PAUSE _SB_MAKEMASK1(6) 116#define M_DMA_TX_CPU_PAUSE _SB_MAKEMASK1(6)
117#define M_DMA_TX_FC_PAUSE_EN _SB_MAKEMASK1(7) 117#define M_DMA_TX_FC_PAUSE_EN _SB_MAKEMASK1(7)
118#endif /* 1250 PASS3 || 112x PASS1 */ 118#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
119 119
120#define M_DMA_MBZ1 _SB_MAKEMASK(6,15) 120#define M_DMA_MBZ1 _SB_MAKEMASK(6,15)
121 121
@@ -165,14 +165,14 @@
165#define S_DMA_CURDSCR_COUNT _SB_MAKE64(40) 165#define S_DMA_CURDSCR_COUNT _SB_MAKE64(40)
166#define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16,S_DMA_CURDSCR_COUNT) 166#define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16,S_DMA_CURDSCR_COUNT)
167 167
168#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 168#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
169#define M_DMA_TX_CH_PAUSE_ON _SB_MAKEMASK1(56) 169#define M_DMA_TX_CH_PAUSE_ON _SB_MAKEMASK1(56)
170#endif /* 1250 PASS3 || 112x PASS1 */ 170#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
171 171
172/* 172/*
173 * Receive Packet Drop Registers 173 * Receive Packet Drop Registers
174 */ 174 */
175#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 175#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
176#define S_DMA_OODLOST_RX _SB_MAKE64(0) 176#define S_DMA_OODLOST_RX _SB_MAKE64(0)
177#define M_DMA_OODLOST_RX _SB_MAKEMASK(16,S_DMA_OODLOST_RX) 177#define M_DMA_OODLOST_RX _SB_MAKEMASK(16,S_DMA_OODLOST_RX)
178#define G_DMA_OODLOST_RX(x) _SB_GETVALUE(x,S_DMA_OODLOST_RX,M_DMA_OODLOST_RX) 178#define G_DMA_OODLOST_RX(x) _SB_GETVALUE(x,S_DMA_OODLOST_RX,M_DMA_OODLOST_RX)
@@ -180,7 +180,7 @@
180#define S_DMA_EOP_COUNT_RX _SB_MAKE64(16) 180#define S_DMA_EOP_COUNT_RX _SB_MAKE64(16)
181#define M_DMA_EOP_COUNT_RX _SB_MAKEMASK(8,S_DMA_EOP_COUNT_RX) 181#define M_DMA_EOP_COUNT_RX _SB_MAKEMASK(8,S_DMA_EOP_COUNT_RX)
182#define G_DMA_EOP_COUNT_RX(x) _SB_GETVALUE(x,S_DMA_EOP_COUNT_RX,M_DMA_EOP_COUNT_RX) 182#define G_DMA_EOP_COUNT_RX(x) _SB_GETVALUE(x,S_DMA_EOP_COUNT_RX,M_DMA_EOP_COUNT_RX)
183#endif /* 1250 PASS3 || 112x PASS1 */ 183#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
184 184
185/* ********************************************************************* 185/* *********************************************************************
186 * DMA Descriptors 186 * DMA Descriptors
@@ -201,21 +201,21 @@
201 201
202#define M_DMA_DSCRA_A_ADDR_OFFSET (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR) 202#define M_DMA_DSCRA_A_ADDR_OFFSET (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR)
203 203
204#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 204#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
205#define S_DMA_DSCRA_A_ADDR_UA _SB_MAKE64(0) 205#define S_DMA_DSCRA_A_ADDR_UA _SB_MAKE64(0)
206#define M_DMA_DSCRA_A_ADDR_UA _SB_MAKEMASK(40,S_DMA_DSCRA_A_ADDR_UA) 206#define M_DMA_DSCRA_A_ADDR_UA _SB_MAKEMASK(40,S_DMA_DSCRA_A_ADDR_UA)
207#endif /* 1250 PASS3 || 112x PASS1 */ 207#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
208 208
209#define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40) 209#define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40)
210#define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9,S_DMA_DSCRA_A_SIZE) 210#define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9,S_DMA_DSCRA_A_SIZE)
211#define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_A_SIZE) 211#define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_A_SIZE)
212#define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRA_A_SIZE,M_DMA_DSCRA_A_SIZE) 212#define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRA_A_SIZE,M_DMA_DSCRA_A_SIZE)
213 213
214#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 214#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
215#define S_DMA_DSCRA_DSCR_CNT _SB_MAKE64(40) 215#define S_DMA_DSCRA_DSCR_CNT _SB_MAKE64(40)
216#define M_DMA_DSCRA_DSCR_CNT _SB_MAKEMASK(8,S_DMA_DSCRA_DSCR_CNT) 216#define M_DMA_DSCRA_DSCR_CNT _SB_MAKEMASK(8,S_DMA_DSCRA_DSCR_CNT)
217#define G_DMA_DSCRA_DSCR_CNT(x) _SB_GETVALUE(x,S_DMA_DSCRA_DSCR_CNT,M_DMA_DSCRA_DSCR_CNT) 217#define G_DMA_DSCRA_DSCR_CNT(x) _SB_GETVALUE(x,S_DMA_DSCRA_DSCR_CNT,M_DMA_DSCRA_DSCR_CNT)
218#endif /* 1250 PASS3 || 112x PASS1 */ 218#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
219 219
220#define M_DMA_DSCRA_INTERRUPT _SB_MAKEMASK1(49) 220#define M_DMA_DSCRA_INTERRUPT _SB_MAKEMASK1(49)
221#define M_DMA_DSCRA_OFFSETB _SB_MAKEMASK1(50) 221#define M_DMA_DSCRA_OFFSETB _SB_MAKEMASK1(50)
@@ -235,12 +235,12 @@
235#define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_OPTIONS) 235#define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_OPTIONS)
236#define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x,S_DMA_DSCRB_OPTIONS,M_DMA_DSCRB_OPTIONS) 236#define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x,S_DMA_DSCRB_OPTIONS,M_DMA_DSCRB_OPTIONS)
237 237
238#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 238#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
239#define S_DMA_DSCRB_A_SIZE _SB_MAKE64(8) 239#define S_DMA_DSCRB_A_SIZE _SB_MAKE64(8)
240#define M_DMA_DSCRB_A_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_A_SIZE) 240#define M_DMA_DSCRB_A_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_A_SIZE)
241#define V_DMA_DSCRB_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_A_SIZE) 241#define V_DMA_DSCRB_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_A_SIZE)
242#define G_DMA_DSCRB_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_A_SIZE,M_DMA_DSCRB_A_SIZE) 242#define G_DMA_DSCRB_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_A_SIZE,M_DMA_DSCRB_A_SIZE)
243#endif /* 1250 PASS3 || 112x PASS1 */ 243#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
244 244
245#define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10) 245#define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10)
246 246
@@ -255,12 +255,12 @@
255 255
256#define M_DMA_DSCRB_B_VALID _SB_MAKEMASK1(49) 256#define M_DMA_DSCRB_B_VALID _SB_MAKEMASK1(49)
257 257
258#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 258#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
259#define S_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKE64(48) 259#define S_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKE64(48)
260#define M_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKEMASK(2,S_DMA_DSCRB_PKT_SIZE_MSB) 260#define M_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKEMASK(2,S_DMA_DSCRB_PKT_SIZE_MSB)
261#define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB) 261#define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB)
262#define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB,M_DMA_DSCRB_PKT_SIZE_MSB) 262#define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB,M_DMA_DSCRB_PKT_SIZE_MSB)
263#endif /* 1250 PASS3 || 112x PASS1 */ 263#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
264 264
265#define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50) 265#define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50)
266#define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_PKT_SIZE) 266#define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_PKT_SIZE)
@@ -282,15 +282,16 @@
282#define M_DMA_ETHRX_BADIP4CS _SB_MAKEMASK1(51) 282#define M_DMA_ETHRX_BADIP4CS _SB_MAKEMASK1(51)
283#define M_DMA_ETHRX_DSCRERR _SB_MAKEMASK1(52) 283#define M_DMA_ETHRX_DSCRERR _SB_MAKEMASK1(52)
284 284
285#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 285#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
286/* Note: BADTCPCS is actually in DSCR_B options field */ 286/* Note: This bit is in the DSCR_B options field */
287#define M_DMA_ETHRX_BADTCPCS _SB_MAKEMASK1(0) 287#define M_DMA_ETHRX_BADTCPCS _SB_MAKEMASK1(0)
288#endif /* 1250 PASS2 || 112x PASS1 */ 288#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
289 289
290#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 290#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
291/* Note: These bits are in the DSCR_B options field */
291#define M_DMA_ETH_VLAN_FLAG _SB_MAKEMASK1(1) 292#define M_DMA_ETH_VLAN_FLAG _SB_MAKEMASK1(1)
292#define M_DMA_ETH_CRC_FLAG _SB_MAKEMASK1(2) 293#define M_DMA_ETH_CRC_FLAG _SB_MAKEMASK1(2)
293#endif /* 1250 PASS3 || 112x PASS1 */ 294#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
294 295
295#define S_DMA_ETHRX_RXCH 53 296#define S_DMA_ETHRX_RXCH 53
296#define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2,S_DMA_ETHRX_RXCH) 297#define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2,S_DMA_ETHRX_RXCH)
@@ -438,7 +439,7 @@
438 M_DM_CUR_DSCR_DSCR_COUNT) 439 M_DM_CUR_DSCR_DSCR_COUNT)
439 440
440 441
441#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 442#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
442/* 443/*
443 * Data Mover Channel Partial Result Registers 444 * Data Mover Channel Partial Result Registers
444 * Register: DM_PARTIAL_0 445 * Register: DM_PARTIAL_0
@@ -459,10 +460,10 @@
459 M_DM_PARTIAL_TCPCS_PARTIAL) 460 M_DM_PARTIAL_TCPCS_PARTIAL)
460 461
461#define M_DM_PARTIAL_ODD_BYTE _SB_MAKEMASK1(48) 462#define M_DM_PARTIAL_ODD_BYTE _SB_MAKEMASK1(48)
462#endif /* 1250 PASS3 || 112x PASS1 */ 463#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
463 464
464 465
465#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 466#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
466/* 467/*
467 * Data Mover CRC Definition Registers 468 * Data Mover CRC Definition Registers
468 * Register: CRC_DEF_0 469 * Register: CRC_DEF_0
@@ -479,10 +480,10 @@
479#define V_CRC_DEF_CRC_POLY(r) _SB_MAKEVALUE(r,S_CRC_DEF_CRC_POLY) 480#define V_CRC_DEF_CRC_POLY(r) _SB_MAKEVALUE(r,S_CRC_DEF_CRC_POLY)
480#define G_CRC_DEF_CRC_POLY(r) _SB_GETVALUE(r,S_CRC_DEF_CRC_POLY,\ 481#define G_CRC_DEF_CRC_POLY(r) _SB_GETVALUE(r,S_CRC_DEF_CRC_POLY,\
481 M_CRC_DEF_CRC_POLY) 482 M_CRC_DEF_CRC_POLY)
482#endif /* 1250 PASS3 || 112x PASS1 */ 483#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
483 484
484 485
485#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 486#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
486/* 487/*
487 * Data Mover CRC/Checksum Definition Registers 488 * Data Mover CRC/Checksum Definition Registers
488 * Register: CTCP_DEF_0 489 * Register: CTCP_DEF_0
@@ -511,7 +512,7 @@
511#define K_CTCP_DEF_CRC_WIDTH_1 2 512#define K_CTCP_DEF_CRC_WIDTH_1 2
512 513
513#define M_CTCP_DEF_CRC_BIT_ORDER _SB_MAKEMASK1(50) 514#define M_CTCP_DEF_CRC_BIT_ORDER _SB_MAKEMASK1(50)
514#endif /* 1250 PASS3 || 112x PASS1 */ 515#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
515 516
516 517
517/* 518/*
@@ -560,12 +561,12 @@
560#define M_DM_DSCRA_L2C_DEST _SB_MAKEMASK1(50) 561#define M_DM_DSCRA_L2C_DEST _SB_MAKEMASK1(50)
561#define M_DM_DSCRA_L2C_SRC _SB_MAKEMASK1(51) 562#define M_DM_DSCRA_L2C_SRC _SB_MAKEMASK1(51)
562 563
563#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 564#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
564#define M_DM_DSCRA_RD_BKOFF _SB_MAKEMASK1(52) 565#define M_DM_DSCRA_RD_BKOFF _SB_MAKEMASK1(52)
565#define M_DM_DSCRA_WR_BKOFF _SB_MAKEMASK1(53) 566#define M_DM_DSCRA_WR_BKOFF _SB_MAKEMASK1(53)
566#endif /* 1250 PASS2 || 112x PASS1 */ 567#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
567 568
568#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 569#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
569#define M_DM_DSCRA_TCPCS_EN _SB_MAKEMASK1(54) 570#define M_DM_DSCRA_TCPCS_EN _SB_MAKEMASK1(54)
570#define M_DM_DSCRA_TCPCS_RES _SB_MAKEMASK1(55) 571#define M_DM_DSCRA_TCPCS_RES _SB_MAKEMASK1(55)
571#define M_DM_DSCRA_TCPCS_AP _SB_MAKEMASK1(56) 572#define M_DM_DSCRA_TCPCS_AP _SB_MAKEMASK1(56)
@@ -574,7 +575,7 @@
574#define M_DM_DSCRA_CRC_AP _SB_MAKEMASK1(59) 575#define M_DM_DSCRA_CRC_AP _SB_MAKEMASK1(59)
575#define M_DM_DSCRA_CRC_DFN _SB_MAKEMASK1(60) 576#define M_DM_DSCRA_CRC_DFN _SB_MAKEMASK1(60)
576#define M_DM_DSCRA_CRC_XBIT _SB_MAKEMASK1(61) 577#define M_DM_DSCRA_CRC_XBIT _SB_MAKEMASK1(61)
577#endif /* 1250 PASS3 || 112x PASS1 */ 578#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
578 579
579#define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(3,61) 580#define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(3,61)
580 581
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