diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2005-02-10 07:19:59 -0500 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2005-10-29 14:30:31 -0400 |
commit | c6e8b587718c486b55c2ebecc6de231a30beba35 (patch) | |
tree | 7c6162d449c69fb6425bd27ba341e2d874fb0a1b /include/asm-mips/pgtable-32.h | |
parent | 57f0060b8a2bb2a70a4cce1a37d5e0158cea92a6 (diff) |
Update MIPS to use the 4-level pagetable code thereby getting rid of
the compacrapability headers.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/pgtable-32.h')
-rw-r--r-- | include/asm-mips/pgtable-32.h | 40 |
1 files changed, 12 insertions, 28 deletions
diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h index 7fec93b76da..8d66303eabc 100644 --- a/include/asm-mips/pgtable-32.h +++ b/include/asm-mips/pgtable-32.h | |||
@@ -17,6 +17,8 @@ | |||
17 | #include <asm/cachectl.h> | 17 | #include <asm/cachectl.h> |
18 | #include <asm/fixmap.h> | 18 | #include <asm/fixmap.h> |
19 | 19 | ||
20 | #include <asm-generic/pgtable-nopmd.h> | ||
21 | |||
20 | /* | 22 | /* |
21 | * - add_wired_entry() add a fixed TLB entry, and move wired register | 23 | * - add_wired_entry() add a fixed TLB entry, and move wired register |
22 | */ | 24 | */ |
@@ -42,35 +44,35 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, | |||
42 | */ | 44 | */ |
43 | 45 | ||
44 | /* PMD_SHIFT determines the size of the area a second-level page table can map */ | 46 | /* PMD_SHIFT determines the size of the area a second-level page table can map */ |
45 | #ifdef CONFIG_64BIT_PHYS_ADDR | ||
46 | #define PMD_SHIFT 21 | ||
47 | #else | ||
48 | #define PMD_SHIFT 22 | ||
49 | #endif | ||
50 | #define PMD_SIZE (1UL << PMD_SHIFT) | 47 | #define PMD_SIZE (1UL << PMD_SHIFT) |
51 | #define PMD_MASK (~(PMD_SIZE-1)) | 48 | #define PMD_MASK (~(PMD_SIZE-1)) |
52 | 49 | ||
53 | /* PGDIR_SHIFT determines what a third-level page table entry can map */ | 50 | /* PGDIR_SHIFT determines what a third-level page table entry can map */ |
54 | #define PGDIR_SHIFT PMD_SHIFT | 51 | #ifdef CONFIG_64BIT_PHYS_ADDR |
52 | #define PGDIR_SHIFT 21 | ||
53 | #else | ||
54 | #define PGDIR_SHIFT 22 | ||
55 | #endif | ||
55 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) | 56 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) |
56 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | 57 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) |
57 | 58 | ||
58 | /* | 59 | /* |
59 | * Entries per page directory level: we use two-level, so | 60 | * Entries per page directory level: we use two-level, so |
60 | * we don't really have any PMD directory physically. | 61 | * we don't really have any PUD/PMD directory physically. |
61 | */ | 62 | */ |
62 | #ifdef CONFIG_64BIT_PHYS_ADDR | 63 | #ifdef CONFIG_64BIT_PHYS_ADDR |
63 | #define PGD_ORDER 1 | 64 | #define PGD_ORDER 1 |
64 | #define PMD_ORDER 0 | 65 | #define PUD_ORDER aieeee_attempt_to_allocate_pud |
66 | #define PMD_ORDER 1 | ||
65 | #define PTE_ORDER 0 | 67 | #define PTE_ORDER 0 |
66 | #else | 68 | #else |
67 | #define PGD_ORDER 0 | 69 | #define PGD_ORDER 0 |
68 | #define PMD_ORDER 0 | 70 | #define PUD_ORDER aieeee_attempt_to_allocate_pud |
71 | #define PMD_ORDER 1 | ||
69 | #define PTE_ORDER 0 | 72 | #define PTE_ORDER 0 |
70 | #endif | 73 | #endif |
71 | 74 | ||
72 | #define PTRS_PER_PGD ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t)) | 75 | #define PTRS_PER_PGD ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t)) |
73 | #define PTRS_PER_PMD 1 | ||
74 | #define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t)) | 76 | #define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t)) |
75 | 77 | ||
76 | #define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE) | 78 | #define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE) |
@@ -91,8 +93,6 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, | |||
91 | #define pte_ERROR(e) \ | 93 | #define pte_ERROR(e) \ |
92 | printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) | 94 | printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) |
93 | #endif | 95 | #endif |
94 | #define pmd_ERROR(e) \ | ||
95 | printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) | ||
96 | #define pgd_ERROR(e) \ | 96 | #define pgd_ERROR(e) \ |
97 | printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) | 97 | printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) |
98 | 98 | ||
@@ -120,16 +120,6 @@ static inline void pmd_clear(pmd_t *pmdp) | |||
120 | pmd_val(*pmdp) = ((unsigned long) invalid_pte_table); | 120 | pmd_val(*pmdp) = ((unsigned long) invalid_pte_table); |
121 | } | 121 | } |
122 | 122 | ||
123 | /* | ||
124 | * The "pgd_xxx()" functions here are trivial for a folded two-level | ||
125 | * setup: the pgd is never bad, and a pmd always exists (as it's folded | ||
126 | * into the pgd entry) | ||
127 | */ | ||
128 | static inline int pgd_none(pgd_t pgd) { return 0; } | ||
129 | static inline int pgd_bad(pgd_t pgd) { return 0; } | ||
130 | static inline int pgd_present(pgd_t pgd) { return 1; } | ||
131 | static inline void pgd_clear(pgd_t *pgdp) { } | ||
132 | |||
133 | #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) | 123 | #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) |
134 | #define pte_page(x) pfn_to_page(pte_pfn(x)) | 124 | #define pte_page(x) pfn_to_page(pte_pfn(x)) |
135 | #define pte_pfn(x) ((unsigned long)((x).pte_high >> 6)) | 125 | #define pte_pfn(x) ((unsigned long)((x).pte_high >> 6)) |
@@ -166,12 +156,6 @@ pfn_pte(unsigned long pfn, pgprot_t prot) | |||
166 | /* to find an entry in a page-table-directory */ | 156 | /* to find an entry in a page-table-directory */ |
167 | #define pgd_offset(mm,addr) ((mm)->pgd + pgd_index(addr)) | 157 | #define pgd_offset(mm,addr) ((mm)->pgd + pgd_index(addr)) |
168 | 158 | ||
169 | /* Find an entry in the second-level page table.. */ | ||
170 | static inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address) | ||
171 | { | ||
172 | return (pmd_t *) dir; | ||
173 | } | ||
174 | |||
175 | /* Find an entry in the third-level page table.. */ | 159 | /* Find an entry in the third-level page table.. */ |
176 | #define __pte_offset(address) \ | 160 | #define __pte_offset(address) \ |
177 | (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) | 161 | (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) |