aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-blackfin/mach-bf533
diff options
context:
space:
mode:
authorMike Frysinger <michael.frysinger@analog.com>2007-12-24 06:40:05 -0500
committerBryan Wu <cooloney@kernel.org>2007-12-24 06:40:05 -0500
commit0bcfd70ea11a5d6f2362be463513a60245a62baf (patch)
treefdf47e68cc5fc916da5d985f797b262c36997c4e /include/asm-blackfin/mach-bf533
parent4c195ad88b7df54b2e7340dec3446aee6ca84cd1 (diff)
[Blackfin] serial driver: fix bug - cache the bits of the LSR on systems where the LSR is read-to-clear
Cache the bits of the LSR on systems where the LSR is read-to-clear so that we can safely read the LSR in random places. this fixes older parts where break/framing/parity/overflow was not being detected at all in PIO mode, and this fixes newer parts where break/framing/parity/overflow was being reported all the time without being cleared. Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'include/asm-blackfin/mach-bf533')
-rw-r--r--include/asm-blackfin/mach-bf533/bfin_serial_5xx.h19
1 files changed, 18 insertions, 1 deletions
diff --git a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
index 7871d4313f4..b619065ceeb 100644
--- a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
@@ -23,7 +23,6 @@
23#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) 23#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
24#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR)) 24#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
25#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) 25#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
26#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
27#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) 26#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
28 27
29#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) 28#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
@@ -46,6 +45,7 @@
46struct bfin_serial_port { 45struct bfin_serial_port {
47 struct uart_port port; 46 struct uart_port port;
48 unsigned int old_status; 47 unsigned int old_status;
48 unsigned int lsr;
49#ifdef CONFIG_SERIAL_BFIN_DMA 49#ifdef CONFIG_SERIAL_BFIN_DMA
50 int tx_done; 50 int tx_done;
51 int tx_count; 51 int tx_count;
@@ -64,6 +64,23 @@ struct bfin_serial_port {
64#endif 64#endif
65}; 65};
66 66
67/* The hardware clears the LSR bits upon read, so we need to cache
68 * some of the more fun bits in software so they don't get lost
69 * when checking the LSR in other code paths (TX).
70 */
71static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
72{
73 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
74 uart->lsr |= (lsr & (BI|FE|PE|OE));
75 return lsr | uart->lsr;
76}
77
78static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
79{
80 uart->lsr = 0;
81 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
82}
83
67struct bfin_serial_port bfin_serial_ports[NR_PORTS]; 84struct bfin_serial_port bfin_serial_ports[NR_PORTS];
68struct bfin_serial_res { 85struct bfin_serial_res {
69 unsigned long uart_base_addr; 86 unsigned long uart_base_addr;