diff options
author | Lennert Buytenhek <buytenh@wantstofly.org> | 2006-09-18 18:22:24 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-09-25 05:25:46 -0400 |
commit | 610300e8f4f833904096ca1233ffd9dbd73fb11f (patch) | |
tree | 2b8e26c511edbbfc666af184a3de984c03d06220 /include/asm-arm/arch-iop33x | |
parent | 38ce73ebd74a9a1738b73619557f2397c59ba628 (diff) |
[ARM] 3826/1: iop3xx: remove IOP3??_IRQ_OFS irq offset
Get rid of the unused IOP3??_IRQ_OFS irq offset define, start IRQ
numbering from zero.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-iop33x')
-rw-r--r-- | include/asm-arm/arch-iop33x/entry-macro.S | 1 | ||||
-rw-r--r-- | include/asm-arm/arch-iop33x/irqs.h | 110 |
2 files changed, 39 insertions, 72 deletions
diff --git a/include/asm-arm/arch-iop33x/entry-macro.S b/include/asm-arm/arch-iop33x/entry-macro.S index 57f6ea0069e..425aa7aafa0 100644 --- a/include/asm-arm/arch-iop33x/entry-macro.S +++ b/include/asm-arm/arch-iop33x/entry-macro.S | |||
@@ -30,6 +30,5 @@ | |||
30 | b 1001f | 30 | b 1001f |
31 | 1002: clz \irqnr, \irqstat | 31 | 1002: clz \irqnr, \irqstat |
32 | rsbs \irqnr,\irqnr,#31 @ recommend by RMK | 32 | rsbs \irqnr,\irqnr,#31 @ recommend by RMK |
33 | add \irqnr,\irqnr,#IRQ_IOP331_DMA0_EOT | ||
34 | 1001: | 33 | 1001: |
35 | .endm | 34 | .endm |
diff --git a/include/asm-arm/arch-iop33x/irqs.h b/include/asm-arm/arch-iop33x/irqs.h index 45856a12815..2e3ade3b5ff 100644 --- a/include/asm-arm/arch-iop33x/irqs.h +++ b/include/asm-arm/arch-iop33x/irqs.h | |||
@@ -15,78 +15,46 @@ | |||
15 | /* | 15 | /* |
16 | * IOP80331 chipset interrupts | 16 | * IOP80331 chipset interrupts |
17 | */ | 17 | */ |
18 | #define IOP331_IRQ_OFS 0 | 18 | #define IRQ_IOP331_DMA0_EOT 0 |
19 | #define IOP331_IRQ(x) (IOP331_IRQ_OFS + (x)) | 19 | #define IRQ_IOP331_DMA0_EOC 1 |
20 | #define IRQ_IOP331_DMA1_EOT 2 | ||
21 | #define IRQ_IOP331_DMA1_EOC 3 | ||
22 | #define IRQ_IOP331_AA_EOT 6 | ||
23 | #define IRQ_IOP331_AA_EOC 7 | ||
24 | #define IRQ_IOP331_TIMER0 8 | ||
25 | #define IRQ_IOP331_TIMER1 9 | ||
26 | #define IRQ_IOP331_I2C_0 10 | ||
27 | #define IRQ_IOP331_I2C_1 11 | ||
28 | #define IRQ_IOP331_MSG 12 | ||
29 | #define IRQ_IOP331_MSGIBQ 13 | ||
30 | #define IRQ_IOP331_ATU_BIST 14 | ||
31 | #define IRQ_IOP331_PERFMON 15 | ||
32 | #define IRQ_IOP331_CORE_PMU 16 | ||
33 | #define IRQ_IOP331_XINT0 24 | ||
34 | #define IRQ_IOP331_XINT1 25 | ||
35 | #define IRQ_IOP331_XINT2 26 | ||
36 | #define IRQ_IOP331_XINT3 27 | ||
37 | #define IRQ_IOP331_XINT8 32 | ||
38 | #define IRQ_IOP331_XINT9 33 | ||
39 | #define IRQ_IOP331_XINT10 34 | ||
40 | #define IRQ_IOP331_XINT11 35 | ||
41 | #define IRQ_IOP331_XINT12 36 | ||
42 | #define IRQ_IOP331_XINT13 37 | ||
43 | #define IRQ_IOP331_XINT14 38 | ||
44 | #define IRQ_IOP331_XINT15 39 | ||
45 | #define IRQ_IOP331_UART0 51 | ||
46 | #define IRQ_IOP331_UART1 52 | ||
47 | #define IRQ_IOP331_PBIE 53 | ||
48 | #define IRQ_IOP331_ATU_CRW 54 | ||
49 | #define IRQ_IOP331_ATU_ERR 55 | ||
50 | #define IRQ_IOP331_MCU_ERR 56 | ||
51 | #define IRQ_IOP331_DMA0_ERR 57 | ||
52 | #define IRQ_IOP331_DMA1_ERR 58 | ||
53 | #define IRQ_IOP331_AA_ERR 60 | ||
54 | #define IRQ_IOP331_MSG_ERR 62 | ||
55 | #define IRQ_IOP331_HPI 63 | ||
20 | 56 | ||
21 | /* | 57 | #define NR_IRQS 64 |
22 | * On IRQ or FIQ register | ||
23 | */ | ||
24 | #define IRQ_IOP331_DMA0_EOT IOP331_IRQ(0) | ||
25 | #define IRQ_IOP331_DMA0_EOC IOP331_IRQ(1) | ||
26 | #define IRQ_IOP331_DMA1_EOT IOP331_IRQ(2) | ||
27 | #define IRQ_IOP331_DMA1_EOC IOP331_IRQ(3) | ||
28 | #define IRQ_IOP331_RSVD_4 IOP331_IRQ(4) | ||
29 | #define IRQ_IOP331_RSVD_5 IOP331_IRQ(5) | ||
30 | #define IRQ_IOP331_AA_EOT IOP331_IRQ(6) | ||
31 | #define IRQ_IOP331_AA_EOC IOP331_IRQ(7) | ||
32 | #define IRQ_IOP331_TIMER0 IOP331_IRQ(8) | ||
33 | #define IRQ_IOP331_TIMER1 IOP331_IRQ(9) | ||
34 | #define IRQ_IOP331_I2C_0 IOP331_IRQ(10) | ||
35 | #define IRQ_IOP331_I2C_1 IOP331_IRQ(11) | ||
36 | #define IRQ_IOP331_MSG IOP331_IRQ(12) | ||
37 | #define IRQ_IOP331_MSGIBQ IOP331_IRQ(13) | ||
38 | #define IRQ_IOP331_ATU_BIST IOP331_IRQ(14) | ||
39 | #define IRQ_IOP331_PERFMON IOP331_IRQ(15) | ||
40 | #define IRQ_IOP331_CORE_PMU IOP331_IRQ(16) | ||
41 | #define IRQ_IOP331_RSVD_17 IOP331_IRQ(17) | ||
42 | #define IRQ_IOP331_RSVD_18 IOP331_IRQ(18) | ||
43 | #define IRQ_IOP331_RSVD_19 IOP331_IRQ(19) | ||
44 | #define IRQ_IOP331_RSVD_20 IOP331_IRQ(20) | ||
45 | #define IRQ_IOP331_RSVD_21 IOP331_IRQ(21) | ||
46 | #define IRQ_IOP331_RSVD_22 IOP331_IRQ(22) | ||
47 | #define IRQ_IOP331_RSVD_23 IOP331_IRQ(23) | ||
48 | #define IRQ_IOP331_XINT0 IOP331_IRQ(24) | ||
49 | #define IRQ_IOP331_XINT1 IOP331_IRQ(25) | ||
50 | #define IRQ_IOP331_XINT2 IOP331_IRQ(26) | ||
51 | #define IRQ_IOP331_XINT3 IOP331_IRQ(27) | ||
52 | #define IRQ_IOP331_RSVD_28 IOP331_IRQ(28) | ||
53 | #define IRQ_IOP331_RSVD_29 IOP331_IRQ(29) | ||
54 | #define IRQ_IOP331_RSVD_30 IOP331_IRQ(30) | ||
55 | #define IRQ_IOP331_RSVD_31 IOP331_IRQ(31) | ||
56 | #define IRQ_IOP331_XINT8 IOP331_IRQ(32) // 0 | ||
57 | #define IRQ_IOP331_XINT9 IOP331_IRQ(33) // 1 | ||
58 | #define IRQ_IOP331_XINT10 IOP331_IRQ(34) // 2 | ||
59 | #define IRQ_IOP331_XINT11 IOP331_IRQ(35) // 3 | ||
60 | #define IRQ_IOP331_XINT12 IOP331_IRQ(36) // 4 | ||
61 | #define IRQ_IOP331_XINT13 IOP331_IRQ(37) // 5 | ||
62 | #define IRQ_IOP331_XINT14 IOP331_IRQ(38) // 6 | ||
63 | #define IRQ_IOP331_XINT15 IOP331_IRQ(39) // 7 | ||
64 | #define IRQ_IOP331_RSVD_40 IOP331_IRQ(40) // 8 | ||
65 | #define IRQ_IOP331_RSVD_41 IOP331_IRQ(41) // 9 | ||
66 | #define IRQ_IOP331_RSVD_42 IOP331_IRQ(42) // 10 | ||
67 | #define IRQ_IOP331_RSVD_43 IOP331_IRQ(43) // 11 | ||
68 | #define IRQ_IOP331_RSVD_44 IOP331_IRQ(44) // 12 | ||
69 | #define IRQ_IOP331_RSVD_45 IOP331_IRQ(45) // 13 | ||
70 | #define IRQ_IOP331_RSVD_46 IOP331_IRQ(46) // 14 | ||
71 | #define IRQ_IOP331_RSVD_47 IOP331_IRQ(47) // 15 | ||
72 | #define IRQ_IOP331_RSVD_48 IOP331_IRQ(48) // 16 | ||
73 | #define IRQ_IOP331_RSVD_49 IOP331_IRQ(49) // 17 | ||
74 | #define IRQ_IOP331_RSVD_50 IOP331_IRQ(50) // 18 | ||
75 | #define IRQ_IOP331_UART0 IOP331_IRQ(51) // 19 | ||
76 | #define IRQ_IOP331_UART1 IOP331_IRQ(52) // 20 | ||
77 | #define IRQ_IOP331_PBIE IOP331_IRQ(53) // 21 | ||
78 | #define IRQ_IOP331_ATU_CRW IOP331_IRQ(54) // 22 | ||
79 | #define IRQ_IOP331_ATU_ERR IOP331_IRQ(55) // 23 | ||
80 | #define IRQ_IOP331_MCU_ERR IOP331_IRQ(56) // 24 | ||
81 | #define IRQ_IOP331_DMA0_ERR IOP331_IRQ(57) // 25 | ||
82 | #define IRQ_IOP331_DMA1_ERR IOP331_IRQ(58) // 26 | ||
83 | #define IRQ_IOP331_RSVD_59 IOP331_IRQ(59) // 27 | ||
84 | #define IRQ_IOP331_AA_ERR IOP331_IRQ(60) // 28 | ||
85 | #define IRQ_IOP331_RSVD_61 IOP331_IRQ(61) // 29 | ||
86 | #define IRQ_IOP331_MSG_ERR IOP331_IRQ(62) // 30 | ||
87 | #define IRQ_IOP331_HPI IOP331_IRQ(63) // 31 | ||
88 | |||
89 | #define NR_IRQS (IOP331_IRQ(63) + 1) | ||
90 | 58 | ||
91 | 59 | ||
92 | /* | 60 | /* |