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authorAndrew Victor <andrew@sanpeople.com>2007-02-05 05:42:07 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-02-08 09:50:56 -0500
commit9d0412680e6c7b685ee466842047bcfb924d6dc5 (patch)
treec79300964ef1aca5d24571696f95e76b37c14679 /include/asm-arm/arch-at91/at91sam9260_matrix.h
parenta93d48cc6019f84394b31d10c0d830a3b71696be (diff)
[ARM] 4124/1: Rename mach-at91rm9200 and arch-at91rm9200 directories
Now that Linux includes support for the Atmel AT91SAM9260 and AT91SAM9261 processors in addition to the original Atmel AT91RM9200 (with support for more AT91 processors pending), the "mach-at91rm9200" and "arch-at91rm9200" directories should be renamed to indicate their more generic nature. The following git commands should be run BEFORE applying this patch: git-mv arch/arm/mach-at91rm9200 arch/arm/mach-at91 git-mv include/asm-arm/arch-at91rm9200 include/asm-arm/arch-at91 Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-at91/at91sam9260_matrix.h')
-rw-r--r--include/asm-arm/arch-at91/at91sam9260_matrix.h78
1 files changed, 78 insertions, 0 deletions
diff --git a/include/asm-arm/arch-at91/at91sam9260_matrix.h b/include/asm-arm/arch-at91/at91sam9260_matrix.h
new file mode 100644
index 00000000000..573e97a47d2
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91sam9260_matrix.h
@@ -0,0 +1,78 @@
1/*
2 * include/asm-arm/arch-at91/at91sam9260_matrix.h
3 *
4 * Memory Controllers (MATRIX, EBI) - System peripherals registers.
5 * Based on AT91SAM9260 datasheet revision B.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#ifndef AT91SAM9260_MATRIX_H
14#define AT91SAM9260_MATRIX_H
15
16#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
17#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
18#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
19#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
20#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
21#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x04) /* Master Configuration Register 5 */
22#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
23#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
24#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
25#define AT91_MATRIX_ULBT_FOUR (2 << 0)
26#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
27#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
28
29#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
30#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
31#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
32#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
33#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
34#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
35#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
36#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
37#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
38#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
39#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
40#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
41#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
42#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
43
44#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
45#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
46#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
47#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
48#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
49#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
50#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
51#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
52#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
53#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
54#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
55
56#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
57#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
58#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
59
60#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */
61#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
62#define AT91_MATRIX_CS1A_SMC (0 << 1)
63#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
64#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
65#define AT91_MATRIX_CS3A_SMC (0 << 3)
66#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
67#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
68#define AT91_MATRIX_CS4A_SMC (0 << 4)
69#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
70#define AT91_MATRIX_CS5A (1 << 5 ) /* Chip Select 5 Assignment */
71#define AT91_MATRIX_CS5A_SMC (0 << 5)
72#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
73#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
74#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
75#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
76#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
77
78#endif