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authorZhao Yakui <yakui.zhao@intel.com>2009-10-08 23:39:43 -0400
committerEric Anholt <eric@anholt.net>2009-11-05 17:47:12 -0500
commitd0c3b04ae953fd3bf69f9b1430c22608d2d3b90d (patch)
treea1393beb84fb2af282b2c8be8e212dffc2352de1 /drivers
parent3e0f27ed75369298176abdf2fbe59116b6587a56 (diff)
drm/i915: Replace DRM_DEBUG with DRM_DEBUG_KMS in DVO output code.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/i915/dvo_ch7017.c9
-rw-r--r--drivers/gpu/drm/i915/dvo_ch7xxx.c16
-rw-r--r--drivers/gpu/drm/i915/dvo_ivch.c37
-rw-r--r--drivers/gpu/drm/i915/dvo_sil164.c20
-rw-r--r--drivers/gpu/drm/i915/dvo_tfp410.c34
5 files changed, 61 insertions, 55 deletions
diff --git a/drivers/gpu/drm/i915/dvo_ch7017.c b/drivers/gpu/drm/i915/dvo_ch7017.c
index 621815b531d..1184c14ba87 100644
--- a/drivers/gpu/drm/i915/dvo_ch7017.c
+++ b/drivers/gpu/drm/i915/dvo_ch7017.c
@@ -249,7 +249,8 @@ static bool ch7017_init(struct intel_dvo_device *dvo,
249 if (val != CH7017_DEVICE_ID_VALUE && 249 if (val != CH7017_DEVICE_ID_VALUE &&
250 val != CH7018_DEVICE_ID_VALUE && 250 val != CH7018_DEVICE_ID_VALUE &&
251 val != CH7019_DEVICE_ID_VALUE) { 251 val != CH7019_DEVICE_ID_VALUE) {
252 DRM_DEBUG("ch701x not detected, got %d: from %s Slave %d.\n", 252 DRM_DEBUG_KMS("ch701x not detected, got %d: from %s "
253 "Slave %d.\n",
253 val, i2cbus->adapter.name,dvo->slave_addr); 254 val, i2cbus->adapter.name,dvo->slave_addr);
254 goto fail; 255 goto fail;
255 } 256 }
@@ -284,7 +285,7 @@ static void ch7017_mode_set(struct intel_dvo_device *dvo,
284 uint8_t horizontal_active_pixel_output, vertical_active_line_output; 285 uint8_t horizontal_active_pixel_output, vertical_active_line_output;
285 uint8_t active_input_line_output; 286 uint8_t active_input_line_output;
286 287
287 DRM_DEBUG("Registers before mode setting\n"); 288 DRM_DEBUG_KMS("Registers before mode setting\n");
288 ch7017_dump_regs(dvo); 289 ch7017_dump_regs(dvo);
289 290
290 /* LVDS PLL settings from page 75 of 7017-7017ds.pdf*/ 291 /* LVDS PLL settings from page 75 of 7017-7017ds.pdf*/
@@ -346,7 +347,7 @@ static void ch7017_mode_set(struct intel_dvo_device *dvo,
346 /* Turn the LVDS back on with new settings. */ 347 /* Turn the LVDS back on with new settings. */
347 ch7017_write(dvo, CH7017_LVDS_POWER_DOWN, lvds_power_down); 348 ch7017_write(dvo, CH7017_LVDS_POWER_DOWN, lvds_power_down);
348 349
349 DRM_DEBUG("Registers after mode setting\n"); 350 DRM_DEBUG_KMS("Registers after mode setting\n");
350 ch7017_dump_regs(dvo); 351 ch7017_dump_regs(dvo);
351} 352}
352 353
@@ -386,7 +387,7 @@ static void ch7017_dump_regs(struct intel_dvo_device *dvo)
386#define DUMP(reg) \ 387#define DUMP(reg) \
387do { \ 388do { \
388 ch7017_read(dvo, reg, &val); \ 389 ch7017_read(dvo, reg, &val); \
389 DRM_DEBUG(#reg ": %02x\n", val); \ 390 DRM_DEBUG_KMS(#reg ": %02x\n", val); \
390} while (0) 391} while (0)
391 392
392 DUMP(CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT); 393 DUMP(CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT);
diff --git a/drivers/gpu/drm/i915/dvo_ch7xxx.c b/drivers/gpu/drm/i915/dvo_ch7xxx.c
index a9b89628968..d56ff5cc22b 100644
--- a/drivers/gpu/drm/i915/dvo_ch7xxx.c
+++ b/drivers/gpu/drm/i915/dvo_ch7xxx.c
@@ -152,7 +152,7 @@ static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch)
152 }; 152 };
153 153
154 if (!ch7xxx->quiet) { 154 if (!ch7xxx->quiet) {
155 DRM_DEBUG("Unable to read register 0x%02x from %s:%02x.\n", 155 DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n",
156 addr, i2cbus->adapter.name, dvo->slave_addr); 156 addr, i2cbus->adapter.name, dvo->slave_addr);
157 } 157 }
158 return false; 158 return false;
@@ -179,7 +179,7 @@ static bool ch7xxx_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch)
179 return true; 179 return true;
180 180
181 if (!ch7xxx->quiet) { 181 if (!ch7xxx->quiet) {
182 DRM_DEBUG("Unable to write register 0x%02x to %s:%d.\n", 182 DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
183 addr, i2cbus->adapter.name, dvo->slave_addr); 183 addr, i2cbus->adapter.name, dvo->slave_addr);
184 } 184 }
185 185
@@ -207,7 +207,8 @@ static bool ch7xxx_init(struct intel_dvo_device *dvo,
207 207
208 name = ch7xxx_get_id(vendor); 208 name = ch7xxx_get_id(vendor);
209 if (!name) { 209 if (!name) {
210 DRM_DEBUG("ch7xxx not detected; got 0x%02x from %s slave %d.\n", 210 DRM_DEBUG_KMS("ch7xxx not detected; got 0x%02x from %s "
211 "slave %d.\n",
211 vendor, adapter->name, dvo->slave_addr); 212 vendor, adapter->name, dvo->slave_addr);
212 goto out; 213 goto out;
213 } 214 }
@@ -217,13 +218,14 @@ static bool ch7xxx_init(struct intel_dvo_device *dvo,
217 goto out; 218 goto out;
218 219
219 if (device != CH7xxx_DID) { 220 if (device != CH7xxx_DID) {
220 DRM_DEBUG("ch7xxx not detected; got 0x%02x from %s slave %d.\n", 221 DRM_DEBUG_KMS("ch7xxx not detected; got 0x%02x from %s "
222 "slave %d.\n",
221 vendor, adapter->name, dvo->slave_addr); 223 vendor, adapter->name, dvo->slave_addr);
222 goto out; 224 goto out;
223 } 225 }
224 226
225 ch7xxx->quiet = false; 227 ch7xxx->quiet = false;
226 DRM_DEBUG("Detected %s chipset, vendor/device ID 0x%02x/0x%02x\n", 228 DRM_DEBUG_KMS("Detected %s chipset, vendor/device ID 0x%02x/0x%02x\n",
227 name, vendor, device); 229 name, vendor, device);
228 return true; 230 return true;
229out: 231out:
@@ -315,8 +317,8 @@ static void ch7xxx_dump_regs(struct intel_dvo_device *dvo)
315 317
316 for (i = 0; i < CH7xxx_NUM_REGS; i++) { 318 for (i = 0; i < CH7xxx_NUM_REGS; i++) {
317 if ((i % 8) == 0 ) 319 if ((i % 8) == 0 )
318 DRM_DEBUG("\n %02X: ", i); 320 DRM_LOG_KMS("\n %02X: ", i);
319 DRM_DEBUG("%02X ", ch7xxx->mode_reg.regs[i]); 321 DRM_LOG_KMS("%02X ", ch7xxx->mode_reg.regs[i]);
320 } 322 }
321} 323}
322 324
diff --git a/drivers/gpu/drm/i915/dvo_ivch.c b/drivers/gpu/drm/i915/dvo_ivch.c
index aa176f9921f..24169e528f0 100644
--- a/drivers/gpu/drm/i915/dvo_ivch.c
+++ b/drivers/gpu/drm/i915/dvo_ivch.c
@@ -202,7 +202,8 @@ static bool ivch_read(struct intel_dvo_device *dvo, int addr, uint16_t *data)
202 }; 202 };
203 203
204 if (!priv->quiet) { 204 if (!priv->quiet) {
205 DRM_DEBUG("Unable to read register 0x%02x from %s:%02x.\n", 205 DRM_DEBUG_KMS("Unable to read register 0x%02x from "
206 "%s:%02x.\n",
206 addr, i2cbus->adapter.name, dvo->slave_addr); 207 addr, i2cbus->adapter.name, dvo->slave_addr);
207 } 208 }
208 return false; 209 return false;
@@ -230,7 +231,7 @@ static bool ivch_write(struct intel_dvo_device *dvo, int addr, uint16_t data)
230 return true; 231 return true;
231 232
232 if (!priv->quiet) { 233 if (!priv->quiet) {
233 DRM_DEBUG("Unable to write register 0x%02x to %s:%d.\n", 234 DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
234 addr, i2cbus->adapter.name, dvo->slave_addr); 235 addr, i2cbus->adapter.name, dvo->slave_addr);
235 } 236 }
236 237
@@ -261,7 +262,7 @@ static bool ivch_init(struct intel_dvo_device *dvo,
261 * the address it's responding on. 262 * the address it's responding on.
262 */ 263 */
263 if ((temp & VR00_BASE_ADDRESS_MASK) != dvo->slave_addr) { 264 if ((temp & VR00_BASE_ADDRESS_MASK) != dvo->slave_addr) {
264 DRM_DEBUG("ivch detect failed due to address mismatch " 265 DRM_DEBUG_KMS("ivch detect failed due to address mismatch "
265 "(%d vs %d)\n", 266 "(%d vs %d)\n",
266 (temp & VR00_BASE_ADDRESS_MASK), dvo->slave_addr); 267 (temp & VR00_BASE_ADDRESS_MASK), dvo->slave_addr);
267 goto out; 268 goto out;
@@ -367,41 +368,41 @@ static void ivch_dump_regs(struct intel_dvo_device *dvo)
367 uint16_t val; 368 uint16_t val;
368 369
369 ivch_read(dvo, VR00, &val); 370 ivch_read(dvo, VR00, &val);
370 DRM_DEBUG("VR00: 0x%04x\n", val); 371 DRM_LOG_KMS("VR00: 0x%04x\n", val);
371 ivch_read(dvo, VR01, &val); 372 ivch_read(dvo, VR01, &val);
372 DRM_DEBUG("VR01: 0x%04x\n", val); 373 DRM_LOG_KMS("VR01: 0x%04x\n", val);
373 ivch_read(dvo, VR30, &val); 374 ivch_read(dvo, VR30, &val);
374 DRM_DEBUG("VR30: 0x%04x\n", val); 375 DRM_LOG_KMS("VR30: 0x%04x\n", val);
375 ivch_read(dvo, VR40, &val); 376 ivch_read(dvo, VR40, &val);
376 DRM_DEBUG("VR40: 0x%04x\n", val); 377 DRM_LOG_KMS("VR40: 0x%04x\n", val);
377 378
378 /* GPIO registers */ 379 /* GPIO registers */
379 ivch_read(dvo, VR80, &val); 380 ivch_read(dvo, VR80, &val);
380 DRM_DEBUG("VR80: 0x%04x\n", val); 381 DRM_LOG_KMS("VR80: 0x%04x\n", val);
381 ivch_read(dvo, VR81, &val); 382 ivch_read(dvo, VR81, &val);
382 DRM_DEBUG("VR81: 0x%04x\n", val); 383 DRM_LOG_KMS("VR81: 0x%04x\n", val);
383 ivch_read(dvo, VR82, &val); 384 ivch_read(dvo, VR82, &val);
384 DRM_DEBUG("VR82: 0x%04x\n", val); 385 DRM_LOG_KMS("VR82: 0x%04x\n", val);
385 ivch_read(dvo, VR83, &val); 386 ivch_read(dvo, VR83, &val);
386 DRM_DEBUG("VR83: 0x%04x\n", val); 387 DRM_LOG_KMS("VR83: 0x%04x\n", val);
387 ivch_read(dvo, VR84, &val); 388 ivch_read(dvo, VR84, &val);
388 DRM_DEBUG("VR84: 0x%04x\n", val); 389 DRM_LOG_KMS("VR84: 0x%04x\n", val);
389 ivch_read(dvo, VR85, &val); 390 ivch_read(dvo, VR85, &val);
390 DRM_DEBUG("VR85: 0x%04x\n", val); 391 DRM_LOG_KMS("VR85: 0x%04x\n", val);
391 ivch_read(dvo, VR86, &val); 392 ivch_read(dvo, VR86, &val);
392 DRM_DEBUG("VR86: 0x%04x\n", val); 393 DRM_LOG_KMS("VR86: 0x%04x\n", val);
393 ivch_read(dvo, VR87, &val); 394 ivch_read(dvo, VR87, &val);
394 DRM_DEBUG("VR87: 0x%04x\n", val); 395 DRM_LOG_KMS("VR87: 0x%04x\n", val);
395 ivch_read(dvo, VR88, &val); 396 ivch_read(dvo, VR88, &val);
396 DRM_DEBUG("VR88: 0x%04x\n", val); 397 DRM_LOG_KMS("VR88: 0x%04x\n", val);
397 398
398 /* Scratch register 0 - AIM Panel type */ 399 /* Scratch register 0 - AIM Panel type */
399 ivch_read(dvo, VR8E, &val); 400 ivch_read(dvo, VR8E, &val);
400 DRM_DEBUG("VR8E: 0x%04x\n", val); 401 DRM_LOG_KMS("VR8E: 0x%04x\n", val);
401 402
402 /* Scratch register 1 - Status register */ 403 /* Scratch register 1 - Status register */
403 ivch_read(dvo, VR8F, &val); 404 ivch_read(dvo, VR8F, &val);
404 DRM_DEBUG("VR8F: 0x%04x\n", val); 405 DRM_LOG_KMS("VR8F: 0x%04x\n", val);
405} 406}
406 407
407static void ivch_save(struct intel_dvo_device *dvo) 408static void ivch_save(struct intel_dvo_device *dvo)
diff --git a/drivers/gpu/drm/i915/dvo_sil164.c b/drivers/gpu/drm/i915/dvo_sil164.c
index e1c1f7341e5..0001c13f0a8 100644
--- a/drivers/gpu/drm/i915/dvo_sil164.c
+++ b/drivers/gpu/drm/i915/dvo_sil164.c
@@ -105,7 +105,7 @@ static bool sil164_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch)
105 }; 105 };
106 106
107 if (!sil->quiet) { 107 if (!sil->quiet) {
108 DRM_DEBUG("Unable to read register 0x%02x from %s:%02x.\n", 108 DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n",
109 addr, i2cbus->adapter.name, dvo->slave_addr); 109 addr, i2cbus->adapter.name, dvo->slave_addr);
110 } 110 }
111 return false; 111 return false;
@@ -131,7 +131,7 @@ static bool sil164_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch)
131 return true; 131 return true;
132 132
133 if (!sil->quiet) { 133 if (!sil->quiet) {
134 DRM_DEBUG("Unable to write register 0x%02x to %s:%d.\n", 134 DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
135 addr, i2cbus->adapter.name, dvo->slave_addr); 135 addr, i2cbus->adapter.name, dvo->slave_addr);
136 } 136 }
137 137
@@ -158,7 +158,7 @@ static bool sil164_init(struct intel_dvo_device *dvo,
158 goto out; 158 goto out;
159 159
160 if (ch != (SIL164_VID & 0xff)) { 160 if (ch != (SIL164_VID & 0xff)) {
161 DRM_DEBUG("sil164 not detected got %d: from %s Slave %d.\n", 161 DRM_DEBUG_KMS("sil164 not detected got %d: from %s Slave %d.\n",
162 ch, adapter->name, dvo->slave_addr); 162 ch, adapter->name, dvo->slave_addr);
163 goto out; 163 goto out;
164 } 164 }
@@ -167,13 +167,13 @@ static bool sil164_init(struct intel_dvo_device *dvo,
167 goto out; 167 goto out;
168 168
169 if (ch != (SIL164_DID & 0xff)) { 169 if (ch != (SIL164_DID & 0xff)) {
170 DRM_DEBUG("sil164 not detected got %d: from %s Slave %d.\n", 170 DRM_DEBUG_KMS("sil164 not detected got %d: from %s Slave %d.\n",
171 ch, adapter->name, dvo->slave_addr); 171 ch, adapter->name, dvo->slave_addr);
172 goto out; 172 goto out;
173 } 173 }
174 sil->quiet = false; 174 sil->quiet = false;
175 175
176 DRM_DEBUG("init sil164 dvo controller successfully!\n"); 176 DRM_DEBUG_KMS("init sil164 dvo controller successfully!\n");
177 return true; 177 return true;
178 178
179out: 179out:
@@ -241,15 +241,15 @@ static void sil164_dump_regs(struct intel_dvo_device *dvo)
241 uint8_t val; 241 uint8_t val;
242 242
243 sil164_readb(dvo, SIL164_FREQ_LO, &val); 243 sil164_readb(dvo, SIL164_FREQ_LO, &val);
244 DRM_DEBUG("SIL164_FREQ_LO: 0x%02x\n", val); 244 DRM_LOG_KMS("SIL164_FREQ_LO: 0x%02x\n", val);
245 sil164_readb(dvo, SIL164_FREQ_HI, &val); 245 sil164_readb(dvo, SIL164_FREQ_HI, &val);
246 DRM_DEBUG("SIL164_FREQ_HI: 0x%02x\n", val); 246 DRM_LOG_KMS("SIL164_FREQ_HI: 0x%02x\n", val);
247 sil164_readb(dvo, SIL164_REG8, &val); 247 sil164_readb(dvo, SIL164_REG8, &val);
248 DRM_DEBUG("SIL164_REG8: 0x%02x\n", val); 248 DRM_LOG_KMS("SIL164_REG8: 0x%02x\n", val);
249 sil164_readb(dvo, SIL164_REG9, &val); 249 sil164_readb(dvo, SIL164_REG9, &val);
250 DRM_DEBUG("SIL164_REG9: 0x%02x\n", val); 250 DRM_LOG_KMS("SIL164_REG9: 0x%02x\n", val);
251 sil164_readb(dvo, SIL164_REGC, &val); 251 sil164_readb(dvo, SIL164_REGC, &val);
252 DRM_DEBUG("SIL164_REGC: 0x%02x\n", val); 252 DRM_LOG_KMS("SIL164_REGC: 0x%02x\n", val);
253} 253}
254 254
255static void sil164_save(struct intel_dvo_device *dvo) 255static void sil164_save(struct intel_dvo_device *dvo)
diff --git a/drivers/gpu/drm/i915/dvo_tfp410.c b/drivers/gpu/drm/i915/dvo_tfp410.c
index 9ecc907384e..c7c391bc116 100644
--- a/drivers/gpu/drm/i915/dvo_tfp410.c
+++ b/drivers/gpu/drm/i915/dvo_tfp410.c
@@ -130,7 +130,7 @@ static bool tfp410_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch)
130 }; 130 };
131 131
132 if (!tfp->quiet) { 132 if (!tfp->quiet) {
133 DRM_DEBUG("Unable to read register 0x%02x from %s:%02x.\n", 133 DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n",
134 addr, i2cbus->adapter.name, dvo->slave_addr); 134 addr, i2cbus->adapter.name, dvo->slave_addr);
135 } 135 }
136 return false; 136 return false;
@@ -156,7 +156,7 @@ static bool tfp410_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch)
156 return true; 156 return true;
157 157
158 if (!tfp->quiet) { 158 if (!tfp->quiet) {
159 DRM_DEBUG("Unable to write register 0x%02x to %s:%d.\n", 159 DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
160 addr, i2cbus->adapter.name, dvo->slave_addr); 160 addr, i2cbus->adapter.name, dvo->slave_addr);
161 } 161 }
162 162
@@ -191,13 +191,15 @@ static bool tfp410_init(struct intel_dvo_device *dvo,
191 tfp->quiet = true; 191 tfp->quiet = true;
192 192
193 if ((id = tfp410_getid(dvo, TFP410_VID_LO)) != TFP410_VID) { 193 if ((id = tfp410_getid(dvo, TFP410_VID_LO)) != TFP410_VID) {
194 DRM_DEBUG("tfp410 not detected got VID %X: from %s Slave %d.\n", 194 DRM_DEBUG_KMS("tfp410 not detected got VID %X: from %s "
195 "Slave %d.\n",
195 id, adapter->name, dvo->slave_addr); 196 id, adapter->name, dvo->slave_addr);
196 goto out; 197 goto out;
197 } 198 }
198 199
199 if ((id = tfp410_getid(dvo, TFP410_DID_LO)) != TFP410_DID) { 200 if ((id = tfp410_getid(dvo, TFP410_DID_LO)) != TFP410_DID) {
200 DRM_DEBUG("tfp410 not detected got DID %X: from %s Slave %d.\n", 201 DRM_DEBUG_KMS("tfp410 not detected got DID %X: from %s "
202 "Slave %d.\n",
201 id, adapter->name, dvo->slave_addr); 203 id, adapter->name, dvo->slave_addr);
202 goto out; 204 goto out;
203 } 205 }
@@ -262,33 +264,33 @@ static void tfp410_dump_regs(struct intel_dvo_device *dvo)
262 uint8_t val, val2; 264 uint8_t val, val2;
263 265
264 tfp410_readb(dvo, TFP410_REV, &val); 266 tfp410_readb(dvo, TFP410_REV, &val);
265 DRM_DEBUG("TFP410_REV: 0x%02X\n", val); 267 DRM_LOG_KMS("TFP410_REV: 0x%02X\n", val);
266 tfp410_readb(dvo, TFP410_CTL_1, &val); 268 tfp410_readb(dvo, TFP410_CTL_1, &val);
267 DRM_DEBUG("TFP410_CTL1: 0x%02X\n", val); 269 DRM_LOG_KMS("TFP410_CTL1: 0x%02X\n", val);
268 tfp410_readb(dvo, TFP410_CTL_2, &val); 270 tfp410_readb(dvo, TFP410_CTL_2, &val);
269 DRM_DEBUG("TFP410_CTL2: 0x%02X\n", val); 271 DRM_LOG_KMS("TFP410_CTL2: 0x%02X\n", val);
270 tfp410_readb(dvo, TFP410_CTL_3, &val); 272 tfp410_readb(dvo, TFP410_CTL_3, &val);
271 DRM_DEBUG("TFP410_CTL3: 0x%02X\n", val); 273 DRM_LOG_KMS("TFP410_CTL3: 0x%02X\n", val);
272 tfp410_readb(dvo, TFP410_USERCFG, &val); 274 tfp410_readb(dvo, TFP410_USERCFG, &val);
273 DRM_DEBUG("TFP410_USERCFG: 0x%02X\n", val); 275 DRM_LOG_KMS("TFP410_USERCFG: 0x%02X\n", val);
274 tfp410_readb(dvo, TFP410_DE_DLY, &val); 276 tfp410_readb(dvo, TFP410_DE_DLY, &val);
275 DRM_DEBUG("TFP410_DE_DLY: 0x%02X\n", val); 277 DRM_LOG_KMS("TFP410_DE_DLY: 0x%02X\n", val);
276 tfp410_readb(dvo, TFP410_DE_CTL, &val); 278 tfp410_readb(dvo, TFP410_DE_CTL, &val);
277 DRM_DEBUG("TFP410_DE_CTL: 0x%02X\n", val); 279 DRM_LOG_KMS("TFP410_DE_CTL: 0x%02X\n", val);
278 tfp410_readb(dvo, TFP410_DE_TOP, &val); 280 tfp410_readb(dvo, TFP410_DE_TOP, &val);
279 DRM_DEBUG("TFP410_DE_TOP: 0x%02X\n", val); 281 DRM_LOG_KMS("TFP410_DE_TOP: 0x%02X\n", val);
280 tfp410_readb(dvo, TFP410_DE_CNT_LO, &val); 282 tfp410_readb(dvo, TFP410_DE_CNT_LO, &val);
281 tfp410_readb(dvo, TFP410_DE_CNT_HI, &val2); 283 tfp410_readb(dvo, TFP410_DE_CNT_HI, &val2);
282 DRM_DEBUG("TFP410_DE_CNT: 0x%02X%02X\n", val2, val); 284 DRM_LOG_KMS("TFP410_DE_CNT: 0x%02X%02X\n", val2, val);
283 tfp410_readb(dvo, TFP410_DE_LIN_LO, &val); 285 tfp410_readb(dvo, TFP410_DE_LIN_LO, &val);
284 tfp410_readb(dvo, TFP410_DE_LIN_HI, &val2); 286 tfp410_readb(dvo, TFP410_DE_LIN_HI, &val2);
285 DRM_DEBUG("TFP410_DE_LIN: 0x%02X%02X\n", val2, val); 287 DRM_LOG_KMS("TFP410_DE_LIN: 0x%02X%02X\n", val2, val);
286 tfp410_readb(dvo, TFP410_H_RES_LO, &val); 288 tfp410_readb(dvo, TFP410_H_RES_LO, &val);
287 tfp410_readb(dvo, TFP410_H_RES_HI, &val2); 289 tfp410_readb(dvo, TFP410_H_RES_HI, &val2);
288 DRM_DEBUG("TFP410_H_RES: 0x%02X%02X\n", val2, val); 290 DRM_LOG_KMS("TFP410_H_RES: 0x%02X%02X\n", val2, val);
289 tfp410_readb(dvo, TFP410_V_RES_LO, &val); 291 tfp410_readb(dvo, TFP410_V_RES_LO, &val);
290 tfp410_readb(dvo, TFP410_V_RES_HI, &val2); 292 tfp410_readb(dvo, TFP410_V_RES_HI, &val2);
291 DRM_DEBUG("TFP410_V_RES: 0x%02X%02X\n", val2, val); 293 DRM_LOG_KMS("TFP410_V_RES: 0x%02X%02X\n", val2, val);
292} 294}
293 295
294static void tfp410_save(struct intel_dvo_device *dvo) 296static void tfp410_save(struct intel_dvo_device *dvo)