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authorJuuso Oikarinen <juuso.oikarinen@nokia.com>2009-10-13 05:47:44 -0400
committerJohn W. Linville <linville@tuxdriver.com>2009-10-27 16:48:09 -0400
commit8a08048a3722a6b52c2b34e070c4e6a32ad19e0d (patch)
tree0c50ad78a5e1ab5bfdc2604369514579a51d3b08 /drivers
parent47fab7d589d46d87a5dbfd7f2ddd53deccfad504 (diff)
wl1271: Move default FW config struct away from stack
Move the default FW config into a module global static variable, instead of being a stack variable. Signed-off-by: Juuso Oikarinen <juuso.oikarinen@nokia.com> Reviewed-by: Luciano Coelho <luciano.coelho@nokia.com> Signed-off-by: Luciano Coelho <luciano.coelho@nokia.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/wireless/wl12xx/wl1271_main.c535
1 files changed, 264 insertions, 271 deletions
diff --git a/drivers/net/wireless/wl12xx/wl1271_main.c b/drivers/net/wireless/wl12xx/wl1271_main.c
index 0b17b056f3f..eba38dff871 100644
--- a/drivers/net/wireless/wl12xx/wl1271_main.c
+++ b/drivers/net/wireless/wl12xx/wl1271_main.c
@@ -46,289 +46,282 @@
46#include "wl1271_cmd.h" 46#include "wl1271_cmd.h"
47#include "wl1271_boot.h" 47#include "wl1271_boot.h"
48 48
49static void wl1271_conf_init(struct wl1271 *wl) 49static struct conf_drv_settings default_conf = {
50{ 50 .sg = {
51 struct conf_drv_settings conf = { 51 .per_threshold = 7500,
52 .sg = { 52 .max_scan_compensation_time = 120000,
53 .per_threshold = 7500, 53 .nfs_sample_interval = 400,
54 .max_scan_compensation_time = 120000, 54 .load_ratio = 50,
55 .nfs_sample_interval = 400, 55 .auto_ps_mode = 0,
56 .load_ratio = 50, 56 .probe_req_compensation = 170,
57 .auto_ps_mode = 0, 57 .scan_window_compensation = 50,
58 .probe_req_compensation = 170, 58 .antenna_config = 0,
59 .scan_window_compensation = 50, 59 .beacon_miss_threshold = 60,
60 .antenna_config = 0, 60 .rate_adaptation_threshold = CONF_HW_BIT_RATE_12MBPS,
61 .beacon_miss_threshold = 60, 61 .rate_adaptation_snr = 0
62 .rate_adaptation_threshold = CONF_HW_BIT_RATE_12MBPS, 62 },
63 .rate_adaptation_snr = 0 63 .rx = {
64 }, 64 .rx_msdu_life_time = 512000,
65 .rx = { 65 .packet_detection_threshold = 0,
66 .rx_msdu_life_time = 512000, 66 .ps_poll_timeout = 15,
67 .packet_detection_threshold = 0, 67 .upsd_timeout = 15,
68 .ps_poll_timeout = 15, 68 .rts_threshold = 2347,
69 .upsd_timeout = 15, 69 .rx_cca_threshold = 0xFFEF,
70 .rts_threshold = 2347, 70 .irq_blk_threshold = 0,
71 .rx_cca_threshold = 0xFFEF, 71 .irq_pkt_threshold = USHORT_MAX,
72 .irq_blk_threshold = 0, 72 .irq_timeout = 5,
73 .irq_pkt_threshold = USHORT_MAX, 73 .queue_type = CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
74 .irq_timeout = 5, 74 },
75 .queue_type = CONF_RX_QUEUE_TYPE_LOW_PRIORITY, 75 .tx = {
76 .tx_energy_detection = 0,
77 .rc_conf = {
78 .enabled_rates = CONF_TX_RATE_MASK_UNSPECIFIED,
79 .short_retry_limit = 10,
80 .long_retry_limit = 10,
81 .aflags = 0
76 }, 82 },
77 .tx = { 83 .ac_conf_count = 4,
78 .tx_energy_detection = 0, 84 .ac_conf = {
79 .rc_conf = { 85 [0] = {
80 .enabled_rates = 86 .ac = CONF_TX_AC_BE,
81 CONF_TX_RATE_MASK_UNSPECIFIED, 87 .cw_min = 15,
82 .short_retry_limit = 10, 88 .cw_max = 63,
83 .long_retry_limit = 10, 89 .aifsn = 3,
84 .aflags = 0 90 .tx_op_limit = 0,
91 },
92 [1] = {
93 .ac = CONF_TX_AC_BK,
94 .cw_min = 15,
95 .cw_max = 63,
96 .aifsn = 7,
97 .tx_op_limit = 0,
85 }, 98 },
86 .ac_conf_count = 4, 99 [2] = {
87 .ac_conf = { 100 .ac = CONF_TX_AC_VI,
88 [0] = { 101 .cw_min = 15,
89 .ac = CONF_TX_AC_BE, 102 .cw_max = 63,
90 .cw_min = 15, 103 .aifsn = CONF_TX_AIFS_PIFS,
91 .cw_max = 63, 104 .tx_op_limit = 3008,
92 .aifsn = 3,
93 .tx_op_limit = 0,
94 },
95 [1] = {
96 .ac = CONF_TX_AC_BK,
97 .cw_min = 15,
98 .cw_max = 63,
99 .aifsn = 7,
100 .tx_op_limit = 0,
101 },
102 [2] = {
103 .ac = CONF_TX_AC_VI,
104 .cw_min = 15,
105 .cw_max = 63,
106 .aifsn = CONF_TX_AIFS_PIFS,
107 .tx_op_limit = 3008,
108 },
109 [3] = {
110 .ac = CONF_TX_AC_VO,
111 .cw_min = 15,
112 .cw_max = 63,
113 .aifsn = CONF_TX_AIFS_PIFS,
114 .tx_op_limit = 1504,
115 },
116 }, 105 },
117 .tid_conf_count = 7, 106 [3] = {
118 .tid_conf = { 107 .ac = CONF_TX_AC_VO,
119 [0] = { 108 .cw_min = 15,
120 .queue_id = 0, 109 .cw_max = 63,
121 .channel_type = CONF_CHANNEL_TYPE_DCF, 110 .aifsn = CONF_TX_AIFS_PIFS,
122 .tsid = CONF_TX_AC_BE, 111 .tx_op_limit = 1504,
123 .ps_scheme = CONF_PS_SCHEME_LEGACY,
124 .ack_policy = CONF_ACK_POLICY_LEGACY,
125 .apsd_conf = {0, 0},
126 },
127 [1] = {
128 .queue_id = 1,
129 .channel_type = CONF_CHANNEL_TYPE_DCF,
130 .tsid = CONF_TX_AC_BE,
131 .ps_scheme = CONF_PS_SCHEME_LEGACY,
132 .ack_policy = CONF_ACK_POLICY_LEGACY,
133 .apsd_conf = {0, 0},
134 },
135 [2] = {
136 .queue_id = 2,
137 .channel_type = CONF_CHANNEL_TYPE_DCF,
138 .tsid = CONF_TX_AC_BE,
139 .ps_scheme = CONF_PS_SCHEME_LEGACY,
140 .ack_policy = CONF_ACK_POLICY_LEGACY,
141 .apsd_conf = {0, 0},
142 },
143 [3] = {
144 .queue_id = 3,
145 .channel_type = CONF_CHANNEL_TYPE_DCF,
146 .tsid = CONF_TX_AC_BE,
147 .ps_scheme = CONF_PS_SCHEME_LEGACY,
148 .ack_policy = CONF_ACK_POLICY_LEGACY,
149 .apsd_conf = {0, 0},
150 },
151 [4] = {
152 .queue_id = 4,
153 .channel_type = CONF_CHANNEL_TYPE_DCF,
154 .tsid = CONF_TX_AC_BE,
155 .ps_scheme = CONF_PS_SCHEME_LEGACY,
156 .ack_policy = CONF_ACK_POLICY_LEGACY,
157 .apsd_conf = {0, 0},
158 },
159 [5] = {
160 .queue_id = 5,
161 .channel_type = CONF_CHANNEL_TYPE_DCF,
162 .tsid = CONF_TX_AC_BE,
163 .ps_scheme = CONF_PS_SCHEME_LEGACY,
164 .ack_policy = CONF_ACK_POLICY_LEGACY,
165 .apsd_conf = {0, 0},
166 },
167 [6] = {
168 .queue_id = 6,
169 .channel_type = CONF_CHANNEL_TYPE_DCF,
170 .tsid = CONF_TX_AC_BE,
171 .ps_scheme = CONF_PS_SCHEME_LEGACY,
172 .ack_policy = CONF_ACK_POLICY_LEGACY,
173 .apsd_conf = {0, 0},
174 }
175 }, 112 },
176 .frag_threshold = IEEE80211_MAX_FRAG_THRESHOLD,
177 .tx_compl_timeout = 5,
178 .tx_compl_threshold = 5
179 }, 113 },
180 .conn = { 114 .tid_conf_count = 7,
181 .wake_up_event = CONF_WAKE_UP_EVENT_DTIM, 115 .tid_conf = {
182 .listen_interval = 0, 116 [0] = {
183 .bcn_filt_mode = CONF_BCN_FILT_MODE_ENABLED, 117 .queue_id = 0,
184 .bcn_filt_ie_count = 1, 118 .channel_type = CONF_CHANNEL_TYPE_DCF,
185 .bcn_filt_ie = { 119 .tsid = CONF_TX_AC_BE,
186 [0] = { 120 .ps_scheme = CONF_PS_SCHEME_LEGACY,
187 .ie = WLAN_EID_CHANNEL_SWITCH, 121 .ack_policy = CONF_ACK_POLICY_LEGACY,
188 .rule = 122 .apsd_conf = {0, 0},
189 CONF_BCN_RULE_PASS_ON_APPEARANCE, 123 },
190 } 124 [1] = {
125 .queue_id = 1,
126 .channel_type = CONF_CHANNEL_TYPE_DCF,
127 .tsid = CONF_TX_AC_BE,
128 .ps_scheme = CONF_PS_SCHEME_LEGACY,
129 .ack_policy = CONF_ACK_POLICY_LEGACY,
130 .apsd_conf = {0, 0},
191 }, 131 },
192 .synch_fail_thold = 5, 132 [2] = {
193 .bss_lose_timeout = 100, 133 .queue_id = 2,
194 .beacon_rx_timeout = 10000, 134 .channel_type = CONF_CHANNEL_TYPE_DCF,
195 .broadcast_timeout = 20000, 135 .tsid = CONF_TX_AC_BE,
196 .rx_broadcast_in_ps = 1, 136 .ps_scheme = CONF_PS_SCHEME_LEGACY,
197 .ps_poll_threshold = 4, 137 .ack_policy = CONF_ACK_POLICY_LEGACY,
198 .sig_trigger_count = 2, 138 .apsd_conf = {0, 0},
199 .sig_trigger = {
200 [0] = {
201 .threshold = -75,
202 .pacing = 500,
203 .metric = CONF_TRIG_METRIC_RSSI_BEACON,
204 .type = CONF_TRIG_EVENT_TYPE_EDGE,
205 .direction = CONF_TRIG_EVENT_DIR_LOW,
206 .hysteresis = 2,
207 .index = 0,
208 .enable = 1
209 },
210 [1] = {
211 .threshold = -75,
212 .pacing = 500,
213 .metric = CONF_TRIG_METRIC_RSSI_BEACON,
214 .type = CONF_TRIG_EVENT_TYPE_EDGE,
215 .direction = CONF_TRIG_EVENT_DIR_HIGH,
216 .hysteresis = 2,
217 .index = 1,
218 .enable = 1
219 }
220 }, 139 },
221 .sig_weights = { 140 [3] = {
222 .rssi_bcn_avg_weight = 10, 141 .queue_id = 3,
223 .rssi_pkt_avg_weight = 10, 142 .channel_type = CONF_CHANNEL_TYPE_DCF,
224 .snr_bcn_avg_weight = 10, 143 .tsid = CONF_TX_AC_BE,
225 .snr_pkt_avg_weight = 10 144 .ps_scheme = CONF_PS_SCHEME_LEGACY,
145 .ack_policy = CONF_ACK_POLICY_LEGACY,
146 .apsd_conf = {0, 0},
147 },
148 [4] = {
149 .queue_id = 4,
150 .channel_type = CONF_CHANNEL_TYPE_DCF,
151 .tsid = CONF_TX_AC_BE,
152 .ps_scheme = CONF_PS_SCHEME_LEGACY,
153 .ack_policy = CONF_ACK_POLICY_LEGACY,
154 .apsd_conf = {0, 0},
155 },
156 [5] = {
157 .queue_id = 5,
158 .channel_type = CONF_CHANNEL_TYPE_DCF,
159 .tsid = CONF_TX_AC_BE,
160 .ps_scheme = CONF_PS_SCHEME_LEGACY,
161 .ack_policy = CONF_ACK_POLICY_LEGACY,
162 .apsd_conf = {0, 0},
163 },
164 [6] = {
165 .queue_id = 6,
166 .channel_type = CONF_CHANNEL_TYPE_DCF,
167 .tsid = CONF_TX_AC_BE,
168 .ps_scheme = CONF_PS_SCHEME_LEGACY,
169 .ack_policy = CONF_ACK_POLICY_LEGACY,
170 .apsd_conf = {0, 0},
226 } 171 }
227 }, 172 },
228 .init = { 173 .frag_threshold = IEEE80211_MAX_FRAG_THRESHOLD,
229 .sr_err_tbl = { 174 .tx_compl_timeout = 5,
230 [0] = { 175 .tx_compl_threshold = 5
231 .len = 7, 176 },
232 .upper_limit = 0x03, 177 .conn = {
233 .values = { 178 .wake_up_event = CONF_WAKE_UP_EVENT_DTIM,
234 0x18, 0x10, 0x05, 0xfb, 179 .listen_interval = 0,
235 0xf0, 0xe8, 0x00 } 180 .bcn_filt_mode = CONF_BCN_FILT_MODE_ENABLED,
236 }, 181 .bcn_filt_ie_count = 1,
237 [1] = { 182 .bcn_filt_ie = {
238 .len = 7, 183 [0] = {
239 .upper_limit = 0x03, 184 .ie = WLAN_EID_CHANNEL_SWITCH,
240 .values = { 185 .rule = CONF_BCN_RULE_PASS_ON_APPEARANCE,
241 0x18, 0x10, 0x05, 0xf6, 186 }
242 0xf0, 0xe8, 0x00 } 187 },
243 }, 188 .synch_fail_thold = 5,
244 [2] = { 189 .bss_lose_timeout = 100,
245 .len = 7, 190 .beacon_rx_timeout = 10000,
246 .upper_limit = 0x03, 191 .broadcast_timeout = 20000,
247 .values = { 192 .rx_broadcast_in_ps = 1,
248 0x18, 0x10, 0x05, 0xfb, 193 .ps_poll_threshold = 4,
249 0xf0, 0xe8, 0x00 } 194 .sig_trigger_count = 2,
250 } 195 .sig_trigger = {
196 [0] = {
197 .threshold = -75,
198 .pacing = 500,
199 .metric = CONF_TRIG_METRIC_RSSI_BEACON,
200 .type = CONF_TRIG_EVENT_TYPE_EDGE,
201 .direction = CONF_TRIG_EVENT_DIR_LOW,
202 .hysteresis = 2,
203 .index = 0,
204 .enable = 1
251 }, 205 },
252 .sr_enable = 1, 206 [1] = {
253 .genparam = { 207 .threshold = -75,
254 /* 208 .pacing = 500,
255 * FIXME: The correct value CONF_REF_CLK_38_4_E 209 .metric = CONF_TRIG_METRIC_RSSI_BEACON,
256 * causes the firmware to crash on boot. 210 .type = CONF_TRIG_EVENT_TYPE_EDGE,
257 * The value 5 apparently is an 211 .direction = CONF_TRIG_EVENT_DIR_HIGH,
258 * unnoficial XTAL configuration of the 212 .hysteresis = 2,
259 * same frequency, which appears to work. 213 .index = 1,
260 */ 214 .enable = 1
261 .ref_clk = 5, 215 }
262 .settling_time = 5, 216 },
263 .clk_valid_on_wakeup = 0, 217 .sig_weights = {
264 .dc2dcmode = 0, 218 .rssi_bcn_avg_weight = 10,
265 .single_dual_band = 0, 219 .rssi_pkt_avg_weight = 10,
266 .tx_bip_fem_autodetect = 0, 220 .snr_bcn_avg_weight = 10,
267 .tx_bip_fem_manufacturer = 1, 221 .snr_pkt_avg_weight = 10
268 .settings = 1, 222 }
223 },
224 .init = {
225 .sr_err_tbl = {
226 [0] = {
227 .len = 7,
228 .upper_limit = 0x03,
229 .values = {
230 0x18, 0x10, 0x05, 0xfb, 0xf0, 0xe8,
231 0x00 }
232 },
233 [1] = {
234 .len = 7,
235 .upper_limit = 0x03,
236 .values = {
237 0x18, 0x10, 0x05, 0xf6, 0xf0, 0xe8,
238 0x00 }
269 }, 239 },
270 .radioparam = { 240 [2] = {
271 /* FIXME: 5GHz values unset! */ 241 .len = 7,
272 .rx_trace_loss = 10, 242 .upper_limit = 0x03,
273 .tx_trace_loss = 10, 243 .values = {
274 .rx_rssi_and_proc_compens = { 244 0x18, 0x10, 0x05, 0xfb, 0xf0, 0xe8,
275 0xec, 0xf6, 0x00, 0x0c, 0x18, 0xf8, 245 0x00 }
276 0xfc, 0x00, 0x08, 0x10, 0xf0, 0xf8,
277 0x00, 0x0a, 0x14 },
278 .rx_trace_loss_5 = {
279 0, 0, 0, 0, 0, 0, 0 },
280 .tx_trace_loss_5 = {
281 0, 0, 0, 0, 0, 0, 0 },
282 .rx_rssi_and_proc_compens_5 = {
283 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
284 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
285 0x00, 0x00, 0x00 },
286 .tx_ref_pd_voltage = 0x24e,
287 .tx_ref_power = 0x78,
288 .tx_offset_db = 0x0,
289 .tx_rate_limits_normal = {
290 0x1e, 0x1f, 0x22, 0x24, 0x28, 0x29 },
291 .tx_rate_limits_degraded = {
292 0x1b, 0x1c, 0x1e, 0x20, 0x24, 0x25 },
293 .tx_channel_limits_11b = {
294 0x22, 0x50, 0x50, 0x50, 0x50, 0x50,
295 0x50, 0x50, 0x50, 0x50, 0x22, 0x50,
296 0x22, 0x50 },
297 .tx_channel_limits_ofdm = {
298 0x20, 0x50, 0x50, 0x50, 0x50, 0x50,
299 0x50, 0x50, 0x50, 0x50, 0x20, 0x50,
300 0x20, 0x50 },
301 .tx_pdv_rate_offsets = {
302 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
303 .tx_ibias = {
304 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x27 },
305 .rx_fem_insertion_loss = 0x14,
306 .tx_ref_pd_voltage_5 = {
307 0, 0, 0, 0, 0, 0, 0 },
308 .tx_ref_power_5 = {
309 0, 0, 0, 0, 0, 0, 0 },
310 .tx_offset_db_5 = {
311 0, 0, 0, 0, 0, 0, 0 },
312 .tx_rate_limits_normal_5 = {
313 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
314 .tx_rate_limits_degraded_5 = {
315 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
316 .tx_channel_limits_ofdm_5 = {
317 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
318 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
319 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
320 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
321 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
322 0x00, 0x00, 0x00, 0x00, 0x00},
323 .tx_pdv_rate_offsets_5 = {
324 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
325 .tx_ibias_5 = {
326 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
327 .rx_fem_insertion_loss_5 = {
328 0, 0, 0, 0, 0, 0, 0 }
329 } 246 }
247 },
248 .sr_enable = 1,
249 .genparam = {
250 /*
251 * FIXME: The correct value CONF_REF_CLK_38_4_E
252 * causes the firmware to crash on boot.
253 * The value 5 apparently is an
254 * unnoficial XTAL configuration of the
255 * same frequency, which appears to work.
256 */
257 .ref_clk = 5,
258 .settling_time = 5,
259 .clk_valid_on_wakeup = 0,
260 .dc2dcmode = 0,
261 .single_dual_band = 0,
262 .tx_bip_fem_autodetect = 0,
263 .tx_bip_fem_manufacturer = 1,
264 .settings = 1,
265 },
266 .radioparam = {
267 /* FIXME: 5GHz values unset! */
268 .rx_trace_loss = 10,
269 .tx_trace_loss = 10,
270 .rx_rssi_and_proc_compens = {
271 0xec, 0xf6, 0x00, 0x0c, 0x18, 0xf8,
272 0xfc, 0x00, 0x08, 0x10, 0xf0, 0xf8,
273 0x00, 0x0a, 0x14 },
274 .rx_trace_loss_5 = { 0, 0, 0, 0, 0, 0, 0 },
275 .tx_trace_loss_5 = { 0, 0, 0, 0, 0, 0, 0 },
276 .rx_rssi_and_proc_compens_5 = {
277 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
278 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
279 0x00, 0x00, 0x00 },
280 .tx_ref_pd_voltage = 0x24e,
281 .tx_ref_power = 0x78,
282 .tx_offset_db = 0x0,
283 .tx_rate_limits_normal = {
284 0x1e, 0x1f, 0x22, 0x24, 0x28, 0x29 },
285 .tx_rate_limits_degraded = {
286 0x1b, 0x1c, 0x1e, 0x20, 0x24, 0x25 },
287 .tx_channel_limits_11b = {
288 0x22, 0x50, 0x50, 0x50, 0x50, 0x50,
289 0x50, 0x50, 0x50, 0x50, 0x22, 0x50,
290 0x22, 0x50 },
291 .tx_channel_limits_ofdm = {
292 0x20, 0x50, 0x50, 0x50, 0x50, 0x50,
293 0x50, 0x50, 0x50, 0x50, 0x20, 0x50,
294 0x20, 0x50 },
295 .tx_pdv_rate_offsets = {
296 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
297 .tx_ibias = {
298 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x27 },
299 .rx_fem_insertion_loss = 0x14,
300 .tx_ref_pd_voltage_5 = { 0, 0, 0, 0, 0, 0, 0 },
301 .tx_ref_power_5 = { 0, 0, 0, 0, 0, 0, 0 },
302 .tx_offset_db_5 = {0, 0, 0, 0, 0, 0, 0 },
303 .tx_rate_limits_normal_5 = {
304 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
305 .tx_rate_limits_degraded_5 = {
306 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
307 .tx_channel_limits_ofdm_5 = {
308 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
309 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
310 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
311 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
312 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
313 0x00, 0x00, 0x00, 0x00, 0x00},
314 .tx_pdv_rate_offsets_5 = {
315 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
316 .tx_ibias_5 = {
317 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
318 .rx_fem_insertion_loss_5 = { 0, 0, 0, 0, 0, 0, 0 }
330 } 319 }
331 }; 320 }
321};
322
323static void wl1271_conf_init(struct wl1271 *wl)
324{
332 325
333 /* 326 /*
334 * This function applies the default configuration to the driver. This 327 * This function applies the default configuration to the driver. This
@@ -341,7 +334,7 @@ static void wl1271_conf_init(struct wl1271 *wl)
341 */ 334 */
342 335
343 /* apply driver default configuration */ 336 /* apply driver default configuration */
344 memcpy(&wl->conf, &conf, sizeof(conf)); 337 memcpy(&wl->conf, &default_conf, sizeof(default_conf));
345} 338}
346 339
347 340