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authorBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2008-06-15 15:00:22 -0400
committerBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2008-06-15 15:00:22 -0400
commit80a65fc5ee04497e6c28bdaefc44d375b19c4a79 (patch)
tree047ca04916fe19acc330ea4a8e7c06f372512714 /drivers
parent810253d44bc92b44b66cd9944b579de54c0cd3ff (diff)
opti621: add PIO 4 support
* Add PIO 4 support. While at it: * Use a single struct ide_port_info instance for OPTi621 and OPTi621X. Based on a bugreport from Juergen Kosel & inspired by pata_opti.c code. Tested-by: Juergen Kosel <juergen.kosel@gmx.de> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/ide/pci/opti621.c46
1 files changed, 14 insertions, 32 deletions
diff --git a/drivers/ide/pci/opti621.c b/drivers/ide/pci/opti621.c
index 8c715b7a85d..725c80508d9 100644
--- a/drivers/ide/pci/opti621.c
+++ b/drivers/ide/pci/opti621.c
@@ -90,16 +90,6 @@
90 90
91#include <asm/io.h> 91#include <asm/io.h>
92 92
93//#define OPTI621_MAX_PIO 3
94/* In fact, I do not have any PIO 4 drive
95 * (address: 25 ns, data: 70 ns, recovery: 35 ns),
96 * but OPTi 82C621 is programmable and it can do (minimal values):
97 * on 40MHz PCI bus (pulse 25 ns):
98 * address: 25 ns, data: 25 ns, recovery: 50 ns;
99 * on 20MHz PCI bus (pulse 50 ns):
100 * address: 50 ns, data: 50 ns, recovery: 100 ns.
101 */
102
103#define READ_REG 0 /* index of Read cycle timing register */ 93#define READ_REG 0 /* index of Read cycle timing register */
104#define WRITE_REG 1 /* index of Write cycle timing register */ 94#define WRITE_REG 1 /* index of Write cycle timing register */
105#define CNTRL_REG 3 /* index of Control register */ 95#define CNTRL_REG 3 /* index of Control register */
@@ -150,13 +140,13 @@ static void opti621_set_pio_mode(ide_drive_t *drive, const u8 pio)
150 u8 tim, misc, addr_pio = pio, clk; 140 u8 tim, misc, addr_pio = pio, clk;
151 141
152 /* DRDY is default 2 (by OPTi Databook) */ 142 /* DRDY is default 2 (by OPTi Databook) */
153 static const u8 addr_timings[2][4] = { 143 static const u8 addr_timings[2][5] = {
154 { 0x20, 0x10, 0x00, 0x00 }, /* 33 MHz */ 144 { 0x20, 0x10, 0x00, 0x00, 0x00 }, /* 33 MHz */
155 { 0x10, 0x10, 0x00, 0x00 }, /* 25 MHz */ 145 { 0x10, 0x10, 0x00, 0x00, 0x00 }, /* 25 MHz */
156 }; 146 };
157 static const u8 data_rec_timings[2][4] = { 147 static const u8 data_rec_timings[2][5] = {
158 { 0x5b, 0x45, 0x32, 0x21 }, /* 33 MHz */ 148 { 0x5b, 0x45, 0x32, 0x21, 0x20 }, /* 33 MHz */
159 { 0x48, 0x34, 0x21, 0x10 } /* 25 MHz */ 149 { 0x48, 0x34, 0x21, 0x10, 0x10 } /* 25 MHz */
160 }; 150 };
161 151
162 drive->drive_data = XFER_PIO_0 + pio; 152 drive->drive_data = XFER_PIO_0 + pio;
@@ -209,30 +199,22 @@ static const struct ide_port_ops opti621_port_ops = {
209 .set_pio_mode = opti621_set_pio_mode, 199 .set_pio_mode = opti621_set_pio_mode,
210}; 200};
211 201
212static const struct ide_port_info opti621_chipsets[] __devinitdata = { 202static const struct ide_port_info opti621_chipset __devinitdata = {
213 { /* 0 */ 203 .name = "OPTI621/X",
214 .name = "OPTI621", 204 .enablebits = { {0x45, 0x80, 0x00}, {0x40, 0x08, 0x00} },
215 .enablebits = { {0x45, 0x80, 0x00}, {0x40, 0x08, 0x00} }, 205 .port_ops = &opti621_port_ops,
216 .port_ops = &opti621_port_ops, 206 .host_flags = IDE_HFLAG_NO_DMA,
217 .host_flags = IDE_HFLAG_NO_DMA, 207 .pio_mask = ATA_PIO4,
218 .pio_mask = ATA_PIO3,
219 }, { /* 1 */
220 .name = "OPTI621X",
221 .enablebits = { {0x45, 0x80, 0x00}, {0x40, 0x08, 0x00} },
222 .port_ops = &opti621_port_ops,
223 .host_flags = IDE_HFLAG_NO_DMA,
224 .pio_mask = ATA_PIO3,
225 }
226}; 208};
227 209
228static int __devinit opti621_init_one(struct pci_dev *dev, const struct pci_device_id *id) 210static int __devinit opti621_init_one(struct pci_dev *dev, const struct pci_device_id *id)
229{ 211{
230 return ide_setup_pci_device(dev, &opti621_chipsets[id->driver_data]); 212 return ide_setup_pci_device(dev, &opti621_chipset);
231} 213}
232 214
233static const struct pci_device_id opti621_pci_tbl[] = { 215static const struct pci_device_id opti621_pci_tbl[] = {
234 { PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C621), 0 }, 216 { PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C621), 0 },
235 { PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C825), 1 }, 217 { PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C825), 0 },
236 { 0, }, 218 { 0, },
237}; 219};
238MODULE_DEVICE_TABLE(pci, opti621_pci_tbl); 220MODULE_DEVICE_TABLE(pci, opti621_pci_tbl);