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authorTimur Tabi <timur@freescale.com>2009-01-11 03:25:21 -0500
committerDavid S. Miller <davem@davemloft.net>2009-01-11 03:25:21 -0500
commit3bc53427e4f323d4f33f70477fc32c1c2ae7fb5d (patch)
tree7b8580791d7ee2d5f019d8bd81881953e8de0dab /drivers
parent649274d993212e7c23c0cb734572c2311c200872 (diff)
ucc_geth: use correct UCCE macros
The UCC Event Register (UCCE) already has unambigous macro definitions in qe.h, so we should not be defining our own in the UCC Ethernet driver. Removed unused local variable 'dev' from ucc_geth_poll(), which fixes a warning caused by commit 908a7a16b852ffd618a9127be8d62432182d81b4 ("net: Remove unused netdev arg from some NAPI interfaces."). Replaced in_be/out_be pairs with setbits32 or clrbits32, where applicable. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/ucc_geth.c128
-rw-r--r--drivers/net/ucc_geth.h114
2 files changed, 68 insertions, 174 deletions
diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c
index 7d5a1303e30..11441225bf4 100644
--- a/drivers/net/ucc_geth.c
+++ b/drivers/net/ucc_geth.c
@@ -442,40 +442,30 @@ static void magic_packet_detection_enable(struct ucc_geth_private *ugeth)
442{ 442{
443 struct ucc_fast_private *uccf; 443 struct ucc_fast_private *uccf;
444 struct ucc_geth __iomem *ug_regs; 444 struct ucc_geth __iomem *ug_regs;
445 u32 maccfg2, uccm;
446 445
447 uccf = ugeth->uccf; 446 uccf = ugeth->uccf;
448 ug_regs = ugeth->ug_regs; 447 ug_regs = ugeth->ug_regs;
449 448
450 /* Enable interrupts for magic packet detection */ 449 /* Enable interrupts for magic packet detection */
451 uccm = in_be32(uccf->p_uccm); 450 setbits32(uccf->p_uccm, UCC_GETH_UCCE_MPD);
452 uccm |= UCCE_MPD;
453 out_be32(uccf->p_uccm, uccm);
454 451
455 /* Enable magic packet detection */ 452 /* Enable magic packet detection */
456 maccfg2 = in_be32(&ug_regs->maccfg2); 453 setbits32(&ug_regs->maccfg2, MACCFG2_MPE);
457 maccfg2 |= MACCFG2_MPE;
458 out_be32(&ug_regs->maccfg2, maccfg2);
459} 454}
460 455
461static void magic_packet_detection_disable(struct ucc_geth_private *ugeth) 456static void magic_packet_detection_disable(struct ucc_geth_private *ugeth)
462{ 457{
463 struct ucc_fast_private *uccf; 458 struct ucc_fast_private *uccf;
464 struct ucc_geth __iomem *ug_regs; 459 struct ucc_geth __iomem *ug_regs;
465 u32 maccfg2, uccm;
466 460
467 uccf = ugeth->uccf; 461 uccf = ugeth->uccf;
468 ug_regs = ugeth->ug_regs; 462 ug_regs = ugeth->ug_regs;
469 463
470 /* Disable interrupts for magic packet detection */ 464 /* Disable interrupts for magic packet detection */
471 uccm = in_be32(uccf->p_uccm); 465 clrbits32(uccf->p_uccm, UCC_GETH_UCCE_MPD);
472 uccm &= ~UCCE_MPD;
473 out_be32(uccf->p_uccm, uccm);
474 466
475 /* Disable magic packet detection */ 467 /* Disable magic packet detection */
476 maccfg2 = in_be32(&ug_regs->maccfg2); 468 clrbits32(&ug_regs->maccfg2, MACCFG2_MPE);
477 maccfg2 &= ~MACCFG2_MPE;
478 out_be32(&ug_regs->maccfg2, maccfg2);
479} 469}
480#endif /* MAGIC_PACKET */ 470#endif /* MAGIC_PACKET */
481 471
@@ -585,7 +575,8 @@ static void get_statistics(struct ucc_geth_private *ugeth,
585 575
586 /* Hardware only if user handed pointer and driver actually 576 /* Hardware only if user handed pointer and driver actually
587 gathers hardware statistics */ 577 gathers hardware statistics */
588 if (hardware_statistics && (in_be32(&uf_regs->upsmr) & UPSMR_HSE)) { 578 if (hardware_statistics &&
579 (in_be32(&uf_regs->upsmr) & UCC_GETH_UPSMR_HSE)) {
589 hardware_statistics->tx64 = in_be32(&ug_regs->tx64); 580 hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
590 hardware_statistics->tx127 = in_be32(&ug_regs->tx127); 581 hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
591 hardware_statistics->tx255 = in_be32(&ug_regs->tx255); 582 hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
@@ -1181,9 +1172,7 @@ int init_flow_control_params(u32 automatic_flow_control_mode,
1181 out_be32(uempr_register, value); 1172 out_be32(uempr_register, value);
1182 1173
1183 /* Set UPSMR register */ 1174 /* Set UPSMR register */
1184 value = in_be32(upsmr_register); 1175 setbits32(upsmr_register, automatic_flow_control_mode);
1185 value |= automatic_flow_control_mode;
1186 out_be32(upsmr_register, value);
1187 1176
1188 value = in_be32(maccfg1_register); 1177 value = in_be32(maccfg1_register);
1189 if (rx_flow_control_enable) 1178 if (rx_flow_control_enable)
@@ -1200,14 +1189,11 @@ static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
1200 u32 __iomem *upsmr_register, 1189 u32 __iomem *upsmr_register,
1201 u16 __iomem *uescr_register) 1190 u16 __iomem *uescr_register)
1202{ 1191{
1203 u32 upsmr_value = 0;
1204 u16 uescr_value = 0; 1192 u16 uescr_value = 0;
1193
1205 /* Enable hardware statistics gathering if requested */ 1194 /* Enable hardware statistics gathering if requested */
1206 if (enable_hardware_statistics) { 1195 if (enable_hardware_statistics)
1207 upsmr_value = in_be32(upsmr_register); 1196 setbits32(upsmr_register, UCC_GETH_UPSMR_HSE);
1208 upsmr_value |= UPSMR_HSE;
1209 out_be32(upsmr_register, upsmr_value);
1210 }
1211 1197
1212 /* Clear hardware statistics counters */ 1198 /* Clear hardware statistics counters */
1213 uescr_value = in_be16(uescr_register); 1199 uescr_value = in_be16(uescr_register);
@@ -1233,23 +1219,17 @@ static int init_firmware_statistics_gathering_mode(int
1233{ 1219{
1234 /* Note: this function does not check if */ 1220 /* Note: this function does not check if */
1235 /* the parameters it receives are NULL */ 1221 /* the parameters it receives are NULL */
1236 u16 temoder_value;
1237 u32 remoder_value;
1238 1222
1239 if (enable_tx_firmware_statistics) { 1223 if (enable_tx_firmware_statistics) {
1240 out_be32(tx_rmon_base_ptr, 1224 out_be32(tx_rmon_base_ptr,
1241 tx_firmware_statistics_structure_address); 1225 tx_firmware_statistics_structure_address);
1242 temoder_value = in_be16(temoder_register); 1226 setbits16(temoder_register, TEMODER_TX_RMON_STATISTICS_ENABLE);
1243 temoder_value |= TEMODER_TX_RMON_STATISTICS_ENABLE;
1244 out_be16(temoder_register, temoder_value);
1245 } 1227 }
1246 1228
1247 if (enable_rx_firmware_statistics) { 1229 if (enable_rx_firmware_statistics) {
1248 out_be32(rx_rmon_base_ptr, 1230 out_be32(rx_rmon_base_ptr,
1249 rx_firmware_statistics_structure_address); 1231 rx_firmware_statistics_structure_address);
1250 remoder_value = in_be32(remoder_register); 1232 setbits32(remoder_register, REMODER_RX_RMON_STATISTICS_ENABLE);
1251 remoder_value |= REMODER_RX_RMON_STATISTICS_ENABLE;
1252 out_be32(remoder_register, remoder_value);
1253 } 1233 }
1254 1234
1255 return 0; 1235 return 0;
@@ -1316,15 +1296,12 @@ static int init_check_frame_length_mode(int length_check,
1316static int init_preamble_length(u8 preamble_length, 1296static int init_preamble_length(u8 preamble_length,
1317 u32 __iomem *maccfg2_register) 1297 u32 __iomem *maccfg2_register)
1318{ 1298{
1319 u32 value = 0;
1320
1321 if ((preamble_length < 3) || (preamble_length > 7)) 1299 if ((preamble_length < 3) || (preamble_length > 7))
1322 return -EINVAL; 1300 return -EINVAL;
1323 1301
1324 value = in_be32(maccfg2_register); 1302 clrsetbits_be32(maccfg2_register, MACCFG2_PREL_MASK,
1325 value &= ~MACCFG2_PREL_MASK; 1303 preamble_length << MACCFG2_PREL_SHIFT);
1326 value |= (preamble_length << MACCFG2_PREL_SHIFT); 1304
1327 out_be32(maccfg2_register, value);
1328 return 0; 1305 return 0;
1329} 1306}
1330 1307
@@ -1337,19 +1314,19 @@ static int init_rx_parameters(int reject_broadcast,
1337 value = in_be32(upsmr_register); 1314 value = in_be32(upsmr_register);
1338 1315
1339 if (reject_broadcast) 1316 if (reject_broadcast)
1340 value |= UPSMR_BRO; 1317 value |= UCC_GETH_UPSMR_BRO;
1341 else 1318 else
1342 value &= ~UPSMR_BRO; 1319 value &= ~UCC_GETH_UPSMR_BRO;
1343 1320
1344 if (receive_short_frames) 1321 if (receive_short_frames)
1345 value |= UPSMR_RSH; 1322 value |= UCC_GETH_UPSMR_RSH;
1346 else 1323 else
1347 value &= ~UPSMR_RSH; 1324 value &= ~UCC_GETH_UPSMR_RSH;
1348 1325
1349 if (promiscuous) 1326 if (promiscuous)
1350 value |= UPSMR_PRO; 1327 value |= UCC_GETH_UPSMR_PRO;
1351 else 1328 else
1352 value &= ~UPSMR_PRO; 1329 value &= ~UCC_GETH_UPSMR_PRO;
1353 1330
1354 out_be32(upsmr_register, value); 1331 out_be32(upsmr_register, value);
1355 1332
@@ -1410,26 +1387,27 @@ static int adjust_enet_interface(struct ucc_geth_private *ugeth)
1410 1387
1411 /* Set UPSMR */ 1388 /* Set UPSMR */
1412 upsmr = in_be32(&uf_regs->upsmr); 1389 upsmr = in_be32(&uf_regs->upsmr);
1413 upsmr &= ~(UPSMR_RPM | UPSMR_R10M | UPSMR_TBIM | UPSMR_RMM); 1390 upsmr &= ~(UCC_GETH_UPSMR_RPM | UCC_GETH_UPSMR_R10M |
1391 UCC_GETH_UPSMR_TBIM | UCC_GETH_UPSMR_RMM);
1414 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) || 1392 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1415 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) || 1393 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1416 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) || 1394 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1417 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) || 1395 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1418 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) || 1396 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1419 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { 1397 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1420 upsmr |= UPSMR_RPM; 1398 upsmr |= UCC_GETH_UPSMR_RPM;
1421 switch (ugeth->max_speed) { 1399 switch (ugeth->max_speed) {
1422 case SPEED_10: 1400 case SPEED_10:
1423 upsmr |= UPSMR_R10M; 1401 upsmr |= UCC_GETH_UPSMR_R10M;
1424 /* FALLTHROUGH */ 1402 /* FALLTHROUGH */
1425 case SPEED_100: 1403 case SPEED_100:
1426 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI) 1404 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI)
1427 upsmr |= UPSMR_RMM; 1405 upsmr |= UCC_GETH_UPSMR_RMM;
1428 } 1406 }
1429 } 1407 }
1430 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) || 1408 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1431 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { 1409 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1432 upsmr |= UPSMR_TBIM; 1410 upsmr |= UCC_GETH_UPSMR_TBIM;
1433 } 1411 }
1434 out_be32(&uf_regs->upsmr, upsmr); 1412 out_be32(&uf_regs->upsmr, upsmr);
1435 1413
@@ -1517,9 +1495,9 @@ static void adjust_link(struct net_device *dev)
1517 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) || 1495 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1518 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { 1496 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1519 if (phydev->speed == SPEED_10) 1497 if (phydev->speed == SPEED_10)
1520 upsmr |= UPSMR_R10M; 1498 upsmr |= UCC_GETH_UPSMR_R10M;
1521 else 1499 else
1522 upsmr &= ~(UPSMR_R10M); 1500 upsmr &= ~UCC_GETH_UPSMR_R10M;
1523 } 1501 }
1524 break; 1502 break;
1525 default: 1503 default:
@@ -1602,10 +1580,8 @@ static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
1602 uccf = ugeth->uccf; 1580 uccf = ugeth->uccf;
1603 1581
1604 /* Mask GRACEFUL STOP TX interrupt bit and clear it */ 1582 /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1605 temp = in_be32(uccf->p_uccm); 1583 clrbits32(uccf->p_uccm, UCC_GETH_UCCE_GRA);
1606 temp &= ~UCCE_GRA; 1584 out_be32(uccf->p_ucce, UCC_GETH_UCCE_GRA); /* clear by writing 1 */
1607 out_be32(uccf->p_uccm, temp);
1608 out_be32(uccf->p_ucce, UCCE_GRA); /* clear by writing 1 */
1609 1585
1610 /* Issue host command */ 1586 /* Issue host command */
1611 cecr_subblock = 1587 cecr_subblock =
@@ -1617,7 +1593,7 @@ static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
1617 do { 1593 do {
1618 msleep(10); 1594 msleep(10);
1619 temp = in_be32(uccf->p_ucce); 1595 temp = in_be32(uccf->p_ucce);
1620 } while (!(temp & UCCE_GRA) && --i); 1596 } while (!(temp & UCC_GETH_UCCE_GRA) && --i);
1621 1597
1622 uccf->stopped_tx = 1; 1598 uccf->stopped_tx = 1;
1623 1599
@@ -1975,12 +1951,9 @@ static void ucc_geth_set_multi(struct net_device *dev)
1975 uf_regs = ugeth->uccf->uf_regs; 1951 uf_regs = ugeth->uccf->uf_regs;
1976 1952
1977 if (dev->flags & IFF_PROMISC) { 1953 if (dev->flags & IFF_PROMISC) {
1978 1954 setbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
1979 out_be32(&uf_regs->upsmr, in_be32(&uf_regs->upsmr) | UPSMR_PRO);
1980
1981 } else { 1955 } else {
1982 1956 clrbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
1983 out_be32(&uf_regs->upsmr, in_be32(&uf_regs->upsmr)&~UPSMR_PRO);
1984 1957
1985 p_82xx_addr_filt = 1958 p_82xx_addr_filt =
1986 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth-> 1959 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
@@ -2020,7 +1993,6 @@ static void ucc_geth_stop(struct ucc_geth_private *ugeth)
2020{ 1993{
2021 struct ucc_geth __iomem *ug_regs = ugeth->ug_regs; 1994 struct ucc_geth __iomem *ug_regs = ugeth->ug_regs;
2022 struct phy_device *phydev = ugeth->phydev; 1995 struct phy_device *phydev = ugeth->phydev;
2023 u32 tempval;
2024 1996
2025 ugeth_vdbg("%s: IN", __func__); 1997 ugeth_vdbg("%s: IN", __func__);
2026 1998
@@ -2037,9 +2009,7 @@ static void ucc_geth_stop(struct ucc_geth_private *ugeth)
2037 out_be32(ugeth->uccf->p_ucce, 0xffffffff); 2009 out_be32(ugeth->uccf->p_ucce, 0xffffffff);
2038 2010
2039 /* Disable Rx and Tx */ 2011 /* Disable Rx and Tx */
2040 tempval = in_be32(&ug_regs->maccfg1); 2012 clrbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2041 tempval &= ~(MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2042 out_be32(&ug_regs->maccfg1, tempval);
2043 2013
2044 ucc_geth_memclean(ugeth); 2014 ucc_geth_memclean(ugeth);
2045} 2015}
@@ -2153,10 +2123,10 @@ static int ucc_struct_init(struct ucc_geth_private *ugeth)
2153 /* Generate uccm_mask for receive */ 2123 /* Generate uccm_mask for receive */
2154 uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */ 2124 uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */
2155 for (i = 0; i < ug_info->numQueuesRx; i++) 2125 for (i = 0; i < ug_info->numQueuesRx; i++)
2156 uf_info->uccm_mask |= (UCCE_RXBF_SINGLE_MASK << i); 2126 uf_info->uccm_mask |= (UCC_GETH_UCCE_RXF0 << i);
2157 2127
2158 for (i = 0; i < ug_info->numQueuesTx; i++) 2128 for (i = 0; i < ug_info->numQueuesTx; i++)
2159 uf_info->uccm_mask |= (UCCE_TXBF_SINGLE_MASK << i); 2129 uf_info->uccm_mask |= (UCC_GETH_UCCE_TXB0 << i);
2160 /* Initialize the general fast UCC block. */ 2130 /* Initialize the general fast UCC block. */
2161 if (ucc_fast_init(uf_info, &ugeth->uccf)) { 2131 if (ucc_fast_init(uf_info, &ugeth->uccf)) {
2162 if (netif_msg_probe(ugeth)) 2132 if (netif_msg_probe(ugeth))
@@ -2185,7 +2155,7 @@ static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2185 struct ucc_geth __iomem *ug_regs; 2155 struct ucc_geth __iomem *ug_regs;
2186 int ret_val = -EINVAL; 2156 int ret_val = -EINVAL;
2187 u32 remoder = UCC_GETH_REMODER_INIT; 2157 u32 remoder = UCC_GETH_REMODER_INIT;
2188 u32 init_enet_pram_offset, cecr_subblock, command, maccfg1; 2158 u32 init_enet_pram_offset, cecr_subblock, command;
2189 u32 ifstat, i, j, size, l2qt, l3qt, length; 2159 u32 ifstat, i, j, size, l2qt, l3qt, length;
2190 u16 temoder = UCC_GETH_TEMODER_INIT; 2160 u16 temoder = UCC_GETH_TEMODER_INIT;
2191 u16 test; 2161 u16 test;
@@ -2281,10 +2251,7 @@ static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2281 &uf_regs->upsmr, 2251 &uf_regs->upsmr,
2282 &ug_regs->uempr, &ug_regs->maccfg1); 2252 &ug_regs->uempr, &ug_regs->maccfg1);
2283 2253
2284 maccfg1 = in_be32(&ug_regs->maccfg1); 2254 setbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2285 maccfg1 |= MACCFG1_ENABLE_RX;
2286 maccfg1 |= MACCFG1_ENABLE_TX;
2287 out_be32(&ug_regs->maccfg1, maccfg1);
2288 2255
2289 /* Set IPGIFG */ 2256 /* Set IPGIFG */
2290 /* For more details see the hardware spec. */ 2257 /* For more details see the hardware spec. */
@@ -3274,7 +3241,6 @@ static int ucc_geth_tx(struct net_device *dev, u8 txQ)
3274static int ucc_geth_poll(struct napi_struct *napi, int budget) 3241static int ucc_geth_poll(struct napi_struct *napi, int budget)
3275{ 3242{
3276 struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi); 3243 struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi);
3277 struct net_device *dev = ugeth->dev;
3278 struct ucc_geth_info *ug_info; 3244 struct ucc_geth_info *ug_info;
3279 int howmany, i; 3245 int howmany, i;
3280 3246
@@ -3285,14 +3251,8 @@ static int ucc_geth_poll(struct napi_struct *napi, int budget)
3285 howmany += ucc_geth_rx(ugeth, i, budget - howmany); 3251 howmany += ucc_geth_rx(ugeth, i, budget - howmany);
3286 3252
3287 if (howmany < budget) { 3253 if (howmany < budget) {
3288 struct ucc_fast_private *uccf;
3289 u32 uccm;
3290
3291 netif_rx_complete(napi); 3254 netif_rx_complete(napi);
3292 uccf = ugeth->uccf; 3255 setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS);
3293 uccm = in_be32(uccf->p_uccm);
3294 uccm |= UCCE_RX_EVENTS;
3295 out_be32(uccf->p_uccm, uccm);
3296 } 3256 }
3297 3257
3298 return howmany; 3258 return howmany;
@@ -3332,7 +3292,7 @@ static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
3332 /* Tx event processing */ 3292 /* Tx event processing */
3333 if (ucce & UCCE_TX_EVENTS) { 3293 if (ucce & UCCE_TX_EVENTS) {
3334 spin_lock(&ugeth->lock); 3294 spin_lock(&ugeth->lock);
3335 tx_mask = UCCE_TXBF_SINGLE_MASK; 3295 tx_mask = UCC_GETH_UCCE_TXB0;
3336 for (i = 0; i < ug_info->numQueuesTx; i++) { 3296 for (i = 0; i < ug_info->numQueuesTx; i++) {
3337 if (ucce & tx_mask) 3297 if (ucce & tx_mask)
3338 ucc_geth_tx(dev, i); 3298 ucc_geth_tx(dev, i);
@@ -3344,12 +3304,10 @@ static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
3344 3304
3345 /* Errors and other events */ 3305 /* Errors and other events */
3346 if (ucce & UCCE_OTHER) { 3306 if (ucce & UCCE_OTHER) {
3347 if (ucce & UCCE_BSY) { 3307 if (ucce & UCC_GETH_UCCE_BSY)
3348 dev->stats.rx_errors++; 3308 dev->stats.rx_errors++;
3349 } 3309 if (ucce & UCC_GETH_UCCE_TXE)
3350 if (ucce & UCCE_TXE) {
3351 dev->stats.tx_errors++; 3310 dev->stats.tx_errors++;
3352 }
3353 } 3311 }
3354 3312
3355 return IRQ_HANDLED; 3313 return IRQ_HANDLED;
diff --git a/drivers/net/ucc_geth.h b/drivers/net/ucc_geth.h
index d74d2f7cb73..8f699cb773e 100644
--- a/drivers/net/ucc_geth.h
+++ b/drivers/net/ucc_geth.h
@@ -162,92 +162,27 @@ struct ucc_geth {
162 boundary */ 162 boundary */
163 163
164/* UCC GETH Event Register */ 164/* UCC GETH Event Register */
165#define UCCE_MPD 0x80000000 /* Magic packet 165#define UCCE_TXB (UCC_GETH_UCCE_TXB7 | UCC_GETH_UCCE_TXB6 | \
166 detection */ 166 UCC_GETH_UCCE_TXB5 | UCC_GETH_UCCE_TXB4 | \
167#define UCCE_SCAR 0x40000000 167 UCC_GETH_UCCE_TXB3 | UCC_GETH_UCCE_TXB2 | \
168#define UCCE_GRA 0x20000000 /* Tx graceful 168 UCC_GETH_UCCE_TXB1 | UCC_GETH_UCCE_TXB0)
169 stop 169
170 complete */ 170#define UCCE_RXB (UCC_GETH_UCCE_RXB7 | UCC_GETH_UCCE_RXB6 | \
171#define UCCE_CBPR 0x10000000 171 UCC_GETH_UCCE_RXB5 | UCC_GETH_UCCE_RXB4 | \
172#define UCCE_BSY 0x08000000 172 UCC_GETH_UCCE_RXB3 | UCC_GETH_UCCE_RXB2 | \
173#define UCCE_RXC 0x04000000 173 UCC_GETH_UCCE_RXB1 | UCC_GETH_UCCE_RXB0)
174#define UCCE_TXC 0x02000000 174
175#define UCCE_TXE 0x01000000 175#define UCCE_RXF (UCC_GETH_UCCE_RXF7 | UCC_GETH_UCCE_RXF6 | \
176#define UCCE_TXB7 0x00800000 176 UCC_GETH_UCCE_RXF5 | UCC_GETH_UCCE_RXF4 | \
177#define UCCE_TXB6 0x00400000 177 UCC_GETH_UCCE_RXF3 | UCC_GETH_UCCE_RXF2 | \
178#define UCCE_TXB5 0x00200000 178 UCC_GETH_UCCE_RXF1 | UCC_GETH_UCCE_RXF0)
179#define UCCE_TXB4 0x00100000 179
180#define UCCE_TXB3 0x00080000 180#define UCCE_OTHER (UCC_GETH_UCCE_SCAR | UCC_GETH_UCCE_GRA | \
181#define UCCE_TXB2 0x00040000 181 UCC_GETH_UCCE_CBPR | UCC_GETH_UCCE_BSY | \
182#define UCCE_TXB1 0x00020000 182 UCC_GETH_UCCE_RXC | UCC_GETH_UCCE_TXC | UCC_GETH_UCCE_TXE)
183#define UCCE_TXB0 0x00010000 183
184#define UCCE_RXB7 0x00008000 184#define UCCE_RX_EVENTS (UCCE_RXF | UCC_GETH_UCCE_BSY)
185#define UCCE_RXB6 0x00004000 185#define UCCE_TX_EVENTS (UCCE_TXB | UCC_GETH_UCCE_TXE)
186#define UCCE_RXB5 0x00002000
187#define UCCE_RXB4 0x00001000
188#define UCCE_RXB3 0x00000800
189#define UCCE_RXB2 0x00000400
190#define UCCE_RXB1 0x00000200
191#define UCCE_RXB0 0x00000100
192#define UCCE_RXF7 0x00000080
193#define UCCE_RXF6 0x00000040
194#define UCCE_RXF5 0x00000020
195#define UCCE_RXF4 0x00000010
196#define UCCE_RXF3 0x00000008
197#define UCCE_RXF2 0x00000004
198#define UCCE_RXF1 0x00000002
199#define UCCE_RXF0 0x00000001
200
201#define UCCE_RXBF_SINGLE_MASK (UCCE_RXF0)
202#define UCCE_TXBF_SINGLE_MASK (UCCE_TXB0)
203
204#define UCCE_TXB (UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 |\
205 UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0)
206#define UCCE_RXB (UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 |\
207 UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0)
208#define UCCE_RXF (UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 |\
209 UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0)
210#define UCCE_OTHER (UCCE_SCAR | UCCE_GRA | UCCE_CBPR | UCCE_BSY |\
211 UCCE_RXC | UCCE_TXC | UCCE_TXE)
212
213#define UCCE_RX_EVENTS (UCCE_RXF | UCCE_BSY)
214#define UCCE_TX_EVENTS (UCCE_TXB | UCCE_TXE)
215
216/* UCC GETH UPSMR (Protocol Specific Mode Register) */
217#define UPSMR_ECM 0x04000000 /* Enable CAM
218 Miss or
219 Enable
220 Filtering
221 Miss */
222#define UPSMR_HSE 0x02000000 /* Hardware
223 Statistics
224 Enable */
225#define UPSMR_PRO 0x00400000 /* Promiscuous*/
226#define UPSMR_CAP 0x00200000 /* CAM polarity
227 */
228#define UPSMR_RSH 0x00100000 /* Receive
229 Short Frames
230 */
231#define UPSMR_RPM 0x00080000 /* Reduced Pin
232 Mode
233 interfaces */
234#define UPSMR_R10M 0x00040000 /* RGMII/RMII
235 10 Mode */
236#define UPSMR_RLPB 0x00020000 /* RMII
237 Loopback
238 Mode */
239#define UPSMR_TBIM 0x00010000 /* Ten-bit
240 Interface
241 Mode */
242#define UPSMR_RMM 0x00001000 /* RMII/RGMII
243 Mode */
244#define UPSMR_CAM 0x00000400 /* CAM Address
245 Matching */
246#define UPSMR_BRO 0x00000200 /* Broadcast
247 Address */
248#define UPSMR_RES1 0x00002000 /* Reserved
249 feild - must
250 be 1 */
251 186
252/* UCC GETH MACCFG1 (MAC Configuration 1 Register) */ 187/* UCC GETH MACCFG1 (MAC Configuration 1 Register) */
253#define MACCFG1_FLOW_RX 0x00000020 /* Flow Control 188#define MACCFG1_FLOW_RX 0x00000020 /* Flow Control
@@ -945,9 +880,10 @@ struct ucc_geth_hardware_statistics {
945#define UCC_GETH_REMODER_INIT 0 /* bits that must be 880#define UCC_GETH_REMODER_INIT 0 /* bits that must be
946 set */ 881 set */
947#define UCC_GETH_TEMODER_INIT 0xC000 /* bits that must */ 882#define UCC_GETH_TEMODER_INIT 0xC000 /* bits that must */
948#define UCC_GETH_UPSMR_INIT (UPSMR_RES1) /* Start value 883
949 for this 884/* Initial value for UPSMR */
950 register */ 885#define UCC_GETH_UPSMR_INIT UCC_GETH_UPSMR_RES1
886
951#define UCC_GETH_MACCFG1_INIT 0 887#define UCC_GETH_MACCFG1_INIT 0
952#define UCC_GETH_MACCFG2_INIT (MACCFG2_RESERVED_1) 888#define UCC_GETH_MACCFG2_INIT (MACCFG2_RESERVED_1)
953 889