diff options
author | Devin Heitmueller <dheitmueller@kernellabs.com> | 2010-06-27 17:12:42 -0400 |
---|---|---|
committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2010-12-29 05:16:34 -0500 |
commit | 301c9f26d7ded6e274a99c3a447a9a36790a3f3e (patch) | |
tree | 4e4efca609605c0c6755bd4393e03abe941ca502 /drivers | |
parent | d2c194ce4781d62bf671aa6b65a2fccb39feb50e (diff) |
[media] au8522: Handle differences in comb filter config for s-video input
Tweak the comb filter config when in s-video mode to match the Hauppauge
Windows driver values (based on register dumps).
This work was sponsored by GetWellNetwork Inc.
Signed-off-by: Devin Heitmueller <dheitmueller@kernellabs.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/media/dvb/frontends/au8522_decoder.c | 16 | ||||
-rw-r--r-- | drivers/media/dvb/frontends/au8522_priv.h | 2 |
2 files changed, 14 insertions, 4 deletions
diff --git a/drivers/media/dvb/frontends/au8522_decoder.c b/drivers/media/dvb/frontends/au8522_decoder.c index 5ec86970640..b537891a4cc 100644 --- a/drivers/media/dvb/frontends/au8522_decoder.c +++ b/drivers/media/dvb/frontends/au8522_decoder.c | |||
@@ -278,10 +278,18 @@ static void setup_decoder_defaults(struct au8522_state *state, u8 input_mode) | |||
278 | AU8522_TVDEC_COMB_HDIF_THR2_REG06AH_CVBS); | 278 | AU8522_TVDEC_COMB_HDIF_THR2_REG06AH_CVBS); |
279 | au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR3_REG06BH, | 279 | au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR3_REG06BH, |
280 | AU8522_TVDEC_COMB_HDIF_THR3_REG06BH_CVBS); | 280 | AU8522_TVDEC_COMB_HDIF_THR3_REG06BH_CVBS); |
281 | au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH, | 281 | if (input_mode == AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13 || |
282 | AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_CVBS); | 282 | input_mode == AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24) { |
283 | au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH, | 283 | au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH, |
284 | AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_CVBS); | 284 | AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_SVIDEO); |
285 | au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH, | ||
286 | AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_SVIDEO); | ||
287 | } else { | ||
288 | au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH, | ||
289 | AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_CVBS); | ||
290 | au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH, | ||
291 | AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_CVBS); | ||
292 | } | ||
285 | au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH, | 293 | au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH, |
286 | AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH_CVBS); | 294 | AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH_CVBS); |
287 | au8522_writereg(state, AU8522_TVDEC_UV_SEP_THR_REG06FH, | 295 | au8522_writereg(state, AU8522_TVDEC_UV_SEP_THR_REG06FH, |
diff --git a/drivers/media/dvb/frontends/au8522_priv.h b/drivers/media/dvb/frontends/au8522_priv.h index 609cf04bc31..751e17d692a 100644 --- a/drivers/media/dvb/frontends/au8522_priv.h +++ b/drivers/media/dvb/frontends/au8522_priv.h | |||
@@ -397,7 +397,9 @@ void au8522_release_state(struct au8522_state *state); | |||
397 | #define AU8522_TVDEC_COMB_HDIF_THR2_REG06AH_CVBS 0x0A | 397 | #define AU8522_TVDEC_COMB_HDIF_THR2_REG06AH_CVBS 0x0A |
398 | #define AU8522_TVDEC_COMB_HDIF_THR3_REG06BH_CVBS 0x32 | 398 | #define AU8522_TVDEC_COMB_HDIF_THR3_REG06BH_CVBS 0x32 |
399 | #define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_CVBS 0x34 | 399 | #define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_CVBS 0x34 |
400 | #define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_SVIDEO 0x2a | ||
400 | #define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_CVBS 0x05 | 401 | #define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_CVBS 0x05 |
402 | #define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_SVIDEO 0x15 | ||
401 | #define AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH_CVBS 0x6E | 403 | #define AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH_CVBS 0x6E |
402 | #define AU8522_TVDEC_UV_SEP_THR_REG06FH_CVBS 0x0F | 404 | #define AU8522_TVDEC_UV_SEP_THR_REG06FH_CVBS 0x0F |
403 | #define AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H_CVBS 0x80 | 405 | #define AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H_CVBS 0x80 |