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authorArchit Taneja <archit@ti.com>2011-05-12 07:56:29 -0400
committerTomi Valkeinen <tomi.valkeinen@ti.com>2011-05-12 12:30:27 -0400
commit5a8b572d832772722c3b3b7578e7fb968560fcf3 (patch)
tree1d99897d89fcc0f5743cf7503a28a2f6793eed03 /drivers/video/omap2/dss/dss.c
parent2e868dbe1d24a908fcb4dee0733500fd0aab0bce (diff)
OMAP4: DSS2: DSI: Changes for DSI2 on OMAP4
Introduce DSI2 PLL clock sources needed by LCD2 channel and DSI2 Protocol engine and DISPC Functional clock. Do the following: - Modify dss_get_dsi_clk_source() and dss_select_dsi_clk_source() to take the dsi module number as an argument. - Create debugfs files for dsi2, split the corresponding debugfs functions. - Allow DPI to use these new clock sources. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video/omap2/dss/dss.c')
-rw-r--r--drivers/video/omap2/dss/dss.c32
1 files changed, 26 insertions, 6 deletions
diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
index 3bf6e626f86..d9489d5c4f0 100644
--- a/drivers/video/omap2/dss/dss.c
+++ b/drivers/video/omap2/dss/dss.c
@@ -74,7 +74,7 @@ static struct {
74 struct dss_clock_info cache_dss_cinfo; 74 struct dss_clock_info cache_dss_cinfo;
75 struct dispc_clock_info cache_dispc_cinfo; 75 struct dispc_clock_info cache_dispc_cinfo;
76 76
77 enum omap_dss_clk_source dsi_clk_source; 77 enum omap_dss_clk_source dsi_clk_source[MAX_NUM_DSI];
78 enum omap_dss_clk_source dispc_clk_source; 78 enum omap_dss_clk_source dispc_clk_source;
79 enum omap_dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS]; 79 enum omap_dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
80 80
@@ -313,6 +313,11 @@ void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src)
313 dsidev = dsi_get_dsidev_from_id(0); 313 dsidev = dsi_get_dsidev_from_id(0);
314 dsi_wait_pll_hsdiv_dispc_active(dsidev); 314 dsi_wait_pll_hsdiv_dispc_active(dsidev);
315 break; 315 break;
316 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
317 b = 2;
318 dsidev = dsi_get_dsidev_from_id(1);
319 dsi_wait_pll_hsdiv_dispc_active(dsidev);
320 break;
316 default: 321 default:
317 BUG(); 322 BUG();
318 } 323 }
@@ -324,7 +329,8 @@ void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src)
324 dss.dispc_clk_source = clk_src; 329 dss.dispc_clk_source = clk_src;
325} 330}
326 331
327void dss_select_dsi_clk_source(enum omap_dss_clk_source clk_src) 332void dss_select_dsi_clk_source(int dsi_module,
333 enum omap_dss_clk_source clk_src)
328{ 334{
329 struct platform_device *dsidev; 335 struct platform_device *dsidev;
330 int b; 336 int b;
@@ -334,17 +340,24 @@ void dss_select_dsi_clk_source(enum omap_dss_clk_source clk_src)
334 b = 0; 340 b = 0;
335 break; 341 break;
336 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI: 342 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI:
343 BUG_ON(dsi_module != 0);
337 b = 1; 344 b = 1;
338 dsidev = dsi_get_dsidev_from_id(0); 345 dsidev = dsi_get_dsidev_from_id(0);
339 dsi_wait_pll_hsdiv_dsi_active(dsidev); 346 dsi_wait_pll_hsdiv_dsi_active(dsidev);
340 break; 347 break;
348 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI:
349 BUG_ON(dsi_module != 1);
350 b = 1;
351 dsidev = dsi_get_dsidev_from_id(1);
352 dsi_wait_pll_hsdiv_dsi_active(dsidev);
353 break;
341 default: 354 default:
342 BUG(); 355 BUG();
343 } 356 }
344 357
345 REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */ 358 REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */
346 359
347 dss.dsi_clk_source = clk_src; 360 dss.dsi_clk_source[dsi_module] = clk_src;
348} 361}
349 362
350void dss_select_lcd_clk_source(enum omap_channel channel, 363void dss_select_lcd_clk_source(enum omap_channel channel,
@@ -366,6 +379,12 @@ void dss_select_lcd_clk_source(enum omap_channel channel,
366 dsidev = dsi_get_dsidev_from_id(0); 379 dsidev = dsi_get_dsidev_from_id(0);
367 dsi_wait_pll_hsdiv_dispc_active(dsidev); 380 dsi_wait_pll_hsdiv_dispc_active(dsidev);
368 break; 381 break;
382 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
383 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD2);
384 b = 1;
385 dsidev = dsi_get_dsidev_from_id(1);
386 dsi_wait_pll_hsdiv_dispc_active(dsidev);
387 break;
369 default: 388 default:
370 BUG(); 389 BUG();
371 } 390 }
@@ -382,9 +401,9 @@ enum omap_dss_clk_source dss_get_dispc_clk_source(void)
382 return dss.dispc_clk_source; 401 return dss.dispc_clk_source;
383} 402}
384 403
385enum omap_dss_clk_source dss_get_dsi_clk_source(void) 404enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module)
386{ 405{
387 return dss.dsi_clk_source; 406 return dss.dsi_clk_source[dsi_module];
388} 407}
389 408
390enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel) 409enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
@@ -715,7 +734,8 @@ static int dss_init(void)
715 734
716 dss.dpll4_m4_ck = dpll4_m4_ck; 735 dss.dpll4_m4_ck = dpll4_m4_ck;
717 736
718 dss.dsi_clk_source = OMAP_DSS_CLK_SRC_FCK; 737 dss.dsi_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
738 dss.dsi_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
719 dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK; 739 dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK;
720 dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK; 740 dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
721 dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK; 741 dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;