diff options
author | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
commit | 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch) | |
tree | 0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/video/aty/aty128fb.c |
Linux-2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
Diffstat (limited to 'drivers/video/aty/aty128fb.c')
-rw-r--r-- | drivers/video/aty/aty128fb.c | 2485 |
1 files changed, 2485 insertions, 0 deletions
diff --git a/drivers/video/aty/aty128fb.c b/drivers/video/aty/aty128fb.c new file mode 100644 index 00000000000..8a4ba3bb987 --- /dev/null +++ b/drivers/video/aty/aty128fb.c | |||
@@ -0,0 +1,2485 @@ | |||
1 | /* $Id: aty128fb.c,v 1.1.1.1.36.1 1999/12/11 09:03:05 Exp $ | ||
2 | * linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128 | ||
3 | * | ||
4 | * Copyright (C) 1999-2003, Brad Douglas <brad@neruo.com> | ||
5 | * Copyright (C) 1999, Anthony Tong <atong@uiuc.edu> | ||
6 | * | ||
7 | * Ani Joshi / Jeff Garzik | ||
8 | * - Code cleanup | ||
9 | * | ||
10 | * Michel Danzer <michdaen@iiic.ethz.ch> | ||
11 | * - 15/16 bit cleanup | ||
12 | * - fix panning | ||
13 | * | ||
14 | * Benjamin Herrenschmidt | ||
15 | * - pmac-specific PM stuff | ||
16 | * - various fixes & cleanups | ||
17 | * | ||
18 | * Andreas Hundt <andi@convergence.de> | ||
19 | * - FB_ACTIVATE fixes | ||
20 | * | ||
21 | * Paul Mackerras <paulus@samba.org> | ||
22 | * - Convert to new framebuffer API, | ||
23 | * fix colormap setting at 16 bits/pixel (565) | ||
24 | * | ||
25 | * Paul Mundt | ||
26 | * - PCI hotplug | ||
27 | * | ||
28 | * Jon Smirl <jonsmirl@yahoo.com> | ||
29 | * - PCI ID update | ||
30 | * - replace ROM BIOS search | ||
31 | * | ||
32 | * Based off of Geert's atyfb.c and vfb.c. | ||
33 | * | ||
34 | * TODO: | ||
35 | * - monitor sensing (DDC) | ||
36 | * - virtual display | ||
37 | * - other platform support (only ppc/x86 supported) | ||
38 | * - hardware cursor support | ||
39 | * | ||
40 | * Please cc: your patches to brad@neruo.com. | ||
41 | */ | ||
42 | |||
43 | /* | ||
44 | * A special note of gratitude to ATI's devrel for providing documentation, | ||
45 | * example code and hardware. Thanks Nitya. -atong and brad | ||
46 | */ | ||
47 | |||
48 | |||
49 | #include <linux/config.h> | ||
50 | #include <linux/module.h> | ||
51 | #include <linux/moduleparam.h> | ||
52 | #include <linux/kernel.h> | ||
53 | #include <linux/errno.h> | ||
54 | #include <linux/string.h> | ||
55 | #include <linux/mm.h> | ||
56 | #include <linux/tty.h> | ||
57 | #include <linux/slab.h> | ||
58 | #include <linux/vmalloc.h> | ||
59 | #include <linux/delay.h> | ||
60 | #include <linux/interrupt.h> | ||
61 | #include <asm/uaccess.h> | ||
62 | #include <linux/fb.h> | ||
63 | #include <linux/init.h> | ||
64 | #include <linux/pci.h> | ||
65 | #include <linux/ioport.h> | ||
66 | #include <linux/console.h> | ||
67 | #include <asm/io.h> | ||
68 | |||
69 | #ifdef CONFIG_PPC_PMAC | ||
70 | #include <asm/pmac_feature.h> | ||
71 | #include <asm/prom.h> | ||
72 | #include <asm/pci-bridge.h> | ||
73 | #include "../macmodes.h" | ||
74 | #endif | ||
75 | |||
76 | #ifdef CONFIG_PMAC_BACKLIGHT | ||
77 | #include <asm/backlight.h> | ||
78 | #endif | ||
79 | |||
80 | #ifdef CONFIG_BOOTX_TEXT | ||
81 | #include <asm/btext.h> | ||
82 | #endif /* CONFIG_BOOTX_TEXT */ | ||
83 | |||
84 | #ifdef CONFIG_MTRR | ||
85 | #include <asm/mtrr.h> | ||
86 | #endif | ||
87 | |||
88 | #include <video/aty128.h> | ||
89 | |||
90 | /* Debug flag */ | ||
91 | #undef DEBUG | ||
92 | |||
93 | #ifdef DEBUG | ||
94 | #define DBG(fmt, args...) printk(KERN_DEBUG "aty128fb: %s " fmt, __FUNCTION__, ##args); | ||
95 | #else | ||
96 | #define DBG(fmt, args...) | ||
97 | #endif | ||
98 | |||
99 | #ifndef CONFIG_PPC_PMAC | ||
100 | /* default mode */ | ||
101 | static struct fb_var_screeninfo default_var __initdata = { | ||
102 | /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */ | ||
103 | 640, 480, 640, 480, 0, 0, 8, 0, | ||
104 | {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, | ||
105 | 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2, | ||
106 | 0, FB_VMODE_NONINTERLACED | ||
107 | }; | ||
108 | |||
109 | #else /* CONFIG_PPC_PMAC */ | ||
110 | /* default to 1024x768 at 75Hz on PPC - this will work | ||
111 | * on the iMac, the usual 640x480 @ 60Hz doesn't. */ | ||
112 | static struct fb_var_screeninfo default_var = { | ||
113 | /* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */ | ||
114 | 1024, 768, 1024, 768, 0, 0, 8, 0, | ||
115 | {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, | ||
116 | 0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3, | ||
117 | FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | ||
118 | FB_VMODE_NONINTERLACED | ||
119 | }; | ||
120 | #endif /* CONFIG_PPC_PMAC */ | ||
121 | |||
122 | /* default modedb mode */ | ||
123 | /* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */ | ||
124 | static struct fb_videomode defaultmode __initdata = { | ||
125 | .refresh = 60, | ||
126 | .xres = 640, | ||
127 | .yres = 480, | ||
128 | .pixclock = 39722, | ||
129 | .left_margin = 48, | ||
130 | .right_margin = 16, | ||
131 | .upper_margin = 33, | ||
132 | .lower_margin = 10, | ||
133 | .hsync_len = 96, | ||
134 | .vsync_len = 2, | ||
135 | .sync = 0, | ||
136 | .vmode = FB_VMODE_NONINTERLACED | ||
137 | }; | ||
138 | |||
139 | /* Chip generations */ | ||
140 | enum { | ||
141 | rage_128, | ||
142 | rage_128_pci, | ||
143 | rage_128_pro, | ||
144 | rage_128_pro_pci, | ||
145 | rage_M3, | ||
146 | rage_M3_pci, | ||
147 | rage_M4, | ||
148 | rage_128_ultra, | ||
149 | }; | ||
150 | |||
151 | /* Must match above enum */ | ||
152 | static const char *r128_family[] __devinitdata = { | ||
153 | "AGP", | ||
154 | "PCI", | ||
155 | "PRO AGP", | ||
156 | "PRO PCI", | ||
157 | "M3 AGP", | ||
158 | "M3 PCI", | ||
159 | "M4 AGP", | ||
160 | "Ultra AGP", | ||
161 | }; | ||
162 | |||
163 | /* | ||
164 | * PCI driver prototypes | ||
165 | */ | ||
166 | static int aty128_probe(struct pci_dev *pdev, | ||
167 | const struct pci_device_id *ent); | ||
168 | static void aty128_remove(struct pci_dev *pdev); | ||
169 | static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state); | ||
170 | static int aty128_pci_resume(struct pci_dev *pdev); | ||
171 | static int aty128_do_resume(struct pci_dev *pdev); | ||
172 | |||
173 | /* supported Rage128 chipsets */ | ||
174 | static struct pci_device_id aty128_pci_tbl[] = { | ||
175 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LE, | ||
176 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3_pci }, | ||
177 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LF, | ||
178 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3 }, | ||
179 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_MF, | ||
180 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 }, | ||
181 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_ML, | ||
182 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 }, | ||
183 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PA, | ||
184 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | ||
185 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PB, | ||
186 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | ||
187 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PC, | ||
188 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | ||
189 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PD, | ||
190 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci }, | ||
191 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PE, | ||
192 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | ||
193 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PF, | ||
194 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | ||
195 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PG, | ||
196 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | ||
197 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PH, | ||
198 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | ||
199 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PI, | ||
200 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | ||
201 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PJ, | ||
202 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | ||
203 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PK, | ||
204 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | ||
205 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PL, | ||
206 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | ||
207 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PM, | ||
208 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | ||
209 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PN, | ||
210 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | ||
211 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PO, | ||
212 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | ||
213 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PP, | ||
214 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci }, | ||
215 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PQ, | ||
216 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | ||
217 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PR, | ||
218 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci }, | ||
219 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PS, | ||
220 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | ||
221 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PT, | ||
222 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | ||
223 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PU, | ||
224 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | ||
225 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PV, | ||
226 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | ||
227 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PW, | ||
228 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | ||
229 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PX, | ||
230 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, | ||
231 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RE, | ||
232 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci }, | ||
233 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RF, | ||
234 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, | ||
235 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RG, | ||
236 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, | ||
237 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RK, | ||
238 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci }, | ||
239 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RL, | ||
240 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, | ||
241 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SE, | ||
242 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, | ||
243 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SF, | ||
244 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci }, | ||
245 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SG, | ||
246 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, | ||
247 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SH, | ||
248 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, | ||
249 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SK, | ||
250 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, | ||
251 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SL, | ||
252 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, | ||
253 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SM, | ||
254 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, | ||
255 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SN, | ||
256 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, | ||
257 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TF, | ||
258 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, | ||
259 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TL, | ||
260 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, | ||
261 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TR, | ||
262 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, | ||
263 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TS, | ||
264 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, | ||
265 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TT, | ||
266 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, | ||
267 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TU, | ||
268 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, | ||
269 | { 0, } | ||
270 | }; | ||
271 | |||
272 | MODULE_DEVICE_TABLE(pci, aty128_pci_tbl); | ||
273 | |||
274 | static struct pci_driver aty128fb_driver = { | ||
275 | .name = "aty128fb", | ||
276 | .id_table = aty128_pci_tbl, | ||
277 | .probe = aty128_probe, | ||
278 | .remove = __devexit_p(aty128_remove), | ||
279 | .suspend = aty128_pci_suspend, | ||
280 | .resume = aty128_pci_resume, | ||
281 | }; | ||
282 | |||
283 | /* packed BIOS settings */ | ||
284 | #ifndef CONFIG_PPC | ||
285 | typedef struct { | ||
286 | u8 clock_chip_type; | ||
287 | u8 struct_size; | ||
288 | u8 accelerator_entry; | ||
289 | u8 VGA_entry; | ||
290 | u16 VGA_table_offset; | ||
291 | u16 POST_table_offset; | ||
292 | u16 XCLK; | ||
293 | u16 MCLK; | ||
294 | u8 num_PLL_blocks; | ||
295 | u8 size_PLL_blocks; | ||
296 | u16 PCLK_ref_freq; | ||
297 | u16 PCLK_ref_divider; | ||
298 | u32 PCLK_min_freq; | ||
299 | u32 PCLK_max_freq; | ||
300 | u16 MCLK_ref_freq; | ||
301 | u16 MCLK_ref_divider; | ||
302 | u32 MCLK_min_freq; | ||
303 | u32 MCLK_max_freq; | ||
304 | u16 XCLK_ref_freq; | ||
305 | u16 XCLK_ref_divider; | ||
306 | u32 XCLK_min_freq; | ||
307 | u32 XCLK_max_freq; | ||
308 | } __attribute__ ((packed)) PLL_BLOCK; | ||
309 | #endif /* !CONFIG_PPC */ | ||
310 | |||
311 | /* onboard memory information */ | ||
312 | struct aty128_meminfo { | ||
313 | u8 ML; | ||
314 | u8 MB; | ||
315 | u8 Trcd; | ||
316 | u8 Trp; | ||
317 | u8 Twr; | ||
318 | u8 CL; | ||
319 | u8 Tr2w; | ||
320 | u8 LoopLatency; | ||
321 | u8 DspOn; | ||
322 | u8 Rloop; | ||
323 | const char *name; | ||
324 | }; | ||
325 | |||
326 | /* various memory configurations */ | ||
327 | static const struct aty128_meminfo sdr_128 = | ||
328 | { 4, 4, 3, 3, 1, 3, 1, 16, 30, 16, "128-bit SDR SGRAM (1:1)" }; | ||
329 | static const struct aty128_meminfo sdr_64 = | ||
330 | { 4, 8, 3, 3, 1, 3, 1, 17, 46, 17, "64-bit SDR SGRAM (1:1)" }; | ||
331 | static const struct aty128_meminfo sdr_sgram = | ||
332 | { 4, 4, 1, 2, 1, 2, 1, 16, 24, 16, "64-bit SDR SGRAM (2:1)" }; | ||
333 | static const struct aty128_meminfo ddr_sgram = | ||
334 | { 4, 4, 3, 3, 2, 3, 1, 16, 31, 16, "64-bit DDR SGRAM" }; | ||
335 | |||
336 | static struct fb_fix_screeninfo aty128fb_fix __initdata = { | ||
337 | .id = "ATY Rage128", | ||
338 | .type = FB_TYPE_PACKED_PIXELS, | ||
339 | .visual = FB_VISUAL_PSEUDOCOLOR, | ||
340 | .xpanstep = 8, | ||
341 | .ypanstep = 1, | ||
342 | .mmio_len = 0x2000, | ||
343 | .accel = FB_ACCEL_ATI_RAGE128, | ||
344 | }; | ||
345 | |||
346 | static char *mode_option __initdata = NULL; | ||
347 | |||
348 | #ifdef CONFIG_PPC_PMAC | ||
349 | static int default_vmode __initdata = VMODE_1024_768_60; | ||
350 | static int default_cmode __initdata = CMODE_8; | ||
351 | #endif | ||
352 | |||
353 | #ifdef CONFIG_PMAC_PBOOK | ||
354 | static int default_crt_on __initdata = 0; | ||
355 | static int default_lcd_on __initdata = 1; | ||
356 | #endif | ||
357 | |||
358 | #ifdef CONFIG_MTRR | ||
359 | static int mtrr = 1; | ||
360 | #endif | ||
361 | |||
362 | /* PLL constants */ | ||
363 | struct aty128_constants { | ||
364 | u32 ref_clk; | ||
365 | u32 ppll_min; | ||
366 | u32 ppll_max; | ||
367 | u32 ref_divider; | ||
368 | u32 xclk; | ||
369 | u32 fifo_width; | ||
370 | u32 fifo_depth; | ||
371 | }; | ||
372 | |||
373 | struct aty128_crtc { | ||
374 | u32 gen_cntl; | ||
375 | u32 h_total, h_sync_strt_wid; | ||
376 | u32 v_total, v_sync_strt_wid; | ||
377 | u32 pitch; | ||
378 | u32 offset, offset_cntl; | ||
379 | u32 xoffset, yoffset; | ||
380 | u32 vxres, vyres; | ||
381 | u32 depth, bpp; | ||
382 | }; | ||
383 | |||
384 | struct aty128_pll { | ||
385 | u32 post_divider; | ||
386 | u32 feedback_divider; | ||
387 | u32 vclk; | ||
388 | }; | ||
389 | |||
390 | struct aty128_ddafifo { | ||
391 | u32 dda_config; | ||
392 | u32 dda_on_off; | ||
393 | }; | ||
394 | |||
395 | /* register values for a specific mode */ | ||
396 | struct aty128fb_par { | ||
397 | struct aty128_crtc crtc; | ||
398 | struct aty128_pll pll; | ||
399 | struct aty128_ddafifo fifo_reg; | ||
400 | u32 accel_flags; | ||
401 | struct aty128_constants constants; /* PLL and others */ | ||
402 | void __iomem *regbase; /* remapped mmio */ | ||
403 | u32 vram_size; /* onboard video ram */ | ||
404 | int chip_gen; | ||
405 | const struct aty128_meminfo *mem; /* onboard mem info */ | ||
406 | #ifdef CONFIG_MTRR | ||
407 | struct { int vram; int vram_valid; } mtrr; | ||
408 | #endif | ||
409 | int blitter_may_be_busy; | ||
410 | int fifo_slots; /* free slots in FIFO (64 max) */ | ||
411 | |||
412 | int pm_reg; | ||
413 | int crt_on, lcd_on; | ||
414 | struct pci_dev *pdev; | ||
415 | struct fb_info *next; | ||
416 | int asleep; | ||
417 | int lock_blank; | ||
418 | |||
419 | u8 red[32]; /* see aty128fb_setcolreg */ | ||
420 | u8 green[64]; | ||
421 | u8 blue[32]; | ||
422 | u32 pseudo_palette[16]; /* used for TRUECOLOR */ | ||
423 | }; | ||
424 | |||
425 | |||
426 | #define round_div(n, d) ((n+(d/2))/d) | ||
427 | |||
428 | static int aty128fb_check_var(struct fb_var_screeninfo *var, | ||
429 | struct fb_info *info); | ||
430 | static int aty128fb_set_par(struct fb_info *info); | ||
431 | static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, | ||
432 | u_int transp, struct fb_info *info); | ||
433 | static int aty128fb_pan_display(struct fb_var_screeninfo *var, | ||
434 | struct fb_info *fb); | ||
435 | static int aty128fb_blank(int blank, struct fb_info *fb); | ||
436 | static int aty128fb_ioctl(struct inode *inode, struct file *file, u_int cmd, | ||
437 | u_long arg, struct fb_info *info); | ||
438 | static int aty128fb_sync(struct fb_info *info); | ||
439 | |||
440 | /* | ||
441 | * Internal routines | ||
442 | */ | ||
443 | |||
444 | static int aty128_encode_var(struct fb_var_screeninfo *var, | ||
445 | const struct aty128fb_par *par); | ||
446 | static int aty128_decode_var(struct fb_var_screeninfo *var, | ||
447 | struct aty128fb_par *par); | ||
448 | #if 0 | ||
449 | static void __init aty128_get_pllinfo(struct aty128fb_par *par, | ||
450 | void __iomem *bios); | ||
451 | static void __init __iomem *aty128_map_ROM(struct pci_dev *pdev, const struct aty128fb_par *par); | ||
452 | #endif | ||
453 | static void aty128_timings(struct aty128fb_par *par); | ||
454 | static void aty128_init_engine(struct aty128fb_par *par); | ||
455 | static void aty128_reset_engine(const struct aty128fb_par *par); | ||
456 | static void aty128_flush_pixel_cache(const struct aty128fb_par *par); | ||
457 | static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par); | ||
458 | static void wait_for_fifo(u16 entries, struct aty128fb_par *par); | ||
459 | static void wait_for_idle(struct aty128fb_par *par); | ||
460 | static u32 depth_to_dst(u32 depth); | ||
461 | |||
462 | #define BIOS_IN8(v) (readb(bios + (v))) | ||
463 | #define BIOS_IN16(v) (readb(bios + (v)) | \ | ||
464 | (readb(bios + (v) + 1) << 8)) | ||
465 | #define BIOS_IN32(v) (readb(bios + (v)) | \ | ||
466 | (readb(bios + (v) + 1) << 8) | \ | ||
467 | (readb(bios + (v) + 2) << 16) | \ | ||
468 | (readb(bios + (v) + 3) << 24)) | ||
469 | |||
470 | |||
471 | static struct fb_ops aty128fb_ops = { | ||
472 | .owner = THIS_MODULE, | ||
473 | .fb_check_var = aty128fb_check_var, | ||
474 | .fb_set_par = aty128fb_set_par, | ||
475 | .fb_setcolreg = aty128fb_setcolreg, | ||
476 | .fb_pan_display = aty128fb_pan_display, | ||
477 | .fb_blank = aty128fb_blank, | ||
478 | .fb_ioctl = aty128fb_ioctl, | ||
479 | .fb_sync = aty128fb_sync, | ||
480 | .fb_fillrect = cfb_fillrect, | ||
481 | .fb_copyarea = cfb_copyarea, | ||
482 | .fb_imageblit = cfb_imageblit, | ||
483 | .fb_cursor = soft_cursor, | ||
484 | }; | ||
485 | |||
486 | #ifdef CONFIG_PMAC_BACKLIGHT | ||
487 | static int aty128_set_backlight_enable(int on, int level, void* data); | ||
488 | static int aty128_set_backlight_level(int level, void* data); | ||
489 | |||
490 | static struct backlight_controller aty128_backlight_controller = { | ||
491 | aty128_set_backlight_enable, | ||
492 | aty128_set_backlight_level | ||
493 | }; | ||
494 | #endif /* CONFIG_PMAC_BACKLIGHT */ | ||
495 | |||
496 | /* | ||
497 | * Functions to read from/write to the mmio registers | ||
498 | * - endian conversions may possibly be avoided by | ||
499 | * using the other register aperture. TODO. | ||
500 | */ | ||
501 | static inline u32 _aty_ld_le32(volatile unsigned int regindex, | ||
502 | const struct aty128fb_par *par) | ||
503 | { | ||
504 | return readl (par->regbase + regindex); | ||
505 | } | ||
506 | |||
507 | static inline void _aty_st_le32(volatile unsigned int regindex, u32 val, | ||
508 | const struct aty128fb_par *par) | ||
509 | { | ||
510 | writel (val, par->regbase + regindex); | ||
511 | } | ||
512 | |||
513 | static inline u8 _aty_ld_8(unsigned int regindex, | ||
514 | const struct aty128fb_par *par) | ||
515 | { | ||
516 | return readb (par->regbase + regindex); | ||
517 | } | ||
518 | |||
519 | static inline void _aty_st_8(unsigned int regindex, u8 val, | ||
520 | const struct aty128fb_par *par) | ||
521 | { | ||
522 | writeb (val, par->regbase + regindex); | ||
523 | } | ||
524 | |||
525 | #define aty_ld_le32(regindex) _aty_ld_le32(regindex, par) | ||
526 | #define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, par) | ||
527 | #define aty_ld_8(regindex) _aty_ld_8(regindex, par) | ||
528 | #define aty_st_8(regindex, val) _aty_st_8(regindex, val, par) | ||
529 | |||
530 | /* | ||
531 | * Functions to read from/write to the pll registers | ||
532 | */ | ||
533 | |||
534 | #define aty_ld_pll(pll_index) _aty_ld_pll(pll_index, par) | ||
535 | #define aty_st_pll(pll_index, val) _aty_st_pll(pll_index, val, par) | ||
536 | |||
537 | |||
538 | static u32 _aty_ld_pll(unsigned int pll_index, | ||
539 | const struct aty128fb_par *par) | ||
540 | { | ||
541 | aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F); | ||
542 | return aty_ld_le32(CLOCK_CNTL_DATA); | ||
543 | } | ||
544 | |||
545 | |||
546 | static void _aty_st_pll(unsigned int pll_index, u32 val, | ||
547 | const struct aty128fb_par *par) | ||
548 | { | ||
549 | aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN); | ||
550 | aty_st_le32(CLOCK_CNTL_DATA, val); | ||
551 | } | ||
552 | |||
553 | |||
554 | /* return true when the PLL has completed an atomic update */ | ||
555 | static int aty_pll_readupdate(const struct aty128fb_par *par) | ||
556 | { | ||
557 | return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); | ||
558 | } | ||
559 | |||
560 | |||
561 | static void aty_pll_wait_readupdate(const struct aty128fb_par *par) | ||
562 | { | ||
563 | unsigned long timeout = jiffies + HZ/100; // should be more than enough | ||
564 | int reset = 1; | ||
565 | |||
566 | while (time_before(jiffies, timeout)) | ||
567 | if (aty_pll_readupdate(par)) { | ||
568 | reset = 0; | ||
569 | break; | ||
570 | } | ||
571 | |||
572 | if (reset) /* reset engine?? */ | ||
573 | printk(KERN_DEBUG "aty128fb: PLL write timeout!\n"); | ||
574 | } | ||
575 | |||
576 | |||
577 | /* tell PLL to update */ | ||
578 | static void aty_pll_writeupdate(const struct aty128fb_par *par) | ||
579 | { | ||
580 | aty_pll_wait_readupdate(par); | ||
581 | |||
582 | aty_st_pll(PPLL_REF_DIV, | ||
583 | aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W); | ||
584 | } | ||
585 | |||
586 | |||
587 | /* write to the scratch register to test r/w functionality */ | ||
588 | static int __init register_test(const struct aty128fb_par *par) | ||
589 | { | ||
590 | u32 val; | ||
591 | int flag = 0; | ||
592 | |||
593 | val = aty_ld_le32(BIOS_0_SCRATCH); | ||
594 | |||
595 | aty_st_le32(BIOS_0_SCRATCH, 0x55555555); | ||
596 | if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) { | ||
597 | aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA); | ||
598 | |||
599 | if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA) | ||
600 | flag = 1; | ||
601 | } | ||
602 | |||
603 | aty_st_le32(BIOS_0_SCRATCH, val); // restore value | ||
604 | return flag; | ||
605 | } | ||
606 | |||
607 | |||
608 | /* | ||
609 | * Accelerator engine functions | ||
610 | */ | ||
611 | static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par) | ||
612 | { | ||
613 | int i; | ||
614 | |||
615 | for (;;) { | ||
616 | for (i = 0; i < 2000000; i++) { | ||
617 | par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff; | ||
618 | if (par->fifo_slots >= entries) | ||
619 | return; | ||
620 | } | ||
621 | aty128_reset_engine(par); | ||
622 | } | ||
623 | } | ||
624 | |||
625 | |||
626 | static void wait_for_idle(struct aty128fb_par *par) | ||
627 | { | ||
628 | int i; | ||
629 | |||
630 | do_wait_for_fifo(64, par); | ||
631 | |||
632 | for (;;) { | ||
633 | for (i = 0; i < 2000000; i++) { | ||
634 | if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) { | ||
635 | aty128_flush_pixel_cache(par); | ||
636 | par->blitter_may_be_busy = 0; | ||
637 | return; | ||
638 | } | ||
639 | } | ||
640 | aty128_reset_engine(par); | ||
641 | } | ||
642 | } | ||
643 | |||
644 | |||
645 | static void wait_for_fifo(u16 entries, struct aty128fb_par *par) | ||
646 | { | ||
647 | if (par->fifo_slots < entries) | ||
648 | do_wait_for_fifo(64, par); | ||
649 | par->fifo_slots -= entries; | ||
650 | } | ||
651 | |||
652 | |||
653 | static void aty128_flush_pixel_cache(const struct aty128fb_par *par) | ||
654 | { | ||
655 | int i; | ||
656 | u32 tmp; | ||
657 | |||
658 | tmp = aty_ld_le32(PC_NGUI_CTLSTAT); | ||
659 | tmp &= ~(0x00ff); | ||
660 | tmp |= 0x00ff; | ||
661 | aty_st_le32(PC_NGUI_CTLSTAT, tmp); | ||
662 | |||
663 | for (i = 0; i < 2000000; i++) | ||
664 | if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY)) | ||
665 | break; | ||
666 | } | ||
667 | |||
668 | |||
669 | static void aty128_reset_engine(const struct aty128fb_par *par) | ||
670 | { | ||
671 | u32 gen_reset_cntl, clock_cntl_index, mclk_cntl; | ||
672 | |||
673 | aty128_flush_pixel_cache(par); | ||
674 | |||
675 | clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX); | ||
676 | mclk_cntl = aty_ld_pll(MCLK_CNTL); | ||
677 | |||
678 | aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000); | ||
679 | |||
680 | gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL); | ||
681 | aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI); | ||
682 | aty_ld_le32(GEN_RESET_CNTL); | ||
683 | aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI)); | ||
684 | aty_ld_le32(GEN_RESET_CNTL); | ||
685 | |||
686 | aty_st_pll(MCLK_CNTL, mclk_cntl); | ||
687 | aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index); | ||
688 | aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl); | ||
689 | |||
690 | /* use old pio mode */ | ||
691 | aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4); | ||
692 | |||
693 | DBG("engine reset"); | ||
694 | } | ||
695 | |||
696 | |||
697 | static void aty128_init_engine(struct aty128fb_par *par) | ||
698 | { | ||
699 | u32 pitch_value; | ||
700 | |||
701 | wait_for_idle(par); | ||
702 | |||
703 | /* 3D scaler not spoken here */ | ||
704 | wait_for_fifo(1, par); | ||
705 | aty_st_le32(SCALE_3D_CNTL, 0x00000000); | ||
706 | |||
707 | aty128_reset_engine(par); | ||
708 | |||
709 | pitch_value = par->crtc.pitch; | ||
710 | if (par->crtc.bpp == 24) { | ||
711 | pitch_value = pitch_value * 3; | ||
712 | } | ||
713 | |||
714 | wait_for_fifo(4, par); | ||
715 | /* setup engine offset registers */ | ||
716 | aty_st_le32(DEFAULT_OFFSET, 0x00000000); | ||
717 | |||
718 | /* setup engine pitch registers */ | ||
719 | aty_st_le32(DEFAULT_PITCH, pitch_value); | ||
720 | |||
721 | /* set the default scissor register to max dimensions */ | ||
722 | aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF); | ||
723 | |||
724 | /* set the drawing controls registers */ | ||
725 | aty_st_le32(DP_GUI_MASTER_CNTL, | ||
726 | GMC_SRC_PITCH_OFFSET_DEFAULT | | ||
727 | GMC_DST_PITCH_OFFSET_DEFAULT | | ||
728 | GMC_SRC_CLIP_DEFAULT | | ||
729 | GMC_DST_CLIP_DEFAULT | | ||
730 | GMC_BRUSH_SOLIDCOLOR | | ||
731 | (depth_to_dst(par->crtc.depth) << 8) | | ||
732 | GMC_SRC_DSTCOLOR | | ||
733 | GMC_BYTE_ORDER_MSB_TO_LSB | | ||
734 | GMC_DP_CONVERSION_TEMP_6500 | | ||
735 | ROP3_PATCOPY | | ||
736 | GMC_DP_SRC_RECT | | ||
737 | GMC_3D_FCN_EN_CLR | | ||
738 | GMC_DST_CLR_CMP_FCN_CLEAR | | ||
739 | GMC_AUX_CLIP_CLEAR | | ||
740 | GMC_WRITE_MASK_SET); | ||
741 | |||
742 | wait_for_fifo(8, par); | ||
743 | /* clear the line drawing registers */ | ||
744 | aty_st_le32(DST_BRES_ERR, 0); | ||
745 | aty_st_le32(DST_BRES_INC, 0); | ||
746 | aty_st_le32(DST_BRES_DEC, 0); | ||
747 | |||
748 | /* set brush color registers */ | ||
749 | aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */ | ||
750 | aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */ | ||
751 | |||
752 | /* set source color registers */ | ||
753 | aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */ | ||
754 | aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */ | ||
755 | |||
756 | /* default write mask */ | ||
757 | aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF); | ||
758 | |||
759 | /* Wait for all the writes to be completed before returning */ | ||
760 | wait_for_idle(par); | ||
761 | } | ||
762 | |||
763 | |||
764 | /* convert depth values to their register representation */ | ||
765 | static u32 depth_to_dst(u32 depth) | ||
766 | { | ||
767 | if (depth <= 8) | ||
768 | return DST_8BPP; | ||
769 | else if (depth <= 15) | ||
770 | return DST_15BPP; | ||
771 | else if (depth == 16) | ||
772 | return DST_16BPP; | ||
773 | else if (depth <= 24) | ||
774 | return DST_24BPP; | ||
775 | else if (depth <= 32) | ||
776 | return DST_32BPP; | ||
777 | |||
778 | return -EINVAL; | ||
779 | } | ||
780 | |||
781 | /* | ||
782 | * PLL informations retreival | ||
783 | */ | ||
784 | |||
785 | |||
786 | #ifndef __sparc__ | ||
787 | static void __iomem * __init aty128_map_ROM(const struct aty128fb_par *par, struct pci_dev *dev) | ||
788 | { | ||
789 | u16 dptr; | ||
790 | u8 rom_type; | ||
791 | void __iomem *bios; | ||
792 | size_t rom_size; | ||
793 | |||
794 | /* Fix from ATI for problem with Rage128 hardware not leaving ROM enabled */ | ||
795 | unsigned int temp; | ||
796 | temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG); | ||
797 | temp &= 0x00ffffffu; | ||
798 | temp |= 0x04 << 24; | ||
799 | aty_st_le32(RAGE128_MPP_TB_CONFIG, temp); | ||
800 | temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG); | ||
801 | |||
802 | bios = pci_map_rom(dev, &rom_size); | ||
803 | |||
804 | if (!bios) { | ||
805 | printk(KERN_ERR "aty128fb: ROM failed to map\n"); | ||
806 | return NULL; | ||
807 | } | ||
808 | |||
809 | /* Very simple test to make sure it appeared */ | ||
810 | if (BIOS_IN16(0) != 0xaa55) { | ||
811 | printk(KERN_ERR "aty128fb: Invalid ROM signature %x should be 0xaa55\n", | ||
812 | BIOS_IN16(0)); | ||
813 | goto failed; | ||
814 | } | ||
815 | |||
816 | /* Look for the PCI data to check the ROM type */ | ||
817 | dptr = BIOS_IN16(0x18); | ||
818 | |||
819 | /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM | ||
820 | * for now, until I've verified this works everywhere. The goal here is more | ||
821 | * to phase out Open Firmware images. | ||
822 | * | ||
823 | * Currently, we only look at the first PCI data, we could iteratre and deal with | ||
824 | * them all, and we should use fb_bios_start relative to start of image and not | ||
825 | * relative start of ROM, but so far, I never found a dual-image ATI card | ||
826 | * | ||
827 | * typedef struct { | ||
828 | * u32 signature; + 0x00 | ||
829 | * u16 vendor; + 0x04 | ||
830 | * u16 device; + 0x06 | ||
831 | * u16 reserved_1; + 0x08 | ||
832 | * u16 dlen; + 0x0a | ||
833 | * u8 drevision; + 0x0c | ||
834 | * u8 class_hi; + 0x0d | ||
835 | * u16 class_lo; + 0x0e | ||
836 | * u16 ilen; + 0x10 | ||
837 | * u16 irevision; + 0x12 | ||
838 | * u8 type; + 0x14 | ||
839 | * u8 indicator; + 0x15 | ||
840 | * u16 reserved_2; + 0x16 | ||
841 | * } pci_data_t; | ||
842 | */ | ||
843 | if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) { | ||
844 | printk(KERN_WARNING "aty128fb: PCI DATA signature in ROM incorrect: %08x\n", | ||
845 | BIOS_IN32(dptr)); | ||
846 | goto anyway; | ||
847 | } | ||
848 | rom_type = BIOS_IN8(dptr + 0x14); | ||
849 | switch(rom_type) { | ||
850 | case 0: | ||
851 | printk(KERN_INFO "aty128fb: Found Intel x86 BIOS ROM Image\n"); | ||
852 | break; | ||
853 | case 1: | ||
854 | printk(KERN_INFO "aty128fb: Found Open Firmware ROM Image\n"); | ||
855 | goto failed; | ||
856 | case 2: | ||
857 | printk(KERN_INFO "aty128fb: Found HP PA-RISC ROM Image\n"); | ||
858 | goto failed; | ||
859 | default: | ||
860 | printk(KERN_INFO "aty128fb: Found unknown type %d ROM Image\n", rom_type); | ||
861 | goto failed; | ||
862 | } | ||
863 | anyway: | ||
864 | return bios; | ||
865 | |||
866 | failed: | ||
867 | pci_unmap_rom(dev, bios); | ||
868 | return NULL; | ||
869 | } | ||
870 | |||
871 | static void __init aty128_get_pllinfo(struct aty128fb_par *par, unsigned char __iomem *bios) | ||
872 | { | ||
873 | unsigned int bios_hdr; | ||
874 | unsigned int bios_pll; | ||
875 | |||
876 | bios_hdr = BIOS_IN16(0x48); | ||
877 | bios_pll = BIOS_IN16(bios_hdr + 0x30); | ||
878 | |||
879 | par->constants.ppll_max = BIOS_IN32(bios_pll + 0x16); | ||
880 | par->constants.ppll_min = BIOS_IN32(bios_pll + 0x12); | ||
881 | par->constants.xclk = BIOS_IN16(bios_pll + 0x08); | ||
882 | par->constants.ref_divider = BIOS_IN16(bios_pll + 0x10); | ||
883 | par->constants.ref_clk = BIOS_IN16(bios_pll + 0x0e); | ||
884 | |||
885 | DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d ref clock %d\n", | ||
886 | par->constants.ppll_max, par->constants.ppll_min, | ||
887 | par->constants.xclk, par->constants.ref_divider, | ||
888 | par->constants.ref_clk); | ||
889 | |||
890 | } | ||
891 | |||
892 | #ifdef CONFIG_X86 | ||
893 | static void __iomem * __devinit aty128_find_mem_vbios(struct aty128fb_par *par) | ||
894 | { | ||
895 | /* I simplified this code as we used to miss the signatures in | ||
896 | * a lot of case. It's now closer to XFree, we just don't check | ||
897 | * for signatures at all... Something better will have to be done | ||
898 | * if we end up having conflicts | ||
899 | */ | ||
900 | u32 segstart; | ||
901 | unsigned char __iomem *rom_base = NULL; | ||
902 | |||
903 | for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) { | ||
904 | rom_base = ioremap(segstart, 0x10000); | ||
905 | if (rom_base == NULL) | ||
906 | return NULL; | ||
907 | if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa) | ||
908 | break; | ||
909 | iounmap(rom_base); | ||
910 | rom_base = NULL; | ||
911 | } | ||
912 | return rom_base; | ||
913 | } | ||
914 | #endif | ||
915 | #endif /* ndef(__sparc__) */ | ||
916 | |||
917 | /* fill in known card constants if pll_block is not available */ | ||
918 | static void __init aty128_timings(struct aty128fb_par *par) | ||
919 | { | ||
920 | #ifdef CONFIG_PPC_OF | ||
921 | /* instead of a table lookup, assume OF has properly | ||
922 | * setup the PLL registers and use their values | ||
923 | * to set the XCLK values and reference divider values */ | ||
924 | |||
925 | u32 x_mpll_ref_fb_div; | ||
926 | u32 xclk_cntl; | ||
927 | u32 Nx, M; | ||
928 | unsigned PostDivSet[] = { 0, 1, 2, 4, 8, 3, 6, 12 }; | ||
929 | #endif | ||
930 | |||
931 | if (!par->constants.ref_clk) | ||
932 | par->constants.ref_clk = 2950; | ||
933 | |||
934 | #ifdef CONFIG_PPC_OF | ||
935 | x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV); | ||
936 | xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7; | ||
937 | Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8; | ||
938 | M = x_mpll_ref_fb_div & 0x0000ff; | ||
939 | |||
940 | par->constants.xclk = round_div((2 * Nx * par->constants.ref_clk), | ||
941 | (M * PostDivSet[xclk_cntl])); | ||
942 | |||
943 | par->constants.ref_divider = | ||
944 | aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK; | ||
945 | #endif | ||
946 | |||
947 | if (!par->constants.ref_divider) { | ||
948 | par->constants.ref_divider = 0x3b; | ||
949 | |||
950 | aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e); | ||
951 | aty_pll_writeupdate(par); | ||
952 | } | ||
953 | aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider); | ||
954 | aty_pll_writeupdate(par); | ||
955 | |||
956 | /* from documentation */ | ||
957 | if (!par->constants.ppll_min) | ||
958 | par->constants.ppll_min = 12500; | ||
959 | if (!par->constants.ppll_max) | ||
960 | par->constants.ppll_max = 25000; /* 23000 on some cards? */ | ||
961 | if (!par->constants.xclk) | ||
962 | par->constants.xclk = 0x1d4d; /* same as mclk */ | ||
963 | |||
964 | par->constants.fifo_width = 128; | ||
965 | par->constants.fifo_depth = 32; | ||
966 | |||
967 | switch (aty_ld_le32(MEM_CNTL) & 0x3) { | ||
968 | case 0: | ||
969 | par->mem = &sdr_128; | ||
970 | break; | ||
971 | case 1: | ||
972 | par->mem = &sdr_sgram; | ||
973 | break; | ||
974 | case 2: | ||
975 | par->mem = &ddr_sgram; | ||
976 | break; | ||
977 | default: | ||
978 | par->mem = &sdr_sgram; | ||
979 | } | ||
980 | } | ||
981 | |||
982 | |||
983 | |||
984 | /* | ||
985 | * CRTC programming | ||
986 | */ | ||
987 | |||
988 | /* Program the CRTC registers */ | ||
989 | static void aty128_set_crtc(const struct aty128_crtc *crtc, | ||
990 | const struct aty128fb_par *par) | ||
991 | { | ||
992 | aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl); | ||
993 | aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total); | ||
994 | aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); | ||
995 | aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total); | ||
996 | aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); | ||
997 | aty_st_le32(CRTC_PITCH, crtc->pitch); | ||
998 | aty_st_le32(CRTC_OFFSET, crtc->offset); | ||
999 | aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl); | ||
1000 | /* Disable ATOMIC updating. Is this the right place? */ | ||
1001 | aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~(0x00030000)); | ||
1002 | } | ||
1003 | |||
1004 | |||
1005 | static int aty128_var_to_crtc(const struct fb_var_screeninfo *var, | ||
1006 | struct aty128_crtc *crtc, | ||
1007 | const struct aty128fb_par *par) | ||
1008 | { | ||
1009 | u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp, dst; | ||
1010 | u32 left, right, upper, lower, hslen, vslen, sync, vmode; | ||
1011 | u32 h_total, h_disp, h_sync_strt, h_sync_wid, h_sync_pol; | ||
1012 | u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync; | ||
1013 | u32 depth, bytpp; | ||
1014 | u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 }; | ||
1015 | |||
1016 | /* input */ | ||
1017 | xres = var->xres; | ||
1018 | yres = var->yres; | ||
1019 | vxres = var->xres_virtual; | ||
1020 | vyres = var->yres_virtual; | ||
1021 | xoffset = var->xoffset; | ||
1022 | yoffset = var->yoffset; | ||
1023 | bpp = var->bits_per_pixel; | ||
1024 | left = var->left_margin; | ||
1025 | right = var->right_margin; | ||
1026 | upper = var->upper_margin; | ||
1027 | lower = var->lower_margin; | ||
1028 | hslen = var->hsync_len; | ||
1029 | vslen = var->vsync_len; | ||
1030 | sync = var->sync; | ||
1031 | vmode = var->vmode; | ||
1032 | |||
1033 | if (bpp != 16) | ||
1034 | depth = bpp; | ||
1035 | else | ||
1036 | depth = (var->green.length == 6) ? 16 : 15; | ||
1037 | |||
1038 | /* check for mode eligibility | ||
1039 | * accept only non interlaced modes */ | ||
1040 | if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED) | ||
1041 | return -EINVAL; | ||
1042 | |||
1043 | /* convert (and round up) and validate */ | ||
1044 | xres = (xres + 7) & ~7; | ||
1045 | xoffset = (xoffset + 7) & ~7; | ||
1046 | |||
1047 | if (vxres < xres + xoffset) | ||
1048 | vxres = xres + xoffset; | ||
1049 | |||
1050 | if (vyres < yres + yoffset) | ||
1051 | vyres = yres + yoffset; | ||
1052 | |||
1053 | /* convert depth into ATI register depth */ | ||
1054 | dst = depth_to_dst(depth); | ||
1055 | |||
1056 | if (dst == -EINVAL) { | ||
1057 | printk(KERN_ERR "aty128fb: Invalid depth or RGBA\n"); | ||
1058 | return -EINVAL; | ||
1059 | } | ||
1060 | |||
1061 | /* convert register depth to bytes per pixel */ | ||
1062 | bytpp = mode_bytpp[dst]; | ||
1063 | |||
1064 | /* make sure there is enough video ram for the mode */ | ||
1065 | if ((u32)(vxres * vyres * bytpp) > par->vram_size) { | ||
1066 | printk(KERN_ERR "aty128fb: Not enough memory for mode\n"); | ||
1067 | return -EINVAL; | ||
1068 | } | ||
1069 | |||
1070 | h_disp = (xres >> 3) - 1; | ||
1071 | h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL; | ||
1072 | |||
1073 | v_disp = yres - 1; | ||
1074 | v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL; | ||
1075 | |||
1076 | /* check to make sure h_total and v_total are in range */ | ||
1077 | if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) { | ||
1078 | printk(KERN_ERR "aty128fb: invalid width ranges\n"); | ||
1079 | return -EINVAL; | ||
1080 | } | ||
1081 | |||
1082 | h_sync_wid = (hslen + 7) >> 3; | ||
1083 | if (h_sync_wid == 0) | ||
1084 | h_sync_wid = 1; | ||
1085 | else if (h_sync_wid > 0x3f) /* 0x3f = max hwidth */ | ||
1086 | h_sync_wid = 0x3f; | ||
1087 | |||
1088 | h_sync_strt = (h_disp << 3) + right; | ||
1089 | |||
1090 | v_sync_wid = vslen; | ||
1091 | if (v_sync_wid == 0) | ||
1092 | v_sync_wid = 1; | ||
1093 | else if (v_sync_wid > 0x1f) /* 0x1f = max vwidth */ | ||
1094 | v_sync_wid = 0x1f; | ||
1095 | |||
1096 | v_sync_strt = v_disp + lower; | ||
1097 | |||
1098 | h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1; | ||
1099 | v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1; | ||
1100 | |||
1101 | c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0; | ||
1102 | |||
1103 | crtc->gen_cntl = 0x3000000L | c_sync | (dst << 8); | ||
1104 | |||
1105 | crtc->h_total = h_total | (h_disp << 16); | ||
1106 | crtc->v_total = v_total | (v_disp << 16); | ||
1107 | |||
1108 | crtc->h_sync_strt_wid = h_sync_strt | (h_sync_wid << 16) | | ||
1109 | (h_sync_pol << 23); | ||
1110 | crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) | | ||
1111 | (v_sync_pol << 23); | ||
1112 | |||
1113 | crtc->pitch = vxres >> 3; | ||
1114 | |||
1115 | crtc->offset = 0; | ||
1116 | |||
1117 | if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) | ||
1118 | crtc->offset_cntl = 0x00010000; | ||
1119 | else | ||
1120 | crtc->offset_cntl = 0; | ||
1121 | |||
1122 | crtc->vxres = vxres; | ||
1123 | crtc->vyres = vyres; | ||
1124 | crtc->xoffset = xoffset; | ||
1125 | crtc->yoffset = yoffset; | ||
1126 | crtc->depth = depth; | ||
1127 | crtc->bpp = bpp; | ||
1128 | |||
1129 | return 0; | ||
1130 | } | ||
1131 | |||
1132 | |||
1133 | static int aty128_pix_width_to_var(int pix_width, struct fb_var_screeninfo *var) | ||
1134 | { | ||
1135 | |||
1136 | /* fill in pixel info */ | ||
1137 | var->red.msb_right = 0; | ||
1138 | var->green.msb_right = 0; | ||
1139 | var->blue.offset = 0; | ||
1140 | var->blue.msb_right = 0; | ||
1141 | var->transp.offset = 0; | ||
1142 | var->transp.length = 0; | ||
1143 | var->transp.msb_right = 0; | ||
1144 | switch (pix_width) { | ||
1145 | case CRTC_PIX_WIDTH_8BPP: | ||
1146 | var->bits_per_pixel = 8; | ||
1147 | var->red.offset = 0; | ||
1148 | var->red.length = 8; | ||
1149 | var->green.offset = 0; | ||
1150 | var->green.length = 8; | ||
1151 | var->blue.length = 8; | ||
1152 | break; | ||
1153 | case CRTC_PIX_WIDTH_15BPP: | ||
1154 | var->bits_per_pixel = 16; | ||
1155 | var->red.offset = 10; | ||
1156 | var->red.length = 5; | ||
1157 | var->green.offset = 5; | ||
1158 | var->green.length = 5; | ||
1159 | var->blue.length = 5; | ||
1160 | break; | ||
1161 | case CRTC_PIX_WIDTH_16BPP: | ||
1162 | var->bits_per_pixel = 16; | ||
1163 | var->red.offset = 11; | ||
1164 | var->red.length = 5; | ||
1165 | var->green.offset = 5; | ||
1166 | var->green.length = 6; | ||
1167 | var->blue.length = 5; | ||
1168 | break; | ||
1169 | case CRTC_PIX_WIDTH_24BPP: | ||
1170 | var->bits_per_pixel = 24; | ||
1171 | var->red.offset = 16; | ||
1172 | var->red.length = 8; | ||
1173 | var->green.offset = 8; | ||
1174 | var->green.length = 8; | ||
1175 | var->blue.length = 8; | ||
1176 | break; | ||
1177 | case CRTC_PIX_WIDTH_32BPP: | ||
1178 | var->bits_per_pixel = 32; | ||
1179 | var->red.offset = 16; | ||
1180 | var->red.length = 8; | ||
1181 | var->green.offset = 8; | ||
1182 | var->green.length = 8; | ||
1183 | var->blue.length = 8; | ||
1184 | var->transp.offset = 24; | ||
1185 | var->transp.length = 8; | ||
1186 | break; | ||
1187 | default: | ||
1188 | printk(KERN_ERR "aty128fb: Invalid pixel width\n"); | ||
1189 | return -EINVAL; | ||
1190 | } | ||
1191 | |||
1192 | return 0; | ||
1193 | } | ||
1194 | |||
1195 | |||
1196 | static int aty128_crtc_to_var(const struct aty128_crtc *crtc, | ||
1197 | struct fb_var_screeninfo *var) | ||
1198 | { | ||
1199 | u32 xres, yres, left, right, upper, lower, hslen, vslen, sync; | ||
1200 | u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol; | ||
1201 | u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync; | ||
1202 | u32 pix_width; | ||
1203 | |||
1204 | /* fun with masking */ | ||
1205 | h_total = crtc->h_total & 0x1ff; | ||
1206 | h_disp = (crtc->h_total >> 16) & 0xff; | ||
1207 | h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff; | ||
1208 | h_sync_dly = crtc->h_sync_strt_wid & 0x7; | ||
1209 | h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x3f; | ||
1210 | h_sync_pol = (crtc->h_sync_strt_wid >> 23) & 0x1; | ||
1211 | v_total = crtc->v_total & 0x7ff; | ||
1212 | v_disp = (crtc->v_total >> 16) & 0x7ff; | ||
1213 | v_sync_strt = crtc->v_sync_strt_wid & 0x7ff; | ||
1214 | v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f; | ||
1215 | v_sync_pol = (crtc->v_sync_strt_wid >> 23) & 0x1; | ||
1216 | c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0; | ||
1217 | pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK; | ||
1218 | |||
1219 | /* do conversions */ | ||
1220 | xres = (h_disp + 1) << 3; | ||
1221 | yres = v_disp + 1; | ||
1222 | left = ((h_total - h_sync_strt - h_sync_wid) << 3) - h_sync_dly; | ||
1223 | right = ((h_sync_strt - h_disp) << 3) + h_sync_dly; | ||
1224 | hslen = h_sync_wid << 3; | ||
1225 | upper = v_total - v_sync_strt - v_sync_wid; | ||
1226 | lower = v_sync_strt - v_disp; | ||
1227 | vslen = v_sync_wid; | ||
1228 | sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) | | ||
1229 | (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) | | ||
1230 | (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0); | ||
1231 | |||
1232 | aty128_pix_width_to_var(pix_width, var); | ||
1233 | |||
1234 | var->xres = xres; | ||
1235 | var->yres = yres; | ||
1236 | var->xres_virtual = crtc->vxres; | ||
1237 | var->yres_virtual = crtc->vyres; | ||
1238 | var->xoffset = crtc->xoffset; | ||
1239 | var->yoffset = crtc->yoffset; | ||
1240 | var->left_margin = left; | ||
1241 | var->right_margin = right; | ||
1242 | var->upper_margin = upper; | ||
1243 | var->lower_margin = lower; | ||
1244 | var->hsync_len = hslen; | ||
1245 | var->vsync_len = vslen; | ||
1246 | var->sync = sync; | ||
1247 | var->vmode = FB_VMODE_NONINTERLACED; | ||
1248 | |||
1249 | return 0; | ||
1250 | } | ||
1251 | |||
1252 | #ifdef CONFIG_PMAC_PBOOK | ||
1253 | static void aty128_set_crt_enable(struct aty128fb_par *par, int on) | ||
1254 | { | ||
1255 | if (on) { | ||
1256 | aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) | CRT_CRTC_ON); | ||
1257 | aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) | DAC_PALETTE2_SNOOP_EN)); | ||
1258 | } else | ||
1259 | aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) & ~CRT_CRTC_ON); | ||
1260 | } | ||
1261 | |||
1262 | static void aty128_set_lcd_enable(struct aty128fb_par *par, int on) | ||
1263 | { | ||
1264 | u32 reg; | ||
1265 | |||
1266 | if (on) { | ||
1267 | reg = aty_ld_le32(LVDS_GEN_CNTL); | ||
1268 | reg |= LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION; | ||
1269 | reg &= ~LVDS_DISPLAY_DIS; | ||
1270 | aty_st_le32(LVDS_GEN_CNTL, reg); | ||
1271 | #ifdef CONFIG_PMAC_BACKLIGHT | ||
1272 | aty128_set_backlight_enable(get_backlight_enable(), | ||
1273 | get_backlight_level(), par); | ||
1274 | #endif | ||
1275 | } else { | ||
1276 | #ifdef CONFIG_PMAC_BACKLIGHT | ||
1277 | aty128_set_backlight_enable(0, 0, par); | ||
1278 | #endif | ||
1279 | reg = aty_ld_le32(LVDS_GEN_CNTL); | ||
1280 | reg |= LVDS_DISPLAY_DIS; | ||
1281 | aty_st_le32(LVDS_GEN_CNTL, reg); | ||
1282 | mdelay(100); | ||
1283 | reg &= ~(LVDS_ON /*| LVDS_EN*/); | ||
1284 | aty_st_le32(LVDS_GEN_CNTL, reg); | ||
1285 | } | ||
1286 | } | ||
1287 | #endif /* CONFIG_PMAC_PBOOK */ | ||
1288 | |||
1289 | static void aty128_set_pll(struct aty128_pll *pll, const struct aty128fb_par *par) | ||
1290 | { | ||
1291 | u32 div3; | ||
1292 | |||
1293 | unsigned char post_conv[] = /* register values for post dividers */ | ||
1294 | { 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 }; | ||
1295 | |||
1296 | /* select PPLL_DIV_3 */ | ||
1297 | aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8)); | ||
1298 | |||
1299 | /* reset PLL */ | ||
1300 | aty_st_pll(PPLL_CNTL, | ||
1301 | aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN); | ||
1302 | |||
1303 | /* write the reference divider */ | ||
1304 | aty_pll_wait_readupdate(par); | ||
1305 | aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider & 0x3ff); | ||
1306 | aty_pll_writeupdate(par); | ||
1307 | |||
1308 | div3 = aty_ld_pll(PPLL_DIV_3); | ||
1309 | div3 &= ~PPLL_FB3_DIV_MASK; | ||
1310 | div3 |= pll->feedback_divider; | ||
1311 | div3 &= ~PPLL_POST3_DIV_MASK; | ||
1312 | div3 |= post_conv[pll->post_divider] << 16; | ||
1313 | |||
1314 | /* write feedback and post dividers */ | ||
1315 | aty_pll_wait_readupdate(par); | ||
1316 | aty_st_pll(PPLL_DIV_3, div3); | ||
1317 | aty_pll_writeupdate(par); | ||
1318 | |||
1319 | aty_pll_wait_readupdate(par); | ||
1320 | aty_st_pll(HTOTAL_CNTL, 0); /* no horiz crtc adjustment */ | ||
1321 | aty_pll_writeupdate(par); | ||
1322 | |||
1323 | /* clear the reset, just in case */ | ||
1324 | aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET); | ||
1325 | } | ||
1326 | |||
1327 | |||
1328 | static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll, | ||
1329 | const struct aty128fb_par *par) | ||
1330 | { | ||
1331 | const struct aty128_constants c = par->constants; | ||
1332 | unsigned char post_dividers[] = {1,2,4,8,3,6,12}; | ||
1333 | u32 output_freq; | ||
1334 | u32 vclk; /* in .01 MHz */ | ||
1335 | int i; | ||
1336 | u32 n, d; | ||
1337 | |||
1338 | vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */ | ||
1339 | |||
1340 | /* adjust pixel clock if necessary */ | ||
1341 | if (vclk > c.ppll_max) | ||
1342 | vclk = c.ppll_max; | ||
1343 | if (vclk * 12 < c.ppll_min) | ||
1344 | vclk = c.ppll_min/12; | ||
1345 | |||
1346 | /* now, find an acceptable divider */ | ||
1347 | for (i = 0; i < sizeof(post_dividers); i++) { | ||
1348 | output_freq = post_dividers[i] * vclk; | ||
1349 | if (output_freq >= c.ppll_min && output_freq <= c.ppll_max) | ||
1350 | break; | ||
1351 | } | ||
1352 | |||
1353 | /* calculate feedback divider */ | ||
1354 | n = c.ref_divider * output_freq; | ||
1355 | d = c.ref_clk; | ||
1356 | |||
1357 | pll->post_divider = post_dividers[i]; | ||
1358 | pll->feedback_divider = round_div(n, d); | ||
1359 | pll->vclk = vclk; | ||
1360 | |||
1361 | DBG("post %d feedback %d vlck %d output %d ref_divider %d " | ||
1362 | "vclk_per: %d\n", pll->post_divider, | ||
1363 | pll->feedback_divider, vclk, output_freq, | ||
1364 | c.ref_divider, period_in_ps); | ||
1365 | |||
1366 | return 0; | ||
1367 | } | ||
1368 | |||
1369 | |||
1370 | static int aty128_pll_to_var(const struct aty128_pll *pll, struct fb_var_screeninfo *var) | ||
1371 | { | ||
1372 | var->pixclock = 100000000 / pll->vclk; | ||
1373 | |||
1374 | return 0; | ||
1375 | } | ||
1376 | |||
1377 | |||
1378 | static void aty128_set_fifo(const struct aty128_ddafifo *dsp, | ||
1379 | const struct aty128fb_par *par) | ||
1380 | { | ||
1381 | aty_st_le32(DDA_CONFIG, dsp->dda_config); | ||
1382 | aty_st_le32(DDA_ON_OFF, dsp->dda_on_off); | ||
1383 | } | ||
1384 | |||
1385 | |||
1386 | static int aty128_ddafifo(struct aty128_ddafifo *dsp, | ||
1387 | const struct aty128_pll *pll, | ||
1388 | u32 depth, | ||
1389 | const struct aty128fb_par *par) | ||
1390 | { | ||
1391 | const struct aty128_meminfo *m = par->mem; | ||
1392 | u32 xclk = par->constants.xclk; | ||
1393 | u32 fifo_width = par->constants.fifo_width; | ||
1394 | u32 fifo_depth = par->constants.fifo_depth; | ||
1395 | s32 x, b, p, ron, roff; | ||
1396 | u32 n, d, bpp; | ||
1397 | |||
1398 | /* round up to multiple of 8 */ | ||
1399 | bpp = (depth+7) & ~7; | ||
1400 | |||
1401 | n = xclk * fifo_width; | ||
1402 | d = pll->vclk * bpp; | ||
1403 | x = round_div(n, d); | ||
1404 | |||
1405 | ron = 4 * m->MB + | ||
1406 | 3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) + | ||
1407 | 2 * m->Trp + | ||
1408 | m->Twr + | ||
1409 | m->CL + | ||
1410 | m->Tr2w + | ||
1411 | x; | ||
1412 | |||
1413 | DBG("x %x\n", x); | ||
1414 | |||
1415 | b = 0; | ||
1416 | while (x) { | ||
1417 | x >>= 1; | ||
1418 | b++; | ||
1419 | } | ||
1420 | p = b + 1; | ||
1421 | |||
1422 | ron <<= (11 - p); | ||
1423 | |||
1424 | n <<= (11 - p); | ||
1425 | x = round_div(n, d); | ||
1426 | roff = x * (fifo_depth - 4); | ||
1427 | |||
1428 | if ((ron + m->Rloop) >= roff) { | ||
1429 | printk(KERN_ERR "aty128fb: Mode out of range!\n"); | ||
1430 | return -EINVAL; | ||
1431 | } | ||
1432 | |||
1433 | DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n", | ||
1434 | p, m->Rloop, x, ron, roff); | ||
1435 | |||
1436 | dsp->dda_config = p << 16 | m->Rloop << 20 | x; | ||
1437 | dsp->dda_on_off = ron << 16 | roff; | ||
1438 | |||
1439 | return 0; | ||
1440 | } | ||
1441 | |||
1442 | |||
1443 | /* | ||
1444 | * This actually sets the video mode. | ||
1445 | */ | ||
1446 | static int aty128fb_set_par(struct fb_info *info) | ||
1447 | { | ||
1448 | struct aty128fb_par *par = info->par; | ||
1449 | u32 config; | ||
1450 | int err; | ||
1451 | |||
1452 | if ((err = aty128_decode_var(&info->var, par)) != 0) | ||
1453 | return err; | ||
1454 | |||
1455 | if (par->blitter_may_be_busy) | ||
1456 | wait_for_idle(par); | ||
1457 | |||
1458 | /* clear all registers that may interfere with mode setting */ | ||
1459 | aty_st_le32(OVR_CLR, 0); | ||
1460 | aty_st_le32(OVR_WID_LEFT_RIGHT, 0); | ||
1461 | aty_st_le32(OVR_WID_TOP_BOTTOM, 0); | ||
1462 | aty_st_le32(OV0_SCALE_CNTL, 0); | ||
1463 | aty_st_le32(MPP_TB_CONFIG, 0); | ||
1464 | aty_st_le32(MPP_GP_CONFIG, 0); | ||
1465 | aty_st_le32(SUBPIC_CNTL, 0); | ||
1466 | aty_st_le32(VIPH_CONTROL, 0); | ||
1467 | aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */ | ||
1468 | aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */ | ||
1469 | aty_st_le32(CAP0_TRIG_CNTL, 0); | ||
1470 | aty_st_le32(CAP1_TRIG_CNTL, 0); | ||
1471 | |||
1472 | aty_st_8(CRTC_EXT_CNTL + 1, 4); /* turn video off */ | ||
1473 | |||
1474 | aty128_set_crtc(&par->crtc, par); | ||
1475 | aty128_set_pll(&par->pll, par); | ||
1476 | aty128_set_fifo(&par->fifo_reg, par); | ||
1477 | |||
1478 | config = aty_ld_le32(CONFIG_CNTL) & ~3; | ||
1479 | |||
1480 | #if defined(__BIG_ENDIAN) | ||
1481 | if (par->crtc.bpp == 32) | ||
1482 | config |= 2; /* make aperture do 32 bit swapping */ | ||
1483 | else if (par->crtc.bpp == 16) | ||
1484 | config |= 1; /* make aperture do 16 bit swapping */ | ||
1485 | #endif | ||
1486 | |||
1487 | aty_st_le32(CONFIG_CNTL, config); | ||
1488 | aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */ | ||
1489 | |||
1490 | info->fix.line_length = (par->crtc.vxres * par->crtc.bpp) >> 3; | ||
1491 | info->fix.visual = par->crtc.bpp == 8 ? FB_VISUAL_PSEUDOCOLOR | ||
1492 | : FB_VISUAL_DIRECTCOLOR; | ||
1493 | |||
1494 | #ifdef CONFIG_PMAC_PBOOK | ||
1495 | if (par->chip_gen == rage_M3) { | ||
1496 | aty128_set_crt_enable(par, par->crt_on); | ||
1497 | aty128_set_lcd_enable(par, par->lcd_on); | ||
1498 | } | ||
1499 | #endif | ||
1500 | if (par->accel_flags & FB_ACCELF_TEXT) | ||
1501 | aty128_init_engine(par); | ||
1502 | |||
1503 | #ifdef CONFIG_BOOTX_TEXT | ||
1504 | btext_update_display(info->fix.smem_start, | ||
1505 | (((par->crtc.h_total>>16) & 0xff)+1)*8, | ||
1506 | ((par->crtc.v_total>>16) & 0x7ff)+1, | ||
1507 | par->crtc.bpp, | ||
1508 | par->crtc.vxres*par->crtc.bpp/8); | ||
1509 | #endif /* CONFIG_BOOTX_TEXT */ | ||
1510 | |||
1511 | return 0; | ||
1512 | } | ||
1513 | |||
1514 | /* | ||
1515 | * encode/decode the User Defined Part of the Display | ||
1516 | */ | ||
1517 | |||
1518 | static int aty128_decode_var(struct fb_var_screeninfo *var, struct aty128fb_par *par) | ||
1519 | { | ||
1520 | int err; | ||
1521 | struct aty128_crtc crtc; | ||
1522 | struct aty128_pll pll; | ||
1523 | struct aty128_ddafifo fifo_reg; | ||
1524 | |||
1525 | if ((err = aty128_var_to_crtc(var, &crtc, par))) | ||
1526 | return err; | ||
1527 | |||
1528 | if ((err = aty128_var_to_pll(var->pixclock, &pll, par))) | ||
1529 | return err; | ||
1530 | |||
1531 | if ((err = aty128_ddafifo(&fifo_reg, &pll, crtc.depth, par))) | ||
1532 | return err; | ||
1533 | |||
1534 | par->crtc = crtc; | ||
1535 | par->pll = pll; | ||
1536 | par->fifo_reg = fifo_reg; | ||
1537 | par->accel_flags = var->accel_flags; | ||
1538 | |||
1539 | return 0; | ||
1540 | } | ||
1541 | |||
1542 | |||
1543 | static int aty128_encode_var(struct fb_var_screeninfo *var, | ||
1544 | const struct aty128fb_par *par) | ||
1545 | { | ||
1546 | int err; | ||
1547 | |||
1548 | if ((err = aty128_crtc_to_var(&par->crtc, var))) | ||
1549 | return err; | ||
1550 | |||
1551 | if ((err = aty128_pll_to_var(&par->pll, var))) | ||
1552 | return err; | ||
1553 | |||
1554 | var->nonstd = 0; | ||
1555 | var->activate = 0; | ||
1556 | |||
1557 | var->height = -1; | ||
1558 | var->width = -1; | ||
1559 | var->accel_flags = par->accel_flags; | ||
1560 | |||
1561 | return 0; | ||
1562 | } | ||
1563 | |||
1564 | |||
1565 | static int aty128fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) | ||
1566 | { | ||
1567 | struct aty128fb_par par; | ||
1568 | int err; | ||
1569 | |||
1570 | par = *(struct aty128fb_par *)info->par; | ||
1571 | if ((err = aty128_decode_var(var, &par)) != 0) | ||
1572 | return err; | ||
1573 | aty128_encode_var(var, &par); | ||
1574 | return 0; | ||
1575 | } | ||
1576 | |||
1577 | |||
1578 | /* | ||
1579 | * Pan or Wrap the Display | ||
1580 | */ | ||
1581 | static int aty128fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *fb) | ||
1582 | { | ||
1583 | struct aty128fb_par *par = fb->par; | ||
1584 | u32 xoffset, yoffset; | ||
1585 | u32 offset; | ||
1586 | u32 xres, yres; | ||
1587 | |||
1588 | xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3; | ||
1589 | yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1; | ||
1590 | |||
1591 | xoffset = (var->xoffset +7) & ~7; | ||
1592 | yoffset = var->yoffset; | ||
1593 | |||
1594 | if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres) | ||
1595 | return -EINVAL; | ||
1596 | |||
1597 | par->crtc.xoffset = xoffset; | ||
1598 | par->crtc.yoffset = yoffset; | ||
1599 | |||
1600 | offset = ((yoffset * par->crtc.vxres + xoffset)*(par->crtc.bpp >> 3)) & ~7; | ||
1601 | |||
1602 | if (par->crtc.bpp == 24) | ||
1603 | offset += 8 * (offset % 3); /* Must be multiple of 8 and 3 */ | ||
1604 | |||
1605 | aty_st_le32(CRTC_OFFSET, offset); | ||
1606 | |||
1607 | return 0; | ||
1608 | } | ||
1609 | |||
1610 | |||
1611 | /* | ||
1612 | * Helper function to store a single palette register | ||
1613 | */ | ||
1614 | static void aty128_st_pal(u_int regno, u_int red, u_int green, u_int blue, | ||
1615 | struct aty128fb_par *par) | ||
1616 | { | ||
1617 | if (par->chip_gen == rage_M3) { | ||
1618 | #if 0 | ||
1619 | /* Note: For now, on M3, we set palette on both heads, which may | ||
1620 | * be useless. Can someone with a M3 check this ? | ||
1621 | * | ||
1622 | * This code would still be useful if using the second CRTC to | ||
1623 | * do mirroring | ||
1624 | */ | ||
1625 | |||
1626 | aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PALETTE_ACCESS_CNTL); | ||
1627 | aty_st_8(PALETTE_INDEX, regno); | ||
1628 | aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue); | ||
1629 | #endif | ||
1630 | aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & ~DAC_PALETTE_ACCESS_CNTL); | ||
1631 | } | ||
1632 | |||
1633 | aty_st_8(PALETTE_INDEX, regno); | ||
1634 | aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue); | ||
1635 | } | ||
1636 | |||
1637 | static int aty128fb_sync(struct fb_info *info) | ||
1638 | { | ||
1639 | struct aty128fb_par *par = info->par; | ||
1640 | |||
1641 | if (par->blitter_may_be_busy) | ||
1642 | wait_for_idle(par); | ||
1643 | return 0; | ||
1644 | } | ||
1645 | |||
1646 | #ifndef MODULE | ||
1647 | static int __init aty128fb_setup(char *options) | ||
1648 | { | ||
1649 | char *this_opt; | ||
1650 | |||
1651 | if (!options || !*options) | ||
1652 | return 0; | ||
1653 | |||
1654 | while ((this_opt = strsep(&options, ",")) != NULL) { | ||
1655 | #ifdef CONFIG_PMAC_PBOOK | ||
1656 | if (!strncmp(this_opt, "lcd:", 4)) { | ||
1657 | default_lcd_on = simple_strtoul(this_opt+4, NULL, 0); | ||
1658 | continue; | ||
1659 | } else if (!strncmp(this_opt, "crt:", 4)) { | ||
1660 | default_crt_on = simple_strtoul(this_opt+4, NULL, 0); | ||
1661 | continue; | ||
1662 | } | ||
1663 | #endif | ||
1664 | #ifdef CONFIG_MTRR | ||
1665 | if(!strncmp(this_opt, "nomtrr", 6)) { | ||
1666 | mtrr = 0; | ||
1667 | continue; | ||
1668 | } | ||
1669 | #endif | ||
1670 | #ifdef CONFIG_PPC_PMAC | ||
1671 | /* vmode and cmode deprecated */ | ||
1672 | if (!strncmp(this_opt, "vmode:", 6)) { | ||
1673 | unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0); | ||
1674 | if (vmode > 0 && vmode <= VMODE_MAX) | ||
1675 | default_vmode = vmode; | ||
1676 | continue; | ||
1677 | } else if (!strncmp(this_opt, "cmode:", 6)) { | ||
1678 | unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0); | ||
1679 | switch (cmode) { | ||
1680 | case 0: | ||
1681 | case 8: | ||
1682 | default_cmode = CMODE_8; | ||
1683 | break; | ||
1684 | case 15: | ||
1685 | case 16: | ||
1686 | default_cmode = CMODE_16; | ||
1687 | break; | ||
1688 | case 24: | ||
1689 | case 32: | ||
1690 | default_cmode = CMODE_32; | ||
1691 | break; | ||
1692 | } | ||
1693 | continue; | ||
1694 | } | ||
1695 | #endif /* CONFIG_PPC_PMAC */ | ||
1696 | mode_option = this_opt; | ||
1697 | } | ||
1698 | return 0; | ||
1699 | } | ||
1700 | #endif /* MODULE */ | ||
1701 | |||
1702 | |||
1703 | /* | ||
1704 | * Initialisation | ||
1705 | */ | ||
1706 | |||
1707 | #ifdef CONFIG_PPC_PMAC | ||
1708 | static void aty128_early_resume(void *data) | ||
1709 | { | ||
1710 | struct aty128fb_par *par = data; | ||
1711 | |||
1712 | if (try_acquire_console_sem()) | ||
1713 | return; | ||
1714 | aty128_do_resume(par->pdev); | ||
1715 | release_console_sem(); | ||
1716 | } | ||
1717 | #endif /* CONFIG_PPC_PMAC */ | ||
1718 | |||
1719 | static int __init aty128_init(struct pci_dev *pdev, const struct pci_device_id *ent) | ||
1720 | { | ||
1721 | struct fb_info *info = pci_get_drvdata(pdev); | ||
1722 | struct aty128fb_par *par = info->par; | ||
1723 | struct fb_var_screeninfo var; | ||
1724 | char video_card[DEVICE_NAME_SIZE]; | ||
1725 | u8 chip_rev; | ||
1726 | u32 dac; | ||
1727 | |||
1728 | if (!par->vram_size) /* may have already been probed */ | ||
1729 | par->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF; | ||
1730 | |||
1731 | /* Get the chip revision */ | ||
1732 | chip_rev = (aty_ld_le32(CONFIG_CNTL) >> 16) & 0x1F; | ||
1733 | |||
1734 | strcpy(video_card, "Rage128 XX "); | ||
1735 | video_card[8] = ent->device >> 8; | ||
1736 | video_card[9] = ent->device & 0xFF; | ||
1737 | |||
1738 | /* range check to make sure */ | ||
1739 | if (ent->driver_data < (sizeof(r128_family)/sizeof(char *))) | ||
1740 | strncat(video_card, r128_family[ent->driver_data], sizeof(video_card)); | ||
1741 | |||
1742 | printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev); | ||
1743 | |||
1744 | if (par->vram_size % (1024 * 1024) == 0) | ||
1745 | printk("%dM %s\n", par->vram_size / (1024*1024), par->mem->name); | ||
1746 | else | ||
1747 | printk("%dk %s\n", par->vram_size / 1024, par->mem->name); | ||
1748 | |||
1749 | par->chip_gen = ent->driver_data; | ||
1750 | |||
1751 | /* fill in info */ | ||
1752 | info->fbops = &aty128fb_ops; | ||
1753 | info->flags = FBINFO_FLAG_DEFAULT; | ||
1754 | |||
1755 | #ifdef CONFIG_PMAC_PBOOK | ||
1756 | par->lcd_on = default_lcd_on; | ||
1757 | par->crt_on = default_crt_on; | ||
1758 | #endif | ||
1759 | |||
1760 | var = default_var; | ||
1761 | #ifdef CONFIG_PPC_PMAC | ||
1762 | if (_machine == _MACH_Pmac) { | ||
1763 | /* Indicate sleep capability */ | ||
1764 | if (par->chip_gen == rage_M3) { | ||
1765 | pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, NULL, 0, 1); | ||
1766 | pmac_set_early_video_resume(aty128_early_resume, par); | ||
1767 | } | ||
1768 | |||
1769 | /* Find default mode */ | ||
1770 | if (mode_option) { | ||
1771 | if (!mac_find_mode(&var, info, mode_option, 8)) | ||
1772 | var = default_var; | ||
1773 | } else { | ||
1774 | if (default_vmode <= 0 || default_vmode > VMODE_MAX) | ||
1775 | default_vmode = VMODE_1024_768_60; | ||
1776 | |||
1777 | /* iMacs need that resolution | ||
1778 | * PowerMac2,1 first r128 iMacs | ||
1779 | * PowerMac2,2 summer 2000 iMacs | ||
1780 | * PowerMac4,1 january 2001 iMacs "flower power" | ||
1781 | */ | ||
1782 | if (machine_is_compatible("PowerMac2,1") || | ||
1783 | machine_is_compatible("PowerMac2,2") || | ||
1784 | machine_is_compatible("PowerMac4,1")) | ||
1785 | default_vmode = VMODE_1024_768_75; | ||
1786 | |||
1787 | /* iBook SE */ | ||
1788 | if (machine_is_compatible("PowerBook2,2")) | ||
1789 | default_vmode = VMODE_800_600_60; | ||
1790 | |||
1791 | /* PowerBook Firewire (Pismo), iBook Dual USB */ | ||
1792 | if (machine_is_compatible("PowerBook3,1") || | ||
1793 | machine_is_compatible("PowerBook4,1")) | ||
1794 | default_vmode = VMODE_1024_768_60; | ||
1795 | |||
1796 | /* PowerBook Titanium */ | ||
1797 | if (machine_is_compatible("PowerBook3,2")) | ||
1798 | default_vmode = VMODE_1152_768_60; | ||
1799 | |||
1800 | if (default_cmode > 16) | ||
1801 | default_cmode = CMODE_32; | ||
1802 | else if (default_cmode > 8) | ||
1803 | default_cmode = CMODE_16; | ||
1804 | else | ||
1805 | default_cmode = CMODE_8; | ||
1806 | |||
1807 | if (mac_vmode_to_var(default_vmode, default_cmode, &var)) | ||
1808 | var = default_var; | ||
1809 | } | ||
1810 | } else | ||
1811 | #endif /* CONFIG_PPC_PMAC */ | ||
1812 | { | ||
1813 | if (mode_option) | ||
1814 | if (fb_find_mode(&var, info, mode_option, NULL, | ||
1815 | 0, &defaultmode, 8) == 0) | ||
1816 | var = default_var; | ||
1817 | } | ||
1818 | |||
1819 | var.accel_flags &= ~FB_ACCELF_TEXT; | ||
1820 | // var.accel_flags |= FB_ACCELF_TEXT;/* FIXME Will add accel later */ | ||
1821 | |||
1822 | if (aty128fb_check_var(&var, info)) { | ||
1823 | printk(KERN_ERR "aty128fb: Cannot set default mode.\n"); | ||
1824 | return 0; | ||
1825 | } | ||
1826 | |||
1827 | /* setup the DAC the way we like it */ | ||
1828 | dac = aty_ld_le32(DAC_CNTL); | ||
1829 | dac |= (DAC_8BIT_EN | DAC_RANGE_CNTL); | ||
1830 | dac |= DAC_MASK; | ||
1831 | if (par->chip_gen == rage_M3) | ||
1832 | dac |= DAC_PALETTE2_SNOOP_EN; | ||
1833 | aty_st_le32(DAC_CNTL, dac); | ||
1834 | |||
1835 | /* turn off bus mastering, just in case */ | ||
1836 | aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS); | ||
1837 | |||
1838 | info->var = var; | ||
1839 | fb_alloc_cmap(&info->cmap, 256, 0); | ||
1840 | |||
1841 | var.activate = FB_ACTIVATE_NOW; | ||
1842 | |||
1843 | aty128_init_engine(par); | ||
1844 | |||
1845 | if (register_framebuffer(info) < 0) | ||
1846 | return 0; | ||
1847 | |||
1848 | #ifdef CONFIG_PMAC_BACKLIGHT | ||
1849 | /* Could be extended to Rage128Pro LVDS output too */ | ||
1850 | if (par->chip_gen == rage_M3) | ||
1851 | register_backlight_controller(&aty128_backlight_controller, par, "ati"); | ||
1852 | #endif /* CONFIG_PMAC_BACKLIGHT */ | ||
1853 | |||
1854 | par->pm_reg = pci_find_capability(pdev, PCI_CAP_ID_PM); | ||
1855 | par->pdev = pdev; | ||
1856 | par->asleep = 0; | ||
1857 | par->lock_blank = 0; | ||
1858 | |||
1859 | printk(KERN_INFO "fb%d: %s frame buffer device on %s\n", | ||
1860 | info->node, info->fix.id, video_card); | ||
1861 | |||
1862 | return 1; /* success! */ | ||
1863 | } | ||
1864 | |||
1865 | #ifdef CONFIG_PCI | ||
1866 | /* register a card ++ajoshi */ | ||
1867 | static int __init aty128_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | ||
1868 | { | ||
1869 | unsigned long fb_addr, reg_addr; | ||
1870 | struct aty128fb_par *par; | ||
1871 | struct fb_info *info; | ||
1872 | int err; | ||
1873 | #ifndef __sparc__ | ||
1874 | void __iomem *bios = NULL; | ||
1875 | #endif | ||
1876 | |||
1877 | /* Enable device in PCI config */ | ||
1878 | if ((err = pci_enable_device(pdev))) { | ||
1879 | printk(KERN_ERR "aty128fb: Cannot enable PCI device: %d\n", | ||
1880 | err); | ||
1881 | return -ENODEV; | ||
1882 | } | ||
1883 | |||
1884 | fb_addr = pci_resource_start(pdev, 0); | ||
1885 | if (!request_mem_region(fb_addr, pci_resource_len(pdev, 0), | ||
1886 | "aty128fb FB")) { | ||
1887 | printk(KERN_ERR "aty128fb: cannot reserve frame " | ||
1888 | "buffer memory\n"); | ||
1889 | return -ENODEV; | ||
1890 | } | ||
1891 | |||
1892 | reg_addr = pci_resource_start(pdev, 2); | ||
1893 | if (!request_mem_region(reg_addr, pci_resource_len(pdev, 2), | ||
1894 | "aty128fb MMIO")) { | ||
1895 | printk(KERN_ERR "aty128fb: cannot reserve MMIO region\n"); | ||
1896 | goto err_free_fb; | ||
1897 | } | ||
1898 | |||
1899 | /* We have the resources. Now virtualize them */ | ||
1900 | info = framebuffer_alloc(sizeof(struct aty128fb_par), &pdev->dev); | ||
1901 | if (info == NULL) { | ||
1902 | printk(KERN_ERR "aty128fb: can't alloc fb_info_aty128\n"); | ||
1903 | goto err_free_mmio; | ||
1904 | } | ||
1905 | par = info->par; | ||
1906 | |||
1907 | info->pseudo_palette = par->pseudo_palette; | ||
1908 | info->fix = aty128fb_fix; | ||
1909 | |||
1910 | /* Virtualize mmio region */ | ||
1911 | info->fix.mmio_start = reg_addr; | ||
1912 | par->regbase = ioremap(reg_addr, pci_resource_len(pdev, 2)); | ||
1913 | if (!par->regbase) | ||
1914 | goto err_free_info; | ||
1915 | |||
1916 | /* Grab memory size from the card */ | ||
1917 | // How does this relate to the resource length from the PCI hardware? | ||
1918 | par->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF; | ||
1919 | |||
1920 | /* Virtualize the framebuffer */ | ||
1921 | info->screen_base = ioremap(fb_addr, par->vram_size); | ||
1922 | if (!info->screen_base) | ||
1923 | goto err_unmap_out; | ||
1924 | |||
1925 | /* Set up info->fix */ | ||
1926 | info->fix = aty128fb_fix; | ||
1927 | info->fix.smem_start = fb_addr; | ||
1928 | info->fix.smem_len = par->vram_size; | ||
1929 | info->fix.mmio_start = reg_addr; | ||
1930 | |||
1931 | /* If we can't test scratch registers, something is seriously wrong */ | ||
1932 | if (!register_test(par)) { | ||
1933 | printk(KERN_ERR "aty128fb: Can't write to video register!\n"); | ||
1934 | goto err_out; | ||
1935 | } | ||
1936 | |||
1937 | #ifndef __sparc__ | ||
1938 | bios = aty128_map_ROM(par, pdev); | ||
1939 | #ifdef CONFIG_X86 | ||
1940 | if (bios == NULL) | ||
1941 | bios = aty128_find_mem_vbios(par); | ||
1942 | #endif | ||
1943 | if (bios == NULL) | ||
1944 | printk(KERN_INFO "aty128fb: BIOS not located, guessing timings.\n"); | ||
1945 | else { | ||
1946 | printk(KERN_INFO "aty128fb: Rage128 BIOS located\n"); | ||
1947 | aty128_get_pllinfo(par, bios); | ||
1948 | pci_unmap_rom(pdev, bios); | ||
1949 | } | ||
1950 | #endif /* __sparc__ */ | ||
1951 | |||
1952 | aty128_timings(par); | ||
1953 | pci_set_drvdata(pdev, info); | ||
1954 | |||
1955 | if (!aty128_init(pdev, ent)) | ||
1956 | goto err_out; | ||
1957 | |||
1958 | #ifdef CONFIG_MTRR | ||
1959 | if (mtrr) { | ||
1960 | par->mtrr.vram = mtrr_add(info->fix.smem_start, | ||
1961 | par->vram_size, MTRR_TYPE_WRCOMB, 1); | ||
1962 | par->mtrr.vram_valid = 1; | ||
1963 | /* let there be speed */ | ||
1964 | printk(KERN_INFO "aty128fb: Rage128 MTRR set to ON\n"); | ||
1965 | } | ||
1966 | #endif /* CONFIG_MTRR */ | ||
1967 | return 0; | ||
1968 | |||
1969 | err_out: | ||
1970 | iounmap(info->screen_base); | ||
1971 | err_unmap_out: | ||
1972 | iounmap(par->regbase); | ||
1973 | err_free_info: | ||
1974 | framebuffer_release(info); | ||
1975 | err_free_mmio: | ||
1976 | release_mem_region(pci_resource_start(pdev, 2), | ||
1977 | pci_resource_len(pdev, 2)); | ||
1978 | err_free_fb: | ||
1979 | release_mem_region(pci_resource_start(pdev, 0), | ||
1980 | pci_resource_len(pdev, 0)); | ||
1981 | return -ENODEV; | ||
1982 | } | ||
1983 | |||
1984 | static void __devexit aty128_remove(struct pci_dev *pdev) | ||
1985 | { | ||
1986 | struct fb_info *info = pci_get_drvdata(pdev); | ||
1987 | struct aty128fb_par *par; | ||
1988 | |||
1989 | if (!info) | ||
1990 | return; | ||
1991 | |||
1992 | par = info->par; | ||
1993 | |||
1994 | unregister_framebuffer(info); | ||
1995 | #ifdef CONFIG_MTRR | ||
1996 | if (par->mtrr.vram_valid) | ||
1997 | mtrr_del(par->mtrr.vram, info->fix.smem_start, | ||
1998 | par->vram_size); | ||
1999 | #endif /* CONFIG_MTRR */ | ||
2000 | iounmap(par->regbase); | ||
2001 | iounmap(info->screen_base); | ||
2002 | |||
2003 | release_mem_region(pci_resource_start(pdev, 0), | ||
2004 | pci_resource_len(pdev, 0)); | ||
2005 | release_mem_region(pci_resource_start(pdev, 2), | ||
2006 | pci_resource_len(pdev, 2)); | ||
2007 | framebuffer_release(info); | ||
2008 | } | ||
2009 | #endif /* CONFIG_PCI */ | ||
2010 | |||
2011 | |||
2012 | |||
2013 | /* | ||
2014 | * Blank the display. | ||
2015 | */ | ||
2016 | static int aty128fb_blank(int blank, struct fb_info *fb) | ||
2017 | { | ||
2018 | struct aty128fb_par *par = fb->par; | ||
2019 | u8 state = 0; | ||
2020 | |||
2021 | if (par->lock_blank || par->asleep) | ||
2022 | return 0; | ||
2023 | |||
2024 | #ifdef CONFIG_PMAC_BACKLIGHT | ||
2025 | if ((_machine == _MACH_Pmac) && blank) | ||
2026 | set_backlight_enable(0); | ||
2027 | #endif /* CONFIG_PMAC_BACKLIGHT */ | ||
2028 | |||
2029 | if (blank & FB_BLANK_VSYNC_SUSPEND) | ||
2030 | state |= 2; | ||
2031 | if (blank & FB_BLANK_HSYNC_SUSPEND) | ||
2032 | state |= 1; | ||
2033 | if (blank & FB_BLANK_POWERDOWN) | ||
2034 | state |= 4; | ||
2035 | |||
2036 | aty_st_8(CRTC_EXT_CNTL+1, state); | ||
2037 | |||
2038 | #ifdef CONFIG_PMAC_PBOOK | ||
2039 | if (par->chip_gen == rage_M3) { | ||
2040 | aty128_set_crt_enable(par, par->crt_on && !blank); | ||
2041 | aty128_set_lcd_enable(par, par->lcd_on && !blank); | ||
2042 | } | ||
2043 | #endif | ||
2044 | #ifdef CONFIG_PMAC_BACKLIGHT | ||
2045 | if ((_machine == _MACH_Pmac) && !blank) | ||
2046 | set_backlight_enable(1); | ||
2047 | #endif /* CONFIG_PMAC_BACKLIGHT */ | ||
2048 | return 0; | ||
2049 | } | ||
2050 | |||
2051 | /* | ||
2052 | * Set a single color register. The values supplied are already | ||
2053 | * rounded down to the hardware's capabilities (according to the | ||
2054 | * entries in the var structure). Return != 0 for invalid regno. | ||
2055 | */ | ||
2056 | static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, | ||
2057 | u_int transp, struct fb_info *info) | ||
2058 | { | ||
2059 | struct aty128fb_par *par = info->par; | ||
2060 | |||
2061 | if (regno > 255 | ||
2062 | || (par->crtc.depth == 16 && regno > 63) | ||
2063 | || (par->crtc.depth == 15 && regno > 31)) | ||
2064 | return 1; | ||
2065 | |||
2066 | red >>= 8; | ||
2067 | green >>= 8; | ||
2068 | blue >>= 8; | ||
2069 | |||
2070 | if (regno < 16) { | ||
2071 | int i; | ||
2072 | u32 *pal = info->pseudo_palette; | ||
2073 | |||
2074 | switch (par->crtc.depth) { | ||
2075 | case 15: | ||
2076 | pal[regno] = (regno << 10) | (regno << 5) | regno; | ||
2077 | break; | ||
2078 | case 16: | ||
2079 | pal[regno] = (regno << 11) | (regno << 6) | regno; | ||
2080 | break; | ||
2081 | case 24: | ||
2082 | pal[regno] = (regno << 16) | (regno << 8) | regno; | ||
2083 | break; | ||
2084 | case 32: | ||
2085 | i = (regno << 8) | regno; | ||
2086 | pal[regno] = (i << 16) | i; | ||
2087 | break; | ||
2088 | } | ||
2089 | } | ||
2090 | |||
2091 | if (par->crtc.depth == 16 && regno > 0) { | ||
2092 | /* | ||
2093 | * With the 5-6-5 split of bits for RGB at 16 bits/pixel, we | ||
2094 | * have 32 slots for R and B values but 64 slots for G values. | ||
2095 | * Thus the R and B values go in one slot but the G value | ||
2096 | * goes in a different slot, and we have to avoid disturbing | ||
2097 | * the other fields in the slots we touch. | ||
2098 | */ | ||
2099 | par->green[regno] = green; | ||
2100 | if (regno < 32) { | ||
2101 | par->red[regno] = red; | ||
2102 | par->blue[regno] = blue; | ||
2103 | aty128_st_pal(regno * 8, red, par->green[regno*2], | ||
2104 | blue, par); | ||
2105 | } | ||
2106 | red = par->red[regno/2]; | ||
2107 | blue = par->blue[regno/2]; | ||
2108 | regno <<= 2; | ||
2109 | } else if (par->crtc.bpp == 16) | ||
2110 | regno <<= 3; | ||
2111 | aty128_st_pal(regno, red, green, blue, par); | ||
2112 | |||
2113 | return 0; | ||
2114 | } | ||
2115 | |||
2116 | #define ATY_MIRROR_LCD_ON 0x00000001 | ||
2117 | #define ATY_MIRROR_CRT_ON 0x00000002 | ||
2118 | |||
2119 | /* out param: u32* backlight value: 0 to 15 */ | ||
2120 | #define FBIO_ATY128_GET_MIRROR _IOR('@', 1, __u32) | ||
2121 | /* in param: u32* backlight value: 0 to 15 */ | ||
2122 | #define FBIO_ATY128_SET_MIRROR _IOW('@', 2, __u32) | ||
2123 | |||
2124 | static int aty128fb_ioctl(struct inode *inode, struct file *file, u_int cmd, | ||
2125 | u_long arg, struct fb_info *info) | ||
2126 | { | ||
2127 | #ifdef CONFIG_PMAC_PBOOK | ||
2128 | struct aty128fb_par *par = info->par; | ||
2129 | u32 value; | ||
2130 | int rc; | ||
2131 | |||
2132 | switch (cmd) { | ||
2133 | case FBIO_ATY128_SET_MIRROR: | ||
2134 | if (par->chip_gen != rage_M3) | ||
2135 | return -EINVAL; | ||
2136 | rc = get_user(value, (__u32 __user *)arg); | ||
2137 | if (rc) | ||
2138 | return rc; | ||
2139 | par->lcd_on = (value & 0x01) != 0; | ||
2140 | par->crt_on = (value & 0x02) != 0; | ||
2141 | if (!par->crt_on && !par->lcd_on) | ||
2142 | par->lcd_on = 1; | ||
2143 | aty128_set_crt_enable(par, par->crt_on); | ||
2144 | aty128_set_lcd_enable(par, par->lcd_on); | ||
2145 | return 0; | ||
2146 | case FBIO_ATY128_GET_MIRROR: | ||
2147 | if (par->chip_gen != rage_M3) | ||
2148 | return -EINVAL; | ||
2149 | value = (par->crt_on << 1) | par->lcd_on; | ||
2150 | return put_user(value, (__u32 __user *)arg); | ||
2151 | } | ||
2152 | #endif | ||
2153 | return -EINVAL; | ||
2154 | } | ||
2155 | |||
2156 | #ifdef CONFIG_PMAC_BACKLIGHT | ||
2157 | static int backlight_conv[] = { | ||
2158 | 0xff, 0xc0, 0xb5, 0xaa, 0x9f, 0x94, 0x89, 0x7e, | ||
2159 | 0x73, 0x68, 0x5d, 0x52, 0x47, 0x3c, 0x31, 0x24 | ||
2160 | }; | ||
2161 | |||
2162 | /* We turn off the LCD completely instead of just dimming the backlight. | ||
2163 | * This provides greater power saving and the display is useless without | ||
2164 | * backlight anyway | ||
2165 | */ | ||
2166 | #define BACKLIGHT_LVDS_OFF | ||
2167 | /* That one prevents proper CRT output with LCD off */ | ||
2168 | #undef BACKLIGHT_DAC_OFF | ||
2169 | |||
2170 | static int aty128_set_backlight_enable(int on, int level, void *data) | ||
2171 | { | ||
2172 | struct aty128fb_par *par = data; | ||
2173 | unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL); | ||
2174 | |||
2175 | if (!par->lcd_on) | ||
2176 | on = 0; | ||
2177 | reg |= LVDS_BL_MOD_EN | LVDS_BLON; | ||
2178 | if (on && level > BACKLIGHT_OFF) { | ||
2179 | reg |= LVDS_DIGION; | ||
2180 | if (!(reg & LVDS_ON)) { | ||
2181 | reg &= ~LVDS_BLON; | ||
2182 | aty_st_le32(LVDS_GEN_CNTL, reg); | ||
2183 | (void)aty_ld_le32(LVDS_GEN_CNTL); | ||
2184 | mdelay(10); | ||
2185 | reg |= LVDS_BLON; | ||
2186 | aty_st_le32(LVDS_GEN_CNTL, reg); | ||
2187 | } | ||
2188 | reg &= ~LVDS_BL_MOD_LEVEL_MASK; | ||
2189 | reg |= (backlight_conv[level] << LVDS_BL_MOD_LEVEL_SHIFT); | ||
2190 | #ifdef BACKLIGHT_LVDS_OFF | ||
2191 | reg |= LVDS_ON | LVDS_EN; | ||
2192 | reg &= ~LVDS_DISPLAY_DIS; | ||
2193 | #endif | ||
2194 | aty_st_le32(LVDS_GEN_CNTL, reg); | ||
2195 | #ifdef BACKLIGHT_DAC_OFF | ||
2196 | aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN)); | ||
2197 | #endif | ||
2198 | } else { | ||
2199 | reg &= ~LVDS_BL_MOD_LEVEL_MASK; | ||
2200 | reg |= (backlight_conv[0] << LVDS_BL_MOD_LEVEL_SHIFT); | ||
2201 | #ifdef BACKLIGHT_LVDS_OFF | ||
2202 | reg |= LVDS_DISPLAY_DIS; | ||
2203 | aty_st_le32(LVDS_GEN_CNTL, reg); | ||
2204 | (void)aty_ld_le32(LVDS_GEN_CNTL); | ||
2205 | udelay(10); | ||
2206 | reg &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION); | ||
2207 | #endif | ||
2208 | aty_st_le32(LVDS_GEN_CNTL, reg); | ||
2209 | #ifdef BACKLIGHT_DAC_OFF | ||
2210 | aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN); | ||
2211 | #endif | ||
2212 | } | ||
2213 | |||
2214 | return 0; | ||
2215 | } | ||
2216 | |||
2217 | static int aty128_set_backlight_level(int level, void* data) | ||
2218 | { | ||
2219 | return aty128_set_backlight_enable(1, level, data); | ||
2220 | } | ||
2221 | #endif /* CONFIG_PMAC_BACKLIGHT */ | ||
2222 | |||
2223 | #if 0 | ||
2224 | /* | ||
2225 | * Accelerated functions | ||
2226 | */ | ||
2227 | |||
2228 | static inline void aty128_rectcopy(int srcx, int srcy, int dstx, int dsty, | ||
2229 | u_int width, u_int height, | ||
2230 | struct fb_info_aty128 *par) | ||
2231 | { | ||
2232 | u32 save_dp_datatype, save_dp_cntl, dstval; | ||
2233 | |||
2234 | if (!width || !height) | ||
2235 | return; | ||
2236 | |||
2237 | dstval = depth_to_dst(par->current_par.crtc.depth); | ||
2238 | if (dstval == DST_24BPP) { | ||
2239 | srcx *= 3; | ||
2240 | dstx *= 3; | ||
2241 | width *= 3; | ||
2242 | } else if (dstval == -EINVAL) { | ||
2243 | printk("aty128fb: invalid depth or RGBA\n"); | ||
2244 | return; | ||
2245 | } | ||
2246 | |||
2247 | wait_for_fifo(2, par); | ||
2248 | save_dp_datatype = aty_ld_le32(DP_DATATYPE); | ||
2249 | save_dp_cntl = aty_ld_le32(DP_CNTL); | ||
2250 | |||
2251 | wait_for_fifo(6, par); | ||
2252 | aty_st_le32(SRC_Y_X, (srcy << 16) | srcx); | ||
2253 | aty_st_le32(DP_MIX, ROP3_SRCCOPY | DP_SRC_RECT); | ||
2254 | aty_st_le32(DP_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); | ||
2255 | aty_st_le32(DP_DATATYPE, save_dp_datatype | dstval | SRC_DSTCOLOR); | ||
2256 | |||
2257 | aty_st_le32(DST_Y_X, (dsty << 16) | dstx); | ||
2258 | aty_st_le32(DST_HEIGHT_WIDTH, (height << 16) | width); | ||
2259 | |||
2260 | par->blitter_may_be_busy = 1; | ||
2261 | |||
2262 | wait_for_fifo(2, par); | ||
2263 | aty_st_le32(DP_DATATYPE, save_dp_datatype); | ||
2264 | aty_st_le32(DP_CNTL, save_dp_cntl); | ||
2265 | } | ||
2266 | |||
2267 | |||
2268 | /* | ||
2269 | * Text mode accelerated functions | ||
2270 | */ | ||
2271 | |||
2272 | static void fbcon_aty128_bmove(struct display *p, int sy, int sx, int dy, int dx, | ||
2273 | int height, int width) | ||
2274 | { | ||
2275 | sx *= fontwidth(p); | ||
2276 | sy *= fontheight(p); | ||
2277 | dx *= fontwidth(p); | ||
2278 | dy *= fontheight(p); | ||
2279 | width *= fontwidth(p); | ||
2280 | height *= fontheight(p); | ||
2281 | |||
2282 | aty128_rectcopy(sx, sy, dx, dy, width, height, | ||
2283 | (struct fb_info_aty128 *)p->fb_info); | ||
2284 | } | ||
2285 | #endif /* 0 */ | ||
2286 | |||
2287 | static void aty128_set_suspend(struct aty128fb_par *par, int suspend) | ||
2288 | { | ||
2289 | u32 pmgt; | ||
2290 | u16 pwr_command; | ||
2291 | struct pci_dev *pdev = par->pdev; | ||
2292 | |||
2293 | if (!par->pm_reg) | ||
2294 | return; | ||
2295 | |||
2296 | /* Set the chip into the appropriate suspend mode (we use D2, | ||
2297 | * D3 would require a complete re-initialisation of the chip, | ||
2298 | * including PCI config registers, clocks, AGP configuration, ...) | ||
2299 | */ | ||
2300 | if (suspend) { | ||
2301 | /* Make sure CRTC2 is reset. Remove that the day we decide to | ||
2302 | * actually use CRTC2 and replace it with real code for disabling | ||
2303 | * the CRTC2 output during sleep | ||
2304 | */ | ||
2305 | aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) & | ||
2306 | ~(CRTC2_EN)); | ||
2307 | |||
2308 | /* Set the power management mode to be PCI based */ | ||
2309 | /* Use this magic value for now */ | ||
2310 | pmgt = 0x0c005407; | ||
2311 | aty_st_pll(POWER_MANAGEMENT, pmgt); | ||
2312 | (void)aty_ld_pll(POWER_MANAGEMENT); | ||
2313 | aty_st_le32(BUS_CNTL1, 0x00000010); | ||
2314 | aty_st_le32(MEM_POWER_MISC, 0x0c830000); | ||
2315 | mdelay(100); | ||
2316 | pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command); | ||
2317 | /* Switch PCI power management to D2 */ | ||
2318 | pci_write_config_word(pdev, par->pm_reg+PCI_PM_CTRL, | ||
2319 | (pwr_command & ~PCI_PM_CTRL_STATE_MASK) | 2); | ||
2320 | pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command); | ||
2321 | } else { | ||
2322 | /* Switch back PCI power management to D0 */ | ||
2323 | mdelay(100); | ||
2324 | pci_write_config_word(pdev, par->pm_reg+PCI_PM_CTRL, 0); | ||
2325 | pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command); | ||
2326 | mdelay(100); | ||
2327 | } | ||
2328 | } | ||
2329 | |||
2330 | static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state) | ||
2331 | { | ||
2332 | struct fb_info *info = pci_get_drvdata(pdev); | ||
2333 | struct aty128fb_par *par = info->par; | ||
2334 | u8 agp; | ||
2335 | |||
2336 | /* We don't do anything but D2, for now we return 0, but | ||
2337 | * we may want to change that. How do we know if the BIOS | ||
2338 | * can properly take care of D3 ? Also, with swsusp, we | ||
2339 | * know we'll be rebooted, ... | ||
2340 | */ | ||
2341 | #ifdef CONFIG_PPC_PMAC | ||
2342 | /* HACK ALERT ! Once I find a proper way to say to each driver | ||
2343 | * individually what will happen with it's PCI slot, I'll change | ||
2344 | * that. On laptops, the AGP slot is just unclocked, so D2 is | ||
2345 | * expected, while on desktops, the card is powered off | ||
2346 | */ | ||
2347 | if (state >= 3) | ||
2348 | state = 2; | ||
2349 | #endif /* CONFIG_PPC_PMAC */ | ||
2350 | |||
2351 | if (state != 2 || state == pdev->dev.power.power_state) | ||
2352 | return 0; | ||
2353 | |||
2354 | printk(KERN_DEBUG "aty128fb: suspending...\n"); | ||
2355 | |||
2356 | acquire_console_sem(); | ||
2357 | |||
2358 | fb_set_suspend(info, 1); | ||
2359 | |||
2360 | /* Make sure engine is reset */ | ||
2361 | wait_for_idle(par); | ||
2362 | aty128_reset_engine(par); | ||
2363 | wait_for_idle(par); | ||
2364 | |||
2365 | /* Blank display and LCD */ | ||
2366 | aty128fb_blank(VESA_POWERDOWN, info); | ||
2367 | |||
2368 | /* Sleep */ | ||
2369 | par->asleep = 1; | ||
2370 | par->lock_blank = 1; | ||
2371 | |||
2372 | /* Disable AGP. The AGP host should have done it, but since ordering | ||
2373 | * isn't always properly guaranteed in this specific case, let's make | ||
2374 | * sure it's disabled on card side now. Ultimately, when merging fbdev | ||
2375 | * and dri into some common infrastructure, this will be handled | ||
2376 | * more nicely. The host bridge side will (or will not) be dealt with | ||
2377 | * by the bridge AGP driver, we don't attempt to touch it here. | ||
2378 | */ | ||
2379 | agp = pci_find_capability(pdev, PCI_CAP_ID_AGP); | ||
2380 | if (agp) { | ||
2381 | u32 cmd; | ||
2382 | |||
2383 | pci_read_config_dword(pdev, agp + PCI_AGP_COMMAND, &cmd); | ||
2384 | if (cmd & PCI_AGP_COMMAND_AGP) { | ||
2385 | printk(KERN_INFO "aty128fb: AGP was enabled, " | ||
2386 | "disabling ...\n"); | ||
2387 | cmd &= ~PCI_AGP_COMMAND_AGP; | ||
2388 | pci_write_config_dword(pdev, agp + PCI_AGP_COMMAND, | ||
2389 | cmd); | ||
2390 | } | ||
2391 | } | ||
2392 | |||
2393 | /* We need a way to make sure the fbdev layer will _not_ touch the | ||
2394 | * framebuffer before we put the chip to suspend state. On 2.4, I | ||
2395 | * used dummy fb ops, 2.5 need proper support for this at the | ||
2396 | * fbdev level | ||
2397 | */ | ||
2398 | if (state == 2) | ||
2399 | aty128_set_suspend(par, 1); | ||
2400 | |||
2401 | release_console_sem(); | ||
2402 | |||
2403 | pdev->dev.power.power_state = state; | ||
2404 | |||
2405 | return 0; | ||
2406 | } | ||
2407 | |||
2408 | static int aty128_do_resume(struct pci_dev *pdev) | ||
2409 | { | ||
2410 | struct fb_info *info = pci_get_drvdata(pdev); | ||
2411 | struct aty128fb_par *par = info->par; | ||
2412 | |||
2413 | if (pdev->dev.power.power_state == 0) | ||
2414 | return 0; | ||
2415 | |||
2416 | /* Wakeup chip */ | ||
2417 | if (pdev->dev.power.power_state == 2) | ||
2418 | aty128_set_suspend(par, 0); | ||
2419 | par->asleep = 0; | ||
2420 | |||
2421 | /* Restore display & engine */ | ||
2422 | aty128_reset_engine(par); | ||
2423 | wait_for_idle(par); | ||
2424 | aty128fb_set_par(info); | ||
2425 | fb_pan_display(info, &info->var); | ||
2426 | fb_set_cmap(&info->cmap, info); | ||
2427 | |||
2428 | /* Refresh */ | ||
2429 | fb_set_suspend(info, 0); | ||
2430 | |||
2431 | /* Unblank */ | ||
2432 | par->lock_blank = 0; | ||
2433 | aty128fb_blank(0, info); | ||
2434 | |||
2435 | pdev->dev.power.power_state = PMSG_ON; | ||
2436 | |||
2437 | printk(KERN_DEBUG "aty128fb: resumed !\n"); | ||
2438 | |||
2439 | return 0; | ||
2440 | } | ||
2441 | |||
2442 | static int aty128_pci_resume(struct pci_dev *pdev) | ||
2443 | { | ||
2444 | int rc; | ||
2445 | |||
2446 | acquire_console_sem(); | ||
2447 | rc = aty128_do_resume(pdev); | ||
2448 | release_console_sem(); | ||
2449 | |||
2450 | return rc; | ||
2451 | } | ||
2452 | |||
2453 | |||
2454 | static int __init aty128fb_init(void) | ||
2455 | { | ||
2456 | #ifndef MODULE | ||
2457 | char *option = NULL; | ||
2458 | |||
2459 | if (fb_get_options("aty128fb", &option)) | ||
2460 | return -ENODEV; | ||
2461 | aty128fb_setup(option); | ||
2462 | #endif | ||
2463 | |||
2464 | return pci_register_driver(&aty128fb_driver); | ||
2465 | } | ||
2466 | |||
2467 | static void __exit aty128fb_exit(void) | ||
2468 | { | ||
2469 | pci_unregister_driver(&aty128fb_driver); | ||
2470 | } | ||
2471 | |||
2472 | module_init(aty128fb_init); | ||
2473 | |||
2474 | module_exit(aty128fb_exit); | ||
2475 | |||
2476 | MODULE_AUTHOR("(c)1999-2003 Brad Douglas <brad@neruo.com>"); | ||
2477 | MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards"); | ||
2478 | MODULE_LICENSE("GPL"); | ||
2479 | module_param(mode_option, charp, 0); | ||
2480 | MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" "); | ||
2481 | #ifdef CONFIG_MTRR | ||
2482 | module_param_named(nomtrr, mtrr, invbool, 0); | ||
2483 | MODULE_PARM_DESC(nomtrr, "bool: Disable MTRR support (0 or 1=disabled) (default=0)"); | ||
2484 | #endif | ||
2485 | |||