diff options
| author | Pete Zaitcev <zaitcev@redhat.com> | 2006-04-02 14:21:26 -0400 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2006-04-14 14:12:25 -0400 |
| commit | 9fc4831cc3e063019079581ff5062f9790d9b0c7 (patch) | |
| tree | 415bd4d00751d7b3e50522435f279d591739e48f /drivers/usb/gadget | |
| parent | e1394b49ee70bd8686acaf969e4d61b57da1c263 (diff) | |
[PATCH] USB: linux/usb/net2280.h common definitions
Move common definitions for NET2280 to <linux/usb/net2280.h>, so that I can
use them in prism54usb (it is not merged yet, but I plan to do it soon).
Signed-off-by: Pete Zaitcev <zaitcev@redhat.com>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/usb/gadget')
| -rw-r--r-- | drivers/usb/gadget/net2280.h | 417 |
1 files changed, 1 insertions, 416 deletions
diff --git a/drivers/usb/gadget/net2280.h b/drivers/usb/gadget/net2280.h index e195abec8d7..957d6df3401 100644 --- a/drivers/usb/gadget/net2280.h +++ b/drivers/usb/gadget/net2280.h | |||
| @@ -22,422 +22,7 @@ | |||
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 23 | */ | 23 | */ |
| 24 | 24 | ||
| 25 | /*-------------------------------------------------------------------------*/ | 25 | #include <linux/usb/net2280.h> |
| 26 | |||
| 27 | /* NET2280 MEMORY MAPPED REGISTERS | ||
| 28 | * | ||
| 29 | * The register layout came from the chip documentation, and the bit | ||
| 30 | * number definitions were extracted from chip specification. | ||
| 31 | * | ||
| 32 | * Use the shift operator ('<<') to build bit masks, with readl/writel | ||
| 33 | * to access the registers through PCI. | ||
| 34 | */ | ||
| 35 | |||
| 36 | /* main registers, BAR0 + 0x0000 */ | ||
| 37 | struct net2280_regs { | ||
| 38 | // offset 0x0000 | ||
| 39 | u32 devinit; | ||
| 40 | #define LOCAL_CLOCK_FREQUENCY 8 | ||
| 41 | #define FORCE_PCI_RESET 7 | ||
| 42 | #define PCI_ID 6 | ||
| 43 | #define PCI_ENABLE 5 | ||
| 44 | #define FIFO_SOFT_RESET 4 | ||
| 45 | #define CFG_SOFT_RESET 3 | ||
| 46 | #define PCI_SOFT_RESET 2 | ||
| 47 | #define USB_SOFT_RESET 1 | ||
| 48 | #define M8051_RESET 0 | ||
| 49 | u32 eectl; | ||
| 50 | #define EEPROM_ADDRESS_WIDTH 23 | ||
| 51 | #define EEPROM_CHIP_SELECT_ACTIVE 22 | ||
| 52 | #define EEPROM_PRESENT 21 | ||
| 53 | #define EEPROM_VALID 20 | ||
| 54 | #define EEPROM_BUSY 19 | ||
| 55 | #define EEPROM_CHIP_SELECT_ENABLE 18 | ||
| 56 | #define EEPROM_BYTE_READ_START 17 | ||
| 57 | #define EEPROM_BYTE_WRITE_START 16 | ||
| 58 | #define EEPROM_READ_DATA 8 | ||
| 59 | #define EEPROM_WRITE_DATA 0 | ||
| 60 | u32 eeclkfreq; | ||
| 61 | u32 _unused0; | ||
| 62 | // offset 0x0010 | ||
| 63 | |||
| 64 | u32 pciirqenb0; /* interrupt PCI master ... */ | ||
| 65 | #define SETUP_PACKET_INTERRUPT_ENABLE 7 | ||
| 66 | #define ENDPOINT_F_INTERRUPT_ENABLE 6 | ||
| 67 | #define ENDPOINT_E_INTERRUPT_ENABLE 5 | ||
| 68 | #define ENDPOINT_D_INTERRUPT_ENABLE 4 | ||
| 69 | #define ENDPOINT_C_INTERRUPT_ENABLE 3 | ||
| 70 | #define ENDPOINT_B_INTERRUPT_ENABLE 2 | ||
| 71 | #define ENDPOINT_A_INTERRUPT_ENABLE 1 | ||
| 72 | #define ENDPOINT_0_INTERRUPT_ENABLE 0 | ||
| 73 | u32 pciirqenb1; | ||
| 74 | #define PCI_INTERRUPT_ENABLE 31 | ||
| 75 | #define POWER_STATE_CHANGE_INTERRUPT_ENABLE 27 | ||
| 76 | #define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE 26 | ||
| 77 | #define PCI_PARITY_ERROR_INTERRUPT_ENABLE 25 | ||
| 78 | #define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE 20 | ||
| 79 | #define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE 19 | ||
| 80 | #define PCI_TARGET_ABORT_ASSERTED_INTERRUPT_ENABLE 18 | ||
| 81 | #define PCI_RETRY_ABORT_INTERRUPT_ENABLE 17 | ||
| 82 | #define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE 16 | ||
| 83 | #define GPIO_INTERRUPT_ENABLE 13 | ||
| 84 | #define DMA_D_INTERRUPT_ENABLE 12 | ||
| 85 | #define DMA_C_INTERRUPT_ENABLE 11 | ||
| 86 | #define DMA_B_INTERRUPT_ENABLE 10 | ||
| 87 | #define DMA_A_INTERRUPT_ENABLE 9 | ||
| 88 | #define EEPROM_DONE_INTERRUPT_ENABLE 8 | ||
| 89 | #define VBUS_INTERRUPT_ENABLE 7 | ||
| 90 | #define CONTROL_STATUS_INTERRUPT_ENABLE 6 | ||
| 91 | #define ROOT_PORT_RESET_INTERRUPT_ENABLE 4 | ||
| 92 | #define SUSPEND_REQUEST_INTERRUPT_ENABLE 3 | ||
| 93 | #define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 2 | ||
| 94 | #define RESUME_INTERRUPT_ENABLE 1 | ||
| 95 | #define SOF_INTERRUPT_ENABLE 0 | ||
| 96 | u32 cpu_irqenb0; /* ... or onboard 8051 */ | ||
| 97 | #define SETUP_PACKET_INTERRUPT_ENABLE 7 | ||
| 98 | #define ENDPOINT_F_INTERRUPT_ENABLE 6 | ||
| 99 | #define ENDPOINT_E_INTERRUPT_ENABLE 5 | ||
| 100 | #define ENDPOINT_D_INTERRUPT_ENABLE 4 | ||
| 101 | #define ENDPOINT_C_INTERRUPT_ENABLE 3 | ||
| 102 | #define ENDPOINT_B_INTERRUPT_ENABLE 2 | ||
| 103 | #define ENDPOINT_A_INTERRUPT_ENABLE 1 | ||
| 104 | #define ENDPOINT_0_INTERRUPT_ENABLE 0 | ||
| 105 | u32 cpu_irqenb1; | ||
| 106 | #define CPU_INTERRUPT_ENABLE 31 | ||
| 107 | #define POWER_STATE_CHANGE_INTERRUPT_ENABLE 27 | ||
| 108 | #define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE 26 | ||
| 109 | #define PCI_PARITY_ERROR_INTERRUPT_ENABLE 25 | ||
| 110 | #define PCI_INTA_INTERRUPT_ENABLE 24 | ||
| 111 | #define PCI_PME_INTERRUPT_ENABLE 23 | ||
| 112 | #define PCI_SERR_INTERRUPT_ENABLE 22 | ||
| 113 | #define PCI_PERR_INTERRUPT_ENABLE 21 | ||
| 114 | #define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE 20 | ||
| 115 | #define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE 19 | ||
| 116 | #define PCI_RETRY_ABORT_INTERRUPT_ENABLE 17 | ||
| 117 | #define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE 16 | ||
| 118 | #define GPIO_INTERRUPT_ENABLE 13 | ||
| 119 | #define DMA_D_INTERRUPT_ENABLE 12 | ||
| 120 | #define DMA_C_INTERRUPT_ENABLE 11 | ||
| 121 | #define DMA_B_INTERRUPT_ENABLE 10 | ||
| 122 | #define DMA_A_INTERRUPT_ENABLE 9 | ||
| 123 | #define EEPROM_DONE_INTERRUPT_ENABLE 8 | ||
| 124 | #define VBUS_INTERRUPT_ENABLE 7 | ||
| 125 | #define CONTROL_STATUS_INTERRUPT_ENABLE 6 | ||
| 126 | #define ROOT_PORT_RESET_INTERRUPT_ENABLE 4 | ||
| 127 | #define SUSPEND_REQUEST_INTERRUPT_ENABLE 3 | ||
| 128 | #define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 2 | ||
| 129 | #define RESUME_INTERRUPT_ENABLE 1 | ||
| 130 | #define SOF_INTERRUPT_ENABLE 0 | ||
| 131 | |||
| 132 | // offset 0x0020 | ||
| 133 | u32 _unused1; | ||
| 134 | u32 usbirqenb1; | ||
| 135 | #define USB_INTERRUPT_ENABLE 31 | ||
| 136 | #define POWER_STATE_CHANGE_INTERRUPT_ENABLE 27 | ||
| 137 | #define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE 26 | ||
| 138 | #define PCI_PARITY_ERROR_INTERRUPT_ENABLE 25 | ||
| 139 | #define PCI_INTA_INTERRUPT_ENABLE 24 | ||
| 140 | #define PCI_PME_INTERRUPT_ENABLE 23 | ||
| 141 | #define PCI_SERR_INTERRUPT_ENABLE 22 | ||
| 142 | #define PCI_PERR_INTERRUPT_ENABLE 21 | ||
| 143 | #define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE 20 | ||
| 144 | #define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE 19 | ||
| 145 | #define PCI_RETRY_ABORT_INTERRUPT_ENABLE 17 | ||
| 146 | #define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE 16 | ||
| 147 | #define GPIO_INTERRUPT_ENABLE 13 | ||
| 148 | #define DMA_D_INTERRUPT_ENABLE 12 | ||
| 149 | #define DMA_C_INTERRUPT_ENABLE 11 | ||
| 150 | #define DMA_B_INTERRUPT_ENABLE 10 | ||
| 151 | #define DMA_A_INTERRUPT_ENABLE 9 | ||
| 152 | #define EEPROM_DONE_INTERRUPT_ENABLE 8 | ||
| 153 | #define VBUS_INTERRUPT_ENABLE 7 | ||
| 154 | #define CONTROL_STATUS_INTERRUPT_ENABLE 6 | ||
| 155 | #define ROOT_PORT_RESET_INTERRUPT_ENABLE 4 | ||
| 156 | #define SUSPEND_REQUEST_INTERRUPT_ENABLE 3 | ||
| 157 | #define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 2 | ||
| 158 | #define RESUME_INTERRUPT_ENABLE 1 | ||
| 159 | #define SOF_INTERRUPT_ENABLE 0 | ||
| 160 | u32 irqstat0; | ||
| 161 | #define INTA_ASSERTED 12 | ||
| 162 | #define SETUP_PACKET_INTERRUPT 7 | ||
| 163 | #define ENDPOINT_F_INTERRUPT 6 | ||
| 164 | #define ENDPOINT_E_INTERRUPT 5 | ||
| 165 | #define ENDPOINT_D_INTERRUPT 4 | ||
| 166 | #define ENDPOINT_C_INTERRUPT 3 | ||
| 167 | #define ENDPOINT_B_INTERRUPT 2 | ||
| 168 | #define ENDPOINT_A_INTERRUPT 1 | ||
| 169 | #define ENDPOINT_0_INTERRUPT 0 | ||
| 170 | u32 irqstat1; | ||
| 171 | #define POWER_STATE_CHANGE_INTERRUPT 27 | ||
| 172 | #define PCI_ARBITER_TIMEOUT_INTERRUPT 26 | ||
| 173 | #define PCI_PARITY_ERROR_INTERRUPT 25 | ||
| 174 | #define PCI_INTA_INTERRUPT 24 | ||
| 175 | #define PCI_PME_INTERRUPT 23 | ||
| 176 | #define PCI_SERR_INTERRUPT 22 | ||
| 177 | #define PCI_PERR_INTERRUPT 21 | ||
| 178 | #define PCI_MASTER_ABORT_RECEIVED_INTERRUPT 20 | ||
| 179 | #define PCI_TARGET_ABORT_RECEIVED_INTERRUPT 19 | ||
| 180 | #define PCI_RETRY_ABORT_INTERRUPT 17 | ||
| 181 | #define PCI_MASTER_CYCLE_DONE_INTERRUPT 16 | ||
| 182 | #define SOF_DOWN_INTERRUPT 14 | ||
| 183 | #define GPIO_INTERRUPT 13 | ||
| 184 | #define DMA_D_INTERRUPT 12 | ||
| 185 | #define DMA_C_INTERRUPT 11 | ||
| 186 | #define DMA_B_INTERRUPT 10 | ||
| 187 | #define DMA_A_INTERRUPT 9 | ||
| 188 | #define EEPROM_DONE_INTERRUPT 8 | ||
| 189 | #define VBUS_INTERRUPT 7 | ||
| 190 | #define CONTROL_STATUS_INTERRUPT 6 | ||
| 191 | #define ROOT_PORT_RESET_INTERRUPT 4 | ||
| 192 | #define SUSPEND_REQUEST_INTERRUPT 3 | ||
| 193 | #define SUSPEND_REQUEST_CHANGE_INTERRUPT 2 | ||
| 194 | #define RESUME_INTERRUPT 1 | ||
| 195 | #define SOF_INTERRUPT 0 | ||
| 196 | // offset 0x0030 | ||
| 197 | u32 idxaddr; | ||
| 198 | u32 idxdata; | ||
| 199 | u32 fifoctl; | ||
| 200 | #define PCI_BASE2_RANGE 16 | ||
| 201 | #define IGNORE_FIFO_AVAILABILITY 3 | ||
| 202 | #define PCI_BASE2_SELECT 2 | ||
| 203 | #define FIFO_CONFIGURATION_SELECT 0 | ||
| 204 | u32 _unused2; | ||
| 205 | // offset 0x0040 | ||
| 206 | u32 memaddr; | ||
| 207 | #define START 28 | ||
| 208 | #define DIRECTION 27 | ||
| 209 | #define FIFO_DIAGNOSTIC_SELECT 24 | ||
| 210 | #define MEMORY_ADDRESS 0 | ||
| 211 | u32 memdata0; | ||
| 212 | u32 memdata1; | ||
| 213 | u32 _unused3; | ||
| 214 | // offset 0x0050 | ||
| 215 | u32 gpioctl; | ||
| 216 | #define GPIO3_LED_SELECT 12 | ||
| 217 | #define GPIO3_INTERRUPT_ENABLE 11 | ||
| 218 | #define GPIO2_INTERRUPT_ENABLE 10 | ||
| 219 | #define GPIO1_INTERRUPT_ENABLE 9 | ||
| 220 | #define GPIO0_INTERRUPT_ENABLE 8 | ||
| 221 | #define GPIO3_OUTPUT_ENABLE 7 | ||
| 222 | #define GPIO2_OUTPUT_ENABLE 6 | ||
| 223 | #define GPIO1_OUTPUT_ENABLE 5 | ||
| 224 | #define GPIO0_OUTPUT_ENABLE 4 | ||
| 225 | #define GPIO3_DATA 3 | ||
| 226 | #define GPIO2_DATA 2 | ||
| 227 | #define GPIO1_DATA 1 | ||
| 228 | #define GPIO0_DATA 0 | ||
| 229 | u32 gpiostat; | ||
| 230 | #define GPIO3_INTERRUPT 3 | ||
| 231 | #define GPIO2_INTERRUPT 2 | ||
| 232 | #define GPIO1_INTERRUPT 1 | ||
| 233 | #define GPIO0_INTERRUPT 0 | ||
| 234 | } __attribute__ ((packed)); | ||
| 235 | |||
| 236 | /* usb control, BAR0 + 0x0080 */ | ||
| 237 | struct net2280_usb_regs { | ||
| 238 | // offset 0x0080 | ||
| 239 | u32 stdrsp; | ||
| 240 | #define STALL_UNSUPPORTED_REQUESTS 31 | ||
| 241 | #define SET_TEST_MODE 16 | ||
| 242 | #define GET_OTHER_SPEED_CONFIGURATION 15 | ||
| 243 | #define GET_DEVICE_QUALIFIER 14 | ||
| 244 | #define SET_ADDRESS 13 | ||
| 245 | #define ENDPOINT_SET_CLEAR_HALT 12 | ||
| 246 | #define DEVICE_SET_CLEAR_DEVICE_REMOTE_WAKEUP 11 | ||
| 247 | #define GET_STRING_DESCRIPTOR_2 10 | ||
| 248 | #define GET_STRING_DESCRIPTOR_1 9 | ||
| 249 | #define GET_STRING_DESCRIPTOR_0 8 | ||
| 250 | #define GET_SET_INTERFACE 6 | ||
| 251 | #define GET_SET_CONFIGURATION 5 | ||
| 252 | #define GET_CONFIGURATION_DESCRIPTOR 4 | ||
| 253 | #define GET_DEVICE_DESCRIPTOR 3 | ||
| 254 | #define GET_ENDPOINT_STATUS 2 | ||
| 255 | #define GET_INTERFACE_STATUS 1 | ||
| 256 | #define GET_DEVICE_STATUS 0 | ||
| 257 | u32 prodvendid; | ||
| 258 | #define PRODUCT_ID 16 | ||
| 259 | #define VENDOR_ID 0 | ||
| 260 | u32 relnum; | ||
| 261 | u32 usbctl; | ||
| 262 | #define SERIAL_NUMBER_INDEX 16 | ||
| 263 | #define PRODUCT_ID_STRING_ENABLE 13 | ||
| 264 | #define VENDOR_ID_STRING_ENABLE 12 | ||
| 265 | #define USB_ROOT_PORT_WAKEUP_ENABLE 11 | ||
| 266 | #define VBUS_PIN 10 | ||
| 267 | #define TIMED_DISCONNECT 9 | ||
| 268 | #define SUSPEND_IMMEDIATELY 7 | ||
| 269 | #define SELF_POWERED_USB_DEVICE 6 | ||
| 270 | #define REMOTE_WAKEUP_SUPPORT 5 | ||
| 271 | #define PME_POLARITY 4 | ||
| 272 | #define USB_DETECT_ENABLE 3 | ||
| 273 | #define PME_WAKEUP_ENABLE 2 | ||
| 274 | #define DEVICE_REMOTE_WAKEUP_ENABLE 1 | ||
| 275 | #define SELF_POWERED_STATUS 0 | ||
| 276 | // offset 0x0090 | ||
| 277 | u32 usbstat; | ||
| 278 | #define HIGH_SPEED 7 | ||
| 279 | #define FULL_SPEED 6 | ||
| 280 | #define GENERATE_RESUME 5 | ||
| 281 | #define GENERATE_DEVICE_REMOTE_WAKEUP 4 | ||
| 282 | u32 xcvrdiag; | ||
| 283 | #define FORCE_HIGH_SPEED_MODE 31 | ||
| 284 | #define FORCE_FULL_SPEED_MODE 30 | ||
| 285 | #define USB_TEST_MODE 24 | ||
| 286 | #define LINE_STATE 16 | ||
| 287 | #define TRANSCEIVER_OPERATION_MODE 2 | ||
| 288 | #define TRANSCEIVER_SELECT 1 | ||
| 289 | #define TERMINATION_SELECT 0 | ||
| 290 | u32 setup0123; | ||
| 291 | u32 setup4567; | ||
| 292 | // offset 0x0090 | ||
| 293 | u32 _unused0; | ||
| 294 | u32 ouraddr; | ||
| 295 | #define FORCE_IMMEDIATE 7 | ||
| 296 | #define OUR_USB_ADDRESS 0 | ||
| 297 | u32 ourconfig; | ||
| 298 | } __attribute__ ((packed)); | ||
| 299 | |||
| 300 | /* pci control, BAR0 + 0x0100 */ | ||
| 301 | struct net2280_pci_regs { | ||
| 302 | // offset 0x0100 | ||
| 303 | u32 pcimstctl; | ||
| 304 | #define PCI_ARBITER_PARK_SELECT 13 | ||
| 305 | #define PCI_MULTI LEVEL_ARBITER 12 | ||
| 306 | #define PCI_RETRY_ABORT_ENABLE 11 | ||
| 307 | #define DMA_MEMORY_WRITE_AND_INVALIDATE_ENABLE 10 | ||
| 308 | #define DMA_READ_MULTIPLE_ENABLE 9 | ||
| 309 | #define DMA_READ_LINE_ENABLE 8 | ||
| 310 | #define PCI_MASTER_COMMAND_SELECT 6 | ||
| 311 | #define MEM_READ_OR_WRITE 0 | ||
| 312 | #define IO_READ_OR_WRITE 1 | ||
| 313 | #define CFG_READ_OR_WRITE 2 | ||
| 314 | #define PCI_MASTER_START 5 | ||
| 315 | #define PCI_MASTER_READ_WRITE 4 | ||
| 316 | #define PCI_MASTER_WRITE 0 | ||
| 317 | #define PCI_MASTER_READ 1 | ||
| 318 | #define PCI_MASTER_BYTE_WRITE_ENABLES 0 | ||
| 319 | u32 pcimstaddr; | ||
| 320 | u32 pcimstdata; | ||
| 321 | u32 pcimststat; | ||
| 322 | #define PCI_ARBITER_CLEAR 2 | ||
| 323 | #define PCI_EXTERNAL_ARBITER 1 | ||
| 324 | #define PCI_HOST_MODE 0 | ||
| 325 | } __attribute__ ((packed)); | ||
| 326 | |||
| 327 | /* dma control, BAR0 + 0x0180 ... array of four structs like this, | ||
| 328 | * for channels 0..3. see also struct net2280_dma: descriptor | ||
| 329 | * that can be loaded into some of these registers. | ||
| 330 | */ | ||
| 331 | struct net2280_dma_regs { /* [11.7] */ | ||
| 332 | // offset 0x0180, 0x01a0, 0x01c0, 0x01e0, | ||
| 333 | u32 dmactl; | ||
| 334 | #define DMA_SCATTER_GATHER_DONE_INTERRUPT_ENABLE 25 | ||
| 335 | #define DMA_CLEAR_COUNT_ENABLE 21 | ||
| 336 | #define DESCRIPTOR_POLLING_RATE 19 | ||
| 337 | #define POLL_CONTINUOUS 0 | ||
| 338 | #define POLL_1_USEC 1 | ||
| 339 | #define POLL_100_USEC 2 | ||
| 340 | #define POLL_1_MSEC 3 | ||
| 341 | #define DMA_VALID_BIT_POLLING_ENABLE 18 | ||
| 342 | #define DMA_VALID_BIT_ENABLE 17 | ||
| 343 | #define DMA_SCATTER_GATHER_ENABLE 16 | ||
| 344 | #define DMA_OUT_AUTO_START_ENABLE 4 | ||
| 345 | #define DMA_PREEMPT_ENABLE 3 | ||
| 346 | #define DMA_FIFO_VALIDATE 2 | ||
| 347 | #define DMA_ENABLE 1 | ||
| 348 | #define DMA_ADDRESS_HOLD 0 | ||
| 349 | u32 dmastat; | ||
| 350 | #define DMA_ABORT_DONE_INTERRUPT 27 | ||
| 351 | #define DMA_SCATTER_GATHER_DONE_INTERRUPT 25 | ||
| 352 | #define DMA_TRANSACTION_DONE_INTERRUPT 24 | ||
| 353 | #define DMA_ABORT 1 | ||
| 354 | #define DMA_START 0 | ||
| 355 | u32 _unused0 [2]; | ||
| 356 | // offset 0x0190, 0x01b0, 0x01d0, 0x01f0, | ||
| 357 | u32 dmacount; | ||
| 358 | #define VALID_BIT 31 | ||
| 359 | #define DMA_DIRECTION 30 | ||
| 360 | #define DMA_DONE_INTERRUPT_ENABLE 29 | ||
| 361 | #define END_OF_CHAIN 28 | ||
| 362 | #define DMA_BYTE_COUNT_MASK ((1<<24)-1) | ||
| 363 | #define DMA_BYTE_COUNT 0 | ||
| 364 | u32 dmaaddr; | ||
| 365 | u32 dmadesc; | ||
| 366 | u32 _unused1; | ||
| 367 | } __attribute__ ((packed)); | ||
| 368 | |||
| 369 | /* dedicated endpoint registers, BAR0 + 0x0200 */ | ||
| 370 | |||
| 371 | struct net2280_dep_regs { /* [11.8] */ | ||
| 372 | // offset 0x0200, 0x0210, 0x220, 0x230, 0x240 | ||
| 373 | u32 dep_cfg; | ||
| 374 | // offset 0x0204, 0x0214, 0x224, 0x234, 0x244 | ||
| 375 | u32 dep_rsp; | ||
| 376 | u32 _unused [2]; | ||
| 377 | } __attribute__ ((packed)); | ||
| 378 | |||
| 379 | /* configurable endpoint registers, BAR0 + 0x0300 ... array of seven structs | ||
| 380 | * like this, for ep0 then the configurable endpoints A..F | ||
| 381 | * ep0 reserved for control; E and F have only 64 bytes of fifo | ||
| 382 | */ | ||
| 383 | struct net2280_ep_regs { /* [11.9] */ | ||
| 384 | // offset 0x0300, 0x0320, 0x0340, 0x0360, 0x0380, 0x03a0, 0x03c0 | ||
| 385 | u32 ep_cfg; | ||
| 386 | #define ENDPOINT_BYTE_COUNT 16 | ||
| 387 | #define ENDPOINT_ENABLE 10 | ||
| 388 | #define ENDPOINT_TYPE 8 | ||
| 389 | #define ENDPOINT_DIRECTION 7 | ||
| 390 | #define ENDPOINT_NUMBER 0 | ||
| 391 | u32 ep_rsp; | ||
| 392 | #define SET_NAK_OUT_PACKETS 15 | ||
| 393 | #define SET_EP_HIDE_STATUS_PHASE 14 | ||
| 394 | #define SET_EP_FORCE_CRC_ERROR 13 | ||
| 395 | #define SET_INTERRUPT_MODE 12 | ||
| 396 | #define SET_CONTROL_STATUS_PHASE_HANDSHAKE 11 | ||
| 397 | #define SET_NAK_OUT_PACKETS_MODE 10 | ||
| 398 | #define SET_ENDPOINT_TOGGLE 9 | ||
| 399 | #define SET_ENDPOINT_HALT 8 | ||
| 400 | #define CLEAR_NAK_OUT_PACKETS 7 | ||
| 401 | #define CLEAR_EP_HIDE_STATUS_PHASE 6 | ||
| 402 | #define CLEAR_EP_FORCE_CRC_ERROR 5 | ||
| 403 | #define CLEAR_INTERRUPT_MODE 4 | ||
| 404 | #define CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE 3 | ||
| 405 | #define CLEAR_NAK_OUT_PACKETS_MODE 2 | ||
| 406 | #define CLEAR_ENDPOINT_TOGGLE 1 | ||
| 407 | #define CLEAR_ENDPOINT_HALT 0 | ||
| 408 | u32 ep_irqenb; | ||
| 409 | #define SHORT_PACKET_OUT_DONE_INTERRUPT_ENABLE 6 | ||
| 410 | #define SHORT_PACKET_TRANSFERRED_INTERRUPT_ENABLE 5 | ||
| 411 | #define DATA_PACKET_RECEIVED_INTERRUPT_ENABLE 3 | ||
| 412 | #define DATA_PACKET_TRANSMITTED_INTERRUPT_ENABLE 2 | ||
| 413 | #define DATA_OUT_PING_TOKEN_INTERRUPT_ENABLE 1 | ||
| 414 | #define DATA_IN_TOKEN_INTERRUPT_ENABLE 0 | ||
| 415 | u32 ep_stat; | ||
| 416 | #define FIFO_VALID_COUNT 24 | ||
| 417 | #define HIGH_BANDWIDTH_OUT_TRANSACTION_PID 22 | ||
| 418 | #define TIMEOUT 21 | ||
| 419 | #define USB_STALL_SENT 20 | ||
| 420 | #define USB_IN_NAK_SENT 19 | ||
| 421 | #define USB_IN_ACK_RCVD 18 | ||
| 422 | #define USB_OUT_PING_NAK_SENT 17 | ||
| 423 | #define USB_OUT_ACK_SENT 16 | ||
| 424 | #define FIFO_OVERFLOW 13 | ||
| 425 | #define FIFO_UNDERFLOW 12 | ||
| 426 | #define FIFO_FULL 11 | ||
| 427 | #define FIFO_EMPTY 10 | ||
| 428 | #define FIFO_FLUSH 9 | ||
| 429 | #define SHORT_PACKET_OUT_DONE_INTERRUPT 6 | ||
| 430 | #define SHORT_PACKET_TRANSFERRED_INTERRUPT 5 | ||
| 431 | #define NAK_OUT_PACKETS 4 | ||
| 432 | #define DATA_PACKET_RECEIVED_INTERRUPT 3 | ||
| 433 | #define DATA_PACKET_TRANSMITTED_INTERRUPT 2 | ||
| 434 | #define DATA_OUT_PING_TOKEN_INTERRUPT 1 | ||
| 435 | #define DATA_IN_TOKEN_INTERRUPT 0 | ||
| 436 | // offset 0x0310, 0x0330, 0x0350, 0x0370, 0x0390, 0x03b0, 0x03d0 | ||
| 437 | u32 ep_avail; | ||
| 438 | u32 ep_data; | ||
| 439 | u32 _unused0 [2]; | ||
| 440 | } __attribute__ ((packed)); | ||
| 441 | 26 | ||
| 442 | /*-------------------------------------------------------------------------*/ | 27 | /*-------------------------------------------------------------------------*/ |
| 443 | 28 | ||