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authorMagnus Damm <damm@igel.co.jp>2009-07-22 10:41:35 -0400
committerPaul Mundt <lethal@linux-sh.org>2009-07-23 00:04:15 -0400
commit2c59b0b70b9d5d61c726f179724660c4c2423f31 (patch)
treedc7629d1ed0627f3651669d8b483f88a8cd4955e /drivers/usb/gadget/m66592-udc.h
parentcf4f1e76c49dacfde0680b170b9a9b6a42f296bb (diff)
usb: m66592-udc platform data on_chip support
Convert the m66592-udc driver to use the on_chip flag from platform data to enable on chip behaviour instead of relying on CONFIG_SUPERH_BUILT_IN_M66592 ugliness. This makes the code cleaner and also allows us to support both external and internal m66592 with the same kernel. It also makes the Kconfig part more future proof since we with this patch can add support for new processors with on-chip m66592 without modifying the Kconfig. The patch adds a m66592 header file for platform data and ties in platform data to the existing m66592 devices. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'drivers/usb/gadget/m66592-udc.h')
-rw-r--r--drivers/usb/gadget/m66592-udc.h89
1 files changed, 45 insertions, 44 deletions
diff --git a/drivers/usb/gadget/m66592-udc.h b/drivers/usb/gadget/m66592-udc.h
index 9a9c2bf9fbd..8b960deed68 100644
--- a/drivers/usb/gadget/m66592-udc.h
+++ b/drivers/usb/gadget/m66592-udc.h
@@ -23,10 +23,12 @@
23#ifndef __M66592_UDC_H__ 23#ifndef __M66592_UDC_H__
24#define __M66592_UDC_H__ 24#define __M66592_UDC_H__
25 25
26#if defined(CONFIG_SUPERH_BUILT_IN_M66592) && defined(CONFIG_HAVE_CLK) 26#ifdef CONFIG_HAVE_CLK
27#include <linux/clk.h> 27#include <linux/clk.h>
28#endif 28#endif
29 29
30#include <linux/usb/m66592.h>
31
30#define M66592_SYSCFG 0x00 32#define M66592_SYSCFG 0x00
31#define M66592_XTAL 0xC000 /* b15-14: Crystal selection */ 33#define M66592_XTAL 0xC000 /* b15-14: Crystal selection */
32#define M66592_XTAL48 0x8000 /* 48MHz */ 34#define M66592_XTAL48 0x8000 /* 48MHz */
@@ -76,11 +78,11 @@
76#define M66592_P_TST_J 0x0001 /* PERI TEST J */ 78#define M66592_P_TST_J 0x0001 /* PERI TEST J */
77#define M66592_P_TST_NORMAL 0x0000 /* PERI Normal Mode */ 79#define M66592_P_TST_NORMAL 0x0000 /* PERI Normal Mode */
78 80
79#if defined(CONFIG_SUPERH_BUILT_IN_M66592) 81/* built-in registers */
80#define M66592_CFBCFG 0x0A 82#define M66592_CFBCFG 0x0A
81#define M66592_D0FBCFG 0x0C 83#define M66592_D0FBCFG 0x0C
82#define M66592_LITTLE 0x0100 /* b8: Little endian mode */ 84#define M66592_LITTLE 0x0100 /* b8: Little endian mode */
83#else 85/* external chip case */
84#define M66592_PINCFG 0x0A 86#define M66592_PINCFG 0x0A
85#define M66592_LDRV 0x8000 /* b15: Drive Current Adjust */ 87#define M66592_LDRV 0x8000 /* b15: Drive Current Adjust */
86#define M66592_BIGEND 0x0100 /* b8: Big endian mode */ 88#define M66592_BIGEND 0x0100 /* b8: Big endian mode */
@@ -100,8 +102,8 @@
100#define M66592_PKTM 0x0020 /* b5: Packet mode */ 102#define M66592_PKTM 0x0020 /* b5: Packet mode */
101#define M66592_DENDE 0x0010 /* b4: Dend enable */ 103#define M66592_DENDE 0x0010 /* b4: Dend enable */
102#define M66592_OBUS 0x0004 /* b2: OUTbus mode */ 104#define M66592_OBUS 0x0004 /* b2: OUTbus mode */
103#endif /* #if defined(CONFIG_SUPERH_BUILT_IN_M66592) */
104 105
106/* common case */
105#define M66592_CFIFO 0x10 107#define M66592_CFIFO 0x10
106#define M66592_D0FIFO 0x14 108#define M66592_D0FIFO 0x14
107#define M66592_D1FIFO 0x18 109#define M66592_D1FIFO 0x18
@@ -113,13 +115,9 @@
113#define M66592_REW 0x4000 /* b14: Buffer rewind */ 115#define M66592_REW 0x4000 /* b14: Buffer rewind */
114#define M66592_DCLRM 0x2000 /* b13: DMA buffer clear mode */ 116#define M66592_DCLRM 0x2000 /* b13: DMA buffer clear mode */
115#define M66592_DREQE 0x1000 /* b12: DREQ output enable */ 117#define M66592_DREQE 0x1000 /* b12: DREQ output enable */
116#if defined(CONFIG_SUPERH_BUILT_IN_M66592) 118#define M66592_MBW_8 0x0000 /* 8bit */
117#define M66592_MBW 0x0800 /* b11: Maximum bit width for FIFO */ 119#define M66592_MBW_16 0x0400 /* 16bit */
118#else 120#define M66592_MBW_32 0x0800 /* 32bit */
119#define M66592_MBW 0x0400 /* b10: Maximum bit width for FIFO */
120#define M66592_MBW_8 0x0000 /* 8bit */
121#define M66592_MBW_16 0x0400 /* 16bit */
122#endif /* #if defined(CONFIG_SUPERH_BUILT_IN_M66592) */
123#define M66592_TRENB 0x0200 /* b9: Transaction counter enable */ 121#define M66592_TRENB 0x0200 /* b9: Transaction counter enable */
124#define M66592_TRCLR 0x0100 /* b8: Transaction counter clear */ 122#define M66592_TRCLR 0x0100 /* b8: Transaction counter clear */
125#define M66592_DEZPM 0x0080 /* b7: Zero-length packet mode */ 123#define M66592_DEZPM 0x0080 /* b7: Zero-length packet mode */
@@ -480,9 +478,11 @@ struct m66592_ep {
480struct m66592 { 478struct m66592 {
481 spinlock_t lock; 479 spinlock_t lock;
482 void __iomem *reg; 480 void __iomem *reg;
483#if defined(CONFIG_SUPERH_BUILT_IN_M66592) && defined(CONFIG_HAVE_CLK) 481#ifdef CONFIG_HAVE_CLK
484 struct clk *clk; 482 struct clk *clk;
485#endif 483#endif
484 struct m66592_platdata *pdata;
485 unsigned long irq_trigger;
486 486
487 struct usb_gadget gadget; 487 struct usb_gadget gadget;
488 struct usb_gadget_driver *driver; 488 struct usb_gadget_driver *driver;
@@ -546,13 +546,13 @@ static inline void m66592_read_fifo(struct m66592 *m66592,
546{ 546{
547 unsigned long fifoaddr = (unsigned long)m66592->reg + offset; 547 unsigned long fifoaddr = (unsigned long)m66592->reg + offset;
548 548
549#if defined(CONFIG_SUPERH_BUILT_IN_M66592) 549 if (m66592->pdata->on_chip) {
550 len = (len + 3) / 4; 550 len = (len + 3) / 4;
551 insl(fifoaddr, buf, len); 551 insl(fifoaddr, buf, len);
552#else 552 } else {
553 len = (len + 1) / 2; 553 len = (len + 1) / 2;
554 insw(fifoaddr, buf, len); 554 insw(fifoaddr, buf, len);
555#endif 555 }
556} 556}
557 557
558static inline void m66592_write(struct m66592 *m66592, u16 val, 558static inline void m66592_write(struct m66592 *m66592, u16 val,
@@ -566,33 +566,34 @@ static inline void m66592_write_fifo(struct m66592 *m66592,
566 void *buf, unsigned long len) 566 void *buf, unsigned long len)
567{ 567{
568 unsigned long fifoaddr = (unsigned long)m66592->reg + offset; 568 unsigned long fifoaddr = (unsigned long)m66592->reg + offset;
569#if defined(CONFIG_SUPERH_BUILT_IN_M66592) 569
570 unsigned long count; 570 if (m66592->pdata->on_chip) {
571 unsigned char *pb; 571 unsigned long count;
572 int i; 572 unsigned char *pb;
573 573 int i;
574 count = len / 4; 574
575 outsl(fifoaddr, buf, count); 575 count = len / 4;
576 576 outsl(fifoaddr, buf, count);
577 if (len & 0x00000003) { 577
578 pb = buf + count * 4; 578 if (len & 0x00000003) {
579 for (i = 0; i < (len & 0x00000003); i++) { 579 pb = buf + count * 4;
580 if (m66592_read(m66592, M66592_CFBCFG)) /* little */ 580 for (i = 0; i < (len & 0x00000003); i++) {
581 outb(pb[i], fifoaddr + (3 - i)); 581 if (m66592_read(m66592, M66592_CFBCFG)) /* le */
582 else 582 outb(pb[i], fifoaddr + (3 - i));
583 outb(pb[i], fifoaddr + i); 583 else
584 outb(pb[i], fifoaddr + i);
585 }
586 }
587 } else {
588 unsigned long odd = len & 0x0001;
589
590 len = len / 2;
591 outsw(fifoaddr, buf, len);
592 if (odd) {
593 unsigned char *p = buf + len*2;
594 outb(*p, fifoaddr);
584 } 595 }
585 } 596 }
586#else
587 unsigned long odd = len & 0x0001;
588
589 len = len / 2;
590 outsw(fifoaddr, buf, len);
591 if (odd) {
592 unsigned char *p = buf + len*2;
593 outb(*p, fifoaddr);
594 }
595#endif /* #if defined(CONFIG_SUPERH_BUILT_IN_M66592) */
596} 597}
597 598
598static inline void m66592_mdfy(struct m66592 *m66592, u16 val, u16 pat, 599static inline void m66592_mdfy(struct m66592 *m66592, u16 val, u16 pat,