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authorJiri Kosina <jkosina@suse.cz>2011-04-26 04:22:15 -0400
committerJiri Kosina <jkosina@suse.cz>2011-04-26 04:22:59 -0400
commit07f9479a40cc778bc1462ada11f95b01360ae4ff (patch)
tree0676cf38df3844004bb3ebfd99dfa67a4a8998f5 /drivers/tty/serial/imx.c
parent9d5e6bdb3013acfb311ab407eeca0b6a6a3dedbf (diff)
parentcd2e49e90f1cae7726c9a2c54488d881d7f1cd1c (diff)
Merge branch 'master' into for-next
Fast-forwarded to current state of Linus' tree as there are patches to be applied for files that didn't exist on the old branch.
Diffstat (limited to 'drivers/tty/serial/imx.c')
-rw-r--r--drivers/tty/serial/imx.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index dfcf4b1878a..62df72d9f0a 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -78,7 +78,7 @@
78#define URXD_FRMERR (1<<12) 78#define URXD_FRMERR (1<<12)
79#define URXD_BRK (1<<11) 79#define URXD_BRK (1<<11)
80#define URXD_PRERR (1<<10) 80#define URXD_PRERR (1<<10)
81#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ 81#define UCR1_ADEN (1<<15) /* Auto detect interrupt */
82#define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 82#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
83#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 83#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
84#define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 84#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
@@ -382,12 +382,13 @@ static void imx_start_tx(struct uart_port *port)
382static irqreturn_t imx_rtsint(int irq, void *dev_id) 382static irqreturn_t imx_rtsint(int irq, void *dev_id)
383{ 383{
384 struct imx_port *sport = dev_id; 384 struct imx_port *sport = dev_id;
385 unsigned int val = readl(sport->port.membase + USR1) & USR1_RTSS; 385 unsigned int val;
386 unsigned long flags; 386 unsigned long flags;
387 387
388 spin_lock_irqsave(&sport->port.lock, flags); 388 spin_lock_irqsave(&sport->port.lock, flags);
389 389
390 writel(USR1_RTSD, sport->port.membase + USR1); 390 writel(USR1_RTSD, sport->port.membase + USR1);
391 val = readl(sport->port.membase + USR1) & USR1_RTSS;
391 uart_handle_cts_change(&sport->port, !!val); 392 uart_handle_cts_change(&sport->port, !!val);
392 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 393 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
393 394