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authorDavid Woodhouse <dwmw2@infradead.org>2006-05-24 04:22:21 -0400
committerDavid Woodhouse <dwmw2@infradead.org>2006-05-24 04:22:21 -0400
commit66643de455c27973ac31ad6de9f859d399916842 (patch)
tree7ebed7f051879007d4b11d6aaa9e65a1bcb0b08f /drivers/spi
parent2c23d62abb820e19c54012520f08a198c2233a85 (diff)
parent387e2b0439026aa738a9edca15a57e5c0bcb4dfc (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Conflicts: include/asm-powerpc/unistd.h include/asm-sparc/unistd.h include/asm-sparc64/unistd.h Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Diffstat (limited to 'drivers/spi')
-rw-r--r--drivers/spi/Kconfig34
-rw-r--r--drivers/spi/Makefile4
-rw-r--r--drivers/spi/pxa2xx_spi.c1486
-rw-r--r--drivers/spi/spi.c13
-rw-r--r--drivers/spi/spi_bitbang.c104
-rw-r--r--drivers/spi/spi_butterfly.c1
-rw-r--r--drivers/spi/spi_mpc83xx.c483
-rw-r--r--drivers/spi/spi_s3c24xx.c453
-rw-r--r--drivers/spi/spi_s3c24xx_gpio.c188
9 files changed, 2740 insertions, 26 deletions
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 7a75faeb052..23334c8bc4c 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -75,11 +75,45 @@ config SPI_BUTTERFLY
75 inexpensive battery powered microcontroller evaluation board. 75 inexpensive battery powered microcontroller evaluation board.
76 This same cable can be used to flash new firmware. 76 This same cable can be used to flash new firmware.
77 77
78config SPI_MPC83xx
79 tristate "Freescale MPC83xx SPI controller"
80 depends on SPI_MASTER && PPC_83xx && EXPERIMENTAL
81 select SPI_BITBANG
82 help
83 This enables using the Freescale MPC83xx SPI controller in master
84 mode.
85
86 Note, this driver uniquely supports the SPI controller on the MPC83xx
87 family of PowerPC processors. The MPC83xx uses a simple set of shift
88 registers for data (opposed to the CPM based descriptor model).
89
90config SPI_PXA2XX
91 tristate "PXA2xx SSP SPI master"
92 depends on SPI_MASTER && ARCH_PXA && EXPERIMENTAL
93 help
94 This enables using a PXA2xx SSP port as a SPI master controller.
95 The driver can be configured to use any SSP port and additional
96 documentation can be found a Documentation/spi/pxa2xx.
97
98config SPI_S3C24XX_GPIO
99 tristate "Samsung S3C24XX series SPI by GPIO"
100 depends on SPI_MASTER && ARCH_S3C2410 && SPI_BITBANG && EXPERIMENTAL
101 help
102 SPI driver for Samsung S3C24XX series ARM SoCs using
103 GPIO lines to provide the SPI bus. This can be used where
104 the inbuilt hardware cannot provide the transfer mode, or
105 where the board is using non hardware connected pins.
78# 106#
79# Add new SPI master controllers in alphabetical order above this line 107# Add new SPI master controllers in alphabetical order above this line
80# 108#
81 109
82 110
111config SPI_S3C24XX
112 tristate "Samsung S3C24XX series SPI"
113 depends on SPI_MASTER && ARCH_S3C2410 && EXPERIMENTAL
114 help
115 SPI driver for Samsung S3C24XX series ARM SoCs
116
83# 117#
84# There are lots of SPI device types, with sensors and memory 118# There are lots of SPI device types, with sensors and memory
85# being probably the most widely used ones. 119# being probably the most widely used ones.
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index c2c87e845ab..8f4cb67997b 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -13,6 +13,10 @@ obj-$(CONFIG_SPI_MASTER) += spi.o
13# SPI master controller drivers (bus) 13# SPI master controller drivers (bus)
14obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o 14obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o
15obj-$(CONFIG_SPI_BUTTERFLY) += spi_butterfly.o 15obj-$(CONFIG_SPI_BUTTERFLY) += spi_butterfly.o
16obj-$(CONFIG_SPI_PXA2XX) += pxa2xx_spi.o
17obj-$(CONFIG_SPI_MPC83xx) += spi_mpc83xx.o
18obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o
19obj-$(CONFIG_SPI_S3C24XX) += spi_s3c24xx.o
16# ... add above this line ... 20# ... add above this line ...
17 21
18# SPI protocol drivers (device/link on bus) 22# SPI protocol drivers (device/link on bus)
diff --git a/drivers/spi/pxa2xx_spi.c b/drivers/spi/pxa2xx_spi.c
new file mode 100644
index 00000000000..29aec77f98b
--- /dev/null
+++ b/drivers/spi/pxa2xx_spi.c
@@ -0,0 +1,1486 @@
1/*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19#include <linux/init.h>
20#include <linux/module.h>
21#include <linux/device.h>
22#include <linux/ioport.h>
23#include <linux/errno.h>
24#include <linux/interrupt.h>
25#include <linux/platform_device.h>
26#include <linux/dma-mapping.h>
27#include <linux/spi/spi.h>
28#include <linux/workqueue.h>
29#include <linux/errno.h>
30#include <linux/delay.h>
31
32#include <asm/io.h>
33#include <asm/irq.h>
34#include <asm/hardware.h>
35#include <asm/delay.h>
36#include <asm/dma.h>
37
38#include <asm/arch/hardware.h>
39#include <asm/arch/pxa-regs.h>
40#include <asm/arch/pxa2xx_spi.h>
41
42MODULE_AUTHOR("Stephen Street");
43MODULE_DESCRIPTION("PXA2xx SSP SPI Contoller");
44MODULE_LICENSE("GPL");
45
46#define MAX_BUSES 3
47
48#define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
49#define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK)
50#define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0)
51
52#define DEFINE_SSP_REG(reg, off) \
53static inline u32 read_##reg(void *p) { return __raw_readl(p + (off)); } \
54static inline void write_##reg(u32 v, void *p) { __raw_writel(v, p + (off)); }
55
56DEFINE_SSP_REG(SSCR0, 0x00)
57DEFINE_SSP_REG(SSCR1, 0x04)
58DEFINE_SSP_REG(SSSR, 0x08)
59DEFINE_SSP_REG(SSITR, 0x0c)
60DEFINE_SSP_REG(SSDR, 0x10)
61DEFINE_SSP_REG(SSTO, 0x28)
62DEFINE_SSP_REG(SSPSP, 0x2c)
63
64#define START_STATE ((void*)0)
65#define RUNNING_STATE ((void*)1)
66#define DONE_STATE ((void*)2)
67#define ERROR_STATE ((void*)-1)
68
69#define QUEUE_RUNNING 0
70#define QUEUE_STOPPED 1
71
72struct driver_data {
73 /* Driver model hookup */
74 struct platform_device *pdev;
75
76 /* SPI framework hookup */
77 enum pxa_ssp_type ssp_type;
78 struct spi_master *master;
79
80 /* PXA hookup */
81 struct pxa2xx_spi_master *master_info;
82
83 /* DMA setup stuff */
84 int rx_channel;
85 int tx_channel;
86 u32 *null_dma_buf;
87
88 /* SSP register addresses */
89 void *ioaddr;
90 u32 ssdr_physical;
91
92 /* SSP masks*/
93 u32 dma_cr1;
94 u32 int_cr1;
95 u32 clear_sr;
96 u32 mask_sr;
97
98 /* Driver message queue */
99 struct workqueue_struct *workqueue;
100 struct work_struct pump_messages;
101 spinlock_t lock;
102 struct list_head queue;
103 int busy;
104 int run;
105
106 /* Message Transfer pump */
107 struct tasklet_struct pump_transfers;
108
109 /* Current message transfer state info */
110 struct spi_message* cur_msg;
111 struct spi_transfer* cur_transfer;
112 struct chip_data *cur_chip;
113 size_t len;
114 void *tx;
115 void *tx_end;
116 void *rx;
117 void *rx_end;
118 int dma_mapped;
119 dma_addr_t rx_dma;
120 dma_addr_t tx_dma;
121 size_t rx_map_len;
122 size_t tx_map_len;
123 u8 n_bytes;
124 u32 dma_width;
125 int cs_change;
126 void (*write)(struct driver_data *drv_data);
127 void (*read)(struct driver_data *drv_data);
128 irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
129 void (*cs_control)(u32 command);
130};
131
132struct chip_data {
133 u32 cr0;
134 u32 cr1;
135 u32 to;
136 u32 psp;
137 u32 timeout;
138 u8 n_bytes;
139 u32 dma_width;
140 u32 dma_burst_size;
141 u32 threshold;
142 u32 dma_threshold;
143 u8 enable_dma;
144 u8 bits_per_word;
145 u32 speed_hz;
146 void (*write)(struct driver_data *drv_data);
147 void (*read)(struct driver_data *drv_data);
148 void (*cs_control)(u32 command);
149};
150
151static void pump_messages(void *data);
152
153static int flush(struct driver_data *drv_data)
154{
155 unsigned long limit = loops_per_jiffy << 1;
156
157 void *reg = drv_data->ioaddr;
158
159 do {
160 while (read_SSSR(reg) & SSSR_RNE) {
161 read_SSDR(reg);
162 }
163 } while ((read_SSSR(reg) & SSSR_BSY) && limit--);
164 write_SSSR(SSSR_ROR, reg);
165
166 return limit;
167}
168
169static void restore_state(struct driver_data *drv_data)
170{
171 void *reg = drv_data->ioaddr;
172
173 /* Clear status and disable clock */
174 write_SSSR(drv_data->clear_sr, reg);
175 write_SSCR0(drv_data->cur_chip->cr0 & ~SSCR0_SSE, reg);
176
177 /* Load the registers */
178 write_SSCR1(drv_data->cur_chip->cr1, reg);
179 write_SSCR0(drv_data->cur_chip->cr0, reg);
180 if (drv_data->ssp_type != PXA25x_SSP) {
181 write_SSTO(0, reg);
182 write_SSPSP(drv_data->cur_chip->psp, reg);
183 }
184}
185
186static void null_cs_control(u32 command)
187{
188}
189
190static void null_writer(struct driver_data *drv_data)
191{
192 void *reg = drv_data->ioaddr;
193 u8 n_bytes = drv_data->n_bytes;
194
195 while ((read_SSSR(reg) & SSSR_TNF)
196 && (drv_data->tx < drv_data->tx_end)) {
197 write_SSDR(0, reg);
198 drv_data->tx += n_bytes;
199 }
200}
201
202static void null_reader(struct driver_data *drv_data)
203{
204 void *reg = drv_data->ioaddr;
205 u8 n_bytes = drv_data->n_bytes;
206
207 while ((read_SSSR(reg) & SSSR_RNE)
208 && (drv_data->rx < drv_data->rx_end)) {
209 read_SSDR(reg);
210 drv_data->rx += n_bytes;
211 }
212}
213
214static void u8_writer(struct driver_data *drv_data)
215{
216 void *reg = drv_data->ioaddr;
217
218 while ((read_SSSR(reg) & SSSR_TNF)
219 && (drv_data->tx < drv_data->tx_end)) {
220 write_SSDR(*(u8 *)(drv_data->tx), reg);
221 ++drv_data->tx;
222 }
223}
224
225static void u8_reader(struct driver_data *drv_data)
226{
227 void *reg = drv_data->ioaddr;
228
229 while ((read_SSSR(reg) & SSSR_RNE)
230 && (drv_data->rx < drv_data->rx_end)) {
231 *(u8 *)(drv_data->rx) = read_SSDR(reg);
232 ++drv_data->rx;
233 }
234}
235
236static void u16_writer(struct driver_data *drv_data)
237{
238 void *reg = drv_data->ioaddr;
239
240 while ((read_SSSR(reg) & SSSR_TNF)
241 && (drv_data->tx < drv_data->tx_end)) {
242 write_SSDR(*(u16 *)(drv_data->tx), reg);
243 drv_data->tx += 2;
244 }
245}
246
247static void u16_reader(struct driver_data *drv_data)
248{
249 void *reg = drv_data->ioaddr;
250
251 while ((read_SSSR(reg) & SSSR_RNE)
252 && (drv_data->rx < drv_data->rx_end)) {
253 *(u16 *)(drv_data->rx) = read_SSDR(reg);
254 drv_data->rx += 2;
255 }
256}
257static void u32_writer(struct driver_data *drv_data)
258{
259 void *reg = drv_data->ioaddr;
260
261 while ((read_SSSR(reg) & SSSR_TNF)
262 && (drv_data->tx < drv_data->tx_end)) {
263 write_SSDR(*(u32 *)(drv_data->tx), reg);
264 drv_data->tx += 4;
265 }
266}
267
268static void u32_reader(struct driver_data *drv_data)
269{
270 void *reg = drv_data->ioaddr;
271
272 while ((read_SSSR(reg) & SSSR_RNE)
273 && (drv_data->rx < drv_data->rx_end)) {
274 *(u32 *)(drv_data->rx) = read_SSDR(reg);
275 drv_data->rx += 4;
276 }
277}
278
279static void *next_transfer(struct driver_data *drv_data)
280{
281 struct spi_message *msg = drv_data->cur_msg;
282 struct spi_transfer *trans = drv_data->cur_transfer;
283
284 /* Move to next transfer */
285 if (trans->transfer_list.next != &msg->transfers) {
286 drv_data->cur_transfer =
287 list_entry(trans->transfer_list.next,
288 struct spi_transfer,
289 transfer_list);
290 return RUNNING_STATE;
291 } else
292 return DONE_STATE;
293}
294
295static int map_dma_buffers(struct driver_data *drv_data)
296{
297 struct spi_message *msg = drv_data->cur_msg;
298 struct device *dev = &msg->spi->dev;
299
300 if (!drv_data->cur_chip->enable_dma)
301 return 0;
302
303 if (msg->is_dma_mapped)
304 return drv_data->rx_dma && drv_data->tx_dma;
305
306 if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx))
307 return 0;
308
309 /* Modify setup if rx buffer is null */
310 if (drv_data->rx == NULL) {
311 *drv_data->null_dma_buf = 0;
312 drv_data->rx = drv_data->null_dma_buf;
313 drv_data->rx_map_len = 4;
314 } else
315 drv_data->rx_map_len = drv_data->len;
316
317
318 /* Modify setup if tx buffer is null */
319 if (drv_data->tx == NULL) {
320 *drv_data->null_dma_buf = 0;
321 drv_data->tx = drv_data->null_dma_buf;
322 drv_data->tx_map_len = 4;
323 } else
324 drv_data->tx_map_len = drv_data->len;
325
326 /* Stream map the rx buffer */
327 drv_data->rx_dma = dma_map_single(dev, drv_data->rx,
328 drv_data->rx_map_len,
329 DMA_FROM_DEVICE);
330 if (dma_mapping_error(drv_data->rx_dma))
331 return 0;
332
333 /* Stream map the tx buffer */
334 drv_data->tx_dma = dma_map_single(dev, drv_data->tx,
335 drv_data->tx_map_len,
336 DMA_TO_DEVICE);
337
338 if (dma_mapping_error(drv_data->tx_dma)) {
339 dma_unmap_single(dev, drv_data->rx_dma,
340 drv_data->rx_map_len, DMA_FROM_DEVICE);
341 return 0;
342 }
343
344 return 1;
345}
346
347static void unmap_dma_buffers(struct driver_data *drv_data)
348{
349 struct device *dev;
350
351 if (!drv_data->dma_mapped)
352 return;
353
354 if (!drv_data->cur_msg->is_dma_mapped) {
355 dev = &drv_data->cur_msg->spi->dev;
356 dma_unmap_single(dev, drv_data->rx_dma,
357 drv_data->rx_map_len, DMA_FROM_DEVICE);
358 dma_unmap_single(dev, drv_data->tx_dma,
359 drv_data->tx_map_len, DMA_TO_DEVICE);
360 }
361
362 drv_data->dma_mapped = 0;
363}
364
365/* caller already set message->status; dma and pio irqs are blocked */
366static void giveback(struct driver_data *drv_data)
367{
368 struct spi_transfer* last_transfer;
369 unsigned long flags;
370 struct spi_message *msg;
371
372 spin_lock_irqsave(&drv_data->lock, flags);
373 msg = drv_data->cur_msg;
374 drv_data->cur_msg = NULL;
375 drv_data->cur_transfer = NULL;
376 drv_data->cur_chip = NULL;
377 queue_work(drv_data->workqueue, &drv_data->pump_messages);
378 spin_unlock_irqrestore(&drv_data->lock, flags);
379
380 last_transfer = list_entry(msg->transfers.prev,
381 struct spi_transfer,
382 transfer_list);
383
384 if (!last_transfer->cs_change)
385 drv_data->cs_control(PXA2XX_CS_DEASSERT);
386
387 msg->state = NULL;
388 if (msg->complete)
389 msg->complete(msg->context);
390}
391
392static int wait_ssp_rx_stall(void *ioaddr)
393{
394 unsigned long limit = loops_per_jiffy << 1;
395
396 while ((read_SSSR(ioaddr) & SSSR_BSY) && limit--)
397 cpu_relax();
398
399 return limit;
400}
401
402static int wait_dma_channel_stop(int channel)
403{
404 unsigned long limit = loops_per_jiffy << 1;
405
406 while (!(DCSR(channel) & DCSR_STOPSTATE) && limit--)
407 cpu_relax();
408
409 return limit;
410}
411
412static void dma_handler(int channel, void *data, struct pt_regs *regs)
413{
414 struct driver_data *drv_data = data;
415 struct spi_message *msg = drv_data->cur_msg;
416 void *reg = drv_data->ioaddr;
417 u32 irq_status = DCSR(channel) & DMA_INT_MASK;
418 u32 trailing_sssr = 0;
419
420 if (irq_status & DCSR_BUSERR) {
421
422 /* Disable interrupts, clear status and reset DMA */
423 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
424 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
425 if (drv_data->ssp_type != PXA25x_SSP)
426 write_SSTO(0, reg);
427 write_SSSR(drv_data->clear_sr, reg);
428 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
429 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
430
431 if (flush(drv_data) == 0)
432 dev_err(&drv_data->pdev->dev,
433 "dma_handler: flush fail\n");
434
435 unmap_dma_buffers(drv_data);
436
437 if (channel == drv_data->tx_channel)
438 dev_err(&drv_data->pdev->dev,
439 "dma_handler: bad bus address on "
440 "tx channel %d, source %x target = %x\n",
441 channel, DSADR(channel), DTADR(channel));
442 else
443 dev_err(&drv_data->pdev->dev,
444 "dma_handler: bad bus address on "
445 "rx channel %d, source %x target = %x\n",
446 channel, DSADR(channel), DTADR(channel));
447
448 msg->state = ERROR_STATE;
449 tasklet_schedule(&drv_data->pump_transfers);
450 }
451
452 /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */
453 if ((drv_data->ssp_type == PXA25x_SSP)
454 && (channel == drv_data->tx_channel)
455 && (irq_status & DCSR_ENDINTR)) {
456
457 /* Wait for rx to stall */
458 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
459 dev_err(&drv_data->pdev->dev,
460 "dma_handler: ssp rx stall failed\n");
461
462 /* Clear and disable interrupts on SSP and DMA channels*/
463 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
464 write_SSSR(drv_data->clear_sr, reg);
465 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
466 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
467 if (wait_dma_channel_stop(drv_data->rx_channel) == 0)
468 dev_err(&drv_data->pdev->dev,
469 "dma_handler: dma rx channel stop failed\n");
470
471 unmap_dma_buffers(drv_data);
472
473 /* Read trailing bytes */
474 /* Calculate number of trailing bytes, read them */
475 trailing_sssr = read_SSSR(reg);
476 if ((trailing_sssr & 0xf008) != 0xf000) {
477 drv_data->rx = drv_data->rx_end -
478 (((trailing_sssr >> 12) & 0x0f) + 1);
479 drv_data->read(drv_data);
480 }
481 msg->actual_length += drv_data->len;
482
483 /* Release chip select if requested, transfer delays are
484 * handled in pump_transfers */
485 if (drv_data->cs_change)
486 drv_data->cs_control(PXA2XX_CS_DEASSERT);
487
488 /* Move to next transfer */
489 msg->state = next_transfer(drv_data);
490
491 /* Schedule transfer tasklet */
492 tasklet_schedule(&drv_data->pump_transfers);
493 }
494}
495
496static irqreturn_t dma_transfer(struct driver_data *drv_data)
497{
498 u32 irq_status;
499 u32 trailing_sssr = 0;
500 struct spi_message *msg = drv_data->cur_msg;
501 void *reg = drv_data->ioaddr;
502
503 irq_status = read_SSSR(reg) & drv_data->mask_sr;
504 if (irq_status & SSSR_ROR) {
505 /* Clear and disable interrupts on SSP and DMA channels*/
506 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
507 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
508 if (drv_data->ssp_type != PXA25x_SSP)
509 write_SSTO(0, reg);
510 write_SSSR(drv_data->clear_sr, reg);
511 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
512 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
513 unmap_dma_buffers(drv_data);
514
515 if (flush(drv_data) == 0)
516 dev_err(&drv_data->pdev->dev,
517 "dma_transfer: flush fail\n");
518
519 dev_warn(&drv_data->pdev->dev, "dma_transfer: fifo overun\n");
520
521 drv_data->cur_msg->state = ERROR_STATE;
522 tasklet_schedule(&drv_data->pump_transfers);
523
524 return IRQ_HANDLED;
525 }
526
527 /* Check for false positive timeout */
528 if ((irq_status & SSSR_TINT) && DCSR(drv_data->tx_channel) & DCSR_RUN) {
529 write_SSSR(SSSR_TINT, reg);
530 return IRQ_HANDLED;
531 }
532
533 if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) {
534
535 /* Clear and disable interrupts on SSP and DMA channels*/
536 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
537 if (drv_data->ssp_type != PXA25x_SSP)
538 write_SSTO(0, reg);
539 write_SSSR(drv_data->clear_sr, reg);
540 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
541 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
542
543 if (wait_dma_channel_stop(drv_data->rx_channel) == 0)
544 dev_err(&drv_data->pdev->dev,
545 "dma_transfer: dma rx channel stop failed\n");
546
547 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
548 dev_err(&drv_data->pdev->dev,
549 "dma_transfer: ssp rx stall failed\n");
550
551 unmap_dma_buffers(drv_data);
552
553 /* Calculate number of trailing bytes, read them */
554 trailing_sssr = read_SSSR(reg);
555 if ((trailing_sssr & 0xf008) != 0xf000) {
556 drv_data->rx = drv_data->rx_end -
557 (((trailing_sssr >> 12) & 0x0f) + 1);
558 drv_data->read(drv_data);
559 }
560 msg->actual_length += drv_data->len;
561
562 /* Release chip select if requested, transfer delays are
563 * handled in pump_transfers */
564 if (drv_data->cs_change)
565 drv_data->cs_control(PXA2XX_CS_DEASSERT);
566
567 /* Move to next transfer */
568 msg->state = next_transfer(drv_data);
569
570 /* Schedule transfer tasklet */
571 tasklet_schedule(&drv_data->pump_transfers);
572
573 return IRQ_HANDLED;
574 }
575
576 /* Opps problem detected */
577 return IRQ_NONE;
578}
579
580static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
581{
582 struct spi_message *msg = drv_data->cur_msg;
583 void *reg = drv_data->ioaddr;
584 unsigned long limit = loops_per_jiffy << 1;
585 u32 irq_status;
586 u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
587 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
588
589 while ((irq_status = read_SSSR(reg) & irq_mask)) {
590
591 if (irq_status & SSSR_ROR) {
592
593 /* Clear and disable interrupts */
594 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
595 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
596 if (drv_data->ssp_type != PXA25x_SSP)
597 write_SSTO(0, reg);
598 write_SSSR(drv_data->clear_sr, reg);
599
600 if (flush(drv_data) == 0)
601 dev_err(&drv_data->pdev->dev,
602 "interrupt_transfer: flush fail\n");
603
604 /* Stop the SSP */
605
606 dev_warn(&drv_data->pdev->dev,
607 "interrupt_transfer: fifo overun\n");
608
609 msg->state = ERROR_STATE;
610 tasklet_schedule(&drv_data->pump_transfers);
611
612 return IRQ_HANDLED;
613 }
614
615 /* Look for false positive timeout */
616 if ((irq_status & SSSR_TINT)
617 && (drv_data->rx < drv_data->rx_end))
618 write_SSSR(SSSR_TINT, reg);
619
620 /* Pump data */
621 drv_data->read(drv_data);
622 drv_data->write(drv_data);
623
624 if (drv_data->tx == drv_data->tx_end) {
625 /* Disable tx interrupt */
626 write_SSCR1(read_SSCR1(reg) & ~SSCR1_TIE, reg);
627 irq_mask = drv_data->mask_sr & ~SSSR_TFS;
628
629 /* PXA25x_SSP has no timeout, read trailing bytes */
630 if (drv_data->ssp_type == PXA25x_SSP) {
631 while ((read_SSSR(reg) & SSSR_BSY) && limit--)
632 drv_data->read(drv_data);
633
634 if (limit == 0)
635 dev_err(&drv_data->pdev->dev,
636 "interrupt_transfer: "
637 "trailing byte read failed\n");
638 }
639 }
640
641 if ((irq_status & SSSR_TINT)
642 || (drv_data->rx == drv_data->rx_end)) {
643
644 /* Clear timeout */
645 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
646 if (drv_data->ssp_type != PXA25x_SSP)
647 write_SSTO(0, reg);
648 write_SSSR(drv_data->clear_sr, reg);
649
650 /* Update total byte transfered */
651 msg->actual_length += drv_data->len;
652
653 /* Release chip select if requested, transfer delays are
654 * handled in pump_transfers */
655 if (drv_data->cs_change)
656 drv_data->cs_control(PXA2XX_CS_DEASSERT);
657
658 /* Move to next transfer */
659 msg->state = next_transfer(drv_data);
660
661 /* Schedule transfer tasklet */
662 tasklet_schedule(&drv_data->pump_transfers);
663 }
664 }
665
666 /* We did something */
667 return IRQ_HANDLED;
668}
669
670static irqreturn_t ssp_int(int irq, void *dev_id, struct pt_regs *regs)
671{
672 struct driver_data *drv_data = (struct driver_data *)dev_id;
673 void *reg = drv_data->ioaddr;
674
675 if (!drv_data->cur_msg) {
676
677 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
678 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
679 if (drv_data->ssp_type != PXA25x_SSP)
680 write_SSTO(0, reg);
681 write_SSSR(drv_data->clear_sr, reg);
682
683 dev_err(&drv_data->pdev->dev, "bad message state "
684 "in interrupt handler");
685
686 /* Never fail */
687 return IRQ_HANDLED;
688 }
689
690 return drv_data->transfer_handler(drv_data);
691}
692
693static void pump_transfers(unsigned long data)
694{
695 struct driver_data *drv_data = (struct driver_data *)data;
696 struct spi_message *message = NULL;
697 struct spi_transfer *transfer = NULL;
698 struct spi_transfer *previous = NULL;
699 struct chip_data *chip = NULL;
700 void *reg = drv_data->ioaddr;
701 u32 clk_div = 0;
702 u8 bits = 0;
703 u32 speed = 0;
704 u32 cr0;
705
706 /* Get current state information */
707 message = drv_data->cur_msg;
708 transfer = drv_data->cur_transfer;
709 chip = drv_data->cur_chip;
710
711 /* Handle for abort */
712 if (message->state == ERROR_STATE) {
713 message->status = -EIO;
714 giveback(drv_data);
715 return;
716 }
717
718 /* Handle end of message */
719 if (message->state == DONE_STATE) {
720 message->status = 0;
721 giveback(drv_data);
722 return;
723 }
724
725 /* Delay if requested at end of transfer*/
726 if (message->state == RUNNING_STATE) {
727 previous = list_entry(transfer->transfer_list.prev,
728 struct spi_transfer,
729 transfer_list);
730 if (previous->delay_usecs)
731 udelay(previous->delay_usecs);
732 }
733
734 /* Setup the transfer state based on the type of transfer */
735 if (flush(drv_data) == 0) {
736 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
737 message->status = -EIO;
738 giveback(drv_data);
739 return;
740 }
741 drv_data->n_bytes = chip->n_bytes;
742 drv_data->dma_width = chip->dma_width;
743 drv_data->cs_control = chip->cs_control;
744 drv_data->tx = (void *)transfer->tx_buf;
745 drv_data->tx_end = drv_data->tx + transfer->len;
746 drv_data->rx = transfer->rx_buf;
747 drv_data->rx_end = drv_data->rx + transfer->len;
748 drv_data->rx_dma = transfer->rx_dma;
749 drv_data->tx_dma = transfer->tx_dma;
750 drv_data->len = transfer->len;
751 drv_data->write = drv_data->tx ? chip->write : null_writer;
752 drv_data->read = drv_data->rx ? chip->read : null_reader;
753 drv_data->cs_change = transfer->cs_change;
754
755 /* Change speed and bit per word on a per transfer */
756 if (transfer->speed_hz || transfer->bits_per_word) {
757
758 /* Disable clock */
759 write_SSCR0(chip->cr0 & ~SSCR0_SSE, reg);
760 cr0 = chip->cr0;
761 bits = chip->bits_per_word;
762 speed = chip->speed_hz;
763
764 if (transfer->speed_hz)
765 speed = transfer->speed_hz;
766
767 if (transfer->bits_per_word)
768 bits = transfer->bits_per_word;
769
770 if (reg == SSP1_VIRT)
771 clk_div = SSP1_SerClkDiv(speed);
772 else if (reg == SSP2_VIRT)
773 clk_div = SSP2_SerClkDiv(speed);
774 else if (reg == SSP3_VIRT)
775 clk_div = SSP3_SerClkDiv(speed);
776
777 if (bits <= 8) {
778 drv_data->n_bytes = 1;
779 drv_data->dma_width = DCMD_WIDTH1;
780 drv_data->read = drv_data->read != null_reader ?
781 u8_reader : null_reader;
782 drv_data->write = drv_data->write != null_writer ?
783 u8_writer : null_writer;
784 } else if (bits <= 16) {
785 drv_data->n_bytes = 2;
786 drv_data->dma_width = DCMD_WIDTH2;
787 drv_data->read = drv_data->read != null_reader ?
788 u16_reader : null_reader;
789 drv_data->write = drv_data->write != null_writer ?
790 u16_writer : null_writer;
791 } else if (bits <= 32) {
792 drv_data->n_bytes = 4;
793 drv_data->dma_width = DCMD_WIDTH4;
794 drv_data->read = drv_data->read != null_reader ?
795 u32_reader : null_reader;
796 drv_data->write = drv_data->write != null_writer ?
797 u32_writer : null_writer;
798 }
799
800 cr0 = clk_div
801 | SSCR0_Motorola
802 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
803 | SSCR0_SSE
804 | (bits > 16 ? SSCR0_EDSS : 0);
805
806 /* Start it back up */
807 write_SSCR0(cr0, reg);
808 }
809
810 message->state = RUNNING_STATE;
811
812 /* Try to map dma buffer and do a dma transfer if successful */
813 if ((drv_data->dma_mapped = map_dma_buffers(drv_data))) {
814
815 /* Ensure we have the correct interrupt handler */
816 drv_data->transfer_handler = dma_transfer;
817
818 /* Setup rx DMA Channel */
819 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
820 DSADR(drv_data->rx_channel) = drv_data->ssdr_physical;
821 DTADR(drv_data->rx_channel) = drv_data->rx_dma;
822 if (drv_data->rx == drv_data->null_dma_buf)
823 /* No target address increment */
824 DCMD(drv_data->rx_channel) = DCMD_FLOWSRC
825 | drv_data->dma_width
826 | chip->dma_burst_size
827 | drv_data->len;
828 else
829 DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR
830 | DCMD_FLOWSRC
831 | drv_data->dma_width
832 | chip->dma_burst_size
833 | drv_data->len;
834
835 /* Setup tx DMA Channel */
836 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
837 DSADR(drv_data->tx_channel) = drv_data->tx_dma;
838 DTADR(drv_data->tx_channel) = drv_data->ssdr_physical;
839 if (drv_data->tx == drv_data->null_dma_buf)
840 /* No source address increment */
841 DCMD(drv_data->tx_channel) = DCMD_FLOWTRG
842 | drv_data->dma_width
843 | chip->dma_burst_size
844 | drv_data->len;
845 else
846 DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR
847 | DCMD_FLOWTRG
848 | drv_data->dma_width
849 | chip->dma_burst_size
850 | drv_data->len;
851
852 /* Enable dma end irqs on SSP to detect end of transfer */
853 if (drv_data->ssp_type == PXA25x_SSP)
854 DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN;
855
856 /* Fix me, need to handle cs polarity */
857 drv_data->cs_control(PXA2XX_CS_ASSERT);
858
859 /* Go baby, go */
860 write_SSSR(drv_data->clear_sr, reg);
861 DCSR(drv_data->rx_channel) |= DCSR_RUN;
862 DCSR(drv_data->tx_channel) |= DCSR_RUN;
863 if (drv_data->ssp_type != PXA25x_SSP)
864 write_SSTO(chip->timeout, reg);
865 write_SSCR1(chip->cr1
866 | chip->dma_threshold
867 | drv_data->dma_cr1,
868 reg);
869 } else {
870 /* Ensure we have the correct interrupt handler */
871 drv_data->transfer_handler = interrupt_transfer;
872
873 /* Fix me, need to handle cs polarity */
874 drv_data->cs_control(PXA2XX_CS_ASSERT);
875
876 /* Go baby, go */
877 write_SSSR(drv_data->clear_sr, reg);
878 if (drv_data->ssp_type != PXA25x_SSP)
879 write_SSTO(chip->timeout, reg);
880 write_SSCR1(chip->cr1
881 | chip->threshold
882 | drv_data->int_cr1,
883 reg);
884 }
885}
886
887static void pump_messages(void *data)
888{
889 struct driver_data *drv_data = data;
890 unsigned long flags;
891
892 /* Lock queue and check for queue work */
893 spin_lock_irqsave(&drv_data->lock, flags);
894 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
895 drv_data->busy = 0;
896 spin_unlock_irqrestore(&drv_data->lock, flags);
897 return;
898 }
899
900 /* Make sure we are not already running a message */
901 if (drv_data->cur_msg) {
902 spin_unlock_irqrestore(&drv_data->lock, flags);
903 return;
904 }
905
906 /* Extract head of queue */
907 drv_data->cur_msg = list_entry(drv_data->queue.next,
908 struct spi_message, queue);
909 list_del_init(&drv_data->cur_msg->queue);
910
911 /* Initial message state*/
912 drv_data->cur_msg->state = START_STATE;
913 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
914 struct spi_transfer,
915 transfer_list);
916
917 /* Setup the SSP using the per chip configuration */
918 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
919 restore_state(drv_data);
920
921 /* Mark as busy and launch transfers */
922 tasklet_schedule(&drv_data->pump_transfers);
923
924 drv_data->busy = 1;
925 spin_unlock_irqrestore(&drv_data->lock, flags);
926}
927
928static int transfer(struct spi_device *spi, struct spi_message *msg)
929{
930 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
931 unsigned long flags;
932
933 spin_lock_irqsave(&drv_data->lock, flags);
934
935 if (drv_data->run == QUEUE_STOPPED) {
936 spin_unlock_irqrestore(&drv_data->lock, flags);
937 return -ESHUTDOWN;
938 }
939
940 msg->actual_length = 0;
941 msg->status = -EINPROGRESS;
942 msg->state = START_STATE;
943
944 list_add_tail(&msg->queue, &drv_data->queue);
945
946 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
947 queue_work(drv_data->workqueue, &drv_data->pump_messages);
948
949 spin_unlock_irqrestore(&drv_data->lock, flags);
950
951 return 0;
952}
953
954static int setup(struct spi_device *spi)
955{
956 struct pxa2xx_spi_chip *chip_info = NULL;
957 struct chip_data *chip;
958 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
959 unsigned int clk_div;
960
961 if (!spi->bits_per_word)
962 spi->bits_per_word = 8;
963
964 if (drv_data->ssp_type != PXA25x_SSP
965 && (spi->bits_per_word < 4 || spi->bits_per_word > 32))
966 return -EINVAL;
967 else if (spi->bits_per_word < 4 || spi->bits_per_word > 16)
968 return -EINVAL;
969
970 /* Only alloc (or use chip_info) on first setup */
971 chip = spi_get_ctldata(spi);
972 if (chip == NULL) {
973 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
974 if (!chip)
975 return -ENOMEM;
976
977 chip->cs_control = null_cs_control;
978 chip->enable_dma = 0;
979 chip->timeout = SSP_TIMEOUT(1000);
980 chip->threshold = SSCR1_RxTresh(1) | SSCR1_TxTresh(1);
981 chip->dma_burst_size = drv_data->master_info->enable_dma ?
982 DCMD_BURST8 : 0;
983
984 chip_info = spi->controller_data;
985 }
986
987 /* chip_info isn't always needed */
988 if (chip_info) {
989 if (chip_info->cs_control)
990 chip->cs_control = chip_info->cs_control;
991
992 chip->timeout = SSP_TIMEOUT(chip_info->timeout_microsecs);
993
994 chip->threshold = SSCR1_RxTresh(chip_info->rx_threshold)
995 | SSCR1_TxTresh(chip_info->tx_threshold);
996
997 chip->enable_dma = chip_info->dma_burst_size != 0
998 && drv_data->master_info->enable_dma;
999 chip->dma_threshold = 0;
1000
1001 if (chip->enable_dma) {
1002 if (chip_info->dma_burst_size <= 8) {
1003 chip->dma_threshold = SSCR1_RxTresh(8)
1004 | SSCR1_TxTresh(8);
1005 chip->dma_burst_size = DCMD_BURST8;
1006 } else if (chip_info->dma_burst_size <= 16) {
1007 chip->dma_threshold = SSCR1_RxTresh(16)
1008 | SSCR1_TxTresh(16);
1009 chip->dma_burst_size = DCMD_BURST16;
1010 } else {
1011 chip->dma_threshold = SSCR1_RxTresh(32)
1012 | SSCR1_TxTresh(32);
1013 chip->dma_burst_size = DCMD_BURST32;
1014 }
1015 }
1016
1017
1018 if (chip_info->enable_loopback)
1019 chip->cr1 = SSCR1_LBM;
1020 }
1021
1022 if (drv_data->ioaddr == SSP1_VIRT)
1023 clk_div = SSP1_SerClkDiv(spi->max_speed_hz);
1024 else if (drv_data->ioaddr == SSP2_VIRT)
1025 clk_div = SSP2_SerClkDiv(spi->max_speed_hz);
1026 else if (drv_data->ioaddr == SSP3_VIRT)
1027 clk_div = SSP3_SerClkDiv(spi->max_speed_hz);
1028 else
1029 return -ENODEV;
1030 chip->speed_hz = spi->max_speed_hz;
1031
1032 chip->cr0 = clk_div
1033 | SSCR0_Motorola
1034 | SSCR0_DataSize(spi->bits_per_word > 16 ?
1035 spi->bits_per_word - 16 : spi->bits_per_word)
1036 | SSCR0_SSE
1037 | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
1038 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) << 4)
1039 | (((spi->mode & SPI_CPOL) != 0) << 3);
1040
1041 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1042 if (drv_data->ssp_type != PXA25x_SSP)
1043 dev_dbg(&spi->dev, "%d bits/word, %d Hz, mode %d\n",
1044 spi->bits_per_word,
1045 (CLOCK_SPEED_HZ)
1046 / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
1047 spi->mode & 0x3);
1048 else
1049 dev_dbg(&spi->dev, "%d bits/word, %d Hz, mode %d\n",
1050 spi->bits_per_word,
1051 (CLOCK_SPEED_HZ/2)
1052 / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
1053 spi->mode & 0x3);
1054
1055 if (spi->bits_per_word <= 8) {
1056 chip->n_bytes = 1;
1057 chip->dma_width = DCMD_WIDTH1;
1058 chip->read = u8_reader;
1059 chip->write = u8_writer;
1060 } else if (spi->bits_per_word <= 16) {
1061 chip->n_bytes = 2;
1062 chip->dma_width = DCMD_WIDTH2;
1063 chip->read = u16_reader;
1064 chip->write = u16_writer;
1065 } else if (spi->bits_per_word <= 32) {
1066 chip->cr0 |= SSCR0_EDSS;
1067 chip->n_bytes = 4;
1068 chip->dma_width = DCMD_WIDTH4;
1069 chip->read = u32_reader;
1070 chip->write = u32_writer;
1071 } else {
1072 dev_err(&spi->dev, "invalid wordsize\n");
1073 kfree(chip);
1074 return -ENODEV;
1075 }
1076 chip->bits_per_word = spi->bits_per_word;
1077
1078 spi_set_ctldata(spi, chip);
1079
1080 return 0;
1081}
1082
1083static void cleanup(const struct spi_device *spi)
1084{
1085 struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
1086
1087 kfree(chip);
1088}
1089
1090static int init_queue(struct driver_data *drv_data)
1091{
1092 INIT_LIST_HEAD(&drv_data->queue);
1093 spin_lock_init(&drv_data->lock);
1094
1095 drv_data->run = QUEUE_STOPPED;
1096 drv_data->busy = 0;
1097
1098 tasklet_init(&drv_data->pump_transfers,
1099 pump_transfers, (unsigned long)drv_data);
1100
1101 INIT_WORK(&drv_data->pump_messages, pump_messages, drv_data);
1102 drv_data->workqueue = create_singlethread_workqueue(
1103 drv_data->master->cdev.dev->bus_id);
1104 if (drv_data->workqueue == NULL)
1105 return -EBUSY;
1106
1107 return 0;
1108}
1109
1110static int start_queue(struct driver_data *drv_data)
1111{
1112 unsigned long flags;
1113
1114 spin_lock_irqsave(&drv_data->lock, flags);
1115
1116 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1117 spin_unlock_irqrestore(&drv_data->lock, flags);
1118 return -EBUSY;
1119 }
1120
1121 drv_data->run = QUEUE_RUNNING;
1122 drv_data->cur_msg = NULL;
1123 drv_data->cur_transfer = NULL;
1124 drv_data->cur_chip = NULL;
1125 spin_unlock_irqrestore(&drv_data->lock, flags);
1126
1127 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1128
1129 return 0;
1130}
1131
1132static int stop_queue(struct driver_data *drv_data)
1133{
1134 unsigned long flags;
1135 unsigned limit = 500;
1136 int status = 0;
1137
1138 spin_lock_irqsave(&drv_data->lock, flags);
1139
1140 /* This is a bit lame, but is optimized for the common execution path.
1141 * A wait_queue on the drv_data->busy could be used, but then the common
1142 * execution path (pump_messages) would be required to call wake_up or
1143 * friends on every SPI message. Do this instead */
1144 drv_data->run = QUEUE_STOPPED;
1145 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1146 spin_unlock_irqrestore(&drv_data->lock, flags);
1147 msleep(10);
1148 spin_lock_irqsave(&drv_data->lock, flags);
1149 }
1150
1151 if (!list_empty(&drv_data->queue) || drv_data->busy)
1152 status = -EBUSY;
1153
1154 spin_unlock_irqrestore(&drv_data->lock, flags);
1155
1156 return status;
1157}
1158
1159static int destroy_queue(struct driver_data *drv_data)
1160{
1161 int status;
1162
1163 status = stop_queue(drv_data);
1164 if (status != 0)
1165 return status;
1166
1167 destroy_workqueue(drv_data->workqueue);
1168
1169 return 0;
1170}
1171
1172static int pxa2xx_spi_probe(struct platform_device *pdev)
1173{
1174 struct device *dev = &pdev->dev;
1175 struct pxa2xx_spi_master *platform_info;
1176 struct spi_master *master;
1177 struct driver_data *drv_data = 0;
1178 struct resource *memory_resource;
1179 int irq;
1180 int status = 0;
1181
1182 platform_info = dev->platform_data;
1183
1184 if (platform_info->ssp_type == SSP_UNDEFINED) {
1185 dev_err(&pdev->dev, "undefined SSP\n");
1186 return -ENODEV;
1187 }
1188
1189 /* Allocate master with space for drv_data and null dma buffer */
1190 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1191 if (!master) {
1192 dev_err(&pdev->dev, "can not alloc spi_master\n");
1193 return -ENOMEM;
1194 }
1195 drv_data = spi_master_get_devdata(master);
1196 drv_data->master = master;
1197 drv_data->master_info = platform_info;
1198 drv_data->pdev = pdev;
1199
1200 master->bus_num = pdev->id;
1201 master->num_chipselect = platform_info->num_chipselect;
1202 master->cleanup = cleanup;
1203 master->setup = setup;
1204 master->transfer = transfer;
1205
1206 drv_data->ssp_type = platform_info->ssp_type;
1207 drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data +
1208 sizeof(struct driver_data)), 8);
1209
1210 /* Setup register addresses */
1211 memory_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1212 if (!memory_resource) {
1213 dev_err(&pdev->dev, "memory resources not defined\n");
1214 status = -ENODEV;
1215 goto out_error_master_alloc;
1216 }
1217
1218 drv_data->ioaddr = (void *)io_p2v((unsigned long)(memory_resource->start));
1219 drv_data->ssdr_physical = memory_resource->start + 0x00000010;
1220 if (platform_info->ssp_type == PXA25x_SSP) {
1221 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1222 drv_data->dma_cr1 = 0;
1223 drv_data->clear_sr = SSSR_ROR;
1224 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1225 } else {
1226 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1227 drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE;
1228 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1229 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1230 }
1231
1232 /* Attach to IRQ */
1233 irq = platform_get_irq(pdev, 0);
1234 if (irq < 0) {
1235 dev_err(&pdev->dev, "irq resource not defined\n");
1236 status = -ENODEV;
1237 goto out_error_master_alloc;
1238 }
1239
1240 status = request_irq(irq, ssp_int, 0, dev->bus_id, drv_data);
1241 if (status < 0) {
1242 dev_err(&pdev->dev, "can not get IRQ\n");
1243 goto out_error_master_alloc;
1244 }
1245
1246 /* Setup DMA if requested */
1247 drv_data->tx_channel = -1;
1248 drv_data->rx_channel = -1;
1249 if (platform_info->enable_dma) {
1250
1251 /* Get two DMA channels (rx and tx) */
1252 drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx",
1253 DMA_PRIO_HIGH,
1254 dma_handler,
1255 drv_data);
1256 if (drv_data->rx_channel < 0) {
1257 dev_err(dev, "problem (%d) requesting rx channel\n",
1258 drv_data->rx_channel);
1259 status = -ENODEV;
1260 goto out_error_irq_alloc;
1261 }
1262 drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx",
1263 DMA_PRIO_MEDIUM,
1264 dma_handler,
1265 drv_data);
1266 if (drv_data->tx_channel < 0) {
1267 dev_err(dev, "problem (%d) requesting tx channel\n",
1268 drv_data->tx_channel);
1269 status = -ENODEV;
1270 goto out_error_dma_alloc;
1271 }
1272
1273 if (drv_data->ioaddr == SSP1_VIRT) {
1274 DRCMRRXSSDR = DRCMR_MAPVLD
1275 | drv_data->rx_channel;
1276 DRCMRTXSSDR = DRCMR_MAPVLD
1277 | drv_data->tx_channel;
1278 } else if (drv_data->ioaddr == SSP2_VIRT) {
1279 DRCMRRXSS2DR = DRCMR_MAPVLD
1280 | drv_data->rx_channel;
1281 DRCMRTXSS2DR = DRCMR_MAPVLD
1282 | drv_data->tx_channel;
1283 } else if (drv_data->ioaddr == SSP3_VIRT) {
1284 DRCMRRXSS3DR = DRCMR_MAPVLD
1285 | drv_data->rx_channel;
1286 DRCMRTXSS3DR = DRCMR_MAPVLD
1287 | drv_data->tx_channel;
1288 } else {
1289 dev_err(dev, "bad SSP type\n");
1290 goto out_error_dma_alloc;
1291 }
1292 }
1293
1294 /* Enable SOC clock */
1295 pxa_set_cken(platform_info->clock_enable, 1);
1296
1297 /* Load default SSP configuration */
1298 write_SSCR0(0, drv_data->ioaddr);
1299 write_SSCR1(SSCR1_RxTresh(4) | SSCR1_TxTresh(12), drv_data->ioaddr);
1300 write_SSCR0(SSCR0_SerClkDiv(2)
1301 | SSCR0_Motorola
1302 | SSCR0_DataSize(8),
1303 drv_data->ioaddr);
1304 if (drv_data->ssp_type != PXA25x_SSP)
1305 write_SSTO(0, drv_data->ioaddr);
1306 write_SSPSP(0, drv_data->ioaddr);
1307
1308 /* Initial and start queue */
1309 status = init_queue(drv_data);
1310 if (status != 0) {
1311 dev_err(&pdev->dev, "problem initializing queue\n");
1312 goto out_error_clock_enabled;
1313 }
1314 status = start_queue(drv_data);
1315 if (status != 0) {
1316 dev_err(&pdev->dev, "problem starting queue\n");
1317 goto out_error_clock_enabled;
1318 }
1319
1320 /* Register with the SPI framework */
1321 platform_set_drvdata(pdev, drv_data);
1322 status = spi_register_master(master);
1323 if (status != 0) {
1324 dev_err(&pdev->dev, "problem registering spi master\n");
1325 goto out_error_queue_alloc;
1326 }
1327
1328 return status;
1329
1330out_error_queue_alloc:
1331 destroy_queue(drv_data);
1332
1333out_error_clock_enabled:
1334 pxa_set_cken(platform_info->clock_enable, 0);
1335
1336out_error_dma_alloc:
1337 if (drv_data->tx_channel != -1)
1338 pxa_free_dma(drv_data->tx_channel);
1339 if (drv_data->rx_channel != -1)
1340 pxa_free_dma(drv_data->rx_channel);
1341
1342out_error_irq_alloc:
1343 free_irq(irq, drv_data);
1344
1345out_error_master_alloc:
1346 spi_master_put(master);
1347 return status;
1348}
1349
1350static int pxa2xx_spi_remove(struct platform_device *pdev)
1351{
1352 struct driver_data *drv_data = platform_get_drvdata(pdev);
1353 int irq;
1354 int status = 0;
1355
1356 if (!drv_data)
1357 return 0;
1358
1359 /* Remove the queue */
1360 status = destroy_queue(drv_data);
1361 if (status != 0)
1362 return status;
1363
1364 /* Disable the SSP at the peripheral and SOC level */
1365 write_SSCR0(0, drv_data->ioaddr);
1366 pxa_set_cken(drv_data->master_info->clock_enable, 0);
1367
1368 /* Release DMA */
1369 if (drv_data->master_info->enable_dma) {
1370 if (drv_data->ioaddr == SSP1_VIRT) {
1371 DRCMRRXSSDR = 0;
1372 DRCMRTXSSDR = 0;
1373 } else if (drv_data->ioaddr == SSP2_VIRT) {
1374 DRCMRRXSS2DR = 0;
1375 DRCMRTXSS2DR = 0;
1376 } else if (drv_data->ioaddr == SSP3_VIRT) {
1377 DRCMRRXSS3DR = 0;
1378 DRCMRTXSS3DR = 0;
1379 }
1380 pxa_free_dma(drv_data->tx_channel);
1381 pxa_free_dma(drv_data->rx_channel);
1382 }
1383
1384 /* Release IRQ */
1385 irq = platform_get_irq(pdev, 0);
1386 if (irq >= 0)
1387 free_irq(irq, drv_data);
1388
1389 /* Disconnect from the SPI framework */
1390 spi_unregister_master(drv_data->master);
1391
1392 /* Prevent double remove */
1393 platform_set_drvdata(pdev, NULL);
1394
1395 return 0;
1396}
1397
1398static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1399{
1400 int status = 0;
1401
1402 if ((status = pxa2xx_spi_remove(pdev)) != 0)
1403 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1404}
1405
1406#ifdef CONFIG_PM
1407static int suspend_devices(struct device *dev, void *pm_message)
1408{
1409 pm_message_t *state = pm_message;
1410
1411 if (dev->power.power_state.event != state->event) {
1412 dev_warn(dev, "pm state does not match request\n");
1413 return -1;
1414 }
1415
1416 return 0;
1417}
1418
1419static int pxa2xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1420{
1421 struct driver_data *drv_data = platform_get_drvdata(pdev);
1422 int status = 0;
1423
1424 /* Check all childern for current power state */
1425 if (device_for_each_child(&pdev->dev, &state, suspend_devices) != 0) {
1426 dev_warn(&pdev->dev, "suspend aborted\n");
1427 return -1;
1428 }
1429
1430 status = stop_queue(drv_data);
1431 if (status != 0)
1432 return status;
1433 write_SSCR0(0, drv_data->ioaddr);
1434 pxa_set_cken(drv_data->master_info->clock_enable, 0);
1435
1436 return 0;
1437}
1438
1439static int pxa2xx_spi_resume(struct platform_device *pdev)
1440{
1441 struct driver_data *drv_data = platform_get_drvdata(pdev);
1442 int status = 0;
1443
1444 /* Enable the SSP clock */
1445 pxa_set_cken(drv_data->master_info->clock_enable, 1);
1446
1447 /* Start the queue running */
1448 status = start_queue(drv_data);
1449 if (status != 0) {
1450 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1451 return status;
1452 }
1453
1454 return 0;
1455}
1456#else
1457#define pxa2xx_spi_suspend NULL
1458#define pxa2xx_spi_resume NULL
1459#endif /* CONFIG_PM */
1460
1461static struct platform_driver driver = {
1462 .driver = {
1463 .name = "pxa2xx-spi",
1464 .bus = &platform_bus_type,
1465 .owner = THIS_MODULE,
1466 },
1467 .probe = pxa2xx_spi_probe,
1468 .remove = __devexit_p(pxa2xx_spi_remove),
1469 .shutdown = pxa2xx_spi_shutdown,
1470 .suspend = pxa2xx_spi_suspend,
1471 .resume = pxa2xx_spi_resume,
1472};
1473
1474static int __init pxa2xx_spi_init(void)
1475{
1476 platform_driver_register(&driver);
1477
1478 return 0;
1479}
1480module_init(pxa2xx_spi_init);
1481
1482static void __exit pxa2xx_spi_exit(void)
1483{
1484 platform_driver_unregister(&driver);
1485}
1486module_exit(pxa2xx_spi_exit);
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 94f5e8ed83a..1cea4a6799f 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -338,18 +338,18 @@ static struct class spi_master_class = {
338 * spi_alloc_master - allocate SPI master controller 338 * spi_alloc_master - allocate SPI master controller
339 * @dev: the controller, possibly using the platform_bus 339 * @dev: the controller, possibly using the platform_bus
340 * @size: how much driver-private data to preallocate; the pointer to this 340 * @size: how much driver-private data to preallocate; the pointer to this
341 * memory is in the class_data field of the returned class_device, 341 * memory is in the class_data field of the returned class_device,
342 * accessible with spi_master_get_devdata(). 342 * accessible with spi_master_get_devdata().
343 * 343 *
344 * This call is used only by SPI master controller drivers, which are the 344 * This call is used only by SPI master controller drivers, which are the
345 * only ones directly touching chip registers. It's how they allocate 345 * only ones directly touching chip registers. It's how they allocate
346 * an spi_master structure, prior to calling spi_add_master(). 346 * an spi_master structure, prior to calling spi_register_master().
347 * 347 *
348 * This must be called from context that can sleep. It returns the SPI 348 * This must be called from context that can sleep. It returns the SPI
349 * master structure on success, else NULL. 349 * master structure on success, else NULL.
350 * 350 *
351 * The caller is responsible for assigning the bus number and initializing 351 * The caller is responsible for assigning the bus number and initializing
352 * the master's methods before calling spi_add_master(); and (after errors 352 * the master's methods before calling spi_register_master(); and (after errors
353 * adding the device) calling spi_master_put() to prevent a memory leak. 353 * adding the device) calling spi_master_put() to prevent a memory leak.
354 */ 354 */
355struct spi_master * __init_or_module 355struct spi_master * __init_or_module
@@ -395,7 +395,7 @@ EXPORT_SYMBOL_GPL(spi_alloc_master);
395int __init_or_module 395int __init_or_module
396spi_register_master(struct spi_master *master) 396spi_register_master(struct spi_master *master)
397{ 397{
398 static atomic_t dyn_bus_id = ATOMIC_INIT(0); 398 static atomic_t dyn_bus_id = ATOMIC_INIT((1<<16) - 1);
399 struct device *dev = master->cdev.dev; 399 struct device *dev = master->cdev.dev;
400 int status = -ENODEV; 400 int status = -ENODEV;
401 int dynamic = 0; 401 int dynamic = 0;
@@ -404,7 +404,7 @@ spi_register_master(struct spi_master *master)
404 return -ENODEV; 404 return -ENODEV;
405 405
406 /* convention: dynamically assigned bus IDs count down from the max */ 406 /* convention: dynamically assigned bus IDs count down from the max */
407 if (master->bus_num == 0) { 407 if (master->bus_num < 0) {
408 master->bus_num = atomic_dec_return(&dyn_bus_id); 408 master->bus_num = atomic_dec_return(&dyn_bus_id);
409 dynamic = 1; 409 dynamic = 1;
410 } 410 }
@@ -522,7 +522,8 @@ int spi_sync(struct spi_device *spi, struct spi_message *message)
522} 522}
523EXPORT_SYMBOL_GPL(spi_sync); 523EXPORT_SYMBOL_GPL(spi_sync);
524 524
525#define SPI_BUFSIZ (SMP_CACHE_BYTES) 525/* portable code must never pass more than 32 bytes */
526#define SPI_BUFSIZ max(32,SMP_CACHE_BYTES)
526 527
527static u8 *buf; 528static u8 *buf;
528 529
diff --git a/drivers/spi/spi_bitbang.c b/drivers/spi/spi_bitbang.c
index f037e559326..dd2f950b21a 100644
--- a/drivers/spi/spi_bitbang.c
+++ b/drivers/spi/spi_bitbang.c
@@ -138,6 +138,45 @@ static unsigned bitbang_txrx_32(
138 return t->len - count; 138 return t->len - count;
139} 139}
140 140
141int spi_bitbang_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
142{
143 struct spi_bitbang_cs *cs = spi->controller_state;
144 u8 bits_per_word;
145 u32 hz;
146
147 if (t) {
148 bits_per_word = t->bits_per_word;
149 hz = t->speed_hz;
150 } else {
151 bits_per_word = 0;
152 hz = 0;
153 }
154
155 /* spi_transfer level calls that work per-word */
156 if (!bits_per_word)
157 bits_per_word = spi->bits_per_word;
158 if (bits_per_word <= 8)
159 cs->txrx_bufs = bitbang_txrx_8;
160 else if (bits_per_word <= 16)
161 cs->txrx_bufs = bitbang_txrx_16;
162 else if (bits_per_word <= 32)
163 cs->txrx_bufs = bitbang_txrx_32;
164 else
165 return -EINVAL;
166
167 /* nsecs = (clock period)/2 */
168 if (!hz)
169 hz = spi->max_speed_hz;
170 if (hz) {
171 cs->nsecs = (1000000000/2) / hz;
172 if (cs->nsecs > (MAX_UDELAY_MS * 1000 * 1000))
173 return -EINVAL;
174 }
175
176 return 0;
177}
178EXPORT_SYMBOL_GPL(spi_bitbang_setup_transfer);
179
141/** 180/**
142 * spi_bitbang_setup - default setup for per-word I/O loops 181 * spi_bitbang_setup - default setup for per-word I/O loops
143 */ 182 */
@@ -145,8 +184,16 @@ int spi_bitbang_setup(struct spi_device *spi)
145{ 184{
146 struct spi_bitbang_cs *cs = spi->controller_state; 185 struct spi_bitbang_cs *cs = spi->controller_state;
147 struct spi_bitbang *bitbang; 186 struct spi_bitbang *bitbang;
187 int retval;
148 188
149 if (!spi->max_speed_hz) 189 bitbang = spi_master_get_devdata(spi->master);
190
191 /* REVISIT: some systems will want to support devices using lsb-first
192 * bit encodings on the wire. In pure software that would be trivial,
193 * just bitbang_txrx_le_cphaX() routines shifting the other way, and
194 * some hardware controllers also have this support.
195 */
196 if ((spi->mode & SPI_LSB_FIRST) != 0)
150 return -EINVAL; 197 return -EINVAL;
151 198
152 if (!cs) { 199 if (!cs) {
@@ -155,32 +202,20 @@ int spi_bitbang_setup(struct spi_device *spi)
155 return -ENOMEM; 202 return -ENOMEM;
156 spi->controller_state = cs; 203 spi->controller_state = cs;
157 } 204 }
158 bitbang = spi_master_get_devdata(spi->master);
159 205
160 if (!spi->bits_per_word) 206 if (!spi->bits_per_word)
161 spi->bits_per_word = 8; 207 spi->bits_per_word = 8;
162 208
163 /* spi_transfer level calls that work per-word */
164 if (spi->bits_per_word <= 8)
165 cs->txrx_bufs = bitbang_txrx_8;
166 else if (spi->bits_per_word <= 16)
167 cs->txrx_bufs = bitbang_txrx_16;
168 else if (spi->bits_per_word <= 32)
169 cs->txrx_bufs = bitbang_txrx_32;
170 else
171 return -EINVAL;
172
173 /* per-word shift register access, in hardware or bitbanging */ 209 /* per-word shift register access, in hardware or bitbanging */
174 cs->txrx_word = bitbang->txrx_word[spi->mode & (SPI_CPOL|SPI_CPHA)]; 210 cs->txrx_word = bitbang->txrx_word[spi->mode & (SPI_CPOL|SPI_CPHA)];
175 if (!cs->txrx_word) 211 if (!cs->txrx_word)
176 return -EINVAL; 212 return -EINVAL;
177 213
178 /* nsecs = (clock period)/2 */ 214 retval = spi_bitbang_setup_transfer(spi, NULL);
179 cs->nsecs = (1000000000/2) / (spi->max_speed_hz); 215 if (retval < 0)
180 if (cs->nsecs > MAX_UDELAY_MS * 1000) 216 return retval;
181 return -EINVAL;
182 217
183 dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec\n", 218 dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
184 __FUNCTION__, spi->mode & (SPI_CPOL | SPI_CPHA), 219 __FUNCTION__, spi->mode & (SPI_CPOL | SPI_CPHA),
185 spi->bits_per_word, 2 * cs->nsecs); 220 spi->bits_per_word, 2 * cs->nsecs);
186 221
@@ -246,6 +281,8 @@ static void bitbang_work(void *_bitbang)
246 unsigned tmp; 281 unsigned tmp;
247 unsigned cs_change; 282 unsigned cs_change;
248 int status; 283 int status;
284 int (*setup_transfer)(struct spi_device *,
285 struct spi_transfer *);
249 286
250 m = container_of(bitbang->queue.next, struct spi_message, 287 m = container_of(bitbang->queue.next, struct spi_message,
251 queue); 288 queue);
@@ -262,6 +299,7 @@ static void bitbang_work(void *_bitbang)
262 tmp = 0; 299 tmp = 0;
263 cs_change = 1; 300 cs_change = 1;
264 status = 0; 301 status = 0;
302 setup_transfer = NULL;
265 303
266 list_for_each_entry (t, &m->transfers, transfer_list) { 304 list_for_each_entry (t, &m->transfers, transfer_list) {
267 if (bitbang->shutdown) { 305 if (bitbang->shutdown) {
@@ -269,6 +307,20 @@ static void bitbang_work(void *_bitbang)
269 break; 307 break;
270 } 308 }
271 309
310 /* override or restore speed and wordsize */
311 if (t->speed_hz || t->bits_per_word) {
312 setup_transfer = bitbang->setup_transfer;
313 if (!setup_transfer) {
314 status = -ENOPROTOOPT;
315 break;
316 }
317 }
318 if (setup_transfer) {
319 status = setup_transfer(spi, t);
320 if (status < 0)
321 break;
322 }
323
272 /* set up default clock polarity, and activate chip; 324 /* set up default clock polarity, and activate chip;
273 * this implicitly updates clock and spi modes as 325 * this implicitly updates clock and spi modes as
274 * previously recorded for this device via setup(). 326 * previously recorded for this device via setup().
@@ -325,6 +377,10 @@ static void bitbang_work(void *_bitbang)
325 m->status = status; 377 m->status = status;
326 m->complete(m->context); 378 m->complete(m->context);
327 379
380 /* restore speed and wordsize */
381 if (setup_transfer)
382 setup_transfer(spi, NULL);
383
328 /* normally deactivate chipselect ... unless no error and 384 /* normally deactivate chipselect ... unless no error and
329 * cs_change has hinted that the next message will probably 385 * cs_change has hinted that the next message will probably
330 * be for this chip too. 386 * be for this chip too.
@@ -348,6 +404,7 @@ int spi_bitbang_transfer(struct spi_device *spi, struct spi_message *m)
348{ 404{
349 struct spi_bitbang *bitbang; 405 struct spi_bitbang *bitbang;
350 unsigned long flags; 406 unsigned long flags;
407 int status = 0;
351 408
352 m->actual_length = 0; 409 m->actual_length = 0;
353 m->status = -EINPROGRESS; 410 m->status = -EINPROGRESS;
@@ -357,11 +414,15 @@ int spi_bitbang_transfer(struct spi_device *spi, struct spi_message *m)
357 return -ESHUTDOWN; 414 return -ESHUTDOWN;
358 415
359 spin_lock_irqsave(&bitbang->lock, flags); 416 spin_lock_irqsave(&bitbang->lock, flags);
360 list_add_tail(&m->queue, &bitbang->queue); 417 if (!spi->max_speed_hz)
361 queue_work(bitbang->workqueue, &bitbang->work); 418 status = -ENETDOWN;
419 else {
420 list_add_tail(&m->queue, &bitbang->queue);
421 queue_work(bitbang->workqueue, &bitbang->work);
422 }
362 spin_unlock_irqrestore(&bitbang->lock, flags); 423 spin_unlock_irqrestore(&bitbang->lock, flags);
363 424
364 return 0; 425 return status;
365} 426}
366EXPORT_SYMBOL_GPL(spi_bitbang_transfer); 427EXPORT_SYMBOL_GPL(spi_bitbang_transfer);
367 428
@@ -406,6 +467,9 @@ int spi_bitbang_start(struct spi_bitbang *bitbang)
406 bitbang->use_dma = 0; 467 bitbang->use_dma = 0;
407 bitbang->txrx_bufs = spi_bitbang_bufs; 468 bitbang->txrx_bufs = spi_bitbang_bufs;
408 if (!bitbang->master->setup) { 469 if (!bitbang->master->setup) {
470 if (!bitbang->setup_transfer)
471 bitbang->setup_transfer =
472 spi_bitbang_setup_transfer;
409 bitbang->master->setup = spi_bitbang_setup; 473 bitbang->master->setup = spi_bitbang_setup;
410 bitbang->master->cleanup = spi_bitbang_cleanup; 474 bitbang->master->cleanup = spi_bitbang_cleanup;
411 } 475 }
diff --git a/drivers/spi/spi_butterfly.c b/drivers/spi/spi_butterfly.c
index ff9e5faa4dc..a006a1ee27a 100644
--- a/drivers/spi/spi_butterfly.c
+++ b/drivers/spi/spi_butterfly.c
@@ -321,6 +321,7 @@ static void butterfly_attach(struct parport *p)
321 * (firmware resets at45, acts as spi slave) or neither (we ignore 321 * (firmware resets at45, acts as spi slave) or neither (we ignore
322 * both, AVR uses AT45). Here we expect firmware for the first option. 322 * both, AVR uses AT45). Here we expect firmware for the first option.
323 */ 323 */
324
324 pp->info[0].max_speed_hz = 15 * 1000 * 1000; 325 pp->info[0].max_speed_hz = 15 * 1000 * 1000;
325 strcpy(pp->info[0].modalias, "mtd_dataflash"); 326 strcpy(pp->info[0].modalias, "mtd_dataflash");
326 pp->info[0].platform_data = &flash; 327 pp->info[0].platform_data = &flash;
diff --git a/drivers/spi/spi_mpc83xx.c b/drivers/spi/spi_mpc83xx.c
new file mode 100644
index 00000000000..5d92a7e5cb4
--- /dev/null
+++ b/drivers/spi/spi_mpc83xx.c
@@ -0,0 +1,483 @@
1/*
2 * MPC83xx SPI controller driver.
3 *
4 * Maintainer: Kumar Gala
5 *
6 * Copyright (C) 2006 Polycom, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/types.h>
16#include <linux/kernel.h>
17#include <linux/completion.h>
18#include <linux/interrupt.h>
19#include <linux/delay.h>
20#include <linux/irq.h>
21#include <linux/device.h>
22#include <linux/spi/spi.h>
23#include <linux/spi/spi_bitbang.h>
24#include <linux/platform_device.h>
25#include <linux/fsl_devices.h>
26
27#include <asm/irq.h>
28#include <asm/io.h>
29
30/* SPI Controller registers */
31struct mpc83xx_spi_reg {
32 u8 res1[0x20];
33 __be32 mode;
34 __be32 event;
35 __be32 mask;
36 __be32 command;
37 __be32 transmit;
38 __be32 receive;
39};
40
41/* SPI Controller mode register definitions */
42#define SPMODE_CI_INACTIVEHIGH (1 << 29)
43#define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
44#define SPMODE_DIV16 (1 << 27)
45#define SPMODE_REV (1 << 26)
46#define SPMODE_MS (1 << 25)
47#define SPMODE_ENABLE (1 << 24)
48#define SPMODE_LEN(x) ((x) << 20)
49#define SPMODE_PM(x) ((x) << 16)
50
51/*
52 * Default for SPI Mode:
53 * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
54 */
55#define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
56 SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
57
58/* SPIE register values */
59#define SPIE_NE 0x00000200 /* Not empty */
60#define SPIE_NF 0x00000100 /* Not full */
61
62/* SPIM register values */
63#define SPIM_NE 0x00000200 /* Not empty */
64#define SPIM_NF 0x00000100 /* Not full */
65
66/* SPI Controller driver's private data. */
67struct mpc83xx_spi {
68 /* bitbang has to be first */
69 struct spi_bitbang bitbang;
70 struct completion done;
71
72 struct mpc83xx_spi_reg __iomem *base;
73
74 /* rx & tx bufs from the spi_transfer */
75 const void *tx;
76 void *rx;
77
78 /* functions to deal with different sized buffers */
79 void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
80 u32(*get_tx) (struct mpc83xx_spi *);
81
82 unsigned int count;
83 u32 irq;
84
85 unsigned nsecs; /* (clock cycle time)/2 */
86
87 u32 sysclk;
88 void (*activate_cs) (u8 cs, u8 polarity);
89 void (*deactivate_cs) (u8 cs, u8 polarity);
90};
91
92static inline void mpc83xx_spi_write_reg(__be32 __iomem * reg, u32 val)
93{
94 out_be32(reg, val);
95}
96
97static inline u32 mpc83xx_spi_read_reg(__be32 __iomem * reg)
98{
99 return in_be32(reg);
100}
101
102#define MPC83XX_SPI_RX_BUF(type) \
103void mpc83xx_spi_rx_buf_##type(u32 data, struct mpc83xx_spi *mpc83xx_spi) \
104{ \
105 type * rx = mpc83xx_spi->rx; \
106 *rx++ = (type)data; \
107 mpc83xx_spi->rx = rx; \
108}
109
110#define MPC83XX_SPI_TX_BUF(type) \
111u32 mpc83xx_spi_tx_buf_##type(struct mpc83xx_spi *mpc83xx_spi) \
112{ \
113 u32 data; \
114 const type * tx = mpc83xx_spi->tx; \
115 data = *tx++; \
116 mpc83xx_spi->tx = tx; \
117 return data; \
118}
119
120MPC83XX_SPI_RX_BUF(u8)
121MPC83XX_SPI_RX_BUF(u16)
122MPC83XX_SPI_RX_BUF(u32)
123MPC83XX_SPI_TX_BUF(u8)
124MPC83XX_SPI_TX_BUF(u16)
125MPC83XX_SPI_TX_BUF(u32)
126
127static void mpc83xx_spi_chipselect(struct spi_device *spi, int value)
128{
129 struct mpc83xx_spi *mpc83xx_spi;
130 u8 pol = spi->mode & SPI_CS_HIGH ? 1 : 0;
131
132 mpc83xx_spi = spi_master_get_devdata(spi->master);
133
134 if (value == BITBANG_CS_INACTIVE) {
135 if (mpc83xx_spi->deactivate_cs)
136 mpc83xx_spi->deactivate_cs(spi->chip_select, pol);
137 }
138
139 if (value == BITBANG_CS_ACTIVE) {
140 u32 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
141 u32 len = spi->bits_per_word;
142 if (len == 32)
143 len = 0;
144 else
145 len = len - 1;
146
147 /* mask out bits we are going to set */
148 regval &= ~0x38ff0000;
149
150 if (spi->mode & SPI_CPHA)
151 regval |= SPMODE_CP_BEGIN_EDGECLK;
152 if (spi->mode & SPI_CPOL)
153 regval |= SPMODE_CI_INACTIVEHIGH;
154
155 regval |= SPMODE_LEN(len);
156
157 if ((mpc83xx_spi->sysclk / spi->max_speed_hz) >= 64) {
158 u8 pm = mpc83xx_spi->sysclk / (spi->max_speed_hz * 64);
159 regval |= SPMODE_PM(pm) | SPMODE_DIV16;
160 } else {
161 u8 pm = mpc83xx_spi->sysclk / (spi->max_speed_hz * 4);
162 regval |= SPMODE_PM(pm);
163 }
164
165 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
166 if (mpc83xx_spi->activate_cs)
167 mpc83xx_spi->activate_cs(spi->chip_select, pol);
168 }
169}
170
171static
172int mpc83xx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
173{
174 struct mpc83xx_spi *mpc83xx_spi;
175 u32 regval;
176 u8 bits_per_word;
177 u32 hz;
178
179 mpc83xx_spi = spi_master_get_devdata(spi->master);
180
181 if (t) {
182 bits_per_word = t->bits_per_word;
183 hz = t->speed_hz;
184 } else {
185 bits_per_word = 0;
186 hz = 0;
187 }
188
189 /* spi_transfer level calls that work per-word */
190 if (!bits_per_word)
191 bits_per_word = spi->bits_per_word;
192
193 /* Make sure its a bit width we support [4..16, 32] */
194 if ((bits_per_word < 4)
195 || ((bits_per_word > 16) && (bits_per_word != 32)))
196 return -EINVAL;
197
198 if (bits_per_word <= 8) {
199 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
200 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
201 } else if (bits_per_word <= 16) {
202 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u16;
203 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u16;
204 } else if (bits_per_word <= 32) {
205 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u32;
206 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u32;
207 } else
208 return -EINVAL;
209
210 /* nsecs = (clock period)/2 */
211 if (!hz)
212 hz = spi->max_speed_hz;
213 mpc83xx_spi->nsecs = (1000000000 / 2) / hz;
214 if (mpc83xx_spi->nsecs > MAX_UDELAY_MS * 1000)
215 return -EINVAL;
216
217 if (bits_per_word == 32)
218 bits_per_word = 0;
219 else
220 bits_per_word = bits_per_word - 1;
221
222 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
223
224 /* Mask out bits_per_wordgth */
225 regval &= 0xff0fffff;
226 regval |= SPMODE_LEN(bits_per_word);
227
228 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
229
230 return 0;
231}
232
233static int mpc83xx_spi_setup(struct spi_device *spi)
234{
235 struct spi_bitbang *bitbang;
236 struct mpc83xx_spi *mpc83xx_spi;
237 int retval;
238
239 if (!spi->max_speed_hz)
240 return -EINVAL;
241
242 bitbang = spi_master_get_devdata(spi->master);
243 mpc83xx_spi = spi_master_get_devdata(spi->master);
244
245 if (!spi->bits_per_word)
246 spi->bits_per_word = 8;
247
248 retval = mpc83xx_spi_setup_transfer(spi, NULL);
249 if (retval < 0)
250 return retval;
251
252 dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec\n",
253 __FUNCTION__, spi->mode & (SPI_CPOL | SPI_CPHA),
254 spi->bits_per_word, 2 * mpc83xx_spi->nsecs);
255
256 /* NOTE we _need_ to call chipselect() early, ideally with adapter
257 * setup, unless the hardware defaults cooperate to avoid confusion
258 * between normal (active low) and inverted chipselects.
259 */
260
261 /* deselect chip (low or high) */
262 spin_lock(&bitbang->lock);
263 if (!bitbang->busy) {
264 bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
265 ndelay(mpc83xx_spi->nsecs);
266 }
267 spin_unlock(&bitbang->lock);
268
269 return 0;
270}
271
272static int mpc83xx_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
273{
274 struct mpc83xx_spi *mpc83xx_spi;
275 u32 word;
276
277 mpc83xx_spi = spi_master_get_devdata(spi->master);
278
279 mpc83xx_spi->tx = t->tx_buf;
280 mpc83xx_spi->rx = t->rx_buf;
281 mpc83xx_spi->count = t->len;
282 INIT_COMPLETION(mpc83xx_spi->done);
283
284 /* enable rx ints */
285 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, SPIM_NE);
286
287 /* transmit word */
288 word = mpc83xx_spi->get_tx(mpc83xx_spi);
289 mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
290
291 wait_for_completion(&mpc83xx_spi->done);
292
293 /* disable rx ints */
294 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
295
296 return t->len - mpc83xx_spi->count;
297}
298
299irqreturn_t mpc83xx_spi_irq(s32 irq, void *context_data,
300 struct pt_regs * ptregs)
301{
302 struct mpc83xx_spi *mpc83xx_spi = context_data;
303 u32 event;
304 irqreturn_t ret = IRQ_NONE;
305
306 /* Get interrupt events(tx/rx) */
307 event = mpc83xx_spi_read_reg(&mpc83xx_spi->base->event);
308
309 /* We need handle RX first */
310 if (event & SPIE_NE) {
311 u32 rx_data = mpc83xx_spi_read_reg(&mpc83xx_spi->base->receive);
312
313 if (mpc83xx_spi->rx)
314 mpc83xx_spi->get_rx(rx_data, mpc83xx_spi);
315
316 ret = IRQ_HANDLED;
317 }
318
319 if ((event & SPIE_NF) == 0)
320 /* spin until TX is done */
321 while (((event =
322 mpc83xx_spi_read_reg(&mpc83xx_spi->base->event)) &
323 SPIE_NF) == 0)
324 cpu_relax();
325
326 mpc83xx_spi->count -= 1;
327 if (mpc83xx_spi->count) {
328 if (mpc83xx_spi->tx) {
329 u32 word = mpc83xx_spi->get_tx(mpc83xx_spi);
330 mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit,
331 word);
332 }
333 } else {
334 complete(&mpc83xx_spi->done);
335 }
336
337 /* Clear the events */
338 mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, event);
339
340 return ret;
341}
342
343static int __init mpc83xx_spi_probe(struct platform_device *dev)
344{
345 struct spi_master *master;
346 struct mpc83xx_spi *mpc83xx_spi;
347 struct fsl_spi_platform_data *pdata;
348 struct resource *r;
349 u32 regval;
350 int ret = 0;
351
352 /* Get resources(memory, IRQ) associated with the device */
353 master = spi_alloc_master(&dev->dev, sizeof(struct mpc83xx_spi));
354
355 if (master == NULL) {
356 ret = -ENOMEM;
357 goto err;
358 }
359
360 platform_set_drvdata(dev, master);
361 pdata = dev->dev.platform_data;
362
363 if (pdata == NULL) {
364 ret = -ENODEV;
365 goto free_master;
366 }
367
368 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
369 if (r == NULL) {
370 ret = -ENODEV;
371 goto free_master;
372 }
373
374 mpc83xx_spi = spi_master_get_devdata(master);
375 mpc83xx_spi->bitbang.master = spi_master_get(master);
376 mpc83xx_spi->bitbang.chipselect = mpc83xx_spi_chipselect;
377 mpc83xx_spi->bitbang.setup_transfer = mpc83xx_spi_setup_transfer;
378 mpc83xx_spi->bitbang.txrx_bufs = mpc83xx_spi_bufs;
379 mpc83xx_spi->sysclk = pdata->sysclk;
380 mpc83xx_spi->activate_cs = pdata->activate_cs;
381 mpc83xx_spi->deactivate_cs = pdata->deactivate_cs;
382 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
383 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
384
385 mpc83xx_spi->bitbang.master->setup = mpc83xx_spi_setup;
386 init_completion(&mpc83xx_spi->done);
387
388 mpc83xx_spi->base = ioremap(r->start, r->end - r->start + 1);
389 if (mpc83xx_spi->base == NULL) {
390 ret = -ENOMEM;
391 goto put_master;
392 }
393
394 mpc83xx_spi->irq = platform_get_irq(dev, 0);
395
396 if (mpc83xx_spi->irq < 0) {
397 ret = -ENXIO;
398 goto unmap_io;
399 }
400
401 /* Register for SPI Interrupt */
402 ret = request_irq(mpc83xx_spi->irq, mpc83xx_spi_irq,
403 0, "mpc83xx_spi", mpc83xx_spi);
404
405 if (ret != 0)
406 goto unmap_io;
407
408 master->bus_num = pdata->bus_num;
409 master->num_chipselect = pdata->max_chipselect;
410
411 /* SPI controller initializations */
412 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
413 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
414 mpc83xx_spi_write_reg(&mpc83xx_spi->base->command, 0);
415 mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, 0xffffffff);
416
417 /* Enable SPI interface */
418 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
419 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
420
421 ret = spi_bitbang_start(&mpc83xx_spi->bitbang);
422
423 if (ret != 0)
424 goto free_irq;
425
426 printk(KERN_INFO
427 "%s: MPC83xx SPI Controller driver at 0x%p (irq = %d)\n",
428 dev->dev.bus_id, mpc83xx_spi->base, mpc83xx_spi->irq);
429
430 return ret;
431
432free_irq:
433 free_irq(mpc83xx_spi->irq, mpc83xx_spi);
434unmap_io:
435 iounmap(mpc83xx_spi->base);
436put_master:
437 spi_master_put(master);
438free_master:
439 kfree(master);
440err:
441 return ret;
442}
443
444static int __devexit mpc83xx_spi_remove(struct platform_device *dev)
445{
446 struct mpc83xx_spi *mpc83xx_spi;
447 struct spi_master *master;
448
449 master = platform_get_drvdata(dev);
450 mpc83xx_spi = spi_master_get_devdata(master);
451
452 spi_bitbang_stop(&mpc83xx_spi->bitbang);
453 free_irq(mpc83xx_spi->irq, mpc83xx_spi);
454 iounmap(mpc83xx_spi->base);
455 spi_master_put(mpc83xx_spi->bitbang.master);
456
457 return 0;
458}
459
460static struct platform_driver mpc83xx_spi_driver = {
461 .probe = mpc83xx_spi_probe,
462 .remove = __devexit_p(mpc83xx_spi_remove),
463 .driver = {
464 .name = "mpc83xx_spi",
465 },
466};
467
468static int __init mpc83xx_spi_init(void)
469{
470 return platform_driver_register(&mpc83xx_spi_driver);
471}
472
473static void __exit mpc83xx_spi_exit(void)
474{
475 platform_driver_unregister(&mpc83xx_spi_driver);
476}
477
478module_init(mpc83xx_spi_init);
479module_exit(mpc83xx_spi_exit);
480
481MODULE_AUTHOR("Kumar Gala");
482MODULE_DESCRIPTION("Simple MPC83xx SPI Driver");
483MODULE_LICENSE("GPL");
diff --git a/drivers/spi/spi_s3c24xx.c b/drivers/spi/spi_s3c24xx.c
new file mode 100644
index 00000000000..9de4b5a04d7
--- /dev/null
+++ b/drivers/spi/spi_s3c24xx.c
@@ -0,0 +1,453 @@
1/* linux/drivers/spi/spi_s3c24xx.c
2 *
3 * Copyright (c) 2006 Ben Dooks
4 * Copyright (c) 2006 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11*/
12
13
14//#define DEBUG
15
16#include <linux/config.h>
17#include <linux/init.h>
18#include <linux/spinlock.h>
19#include <linux/workqueue.h>
20#include <linux/interrupt.h>
21#include <linux/delay.h>
22#include <linux/errno.h>
23#include <linux/err.h>
24#include <linux/clk.h>
25#include <linux/platform_device.h>
26
27#include <linux/spi/spi.h>
28#include <linux/spi/spi_bitbang.h>
29
30#include <asm/io.h>
31#include <asm/dma.h>
32#include <asm/hardware.h>
33
34#include <asm/arch/regs-gpio.h>
35#include <asm/arch/regs-spi.h>
36#include <asm/arch/spi.h>
37
38struct s3c24xx_spi {
39 /* bitbang has to be first */
40 struct spi_bitbang bitbang;
41 struct completion done;
42
43 void __iomem *regs;
44 int irq;
45 int len;
46 int count;
47
48 /* data buffers */
49 const unsigned char *tx;
50 unsigned char *rx;
51
52 struct clk *clk;
53 struct resource *ioarea;
54 struct spi_master *master;
55 struct spi_device *curdev;
56 struct device *dev;
57 struct s3c2410_spi_info *pdata;
58};
59
60#define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
61#define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
62
63static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
64{
65 return spi_master_get_devdata(sdev->master);
66}
67
68static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
69{
70 struct s3c24xx_spi *hw = to_hw(spi);
71 unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
72 unsigned int spcon;
73
74 switch (value) {
75 case BITBANG_CS_INACTIVE:
76 if (hw->pdata->set_cs)
77 hw->pdata->set_cs(hw->pdata, value, cspol);
78 else
79 s3c2410_gpio_setpin(hw->pdata->pin_cs, cspol ^ 1);
80 break;
81
82 case BITBANG_CS_ACTIVE:
83 spcon = readb(hw->regs + S3C2410_SPCON);
84
85 if (spi->mode & SPI_CPHA)
86 spcon |= S3C2410_SPCON_CPHA_FMTB;
87 else
88 spcon &= ~S3C2410_SPCON_CPHA_FMTB;
89
90 if (spi->mode & SPI_CPOL)
91 spcon |= S3C2410_SPCON_CPOL_HIGH;
92 else
93 spcon &= ~S3C2410_SPCON_CPOL_HIGH;
94
95 spcon |= S3C2410_SPCON_ENSCK;
96
97 /* write new configration */
98
99 writeb(spcon, hw->regs + S3C2410_SPCON);
100
101 if (hw->pdata->set_cs)
102 hw->pdata->set_cs(hw->pdata, value, cspol);
103 else
104 s3c2410_gpio_setpin(hw->pdata->pin_cs, cspol);
105
106 break;
107
108 }
109}
110
111static int s3c24xx_spi_setupxfer(struct spi_device *spi,
112 struct spi_transfer *t)
113{
114 struct s3c24xx_spi *hw = to_hw(spi);
115 unsigned int bpw;
116 unsigned int hz;
117 unsigned int div;
118
119 bpw = t ? t->bits_per_word : spi->bits_per_word;
120 hz = t ? t->speed_hz : spi->max_speed_hz;
121
122 if (bpw != 8) {
123 dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);
124 return -EINVAL;
125 }
126
127 div = clk_get_rate(hw->clk) / hz;
128
129 /* is clk = pclk / (2 * (pre+1)), or is it
130 * clk = (pclk * 2) / ( pre + 1) */
131
132 div = (div / 2) - 1;
133
134 if (div < 0)
135 div = 1;
136
137 if (div > 255)
138 div = 255;
139
140 dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", div, hz);
141 writeb(div, hw->regs + S3C2410_SPPRE);
142
143 spin_lock(&hw->bitbang.lock);
144 if (!hw->bitbang.busy) {
145 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
146 /* need to ndelay for 0.5 clocktick ? */
147 }
148 spin_unlock(&hw->bitbang.lock);
149
150 return 0;
151}
152
153static int s3c24xx_spi_setup(struct spi_device *spi)
154{
155 int ret;
156
157 if (!spi->bits_per_word)
158 spi->bits_per_word = 8;
159
160 if ((spi->mode & SPI_LSB_FIRST) != 0)
161 return -EINVAL;
162
163 ret = s3c24xx_spi_setupxfer(spi, NULL);
164 if (ret < 0) {
165 dev_err(&spi->dev, "setupxfer returned %d\n", ret);
166 return ret;
167 }
168
169 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n",
170 __FUNCTION__, spi->mode, spi->bits_per_word,
171 spi->max_speed_hz);
172
173 return 0;
174}
175
176static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
177{
178 return hw->tx ? hw->tx[count] : 0xff;
179}
180
181static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
182{
183 struct s3c24xx_spi *hw = to_hw(spi);
184
185 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
186 t->tx_buf, t->rx_buf, t->len);
187
188 hw->tx = t->tx_buf;
189 hw->rx = t->rx_buf;
190 hw->len = t->len;
191 hw->count = 0;
192
193 /* send the first byte */
194 writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
195 wait_for_completion(&hw->done);
196
197 return hw->count;
198}
199
200static irqreturn_t s3c24xx_spi_irq(int irq, void *dev, struct pt_regs *regs)
201{
202 struct s3c24xx_spi *hw = dev;
203 unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
204 unsigned int count = hw->count;
205
206 if (spsta & S3C2410_SPSTA_DCOL) {
207 dev_dbg(hw->dev, "data-collision\n");
208 complete(&hw->done);
209 goto irq_done;
210 }
211
212 if (!(spsta & S3C2410_SPSTA_READY)) {
213 dev_dbg(hw->dev, "spi not ready for tx?\n");
214 complete(&hw->done);
215 goto irq_done;
216 }
217
218 hw->count++;
219
220 if (hw->rx)
221 hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
222
223 count++;
224
225 if (count < hw->len)
226 writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
227 else
228 complete(&hw->done);
229
230 irq_done:
231 return IRQ_HANDLED;
232}
233
234static int s3c24xx_spi_probe(struct platform_device *pdev)
235{
236 struct s3c24xx_spi *hw;
237 struct spi_master *master;
238 struct spi_board_info *bi;
239 struct resource *res;
240 int err = 0;
241 int i;
242
243 master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
244 if (master == NULL) {
245 dev_err(&pdev->dev, "No memory for spi_master\n");
246 err = -ENOMEM;
247 goto err_nomem;
248 }
249
250 hw = spi_master_get_devdata(master);
251 memset(hw, 0, sizeof(struct s3c24xx_spi));
252
253 hw->master = spi_master_get(master);
254 hw->pdata = pdev->dev.platform_data;
255 hw->dev = &pdev->dev;
256
257 if (hw->pdata == NULL) {
258 dev_err(&pdev->dev, "No platform data supplied\n");
259 err = -ENOENT;
260 goto err_no_pdata;
261 }
262
263 platform_set_drvdata(pdev, hw);
264 init_completion(&hw->done);
265
266 /* setup the state for the bitbang driver */
267
268 hw->bitbang.master = hw->master;
269 hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
270 hw->bitbang.chipselect = s3c24xx_spi_chipsel;
271 hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
272 hw->bitbang.master->setup = s3c24xx_spi_setup;
273
274 dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
275
276 /* find and map our resources */
277
278 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
279 if (res == NULL) {
280 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
281 err = -ENOENT;
282 goto err_no_iores;
283 }
284
285 hw->ioarea = request_mem_region(res->start, (res->end - res->start)+1,
286 pdev->name);
287
288 if (hw->ioarea == NULL) {
289 dev_err(&pdev->dev, "Cannot reserve region\n");
290 err = -ENXIO;
291 goto err_no_iores;
292 }
293
294 hw->regs = ioremap(res->start, (res->end - res->start)+1);
295 if (hw->regs == NULL) {
296 dev_err(&pdev->dev, "Cannot map IO\n");
297 err = -ENXIO;
298 goto err_no_iomap;
299 }
300
301 hw->irq = platform_get_irq(pdev, 0);
302 if (hw->irq < 0) {
303 dev_err(&pdev->dev, "No IRQ specified\n");
304 err = -ENOENT;
305 goto err_no_irq;
306 }
307
308 err = request_irq(hw->irq, s3c24xx_spi_irq, 0, pdev->name, hw);
309 if (err) {
310 dev_err(&pdev->dev, "Cannot claim IRQ\n");
311 goto err_no_irq;
312 }
313
314 hw->clk = clk_get(&pdev->dev, "spi");
315 if (IS_ERR(hw->clk)) {
316 dev_err(&pdev->dev, "No clock for device\n");
317 err = PTR_ERR(hw->clk);
318 goto err_no_clk;
319 }
320
321 /* for the moment, permanently enable the clock */
322
323 clk_enable(hw->clk);
324
325 /* program defaults into the registers */
326
327 writeb(0xff, hw->regs + S3C2410_SPPRE);
328 writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
329 writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
330
331 /* setup any gpio we can */
332
333 if (!hw->pdata->set_cs) {
334 s3c2410_gpio_setpin(hw->pdata->pin_cs, 1);
335 s3c2410_gpio_cfgpin(hw->pdata->pin_cs, S3C2410_GPIO_OUTPUT);
336 }
337
338 /* register our spi controller */
339
340 err = spi_bitbang_start(&hw->bitbang);
341 if (err) {
342 dev_err(&pdev->dev, "Failed to register SPI master\n");
343 goto err_register;
344 }
345
346 dev_dbg(hw->dev, "shutdown=%d\n", hw->bitbang.shutdown);
347
348 /* register all the devices associated */
349
350 bi = &hw->pdata->board_info[0];
351 for (i = 0; i < hw->pdata->board_size; i++, bi++) {
352 dev_info(hw->dev, "registering %s\n", bi->modalias);
353
354 bi->controller_data = hw;
355 spi_new_device(master, bi);
356 }
357
358 return 0;
359
360 err_register:
361 clk_disable(hw->clk);
362 clk_put(hw->clk);
363
364 err_no_clk:
365 free_irq(hw->irq, hw);
366
367 err_no_irq:
368 iounmap(hw->regs);
369
370 err_no_iomap:
371 release_resource(hw->ioarea);
372 kfree(hw->ioarea);
373
374 err_no_iores:
375 err_no_pdata:
376 spi_master_put(hw->master);;
377
378 err_nomem:
379 return err;
380}
381
382static int s3c24xx_spi_remove(struct platform_device *dev)
383{
384 struct s3c24xx_spi *hw = platform_get_drvdata(dev);
385
386 platform_set_drvdata(dev, NULL);
387
388 spi_unregister_master(hw->master);
389
390 clk_disable(hw->clk);
391 clk_put(hw->clk);
392
393 free_irq(hw->irq, hw);
394 iounmap(hw->regs);
395
396 release_resource(hw->ioarea);
397 kfree(hw->ioarea);
398
399 spi_master_put(hw->master);
400 return 0;
401}
402
403
404#ifdef CONFIG_PM
405
406static int s3c24xx_spi_suspend(struct platform_device *pdev, pm_message_t msg)
407{
408 struct s3c24xx_spi *hw = platform_get_drvdata(dev);
409
410 clk_disable(hw->clk);
411 return 0;
412}
413
414static int s3c24xx_spi_resume(struct platform_device *pdev)
415{
416 struct s3c24xx_spi *hw = platform_get_drvdata(dev);
417
418 clk_enable(hw->clk);
419 return 0;
420}
421
422#else
423#define s3c24xx_spi_suspend NULL
424#define s3c24xx_spi_resume NULL
425#endif
426
427static struct platform_driver s3c24xx_spidrv = {
428 .probe = s3c24xx_spi_probe,
429 .remove = s3c24xx_spi_remove,
430 .suspend = s3c24xx_spi_suspend,
431 .resume = s3c24xx_spi_resume,
432 .driver = {
433 .name = "s3c2410-spi",
434 .owner = THIS_MODULE,
435 },
436};
437
438static int __init s3c24xx_spi_init(void)
439{
440 return platform_driver_register(&s3c24xx_spidrv);
441}
442
443static void __exit s3c24xx_spi_exit(void)
444{
445 platform_driver_unregister(&s3c24xx_spidrv);
446}
447
448module_init(s3c24xx_spi_init);
449module_exit(s3c24xx_spi_exit);
450
451MODULE_DESCRIPTION("S3C24XX SPI Driver");
452MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
453MODULE_LICENSE("GPL");
diff --git a/drivers/spi/spi_s3c24xx_gpio.c b/drivers/spi/spi_s3c24xx_gpio.c
new file mode 100644
index 00000000000..aacdceb8f44
--- /dev/null
+++ b/drivers/spi/spi_s3c24xx_gpio.c
@@ -0,0 +1,188 @@
1/* linux/drivers/spi/spi_s3c24xx_gpio.c
2 *
3 * Copyright (c) 2006 Ben Dooks
4 * Copyright (c) 2006 Simtec Electronics
5 *
6 * S3C24XX GPIO based SPI driver
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#include <linux/config.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/spinlock.h>
19#include <linux/platform_device.h>
20
21#include <linux/spi/spi.h>
22#include <linux/spi/spi_bitbang.h>
23
24#include <asm/arch/regs-gpio.h>
25#include <asm/arch/spi-gpio.h>
26#include <asm/arch/hardware.h>
27
28struct s3c2410_spigpio {
29 struct spi_bitbang bitbang;
30
31 struct s3c2410_spigpio_info *info;
32 struct platform_device *dev;
33};
34
35static inline struct s3c2410_spigpio *spidev_to_sg(struct spi_device *spi)
36{
37 return spi->controller_data;
38}
39
40static inline void setsck(struct spi_device *dev, int on)
41{
42 struct s3c2410_spigpio *sg = spidev_to_sg(dev);
43 s3c2410_gpio_setpin(sg->info->pin_clk, on ? 1 : 0);
44}
45
46static inline void setmosi(struct spi_device *dev, int on)
47{
48 struct s3c2410_spigpio *sg = spidev_to_sg(dev);
49 s3c2410_gpio_setpin(sg->info->pin_mosi, on ? 1 : 0);
50}
51
52static inline u32 getmiso(struct spi_device *dev)
53{
54 struct s3c2410_spigpio *sg = spidev_to_sg(dev);
55 return s3c2410_gpio_getpin(sg->info->pin_miso) ? 1 : 0;
56}
57
58#define spidelay(x) ndelay(x)
59
60#define EXPAND_BITBANG_TXRX
61#include <linux/spi/spi_bitbang.h>
62
63
64static u32 s3c2410_spigpio_txrx_mode0(struct spi_device *spi,
65 unsigned nsecs, u32 word, u8 bits)
66{
67 return bitbang_txrx_be_cpha0(spi, nsecs, 0, word, bits);
68}
69
70static u32 s3c2410_spigpio_txrx_mode1(struct spi_device *spi,
71 unsigned nsecs, u32 word, u8 bits)
72{
73 return bitbang_txrx_be_cpha1(spi, nsecs, 0, word, bits);
74}
75
76static void s3c2410_spigpio_chipselect(struct spi_device *dev, int value)
77{
78 struct s3c2410_spigpio *sg = spidev_to_sg(dev);
79
80 if (sg->info && sg->info->chip_select)
81 (sg->info->chip_select)(sg->info, value);
82}
83
84static int s3c2410_spigpio_probe(struct platform_device *dev)
85{
86 struct spi_master *master;
87 struct s3c2410_spigpio *sp;
88 int ret;
89 int i;
90
91 master = spi_alloc_master(&dev->dev, sizeof(struct s3c2410_spigpio));
92 if (master == NULL) {
93 dev_err(&dev->dev, "failed to allocate spi master\n");
94 ret = -ENOMEM;
95 goto err;
96 }
97
98 sp = spi_master_get_devdata(master);
99
100 platform_set_drvdata(dev, sp);
101
102 /* copy in the plkatform data */
103 sp->info = dev->dev.platform_data;
104
105 /* setup spi bitbang adaptor */
106 sp->bitbang.master = spi_master_get(master);
107 sp->bitbang.chipselect = s3c2410_spigpio_chipselect;
108
109 sp->bitbang.txrx_word[SPI_MODE_0] = s3c2410_spigpio_txrx_mode0;
110 sp->bitbang.txrx_word[SPI_MODE_1] = s3c2410_spigpio_txrx_mode1;
111
112 /* set state of spi pins */
113 s3c2410_gpio_setpin(sp->info->pin_clk, 0);
114 s3c2410_gpio_setpin(sp->info->pin_mosi, 0);
115
116 s3c2410_gpio_cfgpin(sp->info->pin_clk, S3C2410_GPIO_OUTPUT);
117 s3c2410_gpio_cfgpin(sp->info->pin_mosi, S3C2410_GPIO_OUTPUT);
118 s3c2410_gpio_cfgpin(sp->info->pin_miso, S3C2410_GPIO_INPUT);
119
120 ret = spi_bitbang_start(&sp->bitbang);
121 if (ret)
122 goto err_no_bitbang;
123
124 /* register the chips to go with the board */
125
126 for (i = 0; i < sp->info->board_size; i++) {
127 dev_info(&dev->dev, "registering %p: %s\n",
128 &sp->info->board_info[i],
129 sp->info->board_info[i].modalias);
130
131 sp->info->board_info[i].controller_data = sp;
132 spi_new_device(master, sp->info->board_info + i);
133 }
134
135 return 0;
136
137 err_no_bitbang:
138 spi_master_put(sp->bitbang.master);
139 err:
140 return ret;
141
142}
143
144static int s3c2410_spigpio_remove(struct platform_device *dev)
145{
146 struct s3c2410_spigpio *sp = platform_get_drvdata(dev);
147
148 spi_bitbang_stop(&sp->bitbang);
149 spi_master_put(sp->bitbang.master);
150
151 return 0;
152}
153
154/* all gpio should be held over suspend/resume, so we should
155 * not need to deal with this
156*/
157
158#define s3c2410_spigpio_suspend NULL
159#define s3c2410_spigpio_resume NULL
160
161
162static struct platform_driver s3c2410_spigpio_drv = {
163 .probe = s3c2410_spigpio_probe,
164 .remove = s3c2410_spigpio_remove,
165 .suspend = s3c2410_spigpio_suspend,
166 .resume = s3c2410_spigpio_resume,
167 .driver = {
168 .name = "s3c24xx-spi-gpio",
169 .owner = THIS_MODULE,
170 },
171};
172
173static int __init s3c2410_spigpio_init(void)
174{
175 return platform_driver_register(&s3c2410_spigpio_drv);
176}
177
178static void __exit s3c2410_spigpio_exit(void)
179{
180 platform_driver_unregister(&s3c2410_spigpio_drv);
181}
182
183module_init(s3c2410_spigpio_init);
184module_exit(s3c2410_spigpio_exit);
185
186MODULE_DESCRIPTION("S3C24XX SPI Driver");
187MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
188MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 19:49:06 -0500