aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/serial/sh-sci.h
diff options
context:
space:
mode:
authorMagnus Damm <damm@igel.co.jp>2007-07-24 22:42:56 -0400
committerPaul Mundt <lethal@linux-sh.org>2007-07-26 02:37:57 -0400
commitd89ddd1c847637d91625c8cb6b0d064e1717057c (patch)
tree7f2547f112e3cd70e06a190fc26ab701dbab71b9 /drivers/serial/sh-sci.h
parent32582fa46020cd8940006a8d42dec083d72d6d8b (diff)
sh: remove support for sh7300 and solution engine 7300
This patch removes old dead code: - kill off sh7300 cpu support - get rid of broken solution engine 7300 board support Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'drivers/serial/sh-sci.h')
-rw-r--r--drivers/serial/sh-sci.h30
1 files changed, 8 insertions, 22 deletions
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index b11127d0eda..cf75466ebf5 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -9,6 +9,7 @@
9 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 9 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
10 * Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003). 10 * Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003).
11 * Modified to support H8/300 Series Yoshinori Sato (Feb 2004). 11 * Modified to support H8/300 Series Yoshinori Sato (Feb 2004).
12 * Removed SH7300 support (Jul 2007).
12 */ 13 */
13#include <linux/serial_core.h> 14#include <linux/serial_core.h>
14#include <asm/io.h> 15#include <asm/io.h>
@@ -70,11 +71,6 @@
70# define SCIF_ORER 0x0001 /* overrun error bit */ 71# define SCIF_ORER 0x0001 /* overrun error bit */
71# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 72# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
72# define SCIF_ONLY 73# define SCIF_ONLY
73#elif defined(CONFIG_CPU_SUBTYPE_SH7300)
74# define SCPCR 0xA4050116 /* 16 bit SCIF */
75# define SCPDR 0xA4050136 /* 16 bit SCIF */
76# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
77# define SCIF_ONLY
78#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) 74#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
79# define SCSPTR0 0xA4400000 /* 16 bit SCIF */ 75# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
80# define SCI_NPORTS 2 76# define SCI_NPORTS 2
@@ -221,7 +217,7 @@
221#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 217#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
222#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 218#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
223 219
224#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) 220#if defined(CONFIG_CPU_SUBTYPE_SH7705)
225#define SCIF_ORER 0x0200 221#define SCIF_ORER 0x0200
226#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) 222#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
227#define SCIF_RFDC_MASK 0x007f 223#define SCIF_RFDC_MASK 0x007f
@@ -250,7 +246,7 @@
250# define SCxSR_ERRORS(port) SCIF_ERRORS 246# define SCxSR_ERRORS(port) SCIF_ERRORS
251# define SCxSR_RDxF(port) SCIF_RDF 247# define SCxSR_RDxF(port) SCIF_RDF
252# define SCxSR_TDxE(port) SCIF_TDFE 248# define SCxSR_TDxE(port) SCIF_TDFE
253#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) 249#if defined(CONFIG_CPU_SUBTYPE_SH7705)
254# define SCxSR_ORER(port) SCIF_ORER 250# define SCxSR_ORER(port) SCIF_ORER
255#else 251#else
256# define SCxSR_ORER(port) 0x0000 252# define SCxSR_ORER(port) 0x0000
@@ -258,13 +254,13 @@
258# define SCxSR_FER(port) SCIF_FER 254# define SCxSR_FER(port) SCIF_FER
259# define SCxSR_PER(port) SCIF_PER 255# define SCxSR_PER(port) SCIF_PER
260# define SCxSR_BRK(port) SCIF_BRK 256# define SCxSR_BRK(port) SCIF_BRK
261#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) 257#if defined(CONFIG_CPU_SUBTYPE_SH7705)
262# define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc) 258# define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc)
263# define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73) 259# define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73)
264# define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf) 260# define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf)
265# define SCxSR_BREAK_CLEAR(port) (sci_in(port,SCxSR)&0xffe3) 261# define SCxSR_BREAK_CLEAR(port) (sci_in(port,SCxSR)&0xffe3)
266#else 262#else
267/* SH7705 can also use this, clearing is same between 7705 and 7709 and 7300 */ 263/* SH7705 can also use this, clearing is same between 7705 and 7709 */
268# define SCxSR_RDxF_CLEAR(port) 0x00fc 264# define SCxSR_RDxF_CLEAR(port) 0x00fc
269# define SCxSR_ERROR_CLEAR(port) 0x0073 265# define SCxSR_ERROR_CLEAR(port) 0x0073
270# define SCxSR_TDxE_CLEAR(port) 0x00df 266# define SCxSR_TDxE_CLEAR(port) 0x00df
@@ -366,8 +362,7 @@
366 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size) 362 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
367#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ 363#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
368 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 364 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
369#elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \ 365#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
370 defined(CONFIG_CPU_SUBTYPE_SH7705)
371#define SCIF_FNS(name, scif_offset, scif_size) \ 366#define SCIF_FNS(name, scif_offset, scif_size) \
372 CPU_SCIF_FNS(name, scif_offset, scif_size) 367 CPU_SCIF_FNS(name, scif_offset, scif_size)
373#else 368#else
@@ -393,8 +388,7 @@
393 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 388 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
394#endif 389#endif
395 390
396#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \ 391#if defined(CONFIG_CPU_SUBTYPE_SH7705)
397 defined(CONFIG_CPU_SUBTYPE_SH7705)
398 392
399SCIF_FNS(SCSMR, 0x00, 16) 393SCIF_FNS(SCSMR, 0x00, 16)
400SCIF_FNS(SCBRR, 0x04, 8) 394SCIF_FNS(SCBRR, 0x04, 8)
@@ -547,13 +541,6 @@ static inline int sci_rxd_in(struct uart_port *port)
547 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ 541 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
548 return 1; 542 return 1;
549} 543}
550#elif defined(CONFIG_CPU_SUBTYPE_SH7300)
551static inline int sci_rxd_in(struct uart_port *port)
552{
553 if (port->mapbase == 0xa4430000)
554 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */
555 return 1;
556}
557#elif defined(CONFIG_CPU_SUBTYPE_SH7343) 544#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
558static inline int sci_rxd_in(struct uart_port *port) 545static inline int sci_rxd_in(struct uart_port *port)
559{ 546{
@@ -701,8 +688,7 @@ static inline int sci_rxd_in(struct uart_port *port)
701 * -- Mitch Davis - 15 Jul 2000 688 * -- Mitch Davis - 15 Jul 2000
702 */ 689 */
703 690
704#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \ 691#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
705 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
706 defined(CONFIG_CPU_SUBTYPE_SH7785) 692 defined(CONFIG_CPU_SUBTYPE_SH7785)
707#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) 693#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
708#elif defined(CONFIG_CPU_SUBTYPE_SH7705) 694#elif defined(CONFIG_CPU_SUBTYPE_SH7705)