diff options
author | Tejun Heo <htejun@gmail.com> | 2005-08-17 00:09:18 -0400 |
---|---|---|
committer | Jeff Garzik <jgarzik@pobox.com> | 2005-08-17 00:51:50 -0400 |
commit | 83bbecc905b3431c60fe282830e09aaaab97b26a (patch) | |
tree | d3f11fc4b8672ee57f5234bf6c8616de5f080ab5 /drivers/scsi/sata_sil24.c | |
parent | e382eb1dbdb2dec69806a72551bcb4a736142f6d (diff) |
[PATCH] sil24: add more comments for constants
08_sil24_add-comments-for-constants.patch
Add more comments to constants.
Signed-off-by: Edward Falk
sata_sil24.c | 16 ++++++++--------
1 files changed, 8 insertions(+), 8 deletions(-)
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Diffstat (limited to 'drivers/scsi/sata_sil24.c')
-rw-r--r-- | drivers/scsi/sata_sil24.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/scsi/sata_sil24.c b/drivers/scsi/sata_sil24.c index 7a3d50dcd93..cb91894471f 100644 --- a/drivers/scsi/sata_sil24.c +++ b/drivers/scsi/sata_sil24.c | |||
@@ -107,14 +107,14 @@ enum { | |||
107 | 107 | ||
108 | PORT_PM = 0x0f80, /* 8 bytes PM * 16 (128 bytes) */ | 108 | PORT_PM = 0x0f80, /* 8 bytes PM * 16 (128 bytes) */ |
109 | /* 32 bit regs */ | 109 | /* 32 bit regs */ |
110 | PORT_CTRL_STAT = 0x1000, /* write:ctrl, read:stat */ | 110 | PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */ |
111 | PORT_CTRL_CLR = 0x1004, | 111 | PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */ |
112 | PORT_IRQ_STAT = 0x1008, | 112 | PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */ |
113 | PORT_IRQ_ENABLE_SET = 0x1010, | 113 | PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */ |
114 | PORT_IRQ_ENABLE_CLR = 0x1014, | 114 | PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */ |
115 | PORT_ACTIVATE_UPPER_ADDR= 0x101c, | 115 | PORT_ACTIVATE_UPPER_ADDR= 0x101c, |
116 | PORT_EXEC_FIFO = 0x1020, | 116 | PORT_EXEC_FIFO = 0x1020, /* command execution fifo */ |
117 | PORT_CMD_ERR = 0x1024, | 117 | PORT_CMD_ERR = 0x1024, /* command error number */ |
118 | PORT_FIS_CFG = 0x1028, | 118 | PORT_FIS_CFG = 0x1028, |
119 | PORT_FIFO_THRES = 0x102c, | 119 | PORT_FIFO_THRES = 0x102c, |
120 | /* 16 bit regs */ | 120 | /* 16 bit regs */ |
@@ -187,7 +187,7 @@ enum { | |||
187 | PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */ | 187 | PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */ |
188 | PORT_CERR_XFR_MSGABRT = 34, /* PSD ecode 10 - master abort */ | 188 | PORT_CERR_XFR_MSGABRT = 34, /* PSD ecode 10 - master abort */ |
189 | PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */ | 189 | PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */ |
190 | PORT_CERR_SENDSERVICE = 36, /* FIS received whiel sending service */ | 190 | PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */ |
191 | 191 | ||
192 | /* | 192 | /* |
193 | * Other constants | 193 | * Other constants |