diff options
author | Joe Perches <joe@perches.com> | 2010-12-02 22:12:37 -0500 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2010-12-07 16:34:48 -0500 |
commit | 226afe68fdbd1aa3680158aca0a3631cbd019626 (patch) | |
tree | 89e31323c0798493b9d0b3ec32df33fc21d82bf6 /drivers/net/wireless | |
parent | 3800276a40751539a920ef8e0537ef2e19126799 (diff) |
ath: Convert ath_print to ath_dbg
Remove ath/debug.h and the includes of these files.
Coalesce long formats.
Correct a few misspellings and missing "\n"s from these logging messages.
Remove unnecessary trailing space before a newline.
Remove ARRAY_SIZE casts, use printf type %zu
Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless')
36 files changed, 1009 insertions, 1105 deletions
diff --git a/drivers/net/wireless/ath/ath5k/base.c b/drivers/net/wireless/ath/ath5k/base.c index 380ff2f5f1d..950fc379c3b 100644 --- a/drivers/net/wireless/ath/ath5k/base.c +++ b/drivers/net/wireless/ath/ath5k/base.c | |||
@@ -60,7 +60,6 @@ | |||
60 | #include "reg.h" | 60 | #include "reg.h" |
61 | #include "debug.h" | 61 | #include "debug.h" |
62 | #include "ani.h" | 62 | #include "ani.h" |
63 | #include "../debug.h" | ||
64 | 63 | ||
65 | static int modparam_nohwcrypt; | 64 | static int modparam_nohwcrypt; |
66 | module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO); | 65 | module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO); |
diff --git a/drivers/net/wireless/ath/ath5k/debug.c b/drivers/net/wireless/ath/ath5k/debug.c index 5341dd2860d..d2f84d76bb0 100644 --- a/drivers/net/wireless/ath/ath5k/debug.c +++ b/drivers/net/wireless/ath/ath5k/debug.c | |||
@@ -60,7 +60,6 @@ | |||
60 | 60 | ||
61 | #include "base.h" | 61 | #include "base.h" |
62 | #include "debug.h" | 62 | #include "debug.h" |
63 | #include "../debug.h" | ||
64 | 63 | ||
65 | static unsigned int ath5k_debug; | 64 | static unsigned int ath5k_debug; |
66 | module_param_named(debug, ath5k_debug, uint, 0); | 65 | module_param_named(debug, ath5k_debug, uint, 0); |
diff --git a/drivers/net/wireless/ath/ath9k/ani.c b/drivers/net/wireless/ath/ath9k/ani.c index 29a045da184..e2ffac3d4d8 100644 --- a/drivers/net/wireless/ath/ath9k/ani.c +++ b/drivers/net/wireless/ath/ath9k/ani.c | |||
@@ -135,8 +135,8 @@ static void ath9k_ani_restart(struct ath_hw *ah) | |||
135 | cck_base = AR_PHY_COUNTMAX - ah->config.cck_trig_high; | 135 | cck_base = AR_PHY_COUNTMAX - ah->config.cck_trig_high; |
136 | } | 136 | } |
137 | 137 | ||
138 | ath_print(common, ATH_DBG_ANI, | 138 | ath_dbg(common, ATH_DBG_ANI, |
139 | "Writing ofdmbase=%u cckbase=%u\n", ofdm_base, cck_base); | 139 | "Writing ofdmbase=%u cckbase=%u\n", ofdm_base, cck_base); |
140 | 140 | ||
141 | ENABLE_REGWRITE_BUFFER(ah); | 141 | ENABLE_REGWRITE_BUFFER(ah); |
142 | 142 | ||
@@ -267,11 +267,11 @@ static void ath9k_hw_set_ofdm_nil(struct ath_hw *ah, u8 immunityLevel) | |||
267 | 267 | ||
268 | aniState->noiseFloor = BEACON_RSSI(ah); | 268 | aniState->noiseFloor = BEACON_RSSI(ah); |
269 | 269 | ||
270 | ath_print(common, ATH_DBG_ANI, | 270 | ath_dbg(common, ATH_DBG_ANI, |
271 | "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n", | 271 | "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n", |
272 | aniState->ofdmNoiseImmunityLevel, | 272 | aniState->ofdmNoiseImmunityLevel, |
273 | immunityLevel, aniState->noiseFloor, | 273 | immunityLevel, aniState->noiseFloor, |
274 | aniState->rssiThrLow, aniState->rssiThrHigh); | 274 | aniState->rssiThrLow, aniState->rssiThrHigh); |
275 | 275 | ||
276 | aniState->ofdmNoiseImmunityLevel = immunityLevel; | 276 | aniState->ofdmNoiseImmunityLevel = immunityLevel; |
277 | 277 | ||
@@ -334,11 +334,11 @@ static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel) | |||
334 | const struct ani_cck_level_entry *entry_cck; | 334 | const struct ani_cck_level_entry *entry_cck; |
335 | 335 | ||
336 | aniState->noiseFloor = BEACON_RSSI(ah); | 336 | aniState->noiseFloor = BEACON_RSSI(ah); |
337 | ath_print(common, ATH_DBG_ANI, | 337 | ath_dbg(common, ATH_DBG_ANI, |
338 | "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n", | 338 | "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n", |
339 | aniState->cckNoiseImmunityLevel, immunityLevel, | 339 | aniState->cckNoiseImmunityLevel, immunityLevel, |
340 | aniState->noiseFloor, aniState->rssiThrLow, | 340 | aniState->noiseFloor, aniState->rssiThrLow, |
341 | aniState->rssiThrHigh); | 341 | aniState->rssiThrHigh); |
342 | 342 | ||
343 | if ((ah->opmode == NL80211_IFTYPE_STATION || | 343 | if ((ah->opmode == NL80211_IFTYPE_STATION || |
344 | ah->opmode == NL80211_IFTYPE_ADHOC) && | 344 | ah->opmode == NL80211_IFTYPE_ADHOC) && |
@@ -478,8 +478,8 @@ static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning) | |||
478 | 478 | ||
479 | if (ah->opmode != NL80211_IFTYPE_STATION | 479 | if (ah->opmode != NL80211_IFTYPE_STATION |
480 | && ah->opmode != NL80211_IFTYPE_ADHOC) { | 480 | && ah->opmode != NL80211_IFTYPE_ADHOC) { |
481 | ath_print(common, ATH_DBG_ANI, | 481 | ath_dbg(common, ATH_DBG_ANI, |
482 | "Reset ANI state opmode %u\n", ah->opmode); | 482 | "Reset ANI state opmode %u\n", ah->opmode); |
483 | ah->stats.ast_ani_reset++; | 483 | ah->stats.ast_ani_reset++; |
484 | 484 | ||
485 | if (ah->opmode == NL80211_IFTYPE_AP) { | 485 | if (ah->opmode == NL80211_IFTYPE_AP) { |
@@ -584,16 +584,14 @@ void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning) | |||
584 | ATH9K_ANI_OFDM_DEF_LEVEL || | 584 | ATH9K_ANI_OFDM_DEF_LEVEL || |
585 | aniState->cckNoiseImmunityLevel != | 585 | aniState->cckNoiseImmunityLevel != |
586 | ATH9K_ANI_CCK_DEF_LEVEL) { | 586 | ATH9K_ANI_CCK_DEF_LEVEL) { |
587 | ath_print(common, ATH_DBG_ANI, | 587 | ath_dbg(common, ATH_DBG_ANI, |
588 | "Restore defaults: opmode %u " | 588 | "Restore defaults: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n", |
589 | "chan %d Mhz/0x%x is_scanning=%d " | 589 | ah->opmode, |
590 | "ofdm:%d cck:%d\n", | 590 | chan->channel, |
591 | ah->opmode, | 591 | chan->channelFlags, |
592 | chan->channel, | 592 | is_scanning, |
593 | chan->channelFlags, | 593 | aniState->ofdmNoiseImmunityLevel, |
594 | is_scanning, | 594 | aniState->cckNoiseImmunityLevel); |
595 | aniState->ofdmNoiseImmunityLevel, | ||
596 | aniState->cckNoiseImmunityLevel); | ||
597 | 595 | ||
598 | ath9k_hw_set_ofdm_nil(ah, ATH9K_ANI_OFDM_DEF_LEVEL); | 596 | ath9k_hw_set_ofdm_nil(ah, ATH9K_ANI_OFDM_DEF_LEVEL); |
599 | ath9k_hw_set_cck_nil(ah, ATH9K_ANI_CCK_DEF_LEVEL); | 597 | ath9k_hw_set_cck_nil(ah, ATH9K_ANI_CCK_DEF_LEVEL); |
@@ -602,16 +600,14 @@ void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning) | |||
602 | /* | 600 | /* |
603 | * restore historical levels for this channel | 601 | * restore historical levels for this channel |
604 | */ | 602 | */ |
605 | ath_print(common, ATH_DBG_ANI, | 603 | ath_dbg(common, ATH_DBG_ANI, |
606 | "Restore history: opmode %u " | 604 | "Restore history: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n", |
607 | "chan %d Mhz/0x%x is_scanning=%d " | 605 | ah->opmode, |
608 | "ofdm:%d cck:%d\n", | 606 | chan->channel, |
609 | ah->opmode, | 607 | chan->channelFlags, |
610 | chan->channel, | 608 | is_scanning, |
611 | chan->channelFlags, | 609 | aniState->ofdmNoiseImmunityLevel, |
612 | is_scanning, | 610 | aniState->cckNoiseImmunityLevel); |
613 | aniState->ofdmNoiseImmunityLevel, | ||
614 | aniState->cckNoiseImmunityLevel); | ||
615 | 611 | ||
616 | ath9k_hw_set_ofdm_nil(ah, | 612 | ath9k_hw_set_ofdm_nil(ah, |
617 | aniState->ofdmNoiseImmunityLevel); | 613 | aniState->ofdmNoiseImmunityLevel); |
@@ -666,19 +662,17 @@ static bool ath9k_hw_ani_read_counters(struct ath_hw *ah) | |||
666 | 662 | ||
667 | if (!use_new_ani(ah) && (phyCnt1 < ofdm_base || phyCnt2 < cck_base)) { | 663 | if (!use_new_ani(ah) && (phyCnt1 < ofdm_base || phyCnt2 < cck_base)) { |
668 | if (phyCnt1 < ofdm_base) { | 664 | if (phyCnt1 < ofdm_base) { |
669 | ath_print(common, ATH_DBG_ANI, | 665 | ath_dbg(common, ATH_DBG_ANI, |
670 | "phyCnt1 0x%x, resetting " | 666 | "phyCnt1 0x%x, resetting counter value to 0x%x\n", |
671 | "counter value to 0x%x\n", | 667 | phyCnt1, ofdm_base); |
672 | phyCnt1, ofdm_base); | ||
673 | REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base); | 668 | REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base); |
674 | REG_WRITE(ah, AR_PHY_ERR_MASK_1, | 669 | REG_WRITE(ah, AR_PHY_ERR_MASK_1, |
675 | AR_PHY_ERR_OFDM_TIMING); | 670 | AR_PHY_ERR_OFDM_TIMING); |
676 | } | 671 | } |
677 | if (phyCnt2 < cck_base) { | 672 | if (phyCnt2 < cck_base) { |
678 | ath_print(common, ATH_DBG_ANI, | 673 | ath_dbg(common, ATH_DBG_ANI, |
679 | "phyCnt2 0x%x, resetting " | 674 | "phyCnt2 0x%x, resetting counter value to 0x%x\n", |
680 | "counter value to 0x%x\n", | 675 | phyCnt2, cck_base); |
681 | phyCnt2, cck_base); | ||
682 | REG_WRITE(ah, AR_PHY_ERR_2, cck_base); | 676 | REG_WRITE(ah, AR_PHY_ERR_2, cck_base); |
683 | REG_WRITE(ah, AR_PHY_ERR_MASK_2, | 677 | REG_WRITE(ah, AR_PHY_ERR_MASK_2, |
684 | AR_PHY_ERR_CCK_TIMING); | 678 | AR_PHY_ERR_CCK_TIMING); |
@@ -719,13 +713,12 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan) | |||
719 | cckPhyErrRate = aniState->cckPhyErrCount * 1000 / | 713 | cckPhyErrRate = aniState->cckPhyErrCount * 1000 / |
720 | aniState->listenTime; | 714 | aniState->listenTime; |
721 | 715 | ||
722 | ath_print(common, ATH_DBG_ANI, | 716 | ath_dbg(common, ATH_DBG_ANI, |
723 | "listenTime=%d OFDM:%d errs=%d/s CCK:%d " | 717 | "listenTime=%d OFDM:%d errs=%d/s CCK:%d errs=%d/s ofdm_turn=%d\n", |
724 | "errs=%d/s ofdm_turn=%d\n", | 718 | aniState->listenTime, |
725 | aniState->listenTime, | 719 | aniState->ofdmNoiseImmunityLevel, |
726 | aniState->ofdmNoiseImmunityLevel, | 720 | ofdmPhyErrRate, aniState->cckNoiseImmunityLevel, |
727 | ofdmPhyErrRate, aniState->cckNoiseImmunityLevel, | 721 | cckPhyErrRate, aniState->ofdmsTurn); |
728 | cckPhyErrRate, aniState->ofdmsTurn); | ||
729 | 722 | ||
730 | if (aniState->listenTime > 5 * ah->aniperiod) { | 723 | if (aniState->listenTime > 5 * ah->aniperiod) { |
731 | if (ofdmPhyErrRate <= ah->config.ofdm_trig_low && | 724 | if (ofdmPhyErrRate <= ah->config.ofdm_trig_low && |
@@ -755,7 +748,7 @@ void ath9k_enable_mib_counters(struct ath_hw *ah) | |||
755 | { | 748 | { |
756 | struct ath_common *common = ath9k_hw_common(ah); | 749 | struct ath_common *common = ath9k_hw_common(ah); |
757 | 750 | ||
758 | ath_print(common, ATH_DBG_ANI, "Enable MIB counters\n"); | 751 | ath_dbg(common, ATH_DBG_ANI, "Enable MIB counters\n"); |
759 | 752 | ||
760 | ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); | 753 | ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); |
761 | 754 | ||
@@ -777,7 +770,7 @@ void ath9k_hw_disable_mib_counters(struct ath_hw *ah) | |||
777 | { | 770 | { |
778 | struct ath_common *common = ath9k_hw_common(ah); | 771 | struct ath_common *common = ath9k_hw_common(ah); |
779 | 772 | ||
780 | ath_print(common, ATH_DBG_ANI, "Disable MIB counters\n"); | 773 | ath_dbg(common, ATH_DBG_ANI, "Disable MIB counters\n"); |
781 | 774 | ||
782 | REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); | 775 | REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); |
783 | ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); | 776 | ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); |
@@ -852,7 +845,7 @@ void ath9k_hw_ani_init(struct ath_hw *ah) | |||
852 | struct ath_common *common = ath9k_hw_common(ah); | 845 | struct ath_common *common = ath9k_hw_common(ah); |
853 | int i; | 846 | int i; |
854 | 847 | ||
855 | ath_print(common, ATH_DBG_ANI, "Initialize ANI\n"); | 848 | ath_dbg(common, ATH_DBG_ANI, "Initialize ANI\n"); |
856 | 849 | ||
857 | if (use_new_ani(ah)) { | 850 | if (use_new_ani(ah)) { |
858 | ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_NEW; | 851 | ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_NEW; |
diff --git a/drivers/net/wireless/ath/ath9k/ar5008_phy.c b/drivers/net/wireless/ath/ath9k/ar5008_phy.c index 9af9f23af3c..059330aac64 100644 --- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c +++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c | |||
@@ -130,9 +130,8 @@ static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq) | |||
130 | /* pre-reverse this field */ | 130 | /* pre-reverse this field */ |
131 | tmp_reg = ath9k_hw_reverse_bits(new_bias, 3); | 131 | tmp_reg = ath9k_hw_reverse_bits(new_bias, 3); |
132 | 132 | ||
133 | ath_print(common, ATH_DBG_CONFIG, | 133 | ath_dbg(common, ATH_DBG_CONFIG, "Force rf_pwd_icsyndiv to %1d on %4d\n", |
134 | "Force rf_pwd_icsyndiv to %1d on %4d\n", | 134 | new_bias, synth_freq); |
135 | new_bias, synth_freq); | ||
136 | 135 | ||
137 | /* swizzle rf_pwd_icsyndiv */ | 136 | /* swizzle rf_pwd_icsyndiv */ |
138 | ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3); | 137 | ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3); |
@@ -1054,10 +1053,9 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah, | |||
1054 | u32 level = param; | 1053 | u32 level = param; |
1055 | 1054 | ||
1056 | if (level >= ARRAY_SIZE(ah->totalSizeDesired)) { | 1055 | if (level >= ARRAY_SIZE(ah->totalSizeDesired)) { |
1057 | ath_print(common, ATH_DBG_ANI, | 1056 | ath_dbg(common, ATH_DBG_ANI, |
1058 | "level out of range (%u > %u)\n", | 1057 | "level out of range (%u > %zu)\n", |
1059 | level, | 1058 | level, ARRAY_SIZE(ah->totalSizeDesired)); |
1060 | (unsigned)ARRAY_SIZE(ah->totalSizeDesired)); | ||
1061 | return false; | 1059 | return false; |
1062 | } | 1060 | } |
1063 | 1061 | ||
@@ -1159,10 +1157,9 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah, | |||
1159 | u32 level = param; | 1157 | u32 level = param; |
1160 | 1158 | ||
1161 | if (level >= ARRAY_SIZE(firstep)) { | 1159 | if (level >= ARRAY_SIZE(firstep)) { |
1162 | ath_print(common, ATH_DBG_ANI, | 1160 | ath_dbg(common, ATH_DBG_ANI, |
1163 | "level out of range (%u > %u)\n", | 1161 | "level out of range (%u > %zu)\n", |
1164 | level, | 1162 | level, ARRAY_SIZE(firstep)); |
1165 | (unsigned) ARRAY_SIZE(firstep)); | ||
1166 | return false; | 1163 | return false; |
1167 | } | 1164 | } |
1168 | REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, | 1165 | REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, |
@@ -1180,10 +1177,9 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah, | |||
1180 | u32 level = param; | 1177 | u32 level = param; |
1181 | 1178 | ||
1182 | if (level >= ARRAY_SIZE(cycpwrThr1)) { | 1179 | if (level >= ARRAY_SIZE(cycpwrThr1)) { |
1183 | ath_print(common, ATH_DBG_ANI, | 1180 | ath_dbg(common, ATH_DBG_ANI, |
1184 | "level out of range (%u > %u)\n", | 1181 | "level out of range (%u > %zu)\n", |
1185 | level, | 1182 | level, ARRAY_SIZE(cycpwrThr1)); |
1186 | (unsigned) ARRAY_SIZE(cycpwrThr1)); | ||
1187 | return false; | 1183 | return false; |
1188 | } | 1184 | } |
1189 | REG_RMW_FIELD(ah, AR_PHY_TIMING5, | 1185 | REG_RMW_FIELD(ah, AR_PHY_TIMING5, |
@@ -1199,25 +1195,22 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah, | |||
1199 | case ATH9K_ANI_PRESENT: | 1195 | case ATH9K_ANI_PRESENT: |
1200 | break; | 1196 | break; |
1201 | default: | 1197 | default: |
1202 | ath_print(common, ATH_DBG_ANI, | 1198 | ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd); |
1203 | "invalid cmd %u\n", cmd); | ||
1204 | return false; | 1199 | return false; |
1205 | } | 1200 | } |
1206 | 1201 | ||
1207 | ath_print(common, ATH_DBG_ANI, "ANI parameters:\n"); | 1202 | ath_dbg(common, ATH_DBG_ANI, "ANI parameters:\n"); |
1208 | ath_print(common, ATH_DBG_ANI, | 1203 | ath_dbg(common, ATH_DBG_ANI, |
1209 | "noiseImmunityLevel=%d, spurImmunityLevel=%d, " | 1204 | "noiseImmunityLevel=%d, spurImmunityLevel=%d, ofdmWeakSigDetectOff=%d\n", |
1210 | "ofdmWeakSigDetectOff=%d\n", | 1205 | aniState->noiseImmunityLevel, |
1211 | aniState->noiseImmunityLevel, | 1206 | aniState->spurImmunityLevel, |
1212 | aniState->spurImmunityLevel, | 1207 | !aniState->ofdmWeakSigDetectOff); |
1213 | !aniState->ofdmWeakSigDetectOff); | 1208 | ath_dbg(common, ATH_DBG_ANI, |
1214 | ath_print(common, ATH_DBG_ANI, | 1209 | "cckWeakSigThreshold=%d, firstepLevel=%d, listenTime=%d\n", |
1215 | "cckWeakSigThreshold=%d, " | 1210 | aniState->cckWeakSigThreshold, |
1216 | "firstepLevel=%d, listenTime=%d\n", | 1211 | aniState->firstepLevel, |
1217 | aniState->cckWeakSigThreshold, | 1212 | aniState->listenTime); |
1218 | aniState->firstepLevel, | 1213 | ath_dbg(common, ATH_DBG_ANI, |
1219 | aniState->listenTime); | ||
1220 | ath_print(common, ATH_DBG_ANI, | ||
1221 | "ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n", | 1214 | "ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n", |
1222 | aniState->ofdmPhyErrCount, | 1215 | aniState->ofdmPhyErrCount, |
1223 | aniState->cckPhyErrCount); | 1216 | aniState->cckPhyErrCount); |
@@ -1302,12 +1295,12 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah, | |||
1302 | AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); | 1295 | AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); |
1303 | 1296 | ||
1304 | if (!on != aniState->ofdmWeakSigDetectOff) { | 1297 | if (!on != aniState->ofdmWeakSigDetectOff) { |
1305 | ath_print(common, ATH_DBG_ANI, | 1298 | ath_dbg(common, ATH_DBG_ANI, |
1306 | "** ch %d: ofdm weak signal: %s=>%s\n", | 1299 | "** ch %d: ofdm weak signal: %s=>%s\n", |
1307 | chan->channel, | 1300 | chan->channel, |
1308 | !aniState->ofdmWeakSigDetectOff ? | 1301 | !aniState->ofdmWeakSigDetectOff ? |
1309 | "on" : "off", | 1302 | "on" : "off", |
1310 | on ? "on" : "off"); | 1303 | on ? "on" : "off"); |
1311 | if (on) | 1304 | if (on) |
1312 | ah->stats.ast_ani_ofdmon++; | 1305 | ah->stats.ast_ani_ofdmon++; |
1313 | else | 1306 | else |
@@ -1320,11 +1313,9 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah, | |||
1320 | u32 level = param; | 1313 | u32 level = param; |
1321 | 1314 | ||
1322 | if (level >= ARRAY_SIZE(firstep_table)) { | 1315 | if (level >= ARRAY_SIZE(firstep_table)) { |
1323 | ath_print(common, ATH_DBG_ANI, | 1316 | ath_dbg(common, ATH_DBG_ANI, |
1324 | "ATH9K_ANI_FIRSTEP_LEVEL: level " | 1317 | "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n", |
1325 | "out of range (%u > %u)\n", | 1318 | level, ARRAY_SIZE(firstep_table)); |
1326 | level, | ||
1327 | (unsigned) ARRAY_SIZE(firstep_table)); | ||
1328 | return false; | 1319 | return false; |
1329 | } | 1320 | } |
1330 | 1321 | ||
@@ -1359,24 +1350,22 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah, | |||
1359 | AR_PHY_FIND_SIG_FIRSTEP_LOW, value2); | 1350 | AR_PHY_FIND_SIG_FIRSTEP_LOW, value2); |
1360 | 1351 | ||
1361 | if (level != aniState->firstepLevel) { | 1352 | if (level != aniState->firstepLevel) { |
1362 | ath_print(common, ATH_DBG_ANI, | 1353 | ath_dbg(common, ATH_DBG_ANI, |
1363 | "** ch %d: level %d=>%d[def:%d] " | 1354 | "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n", |
1364 | "firstep[level]=%d ini=%d\n", | 1355 | chan->channel, |
1365 | chan->channel, | 1356 | aniState->firstepLevel, |
1366 | aniState->firstepLevel, | 1357 | level, |
1367 | level, | 1358 | ATH9K_ANI_FIRSTEP_LVL_NEW, |
1368 | ATH9K_ANI_FIRSTEP_LVL_NEW, | 1359 | value, |
1369 | value, | 1360 | aniState->iniDef.firstep); |
1370 | aniState->iniDef.firstep); | 1361 | ath_dbg(common, ATH_DBG_ANI, |
1371 | ath_print(common, ATH_DBG_ANI, | 1362 | "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n", |
1372 | "** ch %d: level %d=>%d[def:%d] " | 1363 | chan->channel, |
1373 | "firstep_low[level]=%d ini=%d\n", | 1364 | aniState->firstepLevel, |
1374 | chan->channel, | 1365 | level, |
1375 | aniState->firstepLevel, | 1366 | ATH9K_ANI_FIRSTEP_LVL_NEW, |
1376 | level, | 1367 | value2, |
1377 | ATH9K_ANI_FIRSTEP_LVL_NEW, | 1368 | aniState->iniDef.firstepLow); |
1378 | value2, | ||
1379 | aniState->iniDef.firstepLow); | ||
1380 | if (level > aniState->firstepLevel) | 1369 | if (level > aniState->firstepLevel) |
1381 | ah->stats.ast_ani_stepup++; | 1370 | ah->stats.ast_ani_stepup++; |
1382 | else if (level < aniState->firstepLevel) | 1371 | else if (level < aniState->firstepLevel) |
@@ -1389,11 +1378,9 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah, | |||
1389 | u32 level = param; | 1378 | u32 level = param; |
1390 | 1379 | ||
1391 | if (level >= ARRAY_SIZE(cycpwrThr1_table)) { | 1380 | if (level >= ARRAY_SIZE(cycpwrThr1_table)) { |
1392 | ath_print(common, ATH_DBG_ANI, | 1381 | ath_dbg(common, ATH_DBG_ANI, |
1393 | "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level " | 1382 | "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n", |
1394 | "out of range (%u > %u)\n", | 1383 | level, ARRAY_SIZE(cycpwrThr1_table)); |
1395 | level, | ||
1396 | (unsigned) ARRAY_SIZE(cycpwrThr1_table)); | ||
1397 | return false; | 1384 | return false; |
1398 | } | 1385 | } |
1399 | /* | 1386 | /* |
@@ -1427,24 +1414,22 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah, | |||
1427 | AR_PHY_EXT_TIMING5_CYCPWR_THR1, value2); | 1414 | AR_PHY_EXT_TIMING5_CYCPWR_THR1, value2); |
1428 | 1415 | ||
1429 | if (level != aniState->spurImmunityLevel) { | 1416 | if (level != aniState->spurImmunityLevel) { |
1430 | ath_print(common, ATH_DBG_ANI, | 1417 | ath_dbg(common, ATH_DBG_ANI, |
1431 | "** ch %d: level %d=>%d[def:%d] " | 1418 | "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n", |
1432 | "cycpwrThr1[level]=%d ini=%d\n", | 1419 | chan->channel, |
1433 | chan->channel, | 1420 | aniState->spurImmunityLevel, |
1434 | aniState->spurImmunityLevel, | 1421 | level, |
1435 | level, | 1422 | ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, |
1436 | ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, | 1423 | value, |
1437 | value, | 1424 | aniState->iniDef.cycpwrThr1); |
1438 | aniState->iniDef.cycpwrThr1); | 1425 | ath_dbg(common, ATH_DBG_ANI, |
1439 | ath_print(common, ATH_DBG_ANI, | 1426 | "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n", |
1440 | "** ch %d: level %d=>%d[def:%d] " | 1427 | chan->channel, |
1441 | "cycpwrThr1Ext[level]=%d ini=%d\n", | 1428 | aniState->spurImmunityLevel, |
1442 | chan->channel, | 1429 | level, |
1443 | aniState->spurImmunityLevel, | 1430 | ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, |
1444 | level, | 1431 | value2, |
1445 | ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, | 1432 | aniState->iniDef.cycpwrThr1Ext); |
1446 | value2, | ||
1447 | aniState->iniDef.cycpwrThr1Ext); | ||
1448 | if (level > aniState->spurImmunityLevel) | 1433 | if (level > aniState->spurImmunityLevel) |
1449 | ah->stats.ast_ani_spurup++; | 1434 | ah->stats.ast_ani_spurup++; |
1450 | else if (level < aniState->spurImmunityLevel) | 1435 | else if (level < aniState->spurImmunityLevel) |
@@ -1463,22 +1448,19 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah, | |||
1463 | case ATH9K_ANI_PRESENT: | 1448 | case ATH9K_ANI_PRESENT: |
1464 | break; | 1449 | break; |
1465 | default: | 1450 | default: |
1466 | ath_print(common, ATH_DBG_ANI, | 1451 | ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd); |
1467 | "invalid cmd %u\n", cmd); | ||
1468 | return false; | 1452 | return false; |
1469 | } | 1453 | } |
1470 | 1454 | ||
1471 | ath_print(common, ATH_DBG_ANI, | 1455 | ath_dbg(common, ATH_DBG_ANI, |
1472 | "ANI parameters: SI=%d, ofdmWS=%s FS=%d " | 1456 | "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n", |
1473 | "MRCcck=%s listenTime=%d " | 1457 | aniState->spurImmunityLevel, |
1474 | "ofdmErrs=%d cckErrs=%d\n", | 1458 | !aniState->ofdmWeakSigDetectOff ? "on" : "off", |
1475 | aniState->spurImmunityLevel, | 1459 | aniState->firstepLevel, |
1476 | !aniState->ofdmWeakSigDetectOff ? "on" : "off", | 1460 | !aniState->mrcCCKOff ? "on" : "off", |
1477 | aniState->firstepLevel, | 1461 | aniState->listenTime, |
1478 | !aniState->mrcCCKOff ? "on" : "off", | 1462 | aniState->ofdmPhyErrCount, |
1479 | aniState->listenTime, | 1463 | aniState->cckPhyErrCount); |
1480 | aniState->ofdmPhyErrCount, | ||
1481 | aniState->cckPhyErrCount); | ||
1482 | return true; | 1464 | return true; |
1483 | } | 1465 | } |
1484 | 1466 | ||
@@ -1524,13 +1506,12 @@ static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah) | |||
1524 | 1506 | ||
1525 | iniDef = &aniState->iniDef; | 1507 | iniDef = &aniState->iniDef; |
1526 | 1508 | ||
1527 | ath_print(common, ATH_DBG_ANI, | 1509 | ath_dbg(common, ATH_DBG_ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n", |
1528 | "ver %d.%d opmode %u chan %d Mhz/0x%x\n", | 1510 | ah->hw_version.macVersion, |
1529 | ah->hw_version.macVersion, | 1511 | ah->hw_version.macRev, |
1530 | ah->hw_version.macRev, | 1512 | ah->opmode, |
1531 | ah->opmode, | 1513 | chan->channel, |
1532 | chan->channel, | 1514 | chan->channelFlags); |
1533 | chan->channelFlags); | ||
1534 | 1515 | ||
1535 | val = REG_READ(ah, AR_PHY_SFCORR); | 1516 | val = REG_READ(ah, AR_PHY_SFCORR); |
1536 | iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); | 1517 | iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); |
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_calib.c b/drivers/net/wireless/ath/ath9k/ar9002_calib.c index 15f62cd0cc3..01880aa13e3 100644 --- a/drivers/net/wireless/ath/ath9k/ar9002_calib.c +++ b/drivers/net/wireless/ath/ath9k/ar9002_calib.c | |||
@@ -39,18 +39,18 @@ static void ar9002_hw_setup_calibration(struct ath_hw *ah, | |||
39 | switch (currCal->calData->calType) { | 39 | switch (currCal->calData->calType) { |
40 | case IQ_MISMATCH_CAL: | 40 | case IQ_MISMATCH_CAL: |
41 | REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); | 41 | REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); |
42 | ath_print(common, ATH_DBG_CALIBRATE, | 42 | ath_dbg(common, ATH_DBG_CALIBRATE, |
43 | "starting IQ Mismatch Calibration\n"); | 43 | "starting IQ Mismatch Calibration\n"); |
44 | break; | 44 | break; |
45 | case ADC_GAIN_CAL: | 45 | case ADC_GAIN_CAL: |
46 | REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN); | 46 | REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN); |
47 | ath_print(common, ATH_DBG_CALIBRATE, | 47 | ath_dbg(common, ATH_DBG_CALIBRATE, |
48 | "starting ADC Gain Calibration\n"); | 48 | "starting ADC Gain Calibration\n"); |
49 | break; | 49 | break; |
50 | case ADC_DC_CAL: | 50 | case ADC_DC_CAL: |
51 | REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER); | 51 | REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER); |
52 | ath_print(common, ATH_DBG_CALIBRATE, | 52 | ath_dbg(common, ATH_DBG_CALIBRATE, |
53 | "starting ADC DC Calibration\n"); | 53 | "starting ADC DC Calibration\n"); |
54 | break; | 54 | break; |
55 | } | 55 | } |
56 | 56 | ||
@@ -107,11 +107,11 @@ static void ar9002_hw_iqcal_collect(struct ath_hw *ah) | |||
107 | REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); | 107 | REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); |
108 | ah->totalIqCorrMeas[i] += | 108 | ah->totalIqCorrMeas[i] += |
109 | (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); | 109 | (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); |
110 | ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE, | 110 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE, |
111 | "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n", | 111 | "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n", |
112 | ah->cal_samples, i, ah->totalPowerMeasI[i], | 112 | ah->cal_samples, i, ah->totalPowerMeasI[i], |
113 | ah->totalPowerMeasQ[i], | 113 | ah->totalPowerMeasQ[i], |
114 | ah->totalIqCorrMeas[i]); | 114 | ah->totalIqCorrMeas[i]); |
115 | } | 115 | } |
116 | } | 116 | } |
117 | 117 | ||
@@ -129,14 +129,13 @@ static void ar9002_hw_adc_gaincal_collect(struct ath_hw *ah) | |||
129 | ah->totalAdcQEvenPhase[i] += | 129 | ah->totalAdcQEvenPhase[i] += |
130 | REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); | 130 | REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); |
131 | 131 | ||
132 | ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE, | 132 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE, |
133 | "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " | 133 | "%d: Chn %d oddi=0x%08x; eveni=0x%08x; oddq=0x%08x; evenq=0x%08x;\n", |
134 | "oddq=0x%08x; evenq=0x%08x;\n", | 134 | ah->cal_samples, i, |
135 | ah->cal_samples, i, | 135 | ah->totalAdcIOddPhase[i], |
136 | ah->totalAdcIOddPhase[i], | 136 | ah->totalAdcIEvenPhase[i], |
137 | ah->totalAdcIEvenPhase[i], | 137 | ah->totalAdcQOddPhase[i], |
138 | ah->totalAdcQOddPhase[i], | 138 | ah->totalAdcQEvenPhase[i]); |
139 | ah->totalAdcQEvenPhase[i]); | ||
140 | } | 139 | } |
141 | } | 140 | } |
142 | 141 | ||
@@ -154,14 +153,13 @@ static void ar9002_hw_adc_dccal_collect(struct ath_hw *ah) | |||
154 | ah->totalAdcDcOffsetQEvenPhase[i] += | 153 | ah->totalAdcDcOffsetQEvenPhase[i] += |
155 | (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); | 154 | (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); |
156 | 155 | ||
157 | ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE, | 156 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE, |
158 | "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " | 157 | "%d: Chn %d oddi=0x%08x; eveni=0x%08x; oddq=0x%08x; evenq=0x%08x;\n", |
159 | "oddq=0x%08x; evenq=0x%08x;\n", | 158 | ah->cal_samples, i, |
160 | ah->cal_samples, i, | 159 | ah->totalAdcDcOffsetIOddPhase[i], |
161 | ah->totalAdcDcOffsetIOddPhase[i], | 160 | ah->totalAdcDcOffsetIEvenPhase[i], |
162 | ah->totalAdcDcOffsetIEvenPhase[i], | 161 | ah->totalAdcDcOffsetQOddPhase[i], |
163 | ah->totalAdcDcOffsetQOddPhase[i], | 162 | ah->totalAdcDcOffsetQEvenPhase[i]); |
164 | ah->totalAdcDcOffsetQEvenPhase[i]); | ||
165 | } | 163 | } |
166 | } | 164 | } |
167 | 165 | ||
@@ -178,13 +176,13 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) | |||
178 | powerMeasQ = ah->totalPowerMeasQ[i]; | 176 | powerMeasQ = ah->totalPowerMeasQ[i]; |
179 | iqCorrMeas = ah->totalIqCorrMeas[i]; | 177 | iqCorrMeas = ah->totalIqCorrMeas[i]; |
180 | 178 | ||
181 | ath_print(common, ATH_DBG_CALIBRATE, | 179 | ath_dbg(common, ATH_DBG_CALIBRATE, |
182 | "Starting IQ Cal and Correction for Chain %d\n", | 180 | "Starting IQ Cal and Correction for Chain %d\n", |
183 | i); | 181 | i); |
184 | 182 | ||
185 | ath_print(common, ATH_DBG_CALIBRATE, | 183 | ath_dbg(common, ATH_DBG_CALIBRATE, |
186 | "Orignal: Chn %diq_corr_meas = 0x%08x\n", | 184 | "Orignal: Chn %diq_corr_meas = 0x%08x\n", |
187 | i, ah->totalIqCorrMeas[i]); | 185 | i, ah->totalIqCorrMeas[i]); |
188 | 186 | ||
189 | iqCorrNeg = 0; | 187 | iqCorrNeg = 0; |
190 | 188 | ||
@@ -193,12 +191,12 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) | |||
193 | iqCorrNeg = 1; | 191 | iqCorrNeg = 1; |
194 | } | 192 | } |
195 | 193 | ||
196 | ath_print(common, ATH_DBG_CALIBRATE, | 194 | ath_dbg(common, ATH_DBG_CALIBRATE, |
197 | "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI); | 195 | "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI); |
198 | ath_print(common, ATH_DBG_CALIBRATE, | 196 | ath_dbg(common, ATH_DBG_CALIBRATE, |
199 | "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ); | 197 | "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ); |
200 | ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n", | 198 | ath_dbg(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n", |
201 | iqCorrNeg); | 199 | iqCorrNeg); |
202 | 200 | ||
203 | iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128; | 201 | iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128; |
204 | qCoffDenom = powerMeasQ / 64; | 202 | qCoffDenom = powerMeasQ / 64; |
@@ -207,14 +205,14 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) | |||
207 | (qCoffDenom != 0)) { | 205 | (qCoffDenom != 0)) { |
208 | iCoff = iqCorrMeas / iCoffDenom; | 206 | iCoff = iqCorrMeas / iCoffDenom; |
209 | qCoff = powerMeasI / qCoffDenom - 64; | 207 | qCoff = powerMeasI / qCoffDenom - 64; |
210 | ath_print(common, ATH_DBG_CALIBRATE, | 208 | ath_dbg(common, ATH_DBG_CALIBRATE, |
211 | "Chn %d iCoff = 0x%08x\n", i, iCoff); | 209 | "Chn %d iCoff = 0x%08x\n", i, iCoff); |
212 | ath_print(common, ATH_DBG_CALIBRATE, | 210 | ath_dbg(common, ATH_DBG_CALIBRATE, |
213 | "Chn %d qCoff = 0x%08x\n", i, qCoff); | 211 | "Chn %d qCoff = 0x%08x\n", i, qCoff); |
214 | 212 | ||
215 | iCoff = iCoff & 0x3f; | 213 | iCoff = iCoff & 0x3f; |
216 | ath_print(common, ATH_DBG_CALIBRATE, | 214 | ath_dbg(common, ATH_DBG_CALIBRATE, |
217 | "New: Chn %d iCoff = 0x%08x\n", i, iCoff); | 215 | "New: Chn %d iCoff = 0x%08x\n", i, iCoff); |
218 | if (iqCorrNeg == 0x0) | 216 | if (iqCorrNeg == 0x0) |
219 | iCoff = 0x40 - iCoff; | 217 | iCoff = 0x40 - iCoff; |
220 | 218 | ||
@@ -223,9 +221,9 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) | |||
223 | else if (qCoff <= -16) | 221 | else if (qCoff <= -16) |
224 | qCoff = -16; | 222 | qCoff = -16; |
225 | 223 | ||
226 | ath_print(common, ATH_DBG_CALIBRATE, | 224 | ath_dbg(common, ATH_DBG_CALIBRATE, |
227 | "Chn %d : iCoff = 0x%x qCoff = 0x%x\n", | 225 | "Chn %d : iCoff = 0x%x qCoff = 0x%x\n", |
228 | i, iCoff, qCoff); | 226 | i, iCoff, qCoff); |
229 | 227 | ||
230 | REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), | 228 | REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), |
231 | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, | 229 | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, |
@@ -233,9 +231,9 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) | |||
233 | REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), | 231 | REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), |
234 | AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, | 232 | AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, |
235 | qCoff); | 233 | qCoff); |
236 | ath_print(common, ATH_DBG_CALIBRATE, | 234 | ath_dbg(common, ATH_DBG_CALIBRATE, |
237 | "IQ Cal and Correction done for Chain %d\n", | 235 | "IQ Cal and Correction done for Chain %d\n", |
238 | i); | 236 | i); |
239 | } | 237 | } |
240 | } | 238 | } |
241 | 239 | ||
@@ -255,21 +253,21 @@ static void ar9002_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains) | |||
255 | qOddMeasOffset = ah->totalAdcQOddPhase[i]; | 253 | qOddMeasOffset = ah->totalAdcQOddPhase[i]; |
256 | qEvenMeasOffset = ah->totalAdcQEvenPhase[i]; | 254 | qEvenMeasOffset = ah->totalAdcQEvenPhase[i]; |
257 | 255 | ||
258 | ath_print(common, ATH_DBG_CALIBRATE, | 256 | ath_dbg(common, ATH_DBG_CALIBRATE, |
259 | "Starting ADC Gain Cal for Chain %d\n", i); | 257 | "Starting ADC Gain Cal for Chain %d\n", i); |
260 | 258 | ||
261 | ath_print(common, ATH_DBG_CALIBRATE, | 259 | ath_dbg(common, ATH_DBG_CALIBRATE, |
262 | "Chn %d pwr_meas_odd_i = 0x%08x\n", i, | 260 | "Chn %d pwr_meas_odd_i = 0x%08x\n", i, |
263 | iOddMeasOffset); | 261 | iOddMeasOffset); |
264 | ath_print(common, ATH_DBG_CALIBRATE, | 262 | ath_dbg(common, ATH_DBG_CALIBRATE, |
265 | "Chn %d pwr_meas_even_i = 0x%08x\n", i, | 263 | "Chn %d pwr_meas_even_i = 0x%08x\n", i, |
266 | iEvenMeasOffset); | 264 | iEvenMeasOffset); |
267 | ath_print(common, ATH_DBG_CALIBRATE, | 265 | ath_dbg(common, ATH_DBG_CALIBRATE, |
268 | "Chn %d pwr_meas_odd_q = 0x%08x\n", i, | 266 | "Chn %d pwr_meas_odd_q = 0x%08x\n", i, |
269 | qOddMeasOffset); | 267 | qOddMeasOffset); |
270 | ath_print(common, ATH_DBG_CALIBRATE, | 268 | ath_dbg(common, ATH_DBG_CALIBRATE, |
271 | "Chn %d pwr_meas_even_q = 0x%08x\n", i, | 269 | "Chn %d pwr_meas_even_q = 0x%08x\n", i, |
272 | qEvenMeasOffset); | 270 | qEvenMeasOffset); |
273 | 271 | ||
274 | if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) { | 272 | if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) { |
275 | iGainMismatch = | 273 | iGainMismatch = |
@@ -279,20 +277,20 @@ static void ar9002_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains) | |||
279 | ((qOddMeasOffset * 32) / | 277 | ((qOddMeasOffset * 32) / |
280 | qEvenMeasOffset) & 0x3f; | 278 | qEvenMeasOffset) & 0x3f; |
281 | 279 | ||
282 | ath_print(common, ATH_DBG_CALIBRATE, | 280 | ath_dbg(common, ATH_DBG_CALIBRATE, |
283 | "Chn %d gain_mismatch_i = 0x%08x\n", i, | 281 | "Chn %d gain_mismatch_i = 0x%08x\n", i, |
284 | iGainMismatch); | 282 | iGainMismatch); |
285 | ath_print(common, ATH_DBG_CALIBRATE, | 283 | ath_dbg(common, ATH_DBG_CALIBRATE, |
286 | "Chn %d gain_mismatch_q = 0x%08x\n", i, | 284 | "Chn %d gain_mismatch_q = 0x%08x\n", i, |
287 | qGainMismatch); | 285 | qGainMismatch); |
288 | 286 | ||
289 | val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); | 287 | val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); |
290 | val &= 0xfffff000; | 288 | val &= 0xfffff000; |
291 | val |= (qGainMismatch) | (iGainMismatch << 6); | 289 | val |= (qGainMismatch) | (iGainMismatch << 6); |
292 | REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); | 290 | REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); |
293 | 291 | ||
294 | ath_print(common, ATH_DBG_CALIBRATE, | 292 | ath_dbg(common, ATH_DBG_CALIBRATE, |
295 | "ADC Gain Cal done for Chain %d\n", i); | 293 | "ADC Gain Cal done for Chain %d\n", i); |
296 | } | 294 | } |
297 | } | 295 | } |
298 | 296 | ||
@@ -317,41 +315,41 @@ static void ar9002_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains) | |||
317 | qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i]; | 315 | qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i]; |
318 | qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i]; | 316 | qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i]; |
319 | 317 | ||
320 | ath_print(common, ATH_DBG_CALIBRATE, | 318 | ath_dbg(common, ATH_DBG_CALIBRATE, |
321 | "Starting ADC DC Offset Cal for Chain %d\n", i); | 319 | "Starting ADC DC Offset Cal for Chain %d\n", i); |
322 | 320 | ||
323 | ath_print(common, ATH_DBG_CALIBRATE, | 321 | ath_dbg(common, ATH_DBG_CALIBRATE, |
324 | "Chn %d pwr_meas_odd_i = %d\n", i, | 322 | "Chn %d pwr_meas_odd_i = %d\n", i, |
325 | iOddMeasOffset); | 323 | iOddMeasOffset); |
326 | ath_print(common, ATH_DBG_CALIBRATE, | 324 | ath_dbg(common, ATH_DBG_CALIBRATE, |
327 | "Chn %d pwr_meas_even_i = %d\n", i, | 325 | "Chn %d pwr_meas_even_i = %d\n", i, |
328 | iEvenMeasOffset); | 326 | iEvenMeasOffset); |
329 | ath_print(common, ATH_DBG_CALIBRATE, | 327 | ath_dbg(common, ATH_DBG_CALIBRATE, |
330 | "Chn %d pwr_meas_odd_q = %d\n", i, | 328 | "Chn %d pwr_meas_odd_q = %d\n", i, |
331 | qOddMeasOffset); | 329 | qOddMeasOffset); |
332 | ath_print(common, ATH_DBG_CALIBRATE, | 330 | ath_dbg(common, ATH_DBG_CALIBRATE, |
333 | "Chn %d pwr_meas_even_q = %d\n", i, | 331 | "Chn %d pwr_meas_even_q = %d\n", i, |
334 | qEvenMeasOffset); | 332 | qEvenMeasOffset); |
335 | 333 | ||
336 | iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) / | 334 | iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) / |
337 | numSamples) & 0x1ff; | 335 | numSamples) & 0x1ff; |
338 | qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) / | 336 | qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) / |
339 | numSamples) & 0x1ff; | 337 | numSamples) & 0x1ff; |
340 | 338 | ||
341 | ath_print(common, ATH_DBG_CALIBRATE, | 339 | ath_dbg(common, ATH_DBG_CALIBRATE, |
342 | "Chn %d dc_offset_mismatch_i = 0x%08x\n", i, | 340 | "Chn %d dc_offset_mismatch_i = 0x%08x\n", i, |
343 | iDcMismatch); | 341 | iDcMismatch); |
344 | ath_print(common, ATH_DBG_CALIBRATE, | 342 | ath_dbg(common, ATH_DBG_CALIBRATE, |
345 | "Chn %d dc_offset_mismatch_q = 0x%08x\n", i, | 343 | "Chn %d dc_offset_mismatch_q = 0x%08x\n", i, |
346 | qDcMismatch); | 344 | qDcMismatch); |
347 | 345 | ||
348 | val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); | 346 | val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); |
349 | val &= 0xc0000fff; | 347 | val &= 0xc0000fff; |
350 | val |= (qDcMismatch << 12) | (iDcMismatch << 21); | 348 | val |= (qDcMismatch << 12) | (iDcMismatch << 21); |
351 | REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); | 349 | REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); |
352 | 350 | ||
353 | ath_print(common, ATH_DBG_CALIBRATE, | 351 | ath_dbg(common, ATH_DBG_CALIBRATE, |
354 | "ADC DC Offset Cal done for Chain %d\n", i); | 352 | "ADC DC Offset Cal done for Chain %d\n", i); |
355 | } | 353 | } |
356 | 354 | ||
357 | REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), | 355 | REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), |
@@ -540,7 +538,7 @@ static inline void ar9285_hw_pa_cal(struct ath_hw *ah, bool is_reset) | |||
540 | { 0x7838, 0 }, | 538 | { 0x7838, 0 }, |
541 | }; | 539 | }; |
542 | 540 | ||
543 | ath_print(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n"); | 541 | ath_dbg(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n"); |
544 | 542 | ||
545 | /* PA CAL is not needed for high power solution */ | 543 | /* PA CAL is not needed for high power solution */ |
546 | if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == | 544 | if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == |
@@ -721,9 +719,8 @@ static bool ar9285_hw_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan) | |||
721 | REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); | 719 | REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); |
722 | if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, | 720 | if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, |
723 | AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) { | 721 | AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) { |
724 | ath_print(common, ATH_DBG_CALIBRATE, "offset " | 722 | ath_dbg(common, ATH_DBG_CALIBRATE, |
725 | "calibration failed to complete in " | 723 | "offset calibration failed to complete in 1ms; noisy environment?\n"); |
726 | "1ms; noisy ??\n"); | ||
727 | return false; | 724 | return false; |
728 | } | 725 | } |
729 | REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); | 726 | REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); |
@@ -736,8 +733,8 @@ static bool ar9285_hw_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan) | |||
736 | REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); | 733 | REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); |
737 | if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, | 734 | if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, |
738 | 0, AH_WAIT_TIMEOUT)) { | 735 | 0, AH_WAIT_TIMEOUT)) { |
739 | ath_print(common, ATH_DBG_CALIBRATE, "offset calibration " | 736 | ath_dbg(common, ATH_DBG_CALIBRATE, |
740 | "failed to complete in 1ms; noisy ??\n"); | 737 | "offset calibration failed to complete in 1ms; noisy environment?\n"); |
741 | return false; | 738 | return false; |
742 | } | 739 | } |
743 | 740 | ||
@@ -829,9 +826,8 @@ static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan) | |||
829 | if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, | 826 | if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, |
830 | AR_PHY_AGC_CONTROL_CAL, | 827 | AR_PHY_AGC_CONTROL_CAL, |
831 | 0, AH_WAIT_TIMEOUT)) { | 828 | 0, AH_WAIT_TIMEOUT)) { |
832 | ath_print(common, ATH_DBG_CALIBRATE, | 829 | ath_dbg(common, ATH_DBG_CALIBRATE, |
833 | "offset calibration failed to " | 830 | "offset calibration failed to complete in 1ms; noisy environment?\n"); |
834 | "complete in 1ms; noisy environment?\n"); | ||
835 | return false; | 831 | return false; |
836 | } | 832 | } |
837 | 833 | ||
@@ -866,19 +862,19 @@ static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan) | |||
866 | 862 | ||
867 | INIT_CAL(&ah->adcgain_caldata); | 863 | INIT_CAL(&ah->adcgain_caldata); |
868 | INSERT_CAL(ah, &ah->adcgain_caldata); | 864 | INSERT_CAL(ah, &ah->adcgain_caldata); |
869 | ath_print(common, ATH_DBG_CALIBRATE, | 865 | ath_dbg(common, ATH_DBG_CALIBRATE, |
870 | "enabling ADC Gain Calibration.\n"); | 866 | "enabling ADC Gain Calibration.\n"); |
871 | 867 | ||
872 | INIT_CAL(&ah->adcdc_caldata); | 868 | INIT_CAL(&ah->adcdc_caldata); |
873 | INSERT_CAL(ah, &ah->adcdc_caldata); | 869 | INSERT_CAL(ah, &ah->adcdc_caldata); |
874 | ath_print(common, ATH_DBG_CALIBRATE, | 870 | ath_dbg(common, ATH_DBG_CALIBRATE, |
875 | "enabling ADC DC Calibration.\n"); | 871 | "enabling ADC DC Calibration.\n"); |
876 | } | 872 | } |
877 | 873 | ||
878 | INIT_CAL(&ah->iq_caldata); | 874 | INIT_CAL(&ah->iq_caldata); |
879 | INSERT_CAL(ah, &ah->iq_caldata); | 875 | INSERT_CAL(ah, &ah->iq_caldata); |
880 | ath_print(common, ATH_DBG_CALIBRATE, | 876 | ath_dbg(common, ATH_DBG_CALIBRATE, |
881 | "enabling IQ Calibration.\n"); | 877 | "enabling IQ Calibration.\n"); |
882 | 878 | ||
883 | ah->cal_list_curr = ah->cal_list; | 879 | ah->cal_list_curr = ah->cal_list; |
884 | 880 | ||
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_mac.c b/drivers/net/wireless/ath/ath9k/ar9002_mac.c index f0268e5eab3..f3f9c589158 100644 --- a/drivers/net/wireless/ath/ath9k/ar9002_mac.c +++ b/drivers/net/wireless/ath/ath9k/ar9002_mac.c | |||
@@ -111,8 +111,8 @@ static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked) | |||
111 | } | 111 | } |
112 | 112 | ||
113 | if (isr & AR_ISR_RXORN) { | 113 | if (isr & AR_ISR_RXORN) { |
114 | ath_print(common, ATH_DBG_INTERRUPT, | 114 | ath_dbg(common, ATH_DBG_INTERRUPT, |
115 | "receive FIFO overrun interrupt\n"); | 115 | "receive FIFO overrun interrupt\n"); |
116 | } | 116 | } |
117 | 117 | ||
118 | *masked |= mask2; | 118 | *masked |= mask2; |
@@ -147,25 +147,25 @@ static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked) | |||
147 | 147 | ||
148 | if (fatal_int) { | 148 | if (fatal_int) { |
149 | if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) { | 149 | if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) { |
150 | ath_print(common, ATH_DBG_ANY, | 150 | ath_dbg(common, ATH_DBG_ANY, |
151 | "received PCI FATAL interrupt\n"); | 151 | "received PCI FATAL interrupt\n"); |
152 | } | 152 | } |
153 | if (sync_cause & AR_INTR_SYNC_HOST1_PERR) { | 153 | if (sync_cause & AR_INTR_SYNC_HOST1_PERR) { |
154 | ath_print(common, ATH_DBG_ANY, | 154 | ath_dbg(common, ATH_DBG_ANY, |
155 | "received PCI PERR interrupt\n"); | 155 | "received PCI PERR interrupt\n"); |
156 | } | 156 | } |
157 | *masked |= ATH9K_INT_FATAL; | 157 | *masked |= ATH9K_INT_FATAL; |
158 | } | 158 | } |
159 | if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { | 159 | if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { |
160 | ath_print(common, ATH_DBG_INTERRUPT, | 160 | ath_dbg(common, ATH_DBG_INTERRUPT, |
161 | "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n"); | 161 | "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n"); |
162 | REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); | 162 | REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); |
163 | REG_WRITE(ah, AR_RC, 0); | 163 | REG_WRITE(ah, AR_RC, 0); |
164 | *masked |= ATH9K_INT_FATAL; | 164 | *masked |= ATH9K_INT_FATAL; |
165 | } | 165 | } |
166 | if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) { | 166 | if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) { |
167 | ath_print(common, ATH_DBG_INTERRUPT, | 167 | ath_dbg(common, ATH_DBG_INTERRUPT, |
168 | "AR_INTR_SYNC_LOCAL_TIMEOUT\n"); | 168 | "AR_INTR_SYNC_LOCAL_TIMEOUT\n"); |
169 | } | 169 | } |
170 | 170 | ||
171 | REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); | 171 | REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); |
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_calib.c b/drivers/net/wireless/ath/ath9k/ar9003_calib.c index 4c94c9ed5f8..16d20294c33 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c | |||
@@ -40,8 +40,8 @@ static void ar9003_hw_setup_calibration(struct ath_hw *ah, | |||
40 | currCal->calData->calCountMax); | 40 | currCal->calData->calCountMax); |
41 | REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); | 41 | REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); |
42 | 42 | ||
43 | ath_print(common, ATH_DBG_CALIBRATE, | 43 | ath_dbg(common, ATH_DBG_CALIBRATE, |
44 | "starting IQ Mismatch Calibration\n"); | 44 | "starting IQ Mismatch Calibration\n"); |
45 | 45 | ||
46 | /* Kick-off cal */ | 46 | /* Kick-off cal */ |
47 | REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL); | 47 | REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL); |
@@ -52,8 +52,8 @@ static void ar9003_hw_setup_calibration(struct ath_hw *ah, | |||
52 | REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_THERM, | 52 | REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_THERM, |
53 | AR_PHY_65NM_CH0_THERM_START, 1); | 53 | AR_PHY_65NM_CH0_THERM_START, 1); |
54 | 54 | ||
55 | ath_print(common, ATH_DBG_CALIBRATE, | 55 | ath_dbg(common, ATH_DBG_CALIBRATE, |
56 | "starting Temperature Compensation Calibration\n"); | 56 | "starting Temperature Compensation Calibration\n"); |
57 | break; | 57 | break; |
58 | } | 58 | } |
59 | } | 59 | } |
@@ -181,11 +181,11 @@ static void ar9003_hw_iqcal_collect(struct ath_hw *ah) | |||
181 | REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); | 181 | REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); |
182 | ah->totalIqCorrMeas[i] += | 182 | ah->totalIqCorrMeas[i] += |
183 | (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); | 183 | (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); |
184 | ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE, | 184 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE, |
185 | "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n", | 185 | "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n", |
186 | ah->cal_samples, i, ah->totalPowerMeasI[i], | 186 | ah->cal_samples, i, ah->totalPowerMeasI[i], |
187 | ah->totalPowerMeasQ[i], | 187 | ah->totalPowerMeasQ[i], |
188 | ah->totalIqCorrMeas[i]); | 188 | ah->totalIqCorrMeas[i]); |
189 | } | 189 | } |
190 | } | 190 | } |
191 | 191 | ||
@@ -207,13 +207,13 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) | |||
207 | powerMeasQ = ah->totalPowerMeasQ[i]; | 207 | powerMeasQ = ah->totalPowerMeasQ[i]; |
208 | iqCorrMeas = ah->totalIqCorrMeas[i]; | 208 | iqCorrMeas = ah->totalIqCorrMeas[i]; |
209 | 209 | ||
210 | ath_print(common, ATH_DBG_CALIBRATE, | 210 | ath_dbg(common, ATH_DBG_CALIBRATE, |
211 | "Starting IQ Cal and Correction for Chain %d\n", | 211 | "Starting IQ Cal and Correction for Chain %d\n", |
212 | i); | 212 | i); |
213 | 213 | ||
214 | ath_print(common, ATH_DBG_CALIBRATE, | 214 | ath_dbg(common, ATH_DBG_CALIBRATE, |
215 | "Orignal: Chn %diq_corr_meas = 0x%08x\n", | 215 | "Orignal: Chn %diq_corr_meas = 0x%08x\n", |
216 | i, ah->totalIqCorrMeas[i]); | 216 | i, ah->totalIqCorrMeas[i]); |
217 | 217 | ||
218 | iqCorrNeg = 0; | 218 | iqCorrNeg = 0; |
219 | 219 | ||
@@ -222,12 +222,12 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) | |||
222 | iqCorrNeg = 1; | 222 | iqCorrNeg = 1; |
223 | } | 223 | } |
224 | 224 | ||
225 | ath_print(common, ATH_DBG_CALIBRATE, | 225 | ath_dbg(common, ATH_DBG_CALIBRATE, |
226 | "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI); | 226 | "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI); |
227 | ath_print(common, ATH_DBG_CALIBRATE, | 227 | ath_dbg(common, ATH_DBG_CALIBRATE, |
228 | "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ); | 228 | "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ); |
229 | ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n", | 229 | ath_dbg(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n", |
230 | iqCorrNeg); | 230 | iqCorrNeg); |
231 | 231 | ||
232 | iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 256; | 232 | iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 256; |
233 | qCoffDenom = powerMeasQ / 64; | 233 | qCoffDenom = powerMeasQ / 64; |
@@ -235,10 +235,10 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) | |||
235 | if ((iCoffDenom != 0) && (qCoffDenom != 0)) { | 235 | if ((iCoffDenom != 0) && (qCoffDenom != 0)) { |
236 | iCoff = iqCorrMeas / iCoffDenom; | 236 | iCoff = iqCorrMeas / iCoffDenom; |
237 | qCoff = powerMeasI / qCoffDenom - 64; | 237 | qCoff = powerMeasI / qCoffDenom - 64; |
238 | ath_print(common, ATH_DBG_CALIBRATE, | 238 | ath_dbg(common, ATH_DBG_CALIBRATE, |
239 | "Chn %d iCoff = 0x%08x\n", i, iCoff); | 239 | "Chn %d iCoff = 0x%08x\n", i, iCoff); |
240 | ath_print(common, ATH_DBG_CALIBRATE, | 240 | ath_dbg(common, ATH_DBG_CALIBRATE, |
241 | "Chn %d qCoff = 0x%08x\n", i, qCoff); | 241 | "Chn %d qCoff = 0x%08x\n", i, qCoff); |
242 | 242 | ||
243 | /* Force bounds on iCoff */ | 243 | /* Force bounds on iCoff */ |
244 | if (iCoff >= 63) | 244 | if (iCoff >= 63) |
@@ -259,14 +259,13 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) | |||
259 | iCoff = iCoff & 0x7f; | 259 | iCoff = iCoff & 0x7f; |
260 | qCoff = qCoff & 0x7f; | 260 | qCoff = qCoff & 0x7f; |
261 | 261 | ||
262 | ath_print(common, ATH_DBG_CALIBRATE, | 262 | ath_dbg(common, ATH_DBG_CALIBRATE, |
263 | "Chn %d : iCoff = 0x%x qCoff = 0x%x\n", | 263 | "Chn %d : iCoff = 0x%x qCoff = 0x%x\n", |
264 | i, iCoff, qCoff); | 264 | i, iCoff, qCoff); |
265 | ath_print(common, ATH_DBG_CALIBRATE, | 265 | ath_dbg(common, ATH_DBG_CALIBRATE, |
266 | "Register offset (0x%04x) " | 266 | "Register offset (0x%04x) before update = 0x%x\n", |
267 | "before update = 0x%x\n", | 267 | offset_array[i], |
268 | offset_array[i], | 268 | REG_READ(ah, offset_array[i])); |
269 | REG_READ(ah, offset_array[i])); | ||
270 | 269 | ||
271 | REG_RMW_FIELD(ah, offset_array[i], | 270 | REG_RMW_FIELD(ah, offset_array[i], |
272 | AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF, | 271 | AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF, |
@@ -274,33 +273,29 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) | |||
274 | REG_RMW_FIELD(ah, offset_array[i], | 273 | REG_RMW_FIELD(ah, offset_array[i], |
275 | AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF, | 274 | AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF, |
276 | qCoff); | 275 | qCoff); |
277 | ath_print(common, ATH_DBG_CALIBRATE, | 276 | ath_dbg(common, ATH_DBG_CALIBRATE, |
278 | "Register offset (0x%04x) QI COFF " | 277 | "Register offset (0x%04x) QI COFF (bitfields 0x%08x) after update = 0x%x\n", |
279 | "(bitfields 0x%08x) after update = 0x%x\n", | 278 | offset_array[i], |
280 | offset_array[i], | 279 | AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF, |
281 | AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF, | 280 | REG_READ(ah, offset_array[i])); |
282 | REG_READ(ah, offset_array[i])); | 281 | ath_dbg(common, ATH_DBG_CALIBRATE, |
283 | ath_print(common, ATH_DBG_CALIBRATE, | 282 | "Register offset (0x%04x) QQ COFF (bitfields 0x%08x) after update = 0x%x\n", |
284 | "Register offset (0x%04x) QQ COFF " | 283 | offset_array[i], |
285 | "(bitfields 0x%08x) after update = 0x%x\n", | 284 | AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF, |
286 | offset_array[i], | 285 | REG_READ(ah, offset_array[i])); |
287 | AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF, | 286 | |
288 | REG_READ(ah, offset_array[i])); | 287 | ath_dbg(common, ATH_DBG_CALIBRATE, |
289 | 288 | "IQ Cal and Correction done for Chain %d\n", i); | |
290 | ath_print(common, ATH_DBG_CALIBRATE, | ||
291 | "IQ Cal and Correction done for Chain %d\n", | ||
292 | i); | ||
293 | } | 289 | } |
294 | } | 290 | } |
295 | 291 | ||
296 | REG_SET_BIT(ah, AR_PHY_RX_IQCAL_CORR_B0, | 292 | REG_SET_BIT(ah, AR_PHY_RX_IQCAL_CORR_B0, |
297 | AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE); | 293 | AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE); |
298 | ath_print(common, ATH_DBG_CALIBRATE, | 294 | ath_dbg(common, ATH_DBG_CALIBRATE, |
299 | "IQ Cal and Correction (offset 0x%04x) enabled " | 295 | "IQ Cal and Correction (offset 0x%04x) enabled (bit position 0x%08x). New Value 0x%08x\n", |
300 | "(bit position 0x%08x). New Value 0x%08x\n", | 296 | (unsigned) (AR_PHY_RX_IQCAL_CORR_B0), |
301 | (unsigned) (AR_PHY_RX_IQCAL_CORR_B0), | 297 | AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE, |
302 | AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE, | 298 | REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0)); |
303 | REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0)); | ||
304 | } | 299 | } |
305 | 300 | ||
306 | static const struct ath9k_percal_data iq_cal_single_sample = { | 301 | static const struct ath9k_percal_data iq_cal_single_sample = { |
@@ -340,7 +335,7 @@ static bool ar9003_hw_solve_iq_cal(struct ath_hw *ah, | |||
340 | f2 = (f1 * f1 + f3 * f3) / result_shift; | 335 | f2 = (f1 * f1 + f3 * f3) / result_shift; |
341 | 336 | ||
342 | if (!f2) { | 337 | if (!f2) { |
343 | ath_print(common, ATH_DBG_CALIBRATE, "Divide by 0\n"); | 338 | ath_dbg(common, ATH_DBG_CALIBRATE, "Divide by 0\n"); |
344 | return false; | 339 | return false; |
345 | } | 340 | } |
346 | 341 | ||
@@ -461,11 +456,14 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah, | |||
461 | 456 | ||
462 | if ((i2_p_q2_a0_d0 == 0) || (i2_p_q2_a0_d1 == 0) || | 457 | if ((i2_p_q2_a0_d0 == 0) || (i2_p_q2_a0_d1 == 0) || |
463 | (i2_p_q2_a1_d0 == 0) || (i2_p_q2_a1_d1 == 0)) { | 458 | (i2_p_q2_a1_d0 == 0) || (i2_p_q2_a1_d1 == 0)) { |
464 | ath_print(common, ATH_DBG_CALIBRATE, | 459 | ath_dbg(common, ATH_DBG_CALIBRATE, |
465 | "Divide by 0:\na0_d0=%d\n" | 460 | "Divide by 0:\n" |
466 | "a0_d1=%d\na2_d0=%d\na1_d1=%d\n", | 461 | "a0_d0=%d\n" |
467 | i2_p_q2_a0_d0, i2_p_q2_a0_d1, | 462 | "a0_d1=%d\n" |
468 | i2_p_q2_a1_d0, i2_p_q2_a1_d1); | 463 | "a2_d0=%d\n" |
464 | "a1_d1=%d\n", | ||
465 | i2_p_q2_a0_d0, i2_p_q2_a0_d1, | ||
466 | i2_p_q2_a1_d0, i2_p_q2_a1_d1); | ||
469 | return false; | 467 | return false; |
470 | } | 468 | } |
471 | 469 | ||
@@ -498,9 +496,9 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah, | |||
498 | mag2 = ar9003_hw_find_mag_approx(ah, cos_2phi_2, sin_2phi_2); | 496 | mag2 = ar9003_hw_find_mag_approx(ah, cos_2phi_2, sin_2phi_2); |
499 | 497 | ||
500 | if ((mag1 == 0) || (mag2 == 0)) { | 498 | if ((mag1 == 0) || (mag2 == 0)) { |
501 | ath_print(common, ATH_DBG_CALIBRATE, | 499 | ath_dbg(common, ATH_DBG_CALIBRATE, |
502 | "Divide by 0: mag1=%d, mag2=%d\n", | 500 | "Divide by 0: mag1=%d, mag2=%d\n", |
503 | mag1, mag2); | 501 | mag1, mag2); |
504 | return false; | 502 | return false; |
505 | } | 503 | } |
506 | 504 | ||
@@ -517,8 +515,8 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah, | |||
517 | mag_a0_d0, phs_a0_d0, | 515 | mag_a0_d0, phs_a0_d0, |
518 | mag_a1_d0, | 516 | mag_a1_d0, |
519 | phs_a1_d0, solved_eq)) { | 517 | phs_a1_d0, solved_eq)) { |
520 | ath_print(common, ATH_DBG_CALIBRATE, | 518 | ath_dbg(common, ATH_DBG_CALIBRATE, |
521 | "Call to ar9003_hw_solve_iq_cal() failed.\n"); | 519 | "Call to ar9003_hw_solve_iq_cal() failed.\n"); |
522 | return false; | 520 | return false; |
523 | } | 521 | } |
524 | 522 | ||
@@ -527,14 +525,14 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah, | |||
527 | mag_rx = solved_eq[2]; | 525 | mag_rx = solved_eq[2]; |
528 | phs_rx = solved_eq[3]; | 526 | phs_rx = solved_eq[3]; |
529 | 527 | ||
530 | ath_print(common, ATH_DBG_CALIBRATE, | 528 | ath_dbg(common, ATH_DBG_CALIBRATE, |
531 | "chain %d: mag mismatch=%d phase mismatch=%d\n", | 529 | "chain %d: mag mismatch=%d phase mismatch=%d\n", |
532 | chain_idx, mag_tx/res_scale, phs_tx/res_scale); | 530 | chain_idx, mag_tx/res_scale, phs_tx/res_scale); |
533 | 531 | ||
534 | if (res_scale == mag_tx) { | 532 | if (res_scale == mag_tx) { |
535 | ath_print(common, ATH_DBG_CALIBRATE, | 533 | ath_dbg(common, ATH_DBG_CALIBRATE, |
536 | "Divide by 0: mag_tx=%d, res_scale=%d\n", | 534 | "Divide by 0: mag_tx=%d, res_scale=%d\n", |
537 | mag_tx, res_scale); | 535 | mag_tx, res_scale); |
538 | return false; | 536 | return false; |
539 | } | 537 | } |
540 | 538 | ||
@@ -545,9 +543,9 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah, | |||
545 | q_q_coff = (mag_corr_tx * 128 / res_scale); | 543 | q_q_coff = (mag_corr_tx * 128 / res_scale); |
546 | q_i_coff = (phs_corr_tx * 256 / res_scale); | 544 | q_i_coff = (phs_corr_tx * 256 / res_scale); |
547 | 545 | ||
548 | ath_print(common, ATH_DBG_CALIBRATE, | 546 | ath_dbg(common, ATH_DBG_CALIBRATE, |
549 | "tx chain %d: mag corr=%d phase corr=%d\n", | 547 | "tx chain %d: mag corr=%d phase corr=%d\n", |
550 | chain_idx, q_q_coff, q_i_coff); | 548 | chain_idx, q_q_coff, q_i_coff); |
551 | 549 | ||
552 | if (q_i_coff < -63) | 550 | if (q_i_coff < -63) |
553 | q_i_coff = -63; | 551 | q_i_coff = -63; |
@@ -560,14 +558,14 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah, | |||
560 | 558 | ||
561 | iqc_coeff[0] = (q_q_coff * 128) + q_i_coff; | 559 | iqc_coeff[0] = (q_q_coff * 128) + q_i_coff; |
562 | 560 | ||
563 | ath_print(common, ATH_DBG_CALIBRATE, | 561 | ath_dbg(common, ATH_DBG_CALIBRATE, |
564 | "tx chain %d: iq corr coeff=%x\n", | 562 | "tx chain %d: iq corr coeff=%x\n", |
565 | chain_idx, iqc_coeff[0]); | 563 | chain_idx, iqc_coeff[0]); |
566 | 564 | ||
567 | if (-mag_rx == res_scale) { | 565 | if (-mag_rx == res_scale) { |
568 | ath_print(common, ATH_DBG_CALIBRATE, | 566 | ath_dbg(common, ATH_DBG_CALIBRATE, |
569 | "Divide by 0: mag_rx=%d, res_scale=%d\n", | 567 | "Divide by 0: mag_rx=%d, res_scale=%d\n", |
570 | mag_rx, res_scale); | 568 | mag_rx, res_scale); |
571 | return false; | 569 | return false; |
572 | } | 570 | } |
573 | 571 | ||
@@ -578,9 +576,9 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah, | |||
578 | q_q_coff = (mag_corr_rx * 128 / res_scale); | 576 | q_q_coff = (mag_corr_rx * 128 / res_scale); |
579 | q_i_coff = (phs_corr_rx * 256 / res_scale); | 577 | q_i_coff = (phs_corr_rx * 256 / res_scale); |
580 | 578 | ||
581 | ath_print(common, ATH_DBG_CALIBRATE, | 579 | ath_dbg(common, ATH_DBG_CALIBRATE, |
582 | "rx chain %d: mag corr=%d phase corr=%d\n", | 580 | "rx chain %d: mag corr=%d phase corr=%d\n", |
583 | chain_idx, q_q_coff, q_i_coff); | 581 | chain_idx, q_q_coff, q_i_coff); |
584 | 582 | ||
585 | if (q_i_coff < -63) | 583 | if (q_i_coff < -63) |
586 | q_i_coff = -63; | 584 | q_i_coff = -63; |
@@ -593,9 +591,9 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah, | |||
593 | 591 | ||
594 | iqc_coeff[1] = (q_q_coff * 128) + q_i_coff; | 592 | iqc_coeff[1] = (q_q_coff * 128) + q_i_coff; |
595 | 593 | ||
596 | ath_print(common, ATH_DBG_CALIBRATE, | 594 | ath_dbg(common, ATH_DBG_CALIBRATE, |
597 | "rx chain %d: iq corr coeff=%x\n", | 595 | "rx chain %d: iq corr coeff=%x\n", |
598 | chain_idx, iqc_coeff[1]); | 596 | chain_idx, iqc_coeff[1]); |
599 | 597 | ||
600 | return true; | 598 | return true; |
601 | } | 599 | } |
@@ -643,19 +641,19 @@ static void ar9003_hw_tx_iq_cal(struct ath_hw *ah) | |||
643 | if (!ath9k_hw_wait(ah, AR_PHY_TX_IQCAL_START, | 641 | if (!ath9k_hw_wait(ah, AR_PHY_TX_IQCAL_START, |
644 | AR_PHY_TX_IQCAL_START_DO_CAL, | 642 | AR_PHY_TX_IQCAL_START_DO_CAL, |
645 | 0, AH_WAIT_TIMEOUT)) { | 643 | 0, AH_WAIT_TIMEOUT)) { |
646 | ath_print(common, ATH_DBG_CALIBRATE, | 644 | ath_dbg(common, ATH_DBG_CALIBRATE, |
647 | "Tx IQ Cal not complete.\n"); | 645 | "Tx IQ Cal not complete.\n"); |
648 | goto TX_IQ_CAL_FAILED; | 646 | goto TX_IQ_CAL_FAILED; |
649 | } | 647 | } |
650 | 648 | ||
651 | for (i = 0; i < num_chains; i++) { | 649 | for (i = 0; i < num_chains; i++) { |
652 | ath_print(common, ATH_DBG_CALIBRATE, | 650 | ath_dbg(common, ATH_DBG_CALIBRATE, |
653 | "Doing Tx IQ Cal for chain %d.\n", i); | 651 | "Doing Tx IQ Cal for chain %d.\n", i); |
654 | 652 | ||
655 | if (REG_READ(ah, txiqcal_status[i]) & | 653 | if (REG_READ(ah, txiqcal_status[i]) & |
656 | AR_PHY_TX_IQCAL_STATUS_FAILED) { | 654 | AR_PHY_TX_IQCAL_STATUS_FAILED) { |
657 | ath_print(common, ATH_DBG_CALIBRATE, | 655 | ath_dbg(common, ATH_DBG_CALIBRATE, |
658 | "Tx IQ Cal failed for chain %d.\n", i); | 656 | "Tx IQ Cal failed for chain %d.\n", i); |
659 | goto TX_IQ_CAL_FAILED; | 657 | goto TX_IQ_CAL_FAILED; |
660 | } | 658 | } |
661 | 659 | ||
@@ -677,20 +675,20 @@ static void ar9003_hw_tx_iq_cal(struct ath_hw *ah) | |||
677 | chan_info_tab[i] + | 675 | chan_info_tab[i] + |
678 | offset); | 676 | offset); |
679 | 677 | ||
680 | ath_print(common, ATH_DBG_CALIBRATE, | 678 | ath_dbg(common, ATH_DBG_CALIBRATE, |
681 | "IQ RES[%d]=0x%x IQ_RES[%d]=0x%x\n", | 679 | "IQ RES[%d]=0x%x IQ_RES[%d]=0x%x\n", |
682 | idx, iq_res[idx], idx+1, iq_res[idx+1]); | 680 | idx, iq_res[idx], idx+1, iq_res[idx+1]); |
683 | } | 681 | } |
684 | 682 | ||
685 | if (!ar9003_hw_calc_iq_corr(ah, i, iq_res, iqc_coeff)) { | 683 | if (!ar9003_hw_calc_iq_corr(ah, i, iq_res, iqc_coeff)) { |
686 | ath_print(common, ATH_DBG_CALIBRATE, | 684 | ath_dbg(common, ATH_DBG_CALIBRATE, |
687 | "Failed in calculation of IQ correction.\n"); | 685 | "Failed in calculation of IQ correction.\n"); |
688 | goto TX_IQ_CAL_FAILED; | 686 | goto TX_IQ_CAL_FAILED; |
689 | } | 687 | } |
690 | 688 | ||
691 | ath_print(common, ATH_DBG_CALIBRATE, | 689 | ath_dbg(common, ATH_DBG_CALIBRATE, |
692 | "IQ_COEFF[0] = 0x%x IQ_COEFF[1] = 0x%x\n", | 690 | "IQ_COEFF[0] = 0x%x IQ_COEFF[1] = 0x%x\n", |
693 | iqc_coeff[0], iqc_coeff[1]); | 691 | iqc_coeff[0], iqc_coeff[1]); |
694 | 692 | ||
695 | REG_RMW_FIELD(ah, tx_corr_coeff[i], | 693 | REG_RMW_FIELD(ah, tx_corr_coeff[i], |
696 | AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE, | 694 | AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE, |
@@ -711,7 +709,7 @@ static void ar9003_hw_tx_iq_cal(struct ath_hw *ah) | |||
711 | return; | 709 | return; |
712 | 710 | ||
713 | TX_IQ_CAL_FAILED: | 711 | TX_IQ_CAL_FAILED: |
714 | ath_print(common, ATH_DBG_CALIBRATE, "Tx IQ Cal failed\n"); | 712 | ath_dbg(common, ATH_DBG_CALIBRATE, "Tx IQ Cal failed\n"); |
715 | } | 713 | } |
716 | 714 | ||
717 | static bool ar9003_hw_init_cal(struct ath_hw *ah, | 715 | static bool ar9003_hw_init_cal(struct ath_hw *ah, |
@@ -721,7 +719,7 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah, | |||
721 | int val; | 719 | int val; |
722 | 720 | ||
723 | val = REG_READ(ah, AR_ENT_OTP); | 721 | val = REG_READ(ah, AR_ENT_OTP); |
724 | ath_print(common, ATH_DBG_CALIBRATE, "ath9k: AR_ENT_OTP 0x%x\n", val); | 722 | ath_dbg(common, ATH_DBG_CALIBRATE, "ath9k: AR_ENT_OTP 0x%x\n", val); |
725 | 723 | ||
726 | if (val & AR_ENT_OTP_CHAIN2_DISABLE) | 724 | if (val & AR_ENT_OTP_CHAIN2_DISABLE) |
727 | ar9003_hw_set_chain_masks(ah, 0x3, 0x3); | 725 | ar9003_hw_set_chain_masks(ah, 0x3, 0x3); |
@@ -746,9 +744,8 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah, | |||
746 | /* Poll for offset calibration complete */ | 744 | /* Poll for offset calibration complete */ |
747 | if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, | 745 | if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, |
748 | 0, AH_WAIT_TIMEOUT)) { | 746 | 0, AH_WAIT_TIMEOUT)) { |
749 | ath_print(common, ATH_DBG_CALIBRATE, | 747 | ath_dbg(common, ATH_DBG_CALIBRATE, |
750 | "offset calibration failed to " | 748 | "offset calibration failed to complete in 1ms; noisy environment?\n"); |
751 | "complete in 1ms; noisy environment?\n"); | ||
752 | return false; | 749 | return false; |
753 | } | 750 | } |
754 | 751 | ||
@@ -764,15 +761,15 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah, | |||
764 | if (ah->supp_cals & IQ_MISMATCH_CAL) { | 761 | if (ah->supp_cals & IQ_MISMATCH_CAL) { |
765 | INIT_CAL(&ah->iq_caldata); | 762 | INIT_CAL(&ah->iq_caldata); |
766 | INSERT_CAL(ah, &ah->iq_caldata); | 763 | INSERT_CAL(ah, &ah->iq_caldata); |
767 | ath_print(common, ATH_DBG_CALIBRATE, | 764 | ath_dbg(common, ATH_DBG_CALIBRATE, |
768 | "enabling IQ Calibration.\n"); | 765 | "enabling IQ Calibration.\n"); |
769 | } | 766 | } |
770 | 767 | ||
771 | if (ah->supp_cals & TEMP_COMP_CAL) { | 768 | if (ah->supp_cals & TEMP_COMP_CAL) { |
772 | INIT_CAL(&ah->tempCompCalData); | 769 | INIT_CAL(&ah->tempCompCalData); |
773 | INSERT_CAL(ah, &ah->tempCompCalData); | 770 | INSERT_CAL(ah, &ah->tempCompCalData); |
774 | ath_print(common, ATH_DBG_CALIBRATE, | 771 | ath_dbg(common, ATH_DBG_CALIBRATE, |
775 | "enabling Temperature Compensation Calibration.\n"); | 772 | "enabling Temperature Compensation Calibration.\n"); |
776 | } | 773 | } |
777 | 774 | ||
778 | /* Initialize current pointer to first element in list */ | 775 | /* Initialize current pointer to first element in list */ |
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c index 872b1a3b21c..59236ffd517 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c | |||
@@ -3072,8 +3072,8 @@ static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer, | |||
3072 | int i; | 3072 | int i; |
3073 | 3073 | ||
3074 | if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) { | 3074 | if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) { |
3075 | ath_print(common, ATH_DBG_EEPROM, | 3075 | ath_dbg(common, ATH_DBG_EEPROM, |
3076 | "eeprom address not in range\n"); | 3076 | "eeprom address not in range\n"); |
3077 | return false; | 3077 | return false; |
3078 | } | 3078 | } |
3079 | 3079 | ||
@@ -3104,8 +3104,8 @@ static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer, | |||
3104 | return true; | 3104 | return true; |
3105 | 3105 | ||
3106 | error: | 3106 | error: |
3107 | ath_print(common, ATH_DBG_EEPROM, | 3107 | ath_dbg(common, ATH_DBG_EEPROM, |
3108 | "unable to read eeprom region at offset %d\n", address); | 3108 | "unable to read eeprom region at offset %d\n", address); |
3109 | return false; | 3109 | return false; |
3110 | } | 3110 | } |
3111 | 3111 | ||
@@ -3189,17 +3189,15 @@ static bool ar9300_uncompress_block(struct ath_hw *ah, | |||
3189 | length &= 0xff; | 3189 | length &= 0xff; |
3190 | 3190 | ||
3191 | if (length > 0 && spot >= 0 && spot+length <= mdataSize) { | 3191 | if (length > 0 && spot >= 0 && spot+length <= mdataSize) { |
3192 | ath_print(common, ATH_DBG_EEPROM, | 3192 | ath_dbg(common, ATH_DBG_EEPROM, |
3193 | "Restore at %d: spot=%d " | 3193 | "Restore at %d: spot=%d offset=%d length=%d\n", |
3194 | "offset=%d length=%d\n", | 3194 | it, spot, offset, length); |
3195 | it, spot, offset, length); | ||
3196 | memcpy(&mptr[spot], &block[it+2], length); | 3195 | memcpy(&mptr[spot], &block[it+2], length); |
3197 | spot += length; | 3196 | spot += length; |
3198 | } else if (length > 0) { | 3197 | } else if (length > 0) { |
3199 | ath_print(common, ATH_DBG_EEPROM, | 3198 | ath_dbg(common, ATH_DBG_EEPROM, |
3200 | "Bad restore at %d: spot=%d " | 3199 | "Bad restore at %d: spot=%d offset=%d length=%d\n", |
3201 | "offset=%d length=%d\n", | 3200 | it, spot, offset, length); |
3202 | it, spot, offset, length); | ||
3203 | return false; | 3201 | return false; |
3204 | } | 3202 | } |
3205 | } | 3203 | } |
@@ -3220,14 +3218,15 @@ static int ar9300_compress_decision(struct ath_hw *ah, | |||
3220 | switch (code) { | 3218 | switch (code) { |
3221 | case _CompressNone: | 3219 | case _CompressNone: |
3222 | if (length != mdata_size) { | 3220 | if (length != mdata_size) { |
3223 | ath_print(common, ATH_DBG_EEPROM, | 3221 | ath_dbg(common, ATH_DBG_EEPROM, |
3224 | "EEPROM structure size mismatch" | 3222 | "EEPROM structure size mismatch memory=%d eeprom=%d\n", |
3225 | "memory=%d eeprom=%d\n", mdata_size, length); | 3223 | mdata_size, length); |
3226 | return -1; | 3224 | return -1; |
3227 | } | 3225 | } |
3228 | memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length); | 3226 | memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length); |
3229 | ath_print(common, ATH_DBG_EEPROM, "restored eeprom %d:" | 3227 | ath_dbg(common, ATH_DBG_EEPROM, |
3230 | " uncompressed, length %d\n", it, length); | 3228 | "restored eeprom %d: uncompressed, length %d\n", |
3229 | it, length); | ||
3231 | break; | 3230 | break; |
3232 | case _CompressBlock: | 3231 | case _CompressBlock: |
3233 | if (reference == 0) { | 3232 | if (reference == 0) { |
@@ -3235,22 +3234,22 @@ static int ar9300_compress_decision(struct ath_hw *ah, | |||
3235 | } else { | 3234 | } else { |
3236 | eep = ar9003_eeprom_struct_find_by_id(reference); | 3235 | eep = ar9003_eeprom_struct_find_by_id(reference); |
3237 | if (eep == NULL) { | 3236 | if (eep == NULL) { |
3238 | ath_print(common, ATH_DBG_EEPROM, | 3237 | ath_dbg(common, ATH_DBG_EEPROM, |
3239 | "cant find reference eeprom" | 3238 | "cant find reference eeprom struct %d\n", |
3240 | "struct %d\n", reference); | 3239 | reference); |
3241 | return -1; | 3240 | return -1; |
3242 | } | 3241 | } |
3243 | memcpy(mptr, eep, mdata_size); | 3242 | memcpy(mptr, eep, mdata_size); |
3244 | } | 3243 | } |
3245 | ath_print(common, ATH_DBG_EEPROM, | 3244 | ath_dbg(common, ATH_DBG_EEPROM, |
3246 | "restore eeprom %d: block, reference %d," | 3245 | "restore eeprom %d: block, reference %d, length %d\n", |
3247 | " length %d\n", it, reference, length); | 3246 | it, reference, length); |
3248 | ar9300_uncompress_block(ah, mptr, mdata_size, | 3247 | ar9300_uncompress_block(ah, mptr, mdata_size, |
3249 | (u8 *) (word + COMP_HDR_LEN), length); | 3248 | (u8 *) (word + COMP_HDR_LEN), length); |
3250 | break; | 3249 | break; |
3251 | default: | 3250 | default: |
3252 | ath_print(common, ATH_DBG_EEPROM, "unknown compression" | 3251 | ath_dbg(common, ATH_DBG_EEPROM, |
3253 | " code %d\n", code); | 3252 | "unknown compression code %d\n", code); |
3254 | return -1; | 3253 | return -1; |
3255 | } | 3254 | } |
3256 | return 0; | 3255 | return 0; |
@@ -3321,26 +3320,26 @@ static int ar9300_eeprom_restore_internal(struct ath_hw *ah, | |||
3321 | 3320 | ||
3322 | read = ar9300_read_eeprom; | 3321 | read = ar9300_read_eeprom; |
3323 | cptr = AR9300_BASE_ADDR; | 3322 | cptr = AR9300_BASE_ADDR; |
3324 | ath_print(common, ATH_DBG_EEPROM, | 3323 | ath_dbg(common, ATH_DBG_EEPROM, |
3325 | "Trying EEPROM accesss at Address 0x%04x\n", cptr); | 3324 | "Trying EEPROM accesss at Address 0x%04x\n", cptr); |
3326 | if (ar9300_check_eeprom_header(ah, read, cptr)) | 3325 | if (ar9300_check_eeprom_header(ah, read, cptr)) |
3327 | goto found; | 3326 | goto found; |
3328 | 3327 | ||
3329 | cptr = AR9300_BASE_ADDR_512; | 3328 | cptr = AR9300_BASE_ADDR_512; |
3330 | ath_print(common, ATH_DBG_EEPROM, | 3329 | ath_dbg(common, ATH_DBG_EEPROM, |
3331 | "Trying EEPROM accesss at Address 0x%04x\n", cptr); | 3330 | "Trying EEPROM accesss at Address 0x%04x\n", cptr); |
3332 | if (ar9300_check_eeprom_header(ah, read, cptr)) | 3331 | if (ar9300_check_eeprom_header(ah, read, cptr)) |
3333 | goto found; | 3332 | goto found; |
3334 | 3333 | ||
3335 | read = ar9300_read_otp; | 3334 | read = ar9300_read_otp; |
3336 | cptr = AR9300_BASE_ADDR; | 3335 | cptr = AR9300_BASE_ADDR; |
3337 | ath_print(common, ATH_DBG_EEPROM, | 3336 | ath_dbg(common, ATH_DBG_EEPROM, |
3338 | "Trying OTP accesss at Address 0x%04x\n", cptr); | 3337 | "Trying OTP accesss at Address 0x%04x\n", cptr); |
3339 | if (ar9300_check_eeprom_header(ah, read, cptr)) | 3338 | if (ar9300_check_eeprom_header(ah, read, cptr)) |
3340 | goto found; | 3339 | goto found; |
3341 | 3340 | ||
3342 | cptr = AR9300_BASE_ADDR_512; | 3341 | cptr = AR9300_BASE_ADDR_512; |
3343 | ath_print(common, ATH_DBG_EEPROM, | 3342 | ath_dbg(common, ATH_DBG_EEPROM, |
3344 | "Trying OTP accesss at Address 0x%04x\n", cptr); | 3343 | "Trying OTP accesss at Address 0x%04x\n", cptr); |
3345 | if (ar9300_check_eeprom_header(ah, read, cptr)) | 3344 | if (ar9300_check_eeprom_header(ah, read, cptr)) |
3346 | goto found; | 3345 | goto found; |
@@ -3348,7 +3347,7 @@ static int ar9300_eeprom_restore_internal(struct ath_hw *ah, | |||
3348 | goto fail; | 3347 | goto fail; |
3349 | 3348 | ||
3350 | found: | 3349 | found: |
3351 | ath_print(common, ATH_DBG_EEPROM, "Found valid EEPROM data"); | 3350 | ath_dbg(common, ATH_DBG_EEPROM, "Found valid EEPROM data\n"); |
3352 | 3351 | ||
3353 | for (it = 0; it < MSTATE; it++) { | 3352 | for (it = 0; it < MSTATE; it++) { |
3354 | if (!read(ah, cptr, word, COMP_HDR_LEN)) | 3353 | if (!read(ah, cptr, word, COMP_HDR_LEN)) |
@@ -3359,13 +3358,12 @@ found: | |||
3359 | 3358 | ||
3360 | ar9300_comp_hdr_unpack(word, &code, &reference, | 3359 | ar9300_comp_hdr_unpack(word, &code, &reference, |
3361 | &length, &major, &minor); | 3360 | &length, &major, &minor); |
3362 | ath_print(common, ATH_DBG_EEPROM, | 3361 | ath_dbg(common, ATH_DBG_EEPROM, |
3363 | "Found block at %x: code=%d ref=%d" | 3362 | "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n", |
3364 | "length=%d major=%d minor=%d\n", cptr, code, | 3363 | cptr, code, reference, length, major, minor); |
3365 | reference, length, major, minor); | ||
3366 | if (length >= 1024) { | 3364 | if (length >= 1024) { |
3367 | ath_print(common, ATH_DBG_EEPROM, | 3365 | ath_dbg(common, ATH_DBG_EEPROM, |
3368 | "Skipping bad header\n"); | 3366 | "Skipping bad header\n"); |
3369 | cptr -= COMP_HDR_LEN; | 3367 | cptr -= COMP_HDR_LEN; |
3370 | continue; | 3368 | continue; |
3371 | } | 3369 | } |
@@ -3375,14 +3373,14 @@ found: | |||
3375 | checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length); | 3373 | checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length); |
3376 | mchecksum = word[COMP_HDR_LEN + osize] | | 3374 | mchecksum = word[COMP_HDR_LEN + osize] | |
3377 | (word[COMP_HDR_LEN + osize + 1] << 8); | 3375 | (word[COMP_HDR_LEN + osize + 1] << 8); |
3378 | ath_print(common, ATH_DBG_EEPROM, | 3376 | ath_dbg(common, ATH_DBG_EEPROM, |
3379 | "checksum %x %x\n", checksum, mchecksum); | 3377 | "checksum %x %x\n", checksum, mchecksum); |
3380 | if (checksum == mchecksum) { | 3378 | if (checksum == mchecksum) { |
3381 | ar9300_compress_decision(ah, it, code, reference, mptr, | 3379 | ar9300_compress_decision(ah, it, code, reference, mptr, |
3382 | word, length, mdata_size); | 3380 | word, length, mdata_size); |
3383 | } else { | 3381 | } else { |
3384 | ath_print(common, ATH_DBG_EEPROM, | 3382 | ath_dbg(common, ATH_DBG_EEPROM, |
3385 | "skipping block with bad checksum\n"); | 3383 | "skipping block with bad checksum\n"); |
3386 | } | 3384 | } |
3387 | cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN); | 3385 | cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN); |
3388 | } | 3386 | } |
@@ -4092,20 +4090,20 @@ static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq, | |||
4092 | is2GHz) + ht40PowerIncForPdadc; | 4090 | is2GHz) + ht40PowerIncForPdadc; |
4093 | 4091 | ||
4094 | while (i < ar9300RateSize) { | 4092 | while (i < ar9300RateSize) { |
4095 | ath_print(common, ATH_DBG_EEPROM, | 4093 | ath_dbg(common, ATH_DBG_EEPROM, |
4096 | "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]); | 4094 | "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]); |
4097 | i++; | 4095 | i++; |
4098 | 4096 | ||
4099 | ath_print(common, ATH_DBG_EEPROM, | 4097 | ath_dbg(common, ATH_DBG_EEPROM, |
4100 | "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]); | 4098 | "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]); |
4101 | i++; | 4099 | i++; |
4102 | 4100 | ||
4103 | ath_print(common, ATH_DBG_EEPROM, | 4101 | ath_dbg(common, ATH_DBG_EEPROM, |
4104 | "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]); | 4102 | "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]); |
4105 | i++; | 4103 | i++; |
4106 | 4104 | ||
4107 | ath_print(common, ATH_DBG_EEPROM, | 4105 | ath_dbg(common, ATH_DBG_EEPROM, |
4108 | "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]); | 4106 | "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]); |
4109 | i++; | 4107 | i++; |
4110 | } | 4108 | } |
4111 | } | 4109 | } |
@@ -4125,18 +4123,17 @@ static int ar9003_hw_cal_pier_get(struct ath_hw *ah, | |||
4125 | struct ath_common *common = ath9k_hw_common(ah); | 4123 | struct ath_common *common = ath9k_hw_common(ah); |
4126 | 4124 | ||
4127 | if (ichain >= AR9300_MAX_CHAINS) { | 4125 | if (ichain >= AR9300_MAX_CHAINS) { |
4128 | ath_print(common, ATH_DBG_EEPROM, | 4126 | ath_dbg(common, ATH_DBG_EEPROM, |
4129 | "Invalid chain index, must be less than %d\n", | 4127 | "Invalid chain index, must be less than %d\n", |
4130 | AR9300_MAX_CHAINS); | 4128 | AR9300_MAX_CHAINS); |
4131 | return -1; | 4129 | return -1; |
4132 | } | 4130 | } |
4133 | 4131 | ||
4134 | if (mode) { /* 5GHz */ | 4132 | if (mode) { /* 5GHz */ |
4135 | if (ipier >= AR9300_NUM_5G_CAL_PIERS) { | 4133 | if (ipier >= AR9300_NUM_5G_CAL_PIERS) { |
4136 | ath_print(common, ATH_DBG_EEPROM, | 4134 | ath_dbg(common, ATH_DBG_EEPROM, |
4137 | "Invalid 5GHz cal pier index, must " | 4135 | "Invalid 5GHz cal pier index, must be less than %d\n", |
4138 | "be less than %d\n", | 4136 | AR9300_NUM_5G_CAL_PIERS); |
4139 | AR9300_NUM_5G_CAL_PIERS); | ||
4140 | return -1; | 4137 | return -1; |
4141 | } | 4138 | } |
4142 | pCalPier = &(eep->calFreqPier5G[ipier]); | 4139 | pCalPier = &(eep->calFreqPier5G[ipier]); |
@@ -4144,9 +4141,9 @@ static int ar9003_hw_cal_pier_get(struct ath_hw *ah, | |||
4144 | is2GHz = 0; | 4141 | is2GHz = 0; |
4145 | } else { | 4142 | } else { |
4146 | if (ipier >= AR9300_NUM_2G_CAL_PIERS) { | 4143 | if (ipier >= AR9300_NUM_2G_CAL_PIERS) { |
4147 | ath_print(common, ATH_DBG_EEPROM, | 4144 | ath_dbg(common, ATH_DBG_EEPROM, |
4148 | "Invalid 2GHz cal pier index, must " | 4145 | "Invalid 2GHz cal pier index, must be less than %d\n", |
4149 | "be less than %d\n", AR9300_NUM_2G_CAL_PIERS); | 4146 | AR9300_NUM_2G_CAL_PIERS); |
4150 | return -1; | 4147 | return -1; |
4151 | } | 4148 | } |
4152 | 4149 | ||
@@ -4296,11 +4293,11 @@ static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency) | |||
4296 | 4293 | ||
4297 | /* interpolate */ | 4294 | /* interpolate */ |
4298 | for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) { | 4295 | for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) { |
4299 | ath_print(common, ATH_DBG_EEPROM, | 4296 | ath_dbg(common, ATH_DBG_EEPROM, |
4300 | "ch=%d f=%d low=%d %d h=%d %d\n", | 4297 | "ch=%d f=%d low=%d %d h=%d %d\n", |
4301 | ichain, frequency, lfrequency[ichain], | 4298 | ichain, frequency, lfrequency[ichain], |
4302 | lcorrection[ichain], hfrequency[ichain], | 4299 | lcorrection[ichain], hfrequency[ichain], |
4303 | hcorrection[ichain]); | 4300 | hcorrection[ichain]); |
4304 | /* they're the same, so just pick one */ | 4301 | /* they're the same, so just pick one */ |
4305 | if (hfrequency[ichain] == lfrequency[ichain]) { | 4302 | if (hfrequency[ichain] == lfrequency[ichain]) { |
4306 | correction[ichain] = lcorrection[ichain]; | 4303 | correction[ichain] = lcorrection[ichain]; |
@@ -4352,9 +4349,9 @@ static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency) | |||
4352 | ar9003_hw_power_control_override(ah, frequency, correction, voltage, | 4349 | ar9003_hw_power_control_override(ah, frequency, correction, voltage, |
4353 | temperature); | 4350 | temperature); |
4354 | 4351 | ||
4355 | ath_print(common, ATH_DBG_EEPROM, | 4352 | ath_dbg(common, ATH_DBG_EEPROM, |
4356 | "for frequency=%d, calibration correction = %d %d %d\n", | 4353 | "for frequency=%d, calibration correction = %d %d %d\n", |
4357 | frequency, correction[0], correction[1], correction[2]); | 4354 | frequency, correction[0], correction[1], correction[2]); |
4358 | 4355 | ||
4359 | return 0; | 4356 | return 0; |
4360 | } | 4357 | } |
@@ -4559,11 +4556,10 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah, | |||
4559 | else | 4556 | else |
4560 | freq = centers.ctl_center; | 4557 | freq = centers.ctl_center; |
4561 | 4558 | ||
4562 | ath_print(common, ATH_DBG_REGULATORY, | 4559 | ath_dbg(common, ATH_DBG_REGULATORY, |
4563 | "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, " | 4560 | "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n", |
4564 | "EXT_ADDITIVE %d\n", | 4561 | ctlMode, numCtlModes, isHt40CtlMode, |
4565 | ctlMode, numCtlModes, isHt40CtlMode, | 4562 | (pCtlMode[ctlMode] & EXT_ADDITIVE)); |
4566 | (pCtlMode[ctlMode] & EXT_ADDITIVE)); | ||
4567 | 4563 | ||
4568 | /* walk through each CTL index stored in EEPROM */ | 4564 | /* walk through each CTL index stored in EEPROM */ |
4569 | if (is2ghz) { | 4565 | if (is2ghz) { |
@@ -4575,12 +4571,10 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah, | |||
4575 | } | 4571 | } |
4576 | 4572 | ||
4577 | for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) { | 4573 | for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) { |
4578 | ath_print(common, ATH_DBG_REGULATORY, | 4574 | ath_dbg(common, ATH_DBG_REGULATORY, |
4579 | "LOOP-Ctlidx %d: cfgCtl 0x%2.2x " | 4575 | "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n", |
4580 | "pCtlMode 0x%2.2x ctlIndex 0x%2.2x " | 4576 | i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i], |
4581 | "chan %dn", | 4577 | chan->channel); |
4582 | i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i], | ||
4583 | chan->channel); | ||
4584 | 4578 | ||
4585 | /* | 4579 | /* |
4586 | * compare test group from regulatory | 4580 | * compare test group from regulatory |
@@ -4619,11 +4613,10 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah, | |||
4619 | 4613 | ||
4620 | minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower); | 4614 | minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower); |
4621 | 4615 | ||
4622 | ath_print(common, ATH_DBG_REGULATORY, | 4616 | ath_dbg(common, ATH_DBG_REGULATORY, |
4623 | "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d " | 4617 | "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n", |
4624 | "sP %d minCtlPwr %d\n", | 4618 | ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower, |
4625 | ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower, | 4619 | scaledPower, minCtlPower); |
4626 | scaledPower, minCtlPower); | ||
4627 | 4620 | ||
4628 | /* Apply ctl mode to correct target power set */ | 4621 | /* Apply ctl mode to correct target power set */ |
4629 | switch (pCtlMode[ctlMode]) { | 4622 | switch (pCtlMode[ctlMode]) { |
@@ -4698,17 +4691,17 @@ static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah, | |||
4698 | return; | 4691 | return; |
4699 | 4692 | ||
4700 | for (i = 0; i < ar9300RateSize; i++) { | 4693 | for (i = 0; i < ar9300RateSize; i++) { |
4701 | ath_print(common, ATH_DBG_EEPROM, | 4694 | ath_dbg(common, ATH_DBG_EEPROM, |
4702 | "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]); | 4695 | "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]); |
4703 | i++; | 4696 | i++; |
4704 | ath_print(common, ATH_DBG_EEPROM, | 4697 | ath_dbg(common, ATH_DBG_EEPROM, |
4705 | "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]); | 4698 | "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]); |
4706 | i++; | 4699 | i++; |
4707 | ath_print(common, ATH_DBG_EEPROM, | 4700 | ath_dbg(common, ATH_DBG_EEPROM, |
4708 | "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]); | 4701 | "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]); |
4709 | i++; | 4702 | i++; |
4710 | ath_print(common, ATH_DBG_EEPROM, | 4703 | ath_dbg(common, ATH_DBG_EEPROM, |
4711 | "TPC[%02d] 0x%08x\n\n", i, targetPowerValT2[i]); | 4704 | "TPC[%02d] 0x%08x\n\n", i, targetPowerValT2[i]); |
4712 | i++; | 4705 | i++; |
4713 | } | 4706 | } |
4714 | 4707 | ||
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mac.c b/drivers/net/wireless/ath/ath9k/ar9003_mac.c index f5896aa3000..bfba6a2b741 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c | |||
@@ -182,8 +182,8 @@ static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked) | |||
182 | } | 182 | } |
183 | 183 | ||
184 | if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) | 184 | if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) |
185 | ath_print(common, ATH_DBG_INTERRUPT, | 185 | ath_dbg(common, ATH_DBG_INTERRUPT, |
186 | "AR_INTR_SYNC_LOCAL_TIMEOUT\n"); | 186 | "AR_INTR_SYNC_LOCAL_TIMEOUT\n"); |
187 | 187 | ||
188 | REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); | 188 | REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); |
189 | (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); | 189 | (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); |
@@ -249,8 +249,8 @@ static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds, | |||
249 | 249 | ||
250 | if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) || | 250 | if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) || |
251 | (MS(ads->ds_info, AR_TxRxDesc) != 1)) { | 251 | (MS(ads->ds_info, AR_TxRxDesc) != 1)) { |
252 | ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT, | 252 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT, |
253 | "Tx Descriptor error %x\n", ads->ds_info); | 253 | "Tx Descriptor error %x\n", ads->ds_info); |
254 | memset(ads, 0, sizeof(*ads)); | 254 | memset(ads, 0, sizeof(*ads)); |
255 | return -EIO; | 255 | return -EIO; |
256 | } | 256 | } |
@@ -658,10 +658,10 @@ void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah) | |||
658 | memset((void *) ah->ts_ring, 0, | 658 | memset((void *) ah->ts_ring, 0, |
659 | ah->ts_size * sizeof(struct ar9003_txs)); | 659 | ah->ts_size * sizeof(struct ar9003_txs)); |
660 | 660 | ||
661 | ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT, | 661 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT, |
662 | "TS Start 0x%x End 0x%x Virt %p, Size %d\n", | 662 | "TS Start 0x%x End 0x%x Virt %p, Size %d\n", |
663 | ah->ts_paddr_start, ah->ts_paddr_end, | 663 | ah->ts_paddr_start, ah->ts_paddr_end, |
664 | ah->ts_ring, ah->ts_size); | 664 | ah->ts_ring, ah->ts_size); |
665 | 665 | ||
666 | REG_WRITE(ah, AR_Q_STATUS_RING_START, ah->ts_paddr_start); | 666 | REG_WRITE(ah, AR_Q_STATUS_RING_START, ah->ts_paddr_start); |
667 | REG_WRITE(ah, AR_Q_STATUS_RING_END, ah->ts_paddr_end); | 667 | REG_WRITE(ah, AR_Q_STATUS_RING_END, ah->ts_paddr_end); |
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c index b34a9e91edd..63b6d560c7f 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c | |||
@@ -824,12 +824,12 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah, | |||
824 | AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); | 824 | AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); |
825 | 825 | ||
826 | if (!on != aniState->ofdmWeakSigDetectOff) { | 826 | if (!on != aniState->ofdmWeakSigDetectOff) { |
827 | ath_print(common, ATH_DBG_ANI, | 827 | ath_dbg(common, ATH_DBG_ANI, |
828 | "** ch %d: ofdm weak signal: %s=>%s\n", | 828 | "** ch %d: ofdm weak signal: %s=>%s\n", |
829 | chan->channel, | 829 | chan->channel, |
830 | !aniState->ofdmWeakSigDetectOff ? | 830 | !aniState->ofdmWeakSigDetectOff ? |
831 | "on" : "off", | 831 | "on" : "off", |
832 | on ? "on" : "off"); | 832 | on ? "on" : "off"); |
833 | if (on) | 833 | if (on) |
834 | ah->stats.ast_ani_ofdmon++; | 834 | ah->stats.ast_ani_ofdmon++; |
835 | else | 835 | else |
@@ -842,11 +842,9 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah, | |||
842 | u32 level = param; | 842 | u32 level = param; |
843 | 843 | ||
844 | if (level >= ARRAY_SIZE(firstep_table)) { | 844 | if (level >= ARRAY_SIZE(firstep_table)) { |
845 | ath_print(common, ATH_DBG_ANI, | 845 | ath_dbg(common, ATH_DBG_ANI, |
846 | "ATH9K_ANI_FIRSTEP_LEVEL: level " | 846 | "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n", |
847 | "out of range (%u > %u)\n", | 847 | level, ARRAY_SIZE(firstep_table)); |
848 | level, | ||
849 | (unsigned) ARRAY_SIZE(firstep_table)); | ||
850 | return false; | 848 | return false; |
851 | } | 849 | } |
852 | 850 | ||
@@ -881,24 +879,22 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah, | |||
881 | AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2); | 879 | AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2); |
882 | 880 | ||
883 | if (level != aniState->firstepLevel) { | 881 | if (level != aniState->firstepLevel) { |
884 | ath_print(common, ATH_DBG_ANI, | 882 | ath_dbg(common, ATH_DBG_ANI, |
885 | "** ch %d: level %d=>%d[def:%d] " | 883 | "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n", |
886 | "firstep[level]=%d ini=%d\n", | 884 | chan->channel, |
887 | chan->channel, | 885 | aniState->firstepLevel, |
888 | aniState->firstepLevel, | 886 | level, |
889 | level, | 887 | ATH9K_ANI_FIRSTEP_LVL_NEW, |
890 | ATH9K_ANI_FIRSTEP_LVL_NEW, | 888 | value, |
891 | value, | 889 | aniState->iniDef.firstep); |
892 | aniState->iniDef.firstep); | 890 | ath_dbg(common, ATH_DBG_ANI, |
893 | ath_print(common, ATH_DBG_ANI, | 891 | "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n", |
894 | "** ch %d: level %d=>%d[def:%d] " | 892 | chan->channel, |
895 | "firstep_low[level]=%d ini=%d\n", | 893 | aniState->firstepLevel, |
896 | chan->channel, | 894 | level, |
897 | aniState->firstepLevel, | 895 | ATH9K_ANI_FIRSTEP_LVL_NEW, |
898 | level, | 896 | value2, |
899 | ATH9K_ANI_FIRSTEP_LVL_NEW, | 897 | aniState->iniDef.firstepLow); |
900 | value2, | ||
901 | aniState->iniDef.firstepLow); | ||
902 | if (level > aniState->firstepLevel) | 898 | if (level > aniState->firstepLevel) |
903 | ah->stats.ast_ani_stepup++; | 899 | ah->stats.ast_ani_stepup++; |
904 | else if (level < aniState->firstepLevel) | 900 | else if (level < aniState->firstepLevel) |
@@ -911,11 +907,9 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah, | |||
911 | u32 level = param; | 907 | u32 level = param; |
912 | 908 | ||
913 | if (level >= ARRAY_SIZE(cycpwrThr1_table)) { | 909 | if (level >= ARRAY_SIZE(cycpwrThr1_table)) { |
914 | ath_print(common, ATH_DBG_ANI, | 910 | ath_dbg(common, ATH_DBG_ANI, |
915 | "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level " | 911 | "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n", |
916 | "out of range (%u > %u)\n", | 912 | level, ARRAY_SIZE(cycpwrThr1_table)); |
917 | level, | ||
918 | (unsigned) ARRAY_SIZE(cycpwrThr1_table)); | ||
919 | return false; | 913 | return false; |
920 | } | 914 | } |
921 | /* | 915 | /* |
@@ -949,24 +943,22 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah, | |||
949 | AR_PHY_EXT_CYCPWR_THR1, value2); | 943 | AR_PHY_EXT_CYCPWR_THR1, value2); |
950 | 944 | ||
951 | if (level != aniState->spurImmunityLevel) { | 945 | if (level != aniState->spurImmunityLevel) { |
952 | ath_print(common, ATH_DBG_ANI, | 946 | ath_dbg(common, ATH_DBG_ANI, |
953 | "** ch %d: level %d=>%d[def:%d] " | 947 | "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n", |
954 | "cycpwrThr1[level]=%d ini=%d\n", | 948 | chan->channel, |
955 | chan->channel, | 949 | aniState->spurImmunityLevel, |
956 | aniState->spurImmunityLevel, | 950 | level, |
957 | level, | 951 | ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, |
958 | ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, | 952 | value, |
959 | value, | 953 | aniState->iniDef.cycpwrThr1); |
960 | aniState->iniDef.cycpwrThr1); | 954 | ath_dbg(common, ATH_DBG_ANI, |
961 | ath_print(common, ATH_DBG_ANI, | 955 | "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n", |
962 | "** ch %d: level %d=>%d[def:%d] " | 956 | chan->channel, |
963 | "cycpwrThr1Ext[level]=%d ini=%d\n", | 957 | aniState->spurImmunityLevel, |
964 | chan->channel, | 958 | level, |
965 | aniState->spurImmunityLevel, | 959 | ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, |
966 | level, | 960 | value2, |
967 | ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, | 961 | aniState->iniDef.cycpwrThr1Ext); |
968 | value2, | ||
969 | aniState->iniDef.cycpwrThr1Ext); | ||
970 | if (level > aniState->spurImmunityLevel) | 962 | if (level > aniState->spurImmunityLevel) |
971 | ah->stats.ast_ani_spurup++; | 963 | ah->stats.ast_ani_spurup++; |
972 | else if (level < aniState->spurImmunityLevel) | 964 | else if (level < aniState->spurImmunityLevel) |
@@ -986,11 +978,11 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah, | |||
986 | REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, | 978 | REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, |
987 | AR_PHY_MRC_CCK_MUX_REG, is_on); | 979 | AR_PHY_MRC_CCK_MUX_REG, is_on); |
988 | if (!is_on != aniState->mrcCCKOff) { | 980 | if (!is_on != aniState->mrcCCKOff) { |
989 | ath_print(common, ATH_DBG_ANI, | 981 | ath_dbg(common, ATH_DBG_ANI, |
990 | "** ch %d: MRC CCK: %s=>%s\n", | 982 | "** ch %d: MRC CCK: %s=>%s\n", |
991 | chan->channel, | 983 | chan->channel, |
992 | !aniState->mrcCCKOff ? "on" : "off", | 984 | !aniState->mrcCCKOff ? "on" : "off", |
993 | is_on ? "on" : "off"); | 985 | is_on ? "on" : "off"); |
994 | if (is_on) | 986 | if (is_on) |
995 | ah->stats.ast_ani_ccklow++; | 987 | ah->stats.ast_ani_ccklow++; |
996 | else | 988 | else |
@@ -1002,22 +994,19 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah, | |||
1002 | case ATH9K_ANI_PRESENT: | 994 | case ATH9K_ANI_PRESENT: |
1003 | break; | 995 | break; |
1004 | default: | 996 | default: |
1005 | ath_print(common, ATH_DBG_ANI, | 997 | ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd); |
1006 | "invalid cmd %u\n", cmd); | ||
1007 | return false; | 998 | return false; |
1008 | } | 999 | } |
1009 | 1000 | ||
1010 | ath_print(common, ATH_DBG_ANI, | 1001 | ath_dbg(common, ATH_DBG_ANI, |
1011 | "ANI parameters: SI=%d, ofdmWS=%s FS=%d " | 1002 | "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n", |
1012 | "MRCcck=%s listenTime=%d " | 1003 | aniState->spurImmunityLevel, |
1013 | "ofdmErrs=%d cckErrs=%d\n", | 1004 | !aniState->ofdmWeakSigDetectOff ? "on" : "off", |
1014 | aniState->spurImmunityLevel, | 1005 | aniState->firstepLevel, |
1015 | !aniState->ofdmWeakSigDetectOff ? "on" : "off", | 1006 | !aniState->mrcCCKOff ? "on" : "off", |
1016 | aniState->firstepLevel, | 1007 | aniState->listenTime, |
1017 | !aniState->mrcCCKOff ? "on" : "off", | 1008 | aniState->ofdmPhyErrCount, |
1018 | aniState->listenTime, | 1009 | aniState->cckPhyErrCount); |
1019 | aniState->ofdmPhyErrCount, | ||
1020 | aniState->cckPhyErrCount); | ||
1021 | return true; | 1010 | return true; |
1022 | } | 1011 | } |
1023 | 1012 | ||
@@ -1074,13 +1063,13 @@ static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah) | |||
1074 | aniState = &ah->curchan->ani; | 1063 | aniState = &ah->curchan->ani; |
1075 | iniDef = &aniState->iniDef; | 1064 | iniDef = &aniState->iniDef; |
1076 | 1065 | ||
1077 | ath_print(common, ATH_DBG_ANI, | 1066 | ath_dbg(common, ATH_DBG_ANI, |
1078 | "ver %d.%d opmode %u chan %d Mhz/0x%x\n", | 1067 | "ver %d.%d opmode %u chan %d Mhz/0x%x\n", |
1079 | ah->hw_version.macVersion, | 1068 | ah->hw_version.macVersion, |
1080 | ah->hw_version.macRev, | 1069 | ah->hw_version.macRev, |
1081 | ah->opmode, | 1070 | ah->opmode, |
1082 | chan->channel, | 1071 | chan->channel, |
1083 | chan->channelFlags); | 1072 | chan->channelFlags); |
1084 | 1073 | ||
1085 | val = REG_READ(ah, AR_PHY_SFCORR); | 1074 | val = REG_READ(ah, AR_PHY_SFCORR); |
1086 | iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); | 1075 | iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); |
@@ -1216,7 +1205,7 @@ void ar9003_hw_bb_watchdog_config(struct ath_hw *ah) | |||
1216 | ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE | | 1205 | ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE | |
1217 | AR_PHY_WATCHDOG_IDLE_ENABLE)); | 1206 | AR_PHY_WATCHDOG_IDLE_ENABLE)); |
1218 | 1207 | ||
1219 | ath_print(common, ATH_DBG_RESET, "Disabled BB Watchdog\n"); | 1208 | ath_dbg(common, ATH_DBG_RESET, "Disabled BB Watchdog\n"); |
1220 | return; | 1209 | return; |
1221 | } | 1210 | } |
1222 | 1211 | ||
@@ -1252,9 +1241,9 @@ void ar9003_hw_bb_watchdog_config(struct ath_hw *ah) | |||
1252 | AR_PHY_WATCHDOG_IDLE_MASK | | 1241 | AR_PHY_WATCHDOG_IDLE_MASK | |
1253 | (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2))); | 1242 | (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2))); |
1254 | 1243 | ||
1255 | ath_print(common, ATH_DBG_RESET, | 1244 | ath_dbg(common, ATH_DBG_RESET, |
1256 | "Enabled BB Watchdog timeout (%u ms)\n", | 1245 | "Enabled BB Watchdog timeout (%u ms)\n", |
1257 | idle_tmo_ms); | 1246 | idle_tmo_ms); |
1258 | } | 1247 | } |
1259 | 1248 | ||
1260 | void ar9003_hw_bb_watchdog_read(struct ath_hw *ah) | 1249 | void ar9003_hw_bb_watchdog_read(struct ath_hw *ah) |
@@ -1282,37 +1271,35 @@ void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah) | |||
1282 | return; | 1271 | return; |
1283 | 1272 | ||
1284 | status = ah->bb_watchdog_last_status; | 1273 | status = ah->bb_watchdog_last_status; |
1285 | ath_print(common, ATH_DBG_RESET, | 1274 | ath_dbg(common, ATH_DBG_RESET, |
1286 | "\n==== BB update: BB status=0x%08x ====\n", status); | 1275 | "\n==== BB update: BB status=0x%08x ====\n", status); |
1287 | ath_print(common, ATH_DBG_RESET, | 1276 | ath_dbg(common, ATH_DBG_RESET, |
1288 | "** BB state: wd=%u det=%u rdar=%u rOFDM=%d " | 1277 | "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n", |
1289 | "rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n", | 1278 | MS(status, AR_PHY_WATCHDOG_INFO), |
1290 | MS(status, AR_PHY_WATCHDOG_INFO), | 1279 | MS(status, AR_PHY_WATCHDOG_DET_HANG), |
1291 | MS(status, AR_PHY_WATCHDOG_DET_HANG), | 1280 | MS(status, AR_PHY_WATCHDOG_RADAR_SM), |
1292 | MS(status, AR_PHY_WATCHDOG_RADAR_SM), | 1281 | MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM), |
1293 | MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM), | 1282 | MS(status, AR_PHY_WATCHDOG_RX_CCK_SM), |
1294 | MS(status, AR_PHY_WATCHDOG_RX_CCK_SM), | 1283 | MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM), |
1295 | MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM), | 1284 | MS(status, AR_PHY_WATCHDOG_TX_CCK_SM), |
1296 | MS(status, AR_PHY_WATCHDOG_TX_CCK_SM), | 1285 | MS(status, AR_PHY_WATCHDOG_AGC_SM), |
1297 | MS(status, AR_PHY_WATCHDOG_AGC_SM), | 1286 | MS(status, AR_PHY_WATCHDOG_SRCH_SM)); |
1298 | MS(status,AR_PHY_WATCHDOG_SRCH_SM)); | 1287 | |
1299 | 1288 | ath_dbg(common, ATH_DBG_RESET, | |
1300 | ath_print(common, ATH_DBG_RESET, | 1289 | "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n", |
1301 | "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n", | 1290 | REG_READ(ah, AR_PHY_WATCHDOG_CTL_1), |
1302 | REG_READ(ah, AR_PHY_WATCHDOG_CTL_1), | 1291 | REG_READ(ah, AR_PHY_WATCHDOG_CTL_2)); |
1303 | REG_READ(ah, AR_PHY_WATCHDOG_CTL_2)); | 1292 | ath_dbg(common, ATH_DBG_RESET, |
1304 | ath_print(common, ATH_DBG_RESET, | 1293 | "** BB mode: BB_gen_controls=0x%08x **\n", |
1305 | "** BB mode: BB_gen_controls=0x%08x **\n", | 1294 | REG_READ(ah, AR_PHY_GEN_CTRL)); |
1306 | REG_READ(ah, AR_PHY_GEN_CTRL)); | ||
1307 | 1295 | ||
1308 | #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles) | 1296 | #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles) |
1309 | if (common->cc_survey.cycles) | 1297 | if (common->cc_survey.cycles) |
1310 | ath_print(common, ATH_DBG_RESET, | 1298 | ath_dbg(common, ATH_DBG_RESET, |
1311 | "** BB busy times: rx_clear=%d%%, " | 1299 | "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n", |
1312 | "rx_frame=%d%%, tx_frame=%d%% **\n", | 1300 | PCT(rx_busy), PCT(rx_frame), PCT(tx_frame)); |
1313 | PCT(rx_busy), PCT(rx_frame), PCT(tx_frame)); | ||
1314 | 1301 | ||
1315 | ath_print(common, ATH_DBG_RESET, | 1302 | ath_dbg(common, ATH_DBG_RESET, |
1316 | "==== BB update: done ====\n\n"); | 1303 | "==== BB update: done ====\n\n"); |
1317 | } | 1304 | } |
1318 | EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info); | 1305 | EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info); |
diff --git a/drivers/net/wireless/ath/ath9k/beacon.c b/drivers/net/wireless/ath/ath9k/beacon.c index 70019e93e73..5e108c08690 100644 --- a/drivers/net/wireless/ath/ath9k/beacon.c +++ b/drivers/net/wireless/ath/ath9k/beacon.c | |||
@@ -120,11 +120,11 @@ static void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb) | |||
120 | memset(&txctl, 0, sizeof(struct ath_tx_control)); | 120 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
121 | txctl.txq = sc->beacon.cabq; | 121 | txctl.txq = sc->beacon.cabq; |
122 | 122 | ||
123 | ath_print(common, ATH_DBG_XMIT, | 123 | ath_dbg(common, ATH_DBG_XMIT, |
124 | "transmitting CABQ packet, skb: %p\n", skb); | 124 | "transmitting CABQ packet, skb: %p\n", skb); |
125 | 125 | ||
126 | if (ath_tx_start(hw, skb, &txctl) != 0) { | 126 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
127 | ath_print(common, ATH_DBG_XMIT, "CABQ TX failed\n"); | 127 | ath_dbg(common, ATH_DBG_XMIT, "CABQ TX failed\n"); |
128 | dev_kfree_skb_any(skb); | 128 | dev_kfree_skb_any(skb); |
129 | } | 129 | } |
130 | } | 130 | } |
@@ -209,8 +209,8 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw, | |||
209 | 209 | ||
210 | if (skb && cabq_depth) { | 210 | if (skb && cabq_depth) { |
211 | if (sc->nvifs > 1) { | 211 | if (sc->nvifs > 1) { |
212 | ath_print(common, ATH_DBG_BEACON, | 212 | ath_dbg(common, ATH_DBG_BEACON, |
213 | "Flushing previous cabq traffic\n"); | 213 | "Flushing previous cabq traffic\n"); |
214 | ath_draintxq(sc, cabq, false); | 214 | ath_draintxq(sc, cabq, false); |
215 | } | 215 | } |
216 | } | 216 | } |
@@ -282,7 +282,7 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif) | |||
282 | /* NB: the beacon data buffer must be 32-bit aligned. */ | 282 | /* NB: the beacon data buffer must be 32-bit aligned. */ |
283 | skb = ieee80211_beacon_get(sc->hw, vif); | 283 | skb = ieee80211_beacon_get(sc->hw, vif); |
284 | if (skb == NULL) { | 284 | if (skb == NULL) { |
285 | ath_print(common, ATH_DBG_BEACON, "cannot get skb\n"); | 285 | ath_dbg(common, ATH_DBG_BEACON, "cannot get skb\n"); |
286 | return -ENOMEM; | 286 | return -ENOMEM; |
287 | } | 287 | } |
288 | 288 | ||
@@ -306,10 +306,9 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif) | |||
306 | tsfadjust = intval * avp->av_bslot / ATH_BCBUF; | 306 | tsfadjust = intval * avp->av_bslot / ATH_BCBUF; |
307 | avp->tsf_adjust = cpu_to_le64(TU_TO_USEC(tsfadjust)); | 307 | avp->tsf_adjust = cpu_to_le64(TU_TO_USEC(tsfadjust)); |
308 | 308 | ||
309 | ath_print(common, ATH_DBG_BEACON, | 309 | ath_dbg(common, ATH_DBG_BEACON, |
310 | "stagger beacons, bslot %d intval " | 310 | "stagger beacons, bslot %d intval %u tsfadjust %llu\n", |
311 | "%u tsfadjust %llu\n", | 311 | avp->av_bslot, intval, (unsigned long long)tsfadjust); |
312 | avp->av_bslot, intval, (unsigned long long)tsfadjust); | ||
313 | 312 | ||
314 | ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp = | 313 | ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp = |
315 | avp->tsf_adjust; | 314 | avp->tsf_adjust; |
@@ -380,13 +379,13 @@ void ath_beacon_tasklet(unsigned long data) | |||
380 | sc->beacon.bmisscnt++; | 379 | sc->beacon.bmisscnt++; |
381 | 380 | ||
382 | if (sc->beacon.bmisscnt < BSTUCK_THRESH) { | 381 | if (sc->beacon.bmisscnt < BSTUCK_THRESH) { |
383 | ath_print(common, ATH_DBG_BSTUCK, | 382 | ath_dbg(common, ATH_DBG_BSTUCK, |
384 | "missed %u consecutive beacons\n", | 383 | "missed %u consecutive beacons\n", |
385 | sc->beacon.bmisscnt); | 384 | sc->beacon.bmisscnt); |
386 | ath9k_hw_bstuck_nfcal(ah); | 385 | ath9k_hw_bstuck_nfcal(ah); |
387 | } else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) { | 386 | } else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) { |
388 | ath_print(common, ATH_DBG_BSTUCK, | 387 | ath_dbg(common, ATH_DBG_BSTUCK, |
389 | "beacon is officially stuck\n"); | 388 | "beacon is officially stuck\n"); |
390 | sc->sc_flags |= SC_OP_TSF_RESET; | 389 | sc->sc_flags |= SC_OP_TSF_RESET; |
391 | ath_reset(sc, true); | 390 | ath_reset(sc, true); |
392 | } | 391 | } |
@@ -395,9 +394,9 @@ void ath_beacon_tasklet(unsigned long data) | |||
395 | } | 394 | } |
396 | 395 | ||
397 | if (sc->beacon.bmisscnt != 0) { | 396 | if (sc->beacon.bmisscnt != 0) { |
398 | ath_print(common, ATH_DBG_BSTUCK, | 397 | ath_dbg(common, ATH_DBG_BSTUCK, |
399 | "resume beacon xmit after %u misses\n", | 398 | "resume beacon xmit after %u misses\n", |
400 | sc->beacon.bmisscnt); | 399 | sc->beacon.bmisscnt); |
401 | sc->beacon.bmisscnt = 0; | 400 | sc->beacon.bmisscnt = 0; |
402 | } | 401 | } |
403 | 402 | ||
@@ -423,9 +422,9 @@ void ath_beacon_tasklet(unsigned long data) | |||
423 | vif = sc->beacon.bslot[slot]; | 422 | vif = sc->beacon.bslot[slot]; |
424 | aphy = sc->beacon.bslot_aphy[slot]; | 423 | aphy = sc->beacon.bslot_aphy[slot]; |
425 | 424 | ||
426 | ath_print(common, ATH_DBG_BEACON, | 425 | ath_dbg(common, ATH_DBG_BEACON, |
427 | "slot %d [tsf %llu tsftu %u intval %u] vif %p\n", | 426 | "slot %d [tsf %llu tsftu %u intval %u] vif %p\n", |
428 | slot, tsf, tsftu, intval, vif); | 427 | slot, tsf, tsftu, intval, vif); |
429 | 428 | ||
430 | bfaddr = 0; | 429 | bfaddr = 0; |
431 | if (vif) { | 430 | if (vif) { |
@@ -554,8 +553,8 @@ static void ath_beacon_config_sta(struct ath_softc *sc, | |||
554 | 553 | ||
555 | /* No need to configure beacon if we are not associated */ | 554 | /* No need to configure beacon if we are not associated */ |
556 | if (!common->curaid) { | 555 | if (!common->curaid) { |
557 | ath_print(common, ATH_DBG_BEACON, | 556 | ath_dbg(common, ATH_DBG_BEACON, |
558 | "STA is not yet associated..skipping beacon config\n"); | 557 | "STA is not yet associated..skipping beacon config\n"); |
559 | return; | 558 | return; |
560 | } | 559 | } |
561 | 560 | ||
@@ -648,11 +647,11 @@ static void ath_beacon_config_sta(struct ath_softc *sc, | |||
648 | /* TSF out of range threshold fixed at 1 second */ | 647 | /* TSF out of range threshold fixed at 1 second */ |
649 | bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD; | 648 | bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD; |
650 | 649 | ||
651 | ath_print(common, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu); | 650 | ath_dbg(common, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu); |
652 | ath_print(common, ATH_DBG_BEACON, | 651 | ath_dbg(common, ATH_DBG_BEACON, |
653 | "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n", | 652 | "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n", |
654 | bs.bs_bmissthreshold, bs.bs_sleepduration, | 653 | bs.bs_bmissthreshold, bs.bs_sleepduration, |
655 | bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext); | 654 | bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext); |
656 | 655 | ||
657 | /* Set the computed STA beacon timers */ | 656 | /* Set the computed STA beacon timers */ |
658 | 657 | ||
@@ -688,9 +687,9 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc, | |||
688 | nexttbtt += intval; | 687 | nexttbtt += intval; |
689 | } while (nexttbtt < tsftu); | 688 | } while (nexttbtt < tsftu); |
690 | 689 | ||
691 | ath_print(common, ATH_DBG_BEACON, | 690 | ath_dbg(common, ATH_DBG_BEACON, |
692 | "IBSS nexttbtt %u intval %u (%u)\n", | 691 | "IBSS nexttbtt %u intval %u (%u)\n", |
693 | nexttbtt, intval, conf->beacon_interval); | 692 | nexttbtt, intval, conf->beacon_interval); |
694 | 693 | ||
695 | /* | 694 | /* |
696 | * In IBSS mode enable the beacon timers but only enable SWBA interrupts | 695 | * In IBSS mode enable the beacon timers but only enable SWBA interrupts |
@@ -753,8 +752,8 @@ void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif) | |||
753 | ath_beacon_config_sta(sc, cur_conf); | 752 | ath_beacon_config_sta(sc, cur_conf); |
754 | break; | 753 | break; |
755 | default: | 754 | default: |
756 | ath_print(common, ATH_DBG_CONFIG, | 755 | ath_dbg(common, ATH_DBG_CONFIG, |
757 | "Unsupported beaconing mode\n"); | 756 | "Unsupported beaconing mode\n"); |
758 | return; | 757 | return; |
759 | } | 758 | } |
760 | 759 | ||
diff --git a/drivers/net/wireless/ath/ath9k/calib.c b/drivers/net/wireless/ath/ath9k/calib.c index 6d509484b5f..b68a1acbddd 100644 --- a/drivers/net/wireless/ath/ath9k/calib.c +++ b/drivers/net/wireless/ath/ath9k/calib.c | |||
@@ -97,12 +97,12 @@ static void ath9k_hw_update_nfcal_hist_buffer(struct ath_hw *ah, | |||
97 | if (h[i].privNF > limit->max) { | 97 | if (h[i].privNF > limit->max) { |
98 | high_nf_mid = true; | 98 | high_nf_mid = true; |
99 | 99 | ||
100 | ath_print(common, ATH_DBG_CALIBRATE, | 100 | ath_dbg(common, ATH_DBG_CALIBRATE, |
101 | "NFmid[%d] (%d) > MAX (%d), %s\n", | 101 | "NFmid[%d] (%d) > MAX (%d), %s\n", |
102 | i, h[i].privNF, limit->max, | 102 | i, h[i].privNF, limit->max, |
103 | (cal->nfcal_interference ? | 103 | (cal->nfcal_interference ? |
104 | "not corrected (due to interference)" : | 104 | "not corrected (due to interference)" : |
105 | "correcting to MAX")); | 105 | "correcting to MAX")); |
106 | 106 | ||
107 | /* | 107 | /* |
108 | * Normally we limit the average noise floor by the | 108 | * Normally we limit the average noise floor by the |
@@ -180,18 +180,18 @@ bool ath9k_hw_reset_calvalid(struct ath_hw *ah) | |||
180 | return true; | 180 | return true; |
181 | 181 | ||
182 | if (currCal->calState != CAL_DONE) { | 182 | if (currCal->calState != CAL_DONE) { |
183 | ath_print(common, ATH_DBG_CALIBRATE, | 183 | ath_dbg(common, ATH_DBG_CALIBRATE, |
184 | "Calibration state incorrect, %d\n", | 184 | "Calibration state incorrect, %d\n", |
185 | currCal->calState); | 185 | currCal->calState); |
186 | return true; | 186 | return true; |
187 | } | 187 | } |
188 | 188 | ||
189 | if (!(ah->supp_cals & currCal->calData->calType)) | 189 | if (!(ah->supp_cals & currCal->calData->calType)) |
190 | return true; | 190 | return true; |
191 | 191 | ||
192 | ath_print(common, ATH_DBG_CALIBRATE, | 192 | ath_dbg(common, ATH_DBG_CALIBRATE, |
193 | "Resetting Cal %d state for channel %u\n", | 193 | "Resetting Cal %d state for channel %u\n", |
194 | currCal->calData->calType, conf->channel->center_freq); | 194 | currCal->calData->calType, conf->channel->center_freq); |
195 | 195 | ||
196 | ah->caldata->CalValid &= ~currCal->calData->calType; | 196 | ah->caldata->CalValid &= ~currCal->calData->calType; |
197 | currCal->calState = CAL_WAITING; | 197 | currCal->calState = CAL_WAITING; |
@@ -279,9 +279,9 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan) | |||
279 | * noisefloor until the next calibration timer. | 279 | * noisefloor until the next calibration timer. |
280 | */ | 280 | */ |
281 | if (j == 1000) { | 281 | if (j == 1000) { |
282 | ath_print(common, ATH_DBG_ANY, "Timeout while waiting for nf " | 282 | ath_dbg(common, ATH_DBG_ANY, |
283 | "to load: AR_PHY_AGC_CONTROL=0x%x\n", | 283 | "Timeout while waiting for nf to load: AR_PHY_AGC_CONTROL=0x%x\n", |
284 | REG_READ(ah, AR_PHY_AGC_CONTROL)); | 284 | REG_READ(ah, AR_PHY_AGC_CONTROL)); |
285 | return; | 285 | return; |
286 | } | 286 | } |
287 | 287 | ||
@@ -318,19 +318,19 @@ static void ath9k_hw_nf_sanitize(struct ath_hw *ah, s16 *nf) | |||
318 | if (!nf[i]) | 318 | if (!nf[i]) |
319 | continue; | 319 | continue; |
320 | 320 | ||
321 | ath_print(common, ATH_DBG_CALIBRATE, | 321 | ath_dbg(common, ATH_DBG_CALIBRATE, |
322 | "NF calibrated [%s] [chain %d] is %d\n", | 322 | "NF calibrated [%s] [chain %d] is %d\n", |
323 | (i >= 3 ? "ext" : "ctl"), i % 3, nf[i]); | 323 | (i >= 3 ? "ext" : "ctl"), i % 3, nf[i]); |
324 | 324 | ||
325 | if (nf[i] > ATH9K_NF_TOO_HIGH) { | 325 | if (nf[i] > ATH9K_NF_TOO_HIGH) { |
326 | ath_print(common, ATH_DBG_CALIBRATE, | 326 | ath_dbg(common, ATH_DBG_CALIBRATE, |
327 | "NF[%d] (%d) > MAX (%d), correcting to MAX", | 327 | "NF[%d] (%d) > MAX (%d), correcting to MAX\n", |
328 | i, nf[i], ATH9K_NF_TOO_HIGH); | 328 | i, nf[i], ATH9K_NF_TOO_HIGH); |
329 | nf[i] = limit->max; | 329 | nf[i] = limit->max; |
330 | } else if (nf[i] < limit->min) { | 330 | } else if (nf[i] < limit->min) { |
331 | ath_print(common, ATH_DBG_CALIBRATE, | 331 | ath_dbg(common, ATH_DBG_CALIBRATE, |
332 | "NF[%d] (%d) < MIN (%d), correcting to NOM", | 332 | "NF[%d] (%d) < MIN (%d), correcting to NOM\n", |
333 | i, nf[i], limit->min); | 333 | i, nf[i], limit->min); |
334 | nf[i] = limit->nominal; | 334 | nf[i] = limit->nominal; |
335 | } | 335 | } |
336 | } | 336 | } |
@@ -347,8 +347,8 @@ bool ath9k_hw_getnf(struct ath_hw *ah, struct ath9k_channel *chan) | |||
347 | 347 | ||
348 | chan->channelFlags &= (~CHANNEL_CW_INT); | 348 | chan->channelFlags &= (~CHANNEL_CW_INT); |
349 | if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { | 349 | if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { |
350 | ath_print(common, ATH_DBG_CALIBRATE, | 350 | ath_dbg(common, ATH_DBG_CALIBRATE, |
351 | "NF did not complete in calibration window\n"); | 351 | "NF did not complete in calibration window\n"); |
352 | return false; | 352 | return false; |
353 | } | 353 | } |
354 | 354 | ||
@@ -357,10 +357,9 @@ bool ath9k_hw_getnf(struct ath_hw *ah, struct ath9k_channel *chan) | |||
357 | nf = nfarray[0]; | 357 | nf = nfarray[0]; |
358 | if (ath9k_hw_get_nf_thresh(ah, c->band, &nfThresh) | 358 | if (ath9k_hw_get_nf_thresh(ah, c->band, &nfThresh) |
359 | && nf > nfThresh) { | 359 | && nf > nfThresh) { |
360 | ath_print(common, ATH_DBG_CALIBRATE, | 360 | ath_dbg(common, ATH_DBG_CALIBRATE, |
361 | "noise floor failed detected; " | 361 | "noise floor failed detected; detected %d, threshold %d\n", |
362 | "detected %d, threshold %d\n", | 362 | nf, nfThresh); |
363 | nf, nfThresh); | ||
364 | chan->channelFlags |= CHANNEL_CW_INT; | 363 | chan->channelFlags |= CHANNEL_CW_INT; |
365 | } | 364 | } |
366 | 365 | ||
diff --git a/drivers/net/wireless/ath/ath9k/common.c b/drivers/net/wireless/ath/ath9k/common.c index 48b07c319a7..df1998d4825 100644 --- a/drivers/net/wireless/ath/ath9k/common.c +++ b/drivers/net/wireless/ath/ath9k/common.c | |||
@@ -180,8 +180,8 @@ void ath9k_cmn_btcoex_bt_stomp(struct ath_common *common, | |||
180 | AR_STOMP_NONE_WLAN_WGHT); | 180 | AR_STOMP_NONE_WLAN_WGHT); |
181 | break; | 181 | break; |
182 | default: | 182 | default: |
183 | ath_print(common, ATH_DBG_BTCOEX, | 183 | ath_dbg(common, ATH_DBG_BTCOEX, |
184 | "Invalid Stomptype\n"); | 184 | "Invalid Stomptype\n"); |
185 | break; | 185 | break; |
186 | } | 186 | } |
187 | 187 | ||
diff --git a/drivers/net/wireless/ath/ath9k/common.h b/drivers/net/wireless/ath/ath9k/common.h index 4c04ee85ff0..a126bddebb0 100644 --- a/drivers/net/wireless/ath/ath9k/common.h +++ b/drivers/net/wireless/ath/ath9k/common.h | |||
@@ -17,7 +17,6 @@ | |||
17 | #include <net/mac80211.h> | 17 | #include <net/mac80211.h> |
18 | 18 | ||
19 | #include "../ath.h" | 19 | #include "../ath.h" |
20 | #include "../debug.h" | ||
21 | 20 | ||
22 | #include "hw.h" | 21 | #include "hw.h" |
23 | #include "hw-ops.h" | 22 | #include "hw-ops.h" |
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.c b/drivers/net/wireless/ath/ath9k/eeprom.c index 2bbf94d0191..fda533cfd88 100644 --- a/drivers/net/wireless/ath/ath9k/eeprom.c +++ b/drivers/net/wireless/ath/ath9k/eeprom.c | |||
@@ -273,8 +273,8 @@ void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah) | |||
273 | regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN; | 273 | regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN; |
274 | break; | 274 | break; |
275 | default: | 275 | default: |
276 | ath_print(common, ATH_DBG_EEPROM, | 276 | ath_dbg(common, ATH_DBG_EEPROM, |
277 | "Invalid chainmask configuration\n"); | 277 | "Invalid chainmask configuration\n"); |
278 | break; | 278 | break; |
279 | } | 279 | } |
280 | } | 280 | } |
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_4k.c b/drivers/net/wireless/ath/ath9k/eeprom_4k.c index f74692da24d..939fc7af86f 100644 --- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c +++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c | |||
@@ -37,14 +37,14 @@ static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah) | |||
37 | eep_start_loc = 64; | 37 | eep_start_loc = 64; |
38 | 38 | ||
39 | if (!ath9k_hw_use_flash(ah)) { | 39 | if (!ath9k_hw_use_flash(ah)) { |
40 | ath_print(common, ATH_DBG_EEPROM, | 40 | ath_dbg(common, ATH_DBG_EEPROM, |
41 | "Reading from EEPROM, not flash\n"); | 41 | "Reading from EEPROM, not flash\n"); |
42 | } | 42 | } |
43 | 43 | ||
44 | for (addr = 0; addr < SIZE_EEPROM_4K; addr++) { | 44 | for (addr = 0; addr < SIZE_EEPROM_4K; addr++) { |
45 | if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, eep_data)) { | 45 | if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, eep_data)) { |
46 | ath_print(common, ATH_DBG_EEPROM, | 46 | ath_dbg(common, ATH_DBG_EEPROM, |
47 | "Unable to read eeprom region\n"); | 47 | "Unable to read eeprom region\n"); |
48 | return false; | 48 | return false; |
49 | } | 49 | } |
50 | eep_data++; | 50 | eep_data++; |
@@ -73,8 +73,8 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) | |||
73 | return false; | 73 | return false; |
74 | } | 74 | } |
75 | 75 | ||
76 | ath_print(common, ATH_DBG_EEPROM, | 76 | ath_dbg(common, ATH_DBG_EEPROM, |
77 | "Read Magic = 0x%04X\n", magic); | 77 | "Read Magic = 0x%04X\n", magic); |
78 | 78 | ||
79 | if (magic != AR5416_EEPROM_MAGIC) { | 79 | if (magic != AR5416_EEPROM_MAGIC) { |
80 | magic2 = swab16(magic); | 80 | magic2 = swab16(magic); |
@@ -90,14 +90,14 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) | |||
90 | } | 90 | } |
91 | } else { | 91 | } else { |
92 | ath_err(common, | 92 | ath_err(common, |
93 | "Invalid EEPROM Magic. endianness mismatch.\n"); | 93 | "Invalid EEPROM Magic. Endianness mismatch.\n"); |
94 | return -EINVAL; | 94 | return -EINVAL; |
95 | } | 95 | } |
96 | } | 96 | } |
97 | } | 97 | } |
98 | 98 | ||
99 | ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n", | 99 | ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n", |
100 | need_swap ? "True" : "False"); | 100 | need_swap ? "True" : "False"); |
101 | 101 | ||
102 | if (need_swap) | 102 | if (need_swap) |
103 | el = swab16(ah->eeprom.map4k.baseEepHeader.length); | 103 | el = swab16(ah->eeprom.map4k.baseEepHeader.length); |
@@ -118,8 +118,8 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) | |||
118 | u32 integer; | 118 | u32 integer; |
119 | u16 word; | 119 | u16 word; |
120 | 120 | ||
121 | ath_print(common, ATH_DBG_EEPROM, | 121 | ath_dbg(common, ATH_DBG_EEPROM, |
122 | "EEPROM Endianness is not native.. Changing\n"); | 122 | "EEPROM Endianness is not native.. Changing\n"); |
123 | 123 | ||
124 | word = swab16(eep->baseEepHeader.length); | 124 | word = swab16(eep->baseEepHeader.length); |
125 | eep->baseEepHeader.length = word; | 125 | eep->baseEepHeader.length = word; |
@@ -485,21 +485,20 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah, | |||
485 | ((pdadcValues[4 * j + 3] & 0xFF) << 24); | 485 | ((pdadcValues[4 * j + 3] & 0xFF) << 24); |
486 | REG_WRITE(ah, regOffset, reg32); | 486 | REG_WRITE(ah, regOffset, reg32); |
487 | 487 | ||
488 | ath_print(common, ATH_DBG_EEPROM, | 488 | ath_dbg(common, ATH_DBG_EEPROM, |
489 | "PDADC (%d,%4x): %4.4x %8.8x\n", | 489 | "PDADC (%d,%4x): %4.4x %8.8x\n", |
490 | i, regChainOffset, regOffset, | 490 | i, regChainOffset, regOffset, |
491 | reg32); | 491 | reg32); |
492 | ath_print(common, ATH_DBG_EEPROM, | 492 | ath_dbg(common, ATH_DBG_EEPROM, |
493 | "PDADC: Chain %d | " | 493 | "PDADC: Chain %d | " |
494 | "PDADC %3d Value %3d | " | 494 | "PDADC %3d Value %3d | " |
495 | "PDADC %3d Value %3d | " | 495 | "PDADC %3d Value %3d | " |
496 | "PDADC %3d Value %3d | " | 496 | "PDADC %3d Value %3d | " |
497 | "PDADC %3d Value %3d |\n", | 497 | "PDADC %3d Value %3d |\n", |
498 | i, 4 * j, pdadcValues[4 * j], | 498 | i, 4 * j, pdadcValues[4 * j], |
499 | 4 * j + 1, pdadcValues[4 * j + 1], | 499 | 4 * j + 1, pdadcValues[4 * j + 1], |
500 | 4 * j + 2, pdadcValues[4 * j + 2], | 500 | 4 * j + 2, pdadcValues[4 * j + 2], |
501 | 4 * j + 3, | 501 | 4 * j + 3, pdadcValues[4 * j + 3]); |
502 | pdadcValues[4 * j + 3]); | ||
503 | 502 | ||
504 | regOffset += 4; | 503 | regOffset += 4; |
505 | } | 504 | } |
@@ -1178,17 +1177,17 @@ static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz) | |||
1178 | 1177 | ||
1179 | u16 spur_val = AR_NO_SPUR; | 1178 | u16 spur_val = AR_NO_SPUR; |
1180 | 1179 | ||
1181 | ath_print(common, ATH_DBG_ANI, | 1180 | ath_dbg(common, ATH_DBG_ANI, |
1182 | "Getting spur idx %d is2Ghz. %d val %x\n", | 1181 | "Getting spur idx:%d is2Ghz:%d val:%x\n", |
1183 | i, is2GHz, ah->config.spurchans[i][is2GHz]); | 1182 | i, is2GHz, ah->config.spurchans[i][is2GHz]); |
1184 | 1183 | ||
1185 | switch (ah->config.spurmode) { | 1184 | switch (ah->config.spurmode) { |
1186 | case SPUR_DISABLE: | 1185 | case SPUR_DISABLE: |
1187 | break; | 1186 | break; |
1188 | case SPUR_ENABLE_IOCTL: | 1187 | case SPUR_ENABLE_IOCTL: |
1189 | spur_val = ah->config.spurchans[i][is2GHz]; | 1188 | spur_val = ah->config.spurchans[i][is2GHz]; |
1190 | ath_print(common, ATH_DBG_ANI, | 1189 | ath_dbg(common, ATH_DBG_ANI, |
1191 | "Getting spur val from new loc. %d\n", spur_val); | 1190 | "Getting spur val from new loc. %d\n", spur_val); |
1192 | break; | 1191 | break; |
1193 | case SPUR_ENABLE_EEPROM: | 1192 | case SPUR_ENABLE_EEPROM: |
1194 | spur_val = EEP_MAP4K_SPURCHAN; | 1193 | spur_val = EEP_MAP4K_SPURCHAN; |
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_9287.c b/drivers/net/wireless/ath/ath9k/eeprom_9287.c index 9308b684eaa..9ec4bc80f75 100644 --- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c +++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c | |||
@@ -43,15 +43,15 @@ static bool ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah) | |||
43 | eep_start_loc = AR9287_HTC_EEP_START_LOC; | 43 | eep_start_loc = AR9287_HTC_EEP_START_LOC; |
44 | 44 | ||
45 | if (!ath9k_hw_use_flash(ah)) { | 45 | if (!ath9k_hw_use_flash(ah)) { |
46 | ath_print(common, ATH_DBG_EEPROM, | 46 | ath_dbg(common, ATH_DBG_EEPROM, |
47 | "Reading from EEPROM, not flash\n"); | 47 | "Reading from EEPROM, not flash\n"); |
48 | } | 48 | } |
49 | 49 | ||
50 | for (addr = 0; addr < NUM_EEP_WORDS; addr++) { | 50 | for (addr = 0; addr < NUM_EEP_WORDS; addr++) { |
51 | if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, | 51 | if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, |
52 | eep_data)) { | 52 | eep_data)) { |
53 | ath_print(common, ATH_DBG_EEPROM, | 53 | ath_dbg(common, ATH_DBG_EEPROM, |
54 | "Unable to read eeprom region\n"); | 54 | "Unable to read eeprom region\n"); |
55 | return false; | 55 | return false; |
56 | } | 56 | } |
57 | eep_data++; | 57 | eep_data++; |
@@ -76,8 +76,8 @@ static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah) | |||
76 | return false; | 76 | return false; |
77 | } | 77 | } |
78 | 78 | ||
79 | ath_print(common, ATH_DBG_EEPROM, | 79 | ath_dbg(common, ATH_DBG_EEPROM, |
80 | "Read Magic = 0x%04X\n", magic); | 80 | "Read Magic = 0x%04X\n", magic); |
81 | 81 | ||
82 | if (magic != AR5416_EEPROM_MAGIC) { | 82 | if (magic != AR5416_EEPROM_MAGIC) { |
83 | magic2 = swab16(magic); | 83 | magic2 = swab16(magic); |
@@ -99,8 +99,8 @@ static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah) | |||
99 | } | 99 | } |
100 | } | 100 | } |
101 | 101 | ||
102 | ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n", | 102 | ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n", |
103 | need_swap ? "True" : "False"); | 103 | need_swap ? "True" : "False"); |
104 | 104 | ||
105 | if (need_swap) | 105 | if (need_swap) |
106 | el = swab16(ah->eeprom.map9287.baseEepHeader.length); | 106 | el = swab16(ah->eeprom.map9287.baseEepHeader.length); |
@@ -1149,17 +1149,17 @@ static u16 ath9k_hw_ar9287_get_spur_channel(struct ath_hw *ah, | |||
1149 | struct ath_common *common = ath9k_hw_common(ah); | 1149 | struct ath_common *common = ath9k_hw_common(ah); |
1150 | u16 spur_val = AR_NO_SPUR; | 1150 | u16 spur_val = AR_NO_SPUR; |
1151 | 1151 | ||
1152 | ath_print(common, ATH_DBG_ANI, | 1152 | ath_dbg(common, ATH_DBG_ANI, |
1153 | "Getting spur idx %d is2Ghz. %d val %x\n", | 1153 | "Getting spur idx:%d is2Ghz:%d val:%x\n", |
1154 | i, is2GHz, ah->config.spurchans[i][is2GHz]); | 1154 | i, is2GHz, ah->config.spurchans[i][is2GHz]); |
1155 | 1155 | ||
1156 | switch (ah->config.spurmode) { | 1156 | switch (ah->config.spurmode) { |
1157 | case SPUR_DISABLE: | 1157 | case SPUR_DISABLE: |
1158 | break; | 1158 | break; |
1159 | case SPUR_ENABLE_IOCTL: | 1159 | case SPUR_ENABLE_IOCTL: |
1160 | spur_val = ah->config.spurchans[i][is2GHz]; | 1160 | spur_val = ah->config.spurchans[i][is2GHz]; |
1161 | ath_print(common, ATH_DBG_ANI, | 1161 | ath_dbg(common, ATH_DBG_ANI, |
1162 | "Getting spur val from new loc. %d\n", spur_val); | 1162 | "Getting spur val from new loc. %d\n", spur_val); |
1163 | break; | 1163 | break; |
1164 | case SPUR_ENABLE_EEPROM: | 1164 | case SPUR_ENABLE_EEPROM: |
1165 | spur_val = EEP_MAP9287_SPURCHAN; | 1165 | spur_val = EEP_MAP9287_SPURCHAN; |
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_def.c b/drivers/net/wireless/ath/ath9k/eeprom_def.c index 864a877bc05..c2b4bba7410 100644 --- a/drivers/net/wireless/ath/ath9k/eeprom_def.c +++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c | |||
@@ -122,8 +122,8 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah) | |||
122 | } | 122 | } |
123 | 123 | ||
124 | if (!ath9k_hw_use_flash(ah)) { | 124 | if (!ath9k_hw_use_flash(ah)) { |
125 | ath_print(common, ATH_DBG_EEPROM, | 125 | ath_dbg(common, ATH_DBG_EEPROM, |
126 | "Read Magic = 0x%04X\n", magic); | 126 | "Read Magic = 0x%04X\n", magic); |
127 | 127 | ||
128 | if (magic != AR5416_EEPROM_MAGIC) { | 128 | if (magic != AR5416_EEPROM_MAGIC) { |
129 | magic2 = swab16(magic); | 129 | magic2 = swab16(magic); |
@@ -146,8 +146,8 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah) | |||
146 | } | 146 | } |
147 | } | 147 | } |
148 | 148 | ||
149 | ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n", | 149 | ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n", |
150 | need_swap ? "True" : "False"); | 150 | need_swap ? "True" : "False"); |
151 | 151 | ||
152 | if (need_swap) | 152 | if (need_swap) |
153 | el = swab16(ah->eeprom.def.baseEepHeader.length); | 153 | el = swab16(ah->eeprom.def.baseEepHeader.length); |
@@ -168,8 +168,8 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah) | |||
168 | u32 integer, j; | 168 | u32 integer, j; |
169 | u16 word; | 169 | u16 word; |
170 | 170 | ||
171 | ath_print(common, ATH_DBG_EEPROM, | 171 | ath_dbg(common, ATH_DBG_EEPROM, |
172 | "EEPROM Endianness is not native.. Changing.\n"); | 172 | "EEPROM Endianness is not native.. Changing.\n"); |
173 | 173 | ||
174 | word = swab16(eep->baseEepHeader.length); | 174 | word = swab16(eep->baseEepHeader.length); |
175 | eep->baseEepHeader.length = word; | 175 | eep->baseEepHeader.length = word; |
@@ -964,20 +964,19 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah, | |||
964 | ((pdadcValues[4 * j + 3] & 0xFF) << 24); | 964 | ((pdadcValues[4 * j + 3] & 0xFF) << 24); |
965 | REG_WRITE(ah, regOffset, reg32); | 965 | REG_WRITE(ah, regOffset, reg32); |
966 | 966 | ||
967 | ath_print(common, ATH_DBG_EEPROM, | 967 | ath_dbg(common, ATH_DBG_EEPROM, |
968 | "PDADC (%d,%4x): %4.4x %8.8x\n", | 968 | "PDADC (%d,%4x): %4.4x %8.8x\n", |
969 | i, regChainOffset, regOffset, | 969 | i, regChainOffset, regOffset, |
970 | reg32); | 970 | reg32); |
971 | ath_print(common, ATH_DBG_EEPROM, | 971 | ath_dbg(common, ATH_DBG_EEPROM, |
972 | "PDADC: Chain %d | PDADC %3d " | 972 | "PDADC: Chain %d | PDADC %3d " |
973 | "Value %3d | PDADC %3d Value %3d | " | 973 | "Value %3d | PDADC %3d Value %3d | " |
974 | "PDADC %3d Value %3d | PDADC %3d " | 974 | "PDADC %3d Value %3d | PDADC %3d " |
975 | "Value %3d |\n", | 975 | "Value %3d |\n", |
976 | i, 4 * j, pdadcValues[4 * j], | 976 | i, 4 * j, pdadcValues[4 * j], |
977 | 4 * j + 1, pdadcValues[4 * j + 1], | 977 | 4 * j + 1, pdadcValues[4 * j + 1], |
978 | 4 * j + 2, pdadcValues[4 * j + 2], | 978 | 4 * j + 2, pdadcValues[4 * j + 2], |
979 | 4 * j + 3, | 979 | 4 * j + 3, pdadcValues[4 * j + 3]); |
980 | pdadcValues[4 * j + 3]); | ||
981 | 980 | ||
982 | regOffset += 4; | 981 | regOffset += 4; |
983 | } | 982 | } |
@@ -1317,8 +1316,8 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah, | |||
1317 | regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN; | 1316 | regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN; |
1318 | break; | 1317 | break; |
1319 | default: | 1318 | default: |
1320 | ath_print(ath9k_hw_common(ah), ATH_DBG_EEPROM, | 1319 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_EEPROM, |
1321 | "Invalid chainmask configuration\n"); | 1320 | "Invalid chainmask configuration\n"); |
1322 | break; | 1321 | break; |
1323 | } | 1322 | } |
1324 | 1323 | ||
@@ -1459,17 +1458,17 @@ static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz) | |||
1459 | 1458 | ||
1460 | u16 spur_val = AR_NO_SPUR; | 1459 | u16 spur_val = AR_NO_SPUR; |
1461 | 1460 | ||
1462 | ath_print(common, ATH_DBG_ANI, | 1461 | ath_dbg(common, ATH_DBG_ANI, |
1463 | "Getting spur idx %d is2Ghz. %d val %x\n", | 1462 | "Getting spur idx:%d is2Ghz:%d val:%x\n", |
1464 | i, is2GHz, ah->config.spurchans[i][is2GHz]); | 1463 | i, is2GHz, ah->config.spurchans[i][is2GHz]); |
1465 | 1464 | ||
1466 | switch (ah->config.spurmode) { | 1465 | switch (ah->config.spurmode) { |
1467 | case SPUR_DISABLE: | 1466 | case SPUR_DISABLE: |
1468 | break; | 1467 | break; |
1469 | case SPUR_ENABLE_IOCTL: | 1468 | case SPUR_ENABLE_IOCTL: |
1470 | spur_val = ah->config.spurchans[i][is2GHz]; | 1469 | spur_val = ah->config.spurchans[i][is2GHz]; |
1471 | ath_print(common, ATH_DBG_ANI, | 1470 | ath_dbg(common, ATH_DBG_ANI, |
1472 | "Getting spur val from new loc. %d\n", spur_val); | 1471 | "Getting spur val from new loc. %d\n", spur_val); |
1473 | break; | 1472 | break; |
1474 | case SPUR_ENABLE_EEPROM: | 1473 | case SPUR_ENABLE_EEPROM: |
1475 | spur_val = EEP_DEF_SPURCHAN; | 1474 | spur_val = EEP_DEF_SPURCHAN; |
diff --git a/drivers/net/wireless/ath/ath9k/gpio.c b/drivers/net/wireless/ath/ath9k/gpio.c index 2b1b5830666..13376406924 100644 --- a/drivers/net/wireless/ath/ath9k/gpio.c +++ b/drivers/net/wireless/ath/ath9k/gpio.c | |||
@@ -236,13 +236,13 @@ static void ath_detect_bt_priority(struct ath_softc *sc) | |||
236 | sc->sc_flags &= ~(SC_OP_BT_PRIORITY_DETECTED | SC_OP_BT_SCAN); | 236 | sc->sc_flags &= ~(SC_OP_BT_PRIORITY_DETECTED | SC_OP_BT_SCAN); |
237 | /* Detect if colocated bt started scanning */ | 237 | /* Detect if colocated bt started scanning */ |
238 | if (btcoex->bt_priority_cnt >= ATH_BT_CNT_SCAN_THRESHOLD) { | 238 | if (btcoex->bt_priority_cnt >= ATH_BT_CNT_SCAN_THRESHOLD) { |
239 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX, | 239 | ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX, |
240 | "BT scan detected"); | 240 | "BT scan detected\n"); |
241 | sc->sc_flags |= (SC_OP_BT_SCAN | | 241 | sc->sc_flags |= (SC_OP_BT_SCAN | |
242 | SC_OP_BT_PRIORITY_DETECTED); | 242 | SC_OP_BT_PRIORITY_DETECTED); |
243 | } else if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) { | 243 | } else if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) { |
244 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX, | 244 | ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX, |
245 | "BT priority traffic detected"); | 245 | "BT priority traffic detected\n"); |
246 | sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED; | 246 | sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED; |
247 | } | 247 | } |
248 | 248 | ||
@@ -331,8 +331,8 @@ static void ath_btcoex_no_stomp_timer(void *arg) | |||
331 | struct ath_common *common = ath9k_hw_common(ah); | 331 | struct ath_common *common = ath9k_hw_common(ah); |
332 | bool is_btscan = sc->sc_flags & SC_OP_BT_SCAN; | 332 | bool is_btscan = sc->sc_flags & SC_OP_BT_SCAN; |
333 | 333 | ||
334 | ath_print(common, ATH_DBG_BTCOEX, | 334 | ath_dbg(common, ATH_DBG_BTCOEX, |
335 | "no stomp timer running\n"); | 335 | "no stomp timer running\n"); |
336 | 336 | ||
337 | spin_lock_bh(&btcoex->btcoex_lock); | 337 | spin_lock_bh(&btcoex->btcoex_lock); |
338 | 338 | ||
@@ -378,8 +378,8 @@ void ath9k_btcoex_timer_resume(struct ath_softc *sc) | |||
378 | struct ath_btcoex *btcoex = &sc->btcoex; | 378 | struct ath_btcoex *btcoex = &sc->btcoex; |
379 | struct ath_hw *ah = sc->sc_ah; | 379 | struct ath_hw *ah = sc->sc_ah; |
380 | 380 | ||
381 | ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX, | 381 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX, |
382 | "Starting btcoex timers"); | 382 | "Starting btcoex timers\n"); |
383 | 383 | ||
384 | /* make sure duty cycle timer is also stopped when resuming */ | 384 | /* make sure duty cycle timer is also stopped when resuming */ |
385 | if (btcoex->hw_timer_enabled) | 385 | if (btcoex->hw_timer_enabled) |
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c b/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c index dd9514e019e..87cc65a78a3 100644 --- a/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c +++ b/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c | |||
@@ -123,11 +123,11 @@ static void ath9k_htc_beacon_config_sta(struct ath9k_htc_priv *priv, | |||
123 | /* TSF out of range threshold fixed at 1 second */ | 123 | /* TSF out of range threshold fixed at 1 second */ |
124 | bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD; | 124 | bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD; |
125 | 125 | ||
126 | ath_print(common, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu); | 126 | ath_dbg(common, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu); |
127 | ath_print(common, ATH_DBG_BEACON, | 127 | ath_dbg(common, ATH_DBG_BEACON, |
128 | "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n", | 128 | "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n", |
129 | bs.bs_bmissthreshold, bs.bs_sleepduration, | 129 | bs.bs_bmissthreshold, bs.bs_sleepduration, |
130 | bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext); | 130 | bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext); |
131 | 131 | ||
132 | /* Set the computed STA beacon timers */ | 132 | /* Set the computed STA beacon timers */ |
133 | 133 | ||
@@ -154,9 +154,9 @@ static void ath9k_htc_beacon_config_adhoc(struct ath9k_htc_priv *priv, | |||
154 | if (priv->op_flags & OP_ENABLE_BEACON) | 154 | if (priv->op_flags & OP_ENABLE_BEACON) |
155 | imask |= ATH9K_INT_SWBA; | 155 | imask |= ATH9K_INT_SWBA; |
156 | 156 | ||
157 | ath_print(common, ATH_DBG_BEACON, | 157 | ath_dbg(common, ATH_DBG_BEACON, |
158 | "IBSS Beacon config, intval: %d, imask: 0x%x\n", | 158 | "IBSS Beacon config, intval: %d, imask: 0x%x\n", |
159 | bss_conf->beacon_interval, imask); | 159 | bss_conf->beacon_interval, imask); |
160 | 160 | ||
161 | WMI_CMD(WMI_DISABLE_INTR_CMDID); | 161 | WMI_CMD(WMI_DISABLE_INTR_CMDID); |
162 | ath9k_hw_beaconinit(priv->ah, nexttbtt, intval); | 162 | ath9k_hw_beaconinit(priv->ah, nexttbtt, intval); |
@@ -278,8 +278,8 @@ void ath9k_htc_beacon_config(struct ath9k_htc_priv *priv, | |||
278 | ath9k_htc_beacon_config_adhoc(priv, cur_conf); | 278 | ath9k_htc_beacon_config_adhoc(priv, cur_conf); |
279 | break; | 279 | break; |
280 | default: | 280 | default: |
281 | ath_print(common, ATH_DBG_CONFIG, | 281 | ath_dbg(common, ATH_DBG_CONFIG, |
282 | "Unsupported beaconing mode\n"); | 282 | "Unsupported beaconing mode\n"); |
283 | return; | 283 | return; |
284 | } | 284 | } |
285 | } | 285 | } |
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_gpio.c b/drivers/net/wireless/ath/ath9k/htc_drv_gpio.c index 50eec9a3b88..283ff97ed44 100644 --- a/drivers/net/wireless/ath/ath9k/htc_drv_gpio.c +++ b/drivers/net/wireless/ath/ath9k/htc_drv_gpio.c | |||
@@ -20,13 +20,13 @@ static void ath_detect_bt_priority(struct ath9k_htc_priv *priv) | |||
20 | priv->op_flags &= ~(OP_BT_PRIORITY_DETECTED | OP_BT_SCAN); | 20 | priv->op_flags &= ~(OP_BT_PRIORITY_DETECTED | OP_BT_SCAN); |
21 | /* Detect if colocated bt started scanning */ | 21 | /* Detect if colocated bt started scanning */ |
22 | if (btcoex->bt_priority_cnt >= ATH_BT_CNT_SCAN_THRESHOLD) { | 22 | if (btcoex->bt_priority_cnt >= ATH_BT_CNT_SCAN_THRESHOLD) { |
23 | ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX, | 23 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX, |
24 | "BT scan detected"); | 24 | "BT scan detected\n"); |
25 | priv->op_flags |= (OP_BT_SCAN | | 25 | priv->op_flags |= (OP_BT_SCAN | |
26 | OP_BT_PRIORITY_DETECTED); | 26 | OP_BT_PRIORITY_DETECTED); |
27 | } else if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) { | 27 | } else if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) { |
28 | ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX, | 28 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX, |
29 | "BT priority traffic detected"); | 29 | "BT priority traffic detected\n"); |
30 | priv->op_flags |= OP_BT_PRIORITY_DETECTED; | 30 | priv->op_flags |= OP_BT_PRIORITY_DETECTED; |
31 | } | 31 | } |
32 | 32 | ||
@@ -83,8 +83,8 @@ static void ath_btcoex_duty_cycle_work(struct work_struct *work) | |||
83 | struct ath_common *common = ath9k_hw_common(ah); | 83 | struct ath_common *common = ath9k_hw_common(ah); |
84 | bool is_btscan = priv->op_flags & OP_BT_SCAN; | 84 | bool is_btscan = priv->op_flags & OP_BT_SCAN; |
85 | 85 | ||
86 | ath_print(common, ATH_DBG_BTCOEX, | 86 | ath_dbg(common, ATH_DBG_BTCOEX, |
87 | "time slice work for bt and wlan\n"); | 87 | "time slice work for bt and wlan\n"); |
88 | 88 | ||
89 | if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW || is_btscan) | 89 | if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW || is_btscan) |
90 | ath9k_cmn_btcoex_bt_stomp(common, ATH_BTCOEX_STOMP_NONE); | 90 | ath9k_cmn_btcoex_bt_stomp(common, ATH_BTCOEX_STOMP_NONE); |
@@ -114,8 +114,7 @@ void ath_htc_resume_btcoex_work(struct ath9k_htc_priv *priv) | |||
114 | struct ath_btcoex *btcoex = &priv->btcoex; | 114 | struct ath_btcoex *btcoex = &priv->btcoex; |
115 | struct ath_hw *ah = priv->ah; | 115 | struct ath_hw *ah = priv->ah; |
116 | 116 | ||
117 | ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX, | 117 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX, "Starting btcoex work\n"); |
118 | "Starting btcoex work"); | ||
119 | 118 | ||
120 | btcoex->bt_priority_cnt = 0; | 119 | btcoex->bt_priority_cnt = 0; |
121 | btcoex->bt_priority_time = jiffies; | 120 | btcoex->bt_priority_time = jiffies; |
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_init.c b/drivers/net/wireless/ath/ath9k/htc_drv_init.c index 20b32f614c1..f89f6635aba 100644 --- a/drivers/net/wireless/ath/ath9k/htc_drv_init.c +++ b/drivers/net/wireless/ath/ath9k/htc_drv_init.c | |||
@@ -288,9 +288,9 @@ static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset) | |||
288 | (u8 *) &val, sizeof(val), | 288 | (u8 *) &val, sizeof(val), |
289 | 100); | 289 | 100); |
290 | if (unlikely(r)) { | 290 | if (unlikely(r)) { |
291 | ath_print(common, ATH_DBG_WMI, | 291 | ath_dbg(common, ATH_DBG_WMI, |
292 | "REGISTER READ FAILED: (0x%04x, %d)\n", | 292 | "REGISTER READ FAILED: (0x%04x, %d)\n", |
293 | reg_offset, r); | 293 | reg_offset, r); |
294 | return -EIO; | 294 | return -EIO; |
295 | } | 295 | } |
296 | 296 | ||
@@ -313,9 +313,9 @@ static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset) | |||
313 | (u8 *) &val, sizeof(val), | 313 | (u8 *) &val, sizeof(val), |
314 | 100); | 314 | 100); |
315 | if (unlikely(r)) { | 315 | if (unlikely(r)) { |
316 | ath_print(common, ATH_DBG_WMI, | 316 | ath_dbg(common, ATH_DBG_WMI, |
317 | "REGISTER WRITE FAILED:(0x%04x, %d)\n", | 317 | "REGISTER WRITE FAILED:(0x%04x, %d)\n", |
318 | reg_offset, r); | 318 | reg_offset, r); |
319 | } | 319 | } |
320 | } | 320 | } |
321 | 321 | ||
@@ -345,9 +345,9 @@ static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset) | |||
345 | (u8 *) &rsp_status, sizeof(rsp_status), | 345 | (u8 *) &rsp_status, sizeof(rsp_status), |
346 | 100); | 346 | 100); |
347 | if (unlikely(r)) { | 347 | if (unlikely(r)) { |
348 | ath_print(common, ATH_DBG_WMI, | 348 | ath_dbg(common, ATH_DBG_WMI, |
349 | "REGISTER WRITE FAILED, multi len: %d\n", | 349 | "REGISTER WRITE FAILED, multi len: %d\n", |
350 | priv->wmi->multi_write_idx); | 350 | priv->wmi->multi_write_idx); |
351 | } | 351 | } |
352 | priv->wmi->multi_write_idx = 0; | 352 | priv->wmi->multi_write_idx = 0; |
353 | } | 353 | } |
@@ -395,9 +395,9 @@ static void ath9k_regwrite_flush(void *hw_priv) | |||
395 | (u8 *) &rsp_status, sizeof(rsp_status), | 395 | (u8 *) &rsp_status, sizeof(rsp_status), |
396 | 100); | 396 | 100); |
397 | if (unlikely(r)) { | 397 | if (unlikely(r)) { |
398 | ath_print(common, ATH_DBG_WMI, | 398 | ath_dbg(common, ATH_DBG_WMI, |
399 | "REGISTER WRITE FAILED, multi len: %d\n", | 399 | "REGISTER WRITE FAILED, multi len: %d\n", |
400 | priv->wmi->multi_write_idx); | 400 | priv->wmi->multi_write_idx); |
401 | } | 401 | } |
402 | priv->wmi->multi_write_idx = 0; | 402 | priv->wmi->multi_write_idx = 0; |
403 | } | 403 | } |
@@ -469,9 +469,9 @@ static void setup_ht_cap(struct ath9k_htc_priv *priv, | |||
469 | tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, 2); | 469 | tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, 2); |
470 | rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, 2); | 470 | rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, 2); |
471 | 471 | ||
472 | ath_print(common, ATH_DBG_CONFIG, | 472 | ath_dbg(common, ATH_DBG_CONFIG, |
473 | "TX streams %d, RX streams: %d\n", | 473 | "TX streams %d, RX streams: %d\n", |
474 | tx_streams, rx_streams); | 474 | tx_streams, rx_streams); |
475 | 475 | ||
476 | if (tx_streams != rx_streams) { | 476 | if (tx_streams != rx_streams) { |
477 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; | 477 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; |
@@ -537,9 +537,9 @@ static void ath9k_init_crypto(struct ath9k_htc_priv *priv) | |||
537 | /* Get the hardware key cache size. */ | 537 | /* Get the hardware key cache size. */ |
538 | common->keymax = priv->ah->caps.keycache_size; | 538 | common->keymax = priv->ah->caps.keycache_size; |
539 | if (common->keymax > ATH_KEYMAX) { | 539 | if (common->keymax > ATH_KEYMAX) { |
540 | ath_print(common, ATH_DBG_ANY, | 540 | ath_dbg(common, ATH_DBG_ANY, |
541 | "Warning, using only %u entries in %u key cache\n", | 541 | "Warning, using only %u entries in %u key cache\n", |
542 | ATH_KEYMAX, common->keymax); | 542 | ATH_KEYMAX, common->keymax); |
543 | common->keymax = ATH_KEYMAX; | 543 | common->keymax = ATH_KEYMAX; |
544 | } | 544 | } |
545 | 545 | ||
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_main.c b/drivers/net/wireless/ath/ath9k/htc_drv_main.c index a8007af4e14..87731c2daae 100644 --- a/drivers/net/wireless/ath/ath9k/htc_drv_main.c +++ b/drivers/net/wireless/ath/ath9k/htc_drv_main.c | |||
@@ -143,11 +143,11 @@ static int ath9k_htc_set_channel(struct ath9k_htc_priv *priv, | |||
143 | WMI_CMD(WMI_DRAIN_TXQ_ALL_CMDID); | 143 | WMI_CMD(WMI_DRAIN_TXQ_ALL_CMDID); |
144 | WMI_CMD(WMI_STOP_RECV_CMDID); | 144 | WMI_CMD(WMI_STOP_RECV_CMDID); |
145 | 145 | ||
146 | ath_print(common, ATH_DBG_CONFIG, | 146 | ath_dbg(common, ATH_DBG_CONFIG, |
147 | "(%u MHz) -> (%u MHz), HT: %d, HT40: %d fastcc: %d\n", | 147 | "(%u MHz) -> (%u MHz), HT: %d, HT40: %d fastcc: %d\n", |
148 | priv->ah->curchan->channel, | 148 | priv->ah->curchan->channel, |
149 | channel->center_freq, conf_is_ht(conf), conf_is_ht40(conf), | 149 | channel->center_freq, conf_is_ht(conf), conf_is_ht40(conf), |
150 | fastcc); | 150 | fastcc); |
151 | 151 | ||
152 | caldata = &priv->caldata[channel->hw_value]; | 152 | caldata = &priv->caldata[channel->hw_value]; |
153 | ret = ath9k_hw_reset(ah, hchan, caldata, fastcc); | 153 | ret = ath9k_hw_reset(ah, hchan, caldata, fastcc); |
@@ -270,9 +270,9 @@ static int ath9k_htc_add_station(struct ath9k_htc_priv *priv, | |||
270 | } | 270 | } |
271 | 271 | ||
272 | if (sta) | 272 | if (sta) |
273 | ath_print(common, ATH_DBG_CONFIG, | 273 | ath_dbg(common, ATH_DBG_CONFIG, |
274 | "Added a station entry for: %pM (idx: %d)\n", | 274 | "Added a station entry for: %pM (idx: %d)\n", |
275 | sta->addr, tsta.sta_index); | 275 | sta->addr, tsta.sta_index); |
276 | 276 | ||
277 | priv->nstations++; | 277 | priv->nstations++; |
278 | return 0; | 278 | return 0; |
@@ -304,9 +304,9 @@ static int ath9k_htc_remove_station(struct ath9k_htc_priv *priv, | |||
304 | } | 304 | } |
305 | 305 | ||
306 | if (sta) | 306 | if (sta) |
307 | ath_print(common, ATH_DBG_CONFIG, | 307 | ath_dbg(common, ATH_DBG_CONFIG, |
308 | "Removed a station entry for: %pM (idx: %d)\n", | 308 | "Removed a station entry for: %pM (idx: %d)\n", |
309 | sta->addr, sta_idx); | 309 | sta->addr, sta_idx); |
310 | 310 | ||
311 | priv->nstations--; | 311 | priv->nstations--; |
312 | return 0; | 312 | return 0; |
@@ -409,9 +409,9 @@ static void ath9k_htc_init_rate(struct ath9k_htc_priv *priv, | |||
409 | ath9k_htc_setup_rate(priv, sta, &trate); | 409 | ath9k_htc_setup_rate(priv, sta, &trate); |
410 | ret = ath9k_htc_send_rate_cmd(priv, &trate); | 410 | ret = ath9k_htc_send_rate_cmd(priv, &trate); |
411 | if (!ret) | 411 | if (!ret) |
412 | ath_print(common, ATH_DBG_CONFIG, | 412 | ath_dbg(common, ATH_DBG_CONFIG, |
413 | "Updated target sta: %pM, rate caps: 0x%X\n", | 413 | "Updated target sta: %pM, rate caps: 0x%X\n", |
414 | sta->addr, be32_to_cpu(trate.capflags)); | 414 | sta->addr, be32_to_cpu(trate.capflags)); |
415 | } | 415 | } |
416 | 416 | ||
417 | static void ath9k_htc_update_rate(struct ath9k_htc_priv *priv, | 417 | static void ath9k_htc_update_rate(struct ath9k_htc_priv *priv, |
@@ -436,9 +436,9 @@ static void ath9k_htc_update_rate(struct ath9k_htc_priv *priv, | |||
436 | 436 | ||
437 | ret = ath9k_htc_send_rate_cmd(priv, &trate); | 437 | ret = ath9k_htc_send_rate_cmd(priv, &trate); |
438 | if (!ret) | 438 | if (!ret) |
439 | ath_print(common, ATH_DBG_CONFIG, | 439 | ath_dbg(common, ATH_DBG_CONFIG, |
440 | "Updated target sta: %pM, rate caps: 0x%X\n", | 440 | "Updated target sta: %pM, rate caps: 0x%X\n", |
441 | bss_conf->bssid, be32_to_cpu(trate.capflags)); | 441 | bss_conf->bssid, be32_to_cpu(trate.capflags)); |
442 | } | 442 | } |
443 | 443 | ||
444 | static int ath9k_htc_tx_aggr_oper(struct ath9k_htc_priv *priv, | 444 | static int ath9k_htc_tx_aggr_oper(struct ath9k_htc_priv *priv, |
@@ -465,14 +465,14 @@ static int ath9k_htc_tx_aggr_oper(struct ath9k_htc_priv *priv, | |||
465 | 465 | ||
466 | WMI_CMD_BUF(WMI_TX_AGGR_ENABLE_CMDID, &aggr); | 466 | WMI_CMD_BUF(WMI_TX_AGGR_ENABLE_CMDID, &aggr); |
467 | if (ret) | 467 | if (ret) |
468 | ath_print(common, ATH_DBG_CONFIG, | 468 | ath_dbg(common, ATH_DBG_CONFIG, |
469 | "Unable to %s TX aggregation for (%pM, %d)\n", | 469 | "Unable to %s TX aggregation for (%pM, %d)\n", |
470 | (aggr.aggr_enable) ? "start" : "stop", sta->addr, tid); | 470 | (aggr.aggr_enable) ? "start" : "stop", sta->addr, tid); |
471 | else | 471 | else |
472 | ath_print(common, ATH_DBG_CONFIG, | 472 | ath_dbg(common, ATH_DBG_CONFIG, |
473 | "%s TX aggregation for (%pM, %d)\n", | 473 | "%s TX aggregation for (%pM, %d)\n", |
474 | (aggr.aggr_enable) ? "Starting" : "Stopping", | 474 | (aggr.aggr_enable) ? "Starting" : "Stopping", |
475 | sta->addr, tid); | 475 | sta->addr, tid); |
476 | 476 | ||
477 | spin_lock_bh(&priv->tx_lock); | 477 | spin_lock_bh(&priv->tx_lock); |
478 | ista->tid_state[tid] = (aggr.aggr_enable && !ret) ? AGGR_START : AGGR_STOP; | 478 | ista->tid_state[tid] = (aggr.aggr_enable && !ret) ? AGGR_START : AGGR_STOP; |
@@ -725,7 +725,7 @@ void ath9k_ani_work(struct work_struct *work) | |||
725 | /* Long calibration runs independently of short calibration. */ | 725 | /* Long calibration runs independently of short calibration. */ |
726 | if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) { | 726 | if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) { |
727 | longcal = true; | 727 | longcal = true; |
728 | ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies); | 728 | ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies); |
729 | common->ani.longcal_timer = timestamp; | 729 | common->ani.longcal_timer = timestamp; |
730 | } | 730 | } |
731 | 731 | ||
@@ -734,8 +734,8 @@ void ath9k_ani_work(struct work_struct *work) | |||
734 | if ((timestamp - common->ani.shortcal_timer) >= | 734 | if ((timestamp - common->ani.shortcal_timer) >= |
735 | short_cal_interval) { | 735 | short_cal_interval) { |
736 | shortcal = true; | 736 | shortcal = true; |
737 | ath_print(common, ATH_DBG_ANI, | 737 | ath_dbg(common, ATH_DBG_ANI, |
738 | "shortcal @%lu\n", jiffies); | 738 | "shortcal @%lu\n", jiffies); |
739 | common->ani.shortcal_timer = timestamp; | 739 | common->ani.shortcal_timer = timestamp; |
740 | common->ani.resetcal_timer = timestamp; | 740 | common->ani.resetcal_timer = timestamp; |
741 | } | 741 | } |
@@ -1125,15 +1125,15 @@ static int ath9k_htc_tx(struct ieee80211_hw *hw, struct sk_buff *skb) | |||
1125 | ret = ath9k_htc_tx_start(priv, skb); | 1125 | ret = ath9k_htc_tx_start(priv, skb); |
1126 | if (ret != 0) { | 1126 | if (ret != 0) { |
1127 | if (ret == -ENOMEM) { | 1127 | if (ret == -ENOMEM) { |
1128 | ath_print(ath9k_hw_common(priv->ah), ATH_DBG_XMIT, | 1128 | ath_dbg(ath9k_hw_common(priv->ah), ATH_DBG_XMIT, |
1129 | "Stopping TX queues\n"); | 1129 | "Stopping TX queues\n"); |
1130 | ieee80211_stop_queues(hw); | 1130 | ieee80211_stop_queues(hw); |
1131 | spin_lock_bh(&priv->tx_lock); | 1131 | spin_lock_bh(&priv->tx_lock); |
1132 | priv->tx_queues_stop = true; | 1132 | priv->tx_queues_stop = true; |
1133 | spin_unlock_bh(&priv->tx_lock); | 1133 | spin_unlock_bh(&priv->tx_lock); |
1134 | } else { | 1134 | } else { |
1135 | ath_print(ath9k_hw_common(priv->ah), ATH_DBG_XMIT, | 1135 | ath_dbg(ath9k_hw_common(priv->ah), ATH_DBG_XMIT, |
1136 | "Tx failed"); | 1136 | "Tx failed\n"); |
1137 | } | 1137 | } |
1138 | goto fail_tx; | 1138 | goto fail_tx; |
1139 | } | 1139 | } |
@@ -1159,9 +1159,9 @@ static int ath9k_htc_start(struct ieee80211_hw *hw) | |||
1159 | 1159 | ||
1160 | mutex_lock(&priv->mutex); | 1160 | mutex_lock(&priv->mutex); |
1161 | 1161 | ||
1162 | ath_print(common, ATH_DBG_CONFIG, | 1162 | ath_dbg(common, ATH_DBG_CONFIG, |
1163 | "Starting driver with initial channel: %d MHz\n", | 1163 | "Starting driver with initial channel: %d MHz\n", |
1164 | curchan->center_freq); | 1164 | curchan->center_freq); |
1165 | 1165 | ||
1166 | /* Ensure that HW is awake before flushing RX */ | 1166 | /* Ensure that HW is awake before flushing RX */ |
1167 | ath9k_htc_setpower(priv, ATH9K_PM_AWAKE); | 1167 | ath9k_htc_setpower(priv, ATH9K_PM_AWAKE); |
@@ -1224,7 +1224,7 @@ static void ath9k_htc_stop(struct ieee80211_hw *hw) | |||
1224 | mutex_lock(&priv->mutex); | 1224 | mutex_lock(&priv->mutex); |
1225 | 1225 | ||
1226 | if (priv->op_flags & OP_INVALID) { | 1226 | if (priv->op_flags & OP_INVALID) { |
1227 | ath_print(common, ATH_DBG_ANY, "Device not present\n"); | 1227 | ath_dbg(common, ATH_DBG_ANY, "Device not present\n"); |
1228 | mutex_unlock(&priv->mutex); | 1228 | mutex_unlock(&priv->mutex); |
1229 | return; | 1229 | return; |
1230 | } | 1230 | } |
@@ -1246,8 +1246,8 @@ static void ath9k_htc_stop(struct ieee80211_hw *hw) | |||
1246 | if (ath9k_htc_remove_monitor_interface(priv)) | 1246 | if (ath9k_htc_remove_monitor_interface(priv)) |
1247 | ath_err(common, "Unable to remove monitor interface\n"); | 1247 | ath_err(common, "Unable to remove monitor interface\n"); |
1248 | else | 1248 | else |
1249 | ath_print(common, ATH_DBG_CONFIG, | 1249 | ath_dbg(common, ATH_DBG_CONFIG, |
1250 | "Monitor interface removed\n"); | 1250 | "Monitor interface removed\n"); |
1251 | } | 1251 | } |
1252 | 1252 | ||
1253 | if (ah->btcoex_hw.enabled) { | 1253 | if (ah->btcoex_hw.enabled) { |
@@ -1264,7 +1264,7 @@ static void ath9k_htc_stop(struct ieee80211_hw *hw) | |||
1264 | 1264 | ||
1265 | priv->op_flags |= OP_INVALID; | 1265 | priv->op_flags |= OP_INVALID; |
1266 | 1266 | ||
1267 | ath_print(common, ATH_DBG_CONFIG, "Driver halt\n"); | 1267 | ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n"); |
1268 | mutex_unlock(&priv->mutex); | 1268 | mutex_unlock(&priv->mutex); |
1269 | } | 1269 | } |
1270 | 1270 | ||
@@ -1304,8 +1304,8 @@ static int ath9k_htc_add_interface(struct ieee80211_hw *hw, | |||
1304 | goto out; | 1304 | goto out; |
1305 | } | 1305 | } |
1306 | 1306 | ||
1307 | ath_print(common, ATH_DBG_CONFIG, | 1307 | ath_dbg(common, ATH_DBG_CONFIG, |
1308 | "Attach a VIF of type: %d\n", vif->type); | 1308 | "Attach a VIF of type: %d\n", vif->type); |
1309 | 1309 | ||
1310 | priv->ah->opmode = vif->type; | 1310 | priv->ah->opmode = vif->type; |
1311 | 1311 | ||
@@ -1328,8 +1328,8 @@ static int ath9k_htc_add_interface(struct ieee80211_hw *hw, | |||
1328 | 1328 | ||
1329 | ret = ath9k_htc_update_cap_target(priv); | 1329 | ret = ath9k_htc_update_cap_target(priv); |
1330 | if (ret) | 1330 | if (ret) |
1331 | ath_print(common, ATH_DBG_CONFIG, "Failed to update" | 1331 | ath_dbg(common, ATH_DBG_CONFIG, |
1332 | " capability in target \n"); | 1332 | "Failed to update capability in target\n"); |
1333 | 1333 | ||
1334 | priv->vif = vif; | 1334 | priv->vif = vif; |
1335 | out: | 1335 | out: |
@@ -1349,7 +1349,7 @@ static void ath9k_htc_remove_interface(struct ieee80211_hw *hw, | |||
1349 | int ret = 0; | 1349 | int ret = 0; |
1350 | u8 cmd_rsp; | 1350 | u8 cmd_rsp; |
1351 | 1351 | ||
1352 | ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n"); | 1352 | ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n"); |
1353 | 1353 | ||
1354 | mutex_lock(&priv->mutex); | 1354 | mutex_lock(&priv->mutex); |
1355 | ath9k_htc_ps_wakeup(priv); | 1355 | ath9k_htc_ps_wakeup(priv); |
@@ -1386,8 +1386,8 @@ static int ath9k_htc_config(struct ieee80211_hw *hw, u32 changed) | |||
1386 | mutex_unlock(&priv->htc_pm_lock); | 1386 | mutex_unlock(&priv->htc_pm_lock); |
1387 | 1387 | ||
1388 | if (enable_radio) { | 1388 | if (enable_radio) { |
1389 | ath_print(common, ATH_DBG_CONFIG, | 1389 | ath_dbg(common, ATH_DBG_CONFIG, |
1390 | "not-idle: enabling radio\n"); | 1390 | "not-idle: enabling radio\n"); |
1391 | ath9k_htc_setpower(priv, ATH9K_PM_AWAKE); | 1391 | ath9k_htc_setpower(priv, ATH9K_PM_AWAKE); |
1392 | ath9k_htc_radio_enable(hw); | 1392 | ath9k_htc_radio_enable(hw); |
1393 | } | 1393 | } |
@@ -1397,8 +1397,8 @@ static int ath9k_htc_config(struct ieee80211_hw *hw, u32 changed) | |||
1397 | struct ieee80211_channel *curchan = hw->conf.channel; | 1397 | struct ieee80211_channel *curchan = hw->conf.channel; |
1398 | int pos = curchan->hw_value; | 1398 | int pos = curchan->hw_value; |
1399 | 1399 | ||
1400 | ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n", | 1400 | ath_dbg(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n", |
1401 | curchan->center_freq); | 1401 | curchan->center_freq); |
1402 | 1402 | ||
1403 | ath9k_cmn_update_ichannel(&priv->ah->channels[pos], | 1403 | ath9k_cmn_update_ichannel(&priv->ah->channels[pos], |
1404 | hw->conf.channel, | 1404 | hw->conf.channel, |
@@ -1427,8 +1427,8 @@ static int ath9k_htc_config(struct ieee80211_hw *hw, u32 changed) | |||
1427 | if (ath9k_htc_add_monitor_interface(priv)) | 1427 | if (ath9k_htc_add_monitor_interface(priv)) |
1428 | ath_err(common, "Failed to set monitor mode\n"); | 1428 | ath_err(common, "Failed to set monitor mode\n"); |
1429 | else | 1429 | else |
1430 | ath_print(common, ATH_DBG_CONFIG, | 1430 | ath_dbg(common, ATH_DBG_CONFIG, |
1431 | "HW opmode set to Monitor mode\n"); | 1431 | "HW opmode set to Monitor mode\n"); |
1432 | } | 1432 | } |
1433 | } | 1433 | } |
1434 | 1434 | ||
@@ -1440,8 +1440,8 @@ static int ath9k_htc_config(struct ieee80211_hw *hw, u32 changed) | |||
1440 | } | 1440 | } |
1441 | mutex_unlock(&priv->htc_pm_lock); | 1441 | mutex_unlock(&priv->htc_pm_lock); |
1442 | 1442 | ||
1443 | ath_print(common, ATH_DBG_CONFIG, | 1443 | ath_dbg(common, ATH_DBG_CONFIG, |
1444 | "idle: disabling radio\n"); | 1444 | "idle: disabling radio\n"); |
1445 | ath9k_htc_radio_disable(hw); | 1445 | ath9k_htc_radio_disable(hw); |
1446 | } | 1446 | } |
1447 | 1447 | ||
@@ -1478,8 +1478,8 @@ static void ath9k_htc_configure_filter(struct ieee80211_hw *hw, | |||
1478 | rfilt = ath9k_htc_calcrxfilter(priv); | 1478 | rfilt = ath9k_htc_calcrxfilter(priv); |
1479 | ath9k_hw_setrxfilter(priv->ah, rfilt); | 1479 | ath9k_hw_setrxfilter(priv->ah, rfilt); |
1480 | 1480 | ||
1481 | ath_print(ath9k_hw_common(priv->ah), ATH_DBG_CONFIG, | 1481 | ath_dbg(ath9k_hw_common(priv->ah), ATH_DBG_CONFIG, |
1482 | "Set HW RX filter: 0x%x\n", rfilt); | 1482 | "Set HW RX filter: 0x%x\n", rfilt); |
1483 | 1483 | ||
1484 | ath9k_htc_ps_restore(priv); | 1484 | ath9k_htc_ps_restore(priv); |
1485 | mutex_unlock(&priv->mutex); | 1485 | mutex_unlock(&priv->mutex); |
@@ -1542,11 +1542,10 @@ static int ath9k_htc_conf_tx(struct ieee80211_hw *hw, u16 queue, | |||
1542 | 1542 | ||
1543 | qnum = get_hw_qnum(queue, priv->hwq_map); | 1543 | qnum = get_hw_qnum(queue, priv->hwq_map); |
1544 | 1544 | ||
1545 | ath_print(common, ATH_DBG_CONFIG, | 1545 | ath_dbg(common, ATH_DBG_CONFIG, |
1546 | "Configure tx [queue/hwq] [%d/%d], " | 1546 | "Configure tx [queue/hwq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", |
1547 | "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", | 1547 | queue, qnum, params->aifs, params->cw_min, |
1548 | queue, qnum, params->aifs, params->cw_min, | 1548 | params->cw_max, params->txop); |
1549 | params->cw_max, params->txop); | ||
1550 | 1549 | ||
1551 | ret = ath_htc_txq_update(priv, qnum, &qi); | 1550 | ret = ath_htc_txq_update(priv, qnum, &qi); |
1552 | if (ret) { | 1551 | if (ret) { |
@@ -1578,7 +1577,7 @@ static int ath9k_htc_set_key(struct ieee80211_hw *hw, | |||
1578 | return -ENOSPC; | 1577 | return -ENOSPC; |
1579 | 1578 | ||
1580 | mutex_lock(&priv->mutex); | 1579 | mutex_lock(&priv->mutex); |
1581 | ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n"); | 1580 | ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n"); |
1582 | ath9k_htc_ps_wakeup(priv); | 1581 | ath9k_htc_ps_wakeup(priv); |
1583 | 1582 | ||
1584 | switch (cmd) { | 1583 | switch (cmd) { |
@@ -1624,7 +1623,7 @@ static void ath9k_htc_bss_info_changed(struct ieee80211_hw *hw, | |||
1624 | if (changed & BSS_CHANGED_ASSOC) { | 1623 | if (changed & BSS_CHANGED_ASSOC) { |
1625 | common->curaid = bss_conf->assoc ? | 1624 | common->curaid = bss_conf->assoc ? |
1626 | bss_conf->aid : 0; | 1625 | bss_conf->aid : 0; |
1627 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n", | 1626 | ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n", |
1628 | bss_conf->assoc); | 1627 | bss_conf->assoc); |
1629 | 1628 | ||
1630 | if (bss_conf->assoc) { | 1629 | if (bss_conf->assoc) { |
@@ -1641,9 +1640,9 @@ static void ath9k_htc_bss_info_changed(struct ieee80211_hw *hw, | |||
1641 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); | 1640 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); |
1642 | ath9k_hw_write_associd(ah); | 1641 | ath9k_hw_write_associd(ah); |
1643 | 1642 | ||
1644 | ath_print(common, ATH_DBG_CONFIG, | 1643 | ath_dbg(common, ATH_DBG_CONFIG, |
1645 | "BSSID: %pM aid: 0x%x\n", | 1644 | "BSSID: %pM aid: 0x%x\n", |
1646 | common->curbssid, common->curaid); | 1645 | common->curbssid, common->curaid); |
1647 | } | 1646 | } |
1648 | 1647 | ||
1649 | if ((changed & BSS_CHANGED_BEACON_INT) || | 1648 | if ((changed & BSS_CHANGED_BEACON_INT) || |
@@ -1661,8 +1660,8 @@ static void ath9k_htc_bss_info_changed(struct ieee80211_hw *hw, | |||
1661 | } | 1660 | } |
1662 | 1661 | ||
1663 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { | 1662 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
1664 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", | 1663 | ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", |
1665 | bss_conf->use_short_preamble); | 1664 | bss_conf->use_short_preamble); |
1666 | if (bss_conf->use_short_preamble) | 1665 | if (bss_conf->use_short_preamble) |
1667 | priv->op_flags |= OP_PREAMBLE_SHORT; | 1666 | priv->op_flags |= OP_PREAMBLE_SHORT; |
1668 | else | 1667 | else |
@@ -1670,8 +1669,8 @@ static void ath9k_htc_bss_info_changed(struct ieee80211_hw *hw, | |||
1670 | } | 1669 | } |
1671 | 1670 | ||
1672 | if (changed & BSS_CHANGED_ERP_CTS_PROT) { | 1671 | if (changed & BSS_CHANGED_ERP_CTS_PROT) { |
1673 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", | 1672 | ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", |
1674 | bss_conf->use_cts_prot); | 1673 | bss_conf->use_cts_prot); |
1675 | if (bss_conf->use_cts_prot && | 1674 | if (bss_conf->use_cts_prot && |
1676 | hw->conf.channel->band != IEEE80211_BAND_5GHZ) | 1675 | hw->conf.channel->band != IEEE80211_BAND_5GHZ) |
1677 | priv->op_flags |= OP_PROTECT_ENABLE; | 1676 | priv->op_flags |= OP_PROTECT_ENABLE; |
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c b/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c index 5bef41f8c82..31fad82239b 100644 --- a/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c +++ b/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c | |||
@@ -270,8 +270,8 @@ void ath9k_tx_tasklet(unsigned long data) | |||
270 | if (priv->tx_queues_stop) { | 270 | if (priv->tx_queues_stop) { |
271 | priv->tx_queues_stop = false; | 271 | priv->tx_queues_stop = false; |
272 | spin_unlock_bh(&priv->tx_lock); | 272 | spin_unlock_bh(&priv->tx_lock); |
273 | ath_print(ath9k_hw_common(priv->ah), ATH_DBG_XMIT, | 273 | ath_dbg(ath9k_hw_common(priv->ah), ATH_DBG_XMIT, |
274 | "Waking up TX queues\n"); | 274 | "Waking up TX queues\n"); |
275 | ieee80211_wake_queues(priv->hw); | 275 | ieee80211_wake_queues(priv->hw); |
276 | return; | 276 | return; |
277 | } | 277 | } |
@@ -681,8 +681,8 @@ void ath9k_htc_rxep(void *drv_priv, struct sk_buff *skb, | |||
681 | spin_unlock(&priv->rx.rxbuflock); | 681 | spin_unlock(&priv->rx.rxbuflock); |
682 | 682 | ||
683 | if (rxbuf == NULL) { | 683 | if (rxbuf == NULL) { |
684 | ath_print(common, ATH_DBG_ANY, | 684 | ath_dbg(common, ATH_DBG_ANY, |
685 | "No free RX buffer\n"); | 685 | "No free RX buffer\n"); |
686 | goto err; | 686 | goto err; |
687 | } | 687 | } |
688 | 688 | ||
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c index 00ecbfa07df..9d3be0392a9 100644 --- a/drivers/net/wireless/ath/ath9k/hw.c +++ b/drivers/net/wireless/ath/ath9k/hw.c | |||
@@ -129,9 +129,9 @@ bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) | |||
129 | udelay(AH_TIME_QUANTUM); | 129 | udelay(AH_TIME_QUANTUM); |
130 | } | 130 | } |
131 | 131 | ||
132 | ath_print(ath9k_hw_common(ah), ATH_DBG_ANY, | 132 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY, |
133 | "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", | 133 | "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", |
134 | timeout, reg, REG_READ(ah, reg), mask, val); | 134 | timeout, reg, REG_READ(ah, reg), mask, val); |
135 | 135 | ||
136 | return false; | 136 | return false; |
137 | } | 137 | } |
@@ -465,10 +465,10 @@ static int ath9k_hw_post_init(struct ath_hw *ah) | |||
465 | if (ecode != 0) | 465 | if (ecode != 0) |
466 | return ecode; | 466 | return ecode; |
467 | 467 | ||
468 | ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG, | 468 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG, |
469 | "Eeprom VER: %d, REV: %d\n", | 469 | "Eeprom VER: %d, REV: %d\n", |
470 | ah->eep_ops->get_eeprom_ver(ah), | 470 | ah->eep_ops->get_eeprom_ver(ah), |
471 | ah->eep_ops->get_eeprom_rev(ah)); | 471 | ah->eep_ops->get_eeprom_rev(ah)); |
472 | 472 | ||
473 | ecode = ath9k_hw_rf_alloc_ext_banks(ah); | 473 | ecode = ath9k_hw_rf_alloc_ext_banks(ah); |
474 | if (ecode) { | 474 | if (ecode) { |
@@ -530,7 +530,7 @@ static int __ath9k_hw_init(struct ath_hw *ah) | |||
530 | } | 530 | } |
531 | } | 531 | } |
532 | 532 | ||
533 | ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n", | 533 | ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n", |
534 | ah->config.serialize_regmode); | 534 | ah->config.serialize_regmode); |
535 | 535 | ||
536 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) | 536 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) |
@@ -758,8 +758,8 @@ static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) | |||
758 | static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) | 758 | static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) |
759 | { | 759 | { |
760 | if (tu > 0xFFFF) { | 760 | if (tu > 0xFFFF) { |
761 | ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT, | 761 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT, |
762 | "bad global tx timeout %u\n", tu); | 762 | "bad global tx timeout %u\n", tu); |
763 | ah->globaltxtimeout = (u32) -1; | 763 | ah->globaltxtimeout = (u32) -1; |
764 | return false; | 764 | return false; |
765 | } else { | 765 | } else { |
@@ -776,8 +776,8 @@ void ath9k_hw_init_global_settings(struct ath_hw *ah) | |||
776 | int slottime; | 776 | int slottime; |
777 | int sifstime; | 777 | int sifstime; |
778 | 778 | ||
779 | ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n", | 779 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n", |
780 | ah->misc_mode); | 780 | ah->misc_mode); |
781 | 781 | ||
782 | if (ah->misc_mode != 0) | 782 | if (ah->misc_mode != 0) |
783 | REG_WRITE(ah, AR_PCU_MISC, | 783 | REG_WRITE(ah, AR_PCU_MISC, |
@@ -1020,8 +1020,8 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) | |||
1020 | 1020 | ||
1021 | REG_WRITE(ah, AR_RTC_RC, 0); | 1021 | REG_WRITE(ah, AR_RTC_RC, 0); |
1022 | if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { | 1022 | if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { |
1023 | ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, | 1023 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, |
1024 | "RTC stuck in MAC reset\n"); | 1024 | "RTC stuck in MAC reset\n"); |
1025 | return false; | 1025 | return false; |
1026 | } | 1026 | } |
1027 | 1027 | ||
@@ -1067,8 +1067,8 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) | |||
1067 | AR_RTC_STATUS_M, | 1067 | AR_RTC_STATUS_M, |
1068 | AR_RTC_STATUS_ON, | 1068 | AR_RTC_STATUS_ON, |
1069 | AH_WAIT_TIMEOUT)) { | 1069 | AH_WAIT_TIMEOUT)) { |
1070 | ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, | 1070 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, |
1071 | "RTC not waking up\n"); | 1071 | "RTC not waking up\n"); |
1072 | return false; | 1072 | return false; |
1073 | } | 1073 | } |
1074 | 1074 | ||
@@ -1128,9 +1128,8 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah, | |||
1128 | 1128 | ||
1129 | for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { | 1129 | for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { |
1130 | if (ath9k_hw_numtxpending(ah, qnum)) { | 1130 | if (ath9k_hw_numtxpending(ah, qnum)) { |
1131 | ath_print(common, ATH_DBG_QUEUE, | 1131 | ath_dbg(common, ATH_DBG_QUEUE, |
1132 | "Transmit frames pending on " | 1132 | "Transmit frames pending on queue %d\n", qnum); |
1133 | "queue %d\n", qnum); | ||
1134 | return false; | 1133 | return false; |
1135 | } | 1134 | } |
1136 | } | 1135 | } |
@@ -1211,7 +1210,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, | |||
1211 | if (!ah->chip_fullsleep) { | 1210 | if (!ah->chip_fullsleep) { |
1212 | ath9k_hw_abortpcurecv(ah); | 1211 | ath9k_hw_abortpcurecv(ah); |
1213 | if (!ath9k_hw_stopdmarecv(ah)) { | 1212 | if (!ath9k_hw_stopdmarecv(ah)) { |
1214 | ath_print(common, ATH_DBG_XMIT, | 1213 | ath_dbg(common, ATH_DBG_XMIT, |
1215 | "Failed to stop receive dma\n"); | 1214 | "Failed to stop receive dma\n"); |
1216 | bChannelChange = false; | 1215 | bChannelChange = false; |
1217 | } | 1216 | } |
@@ -1423,13 +1422,13 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, | |||
1423 | u32 mask; | 1422 | u32 mask; |
1424 | mask = REG_READ(ah, AR_CFG); | 1423 | mask = REG_READ(ah, AR_CFG); |
1425 | if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { | 1424 | if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { |
1426 | ath_print(common, ATH_DBG_RESET, | 1425 | ath_dbg(common, ATH_DBG_RESET, |
1427 | "CFG Byte Swap Set 0x%x\n", mask); | 1426 | "CFG Byte Swap Set 0x%x\n", mask); |
1428 | } else { | 1427 | } else { |
1429 | mask = | 1428 | mask = |
1430 | INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; | 1429 | INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; |
1431 | REG_WRITE(ah, AR_CFG, mask); | 1430 | REG_WRITE(ah, AR_CFG, mask); |
1432 | ath_print(common, ATH_DBG_RESET, | 1431 | ath_dbg(common, ATH_DBG_RESET, |
1433 | "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); | 1432 | "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); |
1434 | } | 1433 | } |
1435 | } else { | 1434 | } else { |
@@ -1583,8 +1582,8 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) | |||
1583 | if (ah->power_mode == mode) | 1582 | if (ah->power_mode == mode) |
1584 | return status; | 1583 | return status; |
1585 | 1584 | ||
1586 | ath_print(common, ATH_DBG_RESET, "%s -> %s\n", | 1585 | ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n", |
1587 | modes[ah->power_mode], modes[mode]); | 1586 | modes[ah->power_mode], modes[mode]); |
1588 | 1587 | ||
1589 | switch (mode) { | 1588 | switch (mode) { |
1590 | case ATH9K_PM_AWAKE: | 1589 | case ATH9K_PM_AWAKE: |
@@ -1657,9 +1656,9 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) | |||
1657 | flags |= AR_TBTT_TIMER_EN; | 1656 | flags |= AR_TBTT_TIMER_EN; |
1658 | break; | 1657 | break; |
1659 | } | 1658 | } |
1660 | ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON, | 1659 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON, |
1661 | "%s: unsupported opmode: %d\n", | 1660 | "%s: unsupported opmode: %d\n", |
1662 | __func__, ah->opmode); | 1661 | __func__, ah->opmode); |
1663 | return; | 1662 | return; |
1664 | break; | 1663 | break; |
1665 | } | 1664 | } |
@@ -1715,10 +1714,10 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, | |||
1715 | else | 1714 | else |
1716 | nextTbtt = bs->bs_nexttbtt; | 1715 | nextTbtt = bs->bs_nexttbtt; |
1717 | 1716 | ||
1718 | ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim); | 1717 | ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim); |
1719 | ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt); | 1718 | ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt); |
1720 | ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); | 1719 | ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); |
1721 | ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); | 1720 | ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); |
1722 | 1721 | ||
1723 | ENABLE_REGWRITE_BUFFER(ah); | 1722 | ENABLE_REGWRITE_BUFFER(ah); |
1724 | 1723 | ||
@@ -1783,8 +1782,8 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah) | |||
1783 | regulatory->current_rd += 5; | 1782 | regulatory->current_rd += 5; |
1784 | else if (regulatory->current_rd == 0x41) | 1783 | else if (regulatory->current_rd == 0x41) |
1785 | regulatory->current_rd = 0x43; | 1784 | regulatory->current_rd = 0x43; |
1786 | ath_print(common, ATH_DBG_REGULATORY, | 1785 | ath_dbg(common, ATH_DBG_REGULATORY, |
1787 | "regdomain mapped to 0x%x\n", regulatory->current_rd); | 1786 | "regdomain mapped to 0x%x\n", regulatory->current_rd); |
1788 | } | 1787 | } |
1789 | 1788 | ||
1790 | eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); | 1789 | eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); |
@@ -2245,8 +2244,8 @@ void ath9k_hw_reset_tsf(struct ath_hw *ah) | |||
2245 | { | 2244 | { |
2246 | if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, | 2245 | if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, |
2247 | AH_TSF_WRITE_TIMEOUT)) | 2246 | AH_TSF_WRITE_TIMEOUT)) |
2248 | ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, | 2247 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, |
2249 | "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); | 2248 | "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); |
2250 | 2249 | ||
2251 | REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); | 2250 | REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); |
2252 | } | 2251 | } |
@@ -2367,9 +2366,9 @@ void ath9k_hw_gen_timer_start(struct ath_hw *ah, | |||
2367 | 2366 | ||
2368 | tsf = ath9k_hw_gettsf32(ah); | 2367 | tsf = ath9k_hw_gettsf32(ah); |
2369 | 2368 | ||
2370 | ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER, | 2369 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER, |
2371 | "curent tsf %x period %x" | 2370 | "current tsf %x period %x timer_next %x\n", |
2372 | "timer_next %x\n", tsf, timer_period, timer_next); | 2371 | tsf, timer_period, timer_next); |
2373 | 2372 | ||
2374 | /* | 2373 | /* |
2375 | * Pull timer_next forward if the current TSF already passed it | 2374 | * Pull timer_next forward if the current TSF already passed it |
@@ -2449,8 +2448,8 @@ void ath_gen_timer_isr(struct ath_hw *ah) | |||
2449 | index = rightmost_index(timer_table, &thresh_mask); | 2448 | index = rightmost_index(timer_table, &thresh_mask); |
2450 | timer = timer_table->timers[index]; | 2449 | timer = timer_table->timers[index]; |
2451 | BUG_ON(!timer); | 2450 | BUG_ON(!timer); |
2452 | ath_print(common, ATH_DBG_HWTIMER, | 2451 | ath_dbg(common, ATH_DBG_HWTIMER, |
2453 | "TSF overflow for Gen timer %d\n", index); | 2452 | "TSF overflow for Gen timer %d\n", index); |
2454 | timer->overflow(timer->arg); | 2453 | timer->overflow(timer->arg); |
2455 | } | 2454 | } |
2456 | 2455 | ||
@@ -2458,8 +2457,8 @@ void ath_gen_timer_isr(struct ath_hw *ah) | |||
2458 | index = rightmost_index(timer_table, &trigger_mask); | 2457 | index = rightmost_index(timer_table, &trigger_mask); |
2459 | timer = timer_table->timers[index]; | 2458 | timer = timer_table->timers[index]; |
2460 | BUG_ON(!timer); | 2459 | BUG_ON(!timer); |
2461 | ath_print(common, ATH_DBG_HWTIMER, | 2460 | ath_dbg(common, ATH_DBG_HWTIMER, |
2462 | "Gen timer[%d] trigger\n", index); | 2461 | "Gen timer[%d] trigger\n", index); |
2463 | timer->trigger(timer->arg); | 2462 | timer->trigger(timer->arg); |
2464 | } | 2463 | } |
2465 | } | 2464 | } |
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h index 5fcfa48a45d..ee0b1cfe9c5 100644 --- a/drivers/net/wireless/ath/ath9k/hw.h +++ b/drivers/net/wireless/ath/ath9k/hw.h | |||
@@ -30,7 +30,6 @@ | |||
30 | #include "btcoex.h" | 30 | #include "btcoex.h" |
31 | 31 | ||
32 | #include "../regd.h" | 32 | #include "../regd.h" |
33 | #include "../debug.h" | ||
34 | 33 | ||
35 | #define ATHEROS_VENDOR_ID 0x168c | 34 | #define ATHEROS_VENDOR_ID 0x168c |
36 | 35 | ||
diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c index 2b519b387a2..5987ed1cd97 100644 --- a/drivers/net/wireless/ath/ath9k/init.c +++ b/drivers/net/wireless/ath/ath9k/init.c | |||
@@ -226,9 +226,9 @@ static void setup_ht_cap(struct ath_softc *sc, | |||
226 | tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, max_streams); | 226 | tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, max_streams); |
227 | rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, max_streams); | 227 | rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, max_streams); |
228 | 228 | ||
229 | ath_print(common, ATH_DBG_CONFIG, | 229 | ath_dbg(common, ATH_DBG_CONFIG, |
230 | "TX streams %d, RX streams: %d\n", | 230 | "TX streams %d, RX streams: %d\n", |
231 | tx_streams, rx_streams); | 231 | tx_streams, rx_streams); |
232 | 232 | ||
233 | if (tx_streams != rx_streams) { | 233 | if (tx_streams != rx_streams) { |
234 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; | 234 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; |
@@ -271,8 +271,8 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |||
271 | struct ath_buf *bf; | 271 | struct ath_buf *bf; |
272 | int i, bsize, error, desc_len; | 272 | int i, bsize, error, desc_len; |
273 | 273 | ||
274 | ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n", | 274 | ath_dbg(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n", |
275 | name, nbuf, ndesc); | 275 | name, nbuf, ndesc); |
276 | 276 | ||
277 | INIT_LIST_HEAD(head); | 277 | INIT_LIST_HEAD(head); |
278 | 278 | ||
@@ -317,9 +317,9 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |||
317 | goto fail; | 317 | goto fail; |
318 | } | 318 | } |
319 | ds = (u8 *) dd->dd_desc; | 319 | ds = (u8 *) dd->dd_desc; |
320 | ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", | 320 | ath_dbg(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", |
321 | name, ds, (u32) dd->dd_desc_len, | 321 | name, ds, (u32) dd->dd_desc_len, |
322 | ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); | 322 | ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); |
323 | 323 | ||
324 | /* allocate buffers */ | 324 | /* allocate buffers */ |
325 | bsize = sizeof(struct ath_buf) * nbuf; | 325 | bsize = sizeof(struct ath_buf) * nbuf; |
@@ -373,9 +373,9 @@ static void ath9k_init_crypto(struct ath_softc *sc) | |||
373 | /* Get the hardware key cache size. */ | 373 | /* Get the hardware key cache size. */ |
374 | common->keymax = sc->sc_ah->caps.keycache_size; | 374 | common->keymax = sc->sc_ah->caps.keycache_size; |
375 | if (common->keymax > ATH_KEYMAX) { | 375 | if (common->keymax > ATH_KEYMAX) { |
376 | ath_print(common, ATH_DBG_ANY, | 376 | ath_dbg(common, ATH_DBG_ANY, |
377 | "Warning, using only %u entries in %u key cache\n", | 377 | "Warning, using only %u entries in %u key cache\n", |
378 | ATH_KEYMAX, common->keymax); | 378 | ATH_KEYMAX, common->keymax); |
379 | common->keymax = ATH_KEYMAX; | 379 | common->keymax = ATH_KEYMAX; |
380 | } | 380 | } |
381 | 381 | ||
diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c index b96e750d4c3..f05462ace4e 100644 --- a/drivers/net/wireless/ath/ath9k/mac.c +++ b/drivers/net/wireless/ath/ath9k/mac.c | |||
@@ -20,11 +20,11 @@ | |||
20 | static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah, | 20 | static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah, |
21 | struct ath9k_tx_queue_info *qi) | 21 | struct ath9k_tx_queue_info *qi) |
22 | { | 22 | { |
23 | ath_print(ath9k_hw_common(ah), ATH_DBG_INTERRUPT, | 23 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_INTERRUPT, |
24 | "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", | 24 | "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", |
25 | ah->txok_interrupt_mask, ah->txerr_interrupt_mask, | 25 | ah->txok_interrupt_mask, ah->txerr_interrupt_mask, |
26 | ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask, | 26 | ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask, |
27 | ah->txurn_interrupt_mask); | 27 | ah->txurn_interrupt_mask); |
28 | 28 | ||
29 | ENABLE_REGWRITE_BUFFER(ah); | 29 | ENABLE_REGWRITE_BUFFER(ah); |
30 | 30 | ||
@@ -56,8 +56,8 @@ EXPORT_SYMBOL(ath9k_hw_puttxbuf); | |||
56 | 56 | ||
57 | void ath9k_hw_txstart(struct ath_hw *ah, u32 q) | 57 | void ath9k_hw_txstart(struct ath_hw *ah, u32 q) |
58 | { | 58 | { |
59 | ath_print(ath9k_hw_common(ah), ATH_DBG_QUEUE, | 59 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_QUEUE, |
60 | "Enable TXE on queue: %u\n", q); | 60 | "Enable TXE on queue: %u\n", q); |
61 | REG_WRITE(ah, AR_Q_TXE, 1 << q); | 61 | REG_WRITE(ah, AR_Q_TXE, 1 << q); |
62 | } | 62 | } |
63 | EXPORT_SYMBOL(ath9k_hw_txstart); | 63 | EXPORT_SYMBOL(ath9k_hw_txstart); |
@@ -154,15 +154,15 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q) | |||
154 | u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM; | 154 | u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM; |
155 | 155 | ||
156 | if (q >= pCap->total_queues) { | 156 | if (q >= pCap->total_queues) { |
157 | ath_print(common, ATH_DBG_QUEUE, "Stopping TX DMA, " | 157 | ath_dbg(common, ATH_DBG_QUEUE, |
158 | "invalid queue: %u\n", q); | 158 | "Stopping TX DMA, invalid queue: %u\n", q); |
159 | return false; | 159 | return false; |
160 | } | 160 | } |
161 | 161 | ||
162 | qi = &ah->txq[q]; | 162 | qi = &ah->txq[q]; |
163 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { | 163 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { |
164 | ath_print(common, ATH_DBG_QUEUE, "Stopping TX DMA, " | 164 | ath_dbg(common, ATH_DBG_QUEUE, |
165 | "inactive queue: %u\n", q); | 165 | "Stopping TX DMA, inactive queue: %u\n", q); |
166 | return false; | 166 | return false; |
167 | } | 167 | } |
168 | 168 | ||
@@ -175,9 +175,9 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q) | |||
175 | } | 175 | } |
176 | 176 | ||
177 | if (ath9k_hw_numtxpending(ah, q)) { | 177 | if (ath9k_hw_numtxpending(ah, q)) { |
178 | ath_print(common, ATH_DBG_QUEUE, | 178 | ath_dbg(common, ATH_DBG_QUEUE, |
179 | "%s: Num of pending TX Frames %d on Q %d\n", | 179 | "%s: Num of pending TX Frames %d on Q %d\n", |
180 | __func__, ath9k_hw_numtxpending(ah, q), q); | 180 | __func__, ath9k_hw_numtxpending(ah, q), q); |
181 | 181 | ||
182 | for (j = 0; j < 2; j++) { | 182 | for (j = 0; j < 2; j++) { |
183 | tsfLow = REG_READ(ah, AR_TSF_L32); | 183 | tsfLow = REG_READ(ah, AR_TSF_L32); |
@@ -191,9 +191,9 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q) | |||
191 | if ((REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10)) | 191 | if ((REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10)) |
192 | break; | 192 | break; |
193 | 193 | ||
194 | ath_print(common, ATH_DBG_QUEUE, | 194 | ath_dbg(common, ATH_DBG_QUEUE, |
195 | "TSF has moved while trying to set " | 195 | "TSF has moved while trying to set quiet time TSF: 0x%08x\n", |
196 | "quiet time TSF: 0x%08x\n", tsfLow); | 196 | tsfLow); |
197 | } | 197 | } |
198 | 198 | ||
199 | REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); | 199 | REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); |
@@ -238,19 +238,19 @@ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, | |||
238 | struct ath9k_tx_queue_info *qi; | 238 | struct ath9k_tx_queue_info *qi; |
239 | 239 | ||
240 | if (q >= pCap->total_queues) { | 240 | if (q >= pCap->total_queues) { |
241 | ath_print(common, ATH_DBG_QUEUE, "Set TXQ properties, " | 241 | ath_dbg(common, ATH_DBG_QUEUE, |
242 | "invalid queue: %u\n", q); | 242 | "Set TXQ properties, invalid queue: %u\n", q); |
243 | return false; | 243 | return false; |
244 | } | 244 | } |
245 | 245 | ||
246 | qi = &ah->txq[q]; | 246 | qi = &ah->txq[q]; |
247 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { | 247 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { |
248 | ath_print(common, ATH_DBG_QUEUE, "Set TXQ properties, " | 248 | ath_dbg(common, ATH_DBG_QUEUE, |
249 | "inactive queue: %u\n", q); | 249 | "Set TXQ properties, inactive queue: %u\n", q); |
250 | return false; | 250 | return false; |
251 | } | 251 | } |
252 | 252 | ||
253 | ath_print(common, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q); | 253 | ath_dbg(common, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q); |
254 | 254 | ||
255 | qi->tqi_ver = qinfo->tqi_ver; | 255 | qi->tqi_ver = qinfo->tqi_ver; |
256 | qi->tqi_subtype = qinfo->tqi_subtype; | 256 | qi->tqi_subtype = qinfo->tqi_subtype; |
@@ -309,15 +309,15 @@ bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q, | |||
309 | struct ath9k_tx_queue_info *qi; | 309 | struct ath9k_tx_queue_info *qi; |
310 | 310 | ||
311 | if (q >= pCap->total_queues) { | 311 | if (q >= pCap->total_queues) { |
312 | ath_print(common, ATH_DBG_QUEUE, "Get TXQ properties, " | 312 | ath_dbg(common, ATH_DBG_QUEUE, |
313 | "invalid queue: %u\n", q); | 313 | "Get TXQ properties, invalid queue: %u\n", q); |
314 | return false; | 314 | return false; |
315 | } | 315 | } |
316 | 316 | ||
317 | qi = &ah->txq[q]; | 317 | qi = &ah->txq[q]; |
318 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { | 318 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { |
319 | ath_print(common, ATH_DBG_QUEUE, "Get TXQ properties, " | 319 | ath_dbg(common, ATH_DBG_QUEUE, |
320 | "inactive queue: %u\n", q); | 320 | "Get TXQ properties, inactive queue: %u\n", q); |
321 | return false; | 321 | return false; |
322 | } | 322 | } |
323 | 323 | ||
@@ -376,7 +376,7 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, | |||
376 | return -1; | 376 | return -1; |
377 | } | 377 | } |
378 | 378 | ||
379 | ath_print(common, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q); | 379 | ath_dbg(common, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q); |
380 | 380 | ||
381 | qi = &ah->txq[q]; | 381 | qi = &ah->txq[q]; |
382 | if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) { | 382 | if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) { |
@@ -412,18 +412,18 @@ bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q) | |||
412 | struct ath9k_tx_queue_info *qi; | 412 | struct ath9k_tx_queue_info *qi; |
413 | 413 | ||
414 | if (q >= pCap->total_queues) { | 414 | if (q >= pCap->total_queues) { |
415 | ath_print(common, ATH_DBG_QUEUE, "Release TXQ, " | 415 | ath_dbg(common, ATH_DBG_QUEUE, |
416 | "invalid queue: %u\n", q); | 416 | "Release TXQ, invalid queue: %u\n", q); |
417 | return false; | 417 | return false; |
418 | } | 418 | } |
419 | qi = &ah->txq[q]; | 419 | qi = &ah->txq[q]; |
420 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { | 420 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { |
421 | ath_print(common, ATH_DBG_QUEUE, "Release TXQ, " | 421 | ath_dbg(common, ATH_DBG_QUEUE, |
422 | "inactive queue: %u\n", q); | 422 | "Release TXQ, inactive queue: %u\n", q); |
423 | return false; | 423 | return false; |
424 | } | 424 | } |
425 | 425 | ||
426 | ath_print(common, ATH_DBG_QUEUE, "Release TX queue: %u\n", q); | 426 | ath_dbg(common, ATH_DBG_QUEUE, "Release TX queue: %u\n", q); |
427 | 427 | ||
428 | qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE; | 428 | qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE; |
429 | ah->txok_interrupt_mask &= ~(1 << q); | 429 | ah->txok_interrupt_mask &= ~(1 << q); |
@@ -446,19 +446,19 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) | |||
446 | u32 cwMin, chanCwMin, value; | 446 | u32 cwMin, chanCwMin, value; |
447 | 447 | ||
448 | if (q >= pCap->total_queues) { | 448 | if (q >= pCap->total_queues) { |
449 | ath_print(common, ATH_DBG_QUEUE, "Reset TXQ, " | 449 | ath_dbg(common, ATH_DBG_QUEUE, |
450 | "invalid queue: %u\n", q); | 450 | "Reset TXQ, invalid queue: %u\n", q); |
451 | return false; | 451 | return false; |
452 | } | 452 | } |
453 | 453 | ||
454 | qi = &ah->txq[q]; | 454 | qi = &ah->txq[q]; |
455 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { | 455 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { |
456 | ath_print(common, ATH_DBG_QUEUE, "Reset TXQ, " | 456 | ath_dbg(common, ATH_DBG_QUEUE, |
457 | "inactive queue: %u\n", q); | 457 | "Reset TXQ, inactive queue: %u\n", q); |
458 | return true; | 458 | return true; |
459 | } | 459 | } |
460 | 460 | ||
461 | ath_print(common, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q); | 461 | ath_dbg(common, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q); |
462 | 462 | ||
463 | if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) { | 463 | if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) { |
464 | if (chan && IS_CHAN_B(chan)) | 464 | if (chan && IS_CHAN_B(chan)) |
@@ -839,7 +839,7 @@ void ath9k_hw_disable_interrupts(struct ath_hw *ah) | |||
839 | { | 839 | { |
840 | struct ath_common *common = ath9k_hw_common(ah); | 840 | struct ath_common *common = ath9k_hw_common(ah); |
841 | 841 | ||
842 | ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n"); | 842 | ath_dbg(common, ATH_DBG_INTERRUPT, "disable IER\n"); |
843 | REG_WRITE(ah, AR_IER, AR_IER_DISABLE); | 843 | REG_WRITE(ah, AR_IER, AR_IER_DISABLE); |
844 | (void) REG_READ(ah, AR_IER); | 844 | (void) REG_READ(ah, AR_IER); |
845 | if (!AR_SREV_9100(ah)) { | 845 | if (!AR_SREV_9100(ah)) { |
@@ -859,7 +859,7 @@ void ath9k_hw_enable_interrupts(struct ath_hw *ah) | |||
859 | if (!(ah->imask & ATH9K_INT_GLOBAL)) | 859 | if (!(ah->imask & ATH9K_INT_GLOBAL)) |
860 | return; | 860 | return; |
861 | 861 | ||
862 | ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n"); | 862 | ath_dbg(common, ATH_DBG_INTERRUPT, "enable IER\n"); |
863 | REG_WRITE(ah, AR_IER, AR_IER_ENABLE); | 863 | REG_WRITE(ah, AR_IER, AR_IER_ENABLE); |
864 | if (!AR_SREV_9100(ah)) { | 864 | if (!AR_SREV_9100(ah)) { |
865 | REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, | 865 | REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, |
@@ -872,8 +872,8 @@ void ath9k_hw_enable_interrupts(struct ath_hw *ah) | |||
872 | REG_WRITE(ah, AR_INTR_SYNC_MASK, | 872 | REG_WRITE(ah, AR_INTR_SYNC_MASK, |
873 | AR_INTR_SYNC_DEFAULT); | 873 | AR_INTR_SYNC_DEFAULT); |
874 | } | 874 | } |
875 | ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n", | 875 | ath_dbg(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n", |
876 | REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER)); | 876 | REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER)); |
877 | } | 877 | } |
878 | EXPORT_SYMBOL(ath9k_hw_enable_interrupts); | 878 | EXPORT_SYMBOL(ath9k_hw_enable_interrupts); |
879 | 879 | ||
@@ -887,7 +887,7 @@ void ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints) | |||
887 | if (!(ints & ATH9K_INT_GLOBAL)) | 887 | if (!(ints & ATH9K_INT_GLOBAL)) |
888 | ath9k_hw_enable_interrupts(ah); | 888 | ath9k_hw_enable_interrupts(ah); |
889 | 889 | ||
890 | ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints); | 890 | ath_dbg(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints); |
891 | 891 | ||
892 | /* TODO: global int Ref count */ | 892 | /* TODO: global int Ref count */ |
893 | mask = ints & ATH9K_INT_COMMON; | 893 | mask = ints & ATH9K_INT_COMMON; |
@@ -948,7 +948,7 @@ void ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints) | |||
948 | mask2 |= AR_IMR_S2_CST; | 948 | mask2 |= AR_IMR_S2_CST; |
949 | } | 949 | } |
950 | 950 | ||
951 | ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask); | 951 | ath_dbg(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask); |
952 | REG_WRITE(ah, AR_IMR, mask); | 952 | REG_WRITE(ah, AR_IMR, mask); |
953 | ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | | 953 | ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | |
954 | AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | | 954 | AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | |
diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c index c7a7abfb222..a59cfce3335 100644 --- a/drivers/net/wireless/ath/ath9k/main.c +++ b/drivers/net/wireless/ath/ath9k/main.c | |||
@@ -260,11 +260,11 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, | |||
260 | if (!(sc->sc_flags & SC_OP_OFFCHANNEL)) | 260 | if (!(sc->sc_flags & SC_OP_OFFCHANNEL)) |
261 | caldata = &aphy->caldata; | 261 | caldata = &aphy->caldata; |
262 | 262 | ||
263 | ath_print(common, ATH_DBG_CONFIG, | 263 | ath_dbg(common, ATH_DBG_CONFIG, |
264 | "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n", | 264 | "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n", |
265 | sc->sc_ah->curchan->channel, | 265 | sc->sc_ah->curchan->channel, |
266 | channel->center_freq, conf_is_ht40(conf), | 266 | channel->center_freq, conf_is_ht40(conf), |
267 | fastcc); | 267 | fastcc); |
268 | 268 | ||
269 | r = ath9k_hw_reset(ah, hchan, caldata, fastcc); | 269 | r = ath9k_hw_reset(ah, hchan, caldata, fastcc); |
270 | if (r) { | 270 | if (r) { |
@@ -387,10 +387,9 @@ void ath_paprd_calibrate(struct work_struct *work) | |||
387 | msecs_to_jiffies(ATH_PAPRD_TIMEOUT)); | 387 | msecs_to_jiffies(ATH_PAPRD_TIMEOUT)); |
388 | sc->paprd_pending = false; | 388 | sc->paprd_pending = false; |
389 | if (!time_left) { | 389 | if (!time_left) { |
390 | ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE, | 390 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE, |
391 | "Timeout waiting for paprd training on " | 391 | "Timeout waiting for paprd training on TX chain %d\n", |
392 | "TX chain %d\n", | 392 | chain); |
393 | chain); | ||
394 | goto fail_paprd; | 393 | goto fail_paprd; |
395 | } | 394 | } |
396 | 395 | ||
@@ -449,7 +448,7 @@ void ath_ani_calibrate(unsigned long data) | |||
449 | /* Long calibration runs independently of short calibration. */ | 448 | /* Long calibration runs independently of short calibration. */ |
450 | if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) { | 449 | if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) { |
451 | longcal = true; | 450 | longcal = true; |
452 | ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies); | 451 | ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies); |
453 | common->ani.longcal_timer = timestamp; | 452 | common->ani.longcal_timer = timestamp; |
454 | } | 453 | } |
455 | 454 | ||
@@ -457,8 +456,8 @@ void ath_ani_calibrate(unsigned long data) | |||
457 | if (!common->ani.caldone) { | 456 | if (!common->ani.caldone) { |
458 | if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) { | 457 | if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) { |
459 | shortcal = true; | 458 | shortcal = true; |
460 | ath_print(common, ATH_DBG_ANI, | 459 | ath_dbg(common, ATH_DBG_ANI, |
461 | "shortcal @%lu\n", jiffies); | 460 | "shortcal @%lu\n", jiffies); |
462 | common->ani.shortcal_timer = timestamp; | 461 | common->ani.shortcal_timer = timestamp; |
463 | common->ani.resetcal_timer = timestamp; | 462 | common->ani.resetcal_timer = timestamp; |
464 | } | 463 | } |
@@ -542,10 +541,10 @@ void ath_update_chainmask(struct ath_softc *sc, int is_ht) | |||
542 | common->rx_chainmask = 1; | 541 | common->rx_chainmask = 1; |
543 | } | 542 | } |
544 | 543 | ||
545 | ath_print(common, ATH_DBG_CONFIG, | 544 | ath_dbg(common, ATH_DBG_CONFIG, |
546 | "tx chmask: %d, rx chmask: %d\n", | 545 | "tx chmask: %d, rx chmask: %d\n", |
547 | common->tx_chainmask, | 546 | common->tx_chainmask, |
548 | common->rx_chainmask); | 547 | common->rx_chainmask); |
549 | } | 548 | } |
550 | 549 | ||
551 | static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta) | 550 | static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta) |
@@ -641,8 +640,8 @@ void ath9k_tasklet(unsigned long data) | |||
641 | * TSF sync does not look correct; remain awake to sync with | 640 | * TSF sync does not look correct; remain awake to sync with |
642 | * the next Beacon. | 641 | * the next Beacon. |
643 | */ | 642 | */ |
644 | ath_print(common, ATH_DBG_PS, | 643 | ath_dbg(common, ATH_DBG_PS, |
645 | "TSFOOR - Sync with next Beacon\n"); | 644 | "TSFOOR - Sync with next Beacon\n"); |
646 | sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; | 645 | sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; |
647 | } | 646 | } |
648 | 647 | ||
@@ -840,9 +839,9 @@ static void ath9k_bss_assoc_info(struct ath_softc *sc, | |||
840 | struct ath_common *common = ath9k_hw_common(ah); | 839 | struct ath_common *common = ath9k_hw_common(ah); |
841 | 840 | ||
842 | if (bss_conf->assoc) { | 841 | if (bss_conf->assoc) { |
843 | ath_print(common, ATH_DBG_CONFIG, | 842 | ath_dbg(common, ATH_DBG_CONFIG, |
844 | "Bss Info ASSOC %d, bssid: %pM\n", | 843 | "Bss Info ASSOC %d, bssid: %pM\n", |
845 | bss_conf->aid, common->curbssid); | 844 | bss_conf->aid, common->curbssid); |
846 | 845 | ||
847 | /* New association, store aid */ | 846 | /* New association, store aid */ |
848 | common->curaid = bss_conf->aid; | 847 | common->curaid = bss_conf->aid; |
@@ -865,7 +864,7 @@ static void ath9k_bss_assoc_info(struct ath_softc *sc, | |||
865 | sc->sc_flags |= SC_OP_ANI_RUN; | 864 | sc->sc_flags |= SC_OP_ANI_RUN; |
866 | ath_start_ani(common); | 865 | ath_start_ani(common); |
867 | } else { | 866 | } else { |
868 | ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n"); | 867 | ath_dbg(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n"); |
869 | common->curaid = 0; | 868 | common->curaid = 0; |
870 | /* Stop ANI */ | 869 | /* Stop ANI */ |
871 | sc->sc_flags &= ~SC_OP_ANI_RUN; | 870 | sc->sc_flags &= ~SC_OP_ANI_RUN; |
@@ -1064,9 +1063,9 @@ static int ath9k_start(struct ieee80211_hw *hw) | |||
1064 | struct ath9k_channel *init_channel; | 1063 | struct ath9k_channel *init_channel; |
1065 | int r; | 1064 | int r; |
1066 | 1065 | ||
1067 | ath_print(common, ATH_DBG_CONFIG, | 1066 | ath_dbg(common, ATH_DBG_CONFIG, |
1068 | "Starting driver with initial channel: %d MHz\n", | 1067 | "Starting driver with initial channel: %d MHz\n", |
1069 | curchan->center_freq); | 1068 | curchan->center_freq); |
1070 | 1069 | ||
1071 | mutex_lock(&sc->mutex); | 1070 | mutex_lock(&sc->mutex); |
1072 | 1071 | ||
@@ -1196,9 +1195,9 @@ static int ath9k_tx(struct ieee80211_hw *hw, | |||
1196 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | 1195 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; |
1197 | 1196 | ||
1198 | if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) { | 1197 | if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) { |
1199 | ath_print(common, ATH_DBG_XMIT, | 1198 | ath_dbg(common, ATH_DBG_XMIT, |
1200 | "ath9k: %s: TX in unexpected wiphy state " | 1199 | "ath9k: %s: TX in unexpected wiphy state %d\n", |
1201 | "%d\n", wiphy_name(hw->wiphy), aphy->state); | 1200 | wiphy_name(hw->wiphy), aphy->state); |
1202 | goto exit; | 1201 | goto exit; |
1203 | } | 1202 | } |
1204 | 1203 | ||
@@ -1210,8 +1209,8 @@ static int ath9k_tx(struct ieee80211_hw *hw, | |||
1210 | if (ieee80211_is_data(hdr->frame_control) && | 1209 | if (ieee80211_is_data(hdr->frame_control) && |
1211 | !ieee80211_is_nullfunc(hdr->frame_control) && | 1210 | !ieee80211_is_nullfunc(hdr->frame_control) && |
1212 | !ieee80211_has_pm(hdr->frame_control)) { | 1211 | !ieee80211_has_pm(hdr->frame_control)) { |
1213 | ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame " | 1212 | ath_dbg(common, ATH_DBG_PS, |
1214 | "while in PS mode\n"); | 1213 | "Add PM=1 for a TX frame while in PS mode\n"); |
1215 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); | 1214 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); |
1216 | } | 1215 | } |
1217 | } | 1216 | } |
@@ -1226,12 +1225,12 @@ static int ath9k_tx(struct ieee80211_hw *hw, | |||
1226 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) | 1225 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
1227 | ath9k_hw_setrxabort(sc->sc_ah, 0); | 1226 | ath9k_hw_setrxabort(sc->sc_ah, 0); |
1228 | if (ieee80211_is_pspoll(hdr->frame_control)) { | 1227 | if (ieee80211_is_pspoll(hdr->frame_control)) { |
1229 | ath_print(common, ATH_DBG_PS, | 1228 | ath_dbg(common, ATH_DBG_PS, |
1230 | "Sending PS-Poll to pick a buffered frame\n"); | 1229 | "Sending PS-Poll to pick a buffered frame\n"); |
1231 | sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; | 1230 | sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; |
1232 | } else { | 1231 | } else { |
1233 | ath_print(common, ATH_DBG_PS, | 1232 | ath_dbg(common, ATH_DBG_PS, |
1234 | "Wake up to complete TX\n"); | 1233 | "Wake up to complete TX\n"); |
1235 | sc->ps_flags |= PS_WAIT_FOR_TX_ACK; | 1234 | sc->ps_flags |= PS_WAIT_FOR_TX_ACK; |
1236 | } | 1235 | } |
1237 | /* | 1236 | /* |
@@ -1245,10 +1244,10 @@ static int ath9k_tx(struct ieee80211_hw *hw, | |||
1245 | memset(&txctl, 0, sizeof(struct ath_tx_control)); | 1244 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
1246 | txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; | 1245 | txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; |
1247 | 1246 | ||
1248 | ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb); | 1247 | ath_dbg(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb); |
1249 | 1248 | ||
1250 | if (ath_tx_start(hw, skb, &txctl) != 0) { | 1249 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
1251 | ath_print(common, ATH_DBG_XMIT, "TX failed\n"); | 1250 | ath_dbg(common, ATH_DBG_XMIT, "TX failed\n"); |
1252 | goto exit; | 1251 | goto exit; |
1253 | } | 1252 | } |
1254 | 1253 | ||
@@ -1288,7 +1287,7 @@ static void ath9k_stop(struct ieee80211_hw *hw) | |||
1288 | } | 1287 | } |
1289 | 1288 | ||
1290 | if (sc->sc_flags & SC_OP_INVALID) { | 1289 | if (sc->sc_flags & SC_OP_INVALID) { |
1291 | ath_print(common, ATH_DBG_ANY, "Device not present\n"); | 1290 | ath_dbg(common, ATH_DBG_ANY, "Device not present\n"); |
1292 | mutex_unlock(&sc->mutex); | 1291 | mutex_unlock(&sc->mutex); |
1293 | return; | 1292 | return; |
1294 | } | 1293 | } |
@@ -1337,7 +1336,7 @@ static void ath9k_stop(struct ieee80211_hw *hw) | |||
1337 | 1336 | ||
1338 | mutex_unlock(&sc->mutex); | 1337 | mutex_unlock(&sc->mutex); |
1339 | 1338 | ||
1340 | ath_print(common, ATH_DBG_CONFIG, "Driver halt\n"); | 1339 | ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n"); |
1341 | } | 1340 | } |
1342 | 1341 | ||
1343 | static int ath9k_add_interface(struct ieee80211_hw *hw, | 1342 | static int ath9k_add_interface(struct ieee80211_hw *hw, |
@@ -1376,8 +1375,8 @@ static int ath9k_add_interface(struct ieee80211_hw *hw, | |||
1376 | goto out; | 1375 | goto out; |
1377 | } | 1376 | } |
1378 | 1377 | ||
1379 | ath_print(common, ATH_DBG_CONFIG, | 1378 | ath_dbg(common, ATH_DBG_CONFIG, |
1380 | "Attach a VIF of type: %d\n", ic_opmode); | 1379 | "Attach a VIF of type: %d\n", ic_opmode); |
1381 | 1380 | ||
1382 | /* Set the VIF opmode */ | 1381 | /* Set the VIF opmode */ |
1383 | avp->av_opmode = ic_opmode; | 1382 | avp->av_opmode = ic_opmode; |
@@ -1433,7 +1432,7 @@ static void ath9k_remove_interface(struct ieee80211_hw *hw, | |||
1433 | bool bs_valid = false; | 1432 | bool bs_valid = false; |
1434 | int i; | 1433 | int i; |
1435 | 1434 | ||
1436 | ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n"); | 1435 | ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n"); |
1437 | 1436 | ||
1438 | mutex_lock(&sc->mutex); | 1437 | mutex_lock(&sc->mutex); |
1439 | 1438 | ||
@@ -1548,8 +1547,8 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed) | |||
1548 | if (enable_radio) { | 1547 | if (enable_radio) { |
1549 | sc->ps_idle = false; | 1548 | sc->ps_idle = false; |
1550 | ath_radio_enable(sc, hw); | 1549 | ath_radio_enable(sc, hw); |
1551 | ath_print(common, ATH_DBG_CONFIG, | 1550 | ath_dbg(common, ATH_DBG_CONFIG, |
1552 | "not-idle: enabling radio\n"); | 1551 | "not-idle: enabling radio\n"); |
1553 | } | 1552 | } |
1554 | } | 1553 | } |
1555 | 1554 | ||
@@ -1571,12 +1570,12 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed) | |||
1571 | 1570 | ||
1572 | if (changed & IEEE80211_CONF_CHANGE_MONITOR) { | 1571 | if (changed & IEEE80211_CONF_CHANGE_MONITOR) { |
1573 | if (conf->flags & IEEE80211_CONF_MONITOR) { | 1572 | if (conf->flags & IEEE80211_CONF_MONITOR) { |
1574 | ath_print(common, ATH_DBG_CONFIG, | 1573 | ath_dbg(common, ATH_DBG_CONFIG, |
1575 | "Monitor mode is enabled\n"); | 1574 | "Monitor mode is enabled\n"); |
1576 | sc->sc_ah->is_monitoring = true; | 1575 | sc->sc_ah->is_monitoring = true; |
1577 | } else { | 1576 | } else { |
1578 | ath_print(common, ATH_DBG_CONFIG, | 1577 | ath_dbg(common, ATH_DBG_CONFIG, |
1579 | "Monitor mode is disabled\n"); | 1578 | "Monitor mode is disabled\n"); |
1580 | sc->sc_ah->is_monitoring = false; | 1579 | sc->sc_ah->is_monitoring = false; |
1581 | } | 1580 | } |
1582 | } | 1581 | } |
@@ -1608,8 +1607,8 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed) | |||
1608 | goto skip_chan_change; | 1607 | goto skip_chan_change; |
1609 | } | 1608 | } |
1610 | 1609 | ||
1611 | ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n", | 1610 | ath_dbg(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n", |
1612 | curchan->center_freq); | 1611 | curchan->center_freq); |
1613 | 1612 | ||
1614 | /* XXX: remove me eventualy */ | 1613 | /* XXX: remove me eventualy */ |
1615 | ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]); | 1614 | ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]); |
@@ -1667,7 +1666,7 @@ skip_chan_change: | |||
1667 | spin_unlock_bh(&sc->wiphy_lock); | 1666 | spin_unlock_bh(&sc->wiphy_lock); |
1668 | 1667 | ||
1669 | if (disable_radio) { | 1668 | if (disable_radio) { |
1670 | ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n"); | 1669 | ath_dbg(common, ATH_DBG_CONFIG, "idle: disabling radio\n"); |
1671 | sc->ps_idle = true; | 1670 | sc->ps_idle = true; |
1672 | ath_radio_disable(sc, hw); | 1671 | ath_radio_disable(sc, hw); |
1673 | } | 1672 | } |
@@ -1706,8 +1705,8 @@ static void ath9k_configure_filter(struct ieee80211_hw *hw, | |||
1706 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); | 1705 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); |
1707 | ath9k_ps_restore(sc); | 1706 | ath9k_ps_restore(sc); |
1708 | 1707 | ||
1709 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG, | 1708 | ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG, |
1710 | "Set HW RX filter: 0x%x\n", rfilt); | 1709 | "Set HW RX filter: 0x%x\n", rfilt); |
1711 | } | 1710 | } |
1712 | 1711 | ||
1713 | static int ath9k_sta_add(struct ieee80211_hw *hw, | 1712 | static int ath9k_sta_add(struct ieee80211_hw *hw, |
@@ -1758,11 +1757,10 @@ static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue, | |||
1758 | qi.tqi_cwmax = params->cw_max; | 1757 | qi.tqi_cwmax = params->cw_max; |
1759 | qi.tqi_burstTime = params->txop; | 1758 | qi.tqi_burstTime = params->txop; |
1760 | 1759 | ||
1761 | ath_print(common, ATH_DBG_CONFIG, | 1760 | ath_dbg(common, ATH_DBG_CONFIG, |
1762 | "Configure tx [queue/halq] [%d/%d], " | 1761 | "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", |
1763 | "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", | 1762 | queue, txq->axq_qnum, params->aifs, params->cw_min, |
1764 | queue, txq->axq_qnum, params->aifs, params->cw_min, | 1763 | params->cw_max, params->txop); |
1765 | params->cw_max, params->txop); | ||
1766 | 1764 | ||
1767 | ret = ath_txq_update(sc, txq->axq_qnum, &qi); | 1765 | ret = ath_txq_update(sc, txq->axq_qnum, &qi); |
1768 | if (ret) | 1766 | if (ret) |
@@ -1793,7 +1791,7 @@ static int ath9k_set_key(struct ieee80211_hw *hw, | |||
1793 | 1791 | ||
1794 | mutex_lock(&sc->mutex); | 1792 | mutex_lock(&sc->mutex); |
1795 | ath9k_ps_wakeup(sc); | 1793 | ath9k_ps_wakeup(sc); |
1796 | ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n"); | 1794 | ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n"); |
1797 | 1795 | ||
1798 | switch (cmd) { | 1796 | switch (cmd) { |
1799 | case SET_KEY: | 1797 | case SET_KEY: |
@@ -1852,9 +1850,8 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw, | |||
1852 | if (vif->type == NL80211_IFTYPE_ADHOC) | 1850 | if (vif->type == NL80211_IFTYPE_ADHOC) |
1853 | ath_update_chainmask(sc, 0); | 1851 | ath_update_chainmask(sc, 0); |
1854 | 1852 | ||
1855 | ath_print(common, ATH_DBG_CONFIG, | 1853 | ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n", |
1856 | "BSSID: %pM aid: 0x%x\n", | 1854 | common->curbssid, common->curaid); |
1857 | common->curbssid, common->curaid); | ||
1858 | 1855 | ||
1859 | /* need to reconfigure the beacon */ | 1856 | /* need to reconfigure the beacon */ |
1860 | sc->sc_flags &= ~SC_OP_BEACONS ; | 1857 | sc->sc_flags &= ~SC_OP_BEACONS ; |
@@ -1910,8 +1907,8 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw, | |||
1910 | } | 1907 | } |
1911 | 1908 | ||
1912 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { | 1909 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
1913 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", | 1910 | ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", |
1914 | bss_conf->use_short_preamble); | 1911 | bss_conf->use_short_preamble); |
1915 | if (bss_conf->use_short_preamble) | 1912 | if (bss_conf->use_short_preamble) |
1916 | sc->sc_flags |= SC_OP_PREAMBLE_SHORT; | 1913 | sc->sc_flags |= SC_OP_PREAMBLE_SHORT; |
1917 | else | 1914 | else |
@@ -1919,8 +1916,8 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw, | |||
1919 | } | 1916 | } |
1920 | 1917 | ||
1921 | if (changed & BSS_CHANGED_ERP_CTS_PROT) { | 1918 | if (changed & BSS_CHANGED_ERP_CTS_PROT) { |
1922 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", | 1919 | ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", |
1923 | bss_conf->use_cts_prot); | 1920 | bss_conf->use_cts_prot); |
1924 | if (bss_conf->use_cts_prot && | 1921 | if (bss_conf->use_cts_prot && |
1925 | hw->conf.channel->band != IEEE80211_BAND_5GHZ) | 1922 | hw->conf.channel->band != IEEE80211_BAND_5GHZ) |
1926 | sc->sc_flags |= SC_OP_PROTECT_ENABLE; | 1923 | sc->sc_flags |= SC_OP_PROTECT_ENABLE; |
@@ -1929,7 +1926,7 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw, | |||
1929 | } | 1926 | } |
1930 | 1927 | ||
1931 | if (changed & BSS_CHANGED_ASSOC) { | 1928 | if (changed & BSS_CHANGED_ASSOC) { |
1932 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n", | 1929 | ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n", |
1933 | bss_conf->assoc); | 1930 | bss_conf->assoc); |
1934 | ath9k_bss_assoc_info(sc, hw, vif, bss_conf); | 1931 | ath9k_bss_assoc_info(sc, hw, vif, bss_conf); |
1935 | } | 1932 | } |
diff --git a/drivers/net/wireless/ath/ath9k/rc.c b/drivers/net/wireless/ath/ath9k/rc.c index d8dcaab1829..2061a755a02 100644 --- a/drivers/net/wireless/ath/ath9k/rc.c +++ b/drivers/net/wireless/ath/ath9k/rc.c | |||
@@ -1184,7 +1184,7 @@ struct ath_rate_table *ath_choose_rate_table(struct ath_softc *sc, | |||
1184 | return &ar5416_11na_ratetable; | 1184 | return &ar5416_11na_ratetable; |
1185 | return &ar5416_11a_ratetable; | 1185 | return &ar5416_11a_ratetable; |
1186 | default: | 1186 | default: |
1187 | ath_print(common, ATH_DBG_CONFIG, "Invalid band\n"); | 1187 | ath_dbg(common, ATH_DBG_CONFIG, "Invalid band\n"); |
1188 | return NULL; | 1188 | return NULL; |
1189 | } | 1189 | } |
1190 | } | 1190 | } |
@@ -1259,9 +1259,9 @@ static void ath_rc_init(struct ath_softc *sc, | |||
1259 | ath_rc_priv->rate_max_phy = ath_rc_priv->valid_rate_index[k-4]; | 1259 | ath_rc_priv->rate_max_phy = ath_rc_priv->valid_rate_index[k-4]; |
1260 | ath_rc_priv->rate_table = rate_table; | 1260 | ath_rc_priv->rate_table = rate_table; |
1261 | 1261 | ||
1262 | ath_print(common, ATH_DBG_CONFIG, | 1262 | ath_dbg(common, ATH_DBG_CONFIG, |
1263 | "RC Initialized with capabilities: 0x%x\n", | 1263 | "RC Initialized with capabilities: 0x%x\n", |
1264 | ath_rc_priv->ht_cap); | 1264 | ath_rc_priv->ht_cap); |
1265 | } | 1265 | } |
1266 | 1266 | ||
1267 | static u8 ath_rc_build_ht_caps(struct ath_softc *sc, struct ieee80211_sta *sta, | 1267 | static u8 ath_rc_build_ht_caps(struct ath_softc *sc, struct ieee80211_sta *sta, |
@@ -1463,9 +1463,9 @@ static void ath_rate_update(void *priv, struct ieee80211_supported_band *sband, | |||
1463 | oper_cw40, oper_sgi); | 1463 | oper_cw40, oper_sgi); |
1464 | ath_rc_init(sc, priv_sta, sband, sta, rate_table); | 1464 | ath_rc_init(sc, priv_sta, sband, sta, rate_table); |
1465 | 1465 | ||
1466 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG, | 1466 | ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG, |
1467 | "Operating HT Bandwidth changed to: %d\n", | 1467 | "Operating HT Bandwidth changed to: %d\n", |
1468 | sc->hw->conf.channel_type); | 1468 | sc->hw->conf.channel_type); |
1469 | } | 1469 | } |
1470 | } | 1470 | } |
1471 | } | 1471 | } |
diff --git a/drivers/net/wireless/ath/ath9k/recv.c b/drivers/net/wireless/ath/ath9k/recv.c index c477be06894..70f3fa69c9a 100644 --- a/drivers/net/wireless/ath/ath9k/recv.c +++ b/drivers/net/wireless/ath/ath9k/recv.c | |||
@@ -165,7 +165,7 @@ static void ath_rx_addbuffer_edma(struct ath_softc *sc, | |||
165 | u32 nbuf = 0; | 165 | u32 nbuf = 0; |
166 | 166 | ||
167 | if (list_empty(&sc->rx.rxbuf)) { | 167 | if (list_empty(&sc->rx.rxbuf)) { |
168 | ath_print(common, ATH_DBG_QUEUE, "No free rx buf available\n"); | 168 | ath_dbg(common, ATH_DBG_QUEUE, "No free rx buf available\n"); |
169 | return; | 169 | return; |
170 | } | 170 | } |
171 | 171 | ||
@@ -327,8 +327,8 @@ int ath_rx_init(struct ath_softc *sc, int nbufs) | |||
327 | common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN, | 327 | common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN, |
328 | min(common->cachelsz, (u16)64)); | 328 | min(common->cachelsz, (u16)64)); |
329 | 329 | ||
330 | ath_print(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n", | 330 | ath_dbg(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n", |
331 | common->cachelsz, common->rx_bufsize); | 331 | common->cachelsz, common->rx_bufsize); |
332 | 332 | ||
333 | /* Initialize rx descriptors */ | 333 | /* Initialize rx descriptors */ |
334 | 334 | ||
@@ -590,9 +590,8 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb) | |||
590 | 590 | ||
591 | if (sc->ps_flags & PS_BEACON_SYNC) { | 591 | if (sc->ps_flags & PS_BEACON_SYNC) { |
592 | sc->ps_flags &= ~PS_BEACON_SYNC; | 592 | sc->ps_flags &= ~PS_BEACON_SYNC; |
593 | ath_print(common, ATH_DBG_PS, | 593 | ath_dbg(common, ATH_DBG_PS, |
594 | "Reconfigure Beacon timers based on " | 594 | "Reconfigure Beacon timers based on timestamp from the AP\n"); |
595 | "timestamp from the AP\n"); | ||
596 | ath_beacon_config(sc, NULL); | 595 | ath_beacon_config(sc, NULL); |
597 | } | 596 | } |
598 | 597 | ||
@@ -604,8 +603,8 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb) | |||
604 | * a backup trigger for returning into NETWORK SLEEP state, | 603 | * a backup trigger for returning into NETWORK SLEEP state, |
605 | * so we are waiting for it as well. | 604 | * so we are waiting for it as well. |
606 | */ | 605 | */ |
607 | ath_print(common, ATH_DBG_PS, "Received DTIM beacon indicating " | 606 | ath_dbg(common, ATH_DBG_PS, |
608 | "buffered broadcast/multicast frame(s)\n"); | 607 | "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n"); |
609 | sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON; | 608 | sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON; |
610 | return; | 609 | return; |
611 | } | 610 | } |
@@ -617,8 +616,8 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb) | |||
617 | * been delivered. | 616 | * been delivered. |
618 | */ | 617 | */ |
619 | sc->ps_flags &= ~PS_WAIT_FOR_CAB; | 618 | sc->ps_flags &= ~PS_WAIT_FOR_CAB; |
620 | ath_print(common, ATH_DBG_PS, | 619 | ath_dbg(common, ATH_DBG_PS, |
621 | "PS wait for CAB frames timed out\n"); | 620 | "PS wait for CAB frames timed out\n"); |
622 | } | 621 | } |
623 | } | 622 | } |
624 | 623 | ||
@@ -643,15 +642,14 @@ static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb) | |||
643 | * point. | 642 | * point. |
644 | */ | 643 | */ |
645 | sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON); | 644 | sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON); |
646 | ath_print(common, ATH_DBG_PS, | 645 | ath_dbg(common, ATH_DBG_PS, |
647 | "All PS CAB frames received, back to sleep\n"); | 646 | "All PS CAB frames received, back to sleep\n"); |
648 | } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) && | 647 | } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) && |
649 | !is_multicast_ether_addr(hdr->addr1) && | 648 | !is_multicast_ether_addr(hdr->addr1) && |
650 | !ieee80211_has_morefrags(hdr->frame_control)) { | 649 | !ieee80211_has_morefrags(hdr->frame_control)) { |
651 | sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA; | 650 | sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA; |
652 | ath_print(common, ATH_DBG_PS, | 651 | ath_dbg(common, ATH_DBG_PS, |
653 | "Going back to sleep after having received " | 652 | "Going back to sleep after having received PS-Poll data (0x%lx)\n", |
654 | "PS-Poll data (0x%lx)\n", | ||
655 | sc->ps_flags & (PS_WAIT_FOR_BEACON | | 653 | sc->ps_flags & (PS_WAIT_FOR_BEACON | |
656 | PS_WAIT_FOR_CAB | | 654 | PS_WAIT_FOR_CAB | |
657 | PS_WAIT_FOR_PSPOLL_DATA | | 655 | PS_WAIT_FOR_PSPOLL_DATA | |
@@ -953,8 +951,9 @@ static int ath9k_process_rate(struct ath_common *common, | |||
953 | * No valid hardware bitrate found -- we should not get here | 951 | * No valid hardware bitrate found -- we should not get here |
954 | * because hardware has already validated this frame as OK. | 952 | * because hardware has already validated this frame as OK. |
955 | */ | 953 | */ |
956 | ath_print(common, ATH_DBG_XMIT, "unsupported hw bitrate detected " | 954 | ath_dbg(common, ATH_DBG_XMIT, |
957 | "0x%02x using 1 Mbit\n", rx_stats->rs_rate); | 955 | "unsupported hw bitrate detected 0x%02x using 1 Mbit\n", |
956 | rx_stats->rs_rate); | ||
958 | 957 | ||
959 | return -EINVAL; | 958 | return -EINVAL; |
960 | } | 959 | } |
diff --git a/drivers/net/wireless/ath/ath9k/virtual.c b/drivers/net/wireless/ath/ath9k/virtual.c index d5442c3745c..fbfbc823997 100644 --- a/drivers/net/wireless/ath/ath9k/virtual.c +++ b/drivers/net/wireless/ath/ath9k/virtual.c | |||
@@ -656,10 +656,9 @@ void ath9k_set_wiphy_idle(struct ath_wiphy *aphy, bool idle) | |||
656 | struct ath_softc *sc = aphy->sc; | 656 | struct ath_softc *sc = aphy->sc; |
657 | 657 | ||
658 | aphy->idle = idle; | 658 | aphy->idle = idle; |
659 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG, | 659 | ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG, |
660 | "Marking %s as %s\n", | 660 | "Marking %s as %sidle\n", |
661 | wiphy_name(aphy->hw->wiphy), | 661 | wiphy_name(aphy->hw->wiphy), idle ? "" : "not-"); |
662 | idle ? "idle" : "not-idle"); | ||
663 | } | 662 | } |
664 | /* Only bother starting a queue on an active virtual wiphy */ | 663 | /* Only bother starting a queue on an active virtual wiphy */ |
665 | bool ath_mac80211_start_queue(struct ath_softc *sc, u16 skb_queue) | 664 | bool ath_mac80211_start_queue(struct ath_softc *sc, u16 skb_queue) |
diff --git a/drivers/net/wireless/ath/ath9k/wmi.c b/drivers/net/wireless/ath/ath9k/wmi.c index 93a8bda09c2..8f42ea78198 100644 --- a/drivers/net/wireless/ath/ath9k/wmi.c +++ b/drivers/net/wireless/ath/ath9k/wmi.c | |||
@@ -125,7 +125,7 @@ void ath9k_wmi_tasklet(unsigned long data) | |||
125 | struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *)data; | 125 | struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *)data; |
126 | struct ath_common *common = ath9k_hw_common(priv->ah); | 126 | struct ath_common *common = ath9k_hw_common(priv->ah); |
127 | 127 | ||
128 | ath_print(common, ATH_DBG_WMI, "SWBA Event received\n"); | 128 | ath_dbg(common, ATH_DBG_WMI, "SWBA Event received\n"); |
129 | 129 | ||
130 | ath9k_htc_swba(priv, priv->wmi->beacon_pending); | 130 | ath9k_htc_swba(priv, priv->wmi->beacon_pending); |
131 | 131 | ||
@@ -286,9 +286,9 @@ int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id, | |||
286 | 286 | ||
287 | time_left = wait_for_completion_timeout(&wmi->cmd_wait, timeout); | 287 | time_left = wait_for_completion_timeout(&wmi->cmd_wait, timeout); |
288 | if (!time_left) { | 288 | if (!time_left) { |
289 | ath_print(common, ATH_DBG_WMI, | 289 | ath_dbg(common, ATH_DBG_WMI, |
290 | "Timeout waiting for WMI command: %s\n", | 290 | "Timeout waiting for WMI command: %s\n", |
291 | wmi_cmd_to_name(cmd_id)); | 291 | wmi_cmd_to_name(cmd_id)); |
292 | mutex_unlock(&wmi->op_mutex); | 292 | mutex_unlock(&wmi->op_mutex); |
293 | return -ETIMEDOUT; | 293 | return -ETIMEDOUT; |
294 | } | 294 | } |
@@ -298,8 +298,8 @@ int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id, | |||
298 | return 0; | 298 | return 0; |
299 | 299 | ||
300 | out: | 300 | out: |
301 | ath_print(common, ATH_DBG_WMI, | 301 | ath_dbg(common, ATH_DBG_WMI, |
302 | "WMI failure for: %s\n", wmi_cmd_to_name(cmd_id)); | 302 | "WMI failure for: %s\n", wmi_cmd_to_name(cmd_id)); |
303 | mutex_unlock(&wmi->op_mutex); | 303 | mutex_unlock(&wmi->op_mutex); |
304 | kfree_skb(skb); | 304 | kfree_skb(skb); |
305 | 305 | ||
diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c index d26449c91d5..16d83d0c095 100644 --- a/drivers/net/wireless/ath/ath9k/xmit.c +++ b/drivers/net/wireless/ath/ath9k/xmit.c | |||
@@ -1285,8 +1285,8 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, | |||
1285 | 1285 | ||
1286 | bf = list_first_entry(head, struct ath_buf, list); | 1286 | bf = list_first_entry(head, struct ath_buf, list); |
1287 | 1287 | ||
1288 | ath_print(common, ATH_DBG_QUEUE, | 1288 | ath_dbg(common, ATH_DBG_QUEUE, |
1289 | "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth); | 1289 | "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth); |
1290 | 1290 | ||
1291 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { | 1291 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
1292 | if (txq->axq_depth >= ATH_TXFIFO_DEPTH) { | 1292 | if (txq->axq_depth >= ATH_TXFIFO_DEPTH) { |
@@ -1294,32 +1294,29 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, | |||
1294 | return; | 1294 | return; |
1295 | } | 1295 | } |
1296 | if (!list_empty(&txq->txq_fifo[txq->txq_headidx])) | 1296 | if (!list_empty(&txq->txq_fifo[txq->txq_headidx])) |
1297 | ath_print(common, ATH_DBG_XMIT, | 1297 | ath_dbg(common, ATH_DBG_XMIT, |
1298 | "Initializing tx fifo %d which " | 1298 | "Initializing tx fifo %d which is non-empty\n", |
1299 | "is non-empty\n", | 1299 | txq->txq_headidx); |
1300 | txq->txq_headidx); | ||
1301 | INIT_LIST_HEAD(&txq->txq_fifo[txq->txq_headidx]); | 1300 | INIT_LIST_HEAD(&txq->txq_fifo[txq->txq_headidx]); |
1302 | list_splice_init(head, &txq->txq_fifo[txq->txq_headidx]); | 1301 | list_splice_init(head, &txq->txq_fifo[txq->txq_headidx]); |
1303 | INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH); | 1302 | INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH); |
1304 | ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); | 1303 | ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); |
1305 | ath_print(common, ATH_DBG_XMIT, | 1304 | ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n", |
1306 | "TXDP[%u] = %llx (%p)\n", | 1305 | txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); |
1307 | txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); | ||
1308 | } else { | 1306 | } else { |
1309 | list_splice_tail_init(head, &txq->axq_q); | 1307 | list_splice_tail_init(head, &txq->axq_q); |
1310 | 1308 | ||
1311 | if (txq->axq_link == NULL) { | 1309 | if (txq->axq_link == NULL) { |
1312 | ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); | 1310 | ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); |
1313 | ath_print(common, ATH_DBG_XMIT, | 1311 | ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n", |
1314 | "TXDP[%u] = %llx (%p)\n", | 1312 | txq->axq_qnum, ito64(bf->bf_daddr), |
1315 | txq->axq_qnum, ito64(bf->bf_daddr), | 1313 | bf->bf_desc); |
1316 | bf->bf_desc); | ||
1317 | } else { | 1314 | } else { |
1318 | *txq->axq_link = bf->bf_daddr; | 1315 | *txq->axq_link = bf->bf_daddr; |
1319 | ath_print(common, ATH_DBG_XMIT, | 1316 | ath_dbg(common, ATH_DBG_XMIT, |
1320 | "link[%u] (%p)=%llx (%p)\n", | 1317 | "link[%u] (%p)=%llx (%p)\n", |
1321 | txq->axq_qnum, txq->axq_link, | 1318 | txq->axq_qnum, txq->axq_link, |
1322 | ito64(bf->bf_daddr), bf->bf_desc); | 1319 | ito64(bf->bf_daddr), bf->bf_desc); |
1323 | } | 1320 | } |
1324 | ath9k_hw_get_desc_link(ah, bf->bf_lastbf->bf_desc, | 1321 | ath9k_hw_get_desc_link(ah, bf->bf_lastbf->bf_desc, |
1325 | &txq->axq_link); | 1322 | &txq->axq_link); |
@@ -1646,7 +1643,7 @@ static struct ath_buf *ath_tx_setup_buffer(struct ieee80211_hw *hw, | |||
1646 | 1643 | ||
1647 | bf = ath_tx_get_buffer(sc); | 1644 | bf = ath_tx_get_buffer(sc); |
1648 | if (!bf) { | 1645 | if (!bf) { |
1649 | ath_print(common, ATH_DBG_XMIT, "TX buffers are full\n"); | 1646 | ath_dbg(common, ATH_DBG_XMIT, "TX buffers are full\n"); |
1650 | return NULL; | 1647 | return NULL; |
1651 | } | 1648 | } |
1652 | 1649 | ||
@@ -1809,7 +1806,7 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, | |||
1809 | struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data; | 1806 | struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data; |
1810 | int q, padpos, padsize; | 1807 | int q, padpos, padsize; |
1811 | 1808 | ||
1812 | ath_print(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb); | 1809 | ath_dbg(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb); |
1813 | 1810 | ||
1814 | if (aphy) | 1811 | if (aphy) |
1815 | hw = aphy->hw; | 1812 | hw = aphy->hw; |
@@ -1835,9 +1832,8 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, | |||
1835 | 1832 | ||
1836 | if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) { | 1833 | if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) { |
1837 | sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK; | 1834 | sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK; |
1838 | ath_print(common, ATH_DBG_PS, | 1835 | ath_dbg(common, ATH_DBG_PS, |
1839 | "Going back to sleep after having " | 1836 | "Going back to sleep after having received TX status (0x%lx)\n", |
1840 | "received TX status (0x%lx)\n", | ||
1841 | sc->ps_flags & (PS_WAIT_FOR_BEACON | | 1837 | sc->ps_flags & (PS_WAIT_FOR_BEACON | |
1842 | PS_WAIT_FOR_CAB | | 1838 | PS_WAIT_FOR_CAB | |
1843 | PS_WAIT_FOR_PSPOLL_DATA | | 1839 | PS_WAIT_FOR_PSPOLL_DATA | |
@@ -1986,9 +1982,9 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) | |||
1986 | int status; | 1982 | int status; |
1987 | int qnum; | 1983 | int qnum; |
1988 | 1984 | ||
1989 | ath_print(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n", | 1985 | ath_dbg(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n", |
1990 | txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), | 1986 | txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), |
1991 | txq->axq_link); | 1987 | txq->axq_link); |
1992 | 1988 | ||
1993 | for (;;) { | 1989 | for (;;) { |
1994 | spin_lock_bh(&txq->axq_lock); | 1990 | spin_lock_bh(&txq->axq_lock); |
@@ -2103,8 +2099,8 @@ static void ath_tx_complete_poll_work(struct work_struct *work) | |||
2103 | } | 2099 | } |
2104 | 2100 | ||
2105 | if (needreset) { | 2101 | if (needreset) { |
2106 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET, | 2102 | ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET, |
2107 | "tx hung, resetting the chip\n"); | 2103 | "tx hung, resetting the chip\n"); |
2108 | ath9k_ps_wakeup(sc); | 2104 | ath9k_ps_wakeup(sc); |
2109 | ath_reset(sc, true); | 2105 | ath_reset(sc, true); |
2110 | ath9k_ps_restore(sc); | 2106 | ath9k_ps_restore(sc); |
@@ -2146,8 +2142,8 @@ void ath_tx_edma_tasklet(struct ath_softc *sc) | |||
2146 | if (status == -EINPROGRESS) | 2142 | if (status == -EINPROGRESS) |
2147 | break; | 2143 | break; |
2148 | if (status == -EIO) { | 2144 | if (status == -EIO) { |
2149 | ath_print(common, ATH_DBG_XMIT, | 2145 | ath_dbg(common, ATH_DBG_XMIT, |
2150 | "Error processing tx status\n"); | 2146 | "Error processing tx status\n"); |
2151 | break; | 2147 | break; |
2152 | } | 2148 | } |
2153 | 2149 | ||
diff --git a/drivers/net/wireless/ath/debug.h b/drivers/net/wireless/ath/debug.h deleted file mode 100644 index cec951cdfac..00000000000 --- a/drivers/net/wireless/ath/debug.h +++ /dev/null | |||
@@ -1,22 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2008-2009 Atheros Communications Inc. | ||
3 | * | ||
4 | * Permission to use, copy, modify, and/or distribute this software for any | ||
5 | * purpose with or without fee is hereby granted, provided that the above | ||
6 | * copyright notice and this permission notice appear in all copies. | ||
7 | * | ||
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
15 | */ | ||
16 | |||
17 | #ifndef ATH_DEBUG_H | ||
18 | #define ATH_DEBUG_H | ||
19 | |||
20 | #define ath_print ath_dbg | ||
21 | |||
22 | #endif /* ATH_DEBUG_H */ | ||
diff --git a/drivers/net/wireless/ath/key.c b/drivers/net/wireless/ath/key.c index 3a4769506ce..29a2961af5f 100644 --- a/drivers/net/wireless/ath/key.c +++ b/drivers/net/wireless/ath/key.c | |||
@@ -20,7 +20,6 @@ | |||
20 | 20 | ||
21 | #include "ath.h" | 21 | #include "ath.h" |
22 | #include "reg.h" | 22 | #include "reg.h" |
23 | #include "debug.h" | ||
24 | 23 | ||
25 | #define REG_READ (common->ops->read) | 24 | #define REG_READ (common->ops->read) |
26 | #define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg) | 25 | #define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg) |
@@ -125,8 +124,8 @@ static bool ath_hw_set_keycache_entry(struct ath_common *common, u16 entry, | |||
125 | break; | 124 | break; |
126 | case ATH_CIPHER_AES_CCM: | 125 | case ATH_CIPHER_AES_CCM: |
127 | if (!(common->crypt_caps & ATH_CRYPT_CAP_CIPHER_AESCCM)) { | 126 | if (!(common->crypt_caps & ATH_CRYPT_CAP_CIPHER_AESCCM)) { |
128 | ath_print(common, ATH_DBG_ANY, | 127 | ath_dbg(common, ATH_DBG_ANY, |
129 | "AES-CCM not supported by this mac rev\n"); | 128 | "AES-CCM not supported by this mac rev\n"); |
130 | return false; | 129 | return false; |
131 | } | 130 | } |
132 | keyType = AR_KEYTABLE_TYPE_CCM; | 131 | keyType = AR_KEYTABLE_TYPE_CCM; |
@@ -134,15 +133,15 @@ static bool ath_hw_set_keycache_entry(struct ath_common *common, u16 entry, | |||
134 | case ATH_CIPHER_TKIP: | 133 | case ATH_CIPHER_TKIP: |
135 | keyType = AR_KEYTABLE_TYPE_TKIP; | 134 | keyType = AR_KEYTABLE_TYPE_TKIP; |
136 | if (entry + 64 >= common->keymax) { | 135 | if (entry + 64 >= common->keymax) { |
137 | ath_print(common, ATH_DBG_ANY, | 136 | ath_dbg(common, ATH_DBG_ANY, |
138 | "entry %u inappropriate for TKIP\n", entry); | 137 | "entry %u inappropriate for TKIP\n", entry); |
139 | return false; | 138 | return false; |
140 | } | 139 | } |
141 | break; | 140 | break; |
142 | case ATH_CIPHER_WEP: | 141 | case ATH_CIPHER_WEP: |
143 | if (k->kv_len < WLAN_KEY_LEN_WEP40) { | 142 | if (k->kv_len < WLAN_KEY_LEN_WEP40) { |
144 | ath_print(common, ATH_DBG_ANY, | 143 | ath_dbg(common, ATH_DBG_ANY, |
145 | "WEP key length %u too small\n", k->kv_len); | 144 | "WEP key length %u too small\n", k->kv_len); |
146 | return false; | 145 | return false; |
147 | } | 146 | } |
148 | if (k->kv_len <= WLAN_KEY_LEN_WEP40) | 147 | if (k->kv_len <= WLAN_KEY_LEN_WEP40) |