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authorIvo van Doorn <ivdoorn@gmail.com>2009-10-15 16:04:14 -0400
committerJohn W. Linville <linville@tuxdriver.com>2009-10-27 16:48:22 -0400
commita9b3a9f7214b3acc56330c2257aeaa5fa85bf520 (patch)
tree494dab0851de7ba2b3d34d21aac7bb78f46f89c8 /drivers/net/wireless/rt2x00/rt2800pci.c
parent5d78d34ba2d4a044983b599a697dc1d71af38c96 (diff)
rt2x00: Implement support for rt2800pci
Add support for the rt2860/rt3090 chipsets from Ralink. Includes various patches from a lot of people who helped getting this driver into the current shape. Signed-off-by: Alban Browaeys <prahal@yahoo.com> Signed-off-by: Benoit PAPILLAULT <benoit.papillault@free.fr> Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: Luis Correia <luis.f.correia@gmail.com> Signed-off-by: Mattias Nissler <mattias.nissler@gmx.de> Signed-off-by: Mark Asselstine <asselsm@gmail.com> Signed-off-by: Xose Vazquez Perez <xose.vazquez@gmail.com> Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/rt2x00/rt2800pci.c')
-rw-r--r--drivers/net/wireless/rt2x00/rt2800pci.c3323
1 files changed, 3323 insertions, 0 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2800pci.c b/drivers/net/wireless/rt2x00/rt2800pci.c
new file mode 100644
index 00000000000..be81788b80c
--- /dev/null
+++ b/drivers/net/wireless/rt2x00/rt2800pci.c
@@ -0,0 +1,3323 @@
1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2800pci
23 Abstract: rt2800pci device specific routines.
24 Supported chipsets: RT2800E & RT2800ED.
25 */
26
27#include <linux/crc-ccitt.h>
28#include <linux/delay.h>
29#include <linux/etherdevice.h>
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/pci.h>
34#include <linux/platform_device.h>
35#include <linux/eeprom_93cx6.h>
36
37#include "rt2x00.h"
38#include "rt2x00pci.h"
39#include "rt2x00soc.h"
40#include "rt2800pci.h"
41
42#ifdef CONFIG_RT2800PCI_PCI_MODULE
43#define CONFIG_RT2800PCI_PCI
44#endif
45
46#ifdef CONFIG_RT2800PCI_WISOC_MODULE
47#define CONFIG_RT2800PCI_WISOC
48#endif
49
50/*
51 * Allow hardware encryption to be disabled.
52 */
53static int modparam_nohwcrypt = 1;
54module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
55MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
56
57/*
58 * Register access.
59 * BBP and RF register require indirect register access,
60 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
61 * These indirect registers work with busy bits,
62 * and we will try maximal REGISTER_BUSY_COUNT times to access
63 * the register while taking a REGISTER_BUSY_DELAY us delay
64 * between each attampt. When the busy bit is still set at that time,
65 * the access attempt is considered to have failed,
66 * and we will print an error.
67 */
68#define WAIT_FOR_BBP(__dev, __reg) \
69 rt2x00pci_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
70#define WAIT_FOR_RFCSR(__dev, __reg) \
71 rt2x00pci_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
72#define WAIT_FOR_RF(__dev, __reg) \
73 rt2x00pci_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
74#define WAIT_FOR_MCU(__dev, __reg) \
75 rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
76 H2M_MAILBOX_CSR_OWNER, (__reg))
77
78static void rt2800pci_bbp_write(struct rt2x00_dev *rt2x00dev,
79 const unsigned int word, const u8 value)
80{
81 u32 reg;
82
83 mutex_lock(&rt2x00dev->csr_mutex);
84
85 /*
86 * Wait until the BBP becomes available, afterwards we
87 * can safely write the new data into the register.
88 */
89 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
90 reg = 0;
91 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
92 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
93 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
94 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
95 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
96
97 rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
98 }
99
100 mutex_unlock(&rt2x00dev->csr_mutex);
101}
102
103static void rt2800pci_bbp_read(struct rt2x00_dev *rt2x00dev,
104 const unsigned int word, u8 *value)
105{
106 u32 reg;
107
108 mutex_lock(&rt2x00dev->csr_mutex);
109
110 /*
111 * Wait until the BBP becomes available, afterwards we
112 * can safely write the read request into the register.
113 * After the data has been written, we wait until hardware
114 * returns the correct value, if at any time the register
115 * doesn't become available in time, reg will be 0xffffffff
116 * which means we return 0xff to the caller.
117 */
118 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
119 reg = 0;
120 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
121 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
122 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
123 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
124
125 rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
126
127 WAIT_FOR_BBP(rt2x00dev, &reg);
128 }
129
130 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
131
132 mutex_unlock(&rt2x00dev->csr_mutex);
133}
134
135static void rt2800pci_rfcsr_write(struct rt2x00_dev *rt2x00dev,
136 const unsigned int word, const u8 value)
137{
138 u32 reg;
139
140 mutex_lock(&rt2x00dev->csr_mutex);
141
142 /*
143 * Wait until the RFCSR becomes available, afterwards we
144 * can safely write the new data into the register.
145 */
146 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
147 reg = 0;
148 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
149 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
150 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
151 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
152
153 rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG, reg);
154 }
155
156 mutex_unlock(&rt2x00dev->csr_mutex);
157}
158
159static void rt2800pci_rfcsr_read(struct rt2x00_dev *rt2x00dev,
160 const unsigned int word, u8 *value)
161{
162 u32 reg;
163
164 mutex_lock(&rt2x00dev->csr_mutex);
165
166 /*
167 * Wait until the RFCSR becomes available, afterwards we
168 * can safely write the read request into the register.
169 * After the data has been written, we wait until hardware
170 * returns the correct value, if at any time the register
171 * doesn't become available in time, reg will be 0xffffffff
172 * which means we return 0xff to the caller.
173 */
174 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
175 reg = 0;
176 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
177 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
178 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
179
180 rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG, reg);
181
182 WAIT_FOR_RFCSR(rt2x00dev, &reg);
183 }
184
185 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
186
187 mutex_unlock(&rt2x00dev->csr_mutex);
188}
189
190static void rt2800pci_rf_write(struct rt2x00_dev *rt2x00dev,
191 const unsigned int word, const u32 value)
192{
193 u32 reg;
194
195 mutex_lock(&rt2x00dev->csr_mutex);
196
197 /*
198 * Wait until the RF becomes available, afterwards we
199 * can safely write the new data into the register.
200 */
201 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
202 reg = 0;
203 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
204 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
205 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
206 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
207
208 rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG0, reg);
209 rt2x00_rf_write(rt2x00dev, word, value);
210 }
211
212 mutex_unlock(&rt2x00dev->csr_mutex);
213}
214
215static void rt2800pci_mcu_request(struct rt2x00_dev *rt2x00dev,
216 const u8 command, const u8 token,
217 const u8 arg0, const u8 arg1)
218{
219 u32 reg;
220
221 /*
222 * RT2880 and RT3052 don't support MCU requests.
223 */
224 if (rt2x00_rt(&rt2x00dev->chip, RT2880) ||
225 rt2x00_rt(&rt2x00dev->chip, RT3052))
226 return;
227
228 mutex_lock(&rt2x00dev->csr_mutex);
229
230 /*
231 * Wait until the MCU becomes available, afterwards we
232 * can safely write the new data into the register.
233 */
234 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
235 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
236 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
237 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
238 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
239 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
240
241 reg = 0;
242 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
243 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
244 }
245
246 mutex_unlock(&rt2x00dev->csr_mutex);
247}
248
249static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
250{
251 unsigned int i;
252 u32 reg;
253
254 for (i = 0; i < 200; i++) {
255 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
256
257 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
258 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
259 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
260 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
261 break;
262
263 udelay(REGISTER_BUSY_DELAY);
264 }
265
266 if (i == 200)
267 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
268
269 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
270 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
271}
272
273#ifdef CONFIG_RT2800PCI_WISOC
274static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
275{
276 u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */
277
278 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
279}
280#else
281static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
282{
283}
284#endif /* CONFIG_RT2800PCI_WISOC */
285
286#ifdef CONFIG_RT2800PCI_PCI
287static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
288{
289 struct rt2x00_dev *rt2x00dev = eeprom->data;
290 u32 reg;
291
292 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
293
294 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
295 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
296 eeprom->reg_data_clock =
297 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
298 eeprom->reg_chip_select =
299 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
300}
301
302static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
303{
304 struct rt2x00_dev *rt2x00dev = eeprom->data;
305 u32 reg = 0;
306
307 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
308 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
309 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
310 !!eeprom->reg_data_clock);
311 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
312 !!eeprom->reg_chip_select);
313
314 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
315}
316
317static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
318{
319 struct eeprom_93cx6 eeprom;
320 u32 reg;
321
322 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
323
324 eeprom.data = rt2x00dev;
325 eeprom.register_read = rt2800pci_eepromregister_read;
326 eeprom.register_write = rt2800pci_eepromregister_write;
327 eeprom.width = !rt2x00_get_field32(reg, E2PROM_CSR_TYPE) ?
328 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
329 eeprom.reg_data_in = 0;
330 eeprom.reg_data_out = 0;
331 eeprom.reg_data_clock = 0;
332 eeprom.reg_chip_select = 0;
333
334 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
335 EEPROM_SIZE / sizeof(u16));
336}
337
338static void rt2800pci_efuse_read(struct rt2x00_dev *rt2x00dev,
339 unsigned int i)
340{
341 u32 reg;
342
343 rt2x00pci_register_read(rt2x00dev, EFUSE_CTRL, &reg);
344 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
345 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
346 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
347 rt2x00pci_register_write(rt2x00dev, EFUSE_CTRL, reg);
348
349 /* Wait until the EEPROM has been loaded */
350 rt2x00pci_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
351
352 /* Apparently the data is read from end to start */
353 rt2x00pci_register_read(rt2x00dev, EFUSE_DATA3,
354 (u32 *)&rt2x00dev->eeprom[i]);
355 rt2x00pci_register_read(rt2x00dev, EFUSE_DATA2,
356 (u32 *)&rt2x00dev->eeprom[i + 2]);
357 rt2x00pci_register_read(rt2x00dev, EFUSE_DATA1,
358 (u32 *)&rt2x00dev->eeprom[i + 4]);
359 rt2x00pci_register_read(rt2x00dev, EFUSE_DATA0,
360 (u32 *)&rt2x00dev->eeprom[i + 6]);
361}
362
363static void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
364{
365 unsigned int i;
366
367 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
368 rt2800pci_efuse_read(rt2x00dev, i);
369}
370#else
371static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
372{
373}
374
375static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
376{
377}
378#endif /* CONFIG_RT2800PCI_PCI */
379
380#ifdef CONFIG_RT2X00_LIB_DEBUGFS
381static const struct rt2x00debug rt2800pci_rt2x00debug = {
382 .owner = THIS_MODULE,
383 .csr = {
384 .read = rt2x00pci_register_read,
385 .write = rt2x00pci_register_write,
386 .flags = RT2X00DEBUGFS_OFFSET,
387 .word_base = CSR_REG_BASE,
388 .word_size = sizeof(u32),
389 .word_count = CSR_REG_SIZE / sizeof(u32),
390 },
391 .eeprom = {
392 .read = rt2x00_eeprom_read,
393 .write = rt2x00_eeprom_write,
394 .word_base = EEPROM_BASE,
395 .word_size = sizeof(u16),
396 .word_count = EEPROM_SIZE / sizeof(u16),
397 },
398 .bbp = {
399 .read = rt2800pci_bbp_read,
400 .write = rt2800pci_bbp_write,
401 .word_base = BBP_BASE,
402 .word_size = sizeof(u8),
403 .word_count = BBP_SIZE / sizeof(u8),
404 },
405 .rf = {
406 .read = rt2x00_rf_read,
407 .write = rt2800pci_rf_write,
408 .word_base = RF_BASE,
409 .word_size = sizeof(u32),
410 .word_count = RF_SIZE / sizeof(u32),
411 },
412};
413#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
414
415static int rt2800pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
416{
417 u32 reg;
418
419 rt2x00pci_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
420 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
421}
422
423#ifdef CONFIG_RT2X00_LIB_LEDS
424static void rt2800pci_brightness_set(struct led_classdev *led_cdev,
425 enum led_brightness brightness)
426{
427 struct rt2x00_led *led =
428 container_of(led_cdev, struct rt2x00_led, led_dev);
429 unsigned int enabled = brightness != LED_OFF;
430 unsigned int bg_mode =
431 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
432 unsigned int polarity =
433 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
434 EEPROM_FREQ_LED_POLARITY);
435 unsigned int ledmode =
436 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
437 EEPROM_FREQ_LED_MODE);
438
439 if (led->type == LED_TYPE_RADIO) {
440 rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
441 enabled ? 0x20 : 0);
442 } else if (led->type == LED_TYPE_ASSOC) {
443 rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
444 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
445 } else if (led->type == LED_TYPE_QUALITY) {
446 /*
447 * The brightness is divided into 6 levels (0 - 5),
448 * The specs tell us the following levels:
449 * 0, 1 ,3, 7, 15, 31
450 * to determine the level in a simple way we can simply
451 * work with bitshifting:
452 * (1 << level) - 1
453 */
454 rt2800pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
455 (1 << brightness / (LED_FULL / 6)) - 1,
456 polarity);
457 }
458}
459
460static int rt2800pci_blink_set(struct led_classdev *led_cdev,
461 unsigned long *delay_on,
462 unsigned long *delay_off)
463{
464 struct rt2x00_led *led =
465 container_of(led_cdev, struct rt2x00_led, led_dev);
466 u32 reg;
467
468 rt2x00pci_register_read(led->rt2x00dev, LED_CFG, &reg);
469 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
470 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
471 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
472 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
473 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
474 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
475 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
476 rt2x00pci_register_write(led->rt2x00dev, LED_CFG, reg);
477
478 return 0;
479}
480
481static void rt2800pci_init_led(struct rt2x00_dev *rt2x00dev,
482 struct rt2x00_led *led,
483 enum led_type type)
484{
485 led->rt2x00dev = rt2x00dev;
486 led->type = type;
487 led->led_dev.brightness_set = rt2800pci_brightness_set;
488 led->led_dev.blink_set = rt2800pci_blink_set;
489 led->flags = LED_INITIALIZED;
490}
491#endif /* CONFIG_RT2X00_LIB_LEDS */
492
493/*
494 * Configuration handlers.
495 */
496static void rt2800pci_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
497 struct rt2x00lib_crypto *crypto,
498 struct ieee80211_key_conf *key)
499{
500 struct mac_wcid_entry wcid_entry;
501 struct mac_iveiv_entry iveiv_entry;
502 u32 offset;
503 u32 reg;
504
505 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
506
507 rt2x00pci_register_read(rt2x00dev, offset, &reg);
508 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
509 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
510 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
511 (crypto->cmd == SET_KEY) * crypto->cipher);
512 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
513 (crypto->cmd == SET_KEY) * crypto->bssidx);
514 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
515 rt2x00pci_register_write(rt2x00dev, offset, reg);
516
517 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
518
519 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
520 if ((crypto->cipher == CIPHER_TKIP) ||
521 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
522 (crypto->cipher == CIPHER_AES))
523 iveiv_entry.iv[3] |= 0x20;
524 iveiv_entry.iv[3] |= key->keyidx << 6;
525 rt2x00pci_register_multiwrite(rt2x00dev, offset,
526 &iveiv_entry, sizeof(iveiv_entry));
527
528 offset = MAC_WCID_ENTRY(key->hw_key_idx);
529
530 memset(&wcid_entry, 0, sizeof(wcid_entry));
531 if (crypto->cmd == SET_KEY)
532 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
533 rt2x00pci_register_multiwrite(rt2x00dev, offset,
534 &wcid_entry, sizeof(wcid_entry));
535}
536
537static int rt2800pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
538 struct rt2x00lib_crypto *crypto,
539 struct ieee80211_key_conf *key)
540{
541 struct hw_key_entry key_entry;
542 struct rt2x00_field32 field;
543 u32 offset;
544 u32 reg;
545
546 if (crypto->cmd == SET_KEY) {
547 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
548
549 memcpy(key_entry.key, crypto->key,
550 sizeof(key_entry.key));
551 memcpy(key_entry.tx_mic, crypto->tx_mic,
552 sizeof(key_entry.tx_mic));
553 memcpy(key_entry.rx_mic, crypto->rx_mic,
554 sizeof(key_entry.rx_mic));
555
556 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
557 rt2x00pci_register_multiwrite(rt2x00dev, offset,
558 &key_entry, sizeof(key_entry));
559 }
560
561 /*
562 * The cipher types are stored over multiple registers
563 * starting with SHARED_KEY_MODE_BASE each word will have
564 * 32 bits and contains the cipher types for 2 bssidx each.
565 * Using the correct defines correctly will cause overhead,
566 * so just calculate the correct offset.
567 */
568 field.bit_offset = 4 * (key->hw_key_idx % 8);
569 field.bit_mask = 0x7 << field.bit_offset;
570
571 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
572
573 rt2x00pci_register_read(rt2x00dev, offset, &reg);
574 rt2x00_set_field32(&reg, field,
575 (crypto->cmd == SET_KEY) * crypto->cipher);
576 rt2x00pci_register_write(rt2x00dev, offset, reg);
577
578 /*
579 * Update WCID information
580 */
581 rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
582
583 return 0;
584}
585
586static int rt2800pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
587 struct rt2x00lib_crypto *crypto,
588 struct ieee80211_key_conf *key)
589{
590 struct hw_key_entry key_entry;
591 u32 offset;
592
593 if (crypto->cmd == SET_KEY) {
594 /*
595 * 1 pairwise key is possible per AID, this means that the AID
596 * equals our hw_key_idx. Make sure the WCID starts _after_ the
597 * last possible shared key entry.
598 */
599 if (crypto->aid > (256 - 32))
600 return -ENOSPC;
601
602 key->hw_key_idx = 32 + crypto->aid;
603
604
605 memcpy(key_entry.key, crypto->key,
606 sizeof(key_entry.key));
607 memcpy(key_entry.tx_mic, crypto->tx_mic,
608 sizeof(key_entry.tx_mic));
609 memcpy(key_entry.rx_mic, crypto->rx_mic,
610 sizeof(key_entry.rx_mic));
611
612 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
613 rt2x00pci_register_multiwrite(rt2x00dev, offset,
614 &key_entry, sizeof(key_entry));
615 }
616
617 /*
618 * Update WCID information
619 */
620 rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
621
622 return 0;
623}
624
625static void rt2800pci_config_filter(struct rt2x00_dev *rt2x00dev,
626 const unsigned int filter_flags)
627{
628 u32 reg;
629
630 /*
631 * Start configuration steps.
632 * Note that the version error will always be dropped
633 * and broadcast frames will always be accepted since
634 * there is no filter for it at this time.
635 */
636 rt2x00pci_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
637 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
638 !(filter_flags & FIF_FCSFAIL));
639 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
640 !(filter_flags & FIF_PLCPFAIL));
641 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
642 !(filter_flags & FIF_PROMISC_IN_BSS));
643 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
644 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
645 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
646 !(filter_flags & FIF_ALLMULTI));
647 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
648 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
649 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
650 !(filter_flags & FIF_CONTROL));
651 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
652 !(filter_flags & FIF_CONTROL));
653 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
654 !(filter_flags & FIF_CONTROL));
655 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
656 !(filter_flags & FIF_CONTROL));
657 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
658 !(filter_flags & FIF_CONTROL));
659 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
660 !(filter_flags & FIF_PSPOLL));
661 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
662 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
663 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
664 !(filter_flags & FIF_CONTROL));
665 rt2x00pci_register_write(rt2x00dev, RX_FILTER_CFG, reg);
666}
667
668static void rt2800pci_config_intf(struct rt2x00_dev *rt2x00dev,
669 struct rt2x00_intf *intf,
670 struct rt2x00intf_conf *conf,
671 const unsigned int flags)
672{
673 unsigned int beacon_base;
674 u32 reg;
675
676 if (flags & CONFIG_UPDATE_TYPE) {
677 /*
678 * Clear current synchronisation setup.
679 * For the Beacon base registers we only need to clear
680 * the first byte since that byte contains the VALID and OWNER
681 * bits which (when set to 0) will invalidate the entire beacon.
682 */
683 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
684 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
685
686 /*
687 * Enable synchronisation.
688 */
689 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
690 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
691 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
692 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
693 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
694 }
695
696 if (flags & CONFIG_UPDATE_MAC) {
697 reg = le32_to_cpu(conf->mac[1]);
698 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
699 conf->mac[1] = cpu_to_le32(reg);
700
701 rt2x00pci_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
702 conf->mac, sizeof(conf->mac));
703 }
704
705 if (flags & CONFIG_UPDATE_BSSID) {
706 reg = le32_to_cpu(conf->bssid[1]);
707 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
708 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
709 conf->bssid[1] = cpu_to_le32(reg);
710
711 rt2x00pci_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
712 conf->bssid, sizeof(conf->bssid));
713 }
714}
715
716static void rt2800pci_config_erp(struct rt2x00_dev *rt2x00dev,
717 struct rt2x00lib_erp *erp)
718{
719 u32 reg;
720
721 rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
722 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20);
723 rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
724
725 rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
726 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
727 !!erp->short_preamble);
728 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
729 !!erp->short_preamble);
730 rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
731
732 rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
733 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
734 erp->cts_protection ? 2 : 0);
735 rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
736
737 rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE,
738 erp->basic_rates);
739 rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
740
741 rt2x00pci_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
742 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
743 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
744 rt2x00pci_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
745
746 rt2x00pci_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
747 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
748 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
749 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
750 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
751 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
752 rt2x00pci_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
753
754 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
755 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
756 erp->beacon_int * 16);
757 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
758}
759
760static void rt2800pci_config_ant(struct rt2x00_dev *rt2x00dev,
761 struct antenna_setup *ant)
762{
763 u8 r1;
764 u8 r3;
765
766 rt2800pci_bbp_read(rt2x00dev, 1, &r1);
767 rt2800pci_bbp_read(rt2x00dev, 3, &r3);
768
769 /*
770 * Configure the TX antenna.
771 */
772 switch ((int)ant->tx) {
773 case 1:
774 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
775 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
776 break;
777 case 2:
778 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
779 break;
780 case 3:
781 /* Do nothing */
782 break;
783 }
784
785 /*
786 * Configure the RX antenna.
787 */
788 switch ((int)ant->rx) {
789 case 1:
790 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
791 break;
792 case 2:
793 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
794 break;
795 case 3:
796 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
797 break;
798 }
799
800 rt2800pci_bbp_write(rt2x00dev, 3, r3);
801 rt2800pci_bbp_write(rt2x00dev, 1, r1);
802}
803
804static void rt2800pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
805 struct rt2x00lib_conf *libconf)
806{
807 u16 eeprom;
808 short lna_gain;
809
810 if (libconf->rf.channel <= 14) {
811 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
812 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
813 } else if (libconf->rf.channel <= 64) {
814 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
815 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
816 } else if (libconf->rf.channel <= 128) {
817 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
818 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
819 } else {
820 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
821 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
822 }
823
824 rt2x00dev->lna_gain = lna_gain;
825}
826
827static void rt2800pci_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
828 struct ieee80211_conf *conf,
829 struct rf_channel *rf,
830 struct channel_info *info)
831{
832 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
833
834 if (rt2x00dev->default_ant.tx == 1)
835 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
836
837 if (rt2x00dev->default_ant.rx == 1) {
838 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
839 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
840 } else if (rt2x00dev->default_ant.rx == 2)
841 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
842
843 if (rf->channel > 14) {
844 /*
845 * When TX power is below 0, we should increase it by 7 to
846 * make it a positive value (Minumum value is -7).
847 * However this means that values between 0 and 7 have
848 * double meaning, and we should set a 7DBm boost flag.
849 */
850 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
851 (info->tx_power1 >= 0));
852
853 if (info->tx_power1 < 0)
854 info->tx_power1 += 7;
855
856 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
857 TXPOWER_A_TO_DEV(info->tx_power1));
858
859 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
860 (info->tx_power2 >= 0));
861
862 if (info->tx_power2 < 0)
863 info->tx_power2 += 7;
864
865 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
866 TXPOWER_A_TO_DEV(info->tx_power2));
867 } else {
868 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
869 TXPOWER_G_TO_DEV(info->tx_power1));
870 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
871 TXPOWER_G_TO_DEV(info->tx_power2));
872 }
873
874 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
875
876 rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
877 rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
878 rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
879 rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
880
881 udelay(200);
882
883 rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
884 rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
885 rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
886 rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
887
888 udelay(200);
889
890 rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
891 rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
892 rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
893 rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
894}
895
896static void rt2800pci_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
897 struct ieee80211_conf *conf,
898 struct rf_channel *rf,
899 struct channel_info *info)
900{
901 u8 rfcsr;
902
903 rt2800pci_rfcsr_write(rt2x00dev, 2, rf->rf1);
904 rt2800pci_rfcsr_write(rt2x00dev, 2, rf->rf3);
905
906 rt2800pci_rfcsr_read(rt2x00dev, 6, &rfcsr);
907 rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
908 rt2800pci_rfcsr_write(rt2x00dev, 6, rfcsr);
909
910 rt2800pci_rfcsr_read(rt2x00dev, 12, &rfcsr);
911 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
912 TXPOWER_G_TO_DEV(info->tx_power1));
913 rt2800pci_rfcsr_write(rt2x00dev, 12, rfcsr);
914
915 rt2800pci_rfcsr_read(rt2x00dev, 23, &rfcsr);
916 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
917 rt2800pci_rfcsr_write(rt2x00dev, 23, rfcsr);
918
919 rt2800pci_rfcsr_write(rt2x00dev, 24,
920 rt2x00dev->calibration[conf_is_ht40(conf)]);
921
922 rt2800pci_rfcsr_read(rt2x00dev, 23, &rfcsr);
923 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
924 rt2800pci_rfcsr_write(rt2x00dev, 23, rfcsr);
925}
926
927static void rt2800pci_config_channel(struct rt2x00_dev *rt2x00dev,
928 struct ieee80211_conf *conf,
929 struct rf_channel *rf,
930 struct channel_info *info)
931{
932 u32 reg;
933 unsigned int tx_pin;
934 u8 bbp;
935
936 if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
937 rt2800pci_config_channel_rt2x(rt2x00dev, conf, rf, info);
938 else
939 rt2800pci_config_channel_rt3x(rt2x00dev, conf, rf, info);
940
941 /*
942 * Change BBP settings
943 */
944 rt2800pci_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
945 rt2800pci_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
946 rt2800pci_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
947 rt2800pci_bbp_write(rt2x00dev, 86, 0);
948
949 if (rf->channel <= 14) {
950 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
951 rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
952 rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
953 } else {
954 rt2800pci_bbp_write(rt2x00dev, 82, 0x84);
955 rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
956 }
957 } else {
958 rt2800pci_bbp_write(rt2x00dev, 82, 0xf2);
959
960 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
961 rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
962 else
963 rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
964 }
965
966 rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, &reg);
967 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
968 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
969 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
970 rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
971
972 tx_pin = 0;
973
974 /* Turn on unused PA or LNA when not using 1T or 1R */
975 if (rt2x00dev->default_ant.tx != 1) {
976 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
977 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
978 }
979
980 /* Turn on unused PA or LNA when not using 1T or 1R */
981 if (rt2x00dev->default_ant.rx != 1) {
982 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
983 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
984 }
985
986 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
987 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
988 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
989 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
990 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
991 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
992
993 rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
994
995 rt2800pci_bbp_read(rt2x00dev, 4, &bbp);
996 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
997 rt2800pci_bbp_write(rt2x00dev, 4, bbp);
998
999 rt2800pci_bbp_read(rt2x00dev, 3, &bbp);
1000 rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
1001 rt2800pci_bbp_write(rt2x00dev, 3, bbp);
1002
1003 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1004 if (conf_is_ht40(conf)) {
1005 rt2800pci_bbp_write(rt2x00dev, 69, 0x1a);
1006 rt2800pci_bbp_write(rt2x00dev, 70, 0x0a);
1007 rt2800pci_bbp_write(rt2x00dev, 73, 0x16);
1008 } else {
1009 rt2800pci_bbp_write(rt2x00dev, 69, 0x16);
1010 rt2800pci_bbp_write(rt2x00dev, 70, 0x08);
1011 rt2800pci_bbp_write(rt2x00dev, 73, 0x11);
1012 }
1013 }
1014
1015 msleep(1);
1016}
1017
1018static void rt2800pci_config_txpower(struct rt2x00_dev *rt2x00dev,
1019 const int txpower)
1020{
1021 u32 reg;
1022 u32 value = TXPOWER_G_TO_DEV(txpower);
1023 u8 r1;
1024
1025 rt2800pci_bbp_read(rt2x00dev, 1, &r1);
1026 rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
1027 rt2800pci_bbp_write(rt2x00dev, 1, r1);
1028
1029 rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
1030 rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
1031 rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
1032 rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
1033 rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
1034 rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
1035 rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
1036 rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
1037 rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
1038 rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
1039
1040 rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
1041 rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
1042 rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
1043 rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
1044 rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
1045 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
1046 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
1047 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
1048 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
1049 rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
1050
1051 rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
1052 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
1053 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
1054 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
1055 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
1056 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
1057 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
1058 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
1059 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
1060 rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
1061
1062 rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
1063 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
1064 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
1065 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
1066 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
1067 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
1068 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
1069 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
1070 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
1071 rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
1072
1073 rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
1074 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
1075 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
1076 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
1077 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
1078 rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
1079}
1080
1081static void rt2800pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1082 struct rt2x00lib_conf *libconf)
1083{
1084 u32 reg;
1085
1086 rt2x00pci_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1087 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1088 libconf->conf->short_frame_max_tx_count);
1089 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1090 libconf->conf->long_frame_max_tx_count);
1091 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1092 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1093 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1094 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1095 rt2x00pci_register_write(rt2x00dev, TX_RTY_CFG, reg);
1096}
1097
1098static void rt2800pci_config_ps(struct rt2x00_dev *rt2x00dev,
1099 struct rt2x00lib_conf *libconf)
1100{
1101 enum dev_state state =
1102 (libconf->conf->flags & IEEE80211_CONF_PS) ?
1103 STATE_SLEEP : STATE_AWAKE;
1104 u32 reg;
1105
1106 if (state == STATE_SLEEP) {
1107 rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1108
1109 rt2x00pci_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1110 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1111 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1112 libconf->conf->listen_interval - 1);
1113 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1114 rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1115
1116 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1117 } else {
1118 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1119
1120 rt2x00pci_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1121 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1122 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1123 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1124 rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1125 }
1126}
1127
1128static void rt2800pci_config(struct rt2x00_dev *rt2x00dev,
1129 struct rt2x00lib_conf *libconf,
1130 const unsigned int flags)
1131{
1132 /* Always recalculate LNA gain before changing configuration */
1133 rt2800pci_config_lna_gain(rt2x00dev, libconf);
1134
1135 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1136 rt2800pci_config_channel(rt2x00dev, libconf->conf,
1137 &libconf->rf, &libconf->channel);
1138 if (flags & IEEE80211_CONF_CHANGE_POWER)
1139 rt2800pci_config_txpower(rt2x00dev, libconf->conf->power_level);
1140 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1141 rt2800pci_config_retry_limit(rt2x00dev, libconf);
1142 if (flags & IEEE80211_CONF_CHANGE_PS)
1143 rt2800pci_config_ps(rt2x00dev, libconf);
1144}
1145
1146/*
1147 * Link tuning
1148 */
1149static void rt2800pci_link_stats(struct rt2x00_dev *rt2x00dev,
1150 struct link_qual *qual)
1151{
1152 u32 reg;
1153
1154 /*
1155 * Update FCS error count from register.
1156 */
1157 rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1158 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1159}
1160
1161static u8 rt2800pci_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1162{
1163 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)
1164 return 0x2e + rt2x00dev->lna_gain;
1165
1166 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1167 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1168 else
1169 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1170}
1171
1172static inline void rt2800pci_set_vgc(struct rt2x00_dev *rt2x00dev,
1173 struct link_qual *qual, u8 vgc_level)
1174{
1175 if (qual->vgc_level != vgc_level) {
1176 rt2800pci_bbp_write(rt2x00dev, 66, vgc_level);
1177 qual->vgc_level = vgc_level;
1178 qual->vgc_level_reg = vgc_level;
1179 }
1180}
1181
1182static void rt2800pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
1183 struct link_qual *qual)
1184{
1185 rt2800pci_set_vgc(rt2x00dev, qual,
1186 rt2800pci_get_default_vgc(rt2x00dev));
1187}
1188
1189static void rt2800pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1190 struct link_qual *qual, const u32 count)
1191{
1192 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1193 return;
1194
1195 /*
1196 * When RSSI is better then -80 increase VGC level with 0x10
1197 */
1198 rt2800pci_set_vgc(rt2x00dev, qual,
1199 rt2800pci_get_default_vgc(rt2x00dev) +
1200 ((qual->rssi > -80) * 0x10));
1201}
1202
1203/*
1204 * Firmware functions
1205 */
1206static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1207{
1208 return FIRMWARE_RT2860;
1209}
1210
1211static int rt2800pci_check_firmware(struct rt2x00_dev *rt2x00dev,
1212 const u8 *data, const size_t len)
1213{
1214 u16 fw_crc;
1215 u16 crc;
1216
1217 /*
1218 * Only support 8kb firmware files.
1219 */
1220 if (len != 8192)
1221 return FW_BAD_LENGTH;
1222
1223 /*
1224 * The last 2 bytes in the firmware array are the crc checksum itself,
1225 * this means that we should never pass those 2 bytes to the crc
1226 * algorithm.
1227 */
1228 fw_crc = (data[len - 2] << 8 | data[len - 1]);
1229
1230 /*
1231 * Use the crc ccitt algorithm.
1232 * This will return the same value as the legacy driver which
1233 * used bit ordering reversion on the both the firmware bytes
1234 * before input input as well as on the final output.
1235 * Obviously using crc ccitt directly is much more efficient.
1236 */
1237 crc = crc_ccitt(~0, data, len - 2);
1238
1239 /*
1240 * There is a small difference between the crc-itu-t + bitrev and
1241 * the crc-ccitt crc calculation. In the latter method the 2 bytes
1242 * will be swapped, use swab16 to convert the crc to the correct
1243 * value.
1244 */
1245 crc = swab16(crc);
1246
1247 return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
1248}
1249
1250static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1251 const u8 *data, const size_t len)
1252{
1253 unsigned int i;
1254 u32 reg;
1255
1256 /*
1257 * Wait for stable hardware.
1258 */
1259 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1260 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1261 if (reg && reg != ~0)
1262 break;
1263 msleep(1);
1264 }
1265
1266 if (i == REGISTER_BUSY_COUNT) {
1267 ERROR(rt2x00dev, "Unstable hardware.\n");
1268 return -EBUSY;
1269 }
1270
1271 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
1272 rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
1273
1274 /*
1275 * Disable DMA, will be reenabled later when enabling
1276 * the radio.
1277 */
1278 rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1279 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1280 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1281 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1282 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1283 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1284 rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1285
1286 /*
1287 * enable Host program ram write selection
1288 */
1289 reg = 0;
1290 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
1291 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
1292
1293 /*
1294 * Write firmware to device.
1295 */
1296 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1297 data, len);
1298
1299 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
1300 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
1301
1302 /*
1303 * Wait for device to stabilize.
1304 */
1305 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1306 rt2x00pci_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1307 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1308 break;
1309 msleep(1);
1310 }
1311
1312 if (i == REGISTER_BUSY_COUNT) {
1313 ERROR(rt2x00dev, "PBF system register not ready.\n");
1314 return -EBUSY;
1315 }
1316
1317 /*
1318 * Disable interrupts
1319 */
1320 rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_OFF);
1321
1322 /*
1323 * Initialize BBP R/W access agent
1324 */
1325 rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1326 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1327
1328 return 0;
1329}
1330
1331/*
1332 * Initialization functions.
1333 */
1334static bool rt2800pci_get_entry_state(struct queue_entry *entry)
1335{
1336 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1337 u32 word;
1338
1339 if (entry->queue->qid == QID_RX) {
1340 rt2x00_desc_read(entry_priv->desc, 1, &word);
1341
1342 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
1343 } else {
1344 rt2x00_desc_read(entry_priv->desc, 1, &word);
1345
1346 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
1347 }
1348}
1349
1350static void rt2800pci_clear_entry(struct queue_entry *entry)
1351{
1352 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1353 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1354 u32 word;
1355
1356 if (entry->queue->qid == QID_RX) {
1357 rt2x00_desc_read(entry_priv->desc, 0, &word);
1358 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
1359 rt2x00_desc_write(entry_priv->desc, 0, word);
1360
1361 rt2x00_desc_read(entry_priv->desc, 1, &word);
1362 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
1363 rt2x00_desc_write(entry_priv->desc, 1, word);
1364 } else {
1365 rt2x00_desc_read(entry_priv->desc, 1, &word);
1366 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
1367 rt2x00_desc_write(entry_priv->desc, 1, word);
1368 }
1369}
1370
1371static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
1372{
1373 struct queue_entry_priv_pci *entry_priv;
1374 u32 reg;
1375
1376 rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1377 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
1378 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
1379 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
1380 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
1381 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
1382 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
1383 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
1384 rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1385
1386 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
1387 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
1388
1389 /*
1390 * Initialize registers.
1391 */
1392 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1393 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
1394 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
1395 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
1396 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX0, 0);
1397
1398 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1399 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
1400 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
1401 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
1402 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX1, 0);
1403
1404 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1405 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
1406 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
1407 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
1408 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX2, 0);
1409
1410 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1411 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
1412 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
1413 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
1414 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX3, 0);
1415
1416 entry_priv = rt2x00dev->rx->entries[0].priv_data;
1417 rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
1418 rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
1419 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
1420 rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0);
1421
1422 /*
1423 * Enable global DMA configuration
1424 */
1425 rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1426 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1427 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1428 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1429 rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1430
1431 rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
1432
1433 return 0;
1434}
1435
1436static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1437{
1438 u32 reg;
1439 unsigned int i;
1440
1441 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1442
1443 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1444 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1445 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1446 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1447
1448 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1449
1450 rt2x00pci_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1451 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1452 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1453 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1454 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1455 rt2x00pci_register_write(rt2x00dev, BCN_OFFSET0, reg);
1456
1457 rt2x00pci_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1458 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1459 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1460 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1461 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1462 rt2x00pci_register_write(rt2x00dev, BCN_OFFSET1, reg);
1463
1464 rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1465 rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1466
1467 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1468
1469 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1470 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1471 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1472 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1473 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1474 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1475 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1476 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1477
1478 rt2x00pci_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1479 rt2x00pci_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1480
1481 rt2x00pci_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1482 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1483 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1484 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1485 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1486 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1487 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1488 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1489 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1490 rt2x00pci_register_write(rt2x00dev, TX_LINK_CFG, reg);
1491
1492 rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1493 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1494 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1495 rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1496
1497 rt2x00pci_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1498 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1499 if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1500 rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1501 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1502 else
1503 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1504 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1505 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1506 rt2x00pci_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1507
1508 rt2x00pci_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1509
1510 rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1511 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1512 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1513 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1514 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1515 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1516 rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1517
1518 rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1519 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1520 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1521 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1522 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1523 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1524 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1525 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1526 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1527 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1528 rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1529
1530 rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1531 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1532 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1533 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1534 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1535 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1536 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1537 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1538 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1539 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1540 rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1541
1542 rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1543 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1544 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1545 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1546 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1547 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1548 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1549 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1550 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1551 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1552 rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1553
1554 rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1555 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1556 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1557 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1558 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1559 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1560 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1561 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1562 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1563 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1564 rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1565
1566 rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1567 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1568 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1569 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1570 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1571 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1572 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1573 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1574 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1575 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1576 rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1577
1578 rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1579 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1580 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1581 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1582 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1583 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1584 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1585 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1586 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1587 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1588 rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1589
1590 rt2x00pci_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1591 rt2x00pci_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1592
1593 rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1594 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1595 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1596 IEEE80211_MAX_RTS_THRESHOLD);
1597 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1598 rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
1599
1600 rt2x00pci_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1601 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1602
1603 /*
1604 * ASIC will keep garbage value after boot, clear encryption keys.
1605 */
1606 for (i = 0; i < 4; i++)
1607 rt2x00pci_register_write(rt2x00dev,
1608 SHARED_KEY_MODE_ENTRY(i), 0);
1609
1610 for (i = 0; i < 256; i++) {
1611 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1612 rt2x00pci_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1613 wcid, sizeof(wcid));
1614
1615 rt2x00pci_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1616 rt2x00pci_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1617 }
1618
1619 /*
1620 * Clear all beacons
1621 * For the Beacon base registers we only need to clear
1622 * the first byte since that byte contains the VALID and OWNER
1623 * bits which (when set to 0) will invalidate the entire beacon.
1624 */
1625 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1626 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1627 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1628 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1629 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1630 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1631 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1632 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1633
1634 rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1635 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1636 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1637 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1638 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1639 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1640 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1641 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1642 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1643 rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1644
1645 rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1646 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1647 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1648 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1649 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1650 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1651 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1652 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1653 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1654 rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1655
1656 rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1657 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1658 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1659 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1660 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1661 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1662 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1663 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1664 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1665 rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1666
1667 rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1668 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1669 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1670 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1671 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1672 rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1673
1674 /*
1675 * We must clear the error counters.
1676 * These registers are cleared on read,
1677 * so we may pass a useless variable to store the value.
1678 */
1679 rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1680 rt2x00pci_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1681 rt2x00pci_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1682 rt2x00pci_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1683 rt2x00pci_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1684 rt2x00pci_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1685
1686 return 0;
1687}
1688
1689static int rt2800pci_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1690{
1691 unsigned int i;
1692 u32 reg;
1693
1694 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1695 rt2x00pci_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1696 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1697 return 0;
1698
1699 udelay(REGISTER_BUSY_DELAY);
1700 }
1701
1702 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1703 return -EACCES;
1704}
1705
1706static int rt2800pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1707{
1708 unsigned int i;
1709 u8 value;
1710
1711 /*
1712 * BBP was enabled after firmware was loaded,
1713 * but we need to reactivate it now.
1714 */
1715 rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1716 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1717 msleep(1);
1718
1719 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1720 rt2800pci_bbp_read(rt2x00dev, 0, &value);
1721 if ((value != 0xff) && (value != 0x00))
1722 return 0;
1723 udelay(REGISTER_BUSY_DELAY);
1724 }
1725
1726 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1727 return -EACCES;
1728}
1729
1730static int rt2800pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1731{
1732 unsigned int i;
1733 u16 eeprom;
1734 u8 reg_id;
1735 u8 value;
1736
1737 if (unlikely(rt2800pci_wait_bbp_rf_ready(rt2x00dev) ||
1738 rt2800pci_wait_bbp_ready(rt2x00dev)))
1739 return -EACCES;
1740
1741 rt2800pci_bbp_write(rt2x00dev, 65, 0x2c);
1742 rt2800pci_bbp_write(rt2x00dev, 66, 0x38);
1743 rt2800pci_bbp_write(rt2x00dev, 69, 0x12);
1744 rt2800pci_bbp_write(rt2x00dev, 70, 0x0a);
1745 rt2800pci_bbp_write(rt2x00dev, 73, 0x10);
1746 rt2800pci_bbp_write(rt2x00dev, 81, 0x37);
1747 rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
1748 rt2800pci_bbp_write(rt2x00dev, 83, 0x6a);
1749 rt2800pci_bbp_write(rt2x00dev, 84, 0x99);
1750 rt2800pci_bbp_write(rt2x00dev, 86, 0x00);
1751 rt2800pci_bbp_write(rt2x00dev, 91, 0x04);
1752 rt2800pci_bbp_write(rt2x00dev, 92, 0x00);
1753 rt2800pci_bbp_write(rt2x00dev, 103, 0x00);
1754 rt2800pci_bbp_write(rt2x00dev, 105, 0x05);
1755
1756 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1757 rt2800pci_bbp_write(rt2x00dev, 69, 0x16);
1758 rt2800pci_bbp_write(rt2x00dev, 73, 0x12);
1759 }
1760
1761 if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION)
1762 rt2800pci_bbp_write(rt2x00dev, 84, 0x19);
1763
1764 if (rt2x00_rt(&rt2x00dev->chip, RT3052)) {
1765 rt2800pci_bbp_write(rt2x00dev, 31, 0x08);
1766 rt2800pci_bbp_write(rt2x00dev, 78, 0x0e);
1767 rt2800pci_bbp_write(rt2x00dev, 80, 0x08);
1768 }
1769
1770 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1771 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1772
1773 if (eeprom != 0xffff && eeprom != 0x0000) {
1774 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1775 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1776 rt2800pci_bbp_write(rt2x00dev, reg_id, value);
1777 }
1778 }
1779
1780 return 0;
1781}
1782
1783static u8 rt2800pci_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1784 bool bw40, u8 rfcsr24, u8 filter_target)
1785{
1786 unsigned int i;
1787 u8 bbp;
1788 u8 rfcsr;
1789 u8 passband;
1790 u8 stopband;
1791 u8 overtuned = 0;
1792
1793 rt2800pci_rfcsr_write(rt2x00dev, 24, rfcsr24);
1794
1795 rt2800pci_bbp_read(rt2x00dev, 4, &bbp);
1796 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1797 rt2800pci_bbp_write(rt2x00dev, 4, bbp);
1798
1799 rt2800pci_rfcsr_read(rt2x00dev, 22, &rfcsr);
1800 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1801 rt2800pci_rfcsr_write(rt2x00dev, 22, rfcsr);
1802
1803 /*
1804 * Set power & frequency of passband test tone
1805 */
1806 rt2800pci_bbp_write(rt2x00dev, 24, 0);
1807
1808 for (i = 0; i < 100; i++) {
1809 rt2800pci_bbp_write(rt2x00dev, 25, 0x90);
1810 msleep(1);
1811
1812 rt2800pci_bbp_read(rt2x00dev, 55, &passband);
1813 if (passband)
1814 break;
1815 }
1816
1817 /*
1818 * Set power & frequency of stopband test tone
1819 */
1820 rt2800pci_bbp_write(rt2x00dev, 24, 0x06);
1821
1822 for (i = 0; i < 100; i++) {
1823 rt2800pci_bbp_write(rt2x00dev, 25, 0x90);
1824 msleep(1);
1825
1826 rt2800pci_bbp_read(rt2x00dev, 55, &stopband);
1827
1828 if ((passband - stopband) <= filter_target) {
1829 rfcsr24++;
1830 overtuned += ((passband - stopband) == filter_target);
1831 } else
1832 break;
1833
1834 rt2800pci_rfcsr_write(rt2x00dev, 24, rfcsr24);
1835 }
1836
1837 rfcsr24 -= !!overtuned;
1838
1839 rt2800pci_rfcsr_write(rt2x00dev, 24, rfcsr24);
1840 return rfcsr24;
1841}
1842
1843static int rt2800pci_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1844{
1845 u8 rfcsr;
1846 u8 bbp;
1847
1848 if (!rt2x00_rf(&rt2x00dev->chip, RF3020) &&
1849 !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
1850 !rt2x00_rf(&rt2x00dev->chip, RF3022))
1851 return 0;
1852
1853 /*
1854 * Init RF calibration.
1855 */
1856 rt2800pci_rfcsr_read(rt2x00dev, 30, &rfcsr);
1857 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1858 rt2800pci_rfcsr_write(rt2x00dev, 30, rfcsr);
1859 msleep(1);
1860 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1861 rt2800pci_rfcsr_write(rt2x00dev, 30, rfcsr);
1862
1863 rt2800pci_rfcsr_write(rt2x00dev, 0, 0x50);
1864 rt2800pci_rfcsr_write(rt2x00dev, 1, 0x01);
1865 rt2800pci_rfcsr_write(rt2x00dev, 2, 0xf7);
1866 rt2800pci_rfcsr_write(rt2x00dev, 3, 0x75);
1867 rt2800pci_rfcsr_write(rt2x00dev, 4, 0x40);
1868 rt2800pci_rfcsr_write(rt2x00dev, 5, 0x03);
1869 rt2800pci_rfcsr_write(rt2x00dev, 6, 0x02);
1870 rt2800pci_rfcsr_write(rt2x00dev, 7, 0x50);
1871 rt2800pci_rfcsr_write(rt2x00dev, 8, 0x39);
1872 rt2800pci_rfcsr_write(rt2x00dev, 9, 0x0f);
1873 rt2800pci_rfcsr_write(rt2x00dev, 10, 0x60);
1874 rt2800pci_rfcsr_write(rt2x00dev, 11, 0x21);
1875 rt2800pci_rfcsr_write(rt2x00dev, 12, 0x75);
1876 rt2800pci_rfcsr_write(rt2x00dev, 13, 0x75);
1877 rt2800pci_rfcsr_write(rt2x00dev, 14, 0x90);
1878 rt2800pci_rfcsr_write(rt2x00dev, 15, 0x58);
1879 rt2800pci_rfcsr_write(rt2x00dev, 16, 0xb3);
1880 rt2800pci_rfcsr_write(rt2x00dev, 17, 0x92);
1881 rt2800pci_rfcsr_write(rt2x00dev, 18, 0x2c);
1882 rt2800pci_rfcsr_write(rt2x00dev, 19, 0x02);
1883 rt2800pci_rfcsr_write(rt2x00dev, 20, 0xba);
1884 rt2800pci_rfcsr_write(rt2x00dev, 21, 0xdb);
1885 rt2800pci_rfcsr_write(rt2x00dev, 22, 0x00);
1886 rt2800pci_rfcsr_write(rt2x00dev, 23, 0x31);
1887 rt2800pci_rfcsr_write(rt2x00dev, 24, 0x08);
1888 rt2800pci_rfcsr_write(rt2x00dev, 25, 0x01);
1889 rt2800pci_rfcsr_write(rt2x00dev, 26, 0x25);
1890 rt2800pci_rfcsr_write(rt2x00dev, 27, 0x23);
1891 rt2800pci_rfcsr_write(rt2x00dev, 28, 0x13);
1892 rt2800pci_rfcsr_write(rt2x00dev, 29, 0x83);
1893
1894 /*
1895 * Set RX Filter calibration for 20MHz and 40MHz
1896 */
1897 rt2x00dev->calibration[0] =
1898 rt2800pci_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1899 rt2x00dev->calibration[1] =
1900 rt2800pci_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1901
1902 /*
1903 * Set back to initial state
1904 */
1905 rt2800pci_bbp_write(rt2x00dev, 24, 0);
1906
1907 rt2800pci_rfcsr_read(rt2x00dev, 22, &rfcsr);
1908 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1909 rt2800pci_rfcsr_write(rt2x00dev, 22, rfcsr);
1910
1911 /*
1912 * set BBP back to BW20
1913 */
1914 rt2800pci_bbp_read(rt2x00dev, 4, &bbp);
1915 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1916 rt2800pci_bbp_write(rt2x00dev, 4, bbp);
1917
1918 return 0;
1919}
1920
1921/*
1922 * Device state switch handlers.
1923 */
1924static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1925 enum dev_state state)
1926{
1927 u32 reg;
1928
1929 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1930 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1931 (state == STATE_RADIO_RX_ON) ||
1932 (state == STATE_RADIO_RX_ON_LINK));
1933 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1934}
1935
1936static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1937 enum dev_state state)
1938{
1939 int mask = (state == STATE_RADIO_IRQ_ON);
1940 u32 reg;
1941
1942 /*
1943 * When interrupts are being enabled, the interrupt registers
1944 * should clear the register to assure a clean state.
1945 */
1946 if (state == STATE_RADIO_IRQ_ON) {
1947 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1948 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1949 }
1950
1951 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1952 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
1953 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
1954 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
1955 rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
1956 rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
1957 rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
1958 rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
1959 rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
1960 rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
1961 rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
1962 rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, mask);
1963 rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
1964 rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
1965 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
1966 rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
1967 rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
1968 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
1969 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
1970 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1971}
1972
1973static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1974{
1975 unsigned int i;
1976 u32 reg;
1977
1978 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1979 rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1980 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1981 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1982 return 0;
1983
1984 msleep(1);
1985 }
1986
1987 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
1988 return -EACCES;
1989}
1990
1991static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1992{
1993 u32 reg;
1994 u16 word;
1995
1996 /*
1997 * Initialize all registers.
1998 */
1999 if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) ||
2000 rt2800pci_init_queues(rt2x00dev) ||
2001 rt2800pci_init_registers(rt2x00dev) ||
2002 rt2800pci_wait_wpdma_ready(rt2x00dev) ||
2003 rt2800pci_init_bbp(rt2x00dev) ||
2004 rt2800pci_init_rfcsr(rt2x00dev)))
2005 return -EIO;
2006
2007 /*
2008 * Send signal to firmware during boot time.
2009 */
2010 rt2800pci_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
2011
2012 /*
2013 * Enable RX.
2014 */
2015 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2016 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2017 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2018 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2019
2020 rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2021 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
2022 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
2023 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
2024 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2025 rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2026
2027 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2028 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2029 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
2030 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2031
2032 /*
2033 * Initialize LED control
2034 */
2035 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
2036 rt2800pci_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
2037 word & 0xff, (word >> 8) & 0xff);
2038
2039 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
2040 rt2800pci_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
2041 word & 0xff, (word >> 8) & 0xff);
2042
2043 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
2044 rt2800pci_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
2045 word & 0xff, (word >> 8) & 0xff);
2046
2047 return 0;
2048}
2049
2050static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
2051{
2052 u32 reg;
2053
2054 rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2055 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2056 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2057 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2058 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2059 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2060 rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2061
2062 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
2063 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
2064 rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
2065
2066 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
2067
2068 rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
2069 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
2070 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
2071 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
2072 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
2073 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
2074 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
2075 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
2076 rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
2077
2078 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
2079 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
2080
2081 /* Wait for DMA, ignore error */
2082 rt2800pci_wait_wpdma_ready(rt2x00dev);
2083}
2084
2085static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
2086 enum dev_state state)
2087{
2088 /*
2089 * Always put the device to sleep (even when we intend to wakeup!)
2090 * if the device is booting and wasn't asleep it will return
2091 * failure when attempting to wakeup.
2092 */
2093 rt2800pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
2094
2095 if (state == STATE_AWAKE) {
2096 rt2800pci_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
2097 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
2098 }
2099
2100 return 0;
2101}
2102
2103static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
2104 enum dev_state state)
2105{
2106 int retval = 0;
2107
2108 switch (state) {
2109 case STATE_RADIO_ON:
2110 /*
2111 * Before the radio can be enabled, the device first has
2112 * to be woken up. After that it needs a bit of time
2113 * to be fully awake and then the radio can be enabled.
2114 */
2115 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
2116 msleep(1);
2117 retval = rt2800pci_enable_radio(rt2x00dev);
2118 break;
2119 case STATE_RADIO_OFF:
2120 /*
2121 * After the radio has been disabled, the device should
2122 * be put to sleep for powersaving.
2123 */
2124 rt2800pci_disable_radio(rt2x00dev);
2125 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
2126 break;
2127 case STATE_RADIO_RX_ON:
2128 case STATE_RADIO_RX_ON_LINK:
2129 case STATE_RADIO_RX_OFF:
2130 case STATE_RADIO_RX_OFF_LINK:
2131 rt2800pci_toggle_rx(rt2x00dev, state);
2132 break;
2133 case STATE_RADIO_IRQ_ON:
2134 case STATE_RADIO_IRQ_OFF:
2135 rt2800pci_toggle_irq(rt2x00dev, state);
2136 break;
2137 case STATE_DEEP_SLEEP:
2138 case STATE_SLEEP:
2139 case STATE_STANDBY:
2140 case STATE_AWAKE:
2141 retval = rt2800pci_set_state(rt2x00dev, state);
2142 break;
2143 default:
2144 retval = -ENOTSUPP;
2145 break;
2146 }
2147
2148 if (unlikely(retval))
2149 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
2150 state, retval);
2151
2152 return retval;
2153}
2154
2155/*
2156 * TX descriptor initialization
2157 */
2158static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
2159 struct sk_buff *skb,
2160 struct txentry_desc *txdesc)
2161{
2162 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
2163 __le32 *txd = skbdesc->desc;
2164 __le32 *txwi = (__le32 *)(skb->data - rt2x00dev->hw->extra_tx_headroom);
2165 u32 word;
2166
2167 /*
2168 * Initialize TX Info descriptor
2169 */
2170 rt2x00_desc_read(txwi, 0, &word);
2171 rt2x00_set_field32(&word, TXWI_W0_FRAG,
2172 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
2173 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
2174 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
2175 rt2x00_set_field32(&word, TXWI_W0_TS,
2176 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
2177 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
2178 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
2179 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
2180 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
2181 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
2182 rt2x00_set_field32(&word, TXWI_W0_BW,
2183 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
2184 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
2185 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
2186 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
2187 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
2188 rt2x00_desc_write(txwi, 0, word);
2189
2190 rt2x00_desc_read(txwi, 1, &word);
2191 rt2x00_set_field32(&word, TXWI_W1_ACK,
2192 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
2193 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
2194 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
2195 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
2196 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
2197 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
2198 (skbdesc->entry->entry_idx + 1) : 0xff);
2199 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
2200 skb->len - txdesc->l2pad);
2201 rt2x00_set_field32(&word, TXWI_W1_PACKETID,
2202 skbdesc->entry->queue->qid + 1);
2203 rt2x00_desc_write(txwi, 1, word);
2204
2205 /*
2206 * Always write 0 to IV/EIV fields, hardware will insert the IV
2207 * from the IVEIV register when ENTRY_TXD_ENCRYPT_IV is set to 0.
2208 * When ENTRY_TXD_ENCRYPT_IV is set to 1 it will use the IV data
2209 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
2210 * crypto entry in the registers should be used to encrypt the frame.
2211 */
2212 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
2213 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
2214
2215 /*
2216 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
2217 * must contains a TXWI structure + 802.11 header + padding + 802.11
2218 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
2219 * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
2220 * data. It means that LAST_SEC0 is always 0.
2221 */
2222
2223 /*
2224 * Initialize TX descriptor
2225 */
2226 rt2x00_desc_read(txd, 0, &word);
2227 rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
2228 rt2x00_desc_write(txd, 0, word);
2229
2230 rt2x00_desc_read(txd, 1, &word);
2231 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
2232 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
2233 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
2234 rt2x00_set_field32(&word, TXD_W1_BURST,
2235 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
2236 rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
2237 rt2x00dev->hw->extra_tx_headroom);
2238 rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
2239 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
2240 rt2x00_desc_write(txd, 1, word);
2241
2242 rt2x00_desc_read(txd, 2, &word);
2243 rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
2244 skbdesc->skb_dma + rt2x00dev->hw->extra_tx_headroom);
2245 rt2x00_desc_write(txd, 2, word);
2246
2247 rt2x00_desc_read(txd, 3, &word);
2248 rt2x00_set_field32(&word, TXD_W3_WIV,
2249 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
2250 rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
2251 rt2x00_desc_write(txd, 3, word);
2252}
2253
2254/*
2255 * TX data initialization
2256 */
2257static void rt2800pci_write_beacon(struct queue_entry *entry)
2258{
2259 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2260 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2261 unsigned int beacon_base;
2262 u32 reg;
2263
2264 /*
2265 * Disable beaconing while we are reloading the beacon data,
2266 * otherwise we might be sending out invalid data.
2267 */
2268 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2269 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2270 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2271
2272 /*
2273 * Write entire beacon with descriptor to register.
2274 */
2275 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2276 rt2x00pci_register_multiwrite(rt2x00dev,
2277 beacon_base,
2278 skbdesc->desc, skbdesc->desc_len);
2279 rt2x00pci_register_multiwrite(rt2x00dev,
2280 beacon_base + skbdesc->desc_len,
2281 entry->skb->data, entry->skb->len);
2282
2283 /*
2284 * Clean up beacon skb.
2285 */
2286 dev_kfree_skb_any(entry->skb);
2287 entry->skb = NULL;
2288}
2289
2290static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2291 const enum data_queue_qid queue_idx)
2292{
2293 struct data_queue *queue;
2294 unsigned int idx, qidx = 0;
2295 u32 reg;
2296
2297 if (queue_idx == QID_BEACON) {
2298 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2299 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
2300 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
2301 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
2302 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
2303 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2304 }
2305 return;
2306 }
2307
2308 if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
2309 return;
2310
2311 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2312 idx = queue->index[Q_INDEX];
2313
2314 if (queue_idx == QID_MGMT)
2315 qidx = 5;
2316 else
2317 qidx = queue_idx;
2318
2319 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
2320}
2321
2322static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
2323 const enum data_queue_qid qid)
2324{
2325 u32 reg;
2326
2327 if (qid == QID_BEACON) {
2328 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, 0);
2329 return;
2330 }
2331
2332 rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
2333 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
2334 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
2335 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
2336 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
2337 rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
2338}
2339
2340/*
2341 * RX control handlers
2342 */
2343static void rt2800pci_fill_rxdone(struct queue_entry *entry,
2344 struct rxdone_entry_desc *rxdesc)
2345{
2346 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2347 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2348 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
2349 __le32 *rxd = entry_priv->desc;
2350 __le32 *rxwi = (__le32 *)entry->skb->data;
2351 u32 rxd3;
2352 u32 rxwi0;
2353 u32 rxwi1;
2354 u32 rxwi2;
2355 u32 rxwi3;
2356
2357 rt2x00_desc_read(rxd, 3, &rxd3);
2358 rt2x00_desc_read(rxwi, 0, &rxwi0);
2359 rt2x00_desc_read(rxwi, 1, &rxwi1);
2360 rt2x00_desc_read(rxwi, 2, &rxwi2);
2361 rt2x00_desc_read(rxwi, 3, &rxwi3);
2362
2363 if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR))
2364 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2365
2366 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
2367 /*
2368 * Unfortunately we don't know the cipher type used during
2369 * decryption. This prevents us from correct providing
2370 * correct statistics through debugfs.
2371 */
2372 rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
2373 rxdesc->cipher_status =
2374 rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);
2375 }
2376
2377 if (rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED)) {
2378 /*
2379 * Hardware has stripped IV/EIV data from 802.11 frame during
2380 * decryption. Unfortunately the descriptor doesn't contain
2381 * any fields with the EIV/IV data either, so they can't
2382 * be restored by rt2x00lib.
2383 */
2384 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2385
2386 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2387 rxdesc->flags |= RX_FLAG_DECRYPTED;
2388 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2389 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2390 }
2391
2392 if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS))
2393 rxdesc->dev_flags |= RXDONE_MY_BSS;
2394
2395 if (rt2x00_get_field32(rxd3, RXD_W3_L2PAD)) {
2396 rxdesc->dev_flags |= RXDONE_L2PAD;
2397 skbdesc->flags |= SKBDESC_L2_PADDED;
2398 }
2399
2400 if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
2401 rxdesc->flags |= RX_FLAG_SHORT_GI;
2402
2403 if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
2404 rxdesc->flags |= RX_FLAG_40MHZ;
2405
2406 /*
2407 * Detect RX rate, always use MCS as signal type.
2408 */
2409 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
2410 rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
2411 rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
2412
2413 /*
2414 * Mask of 0x8 bit to remove the short preamble flag.
2415 */
2416 if (rxdesc->rate_mode == RATE_MODE_CCK)
2417 rxdesc->signal &= ~0x8;
2418
2419 rxdesc->rssi =
2420 (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
2421 rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
2422
2423 rxdesc->noise =
2424 (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
2425 rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
2426
2427 rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
2428
2429 /*
2430 * Set RX IDX in register to inform hardware that we have handled
2431 * this entry and it is available for reuse again.
2432 */
2433 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
2434
2435 /*
2436 * Remove TXWI descriptor from start of buffer.
2437 */
2438 skb_pull(entry->skb, RXWI_DESC_SIZE);
2439 skb_trim(entry->skb, rxdesc->size);
2440}
2441
2442/*
2443 * Interrupt functions.
2444 */
2445static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
2446{
2447 struct data_queue *queue;
2448 struct queue_entry *entry;
2449 struct queue_entry *entry_done;
2450 struct queue_entry_priv_pci *entry_priv;
2451 struct txdone_entry_desc txdesc;
2452 u32 word;
2453 u32 reg;
2454 u32 old_reg;
2455 unsigned int type;
2456 unsigned int index;
2457 u16 mcs, real_mcs;
2458
2459 /*
2460 * During each loop we will compare the freshly read
2461 * TX_STA_FIFO register value with the value read from
2462 * the previous loop. If the 2 values are equal then
2463 * we should stop processing because the chance it
2464 * quite big that the device has been unplugged and
2465 * we risk going into an endless loop.
2466 */
2467 old_reg = 0;
2468
2469 while (1) {
2470 rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &reg);
2471 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
2472 break;
2473
2474 if (old_reg == reg)
2475 break;
2476 old_reg = reg;
2477
2478 /*
2479 * Skip this entry when it contains an invalid
2480 * queue identication number.
2481 */
2482 type = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE) - 1;
2483 if (type >= QID_RX)
2484 continue;
2485
2486 queue = rt2x00queue_get_queue(rt2x00dev, type);
2487 if (unlikely(!queue))
2488 continue;
2489
2490 /*
2491 * Skip this entry when it contains an invalid
2492 * index number.
2493 */
2494 index = rt2x00_get_field32(reg, TX_STA_FIFO_WCID) - 1;
2495 if (unlikely(index >= queue->limit))
2496 continue;
2497
2498 entry = &queue->entries[index];
2499 entry_priv = entry->priv_data;
2500 rt2x00_desc_read((__le32 *)entry->skb->data, 0, &word);
2501
2502 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2503 while (entry != entry_done) {
2504 /*
2505 * Catch up.
2506 * Just report any entries we missed as failed.
2507 */
2508 WARNING(rt2x00dev,
2509 "TX status report missed for entry %d\n",
2510 entry_done->entry_idx);
2511
2512 txdesc.flags = 0;
2513 __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
2514 txdesc.retry = 0;
2515
2516 rt2x00lib_txdone(entry_done, &txdesc);
2517 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2518 }
2519
2520 /*
2521 * Obtain the status about this packet.
2522 */
2523 txdesc.flags = 0;
2524 if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS))
2525 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2526 else
2527 __set_bit(TXDONE_FAILURE, &txdesc.flags);
2528
2529 /*
2530 * Ralink has a retry mechanism using a global fallback
2531 * table. We setup this fallback table to try immediate
2532 * lower rate for all rates. In the TX_STA_FIFO,
2533 * the MCS field contains the MCS used for the successfull
2534 * transmission. If the first transmission succeed,
2535 * we have mcs == tx_mcs. On the second transmission,
2536 * we have mcs = tx_mcs - 1. So the number of
2537 * retry is (tx_mcs - mcs).
2538 */
2539 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
2540 real_mcs = rt2x00_get_field32(reg, TX_STA_FIFO_MCS);
2541 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
2542 txdesc.retry = mcs - min(mcs, real_mcs);
2543
2544 rt2x00lib_txdone(entry, &txdesc);
2545 }
2546}
2547
2548static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
2549{
2550 struct rt2x00_dev *rt2x00dev = dev_instance;
2551 u32 reg;
2552
2553 /* Read status and ACK all interrupts */
2554 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2555 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2556
2557 if (!reg)
2558 return IRQ_NONE;
2559
2560 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2561 return IRQ_HANDLED;
2562
2563 /*
2564 * 1 - Rx ring done interrupt.
2565 */
2566 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
2567 rt2x00pci_rxdone(rt2x00dev);
2568
2569 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
2570 rt2800pci_txdone(rt2x00dev);
2571
2572 return IRQ_HANDLED;
2573}
2574
2575/*
2576 * Device probe functions.
2577 */
2578static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2579{
2580 u16 word;
2581 u8 *mac;
2582 u8 default_lna_gain;
2583
2584 /*
2585 * Read EEPROM into buffer
2586 */
2587 switch(rt2x00dev->chip.rt) {
2588 case RT2880:
2589 case RT3052:
2590 rt2800pci_read_eeprom_soc(rt2x00dev);
2591 break;
2592 case RT3090:
2593 rt2800pci_read_eeprom_efuse(rt2x00dev);
2594 break;
2595 default:
2596 rt2800pci_read_eeprom_pci(rt2x00dev);
2597 break;
2598 }
2599
2600 /*
2601 * Start validation of the data that has been read.
2602 */
2603 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2604 if (!is_valid_ether_addr(mac)) {
2605 random_ether_addr(mac);
2606 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2607 }
2608
2609 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2610 if (word == 0xffff) {
2611 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2612 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2613 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2614 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2615 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2616 } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) {
2617 /*
2618 * There is a max of 2 RX streams for RT2860 series
2619 */
2620 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2621 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2622 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2623 }
2624
2625 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2626 if (word == 0xffff) {
2627 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2628 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2629 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2630 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2631 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2632 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2633 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2634 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2635 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2636 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2637 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2638 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2639 }
2640
2641 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2642 if ((word & 0x00ff) == 0x00ff) {
2643 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2644 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2645 LED_MODE_TXRX_ACTIVITY);
2646 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2647 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2648 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2649 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2650 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2651 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2652 }
2653
2654 /*
2655 * During the LNA validation we are going to use
2656 * lna0 as correct value. Note that EEPROM_LNA
2657 * is never validated.
2658 */
2659 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2660 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2661
2662 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2663 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2664 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2665 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2666 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2667 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2668
2669 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2670 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2671 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2672 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2673 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2674 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2675 default_lna_gain);
2676 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2677
2678 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2679 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2680 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2681 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2682 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2683 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2684
2685 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2686 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2687 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2688 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2689 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2690 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2691 default_lna_gain);
2692 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2693
2694 return 0;
2695}
2696
2697static int rt2800pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2698{
2699 u32 reg;
2700 u16 value;
2701 u16 eeprom;
2702
2703 /*
2704 * Read EEPROM word for configuration.
2705 */
2706 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2707
2708 /*
2709 * Identify RF chipset.
2710 */
2711 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2712 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2713 rt2x00_set_chip_rf(rt2x00dev, value, reg);
2714
2715 if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2716 !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2717 !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2718 !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
2719 !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
2720 !rt2x00_rf(&rt2x00dev->chip, RF2020) &&
2721 !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
2722 !rt2x00_rf(&rt2x00dev->chip, RF3022)) {
2723 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2724 return -ENODEV;
2725 }
2726
2727 /*
2728 * Identify default antenna configuration.
2729 */
2730 rt2x00dev->default_ant.tx =
2731 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2732 rt2x00dev->default_ant.rx =
2733 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2734
2735 /*
2736 * Read frequency offset and RF programming sequence.
2737 */
2738 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2739 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2740
2741 /*
2742 * Read external LNA informations.
2743 */
2744 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2745
2746 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2747 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2748 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2749 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2750
2751 /*
2752 * Detect if this device has an hardware controlled radio.
2753 */
2754 if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2755 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2756
2757 /*
2758 * Store led settings, for correct led behaviour.
2759 */
2760#ifdef CONFIG_RT2X00_LIB_LEDS
2761 rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2762 rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2763 rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2764
2765 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2766#endif /* CONFIG_RT2X00_LIB_LEDS */
2767
2768 return 0;
2769}
2770
2771/*
2772 * RF value list for rt2860
2773 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2774 */
2775static const struct rf_channel rf_vals[] = {
2776 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2777 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2778 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2779 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2780 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2781 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2782 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2783 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2784 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2785 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2786 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2787 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2788 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2789 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2790
2791 /* 802.11 UNI / HyperLan 2 */
2792 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2793 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2794 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2795 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2796 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2797 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2798 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2799 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2800 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2801 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2802 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2803 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2804
2805 /* 802.11 HyperLan 2 */
2806 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2807 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2808 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2809 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2810 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2811 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2812 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2813 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2814 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2815 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2816 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2817 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2818 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2819 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2820 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2821 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2822
2823 /* 802.11 UNII */
2824 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2825 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2826 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2827 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2828 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2829 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2830 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2831
2832 /* 802.11 Japan */
2833 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2834 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2835 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2836 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2837 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2838 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2839 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2840};
2841
2842static int rt2800pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2843{
2844 struct hw_mode_spec *spec = &rt2x00dev->spec;
2845 struct channel_info *info;
2846 char *tx_power1;
2847 char *tx_power2;
2848 unsigned int i;
2849 u16 eeprom;
2850
2851 /*
2852 * Initialize all hw fields.
2853 */
2854 rt2x00dev->hw->flags =
2855 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2856 IEEE80211_HW_SIGNAL_DBM |
2857 IEEE80211_HW_SUPPORTS_PS |
2858 IEEE80211_HW_PS_NULLFUNC_STACK;
2859 rt2x00dev->hw->extra_tx_headroom = TXWI_DESC_SIZE;
2860
2861 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2862 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2863 rt2x00_eeprom_addr(rt2x00dev,
2864 EEPROM_MAC_ADDR_0));
2865
2866 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2867
2868 /*
2869 * Initialize hw_mode information.
2870 */
2871 spec->supported_bands = SUPPORT_BAND_2GHZ;
2872 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2873
2874 if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2875 rt2x00_rf(&rt2x00dev->chip, RF2720) ||
2876 rt2x00_rf(&rt2x00dev->chip, RF3020) ||
2877 rt2x00_rf(&rt2x00dev->chip, RF3021) ||
2878 rt2x00_rf(&rt2x00dev->chip, RF3022) ||
2879 rt2x00_rf(&rt2x00dev->chip, RF2020) ||
2880 rt2x00_rf(&rt2x00dev->chip, RF3052)) {
2881 spec->num_channels = 14;
2882 spec->channels = rf_vals;
2883 } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2884 rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2885 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2886 spec->num_channels = ARRAY_SIZE(rf_vals);
2887 spec->channels = rf_vals;
2888 }
2889
2890 /*
2891 * Initialize HT information.
2892 */
2893 spec->ht.ht_supported = true;
2894 spec->ht.cap =
2895 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2896 IEEE80211_HT_CAP_GRN_FLD |
2897 IEEE80211_HT_CAP_SGI_20 |
2898 IEEE80211_HT_CAP_SGI_40 |
2899 IEEE80211_HT_CAP_TX_STBC |
2900 IEEE80211_HT_CAP_RX_STBC |
2901 IEEE80211_HT_CAP_PSMP_SUPPORT;
2902 spec->ht.ampdu_factor = 3;
2903 spec->ht.ampdu_density = 4;
2904 spec->ht.mcs.tx_params =
2905 IEEE80211_HT_MCS_TX_DEFINED |
2906 IEEE80211_HT_MCS_TX_RX_DIFF |
2907 ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2908 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2909
2910 switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2911 case 3:
2912 spec->ht.mcs.rx_mask[2] = 0xff;
2913 case 2:
2914 spec->ht.mcs.rx_mask[1] = 0xff;
2915 case 1:
2916 spec->ht.mcs.rx_mask[0] = 0xff;
2917 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2918 break;
2919 }
2920
2921 /*
2922 * Create channel information array
2923 */
2924 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2925 if (!info)
2926 return -ENOMEM;
2927
2928 spec->channels_info = info;
2929
2930 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2931 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2932
2933 for (i = 0; i < 14; i++) {
2934 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2935 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2936 }
2937
2938 if (spec->num_channels > 14) {
2939 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2940 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2941
2942 for (i = 14; i < spec->num_channels; i++) {
2943 info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2944 info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2945 }
2946 }
2947
2948 return 0;
2949}
2950
2951static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2952{
2953 int retval;
2954
2955 /*
2956 * Allocate eeprom data.
2957 */
2958 retval = rt2800pci_validate_eeprom(rt2x00dev);
2959 if (retval)
2960 return retval;
2961
2962 retval = rt2800pci_init_eeprom(rt2x00dev);
2963 if (retval)
2964 return retval;
2965
2966 /*
2967 * Initialize hw specifications.
2968 */
2969 retval = rt2800pci_probe_hw_mode(rt2x00dev);
2970 if (retval)
2971 return retval;
2972
2973 /*
2974 * This device has multiple filters for control frames
2975 * and has a separate filter for PS Poll frames.
2976 */
2977 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
2978 __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
2979
2980 /*
2981 * This device requires firmware.
2982 */
2983 if (!rt2x00_rt(&rt2x00dev->chip, RT2880) &&
2984 !rt2x00_rt(&rt2x00dev->chip, RT3052))
2985 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2986 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
2987 __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
2988 if (!modparam_nohwcrypt)
2989 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2990
2991 /*
2992 * Set the rssi offset.
2993 */
2994 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2995
2996 return 0;
2997}
2998
2999/*
3000 * IEEE80211 stack callback functions.
3001 */
3002static void rt2800pci_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
3003 u32 *iv32, u16 *iv16)
3004{
3005 struct rt2x00_dev *rt2x00dev = hw->priv;
3006 struct mac_iveiv_entry iveiv_entry;
3007 u32 offset;
3008
3009 offset = MAC_IVEIV_ENTRY(hw_key_idx);
3010 rt2x00pci_register_multiread(rt2x00dev, offset,
3011 &iveiv_entry, sizeof(iveiv_entry));
3012
3013 memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
3014 memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
3015}
3016
3017static int rt2800pci_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3018{
3019 struct rt2x00_dev *rt2x00dev = hw->priv;
3020 u32 reg;
3021 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
3022
3023 rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3024 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
3025 rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
3026
3027 rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3028 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
3029 rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3030
3031 rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3032 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
3033 rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3034
3035 rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3036 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
3037 rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3038
3039 rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3040 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
3041 rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3042
3043 rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3044 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
3045 rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3046
3047 rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3048 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
3049 rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3050
3051 return 0;
3052}
3053
3054static int rt2800pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
3055 const struct ieee80211_tx_queue_params *params)
3056{
3057 struct rt2x00_dev *rt2x00dev = hw->priv;
3058 struct data_queue *queue;
3059 struct rt2x00_field32 field;
3060 int retval;
3061 u32 reg;
3062 u32 offset;
3063
3064 /*
3065 * First pass the configuration through rt2x00lib, that will
3066 * update the queue settings and validate the input. After that
3067 * we are free to update the registers based on the value
3068 * in the queue parameter.
3069 */
3070 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
3071 if (retval)
3072 return retval;
3073
3074 /*
3075 * We only need to perform additional register initialization
3076 * for WMM queues/
3077 */
3078 if (queue_idx >= 4)
3079 return 0;
3080
3081 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
3082
3083 /* Update WMM TXOP register */
3084 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
3085 field.bit_offset = (queue_idx & 1) * 16;
3086 field.bit_mask = 0xffff << field.bit_offset;
3087
3088 rt2x00pci_register_read(rt2x00dev, offset, &reg);
3089 rt2x00_set_field32(&reg, field, queue->txop);
3090 rt2x00pci_register_write(rt2x00dev, offset, reg);
3091
3092 /* Update WMM registers */
3093 field.bit_offset = queue_idx * 4;
3094 field.bit_mask = 0xf << field.bit_offset;
3095
3096 rt2x00pci_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
3097 rt2x00_set_field32(&reg, field, queue->aifs);
3098 rt2x00pci_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
3099
3100 rt2x00pci_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
3101 rt2x00_set_field32(&reg, field, queue->cw_min);
3102 rt2x00pci_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
3103
3104 rt2x00pci_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
3105 rt2x00_set_field32(&reg, field, queue->cw_max);
3106 rt2x00pci_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
3107
3108 /* Update EDCA registers */
3109 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
3110
3111 rt2x00pci_register_read(rt2x00dev, offset, &reg);
3112 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
3113 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
3114 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
3115 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
3116 rt2x00pci_register_write(rt2x00dev, offset, reg);
3117
3118 return 0;
3119}
3120
3121static u64 rt2800pci_get_tsf(struct ieee80211_hw *hw)
3122{
3123 struct rt2x00_dev *rt2x00dev = hw->priv;
3124 u64 tsf;
3125 u32 reg;
3126
3127 rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
3128 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
3129 rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
3130 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
3131
3132 return tsf;
3133}
3134
3135static const struct ieee80211_ops rt2800pci_mac80211_ops = {
3136 .tx = rt2x00mac_tx,
3137 .start = rt2x00mac_start,
3138 .stop = rt2x00mac_stop,
3139 .add_interface = rt2x00mac_add_interface,
3140 .remove_interface = rt2x00mac_remove_interface,
3141 .config = rt2x00mac_config,
3142 .configure_filter = rt2x00mac_configure_filter,
3143 .set_key = rt2x00mac_set_key,
3144 .get_stats = rt2x00mac_get_stats,
3145 .get_tkip_seq = rt2800pci_get_tkip_seq,
3146 .set_rts_threshold = rt2800pci_set_rts_threshold,
3147 .bss_info_changed = rt2x00mac_bss_info_changed,
3148 .conf_tx = rt2800pci_conf_tx,
3149 .get_tx_stats = rt2x00mac_get_tx_stats,
3150 .get_tsf = rt2800pci_get_tsf,
3151 .rfkill_poll = rt2x00mac_rfkill_poll,
3152};
3153
3154static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
3155 .irq_handler = rt2800pci_interrupt,
3156 .probe_hw = rt2800pci_probe_hw,
3157 .get_firmware_name = rt2800pci_get_firmware_name,
3158 .check_firmware = rt2800pci_check_firmware,
3159 .load_firmware = rt2800pci_load_firmware,
3160 .initialize = rt2x00pci_initialize,
3161 .uninitialize = rt2x00pci_uninitialize,
3162 .get_entry_state = rt2800pci_get_entry_state,
3163 .clear_entry = rt2800pci_clear_entry,
3164 .set_device_state = rt2800pci_set_device_state,
3165 .rfkill_poll = rt2800pci_rfkill_poll,
3166 .link_stats = rt2800pci_link_stats,
3167 .reset_tuner = rt2800pci_reset_tuner,
3168 .link_tuner = rt2800pci_link_tuner,
3169 .write_tx_desc = rt2800pci_write_tx_desc,
3170 .write_tx_data = rt2x00pci_write_tx_data,
3171 .write_beacon = rt2800pci_write_beacon,
3172 .kick_tx_queue = rt2800pci_kick_tx_queue,
3173 .kill_tx_queue = rt2800pci_kill_tx_queue,
3174 .fill_rxdone = rt2800pci_fill_rxdone,
3175 .config_shared_key = rt2800pci_config_shared_key,
3176 .config_pairwise_key = rt2800pci_config_pairwise_key,
3177 .config_filter = rt2800pci_config_filter,
3178 .config_intf = rt2800pci_config_intf,
3179 .config_erp = rt2800pci_config_erp,
3180 .config_ant = rt2800pci_config_ant,
3181 .config = rt2800pci_config,
3182};
3183
3184static const struct data_queue_desc rt2800pci_queue_rx = {
3185 .entry_num = RX_ENTRIES,
3186 .data_size = AGGREGATION_SIZE,
3187 .desc_size = RXD_DESC_SIZE,
3188 .priv_size = sizeof(struct queue_entry_priv_pci),
3189};
3190
3191static const struct data_queue_desc rt2800pci_queue_tx = {
3192 .entry_num = TX_ENTRIES,
3193 .data_size = AGGREGATION_SIZE,
3194 .desc_size = TXD_DESC_SIZE,
3195 .priv_size = sizeof(struct queue_entry_priv_pci),
3196};
3197
3198static const struct data_queue_desc rt2800pci_queue_bcn = {
3199 .entry_num = 8 * BEACON_ENTRIES,
3200 .data_size = 0, /* No DMA required for beacons */
3201 .desc_size = TXWI_DESC_SIZE,
3202 .priv_size = sizeof(struct queue_entry_priv_pci),
3203};
3204
3205static const struct rt2x00_ops rt2800pci_ops = {
3206 .name = KBUILD_MODNAME,
3207 .max_sta_intf = 1,
3208 .max_ap_intf = 8,
3209 .eeprom_size = EEPROM_SIZE,
3210 .rf_size = RF_SIZE,
3211 .tx_queues = NUM_TX_QUEUES,
3212 .rx = &rt2800pci_queue_rx,
3213 .tx = &rt2800pci_queue_tx,
3214 .bcn = &rt2800pci_queue_bcn,
3215 .lib = &rt2800pci_rt2x00_ops,
3216 .hw = &rt2800pci_mac80211_ops,
3217#ifdef CONFIG_RT2X00_LIB_DEBUGFS
3218 .debugfs = &rt2800pci_rt2x00debug,
3219#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
3220};
3221
3222/*
3223 * RT2800pci module information.
3224 */
3225static struct pci_device_id rt2800pci_device_table[] = {
3226 { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
3227 { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
3228 { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
3229 { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
3230 { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
3231 { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
3232 { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
3233 { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
3234 { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
3235 { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
3236 { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
3237 { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
3238 { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
3239 { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
3240 { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
3241 { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
3242 { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
3243 { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
3244 { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
3245 { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
3246 { 0, }
3247};
3248
3249MODULE_AUTHOR(DRV_PROJECT);
3250MODULE_VERSION(DRV_VERSION);
3251MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
3252MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
3253#ifdef CONFIG_RT2800PCI_PCI
3254MODULE_FIRMWARE(FIRMWARE_RT2860);
3255MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
3256#endif /* CONFIG_RT2800PCI_PCI */
3257MODULE_LICENSE("GPL");
3258
3259#ifdef CONFIG_RT2800PCI_WISOC
3260#if defined(CONFIG_RALINK_RT288X)
3261__rt2x00soc_probe(RT2880, &rt2800pci_ops);
3262#elif defined(CONFIG_RALINK_RT305X)
3263__rt2x00soc_probe(RT3052, &rt2800pci_ops);
3264#endif
3265
3266static struct platform_driver rt2800soc_driver = {
3267 .driver = {
3268 .name = "rt2800_wmac",
3269 .owner = THIS_MODULE,
3270 .mod_name = KBUILD_MODNAME,
3271 },
3272 .probe = __rt2x00soc_probe,
3273 .remove = __devexit_p(rt2x00soc_remove),
3274 .suspend = rt2x00soc_suspend,
3275 .resume = rt2x00soc_resume,
3276};
3277#endif /* CONFIG_RT2800PCI_WISOC */
3278
3279#ifdef CONFIG_RT2800PCI_PCI
3280static struct pci_driver rt2800pci_driver = {
3281 .name = KBUILD_MODNAME,
3282 .id_table = rt2800pci_device_table,
3283 .probe = rt2x00pci_probe,
3284 .remove = __devexit_p(rt2x00pci_remove),
3285 .suspend = rt2x00pci_suspend,
3286 .resume = rt2x00pci_resume,
3287};
3288#endif /* CONFIG_RT2800PCI_PCI */
3289
3290static int __init rt2800pci_init(void)
3291{
3292 int ret = 0;
3293
3294#ifdef CONFIG_RT2800PCI_WISOC
3295 ret = platform_driver_register(&rt2800soc_driver);
3296 if (ret)
3297 return ret;
3298#endif
3299#ifdef CONFIG_RT2800PCI_PCI
3300 ret = pci_register_driver(&rt2800pci_driver);
3301 if (ret) {
3302#ifdef CONFIG_RT2800PCI_WISOC
3303 platform_driver_unregister(&rt2800soc_driver);
3304#endif
3305 return ret;
3306 }
3307#endif
3308
3309 return ret;
3310}
3311
3312static void __exit rt2800pci_exit(void)
3313{
3314#ifdef CONFIG_RT2800PCI_PCI
3315 pci_unregister_driver(&rt2800pci_driver);
3316#endif
3317#ifdef CONFIG_RT2800PCI_WISOC
3318 platform_driver_unregister(&rt2800soc_driver);
3319#endif
3320}
3321
3322module_init(rt2800pci_init);
3323module_exit(rt2800pci_exit);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-20 12:15:58 -0500