diff options
author | Wey-Yi Guy <wey-yi.w.guy@intel.com> | 2009-10-02 16:44:06 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2009-10-07 16:39:45 -0400 |
commit | f41bb897f202d23a7d896c716002a3d6050b991e (patch) | |
tree | d33eb3f81dbe75652d6ae6d4963fef9e34dc7311 /drivers/net/wireless/iwlwifi/iwl-csr.h | |
parent | 1739d3322008fb95e88ad0530bcc057789107879 (diff) |
iwlwifi: validate the signature for EEPROM and OTP
Both 1000 & 6000 series NICs contain on-chip OTP memory that
replaces the off-chip EEPROM memory. The nature of OTP means
there is a limited number of times a particular board can go through the
factory flow and be (re)calibrated. As a consequence there will be some boards
that contain EEPROM memory because OTP blocks were full.
In the signature validation routine, iwlwifi needs to make sure
"select bit" and "EEPROM/OTP signature" agree on the type of
NVM to be used to configure the system.
Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
Signed-off-by: Reinette Chatre <reinette.chatre@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-csr.h')
-rw-r--r-- | drivers/net/wireless/iwlwifi/iwl-csr.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-csr.h b/drivers/net/wireless/iwlwifi/iwl-csr.h index 06437d13e73..8f183e0fa51 100644 --- a/drivers/net/wireless/iwlwifi/iwl-csr.h +++ b/drivers/net/wireless/iwlwifi/iwl-csr.h | |||
@@ -230,13 +230,18 @@ | |||
230 | 230 | ||
231 | /* EEPROM GP */ | 231 | /* EEPROM GP */ |
232 | #define CSR_EEPROM_GP_VALID_MSK (0x00000007) | 232 | #define CSR_EEPROM_GP_VALID_MSK (0x00000007) |
233 | #define CSR_EEPROM_GP_BAD_SIGNATURE (0x00000000) | ||
234 | #define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) | 233 | #define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) |
235 | #define CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */ | 234 | #define CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */ |
236 | #define CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */ | 235 | #define CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */ |
237 | #define CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */ | 236 | #define CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */ |
238 | #define CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */ | 237 | #define CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */ |
239 | 238 | ||
239 | /* EEPROM signature */ | ||
240 | #define CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000) | ||
241 | #define CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001) | ||
242 | #define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) | ||
243 | #define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) | ||
244 | |||
240 | /* CSR GIO */ | 245 | /* CSR GIO */ |
241 | #define CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) | 246 | #define CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) |
242 | 247 | ||